2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H
37 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
38 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
39 F_CPL_SWITCH | F_SGE | F_ULP_TX)
42 MAX_NPORTS = 4, /* max # of ports */
43 SERNUM_LEN = 24, /* Serial # length */
44 EC_LEN = 16, /* E/C length */
45 ID_LEN = 16, /* ID length */
46 PN_LEN = 16, /* Part Number length */
47 MD_LEN = 16, /* MFG diags version length */
48 MACADDR_LEN = 12, /* MAC Address length */
52 T4_REGMAP_SIZE = (160 * 1024),
53 T5_REGMAP_SIZE = (332 * 1024),
56 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
58 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
60 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
65 PAUSE_AUTONEG = 1 << 2
71 FEC_BASER_RS = 1 << 1,
72 FEC_AUTO = 1 << 5, /* M_FW_PORT_CAP32_FEC + 1 */
75 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
78 u64 tx_octets; /* total # of octets in good frames */
79 u64 tx_frames; /* all good frames */
80 u64 tx_bcast_frames; /* all broadcast frames */
81 u64 tx_mcast_frames; /* all multicast frames */
82 u64 tx_ucast_frames; /* all unicast frames */
83 u64 tx_error_frames; /* all error frames */
85 u64 tx_frames_64; /* # of Tx frames in a particular range */
87 u64 tx_frames_128_255;
88 u64 tx_frames_256_511;
89 u64 tx_frames_512_1023;
90 u64 tx_frames_1024_1518;
91 u64 tx_frames_1519_max;
93 u64 tx_drop; /* # of dropped Tx frames */
94 u64 tx_pause; /* # of transmitted pause frames */
95 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
96 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
97 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
98 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
99 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
100 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
101 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
102 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
104 u64 rx_octets; /* total # of octets in good frames */
105 u64 rx_frames; /* all good frames */
106 u64 rx_bcast_frames; /* all broadcast frames */
107 u64 rx_mcast_frames; /* all multicast frames */
108 u64 rx_ucast_frames; /* all unicast frames */
109 u64 rx_too_long; /* # of frames exceeding MTU */
110 u64 rx_jabber; /* # of jabber frames */
111 u64 rx_fcs_err; /* # of received frames with bad FCS */
112 u64 rx_len_err; /* # of received frames with length error */
113 u64 rx_symbol_err; /* symbol errors */
114 u64 rx_runt; /* # of short frames */
116 u64 rx_frames_64; /* # of Rx frames in a particular range */
117 u64 rx_frames_65_127;
118 u64 rx_frames_128_255;
119 u64 rx_frames_256_511;
120 u64 rx_frames_512_1023;
121 u64 rx_frames_1024_1518;
122 u64 rx_frames_1519_max;
124 u64 rx_pause; /* # of received pause frames */
125 u64 rx_ppp0; /* # of received PPP prio 0 frames */
126 u64 rx_ppp1; /* # of received PPP prio 1 frames */
127 u64 rx_ppp2; /* # of received PPP prio 2 frames */
128 u64 rx_ppp3; /* # of received PPP prio 3 frames */
129 u64 rx_ppp4; /* # of received PPP prio 4 frames */
130 u64 rx_ppp5; /* # of received PPP prio 5 frames */
131 u64 rx_ppp6; /* # of received PPP prio 6 frames */
132 u64 rx_ppp7; /* # of received PPP prio 7 frames */
134 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
135 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
136 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
137 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
138 u64 rx_trunc0; /* buffer-group 0 truncated packets */
139 u64 rx_trunc1; /* buffer-group 1 truncated packets */
140 u64 rx_trunc2; /* buffer-group 2 truncated packets */
141 u64 rx_trunc3; /* buffer-group 3 truncated packets */
144 struct lb_port_stats {
157 u64 frames_1024_1518;
172 struct tp_tcp_stats {
176 u64 tcp_retrans_segs;
179 struct tp_usm_stats {
185 struct tp_fcoe_stats {
191 struct tp_err_stats {
192 u32 mac_in_errs[MAX_NCHAN];
193 u32 hdr_in_errs[MAX_NCHAN];
194 u32 tcp_in_errs[MAX_NCHAN];
195 u32 tnl_cong_drops[MAX_NCHAN];
196 u32 ofld_chan_drops[MAX_NCHAN];
197 u32 tnl_tx_drops[MAX_NCHAN];
198 u32 ofld_vlan_drops[MAX_NCHAN];
199 u32 tcp6_in_errs[MAX_NCHAN];
204 struct tp_proxy_stats {
205 u32 proxy[MAX_NCHAN];
208 struct tp_cpl_stats {
213 struct tp_rdma_stats {
219 int timer_val[SGE_NTIMERS]; /* final, scaled values */
220 int counter_val[SGE_NCOUNTERS];
221 int fl_starve_threshold;
222 int fl_starve_threshold2;
231 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES];
235 unsigned int tre; /* log2 of core clocks per TP tick */
236 unsigned int dack_re; /* DACK timer resolution */
237 unsigned int la_mask; /* what events are recorded by TP LA */
238 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
240 uint32_t vlan_pri_map;
241 uint32_t ingress_config;
242 uint64_t hash_filter_mask;
250 int8_t protocol_shift;
251 int8_t ethertype_shift;
252 int8_t macmatch_shift;
253 int8_t matchtype_shift;
260 u8 sn[SERNUM_LEN + 1];
263 u8 na[MACADDR_LEN + 1];
268 unsigned int vpd_cap_addr;
270 unsigned short speed;
271 unsigned short width;
275 * Firmware device log.
277 struct devlog_params {
278 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
279 u32 start; /* start of log in firmware memory */
280 u32 size; /* size of log */
281 u32 addr; /* start address in flat addr space */
284 /* Stores chip specific parameters */
288 u8 cng_ch_bits_log; /* congestion channel map bits width */
297 /* VF-only parameters. */
300 * Global Receive Side Scaling (RSS) parameters in host-native format.
303 unsigned int mode; /* RSS mode */
306 u_int synmapen:1; /* SYN Map Enable */
307 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
308 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
309 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
310 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
311 u_int ofdmapen:1; /* Offload Map Enable */
312 u_int tnlmapen:1; /* Tunnel Map Enable */
313 u_int tnlalllookup:1; /* Tunnel All Lookup */
314 u_int hashtoeplitz:1; /* use Toeplitz hash */
320 * Maximum resources provisioned for a PCI VF.
322 struct vf_resources {
323 unsigned int nvi; /* N virtual interfaces */
324 unsigned int neq; /* N egress Qs */
325 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
326 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
327 unsigned int niq; /* N ingress Qs */
328 unsigned int tc; /* PCI-E traffic class */
329 unsigned int pmask; /* port access rights mask */
330 unsigned int nexactf; /* N exact MPS filters */
331 unsigned int r_caps; /* read capabilities */
332 unsigned int wx_caps; /* write/execute capabilities */
335 struct adapter_params {
336 struct sge_params sge;
337 struct tp_params tp; /* PF-only */
338 struct vpd_params vpd;
339 struct pci_params pci;
340 struct devlog_params devlog; /* PF-only */
341 struct rss_params rss; /* VF-only */
342 struct vf_resources vfres; /* VF-only */
343 unsigned int core_vdd;
345 unsigned int sf_size; /* serial flash size in bytes */
346 unsigned int sf_nsec; /* # of flash sectors */
348 unsigned int fw_vers; /* firmware version */
349 unsigned int bs_vers; /* bootstrap version */
350 unsigned int tp_vers; /* TP microcode version */
351 unsigned int er_vers; /* expansion ROM version */
352 unsigned int scfg_vers; /* Serial Configuration version */
353 unsigned int vpd_vers; /* VPD version */
355 unsigned short mtus[NMTUS];
356 unsigned short a_wnd[NCCTRL_WIN];
357 unsigned short b_wnd[NCCTRL_WIN];
359 unsigned int cim_la_size;
361 uint8_t nports; /* # of ethernet ports */
363 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
364 unsigned int rev:4; /* chip revision */
365 unsigned int fpga:1; /* this is an FPGA */
366 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
367 resources for TOE operation. */
368 unsigned int bypass:1; /* this is a bypass card */
369 unsigned int ethoffload:1;
370 unsigned int hash_filter:1;
371 unsigned int filter2_wr_support:1;
372 unsigned int port_caps32:1;
374 unsigned int ofldq_wr_cred;
375 unsigned int eo_wr_cred;
377 unsigned int max_ordird_qp;
378 unsigned int max_ird_adapter;
380 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */
382 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
383 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
386 #define CHELSIO_T4 0x4
387 #define CHELSIO_T5 0x5
388 #define CHELSIO_T6 0x6
391 * State needed to monitor the forward progress of SGE Ingress DMA activities
392 * and possible hangs.
394 struct sge_idma_monitor_state {
395 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
396 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
397 unsigned int idma_state[2]; /* IDMA Hang detect state */
398 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
399 unsigned int idma_warn[2]; /* time to warning in HZ */
402 struct trace_params {
403 u32 data[TRACE_LEN / 4];
404 u32 mask[TRACE_LEN / 4];
405 unsigned short snap_len;
406 unsigned short min_len;
407 unsigned char skip_ofst;
408 unsigned char skip_len;
409 unsigned char invert;
414 /* OS-specific code owns all the requested_* fields. */
415 int8_t requested_aneg; /* link autonegotiation */
416 int8_t requested_fc; /* flow control */
417 int8_t requested_fec; /* FEC */
418 u_int requested_speed; /* speed (Mbps) */
420 uint32_t supported; /* link capabilities */
421 uint32_t advertising; /* advertised capabilities */
422 uint32_t lp_advertising; /* peer advertised capabilities */
423 uint32_t fec_hint; /* use this fec */
424 u_int speed; /* actual link speed (Mbps) */
425 int8_t fc; /* actual link flow control */
426 int8_t fec; /* actual FEC */
427 bool link_ok; /* link up? */
428 uint8_t link_down_rc; /* link down reason */
433 #ifndef PCI_VENDOR_ID_CHELSIO
434 # define PCI_VENDOR_ID_CHELSIO 0x1425
437 #define for_each_port(adapter, iter) \
438 for (iter = 0; iter < (adapter)->params.nports; ++iter)
440 static inline int is_ftid(const struct adapter *sc, u_int tid)
443 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base &&
444 tid <= sc->tids.ftid_end);
447 static inline int is_hpftid(const struct adapter *sc, u_int tid)
450 return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base &&
451 tid <= sc->tids.hpftid_end);
454 static inline int is_etid(const struct adapter *sc, u_int tid)
457 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base &&
458 tid <= sc->tids.etid_end);
461 static inline int is_offload(const struct adapter *adap)
463 return adap->params.offload;
466 static inline int is_ethoffload(const struct adapter *adap)
468 return adap->params.ethoffload;
471 static inline int is_hashfilter(const struct adapter *adap)
473 return adap->params.hash_filter;
476 static inline int chip_id(struct adapter *adap)
478 return adap->params.chipid;
481 static inline int chip_rev(struct adapter *adap)
483 return adap->params.rev;
486 static inline int is_t4(struct adapter *adap)
488 return adap->params.chipid == CHELSIO_T4;
491 static inline int is_t5(struct adapter *adap)
493 return adap->params.chipid == CHELSIO_T5;
496 static inline int is_t6(struct adapter *adap)
498 return adap->params.chipid == CHELSIO_T6;
501 static inline int is_fpga(struct adapter *adap)
503 return adap->params.fpga;
506 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
508 return adap->params.vpd.cclk / 1000;
511 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
514 return (us * adap->params.vpd.cclk) / 1000;
517 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
520 /* add Core Clock / 2 to round ticks to nearest uS */
521 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
522 adapter->params.vpd.cclk);
525 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
528 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
531 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us)
534 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre);
537 static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks)
539 return ((uint64_t)ticks << adap->params.tp.tre) /
540 core_ticks_per_usec(adap);
543 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
545 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
546 int size, void *rpl, bool sleep_ok, int timeout);
547 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
548 void *rpl, bool sleep_ok);
550 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
551 const void *cmd, int size, void *rpl,
554 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
558 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
561 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
564 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
567 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
570 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
571 unsigned int data_reg, u32 *vals, unsigned int nregs,
572 unsigned int start_idx);
573 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
574 unsigned int data_reg, const u32 *vals,
575 unsigned int nregs, unsigned int start_idx);
577 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
581 void t4_intr_enable(struct adapter *adapter);
582 void t4_intr_disable(struct adapter *adapter);
583 void t4_intr_clear(struct adapter *adapter);
584 int t4_slow_intr_handler(struct adapter *adapter);
586 int t4_hash_mac_addr(const u8 *addr);
587 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
588 struct link_config *lc);
589 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
590 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
591 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
592 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
593 int t4_seeprom_wp(struct adapter *adapter, int enable);
594 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
595 u32 *data, int byte_oriented);
596 int t4_write_flash(struct adapter *adapter, unsigned int addr,
597 unsigned int n, const u8 *data, int byte_oriented);
598 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
600 int t5_fw_init_extern_mem(struct adapter *adap);
601 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
602 int t4_load_boot(struct adapter *adap, u8 *boot_data,
603 unsigned int boot_addr, unsigned int size);
604 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
605 int t4_flash_cfg_addr(struct adapter *adapter);
606 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
607 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
608 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
609 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
610 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
611 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
612 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
613 int t4_get_version_info(struct adapter *adapter);
614 int t4_init_hw(struct adapter *adapter, u32 fw_params);
615 const struct chip_params *t4_get_chip_params(int chipid);
616 int t4_prep_adapter(struct adapter *adapter, u32 *buf);
617 int t4_shutdown_adapter(struct adapter *adapter);
618 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
619 int t4_init_sge_params(struct adapter *adapter);
620 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
621 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
622 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
623 void t4_fatal_err(struct adapter *adapter);
624 void t4_db_full(struct adapter *adapter);
625 void t4_db_dropped(struct adapter *adapter);
626 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
627 int filter_index, int enable);
628 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
629 int filter_index, int *enabled);
630 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
631 int start, int n, const u16 *rspq, unsigned int nrspq);
632 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
634 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
635 unsigned int flags, unsigned int defq, unsigned int skeyidx,
637 int t4_read_rss(struct adapter *adapter, u16 *entries);
638 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
639 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
641 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
642 u32 *valp, bool sleep_ok);
643 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
644 u32 val, bool sleep_ok);
645 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
646 u32 *vfl, u32 *vfh, bool sleep_ok);
647 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
648 u32 vfl, u32 vfh, bool sleep_ok);
649 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
650 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok);
651 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
652 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok);
653 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
654 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
655 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
656 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
657 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
658 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
659 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
661 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
662 const unsigned int *valp);
663 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
665 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
666 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
667 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
668 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
669 int t4_get_flash_params(struct adapter *adapter);
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
672 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
673 __be32 *data, u64 *parity);
674 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
675 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
677 void t4_idma_monitor_init(struct adapter *adapter,
678 struct sge_idma_monitor_state *idma);
679 void t4_idma_monitor(struct adapter *adapter,
680 struct sge_idma_monitor_state *idma,
683 unsigned int t4_get_regs_len(struct adapter *adapter);
684 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
686 const char *t4_get_port_type_description(enum fw_port_type port_type);
687 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
688 void t4_get_port_stats_offset(struct adapter *adap, int idx,
689 struct port_stats *stats,
690 struct port_stats *offset);
691 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
692 void t4_clr_port_stats(struct adapter *adap, int idx);
694 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
695 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
696 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
697 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
698 unsigned int *ipg, bool sleep_ok);
699 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
700 unsigned int mask, unsigned int val);
701 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
702 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
704 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
706 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
708 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
710 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
712 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
713 struct tp_tcp_stats *v6, bool sleep_ok);
714 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
715 struct tp_fcoe_stats *st, bool sleep_ok);
716 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
717 const unsigned short *alpha, const unsigned short *beta);
719 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
721 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
722 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
723 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
724 unsigned int start, unsigned int n);
725 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
726 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
728 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
730 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
731 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
732 u64 mask0, u64 mask1, unsigned int crc, bool enable);
734 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
735 enum dev_master master, enum dev_state *state);
736 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
737 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
738 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
739 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
740 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
741 const u8 *fw_data, unsigned int size, int force);
742 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data,
744 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
745 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
746 unsigned int vf, unsigned int nparams, const u32 *params,
748 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
749 unsigned int vf, unsigned int nparams, const u32 *params,
751 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
752 unsigned int pf, unsigned int vf,
753 unsigned int nparams, const u32 *params,
754 const u32 *val, int timeout);
755 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
756 unsigned int vf, unsigned int nparams, const u32 *params,
758 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
759 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
760 unsigned int rxqi, unsigned int rxq, unsigned int tc,
761 unsigned int vi, unsigned int cmask, unsigned int pmask,
762 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
763 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
764 unsigned int port, unsigned int pf, unsigned int vf,
765 unsigned int nmac, u8 *mac, u16 *rss_size,
766 unsigned int portfunc, unsigned int idstype);
767 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
768 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
770 int t4_free_vi(struct adapter *adap, unsigned int mbox,
771 unsigned int pf, unsigned int vf,
773 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
774 int mtu, int promisc, int all_multi, int bcast, int vlanex,
776 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
777 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
778 u64 *hash, bool sleep_ok);
779 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
780 int idx, const u8 *addr, bool persist, bool add_smt);
781 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
782 bool ucast, u64 vec, bool sleep_ok);
783 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
784 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
785 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
786 bool rx_en, bool tx_en);
787 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
788 unsigned int nblinks);
789 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
790 unsigned int mmd, unsigned int reg, unsigned int *valp);
791 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
792 unsigned int mmd, unsigned int reg, unsigned int val);
793 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
794 int port, unsigned int devid,
795 unsigned int offset, unsigned int len,
797 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
798 int port, unsigned int devid,
799 unsigned int offset, unsigned int len,
801 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
802 unsigned int vf, unsigned int iqtype, unsigned int iqid,
803 unsigned int fl0id, unsigned int fl1id);
804 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
805 unsigned int vf, unsigned int iqtype, unsigned int iqid,
806 unsigned int fl0id, unsigned int fl1id);
807 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
808 unsigned int vf, unsigned int eqid);
809 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
810 unsigned int vf, unsigned int eqid);
811 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
812 unsigned int vf, unsigned int eqid);
813 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
814 enum ctxt_type ctype, u32 *data);
815 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
817 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
818 const char *t4_link_down_rc_str(unsigned char link_down_rc);
819 int t4_update_port_info(struct port_info *pi);
820 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
821 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
822 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
824 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
825 int rateunit, int ratemode, int channel, int cl,
826 int minrate, int maxrate, int weight, int pktsize,
827 int burstsize, int sleep_ok);
828 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
829 unsigned int maxrate, int sleep_ok);
830 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
831 int weight, int sleep_ok);
832 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
833 int mode, unsigned int maxrate, int pktsize,
835 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
836 unsigned int pf, unsigned int vf,
837 unsigned int timeout, unsigned int action);
838 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
839 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
840 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
842 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
843 u32 start_index, bool sleep_ok);
844 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
845 u32 start_index, bool sleep_ok);
846 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
847 u32 start_index, bool sleep_ok);
848 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
849 u32 start_index, bool sleep_ok);
851 static inline int t4vf_query_params(struct adapter *adapter,
852 unsigned int nparams, const u32 *params,
855 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals);
858 static inline int t4vf_set_params(struct adapter *adapter,
859 unsigned int nparams, const u32 *params,
862 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals);
865 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd,
868 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
871 int t4vf_wait_dev_ready(struct adapter *adapter);
872 int t4vf_fw_reset(struct adapter *adapter);
873 int t4vf_get_sge_params(struct adapter *adapter);
874 int t4vf_get_rss_glb_config(struct adapter *adapter);
875 int t4vf_get_vfres(struct adapter *adapter);
876 int t4vf_prep_adapter(struct adapter *adapter);
877 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
878 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset,
879 unsigned int *pbar2_qid);
880 unsigned int fwcap_to_speed(uint32_t caps);
881 uint32_t speed_to_fwcap(unsigned int speed);
882 uint32_t fwcap_top_speed(uint32_t caps);
885 port_top_speed(const struct port_info *pi)
889 return (fwcap_to_speed(pi->link_cfg.supported) / 1000);
892 #endif /* __CHELSIO_COMMON_H */