2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/eventhandler.h>
39 #include "t4_regs_values.h"
40 #include "firmware/t4fw_interface.h"
43 #define msleep(x) do { \
47 pause("t4hw", (x) * hz / 1000); \
51 * t4_wait_op_done_val - wait until an operation is completed
52 * @adapter: the adapter performing the operation
53 * @reg: the register to check for completion
54 * @mask: a single-bit field within @reg that indicates completion
55 * @polarity: the value of the field when the operation is completed
56 * @attempts: number of check iterations
57 * @delay: delay in usecs between iterations
58 * @valp: where to store the value of the register at completion time
60 * Wait until an operation is completed by checking a bit in a register
61 * up to @attempts times. If @valp is not NULL the value of the register
62 * at the time it indicated completion is stored there. Returns 0 if the
63 * operation completes and -EAGAIN otherwise.
65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
66 int polarity, int attempts, int delay, u32 *valp)
69 u32 val = t4_read_reg(adapter, reg);
71 if (!!(val & mask) == polarity) {
83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
84 int polarity, int attempts, int delay)
86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
91 * t4_set_reg_field - set a register field to a value
92 * @adapter: the adapter to program
93 * @addr: the register address
94 * @mask: specifies the portion of the register to modify
95 * @val: the new value for the register field
97 * Sets a register field specified by the supplied mask to the
100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
103 u32 v = t4_read_reg(adapter, addr) & ~mask;
105 t4_write_reg(adapter, addr, v | val);
106 (void) t4_read_reg(adapter, addr); /* flush */
110 * t4_read_indirect - read indirectly addressed registers
112 * @addr_reg: register holding the indirect address
113 * @data_reg: register holding the value of the indirect register
114 * @vals: where the read register values are stored
115 * @nregs: how many indirect registers to read
116 * @start_idx: index of first indirect register to read
118 * Reads registers that are accessed indirectly through an address/data
121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
122 unsigned int data_reg, u32 *vals,
123 unsigned int nregs, unsigned int start_idx)
126 t4_write_reg(adap, addr_reg, start_idx);
127 *vals++ = t4_read_reg(adap, data_reg);
133 * t4_write_indirect - write indirectly addressed registers
135 * @addr_reg: register holding the indirect addresses
136 * @data_reg: register holding the value for the indirect registers
137 * @vals: values to write
138 * @nregs: how many indirect registers to write
139 * @start_idx: address of first indirect register to write
141 * Writes a sequential block of registers that are accessed indirectly
142 * through an address/data register pair.
144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
145 unsigned int data_reg, const u32 *vals,
146 unsigned int nregs, unsigned int start_idx)
149 t4_write_reg(adap, addr_reg, start_idx++);
150 t4_write_reg(adap, data_reg, *vals++);
155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
156 * mechanism. This guarantees that we get the real value even if we're
157 * operating within a Virtual Machine and the Hypervisor is trapping our
158 * Configuration Space accesses.
160 * N.B. This routine should only be used as a last resort: the firmware uses
161 * the backdoor registers on a regular basis and we can end up
162 * conflicting with it's uses!
164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
169 if (chip_id(adap) <= CHELSIO_T5)
177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
182 * Configuration Space read. (None of the other fields matter when
183 * F_ENABLE is 0 so a simple register write is easier than a
184 * read-modify-write via t4_set_reg_field().)
186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
192 * t4_report_fw_error - report firmware error
195 * The adapter firmware can indicate error conditions to the host.
196 * If the firmware has indicated an error, print out the reason for
197 * the firmware error.
199 static void t4_report_fw_error(struct adapter *adap)
201 static const char *const reason[] = {
202 "Crash", /* PCIE_FW_EVAL_CRASH */
203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
209 "Reserved", /* reserved */
213 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
214 if (pcie_fw & F_PCIE_FW_ERR) {
215 adap->flags &= ~FW_OK;
216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
218 if (pcie_fw != 0xffffffff)
219 t4_os_dump_devlog(adap);
224 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
229 for ( ; nflit; nflit--, mbox_addr += 8)
230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
234 * Handle a FW assertion reported in a mailbox.
236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
240 asrt->u.assert.filename_0_7,
241 be32_to_cpu(asrt->u.assert.line),
242 be32_to_cpu(asrt->u.assert.x),
243 be32_to_cpu(asrt->u.assert.y));
246 struct port_tx_state {
252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
254 uint32_t rx_pause_reg, tx_frames_reg;
257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
274 read_tx_state_one(sc, i, &tx_state[i]);
278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
280 uint32_t port_ctl_reg;
281 uint64_t tx_frames, rx_pause;
284 for_each_port(sc, i) {
285 rx_pause = tx_state[i].rx_pause;
286 tx_frames = tx_state[i].tx_frames;
287 read_tx_state_one(sc, i, &tx_state[i]); /* update */
290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL);
292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL);
293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
294 rx_pause != tx_state[i].rx_pause &&
295 tx_frames == tx_state[i].tx_frames) {
296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
303 #define X_CIM_PF_NOACCESS 0xeeeeeeee
305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
307 * @mbox: index of the mailbox to use
308 * @cmd: the command to write
309 * @size: command length in bytes
310 * @rpl: where to optionally store the reply
311 * @sleep_ok: if true we may sleep while awaiting command completion
312 * @timeout: time to wait for command to finish before timing out
313 * (negative implies @sleep_ok=false)
315 * Sends the given command to FW through the selected mailbox and waits
316 * for the FW to execute the command. If @rpl is not %NULL it is used to
317 * store the FW's reply to the command. The command and its optional
318 * reply are of the same length. Some FW commands like RESET and
319 * INITIALIZE can take a considerable amount of time to execute.
320 * @sleep_ok determines whether we may sleep while awaiting the response.
321 * If sleeping is allowed we use progressive backoff otherwise we spin.
322 * Note that passing in a negative @timeout is an alternate mechanism
323 * for specifying @sleep_ok=false. This is useful when a higher level
324 * interface allows for specification of @timeout but not @sleep_ok ...
326 * The return value is 0 on success or a negative errno on failure. A
327 * failure can happen either because we are not able to execute the
328 * command or FW executes it but signals an error. In the latter case
329 * the return value is the error code indicated by FW (negated).
331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
332 int size, void *rpl, bool sleep_ok, int timeout)
335 * We delay in small increments at first in an effort to maintain
336 * responsiveness for simple, fast executing commands but then back
337 * off to larger delays to a maximum retry delay.
339 static const int delay[] = {
340 1, 1, 3, 5, 10, 10, 20, 50, 100
344 int i, ms, delay_idx, ret, next_tx_check;
345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
348 __be64 cmd_rpl[MBOX_LEN/8];
350 struct port_tx_state tx_state[MAX_NPORTS];
352 if (adap->flags & CHK_MBOX_ACCESS)
353 ASSERT_SYNCHRONIZED_OP(adap);
355 if (size <= 0 || (size & 15) || size > MBOX_LEN)
358 if (adap->flags & IS_VF) {
360 data_reg = FW_T6VF_MBDATA_BASE_ADDR;
362 data_reg = FW_T4VF_MBDATA_BASE_ADDR;
363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
367 * If we have a negative timeout, that implies that we can't sleep.
375 * Attempt to gain access to the mailbox.
377 for (i = 0; i < 4; i++) {
378 ctl = t4_read_reg(adap, ctl_reg);
380 if (v != X_MBOWNER_NONE)
385 * If we were unable to gain access, report the error to our caller.
387 if (v != X_MBOWNER_PL) {
388 t4_report_fw_error(adap);
389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
394 * If we gain ownership of the mailbox and there's a "valid" message
395 * in it, this is likely an asynchronous error message from the
396 * firmware. So we'll report that and then proceed on with attempting
397 * to issue our own command ... which may well fail if the error
398 * presaged the firmware crashing ...
400 if (ctl & F_MBMSGVALID) {
401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
405 * Copy in the new mailbox command and send it on its way ...
407 memset(cmd_rpl, 0, sizeof(cmd_rpl));
408 memcpy(cmd_rpl, cmd, size);
409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
413 if (adap->flags & IS_VF) {
415 * For the VFs, the Mailbox Data "registers" are
416 * actually backed by T4's "MA" interface rather than
417 * PL Registers (as is the case for the PFs). Because
418 * these are in different coherency domains, the write
419 * to the VF's PL-register-backed Mailbox Control can
420 * race in front of the writes to the MA-backed VF
421 * Mailbox Data "registers". So we need to do a
422 * read-back on at least one byte of the VF Mailbox
423 * Data registers before doing the write to the VF
424 * Mailbox Control register.
426 t4_read_reg(adap, data_reg);
429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
431 next_tx_check = 1000;
436 * Loop waiting for the reply; bail out if we time out or the firmware
440 for (i = 0; i < timeout; i += ms) {
441 if (!(adap->flags & IS_VF)) {
442 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
443 if (pcie_fw & F_PCIE_FW_ERR)
447 if (i >= next_tx_check) {
448 check_tx_state(adap, &tx_state[0]);
449 next_tx_check = i + 1000;
453 ms = delay[delay_idx]; /* last element may repeat */
454 if (delay_idx < ARRAY_SIZE(delay) - 1)
461 v = t4_read_reg(adap, ctl_reg);
462 if (v == X_CIM_PF_NOACCESS)
464 if (G_MBOWNER(v) == X_MBOWNER_PL) {
465 if (!(v & F_MBMSGVALID)) {
466 t4_write_reg(adap, ctl_reg,
467 V_MBOWNER(X_MBOWNER_NONE));
472 * Retrieve the command reply and release the mailbox.
474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
478 res = be64_to_cpu(cmd_rpl[0]);
479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
481 res = V_FW_CMD_RETVAL(EIO);
483 memcpy(rpl, cmd_rpl, size);
484 return -G_FW_CMD_RETVAL((int)res);
489 * We timed out waiting for a reply to our mailbox command. Report
490 * the error and also check to see if the firmware reported any
493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
494 *(const u8 *)cmd, mbox, pcie_fw);
495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
498 if (pcie_fw & F_PCIE_FW_ERR) {
500 t4_report_fw_error(adap);
503 t4_os_dump_devlog(adap);
506 t4_fatal_err(adap, true);
510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
511 void *rpl, bool sleep_ok)
513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
514 sleep_ok, FW_CMD_MAX_TIMEOUT);
518 static int t4_edc_err_read(struct adapter *adap, int idx)
520 u32 edc_ecc_err_addr_reg;
521 u32 edc_bist_status_rdata_reg;
524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
527 if (idx != MEM_EDC0 && idx != MEM_EDC1) {
528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
536 "edc%d err addr 0x%x: 0x%x.\n",
537 idx, edc_ecc_err_addr_reg,
538 t4_read_reg(adap, edc_ecc_err_addr_reg));
540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
541 edc_bist_status_rdata_reg,
542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
556 * t4_mc_read - read from MC through backdoor accesses
558 * @idx: which MC to access
559 * @addr: address of first byte requested
560 * @data: 64 bytes of data containing the requested address
561 * @ecc: where to store the corresponding 64-bit ECC word
563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
564 * that covers the requested address @addr. If @parity is not %NULL it
565 * is assigned the 64-bit ECC word for the read data.
567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
574 mc_bist_cmd_reg = A_MC_BIST_CMD;
575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
595 F_START_BIST | V_BIST_CMD_GAP(1));
596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
602 for (i = 15; i >= 0; i--)
603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
605 *ecc = t4_read_reg64(adap, MC_DATA(16));
611 * t4_edc_read - read from EDC through backdoor accesses
613 * @idx: which EDC to access
614 * @addr: address of first byte requested
615 * @data: 64 bytes of data containing the requested address
616 * @ecc: where to store the corresponding 64-bit ECC word
618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
619 * that covers the requested address @addr. If @parity is not %NULL it
620 * is assigned the 64-bit ECC word for the read data.
622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
638 * These macro are missing in t4_regs.h file.
639 * Added temporarily for testing.
641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
659 t4_write_reg(adap, edc_bist_cmd_reg,
660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
667 for (i = 15; i >= 0; i--)
668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
670 *ecc = t4_read_reg64(adap, EDC_DATA(16));
676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
679 * @addr: address within indicated memory type
680 * @len: amount of memory to read
681 * @buf: host memory buffer
683 * Reads an [almost] arbitrary memory region in the firmware: the
684 * firmware memory address, length and host buffer must be aligned on
685 * 32-bit boudaries. The memory is returned as a raw byte sequence from
686 * the firmware's memory. If this memory contains data structures which
687 * contain multi-byte integers, it's the callers responsibility to
688 * perform appropriate byte order conversions.
690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
693 u32 pos, start, end, offset;
697 * Argument sanity checks ...
699 if ((addr & 0x3) || (len & 0x3))
703 * The underlaying EDC/MC read routines read 64 bytes at a time so we
704 * need to round down the start and round up the end. We'll start
705 * copying out of the first line at (addr - start) a word at a time.
707 start = rounddown2(addr, 64);
708 end = roundup2(addr + len, 64);
709 offset = (addr - start)/sizeof(__be32);
711 for (pos = start; pos < end; pos += 64, offset = 0) {
715 * Read the chip's memory block and bail if there's an error.
717 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
720 ret = t4_edc_read(adap, mtype, pos, data, NULL);
725 * Copy the data into the caller's memory buffer.
727 while (offset < 16 && len > 0) {
728 *buf++ = data[offset++];
729 len -= sizeof(__be32);
737 * Return the specified PCI-E Configuration Space register from our Physical
738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
739 * since we prefer to let the firmware own all of these registers, but if that
740 * fails we go for it directly ourselves.
742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
746 * If fw_attach != 0, construct and send the Firmware LDST Command to
747 * retrieve the specified PCI-E Configuration Space register.
749 if (drv_fw_attach != 0) {
750 struct fw_ldst_cmd ldst_cmd;
753 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
754 ldst_cmd.op_to_addrspace =
755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
761 ldst_cmd.u.pcie.ctrl_to_fn =
762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
763 ldst_cmd.u.pcie.r = reg;
766 * If the LDST Command succeeds, return the result, otherwise
767 * fall through to reading it directly ourselves ...
769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
774 CH_WARN(adap, "Firmware failed to return "
775 "Configuration Space register %d, err = %d\n",
780 * Read the desired Configuration Space register via the PCI-E
781 * Backdoor mechanism.
783 return t4_hw_pci_read_cfg4(adap, reg);
787 * t4_get_regs_len - return the size of the chips register set
788 * @adapter: the adapter
790 * Returns the size of the chip's BAR0 register space.
792 unsigned int t4_get_regs_len(struct adapter *adapter)
794 unsigned int chip_version = chip_id(adapter);
796 switch (chip_version) {
798 if (adapter->flags & IS_VF)
799 return FW_T4VF_REGMAP_SIZE;
800 return T4_REGMAP_SIZE;
804 if (adapter->flags & IS_VF)
805 return FW_T4VF_REGMAP_SIZE;
806 return T5_REGMAP_SIZE;
810 "Unsupported chip version %d\n", chip_version);
815 * t4_get_regs - read chip registers into provided buffer
817 * @buf: register buffer
818 * @buf_size: size (in bytes) of register buffer
820 * If the provided register buffer isn't large enough for the chip's
821 * full register range, the register dump will be truncated to the
822 * register buffer's size.
824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
826 static const unsigned int t4_reg_ranges[] = {
1285 static const unsigned int t4vf_reg_ranges[] = {
1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1287 VF_MPS_REG(A_MPS_VF_CTL),
1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1292 FW_T4VF_MBDATA_BASE_ADDR,
1293 FW_T4VF_MBDATA_BASE_ADDR +
1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1297 static const unsigned int t5_reg_ranges[] = {
2064 static const unsigned int t5vf_reg_ranges[] = {
2065 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2066 VF_MPS_REG(A_MPS_VF_CTL),
2067 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2068 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2069 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2070 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2071 FW_T4VF_MBDATA_BASE_ADDR,
2072 FW_T4VF_MBDATA_BASE_ADDR +
2073 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2076 static const unsigned int t6_reg_ranges[] = {
2637 static const unsigned int t6vf_reg_ranges[] = {
2638 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2639 VF_MPS_REG(A_MPS_VF_CTL),
2640 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2641 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2642 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2643 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2644 FW_T6VF_MBDATA_BASE_ADDR,
2645 FW_T6VF_MBDATA_BASE_ADDR +
2646 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2649 u32 *buf_end = (u32 *)(buf + buf_size);
2650 const unsigned int *reg_ranges;
2651 int reg_ranges_size, range;
2652 unsigned int chip_version = chip_id(adap);
2655 * Select the right set of register ranges to dump depending on the
2656 * adapter chip type.
2658 switch (chip_version) {
2660 if (adap->flags & IS_VF) {
2661 reg_ranges = t4vf_reg_ranges;
2662 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2664 reg_ranges = t4_reg_ranges;
2665 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2670 if (adap->flags & IS_VF) {
2671 reg_ranges = t5vf_reg_ranges;
2672 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2674 reg_ranges = t5_reg_ranges;
2675 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2680 if (adap->flags & IS_VF) {
2681 reg_ranges = t6vf_reg_ranges;
2682 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2684 reg_ranges = t6_reg_ranges;
2685 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2691 "Unsupported chip version %d\n", chip_version);
2696 * Clear the register buffer and insert the appropriate register
2697 * values selected by the above register ranges.
2699 memset(buf, 0, buf_size);
2700 for (range = 0; range < reg_ranges_size; range += 2) {
2701 unsigned int reg = reg_ranges[range];
2702 unsigned int last_reg = reg_ranges[range + 1];
2703 u32 *bufp = (u32 *)(buf + reg);
2706 * Iterate across the register range filling in the register
2707 * buffer but don't write past the end of the register buffer.
2709 while (reg <= last_reg && bufp < buf_end) {
2710 *bufp++ = t4_read_reg(adap, reg);
2717 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID
2718 * header followed by one or more VPD-R sections, each with its own header.
2726 struct t4_vpdr_hdr {
2732 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2734 #define EEPROM_DELAY 10 /* 10us per poll spin */
2735 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
2737 #define EEPROM_STAT_ADDR 0x7bfc
2738 #define VPD_SIZE 0x800
2739 #define VPD_BASE 0x400
2740 #define VPD_BASE_OLD 0
2741 #define VPD_LEN 1024
2742 #define VPD_INFO_FLD_HDR_SIZE 3
2743 #define CHELSIO_VPD_UNIQUE_ID 0x82
2746 * Small utility function to wait till any outstanding VPD Access is complete.
2747 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2748 * VPD Access in flight. This allows us to handle the problem of having a
2749 * previous VPD Access time out and prevent an attempt to inject a new VPD
2750 * Request before any in-flight VPD reguest has completed.
2752 static int t4_seeprom_wait(struct adapter *adapter)
2754 unsigned int base = adapter->params.pci.vpd_cap_addr;
2758 * If no VPD Access is in flight, we can just return success right
2761 if (!adapter->vpd_busy)
2765 * Poll the VPD Capability Address/Flag register waiting for it
2766 * to indicate that the operation is complete.
2768 max_poll = EEPROM_MAX_POLL;
2772 udelay(EEPROM_DELAY);
2773 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2776 * If the operation is complete, mark the VPD as no longer
2777 * busy and return success.
2779 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2780 adapter->vpd_busy = 0;
2783 } while (--max_poll);
2786 * Failure! Note that we leave the VPD Busy status set in order to
2787 * avoid pushing a new VPD Access request into the VPD Capability till
2788 * the current operation eventually succeeds. It's a bug to issue a
2789 * new request when an existing request is in flight and will result
2790 * in corrupt hardware state.
2796 * t4_seeprom_read - read a serial EEPROM location
2797 * @adapter: adapter to read
2798 * @addr: EEPROM virtual address
2799 * @data: where to store the read data
2801 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2802 * VPD capability. Note that this function must be called with a virtual
2805 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2807 unsigned int base = adapter->params.pci.vpd_cap_addr;
2811 * VPD Accesses must alway be 4-byte aligned!
2813 if (addr >= EEPROMVSIZE || (addr & 3))
2817 * Wait for any previous operation which may still be in flight to
2820 ret = t4_seeprom_wait(adapter);
2822 CH_ERR(adapter, "VPD still busy from previous operation\n");
2827 * Issue our new VPD Read request, mark the VPD as being busy and wait
2828 * for our request to complete. If it doesn't complete, note the
2829 * error and return it to our caller. Note that we do not reset the
2832 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2833 adapter->vpd_busy = 1;
2834 adapter->vpd_flag = PCI_VPD_ADDR_F;
2835 ret = t4_seeprom_wait(adapter);
2837 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2842 * Grab the returned data, swizzle it into our endianness and
2845 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2846 *data = le32_to_cpu(*data);
2851 * t4_seeprom_write - write a serial EEPROM location
2852 * @adapter: adapter to write
2853 * @addr: virtual EEPROM address
2854 * @data: value to write
2856 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2857 * VPD capability. Note that this function must be called with a virtual
2860 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2862 unsigned int base = adapter->params.pci.vpd_cap_addr;
2868 * VPD Accesses must alway be 4-byte aligned!
2870 if (addr >= EEPROMVSIZE || (addr & 3))
2874 * Wait for any previous operation which may still be in flight to
2877 ret = t4_seeprom_wait(adapter);
2879 CH_ERR(adapter, "VPD still busy from previous operation\n");
2884 * Issue our new VPD Read request, mark the VPD as being busy and wait
2885 * for our request to complete. If it doesn't complete, note the
2886 * error and return it to our caller. Note that we do not reset the
2889 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2891 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2892 (u16)addr | PCI_VPD_ADDR_F);
2893 adapter->vpd_busy = 1;
2894 adapter->vpd_flag = 0;
2895 ret = t4_seeprom_wait(adapter);
2897 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2902 * Reset PCI_VPD_DATA register after a transaction and wait for our
2903 * request to complete. If it doesn't complete, return error.
2905 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2906 max_poll = EEPROM_MAX_POLL;
2908 udelay(EEPROM_DELAY);
2909 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2910 } while ((stats_reg & 0x1) && --max_poll);
2914 /* Return success! */
2919 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2920 * @phys_addr: the physical EEPROM address
2921 * @fn: the PCI function number
2922 * @sz: size of function-specific area
2924 * Translate a physical EEPROM address to virtual. The first 1K is
2925 * accessed through virtual addresses starting at 31K, the rest is
2926 * accessed through virtual addresses starting at 0.
2928 * The mapping is as follows:
2929 * [0..1K) -> [31K..32K)
2930 * [1K..1K+A) -> [ES-A..ES)
2931 * [1K+A..ES) -> [0..ES-A-1K)
2933 * where A = @fn * @sz, and ES = EEPROM size.
2935 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2938 if (phys_addr < 1024)
2939 return phys_addr + (31 << 10);
2940 if (phys_addr < 1024 + fn)
2941 return EEPROMSIZE - fn + phys_addr - 1024;
2942 if (phys_addr < EEPROMSIZE)
2943 return phys_addr - 1024 - fn;
2948 * t4_seeprom_wp - enable/disable EEPROM write protection
2949 * @adapter: the adapter
2950 * @enable: whether to enable or disable write protection
2952 * Enables or disables write protection on the serial EEPROM.
2954 int t4_seeprom_wp(struct adapter *adapter, int enable)
2956 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2960 * get_vpd_keyword_val - Locates an information field keyword in the VPD
2961 * @vpd: Pointer to buffered vpd data structure
2962 * @kw: The keyword to search for
2963 * @region: VPD region to search (starting from 0)
2965 * Returns the value of the information field keyword or
2966 * -ENOENT otherwise.
2968 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2971 unsigned int offset, len;
2972 const struct t4_vpdr_hdr *vpdr;
2974 offset = sizeof(struct t4_vpd_hdr);
2975 vpdr = (const void *)(vpd + offset);
2976 tag = vpdr->vpdr_tag;
2977 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2979 offset += sizeof(struct t4_vpdr_hdr) + len;
2980 vpdr = (const void *)(vpd + offset);
2981 if (++tag != vpdr->vpdr_tag)
2983 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2985 offset += sizeof(struct t4_vpdr_hdr);
2987 if (offset + len > VPD_LEN) {
2991 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2992 if (memcmp(vpd + i , kw , 2) == 0){
2993 i += VPD_INFO_FLD_HDR_SIZE;
2997 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
3005 * get_vpd_params - read VPD parameters from VPD EEPROM
3006 * @adapter: adapter to read
3007 * @p: where to store the parameters
3008 * @vpd: caller provided temporary space to read the VPD into
3010 * Reads card parameters stored in VPD EEPROM.
3012 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3013 uint16_t device_id, u32 *buf)
3016 int ec, sn, pn, na, md;
3018 const u8 *vpd = (const u8 *)buf;
3021 * Card information normally starts at VPD_BASE but early cards had
3024 ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3029 * The VPD shall have a unique identifier specified by the PCI SIG.
3030 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3031 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3032 * is expected to automatically put this entry at the
3033 * beginning of the VPD.
3035 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3037 for (i = 0; i < VPD_LEN; i += 4) {
3038 ret = t4_seeprom_read(adapter, addr + i, buf++);
3043 #define FIND_VPD_KW(var,name) do { \
3044 var = get_vpd_keyword_val(vpd, name, 0); \
3046 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3051 FIND_VPD_KW(i, "RV");
3052 for (csum = 0; i >= 0; i--)
3057 "corrupted VPD EEPROM, actual csum %u\n", csum);
3061 FIND_VPD_KW(ec, "EC");
3062 FIND_VPD_KW(sn, "SN");
3063 FIND_VPD_KW(pn, "PN");
3064 FIND_VPD_KW(na, "NA");
3067 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3069 memcpy(p->ec, vpd + ec, EC_LEN);
3071 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3072 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3074 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3075 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3076 strstrip((char *)p->pn);
3077 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3078 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3079 strstrip((char *)p->na);
3081 if (device_id & 0x80)
3082 return 0; /* Custom card */
3084 md = get_vpd_keyword_val(vpd, "VF", 1);
3086 snprintf(p->md, sizeof(p->md), "unknown");
3088 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3089 memcpy(p->md, vpd + md, min(i, MD_LEN));
3090 strstrip((char *)p->md);
3096 /* serial flash and firmware constants and flash config file constants */
3098 SF_ATTEMPTS = 10, /* max retries for SF operations */
3100 /* flash command opcodes */
3101 SF_PROG_PAGE = 2, /* program 256B page */
3102 SF_WR_DISABLE = 4, /* disable writes */
3103 SF_RD_STATUS = 5, /* read status register */
3104 SF_WR_ENABLE = 6, /* enable writes */
3105 SF_RD_DATA_FAST = 0xb, /* read flash */
3106 SF_RD_ID = 0x9f, /* read ID */
3107 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3111 * sf1_read - read data from the serial flash
3112 * @adapter: the adapter
3113 * @byte_cnt: number of bytes to read
3114 * @cont: whether another operation will be chained
3115 * @lock: whether to lock SF for PL access only
3116 * @valp: where to store the read data
3118 * Reads up to 4 bytes of data from the serial flash. The location of
3119 * the read needs to be specified prior to calling this by issuing the
3120 * appropriate commands to the serial flash.
3122 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3123 int lock, u32 *valp)
3127 if (!byte_cnt || byte_cnt > 4)
3129 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3131 t4_write_reg(adapter, A_SF_OP,
3132 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3133 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3135 *valp = t4_read_reg(adapter, A_SF_DATA);
3140 * sf1_write - write data to the serial flash
3141 * @adapter: the adapter
3142 * @byte_cnt: number of bytes to write
3143 * @cont: whether another operation will be chained
3144 * @lock: whether to lock SF for PL access only
3145 * @val: value to write
3147 * Writes up to 4 bytes of data to the serial flash. The location of
3148 * the write needs to be specified prior to calling this by issuing the
3149 * appropriate commands to the serial flash.
3151 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3154 if (!byte_cnt || byte_cnt > 4)
3156 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3158 t4_write_reg(adapter, A_SF_DATA, val);
3159 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3160 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3161 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3165 * flash_wait_op - wait for a flash operation to complete
3166 * @adapter: the adapter
3167 * @attempts: max number of polls of the status register
3168 * @delay: delay between polls in ms
3170 * Wait for a flash operation to complete by polling the status register.
3172 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3178 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3179 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3183 if (--attempts == 0)
3191 * t4_read_flash - read words from serial flash
3192 * @adapter: the adapter
3193 * @addr: the start address for the read
3194 * @nwords: how many 32-bit words to read
3195 * @data: where to store the read data
3196 * @byte_oriented: whether to store data as bytes or as words
3198 * Read the specified number of 32-bit words from the serial flash.
3199 * If @byte_oriented is set the read data is stored as a byte array
3200 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3201 * natural endianness.
3203 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3204 unsigned int nwords, u32 *data, int byte_oriented)
3208 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3211 addr = swab32(addr) | SF_RD_DATA_FAST;
3213 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3214 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3217 for ( ; nwords; nwords--, data++) {
3218 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3220 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3224 *data = (__force __u32)(cpu_to_be32(*data));
3230 * t4_write_flash - write up to a page of data to the serial flash
3231 * @adapter: the adapter
3232 * @addr: the start address to write
3233 * @n: length of data to write in bytes
3234 * @data: the data to write
3235 * @byte_oriented: whether to store data as bytes or as words
3237 * Writes up to a page of data (256 bytes) to the serial flash starting
3238 * at the given address. All the data must be written to the same page.
3239 * If @byte_oriented is set the write data is stored as byte stream
3240 * (i.e. matches what on disk), otherwise in big-endian.
3242 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3243 unsigned int n, const u8 *data, int byte_oriented)
3246 u32 buf[SF_PAGE_SIZE / 4];
3247 unsigned int i, c, left, val, offset = addr & 0xff;
3249 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3252 val = swab32(addr) | SF_PROG_PAGE;
3254 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3255 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3258 for (left = n; left; left -= c) {
3260 for (val = 0, i = 0; i < c; ++i)
3261 val = (val << 8) + *data++;
3264 val = cpu_to_be32(val);
3266 ret = sf1_write(adapter, c, c != left, 1, val);
3270 ret = flash_wait_op(adapter, 8, 1);
3274 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3276 /* Read the page to verify the write succeeded */
3277 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3282 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3284 "failed to correctly write the flash page at %#x\n",
3291 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3296 * t4_get_fw_version - read the firmware version
3297 * @adapter: the adapter
3298 * @vers: where to place the version
3300 * Reads the FW version from flash.
3302 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3304 return t4_read_flash(adapter, FLASH_FW_START +
3305 offsetof(struct fw_hdr, fw_ver), 1,
3310 * t4_get_fw_hdr - read the firmware header
3311 * @adapter: the adapter
3312 * @hdr: where to place the version
3314 * Reads the FW header from flash into caller provided buffer.
3316 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3318 return t4_read_flash(adapter, FLASH_FW_START,
3319 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3323 * t4_get_bs_version - read the firmware bootstrap version
3324 * @adapter: the adapter
3325 * @vers: where to place the version
3327 * Reads the FW Bootstrap version from flash.
3329 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3331 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3332 offsetof(struct fw_hdr, fw_ver), 1,
3337 * t4_get_tp_version - read the TP microcode version
3338 * @adapter: the adapter
3339 * @vers: where to place the version
3341 * Reads the TP microcode version from flash.
3343 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3345 return t4_read_flash(adapter, FLASH_FW_START +
3346 offsetof(struct fw_hdr, tp_microcode_ver),
3351 * t4_get_exprom_version - return the Expansion ROM version (if any)
3352 * @adapter: the adapter
3353 * @vers: where to place the version
3355 * Reads the Expansion ROM header from FLASH and returns the version
3356 * number (if present) through the @vers return value pointer. We return
3357 * this in the Firmware Version Format since it's convenient. Return
3358 * 0 on success, -ENOENT if no Expansion ROM is present.
3360 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3362 struct exprom_header {
3363 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3364 unsigned char hdr_ver[4]; /* Expansion ROM version */
3366 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3370 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3371 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3376 hdr = (struct exprom_header *)exprom_header_buf;
3377 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3380 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3381 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3382 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3383 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3388 * t4_get_scfg_version - return the Serial Configuration version
3389 * @adapter: the adapter
3390 * @vers: where to place the version
3392 * Reads the Serial Configuration Version via the Firmware interface
3393 * (thus this can only be called once we're ready to issue Firmware
3394 * commands). The format of the Serial Configuration version is
3395 * adapter specific. Returns 0 on success, an error on failure.
3397 * Note that early versions of the Firmware didn't include the ability
3398 * to retrieve the Serial Configuration version, so we zero-out the
3399 * return-value parameter in that case to avoid leaving it with
3402 * Also note that the Firmware will return its cached copy of the Serial
3403 * Initialization Revision ID, not the actual Revision ID as written in
3404 * the Serial EEPROM. This is only an issue if a new VPD has been written
3405 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3406 * it's best to defer calling this routine till after a FW_RESET_CMD has
3407 * been issued if the Host Driver will be performing a full adapter
3410 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3415 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3416 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3417 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3418 1, &scfgrev_param, vers);
3425 * t4_get_vpd_version - return the VPD version
3426 * @adapter: the adapter
3427 * @vers: where to place the version
3429 * Reads the VPD via the Firmware interface (thus this can only be called
3430 * once we're ready to issue Firmware commands). The format of the
3431 * VPD version is adapter specific. Returns 0 on success, an error on
3434 * Note that early versions of the Firmware didn't include the ability
3435 * to retrieve the VPD version, so we zero-out the return-value parameter
3436 * in that case to avoid leaving it with garbage in it.
3438 * Also note that the Firmware will return its cached copy of the VPD
3439 * Revision ID, not the actual Revision ID as written in the Serial
3440 * EEPROM. This is only an issue if a new VPD has been written and the
3441 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3442 * to defer calling this routine till after a FW_RESET_CMD has been issued
3443 * if the Host Driver will be performing a full adapter initialization.
3445 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3450 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3451 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3452 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3453 1, &vpdrev_param, vers);
3460 * t4_get_version_info - extract various chip/firmware version information
3461 * @adapter: the adapter
3463 * Reads various chip/firmware version numbers and stores them into the
3464 * adapter Adapter Parameters structure. If any of the efforts fails
3465 * the first failure will be returned, but all of the version numbers
3468 int t4_get_version_info(struct adapter *adapter)
3472 #define FIRST_RET(__getvinfo) \
3474 int __ret = __getvinfo; \
3475 if (__ret && !ret) \
3479 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3480 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3481 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3482 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3483 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3484 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3492 * t4_flash_erase_sectors - erase a range of flash sectors
3493 * @adapter: the adapter
3494 * @start: the first sector to erase
3495 * @end: the last sector to erase
3497 * Erases the sectors in the given inclusive range.
3499 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3503 if (end >= adapter->params.sf_nsec)
3506 while (start <= end) {
3507 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3508 (ret = sf1_write(adapter, 4, 0, 1,
3509 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3510 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3512 "erase of flash sector %d failed, error %d\n",
3518 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3523 * t4_flash_cfg_addr - return the address of the flash configuration file
3524 * @adapter: the adapter
3526 * Return the address within the flash where the Firmware Configuration
3527 * File is stored, or an error if the device FLASH is too small to contain
3528 * a Firmware Configuration File.
3530 int t4_flash_cfg_addr(struct adapter *adapter)
3533 * If the device FLASH isn't large enough to hold a Firmware
3534 * Configuration File, return an error.
3536 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3539 return FLASH_CFG_START;
3543 * Return TRUE if the specified firmware matches the adapter. I.e. T4
3544 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3545 * and emit an error message for mismatched firmware to save our caller the
3548 static int t4_fw_matches_chip(struct adapter *adap,
3549 const struct fw_hdr *hdr)
3552 * The expression below will return FALSE for any unsupported adapter
3553 * which will keep us "honest" in the future ...
3555 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3556 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3557 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3561 "FW image (%d) is not suitable for this adapter (%d)\n",
3562 hdr->chip, chip_id(adap));
3567 * t4_load_fw - download firmware
3568 * @adap: the adapter
3569 * @fw_data: the firmware image to write
3572 * Write the supplied firmware image to the card's serial flash.
3574 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3579 u8 first_page[SF_PAGE_SIZE];
3580 const u32 *p = (const u32 *)fw_data;
3581 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3582 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3583 unsigned int fw_start_sec;
3584 unsigned int fw_start;
3585 unsigned int fw_size;
3587 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3588 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3589 fw_start = FLASH_FWBOOTSTRAP_START;
3590 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3592 fw_start_sec = FLASH_FW_START_SEC;
3593 fw_start = FLASH_FW_START;
3594 fw_size = FLASH_FW_MAX_SIZE;
3598 CH_ERR(adap, "FW image has no data\n");
3603 "FW image size not multiple of 512 bytes\n");
3606 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3608 "FW image size differs from size in FW header\n");
3611 if (size > fw_size) {
3612 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3616 if (!t4_fw_matches_chip(adap, hdr))
3619 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3620 csum += be32_to_cpu(p[i]);
3622 if (csum != 0xffffffff) {
3624 "corrupted firmware image, checksum %#x\n", csum);
3628 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3629 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3634 * We write the correct version at the end so the driver can see a bad
3635 * version if the FW write fails. Start by writing a copy of the
3636 * first page with a bad version.
3638 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3639 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3640 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3645 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3646 addr += SF_PAGE_SIZE;
3647 fw_data += SF_PAGE_SIZE;
3648 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3653 ret = t4_write_flash(adap,
3654 fw_start + offsetof(struct fw_hdr, fw_ver),
3655 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3658 CH_ERR(adap, "firmware download failed, error %d\n",
3664 * t4_fwcache - firmware cache operation
3665 * @adap: the adapter
3666 * @op : the operation (flush or flush and invalidate)
3668 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3670 struct fw_params_cmd c;
3672 memset(&c, 0, sizeof(c));
3674 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3675 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3676 V_FW_PARAMS_CMD_PFN(adap->pf) |
3677 V_FW_PARAMS_CMD_VFN(0));
3678 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3680 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3681 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3682 c.param[0].val = (__force __be32)op;
3684 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3687 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3688 unsigned int *pif_req_wrptr,
3689 unsigned int *pif_rsp_wrptr)
3692 u32 cfg, val, req, rsp;
3694 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3695 if (cfg & F_LADBGEN)
3696 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3698 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3699 req = G_POLADBGWRPTR(val);
3700 rsp = G_PILADBGWRPTR(val);
3702 *pif_req_wrptr = req;
3704 *pif_rsp_wrptr = rsp;
3706 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3707 for (j = 0; j < 6; j++) {
3708 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3709 V_PILADBGRDPTR(rsp));
3710 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3711 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3715 req = (req + 2) & M_POLADBGRDPTR;
3716 rsp = (rsp + 2) & M_PILADBGRDPTR;
3718 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3721 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3726 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3727 if (cfg & F_LADBGEN)
3728 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3730 for (i = 0; i < CIM_MALA_SIZE; i++) {
3731 for (j = 0; j < 5; j++) {
3733 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3734 V_PILADBGRDPTR(idx));
3735 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3736 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3739 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3742 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3746 for (i = 0; i < 8; i++) {
3747 u32 *p = la_buf + i;
3749 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3750 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3751 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3752 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3753 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3758 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3759 * @caps16: a 16-bit Port Capabilities value
3761 * Returns the equivalent 32-bit Port Capabilities value.
3763 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3765 uint32_t caps32 = 0;
3767 #define CAP16_TO_CAP32(__cap) \
3769 if (caps16 & FW_PORT_CAP_##__cap) \
3770 caps32 |= FW_PORT_CAP32_##__cap; \
3773 CAP16_TO_CAP32(SPEED_100M);
3774 CAP16_TO_CAP32(SPEED_1G);
3775 CAP16_TO_CAP32(SPEED_25G);
3776 CAP16_TO_CAP32(SPEED_10G);
3777 CAP16_TO_CAP32(SPEED_40G);
3778 CAP16_TO_CAP32(SPEED_100G);
3779 CAP16_TO_CAP32(FC_RX);
3780 CAP16_TO_CAP32(FC_TX);
3781 CAP16_TO_CAP32(ANEG);
3782 CAP16_TO_CAP32(FORCE_PAUSE);
3783 CAP16_TO_CAP32(MDIAUTO);
3784 CAP16_TO_CAP32(MDISTRAIGHT);
3785 CAP16_TO_CAP32(FEC_RS);
3786 CAP16_TO_CAP32(FEC_BASER_RS);
3787 CAP16_TO_CAP32(802_3_PAUSE);
3788 CAP16_TO_CAP32(802_3_ASM_DIR);
3790 #undef CAP16_TO_CAP32
3796 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3797 * @caps32: a 32-bit Port Capabilities value
3799 * Returns the equivalent 16-bit Port Capabilities value. Note that
3800 * not all 32-bit Port Capabilities can be represented in the 16-bit
3801 * Port Capabilities and some fields/values may not make it.
3803 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3805 uint16_t caps16 = 0;
3807 #define CAP32_TO_CAP16(__cap) \
3809 if (caps32 & FW_PORT_CAP32_##__cap) \
3810 caps16 |= FW_PORT_CAP_##__cap; \
3813 CAP32_TO_CAP16(SPEED_100M);
3814 CAP32_TO_CAP16(SPEED_1G);
3815 CAP32_TO_CAP16(SPEED_10G);
3816 CAP32_TO_CAP16(SPEED_25G);
3817 CAP32_TO_CAP16(SPEED_40G);
3818 CAP32_TO_CAP16(SPEED_100G);
3819 CAP32_TO_CAP16(FC_RX);
3820 CAP32_TO_CAP16(FC_TX);
3821 CAP32_TO_CAP16(802_3_PAUSE);
3822 CAP32_TO_CAP16(802_3_ASM_DIR);
3823 CAP32_TO_CAP16(ANEG);
3824 CAP32_TO_CAP16(FORCE_PAUSE);
3825 CAP32_TO_CAP16(MDIAUTO);
3826 CAP32_TO_CAP16(MDISTRAIGHT);
3827 CAP32_TO_CAP16(FEC_RS);
3828 CAP32_TO_CAP16(FEC_BASER_RS);
3830 #undef CAP32_TO_CAP16
3836 is_bt(struct port_info *pi)
3839 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
3840 pi->port_type == FW_PORT_TYPE_BT_XFI ||
3841 pi->port_type == FW_PORT_TYPE_BT_XAUI);
3844 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
3848 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0)
3849 return (unset_means_none ? FEC_NONE : 0);
3851 if (caps & FW_PORT_CAP32_FEC_RS)
3853 if (caps & FW_PORT_CAP32_FEC_BASER_RS)
3854 fec |= FEC_BASER_RS;
3855 if (caps & FW_PORT_CAP32_FEC_NO_FEC)
3862 * Note that 0 is not translated to NO_FEC.
3864 static uint32_t fec_to_fwcap(int8_t fec)
3868 /* Only real FECs allowed. */
3869 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0);
3872 caps |= FW_PORT_CAP32_FEC_RS;
3873 if (fec & FEC_BASER_RS)
3874 caps |= FW_PORT_CAP32_FEC_BASER_RS;
3876 caps |= FW_PORT_CAP32_FEC_NO_FEC;
3882 * t4_link_l1cfg - apply link configuration to MAC/PHY
3883 * @phy: the PHY to setup
3884 * @mac: the MAC to setup
3885 * @lc: the requested link configuration
3887 * Set up a port's MAC and PHY according to a desired link configuration.
3888 * - If the PHY can auto-negotiate first decide what to advertise, then
3889 * enable/disable auto-negotiation as desired, and reset.
3890 * - If the PHY does not auto-negotiate just reset it.
3891 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3892 * otherwise do it later based on the outcome of auto-negotiation.
3894 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3895 struct link_config *lc)
3897 struct fw_port_cmd c;
3898 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3899 unsigned int aneg, fc, fec, speed, rcap;
3902 if (lc->requested_fc & PAUSE_RX)
3903 fc |= FW_PORT_CAP32_FC_RX;
3904 if (lc->requested_fc & PAUSE_TX)
3905 fc |= FW_PORT_CAP32_FC_TX;
3906 if (!(lc->requested_fc & PAUSE_AUTONEG))
3907 fc |= FW_PORT_CAP32_FORCE_PAUSE;
3909 if (lc->requested_aneg == AUTONEG_DISABLE)
3911 else if (lc->requested_aneg == AUTONEG_ENABLE)
3912 aneg = FW_PORT_CAP32_ANEG;
3914 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3918 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3919 } else if (lc->requested_speed != 0)
3920 speed = speed_to_fwcap(lc->requested_speed);
3922 speed = fwcap_top_speed(lc->pcaps);
3925 if (fec_supported(lc->pcaps)) {
3926 if (lc->requested_fec == FEC_AUTO) {
3927 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) {
3928 if (speed & FW_PORT_CAP32_SPEED_100G) {
3929 fec |= FW_PORT_CAP32_FEC_RS;
3930 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3932 fec |= FW_PORT_CAP32_FEC_RS;
3933 fec |= FW_PORT_CAP32_FEC_BASER_RS;
3934 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3937 /* Set only 1b with old firmwares. */
3938 fec |= fec_to_fwcap(lc->fec_hint);
3941 fec |= fec_to_fwcap(lc->requested_fec &
3942 M_FW_PORT_CAP32_FEC);
3943 if (lc->requested_fec & FEC_MODULE)
3944 fec |= fec_to_fwcap(lc->fec_hint);
3947 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
3948 fec |= FW_PORT_CAP32_FORCE_FEC;
3949 else if (fec == FW_PORT_CAP32_FEC_NO_FEC)
3953 /* Force AN on for BT cards. */
3954 if (is_bt(adap->port[adap->chan_map[port]]))
3955 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3957 rcap = aneg | speed | fc | fec;
3958 if ((rcap | lc->pcaps) != lc->pcaps) {
3960 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap,
3961 lc->pcaps, rcap & (rcap ^ lc->pcaps));
3967 memset(&c, 0, sizeof(c));
3968 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3969 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3970 V_FW_PORT_CMD_PORTID(port));
3971 if (adap->params.port_caps32) {
3973 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
3975 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
3978 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3980 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
3983 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3987 * t4_restart_aneg - restart autonegotiation
3988 * @adap: the adapter
3989 * @mbox: mbox to use for the FW command
3990 * @port: the port id
3992 * Restarts autonegotiation for the selected port.
3994 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3996 struct fw_port_cmd c;
3998 memset(&c, 0, sizeof(c));
3999 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4000 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4001 V_FW_PORT_CMD_PORTID(port));
4003 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4005 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4006 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4009 struct intr_details {
4014 struct intr_action {
4017 bool (*action)(struct adapter *, int, bool);
4020 #define NONFATAL_IF_DISABLED 1
4022 const char *name; /* name of the INT_CAUSE register */
4023 int cause_reg; /* INT_CAUSE register */
4024 int enable_reg; /* INT_ENABLE register */
4025 u32 fatal; /* bits that are fatal */
4026 int flags; /* hints */
4027 const struct intr_details *details;
4028 const struct intr_action *actions;
4032 intr_alert_char(u32 cause, u32 enable, u32 fatal)
4043 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
4045 u32 enable, fatal, leftover;
4046 const struct intr_details *details;
4049 enable = t4_read_reg(adap, ii->enable_reg);
4050 if (ii->flags & NONFATAL_IF_DISABLED)
4051 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
4054 alert = intr_alert_char(cause, enable, fatal);
4055 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
4056 alert, ii->name, ii->cause_reg, cause, enable, fatal);
4059 for (details = ii->details; details && details->mask != 0; details++) {
4060 u32 msgbits = details->mask & cause;
4063 alert = intr_alert_char(msgbits, enable, ii->fatal);
4064 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits,
4066 leftover &= ~msgbits;
4068 if (leftover != 0 && leftover != cause)
4069 CH_ALERT(adap, " ? [0x%08x]\n", leftover);
4073 * Returns true for fatal error.
4076 t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4077 u32 additional_cause, bool verbose)
4081 const struct intr_action *action;
4084 * Read and display cause. Note that the top level PL_INT_CAUSE is a
4085 * bit special and we need to completely ignore the bits that are not in
4088 cause = t4_read_reg(adap, ii->cause_reg);
4089 if (ii->cause_reg == A_PL_INT_CAUSE)
4090 cause &= t4_read_reg(adap, ii->enable_reg);
4091 if (verbose || cause != 0)
4092 t4_show_intr_info(adap, ii, cause);
4093 fatal = cause & ii->fatal;
4094 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4095 fatal &= t4_read_reg(adap, ii->enable_reg);
4096 cause |= additional_cause;
4101 for (action = ii->actions; action && action->mask != 0; action++) {
4102 if (!(action->mask & cause))
4104 rc |= (action->action)(adap, action->arg, verbose);
4108 t4_write_reg(adap, ii->cause_reg, cause);
4109 (void)t4_read_reg(adap, ii->cause_reg);
4115 * Interrupt handler for the PCIE module.
4117 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4119 static const struct intr_details sysbus_intr_details[] = {
4120 { F_RNPP, "RXNP array parity error" },
4121 { F_RPCP, "RXPC array parity error" },
4122 { F_RCIP, "RXCIF array parity error" },
4123 { F_RCCP, "Rx completions control array parity error" },
4124 { F_RFTP, "RXFT array parity error" },
4127 static const struct intr_info sysbus_intr_info = {
4128 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4129 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4130 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4131 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4133 .details = sysbus_intr_details,
4136 static const struct intr_details pcie_port_intr_details[] = {
4137 { F_TPCP, "TXPC array parity error" },
4138 { F_TNPP, "TXNP array parity error" },
4139 { F_TFTP, "TXFT array parity error" },
4140 { F_TCAP, "TXCA array parity error" },
4141 { F_TCIP, "TXCIF array parity error" },
4142 { F_RCAP, "RXCA array parity error" },
4143 { F_OTDD, "outbound request TLP discarded" },
4144 { F_RDPE, "Rx data parity error" },
4145 { F_TDUE, "Tx uncorrectable data error" },
4148 static const struct intr_info pcie_port_intr_info = {
4149 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4150 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4151 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4152 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4153 F_OTDD | F_RDPE | F_TDUE,
4155 .details = pcie_port_intr_details,
4158 static const struct intr_details pcie_intr_details[] = {
4159 { F_MSIADDRLPERR, "MSI AddrL parity error" },
4160 { F_MSIADDRHPERR, "MSI AddrH parity error" },
4161 { F_MSIDATAPERR, "MSI data parity error" },
4162 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4163 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4164 { F_MSIXDATAPERR, "MSI-X data parity error" },
4165 { F_MSIXDIPERR, "MSI-X DI parity error" },
4166 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4167 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4168 { F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4169 { F_CCNTPERR, "PCIe CMD channel count parity error" },
4170 { F_CREQPERR, "PCIe CMD channel request parity error" },
4171 { F_CRSPPERR, "PCIe CMD channel response parity error" },
4172 { F_DCNTPERR, "PCIe DMA channel count parity error" },
4173 { F_DREQPERR, "PCIe DMA channel request parity error" },
4174 { F_DRSPPERR, "PCIe DMA channel response parity error" },
4175 { F_HCNTPERR, "PCIe HMA channel count parity error" },
4176 { F_HREQPERR, "PCIe HMA channel request parity error" },
4177 { F_HRSPPERR, "PCIe HMA channel response parity error" },
4178 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4179 { F_FIDPERR, "PCIe FID parity error" },
4180 { F_INTXCLRPERR, "PCIe INTx clear parity error" },
4181 { F_MATAGPERR, "PCIe MA tag parity error" },
4182 { F_PIOTAGPERR, "PCIe PIO tag parity error" },
4183 { F_RXCPLPERR, "PCIe Rx completion parity error" },
4184 { F_RXWRPERR, "PCIe Rx write parity error" },
4185 { F_RPLPERR, "PCIe replay buffer parity error" },
4186 { F_PCIESINT, "PCIe core secondary fault" },
4187 { F_PCIEPINT, "PCIe core primary fault" },
4188 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4191 static const struct intr_details t5_pcie_intr_details[] = {
4192 { F_IPGRPPERR, "Parity errors observed by IP" },
4193 { F_NONFATALERR, "PCIe non-fatal error" },
4194 { F_READRSPERR, "Outbound read error" },
4195 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4196 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4197 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4198 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4199 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4200 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4201 { F_MAGRPPERR, "MA group FIFO parity error" },
4202 { F_VFIDPERR, "VFID SRAM parity error" },
4203 { F_FIDPERR, "FID SRAM parity error" },
4204 { F_CFGSNPPERR, "config snoop FIFO parity error" },
4205 { F_HRSPPERR, "HMA channel response data SRAM parity error" },
4206 { F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4207 { F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4208 { F_DRSPPERR, "DMA channel response data SRAM parity error" },
4209 { F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4210 { F_CRSPPERR, "CMD channel response data SRAM parity error" },
4211 { F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4212 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4213 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4214 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4215 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4216 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4217 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4218 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4219 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4220 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4221 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4222 { F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4225 struct intr_info pcie_intr_info = {
4226 .name = "PCIE_INT_CAUSE",
4227 .cause_reg = A_PCIE_INT_CAUSE,
4228 .enable_reg = A_PCIE_INT_ENABLE,
4229 .fatal = 0xffffffff,
4230 .flags = NONFATAL_IF_DISABLED,
4237 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4238 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4240 pcie_intr_info.details = pcie_intr_details;
4242 pcie_intr_info.details = t5_pcie_intr_details;
4244 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4250 * TP interrupt handler.
4252 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4254 static const struct intr_details tp_intr_details[] = {
4255 { 0x3fffffff, "TP parity error" },
4256 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4259 static const struct intr_info tp_intr_info = {
4260 .name = "TP_INT_CAUSE",
4261 .cause_reg = A_TP_INT_CAUSE,
4262 .enable_reg = A_TP_INT_ENABLE,
4263 .fatal = 0x7fffffff,
4264 .flags = NONFATAL_IF_DISABLED,
4265 .details = tp_intr_details,
4269 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4273 * SGE interrupt handler.
4275 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4277 static const struct intr_info sge_int1_info = {
4278 .name = "SGE_INT_CAUSE1",
4279 .cause_reg = A_SGE_INT_CAUSE1,
4280 .enable_reg = A_SGE_INT_ENABLE1,
4281 .fatal = 0xffffffff,
4282 .flags = NONFATAL_IF_DISABLED,
4286 static const struct intr_info sge_int2_info = {
4287 .name = "SGE_INT_CAUSE2",
4288 .cause_reg = A_SGE_INT_CAUSE2,
4289 .enable_reg = A_SGE_INT_ENABLE2,
4290 .fatal = 0xffffffff,
4291 .flags = NONFATAL_IF_DISABLED,
4295 static const struct intr_details sge_int3_details[] = {
4297 "DBP pointer delivery for invalid context or QID" },
4298 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4299 "Invalid QID or header request by IDMA" },
4300 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4301 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4302 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4303 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4304 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4305 { F_ERR_TIMER_ABOVE_MAX_QID,
4306 "SGE GTS with timer 0-5 for IQID > 1023" },
4307 { F_ERR_CPL_EXCEED_IQE_SIZE,
4308 "SGE received CPL exceeding IQE size" },
4309 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4310 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4311 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4312 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4313 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4314 "SGE IQID > 1023 received CPL for FL" },
4315 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4316 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4317 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4318 { F_ERR_ING_CTXT_PRIO,
4319 "Ingress context manager priority user error" },
4320 { F_ERR_EGR_CTXT_PRIO,
4321 "Egress context manager priority user error" },
4322 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4323 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4324 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4325 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4326 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4327 { 0x0000000f, "SGE context access for invalid queue" },
4330 static const struct intr_details t6_sge_int3_details[] = {
4332 "DBP pointer delivery for invalid context or QID" },
4333 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4334 "Invalid QID or header request by IDMA" },
4335 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4336 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4337 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4338 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4339 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4340 { F_ERR_TIMER_ABOVE_MAX_QID,
4341 "SGE GTS with timer 0-5 for IQID > 1023" },
4342 { F_ERR_CPL_EXCEED_IQE_SIZE,
4343 "SGE received CPL exceeding IQE size" },
4344 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4345 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4346 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4347 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4348 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4349 "SGE IQID > 1023 received CPL for FL" },
4350 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4351 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4352 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4353 { F_ERR_ING_CTXT_PRIO,
4354 "Ingress context manager priority user error" },
4355 { F_ERR_EGR_CTXT_PRIO,
4356 "Egress context manager priority user error" },
4357 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4359 "SGE WRE packet less than advertized length" },
4360 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4361 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4362 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4363 { 0x0000000f, "SGE context access for invalid queue" },
4366 struct intr_info sge_int3_info = {
4367 .name = "SGE_INT_CAUSE3",
4368 .cause_reg = A_SGE_INT_CAUSE3,
4369 .enable_reg = A_SGE_INT_ENABLE3,
4370 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4375 static const struct intr_info sge_int4_info = {
4376 .name = "SGE_INT_CAUSE4",
4377 .cause_reg = A_SGE_INT_CAUSE4,
4378 .enable_reg = A_SGE_INT_ENABLE4,
4384 static const struct intr_info sge_int5_info = {
4385 .name = "SGE_INT_CAUSE5",
4386 .cause_reg = A_SGE_INT_CAUSE5,
4387 .enable_reg = A_SGE_INT_ENABLE5,
4388 .fatal = 0xffffffff,
4389 .flags = NONFATAL_IF_DISABLED,
4393 static const struct intr_info sge_int6_info = {
4394 .name = "SGE_INT_CAUSE6",
4395 .cause_reg = A_SGE_INT_CAUSE6,
4396 .enable_reg = A_SGE_INT_ENABLE6,
4406 if (chip_id(adap) <= CHELSIO_T5) {
4407 sge_int3_info.details = sge_int3_details;
4409 sge_int3_info.details = t6_sge_int3_details;
4413 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4414 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4415 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4416 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4417 if (chip_id(adap) >= CHELSIO_T5)
4418 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4419 if (chip_id(adap) >= CHELSIO_T6)
4420 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4422 v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4423 if (v & F_ERROR_QID_VALID) {
4424 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4425 if (v & F_UNCAPTURED_ERROR)
4426 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4427 t4_write_reg(adap, A_SGE_ERROR_STATS,
4428 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4435 * CIM interrupt handler.
4437 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4439 static const struct intr_action cim_host_intr_actions[] = {
4440 { F_TIMER0INT, 0, t4_os_dump_cimla },
4443 static const struct intr_details cim_host_intr_details[] = {
4445 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4448 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4449 { F_PLCIM_MSTRSPDATAPARERR,
4450 "PL2CIM master response data parity error" },
4451 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4452 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4453 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4454 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4455 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4456 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4459 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4460 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4461 { F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4462 { F_MBUPPARERR, "CIM mailbox uP parity error" },
4463 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4464 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4465 { F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4466 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4467 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */
4468 "CIM IBQ PCIe/SGE_HI parity error" },
4469 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4470 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4471 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4472 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4473 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4474 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4475 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4476 { F_TIMER1INT, "CIM TIMER0 interrupt" },
4477 { F_TIMER0INT, "CIM TIMER0 interrupt" },
4478 { F_PREFDROPINT, "CIM control register prefetch drop" },
4481 static const struct intr_info cim_host_intr_info = {
4482 .name = "CIM_HOST_INT_CAUSE",
4483 .cause_reg = A_CIM_HOST_INT_CAUSE,
4484 .enable_reg = A_CIM_HOST_INT_ENABLE,
4485 .fatal = 0x007fffe6,
4486 .flags = NONFATAL_IF_DISABLED,
4487 .details = cim_host_intr_details,
4488 .actions = cim_host_intr_actions,
4490 static const struct intr_details cim_host_upacc_intr_details[] = {
4491 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4492 { F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4493 { F_TIMEOUTINT, "CIM PIF timeout" },
4494 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4495 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4496 { F_BLKWRPLINT, "CIM block write to PL space" },
4497 { F_BLKRDPLINT, "CIM block read from PL space" },
4499 "CIM single write to PL space with illegal BEs" },
4501 "CIM single read from PL space with illegal BEs" },
4502 { F_BLKWRCTLINT, "CIM block write to CTL space" },
4503 { F_BLKRDCTLINT, "CIM block read from CTL space" },
4505 "CIM single write to CTL space with illegal BEs" },
4507 "CIM single read from CTL space with illegal BEs" },
4508 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4509 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4511 "CIM single write to EEPROM space with illegal BEs" },
4513 "CIM single read from EEPROM space with illegal BEs" },
4514 { F_BLKWRFLASHINT, "CIM block write to flash space" },
4515 { F_BLKRDFLASHINT, "CIM block read from flash space" },
4516 { F_SGLWRFLASHINT, "CIM single write to flash space" },
4518 "CIM single read from flash space with illegal BEs" },
4519 { F_BLKWRBOOTINT, "CIM block write to boot space" },
4520 { F_BLKRDBOOTINT, "CIM block read from boot space" },
4521 { F_SGLWRBOOTINT, "CIM single write to boot space" },
4523 "CIM single read from boot space with illegal BEs" },
4524 { F_ILLWRBEINT, "CIM illegal write BEs" },
4525 { F_ILLRDBEINT, "CIM illegal read BEs" },
4526 { F_ILLRDINT, "CIM illegal read" },
4527 { F_ILLWRINT, "CIM illegal write" },
4528 { F_ILLTRANSINT, "CIM illegal transaction" },
4529 { F_RSVDSPACEINT, "CIM reserved space access" },
4532 static const struct intr_info cim_host_upacc_intr_info = {
4533 .name = "CIM_HOST_UPACC_INT_CAUSE",
4534 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4535 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4536 .fatal = 0x3fffeeff,
4537 .flags = NONFATAL_IF_DISABLED,
4538 .details = cim_host_upacc_intr_details,
4541 static const struct intr_info cim_pf_host_intr_info = {
4542 .name = "CIM_PF_HOST_INT_CAUSE",
4543 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4544 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4553 fw_err = t4_read_reg(adap, A_PCIE_FW);
4554 if (fw_err & F_PCIE_FW_ERR)
4555 t4_report_fw_error(adap);
4558 * When the Firmware detects an internal error which normally wouldn't
4559 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4560 * to make sure the Host sees the Firmware Crash. So if we have a
4561 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4564 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4565 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4566 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4567 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4571 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4572 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4573 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4579 * ULP RX interrupt handler.
4581 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4583 static const struct intr_details ulprx_intr_details[] = {
4585 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4586 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4589 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4590 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4591 { 0x007fffff, "ULPRX parity error" },
4594 static const struct intr_info ulprx_intr_info = {
4595 .name = "ULP_RX_INT_CAUSE",
4596 .cause_reg = A_ULP_RX_INT_CAUSE,
4597 .enable_reg = A_ULP_RX_INT_ENABLE,
4598 .fatal = 0x07ffffff,
4599 .flags = NONFATAL_IF_DISABLED,
4600 .details = ulprx_intr_details,
4603 static const struct intr_info ulprx_intr2_info = {
4604 .name = "ULP_RX_INT_CAUSE_2",
4605 .cause_reg = A_ULP_RX_INT_CAUSE_2,
4606 .enable_reg = A_ULP_RX_INT_ENABLE_2,
4614 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4615 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4621 * ULP TX interrupt handler.
4623 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4625 static const struct intr_details ulptx_intr_details[] = {
4626 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4627 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4628 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4629 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4630 { 0x0fffffff, "ULPTX parity error" },
4633 static const struct intr_info ulptx_intr_info = {
4634 .name = "ULP_TX_INT_CAUSE",
4635 .cause_reg = A_ULP_TX_INT_CAUSE,
4636 .enable_reg = A_ULP_TX_INT_ENABLE,
4637 .fatal = 0x0fffffff,
4638 .flags = NONFATAL_IF_DISABLED,
4639 .details = ulptx_intr_details,
4642 static const struct intr_info ulptx_intr2_info = {
4643 .name = "ULP_TX_INT_CAUSE_2",
4644 .cause_reg = A_ULP_TX_INT_CAUSE_2,
4645 .enable_reg = A_ULP_TX_INT_ENABLE_2,
4647 .flags = NONFATAL_IF_DISABLED,
4653 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4654 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4659 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4664 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4665 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4666 for (i = 0; i < ARRAY_SIZE(data); i++) {
4667 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4668 A_PM_TX_DBG_STAT0 + i, data[i]);
4675 * PM TX interrupt handler.
4677 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4679 static const struct intr_action pmtx_intr_actions[] = {
4680 { 0xffffffff, 0, pmtx_dump_dbg_stats },
4683 static const struct intr_details pmtx_intr_details[] = {
4684 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4685 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4686 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4687 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4688 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4689 { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4690 { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4691 { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4692 { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4693 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4694 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4695 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4696 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4697 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4700 static const struct intr_info pmtx_intr_info = {
4701 .name = "PM_TX_INT_CAUSE",
4702 .cause_reg = A_PM_TX_INT_CAUSE,
4703 .enable_reg = A_PM_TX_INT_ENABLE,
4704 .fatal = 0xffffffff,
4706 .details = pmtx_intr_details,
4707 .actions = pmtx_intr_actions,
4710 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4714 * PM RX interrupt handler.
4716 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4718 static const struct intr_details pmrx_intr_details[] = {
4720 { 0x18000000, "PMRX ospi overflow" },
4721 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4722 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4723 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4724 { F_SDC_ERR, "PMRX SDC error" },
4727 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4728 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4729 { 0x0003c000, "PMRX iespi Rx framing error" },
4730 { 0x00003c00, "PMRX iespi Tx framing error" },
4731 { 0x00000300, "PMRX ocspi Rx framing error" },
4732 { 0x000000c0, "PMRX ocspi Tx framing error" },
4733 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4734 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4735 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4736 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4737 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4740 static const struct intr_info pmrx_intr_info = {
4741 .name = "PM_RX_INT_CAUSE",
4742 .cause_reg = A_PM_RX_INT_CAUSE,
4743 .enable_reg = A_PM_RX_INT_ENABLE,
4744 .fatal = 0x1fffffff,
4745 .flags = NONFATAL_IF_DISABLED,
4746 .details = pmrx_intr_details,
4750 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4754 * CPL switch interrupt handler.
4756 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4758 static const struct intr_details cplsw_intr_details[] = {
4760 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4761 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4764 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4765 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4766 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4767 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4768 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4769 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4772 static const struct intr_info cplsw_intr_info = {
4773 .name = "CPL_INTR_CAUSE",
4774 .cause_reg = A_CPL_INTR_CAUSE,
4775 .enable_reg = A_CPL_INTR_ENABLE,
4777 .flags = NONFATAL_IF_DISABLED,
4778 .details = cplsw_intr_details,
4782 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4785 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4786 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4787 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4788 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4789 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4790 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4791 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4792 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4793 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4796 * LE interrupt handler.
4798 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4800 static const struct intr_details le_intr_details[] = {
4801 { F_REQQPARERR, "LE request queue parity error" },
4802 { F_UNKNOWNCMD, "LE unknown command" },
4803 { F_ACTRGNFULL, "LE active region full" },
4804 { F_PARITYERR, "LE parity error" },
4805 { F_LIPMISS, "LE LIP miss" },
4806 { F_LIP0, "LE 0 LIP error" },
4809 static const struct intr_details t6_le_intr_details[] = {
4810 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4811 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4812 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4813 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4814 { F_TOTCNTERR, "LE total active < TCAM count" },
4815 { F_CMDPRSRINTERR, "LE internal error in parser" },
4816 { F_CMDTIDERR, "Incorrect tid in LE command" },
4817 { F_T6_ACTRGNFULL, "LE active region full" },
4818 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4819 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4820 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4821 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4822 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4823 { F_TCAMACCFAIL, "LE TCAM access failure" },
4824 { F_T6_UNKNOWNCMD, "LE unknown command" },
4825 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4826 { F_T6_LIPMISS, "LE CLIP lookup miss" },
4827 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4830 struct intr_info le_intr_info = {
4831 .name = "LE_DB_INT_CAUSE",
4832 .cause_reg = A_LE_DB_INT_CAUSE,
4833 .enable_reg = A_LE_DB_INT_ENABLE,
4835 .flags = NONFATAL_IF_DISABLED,
4840 if (chip_id(adap) <= CHELSIO_T5) {
4841 le_intr_info.details = le_intr_details;
4842 le_intr_info.fatal = T5_LE_FATAL_MASK;
4844 le_intr_info.details = t6_le_intr_details;
4845 le_intr_info.fatal = T6_LE_FATAL_MASK;
4848 return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4852 * MPS interrupt handler.
4854 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4856 static const struct intr_details mps_rx_perr_intr_details[] = {
4857 { 0xffffffff, "MPS Rx parity error" },
4860 static const struct intr_info mps_rx_perr_intr_info = {
4861 .name = "MPS_RX_PERR_INT_CAUSE",
4862 .cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4863 .enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4864 .fatal = 0xffffffff,
4865 .flags = NONFATAL_IF_DISABLED,
4866 .details = mps_rx_perr_intr_details,
4869 static const struct intr_details mps_tx_intr_details[] = {
4870 { F_PORTERR, "MPS Tx destination port is disabled" },
4871 { F_FRMERR, "MPS Tx framing error" },
4872 { F_SECNTERR, "MPS Tx SOP/EOP error" },
4873 { F_BUBBLE, "MPS Tx underflow" },
4874 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4875 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4876 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4877 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4880 static const struct intr_info mps_tx_intr_info = {
4881 .name = "MPS_TX_INT_CAUSE",
4882 .cause_reg = A_MPS_TX_INT_CAUSE,
4883 .enable_reg = A_MPS_TX_INT_ENABLE,
4885 .flags = NONFATAL_IF_DISABLED,
4886 .details = mps_tx_intr_details,
4889 static const struct intr_details mps_trc_intr_details[] = {
4890 { F_MISCPERR, "MPS TRC misc parity error" },
4891 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4892 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4895 static const struct intr_info mps_trc_intr_info = {
4896 .name = "MPS_TRC_INT_CAUSE",
4897 .cause_reg = A_MPS_TRC_INT_CAUSE,
4898 .enable_reg = A_MPS_TRC_INT_ENABLE,
4899 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4901 .details = mps_trc_intr_details,
4904 static const struct intr_details mps_stat_sram_intr_details[] = {
4905 { 0xffffffff, "MPS statistics SRAM parity error" },
4908 static const struct intr_info mps_stat_sram_intr_info = {
4909 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4910 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4911 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4912 .fatal = 0x1fffffff,
4913 .flags = NONFATAL_IF_DISABLED,
4914 .details = mps_stat_sram_intr_details,
4917 static const struct intr_details mps_stat_tx_intr_details[] = {
4918 { 0xffffff, "MPS statistics Tx FIFO parity error" },
4921 static const struct intr_info mps_stat_tx_intr_info = {
4922 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4923 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4924 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4926 .flags = NONFATAL_IF_DISABLED,
4927 .details = mps_stat_tx_intr_details,
4930 static const struct intr_details mps_stat_rx_intr_details[] = {
4931 { 0xffffff, "MPS statistics Rx FIFO parity error" },
4934 static const struct intr_info mps_stat_rx_intr_info = {
4935 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4936 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4937 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4940 .details = mps_stat_rx_intr_details,
4943 static const struct intr_details mps_cls_intr_details[] = {
4944 { F_HASHSRAM, "MPS hash SRAM parity error" },
4945 { F_MATCHTCAM, "MPS match TCAM parity error" },
4946 { F_MATCHSRAM, "MPS match SRAM parity error" },
4949 static const struct intr_info mps_cls_intr_info = {
4950 .name = "MPS_CLS_INT_CAUSE",
4951 .cause_reg = A_MPS_CLS_INT_CAUSE,
4952 .enable_reg = A_MPS_CLS_INT_ENABLE,
4953 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4955 .details = mps_cls_intr_details,
4958 static const struct intr_details mps_stat_sram1_intr_details[] = {
4959 { 0xff, "MPS statistics SRAM1 parity error" },
4962 static const struct intr_info mps_stat_sram1_intr_info = {
4963 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4964 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4965 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4968 .details = mps_stat_sram1_intr_details,
4975 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
4976 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
4977 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
4978 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
4979 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
4980 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
4981 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
4982 if (chip_id(adap) > CHELSIO_T4) {
4983 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
4987 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
4988 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */
4995 * EDC/MC interrupt handler.
4997 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
4999 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
5000 unsigned int count_reg, v;
5001 static const struct intr_details mem_intr_details[] = {
5002 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
5003 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
5004 { F_PERR_INT_CAUSE, "FIFO parity error" },
5007 struct intr_info ii = {
5008 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
5009 .details = mem_intr_details,
5017 ii.name = "EDC0_INT_CAUSE";
5018 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
5019 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
5020 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
5023 ii.name = "EDC1_INT_CAUSE";
5024 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
5025 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
5026 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
5029 ii.name = "MC0_INT_CAUSE";
5031 ii.cause_reg = A_MC_INT_CAUSE;
5032 ii.enable_reg = A_MC_INT_ENABLE;
5033 count_reg = A_MC_ECC_STATUS;
5035 ii.cause_reg = A_MC_P_INT_CAUSE;
5036 ii.enable_reg = A_MC_P_INT_ENABLE;
5037 count_reg = A_MC_P_ECC_STATUS;
5041 ii.name = "MC1_INT_CAUSE";
5042 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
5043 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
5044 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
5048 fatal = t4_handle_intr(adap, &ii, 0, verbose);
5050 v = t4_read_reg(adap, count_reg);
5052 if (G_ECC_UECNT(v) != 0) {
5054 "%s: %u uncorrectable ECC data error(s)\n",
5055 name[idx], G_ECC_UECNT(v));
5057 if (G_ECC_CECNT(v) != 0) {
5058 if (idx <= MEM_EDC1)
5059 t4_edc_err_read(adap, idx);
5060 CH_WARN_RATELIMIT(adap,
5061 "%s: %u correctable ECC data error(s)\n",
5062 name[idx], G_ECC_CECNT(v));
5064 t4_write_reg(adap, count_reg, 0xffffffff);
5070 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5074 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5076 "MA address wrap-around error by client %u to address %#x\n",
5077 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5078 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5085 * MA interrupt handler.
5087 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5089 static const struct intr_action ma_intr_actions[] = {
5090 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5093 static const struct intr_info ma_intr_info = {
5094 .name = "MA_INT_CAUSE",
5095 .cause_reg = A_MA_INT_CAUSE,
5096 .enable_reg = A_MA_INT_ENABLE,
5097 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5098 .flags = NONFATAL_IF_DISABLED,
5100 .actions = ma_intr_actions,
5102 static const struct intr_info ma_perr_status1 = {
5103 .name = "MA_PARITY_ERROR_STATUS1",
5104 .cause_reg = A_MA_PARITY_ERROR_STATUS1,
5105 .enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5106 .fatal = 0xffffffff,
5111 static const struct intr_info ma_perr_status2 = {
5112 .name = "MA_PARITY_ERROR_STATUS2",
5113 .cause_reg = A_MA_PARITY_ERROR_STATUS2,
5114 .enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5115 .fatal = 0xffffffff,
5123 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5124 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5125 if (chip_id(adap) > CHELSIO_T4)
5126 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5132 * SMB interrupt handler.
5134 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5136 static const struct intr_details smb_intr_details[] = {
5137 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5138 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5139 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5142 static const struct intr_info smb_intr_info = {
5143 .name = "SMB_INT_CAUSE",
5144 .cause_reg = A_SMB_INT_CAUSE,
5145 .enable_reg = A_SMB_INT_ENABLE,
5146 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5148 .details = smb_intr_details,
5152 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5156 * NC-SI interrupt handler.
5158 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5160 static const struct intr_details ncsi_intr_details[] = {
5161 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5162 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5163 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5164 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5167 static const struct intr_info ncsi_intr_info = {
5168 .name = "NCSI_INT_CAUSE",
5169 .cause_reg = A_NCSI_INT_CAUSE,
5170 .enable_reg = A_NCSI_INT_ENABLE,
5171 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5172 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5174 .details = ncsi_intr_details,
5178 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5182 * MAC interrupt handler.
5184 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5186 static const struct intr_details mac_intr_details[] = {
5187 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5188 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5192 struct intr_info ii;
5196 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5198 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5199 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5200 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5202 ii.details = mac_intr_details;
5205 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5207 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5208 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5209 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5211 ii.details = mac_intr_details;
5214 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5216 if (chip_id(adap) >= CHELSIO_T5) {
5217 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5219 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5220 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5225 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5228 if (chip_id(adap) >= CHELSIO_T6) {
5229 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5231 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5232 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5237 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5243 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5245 static const struct intr_details plpl_intr_details[] = {
5246 { F_FATALPERR, "Fatal parity error" },
5247 { F_PERRVFID, "VFID_MAP parity error" },
5250 static const struct intr_info plpl_intr_info = {
5251 .name = "PL_PL_INT_CAUSE",
5252 .cause_reg = A_PL_PL_INT_CAUSE,
5253 .enable_reg = A_PL_PL_INT_ENABLE,
5254 .fatal = F_FATALPERR | F_PERRVFID,
5255 .flags = NONFATAL_IF_DISABLED,
5256 .details = plpl_intr_details,
5260 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5264 * t4_slow_intr_handler - control path interrupt handler
5265 * @adap: the adapter
5266 * @verbose: increased verbosity, for debug
5268 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5269 * The designation 'slow' is because it involves register reads, while
5270 * data interrupts typically don't involve any MMIOs.
5272 int t4_slow_intr_handler(struct adapter *adap, bool verbose)
5274 static const struct intr_details pl_intr_details[] = {
5277 { F_ULP_TX, "ULP TX" },
5280 { F_CPL_SWITCH, "CPL Switch" },
5281 { F_ULP_RX, "ULP RX" },
5282 { F_PM_RX, "PM RX" },
5283 { F_PM_TX, "PM TX" },
5299 { F_NCSI, "NC-SI" },
5307 static const struct intr_info pl_perr_cause = {
5308 .name = "PL_PERR_CAUSE",
5309 .cause_reg = A_PL_PERR_CAUSE,
5310 .enable_reg = A_PL_PERR_ENABLE,
5311 .fatal = 0xffffffff,
5313 .details = pl_intr_details,
5316 static const struct intr_action pl_intr_action[] = {
5317 { F_MC1, MEM_MC1, mem_intr_handler },
5318 { F_ULP_TX, -1, ulptx_intr_handler },
5319 { F_SGE, -1, sge_intr_handler },
5320 { F_CPL_SWITCH, -1, cplsw_intr_handler },
5321 { F_ULP_RX, -1, ulprx_intr_handler },
5322 { F_PM_RX, -1, pmrx_intr_handler},
5323 { F_PM_TX, -1, pmtx_intr_handler},
5324 { F_MA, -1, ma_intr_handler },
5325 { F_TP, -1, tp_intr_handler },
5326 { F_LE, -1, le_intr_handler },
5327 { F_EDC1, MEM_EDC1, mem_intr_handler },
5328 { F_EDC0, MEM_EDC0, mem_intr_handler },
5329 { F_MC0, MEM_MC0, mem_intr_handler },
5330 { F_PCIE, -1, pcie_intr_handler },
5331 { F_MAC3, 3, mac_intr_handler},
5332 { F_MAC2, 2, mac_intr_handler},
5333 { F_MAC1, 1, mac_intr_handler},
5334 { F_MAC0, 0, mac_intr_handler},
5335 { F_SMB, -1, smb_intr_handler},
5336 { F_PL, -1, plpl_intr_handler },
5337 { F_NCSI, -1, ncsi_intr_handler},
5338 { F_MPS, -1, mps_intr_handler },
5339 { F_CIM, -1, cim_intr_handler },
5342 static const struct intr_info pl_intr_info = {
5343 .name = "PL_INT_CAUSE",
5344 .cause_reg = A_PL_INT_CAUSE,
5345 .enable_reg = A_PL_INT_ENABLE,
5348 .details = pl_intr_details,
5349 .actions = pl_intr_action,
5354 perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5355 if (verbose || perr != 0) {
5356 t4_show_intr_info(adap, &pl_perr_cause, perr);
5358 t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5360 perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5362 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose);
5364 t4_fatal_err(adap, false);
5369 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
5372 * t4_intr_enable - enable interrupts
5373 * @adapter: the adapter whose interrupts should be enabled
5375 * Enable PF-specific interrupts for the calling function and the top-level
5376 * interrupt concentrator for global interrupts. Interrupts are already
5377 * enabled at each module, here we just enable the roots of the interrupt
5380 * Note: this function should be called only when the driver manages
5381 * non PF-specific interrupts from the various HW modules. Only one PCI
5382 * function at a time should be doing this.
5384 void t4_intr_enable(struct adapter *adap)
5388 if (chip_id(adap) <= CHELSIO_T5)
5389 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5391 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5392 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5393 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5394 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5395 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5396 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5398 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5399 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5400 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5401 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5405 * t4_intr_disable - disable interrupts
5406 * @adap: the adapter whose interrupts should be disabled
5408 * Disable interrupts. We only disable the top-level interrupt
5409 * concentrators. The caller must be a PCI function managing global
5412 void t4_intr_disable(struct adapter *adap)
5415 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5416 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5420 * t4_intr_clear - clear all interrupts
5421 * @adap: the adapter whose interrupts should be cleared
5423 * Clears all interrupts. The caller must be a PCI function managing
5424 * global interrupts.
5426 void t4_intr_clear(struct adapter *adap)
5428 static const u32 cause_reg[] = {
5429 A_CIM_HOST_INT_CAUSE,
5430 A_CIM_HOST_UPACC_INT_CAUSE,
5431 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5433 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
5435 A_MA_INT_WRAP_STATUS,
5436 A_MA_PARITY_ERROR_STATUS1,
5438 A_MPS_CLS_INT_CAUSE,
5439 A_MPS_RX_PERR_INT_CAUSE,
5440 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
5441 A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5442 A_MPS_TRC_INT_CAUSE,
5444 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
5458 A_ULP_RX_INT_CAUSE_2,
5460 A_ULP_TX_INT_CAUSE_2,
5462 MYPF_REG(A_PL_PF_INT_CAUSE),
5465 const int nchan = adap->chip_params->nchan;
5467 for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5468 t4_write_reg(adap, cause_reg[i], 0xffffffff);
5471 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
5473 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
5475 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
5476 for (i = 0; i < nchan; i++) {
5477 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
5481 if (chip_id(adap) >= CHELSIO_T5) {
5482 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
5483 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
5484 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
5485 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
5487 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
5490 for (i = 0; i < nchan; i++) {
5491 t4_write_reg(adap, T5_PORT_REG(i,
5492 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
5493 if (chip_id(adap) > CHELSIO_T5) {
5494 t4_write_reg(adap, T5_PORT_REG(i,
5495 A_MAC_PORT_PERR_INT_CAUSE_100G),
5498 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
5502 if (chip_id(adap) >= CHELSIO_T6) {
5503 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
5506 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5507 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
5508 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
5509 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */
5513 * hash_mac_addr - return the hash value of a MAC address
5514 * @addr: the 48-bit Ethernet MAC address
5516 * Hashes a MAC address according to the hash function used by HW inexact
5517 * (hash) address matching.
5519 static int hash_mac_addr(const u8 *addr)
5521 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5522 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5530 * t4_config_rss_range - configure a portion of the RSS mapping table
5531 * @adapter: the adapter
5532 * @mbox: mbox to use for the FW command
5533 * @viid: virtual interface whose RSS subtable is to be written
5534 * @start: start entry in the table to write
5535 * @n: how many table entries to write
5536 * @rspq: values for the "response queue" (Ingress Queue) lookup table
5537 * @nrspq: number of values in @rspq
5539 * Programs the selected part of the VI's RSS mapping table with the
5540 * provided values. If @nrspq < @n the supplied values are used repeatedly
5541 * until the full table range is populated.
5543 * The caller must ensure the values in @rspq are in the range allowed for
5546 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5547 int start, int n, const u16 *rspq, unsigned int nrspq)
5550 const u16 *rsp = rspq;
5551 const u16 *rsp_end = rspq + nrspq;
5552 struct fw_rss_ind_tbl_cmd cmd;
5554 memset(&cmd, 0, sizeof(cmd));
5555 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5556 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5557 V_FW_RSS_IND_TBL_CMD_VIID(viid));
5558 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5561 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5562 * Queue Identifiers. These Ingress Queue IDs are packed three to
5563 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5567 int nq = min(n, 32);
5569 __be32 *qp = &cmd.iq0_to_iq2;
5572 * Set up the firmware RSS command header to send the next
5573 * "nq" Ingress Queue IDs to the firmware.
5575 cmd.niqid = cpu_to_be16(nq);
5576 cmd.startidx = cpu_to_be16(start);
5579 * "nq" more done for the start of the next loop.
5585 * While there are still Ingress Queue IDs to stuff into the
5586 * current firmware RSS command, retrieve them from the
5587 * Ingress Queue ID array and insert them into the command.
5591 * Grab up to the next 3 Ingress Queue IDs (wrapping
5592 * around the Ingress Queue ID array if necessary) and
5593 * insert them into the firmware RSS command at the
5594 * current 3-tuple position within the commad.
5598 int nqbuf = min(3, nq);
5601 qbuf[0] = qbuf[1] = qbuf[2] = 0;
5602 while (nqbuf && nq_packed < 32) {
5609 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5610 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5611 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5615 * Send this portion of the RRS table update to the firmware;
5616 * bail out on any errors.
5618 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5626 * t4_config_glbl_rss - configure the global RSS mode
5627 * @adapter: the adapter
5628 * @mbox: mbox to use for the FW command
5629 * @mode: global RSS mode
5630 * @flags: mode-specific flags
5632 * Sets the global RSS mode.
5634 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5637 struct fw_rss_glb_config_cmd c;
5639 memset(&c, 0, sizeof(c));
5640 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5641 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5642 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5643 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5644 c.u.manual.mode_pkd =
5645 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5646 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5647 c.u.basicvirtual.mode_keymode =
5648 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5649 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5652 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5656 * t4_config_vi_rss - configure per VI RSS settings
5657 * @adapter: the adapter
5658 * @mbox: mbox to use for the FW command
5661 * @defq: id of the default RSS queue for the VI.
5662 * @skeyidx: RSS secret key table index for non-global mode
5663 * @skey: RSS vf_scramble key for VI.
5665 * Configures VI-specific RSS properties.
5667 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5668 unsigned int flags, unsigned int defq, unsigned int skeyidx,
5671 struct fw_rss_vi_config_cmd c;
5673 memset(&c, 0, sizeof(c));
5674 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5675 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5676 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5677 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5678 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5679 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5680 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5681 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5682 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5684 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5687 /* Read an RSS table row */
5688 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5690 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5691 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5696 * t4_read_rss - read the contents of the RSS mapping table
5697 * @adapter: the adapter
5698 * @map: holds the contents of the RSS mapping table
5700 * Reads the contents of the RSS hash->queue mapping table.
5702 int t4_read_rss(struct adapter *adapter, u16 *map)
5707 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5708 ret = rd_rss_row(adapter, i, &val);
5711 *map++ = G_LKPTBLQUEUE0(val);
5712 *map++ = G_LKPTBLQUEUE1(val);
5718 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5719 * @adap: the adapter
5720 * @cmd: TP fw ldst address space type
5721 * @vals: where the indirect register values are stored/written
5722 * @nregs: how many indirect registers to read/write
5723 * @start_idx: index of first indirect register to read/write
5724 * @rw: Read (1) or Write (0)
5725 * @sleep_ok: if true we may sleep while awaiting command completion
5727 * Access TP indirect registers through LDST
5729 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5730 unsigned int nregs, unsigned int start_index,
5731 unsigned int rw, bool sleep_ok)
5735 struct fw_ldst_cmd c;
5737 for (i = 0; i < nregs; i++) {
5738 memset(&c, 0, sizeof(c));
5739 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5741 (rw ? F_FW_CMD_READ :
5743 V_FW_LDST_CMD_ADDRSPACE(cmd));
5744 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5746 c.u.addrval.addr = cpu_to_be32(start_index + i);
5747 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5748 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5754 vals[i] = be32_to_cpu(c.u.addrval.val);
5760 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5761 * @adap: the adapter
5762 * @reg_addr: Address Register
5763 * @reg_data: Data register
5764 * @buff: where the indirect register values are stored/written
5765 * @nregs: how many indirect registers to read/write
5766 * @start_index: index of first indirect register to read/write
5767 * @rw: READ(1) or WRITE(0)
5768 * @sleep_ok: if true we may sleep while awaiting command completion
5770 * Read/Write TP indirect registers through LDST if possible.
5771 * Else, use backdoor access
5773 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5774 u32 *buff, u32 nregs, u32 start_index, int rw,
5782 cmd = FW_LDST_ADDRSPC_TP_PIO;
5784 case A_TP_TM_PIO_ADDR:
5785 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5787 case A_TP_MIB_INDEX:
5788 cmd = FW_LDST_ADDRSPC_TP_MIB;
5791 goto indirect_access;
5794 if (t4_use_ldst(adap))
5795 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5802 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5805 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5811 * t4_tp_pio_read - Read TP PIO registers
5812 * @adap: the adapter
5813 * @buff: where the indirect register values are written
5814 * @nregs: how many indirect registers to read
5815 * @start_index: index of first indirect register to read
5816 * @sleep_ok: if true we may sleep while awaiting command completion
5818 * Read TP PIO Registers
5820 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5821 u32 start_index, bool sleep_ok)
5823 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5824 start_index, 1, sleep_ok);
5828 * t4_tp_pio_write - Write TP PIO registers
5829 * @adap: the adapter
5830 * @buff: where the indirect register values are stored
5831 * @nregs: how many indirect registers to write
5832 * @start_index: index of first indirect register to write
5833 * @sleep_ok: if true we may sleep while awaiting command completion
5835 * Write TP PIO Registers
5837 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5838 u32 start_index, bool sleep_ok)
5840 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5841 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5845 * t4_tp_tm_pio_read - Read TP TM PIO registers
5846 * @adap: the adapter
5847 * @buff: where the indirect register values are written
5848 * @nregs: how many indirect registers to read
5849 * @start_index: index of first indirect register to read
5850 * @sleep_ok: if true we may sleep while awaiting command completion
5852 * Read TP TM PIO Registers
5854 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5855 u32 start_index, bool sleep_ok)
5857 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5858 nregs, start_index, 1, sleep_ok);
5862 * t4_tp_mib_read - Read TP MIB registers
5863 * @adap: the adapter
5864 * @buff: where the indirect register values are written
5865 * @nregs: how many indirect registers to read
5866 * @start_index: index of first indirect register to read
5867 * @sleep_ok: if true we may sleep while awaiting command completion
5869 * Read TP MIB Registers
5871 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5874 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5875 start_index, 1, sleep_ok);
5879 * t4_read_rss_key - read the global RSS key
5880 * @adap: the adapter
5881 * @key: 10-entry array holding the 320-bit RSS key
5882 * @sleep_ok: if true we may sleep while awaiting command completion
5884 * Reads the global 320-bit RSS key.
5886 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5888 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5892 * t4_write_rss_key - program one of the RSS keys
5893 * @adap: the adapter
5894 * @key: 10-entry array holding the 320-bit RSS key
5895 * @idx: which RSS key to write
5896 * @sleep_ok: if true we may sleep while awaiting command completion
5898 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5899 * 0..15 the corresponding entry in the RSS key table is written,
5900 * otherwise the global RSS key is written.
5902 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5905 u8 rss_key_addr_cnt = 16;
5906 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5909 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5910 * allows access to key addresses 16-63 by using KeyWrAddrX
5911 * as index[5:4](upper 2) into key table
5913 if ((chip_id(adap) > CHELSIO_T5) &&
5914 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5915 rss_key_addr_cnt = 32;
5917 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5919 if (idx >= 0 && idx < rss_key_addr_cnt) {
5920 if (rss_key_addr_cnt > 16)
5921 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5922 vrt | V_KEYWRADDRX(idx >> 4) |
5923 V_T6_VFWRADDR(idx) | F_KEYWREN);
5925 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5926 vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5931 * t4_read_rss_pf_config - read PF RSS Configuration Table
5932 * @adapter: the adapter
5933 * @index: the entry in the PF RSS table to read
5934 * @valp: where to store the returned value
5935 * @sleep_ok: if true we may sleep while awaiting command completion
5937 * Reads the PF RSS Configuration Table at the specified index and returns
5938 * the value found there.
5940 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5941 u32 *valp, bool sleep_ok)
5943 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5947 * t4_write_rss_pf_config - write PF RSS Configuration Table
5948 * @adapter: the adapter
5949 * @index: the entry in the VF RSS table to read
5950 * @val: the value to store
5951 * @sleep_ok: if true we may sleep while awaiting command completion
5953 * Writes the PF RSS Configuration Table at the specified index with the
5956 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5957 u32 val, bool sleep_ok)
5959 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5964 * t4_read_rss_vf_config - read VF RSS Configuration Table
5965 * @adapter: the adapter
5966 * @index: the entry in the VF RSS table to read
5967 * @vfl: where to store the returned VFL
5968 * @vfh: where to store the returned VFH
5969 * @sleep_ok: if true we may sleep while awaiting command completion
5971 * Reads the VF RSS Configuration Table at the specified index and returns
5972 * the (VFL, VFH) values found there.
5974 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5975 u32 *vfl, u32 *vfh, bool sleep_ok)
5977 u32 vrt, mask, data;
5979 if (chip_id(adapter) <= CHELSIO_T5) {
5980 mask = V_VFWRADDR(M_VFWRADDR);
5981 data = V_VFWRADDR(index);
5983 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
5984 data = V_T6_VFWRADDR(index);
5987 * Request that the index'th VF Table values be read into VFL/VFH.
5989 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5990 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5991 vrt |= data | F_VFRDEN;
5992 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5995 * Grab the VFL/VFH values ...
5997 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5998 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
6002 * t4_write_rss_vf_config - write VF RSS Configuration Table
6004 * @adapter: the adapter
6005 * @index: the entry in the VF RSS table to write
6006 * @vfl: the VFL to store
6007 * @vfh: the VFH to store
6009 * Writes the VF RSS Configuration Table at the specified index with the
6010 * specified (VFL, VFH) values.
6012 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
6013 u32 vfl, u32 vfh, bool sleep_ok)
6015 u32 vrt, mask, data;
6017 if (chip_id(adapter) <= CHELSIO_T5) {
6018 mask = V_VFWRADDR(M_VFWRADDR);
6019 data = V_VFWRADDR(index);
6021 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
6022 data = V_T6_VFWRADDR(index);
6026 * Load up VFL/VFH with the values to be written ...
6028 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
6029 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
6032 * Write the VFL/VFH into the VF Table at index'th location.
6034 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
6035 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
6036 vrt |= data | F_VFRDEN;
6037 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
6041 * t4_read_rss_pf_map - read PF RSS Map
6042 * @adapter: the adapter
6043 * @sleep_ok: if true we may sleep while awaiting command completion
6045 * Reads the PF RSS Map register and returns its value.
6047 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
6051 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6057 * t4_write_rss_pf_map - write PF RSS Map
6058 * @adapter: the adapter
6059 * @pfmap: PF RSS Map value
6061 * Writes the specified value to the PF RSS Map register.
6063 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6065 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6069 * t4_read_rss_pf_mask - read PF RSS Mask
6070 * @adapter: the adapter
6071 * @sleep_ok: if true we may sleep while awaiting command completion
6073 * Reads the PF RSS Mask register and returns its value.
6075 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6079 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6085 * t4_write_rss_pf_mask - write PF RSS Mask
6086 * @adapter: the adapter
6087 * @pfmask: PF RSS Mask value
6089 * Writes the specified value to the PF RSS Mask register.
6091 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6093 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6097 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
6098 * @adap: the adapter
6099 * @v4: holds the TCP/IP counter values
6100 * @v6: holds the TCP/IPv6 counter values
6101 * @sleep_ok: if true we may sleep while awaiting command completion
6103 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
6104 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
6106 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6107 struct tp_tcp_stats *v6, bool sleep_ok)
6109 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6111 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6112 #define STAT(x) val[STAT_IDX(x)]
6113 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6116 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6117 A_TP_MIB_TCP_OUT_RST, sleep_ok);
6118 v4->tcp_out_rsts = STAT(OUT_RST);
6119 v4->tcp_in_segs = STAT64(IN_SEG);
6120 v4->tcp_out_segs = STAT64(OUT_SEG);
6121 v4->tcp_retrans_segs = STAT64(RXT_SEG);
6124 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6125 A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6126 v6->tcp_out_rsts = STAT(OUT_RST);
6127 v6->tcp_in_segs = STAT64(IN_SEG);
6128 v6->tcp_out_segs = STAT64(OUT_SEG);
6129 v6->tcp_retrans_segs = STAT64(RXT_SEG);
6137 * t4_tp_get_err_stats - read TP's error MIB counters
6138 * @adap: the adapter
6139 * @st: holds the counter values
6140 * @sleep_ok: if true we may sleep while awaiting command completion
6142 * Returns the values of TP's error counters.
6144 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6147 int nchan = adap->chip_params->nchan;
6149 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6152 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6155 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6158 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6159 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6161 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6162 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6164 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6167 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6168 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6170 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6171 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6173 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6178 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
6179 * @adap: the adapter
6180 * @st: holds the counter values
6182 * Returns the values of TP's proxy counters.
6184 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6187 int nchan = adap->chip_params->nchan;
6189 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6193 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
6194 * @adap: the adapter
6195 * @st: holds the counter values
6196 * @sleep_ok: if true we may sleep while awaiting command completion
6198 * Returns the values of TP's CPL counters.
6200 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6203 int nchan = adap->chip_params->nchan;
6205 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6207 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6211 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6212 * @adap: the adapter
6213 * @st: holds the counter values
6215 * Returns the values of TP's RDMA counters.
6217 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6220 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6225 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6226 * @adap: the adapter
6227 * @idx: the port index
6228 * @st: holds the counter values
6229 * @sleep_ok: if true we may sleep while awaiting command completion
6231 * Returns the values of TP's FCoE counters for the selected port.
6233 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6234 struct tp_fcoe_stats *st, bool sleep_ok)
6238 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6241 t4_tp_mib_read(adap, &st->frames_drop, 1,
6242 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6244 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6247 st->octets_ddp = ((u64)val[0] << 32) | val[1];
6251 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6252 * @adap: the adapter
6253 * @st: holds the counter values
6254 * @sleep_ok: if true we may sleep while awaiting command completion
6256 * Returns the values of TP's counters for non-TCP directly-placed packets.
6258 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6263 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6265 st->frames = val[0];
6267 st->octets = ((u64)val[2] << 32) | val[3];
6271 * t4_read_mtu_tbl - returns the values in the HW path MTU table
6272 * @adap: the adapter
6273 * @mtus: where to store the MTU values
6274 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
6276 * Reads the HW path MTU table.
6278 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6283 for (i = 0; i < NMTUS; ++i) {
6284 t4_write_reg(adap, A_TP_MTU_TABLE,
6285 V_MTUINDEX(0xff) | V_MTUVALUE(i));
6286 v = t4_read_reg(adap, A_TP_MTU_TABLE);
6287 mtus[i] = G_MTUVALUE(v);
6289 mtu_log[i] = G_MTUWIDTH(v);
6294 * t4_read_cong_tbl - reads the congestion control table
6295 * @adap: the adapter
6296 * @incr: where to store the alpha values
6298 * Reads the additive increments programmed into the HW congestion
6301 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6303 unsigned int mtu, w;
6305 for (mtu = 0; mtu < NMTUS; ++mtu)
6306 for (w = 0; w < NCCTRL_WIN; ++w) {
6307 t4_write_reg(adap, A_TP_CCTRL_TABLE,
6308 V_ROWINDEX(0xffff) | (mtu << 5) | w);
6309 incr[mtu][w] = (u16)t4_read_reg(adap,
6310 A_TP_CCTRL_TABLE) & 0x1fff;
6315 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6316 * @adap: the adapter
6317 * @addr: the indirect TP register address
6318 * @mask: specifies the field within the register to modify
6319 * @val: new value for the field
6321 * Sets a field of an indirect TP register to the given value.
6323 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6324 unsigned int mask, unsigned int val)
6326 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6327 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6328 t4_write_reg(adap, A_TP_PIO_DATA, val);
6332 * init_cong_ctrl - initialize congestion control parameters
6333 * @a: the alpha values for congestion control
6334 * @b: the beta values for congestion control
6336 * Initialize the congestion control parameters.
6338 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6340 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6365 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6368 b[13] = b[14] = b[15] = b[16] = 3;
6369 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6370 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6375 /* The minimum additive increment value for the congestion control table */
6376 #define CC_MIN_INCR 2U
6379 * t4_load_mtus - write the MTU and congestion control HW tables
6380 * @adap: the adapter
6381 * @mtus: the values for the MTU table
6382 * @alpha: the values for the congestion control alpha parameter
6383 * @beta: the values for the congestion control beta parameter
6385 * Write the HW MTU table with the supplied MTUs and the high-speed
6386 * congestion control table with the supplied alpha, beta, and MTUs.
6387 * We write the two tables together because the additive increments
6388 * depend on the MTUs.
6390 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6391 const unsigned short *alpha, const unsigned short *beta)
6393 static const unsigned int avg_pkts[NCCTRL_WIN] = {
6394 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6395 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6396 28672, 40960, 57344, 81920, 114688, 163840, 229376
6401 for (i = 0; i < NMTUS; ++i) {
6402 unsigned int mtu = mtus[i];
6403 unsigned int log2 = fls(mtu);
6405 if (!(mtu & ((1 << log2) >> 2))) /* round */
6407 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6408 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6410 for (w = 0; w < NCCTRL_WIN; ++w) {
6413 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6416 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6417 (w << 16) | (beta[w] << 13) | inc);
6423 * t4_set_pace_tbl - set the pace table
6424 * @adap: the adapter
6425 * @pace_vals: the pace values in microseconds
6426 * @start: index of the first entry in the HW pace table to set
6427 * @n: how many entries to set
6429 * Sets (a subset of the) HW pace table.
6431 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6432 unsigned int start, unsigned int n)
6434 unsigned int vals[NTX_SCHED], i;
6435 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6440 /* convert values from us to dack ticks, rounding to closest value */
6441 for (i = 0; i < n; i++, pace_vals++) {
6442 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6443 if (vals[i] > 0x7ff)
6445 if (*pace_vals && vals[i] == 0)
6448 for (i = 0; i < n; i++, start++)
6449 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6454 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6455 * @adap: the adapter
6456 * @kbps: target rate in Kbps
6457 * @sched: the scheduler index
6459 * Configure a Tx HW scheduler for the target rate.
6461 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6463 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6464 unsigned int clk = adap->params.vpd.cclk * 1000;
6465 unsigned int selected_cpt = 0, selected_bpt = 0;
6468 kbps *= 125; /* -> bytes */
6469 for (cpt = 1; cpt <= 255; cpt++) {
6471 bpt = (kbps + tps / 2) / tps;
6472 if (bpt > 0 && bpt <= 255) {
6474 delta = v >= kbps ? v - kbps : kbps - v;
6475 if (delta < mindelta) {
6480 } else if (selected_cpt)
6486 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6487 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6488 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6490 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6492 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6493 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6498 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6499 * @adap: the adapter
6500 * @sched: the scheduler index
6501 * @ipg: the interpacket delay in tenths of nanoseconds
6503 * Set the interpacket delay for a HW packet rate scheduler.
6505 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6507 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6509 /* convert ipg to nearest number of core clocks */
6510 ipg *= core_ticks_per_usec(adap);
6511 ipg = (ipg + 5000) / 10000;
6512 if (ipg > M_TXTIMERSEPQ0)
6515 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6516 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6518 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6520 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6521 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6522 t4_read_reg(adap, A_TP_TM_PIO_DATA);
6527 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6528 * clocks. The formula is
6530 * bytes/s = bytes256 * 256 * ClkFreq / 4096
6532 * which is equivalent to
6534 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6536 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6538 u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6540 return v * 62 + v / 2;
6544 * t4_get_chan_txrate - get the current per channel Tx rates
6545 * @adap: the adapter
6546 * @nic_rate: rates for NIC traffic
6547 * @ofld_rate: rates for offloaded traffic
6549 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
6552 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6556 v = t4_read_reg(adap, A_TP_TX_TRATE);
6557 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6558 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6559 if (adap->chip_params->nchan > 2) {
6560 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6561 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6564 v = t4_read_reg(adap, A_TP_TX_ORATE);
6565 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6566 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6567 if (adap->chip_params->nchan > 2) {
6568 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6569 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6574 * t4_set_trace_filter - configure one of the tracing filters
6575 * @adap: the adapter
6576 * @tp: the desired trace filter parameters
6577 * @idx: which filter to configure
6578 * @enable: whether to enable or disable the filter
6580 * Configures one of the tracing filters available in HW. If @tp is %NULL
6581 * it indicates that the filter is already written in the register and it
6582 * just needs to be enabled or disabled.
6584 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6585 int idx, int enable)
6587 int i, ofst = idx * 4;
6588 u32 data_reg, mask_reg, cfg;
6589 u32 multitrc = F_TRCMULTIFILTER;
6590 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6592 if (idx < 0 || idx >= NTRACE)
6595 if (tp == NULL || !enable) {
6596 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6602 * TODO - After T4 data book is updated, specify the exact
6605 * See T4 data book - MPS section for a complete description
6606 * of the below if..else handling of A_MPS_TRC_CFG register
6609 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6610 if (cfg & F_TRCMULTIFILTER) {
6612 * If multiple tracers are enabled, then maximum
6613 * capture size is 2.5KB (FIFO size of a single channel)
6614 * minus 2 flits for CPL_TRACE_PKT header.
6616 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6620 * If multiple tracers are disabled, to avoid deadlocks
6621 * maximum packet capture size of 9600 bytes is recommended.
6622 * Also in this mode, only trace0 can be enabled and running.
6625 if (tp->snap_len > 9600 || idx)
6629 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6630 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6631 tp->min_len > M_TFMINPKTSIZE)
6634 /* stop the tracer we'll be changing */
6635 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6637 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6638 data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6639 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6641 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6642 t4_write_reg(adap, data_reg, tp->data[i]);
6643 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6645 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6646 V_TFCAPTUREMAX(tp->snap_len) |
6647 V_TFMINPKTSIZE(tp->min_len));
6648 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6649 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6651 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6652 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6658 * t4_get_trace_filter - query one of the tracing filters
6659 * @adap: the adapter
6660 * @tp: the current trace filter parameters
6661 * @idx: which trace filter to query
6662 * @enabled: non-zero if the filter is enabled
6664 * Returns the current settings of one of the HW tracing filters.
6666 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6670 int i, ofst = idx * 4;
6671 u32 data_reg, mask_reg;
6673 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6674 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6677 *enabled = !!(ctla & F_TFEN);
6678 tp->port = G_TFPORT(ctla);
6679 tp->invert = !!(ctla & F_TFINVERTMATCH);
6681 *enabled = !!(ctla & F_T5_TFEN);
6682 tp->port = G_T5_TFPORT(ctla);
6683 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6685 tp->snap_len = G_TFCAPTUREMAX(ctlb);
6686 tp->min_len = G_TFMINPKTSIZE(ctlb);
6687 tp->skip_ofst = G_TFOFFSET(ctla);
6688 tp->skip_len = G_TFLENGTH(ctla);
6690 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6691 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6692 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6694 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6695 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6696 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6701 * t4_pmtx_get_stats - returns the HW stats from PMTX
6702 * @adap: the adapter
6703 * @cnt: where to store the count statistics
6704 * @cycles: where to store the cycle statistics
6706 * Returns performance statistics from PMTX.
6708 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6713 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6714 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6715 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6717 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6719 t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6720 A_PM_TX_DBG_DATA, data, 2,
6721 A_PM_TX_DBG_STAT_MSB);
6722 cycles[i] = (((u64)data[0] << 32) | data[1]);
6728 * t4_pmrx_get_stats - returns the HW stats from PMRX
6729 * @adap: the adapter
6730 * @cnt: where to store the count statistics
6731 * @cycles: where to store the cycle statistics
6733 * Returns performance statistics from PMRX.
6735 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6740 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6741 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6742 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6744 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6746 t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6747 A_PM_RX_DBG_DATA, data, 2,
6748 A_PM_RX_DBG_STAT_MSB);
6749 cycles[i] = (((u64)data[0] << 32) | data[1]);
6755 * t4_get_mps_bg_map - return the buffer groups associated with a port
6756 * @adap: the adapter
6757 * @idx: the port index
6759 * Returns a bitmap indicating which MPS buffer groups are associated
6760 * with the given port. Bit i is set if buffer group i is used by the
6763 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6767 if (adap->params.mps_bg_map)
6768 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6770 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6772 return idx == 0 ? 0xf : 0;
6773 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6774 return idx < 2 ? (3 << (2 * idx)) : 0;
6779 * TP RX e-channels associated with the port.
6781 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6783 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6786 return idx == 0 ? 0xf : 0;
6787 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6788 return idx < 2 ? (3 << (2 * idx)) : 0;
6793 * t4_get_port_type_description - return Port Type string description
6794 * @port_type: firmware Port Type enumeration
6796 const char *t4_get_port_type_description(enum fw_port_type port_type)
6798 static const char *const port_type_description[] = {
6823 if (port_type < ARRAY_SIZE(port_type_description))
6824 return port_type_description[port_type];
6829 * t4_get_port_stats_offset - collect port stats relative to a previous
6831 * @adap: The adapter
6833 * @stats: Current stats to fill
6834 * @offset: Previous stats snapshot
6836 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6837 struct port_stats *stats,
6838 struct port_stats *offset)
6843 t4_get_port_stats(adap, idx, stats);
6844 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6845 i < (sizeof(struct port_stats)/sizeof(u64)) ;
6851 * t4_get_port_stats - collect port statistics
6852 * @adap: the adapter
6853 * @idx: the port index
6854 * @p: the stats structure to fill
6856 * Collect statistics related to the given port from HW.
6858 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6860 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6861 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6863 #define GET_STAT(name) \
6864 t4_read_reg64(adap, \
6865 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
6866 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
6867 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6869 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6870 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6871 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6872 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6873 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6874 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6875 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6876 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6877 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6878 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6879 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6880 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6881 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6882 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6883 p->tx_drop = GET_STAT(TX_PORT_DROP);
6884 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6885 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6886 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6887 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6888 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6889 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6890 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6891 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6893 if (chip_id(adap) >= CHELSIO_T5) {
6894 if (stat_ctl & F_COUNTPAUSESTATTX) {
6895 p->tx_frames -= p->tx_pause;
6896 p->tx_octets -= p->tx_pause * 64;
6898 if (stat_ctl & F_COUNTPAUSEMCTX)
6899 p->tx_mcast_frames -= p->tx_pause;
6902 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6903 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6904 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6905 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6906 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6907 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6908 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6909 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6910 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6911 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6912 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6913 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6914 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6915 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6916 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6917 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6918 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6919 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6920 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6921 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6922 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6923 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6924 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6925 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6926 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6927 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6928 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6930 if (chip_id(adap) >= CHELSIO_T5) {
6931 if (stat_ctl & F_COUNTPAUSESTATRX) {
6932 p->rx_frames -= p->rx_pause;
6933 p->rx_octets -= p->rx_pause * 64;
6935 if (stat_ctl & F_COUNTPAUSEMCRX)
6936 p->rx_mcast_frames -= p->rx_pause;
6939 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6940 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6941 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6942 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6943 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6944 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6945 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6946 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6953 * t4_get_lb_stats - collect loopback port statistics
6954 * @adap: the adapter
6955 * @idx: the loopback port index
6956 * @p: the stats structure to fill
6958 * Return HW statistics for the given loopback port.
6960 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6962 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6964 #define GET_STAT(name) \
6965 t4_read_reg64(adap, \
6967 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
6968 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
6969 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6971 p->octets = GET_STAT(BYTES);
6972 p->frames = GET_STAT(FRAMES);
6973 p->bcast_frames = GET_STAT(BCAST);
6974 p->mcast_frames = GET_STAT(MCAST);
6975 p->ucast_frames = GET_STAT(UCAST);
6976 p->error_frames = GET_STAT(ERROR);
6978 p->frames_64 = GET_STAT(64B);
6979 p->frames_65_127 = GET_STAT(65B_127B);
6980 p->frames_128_255 = GET_STAT(128B_255B);
6981 p->frames_256_511 = GET_STAT(256B_511B);
6982 p->frames_512_1023 = GET_STAT(512B_1023B);
6983 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6984 p->frames_1519_max = GET_STAT(1519B_MAX);
6985 p->drop = GET_STAT(DROP_FRAMES);
6987 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6988 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6989 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6990 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6991 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6992 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6993 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6994 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
7001 * t4_wol_magic_enable - enable/disable magic packet WoL
7002 * @adap: the adapter
7003 * @port: the physical port index
7004 * @addr: MAC address expected in magic packets, %NULL to disable
7006 * Enables/disables magic packet wake-on-LAN for the selected port.
7008 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
7011 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
7014 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
7015 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
7016 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7018 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
7019 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
7020 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7024 t4_write_reg(adap, mag_id_reg_l,
7025 (addr[2] << 24) | (addr[3] << 16) |
7026 (addr[4] << 8) | addr[5]);
7027 t4_write_reg(adap, mag_id_reg_h,
7028 (addr[0] << 8) | addr[1]);
7030 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
7031 V_MAGICEN(addr != NULL));
7035 * t4_wol_pat_enable - enable/disable pattern-based WoL
7036 * @adap: the adapter
7037 * @port: the physical port index
7038 * @map: bitmap of which HW pattern filters to set
7039 * @mask0: byte mask for bytes 0-63 of a packet
7040 * @mask1: byte mask for bytes 64-127 of a packet
7041 * @crc: Ethernet CRC for selected bytes
7042 * @enable: enable/disable switch
7044 * Sets the pattern filters indicated in @map to mask out the bytes
7045 * specified in @mask0/@mask1 in received packets and compare the CRC of
7046 * the resulting packet against @crc. If @enable is %true pattern-based
7047 * WoL is enabled, otherwise disabled.
7049 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
7050 u64 mask0, u64 mask1, unsigned int crc, bool enable)
7056 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7058 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7061 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7067 #define EPIO_REG(name) \
7068 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7069 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7071 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7072 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7073 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7075 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7079 /* write byte masks */
7080 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7081 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7082 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7083 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7087 t4_write_reg(adap, EPIO_REG(DATA0), crc);
7088 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7089 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7090 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7095 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7099 /* t4_mk_filtdelwr - create a delete filter WR
7100 * @ftid: the filter ID
7101 * @wr: the filter work request to populate
7102 * @qid: ingress queue to receive the delete notification
7104 * Creates a filter work request to delete the supplied filter. If @qid is
7105 * negative the delete notification is suppressed.
7107 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7109 memset(wr, 0, sizeof(*wr));
7110 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7111 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7112 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7113 V_FW_FILTER_WR_NOREPLY(qid < 0));
7114 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7116 wr->rx_chan_rx_rpl_iq =
7117 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7120 #define INIT_CMD(var, cmd, rd_wr) do { \
7121 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7122 F_FW_CMD_REQUEST | \
7123 F_FW_CMD_##rd_wr); \
7124 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7127 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7131 struct fw_ldst_cmd c;
7133 memset(&c, 0, sizeof(c));
7134 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7135 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7139 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7140 c.u.addrval.addr = cpu_to_be32(addr);
7141 c.u.addrval.val = cpu_to_be32(val);
7143 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7147 * t4_mdio_rd - read a PHY register through MDIO
7148 * @adap: the adapter
7149 * @mbox: mailbox to use for the FW command
7150 * @phy_addr: the PHY address
7151 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7152 * @reg: the register to read
7153 * @valp: where to store the value
7155 * Issues a FW command through the given mailbox to read a PHY register.
7157 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7158 unsigned int mmd, unsigned int reg, unsigned int *valp)
7162 struct fw_ldst_cmd c;
7164 memset(&c, 0, sizeof(c));
7165 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7166 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7167 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7169 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7170 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7171 V_FW_LDST_CMD_MMD(mmd));
7172 c.u.mdio.raddr = cpu_to_be16(reg);
7174 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7176 *valp = be16_to_cpu(c.u.mdio.rval);
7181 * t4_mdio_wr - write a PHY register through MDIO
7182 * @adap: the adapter
7183 * @mbox: mailbox to use for the FW command
7184 * @phy_addr: the PHY address
7185 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7186 * @reg: the register to write
7187 * @valp: value to write
7189 * Issues a FW command through the given mailbox to write a PHY register.
7191 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7192 unsigned int mmd, unsigned int reg, unsigned int val)
7195 struct fw_ldst_cmd c;
7197 memset(&c, 0, sizeof(c));
7198 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7199 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7200 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7202 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7203 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7204 V_FW_LDST_CMD_MMD(mmd));
7205 c.u.mdio.raddr = cpu_to_be16(reg);
7206 c.u.mdio.rval = cpu_to_be16(val);
7208 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7213 * t4_sge_decode_idma_state - decode the idma state
7214 * @adap: the adapter
7215 * @state: the state idma is stuck in
7217 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7219 static const char * const t4_decode[] = {
7221 "IDMA_PUSH_MORE_CPL_FIFO",
7222 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7224 "IDMA_PHYSADDR_SEND_PCIEHDR",
7225 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7226 "IDMA_PHYSADDR_SEND_PAYLOAD",
7227 "IDMA_SEND_FIFO_TO_IMSG",
7228 "IDMA_FL_REQ_DATA_FL_PREP",
7229 "IDMA_FL_REQ_DATA_FL",
7231 "IDMA_FL_H_REQ_HEADER_FL",
7232 "IDMA_FL_H_SEND_PCIEHDR",
7233 "IDMA_FL_H_PUSH_CPL_FIFO",
7234 "IDMA_FL_H_SEND_CPL",
7235 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7236 "IDMA_FL_H_SEND_IP_HDR",
7237 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7238 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7239 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7240 "IDMA_FL_D_SEND_PCIEHDR",
7241 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7242 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7243 "IDMA_FL_SEND_PCIEHDR",
7244 "IDMA_FL_PUSH_CPL_FIFO",
7246 "IDMA_FL_SEND_PAYLOAD_FIRST",
7247 "IDMA_FL_SEND_PAYLOAD",
7248 "IDMA_FL_REQ_NEXT_DATA_FL",
7249 "IDMA_FL_SEND_NEXT_PCIEHDR",
7250 "IDMA_FL_SEND_PADDING",
7251 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7252 "IDMA_FL_SEND_FIFO_TO_IMSG",
7253 "IDMA_FL_REQ_DATAFL_DONE",
7254 "IDMA_FL_REQ_HEADERFL_DONE",
7256 static const char * const t5_decode[] = {
7259 "IDMA_PUSH_MORE_CPL_FIFO",
7260 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7261 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7262 "IDMA_PHYSADDR_SEND_PCIEHDR",
7263 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7264 "IDMA_PHYSADDR_SEND_PAYLOAD",
7265 "IDMA_SEND_FIFO_TO_IMSG",
7266 "IDMA_FL_REQ_DATA_FL",
7268 "IDMA_FL_DROP_SEND_INC",
7269 "IDMA_FL_H_REQ_HEADER_FL",
7270 "IDMA_FL_H_SEND_PCIEHDR",
7271 "IDMA_FL_H_PUSH_CPL_FIFO",
7272 "IDMA_FL_H_SEND_CPL",
7273 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7274 "IDMA_FL_H_SEND_IP_HDR",
7275 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7276 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7277 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7278 "IDMA_FL_D_SEND_PCIEHDR",
7279 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7280 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7281 "IDMA_FL_SEND_PCIEHDR",
7282 "IDMA_FL_PUSH_CPL_FIFO",
7284 "IDMA_FL_SEND_PAYLOAD_FIRST",
7285 "IDMA_FL_SEND_PAYLOAD",
7286 "IDMA_FL_REQ_NEXT_DATA_FL",
7287 "IDMA_FL_SEND_NEXT_PCIEHDR",
7288 "IDMA_FL_SEND_PADDING",
7289 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7291 static const char * const t6_decode[] = {
7293 "IDMA_PUSH_MORE_CPL_FIFO",
7294 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7295 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7296 "IDMA_PHYSADDR_SEND_PCIEHDR",
7297 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7298 "IDMA_PHYSADDR_SEND_PAYLOAD",
7299 "IDMA_FL_REQ_DATA_FL",
7301 "IDMA_FL_DROP_SEND_INC",
7302 "IDMA_FL_H_REQ_HEADER_FL",
7303 "IDMA_FL_H_SEND_PCIEHDR",
7304 "IDMA_FL_H_PUSH_CPL_FIFO",
7305 "IDMA_FL_H_SEND_CPL",
7306 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7307 "IDMA_FL_H_SEND_IP_HDR",
7308 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7309 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7310 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7311 "IDMA_FL_D_SEND_PCIEHDR",
7312 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7313 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7314 "IDMA_FL_SEND_PCIEHDR",
7315 "IDMA_FL_PUSH_CPL_FIFO",
7317 "IDMA_FL_SEND_PAYLOAD_FIRST",
7318 "IDMA_FL_SEND_PAYLOAD",
7319 "IDMA_FL_REQ_NEXT_DATA_FL",
7320 "IDMA_FL_SEND_NEXT_PCIEHDR",
7321 "IDMA_FL_SEND_PADDING",
7322 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7324 static const u32 sge_regs[] = {
7325 A_SGE_DEBUG_DATA_LOW_INDEX_2,
7326 A_SGE_DEBUG_DATA_LOW_INDEX_3,
7327 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7329 const char * const *sge_idma_decode;
7330 int sge_idma_decode_nstates;
7332 unsigned int chip_version = chip_id(adapter);
7334 /* Select the right set of decode strings to dump depending on the
7335 * adapter chip type.
7337 switch (chip_version) {
7339 sge_idma_decode = (const char * const *)t4_decode;
7340 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7344 sge_idma_decode = (const char * const *)t5_decode;
7345 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7349 sge_idma_decode = (const char * const *)t6_decode;
7350 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7354 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
7358 if (state < sge_idma_decode_nstates)
7359 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7361 CH_WARN(adapter, "idma state %d unknown\n", state);
7363 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7364 CH_WARN(adapter, "SGE register %#x value %#x\n",
7365 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7369 * t4_sge_ctxt_flush - flush the SGE context cache
7370 * @adap: the adapter
7371 * @mbox: mailbox to use for the FW command
7373 * Issues a FW command through the given mailbox to flush the
7374 * SGE context cache.
7376 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
7380 struct fw_ldst_cmd c;
7382 memset(&c, 0, sizeof(c));
7383 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
7384 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7385 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7387 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7388 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7390 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7395 * t4_fw_hello - establish communication with FW
7396 * @adap: the adapter
7397 * @mbox: mailbox to use for the FW command
7398 * @evt_mbox: mailbox to receive async FW events
7399 * @master: specifies the caller's willingness to be the device master
7400 * @state: returns the current device state (if non-NULL)
7402 * Issues a command to establish communication with FW. Returns either
7403 * an error (negative integer) or the mailbox of the Master PF.
7405 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7406 enum dev_master master, enum dev_state *state)
7409 struct fw_hello_cmd c;
7411 unsigned int master_mbox;
7412 int retries = FW_CMD_HELLO_RETRIES;
7415 memset(&c, 0, sizeof(c));
7416 INIT_CMD(c, HELLO, WRITE);
7417 c.err_to_clearinit = cpu_to_be32(
7418 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7419 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7420 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7421 mbox : M_FW_HELLO_CMD_MBMASTER) |
7422 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7423 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7424 F_FW_HELLO_CMD_CLEARINIT);
7427 * Issue the HELLO command to the firmware. If it's not successful
7428 * but indicates that we got a "busy" or "timeout" condition, retry
7429 * the HELLO until we exhaust our retry limit. If we do exceed our
7430 * retry limit, check to see if the firmware left us any error
7431 * information and report that if so ...
7433 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7434 if (ret != FW_SUCCESS) {
7435 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7437 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
7438 t4_report_fw_error(adap);
7442 v = be32_to_cpu(c.err_to_clearinit);
7443 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7445 if (v & F_FW_HELLO_CMD_ERR)
7446 *state = DEV_STATE_ERR;
7447 else if (v & F_FW_HELLO_CMD_INIT)
7448 *state = DEV_STATE_INIT;
7450 *state = DEV_STATE_UNINIT;
7454 * If we're not the Master PF then we need to wait around for the
7455 * Master PF Driver to finish setting up the adapter.
7457 * Note that we also do this wait if we're a non-Master-capable PF and
7458 * there is no current Master PF; a Master PF may show up momentarily
7459 * and we wouldn't want to fail pointlessly. (This can happen when an
7460 * OS loads lots of different drivers rapidly at the same time). In
7461 * this case, the Master PF returned by the firmware will be
7462 * M_PCIE_FW_MASTER so the test below will work ...
7464 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7465 master_mbox != mbox) {
7466 int waiting = FW_CMD_HELLO_TIMEOUT;
7469 * Wait for the firmware to either indicate an error or
7470 * initialized state. If we see either of these we bail out
7471 * and report the issue to the caller. If we exhaust the
7472 * "hello timeout" and we haven't exhausted our retries, try
7473 * again. Otherwise bail with a timeout error.
7482 * If neither Error nor Initialialized are indicated
7483 * by the firmware keep waiting till we exhaust our
7484 * timeout ... and then retry if we haven't exhausted
7487 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7488 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7499 * We either have an Error or Initialized condition
7500 * report errors preferentially.
7503 if (pcie_fw & F_PCIE_FW_ERR)
7504 *state = DEV_STATE_ERR;
7505 else if (pcie_fw & F_PCIE_FW_INIT)
7506 *state = DEV_STATE_INIT;
7510 * If we arrived before a Master PF was selected and
7511 * there's not a valid Master PF, grab its identity
7514 if (master_mbox == M_PCIE_FW_MASTER &&
7515 (pcie_fw & F_PCIE_FW_MASTER_VLD))
7516 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7525 * t4_fw_bye - end communication with FW
7526 * @adap: the adapter
7527 * @mbox: mailbox to use for the FW command
7529 * Issues a command to terminate communication with FW.
7531 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7533 struct fw_bye_cmd c;
7535 memset(&c, 0, sizeof(c));
7536 INIT_CMD(c, BYE, WRITE);
7537 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7541 * t4_fw_reset - issue a reset to FW
7542 * @adap: the adapter
7543 * @mbox: mailbox to use for the FW command
7544 * @reset: specifies the type of reset to perform
7546 * Issues a reset command of the specified type to FW.
7548 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7550 struct fw_reset_cmd c;
7552 memset(&c, 0, sizeof(c));
7553 INIT_CMD(c, RESET, WRITE);
7554 c.val = cpu_to_be32(reset);
7555 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7559 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7560 * @adap: the adapter
7561 * @mbox: mailbox to use for the FW RESET command (if desired)
7562 * @force: force uP into RESET even if FW RESET command fails
7564 * Issues a RESET command to firmware (if desired) with a HALT indication
7565 * and then puts the microprocessor into RESET state. The RESET command
7566 * will only be issued if a legitimate mailbox is provided (mbox <=
7567 * M_PCIE_FW_MASTER).
7569 * This is generally used in order for the host to safely manipulate the
7570 * adapter without fear of conflicting with whatever the firmware might
7571 * be doing. The only way out of this state is to RESTART the firmware
7574 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7579 * If a legitimate mailbox is provided, issue a RESET command
7580 * with a HALT indication.
7582 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7583 struct fw_reset_cmd c;
7585 memset(&c, 0, sizeof(c));
7586 INIT_CMD(c, RESET, WRITE);
7587 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7588 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7589 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7593 * Normally we won't complete the operation if the firmware RESET
7594 * command fails but if our caller insists we'll go ahead and put the
7595 * uP into RESET. This can be useful if the firmware is hung or even
7596 * missing ... We'll have to take the risk of putting the uP into
7597 * RESET without the cooperation of firmware in that case.
7599 * We also force the firmware's HALT flag to be on in case we bypassed
7600 * the firmware RESET command above or we're dealing with old firmware
7601 * which doesn't have the HALT capability. This will serve as a flag
7602 * for the incoming firmware to know that it's coming out of a HALT
7603 * rather than a RESET ... if it's new enough to understand that ...
7605 if (ret == 0 || force) {
7606 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7607 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7612 * And we always return the result of the firmware RESET command
7613 * even when we force the uP into RESET ...
7619 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7620 * @adap: the adapter
7622 * Restart firmware previously halted by t4_fw_halt(). On successful
7623 * return the previous PF Master remains as the new PF Master and there
7624 * is no need to issue a new HELLO command, etc.
7626 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7630 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7631 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7632 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7642 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7643 * @adap: the adapter
7644 * @mbox: mailbox to use for the FW RESET command (if desired)
7645 * @fw_data: the firmware image to write
7647 * @force: force upgrade even if firmware doesn't cooperate
7649 * Perform all of the steps necessary for upgrading an adapter's
7650 * firmware image. Normally this requires the cooperation of the
7651 * existing firmware in order to halt all existing activities
7652 * but if an invalid mailbox token is passed in we skip that step
7653 * (though we'll still put the adapter microprocessor into RESET in
7656 * On successful return the new firmware will have been loaded and
7657 * the adapter will have been fully RESET losing all previous setup
7658 * state. On unsuccessful return the adapter may be completely hosed ...
7659 * positive errno indicates that the adapter is ~probably~ intact, a
7660 * negative errno indicates that things are looking bad ...
7662 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7663 const u8 *fw_data, unsigned int size, int force)
7665 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7666 unsigned int bootstrap =
7667 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7670 if (!t4_fw_matches_chip(adap, fw_hdr))
7674 ret = t4_fw_halt(adap, mbox, force);
7675 if (ret < 0 && !force)
7679 ret = t4_load_fw(adap, fw_data, size);
7680 if (ret < 0 || bootstrap)
7683 return t4_fw_restart(adap, mbox);
7687 * t4_fw_initialize - ask FW to initialize the device
7688 * @adap: the adapter
7689 * @mbox: mailbox to use for the FW command
7691 * Issues a command to FW to partially initialize the device. This
7692 * performs initialization that generally doesn't depend on user input.
7694 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7696 struct fw_initialize_cmd c;
7698 memset(&c, 0, sizeof(c));
7699 INIT_CMD(c, INITIALIZE, WRITE);
7700 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7704 * t4_query_params_rw - query FW or device parameters
7705 * @adap: the adapter
7706 * @mbox: mailbox to use for the FW command
7709 * @nparams: the number of parameters
7710 * @params: the parameter names
7711 * @val: the parameter values
7712 * @rw: Write and read flag
7714 * Reads the value of FW or device parameters. Up to 7 parameters can be
7717 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7718 unsigned int vf, unsigned int nparams, const u32 *params,
7722 struct fw_params_cmd c;
7723 __be32 *p = &c.param[0].mnem;
7728 memset(&c, 0, sizeof(c));
7729 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7730 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7731 V_FW_PARAMS_CMD_PFN(pf) |
7732 V_FW_PARAMS_CMD_VFN(vf));
7733 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7735 for (i = 0; i < nparams; i++) {
7736 *p++ = cpu_to_be32(*params++);
7738 *p = cpu_to_be32(*(val + i));
7742 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7744 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7745 *val++ = be32_to_cpu(*p);
7749 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7750 unsigned int vf, unsigned int nparams, const u32 *params,
7753 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7757 * t4_set_params_timeout - sets FW or device parameters
7758 * @adap: the adapter
7759 * @mbox: mailbox to use for the FW command
7762 * @nparams: the number of parameters
7763 * @params: the parameter names
7764 * @val: the parameter values
7765 * @timeout: the timeout time
7767 * Sets the value of FW or device parameters. Up to 7 parameters can be
7768 * specified at once.
7770 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7771 unsigned int pf, unsigned int vf,
7772 unsigned int nparams, const u32 *params,
7773 const u32 *val, int timeout)
7775 struct fw_params_cmd c;
7776 __be32 *p = &c.param[0].mnem;
7781 memset(&c, 0, sizeof(c));
7782 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7783 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7784 V_FW_PARAMS_CMD_PFN(pf) |
7785 V_FW_PARAMS_CMD_VFN(vf));
7786 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7789 *p++ = cpu_to_be32(*params++);
7790 *p++ = cpu_to_be32(*val++);
7793 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7797 * t4_set_params - sets FW or device parameters
7798 * @adap: the adapter
7799 * @mbox: mailbox to use for the FW command
7802 * @nparams: the number of parameters
7803 * @params: the parameter names
7804 * @val: the parameter values
7806 * Sets the value of FW or device parameters. Up to 7 parameters can be
7807 * specified at once.
7809 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7810 unsigned int vf, unsigned int nparams, const u32 *params,
7813 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7814 FW_CMD_MAX_TIMEOUT);
7818 * t4_cfg_pfvf - configure PF/VF resource limits
7819 * @adap: the adapter
7820 * @mbox: mailbox to use for the FW command
7821 * @pf: the PF being configured
7822 * @vf: the VF being configured
7823 * @txq: the max number of egress queues
7824 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7825 * @rxqi: the max number of interrupt-capable ingress queues
7826 * @rxq: the max number of interruptless ingress queues
7827 * @tc: the PCI traffic class
7828 * @vi: the max number of virtual interfaces
7829 * @cmask: the channel access rights mask for the PF/VF
7830 * @pmask: the port access rights mask for the PF/VF
7831 * @nexact: the maximum number of exact MPS filters
7832 * @rcaps: read capabilities
7833 * @wxcaps: write/execute capabilities
7835 * Configures resource limits and capabilities for a physical or virtual
7838 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7839 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7840 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7841 unsigned int vi, unsigned int cmask, unsigned int pmask,
7842 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7844 struct fw_pfvf_cmd c;
7846 memset(&c, 0, sizeof(c));
7847 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7848 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7849 V_FW_PFVF_CMD_VFN(vf));
7850 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7851 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7852 V_FW_PFVF_CMD_NIQ(rxq));
7853 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7854 V_FW_PFVF_CMD_PMASK(pmask) |
7855 V_FW_PFVF_CMD_NEQ(txq));
7856 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7857 V_FW_PFVF_CMD_NVI(vi) |
7858 V_FW_PFVF_CMD_NEXACTF(nexact));
7859 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7860 V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7861 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7862 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7866 * t4_alloc_vi_func - allocate a virtual interface
7867 * @adap: the adapter
7868 * @mbox: mailbox to use for the FW command
7869 * @port: physical port associated with the VI
7870 * @pf: the PF owning the VI
7871 * @vf: the VF owning the VI
7872 * @nmac: number of MAC addresses needed (1 to 5)
7873 * @mac: the MAC addresses of the VI
7874 * @rss_size: size of RSS table slice associated with this VI
7875 * @portfunc: which Port Application Function MAC Address is desired
7876 * @idstype: Intrusion Detection Type
7878 * Allocates a virtual interface for the given physical port. If @mac is
7879 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7880 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7881 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7882 * stored consecutively so the space needed is @nmac * 6 bytes.
7883 * Returns a negative error number or the non-negative VI id.
7885 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7886 unsigned int port, unsigned int pf, unsigned int vf,
7887 unsigned int nmac, u8 *mac, u16 *rss_size,
7888 uint8_t *vfvld, uint16_t *vin,
7889 unsigned int portfunc, unsigned int idstype)
7894 memset(&c, 0, sizeof(c));
7895 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7896 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7897 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7898 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7899 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7900 V_FW_VI_CMD_FUNC(portfunc));
7901 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7904 c.norss_rsssize = F_FW_VI_CMD_NORSS;
7906 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7909 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7912 memcpy(mac, c.mac, sizeof(c.mac));
7915 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7917 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7919 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7921 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7925 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7927 *vfvld = adap->params.viid_smt_extn_support ?
7928 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
7929 G_FW_VIID_VIVLD(ret);
7932 *vin = adap->params.viid_smt_extn_support ?
7933 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
7941 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7942 * @adap: the adapter
7943 * @mbox: mailbox to use for the FW command
7944 * @port: physical port associated with the VI
7945 * @pf: the PF owning the VI
7946 * @vf: the VF owning the VI
7947 * @nmac: number of MAC addresses needed (1 to 5)
7948 * @mac: the MAC addresses of the VI
7949 * @rss_size: size of RSS table slice associated with this VI
7951 * backwards compatible and convieniance routine to allocate a Virtual
7952 * Interface with a Ethernet Port Application Function and Intrustion
7953 * Detection System disabled.
7955 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7956 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7957 u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
7959 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7960 vfvld, vin, FW_VI_FUNC_ETH, 0);
7964 * t4_free_vi - free a virtual interface
7965 * @adap: the adapter
7966 * @mbox: mailbox to use for the FW command
7967 * @pf: the PF owning the VI
7968 * @vf: the VF owning the VI
7969 * @viid: virtual interface identifiler
7971 * Free a previously allocated virtual interface.
7973 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7974 unsigned int vf, unsigned int viid)
7978 memset(&c, 0, sizeof(c));
7979 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7982 V_FW_VI_CMD_PFN(pf) |
7983 V_FW_VI_CMD_VFN(vf));
7984 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7985 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7987 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7991 * t4_set_rxmode - set Rx properties of a virtual interface
7992 * @adap: the adapter
7993 * @mbox: mailbox to use for the FW command
7995 * @mtu: the new MTU or -1
7996 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7997 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7998 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7999 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
8000 * @sleep_ok: if true we may sleep while awaiting command completion
8002 * Sets Rx properties of a virtual interface.
8004 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
8005 int mtu, int promisc, int all_multi, int bcast, int vlanex,
8008 struct fw_vi_rxmode_cmd c;
8010 /* convert to FW values */
8012 mtu = M_FW_VI_RXMODE_CMD_MTU;
8014 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
8016 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
8018 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
8020 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
8022 memset(&c, 0, sizeof(c));
8023 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
8024 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8025 V_FW_VI_RXMODE_CMD_VIID(viid));
8026 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
8028 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
8029 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
8030 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
8031 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
8032 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
8033 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8037 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
8038 * @adap: the adapter
8039 * @mbox: mailbox to use for the FW command
8041 * @free: if true any existing filters for this VI id are first removed
8042 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8043 * @addr: the MAC address(es)
8044 * @idx: where to store the index of each allocated filter
8045 * @hash: pointer to hash address filter bitmap
8046 * @sleep_ok: call is allowed to sleep
8048 * Allocates an exact-match filter for each of the supplied addresses and
8049 * sets it to the corresponding address. If @idx is not %NULL it should
8050 * have at least @naddr entries, each of which will be set to the index of
8051 * the filter allocated for the corresponding MAC address. If a filter
8052 * could not be allocated for an address its index is set to 0xffff.
8053 * If @hash is not %NULL addresses that fail to allocate an exact filter
8054 * are hashed and update the hash filter bitmap pointed at by @hash.
8056 * Returns a negative error number or the number of filters allocated.
8058 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8059 unsigned int viid, bool free, unsigned int naddr,
8060 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8062 int offset, ret = 0;
8063 struct fw_vi_mac_cmd c;
8064 unsigned int nfilters = 0;
8065 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8066 unsigned int rem = naddr;
8068 if (naddr > max_naddr)
8071 for (offset = 0; offset < naddr ; /**/) {
8072 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8074 : ARRAY_SIZE(c.u.exact));
8075 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8076 u.exact[fw_naddr]), 16);
8077 struct fw_vi_mac_exact *p;
8080 memset(&c, 0, sizeof(c));
8081 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8084 V_FW_CMD_EXEC(free) |
8085 V_FW_VI_MAC_CMD_VIID(viid));
8086 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8087 V_FW_CMD_LEN16(len16));
8089 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8091 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8092 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8093 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8097 * It's okay if we run out of space in our MAC address arena.
8098 * Some of the addresses we submit may get stored so we need
8099 * to run through the reply to see what the results were ...
8101 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8102 if (ret && ret != -FW_ENOMEM)
8105 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8106 u16 index = G_FW_VI_MAC_CMD_IDX(
8107 be16_to_cpu(p->valid_to_idx));
8110 idx[offset+i] = (index >= max_naddr
8113 if (index < max_naddr)
8116 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8124 if (ret == 0 || ret == -FW_ENOMEM)
8130 * t4_change_mac - modifies the exact-match filter for a MAC address
8131 * @adap: the adapter
8132 * @mbox: mailbox to use for the FW command
8134 * @idx: index of existing filter for old value of MAC address, or -1
8135 * @addr: the new MAC address value
8136 * @persist: whether a new MAC allocation should be persistent
8137 * @smt_idx: add MAC to SMT and return its index, or NULL
8139 * Modifies an exact-match filter and sets it to the new MAC address if
8140 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
8141 * latter case the address is added persistently if @persist is %true.
8143 * Note that in general it is not possible to modify the value of a given
8144 * filter so the generic way to modify an address filter is to free the one
8145 * being used by the old address value and allocate a new filter for the
8146 * new address value.
8148 * Returns a negative error number or the index of the filter with the new
8149 * MAC value. Note that this index may differ from @idx.
8151 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8152 int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8155 struct fw_vi_mac_cmd c;
8156 struct fw_vi_mac_exact *p = c.u.exact;
8157 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8159 if (idx < 0) /* new allocation */
8160 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8161 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8163 memset(&c, 0, sizeof(c));
8164 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8165 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8166 V_FW_VI_MAC_CMD_VIID(viid));
8167 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8168 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8169 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8170 V_FW_VI_MAC_CMD_IDX(idx));
8171 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8173 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8175 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8176 if (ret >= max_mac_addr)
8179 if (adap->params.viid_smt_extn_support)
8180 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8182 if (chip_id(adap) <= CHELSIO_T5)
8183 *smt_idx = (viid & M_FW_VIID_VIN) << 1;
8185 *smt_idx = viid & M_FW_VIID_VIN;
8193 * t4_set_addr_hash - program the MAC inexact-match hash filter
8194 * @adap: the adapter
8195 * @mbox: mailbox to use for the FW command
8197 * @ucast: whether the hash filter should also match unicast addresses
8198 * @vec: the value to be written to the hash filter
8199 * @sleep_ok: call is allowed to sleep
8201 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8203 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8204 bool ucast, u64 vec, bool sleep_ok)
8206 struct fw_vi_mac_cmd c;
8209 memset(&c, 0, sizeof(c));
8210 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8211 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8212 V_FW_VI_ENABLE_CMD_VIID(viid));
8213 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8214 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8215 c.freemacs_to_len16 = cpu_to_be32(val);
8216 c.u.hash.hashvec = cpu_to_be64(vec);
8217 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8221 * t4_enable_vi_params - enable/disable a virtual interface
8222 * @adap: the adapter
8223 * @mbox: mailbox to use for the FW command
8225 * @rx_en: 1=enable Rx, 0=disable Rx
8226 * @tx_en: 1=enable Tx, 0=disable Tx
8227 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8229 * Enables/disables a virtual interface. Note that setting DCB Enable
8230 * only makes sense when enabling a Virtual Interface ...
8232 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8233 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8235 struct fw_vi_enable_cmd c;
8237 memset(&c, 0, sizeof(c));
8238 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8239 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8240 V_FW_VI_ENABLE_CMD_VIID(viid));
8241 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8242 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8243 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8245 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8249 * t4_enable_vi - enable/disable a virtual interface
8250 * @adap: the adapter
8251 * @mbox: mailbox to use for the FW command
8253 * @rx_en: 1=enable Rx, 0=disable Rx
8254 * @tx_en: 1=enable Tx, 0=disable Tx
8256 * Enables/disables a virtual interface. Note that setting DCB Enable
8257 * only makes sense when enabling a Virtual Interface ...
8259 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8260 bool rx_en, bool tx_en)
8262 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8266 * t4_identify_port - identify a VI's port by blinking its LED
8267 * @adap: the adapter
8268 * @mbox: mailbox to use for the FW command
8270 * @nblinks: how many times to blink LED at 2.5 Hz
8272 * Identifies a VI's port by blinking its LED.
8274 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8275 unsigned int nblinks)
8277 struct fw_vi_enable_cmd c;
8279 memset(&c, 0, sizeof(c));
8280 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8281 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8282 V_FW_VI_ENABLE_CMD_VIID(viid));
8283 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8284 c.blinkdur = cpu_to_be16(nblinks);
8285 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8289 * t4_iq_stop - stop an ingress queue and its FLs
8290 * @adap: the adapter
8291 * @mbox: mailbox to use for the FW command
8292 * @pf: the PF owning the queues
8293 * @vf: the VF owning the queues
8294 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8295 * @iqid: ingress queue id
8296 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8297 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8299 * Stops an ingress queue and its associated FLs, if any. This causes
8300 * any current or future data/messages destined for these queues to be
8303 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8304 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8305 unsigned int fl0id, unsigned int fl1id)
8309 memset(&c, 0, sizeof(c));
8310 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8311 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8312 V_FW_IQ_CMD_VFN(vf));
8313 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8314 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8315 c.iqid = cpu_to_be16(iqid);
8316 c.fl0id = cpu_to_be16(fl0id);
8317 c.fl1id = cpu_to_be16(fl1id);
8318 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8322 * t4_iq_free - free an ingress queue and its FLs
8323 * @adap: the adapter
8324 * @mbox: mailbox to use for the FW command
8325 * @pf: the PF owning the queues
8326 * @vf: the VF owning the queues
8327 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8328 * @iqid: ingress queue id
8329 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8330 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8332 * Frees an ingress queue and its associated FLs, if any.
8334 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8335 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8336 unsigned int fl0id, unsigned int fl1id)
8340 memset(&c, 0, sizeof(c));
8341 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8342 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8343 V_FW_IQ_CMD_VFN(vf));
8344 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8345 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8346 c.iqid = cpu_to_be16(iqid);
8347 c.fl0id = cpu_to_be16(fl0id);
8348 c.fl1id = cpu_to_be16(fl1id);
8349 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8353 * t4_eth_eq_free - free an Ethernet egress queue
8354 * @adap: the adapter
8355 * @mbox: mailbox to use for the FW command
8356 * @pf: the PF owning the queue
8357 * @vf: the VF owning the queue
8358 * @eqid: egress queue id
8360 * Frees an Ethernet egress queue.
8362 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8363 unsigned int vf, unsigned int eqid)
8365 struct fw_eq_eth_cmd c;
8367 memset(&c, 0, sizeof(c));
8368 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8369 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8370 V_FW_EQ_ETH_CMD_PFN(pf) |
8371 V_FW_EQ_ETH_CMD_VFN(vf));
8372 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8373 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8374 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8378 * t4_ctrl_eq_free - free a control egress queue
8379 * @adap: the adapter
8380 * @mbox: mailbox to use for the FW command
8381 * @pf: the PF owning the queue
8382 * @vf: the VF owning the queue
8383 * @eqid: egress queue id
8385 * Frees a control egress queue.
8387 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8388 unsigned int vf, unsigned int eqid)
8390 struct fw_eq_ctrl_cmd c;
8392 memset(&c, 0, sizeof(c));
8393 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8394 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8395 V_FW_EQ_CTRL_CMD_PFN(pf) |
8396 V_FW_EQ_CTRL_CMD_VFN(vf));
8397 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8398 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8399 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8403 * t4_ofld_eq_free - free an offload egress queue
8404 * @adap: the adapter
8405 * @mbox: mailbox to use for the FW command
8406 * @pf: the PF owning the queue
8407 * @vf: the VF owning the queue
8408 * @eqid: egress queue id
8410 * Frees a control egress queue.
8412 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8413 unsigned int vf, unsigned int eqid)
8415 struct fw_eq_ofld_cmd c;
8417 memset(&c, 0, sizeof(c));
8418 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8419 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8420 V_FW_EQ_OFLD_CMD_PFN(pf) |
8421 V_FW_EQ_OFLD_CMD_VFN(vf));
8422 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8423 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8424 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8428 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8429 * @link_down_rc: Link Down Reason Code
8431 * Returns a string representation of the Link Down Reason Code.
8433 const char *t4_link_down_rc_str(unsigned char link_down_rc)
8435 static const char *reason[] = {
8438 "Auto-negotiation Failure",
8440 "Insufficient Airflow",
8441 "Unable To Determine Reason",
8442 "No RX Signal Detected",
8446 if (link_down_rc >= ARRAY_SIZE(reason))
8447 return "Bad Reason Code";
8449 return reason[link_down_rc];
8453 * Return the highest speed set in the port capabilities, in Mb/s.
8455 unsigned int fwcap_to_speed(uint32_t caps)
8457 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8459 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8463 TEST_SPEED_RETURN(400G, 400000);
8464 TEST_SPEED_RETURN(200G, 200000);
8465 TEST_SPEED_RETURN(100G, 100000);
8466 TEST_SPEED_RETURN(50G, 50000);
8467 TEST_SPEED_RETURN(40G, 40000);
8468 TEST_SPEED_RETURN(25G, 25000);
8469 TEST_SPEED_RETURN(10G, 10000);
8470 TEST_SPEED_RETURN(1G, 1000);
8471 TEST_SPEED_RETURN(100M, 100);
8473 #undef TEST_SPEED_RETURN
8479 * Return the port capabilities bit for the given speed, which is in Mb/s.
8481 uint32_t speed_to_fwcap(unsigned int speed)
8483 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8485 if (speed == __speed) \
8486 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8489 TEST_SPEED_RETURN(400G, 400000);
8490 TEST_SPEED_RETURN(200G, 200000);
8491 TEST_SPEED_RETURN(100G, 100000);
8492 TEST_SPEED_RETURN(50G, 50000);
8493 TEST_SPEED_RETURN(40G, 40000);
8494 TEST_SPEED_RETURN(25G, 25000);
8495 TEST_SPEED_RETURN(10G, 10000);
8496 TEST_SPEED_RETURN(1G, 1000);
8497 TEST_SPEED_RETURN(100M, 100);
8499 #undef TEST_SPEED_RETURN
8505 * Return the port capabilities bit for the highest speed in the capabilities.
8507 uint32_t fwcap_top_speed(uint32_t caps)
8509 #define TEST_SPEED_RETURN(__caps_speed) \
8511 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8512 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8515 TEST_SPEED_RETURN(400G);
8516 TEST_SPEED_RETURN(200G);
8517 TEST_SPEED_RETURN(100G);
8518 TEST_SPEED_RETURN(50G);
8519 TEST_SPEED_RETURN(40G);
8520 TEST_SPEED_RETURN(25G);
8521 TEST_SPEED_RETURN(10G);
8522 TEST_SPEED_RETURN(1G);
8523 TEST_SPEED_RETURN(100M);
8525 #undef TEST_SPEED_RETURN
8531 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8532 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8534 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8535 * 32-bit Port Capabilities value.
8537 static uint32_t lstatus_to_fwcap(u32 lstatus)
8539 uint32_t linkattr = 0;
8542 * Unfortunately the format of the Link Status in the old
8543 * 16-bit Port Information message isn't the same as the
8544 * 16-bit Port Capabilities bitfield used everywhere else ...
8546 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8547 linkattr |= FW_PORT_CAP32_FC_RX;
8548 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8549 linkattr |= FW_PORT_CAP32_FC_TX;
8550 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8551 linkattr |= FW_PORT_CAP32_SPEED_100M;
8552 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8553 linkattr |= FW_PORT_CAP32_SPEED_1G;
8554 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8555 linkattr |= FW_PORT_CAP32_SPEED_10G;
8556 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8557 linkattr |= FW_PORT_CAP32_SPEED_25G;
8558 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8559 linkattr |= FW_PORT_CAP32_SPEED_40G;
8560 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8561 linkattr |= FW_PORT_CAP32_SPEED_100G;
8567 * Updates all fields owned by the common code in port_info and link_config
8568 * based on information provided by the firmware. Does not touch any
8569 * requested_* field.
8571 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8572 enum fw_port_action action, bool *mod_changed, bool *link_changed)
8574 struct link_config old_lc, *lc = &pi->link_cfg;
8577 int old_ptype, old_mtype;
8579 old_ptype = pi->port_type;
8580 old_mtype = pi->mod_type;
8582 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8583 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8585 pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8586 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8587 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8588 G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8590 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8591 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8592 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8593 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8594 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8596 linkattr = lstatus_to_fwcap(stat);
8597 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8598 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8600 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8601 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8602 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8603 G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8605 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32);
8606 lc->acaps = be32_to_cpu(p->u.info32.acaps32);
8607 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32);
8608 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8609 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8611 linkattr = be32_to_cpu(p->u.info32.linkattr32);
8613 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8617 lc->speed = fwcap_to_speed(linkattr);
8618 lc->fec = fwcap_to_fec(linkattr, true);
8621 if (linkattr & FW_PORT_CAP32_FC_RX)
8623 if (linkattr & FW_PORT_CAP32_FC_TX)
8627 if (mod_changed != NULL)
8628 *mod_changed = false;
8629 if (link_changed != NULL)
8630 *link_changed = false;
8631 if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
8632 old_lc.pcaps != lc->pcaps) {
8633 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE)
8634 lc->fec_hint = fwcap_to_fec(lc->acaps, true);
8635 if (mod_changed != NULL)
8636 *mod_changed = true;
8638 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
8639 old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
8640 if (link_changed != NULL)
8641 *link_changed = true;
8646 * t4_update_port_info - retrieve and update port information if changed
8647 * @pi: the port_info
8649 * We issue a Get Port Information Command to the Firmware and, if
8650 * successful, we check to see if anything is different from what we
8651 * last recorded and update things accordingly.
8653 int t4_update_port_info(struct port_info *pi)
8655 struct adapter *sc = pi->adapter;
8656 struct fw_port_cmd cmd;
8657 enum fw_port_action action;
8660 memset(&cmd, 0, sizeof(cmd));
8661 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
8662 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8663 V_FW_PORT_CMD_PORTID(pi->tx_chan));
8664 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
8665 FW_PORT_ACTION_GET_PORT_INFO;
8666 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
8668 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
8672 handle_port_info(pi, &cmd, action, NULL, NULL);
8677 * t4_handle_fw_rpl - process a FW reply message
8678 * @adap: the adapter
8679 * @rpl: start of the FW message
8681 * Processes a FW message, such as link state change messages.
8683 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8685 u8 opcode = *(const u8 *)rpl;
8686 const struct fw_port_cmd *p = (const void *)rpl;
8687 enum fw_port_action action =
8688 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
8689 bool mod_changed, link_changed;
8691 if (opcode == FW_PORT_CMD &&
8692 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8693 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8694 /* link/module state change message */
8696 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
8697 struct port_info *pi = NULL;
8698 struct link_config *lc;
8700 for_each_port(adap, i) {
8701 pi = adap2pinfo(adap, i);
8702 if (pi->tx_chan == chan)
8708 handle_port_info(pi, p, action, &mod_changed, &link_changed);
8711 t4_os_portmod_changed(pi);
8714 t4_os_link_changed(pi);
8718 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
8725 * get_pci_mode - determine a card's PCI mode
8726 * @adapter: the adapter
8727 * @p: where to store the PCI settings
8729 * Determines a card's PCI mode and associated parameters, such as speed
8732 static void get_pci_mode(struct adapter *adapter,
8733 struct pci_params *p)
8738 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8740 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
8741 p->speed = val & PCI_EXP_LNKSTA_CLS;
8742 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8747 u32 vendor_and_model_id;
8751 int t4_get_flash_params(struct adapter *adapter)
8754 * Table for non-standard supported Flash parts. Note, all Flash
8755 * parts must have 64KB sectors.
8757 static struct flash_desc supported_flash[] = {
8758 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8763 unsigned int part, manufacturer;
8764 unsigned int density, size = 0;
8768 * Issue a Read ID Command to the Flash part. We decode supported
8769 * Flash parts and their sizes from this. There's a newer Query
8770 * Command which can retrieve detailed geometry information but many
8771 * Flash parts don't support it.
8773 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
8775 ret = sf1_read(adapter, 3, 0, 1, &flashid);
8776 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
8781 * Check to see if it's one of our non-standard supported Flash parts.
8783 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8784 if (supported_flash[part].vendor_and_model_id == flashid) {
8785 adapter->params.sf_size =
8786 supported_flash[part].size_mb;
8787 adapter->params.sf_nsec =
8788 adapter->params.sf_size / SF_SEC_SIZE;
8793 * Decode Flash part size. The code below looks repetative with
8794 * common encodings, but that's not guaranteed in the JEDEC
8795 * specification for the Read JADEC ID command. The only thing that
8796 * we're guaranteed by the JADEC specification is where the
8797 * Manufacturer ID is in the returned result. After that each
8798 * Manufacturer ~could~ encode things completely differently.
8799 * Note, all Flash parts must have 64KB sectors.
8801 manufacturer = flashid & 0xff;
8802 switch (manufacturer) {
8803 case 0x20: /* Micron/Numonix */
8805 * This Density -> Size decoding table is taken from Micron
8808 density = (flashid >> 16) & 0xff;
8810 case 0x14: size = 1 << 20; break; /* 1MB */
8811 case 0x15: size = 1 << 21; break; /* 2MB */
8812 case 0x16: size = 1 << 22; break; /* 4MB */
8813 case 0x17: size = 1 << 23; break; /* 8MB */
8814 case 0x18: size = 1 << 24; break; /* 16MB */
8815 case 0x19: size = 1 << 25; break; /* 32MB */
8816 case 0x20: size = 1 << 26; break; /* 64MB */
8817 case 0x21: size = 1 << 27; break; /* 128MB */
8818 case 0x22: size = 1 << 28; break; /* 256MB */
8822 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
8824 * This Density -> Size decoding table is taken from ISSI
8827 density = (flashid >> 16) & 0xff;
8829 case 0x16: size = 1 << 25; break; /* 32MB */
8830 case 0x17: size = 1 << 26; break; /* 64MB */
8834 case 0xc2: /* Macronix */
8836 * This Density -> Size decoding table is taken from Macronix
8839 density = (flashid >> 16) & 0xff;
8841 case 0x17: size = 1 << 23; break; /* 8MB */
8842 case 0x18: size = 1 << 24; break; /* 16MB */
8846 case 0xef: /* Winbond */
8848 * This Density -> Size decoding table is taken from Winbond
8851 density = (flashid >> 16) & 0xff;
8853 case 0x17: size = 1 << 23; break; /* 8MB */
8854 case 0x18: size = 1 << 24; break; /* 16MB */
8859 /* If we didn't recognize the FLASH part, that's no real issue: the
8860 * Hardware/Software contract says that Hardware will _*ALWAYS*_
8861 * use a FLASH part which is at least 4MB in size and has 64KB
8862 * sectors. The unrecognized FLASH part is likely to be much larger
8863 * than 4MB, but that's all we really need.
8866 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
8871 * Store decoded Flash size and fall through into vetting code.
8873 adapter->params.sf_size = size;
8874 adapter->params.sf_nsec = size / SF_SEC_SIZE;
8878 * We should ~probably~ reject adapters with FLASHes which are too
8879 * small but we have some legacy FPGAs with small FLASHes that we'd
8880 * still like to use. So instead we emit a scary message ...
8882 if (adapter->params.sf_size < FLASH_MIN_SIZE)
8883 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8884 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
8889 static void set_pcie_completion_timeout(struct adapter *adapter,
8895 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8897 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
8900 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
8904 const struct chip_params *t4_get_chip_params(int chipid)
8906 static const struct chip_params chip_params[] = {
8910 .pm_stats_cnt = PM_NSTATS,
8911 .cng_ch_bits_log = 2,
8913 .cim_num_obq = CIM_NUM_OBQ,
8914 .mps_rplc_size = 128,
8916 .sge_fl_db = F_DBPRIO,
8917 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
8922 .pm_stats_cnt = PM_NSTATS,
8923 .cng_ch_bits_log = 2,
8925 .cim_num_obq = CIM_NUM_OBQ_T5,
8926 .mps_rplc_size = 128,
8928 .sge_fl_db = F_DBPRIO | F_DBTYPE,
8929 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8934 .pm_stats_cnt = T6_PM_NSTATS,
8935 .cng_ch_bits_log = 3,
8937 .cim_num_obq = CIM_NUM_OBQ_T5,
8938 .mps_rplc_size = 256,
8941 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8945 chipid -= CHELSIO_T4;
8946 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
8949 return &chip_params[chipid];
8953 * t4_prep_adapter - prepare SW and HW for operation
8954 * @adapter: the adapter
8955 * @buf: temporary space of at least VPD_LEN size provided by the caller.
8957 * Initialize adapter SW state for the various HW modules, set initial
8958 * values for some adapter tunables, take PHYs out of reset, and
8959 * initialize the MDIO interface.
8961 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
8967 get_pci_mode(adapter, &adapter->params.pci);
8969 pl_rev = t4_read_reg(adapter, A_PL_REV);
8970 adapter->params.chipid = G_CHIPID(pl_rev);
8971 adapter->params.rev = G_REV(pl_rev);
8972 if (adapter->params.chipid == 0) {
8973 /* T4 did not have chipid in PL_REV (T5 onwards do) */
8974 adapter->params.chipid = CHELSIO_T4;
8976 /* T4A1 chip is not supported */
8977 if (adapter->params.rev == 1) {
8978 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
8983 adapter->chip_params = t4_get_chip_params(chip_id(adapter));
8984 if (adapter->chip_params == NULL)
8987 adapter->params.pci.vpd_cap_addr =
8988 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
8990 ret = t4_get_flash_params(adapter);
8994 /* Cards with real ASICs have the chipid in the PCIe device id */
8995 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
8996 if (device_id >> 12 == chip_id(adapter))
8997 adapter->params.cim_la_size = CIMLA_SIZE;
9000 adapter->params.fpga = 1;
9001 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
9004 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
9008 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9011 * Default port and clock for debugging in case we can't reach FW.
9013 adapter->params.nports = 1;
9014 adapter->params.portvec = 1;
9015 adapter->params.vpd.cclk = 50000;
9017 /* Set pci completion timeout value to 4 seconds. */
9018 set_pcie_completion_timeout(adapter, 0xd);
9023 * t4_shutdown_adapter - shut down adapter, host & wire
9024 * @adapter: the adapter
9026 * Perform an emergency shutdown of the adapter and stop it from
9027 * continuing any further communication on the ports or DMA to the
9028 * host. This is typically used when the adapter and/or firmware
9029 * have crashed and we want to prevent any further accidental
9030 * communication with the rest of the world. This will also force
9031 * the port Link Status to go down -- if register writes work --
9032 * which should help our peers figure out that we're down.
9034 int t4_shutdown_adapter(struct adapter *adapter)
9038 t4_intr_disable(adapter);
9039 t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
9040 for_each_port(adapter, port) {
9041 u32 a_port_cfg = is_t4(adapter) ?
9042 PORT_REG(port, A_XGMAC_PORT_CFG) :
9043 T5_PORT_REG(port, A_MAC_PORT_CFG);
9045 t4_write_reg(adapter, a_port_cfg,
9046 t4_read_reg(adapter, a_port_cfg)
9047 & ~V_SIGNAL_DET(1));
9049 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9055 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9056 * @adapter: the adapter
9057 * @qid: the Queue ID
9058 * @qtype: the Ingress or Egress type for @qid
9059 * @user: true if this request is for a user mode queue
9060 * @pbar2_qoffset: BAR2 Queue Offset
9061 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9063 * Returns the BAR2 SGE Queue Registers information associated with the
9064 * indicated Absolute Queue ID. These are passed back in return value
9065 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9066 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9068 * This may return an error which indicates that BAR2 SGE Queue
9069 * registers aren't available. If an error is not returned, then the
9070 * following values are returned:
9072 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9073 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9075 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9076 * require the "Inferred Queue ID" ability may be used. E.g. the
9077 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9078 * then these "Inferred Queue ID" register may not be used.
9080 int t4_bar2_sge_qregs(struct adapter *adapter,
9082 enum t4_bar2_qtype qtype,
9085 unsigned int *pbar2_qid)
9087 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9088 u64 bar2_page_offset, bar2_qoffset;
9089 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9091 /* T4 doesn't support BAR2 SGE Queue registers for kernel
9094 if (!user && is_t4(adapter))
9097 /* Get our SGE Page Size parameters.
9099 page_shift = adapter->params.sge.page_shift;
9100 page_size = 1 << page_shift;
9102 /* Get the right Queues per Page parameters for our Queue.
9104 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9105 ? adapter->params.sge.eq_s_qpp
9106 : adapter->params.sge.iq_s_qpp);
9107 qpp_mask = (1 << qpp_shift) - 1;
9109 /* Calculate the basics of the BAR2 SGE Queue register area:
9110 * o The BAR2 page the Queue registers will be in.
9111 * o The BAR2 Queue ID.
9112 * o The BAR2 Queue ID Offset into the BAR2 page.
9114 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9115 bar2_qid = qid & qpp_mask;
9116 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9118 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9119 * hardware will infer the Absolute Queue ID simply from the writes to
9120 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9121 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9122 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9123 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9124 * from the BAR2 Page and BAR2 Queue ID.
9126 * One important censequence of this is that some BAR2 SGE registers
9127 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9128 * there. But other registers synthesize the SGE Queue ID purely
9129 * from the writes to the registers -- the Write Combined Doorbell
9130 * Buffer is a good example. These BAR2 SGE Registers are only
9131 * available for those BAR2 SGE Register areas where the SGE Absolute
9132 * Queue ID can be inferred from simple writes.
9134 bar2_qoffset = bar2_page_offset;
9135 bar2_qinferred = (bar2_qid_offset < page_size);
9136 if (bar2_qinferred) {
9137 bar2_qoffset += bar2_qid_offset;
9141 *pbar2_qoffset = bar2_qoffset;
9142 *pbar2_qid = bar2_qid;
9147 * t4_init_devlog_params - initialize adapter->params.devlog
9148 * @adap: the adapter
9149 * @fw_attach: whether we can talk to the firmware
9151 * Initialize various fields of the adapter's Firmware Device Log
9152 * Parameters structure.
9154 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9156 struct devlog_params *dparams = &adap->params.devlog;
9158 unsigned int devlog_meminfo;
9159 struct fw_devlog_cmd devlog_cmd;
9162 /* If we're dealing with newer firmware, the Device Log Paramerters
9163 * are stored in a designated register which allows us to access the
9164 * Device Log even if we can't talk to the firmware.
9167 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9169 unsigned int nentries, nentries128;
9171 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9172 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9174 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9175 nentries = (nentries128 + 1) * 128;
9176 dparams->size = nentries * sizeof(struct fw_devlog_e);
9182 * For any failing returns ...
9184 memset(dparams, 0, sizeof *dparams);
9187 * If we can't talk to the firmware, there's really nothing we can do
9193 /* Otherwise, ask the firmware for it's Device Log Parameters.
9195 memset(&devlog_cmd, 0, sizeof devlog_cmd);
9196 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9197 F_FW_CMD_REQUEST | F_FW_CMD_READ);
9198 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9199 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9205 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9206 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9207 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9208 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9214 * t4_init_sge_params - initialize adap->params.sge
9215 * @adapter: the adapter
9217 * Initialize various fields of the adapter's SGE Parameters structure.
9219 int t4_init_sge_params(struct adapter *adapter)
9222 struct sge_params *sp = &adapter->params.sge;
9223 unsigned i, tscale = 1;
9225 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9226 sp->counter_val[0] = G_THRESHOLD_0(r);
9227 sp->counter_val[1] = G_THRESHOLD_1(r);
9228 sp->counter_val[2] = G_THRESHOLD_2(r);
9229 sp->counter_val[3] = G_THRESHOLD_3(r);
9231 if (chip_id(adapter) >= CHELSIO_T6) {
9232 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9233 tscale = G_TSCALE(r);
9240 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9241 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9242 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9243 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9244 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9245 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9246 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9247 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9248 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9250 r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9251 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9253 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9254 else if (is_t5(adapter))
9255 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9257 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9259 /* egress queues: log2 of # of doorbells per BAR2 page */
9260 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9261 r >>= S_QUEUESPERPAGEPF0 +
9262 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9263 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9265 /* ingress queues: log2 of # of doorbells per BAR2 page */
9266 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9267 r >>= S_QUEUESPERPAGEPF0 +
9268 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9269 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9271 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9272 r >>= S_HOSTPAGESIZEPF0 +
9273 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9274 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9276 r = t4_read_reg(adapter, A_SGE_CONTROL);
9277 sp->sge_control = r;
9278 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9279 sp->fl_pktshift = G_PKTSHIFT(r);
9280 if (chip_id(adapter) <= CHELSIO_T5) {
9281 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9282 X_INGPADBOUNDARY_SHIFT);
9284 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9285 X_T6_INGPADBOUNDARY_SHIFT);
9288 sp->pack_boundary = sp->pad_boundary;
9290 r = t4_read_reg(adapter, A_SGE_CONTROL2);
9291 if (G_INGPACKBOUNDARY(r) == 0)
9292 sp->pack_boundary = 16;
9294 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9296 for (i = 0; i < SGE_FLBUF_SIZES; i++)
9297 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9298 A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9304 * Read and cache the adapter's compressed filter mode and ingress config.
9306 static void read_filter_mode_and_ingress_config(struct adapter *adap,
9310 struct tp_params *tpp = &adap->params.tp;
9312 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP,
9314 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG,
9318 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9319 * shift positions of several elements of the Compressed Filter Tuple
9320 * for this adapter which we need frequently ...
9322 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9323 tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9324 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9325 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9326 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9327 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9328 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9329 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9330 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9331 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9333 if (chip_id(adap) > CHELSIO_T4) {
9334 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9335 adap->params.tp.hash_filter_mask = v;
9336 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9337 adap->params.tp.hash_filter_mask |= (u64)v << 32;
9342 * t4_init_tp_params - initialize adap->params.tp
9343 * @adap: the adapter
9345 * Initialize various fields of the adapter's TP Parameters structure.
9347 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9351 struct tp_params *tpp = &adap->params.tp;
9353 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9354 tpp->tre = G_TIMERRESOLUTION(v);
9355 tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9357 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9358 for (chan = 0; chan < MAX_NCHAN; chan++)
9359 tpp->tx_modq[chan] = chan;
9361 read_filter_mode_and_ingress_config(adap, sleep_ok);
9364 * Cache a mask of the bits that represent the error vector portion of
9365 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room
9366 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
9368 tpp->err_vec_mask = htobe16(0xffff);
9369 if (chip_id(adap) > CHELSIO_T5) {
9370 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9371 if (v & F_CRXPKTENC) {
9373 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
9381 * t4_filter_field_shift - calculate filter field shift
9382 * @adap: the adapter
9383 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9385 * Return the shift position of a filter field within the Compressed
9386 * Filter Tuple. The filter field is specified via its selection bit
9387 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9389 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9391 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9395 if ((filter_mode & filter_sel) == 0)
9398 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9399 switch (filter_mode & sel) {
9401 field_shift += W_FT_FCOE;
9404 field_shift += W_FT_PORT;
9407 field_shift += W_FT_VNIC_ID;
9410 field_shift += W_FT_VLAN;
9413 field_shift += W_FT_TOS;
9416 field_shift += W_FT_PROTOCOL;
9419 field_shift += W_FT_ETHERTYPE;
9422 field_shift += W_FT_MACMATCH;
9425 field_shift += W_FT_MPSHITTYPE;
9427 case F_FRAGMENTATION:
9428 field_shift += W_FT_FRAGMENTATION;
9435 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9439 struct port_info *p = adap2pinfo(adap, port_id);
9441 struct vi_info *vi = &p->vi[0];
9443 for (i = 0, j = -1; i <= p->port_id; i++) {
9446 } while ((adap->params.portvec & (1 << j)) == 0);
9450 p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9451 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9454 if (!(adap->flags & IS_VF) ||
9455 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9456 t4_update_port_info(p);
9459 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9460 &vi->vfvld, &vi->vin);
9465 t4_os_set_hw_addr(p, addr);
9467 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9468 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9469 V_FW_PARAMS_PARAM_YZ(vi->viid);
9470 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val);
9472 vi->rss_base = 0xffff;
9474 /* MPASS((val >> 16) == rss_size); */
9475 vi->rss_base = val & 0xffff;
9482 * t4_read_cimq_cfg - read CIM queue configuration
9483 * @adap: the adapter
9484 * @base: holds the queue base addresses in bytes
9485 * @size: holds the queue sizes in bytes
9486 * @thres: holds the queue full thresholds in bytes
9488 * Returns the current configuration of the CIM queues, starting with
9489 * the IBQs, then the OBQs.
9491 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9494 int cim_num_obq = adap->chip_params->cim_num_obq;
9496 for (i = 0; i < CIM_NUM_IBQ; i++) {
9497 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9499 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9500 /* value is in 256-byte units */
9501 *base++ = G_CIMQBASE(v) * 256;
9502 *size++ = G_CIMQSIZE(v) * 256;
9503 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9505 for (i = 0; i < cim_num_obq; i++) {
9506 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9508 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9509 /* value is in 256-byte units */
9510 *base++ = G_CIMQBASE(v) * 256;
9511 *size++ = G_CIMQSIZE(v) * 256;
9516 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9517 * @adap: the adapter
9518 * @qid: the queue index
9519 * @data: where to store the queue contents
9520 * @n: capacity of @data in 32-bit words
9522 * Reads the contents of the selected CIM queue starting at address 0 up
9523 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9524 * error and the number of 32-bit words actually read on success.
9526 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9528 int i, err, attempts;
9530 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9532 if (qid > 5 || (n & 3))
9535 addr = qid * nwords;
9539 /* It might take 3-10ms before the IBQ debug read access is allowed.
9540 * Wait for 1 Sec with a delay of 1 usec.
9544 for (i = 0; i < n; i++, addr++) {
9545 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9547 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9551 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9553 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9558 * t4_read_cim_obq - read the contents of a CIM outbound queue
9559 * @adap: the adapter
9560 * @qid: the queue index
9561 * @data: where to store the queue contents
9562 * @n: capacity of @data in 32-bit words
9564 * Reads the contents of the selected CIM queue starting at address 0 up
9565 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9566 * error and the number of 32-bit words actually read on success.
9568 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9571 unsigned int addr, v, nwords;
9572 int cim_num_obq = adap->chip_params->cim_num_obq;
9574 if ((qid > (cim_num_obq - 1)) || (n & 3))
9577 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9578 V_QUENUMSELECT(qid));
9579 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9581 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */
9582 nwords = G_CIMQSIZE(v) * 64; /* same */
9586 for (i = 0; i < n; i++, addr++) {
9587 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
9589 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
9593 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
9595 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
9601 CIM_CTL_BASE = 0x2000,
9602 CIM_PBT_ADDR_BASE = 0x2800,
9603 CIM_PBT_LRF_BASE = 0x3000,
9604 CIM_PBT_DATA_BASE = 0x3800
9608 * t4_cim_read - read a block from CIM internal address space
9609 * @adap: the adapter
9610 * @addr: the start address within the CIM address space
9611 * @n: number of words to read
9612 * @valp: where to store the result
9614 * Reads a block of 4-byte words from the CIM intenal address space.
9616 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9621 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9624 for ( ; !ret && n--; addr += 4) {
9625 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
9626 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9629 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
9635 * t4_cim_write - write a block into CIM internal address space
9636 * @adap: the adapter
9637 * @addr: the start address within the CIM address space
9638 * @n: number of words to write
9639 * @valp: set of values to write
9641 * Writes a block of 4-byte words into the CIM intenal address space.
9643 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9644 const unsigned int *valp)
9648 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9651 for ( ; !ret && n--; addr += 4) {
9652 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
9653 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
9654 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9660 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9663 return t4_cim_write(adap, addr, 1, &val);
9667 * t4_cim_ctl_read - read a block from CIM control region
9668 * @adap: the adapter
9669 * @addr: the start address within the CIM control region
9670 * @n: number of words to read
9671 * @valp: where to store the result
9673 * Reads a block of 4-byte words from the CIM control region.
9675 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
9678 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
9682 * t4_cim_read_la - read CIM LA capture buffer
9683 * @adap: the adapter
9684 * @la_buf: where to store the LA data
9685 * @wrptr: the HW write pointer within the capture buffer
9687 * Reads the contents of the CIM LA buffer with the most recent entry at
9688 * the end of the returned data and with the entry at @wrptr first.
9689 * We try to leave the LA in the running state we find it in.
9691 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9694 unsigned int cfg, val, idx;
9696 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
9700 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */
9701 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
9706 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9710 idx = G_UPDBGLAWRPTR(val);
9714 for (i = 0; i < adap->params.cim_la_size; i++) {
9715 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9716 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
9719 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9722 if (val & F_UPDBGLARDEN) {
9726 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
9730 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
9731 idx = (idx + 1) & M_UPDBGLARDPTR;
9733 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9734 * identify the 32-bit portion of the full 312-bit data
9737 while ((idx & 0xf) > 9)
9738 idx = (idx + 1) % M_UPDBGLARDPTR;
9741 if (cfg & F_UPDBGLAEN) {
9742 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9743 cfg & ~F_UPDBGLARDEN);
9751 * t4_tp_read_la - read TP LA capture buffer
9752 * @adap: the adapter
9753 * @la_buf: where to store the LA data
9754 * @wrptr: the HW write pointer within the capture buffer
9756 * Reads the contents of the TP LA buffer with the most recent entry at
9757 * the end of the returned data and with the entry at @wrptr first.
9758 * We leave the LA in the running state we find it in.
9760 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9762 bool last_incomplete;
9763 unsigned int i, cfg, val, idx;
9765 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
9766 if (cfg & F_DBGLAENABLE) /* freeze LA */
9767 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9768 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
9770 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
9771 idx = G_DBGLAWPTR(val);
9772 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
9773 if (last_incomplete)
9774 idx = (idx + 1) & M_DBGLARPTR;
9779 val &= ~V_DBGLARPTR(M_DBGLARPTR);
9780 val |= adap->params.tp.la_mask;
9782 for (i = 0; i < TPLA_SIZE; i++) {
9783 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
9784 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
9785 idx = (idx + 1) & M_DBGLARPTR;
9788 /* Wipe out last entry if it isn't valid */
9789 if (last_incomplete)
9790 la_buf[TPLA_SIZE - 1] = ~0ULL;
9792 if (cfg & F_DBGLAENABLE) /* restore running state */
9793 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9794 cfg | adap->params.tp.la_mask);
9798 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9799 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9800 * state for more than the Warning Threshold then we'll issue a warning about
9801 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9802 * appears to be hung every Warning Repeat second till the situation clears.
9803 * If the situation clears, we'll note that as well.
9805 #define SGE_IDMA_WARN_THRESH 1
9806 #define SGE_IDMA_WARN_REPEAT 300
9809 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9810 * @adapter: the adapter
9811 * @idma: the adapter IDMA Monitor state
9813 * Initialize the state of an SGE Ingress DMA Monitor.
9815 void t4_idma_monitor_init(struct adapter *adapter,
9816 struct sge_idma_monitor_state *idma)
9818 /* Initialize the state variables for detecting an SGE Ingress DMA
9819 * hang. The SGE has internal counters which count up on each clock
9820 * tick whenever the SGE finds its Ingress DMA State Engines in the
9821 * same state they were on the previous clock tick. The clock used is
9822 * the Core Clock so we have a limit on the maximum "time" they can
9823 * record; typically a very small number of seconds. For instance,
9824 * with a 600MHz Core Clock, we can only count up to a bit more than
9825 * 7s. So we'll synthesize a larger counter in order to not run the
9826 * risk of having the "timers" overflow and give us the flexibility to
9827 * maintain a Hung SGE State Machine of our own which operates across
9828 * a longer time frame.
9830 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9831 idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
9835 * t4_idma_monitor - monitor SGE Ingress DMA state
9836 * @adapter: the adapter
9837 * @idma: the adapter IDMA Monitor state
9838 * @hz: number of ticks/second
9839 * @ticks: number of ticks since the last IDMA Monitor call
9841 void t4_idma_monitor(struct adapter *adapter,
9842 struct sge_idma_monitor_state *idma,
9845 int i, idma_same_state_cnt[2];
9847 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9848 * are counters inside the SGE which count up on each clock when the
9849 * SGE finds its Ingress DMA State Engines in the same states they
9850 * were in the previous clock. The counters will peg out at
9851 * 0xffffffff without wrapping around so once they pass the 1s
9852 * threshold they'll stay above that till the IDMA state changes.
9854 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
9855 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
9856 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9858 for (i = 0; i < 2; i++) {
9859 u32 debug0, debug11;
9861 /* If the Ingress DMA Same State Counter ("timer") is less
9862 * than 1s, then we can reset our synthesized Stall Timer and
9863 * continue. If we have previously emitted warnings about a
9864 * potential stalled Ingress Queue, issue a note indicating
9865 * that the Ingress Queue has resumed forward progress.
9867 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9868 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
9869 CH_WARN(adapter, "SGE idma%d, queue %u, "
9870 "resumed after %d seconds\n",
9871 i, idma->idma_qid[i],
9872 idma->idma_stalled[i]/hz);
9873 idma->idma_stalled[i] = 0;
9877 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9878 * domain. The first time we get here it'll be because we
9879 * passed the 1s Threshold; each additional time it'll be
9880 * because the RX Timer Callback is being fired on its regular
9883 * If the stall is below our Potential Hung Ingress Queue
9884 * Warning Threshold, continue.
9886 if (idma->idma_stalled[i] == 0) {
9887 idma->idma_stalled[i] = hz;
9888 idma->idma_warn[i] = 0;
9890 idma->idma_stalled[i] += ticks;
9891 idma->idma_warn[i] -= ticks;
9894 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
9897 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9899 if (idma->idma_warn[i] > 0)
9901 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
9903 /* Read and save the SGE IDMA State and Queue ID information.
9904 * We do this every time in case it changes across time ...
9905 * can't be too careful ...
9907 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
9908 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9909 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9911 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
9912 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9913 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9915 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
9916 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9917 i, idma->idma_qid[i], idma->idma_state[i],
9918 idma->idma_stalled[i]/hz,
9920 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9925 * t4_read_pace_tbl - read the pace table
9926 * @adap: the adapter
9927 * @pace_vals: holds the returned values
9929 * Returns the values of TP's pace table in microseconds.
9931 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9935 for (i = 0; i < NTX_SCHED; i++) {
9936 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
9937 v = t4_read_reg(adap, A_TP_PACE_TABLE);
9938 pace_vals[i] = dack_ticks_to_usec(adap, v);
9943 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9944 * @adap: the adapter
9945 * @sched: the scheduler index
9946 * @kbps: the byte rate in Kbps
9947 * @ipg: the interpacket delay in tenths of nanoseconds
9949 * Return the current configuration of a HW Tx scheduler.
9951 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
9952 unsigned int *ipg, bool sleep_ok)
9954 unsigned int v, addr, bpt, cpt;
9957 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
9958 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9961 bpt = (v >> 8) & 0xff;
9964 *kbps = 0; /* scheduler disabled */
9966 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9967 *kbps = (v * bpt) / 125;
9971 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
9972 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9976 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9981 * t4_load_cfg - download config file
9982 * @adap: the adapter
9983 * @cfg_data: the cfg text file to write
9984 * @size: text file size
9986 * Write the supplied config text file to the card's serial flash.
9988 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9990 int ret, i, n, cfg_addr;
9992 unsigned int flash_cfg_start_sec;
9993 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9995 cfg_addr = t4_flash_cfg_addr(adap);
10000 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10002 if (size > FLASH_CFG_MAX_SIZE) {
10003 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
10004 FLASH_CFG_MAX_SIZE);
10008 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10010 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10011 flash_cfg_start_sec + i - 1);
10013 * If size == 0 then we're simply erasing the FLASH sectors associated
10014 * with the on-adapter Firmware Configuration File.
10016 if (ret || size == 0)
10019 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10020 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10021 if ( (size - i) < SF_PAGE_SIZE)
10025 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
10029 addr += SF_PAGE_SIZE;
10030 cfg_data += SF_PAGE_SIZE;
10035 CH_ERR(adap, "config file %s failed %d\n",
10036 (size == 0 ? "clear" : "download"), ret);
10041 * t5_fw_init_extern_mem - initialize the external memory
10042 * @adap: the adapter
10044 * Initializes the external memory on T5.
10046 int t5_fw_init_extern_mem(struct adapter *adap)
10048 u32 params[1], val[1];
10054 val[0] = 0xff; /* Initialize all MCs */
10055 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10056 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10057 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10058 FW_CMD_MAX_TIMEOUT);
10063 /* BIOS boot headers */
10064 typedef struct pci_expansion_rom_header {
10065 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10066 u8 reserved[22]; /* Reserved per processor Architecture data */
10067 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10068 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10070 /* Legacy PCI Expansion ROM Header */
10071 typedef struct legacy_pci_expansion_rom_header {
10072 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10073 u8 size512; /* Current Image Size in units of 512 bytes */
10074 u8 initentry_point[4];
10075 u8 cksum; /* Checksum computed on the entire Image */
10076 u8 reserved[16]; /* Reserved */
10077 u8 pcir_offset[2]; /* Offset to PCI Data Struture */
10078 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10080 /* EFI PCI Expansion ROM Header */
10081 typedef struct efi_pci_expansion_rom_header {
10082 u8 signature[2]; // ROM signature. The value 0xaa55
10083 u8 initialization_size[2]; /* Units 512. Includes this header */
10084 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10085 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */
10086 u8 efi_machine_type[2]; /* Machine type from EFI image header */
10087 u8 compression_type[2]; /* Compression type. */
10089 * Compression type definition
10090 * 0x0: uncompressed
10092 * 0x2-0xFFFF: Reserved
10094 u8 reserved[8]; /* Reserved */
10095 u8 efi_image_header_offset[2]; /* Offset to EFI Image */
10096 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10097 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10099 /* PCI Data Structure Format */
10100 typedef struct pcir_data_structure { /* PCI Data Structure */
10101 u8 signature[4]; /* Signature. The string "PCIR" */
10102 u8 vendor_id[2]; /* Vendor Identification */
10103 u8 device_id[2]; /* Device Identification */
10104 u8 vital_product[2]; /* Pointer to Vital Product Data */
10105 u8 length[2]; /* PCIR Data Structure Length */
10106 u8 revision; /* PCIR Data Structure Revision */
10107 u8 class_code[3]; /* Class Code */
10108 u8 image_length[2]; /* Image Length. Multiple of 512B */
10109 u8 code_revision[2]; /* Revision Level of Code/Data */
10110 u8 code_type; /* Code Type. */
10112 * PCI Expansion ROM Code Types
10113 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10114 * 0x01: Open Firmware standard for PCI. FCODE
10115 * 0x02: Hewlett-Packard PA RISC. HP reserved
10116 * 0x03: EFI Image. EFI
10117 * 0x04-0xFF: Reserved.
10119 u8 indicator; /* Indicator. Identifies the last image in the ROM */
10120 u8 reserved[2]; /* Reserved */
10121 } pcir_data_t; /* PCI__DATA_STRUCTURE */
10123 /* BOOT constants */
10125 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10126 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
10127 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
10128 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10129 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */
10130 VENDOR_ID = 0x1425, /* Vendor ID */
10131 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10135 * modify_device_id - Modifies the device ID of the Boot BIOS image
10136 * @adatper: the device ID to write.
10137 * @boot_data: the boot image to modify.
10139 * Write the supplied device ID to the boot BIOS image.
10141 static void modify_device_id(int device_id, u8 *boot_data)
10143 legacy_pci_exp_rom_header_t *header;
10144 pcir_data_t *pcir_header;
10145 u32 cur_header = 0;
10148 * Loop through all chained images and change the device ID's
10151 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10152 pcir_header = (pcir_data_t *) &boot_data[cur_header +
10153 le16_to_cpu(*(u16*)header->pcir_offset)];
10156 * Only modify the Device ID if code type is Legacy or HP.
10157 * 0x00: Okay to modify
10158 * 0x01: FCODE. Do not be modify
10159 * 0x03: Okay to modify
10160 * 0x04-0xFF: Do not modify
10162 if (pcir_header->code_type == 0x00) {
10167 * Modify Device ID to match current adatper
10169 *(u16*) pcir_header->device_id = device_id;
10172 * Set checksum temporarily to 0.
10173 * We will recalculate it later.
10175 header->cksum = 0x0;
10178 * Calculate and update checksum
10180 for (i = 0; i < (header->size512 * 512); i++)
10181 csum += (u8)boot_data[cur_header + i];
10184 * Invert summed value to create the checksum
10185 * Writing new checksum value directly to the boot data
10187 boot_data[cur_header + 7] = -csum;
10189 } else if (pcir_header->code_type == 0x03) {
10192 * Modify Device ID to match current adatper
10194 *(u16*) pcir_header->device_id = device_id;
10200 * Check indicator element to identify if this is the last
10201 * image in the ROM.
10203 if (pcir_header->indicator & 0x80)
10207 * Move header pointer up to the next image in the ROM.
10209 cur_header += header->size512 * 512;
10214 * t4_load_boot - download boot flash
10215 * @adapter: the adapter
10216 * @boot_data: the boot image to write
10217 * @boot_addr: offset in flash to write boot_data
10218 * @size: image size
10220 * Write the supplied boot image to the card's serial flash.
10221 * The boot image has the following sections: a 28-byte header and the
10224 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10225 unsigned int boot_addr, unsigned int size)
10227 pci_exp_rom_header_t *header;
10229 pcir_data_t *pcir_header;
10231 uint16_t device_id;
10233 unsigned int boot_sector = (boot_addr * 1024 );
10234 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10237 * Make sure the boot image does not encroach on the firmware region
10239 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10240 CH_ERR(adap, "boot image encroaching on firmware region\n");
10245 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10246 * and Boot configuration data sections. These 3 boot sections span
10247 * sectors 0 to 7 in flash and live right before the FW image location.
10249 i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10251 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10252 (boot_sector >> 16) + i - 1);
10255 * If size == 0 then we're simply erasing the FLASH sectors associated
10256 * with the on-adapter option ROM file
10258 if (ret || (size == 0))
10261 /* Get boot header */
10262 header = (pci_exp_rom_header_t *)boot_data;
10263 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10264 /* PCIR Data Structure */
10265 pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10268 * Perform some primitive sanity testing to avoid accidentally
10269 * writing garbage over the boot sectors. We ought to check for
10270 * more but it's not worth it for now ...
10272 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10273 CH_ERR(adap, "boot image too small/large\n");
10277 #ifndef CHELSIO_T4_DIAGS
10279 * Check BOOT ROM header signature
10281 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10282 CH_ERR(adap, "Boot image missing signature\n");
10287 * Check PCI header signature
10289 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10290 CH_ERR(adap, "PCI header missing signature\n");
10295 * Check Vendor ID matches Chelsio ID
10297 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10298 CH_ERR(adap, "Vendor ID missing signature\n");
10304 * Retrieve adapter's device ID
10306 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10307 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10308 device_id = device_id & 0xf0ff;
10311 * Check PCIE Device ID
10313 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10315 * Change the device ID in the Boot BIOS image to match
10316 * the Device ID of the current adapter.
10318 modify_device_id(device_id, boot_data);
10322 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10323 * we finish copying the rest of the boot image. This will ensure
10324 * that the BIOS boot header will only be written if the boot image
10325 * was written in full.
10327 addr = boot_sector;
10328 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10329 addr += SF_PAGE_SIZE;
10330 boot_data += SF_PAGE_SIZE;
10331 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10336 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10337 (const u8 *)header, 0);
10341 CH_ERR(adap, "boot image download failed, error %d\n", ret);
10346 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10347 * @adapter: the adapter
10349 * Return the address within the flash where the OptionROM Configuration
10350 * is stored, or an error if the device FLASH is too small to contain
10351 * a OptionROM Configuration.
10353 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10356 * If the device FLASH isn't large enough to hold a Firmware
10357 * Configuration File, return an error.
10359 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10362 return FLASH_BOOTCFG_START;
10365 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10367 int ret, i, n, cfg_addr;
10369 unsigned int flash_cfg_start_sec;
10370 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10372 cfg_addr = t4_flash_bootcfg_addr(adap);
10377 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10379 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10380 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10381 FLASH_BOOTCFG_MAX_SIZE);
10385 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10387 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10388 flash_cfg_start_sec + i - 1);
10391 * If size == 0 then we're simply erasing the FLASH sectors associated
10392 * with the on-adapter OptionROM Configuration File.
10394 if (ret || size == 0)
10397 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10398 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10399 if ( (size - i) < SF_PAGE_SIZE)
10403 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10407 addr += SF_PAGE_SIZE;
10408 cfg_data += SF_PAGE_SIZE;
10413 CH_ERR(adap, "boot config data %s failed %d\n",
10414 (size == 0 ? "clear" : "download"), ret);
10419 * t4_set_filter_mode - configure the optional components of filter tuples
10420 * @adap: the adapter
10421 * @mode_map: a bitmap selcting which optional filter components to enable
10422 * @sleep_ok: if true we may sleep while awaiting command completion
10424 * Sets the filter mode by selecting the optional components to enable
10425 * in filter tuples. Returns 0 on success and a negative error if the
10426 * requested mode needs more bits than are available for optional
10429 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
10432 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
10436 for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
10437 if (mode_map & (1 << i))
10439 if (nbits > FILTER_OPT_LEN)
10441 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok);
10442 read_filter_mode_and_ingress_config(adap, sleep_ok);
10448 * t4_clr_port_stats - clear port statistics
10449 * @adap: the adapter
10450 * @idx: the port index
10452 * Clear HW statistics for the given port.
10454 void t4_clr_port_stats(struct adapter *adap, int idx)
10457 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
10458 u32 port_base_addr;
10461 port_base_addr = PORT_BASE(idx);
10463 port_base_addr = T5_PORT_BASE(idx);
10465 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
10466 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
10467 t4_write_reg(adap, port_base_addr + i, 0);
10468 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
10469 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
10470 t4_write_reg(adap, port_base_addr + i, 0);
10471 for (i = 0; i < 4; i++)
10472 if (bgmap & (1 << i)) {
10474 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
10476 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
10481 * t4_i2c_rd - read I2C data from adapter
10482 * @adap: the adapter
10483 * @port: Port number if per-port device; <0 if not
10484 * @devid: per-port device ID or absolute device ID
10485 * @offset: byte offset into device I2C space
10486 * @len: byte length of I2C space data
10487 * @buf: buffer in which to return I2C data
10489 * Reads the I2C data from the indicated device and location.
10491 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
10492 int port, unsigned int devid,
10493 unsigned int offset, unsigned int len,
10496 u32 ldst_addrspace;
10497 struct fw_ldst_cmd ldst;
10503 len > sizeof ldst.u.i2c.data)
10506 memset(&ldst, 0, sizeof ldst);
10507 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10508 ldst.op_to_addrspace =
10509 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10513 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10514 ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10515 ldst.u.i2c.did = devid;
10516 ldst.u.i2c.boffset = offset;
10517 ldst.u.i2c.blen = len;
10518 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10520 memcpy(buf, ldst.u.i2c.data, len);
10525 * t4_i2c_wr - write I2C data to adapter
10526 * @adap: the adapter
10527 * @port: Port number if per-port device; <0 if not
10528 * @devid: per-port device ID or absolute device ID
10529 * @offset: byte offset into device I2C space
10530 * @len: byte length of I2C space data
10531 * @buf: buffer containing new I2C data
10533 * Write the I2C data to the indicated device and location.
10535 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
10536 int port, unsigned int devid,
10537 unsigned int offset, unsigned int len,
10540 u32 ldst_addrspace;
10541 struct fw_ldst_cmd ldst;
10546 len > sizeof ldst.u.i2c.data)
10549 memset(&ldst, 0, sizeof ldst);
10550 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10551 ldst.op_to_addrspace =
10552 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10556 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10557 ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10558 ldst.u.i2c.did = devid;
10559 ldst.u.i2c.boffset = offset;
10560 ldst.u.i2c.blen = len;
10561 memcpy(ldst.u.i2c.data, buf, len);
10562 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10566 * t4_sge_ctxt_rd - read an SGE context through FW
10567 * @adap: the adapter
10568 * @mbox: mailbox to use for the FW command
10569 * @cid: the context id
10570 * @ctype: the context type
10571 * @data: where to store the context data
10573 * Issues a FW command through the given mailbox to read an SGE context.
10575 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10576 enum ctxt_type ctype, u32 *data)
10579 struct fw_ldst_cmd c;
10581 if (ctype == CTXT_EGRESS)
10582 ret = FW_LDST_ADDRSPC_SGE_EGRC;
10583 else if (ctype == CTXT_INGRESS)
10584 ret = FW_LDST_ADDRSPC_SGE_INGC;
10585 else if (ctype == CTXT_FLM)
10586 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10588 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10590 memset(&c, 0, sizeof(c));
10591 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10592 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10593 V_FW_LDST_CMD_ADDRSPACE(ret));
10594 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10595 c.u.idctxt.physid = cpu_to_be32(cid);
10597 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10599 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10600 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10601 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10602 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10603 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10604 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10610 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10611 * @adap: the adapter
10612 * @cid: the context id
10613 * @ctype: the context type
10614 * @data: where to store the context data
10616 * Reads an SGE context directly, bypassing FW. This is only for
10617 * debugging when FW is unavailable.
10619 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
10624 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
10625 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
10627 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
10628 *data++ = t4_read_reg(adap, i);
10632 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
10635 struct fw_sched_cmd cmd;
10637 memset(&cmd, 0, sizeof(cmd));
10638 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10641 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10643 cmd.u.config.sc = FW_SCHED_SC_CONFIG;
10644 cmd.u.config.type = type;
10645 cmd.u.config.minmaxen = minmaxen;
10647 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10651 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10652 int rateunit, int ratemode, int channel, int cl,
10653 int minrate, int maxrate, int weight, int pktsize,
10654 int burstsize, int sleep_ok)
10656 struct fw_sched_cmd cmd;
10658 memset(&cmd, 0, sizeof(cmd));
10659 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10662 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10664 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10665 cmd.u.params.type = type;
10666 cmd.u.params.level = level;
10667 cmd.u.params.mode = mode;
10668 cmd.u.params.ch = channel;
10669 cmd.u.params.cl = cl;
10670 cmd.u.params.unit = rateunit;
10671 cmd.u.params.rate = ratemode;
10672 cmd.u.params.min = cpu_to_be32(minrate);
10673 cmd.u.params.max = cpu_to_be32(maxrate);
10674 cmd.u.params.weight = cpu_to_be16(weight);
10675 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10676 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10678 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10682 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
10683 unsigned int maxrate, int sleep_ok)
10685 struct fw_sched_cmd cmd;
10687 memset(&cmd, 0, sizeof(cmd));
10688 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10691 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10693 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10694 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10695 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
10696 cmd.u.params.ch = channel;
10697 cmd.u.params.rate = ratemode; /* REL or ABS */
10698 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */
10700 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10704 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
10705 int weight, int sleep_ok)
10707 struct fw_sched_cmd cmd;
10709 if (weight < 0 || weight > 100)
10712 memset(&cmd, 0, sizeof(cmd));
10713 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10716 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10718 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10719 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10720 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
10721 cmd.u.params.ch = channel;
10722 cmd.u.params.cl = cl;
10723 cmd.u.params.weight = cpu_to_be16(weight);
10725 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10729 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
10730 int mode, unsigned int maxrate, int pktsize, int sleep_ok)
10732 struct fw_sched_cmd cmd;
10734 memset(&cmd, 0, sizeof(cmd));
10735 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10738 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10740 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10741 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10742 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
10743 cmd.u.params.mode = mode;
10744 cmd.u.params.ch = channel;
10745 cmd.u.params.cl = cl;
10746 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
10747 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
10748 cmd.u.params.max = cpu_to_be32(maxrate);
10749 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10751 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10756 * t4_config_watchdog - configure (enable/disable) a watchdog timer
10757 * @adapter: the adapter
10758 * @mbox: mailbox to use for the FW command
10759 * @pf: the PF owning the queue
10760 * @vf: the VF owning the queue
10761 * @timeout: watchdog timeout in ms
10762 * @action: watchdog timer / action
10764 * There are separate watchdog timers for each possible watchdog
10765 * action. Configure one of the watchdog timers by setting a non-zero
10766 * timeout. Disable a watchdog timer by using a timeout of zero.
10768 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
10769 unsigned int pf, unsigned int vf,
10770 unsigned int timeout, unsigned int action)
10772 struct fw_watchdog_cmd wdog;
10773 unsigned int ticks;
10776 * The watchdog command expects a timeout in units of 10ms so we need
10777 * to convert it here (via rounding) and force a minimum of one 10ms
10778 * "tick" if the timeout is non-zero but the conversion results in 0
10781 ticks = (timeout + 5)/10;
10782 if (timeout && !ticks)
10785 memset(&wdog, 0, sizeof wdog);
10786 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
10789 V_FW_PARAMS_CMD_PFN(pf) |
10790 V_FW_PARAMS_CMD_VFN(vf));
10791 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
10792 wdog.timeout = cpu_to_be32(ticks);
10793 wdog.action = cpu_to_be32(action);
10795 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
10798 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
10800 struct fw_devlog_cmd devlog_cmd;
10803 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10804 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10805 F_FW_CMD_REQUEST | F_FW_CMD_READ);
10806 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10807 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10808 sizeof(devlog_cmd), &devlog_cmd);
10812 *level = devlog_cmd.level;
10816 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
10818 struct fw_devlog_cmd devlog_cmd;
10820 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10821 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10824 devlog_cmd.level = level;
10825 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10826 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10827 sizeof(devlog_cmd), &devlog_cmd);