2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/eventhandler.h>
39 #include "t4_regs_values.h"
40 #include "firmware/t4fw_interface.h"
43 #define msleep(x) do { \
47 pause("t4hw", (x) * hz / 1000); \
51 * t4_wait_op_done_val - wait until an operation is completed
52 * @adapter: the adapter performing the operation
53 * @reg: the register to check for completion
54 * @mask: a single-bit field within @reg that indicates completion
55 * @polarity: the value of the field when the operation is completed
56 * @attempts: number of check iterations
57 * @delay: delay in usecs between iterations
58 * @valp: where to store the value of the register at completion time
60 * Wait until an operation is completed by checking a bit in a register
61 * up to @attempts times. If @valp is not NULL the value of the register
62 * at the time it indicated completion is stored there. Returns 0 if the
63 * operation completes and -EAGAIN otherwise.
65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
66 int polarity, int attempts, int delay, u32 *valp)
69 u32 val = t4_read_reg(adapter, reg);
71 if (!!(val & mask) == polarity) {
83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
84 int polarity, int attempts, int delay)
86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
91 * t4_set_reg_field - set a register field to a value
92 * @adapter: the adapter to program
93 * @addr: the register address
94 * @mask: specifies the portion of the register to modify
95 * @val: the new value for the register field
97 * Sets a register field specified by the supplied mask to the
100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
103 u32 v = t4_read_reg(adapter, addr) & ~mask;
105 t4_write_reg(adapter, addr, v | val);
106 (void) t4_read_reg(adapter, addr); /* flush */
110 * t4_read_indirect - read indirectly addressed registers
112 * @addr_reg: register holding the indirect address
113 * @data_reg: register holding the value of the indirect register
114 * @vals: where the read register values are stored
115 * @nregs: how many indirect registers to read
116 * @start_idx: index of first indirect register to read
118 * Reads registers that are accessed indirectly through an address/data
121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
122 unsigned int data_reg, u32 *vals,
123 unsigned int nregs, unsigned int start_idx)
126 t4_write_reg(adap, addr_reg, start_idx);
127 *vals++ = t4_read_reg(adap, data_reg);
133 * t4_write_indirect - write indirectly addressed registers
135 * @addr_reg: register holding the indirect addresses
136 * @data_reg: register holding the value for the indirect registers
137 * @vals: values to write
138 * @nregs: how many indirect registers to write
139 * @start_idx: address of first indirect register to write
141 * Writes a sequential block of registers that are accessed indirectly
142 * through an address/data register pair.
144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
145 unsigned int data_reg, const u32 *vals,
146 unsigned int nregs, unsigned int start_idx)
149 t4_write_reg(adap, addr_reg, start_idx++);
150 t4_write_reg(adap, data_reg, *vals++);
155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
156 * mechanism. This guarantees that we get the real value even if we're
157 * operating within a Virtual Machine and the Hypervisor is trapping our
158 * Configuration Space accesses.
160 * N.B. This routine should only be used as a last resort: the firmware uses
161 * the backdoor registers on a regular basis and we can end up
162 * conflicting with it's uses!
164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
169 if (chip_id(adap) <= CHELSIO_T5)
177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
182 * Configuration Space read. (None of the other fields matter when
183 * F_ENABLE is 0 so a simple register write is easier than a
184 * read-modify-write via t4_set_reg_field().)
186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
192 * t4_report_fw_error - report firmware error
195 * The adapter firmware can indicate error conditions to the host.
196 * If the firmware has indicated an error, print out the reason for
197 * the firmware error.
199 static void t4_report_fw_error(struct adapter *adap)
201 static const char *const reason[] = {
202 "Crash", /* PCIE_FW_EVAL_CRASH */
203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
209 "Reserved", /* reserved */
213 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
214 if (pcie_fw & F_PCIE_FW_ERR) {
215 adap->flags &= ~FW_OK;
216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
218 if (pcie_fw != 0xffffffff)
219 t4_os_dump_devlog(adap);
224 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
229 for ( ; nflit; nflit--, mbox_addr += 8)
230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
234 * Handle a FW assertion reported in a mailbox.
236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
240 asrt->u.assert.filename_0_7,
241 be32_to_cpu(asrt->u.assert.line),
242 be32_to_cpu(asrt->u.assert.x),
243 be32_to_cpu(asrt->u.assert.y));
246 struct port_tx_state {
252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
254 uint32_t rx_pause_reg, tx_frames_reg;
257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
274 read_tx_state_one(sc, i, &tx_state[i]);
278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
280 uint32_t port_ctl_reg;
281 uint64_t tx_frames, rx_pause;
284 for_each_port(sc, i) {
285 rx_pause = tx_state[i].rx_pause;
286 tx_frames = tx_state[i].tx_frames;
287 read_tx_state_one(sc, i, &tx_state[i]); /* update */
290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL);
292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL);
293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
294 rx_pause != tx_state[i].rx_pause &&
295 tx_frames == tx_state[i].tx_frames) {
296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
303 #define X_CIM_PF_NOACCESS 0xeeeeeeee
305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
307 * @mbox: index of the mailbox to use
308 * @cmd: the command to write
309 * @size: command length in bytes
310 * @rpl: where to optionally store the reply
311 * @sleep_ok: if true we may sleep while awaiting command completion
312 * @timeout: time to wait for command to finish before timing out
313 * (negative implies @sleep_ok=false)
315 * Sends the given command to FW through the selected mailbox and waits
316 * for the FW to execute the command. If @rpl is not %NULL it is used to
317 * store the FW's reply to the command. The command and its optional
318 * reply are of the same length. Some FW commands like RESET and
319 * INITIALIZE can take a considerable amount of time to execute.
320 * @sleep_ok determines whether we may sleep while awaiting the response.
321 * If sleeping is allowed we use progressive backoff otherwise we spin.
322 * Note that passing in a negative @timeout is an alternate mechanism
323 * for specifying @sleep_ok=false. This is useful when a higher level
324 * interface allows for specification of @timeout but not @sleep_ok ...
326 * The return value is 0 on success or a negative errno on failure. A
327 * failure can happen either because we are not able to execute the
328 * command or FW executes it but signals an error. In the latter case
329 * the return value is the error code indicated by FW (negated).
331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
332 int size, void *rpl, bool sleep_ok, int timeout)
335 * We delay in small increments at first in an effort to maintain
336 * responsiveness for simple, fast executing commands but then back
337 * off to larger delays to a maximum retry delay.
339 static const int delay[] = {
340 1, 1, 3, 5, 10, 10, 20, 50, 100
344 int i, ms, delay_idx, ret, next_tx_check;
345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
348 __be64 cmd_rpl[MBOX_LEN/8];
350 struct port_tx_state tx_state[MAX_NPORTS];
352 if (adap->flags & CHK_MBOX_ACCESS)
353 ASSERT_SYNCHRONIZED_OP(adap);
355 if (size <= 0 || (size & 15) || size > MBOX_LEN)
358 if (adap->flags & IS_VF) {
360 data_reg = FW_T6VF_MBDATA_BASE_ADDR;
362 data_reg = FW_T4VF_MBDATA_BASE_ADDR;
363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
367 * If we have a negative timeout, that implies that we can't sleep.
375 * Attempt to gain access to the mailbox.
377 for (i = 0; i < 4; i++) {
378 ctl = t4_read_reg(adap, ctl_reg);
380 if (v != X_MBOWNER_NONE)
385 * If we were unable to gain access, report the error to our caller.
387 if (v != X_MBOWNER_PL) {
388 t4_report_fw_error(adap);
389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
394 * If we gain ownership of the mailbox and there's a "valid" message
395 * in it, this is likely an asynchronous error message from the
396 * firmware. So we'll report that and then proceed on with attempting
397 * to issue our own command ... which may well fail if the error
398 * presaged the firmware crashing ...
400 if (ctl & F_MBMSGVALID) {
401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
405 * Copy in the new mailbox command and send it on its way ...
407 memset(cmd_rpl, 0, sizeof(cmd_rpl));
408 memcpy(cmd_rpl, cmd, size);
409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
413 if (adap->flags & IS_VF) {
415 * For the VFs, the Mailbox Data "registers" are
416 * actually backed by T4's "MA" interface rather than
417 * PL Registers (as is the case for the PFs). Because
418 * these are in different coherency domains, the write
419 * to the VF's PL-register-backed Mailbox Control can
420 * race in front of the writes to the MA-backed VF
421 * Mailbox Data "registers". So we need to do a
422 * read-back on at least one byte of the VF Mailbox
423 * Data registers before doing the write to the VF
424 * Mailbox Control register.
426 t4_read_reg(adap, data_reg);
429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
431 next_tx_check = 1000;
436 * Loop waiting for the reply; bail out if we time out or the firmware
440 for (i = 0; i < timeout; i += ms) {
441 if (!(adap->flags & IS_VF)) {
442 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
443 if (pcie_fw & F_PCIE_FW_ERR)
447 if (i >= next_tx_check) {
448 check_tx_state(adap, &tx_state[0]);
449 next_tx_check = i + 1000;
453 ms = delay[delay_idx]; /* last element may repeat */
454 if (delay_idx < ARRAY_SIZE(delay) - 1)
461 v = t4_read_reg(adap, ctl_reg);
462 if (v == X_CIM_PF_NOACCESS)
464 if (G_MBOWNER(v) == X_MBOWNER_PL) {
465 if (!(v & F_MBMSGVALID)) {
466 t4_write_reg(adap, ctl_reg,
467 V_MBOWNER(X_MBOWNER_NONE));
472 * Retrieve the command reply and release the mailbox.
474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
478 res = be64_to_cpu(cmd_rpl[0]);
479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
481 res = V_FW_CMD_RETVAL(EIO);
483 memcpy(rpl, cmd_rpl, size);
484 return -G_FW_CMD_RETVAL((int)res);
489 * We timed out waiting for a reply to our mailbox command. Report
490 * the error and also check to see if the firmware reported any
493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
494 *(const u8 *)cmd, mbox, pcie_fw);
495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
498 if (pcie_fw & F_PCIE_FW_ERR) {
500 t4_report_fw_error(adap);
503 t4_os_dump_devlog(adap);
506 t4_fatal_err(adap, true);
510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
511 void *rpl, bool sleep_ok)
513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
514 sleep_ok, FW_CMD_MAX_TIMEOUT);
518 static int t4_edc_err_read(struct adapter *adap, int idx)
520 u32 edc_ecc_err_addr_reg;
521 u32 edc_bist_status_rdata_reg;
524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
527 if (idx != MEM_EDC0 && idx != MEM_EDC1) {
528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
536 "edc%d err addr 0x%x: 0x%x.\n",
537 idx, edc_ecc_err_addr_reg,
538 t4_read_reg(adap, edc_ecc_err_addr_reg));
540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
541 edc_bist_status_rdata_reg,
542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
556 * t4_mc_read - read from MC through backdoor accesses
558 * @idx: which MC to access
559 * @addr: address of first byte requested
560 * @data: 64 bytes of data containing the requested address
561 * @ecc: where to store the corresponding 64-bit ECC word
563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
564 * that covers the requested address @addr. If @parity is not %NULL it
565 * is assigned the 64-bit ECC word for the read data.
567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
574 mc_bist_cmd_reg = A_MC_BIST_CMD;
575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
595 F_START_BIST | V_BIST_CMD_GAP(1));
596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
602 for (i = 15; i >= 0; i--)
603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
605 *ecc = t4_read_reg64(adap, MC_DATA(16));
611 * t4_edc_read - read from EDC through backdoor accesses
613 * @idx: which EDC to access
614 * @addr: address of first byte requested
615 * @data: 64 bytes of data containing the requested address
616 * @ecc: where to store the corresponding 64-bit ECC word
618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
619 * that covers the requested address @addr. If @parity is not %NULL it
620 * is assigned the 64-bit ECC word for the read data.
622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
638 * These macro are missing in t4_regs.h file.
639 * Added temporarily for testing.
641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
659 t4_write_reg(adap, edc_bist_cmd_reg,
660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
667 for (i = 15; i >= 0; i--)
668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
670 *ecc = t4_read_reg64(adap, EDC_DATA(16));
676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
679 * @addr: address within indicated memory type
680 * @len: amount of memory to read
681 * @buf: host memory buffer
683 * Reads an [almost] arbitrary memory region in the firmware: the
684 * firmware memory address, length and host buffer must be aligned on
685 * 32-bit boudaries. The memory is returned as a raw byte sequence from
686 * the firmware's memory. If this memory contains data structures which
687 * contain multi-byte integers, it's the callers responsibility to
688 * perform appropriate byte order conversions.
690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
693 u32 pos, start, end, offset;
697 * Argument sanity checks ...
699 if ((addr & 0x3) || (len & 0x3))
703 * The underlaying EDC/MC read routines read 64 bytes at a time so we
704 * need to round down the start and round up the end. We'll start
705 * copying out of the first line at (addr - start) a word at a time.
707 start = rounddown2(addr, 64);
708 end = roundup2(addr + len, 64);
709 offset = (addr - start)/sizeof(__be32);
711 for (pos = start; pos < end; pos += 64, offset = 0) {
715 * Read the chip's memory block and bail if there's an error.
717 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
720 ret = t4_edc_read(adap, mtype, pos, data, NULL);
725 * Copy the data into the caller's memory buffer.
727 while (offset < 16 && len > 0) {
728 *buf++ = data[offset++];
729 len -= sizeof(__be32);
737 * Return the specified PCI-E Configuration Space register from our Physical
738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
739 * since we prefer to let the firmware own all of these registers, but if that
740 * fails we go for it directly ourselves.
742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
746 * If fw_attach != 0, construct and send the Firmware LDST Command to
747 * retrieve the specified PCI-E Configuration Space register.
749 if (drv_fw_attach != 0) {
750 struct fw_ldst_cmd ldst_cmd;
753 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
754 ldst_cmd.op_to_addrspace =
755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
761 ldst_cmd.u.pcie.ctrl_to_fn =
762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
763 ldst_cmd.u.pcie.r = reg;
766 * If the LDST Command succeeds, return the result, otherwise
767 * fall through to reading it directly ourselves ...
769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
774 CH_WARN(adap, "Firmware failed to return "
775 "Configuration Space register %d, err = %d\n",
780 * Read the desired Configuration Space register via the PCI-E
781 * Backdoor mechanism.
783 return t4_hw_pci_read_cfg4(adap, reg);
787 * t4_get_regs_len - return the size of the chips register set
788 * @adapter: the adapter
790 * Returns the size of the chip's BAR0 register space.
792 unsigned int t4_get_regs_len(struct adapter *adapter)
794 unsigned int chip_version = chip_id(adapter);
796 switch (chip_version) {
798 if (adapter->flags & IS_VF)
799 return FW_T4VF_REGMAP_SIZE;
800 return T4_REGMAP_SIZE;
804 if (adapter->flags & IS_VF)
805 return FW_T4VF_REGMAP_SIZE;
806 return T5_REGMAP_SIZE;
810 "Unsupported chip version %d\n", chip_version);
815 * t4_get_regs - read chip registers into provided buffer
817 * @buf: register buffer
818 * @buf_size: size (in bytes) of register buffer
820 * If the provided register buffer isn't large enough for the chip's
821 * full register range, the register dump will be truncated to the
822 * register buffer's size.
824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
826 static const unsigned int t4_reg_ranges[] = {
1285 static const unsigned int t4vf_reg_ranges[] = {
1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1287 VF_MPS_REG(A_MPS_VF_CTL),
1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1292 FW_T4VF_MBDATA_BASE_ADDR,
1293 FW_T4VF_MBDATA_BASE_ADDR +
1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1297 static const unsigned int t5_reg_ranges[] = {
2064 static const unsigned int t5vf_reg_ranges[] = {
2065 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2066 VF_MPS_REG(A_MPS_VF_CTL),
2067 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2068 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2069 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2070 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2071 FW_T4VF_MBDATA_BASE_ADDR,
2072 FW_T4VF_MBDATA_BASE_ADDR +
2073 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2076 static const unsigned int t6_reg_ranges[] = {
2637 static const unsigned int t6vf_reg_ranges[] = {
2638 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2639 VF_MPS_REG(A_MPS_VF_CTL),
2640 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2641 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2642 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2643 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2644 FW_T6VF_MBDATA_BASE_ADDR,
2645 FW_T6VF_MBDATA_BASE_ADDR +
2646 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2649 u32 *buf_end = (u32 *)(buf + buf_size);
2650 const unsigned int *reg_ranges;
2651 int reg_ranges_size, range;
2652 unsigned int chip_version = chip_id(adap);
2655 * Select the right set of register ranges to dump depending on the
2656 * adapter chip type.
2658 switch (chip_version) {
2660 if (adap->flags & IS_VF) {
2661 reg_ranges = t4vf_reg_ranges;
2662 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2664 reg_ranges = t4_reg_ranges;
2665 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2670 if (adap->flags & IS_VF) {
2671 reg_ranges = t5vf_reg_ranges;
2672 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2674 reg_ranges = t5_reg_ranges;
2675 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2680 if (adap->flags & IS_VF) {
2681 reg_ranges = t6vf_reg_ranges;
2682 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2684 reg_ranges = t6_reg_ranges;
2685 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2691 "Unsupported chip version %d\n", chip_version);
2696 * Clear the register buffer and insert the appropriate register
2697 * values selected by the above register ranges.
2699 memset(buf, 0, buf_size);
2700 for (range = 0; range < reg_ranges_size; range += 2) {
2701 unsigned int reg = reg_ranges[range];
2702 unsigned int last_reg = reg_ranges[range + 1];
2703 u32 *bufp = (u32 *)(buf + reg);
2706 * Iterate across the register range filling in the register
2707 * buffer but don't write past the end of the register buffer.
2709 while (reg <= last_reg && bufp < buf_end) {
2710 *bufp++ = t4_read_reg(adap, reg);
2717 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID
2718 * header followed by one or more VPD-R sections, each with its own header.
2726 struct t4_vpdr_hdr {
2732 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2734 #define EEPROM_DELAY 10 /* 10us per poll spin */
2735 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
2737 #define EEPROM_STAT_ADDR 0x7bfc
2738 #define VPD_SIZE 0x800
2739 #define VPD_BASE 0x400
2740 #define VPD_BASE_OLD 0
2741 #define VPD_LEN 1024
2742 #define VPD_INFO_FLD_HDR_SIZE 3
2743 #define CHELSIO_VPD_UNIQUE_ID 0x82
2746 * Small utility function to wait till any outstanding VPD Access is complete.
2747 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2748 * VPD Access in flight. This allows us to handle the problem of having a
2749 * previous VPD Access time out and prevent an attempt to inject a new VPD
2750 * Request before any in-flight VPD reguest has completed.
2752 static int t4_seeprom_wait(struct adapter *adapter)
2754 unsigned int base = adapter->params.pci.vpd_cap_addr;
2758 * If no VPD Access is in flight, we can just return success right
2761 if (!adapter->vpd_busy)
2765 * Poll the VPD Capability Address/Flag register waiting for it
2766 * to indicate that the operation is complete.
2768 max_poll = EEPROM_MAX_POLL;
2772 udelay(EEPROM_DELAY);
2773 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2776 * If the operation is complete, mark the VPD as no longer
2777 * busy and return success.
2779 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2780 adapter->vpd_busy = 0;
2783 } while (--max_poll);
2786 * Failure! Note that we leave the VPD Busy status set in order to
2787 * avoid pushing a new VPD Access request into the VPD Capability till
2788 * the current operation eventually succeeds. It's a bug to issue a
2789 * new request when an existing request is in flight and will result
2790 * in corrupt hardware state.
2796 * t4_seeprom_read - read a serial EEPROM location
2797 * @adapter: adapter to read
2798 * @addr: EEPROM virtual address
2799 * @data: where to store the read data
2801 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2802 * VPD capability. Note that this function must be called with a virtual
2805 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2807 unsigned int base = adapter->params.pci.vpd_cap_addr;
2811 * VPD Accesses must alway be 4-byte aligned!
2813 if (addr >= EEPROMVSIZE || (addr & 3))
2817 * Wait for any previous operation which may still be in flight to
2820 ret = t4_seeprom_wait(adapter);
2822 CH_ERR(adapter, "VPD still busy from previous operation\n");
2827 * Issue our new VPD Read request, mark the VPD as being busy and wait
2828 * for our request to complete. If it doesn't complete, note the
2829 * error and return it to our caller. Note that we do not reset the
2832 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2833 adapter->vpd_busy = 1;
2834 adapter->vpd_flag = PCI_VPD_ADDR_F;
2835 ret = t4_seeprom_wait(adapter);
2837 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2842 * Grab the returned data, swizzle it into our endianness and
2845 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2846 *data = le32_to_cpu(*data);
2851 * t4_seeprom_write - write a serial EEPROM location
2852 * @adapter: adapter to write
2853 * @addr: virtual EEPROM address
2854 * @data: value to write
2856 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2857 * VPD capability. Note that this function must be called with a virtual
2860 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2862 unsigned int base = adapter->params.pci.vpd_cap_addr;
2868 * VPD Accesses must alway be 4-byte aligned!
2870 if (addr >= EEPROMVSIZE || (addr & 3))
2874 * Wait for any previous operation which may still be in flight to
2877 ret = t4_seeprom_wait(adapter);
2879 CH_ERR(adapter, "VPD still busy from previous operation\n");
2884 * Issue our new VPD Read request, mark the VPD as being busy and wait
2885 * for our request to complete. If it doesn't complete, note the
2886 * error and return it to our caller. Note that we do not reset the
2889 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2891 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2892 (u16)addr | PCI_VPD_ADDR_F);
2893 adapter->vpd_busy = 1;
2894 adapter->vpd_flag = 0;
2895 ret = t4_seeprom_wait(adapter);
2897 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2902 * Reset PCI_VPD_DATA register after a transaction and wait for our
2903 * request to complete. If it doesn't complete, return error.
2905 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2906 max_poll = EEPROM_MAX_POLL;
2908 udelay(EEPROM_DELAY);
2909 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2910 } while ((stats_reg & 0x1) && --max_poll);
2914 /* Return success! */
2919 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2920 * @phys_addr: the physical EEPROM address
2921 * @fn: the PCI function number
2922 * @sz: size of function-specific area
2924 * Translate a physical EEPROM address to virtual. The first 1K is
2925 * accessed through virtual addresses starting at 31K, the rest is
2926 * accessed through virtual addresses starting at 0.
2928 * The mapping is as follows:
2929 * [0..1K) -> [31K..32K)
2930 * [1K..1K+A) -> [ES-A..ES)
2931 * [1K+A..ES) -> [0..ES-A-1K)
2933 * where A = @fn * @sz, and ES = EEPROM size.
2935 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2938 if (phys_addr < 1024)
2939 return phys_addr + (31 << 10);
2940 if (phys_addr < 1024 + fn)
2941 return EEPROMSIZE - fn + phys_addr - 1024;
2942 if (phys_addr < EEPROMSIZE)
2943 return phys_addr - 1024 - fn;
2948 * t4_seeprom_wp - enable/disable EEPROM write protection
2949 * @adapter: the adapter
2950 * @enable: whether to enable or disable write protection
2952 * Enables or disables write protection on the serial EEPROM.
2954 int t4_seeprom_wp(struct adapter *adapter, int enable)
2956 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2960 * get_vpd_keyword_val - Locates an information field keyword in the VPD
2961 * @vpd: Pointer to buffered vpd data structure
2962 * @kw: The keyword to search for
2963 * @region: VPD region to search (starting from 0)
2965 * Returns the value of the information field keyword or
2966 * -ENOENT otherwise.
2968 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2971 unsigned int offset, len;
2972 const struct t4_vpdr_hdr *vpdr;
2974 offset = sizeof(struct t4_vpd_hdr);
2975 vpdr = (const void *)(vpd + offset);
2976 tag = vpdr->vpdr_tag;
2977 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2979 offset += sizeof(struct t4_vpdr_hdr) + len;
2980 vpdr = (const void *)(vpd + offset);
2981 if (++tag != vpdr->vpdr_tag)
2983 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2985 offset += sizeof(struct t4_vpdr_hdr);
2987 if (offset + len > VPD_LEN) {
2991 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2992 if (memcmp(vpd + i , kw , 2) == 0){
2993 i += VPD_INFO_FLD_HDR_SIZE;
2997 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
3005 * get_vpd_params - read VPD parameters from VPD EEPROM
3006 * @adapter: adapter to read
3007 * @p: where to store the parameters
3008 * @vpd: caller provided temporary space to read the VPD into
3010 * Reads card parameters stored in VPD EEPROM.
3012 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3013 uint16_t device_id, u32 *buf)
3016 int ec, sn, pn, na, md;
3018 const u8 *vpd = (const u8 *)buf;
3021 * Card information normally starts at VPD_BASE but early cards had
3024 ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3029 * The VPD shall have a unique identifier specified by the PCI SIG.
3030 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3031 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3032 * is expected to automatically put this entry at the
3033 * beginning of the VPD.
3035 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3037 for (i = 0; i < VPD_LEN; i += 4) {
3038 ret = t4_seeprom_read(adapter, addr + i, buf++);
3043 #define FIND_VPD_KW(var,name) do { \
3044 var = get_vpd_keyword_val(vpd, name, 0); \
3046 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3051 FIND_VPD_KW(i, "RV");
3052 for (csum = 0; i >= 0; i--)
3057 "corrupted VPD EEPROM, actual csum %u\n", csum);
3061 FIND_VPD_KW(ec, "EC");
3062 FIND_VPD_KW(sn, "SN");
3063 FIND_VPD_KW(pn, "PN");
3064 FIND_VPD_KW(na, "NA");
3067 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3069 memcpy(p->ec, vpd + ec, EC_LEN);
3071 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3072 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3074 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3075 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3076 strstrip((char *)p->pn);
3077 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3078 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3079 strstrip((char *)p->na);
3081 if (device_id & 0x80)
3082 return 0; /* Custom card */
3084 md = get_vpd_keyword_val(vpd, "VF", 1);
3086 snprintf(p->md, sizeof(p->md), "unknown");
3088 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3089 memcpy(p->md, vpd + md, min(i, MD_LEN));
3090 strstrip((char *)p->md);
3096 /* serial flash and firmware constants and flash config file constants */
3098 SF_ATTEMPTS = 10, /* max retries for SF operations */
3100 /* flash command opcodes */
3101 SF_PROG_PAGE = 2, /* program 256B page */
3102 SF_WR_DISABLE = 4, /* disable writes */
3103 SF_RD_STATUS = 5, /* read status register */
3104 SF_WR_ENABLE = 6, /* enable writes */
3105 SF_RD_DATA_FAST = 0xb, /* read flash */
3106 SF_RD_ID = 0x9f, /* read ID */
3107 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3111 * sf1_read - read data from the serial flash
3112 * @adapter: the adapter
3113 * @byte_cnt: number of bytes to read
3114 * @cont: whether another operation will be chained
3115 * @lock: whether to lock SF for PL access only
3116 * @valp: where to store the read data
3118 * Reads up to 4 bytes of data from the serial flash. The location of
3119 * the read needs to be specified prior to calling this by issuing the
3120 * appropriate commands to the serial flash.
3122 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3123 int lock, u32 *valp)
3127 if (!byte_cnt || byte_cnt > 4)
3129 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3131 t4_write_reg(adapter, A_SF_OP,
3132 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3133 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3135 *valp = t4_read_reg(adapter, A_SF_DATA);
3140 * sf1_write - write data to the serial flash
3141 * @adapter: the adapter
3142 * @byte_cnt: number of bytes to write
3143 * @cont: whether another operation will be chained
3144 * @lock: whether to lock SF for PL access only
3145 * @val: value to write
3147 * Writes up to 4 bytes of data to the serial flash. The location of
3148 * the write needs to be specified prior to calling this by issuing the
3149 * appropriate commands to the serial flash.
3151 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3154 if (!byte_cnt || byte_cnt > 4)
3156 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3158 t4_write_reg(adapter, A_SF_DATA, val);
3159 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3160 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3161 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3165 * flash_wait_op - wait for a flash operation to complete
3166 * @adapter: the adapter
3167 * @attempts: max number of polls of the status register
3168 * @delay: delay between polls in ms
3170 * Wait for a flash operation to complete by polling the status register.
3172 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3178 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3179 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3183 if (--attempts == 0)
3191 * t4_read_flash - read words from serial flash
3192 * @adapter: the adapter
3193 * @addr: the start address for the read
3194 * @nwords: how many 32-bit words to read
3195 * @data: where to store the read data
3196 * @byte_oriented: whether to store data as bytes or as words
3198 * Read the specified number of 32-bit words from the serial flash.
3199 * If @byte_oriented is set the read data is stored as a byte array
3200 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3201 * natural endianness.
3203 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3204 unsigned int nwords, u32 *data, int byte_oriented)
3208 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3211 addr = swab32(addr) | SF_RD_DATA_FAST;
3213 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3214 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3217 for ( ; nwords; nwords--, data++) {
3218 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3220 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3224 *data = (__force __u32)(cpu_to_be32(*data));
3230 * t4_write_flash - write up to a page of data to the serial flash
3231 * @adapter: the adapter
3232 * @addr: the start address to write
3233 * @n: length of data to write in bytes
3234 * @data: the data to write
3235 * @byte_oriented: whether to store data as bytes or as words
3237 * Writes up to a page of data (256 bytes) to the serial flash starting
3238 * at the given address. All the data must be written to the same page.
3239 * If @byte_oriented is set the write data is stored as byte stream
3240 * (i.e. matches what on disk), otherwise in big-endian.
3242 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3243 unsigned int n, const u8 *data, int byte_oriented)
3246 u32 buf[SF_PAGE_SIZE / 4];
3247 unsigned int i, c, left, val, offset = addr & 0xff;
3249 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3252 val = swab32(addr) | SF_PROG_PAGE;
3254 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3255 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3258 for (left = n; left; left -= c) {
3260 for (val = 0, i = 0; i < c; ++i)
3261 val = (val << 8) + *data++;
3264 val = cpu_to_be32(val);
3266 ret = sf1_write(adapter, c, c != left, 1, val);
3270 ret = flash_wait_op(adapter, 8, 1);
3274 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3276 /* Read the page to verify the write succeeded */
3277 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3282 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3284 "failed to correctly write the flash page at %#x\n",
3291 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3296 * t4_get_fw_version - read the firmware version
3297 * @adapter: the adapter
3298 * @vers: where to place the version
3300 * Reads the FW version from flash.
3302 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3304 return t4_read_flash(adapter, FLASH_FW_START +
3305 offsetof(struct fw_hdr, fw_ver), 1,
3310 * t4_get_fw_hdr - read the firmware header
3311 * @adapter: the adapter
3312 * @hdr: where to place the version
3314 * Reads the FW header from flash into caller provided buffer.
3316 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3318 return t4_read_flash(adapter, FLASH_FW_START,
3319 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3323 * t4_get_bs_version - read the firmware bootstrap version
3324 * @adapter: the adapter
3325 * @vers: where to place the version
3327 * Reads the FW Bootstrap version from flash.
3329 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3331 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3332 offsetof(struct fw_hdr, fw_ver), 1,
3337 * t4_get_tp_version - read the TP microcode version
3338 * @adapter: the adapter
3339 * @vers: where to place the version
3341 * Reads the TP microcode version from flash.
3343 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3345 return t4_read_flash(adapter, FLASH_FW_START +
3346 offsetof(struct fw_hdr, tp_microcode_ver),
3351 * t4_get_exprom_version - return the Expansion ROM version (if any)
3352 * @adapter: the adapter
3353 * @vers: where to place the version
3355 * Reads the Expansion ROM header from FLASH and returns the version
3356 * number (if present) through the @vers return value pointer. We return
3357 * this in the Firmware Version Format since it's convenient. Return
3358 * 0 on success, -ENOENT if no Expansion ROM is present.
3360 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3362 struct exprom_header {
3363 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3364 unsigned char hdr_ver[4]; /* Expansion ROM version */
3366 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3370 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3371 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3376 hdr = (struct exprom_header *)exprom_header_buf;
3377 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3380 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3381 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3382 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3383 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3388 * t4_get_scfg_version - return the Serial Configuration version
3389 * @adapter: the adapter
3390 * @vers: where to place the version
3392 * Reads the Serial Configuration Version via the Firmware interface
3393 * (thus this can only be called once we're ready to issue Firmware
3394 * commands). The format of the Serial Configuration version is
3395 * adapter specific. Returns 0 on success, an error on failure.
3397 * Note that early versions of the Firmware didn't include the ability
3398 * to retrieve the Serial Configuration version, so we zero-out the
3399 * return-value parameter in that case to avoid leaving it with
3402 * Also note that the Firmware will return its cached copy of the Serial
3403 * Initialization Revision ID, not the actual Revision ID as written in
3404 * the Serial EEPROM. This is only an issue if a new VPD has been written
3405 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3406 * it's best to defer calling this routine till after a FW_RESET_CMD has
3407 * been issued if the Host Driver will be performing a full adapter
3410 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3415 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3416 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3417 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3418 1, &scfgrev_param, vers);
3425 * t4_get_vpd_version - return the VPD version
3426 * @adapter: the adapter
3427 * @vers: where to place the version
3429 * Reads the VPD via the Firmware interface (thus this can only be called
3430 * once we're ready to issue Firmware commands). The format of the
3431 * VPD version is adapter specific. Returns 0 on success, an error on
3434 * Note that early versions of the Firmware didn't include the ability
3435 * to retrieve the VPD version, so we zero-out the return-value parameter
3436 * in that case to avoid leaving it with garbage in it.
3438 * Also note that the Firmware will return its cached copy of the VPD
3439 * Revision ID, not the actual Revision ID as written in the Serial
3440 * EEPROM. This is only an issue if a new VPD has been written and the
3441 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3442 * to defer calling this routine till after a FW_RESET_CMD has been issued
3443 * if the Host Driver will be performing a full adapter initialization.
3445 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3450 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3451 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3452 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3453 1, &vpdrev_param, vers);
3460 * t4_get_version_info - extract various chip/firmware version information
3461 * @adapter: the adapter
3463 * Reads various chip/firmware version numbers and stores them into the
3464 * adapter Adapter Parameters structure. If any of the efforts fails
3465 * the first failure will be returned, but all of the version numbers
3468 int t4_get_version_info(struct adapter *adapter)
3472 #define FIRST_RET(__getvinfo) \
3474 int __ret = __getvinfo; \
3475 if (__ret && !ret) \
3479 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3480 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3481 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3482 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3483 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3484 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3492 * t4_flash_erase_sectors - erase a range of flash sectors
3493 * @adapter: the adapter
3494 * @start: the first sector to erase
3495 * @end: the last sector to erase
3497 * Erases the sectors in the given inclusive range.
3499 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3503 if (end >= adapter->params.sf_nsec)
3506 while (start <= end) {
3507 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3508 (ret = sf1_write(adapter, 4, 0, 1,
3509 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3510 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3512 "erase of flash sector %d failed, error %d\n",
3518 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3523 * t4_flash_cfg_addr - return the address of the flash configuration file
3524 * @adapter: the adapter
3526 * Return the address within the flash where the Firmware Configuration
3527 * File is stored, or an error if the device FLASH is too small to contain
3528 * a Firmware Configuration File.
3530 int t4_flash_cfg_addr(struct adapter *adapter)
3533 * If the device FLASH isn't large enough to hold a Firmware
3534 * Configuration File, return an error.
3536 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3539 return FLASH_CFG_START;
3543 * Return TRUE if the specified firmware matches the adapter. I.e. T4
3544 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3545 * and emit an error message for mismatched firmware to save our caller the
3548 static int t4_fw_matches_chip(struct adapter *adap,
3549 const struct fw_hdr *hdr)
3552 * The expression below will return FALSE for any unsupported adapter
3553 * which will keep us "honest" in the future ...
3555 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3556 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3557 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3561 "FW image (%d) is not suitable for this adapter (%d)\n",
3562 hdr->chip, chip_id(adap));
3567 * t4_load_fw - download firmware
3568 * @adap: the adapter
3569 * @fw_data: the firmware image to write
3572 * Write the supplied firmware image to the card's serial flash.
3574 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3579 u8 first_page[SF_PAGE_SIZE];
3580 const u32 *p = (const u32 *)fw_data;
3581 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3582 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3583 unsigned int fw_start_sec;
3584 unsigned int fw_start;
3585 unsigned int fw_size;
3587 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3588 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3589 fw_start = FLASH_FWBOOTSTRAP_START;
3590 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3592 fw_start_sec = FLASH_FW_START_SEC;
3593 fw_start = FLASH_FW_START;
3594 fw_size = FLASH_FW_MAX_SIZE;
3598 CH_ERR(adap, "FW image has no data\n");
3603 "FW image size not multiple of 512 bytes\n");
3606 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3608 "FW image size differs from size in FW header\n");
3611 if (size > fw_size) {
3612 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3616 if (!t4_fw_matches_chip(adap, hdr))
3619 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3620 csum += be32_to_cpu(p[i]);
3622 if (csum != 0xffffffff) {
3624 "corrupted firmware image, checksum %#x\n", csum);
3628 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3629 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3634 * We write the correct version at the end so the driver can see a bad
3635 * version if the FW write fails. Start by writing a copy of the
3636 * first page with a bad version.
3638 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3639 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3640 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3645 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3646 addr += SF_PAGE_SIZE;
3647 fw_data += SF_PAGE_SIZE;
3648 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3653 ret = t4_write_flash(adap,
3654 fw_start + offsetof(struct fw_hdr, fw_ver),
3655 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3658 CH_ERR(adap, "firmware download failed, error %d\n",
3664 * t4_fwcache - firmware cache operation
3665 * @adap: the adapter
3666 * @op : the operation (flush or flush and invalidate)
3668 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3670 struct fw_params_cmd c;
3672 memset(&c, 0, sizeof(c));
3674 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3675 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3676 V_FW_PARAMS_CMD_PFN(adap->pf) |
3677 V_FW_PARAMS_CMD_VFN(0));
3678 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3680 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3681 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3682 c.param[0].val = (__force __be32)op;
3684 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3687 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3688 unsigned int *pif_req_wrptr,
3689 unsigned int *pif_rsp_wrptr)
3692 u32 cfg, val, req, rsp;
3694 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3695 if (cfg & F_LADBGEN)
3696 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3698 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3699 req = G_POLADBGWRPTR(val);
3700 rsp = G_PILADBGWRPTR(val);
3702 *pif_req_wrptr = req;
3704 *pif_rsp_wrptr = rsp;
3706 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3707 for (j = 0; j < 6; j++) {
3708 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3709 V_PILADBGRDPTR(rsp));
3710 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3711 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3715 req = (req + 2) & M_POLADBGRDPTR;
3716 rsp = (rsp + 2) & M_PILADBGRDPTR;
3718 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3721 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3726 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3727 if (cfg & F_LADBGEN)
3728 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3730 for (i = 0; i < CIM_MALA_SIZE; i++) {
3731 for (j = 0; j < 5; j++) {
3733 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3734 V_PILADBGRDPTR(idx));
3735 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3736 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3739 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3742 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3746 for (i = 0; i < 8; i++) {
3747 u32 *p = la_buf + i;
3749 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3750 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3751 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3752 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3753 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3758 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3759 * @caps16: a 16-bit Port Capabilities value
3761 * Returns the equivalent 32-bit Port Capabilities value.
3763 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3765 uint32_t caps32 = 0;
3767 #define CAP16_TO_CAP32(__cap) \
3769 if (caps16 & FW_PORT_CAP_##__cap) \
3770 caps32 |= FW_PORT_CAP32_##__cap; \
3773 CAP16_TO_CAP32(SPEED_100M);
3774 CAP16_TO_CAP32(SPEED_1G);
3775 CAP16_TO_CAP32(SPEED_25G);
3776 CAP16_TO_CAP32(SPEED_10G);
3777 CAP16_TO_CAP32(SPEED_40G);
3778 CAP16_TO_CAP32(SPEED_100G);
3779 CAP16_TO_CAP32(FC_RX);
3780 CAP16_TO_CAP32(FC_TX);
3781 CAP16_TO_CAP32(ANEG);
3782 CAP16_TO_CAP32(FORCE_PAUSE);
3783 CAP16_TO_CAP32(MDIAUTO);
3784 CAP16_TO_CAP32(MDISTRAIGHT);
3785 CAP16_TO_CAP32(FEC_RS);
3786 CAP16_TO_CAP32(FEC_BASER_RS);
3787 CAP16_TO_CAP32(802_3_PAUSE);
3788 CAP16_TO_CAP32(802_3_ASM_DIR);
3790 #undef CAP16_TO_CAP32
3796 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3797 * @caps32: a 32-bit Port Capabilities value
3799 * Returns the equivalent 16-bit Port Capabilities value. Note that
3800 * not all 32-bit Port Capabilities can be represented in the 16-bit
3801 * Port Capabilities and some fields/values may not make it.
3803 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3805 uint16_t caps16 = 0;
3807 #define CAP32_TO_CAP16(__cap) \
3809 if (caps32 & FW_PORT_CAP32_##__cap) \
3810 caps16 |= FW_PORT_CAP_##__cap; \
3813 CAP32_TO_CAP16(SPEED_100M);
3814 CAP32_TO_CAP16(SPEED_1G);
3815 CAP32_TO_CAP16(SPEED_10G);
3816 CAP32_TO_CAP16(SPEED_25G);
3817 CAP32_TO_CAP16(SPEED_40G);
3818 CAP32_TO_CAP16(SPEED_100G);
3819 CAP32_TO_CAP16(FC_RX);
3820 CAP32_TO_CAP16(FC_TX);
3821 CAP32_TO_CAP16(802_3_PAUSE);
3822 CAP32_TO_CAP16(802_3_ASM_DIR);
3823 CAP32_TO_CAP16(ANEG);
3824 CAP32_TO_CAP16(FORCE_PAUSE);
3825 CAP32_TO_CAP16(MDIAUTO);
3826 CAP32_TO_CAP16(MDISTRAIGHT);
3827 CAP32_TO_CAP16(FEC_RS);
3828 CAP32_TO_CAP16(FEC_BASER_RS);
3830 #undef CAP32_TO_CAP16
3836 is_bt(struct port_info *pi)
3839 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
3840 pi->port_type == FW_PORT_TYPE_BT_XFI ||
3841 pi->port_type == FW_PORT_TYPE_BT_XAUI);
3845 * t4_link_l1cfg - apply link configuration to MAC/PHY
3846 * @phy: the PHY to setup
3847 * @mac: the MAC to setup
3848 * @lc: the requested link configuration
3850 * Set up a port's MAC and PHY according to a desired link configuration.
3851 * - If the PHY can auto-negotiate first decide what to advertise, then
3852 * enable/disable auto-negotiation as desired, and reset.
3853 * - If the PHY does not auto-negotiate just reset it.
3854 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3855 * otherwise do it later based on the outcome of auto-negotiation.
3857 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3858 struct link_config *lc)
3860 struct fw_port_cmd c;
3861 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3862 unsigned int aneg, fc, fec, speed, rcap;
3865 if (lc->requested_fc & PAUSE_RX)
3866 fc |= FW_PORT_CAP32_FC_RX;
3867 if (lc->requested_fc & PAUSE_TX)
3868 fc |= FW_PORT_CAP32_FC_TX;
3869 if (!(lc->requested_fc & PAUSE_AUTONEG))
3870 fc |= FW_PORT_CAP32_FORCE_PAUSE;
3873 if (lc->requested_fec == FEC_AUTO)
3876 if (lc->requested_fec & FEC_RS)
3877 fec |= FW_PORT_CAP32_FEC_RS;
3878 if (lc->requested_fec & FEC_BASER_RS)
3879 fec |= FW_PORT_CAP32_FEC_BASER_RS;
3882 if (lc->requested_aneg == AUTONEG_DISABLE)
3884 else if (lc->requested_aneg == AUTONEG_ENABLE)
3885 aneg = FW_PORT_CAP32_ANEG;
3887 aneg = lc->supported & FW_PORT_CAP32_ANEG;
3890 speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3891 } else if (lc->requested_speed != 0)
3892 speed = speed_to_fwcap(lc->requested_speed);
3894 speed = fwcap_top_speed(lc->supported);
3896 /* Force AN on for BT cards. */
3897 if (is_bt(adap->port[adap->chan_map[port]]))
3898 aneg = lc->supported & FW_PORT_CAP32_ANEG;
3900 rcap = aneg | speed | fc | fec;
3901 if ((rcap | lc->supported) != lc->supported) {
3903 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap,
3906 rcap &= lc->supported;
3910 memset(&c, 0, sizeof(c));
3911 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3912 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3913 V_FW_PORT_CMD_PORTID(port));
3914 if (adap->params.port_caps32) {
3916 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
3918 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
3921 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3923 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
3926 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3930 * t4_restart_aneg - restart autonegotiation
3931 * @adap: the adapter
3932 * @mbox: mbox to use for the FW command
3933 * @port: the port id
3935 * Restarts autonegotiation for the selected port.
3937 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3939 struct fw_port_cmd c;
3941 memset(&c, 0, sizeof(c));
3942 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3943 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3944 V_FW_PORT_CMD_PORTID(port));
3946 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3948 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3949 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3952 struct intr_details {
3957 struct intr_action {
3960 bool (*action)(struct adapter *, int, bool);
3963 #define NONFATAL_IF_DISABLED 1
3965 const char *name; /* name of the INT_CAUSE register */
3966 int cause_reg; /* INT_CAUSE register */
3967 int enable_reg; /* INT_ENABLE register */
3968 u32 fatal; /* bits that are fatal */
3969 int flags; /* hints */
3970 const struct intr_details *details;
3971 const struct intr_action *actions;
3975 intr_alert_char(u32 cause, u32 enable, u32 fatal)
3986 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
3988 u32 enable, fatal, leftover;
3989 const struct intr_details *details;
3992 enable = t4_read_reg(adap, ii->enable_reg);
3993 if (ii->flags & NONFATAL_IF_DISABLED)
3994 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
3997 alert = intr_alert_char(cause, enable, fatal);
3998 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
3999 alert, ii->name, ii->cause_reg, cause, enable, fatal);
4002 for (details = ii->details; details && details->mask != 0; details++) {
4003 u32 msgbits = details->mask & cause;
4006 alert = intr_alert_char(msgbits, enable, ii->fatal);
4007 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits,
4009 leftover &= ~msgbits;
4011 if (leftover != 0 && leftover != cause)
4012 CH_ALERT(adap, " ? [0x%08x]\n", leftover);
4016 * Returns true for fatal error.
4019 t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4020 u32 additional_cause, bool verbose)
4024 const struct intr_action *action;
4027 * Read and display cause. Note that the top level PL_INT_CAUSE is a
4028 * bit special and we need to completely ignore the bits that are not in
4031 cause = t4_read_reg(adap, ii->cause_reg);
4032 if (ii->cause_reg == A_PL_INT_CAUSE)
4033 cause &= t4_read_reg(adap, ii->enable_reg);
4034 if (verbose || cause != 0)
4035 t4_show_intr_info(adap, ii, cause);
4036 fatal = cause & ii->fatal;
4037 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4038 fatal &= t4_read_reg(adap, ii->enable_reg);
4039 cause |= additional_cause;
4044 for (action = ii->actions; action && action->mask != 0; action++) {
4045 if (!(action->mask & cause))
4047 rc |= (action->action)(adap, action->arg, verbose);
4051 t4_write_reg(adap, ii->cause_reg, cause);
4052 (void)t4_read_reg(adap, ii->cause_reg);
4058 * Interrupt handler for the PCIE module.
4060 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4062 static const struct intr_details sysbus_intr_details[] = {
4063 { F_RNPP, "RXNP array parity error" },
4064 { F_RPCP, "RXPC array parity error" },
4065 { F_RCIP, "RXCIF array parity error" },
4066 { F_RCCP, "Rx completions control array parity error" },
4067 { F_RFTP, "RXFT array parity error" },
4070 static const struct intr_info sysbus_intr_info = {
4071 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4072 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4073 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4074 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4076 .details = sysbus_intr_details,
4079 static const struct intr_details pcie_port_intr_details[] = {
4080 { F_TPCP, "TXPC array parity error" },
4081 { F_TNPP, "TXNP array parity error" },
4082 { F_TFTP, "TXFT array parity error" },
4083 { F_TCAP, "TXCA array parity error" },
4084 { F_TCIP, "TXCIF array parity error" },
4085 { F_RCAP, "RXCA array parity error" },
4086 { F_OTDD, "outbound request TLP discarded" },
4087 { F_RDPE, "Rx data parity error" },
4088 { F_TDUE, "Tx uncorrectable data error" },
4091 static const struct intr_info pcie_port_intr_info = {
4092 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4093 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4094 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4095 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4096 F_OTDD | F_RDPE | F_TDUE,
4098 .details = pcie_port_intr_details,
4101 static const struct intr_details pcie_intr_details[] = {
4102 { F_MSIADDRLPERR, "MSI AddrL parity error" },
4103 { F_MSIADDRHPERR, "MSI AddrH parity error" },
4104 { F_MSIDATAPERR, "MSI data parity error" },
4105 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4106 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4107 { F_MSIXDATAPERR, "MSI-X data parity error" },
4108 { F_MSIXDIPERR, "MSI-X DI parity error" },
4109 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4110 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4111 { F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4112 { F_CCNTPERR, "PCIe CMD channel count parity error" },
4113 { F_CREQPERR, "PCIe CMD channel request parity error" },
4114 { F_CRSPPERR, "PCIe CMD channel response parity error" },
4115 { F_DCNTPERR, "PCIe DMA channel count parity error" },
4116 { F_DREQPERR, "PCIe DMA channel request parity error" },
4117 { F_DRSPPERR, "PCIe DMA channel response parity error" },
4118 { F_HCNTPERR, "PCIe HMA channel count parity error" },
4119 { F_HREQPERR, "PCIe HMA channel request parity error" },
4120 { F_HRSPPERR, "PCIe HMA channel response parity error" },
4121 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4122 { F_FIDPERR, "PCIe FID parity error" },
4123 { F_INTXCLRPERR, "PCIe INTx clear parity error" },
4124 { F_MATAGPERR, "PCIe MA tag parity error" },
4125 { F_PIOTAGPERR, "PCIe PIO tag parity error" },
4126 { F_RXCPLPERR, "PCIe Rx completion parity error" },
4127 { F_RXWRPERR, "PCIe Rx write parity error" },
4128 { F_RPLPERR, "PCIe replay buffer parity error" },
4129 { F_PCIESINT, "PCIe core secondary fault" },
4130 { F_PCIEPINT, "PCIe core primary fault" },
4131 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4134 static const struct intr_details t5_pcie_intr_details[] = {
4135 { F_IPGRPPERR, "Parity errors observed by IP" },
4136 { F_NONFATALERR, "PCIe non-fatal error" },
4137 { F_READRSPERR, "Outbound read error" },
4138 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4139 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4140 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4141 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4142 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4143 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4144 { F_MAGRPPERR, "MA group FIFO parity error" },
4145 { F_VFIDPERR, "VFID SRAM parity error" },
4146 { F_FIDPERR, "FID SRAM parity error" },
4147 { F_CFGSNPPERR, "config snoop FIFO parity error" },
4148 { F_HRSPPERR, "HMA channel response data SRAM parity error" },
4149 { F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4150 { F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4151 { F_DRSPPERR, "DMA channel response data SRAM parity error" },
4152 { F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4153 { F_CRSPPERR, "CMD channel response data SRAM parity error" },
4154 { F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4155 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4156 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4157 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4158 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4159 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4160 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4161 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4162 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4163 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4164 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4165 { F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4168 struct intr_info pcie_intr_info = {
4169 .name = "PCIE_INT_CAUSE",
4170 .cause_reg = A_PCIE_INT_CAUSE,
4171 .enable_reg = A_PCIE_INT_ENABLE,
4172 .fatal = 0xffffffff,
4173 .flags = NONFATAL_IF_DISABLED,
4180 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4181 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4183 pcie_intr_info.details = pcie_intr_details;
4185 pcie_intr_info.details = t5_pcie_intr_details;
4187 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4193 * TP interrupt handler.
4195 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4197 static const struct intr_details tp_intr_details[] = {
4198 { 0x3fffffff, "TP parity error" },
4199 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4202 static const struct intr_info tp_intr_info = {
4203 .name = "TP_INT_CAUSE",
4204 .cause_reg = A_TP_INT_CAUSE,
4205 .enable_reg = A_TP_INT_ENABLE,
4206 .fatal = 0x7fffffff,
4207 .flags = NONFATAL_IF_DISABLED,
4208 .details = tp_intr_details,
4212 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4216 * SGE interrupt handler.
4218 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4220 static const struct intr_info sge_int1_info = {
4221 .name = "SGE_INT_CAUSE1",
4222 .cause_reg = A_SGE_INT_CAUSE1,
4223 .enable_reg = A_SGE_INT_ENABLE1,
4224 .fatal = 0xffffffff,
4225 .flags = NONFATAL_IF_DISABLED,
4229 static const struct intr_info sge_int2_info = {
4230 .name = "SGE_INT_CAUSE2",
4231 .cause_reg = A_SGE_INT_CAUSE2,
4232 .enable_reg = A_SGE_INT_ENABLE2,
4233 .fatal = 0xffffffff,
4234 .flags = NONFATAL_IF_DISABLED,
4238 static const struct intr_details sge_int3_details[] = {
4240 "DBP pointer delivery for invalid context or QID" },
4241 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4242 "Invalid QID or header request by IDMA" },
4243 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4244 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4245 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4246 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4247 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4248 { F_ERR_TIMER_ABOVE_MAX_QID,
4249 "SGE GTS with timer 0-5 for IQID > 1023" },
4250 { F_ERR_CPL_EXCEED_IQE_SIZE,
4251 "SGE received CPL exceeding IQE size" },
4252 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4253 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4254 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4255 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4256 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4257 "SGE IQID > 1023 received CPL for FL" },
4258 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4259 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4260 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4261 { F_ERR_ING_CTXT_PRIO,
4262 "Ingress context manager priority user error" },
4263 { F_ERR_EGR_CTXT_PRIO,
4264 "Egress context manager priority user error" },
4265 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4266 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4267 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4268 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4269 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4270 { 0x0000000f, "SGE context access for invalid queue" },
4273 static const struct intr_details t6_sge_int3_details[] = {
4275 "DBP pointer delivery for invalid context or QID" },
4276 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4277 "Invalid QID or header request by IDMA" },
4278 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4279 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4280 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4281 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4282 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4283 { F_ERR_TIMER_ABOVE_MAX_QID,
4284 "SGE GTS with timer 0-5 for IQID > 1023" },
4285 { F_ERR_CPL_EXCEED_IQE_SIZE,
4286 "SGE received CPL exceeding IQE size" },
4287 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4288 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4289 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4290 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4291 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4292 "SGE IQID > 1023 received CPL for FL" },
4293 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4294 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4295 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4296 { F_ERR_ING_CTXT_PRIO,
4297 "Ingress context manager priority user error" },
4298 { F_ERR_EGR_CTXT_PRIO,
4299 "Egress context manager priority user error" },
4300 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4302 "SGE WRE packet less than advertized length" },
4303 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4304 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4305 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4306 { 0x0000000f, "SGE context access for invalid queue" },
4309 struct intr_info sge_int3_info = {
4310 .name = "SGE_INT_CAUSE3",
4311 .cause_reg = A_SGE_INT_CAUSE3,
4312 .enable_reg = A_SGE_INT_ENABLE3,
4313 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4318 static const struct intr_info sge_int4_info = {
4319 .name = "SGE_INT_CAUSE4",
4320 .cause_reg = A_SGE_INT_CAUSE4,
4321 .enable_reg = A_SGE_INT_ENABLE4,
4327 static const struct intr_info sge_int5_info = {
4328 .name = "SGE_INT_CAUSE5",
4329 .cause_reg = A_SGE_INT_CAUSE5,
4330 .enable_reg = A_SGE_INT_ENABLE5,
4331 .fatal = 0xffffffff,
4332 .flags = NONFATAL_IF_DISABLED,
4336 static const struct intr_info sge_int6_info = {
4337 .name = "SGE_INT_CAUSE6",
4338 .cause_reg = A_SGE_INT_CAUSE6,
4339 .enable_reg = A_SGE_INT_ENABLE6,
4349 if (chip_id(adap) <= CHELSIO_T5) {
4350 sge_int3_info.details = sge_int3_details;
4352 sge_int3_info.details = t6_sge_int3_details;
4356 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4357 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4358 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4359 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4360 if (chip_id(adap) >= CHELSIO_T5)
4361 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4362 if (chip_id(adap) >= CHELSIO_T6)
4363 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4365 v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4366 if (v & F_ERROR_QID_VALID) {
4367 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4368 if (v & F_UNCAPTURED_ERROR)
4369 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4370 t4_write_reg(adap, A_SGE_ERROR_STATS,
4371 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4378 * CIM interrupt handler.
4380 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4382 static const struct intr_action cim_host_intr_actions[] = {
4383 { F_TIMER0INT, 0, t4_os_dump_cimla },
4386 static const struct intr_details cim_host_intr_details[] = {
4388 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4391 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4392 { F_PLCIM_MSTRSPDATAPARERR,
4393 "PL2CIM master response data parity error" },
4394 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4395 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4396 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4397 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4398 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4399 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4402 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4403 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4404 { F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4405 { F_MBUPPARERR, "CIM mailbox uP parity error" },
4406 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4407 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4408 { F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4409 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4410 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */
4411 "CIM IBQ PCIe/SGE_HI parity error" },
4412 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4413 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4414 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4415 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4416 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4417 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4418 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4419 { F_TIMER1INT, "CIM TIMER0 interrupt" },
4420 { F_TIMER0INT, "CIM TIMER0 interrupt" },
4421 { F_PREFDROPINT, "CIM control register prefetch drop" },
4424 static const struct intr_info cim_host_intr_info = {
4425 .name = "CIM_HOST_INT_CAUSE",
4426 .cause_reg = A_CIM_HOST_INT_CAUSE,
4427 .enable_reg = A_CIM_HOST_INT_ENABLE,
4428 .fatal = 0x007fffe6,
4429 .flags = NONFATAL_IF_DISABLED,
4430 .details = cim_host_intr_details,
4431 .actions = cim_host_intr_actions,
4433 static const struct intr_details cim_host_upacc_intr_details[] = {
4434 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4435 { F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4436 { F_TIMEOUTINT, "CIM PIF timeout" },
4437 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4438 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4439 { F_BLKWRPLINT, "CIM block write to PL space" },
4440 { F_BLKRDPLINT, "CIM block read from PL space" },
4442 "CIM single write to PL space with illegal BEs" },
4444 "CIM single read from PL space with illegal BEs" },
4445 { F_BLKWRCTLINT, "CIM block write to CTL space" },
4446 { F_BLKRDCTLINT, "CIM block read from CTL space" },
4448 "CIM single write to CTL space with illegal BEs" },
4450 "CIM single read from CTL space with illegal BEs" },
4451 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4452 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4454 "CIM single write to EEPROM space with illegal BEs" },
4456 "CIM single read from EEPROM space with illegal BEs" },
4457 { F_BLKWRFLASHINT, "CIM block write to flash space" },
4458 { F_BLKRDFLASHINT, "CIM block read from flash space" },
4459 { F_SGLWRFLASHINT, "CIM single write to flash space" },
4461 "CIM single read from flash space with illegal BEs" },
4462 { F_BLKWRBOOTINT, "CIM block write to boot space" },
4463 { F_BLKRDBOOTINT, "CIM block read from boot space" },
4464 { F_SGLWRBOOTINT, "CIM single write to boot space" },
4466 "CIM single read from boot space with illegal BEs" },
4467 { F_ILLWRBEINT, "CIM illegal write BEs" },
4468 { F_ILLRDBEINT, "CIM illegal read BEs" },
4469 { F_ILLRDINT, "CIM illegal read" },
4470 { F_ILLWRINT, "CIM illegal write" },
4471 { F_ILLTRANSINT, "CIM illegal transaction" },
4472 { F_RSVDSPACEINT, "CIM reserved space access" },
4475 static const struct intr_info cim_host_upacc_intr_info = {
4476 .name = "CIM_HOST_UPACC_INT_CAUSE",
4477 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4478 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4479 .fatal = 0x3fffeeff,
4480 .flags = NONFATAL_IF_DISABLED,
4481 .details = cim_host_upacc_intr_details,
4484 static const struct intr_info cim_pf_host_intr_info = {
4485 .name = "CIM_PF_HOST_INT_CAUSE",
4486 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4487 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4496 fw_err = t4_read_reg(adap, A_PCIE_FW);
4497 if (fw_err & F_PCIE_FW_ERR)
4498 t4_report_fw_error(adap);
4501 * When the Firmware detects an internal error which normally wouldn't
4502 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4503 * to make sure the Host sees the Firmware Crash. So if we have a
4504 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4507 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4508 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4509 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4510 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4514 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4515 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4516 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4522 * ULP RX interrupt handler.
4524 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4526 static const struct intr_details ulprx_intr_details[] = {
4528 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4529 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4532 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4533 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4534 { 0x007fffff, "ULPRX parity error" },
4537 static const struct intr_info ulprx_intr_info = {
4538 .name = "ULP_RX_INT_CAUSE",
4539 .cause_reg = A_ULP_RX_INT_CAUSE,
4540 .enable_reg = A_ULP_RX_INT_ENABLE,
4541 .fatal = 0x07ffffff,
4542 .flags = NONFATAL_IF_DISABLED,
4543 .details = ulprx_intr_details,
4546 static const struct intr_info ulprx_intr2_info = {
4547 .name = "ULP_RX_INT_CAUSE_2",
4548 .cause_reg = A_ULP_RX_INT_CAUSE_2,
4549 .enable_reg = A_ULP_RX_INT_ENABLE_2,
4557 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4558 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4564 * ULP TX interrupt handler.
4566 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4568 static const struct intr_details ulptx_intr_details[] = {
4569 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4570 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4571 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4572 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4573 { 0x0fffffff, "ULPTX parity error" },
4576 static const struct intr_info ulptx_intr_info = {
4577 .name = "ULP_TX_INT_CAUSE",
4578 .cause_reg = A_ULP_TX_INT_CAUSE,
4579 .enable_reg = A_ULP_TX_INT_ENABLE,
4580 .fatal = 0x0fffffff,
4581 .flags = NONFATAL_IF_DISABLED,
4582 .details = ulptx_intr_details,
4585 static const struct intr_info ulptx_intr2_info = {
4586 .name = "ULP_TX_INT_CAUSE_2",
4587 .cause_reg = A_ULP_TX_INT_CAUSE_2,
4588 .enable_reg = A_ULP_TX_INT_ENABLE_2,
4590 .flags = NONFATAL_IF_DISABLED,
4596 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4597 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4602 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4607 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4608 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4609 for (i = 0; i < ARRAY_SIZE(data); i++) {
4610 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4611 A_PM_TX_DBG_STAT0 + i, data[i]);
4618 * PM TX interrupt handler.
4620 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4622 static const struct intr_action pmtx_intr_actions[] = {
4623 { 0xffffffff, 0, pmtx_dump_dbg_stats },
4626 static const struct intr_details pmtx_intr_details[] = {
4627 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4628 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4629 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4630 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4631 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4632 { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4633 { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4634 { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4635 { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4636 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4637 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4638 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4639 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4640 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4643 static const struct intr_info pmtx_intr_info = {
4644 .name = "PM_TX_INT_CAUSE",
4645 .cause_reg = A_PM_TX_INT_CAUSE,
4646 .enable_reg = A_PM_TX_INT_ENABLE,
4647 .fatal = 0xffffffff,
4649 .details = pmtx_intr_details,
4650 .actions = pmtx_intr_actions,
4653 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4657 * PM RX interrupt handler.
4659 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4661 static const struct intr_details pmrx_intr_details[] = {
4663 { 0x18000000, "PMRX ospi overflow" },
4664 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4665 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4666 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4667 { F_SDC_ERR, "PMRX SDC error" },
4670 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4671 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4672 { 0x0003c000, "PMRX iespi Rx framing error" },
4673 { 0x00003c00, "PMRX iespi Tx framing error" },
4674 { 0x00000300, "PMRX ocspi Rx framing error" },
4675 { 0x000000c0, "PMRX ocspi Tx framing error" },
4676 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4677 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4678 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4679 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4680 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4683 static const struct intr_info pmrx_intr_info = {
4684 .name = "PM_RX_INT_CAUSE",
4685 .cause_reg = A_PM_RX_INT_CAUSE,
4686 .enable_reg = A_PM_RX_INT_ENABLE,
4687 .fatal = 0x1fffffff,
4688 .flags = NONFATAL_IF_DISABLED,
4689 .details = pmrx_intr_details,
4693 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4697 * CPL switch interrupt handler.
4699 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4701 static const struct intr_details cplsw_intr_details[] = {
4703 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4704 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4707 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4708 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4709 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4710 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4711 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4712 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4715 static const struct intr_info cplsw_intr_info = {
4716 .name = "CPL_INTR_CAUSE",
4717 .cause_reg = A_CPL_INTR_CAUSE,
4718 .enable_reg = A_CPL_INTR_ENABLE,
4720 .flags = NONFATAL_IF_DISABLED,
4721 .details = cplsw_intr_details,
4725 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4728 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4729 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4730 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4731 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4732 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4733 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4734 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4735 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4736 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4739 * LE interrupt handler.
4741 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4743 static const struct intr_details le_intr_details[] = {
4744 { F_REQQPARERR, "LE request queue parity error" },
4745 { F_UNKNOWNCMD, "LE unknown command" },
4746 { F_ACTRGNFULL, "LE active region full" },
4747 { F_PARITYERR, "LE parity error" },
4748 { F_LIPMISS, "LE LIP miss" },
4749 { F_LIP0, "LE 0 LIP error" },
4752 static const struct intr_details t6_le_intr_details[] = {
4753 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4754 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4755 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4756 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4757 { F_TOTCNTERR, "LE total active < TCAM count" },
4758 { F_CMDPRSRINTERR, "LE internal error in parser" },
4759 { F_CMDTIDERR, "Incorrect tid in LE command" },
4760 { F_T6_ACTRGNFULL, "LE active region full" },
4761 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4762 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4763 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4764 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4765 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4766 { F_TCAMACCFAIL, "LE TCAM access failure" },
4767 { F_T6_UNKNOWNCMD, "LE unknown command" },
4768 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4769 { F_T6_LIPMISS, "LE CLIP lookup miss" },
4770 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4773 struct intr_info le_intr_info = {
4774 .name = "LE_DB_INT_CAUSE",
4775 .cause_reg = A_LE_DB_INT_CAUSE,
4776 .enable_reg = A_LE_DB_INT_ENABLE,
4778 .flags = NONFATAL_IF_DISABLED,
4783 if (chip_id(adap) <= CHELSIO_T5) {
4784 le_intr_info.details = le_intr_details;
4785 le_intr_info.fatal = T5_LE_FATAL_MASK;
4787 le_intr_info.details = t6_le_intr_details;
4788 le_intr_info.fatal = T6_LE_FATAL_MASK;
4791 return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4795 * MPS interrupt handler.
4797 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4799 static const struct intr_details mps_rx_perr_intr_details[] = {
4800 { 0xffffffff, "MPS Rx parity error" },
4803 static const struct intr_info mps_rx_perr_intr_info = {
4804 .name = "MPS_RX_PERR_INT_CAUSE",
4805 .cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4806 .enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4807 .fatal = 0xffffffff,
4808 .flags = NONFATAL_IF_DISABLED,
4809 .details = mps_rx_perr_intr_details,
4812 static const struct intr_details mps_tx_intr_details[] = {
4813 { F_PORTERR, "MPS Tx destination port is disabled" },
4814 { F_FRMERR, "MPS Tx framing error" },
4815 { F_SECNTERR, "MPS Tx SOP/EOP error" },
4816 { F_BUBBLE, "MPS Tx underflow" },
4817 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4818 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4819 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4820 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4823 static const struct intr_info mps_tx_intr_info = {
4824 .name = "MPS_TX_INT_CAUSE",
4825 .cause_reg = A_MPS_TX_INT_CAUSE,
4826 .enable_reg = A_MPS_TX_INT_ENABLE,
4828 .flags = NONFATAL_IF_DISABLED,
4829 .details = mps_tx_intr_details,
4832 static const struct intr_details mps_trc_intr_details[] = {
4833 { F_MISCPERR, "MPS TRC misc parity error" },
4834 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4835 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4838 static const struct intr_info mps_trc_intr_info = {
4839 .name = "MPS_TRC_INT_CAUSE",
4840 .cause_reg = A_MPS_TRC_INT_CAUSE,
4841 .enable_reg = A_MPS_TRC_INT_ENABLE,
4842 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4844 .details = mps_trc_intr_details,
4847 static const struct intr_details mps_stat_sram_intr_details[] = {
4848 { 0xffffffff, "MPS statistics SRAM parity error" },
4851 static const struct intr_info mps_stat_sram_intr_info = {
4852 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4853 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4854 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4855 .fatal = 0x1fffffff,
4856 .flags = NONFATAL_IF_DISABLED,
4857 .details = mps_stat_sram_intr_details,
4860 static const struct intr_details mps_stat_tx_intr_details[] = {
4861 { 0xffffff, "MPS statistics Tx FIFO parity error" },
4864 static const struct intr_info mps_stat_tx_intr_info = {
4865 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4866 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4867 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4869 .flags = NONFATAL_IF_DISABLED,
4870 .details = mps_stat_tx_intr_details,
4873 static const struct intr_details mps_stat_rx_intr_details[] = {
4874 { 0xffffff, "MPS statistics Rx FIFO parity error" },
4877 static const struct intr_info mps_stat_rx_intr_info = {
4878 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4879 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4880 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4883 .details = mps_stat_rx_intr_details,
4886 static const struct intr_details mps_cls_intr_details[] = {
4887 { F_HASHSRAM, "MPS hash SRAM parity error" },
4888 { F_MATCHTCAM, "MPS match TCAM parity error" },
4889 { F_MATCHSRAM, "MPS match SRAM parity error" },
4892 static const struct intr_info mps_cls_intr_info = {
4893 .name = "MPS_CLS_INT_CAUSE",
4894 .cause_reg = A_MPS_CLS_INT_CAUSE,
4895 .enable_reg = A_MPS_CLS_INT_ENABLE,
4896 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4898 .details = mps_cls_intr_details,
4901 static const struct intr_details mps_stat_sram1_intr_details[] = {
4902 { 0xff, "MPS statistics SRAM1 parity error" },
4905 static const struct intr_info mps_stat_sram1_intr_info = {
4906 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4907 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4908 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4911 .details = mps_stat_sram1_intr_details,
4918 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
4919 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
4920 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
4921 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
4922 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
4923 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
4924 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
4925 if (chip_id(adap) > CHELSIO_T4) {
4926 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
4930 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
4931 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */
4938 * EDC/MC interrupt handler.
4940 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
4942 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
4943 unsigned int count_reg, v;
4944 static const struct intr_details mem_intr_details[] = {
4945 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
4946 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
4947 { F_PERR_INT_CAUSE, "FIFO parity error" },
4950 struct intr_info ii = {
4951 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
4952 .details = mem_intr_details,
4960 ii.name = "EDC0_INT_CAUSE";
4961 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
4962 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
4963 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
4966 ii.name = "EDC1_INT_CAUSE";
4967 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
4968 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
4969 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
4972 ii.name = "MC0_INT_CAUSE";
4974 ii.cause_reg = A_MC_INT_CAUSE;
4975 ii.enable_reg = A_MC_INT_ENABLE;
4976 count_reg = A_MC_ECC_STATUS;
4978 ii.cause_reg = A_MC_P_INT_CAUSE;
4979 ii.enable_reg = A_MC_P_INT_ENABLE;
4980 count_reg = A_MC_P_ECC_STATUS;
4984 ii.name = "MC1_INT_CAUSE";
4985 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
4986 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
4987 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
4991 fatal = t4_handle_intr(adap, &ii, 0, verbose);
4993 v = t4_read_reg(adap, count_reg);
4995 if (G_ECC_UECNT(v) != 0) {
4997 "%s: %u uncorrectable ECC data error(s)\n",
4998 name[idx], G_ECC_UECNT(v));
5000 if (G_ECC_CECNT(v) != 0) {
5001 if (idx <= MEM_EDC1)
5002 t4_edc_err_read(adap, idx);
5003 CH_WARN_RATELIMIT(adap,
5004 "%s: %u correctable ECC data error(s)\n",
5005 name[idx], G_ECC_CECNT(v));
5007 t4_write_reg(adap, count_reg, 0xffffffff);
5013 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5017 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5019 "MA address wrap-around error by client %u to address %#x\n",
5020 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5021 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5028 * MA interrupt handler.
5030 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5032 static const struct intr_action ma_intr_actions[] = {
5033 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5036 static const struct intr_info ma_intr_info = {
5037 .name = "MA_INT_CAUSE",
5038 .cause_reg = A_MA_INT_CAUSE,
5039 .enable_reg = A_MA_INT_ENABLE,
5040 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5041 .flags = NONFATAL_IF_DISABLED,
5043 .actions = ma_intr_actions,
5045 static const struct intr_info ma_perr_status1 = {
5046 .name = "MA_PARITY_ERROR_STATUS1",
5047 .cause_reg = A_MA_PARITY_ERROR_STATUS1,
5048 .enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5049 .fatal = 0xffffffff,
5054 static const struct intr_info ma_perr_status2 = {
5055 .name = "MA_PARITY_ERROR_STATUS2",
5056 .cause_reg = A_MA_PARITY_ERROR_STATUS2,
5057 .enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5058 .fatal = 0xffffffff,
5066 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5067 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5068 if (chip_id(adap) > CHELSIO_T4)
5069 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5075 * SMB interrupt handler.
5077 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5079 static const struct intr_details smb_intr_details[] = {
5080 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5081 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5082 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5085 static const struct intr_info smb_intr_info = {
5086 .name = "SMB_INT_CAUSE",
5087 .cause_reg = A_SMB_INT_CAUSE,
5088 .enable_reg = A_SMB_INT_ENABLE,
5089 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5091 .details = smb_intr_details,
5095 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5099 * NC-SI interrupt handler.
5101 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5103 static const struct intr_details ncsi_intr_details[] = {
5104 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5105 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5106 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5107 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5110 static const struct intr_info ncsi_intr_info = {
5111 .name = "NCSI_INT_CAUSE",
5112 .cause_reg = A_NCSI_INT_CAUSE,
5113 .enable_reg = A_NCSI_INT_ENABLE,
5114 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5115 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5117 .details = ncsi_intr_details,
5121 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5125 * MAC interrupt handler.
5127 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5129 static const struct intr_details mac_intr_details[] = {
5130 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5131 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5135 struct intr_info ii;
5139 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5141 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5142 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5143 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5145 ii.details = mac_intr_details;
5148 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5150 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5151 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5152 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5154 ii.details = mac_intr_details;
5157 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5159 if (chip_id(adap) >= CHELSIO_T5) {
5160 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5162 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5163 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5168 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5171 if (chip_id(adap) >= CHELSIO_T6) {
5172 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5174 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5175 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5180 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5186 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5188 static const struct intr_details plpl_intr_details[] = {
5189 { F_FATALPERR, "Fatal parity error" },
5190 { F_PERRVFID, "VFID_MAP parity error" },
5193 static const struct intr_info plpl_intr_info = {
5194 .name = "PL_PL_INT_CAUSE",
5195 .cause_reg = A_PL_PL_INT_CAUSE,
5196 .enable_reg = A_PL_PL_INT_ENABLE,
5197 .fatal = F_FATALPERR | F_PERRVFID,
5198 .flags = NONFATAL_IF_DISABLED,
5199 .details = plpl_intr_details,
5203 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5207 * t4_slow_intr_handler - control path interrupt handler
5208 * @adap: the adapter
5209 * @verbose: increased verbosity, for debug
5211 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5212 * The designation 'slow' is because it involves register reads, while
5213 * data interrupts typically don't involve any MMIOs.
5215 int t4_slow_intr_handler(struct adapter *adap, bool verbose)
5217 static const struct intr_details pl_intr_details[] = {
5220 { F_ULP_TX, "ULP TX" },
5223 { F_CPL_SWITCH, "CPL Switch" },
5224 { F_ULP_RX, "ULP RX" },
5225 { F_PM_RX, "PM RX" },
5226 { F_PM_TX, "PM TX" },
5242 { F_NCSI, "NC-SI" },
5250 static const struct intr_info pl_perr_cause = {
5251 .name = "PL_PERR_CAUSE",
5252 .cause_reg = A_PL_PERR_CAUSE,
5253 .enable_reg = A_PL_PERR_ENABLE,
5254 .fatal = 0xffffffff,
5256 .details = pl_intr_details,
5259 static const struct intr_action pl_intr_action[] = {
5260 { F_MC1, MEM_MC1, mem_intr_handler },
5261 { F_ULP_TX, -1, ulptx_intr_handler },
5262 { F_SGE, -1, sge_intr_handler },
5263 { F_CPL_SWITCH, -1, cplsw_intr_handler },
5264 { F_ULP_RX, -1, ulprx_intr_handler },
5265 { F_PM_RX, -1, pmrx_intr_handler},
5266 { F_PM_TX, -1, pmtx_intr_handler},
5267 { F_MA, -1, ma_intr_handler },
5268 { F_TP, -1, tp_intr_handler },
5269 { F_LE, -1, le_intr_handler },
5270 { F_EDC1, MEM_EDC1, mem_intr_handler },
5271 { F_EDC0, MEM_EDC0, mem_intr_handler },
5272 { F_MC0, MEM_MC0, mem_intr_handler },
5273 { F_PCIE, -1, pcie_intr_handler },
5274 { F_MAC3, 3, mac_intr_handler},
5275 { F_MAC2, 2, mac_intr_handler},
5276 { F_MAC1, 1, mac_intr_handler},
5277 { F_MAC0, 0, mac_intr_handler},
5278 { F_SMB, -1, smb_intr_handler},
5279 { F_PL, -1, plpl_intr_handler },
5280 { F_NCSI, -1, ncsi_intr_handler},
5281 { F_MPS, -1, mps_intr_handler },
5282 { F_CIM, -1, cim_intr_handler },
5285 static const struct intr_info pl_intr_info = {
5286 .name = "PL_INT_CAUSE",
5287 .cause_reg = A_PL_INT_CAUSE,
5288 .enable_reg = A_PL_INT_ENABLE,
5291 .details = pl_intr_details,
5292 .actions = pl_intr_action,
5297 perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5298 if (verbose || perr != 0) {
5299 t4_show_intr_info(adap, &pl_perr_cause, perr);
5301 t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5303 perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5305 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose);
5307 t4_fatal_err(adap, false);
5312 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
5315 * t4_intr_enable - enable interrupts
5316 * @adapter: the adapter whose interrupts should be enabled
5318 * Enable PF-specific interrupts for the calling function and the top-level
5319 * interrupt concentrator for global interrupts. Interrupts are already
5320 * enabled at each module, here we just enable the roots of the interrupt
5323 * Note: this function should be called only when the driver manages
5324 * non PF-specific interrupts from the various HW modules. Only one PCI
5325 * function at a time should be doing this.
5327 void t4_intr_enable(struct adapter *adap)
5331 if (chip_id(adap) <= CHELSIO_T5)
5332 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5334 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5335 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5336 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5337 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5338 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5339 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5341 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5342 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5343 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5344 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5348 * t4_intr_disable - disable interrupts
5349 * @adap: the adapter whose interrupts should be disabled
5351 * Disable interrupts. We only disable the top-level interrupt
5352 * concentrators. The caller must be a PCI function managing global
5355 void t4_intr_disable(struct adapter *adap)
5358 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5359 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5363 * t4_intr_clear - clear all interrupts
5364 * @adap: the adapter whose interrupts should be cleared
5366 * Clears all interrupts. The caller must be a PCI function managing
5367 * global interrupts.
5369 void t4_intr_clear(struct adapter *adap)
5371 static const u32 cause_reg[] = {
5372 A_CIM_HOST_INT_CAUSE,
5373 A_CIM_HOST_UPACC_INT_CAUSE,
5374 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5376 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
5378 A_MA_INT_WRAP_STATUS,
5379 A_MA_PARITY_ERROR_STATUS1,
5381 A_MPS_CLS_INT_CAUSE,
5382 A_MPS_RX_PERR_INT_CAUSE,
5383 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
5384 A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5385 A_MPS_TRC_INT_CAUSE,
5387 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
5401 A_ULP_RX_INT_CAUSE_2,
5403 A_ULP_TX_INT_CAUSE_2,
5405 MYPF_REG(A_PL_PF_INT_CAUSE),
5408 const int nchan = adap->chip_params->nchan;
5410 for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5411 t4_write_reg(adap, cause_reg[i], 0xffffffff);
5414 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
5416 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
5418 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
5419 for (i = 0; i < nchan; i++) {
5420 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
5424 if (chip_id(adap) >= CHELSIO_T5) {
5425 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
5426 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
5427 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
5428 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
5430 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
5433 for (i = 0; i < nchan; i++) {
5434 t4_write_reg(adap, T5_PORT_REG(i,
5435 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
5436 if (chip_id(adap) > CHELSIO_T5) {
5437 t4_write_reg(adap, T5_PORT_REG(i,
5438 A_MAC_PORT_PERR_INT_CAUSE_100G),
5441 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
5445 if (chip_id(adap) >= CHELSIO_T6) {
5446 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
5449 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5450 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
5451 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
5452 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */
5456 * hash_mac_addr - return the hash value of a MAC address
5457 * @addr: the 48-bit Ethernet MAC address
5459 * Hashes a MAC address according to the hash function used by HW inexact
5460 * (hash) address matching.
5462 static int hash_mac_addr(const u8 *addr)
5464 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5465 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5473 * t4_config_rss_range - configure a portion of the RSS mapping table
5474 * @adapter: the adapter
5475 * @mbox: mbox to use for the FW command
5476 * @viid: virtual interface whose RSS subtable is to be written
5477 * @start: start entry in the table to write
5478 * @n: how many table entries to write
5479 * @rspq: values for the "response queue" (Ingress Queue) lookup table
5480 * @nrspq: number of values in @rspq
5482 * Programs the selected part of the VI's RSS mapping table with the
5483 * provided values. If @nrspq < @n the supplied values are used repeatedly
5484 * until the full table range is populated.
5486 * The caller must ensure the values in @rspq are in the range allowed for
5489 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5490 int start, int n, const u16 *rspq, unsigned int nrspq)
5493 const u16 *rsp = rspq;
5494 const u16 *rsp_end = rspq + nrspq;
5495 struct fw_rss_ind_tbl_cmd cmd;
5497 memset(&cmd, 0, sizeof(cmd));
5498 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5499 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5500 V_FW_RSS_IND_TBL_CMD_VIID(viid));
5501 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5504 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5505 * Queue Identifiers. These Ingress Queue IDs are packed three to
5506 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5510 int nq = min(n, 32);
5512 __be32 *qp = &cmd.iq0_to_iq2;
5515 * Set up the firmware RSS command header to send the next
5516 * "nq" Ingress Queue IDs to the firmware.
5518 cmd.niqid = cpu_to_be16(nq);
5519 cmd.startidx = cpu_to_be16(start);
5522 * "nq" more done for the start of the next loop.
5528 * While there are still Ingress Queue IDs to stuff into the
5529 * current firmware RSS command, retrieve them from the
5530 * Ingress Queue ID array and insert them into the command.
5534 * Grab up to the next 3 Ingress Queue IDs (wrapping
5535 * around the Ingress Queue ID array if necessary) and
5536 * insert them into the firmware RSS command at the
5537 * current 3-tuple position within the commad.
5541 int nqbuf = min(3, nq);
5544 qbuf[0] = qbuf[1] = qbuf[2] = 0;
5545 while (nqbuf && nq_packed < 32) {
5552 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5553 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5554 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5558 * Send this portion of the RRS table update to the firmware;
5559 * bail out on any errors.
5561 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5569 * t4_config_glbl_rss - configure the global RSS mode
5570 * @adapter: the adapter
5571 * @mbox: mbox to use for the FW command
5572 * @mode: global RSS mode
5573 * @flags: mode-specific flags
5575 * Sets the global RSS mode.
5577 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5580 struct fw_rss_glb_config_cmd c;
5582 memset(&c, 0, sizeof(c));
5583 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5584 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5585 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5586 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5587 c.u.manual.mode_pkd =
5588 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5589 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5590 c.u.basicvirtual.mode_keymode =
5591 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5592 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5595 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5599 * t4_config_vi_rss - configure per VI RSS settings
5600 * @adapter: the adapter
5601 * @mbox: mbox to use for the FW command
5604 * @defq: id of the default RSS queue for the VI.
5605 * @skeyidx: RSS secret key table index for non-global mode
5606 * @skey: RSS vf_scramble key for VI.
5608 * Configures VI-specific RSS properties.
5610 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5611 unsigned int flags, unsigned int defq, unsigned int skeyidx,
5614 struct fw_rss_vi_config_cmd c;
5616 memset(&c, 0, sizeof(c));
5617 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5618 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5619 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5620 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5621 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5622 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5623 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5624 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5625 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5627 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5630 /* Read an RSS table row */
5631 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5633 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5634 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5639 * t4_read_rss - read the contents of the RSS mapping table
5640 * @adapter: the adapter
5641 * @map: holds the contents of the RSS mapping table
5643 * Reads the contents of the RSS hash->queue mapping table.
5645 int t4_read_rss(struct adapter *adapter, u16 *map)
5650 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5651 ret = rd_rss_row(adapter, i, &val);
5654 *map++ = G_LKPTBLQUEUE0(val);
5655 *map++ = G_LKPTBLQUEUE1(val);
5661 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5662 * @adap: the adapter
5663 * @cmd: TP fw ldst address space type
5664 * @vals: where the indirect register values are stored/written
5665 * @nregs: how many indirect registers to read/write
5666 * @start_idx: index of first indirect register to read/write
5667 * @rw: Read (1) or Write (0)
5668 * @sleep_ok: if true we may sleep while awaiting command completion
5670 * Access TP indirect registers through LDST
5672 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5673 unsigned int nregs, unsigned int start_index,
5674 unsigned int rw, bool sleep_ok)
5678 struct fw_ldst_cmd c;
5680 for (i = 0; i < nregs; i++) {
5681 memset(&c, 0, sizeof(c));
5682 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5684 (rw ? F_FW_CMD_READ :
5686 V_FW_LDST_CMD_ADDRSPACE(cmd));
5687 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5689 c.u.addrval.addr = cpu_to_be32(start_index + i);
5690 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5691 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5697 vals[i] = be32_to_cpu(c.u.addrval.val);
5703 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5704 * @adap: the adapter
5705 * @reg_addr: Address Register
5706 * @reg_data: Data register
5707 * @buff: where the indirect register values are stored/written
5708 * @nregs: how many indirect registers to read/write
5709 * @start_index: index of first indirect register to read/write
5710 * @rw: READ(1) or WRITE(0)
5711 * @sleep_ok: if true we may sleep while awaiting command completion
5713 * Read/Write TP indirect registers through LDST if possible.
5714 * Else, use backdoor access
5716 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5717 u32 *buff, u32 nregs, u32 start_index, int rw,
5725 cmd = FW_LDST_ADDRSPC_TP_PIO;
5727 case A_TP_TM_PIO_ADDR:
5728 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5730 case A_TP_MIB_INDEX:
5731 cmd = FW_LDST_ADDRSPC_TP_MIB;
5734 goto indirect_access;
5737 if (t4_use_ldst(adap))
5738 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5745 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5748 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5754 * t4_tp_pio_read - Read TP PIO registers
5755 * @adap: the adapter
5756 * @buff: where the indirect register values are written
5757 * @nregs: how many indirect registers to read
5758 * @start_index: index of first indirect register to read
5759 * @sleep_ok: if true we may sleep while awaiting command completion
5761 * Read TP PIO Registers
5763 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5764 u32 start_index, bool sleep_ok)
5766 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5767 start_index, 1, sleep_ok);
5771 * t4_tp_pio_write - Write TP PIO registers
5772 * @adap: the adapter
5773 * @buff: where the indirect register values are stored
5774 * @nregs: how many indirect registers to write
5775 * @start_index: index of first indirect register to write
5776 * @sleep_ok: if true we may sleep while awaiting command completion
5778 * Write TP PIO Registers
5780 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5781 u32 start_index, bool sleep_ok)
5783 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5784 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5788 * t4_tp_tm_pio_read - Read TP TM PIO registers
5789 * @adap: the adapter
5790 * @buff: where the indirect register values are written
5791 * @nregs: how many indirect registers to read
5792 * @start_index: index of first indirect register to read
5793 * @sleep_ok: if true we may sleep while awaiting command completion
5795 * Read TP TM PIO Registers
5797 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5798 u32 start_index, bool sleep_ok)
5800 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5801 nregs, start_index, 1, sleep_ok);
5805 * t4_tp_mib_read - Read TP MIB registers
5806 * @adap: the adapter
5807 * @buff: where the indirect register values are written
5808 * @nregs: how many indirect registers to read
5809 * @start_index: index of first indirect register to read
5810 * @sleep_ok: if true we may sleep while awaiting command completion
5812 * Read TP MIB Registers
5814 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5817 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5818 start_index, 1, sleep_ok);
5822 * t4_read_rss_key - read the global RSS key
5823 * @adap: the adapter
5824 * @key: 10-entry array holding the 320-bit RSS key
5825 * @sleep_ok: if true we may sleep while awaiting command completion
5827 * Reads the global 320-bit RSS key.
5829 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5831 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5835 * t4_write_rss_key - program one of the RSS keys
5836 * @adap: the adapter
5837 * @key: 10-entry array holding the 320-bit RSS key
5838 * @idx: which RSS key to write
5839 * @sleep_ok: if true we may sleep while awaiting command completion
5841 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5842 * 0..15 the corresponding entry in the RSS key table is written,
5843 * otherwise the global RSS key is written.
5845 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5848 u8 rss_key_addr_cnt = 16;
5849 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5852 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5853 * allows access to key addresses 16-63 by using KeyWrAddrX
5854 * as index[5:4](upper 2) into key table
5856 if ((chip_id(adap) > CHELSIO_T5) &&
5857 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5858 rss_key_addr_cnt = 32;
5860 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5862 if (idx >= 0 && idx < rss_key_addr_cnt) {
5863 if (rss_key_addr_cnt > 16)
5864 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5865 vrt | V_KEYWRADDRX(idx >> 4) |
5866 V_T6_VFWRADDR(idx) | F_KEYWREN);
5868 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5869 vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5874 * t4_read_rss_pf_config - read PF RSS Configuration Table
5875 * @adapter: the adapter
5876 * @index: the entry in the PF RSS table to read
5877 * @valp: where to store the returned value
5878 * @sleep_ok: if true we may sleep while awaiting command completion
5880 * Reads the PF RSS Configuration Table at the specified index and returns
5881 * the value found there.
5883 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5884 u32 *valp, bool sleep_ok)
5886 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5890 * t4_write_rss_pf_config - write PF RSS Configuration Table
5891 * @adapter: the adapter
5892 * @index: the entry in the VF RSS table to read
5893 * @val: the value to store
5894 * @sleep_ok: if true we may sleep while awaiting command completion
5896 * Writes the PF RSS Configuration Table at the specified index with the
5899 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5900 u32 val, bool sleep_ok)
5902 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5907 * t4_read_rss_vf_config - read VF RSS Configuration Table
5908 * @adapter: the adapter
5909 * @index: the entry in the VF RSS table to read
5910 * @vfl: where to store the returned VFL
5911 * @vfh: where to store the returned VFH
5912 * @sleep_ok: if true we may sleep while awaiting command completion
5914 * Reads the VF RSS Configuration Table at the specified index and returns
5915 * the (VFL, VFH) values found there.
5917 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5918 u32 *vfl, u32 *vfh, bool sleep_ok)
5920 u32 vrt, mask, data;
5922 if (chip_id(adapter) <= CHELSIO_T5) {
5923 mask = V_VFWRADDR(M_VFWRADDR);
5924 data = V_VFWRADDR(index);
5926 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
5927 data = V_T6_VFWRADDR(index);
5930 * Request that the index'th VF Table values be read into VFL/VFH.
5932 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5933 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5934 vrt |= data | F_VFRDEN;
5935 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5938 * Grab the VFL/VFH values ...
5940 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5941 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5945 * t4_write_rss_vf_config - write VF RSS Configuration Table
5947 * @adapter: the adapter
5948 * @index: the entry in the VF RSS table to write
5949 * @vfl: the VFL to store
5950 * @vfh: the VFH to store
5952 * Writes the VF RSS Configuration Table at the specified index with the
5953 * specified (VFL, VFH) values.
5955 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
5956 u32 vfl, u32 vfh, bool sleep_ok)
5958 u32 vrt, mask, data;
5960 if (chip_id(adapter) <= CHELSIO_T5) {
5961 mask = V_VFWRADDR(M_VFWRADDR);
5962 data = V_VFWRADDR(index);
5964 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
5965 data = V_T6_VFWRADDR(index);
5969 * Load up VFL/VFH with the values to be written ...
5971 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5972 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5975 * Write the VFL/VFH into the VF Table at index'th location.
5977 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5978 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5979 vrt |= data | F_VFRDEN;
5980 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5984 * t4_read_rss_pf_map - read PF RSS Map
5985 * @adapter: the adapter
5986 * @sleep_ok: if true we may sleep while awaiting command completion
5988 * Reads the PF RSS Map register and returns its value.
5990 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5994 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6000 * t4_write_rss_pf_map - write PF RSS Map
6001 * @adapter: the adapter
6002 * @pfmap: PF RSS Map value
6004 * Writes the specified value to the PF RSS Map register.
6006 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6008 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6012 * t4_read_rss_pf_mask - read PF RSS Mask
6013 * @adapter: the adapter
6014 * @sleep_ok: if true we may sleep while awaiting command completion
6016 * Reads the PF RSS Mask register and returns its value.
6018 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6022 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6028 * t4_write_rss_pf_mask - write PF RSS Mask
6029 * @adapter: the adapter
6030 * @pfmask: PF RSS Mask value
6032 * Writes the specified value to the PF RSS Mask register.
6034 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6036 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6040 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
6041 * @adap: the adapter
6042 * @v4: holds the TCP/IP counter values
6043 * @v6: holds the TCP/IPv6 counter values
6044 * @sleep_ok: if true we may sleep while awaiting command completion
6046 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
6047 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
6049 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6050 struct tp_tcp_stats *v6, bool sleep_ok)
6052 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6054 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6055 #define STAT(x) val[STAT_IDX(x)]
6056 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6059 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6060 A_TP_MIB_TCP_OUT_RST, sleep_ok);
6061 v4->tcp_out_rsts = STAT(OUT_RST);
6062 v4->tcp_in_segs = STAT64(IN_SEG);
6063 v4->tcp_out_segs = STAT64(OUT_SEG);
6064 v4->tcp_retrans_segs = STAT64(RXT_SEG);
6067 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6068 A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6069 v6->tcp_out_rsts = STAT(OUT_RST);
6070 v6->tcp_in_segs = STAT64(IN_SEG);
6071 v6->tcp_out_segs = STAT64(OUT_SEG);
6072 v6->tcp_retrans_segs = STAT64(RXT_SEG);
6080 * t4_tp_get_err_stats - read TP's error MIB counters
6081 * @adap: the adapter
6082 * @st: holds the counter values
6083 * @sleep_ok: if true we may sleep while awaiting command completion
6085 * Returns the values of TP's error counters.
6087 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6090 int nchan = adap->chip_params->nchan;
6092 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6095 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6098 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6101 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6102 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6104 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6105 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6107 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6110 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6111 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6113 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6114 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6116 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6121 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
6122 * @adap: the adapter
6123 * @st: holds the counter values
6125 * Returns the values of TP's proxy counters.
6127 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6130 int nchan = adap->chip_params->nchan;
6132 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6136 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
6137 * @adap: the adapter
6138 * @st: holds the counter values
6139 * @sleep_ok: if true we may sleep while awaiting command completion
6141 * Returns the values of TP's CPL counters.
6143 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6146 int nchan = adap->chip_params->nchan;
6148 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6150 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6154 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6155 * @adap: the adapter
6156 * @st: holds the counter values
6158 * Returns the values of TP's RDMA counters.
6160 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6163 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6168 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6169 * @adap: the adapter
6170 * @idx: the port index
6171 * @st: holds the counter values
6172 * @sleep_ok: if true we may sleep while awaiting command completion
6174 * Returns the values of TP's FCoE counters for the selected port.
6176 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6177 struct tp_fcoe_stats *st, bool sleep_ok)
6181 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6184 t4_tp_mib_read(adap, &st->frames_drop, 1,
6185 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6187 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6190 st->octets_ddp = ((u64)val[0] << 32) | val[1];
6194 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6195 * @adap: the adapter
6196 * @st: holds the counter values
6197 * @sleep_ok: if true we may sleep while awaiting command completion
6199 * Returns the values of TP's counters for non-TCP directly-placed packets.
6201 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6206 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6208 st->frames = val[0];
6210 st->octets = ((u64)val[2] << 32) | val[3];
6214 * t4_read_mtu_tbl - returns the values in the HW path MTU table
6215 * @adap: the adapter
6216 * @mtus: where to store the MTU values
6217 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
6219 * Reads the HW path MTU table.
6221 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6226 for (i = 0; i < NMTUS; ++i) {
6227 t4_write_reg(adap, A_TP_MTU_TABLE,
6228 V_MTUINDEX(0xff) | V_MTUVALUE(i));
6229 v = t4_read_reg(adap, A_TP_MTU_TABLE);
6230 mtus[i] = G_MTUVALUE(v);
6232 mtu_log[i] = G_MTUWIDTH(v);
6237 * t4_read_cong_tbl - reads the congestion control table
6238 * @adap: the adapter
6239 * @incr: where to store the alpha values
6241 * Reads the additive increments programmed into the HW congestion
6244 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6246 unsigned int mtu, w;
6248 for (mtu = 0; mtu < NMTUS; ++mtu)
6249 for (w = 0; w < NCCTRL_WIN; ++w) {
6250 t4_write_reg(adap, A_TP_CCTRL_TABLE,
6251 V_ROWINDEX(0xffff) | (mtu << 5) | w);
6252 incr[mtu][w] = (u16)t4_read_reg(adap,
6253 A_TP_CCTRL_TABLE) & 0x1fff;
6258 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6259 * @adap: the adapter
6260 * @addr: the indirect TP register address
6261 * @mask: specifies the field within the register to modify
6262 * @val: new value for the field
6264 * Sets a field of an indirect TP register to the given value.
6266 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6267 unsigned int mask, unsigned int val)
6269 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6270 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6271 t4_write_reg(adap, A_TP_PIO_DATA, val);
6275 * init_cong_ctrl - initialize congestion control parameters
6276 * @a: the alpha values for congestion control
6277 * @b: the beta values for congestion control
6279 * Initialize the congestion control parameters.
6281 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6283 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6308 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6311 b[13] = b[14] = b[15] = b[16] = 3;
6312 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6313 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6318 /* The minimum additive increment value for the congestion control table */
6319 #define CC_MIN_INCR 2U
6322 * t4_load_mtus - write the MTU and congestion control HW tables
6323 * @adap: the adapter
6324 * @mtus: the values for the MTU table
6325 * @alpha: the values for the congestion control alpha parameter
6326 * @beta: the values for the congestion control beta parameter
6328 * Write the HW MTU table with the supplied MTUs and the high-speed
6329 * congestion control table with the supplied alpha, beta, and MTUs.
6330 * We write the two tables together because the additive increments
6331 * depend on the MTUs.
6333 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6334 const unsigned short *alpha, const unsigned short *beta)
6336 static const unsigned int avg_pkts[NCCTRL_WIN] = {
6337 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6338 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6339 28672, 40960, 57344, 81920, 114688, 163840, 229376
6344 for (i = 0; i < NMTUS; ++i) {
6345 unsigned int mtu = mtus[i];
6346 unsigned int log2 = fls(mtu);
6348 if (!(mtu & ((1 << log2) >> 2))) /* round */
6350 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6351 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6353 for (w = 0; w < NCCTRL_WIN; ++w) {
6356 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6359 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6360 (w << 16) | (beta[w] << 13) | inc);
6366 * t4_set_pace_tbl - set the pace table
6367 * @adap: the adapter
6368 * @pace_vals: the pace values in microseconds
6369 * @start: index of the first entry in the HW pace table to set
6370 * @n: how many entries to set
6372 * Sets (a subset of the) HW pace table.
6374 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6375 unsigned int start, unsigned int n)
6377 unsigned int vals[NTX_SCHED], i;
6378 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6383 /* convert values from us to dack ticks, rounding to closest value */
6384 for (i = 0; i < n; i++, pace_vals++) {
6385 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6386 if (vals[i] > 0x7ff)
6388 if (*pace_vals && vals[i] == 0)
6391 for (i = 0; i < n; i++, start++)
6392 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6397 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6398 * @adap: the adapter
6399 * @kbps: target rate in Kbps
6400 * @sched: the scheduler index
6402 * Configure a Tx HW scheduler for the target rate.
6404 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6406 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6407 unsigned int clk = adap->params.vpd.cclk * 1000;
6408 unsigned int selected_cpt = 0, selected_bpt = 0;
6411 kbps *= 125; /* -> bytes */
6412 for (cpt = 1; cpt <= 255; cpt++) {
6414 bpt = (kbps + tps / 2) / tps;
6415 if (bpt > 0 && bpt <= 255) {
6417 delta = v >= kbps ? v - kbps : kbps - v;
6418 if (delta < mindelta) {
6423 } else if (selected_cpt)
6429 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6430 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6431 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6433 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6435 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6436 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6441 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6442 * @adap: the adapter
6443 * @sched: the scheduler index
6444 * @ipg: the interpacket delay in tenths of nanoseconds
6446 * Set the interpacket delay for a HW packet rate scheduler.
6448 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6450 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6452 /* convert ipg to nearest number of core clocks */
6453 ipg *= core_ticks_per_usec(adap);
6454 ipg = (ipg + 5000) / 10000;
6455 if (ipg > M_TXTIMERSEPQ0)
6458 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6459 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6461 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6463 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6464 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6465 t4_read_reg(adap, A_TP_TM_PIO_DATA);
6470 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6471 * clocks. The formula is
6473 * bytes/s = bytes256 * 256 * ClkFreq / 4096
6475 * which is equivalent to
6477 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6479 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6481 u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6483 return v * 62 + v / 2;
6487 * t4_get_chan_txrate - get the current per channel Tx rates
6488 * @adap: the adapter
6489 * @nic_rate: rates for NIC traffic
6490 * @ofld_rate: rates for offloaded traffic
6492 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
6495 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6499 v = t4_read_reg(adap, A_TP_TX_TRATE);
6500 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6501 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6502 if (adap->chip_params->nchan > 2) {
6503 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6504 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6507 v = t4_read_reg(adap, A_TP_TX_ORATE);
6508 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6509 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6510 if (adap->chip_params->nchan > 2) {
6511 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6512 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6517 * t4_set_trace_filter - configure one of the tracing filters
6518 * @adap: the adapter
6519 * @tp: the desired trace filter parameters
6520 * @idx: which filter to configure
6521 * @enable: whether to enable or disable the filter
6523 * Configures one of the tracing filters available in HW. If @tp is %NULL
6524 * it indicates that the filter is already written in the register and it
6525 * just needs to be enabled or disabled.
6527 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6528 int idx, int enable)
6530 int i, ofst = idx * 4;
6531 u32 data_reg, mask_reg, cfg;
6532 u32 multitrc = F_TRCMULTIFILTER;
6533 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6535 if (idx < 0 || idx >= NTRACE)
6538 if (tp == NULL || !enable) {
6539 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6545 * TODO - After T4 data book is updated, specify the exact
6548 * See T4 data book - MPS section for a complete description
6549 * of the below if..else handling of A_MPS_TRC_CFG register
6552 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6553 if (cfg & F_TRCMULTIFILTER) {
6555 * If multiple tracers are enabled, then maximum
6556 * capture size is 2.5KB (FIFO size of a single channel)
6557 * minus 2 flits for CPL_TRACE_PKT header.
6559 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6563 * If multiple tracers are disabled, to avoid deadlocks
6564 * maximum packet capture size of 9600 bytes is recommended.
6565 * Also in this mode, only trace0 can be enabled and running.
6568 if (tp->snap_len > 9600 || idx)
6572 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6573 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6574 tp->min_len > M_TFMINPKTSIZE)
6577 /* stop the tracer we'll be changing */
6578 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6580 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6581 data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6582 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6584 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6585 t4_write_reg(adap, data_reg, tp->data[i]);
6586 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6588 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6589 V_TFCAPTUREMAX(tp->snap_len) |
6590 V_TFMINPKTSIZE(tp->min_len));
6591 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6592 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6594 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6595 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6601 * t4_get_trace_filter - query one of the tracing filters
6602 * @adap: the adapter
6603 * @tp: the current trace filter parameters
6604 * @idx: which trace filter to query
6605 * @enabled: non-zero if the filter is enabled
6607 * Returns the current settings of one of the HW tracing filters.
6609 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6613 int i, ofst = idx * 4;
6614 u32 data_reg, mask_reg;
6616 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6617 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6620 *enabled = !!(ctla & F_TFEN);
6621 tp->port = G_TFPORT(ctla);
6622 tp->invert = !!(ctla & F_TFINVERTMATCH);
6624 *enabled = !!(ctla & F_T5_TFEN);
6625 tp->port = G_T5_TFPORT(ctla);
6626 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6628 tp->snap_len = G_TFCAPTUREMAX(ctlb);
6629 tp->min_len = G_TFMINPKTSIZE(ctlb);
6630 tp->skip_ofst = G_TFOFFSET(ctla);
6631 tp->skip_len = G_TFLENGTH(ctla);
6633 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6634 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6635 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6637 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6638 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6639 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6644 * t4_pmtx_get_stats - returns the HW stats from PMTX
6645 * @adap: the adapter
6646 * @cnt: where to store the count statistics
6647 * @cycles: where to store the cycle statistics
6649 * Returns performance statistics from PMTX.
6651 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6656 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6657 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6658 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6660 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6662 t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6663 A_PM_TX_DBG_DATA, data, 2,
6664 A_PM_TX_DBG_STAT_MSB);
6665 cycles[i] = (((u64)data[0] << 32) | data[1]);
6671 * t4_pmrx_get_stats - returns the HW stats from PMRX
6672 * @adap: the adapter
6673 * @cnt: where to store the count statistics
6674 * @cycles: where to store the cycle statistics
6676 * Returns performance statistics from PMRX.
6678 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6683 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6684 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6685 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6687 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6689 t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6690 A_PM_RX_DBG_DATA, data, 2,
6691 A_PM_RX_DBG_STAT_MSB);
6692 cycles[i] = (((u64)data[0] << 32) | data[1]);
6698 * t4_get_mps_bg_map - return the buffer groups associated with a port
6699 * @adap: the adapter
6700 * @idx: the port index
6702 * Returns a bitmap indicating which MPS buffer groups are associated
6703 * with the given port. Bit i is set if buffer group i is used by the
6706 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6710 if (adap->params.mps_bg_map)
6711 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6713 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6715 return idx == 0 ? 0xf : 0;
6716 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6717 return idx < 2 ? (3 << (2 * idx)) : 0;
6722 * TP RX e-channels associated with the port.
6724 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6726 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6729 return idx == 0 ? 0xf : 0;
6730 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6731 return idx < 2 ? (3 << (2 * idx)) : 0;
6736 * t4_get_port_type_description - return Port Type string description
6737 * @port_type: firmware Port Type enumeration
6739 const char *t4_get_port_type_description(enum fw_port_type port_type)
6741 static const char *const port_type_description[] = {
6766 if (port_type < ARRAY_SIZE(port_type_description))
6767 return port_type_description[port_type];
6772 * t4_get_port_stats_offset - collect port stats relative to a previous
6774 * @adap: The adapter
6776 * @stats: Current stats to fill
6777 * @offset: Previous stats snapshot
6779 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6780 struct port_stats *stats,
6781 struct port_stats *offset)
6786 t4_get_port_stats(adap, idx, stats);
6787 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6788 i < (sizeof(struct port_stats)/sizeof(u64)) ;
6794 * t4_get_port_stats - collect port statistics
6795 * @adap: the adapter
6796 * @idx: the port index
6797 * @p: the stats structure to fill
6799 * Collect statistics related to the given port from HW.
6801 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6803 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6804 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6806 #define GET_STAT(name) \
6807 t4_read_reg64(adap, \
6808 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
6809 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
6810 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6812 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6813 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6814 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6815 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6816 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6817 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6818 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6819 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6820 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6821 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6822 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6823 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6824 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6825 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6826 p->tx_drop = GET_STAT(TX_PORT_DROP);
6827 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6828 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6829 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6830 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6831 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6832 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6833 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6834 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6836 if (chip_id(adap) >= CHELSIO_T5) {
6837 if (stat_ctl & F_COUNTPAUSESTATTX) {
6838 p->tx_frames -= p->tx_pause;
6839 p->tx_octets -= p->tx_pause * 64;
6841 if (stat_ctl & F_COUNTPAUSEMCTX)
6842 p->tx_mcast_frames -= p->tx_pause;
6845 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6846 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6847 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6848 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6849 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6850 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6851 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6852 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6853 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6854 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6855 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6856 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6857 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6858 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6859 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6860 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6861 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6862 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6863 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6864 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6865 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6866 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6867 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6868 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6869 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6870 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6871 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6873 if (chip_id(adap) >= CHELSIO_T5) {
6874 if (stat_ctl & F_COUNTPAUSESTATRX) {
6875 p->rx_frames -= p->rx_pause;
6876 p->rx_octets -= p->rx_pause * 64;
6878 if (stat_ctl & F_COUNTPAUSEMCRX)
6879 p->rx_mcast_frames -= p->rx_pause;
6882 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6883 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6884 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6885 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6886 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6887 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6888 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6889 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6896 * t4_get_lb_stats - collect loopback port statistics
6897 * @adap: the adapter
6898 * @idx: the loopback port index
6899 * @p: the stats structure to fill
6901 * Return HW statistics for the given loopback port.
6903 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6905 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6907 #define GET_STAT(name) \
6908 t4_read_reg64(adap, \
6910 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
6911 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
6912 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6914 p->octets = GET_STAT(BYTES);
6915 p->frames = GET_STAT(FRAMES);
6916 p->bcast_frames = GET_STAT(BCAST);
6917 p->mcast_frames = GET_STAT(MCAST);
6918 p->ucast_frames = GET_STAT(UCAST);
6919 p->error_frames = GET_STAT(ERROR);
6921 p->frames_64 = GET_STAT(64B);
6922 p->frames_65_127 = GET_STAT(65B_127B);
6923 p->frames_128_255 = GET_STAT(128B_255B);
6924 p->frames_256_511 = GET_STAT(256B_511B);
6925 p->frames_512_1023 = GET_STAT(512B_1023B);
6926 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6927 p->frames_1519_max = GET_STAT(1519B_MAX);
6928 p->drop = GET_STAT(DROP_FRAMES);
6930 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6931 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6932 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6933 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6934 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6935 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6936 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6937 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6944 * t4_wol_magic_enable - enable/disable magic packet WoL
6945 * @adap: the adapter
6946 * @port: the physical port index
6947 * @addr: MAC address expected in magic packets, %NULL to disable
6949 * Enables/disables magic packet wake-on-LAN for the selected port.
6951 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
6954 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
6957 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
6958 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
6959 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6961 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
6962 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
6963 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6967 t4_write_reg(adap, mag_id_reg_l,
6968 (addr[2] << 24) | (addr[3] << 16) |
6969 (addr[4] << 8) | addr[5]);
6970 t4_write_reg(adap, mag_id_reg_h,
6971 (addr[0] << 8) | addr[1]);
6973 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
6974 V_MAGICEN(addr != NULL));
6978 * t4_wol_pat_enable - enable/disable pattern-based WoL
6979 * @adap: the adapter
6980 * @port: the physical port index
6981 * @map: bitmap of which HW pattern filters to set
6982 * @mask0: byte mask for bytes 0-63 of a packet
6983 * @mask1: byte mask for bytes 64-127 of a packet
6984 * @crc: Ethernet CRC for selected bytes
6985 * @enable: enable/disable switch
6987 * Sets the pattern filters indicated in @map to mask out the bytes
6988 * specified in @mask0/@mask1 in received packets and compare the CRC of
6989 * the resulting packet against @crc. If @enable is %true pattern-based
6990 * WoL is enabled, otherwise disabled.
6992 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
6993 u64 mask0, u64 mask1, unsigned int crc, bool enable)
6999 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7001 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7004 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7010 #define EPIO_REG(name) \
7011 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7012 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7014 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7015 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7016 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7018 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7022 /* write byte masks */
7023 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7024 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7025 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7026 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7030 t4_write_reg(adap, EPIO_REG(DATA0), crc);
7031 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7032 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7033 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7038 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7042 /* t4_mk_filtdelwr - create a delete filter WR
7043 * @ftid: the filter ID
7044 * @wr: the filter work request to populate
7045 * @qid: ingress queue to receive the delete notification
7047 * Creates a filter work request to delete the supplied filter. If @qid is
7048 * negative the delete notification is suppressed.
7050 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7052 memset(wr, 0, sizeof(*wr));
7053 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7054 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7055 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7056 V_FW_FILTER_WR_NOREPLY(qid < 0));
7057 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7059 wr->rx_chan_rx_rpl_iq =
7060 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7063 #define INIT_CMD(var, cmd, rd_wr) do { \
7064 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7065 F_FW_CMD_REQUEST | \
7066 F_FW_CMD_##rd_wr); \
7067 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7070 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7074 struct fw_ldst_cmd c;
7076 memset(&c, 0, sizeof(c));
7077 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7078 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7082 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7083 c.u.addrval.addr = cpu_to_be32(addr);
7084 c.u.addrval.val = cpu_to_be32(val);
7086 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7090 * t4_mdio_rd - read a PHY register through MDIO
7091 * @adap: the adapter
7092 * @mbox: mailbox to use for the FW command
7093 * @phy_addr: the PHY address
7094 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7095 * @reg: the register to read
7096 * @valp: where to store the value
7098 * Issues a FW command through the given mailbox to read a PHY register.
7100 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7101 unsigned int mmd, unsigned int reg, unsigned int *valp)
7105 struct fw_ldst_cmd c;
7107 memset(&c, 0, sizeof(c));
7108 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7109 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7110 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7112 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7113 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7114 V_FW_LDST_CMD_MMD(mmd));
7115 c.u.mdio.raddr = cpu_to_be16(reg);
7117 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7119 *valp = be16_to_cpu(c.u.mdio.rval);
7124 * t4_mdio_wr - write a PHY register through MDIO
7125 * @adap: the adapter
7126 * @mbox: mailbox to use for the FW command
7127 * @phy_addr: the PHY address
7128 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7129 * @reg: the register to write
7130 * @valp: value to write
7132 * Issues a FW command through the given mailbox to write a PHY register.
7134 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7135 unsigned int mmd, unsigned int reg, unsigned int val)
7138 struct fw_ldst_cmd c;
7140 memset(&c, 0, sizeof(c));
7141 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7142 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7143 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7145 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7146 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7147 V_FW_LDST_CMD_MMD(mmd));
7148 c.u.mdio.raddr = cpu_to_be16(reg);
7149 c.u.mdio.rval = cpu_to_be16(val);
7151 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7156 * t4_sge_decode_idma_state - decode the idma state
7157 * @adap: the adapter
7158 * @state: the state idma is stuck in
7160 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7162 static const char * const t4_decode[] = {
7164 "IDMA_PUSH_MORE_CPL_FIFO",
7165 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7167 "IDMA_PHYSADDR_SEND_PCIEHDR",
7168 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7169 "IDMA_PHYSADDR_SEND_PAYLOAD",
7170 "IDMA_SEND_FIFO_TO_IMSG",
7171 "IDMA_FL_REQ_DATA_FL_PREP",
7172 "IDMA_FL_REQ_DATA_FL",
7174 "IDMA_FL_H_REQ_HEADER_FL",
7175 "IDMA_FL_H_SEND_PCIEHDR",
7176 "IDMA_FL_H_PUSH_CPL_FIFO",
7177 "IDMA_FL_H_SEND_CPL",
7178 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7179 "IDMA_FL_H_SEND_IP_HDR",
7180 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7181 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7182 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7183 "IDMA_FL_D_SEND_PCIEHDR",
7184 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7185 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7186 "IDMA_FL_SEND_PCIEHDR",
7187 "IDMA_FL_PUSH_CPL_FIFO",
7189 "IDMA_FL_SEND_PAYLOAD_FIRST",
7190 "IDMA_FL_SEND_PAYLOAD",
7191 "IDMA_FL_REQ_NEXT_DATA_FL",
7192 "IDMA_FL_SEND_NEXT_PCIEHDR",
7193 "IDMA_FL_SEND_PADDING",
7194 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7195 "IDMA_FL_SEND_FIFO_TO_IMSG",
7196 "IDMA_FL_REQ_DATAFL_DONE",
7197 "IDMA_FL_REQ_HEADERFL_DONE",
7199 static const char * const t5_decode[] = {
7202 "IDMA_PUSH_MORE_CPL_FIFO",
7203 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7204 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7205 "IDMA_PHYSADDR_SEND_PCIEHDR",
7206 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7207 "IDMA_PHYSADDR_SEND_PAYLOAD",
7208 "IDMA_SEND_FIFO_TO_IMSG",
7209 "IDMA_FL_REQ_DATA_FL",
7211 "IDMA_FL_DROP_SEND_INC",
7212 "IDMA_FL_H_REQ_HEADER_FL",
7213 "IDMA_FL_H_SEND_PCIEHDR",
7214 "IDMA_FL_H_PUSH_CPL_FIFO",
7215 "IDMA_FL_H_SEND_CPL",
7216 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7217 "IDMA_FL_H_SEND_IP_HDR",
7218 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7219 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7220 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7221 "IDMA_FL_D_SEND_PCIEHDR",
7222 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7223 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7224 "IDMA_FL_SEND_PCIEHDR",
7225 "IDMA_FL_PUSH_CPL_FIFO",
7227 "IDMA_FL_SEND_PAYLOAD_FIRST",
7228 "IDMA_FL_SEND_PAYLOAD",
7229 "IDMA_FL_REQ_NEXT_DATA_FL",
7230 "IDMA_FL_SEND_NEXT_PCIEHDR",
7231 "IDMA_FL_SEND_PADDING",
7232 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7234 static const char * const t6_decode[] = {
7236 "IDMA_PUSH_MORE_CPL_FIFO",
7237 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7238 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7239 "IDMA_PHYSADDR_SEND_PCIEHDR",
7240 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7241 "IDMA_PHYSADDR_SEND_PAYLOAD",
7242 "IDMA_FL_REQ_DATA_FL",
7244 "IDMA_FL_DROP_SEND_INC",
7245 "IDMA_FL_H_REQ_HEADER_FL",
7246 "IDMA_FL_H_SEND_PCIEHDR",
7247 "IDMA_FL_H_PUSH_CPL_FIFO",
7248 "IDMA_FL_H_SEND_CPL",
7249 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7250 "IDMA_FL_H_SEND_IP_HDR",
7251 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7252 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7253 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7254 "IDMA_FL_D_SEND_PCIEHDR",
7255 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7256 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7257 "IDMA_FL_SEND_PCIEHDR",
7258 "IDMA_FL_PUSH_CPL_FIFO",
7260 "IDMA_FL_SEND_PAYLOAD_FIRST",
7261 "IDMA_FL_SEND_PAYLOAD",
7262 "IDMA_FL_REQ_NEXT_DATA_FL",
7263 "IDMA_FL_SEND_NEXT_PCIEHDR",
7264 "IDMA_FL_SEND_PADDING",
7265 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7267 static const u32 sge_regs[] = {
7268 A_SGE_DEBUG_DATA_LOW_INDEX_2,
7269 A_SGE_DEBUG_DATA_LOW_INDEX_3,
7270 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7272 const char * const *sge_idma_decode;
7273 int sge_idma_decode_nstates;
7275 unsigned int chip_version = chip_id(adapter);
7277 /* Select the right set of decode strings to dump depending on the
7278 * adapter chip type.
7280 switch (chip_version) {
7282 sge_idma_decode = (const char * const *)t4_decode;
7283 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7287 sge_idma_decode = (const char * const *)t5_decode;
7288 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7292 sge_idma_decode = (const char * const *)t6_decode;
7293 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7297 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
7301 if (state < sge_idma_decode_nstates)
7302 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7304 CH_WARN(adapter, "idma state %d unknown\n", state);
7306 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7307 CH_WARN(adapter, "SGE register %#x value %#x\n",
7308 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7312 * t4_sge_ctxt_flush - flush the SGE context cache
7313 * @adap: the adapter
7314 * @mbox: mailbox to use for the FW command
7316 * Issues a FW command through the given mailbox to flush the
7317 * SGE context cache.
7319 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
7323 struct fw_ldst_cmd c;
7325 memset(&c, 0, sizeof(c));
7326 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
7327 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7328 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7330 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7331 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7333 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7338 * t4_fw_hello - establish communication with FW
7339 * @adap: the adapter
7340 * @mbox: mailbox to use for the FW command
7341 * @evt_mbox: mailbox to receive async FW events
7342 * @master: specifies the caller's willingness to be the device master
7343 * @state: returns the current device state (if non-NULL)
7345 * Issues a command to establish communication with FW. Returns either
7346 * an error (negative integer) or the mailbox of the Master PF.
7348 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7349 enum dev_master master, enum dev_state *state)
7352 struct fw_hello_cmd c;
7354 unsigned int master_mbox;
7355 int retries = FW_CMD_HELLO_RETRIES;
7358 memset(&c, 0, sizeof(c));
7359 INIT_CMD(c, HELLO, WRITE);
7360 c.err_to_clearinit = cpu_to_be32(
7361 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7362 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7363 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7364 mbox : M_FW_HELLO_CMD_MBMASTER) |
7365 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7366 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7367 F_FW_HELLO_CMD_CLEARINIT);
7370 * Issue the HELLO command to the firmware. If it's not successful
7371 * but indicates that we got a "busy" or "timeout" condition, retry
7372 * the HELLO until we exhaust our retry limit. If we do exceed our
7373 * retry limit, check to see if the firmware left us any error
7374 * information and report that if so ...
7376 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7377 if (ret != FW_SUCCESS) {
7378 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7380 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
7381 t4_report_fw_error(adap);
7385 v = be32_to_cpu(c.err_to_clearinit);
7386 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7388 if (v & F_FW_HELLO_CMD_ERR)
7389 *state = DEV_STATE_ERR;
7390 else if (v & F_FW_HELLO_CMD_INIT)
7391 *state = DEV_STATE_INIT;
7393 *state = DEV_STATE_UNINIT;
7397 * If we're not the Master PF then we need to wait around for the
7398 * Master PF Driver to finish setting up the adapter.
7400 * Note that we also do this wait if we're a non-Master-capable PF and
7401 * there is no current Master PF; a Master PF may show up momentarily
7402 * and we wouldn't want to fail pointlessly. (This can happen when an
7403 * OS loads lots of different drivers rapidly at the same time). In
7404 * this case, the Master PF returned by the firmware will be
7405 * M_PCIE_FW_MASTER so the test below will work ...
7407 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7408 master_mbox != mbox) {
7409 int waiting = FW_CMD_HELLO_TIMEOUT;
7412 * Wait for the firmware to either indicate an error or
7413 * initialized state. If we see either of these we bail out
7414 * and report the issue to the caller. If we exhaust the
7415 * "hello timeout" and we haven't exhausted our retries, try
7416 * again. Otherwise bail with a timeout error.
7425 * If neither Error nor Initialialized are indicated
7426 * by the firmware keep waiting till we exhaust our
7427 * timeout ... and then retry if we haven't exhausted
7430 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7431 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7442 * We either have an Error or Initialized condition
7443 * report errors preferentially.
7446 if (pcie_fw & F_PCIE_FW_ERR)
7447 *state = DEV_STATE_ERR;
7448 else if (pcie_fw & F_PCIE_FW_INIT)
7449 *state = DEV_STATE_INIT;
7453 * If we arrived before a Master PF was selected and
7454 * there's not a valid Master PF, grab its identity
7457 if (master_mbox == M_PCIE_FW_MASTER &&
7458 (pcie_fw & F_PCIE_FW_MASTER_VLD))
7459 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7468 * t4_fw_bye - end communication with FW
7469 * @adap: the adapter
7470 * @mbox: mailbox to use for the FW command
7472 * Issues a command to terminate communication with FW.
7474 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7476 struct fw_bye_cmd c;
7478 memset(&c, 0, sizeof(c));
7479 INIT_CMD(c, BYE, WRITE);
7480 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7484 * t4_fw_reset - issue a reset to FW
7485 * @adap: the adapter
7486 * @mbox: mailbox to use for the FW command
7487 * @reset: specifies the type of reset to perform
7489 * Issues a reset command of the specified type to FW.
7491 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7493 struct fw_reset_cmd c;
7495 memset(&c, 0, sizeof(c));
7496 INIT_CMD(c, RESET, WRITE);
7497 c.val = cpu_to_be32(reset);
7498 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7502 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7503 * @adap: the adapter
7504 * @mbox: mailbox to use for the FW RESET command (if desired)
7505 * @force: force uP into RESET even if FW RESET command fails
7507 * Issues a RESET command to firmware (if desired) with a HALT indication
7508 * and then puts the microprocessor into RESET state. The RESET command
7509 * will only be issued if a legitimate mailbox is provided (mbox <=
7510 * M_PCIE_FW_MASTER).
7512 * This is generally used in order for the host to safely manipulate the
7513 * adapter without fear of conflicting with whatever the firmware might
7514 * be doing. The only way out of this state is to RESTART the firmware
7517 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7522 * If a legitimate mailbox is provided, issue a RESET command
7523 * with a HALT indication.
7525 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7526 struct fw_reset_cmd c;
7528 memset(&c, 0, sizeof(c));
7529 INIT_CMD(c, RESET, WRITE);
7530 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7531 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7532 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7536 * Normally we won't complete the operation if the firmware RESET
7537 * command fails but if our caller insists we'll go ahead and put the
7538 * uP into RESET. This can be useful if the firmware is hung or even
7539 * missing ... We'll have to take the risk of putting the uP into
7540 * RESET without the cooperation of firmware in that case.
7542 * We also force the firmware's HALT flag to be on in case we bypassed
7543 * the firmware RESET command above or we're dealing with old firmware
7544 * which doesn't have the HALT capability. This will serve as a flag
7545 * for the incoming firmware to know that it's coming out of a HALT
7546 * rather than a RESET ... if it's new enough to understand that ...
7548 if (ret == 0 || force) {
7549 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7550 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7555 * And we always return the result of the firmware RESET command
7556 * even when we force the uP into RESET ...
7562 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7563 * @adap: the adapter
7565 * Restart firmware previously halted by t4_fw_halt(). On successful
7566 * return the previous PF Master remains as the new PF Master and there
7567 * is no need to issue a new HELLO command, etc.
7569 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7573 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7574 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7575 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7585 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7586 * @adap: the adapter
7587 * @mbox: mailbox to use for the FW RESET command (if desired)
7588 * @fw_data: the firmware image to write
7590 * @force: force upgrade even if firmware doesn't cooperate
7592 * Perform all of the steps necessary for upgrading an adapter's
7593 * firmware image. Normally this requires the cooperation of the
7594 * existing firmware in order to halt all existing activities
7595 * but if an invalid mailbox token is passed in we skip that step
7596 * (though we'll still put the adapter microprocessor into RESET in
7599 * On successful return the new firmware will have been loaded and
7600 * the adapter will have been fully RESET losing all previous setup
7601 * state. On unsuccessful return the adapter may be completely hosed ...
7602 * positive errno indicates that the adapter is ~probably~ intact, a
7603 * negative errno indicates that things are looking bad ...
7605 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7606 const u8 *fw_data, unsigned int size, int force)
7608 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7609 unsigned int bootstrap =
7610 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7613 if (!t4_fw_matches_chip(adap, fw_hdr))
7617 ret = t4_fw_halt(adap, mbox, force);
7618 if (ret < 0 && !force)
7622 ret = t4_load_fw(adap, fw_data, size);
7623 if (ret < 0 || bootstrap)
7626 return t4_fw_restart(adap, mbox);
7630 * t4_fw_initialize - ask FW to initialize the device
7631 * @adap: the adapter
7632 * @mbox: mailbox to use for the FW command
7634 * Issues a command to FW to partially initialize the device. This
7635 * performs initialization that generally doesn't depend on user input.
7637 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7639 struct fw_initialize_cmd c;
7641 memset(&c, 0, sizeof(c));
7642 INIT_CMD(c, INITIALIZE, WRITE);
7643 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7647 * t4_query_params_rw - query FW or device parameters
7648 * @adap: the adapter
7649 * @mbox: mailbox to use for the FW command
7652 * @nparams: the number of parameters
7653 * @params: the parameter names
7654 * @val: the parameter values
7655 * @rw: Write and read flag
7657 * Reads the value of FW or device parameters. Up to 7 parameters can be
7660 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7661 unsigned int vf, unsigned int nparams, const u32 *params,
7665 struct fw_params_cmd c;
7666 __be32 *p = &c.param[0].mnem;
7671 memset(&c, 0, sizeof(c));
7672 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7673 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7674 V_FW_PARAMS_CMD_PFN(pf) |
7675 V_FW_PARAMS_CMD_VFN(vf));
7676 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7678 for (i = 0; i < nparams; i++) {
7679 *p++ = cpu_to_be32(*params++);
7681 *p = cpu_to_be32(*(val + i));
7685 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7687 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7688 *val++ = be32_to_cpu(*p);
7692 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7693 unsigned int vf, unsigned int nparams, const u32 *params,
7696 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7700 * t4_set_params_timeout - sets FW or device parameters
7701 * @adap: the adapter
7702 * @mbox: mailbox to use for the FW command
7705 * @nparams: the number of parameters
7706 * @params: the parameter names
7707 * @val: the parameter values
7708 * @timeout: the timeout time
7710 * Sets the value of FW or device parameters. Up to 7 parameters can be
7711 * specified at once.
7713 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7714 unsigned int pf, unsigned int vf,
7715 unsigned int nparams, const u32 *params,
7716 const u32 *val, int timeout)
7718 struct fw_params_cmd c;
7719 __be32 *p = &c.param[0].mnem;
7724 memset(&c, 0, sizeof(c));
7725 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7726 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7727 V_FW_PARAMS_CMD_PFN(pf) |
7728 V_FW_PARAMS_CMD_VFN(vf));
7729 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7732 *p++ = cpu_to_be32(*params++);
7733 *p++ = cpu_to_be32(*val++);
7736 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7740 * t4_set_params - sets FW or device parameters
7741 * @adap: the adapter
7742 * @mbox: mailbox to use for the FW command
7745 * @nparams: the number of parameters
7746 * @params: the parameter names
7747 * @val: the parameter values
7749 * Sets the value of FW or device parameters. Up to 7 parameters can be
7750 * specified at once.
7752 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7753 unsigned int vf, unsigned int nparams, const u32 *params,
7756 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7757 FW_CMD_MAX_TIMEOUT);
7761 * t4_cfg_pfvf - configure PF/VF resource limits
7762 * @adap: the adapter
7763 * @mbox: mailbox to use for the FW command
7764 * @pf: the PF being configured
7765 * @vf: the VF being configured
7766 * @txq: the max number of egress queues
7767 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7768 * @rxqi: the max number of interrupt-capable ingress queues
7769 * @rxq: the max number of interruptless ingress queues
7770 * @tc: the PCI traffic class
7771 * @vi: the max number of virtual interfaces
7772 * @cmask: the channel access rights mask for the PF/VF
7773 * @pmask: the port access rights mask for the PF/VF
7774 * @nexact: the maximum number of exact MPS filters
7775 * @rcaps: read capabilities
7776 * @wxcaps: write/execute capabilities
7778 * Configures resource limits and capabilities for a physical or virtual
7781 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7782 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7783 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7784 unsigned int vi, unsigned int cmask, unsigned int pmask,
7785 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7787 struct fw_pfvf_cmd c;
7789 memset(&c, 0, sizeof(c));
7790 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7791 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7792 V_FW_PFVF_CMD_VFN(vf));
7793 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7794 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7795 V_FW_PFVF_CMD_NIQ(rxq));
7796 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7797 V_FW_PFVF_CMD_PMASK(pmask) |
7798 V_FW_PFVF_CMD_NEQ(txq));
7799 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7800 V_FW_PFVF_CMD_NVI(vi) |
7801 V_FW_PFVF_CMD_NEXACTF(nexact));
7802 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7803 V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7804 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7805 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7809 * t4_alloc_vi_func - allocate a virtual interface
7810 * @adap: the adapter
7811 * @mbox: mailbox to use for the FW command
7812 * @port: physical port associated with the VI
7813 * @pf: the PF owning the VI
7814 * @vf: the VF owning the VI
7815 * @nmac: number of MAC addresses needed (1 to 5)
7816 * @mac: the MAC addresses of the VI
7817 * @rss_size: size of RSS table slice associated with this VI
7818 * @portfunc: which Port Application Function MAC Address is desired
7819 * @idstype: Intrusion Detection Type
7821 * Allocates a virtual interface for the given physical port. If @mac is
7822 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7823 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7824 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7825 * stored consecutively so the space needed is @nmac * 6 bytes.
7826 * Returns a negative error number or the non-negative VI id.
7828 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7829 unsigned int port, unsigned int pf, unsigned int vf,
7830 unsigned int nmac, u8 *mac, u16 *rss_size,
7831 uint8_t *vfvld, uint16_t *vin,
7832 unsigned int portfunc, unsigned int idstype)
7837 memset(&c, 0, sizeof(c));
7838 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7839 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7840 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7841 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7842 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7843 V_FW_VI_CMD_FUNC(portfunc));
7844 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7847 c.norss_rsssize = F_FW_VI_CMD_NORSS;
7849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7852 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7855 memcpy(mac, c.mac, sizeof(c.mac));
7858 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7860 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7862 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7864 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7868 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7870 *vfvld = adap->params.viid_smt_extn_support ?
7871 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
7872 G_FW_VIID_VIVLD(ret);
7875 *vin = adap->params.viid_smt_extn_support ?
7876 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
7884 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7885 * @adap: the adapter
7886 * @mbox: mailbox to use for the FW command
7887 * @port: physical port associated with the VI
7888 * @pf: the PF owning the VI
7889 * @vf: the VF owning the VI
7890 * @nmac: number of MAC addresses needed (1 to 5)
7891 * @mac: the MAC addresses of the VI
7892 * @rss_size: size of RSS table slice associated with this VI
7894 * backwards compatible and convieniance routine to allocate a Virtual
7895 * Interface with a Ethernet Port Application Function and Intrustion
7896 * Detection System disabled.
7898 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7899 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7900 u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
7902 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7903 vfvld, vin, FW_VI_FUNC_ETH, 0);
7907 * t4_free_vi - free a virtual interface
7908 * @adap: the adapter
7909 * @mbox: mailbox to use for the FW command
7910 * @pf: the PF owning the VI
7911 * @vf: the VF owning the VI
7912 * @viid: virtual interface identifiler
7914 * Free a previously allocated virtual interface.
7916 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7917 unsigned int vf, unsigned int viid)
7921 memset(&c, 0, sizeof(c));
7922 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7925 V_FW_VI_CMD_PFN(pf) |
7926 V_FW_VI_CMD_VFN(vf));
7927 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7928 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7930 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7934 * t4_set_rxmode - set Rx properties of a virtual interface
7935 * @adap: the adapter
7936 * @mbox: mailbox to use for the FW command
7938 * @mtu: the new MTU or -1
7939 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7940 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7941 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7942 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7943 * @sleep_ok: if true we may sleep while awaiting command completion
7945 * Sets Rx properties of a virtual interface.
7947 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7948 int mtu, int promisc, int all_multi, int bcast, int vlanex,
7951 struct fw_vi_rxmode_cmd c;
7953 /* convert to FW values */
7955 mtu = M_FW_VI_RXMODE_CMD_MTU;
7957 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
7959 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
7961 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
7963 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
7965 memset(&c, 0, sizeof(c));
7966 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
7967 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7968 V_FW_VI_RXMODE_CMD_VIID(viid));
7969 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7971 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
7972 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
7973 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
7974 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
7975 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
7976 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7980 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7981 * @adap: the adapter
7982 * @mbox: mailbox to use for the FW command
7984 * @free: if true any existing filters for this VI id are first removed
7985 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7986 * @addr: the MAC address(es)
7987 * @idx: where to store the index of each allocated filter
7988 * @hash: pointer to hash address filter bitmap
7989 * @sleep_ok: call is allowed to sleep
7991 * Allocates an exact-match filter for each of the supplied addresses and
7992 * sets it to the corresponding address. If @idx is not %NULL it should
7993 * have at least @naddr entries, each of which will be set to the index of
7994 * the filter allocated for the corresponding MAC address. If a filter
7995 * could not be allocated for an address its index is set to 0xffff.
7996 * If @hash is not %NULL addresses that fail to allocate an exact filter
7997 * are hashed and update the hash filter bitmap pointed at by @hash.
7999 * Returns a negative error number or the number of filters allocated.
8001 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8002 unsigned int viid, bool free, unsigned int naddr,
8003 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8005 int offset, ret = 0;
8006 struct fw_vi_mac_cmd c;
8007 unsigned int nfilters = 0;
8008 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8009 unsigned int rem = naddr;
8011 if (naddr > max_naddr)
8014 for (offset = 0; offset < naddr ; /**/) {
8015 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8017 : ARRAY_SIZE(c.u.exact));
8018 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8019 u.exact[fw_naddr]), 16);
8020 struct fw_vi_mac_exact *p;
8023 memset(&c, 0, sizeof(c));
8024 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8027 V_FW_CMD_EXEC(free) |
8028 V_FW_VI_MAC_CMD_VIID(viid));
8029 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8030 V_FW_CMD_LEN16(len16));
8032 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8034 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8035 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8036 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8040 * It's okay if we run out of space in our MAC address arena.
8041 * Some of the addresses we submit may get stored so we need
8042 * to run through the reply to see what the results were ...
8044 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8045 if (ret && ret != -FW_ENOMEM)
8048 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8049 u16 index = G_FW_VI_MAC_CMD_IDX(
8050 be16_to_cpu(p->valid_to_idx));
8053 idx[offset+i] = (index >= max_naddr
8056 if (index < max_naddr)
8059 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8067 if (ret == 0 || ret == -FW_ENOMEM)
8073 * t4_change_mac - modifies the exact-match filter for a MAC address
8074 * @adap: the adapter
8075 * @mbox: mailbox to use for the FW command
8077 * @idx: index of existing filter for old value of MAC address, or -1
8078 * @addr: the new MAC address value
8079 * @persist: whether a new MAC allocation should be persistent
8080 * @smt_idx: add MAC to SMT and return its index, or NULL
8082 * Modifies an exact-match filter and sets it to the new MAC address if
8083 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
8084 * latter case the address is added persistently if @persist is %true.
8086 * Note that in general it is not possible to modify the value of a given
8087 * filter so the generic way to modify an address filter is to free the one
8088 * being used by the old address value and allocate a new filter for the
8089 * new address value.
8091 * Returns a negative error number or the index of the filter with the new
8092 * MAC value. Note that this index may differ from @idx.
8094 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8095 int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8098 struct fw_vi_mac_cmd c;
8099 struct fw_vi_mac_exact *p = c.u.exact;
8100 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8102 if (idx < 0) /* new allocation */
8103 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8104 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8106 memset(&c, 0, sizeof(c));
8107 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8108 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8109 V_FW_VI_MAC_CMD_VIID(viid));
8110 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8111 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8112 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8113 V_FW_VI_MAC_CMD_IDX(idx));
8114 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8116 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8118 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8119 if (ret >= max_mac_addr)
8122 if (adap->params.viid_smt_extn_support)
8123 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8125 if (chip_id(adap) <= CHELSIO_T5)
8126 *smt_idx = (viid & M_FW_VIID_VIN) << 1;
8128 *smt_idx = viid & M_FW_VIID_VIN;
8136 * t4_set_addr_hash - program the MAC inexact-match hash filter
8137 * @adap: the adapter
8138 * @mbox: mailbox to use for the FW command
8140 * @ucast: whether the hash filter should also match unicast addresses
8141 * @vec: the value to be written to the hash filter
8142 * @sleep_ok: call is allowed to sleep
8144 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8146 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8147 bool ucast, u64 vec, bool sleep_ok)
8149 struct fw_vi_mac_cmd c;
8152 memset(&c, 0, sizeof(c));
8153 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8154 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8155 V_FW_VI_ENABLE_CMD_VIID(viid));
8156 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8157 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8158 c.freemacs_to_len16 = cpu_to_be32(val);
8159 c.u.hash.hashvec = cpu_to_be64(vec);
8160 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8164 * t4_enable_vi_params - enable/disable a virtual interface
8165 * @adap: the adapter
8166 * @mbox: mailbox to use for the FW command
8168 * @rx_en: 1=enable Rx, 0=disable Rx
8169 * @tx_en: 1=enable Tx, 0=disable Tx
8170 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8172 * Enables/disables a virtual interface. Note that setting DCB Enable
8173 * only makes sense when enabling a Virtual Interface ...
8175 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8176 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8178 struct fw_vi_enable_cmd c;
8180 memset(&c, 0, sizeof(c));
8181 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8182 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8183 V_FW_VI_ENABLE_CMD_VIID(viid));
8184 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8185 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8186 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8188 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8192 * t4_enable_vi - enable/disable a virtual interface
8193 * @adap: the adapter
8194 * @mbox: mailbox to use for the FW command
8196 * @rx_en: 1=enable Rx, 0=disable Rx
8197 * @tx_en: 1=enable Tx, 0=disable Tx
8199 * Enables/disables a virtual interface. Note that setting DCB Enable
8200 * only makes sense when enabling a Virtual Interface ...
8202 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8203 bool rx_en, bool tx_en)
8205 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8209 * t4_identify_port - identify a VI's port by blinking its LED
8210 * @adap: the adapter
8211 * @mbox: mailbox to use for the FW command
8213 * @nblinks: how many times to blink LED at 2.5 Hz
8215 * Identifies a VI's port by blinking its LED.
8217 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8218 unsigned int nblinks)
8220 struct fw_vi_enable_cmd c;
8222 memset(&c, 0, sizeof(c));
8223 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8224 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8225 V_FW_VI_ENABLE_CMD_VIID(viid));
8226 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8227 c.blinkdur = cpu_to_be16(nblinks);
8228 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8232 * t4_iq_stop - stop an ingress queue and its FLs
8233 * @adap: the adapter
8234 * @mbox: mailbox to use for the FW command
8235 * @pf: the PF owning the queues
8236 * @vf: the VF owning the queues
8237 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8238 * @iqid: ingress queue id
8239 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8240 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8242 * Stops an ingress queue and its associated FLs, if any. This causes
8243 * any current or future data/messages destined for these queues to be
8246 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8247 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8248 unsigned int fl0id, unsigned int fl1id)
8252 memset(&c, 0, sizeof(c));
8253 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8254 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8255 V_FW_IQ_CMD_VFN(vf));
8256 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8257 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8258 c.iqid = cpu_to_be16(iqid);
8259 c.fl0id = cpu_to_be16(fl0id);
8260 c.fl1id = cpu_to_be16(fl1id);
8261 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8265 * t4_iq_free - free an ingress queue and its FLs
8266 * @adap: the adapter
8267 * @mbox: mailbox to use for the FW command
8268 * @pf: the PF owning the queues
8269 * @vf: the VF owning the queues
8270 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8271 * @iqid: ingress queue id
8272 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8273 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8275 * Frees an ingress queue and its associated FLs, if any.
8277 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8278 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8279 unsigned int fl0id, unsigned int fl1id)
8283 memset(&c, 0, sizeof(c));
8284 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8285 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8286 V_FW_IQ_CMD_VFN(vf));
8287 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8288 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8289 c.iqid = cpu_to_be16(iqid);
8290 c.fl0id = cpu_to_be16(fl0id);
8291 c.fl1id = cpu_to_be16(fl1id);
8292 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8296 * t4_eth_eq_free - free an Ethernet egress queue
8297 * @adap: the adapter
8298 * @mbox: mailbox to use for the FW command
8299 * @pf: the PF owning the queue
8300 * @vf: the VF owning the queue
8301 * @eqid: egress queue id
8303 * Frees an Ethernet egress queue.
8305 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8306 unsigned int vf, unsigned int eqid)
8308 struct fw_eq_eth_cmd c;
8310 memset(&c, 0, sizeof(c));
8311 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8312 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8313 V_FW_EQ_ETH_CMD_PFN(pf) |
8314 V_FW_EQ_ETH_CMD_VFN(vf));
8315 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8316 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8317 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8321 * t4_ctrl_eq_free - free a control egress queue
8322 * @adap: the adapter
8323 * @mbox: mailbox to use for the FW command
8324 * @pf: the PF owning the queue
8325 * @vf: the VF owning the queue
8326 * @eqid: egress queue id
8328 * Frees a control egress queue.
8330 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8331 unsigned int vf, unsigned int eqid)
8333 struct fw_eq_ctrl_cmd c;
8335 memset(&c, 0, sizeof(c));
8336 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8337 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8338 V_FW_EQ_CTRL_CMD_PFN(pf) |
8339 V_FW_EQ_CTRL_CMD_VFN(vf));
8340 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8341 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8342 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8346 * t4_ofld_eq_free - free an offload egress queue
8347 * @adap: the adapter
8348 * @mbox: mailbox to use for the FW command
8349 * @pf: the PF owning the queue
8350 * @vf: the VF owning the queue
8351 * @eqid: egress queue id
8353 * Frees a control egress queue.
8355 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8356 unsigned int vf, unsigned int eqid)
8358 struct fw_eq_ofld_cmd c;
8360 memset(&c, 0, sizeof(c));
8361 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8362 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8363 V_FW_EQ_OFLD_CMD_PFN(pf) |
8364 V_FW_EQ_OFLD_CMD_VFN(vf));
8365 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8366 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8367 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8371 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8372 * @link_down_rc: Link Down Reason Code
8374 * Returns a string representation of the Link Down Reason Code.
8376 const char *t4_link_down_rc_str(unsigned char link_down_rc)
8378 static const char *reason[] = {
8381 "Auto-negotiation Failure",
8383 "Insufficient Airflow",
8384 "Unable To Determine Reason",
8385 "No RX Signal Detected",
8389 if (link_down_rc >= ARRAY_SIZE(reason))
8390 return "Bad Reason Code";
8392 return reason[link_down_rc];
8396 * Return the highest speed set in the port capabilities, in Mb/s.
8398 unsigned int fwcap_to_speed(uint32_t caps)
8400 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8402 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8406 TEST_SPEED_RETURN(400G, 400000);
8407 TEST_SPEED_RETURN(200G, 200000);
8408 TEST_SPEED_RETURN(100G, 100000);
8409 TEST_SPEED_RETURN(50G, 50000);
8410 TEST_SPEED_RETURN(40G, 40000);
8411 TEST_SPEED_RETURN(25G, 25000);
8412 TEST_SPEED_RETURN(10G, 10000);
8413 TEST_SPEED_RETURN(1G, 1000);
8414 TEST_SPEED_RETURN(100M, 100);
8416 #undef TEST_SPEED_RETURN
8422 * Return the port capabilities bit for the given speed, which is in Mb/s.
8424 uint32_t speed_to_fwcap(unsigned int speed)
8426 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8428 if (speed == __speed) \
8429 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8432 TEST_SPEED_RETURN(400G, 400000);
8433 TEST_SPEED_RETURN(200G, 200000);
8434 TEST_SPEED_RETURN(100G, 100000);
8435 TEST_SPEED_RETURN(50G, 50000);
8436 TEST_SPEED_RETURN(40G, 40000);
8437 TEST_SPEED_RETURN(25G, 25000);
8438 TEST_SPEED_RETURN(10G, 10000);
8439 TEST_SPEED_RETURN(1G, 1000);
8440 TEST_SPEED_RETURN(100M, 100);
8442 #undef TEST_SPEED_RETURN
8448 * Return the port capabilities bit for the highest speed in the capabilities.
8450 uint32_t fwcap_top_speed(uint32_t caps)
8452 #define TEST_SPEED_RETURN(__caps_speed) \
8454 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8455 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8458 TEST_SPEED_RETURN(400G);
8459 TEST_SPEED_RETURN(200G);
8460 TEST_SPEED_RETURN(100G);
8461 TEST_SPEED_RETURN(50G);
8462 TEST_SPEED_RETURN(40G);
8463 TEST_SPEED_RETURN(25G);
8464 TEST_SPEED_RETURN(10G);
8465 TEST_SPEED_RETURN(1G);
8466 TEST_SPEED_RETURN(100M);
8468 #undef TEST_SPEED_RETURN
8475 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8476 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8478 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8479 * 32-bit Port Capabilities value.
8481 static uint32_t lstatus_to_fwcap(u32 lstatus)
8483 uint32_t linkattr = 0;
8486 * Unfortunately the format of the Link Status in the old
8487 * 16-bit Port Information message isn't the same as the
8488 * 16-bit Port Capabilities bitfield used everywhere else ...
8490 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8491 linkattr |= FW_PORT_CAP32_FC_RX;
8492 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8493 linkattr |= FW_PORT_CAP32_FC_TX;
8494 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8495 linkattr |= FW_PORT_CAP32_SPEED_100M;
8496 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8497 linkattr |= FW_PORT_CAP32_SPEED_1G;
8498 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8499 linkattr |= FW_PORT_CAP32_SPEED_10G;
8500 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8501 linkattr |= FW_PORT_CAP32_SPEED_25G;
8502 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8503 linkattr |= FW_PORT_CAP32_SPEED_40G;
8504 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8505 linkattr |= FW_PORT_CAP32_SPEED_100G;
8511 * Updates all fields owned by the common code in port_info and link_config
8512 * based on information provided by the firmware. Does not touch any
8513 * requested_* field.
8515 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8516 enum fw_port_action action, bool *mod_changed, bool *link_changed)
8518 struct link_config old_lc, *lc = &pi->link_cfg;
8519 unsigned char fc, fec;
8521 int old_ptype, old_mtype;
8523 old_ptype = pi->port_type;
8524 old_mtype = pi->mod_type;
8526 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8527 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8529 pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8530 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8531 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8532 G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8534 lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8535 lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8536 lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8537 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8538 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8540 linkattr = lstatus_to_fwcap(stat);
8541 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8542 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8544 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8545 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8546 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8547 G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8549 lc->supported = be32_to_cpu(p->u.info32.pcaps32);
8550 lc->advertising = be32_to_cpu(p->u.info32.acaps32);
8551 lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32);
8552 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8553 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8555 linkattr = be32_to_cpu(p->u.info32.linkattr32);
8557 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8561 lc->speed = fwcap_to_speed(linkattr);
8564 if (linkattr & FW_PORT_CAP32_FC_RX)
8566 if (linkattr & FW_PORT_CAP32_FC_TX)
8571 if (linkattr & FW_PORT_CAP32_FEC_RS)
8573 if (linkattr & FW_PORT_CAP32_FEC_BASER_RS)
8574 fec |= FEC_BASER_RS;
8577 if (mod_changed != NULL)
8578 *mod_changed = false;
8579 if (link_changed != NULL)
8580 *link_changed = false;
8581 if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
8582 old_lc.supported != lc->supported) {
8583 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
8584 lc->fec_hint = lc->advertising &
8585 V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
8587 if (mod_changed != NULL)
8588 *mod_changed = true;
8590 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
8591 old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
8592 if (link_changed != NULL)
8593 *link_changed = true;
8598 * t4_update_port_info - retrieve and update port information if changed
8599 * @pi: the port_info
8601 * We issue a Get Port Information Command to the Firmware and, if
8602 * successful, we check to see if anything is different from what we
8603 * last recorded and update things accordingly.
8605 int t4_update_port_info(struct port_info *pi)
8607 struct adapter *sc = pi->adapter;
8608 struct fw_port_cmd cmd;
8609 enum fw_port_action action;
8612 memset(&cmd, 0, sizeof(cmd));
8613 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
8614 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8615 V_FW_PORT_CMD_PORTID(pi->tx_chan));
8616 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
8617 FW_PORT_ACTION_GET_PORT_INFO;
8618 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
8620 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
8624 handle_port_info(pi, &cmd, action, NULL, NULL);
8629 * t4_handle_fw_rpl - process a FW reply message
8630 * @adap: the adapter
8631 * @rpl: start of the FW message
8633 * Processes a FW message, such as link state change messages.
8635 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8637 u8 opcode = *(const u8 *)rpl;
8638 const struct fw_port_cmd *p = (const void *)rpl;
8639 enum fw_port_action action =
8640 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
8641 bool mod_changed, link_changed;
8643 if (opcode == FW_PORT_CMD &&
8644 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8645 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8646 /* link/module state change message */
8648 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
8649 struct port_info *pi = NULL;
8650 struct link_config *lc;
8652 for_each_port(adap, i) {
8653 pi = adap2pinfo(adap, i);
8654 if (pi->tx_chan == chan)
8660 handle_port_info(pi, p, action, &mod_changed, &link_changed);
8663 t4_os_portmod_changed(pi);
8666 t4_os_link_changed(pi);
8670 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
8677 * get_pci_mode - determine a card's PCI mode
8678 * @adapter: the adapter
8679 * @p: where to store the PCI settings
8681 * Determines a card's PCI mode and associated parameters, such as speed
8684 static void get_pci_mode(struct adapter *adapter,
8685 struct pci_params *p)
8690 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8692 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
8693 p->speed = val & PCI_EXP_LNKSTA_CLS;
8694 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8699 u32 vendor_and_model_id;
8703 int t4_get_flash_params(struct adapter *adapter)
8706 * Table for non-standard supported Flash parts. Note, all Flash
8707 * parts must have 64KB sectors.
8709 static struct flash_desc supported_flash[] = {
8710 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8715 unsigned int part, manufacturer;
8716 unsigned int density, size = 0;
8720 * Issue a Read ID Command to the Flash part. We decode supported
8721 * Flash parts and their sizes from this. There's a newer Query
8722 * Command which can retrieve detailed geometry information but many
8723 * Flash parts don't support it.
8725 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
8727 ret = sf1_read(adapter, 3, 0, 1, &flashid);
8728 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
8733 * Check to see if it's one of our non-standard supported Flash parts.
8735 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8736 if (supported_flash[part].vendor_and_model_id == flashid) {
8737 adapter->params.sf_size =
8738 supported_flash[part].size_mb;
8739 adapter->params.sf_nsec =
8740 adapter->params.sf_size / SF_SEC_SIZE;
8745 * Decode Flash part size. The code below looks repetative with
8746 * common encodings, but that's not guaranteed in the JEDEC
8747 * specification for the Read JADEC ID command. The only thing that
8748 * we're guaranteed by the JADEC specification is where the
8749 * Manufacturer ID is in the returned result. After that each
8750 * Manufacturer ~could~ encode things completely differently.
8751 * Note, all Flash parts must have 64KB sectors.
8753 manufacturer = flashid & 0xff;
8754 switch (manufacturer) {
8755 case 0x20: /* Micron/Numonix */
8757 * This Density -> Size decoding table is taken from Micron
8760 density = (flashid >> 16) & 0xff;
8762 case 0x14: size = 1 << 20; break; /* 1MB */
8763 case 0x15: size = 1 << 21; break; /* 2MB */
8764 case 0x16: size = 1 << 22; break; /* 4MB */
8765 case 0x17: size = 1 << 23; break; /* 8MB */
8766 case 0x18: size = 1 << 24; break; /* 16MB */
8767 case 0x19: size = 1 << 25; break; /* 32MB */
8768 case 0x20: size = 1 << 26; break; /* 64MB */
8769 case 0x21: size = 1 << 27; break; /* 128MB */
8770 case 0x22: size = 1 << 28; break; /* 256MB */
8774 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
8776 * This Density -> Size decoding table is taken from ISSI
8779 density = (flashid >> 16) & 0xff;
8781 case 0x16: size = 1 << 25; break; /* 32MB */
8782 case 0x17: size = 1 << 26; break; /* 64MB */
8786 case 0xc2: /* Macronix */
8788 * This Density -> Size decoding table is taken from Macronix
8791 density = (flashid >> 16) & 0xff;
8793 case 0x17: size = 1 << 23; break; /* 8MB */
8794 case 0x18: size = 1 << 24; break; /* 16MB */
8798 case 0xef: /* Winbond */
8800 * This Density -> Size decoding table is taken from Winbond
8803 density = (flashid >> 16) & 0xff;
8805 case 0x17: size = 1 << 23; break; /* 8MB */
8806 case 0x18: size = 1 << 24; break; /* 16MB */
8811 /* If we didn't recognize the FLASH part, that's no real issue: the
8812 * Hardware/Software contract says that Hardware will _*ALWAYS*_
8813 * use a FLASH part which is at least 4MB in size and has 64KB
8814 * sectors. The unrecognized FLASH part is likely to be much larger
8815 * than 4MB, but that's all we really need.
8818 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
8823 * Store decoded Flash size and fall through into vetting code.
8825 adapter->params.sf_size = size;
8826 adapter->params.sf_nsec = size / SF_SEC_SIZE;
8830 * We should ~probably~ reject adapters with FLASHes which are too
8831 * small but we have some legacy FPGAs with small FLASHes that we'd
8832 * still like to use. So instead we emit a scary message ...
8834 if (adapter->params.sf_size < FLASH_MIN_SIZE)
8835 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8836 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
8841 static void set_pcie_completion_timeout(struct adapter *adapter,
8847 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8849 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
8852 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
8856 const struct chip_params *t4_get_chip_params(int chipid)
8858 static const struct chip_params chip_params[] = {
8862 .pm_stats_cnt = PM_NSTATS,
8863 .cng_ch_bits_log = 2,
8865 .cim_num_obq = CIM_NUM_OBQ,
8866 .mps_rplc_size = 128,
8868 .sge_fl_db = F_DBPRIO,
8869 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
8874 .pm_stats_cnt = PM_NSTATS,
8875 .cng_ch_bits_log = 2,
8877 .cim_num_obq = CIM_NUM_OBQ_T5,
8878 .mps_rplc_size = 128,
8880 .sge_fl_db = F_DBPRIO | F_DBTYPE,
8881 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8886 .pm_stats_cnt = T6_PM_NSTATS,
8887 .cng_ch_bits_log = 3,
8889 .cim_num_obq = CIM_NUM_OBQ_T5,
8890 .mps_rplc_size = 256,
8893 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8897 chipid -= CHELSIO_T4;
8898 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
8901 return &chip_params[chipid];
8905 * t4_prep_adapter - prepare SW and HW for operation
8906 * @adapter: the adapter
8907 * @buf: temporary space of at least VPD_LEN size provided by the caller.
8909 * Initialize adapter SW state for the various HW modules, set initial
8910 * values for some adapter tunables, take PHYs out of reset, and
8911 * initialize the MDIO interface.
8913 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
8919 get_pci_mode(adapter, &adapter->params.pci);
8921 pl_rev = t4_read_reg(adapter, A_PL_REV);
8922 adapter->params.chipid = G_CHIPID(pl_rev);
8923 adapter->params.rev = G_REV(pl_rev);
8924 if (adapter->params.chipid == 0) {
8925 /* T4 did not have chipid in PL_REV (T5 onwards do) */
8926 adapter->params.chipid = CHELSIO_T4;
8928 /* T4A1 chip is not supported */
8929 if (adapter->params.rev == 1) {
8930 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
8935 adapter->chip_params = t4_get_chip_params(chip_id(adapter));
8936 if (adapter->chip_params == NULL)
8939 adapter->params.pci.vpd_cap_addr =
8940 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
8942 ret = t4_get_flash_params(adapter);
8946 /* Cards with real ASICs have the chipid in the PCIe device id */
8947 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
8948 if (device_id >> 12 == chip_id(adapter))
8949 adapter->params.cim_la_size = CIMLA_SIZE;
8952 adapter->params.fpga = 1;
8953 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
8956 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
8960 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8963 * Default port and clock for debugging in case we can't reach FW.
8965 adapter->params.nports = 1;
8966 adapter->params.portvec = 1;
8967 adapter->params.vpd.cclk = 50000;
8969 /* Set pci completion timeout value to 4 seconds. */
8970 set_pcie_completion_timeout(adapter, 0xd);
8975 * t4_shutdown_adapter - shut down adapter, host & wire
8976 * @adapter: the adapter
8978 * Perform an emergency shutdown of the adapter and stop it from
8979 * continuing any further communication on the ports or DMA to the
8980 * host. This is typically used when the adapter and/or firmware
8981 * have crashed and we want to prevent any further accidental
8982 * communication with the rest of the world. This will also force
8983 * the port Link Status to go down -- if register writes work --
8984 * which should help our peers figure out that we're down.
8986 int t4_shutdown_adapter(struct adapter *adapter)
8990 t4_intr_disable(adapter);
8991 t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
8992 for_each_port(adapter, port) {
8993 u32 a_port_cfg = is_t4(adapter) ?
8994 PORT_REG(port, A_XGMAC_PORT_CFG) :
8995 T5_PORT_REG(port, A_MAC_PORT_CFG);
8997 t4_write_reg(adapter, a_port_cfg,
8998 t4_read_reg(adapter, a_port_cfg)
8999 & ~V_SIGNAL_DET(1));
9001 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9007 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9008 * @adapter: the adapter
9009 * @qid: the Queue ID
9010 * @qtype: the Ingress or Egress type for @qid
9011 * @user: true if this request is for a user mode queue
9012 * @pbar2_qoffset: BAR2 Queue Offset
9013 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9015 * Returns the BAR2 SGE Queue Registers information associated with the
9016 * indicated Absolute Queue ID. These are passed back in return value
9017 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9018 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9020 * This may return an error which indicates that BAR2 SGE Queue
9021 * registers aren't available. If an error is not returned, then the
9022 * following values are returned:
9024 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9025 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9027 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9028 * require the "Inferred Queue ID" ability may be used. E.g. the
9029 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9030 * then these "Inferred Queue ID" register may not be used.
9032 int t4_bar2_sge_qregs(struct adapter *adapter,
9034 enum t4_bar2_qtype qtype,
9037 unsigned int *pbar2_qid)
9039 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9040 u64 bar2_page_offset, bar2_qoffset;
9041 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9043 /* T4 doesn't support BAR2 SGE Queue registers for kernel
9046 if (!user && is_t4(adapter))
9049 /* Get our SGE Page Size parameters.
9051 page_shift = adapter->params.sge.page_shift;
9052 page_size = 1 << page_shift;
9054 /* Get the right Queues per Page parameters for our Queue.
9056 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9057 ? adapter->params.sge.eq_s_qpp
9058 : adapter->params.sge.iq_s_qpp);
9059 qpp_mask = (1 << qpp_shift) - 1;
9061 /* Calculate the basics of the BAR2 SGE Queue register area:
9062 * o The BAR2 page the Queue registers will be in.
9063 * o The BAR2 Queue ID.
9064 * o The BAR2 Queue ID Offset into the BAR2 page.
9066 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9067 bar2_qid = qid & qpp_mask;
9068 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9070 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9071 * hardware will infer the Absolute Queue ID simply from the writes to
9072 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9073 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9074 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9075 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9076 * from the BAR2 Page and BAR2 Queue ID.
9078 * One important censequence of this is that some BAR2 SGE registers
9079 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9080 * there. But other registers synthesize the SGE Queue ID purely
9081 * from the writes to the registers -- the Write Combined Doorbell
9082 * Buffer is a good example. These BAR2 SGE Registers are only
9083 * available for those BAR2 SGE Register areas where the SGE Absolute
9084 * Queue ID can be inferred from simple writes.
9086 bar2_qoffset = bar2_page_offset;
9087 bar2_qinferred = (bar2_qid_offset < page_size);
9088 if (bar2_qinferred) {
9089 bar2_qoffset += bar2_qid_offset;
9093 *pbar2_qoffset = bar2_qoffset;
9094 *pbar2_qid = bar2_qid;
9099 * t4_init_devlog_params - initialize adapter->params.devlog
9100 * @adap: the adapter
9101 * @fw_attach: whether we can talk to the firmware
9103 * Initialize various fields of the adapter's Firmware Device Log
9104 * Parameters structure.
9106 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9108 struct devlog_params *dparams = &adap->params.devlog;
9110 unsigned int devlog_meminfo;
9111 struct fw_devlog_cmd devlog_cmd;
9114 /* If we're dealing with newer firmware, the Device Log Paramerters
9115 * are stored in a designated register which allows us to access the
9116 * Device Log even if we can't talk to the firmware.
9119 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9121 unsigned int nentries, nentries128;
9123 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9124 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9126 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9127 nentries = (nentries128 + 1) * 128;
9128 dparams->size = nentries * sizeof(struct fw_devlog_e);
9134 * For any failing returns ...
9136 memset(dparams, 0, sizeof *dparams);
9139 * If we can't talk to the firmware, there's really nothing we can do
9145 /* Otherwise, ask the firmware for it's Device Log Parameters.
9147 memset(&devlog_cmd, 0, sizeof devlog_cmd);
9148 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9149 F_FW_CMD_REQUEST | F_FW_CMD_READ);
9150 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9151 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9157 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9158 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9159 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9160 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9166 * t4_init_sge_params - initialize adap->params.sge
9167 * @adapter: the adapter
9169 * Initialize various fields of the adapter's SGE Parameters structure.
9171 int t4_init_sge_params(struct adapter *adapter)
9174 struct sge_params *sp = &adapter->params.sge;
9175 unsigned i, tscale = 1;
9177 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9178 sp->counter_val[0] = G_THRESHOLD_0(r);
9179 sp->counter_val[1] = G_THRESHOLD_1(r);
9180 sp->counter_val[2] = G_THRESHOLD_2(r);
9181 sp->counter_val[3] = G_THRESHOLD_3(r);
9183 if (chip_id(adapter) >= CHELSIO_T6) {
9184 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9185 tscale = G_TSCALE(r);
9192 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9193 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9194 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9195 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9196 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9197 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9198 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9199 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9200 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9202 r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9203 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9205 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9206 else if (is_t5(adapter))
9207 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9209 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9211 /* egress queues: log2 of # of doorbells per BAR2 page */
9212 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9213 r >>= S_QUEUESPERPAGEPF0 +
9214 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9215 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9217 /* ingress queues: log2 of # of doorbells per BAR2 page */
9218 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9219 r >>= S_QUEUESPERPAGEPF0 +
9220 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9221 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9223 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9224 r >>= S_HOSTPAGESIZEPF0 +
9225 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9226 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9228 r = t4_read_reg(adapter, A_SGE_CONTROL);
9229 sp->sge_control = r;
9230 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9231 sp->fl_pktshift = G_PKTSHIFT(r);
9232 if (chip_id(adapter) <= CHELSIO_T5) {
9233 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9234 X_INGPADBOUNDARY_SHIFT);
9236 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9237 X_T6_INGPADBOUNDARY_SHIFT);
9240 sp->pack_boundary = sp->pad_boundary;
9242 r = t4_read_reg(adapter, A_SGE_CONTROL2);
9243 if (G_INGPACKBOUNDARY(r) == 0)
9244 sp->pack_boundary = 16;
9246 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9248 for (i = 0; i < SGE_FLBUF_SIZES; i++)
9249 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9250 A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9256 * Read and cache the adapter's compressed filter mode and ingress config.
9258 static void read_filter_mode_and_ingress_config(struct adapter *adap,
9262 struct tp_params *tpp = &adap->params.tp;
9264 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP,
9266 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG,
9270 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9271 * shift positions of several elements of the Compressed Filter Tuple
9272 * for this adapter which we need frequently ...
9274 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9275 tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9276 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9277 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9278 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9279 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9280 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9281 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9282 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9283 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9285 if (chip_id(adap) > CHELSIO_T4) {
9286 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9287 adap->params.tp.hash_filter_mask = v;
9288 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9289 adap->params.tp.hash_filter_mask |= (u64)v << 32;
9294 * t4_init_tp_params - initialize adap->params.tp
9295 * @adap: the adapter
9297 * Initialize various fields of the adapter's TP Parameters structure.
9299 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9303 struct tp_params *tpp = &adap->params.tp;
9305 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9306 tpp->tre = G_TIMERRESOLUTION(v);
9307 tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9309 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9310 for (chan = 0; chan < MAX_NCHAN; chan++)
9311 tpp->tx_modq[chan] = chan;
9313 read_filter_mode_and_ingress_config(adap, sleep_ok);
9316 * Cache a mask of the bits that represent the error vector portion of
9317 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room
9318 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
9320 tpp->err_vec_mask = htobe16(0xffff);
9321 if (chip_id(adap) > CHELSIO_T5) {
9322 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9323 if (v & F_CRXPKTENC) {
9325 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
9333 * t4_filter_field_shift - calculate filter field shift
9334 * @adap: the adapter
9335 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9337 * Return the shift position of a filter field within the Compressed
9338 * Filter Tuple. The filter field is specified via its selection bit
9339 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9341 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9343 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9347 if ((filter_mode & filter_sel) == 0)
9350 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9351 switch (filter_mode & sel) {
9353 field_shift += W_FT_FCOE;
9356 field_shift += W_FT_PORT;
9359 field_shift += W_FT_VNIC_ID;
9362 field_shift += W_FT_VLAN;
9365 field_shift += W_FT_TOS;
9368 field_shift += W_FT_PROTOCOL;
9371 field_shift += W_FT_ETHERTYPE;
9374 field_shift += W_FT_MACMATCH;
9377 field_shift += W_FT_MPSHITTYPE;
9379 case F_FRAGMENTATION:
9380 field_shift += W_FT_FRAGMENTATION;
9387 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9391 struct port_info *p = adap2pinfo(adap, port_id);
9393 struct vi_info *vi = &p->vi[0];
9395 for (i = 0, j = -1; i <= p->port_id; i++) {
9398 } while ((adap->params.portvec & (1 << j)) == 0);
9402 p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9403 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9406 if (!(adap->flags & IS_VF) ||
9407 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9408 t4_update_port_info(p);
9411 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9412 &vi->vfvld, &vi->vin);
9417 t4_os_set_hw_addr(p, addr);
9419 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9420 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9421 V_FW_PARAMS_PARAM_YZ(vi->viid);
9422 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val);
9424 vi->rss_base = 0xffff;
9426 /* MPASS((val >> 16) == rss_size); */
9427 vi->rss_base = val & 0xffff;
9434 * t4_read_cimq_cfg - read CIM queue configuration
9435 * @adap: the adapter
9436 * @base: holds the queue base addresses in bytes
9437 * @size: holds the queue sizes in bytes
9438 * @thres: holds the queue full thresholds in bytes
9440 * Returns the current configuration of the CIM queues, starting with
9441 * the IBQs, then the OBQs.
9443 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9446 int cim_num_obq = adap->chip_params->cim_num_obq;
9448 for (i = 0; i < CIM_NUM_IBQ; i++) {
9449 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9451 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9452 /* value is in 256-byte units */
9453 *base++ = G_CIMQBASE(v) * 256;
9454 *size++ = G_CIMQSIZE(v) * 256;
9455 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9457 for (i = 0; i < cim_num_obq; i++) {
9458 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9460 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9461 /* value is in 256-byte units */
9462 *base++ = G_CIMQBASE(v) * 256;
9463 *size++ = G_CIMQSIZE(v) * 256;
9468 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9469 * @adap: the adapter
9470 * @qid: the queue index
9471 * @data: where to store the queue contents
9472 * @n: capacity of @data in 32-bit words
9474 * Reads the contents of the selected CIM queue starting at address 0 up
9475 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9476 * error and the number of 32-bit words actually read on success.
9478 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9480 int i, err, attempts;
9482 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9484 if (qid > 5 || (n & 3))
9487 addr = qid * nwords;
9491 /* It might take 3-10ms before the IBQ debug read access is allowed.
9492 * Wait for 1 Sec with a delay of 1 usec.
9496 for (i = 0; i < n; i++, addr++) {
9497 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9499 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9503 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9505 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9510 * t4_read_cim_obq - read the contents of a CIM outbound queue
9511 * @adap: the adapter
9512 * @qid: the queue index
9513 * @data: where to store the queue contents
9514 * @n: capacity of @data in 32-bit words
9516 * Reads the contents of the selected CIM queue starting at address 0 up
9517 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9518 * error and the number of 32-bit words actually read on success.
9520 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9523 unsigned int addr, v, nwords;
9524 int cim_num_obq = adap->chip_params->cim_num_obq;
9526 if ((qid > (cim_num_obq - 1)) || (n & 3))
9529 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9530 V_QUENUMSELECT(qid));
9531 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9533 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */
9534 nwords = G_CIMQSIZE(v) * 64; /* same */
9538 for (i = 0; i < n; i++, addr++) {
9539 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
9541 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
9545 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
9547 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
9553 CIM_CTL_BASE = 0x2000,
9554 CIM_PBT_ADDR_BASE = 0x2800,
9555 CIM_PBT_LRF_BASE = 0x3000,
9556 CIM_PBT_DATA_BASE = 0x3800
9560 * t4_cim_read - read a block from CIM internal address space
9561 * @adap: the adapter
9562 * @addr: the start address within the CIM address space
9563 * @n: number of words to read
9564 * @valp: where to store the result
9566 * Reads a block of 4-byte words from the CIM intenal address space.
9568 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9573 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9576 for ( ; !ret && n--; addr += 4) {
9577 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
9578 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9581 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
9587 * t4_cim_write - write a block into CIM internal address space
9588 * @adap: the adapter
9589 * @addr: the start address within the CIM address space
9590 * @n: number of words to write
9591 * @valp: set of values to write
9593 * Writes a block of 4-byte words into the CIM intenal address space.
9595 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9596 const unsigned int *valp)
9600 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9603 for ( ; !ret && n--; addr += 4) {
9604 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
9605 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
9606 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9612 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9615 return t4_cim_write(adap, addr, 1, &val);
9619 * t4_cim_ctl_read - read a block from CIM control region
9620 * @adap: the adapter
9621 * @addr: the start address within the CIM control region
9622 * @n: number of words to read
9623 * @valp: where to store the result
9625 * Reads a block of 4-byte words from the CIM control region.
9627 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
9630 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
9634 * t4_cim_read_la - read CIM LA capture buffer
9635 * @adap: the adapter
9636 * @la_buf: where to store the LA data
9637 * @wrptr: the HW write pointer within the capture buffer
9639 * Reads the contents of the CIM LA buffer with the most recent entry at
9640 * the end of the returned data and with the entry at @wrptr first.
9641 * We try to leave the LA in the running state we find it in.
9643 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9646 unsigned int cfg, val, idx;
9648 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
9652 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */
9653 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
9658 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9662 idx = G_UPDBGLAWRPTR(val);
9666 for (i = 0; i < adap->params.cim_la_size; i++) {
9667 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9668 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
9671 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9674 if (val & F_UPDBGLARDEN) {
9678 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
9682 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
9683 idx = (idx + 1) & M_UPDBGLARDPTR;
9685 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9686 * identify the 32-bit portion of the full 312-bit data
9689 while ((idx & 0xf) > 9)
9690 idx = (idx + 1) % M_UPDBGLARDPTR;
9693 if (cfg & F_UPDBGLAEN) {
9694 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9695 cfg & ~F_UPDBGLARDEN);
9703 * t4_tp_read_la - read TP LA capture buffer
9704 * @adap: the adapter
9705 * @la_buf: where to store the LA data
9706 * @wrptr: the HW write pointer within the capture buffer
9708 * Reads the contents of the TP LA buffer with the most recent entry at
9709 * the end of the returned data and with the entry at @wrptr first.
9710 * We leave the LA in the running state we find it in.
9712 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9714 bool last_incomplete;
9715 unsigned int i, cfg, val, idx;
9717 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
9718 if (cfg & F_DBGLAENABLE) /* freeze LA */
9719 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9720 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
9722 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
9723 idx = G_DBGLAWPTR(val);
9724 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
9725 if (last_incomplete)
9726 idx = (idx + 1) & M_DBGLARPTR;
9731 val &= ~V_DBGLARPTR(M_DBGLARPTR);
9732 val |= adap->params.tp.la_mask;
9734 for (i = 0; i < TPLA_SIZE; i++) {
9735 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
9736 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
9737 idx = (idx + 1) & M_DBGLARPTR;
9740 /* Wipe out last entry if it isn't valid */
9741 if (last_incomplete)
9742 la_buf[TPLA_SIZE - 1] = ~0ULL;
9744 if (cfg & F_DBGLAENABLE) /* restore running state */
9745 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9746 cfg | adap->params.tp.la_mask);
9750 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9751 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9752 * state for more than the Warning Threshold then we'll issue a warning about
9753 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9754 * appears to be hung every Warning Repeat second till the situation clears.
9755 * If the situation clears, we'll note that as well.
9757 #define SGE_IDMA_WARN_THRESH 1
9758 #define SGE_IDMA_WARN_REPEAT 300
9761 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9762 * @adapter: the adapter
9763 * @idma: the adapter IDMA Monitor state
9765 * Initialize the state of an SGE Ingress DMA Monitor.
9767 void t4_idma_monitor_init(struct adapter *adapter,
9768 struct sge_idma_monitor_state *idma)
9770 /* Initialize the state variables for detecting an SGE Ingress DMA
9771 * hang. The SGE has internal counters which count up on each clock
9772 * tick whenever the SGE finds its Ingress DMA State Engines in the
9773 * same state they were on the previous clock tick. The clock used is
9774 * the Core Clock so we have a limit on the maximum "time" they can
9775 * record; typically a very small number of seconds. For instance,
9776 * with a 600MHz Core Clock, we can only count up to a bit more than
9777 * 7s. So we'll synthesize a larger counter in order to not run the
9778 * risk of having the "timers" overflow and give us the flexibility to
9779 * maintain a Hung SGE State Machine of our own which operates across
9780 * a longer time frame.
9782 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9783 idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
9787 * t4_idma_monitor - monitor SGE Ingress DMA state
9788 * @adapter: the adapter
9789 * @idma: the adapter IDMA Monitor state
9790 * @hz: number of ticks/second
9791 * @ticks: number of ticks since the last IDMA Monitor call
9793 void t4_idma_monitor(struct adapter *adapter,
9794 struct sge_idma_monitor_state *idma,
9797 int i, idma_same_state_cnt[2];
9799 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9800 * are counters inside the SGE which count up on each clock when the
9801 * SGE finds its Ingress DMA State Engines in the same states they
9802 * were in the previous clock. The counters will peg out at
9803 * 0xffffffff without wrapping around so once they pass the 1s
9804 * threshold they'll stay above that till the IDMA state changes.
9806 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
9807 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
9808 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9810 for (i = 0; i < 2; i++) {
9811 u32 debug0, debug11;
9813 /* If the Ingress DMA Same State Counter ("timer") is less
9814 * than 1s, then we can reset our synthesized Stall Timer and
9815 * continue. If we have previously emitted warnings about a
9816 * potential stalled Ingress Queue, issue a note indicating
9817 * that the Ingress Queue has resumed forward progress.
9819 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9820 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
9821 CH_WARN(adapter, "SGE idma%d, queue %u, "
9822 "resumed after %d seconds\n",
9823 i, idma->idma_qid[i],
9824 idma->idma_stalled[i]/hz);
9825 idma->idma_stalled[i] = 0;
9829 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9830 * domain. The first time we get here it'll be because we
9831 * passed the 1s Threshold; each additional time it'll be
9832 * because the RX Timer Callback is being fired on its regular
9835 * If the stall is below our Potential Hung Ingress Queue
9836 * Warning Threshold, continue.
9838 if (idma->idma_stalled[i] == 0) {
9839 idma->idma_stalled[i] = hz;
9840 idma->idma_warn[i] = 0;
9842 idma->idma_stalled[i] += ticks;
9843 idma->idma_warn[i] -= ticks;
9846 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
9849 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9851 if (idma->idma_warn[i] > 0)
9853 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
9855 /* Read and save the SGE IDMA State and Queue ID information.
9856 * We do this every time in case it changes across time ...
9857 * can't be too careful ...
9859 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
9860 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9861 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9863 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
9864 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9865 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9867 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
9868 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9869 i, idma->idma_qid[i], idma->idma_state[i],
9870 idma->idma_stalled[i]/hz,
9872 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9877 * t4_read_pace_tbl - read the pace table
9878 * @adap: the adapter
9879 * @pace_vals: holds the returned values
9881 * Returns the values of TP's pace table in microseconds.
9883 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9887 for (i = 0; i < NTX_SCHED; i++) {
9888 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
9889 v = t4_read_reg(adap, A_TP_PACE_TABLE);
9890 pace_vals[i] = dack_ticks_to_usec(adap, v);
9895 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9896 * @adap: the adapter
9897 * @sched: the scheduler index
9898 * @kbps: the byte rate in Kbps
9899 * @ipg: the interpacket delay in tenths of nanoseconds
9901 * Return the current configuration of a HW Tx scheduler.
9903 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
9904 unsigned int *ipg, bool sleep_ok)
9906 unsigned int v, addr, bpt, cpt;
9909 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
9910 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9913 bpt = (v >> 8) & 0xff;
9916 *kbps = 0; /* scheduler disabled */
9918 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9919 *kbps = (v * bpt) / 125;
9923 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
9924 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9928 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9933 * t4_load_cfg - download config file
9934 * @adap: the adapter
9935 * @cfg_data: the cfg text file to write
9936 * @size: text file size
9938 * Write the supplied config text file to the card's serial flash.
9940 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9942 int ret, i, n, cfg_addr;
9944 unsigned int flash_cfg_start_sec;
9945 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9947 cfg_addr = t4_flash_cfg_addr(adap);
9952 flash_cfg_start_sec = addr / SF_SEC_SIZE;
9954 if (size > FLASH_CFG_MAX_SIZE) {
9955 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
9956 FLASH_CFG_MAX_SIZE);
9960 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
9962 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9963 flash_cfg_start_sec + i - 1);
9965 * If size == 0 then we're simply erasing the FLASH sectors associated
9966 * with the on-adapter Firmware Configuration File.
9968 if (ret || size == 0)
9971 /* this will write to the flash up to SF_PAGE_SIZE at a time */
9972 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
9973 if ( (size - i) < SF_PAGE_SIZE)
9977 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
9981 addr += SF_PAGE_SIZE;
9982 cfg_data += SF_PAGE_SIZE;
9987 CH_ERR(adap, "config file %s failed %d\n",
9988 (size == 0 ? "clear" : "download"), ret);
9993 * t5_fw_init_extern_mem - initialize the external memory
9994 * @adap: the adapter
9996 * Initializes the external memory on T5.
9998 int t5_fw_init_extern_mem(struct adapter *adap)
10000 u32 params[1], val[1];
10006 val[0] = 0xff; /* Initialize all MCs */
10007 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10008 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10009 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10010 FW_CMD_MAX_TIMEOUT);
10015 /* BIOS boot headers */
10016 typedef struct pci_expansion_rom_header {
10017 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10018 u8 reserved[22]; /* Reserved per processor Architecture data */
10019 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10020 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10022 /* Legacy PCI Expansion ROM Header */
10023 typedef struct legacy_pci_expansion_rom_header {
10024 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10025 u8 size512; /* Current Image Size in units of 512 bytes */
10026 u8 initentry_point[4];
10027 u8 cksum; /* Checksum computed on the entire Image */
10028 u8 reserved[16]; /* Reserved */
10029 u8 pcir_offset[2]; /* Offset to PCI Data Struture */
10030 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10032 /* EFI PCI Expansion ROM Header */
10033 typedef struct efi_pci_expansion_rom_header {
10034 u8 signature[2]; // ROM signature. The value 0xaa55
10035 u8 initialization_size[2]; /* Units 512. Includes this header */
10036 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10037 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */
10038 u8 efi_machine_type[2]; /* Machine type from EFI image header */
10039 u8 compression_type[2]; /* Compression type. */
10041 * Compression type definition
10042 * 0x0: uncompressed
10044 * 0x2-0xFFFF: Reserved
10046 u8 reserved[8]; /* Reserved */
10047 u8 efi_image_header_offset[2]; /* Offset to EFI Image */
10048 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10049 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10051 /* PCI Data Structure Format */
10052 typedef struct pcir_data_structure { /* PCI Data Structure */
10053 u8 signature[4]; /* Signature. The string "PCIR" */
10054 u8 vendor_id[2]; /* Vendor Identification */
10055 u8 device_id[2]; /* Device Identification */
10056 u8 vital_product[2]; /* Pointer to Vital Product Data */
10057 u8 length[2]; /* PCIR Data Structure Length */
10058 u8 revision; /* PCIR Data Structure Revision */
10059 u8 class_code[3]; /* Class Code */
10060 u8 image_length[2]; /* Image Length. Multiple of 512B */
10061 u8 code_revision[2]; /* Revision Level of Code/Data */
10062 u8 code_type; /* Code Type. */
10064 * PCI Expansion ROM Code Types
10065 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10066 * 0x01: Open Firmware standard for PCI. FCODE
10067 * 0x02: Hewlett-Packard PA RISC. HP reserved
10068 * 0x03: EFI Image. EFI
10069 * 0x04-0xFF: Reserved.
10071 u8 indicator; /* Indicator. Identifies the last image in the ROM */
10072 u8 reserved[2]; /* Reserved */
10073 } pcir_data_t; /* PCI__DATA_STRUCTURE */
10075 /* BOOT constants */
10077 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10078 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
10079 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
10080 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10081 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */
10082 VENDOR_ID = 0x1425, /* Vendor ID */
10083 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10087 * modify_device_id - Modifies the device ID of the Boot BIOS image
10088 * @adatper: the device ID to write.
10089 * @boot_data: the boot image to modify.
10091 * Write the supplied device ID to the boot BIOS image.
10093 static void modify_device_id(int device_id, u8 *boot_data)
10095 legacy_pci_exp_rom_header_t *header;
10096 pcir_data_t *pcir_header;
10097 u32 cur_header = 0;
10100 * Loop through all chained images and change the device ID's
10103 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10104 pcir_header = (pcir_data_t *) &boot_data[cur_header +
10105 le16_to_cpu(*(u16*)header->pcir_offset)];
10108 * Only modify the Device ID if code type is Legacy or HP.
10109 * 0x00: Okay to modify
10110 * 0x01: FCODE. Do not be modify
10111 * 0x03: Okay to modify
10112 * 0x04-0xFF: Do not modify
10114 if (pcir_header->code_type == 0x00) {
10119 * Modify Device ID to match current adatper
10121 *(u16*) pcir_header->device_id = device_id;
10124 * Set checksum temporarily to 0.
10125 * We will recalculate it later.
10127 header->cksum = 0x0;
10130 * Calculate and update checksum
10132 for (i = 0; i < (header->size512 * 512); i++)
10133 csum += (u8)boot_data[cur_header + i];
10136 * Invert summed value to create the checksum
10137 * Writing new checksum value directly to the boot data
10139 boot_data[cur_header + 7] = -csum;
10141 } else if (pcir_header->code_type == 0x03) {
10144 * Modify Device ID to match current adatper
10146 *(u16*) pcir_header->device_id = device_id;
10152 * Check indicator element to identify if this is the last
10153 * image in the ROM.
10155 if (pcir_header->indicator & 0x80)
10159 * Move header pointer up to the next image in the ROM.
10161 cur_header += header->size512 * 512;
10166 * t4_load_boot - download boot flash
10167 * @adapter: the adapter
10168 * @boot_data: the boot image to write
10169 * @boot_addr: offset in flash to write boot_data
10170 * @size: image size
10172 * Write the supplied boot image to the card's serial flash.
10173 * The boot image has the following sections: a 28-byte header and the
10176 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10177 unsigned int boot_addr, unsigned int size)
10179 pci_exp_rom_header_t *header;
10181 pcir_data_t *pcir_header;
10183 uint16_t device_id;
10185 unsigned int boot_sector = (boot_addr * 1024 );
10186 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10189 * Make sure the boot image does not encroach on the firmware region
10191 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10192 CH_ERR(adap, "boot image encroaching on firmware region\n");
10197 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10198 * and Boot configuration data sections. These 3 boot sections span
10199 * sectors 0 to 7 in flash and live right before the FW image location.
10201 i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10203 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10204 (boot_sector >> 16) + i - 1);
10207 * If size == 0 then we're simply erasing the FLASH sectors associated
10208 * with the on-adapter option ROM file
10210 if (ret || (size == 0))
10213 /* Get boot header */
10214 header = (pci_exp_rom_header_t *)boot_data;
10215 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10216 /* PCIR Data Structure */
10217 pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10220 * Perform some primitive sanity testing to avoid accidentally
10221 * writing garbage over the boot sectors. We ought to check for
10222 * more but it's not worth it for now ...
10224 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10225 CH_ERR(adap, "boot image too small/large\n");
10229 #ifndef CHELSIO_T4_DIAGS
10231 * Check BOOT ROM header signature
10233 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10234 CH_ERR(adap, "Boot image missing signature\n");
10239 * Check PCI header signature
10241 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10242 CH_ERR(adap, "PCI header missing signature\n");
10247 * Check Vendor ID matches Chelsio ID
10249 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10250 CH_ERR(adap, "Vendor ID missing signature\n");
10256 * Retrieve adapter's device ID
10258 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10259 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10260 device_id = device_id & 0xf0ff;
10263 * Check PCIE Device ID
10265 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10267 * Change the device ID in the Boot BIOS image to match
10268 * the Device ID of the current adapter.
10270 modify_device_id(device_id, boot_data);
10274 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10275 * we finish copying the rest of the boot image. This will ensure
10276 * that the BIOS boot header will only be written if the boot image
10277 * was written in full.
10279 addr = boot_sector;
10280 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10281 addr += SF_PAGE_SIZE;
10282 boot_data += SF_PAGE_SIZE;
10283 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10288 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10289 (const u8 *)header, 0);
10293 CH_ERR(adap, "boot image download failed, error %d\n", ret);
10298 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10299 * @adapter: the adapter
10301 * Return the address within the flash where the OptionROM Configuration
10302 * is stored, or an error if the device FLASH is too small to contain
10303 * a OptionROM Configuration.
10305 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10308 * If the device FLASH isn't large enough to hold a Firmware
10309 * Configuration File, return an error.
10311 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10314 return FLASH_BOOTCFG_START;
10317 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10319 int ret, i, n, cfg_addr;
10321 unsigned int flash_cfg_start_sec;
10322 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10324 cfg_addr = t4_flash_bootcfg_addr(adap);
10329 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10331 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10332 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10333 FLASH_BOOTCFG_MAX_SIZE);
10337 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10339 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10340 flash_cfg_start_sec + i - 1);
10343 * If size == 0 then we're simply erasing the FLASH sectors associated
10344 * with the on-adapter OptionROM Configuration File.
10346 if (ret || size == 0)
10349 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10350 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10351 if ( (size - i) < SF_PAGE_SIZE)
10355 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10359 addr += SF_PAGE_SIZE;
10360 cfg_data += SF_PAGE_SIZE;
10365 CH_ERR(adap, "boot config data %s failed %d\n",
10366 (size == 0 ? "clear" : "download"), ret);
10371 * t4_set_filter_mode - configure the optional components of filter tuples
10372 * @adap: the adapter
10373 * @mode_map: a bitmap selcting which optional filter components to enable
10374 * @sleep_ok: if true we may sleep while awaiting command completion
10376 * Sets the filter mode by selecting the optional components to enable
10377 * in filter tuples. Returns 0 on success and a negative error if the
10378 * requested mode needs more bits than are available for optional
10381 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
10384 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
10388 for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
10389 if (mode_map & (1 << i))
10391 if (nbits > FILTER_OPT_LEN)
10393 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok);
10394 read_filter_mode_and_ingress_config(adap, sleep_ok);
10400 * t4_clr_port_stats - clear port statistics
10401 * @adap: the adapter
10402 * @idx: the port index
10404 * Clear HW statistics for the given port.
10406 void t4_clr_port_stats(struct adapter *adap, int idx)
10409 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
10410 u32 port_base_addr;
10413 port_base_addr = PORT_BASE(idx);
10415 port_base_addr = T5_PORT_BASE(idx);
10417 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
10418 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
10419 t4_write_reg(adap, port_base_addr + i, 0);
10420 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
10421 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
10422 t4_write_reg(adap, port_base_addr + i, 0);
10423 for (i = 0; i < 4; i++)
10424 if (bgmap & (1 << i)) {
10426 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
10428 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
10433 * t4_i2c_rd - read I2C data from adapter
10434 * @adap: the adapter
10435 * @port: Port number if per-port device; <0 if not
10436 * @devid: per-port device ID or absolute device ID
10437 * @offset: byte offset into device I2C space
10438 * @len: byte length of I2C space data
10439 * @buf: buffer in which to return I2C data
10441 * Reads the I2C data from the indicated device and location.
10443 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
10444 int port, unsigned int devid,
10445 unsigned int offset, unsigned int len,
10448 u32 ldst_addrspace;
10449 struct fw_ldst_cmd ldst;
10455 len > sizeof ldst.u.i2c.data)
10458 memset(&ldst, 0, sizeof ldst);
10459 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10460 ldst.op_to_addrspace =
10461 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10465 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10466 ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10467 ldst.u.i2c.did = devid;
10468 ldst.u.i2c.boffset = offset;
10469 ldst.u.i2c.blen = len;
10470 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10472 memcpy(buf, ldst.u.i2c.data, len);
10477 * t4_i2c_wr - write I2C data to adapter
10478 * @adap: the adapter
10479 * @port: Port number if per-port device; <0 if not
10480 * @devid: per-port device ID or absolute device ID
10481 * @offset: byte offset into device I2C space
10482 * @len: byte length of I2C space data
10483 * @buf: buffer containing new I2C data
10485 * Write the I2C data to the indicated device and location.
10487 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
10488 int port, unsigned int devid,
10489 unsigned int offset, unsigned int len,
10492 u32 ldst_addrspace;
10493 struct fw_ldst_cmd ldst;
10498 len > sizeof ldst.u.i2c.data)
10501 memset(&ldst, 0, sizeof ldst);
10502 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10503 ldst.op_to_addrspace =
10504 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10508 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10509 ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10510 ldst.u.i2c.did = devid;
10511 ldst.u.i2c.boffset = offset;
10512 ldst.u.i2c.blen = len;
10513 memcpy(ldst.u.i2c.data, buf, len);
10514 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10518 * t4_sge_ctxt_rd - read an SGE context through FW
10519 * @adap: the adapter
10520 * @mbox: mailbox to use for the FW command
10521 * @cid: the context id
10522 * @ctype: the context type
10523 * @data: where to store the context data
10525 * Issues a FW command through the given mailbox to read an SGE context.
10527 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10528 enum ctxt_type ctype, u32 *data)
10531 struct fw_ldst_cmd c;
10533 if (ctype == CTXT_EGRESS)
10534 ret = FW_LDST_ADDRSPC_SGE_EGRC;
10535 else if (ctype == CTXT_INGRESS)
10536 ret = FW_LDST_ADDRSPC_SGE_INGC;
10537 else if (ctype == CTXT_FLM)
10538 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10540 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10542 memset(&c, 0, sizeof(c));
10543 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10544 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10545 V_FW_LDST_CMD_ADDRSPACE(ret));
10546 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10547 c.u.idctxt.physid = cpu_to_be32(cid);
10549 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10551 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10552 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10553 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10554 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10555 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10556 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10562 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10563 * @adap: the adapter
10564 * @cid: the context id
10565 * @ctype: the context type
10566 * @data: where to store the context data
10568 * Reads an SGE context directly, bypassing FW. This is only for
10569 * debugging when FW is unavailable.
10571 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
10576 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
10577 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
10579 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
10580 *data++ = t4_read_reg(adap, i);
10584 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
10587 struct fw_sched_cmd cmd;
10589 memset(&cmd, 0, sizeof(cmd));
10590 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10593 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10595 cmd.u.config.sc = FW_SCHED_SC_CONFIG;
10596 cmd.u.config.type = type;
10597 cmd.u.config.minmaxen = minmaxen;
10599 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10603 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10604 int rateunit, int ratemode, int channel, int cl,
10605 int minrate, int maxrate, int weight, int pktsize,
10606 int burstsize, int sleep_ok)
10608 struct fw_sched_cmd cmd;
10610 memset(&cmd, 0, sizeof(cmd));
10611 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10614 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10616 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10617 cmd.u.params.type = type;
10618 cmd.u.params.level = level;
10619 cmd.u.params.mode = mode;
10620 cmd.u.params.ch = channel;
10621 cmd.u.params.cl = cl;
10622 cmd.u.params.unit = rateunit;
10623 cmd.u.params.rate = ratemode;
10624 cmd.u.params.min = cpu_to_be32(minrate);
10625 cmd.u.params.max = cpu_to_be32(maxrate);
10626 cmd.u.params.weight = cpu_to_be16(weight);
10627 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10628 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10630 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10634 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
10635 unsigned int maxrate, int sleep_ok)
10637 struct fw_sched_cmd cmd;
10639 memset(&cmd, 0, sizeof(cmd));
10640 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10643 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10645 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10646 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10647 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
10648 cmd.u.params.ch = channel;
10649 cmd.u.params.rate = ratemode; /* REL or ABS */
10650 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */
10652 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10656 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
10657 int weight, int sleep_ok)
10659 struct fw_sched_cmd cmd;
10661 if (weight < 0 || weight > 100)
10664 memset(&cmd, 0, sizeof(cmd));
10665 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10668 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10670 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10671 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10672 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
10673 cmd.u.params.ch = channel;
10674 cmd.u.params.cl = cl;
10675 cmd.u.params.weight = cpu_to_be16(weight);
10677 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10681 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
10682 int mode, unsigned int maxrate, int pktsize, int sleep_ok)
10684 struct fw_sched_cmd cmd;
10686 memset(&cmd, 0, sizeof(cmd));
10687 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10690 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10692 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10693 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10694 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
10695 cmd.u.params.mode = mode;
10696 cmd.u.params.ch = channel;
10697 cmd.u.params.cl = cl;
10698 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
10699 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
10700 cmd.u.params.max = cpu_to_be32(maxrate);
10701 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10703 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10708 * t4_config_watchdog - configure (enable/disable) a watchdog timer
10709 * @adapter: the adapter
10710 * @mbox: mailbox to use for the FW command
10711 * @pf: the PF owning the queue
10712 * @vf: the VF owning the queue
10713 * @timeout: watchdog timeout in ms
10714 * @action: watchdog timer / action
10716 * There are separate watchdog timers for each possible watchdog
10717 * action. Configure one of the watchdog timers by setting a non-zero
10718 * timeout. Disable a watchdog timer by using a timeout of zero.
10720 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
10721 unsigned int pf, unsigned int vf,
10722 unsigned int timeout, unsigned int action)
10724 struct fw_watchdog_cmd wdog;
10725 unsigned int ticks;
10728 * The watchdog command expects a timeout in units of 10ms so we need
10729 * to convert it here (via rounding) and force a minimum of one 10ms
10730 * "tick" if the timeout is non-zero but the conversion results in 0
10733 ticks = (timeout + 5)/10;
10734 if (timeout && !ticks)
10737 memset(&wdog, 0, sizeof wdog);
10738 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
10741 V_FW_PARAMS_CMD_PFN(pf) |
10742 V_FW_PARAMS_CMD_VFN(vf));
10743 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
10744 wdog.timeout = cpu_to_be32(ticks);
10745 wdog.action = cpu_to_be32(action);
10747 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
10750 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
10752 struct fw_devlog_cmd devlog_cmd;
10755 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10756 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10757 F_FW_CMD_REQUEST | F_FW_CMD_READ);
10758 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10759 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10760 sizeof(devlog_cmd), &devlog_cmd);
10764 *level = devlog_cmd.level;
10768 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
10770 struct fw_devlog_cmd devlog_cmd;
10772 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10773 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10776 devlog_cmd.level = level;
10777 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10778 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10779 sizeof(devlog_cmd), &devlog_cmd);