2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 NCHAN = 4, /* # of HW channels */
41 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
42 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
43 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
44 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
45 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
46 T6_RSS_NENTRIES = 4096,
47 TCB_SIZE = 128, /* TCB size */
48 NMTUS = 16, /* size of MTU table */
49 NCCTRL_WIN = 32, /* # of congestion control windows */
50 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
51 PM_NSTATS = 5, /* # of PM stats */
54 MBOX_LEN = 64, /* mailbox size in bytes */
55 NTRACE = 4, /* # of tracing filters */
56 TRACE_LEN = 112, /* length of trace data and mask */
57 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
58 NWOL_PAT = 8, /* # of WoL patterns */
59 WOL_PAT_LEN = 128, /* length of WoL patterns */
60 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */
61 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */
62 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */
63 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */
67 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
68 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
69 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
70 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
71 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
72 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
73 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
74 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
75 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
76 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
80 SF_PAGE_SIZE = 256, /* serial flash page size */
81 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
84 /* SGE context types */
85 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
87 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
89 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
92 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
93 SGE_CTXT_SIZE = 24, /* size of SGE context */
94 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
95 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
96 SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */
97 SGE_MAX_IQ_SIZE = 65520,
101 struct sge_qstat { /* data written to SGE queue status entries */
103 volatile __be16 cidx;
104 volatile __be16 pidx;
107 #define S_QSTAT_PIDX 0
108 #define M_QSTAT_PIDX 0xffff
109 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
111 #define S_QSTAT_CIDX 16
112 #define M_QSTAT_CIDX 0xffff
113 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
116 * Structure for last 128 bits of response descriptors
119 __be32 hdrbuflen_pidx;
120 __be32 pldbuflen_qid;
127 #define S_RSPD_NEWBUF 31
128 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
129 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
132 #define M_RSPD_LEN 0x7fffffff
133 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
134 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
136 #define S_RSPD_QID S_RSPD_LEN
137 #define M_RSPD_QID M_RSPD_LEN
138 #define V_RSPD_QID(x) V_RSPD_LEN(x)
139 #define G_RSPD_QID(x) G_RSPD_LEN(x)
142 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
143 #define F_RSPD_GEN V_RSPD_GEN(1U)
145 #define S_RSPD_QOVFL 6
146 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
147 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
149 #define S_RSPD_TYPE 4
150 #define M_RSPD_TYPE 0x3
151 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
152 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
154 /* Rx queue interrupt deferral fields: counter enable and timer index */
155 #define S_QINTR_CNT_EN 0
156 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
157 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
159 #define S_QINTR_TIMER_IDX 1
160 #define M_QINTR_TIMER_IDX 0x7
161 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
162 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
164 /* # of pages a pagepod can hold without needing another pagepod */
165 #define PPOD_PAGES 4U
168 __be64 vld_tid_pgsz_tag_color;
171 __be64 addr[PPOD_PAGES + 1];
174 #define S_PPOD_COLOR 0
175 #define M_PPOD_COLOR 0x3F
176 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
179 #define M_PPOD_TAG 0xFFFFFF
180 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
181 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
183 #define S_PPOD_PGSZ 30
184 #define M_PPOD_PGSZ 0x3
185 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
186 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
188 #define S_PPOD_TID 32
189 #define M_PPOD_TID 0xFFFFFF
190 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
192 #define S_PPOD_VALID 56
193 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
194 #define F_PPOD_VALID V_PPOD_VALID(1ULL)
196 #define S_PPOD_LEN 32
197 #define M_PPOD_LEN 0xFFFFFFFF
198 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
200 #define S_PPOD_OFST 0
201 #define M_PPOD_OFST 0xFFFFFFFF
202 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
207 #define FLASH_START(start) ((start) * SF_SEC_SIZE)
208 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
212 * Various Expansion-ROM boot images, etc.
214 FLASH_EXP_ROM_START_SEC = 0,
215 FLASH_EXP_ROM_NSECS = 6,
216 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
217 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
220 * iSCSI Boot Firmware Table (iBFT) and other driver-related
223 FLASH_IBFT_START_SEC = 6,
224 FLASH_IBFT_NSECS = 1,
225 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
226 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
229 * Boot configuration data.
231 FLASH_BOOTCFG_START_SEC = 7,
232 FLASH_BOOTCFG_NSECS = 1,
233 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
234 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
237 * Location of firmware image in FLASH.
239 FLASH_FW_START_SEC = 8,
241 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
242 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
245 * Location of bootstrap firmware image in FLASH.
247 FLASH_FWBOOTSTRAP_START_SEC = 27,
248 FLASH_FWBOOTSTRAP_NSECS = 1,
249 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
250 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
253 * iSCSI persistent/crash information.
255 FLASH_ISCSI_CRASH_START_SEC = 29,
256 FLASH_ISCSI_CRASH_NSECS = 1,
257 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
258 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
261 * FCoE persistent/crash information.
263 FLASH_FCOE_CRASH_START_SEC = 30,
264 FLASH_FCOE_CRASH_NSECS = 1,
265 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
266 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
269 * Location of Firmware Configuration File in FLASH.
271 FLASH_CFG_START_SEC = 31,
273 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
274 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
277 * We don't support FLASH devices which can't support the full
278 * standard set of sections which we need for normal operations.
280 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
283 * Sectors 32-63 for CUDBG.
285 FLASH_CUDBG_START_SEC = 32,
286 FLASH_CUDBG_NSECS = 32,
287 FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
288 FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
291 * Size of defined FLASH regions.
297 #undef FLASH_MAX_SIZE
299 #define S_SGE_TIMESTAMP 0
300 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL
301 #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
302 #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
304 #define I2C_DEV_ADDR_A0 0xa0
305 #define I2C_DEV_ADDR_A2 0xa2
306 #define I2C_PAGE_SIZE 0x100
307 #define SFP_DIAG_TYPE_ADDR 0x5c
308 #define SFP_DIAG_TYPE_LEN 0x1
309 #define SFF_8472_COMP_ADDR 0x5e
310 #define SFF_8472_COMP_LEN 0x1
311 #define SFF_REV_ADDR 0x1
312 #define SFF_REV_LEN 0x1
314 #endif /* __T4_HW_H */