2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013, 2016 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* This file is automatically generated --- changes will be lost */
33 /* Generation Date : Wed Jan 27 10:57:51 IST 2016 */
34 /* Directory name: t4_reg.txt, Changeset: */
35 /* Directory name: t5_reg.txt, Changeset: 6936:7f6342b03d61 */
36 /* Directory name: t6_reg.txt, Changeset: 4191:ce3ccd95c109 */
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
44 #define PF1_BASE 0x1e400
45 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
47 #define PF2_BASE 0x1e800
48 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
50 #define PF3_BASE 0x1ec00
51 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
53 #define PF4_BASE 0x1f000
54 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
56 #define PF5_BASE 0x1f400
57 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
59 #define PF6_BASE 0x1f800
60 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
62 #define PF7_BASE 0x1fc00
63 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
65 #define PF_STRIDE 0x400
66 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
67 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
69 #define VF_SGE_BASE 0x0
70 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
72 #define VF_MPS_BASE 0x100
73 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
75 #define VF_PL_BASE 0x200
76 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
78 #define VF_MBDATA_BASE 0x240
79 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
81 #define VF_CIM_BASE 0x300
82 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
84 #define MYPORT_BASE 0x1c000
85 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
87 #define PORT0_BASE 0x20000
88 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
90 #define PORT1_BASE 0x22000
91 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
93 #define PORT2_BASE 0x24000
94 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
96 #define PORT3_BASE 0x26000
97 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
99 #define PORT_STRIDE 0x2000
100 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
101 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
103 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
104 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
106 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
107 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
109 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
110 #define NUM_PCIE_DMA_INSTANCES 4
112 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
113 #define NUM_PCIE_CMD_INSTANCES 2
115 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
116 #define NUM_PCIE_HMA_INSTANCES 1
118 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
119 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
121 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
122 #define NUM_PCIE_MAILBOX_INSTANCES 1
124 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
125 #define NUM_PCIE_FW_INSTANCES 8
127 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
128 #define NUM_PCIE_FUNC_INSTANCES 256
130 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
131 #define NUM_PCIE_FID_INSTANCES 2048
133 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
134 #define NUM_PCIE_DMA_BUF_INSTANCES 4
136 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
137 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
139 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
140 #define NUM_MC_BIST_STATUS_INSTANCES 18
142 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
143 #define NUM_EDC_BIST_STATUS_INSTANCES 18
145 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
146 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
148 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
149 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
151 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
152 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
154 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
155 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
157 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
158 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
160 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
161 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
163 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
164 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
166 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
167 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
169 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
170 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
172 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
173 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
175 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
176 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
178 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
179 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
181 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
182 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
184 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
185 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
187 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
188 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
190 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
191 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
193 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
194 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
196 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
197 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
199 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
200 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
202 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
203 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
205 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
206 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
208 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
209 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
211 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
212 #define NUM_PL_VF_SLICE_L_INSTANCES 8
214 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
215 #define NUM_PL_VF_SLICE_H_INSTANCES 8
217 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
218 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
220 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
221 #define NUM_PL_VFID_MAP_INSTANCES 256
223 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
224 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
226 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
227 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
229 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
230 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
232 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
233 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
235 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
236 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
238 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
239 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
241 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
242 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
244 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
245 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
247 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
248 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
250 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
251 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
253 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
254 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
256 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
257 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
259 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
260 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
262 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
263 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
265 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
266 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
268 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
269 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
271 #define T5_MYPORT_BASE 0x2c000
272 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
274 #define T5_PORT0_BASE 0x30000
275 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
277 #define T5_PORT1_BASE 0x34000
278 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
280 #define T5_PORT2_BASE 0x38000
281 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
283 #define T5_PORT3_BASE 0x3c000
284 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
286 #define T5_PORT_STRIDE 0x4000
287 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
288 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
290 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
291 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
293 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
294 #define NUM_PCIE_PF_INT_INSTANCES 8
296 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
297 #define NUM_PCIE_VF_INT_INSTANCES 128
299 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
300 #define NUM_PCIE_FID_VFID_INSTANCES 2048
302 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
303 #define NUM_PCIE_COOKIE_INSTANCES 8
305 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
306 #define NUM_PCIE_T5_DMA_INSTANCES 4
308 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
309 #define NUM_PCIE_T5_CMD_INSTANCES 3
311 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
312 #define NUM_PCIE_T5_HMA_INSTANCES 1
314 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
315 #define NUM_PCIE_PHY_PRESET_INSTANCES 11
317 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
318 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
320 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
321 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
323 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
324 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
326 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
327 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
329 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
330 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
332 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
333 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
335 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
336 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
338 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
339 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
341 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
342 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
344 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
345 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
347 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
348 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
350 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
351 #define NUM_MC_ADR_INSTANCES 2
353 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
354 #define NUM_MC_DDRPHY_DP18_INSTANCES 5
356 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
357 #define NUM_MC_CE_ERR_DATA_INSTANCES 8
359 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
360 #define NUM_MC_CE_COR_DATA_INSTANCES 8
362 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
363 #define NUM_MC_UE_ERR_DATA_INSTANCES 8
365 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
366 #define NUM_MC_UE_COR_DATA_INSTANCES 8
368 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
369 #define NUM_MC_P_BIST_STATUS_INSTANCES 18
371 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
372 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18
374 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
375 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
377 #define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
378 #define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
380 #define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
381 #define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
383 #define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
384 #define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
386 #define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
387 #define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
389 #define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
390 #define NUM_PCIE_T6_DMA_INSTANCES 2
392 #define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
393 #define NUM_PCIE_T6_CMD_INSTANCES 1
395 #define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
396 #define NUM_PCIE_VF_256_INT_INSTANCES 128
398 #define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
399 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
401 #define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
402 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
404 #define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
405 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
407 #define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
408 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
410 #define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
411 #define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
413 #define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
414 #define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
416 #define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
417 #define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
419 #define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
420 #define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
422 #define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
423 #define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
425 #define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
426 #define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
428 #define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
429 #define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
431 #define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
432 #define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
434 #define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
435 #define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
437 #define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
438 #define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
440 #define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
441 #define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
443 #define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
444 #define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
446 #define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
447 #define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
449 #define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
450 #define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
452 #define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
453 #define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
455 #define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
456 #define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
458 #define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
459 #define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
461 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
462 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
464 #define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
465 #define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
467 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
468 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
470 #define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
471 #define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
473 #define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
474 #define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
476 #define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
477 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
479 #define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
480 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
482 #define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
483 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
485 #define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
486 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
488 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
489 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
491 #define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
492 #define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
494 #define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
495 #define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
497 #define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
498 #define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
500 #define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
501 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
503 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
504 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
506 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
507 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
509 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
510 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
512 /* registers for module SGE */
513 #define SGE_BASE_ADDR 0x1000
515 #define A_SGE_PF_KDOORBELL 0x0
518 #define M_QID 0x1ffffU
519 #define V_QID(x) ((x) << S_QID)
520 #define G_QID(x) (((x) >> S_QID) & M_QID)
523 #define V_DBPRIO(x) ((x) << S_DBPRIO)
524 #define F_DBPRIO V_DBPRIO(1U)
527 #define M_PIDX 0x3fffU
528 #define V_PIDX(x) ((x) << S_PIDX)
529 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
531 #define A_SGE_VF_KDOORBELL 0x0
534 #define V_DBTYPE(x) ((x) << S_DBTYPE)
535 #define F_DBTYPE V_DBTYPE(1U)
538 #define M_PIDX_T5 0x1fffU
539 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
540 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
543 #define V_SYNC_T6(x) ((x) << S_SYNC_T6)
544 #define F_SYNC_T6 V_SYNC_T6(1U)
546 #define A_SGE_PF_GTS 0x4
548 #define S_INGRESSQID 16
549 #define M_INGRESSQID 0xffffU
550 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
551 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
553 #define S_TIMERREG 13
554 #define M_TIMERREG 0x7U
555 #define V_TIMERREG(x) ((x) << S_TIMERREG)
556 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
558 #define S_SEINTARM 12
559 #define V_SEINTARM(x) ((x) << S_SEINTARM)
560 #define F_SEINTARM V_SEINTARM(1U)
563 #define M_CIDXINC 0xfffU
564 #define V_CIDXINC(x) ((x) << S_CIDXINC)
565 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
567 #define A_SGE_VF_GTS 0x4
568 #define A_SGE_PF_KTIMESTAMP_LO 0x8
569 #define A_SGE_VF_KTIMESTAMP_LO 0x8
570 #define A_SGE_PF_KTIMESTAMP_HI 0xc
572 #define S_TSTAMPVAL 0
573 #define M_TSTAMPVAL 0xfffffffU
574 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
575 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
577 #define A_SGE_VF_KTIMESTAMP_HI 0xc
578 #define A_SGE_CONTROL 0x1008
580 #define S_IGRALLCPLTOFL 31
581 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
582 #define F_IGRALLCPLTOFL V_IGRALLCPLTOFL(1U)
584 #define S_FLSPLITMIN 22
585 #define M_FLSPLITMIN 0x1ffU
586 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
587 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
589 #define S_FLSPLITMODE 20
590 #define M_FLSPLITMODE 0x3U
591 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
592 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
594 #define S_DCASYSTYPE 19
595 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
596 #define F_DCASYSTYPE V_DCASYSTYPE(1U)
598 #define S_RXPKTCPLMODE 18
599 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
600 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
602 #define S_EGRSTATUSPAGESIZE 17
603 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
604 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
606 #define S_INGHINTENABLE1 15
607 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
608 #define F_INGHINTENABLE1 V_INGHINTENABLE1(1U)
610 #define S_INGHINTENABLE0 14
611 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
612 #define F_INGHINTENABLE0 V_INGHINTENABLE0(1U)
614 #define S_INGINTCOMPAREIDX 13
615 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
616 #define F_INGINTCOMPAREIDX V_INGINTCOMPAREIDX(1U)
618 #define S_PKTSHIFT 10
619 #define M_PKTSHIFT 0x7U
620 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
621 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
623 #define S_INGPCIEBOUNDARY 7
624 #define M_INGPCIEBOUNDARY 0x7U
625 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
626 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
628 #define S_INGPADBOUNDARY 4
629 #define M_INGPADBOUNDARY 0x7U
630 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
631 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
633 #define S_EGRPCIEBOUNDARY 1
634 #define M_EGRPCIEBOUNDARY 0x7U
635 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
636 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
638 #define S_GLOBALENABLE 0
639 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
640 #define F_GLOBALENABLE V_GLOBALENABLE(1U)
642 #define A_SGE_HOST_PAGE_SIZE 0x100c
644 #define S_HOSTPAGESIZEPF7 28
645 #define M_HOSTPAGESIZEPF7 0xfU
646 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
647 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
649 #define S_HOSTPAGESIZEPF6 24
650 #define M_HOSTPAGESIZEPF6 0xfU
651 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
652 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
654 #define S_HOSTPAGESIZEPF5 20
655 #define M_HOSTPAGESIZEPF5 0xfU
656 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
657 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
659 #define S_HOSTPAGESIZEPF4 16
660 #define M_HOSTPAGESIZEPF4 0xfU
661 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
662 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
664 #define S_HOSTPAGESIZEPF3 12
665 #define M_HOSTPAGESIZEPF3 0xfU
666 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
667 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
669 #define S_HOSTPAGESIZEPF2 8
670 #define M_HOSTPAGESIZEPF2 0xfU
671 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
672 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
674 #define S_HOSTPAGESIZEPF1 4
675 #define M_HOSTPAGESIZEPF1 0xfU
676 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
677 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
679 #define S_HOSTPAGESIZEPF0 0
680 #define M_HOSTPAGESIZEPF0 0xfU
681 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
682 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
684 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
686 #define S_QUEUESPERPAGEPF7 28
687 #define M_QUEUESPERPAGEPF7 0xfU
688 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
689 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
691 #define S_QUEUESPERPAGEPF6 24
692 #define M_QUEUESPERPAGEPF6 0xfU
693 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
694 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
696 #define S_QUEUESPERPAGEPF5 20
697 #define M_QUEUESPERPAGEPF5 0xfU
698 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
699 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
701 #define S_QUEUESPERPAGEPF4 16
702 #define M_QUEUESPERPAGEPF4 0xfU
703 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
704 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
706 #define S_QUEUESPERPAGEPF3 12
707 #define M_QUEUESPERPAGEPF3 0xfU
708 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
709 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
711 #define S_QUEUESPERPAGEPF2 8
712 #define M_QUEUESPERPAGEPF2 0xfU
713 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
714 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
716 #define S_QUEUESPERPAGEPF1 4
717 #define M_QUEUESPERPAGEPF1 0xfU
718 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
719 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
721 #define S_QUEUESPERPAGEPF0 0
722 #define M_QUEUESPERPAGEPF0 0xfU
723 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
724 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
726 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
728 #define S_QUEUESPERPAGEVFPF7 28
729 #define M_QUEUESPERPAGEVFPF7 0xfU
730 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
731 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
733 #define S_QUEUESPERPAGEVFPF6 24
734 #define M_QUEUESPERPAGEVFPF6 0xfU
735 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
736 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
738 #define S_QUEUESPERPAGEVFPF5 20
739 #define M_QUEUESPERPAGEVFPF5 0xfU
740 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
741 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
743 #define S_QUEUESPERPAGEVFPF4 16
744 #define M_QUEUESPERPAGEVFPF4 0xfU
745 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
746 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
748 #define S_QUEUESPERPAGEVFPF3 12
749 #define M_QUEUESPERPAGEVFPF3 0xfU
750 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
751 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
753 #define S_QUEUESPERPAGEVFPF2 8
754 #define M_QUEUESPERPAGEVFPF2 0xfU
755 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
756 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
758 #define S_QUEUESPERPAGEVFPF1 4
759 #define M_QUEUESPERPAGEVFPF1 0xfU
760 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
761 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
763 #define S_QUEUESPERPAGEVFPF0 0
764 #define M_QUEUESPERPAGEVFPF0 0xfU
765 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
766 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
768 #define A_SGE_USER_MODE_LIMITS 0x1018
770 #define S_OPCODE_MIN 24
771 #define M_OPCODE_MIN 0xffU
772 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
773 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
775 #define S_OPCODE_MAX 16
776 #define M_OPCODE_MAX 0xffU
777 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
778 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
780 #define S_LENGTH_MIN 8
781 #define M_LENGTH_MIN 0xffU
782 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
783 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
785 #define S_LENGTH_MAX 0
786 #define M_LENGTH_MAX 0xffU
787 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
788 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
790 #define A_SGE_WR_ERROR 0x101c
792 #define S_WR_ERROR_OPCODE 0
793 #define M_WR_ERROR_OPCODE 0xffU
794 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
795 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
797 #define A_SGE_PERR_INJECT 0x1020
800 #define M_MEMSEL 0x1fU
801 #define V_MEMSEL(x) ((x) << S_MEMSEL)
802 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
804 #define S_INJECTDATAERR 0
805 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
806 #define F_INJECTDATAERR V_INJECTDATAERR(1U)
808 #define A_SGE_INT_CAUSE1 0x1024
810 #define S_PERR_FLM_CREDITFIFO 30
811 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
812 #define F_PERR_FLM_CREDITFIFO V_PERR_FLM_CREDITFIFO(1U)
814 #define S_PERR_IMSG_HINT_FIFO 29
815 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
816 #define F_PERR_IMSG_HINT_FIFO V_PERR_IMSG_HINT_FIFO(1U)
818 #define S_PERR_MC_PC 28
819 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
820 #define F_PERR_MC_PC V_PERR_MC_PC(1U)
822 #define S_PERR_MC_IGR_CTXT 27
823 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
824 #define F_PERR_MC_IGR_CTXT V_PERR_MC_IGR_CTXT(1U)
826 #define S_PERR_MC_EGR_CTXT 26
827 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
828 #define F_PERR_MC_EGR_CTXT V_PERR_MC_EGR_CTXT(1U)
830 #define S_PERR_MC_FLM 25
831 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
832 #define F_PERR_MC_FLM V_PERR_MC_FLM(1U)
834 #define S_PERR_PC_MCTAG 24
835 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
836 #define F_PERR_PC_MCTAG V_PERR_PC_MCTAG(1U)
838 #define S_PERR_PC_CHPI_RSP1 23
839 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
840 #define F_PERR_PC_CHPI_RSP1 V_PERR_PC_CHPI_RSP1(1U)
842 #define S_PERR_PC_CHPI_RSP0 22
843 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
844 #define F_PERR_PC_CHPI_RSP0 V_PERR_PC_CHPI_RSP0(1U)
846 #define S_PERR_DBP_PC_RSP_FIFO3 21
847 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
848 #define F_PERR_DBP_PC_RSP_FIFO3 V_PERR_DBP_PC_RSP_FIFO3(1U)
850 #define S_PERR_DBP_PC_RSP_FIFO2 20
851 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
852 #define F_PERR_DBP_PC_RSP_FIFO2 V_PERR_DBP_PC_RSP_FIFO2(1U)
854 #define S_PERR_DBP_PC_RSP_FIFO1 19
855 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
856 #define F_PERR_DBP_PC_RSP_FIFO1 V_PERR_DBP_PC_RSP_FIFO1(1U)
858 #define S_PERR_DBP_PC_RSP_FIFO0 18
859 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
860 #define F_PERR_DBP_PC_RSP_FIFO0 V_PERR_DBP_PC_RSP_FIFO0(1U)
862 #define S_PERR_DMARBT 17
863 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
864 #define F_PERR_DMARBT V_PERR_DMARBT(1U)
866 #define S_PERR_FLM_DBPFIFO 16
867 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
868 #define F_PERR_FLM_DBPFIFO V_PERR_FLM_DBPFIFO(1U)
870 #define S_PERR_FLM_MCREQ_FIFO 15
871 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
872 #define F_PERR_FLM_MCREQ_FIFO V_PERR_FLM_MCREQ_FIFO(1U)
874 #define S_PERR_FLM_HINTFIFO 14
875 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
876 #define F_PERR_FLM_HINTFIFO V_PERR_FLM_HINTFIFO(1U)
878 #define S_PERR_ALIGN_CTL_FIFO3 13
879 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
880 #define F_PERR_ALIGN_CTL_FIFO3 V_PERR_ALIGN_CTL_FIFO3(1U)
882 #define S_PERR_ALIGN_CTL_FIFO2 12
883 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
884 #define F_PERR_ALIGN_CTL_FIFO2 V_PERR_ALIGN_CTL_FIFO2(1U)
886 #define S_PERR_ALIGN_CTL_FIFO1 11
887 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
888 #define F_PERR_ALIGN_CTL_FIFO1 V_PERR_ALIGN_CTL_FIFO1(1U)
890 #define S_PERR_ALIGN_CTL_FIFO0 10
891 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
892 #define F_PERR_ALIGN_CTL_FIFO0 V_PERR_ALIGN_CTL_FIFO0(1U)
894 #define S_PERR_EDMA_FIFO3 9
895 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
896 #define F_PERR_EDMA_FIFO3 V_PERR_EDMA_FIFO3(1U)
898 #define S_PERR_EDMA_FIFO2 8
899 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
900 #define F_PERR_EDMA_FIFO2 V_PERR_EDMA_FIFO2(1U)
902 #define S_PERR_EDMA_FIFO1 7
903 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
904 #define F_PERR_EDMA_FIFO1 V_PERR_EDMA_FIFO1(1U)
906 #define S_PERR_EDMA_FIFO0 6
907 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
908 #define F_PERR_EDMA_FIFO0 V_PERR_EDMA_FIFO0(1U)
910 #define S_PERR_PD_FIFO3 5
911 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
912 #define F_PERR_PD_FIFO3 V_PERR_PD_FIFO3(1U)
914 #define S_PERR_PD_FIFO2 4
915 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
916 #define F_PERR_PD_FIFO2 V_PERR_PD_FIFO2(1U)
918 #define S_PERR_PD_FIFO1 3
919 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
920 #define F_PERR_PD_FIFO1 V_PERR_PD_FIFO1(1U)
922 #define S_PERR_PD_FIFO0 2
923 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
924 #define F_PERR_PD_FIFO0 V_PERR_PD_FIFO0(1U)
926 #define S_PERR_ING_CTXT_MIFRSP 1
927 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
928 #define F_PERR_ING_CTXT_MIFRSP V_PERR_ING_CTXT_MIFRSP(1U)
930 #define S_PERR_EGR_CTXT_MIFRSP 0
931 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
932 #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U)
934 #define S_PERR_PC_CHPI_RSP2 31
935 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
936 #define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U)
938 #define S_PERR_PC_RSP 23
939 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
940 #define F_PERR_PC_RSP V_PERR_PC_RSP(1U)
942 #define S_PERR_PC_REQ 22
943 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
944 #define F_PERR_PC_REQ V_PERR_PC_REQ(1U)
946 #define A_SGE_INT_ENABLE1 0x1028
947 #define A_SGE_PERR_ENABLE1 0x102c
948 #define A_SGE_INT_CAUSE2 0x1030
950 #define S_PERR_HINT_DELAY_FIFO1 30
951 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
952 #define F_PERR_HINT_DELAY_FIFO1 V_PERR_HINT_DELAY_FIFO1(1U)
954 #define S_PERR_HINT_DELAY_FIFO0 29
955 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
956 #define F_PERR_HINT_DELAY_FIFO0 V_PERR_HINT_DELAY_FIFO0(1U)
958 #define S_PERR_IMSG_PD_FIFO 28
959 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
960 #define F_PERR_IMSG_PD_FIFO V_PERR_IMSG_PD_FIFO(1U)
962 #define S_PERR_ULPTX_FIFO1 27
963 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
964 #define F_PERR_ULPTX_FIFO1 V_PERR_ULPTX_FIFO1(1U)
966 #define S_PERR_ULPTX_FIFO0 26
967 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
968 #define F_PERR_ULPTX_FIFO0 V_PERR_ULPTX_FIFO0(1U)
970 #define S_PERR_IDMA2IMSG_FIFO1 25
971 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
972 #define F_PERR_IDMA2IMSG_FIFO1 V_PERR_IDMA2IMSG_FIFO1(1U)
974 #define S_PERR_IDMA2IMSG_FIFO0 24
975 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
976 #define F_PERR_IDMA2IMSG_FIFO0 V_PERR_IDMA2IMSG_FIFO0(1U)
978 #define S_PERR_HEADERSPLIT_FIFO1 23
979 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
980 #define F_PERR_HEADERSPLIT_FIFO1 V_PERR_HEADERSPLIT_FIFO1(1U)
982 #define S_PERR_HEADERSPLIT_FIFO0 22
983 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
984 #define F_PERR_HEADERSPLIT_FIFO0 V_PERR_HEADERSPLIT_FIFO0(1U)
986 #define S_PERR_ESWITCH_FIFO3 21
987 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
988 #define F_PERR_ESWITCH_FIFO3 V_PERR_ESWITCH_FIFO3(1U)
990 #define S_PERR_ESWITCH_FIFO2 20
991 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
992 #define F_PERR_ESWITCH_FIFO2 V_PERR_ESWITCH_FIFO2(1U)
994 #define S_PERR_ESWITCH_FIFO1 19
995 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
996 #define F_PERR_ESWITCH_FIFO1 V_PERR_ESWITCH_FIFO1(1U)
998 #define S_PERR_ESWITCH_FIFO0 18
999 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
1000 #define F_PERR_ESWITCH_FIFO0 V_PERR_ESWITCH_FIFO0(1U)
1002 #define S_PERR_PC_DBP1 17
1003 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
1004 #define F_PERR_PC_DBP1 V_PERR_PC_DBP1(1U)
1006 #define S_PERR_PC_DBP0 16
1007 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
1008 #define F_PERR_PC_DBP0 V_PERR_PC_DBP0(1U)
1010 #define S_PERR_IMSG_OB_FIFO 15
1011 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
1012 #define F_PERR_IMSG_OB_FIFO V_PERR_IMSG_OB_FIFO(1U)
1014 #define S_PERR_CONM_SRAM 14
1015 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
1016 #define F_PERR_CONM_SRAM V_PERR_CONM_SRAM(1U)
1018 #define S_PERR_PC_MC_RSP 13
1019 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
1020 #define F_PERR_PC_MC_RSP V_PERR_PC_MC_RSP(1U)
1022 #define S_PERR_ISW_IDMA0_FIFO 12
1023 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
1024 #define F_PERR_ISW_IDMA0_FIFO V_PERR_ISW_IDMA0_FIFO(1U)
1026 #define S_PERR_ISW_IDMA1_FIFO 11
1027 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
1028 #define F_PERR_ISW_IDMA1_FIFO V_PERR_ISW_IDMA1_FIFO(1U)
1030 #define S_PERR_ISW_DBP_FIFO 10
1031 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
1032 #define F_PERR_ISW_DBP_FIFO V_PERR_ISW_DBP_FIFO(1U)
1034 #define S_PERR_ISW_GTS_FIFO 9
1035 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
1036 #define F_PERR_ISW_GTS_FIFO V_PERR_ISW_GTS_FIFO(1U)
1038 #define S_PERR_ITP_EVR 8
1039 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
1040 #define F_PERR_ITP_EVR V_PERR_ITP_EVR(1U)
1042 #define S_PERR_FLM_CNTXMEM 7
1043 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1044 #define F_PERR_FLM_CNTXMEM V_PERR_FLM_CNTXMEM(1U)
1046 #define S_PERR_FLM_L1CACHE 6
1047 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1048 #define F_PERR_FLM_L1CACHE V_PERR_FLM_L1CACHE(1U)
1050 #define S_PERR_DBP_HINT_FIFO 5
1051 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1052 #define F_PERR_DBP_HINT_FIFO V_PERR_DBP_HINT_FIFO(1U)
1054 #define S_PERR_DBP_HP_FIFO 4
1055 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1056 #define F_PERR_DBP_HP_FIFO V_PERR_DBP_HP_FIFO(1U)
1058 #define S_PERR_DBP_LP_FIFO 3
1059 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1060 #define F_PERR_DBP_LP_FIFO V_PERR_DBP_LP_FIFO(1U)
1062 #define S_PERR_ING_CTXT_CACHE 2
1063 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1064 #define F_PERR_ING_CTXT_CACHE V_PERR_ING_CTXT_CACHE(1U)
1066 #define S_PERR_EGR_CTXT_CACHE 1
1067 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1068 #define F_PERR_EGR_CTXT_CACHE V_PERR_EGR_CTXT_CACHE(1U)
1070 #define S_PERR_BASE_SIZE 0
1071 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1072 #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U)
1074 #define S_PERR_DBP_HINT_FL_FIFO 24
1075 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1076 #define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U)
1078 #define S_PERR_EGR_DBP_TX_COAL 23
1079 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1080 #define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U)
1082 #define S_PERR_DBP_FL_FIFO 22
1083 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1084 #define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U)
1086 #define S_PERR_PC_DBP2 15
1087 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1088 #define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U)
1090 #define S_DEQ_LL_PERR 21
1091 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1092 #define F_DEQ_LL_PERR V_DEQ_LL_PERR(1U)
1094 #define S_ENQ_PERR 20
1095 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1096 #define F_ENQ_PERR V_ENQ_PERR(1U)
1098 #define S_DEQ_OUT_PERR 19
1099 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1100 #define F_DEQ_OUT_PERR V_DEQ_OUT_PERR(1U)
1102 #define S_BUF_PERR 18
1103 #define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1104 #define F_BUF_PERR V_BUF_PERR(1U)
1106 #define S_PERR_DB_FIFO 3
1107 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1108 #define F_PERR_DB_FIFO V_PERR_DB_FIFO(1U)
1110 #define A_SGE_INT_ENABLE2 0x1034
1111 #define A_SGE_PERR_ENABLE2 0x1038
1112 #define A_SGE_INT_CAUSE3 0x103c
1114 #define S_ERR_FLM_DBP 31
1115 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1116 #define F_ERR_FLM_DBP V_ERR_FLM_DBP(1U)
1118 #define S_ERR_FLM_IDMA1 30
1119 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1120 #define F_ERR_FLM_IDMA1 V_ERR_FLM_IDMA1(1U)
1122 #define S_ERR_FLM_IDMA0 29
1123 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1124 #define F_ERR_FLM_IDMA0 V_ERR_FLM_IDMA0(1U)
1126 #define S_ERR_FLM_HINT 28
1127 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1128 #define F_ERR_FLM_HINT V_ERR_FLM_HINT(1U)
1130 #define S_ERR_PCIE_ERROR3 27
1131 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1132 #define F_ERR_PCIE_ERROR3 V_ERR_PCIE_ERROR3(1U)
1134 #define S_ERR_PCIE_ERROR2 26
1135 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1136 #define F_ERR_PCIE_ERROR2 V_ERR_PCIE_ERROR2(1U)
1138 #define S_ERR_PCIE_ERROR1 25
1139 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1140 #define F_ERR_PCIE_ERROR1 V_ERR_PCIE_ERROR1(1U)
1142 #define S_ERR_PCIE_ERROR0 24
1143 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1144 #define F_ERR_PCIE_ERROR0 V_ERR_PCIE_ERROR0(1U)
1146 #define S_ERR_TIMER_ABOVE_MAX_QID 23
1147 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1148 #define F_ERR_TIMER_ABOVE_MAX_QID V_ERR_TIMER_ABOVE_MAX_QID(1U)
1150 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
1151 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1152 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1154 #define S_ERR_INVALID_CIDX_INC 21
1155 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1156 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
1158 #define S_ERR_ITP_TIME_PAUSED 20
1159 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1160 #define F_ERR_ITP_TIME_PAUSED V_ERR_ITP_TIME_PAUSED(1U)
1162 #define S_ERR_CPL_OPCODE_0 19
1163 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1164 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
1166 #define S_ERR_DROPPED_DB 18
1167 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1168 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
1170 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
1171 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1172 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1174 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
1175 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1176 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1178 #define S_ERR_BAD_DB_PIDX3 15
1179 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1180 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
1182 #define S_ERR_BAD_DB_PIDX2 14
1183 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1184 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
1186 #define S_ERR_BAD_DB_PIDX1 13
1187 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1188 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
1190 #define S_ERR_BAD_DB_PIDX0 12
1191 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1192 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
1194 #define S_ERR_ING_PCIE_CHAN 11
1195 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1196 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
1198 #define S_ERR_ING_CTXT_PRIO 10
1199 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1200 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
1202 #define S_ERR_EGR_CTXT_PRIO 9
1203 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1204 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
1206 #define S_DBFIFO_HP_INT 8
1207 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1208 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
1210 #define S_DBFIFO_LP_INT 7
1211 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1212 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
1214 #define S_REG_ADDRESS_ERR 6
1215 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1216 #define F_REG_ADDRESS_ERR V_REG_ADDRESS_ERR(1U)
1218 #define S_INGRESS_SIZE_ERR 5
1219 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1220 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
1222 #define S_EGRESS_SIZE_ERR 4
1223 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1224 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
1226 #define S_ERR_INV_CTXT3 3
1227 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1228 #define F_ERR_INV_CTXT3 V_ERR_INV_CTXT3(1U)
1230 #define S_ERR_INV_CTXT2 2
1231 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1232 #define F_ERR_INV_CTXT2 V_ERR_INV_CTXT2(1U)
1234 #define S_ERR_INV_CTXT1 1
1235 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1236 #define F_ERR_INV_CTXT1 V_ERR_INV_CTXT1(1U)
1238 #define S_ERR_INV_CTXT0 0
1239 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1240 #define F_ERR_INV_CTXT0 V_ERR_INV_CTXT0(1U)
1242 #define S_DBP_TBUF_FULL 8
1243 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1244 #define F_DBP_TBUF_FULL V_DBP_TBUF_FULL(1U)
1246 #define S_FATAL_WRE_LEN 7
1247 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1248 #define F_FATAL_WRE_LEN V_FATAL_WRE_LEN(1U)
1250 #define A_SGE_INT_ENABLE3 0x1040
1251 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1254 #define CXGBE_M_SIZE 0xfffffffU
1255 #define V_SIZE(x) ((x) << S_SIZE)
1256 #define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
1259 #define M_T6_SIZE 0xfffffU
1260 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1261 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1263 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1266 #define M_T6_SIZE 0xfffffU
1267 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1268 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1270 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1273 #define M_T6_SIZE 0xfffffU
1274 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1275 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1277 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1280 #define M_T6_SIZE 0xfffffU
1281 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1282 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1284 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1287 #define M_T6_SIZE 0xfffffU
1288 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1289 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1291 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1294 #define M_T6_SIZE 0xfffffU
1295 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1296 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1298 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1301 #define M_T6_SIZE 0xfffffU
1302 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1303 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1305 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1308 #define M_T6_SIZE 0xfffffU
1309 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1310 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1312 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1315 #define M_T6_SIZE 0xfffffU
1316 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1317 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1319 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1322 #define M_T6_SIZE 0xfffffU
1323 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1324 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1326 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1329 #define M_T6_SIZE 0xfffffU
1330 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1331 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1333 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1336 #define M_T6_SIZE 0xfffffU
1337 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1338 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1340 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1343 #define M_T6_SIZE 0xfffffU
1344 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1345 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1347 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1350 #define M_T6_SIZE 0xfffffU
1351 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1352 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1354 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1357 #define M_T6_SIZE 0xfffffU
1358 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1359 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1361 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1364 #define M_T6_SIZE 0xfffffU
1365 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1366 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1368 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1370 #define S_BASEADDR 3
1371 #define M_BASEADDR 0x1fffffffU
1372 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1373 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1375 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1376 #define A_SGE_FLM_CACHE_BADDR 0x108c
1377 #define A_SGE_FLM_CFG 0x1090
1380 #define M_OPMODE 0x3fU
1381 #define V_OPMODE(x) ((x) << S_OPMODE)
1382 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1385 #define V_NOHDR(x) ((x) << S_NOHDR)
1386 #define F_NOHDR V_NOHDR(1U)
1388 #define S_CACHEPTRCNT 16
1389 #define M_CACHEPTRCNT 0x3U
1390 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1391 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1393 #define S_EDRAMPTRCNT 14
1394 #define M_EDRAMPTRCNT 0x3U
1395 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1396 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1398 #define S_HDRSTARTFLQ 11
1399 #define M_HDRSTARTFLQ 0x7U
1400 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1401 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1403 #define S_FETCHTHRESH 6
1404 #define M_FETCHTHRESH 0x1fU
1405 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1406 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1408 #define S_CREDITCNT 4
1409 #define M_CREDITCNT 0x3U
1410 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1411 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1414 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1415 #define F_NOEDRAM V_NOEDRAM(1U)
1417 #define S_CREDITCNTPACKING 2
1418 #define M_CREDITCNTPACKING 0x3U
1419 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1420 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1422 #define S_NULLPTR 20
1423 #define M_NULLPTR 0xfU
1424 #define V_NULLPTR(x) ((x) << S_NULLPTR)
1425 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1427 #define S_NULLPTREN 19
1428 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1429 #define F_NULLPTREN V_NULLPTREN(1U)
1431 #define A_SGE_CONM_CTRL 0x1094
1433 #define S_EGRTHRESHOLD 8
1434 #define M_EGRTHRESHOLD 0x3fU
1435 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1436 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1438 #define S_INGTHRESHOLD 2
1439 #define M_INGTHRESHOLD 0x3fU
1440 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1441 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1443 #define S_MPS_ENABLE 1
1444 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1445 #define F_MPS_ENABLE V_MPS_ENABLE(1U)
1447 #define S_TP_ENABLE 0
1448 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1449 #define F_TP_ENABLE V_TP_ENABLE(1U)
1451 #define S_EGRTHRESHOLDPACKING 14
1452 #define M_EGRTHRESHOLDPACKING 0x3fU
1453 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1454 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1456 #define S_T6_EGRTHRESHOLDPACKING 16
1457 #define M_T6_EGRTHRESHOLDPACKING 0xffU
1458 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1459 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1461 #define S_T6_EGRTHRESHOLD 8
1462 #define M_T6_EGRTHRESHOLD 0xffU
1463 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1464 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1466 #define A_SGE_TIMESTAMP_LO 0x1098
1467 #define A_SGE_TIMESTAMP_HI 0x109c
1471 #define V_TSOP(x) ((x) << S_TSOP)
1472 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1475 #define M_TSVAL 0xfffffffU
1476 #define V_TSVAL(x) ((x) << S_TSVAL)
1477 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1479 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1481 #define S_THRESHOLD_0 24
1482 #define M_THRESHOLD_0 0x3fU
1483 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1484 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1486 #define S_THRESHOLD_1 16
1487 #define M_THRESHOLD_1 0x3fU
1488 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1489 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1491 #define S_THRESHOLD_2 8
1492 #define M_THRESHOLD_2 0x3fU
1493 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1494 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1496 #define S_THRESHOLD_3 0
1497 #define M_THRESHOLD_3 0x3fU
1498 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1499 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1501 #define A_SGE_DBFIFO_STATUS 0x10a4
1503 #define S_HP_INT_THRESH 28
1504 #define M_HP_INT_THRESH 0xfU
1505 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1506 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1508 #define S_HP_COUNT 16
1509 #define M_HP_COUNT 0x7ffU
1510 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1511 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1513 #define S_LP_INT_THRESH 12
1514 #define M_LP_INT_THRESH 0xfU
1515 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1516 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1518 #define S_LP_COUNT 0
1519 #define M_LP_COUNT 0x7ffU
1520 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1521 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1523 #define S_BAR2VALID 31
1524 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1525 #define F_BAR2VALID V_BAR2VALID(1U)
1527 #define S_BAR2FULL 30
1528 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1529 #define F_BAR2FULL V_BAR2FULL(1U)
1531 #define S_LP_INT_THRESH_T5 18
1532 #define M_LP_INT_THRESH_T5 0xfffU
1533 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1534 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1536 #define S_LP_COUNT_T5 0
1537 #define M_LP_COUNT_T5 0x3ffffU
1538 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1539 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1541 #define S_VFIFO_CNT 15
1542 #define M_VFIFO_CNT 0x1ffffU
1543 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1544 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1546 #define S_COAL_CTL_FIFO_CNT 8
1547 #define M_COAL_CTL_FIFO_CNT 0x3fU
1548 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1549 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1551 #define S_MERGE_FIFO_CNT 0
1552 #define M_MERGE_FIFO_CNT 0x3fU
1553 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1554 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1556 #define A_SGE_DOORBELL_CONTROL 0x10a8
1558 #define S_HINTDEPTHCTL 27
1559 #define M_HINTDEPTHCTL 0x1fU
1560 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1561 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1563 #define S_NOCOALESCE 26
1564 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1565 #define F_NOCOALESCE V_NOCOALESCE(1U)
1567 #define S_HP_WEIGHT 24
1568 #define M_HP_WEIGHT 0x3U
1569 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1570 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1572 #define S_HP_DISABLE 23
1573 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1574 #define F_HP_DISABLE V_HP_DISABLE(1U)
1576 #define S_FORCEUSERDBTOLP 22
1577 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1578 #define F_FORCEUSERDBTOLP V_FORCEUSERDBTOLP(1U)
1580 #define S_FORCEVFPF0DBTOLP 21
1581 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1582 #define F_FORCEVFPF0DBTOLP V_FORCEVFPF0DBTOLP(1U)
1584 #define S_FORCEVFPF1DBTOLP 20
1585 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1586 #define F_FORCEVFPF1DBTOLP V_FORCEVFPF1DBTOLP(1U)
1588 #define S_FORCEVFPF2DBTOLP 19
1589 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1590 #define F_FORCEVFPF2DBTOLP V_FORCEVFPF2DBTOLP(1U)
1592 #define S_FORCEVFPF3DBTOLP 18
1593 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1594 #define F_FORCEVFPF3DBTOLP V_FORCEVFPF3DBTOLP(1U)
1596 #define S_FORCEVFPF4DBTOLP 17
1597 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1598 #define F_FORCEVFPF4DBTOLP V_FORCEVFPF4DBTOLP(1U)
1600 #define S_FORCEVFPF5DBTOLP 16
1601 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1602 #define F_FORCEVFPF5DBTOLP V_FORCEVFPF5DBTOLP(1U)
1604 #define S_FORCEVFPF6DBTOLP 15
1605 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1606 #define F_FORCEVFPF6DBTOLP V_FORCEVFPF6DBTOLP(1U)
1608 #define S_FORCEVFPF7DBTOLP 14
1609 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1610 #define F_FORCEVFPF7DBTOLP V_FORCEVFPF7DBTOLP(1U)
1612 #define S_ENABLE_DROP 13
1613 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1614 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
1616 #define S_DROP_TIMEOUT 1
1617 #define M_DROP_TIMEOUT 0xfffU
1618 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1619 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1621 #define S_DROPPED_DB 0
1622 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1623 #define F_DROPPED_DB V_DROPPED_DB(1U)
1625 #define S_T6_DROP_TIMEOUT 7
1626 #define M_T6_DROP_TIMEOUT 0x3fU
1627 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1628 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1630 #define S_INVONDBSYNC 6
1631 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1632 #define F_INVONDBSYNC V_INVONDBSYNC(1U)
1634 #define S_INVONGTSSYNC 5
1635 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1636 #define F_INVONGTSSYNC V_INVONGTSSYNC(1U)
1638 #define S_DB_DBG_EN 4
1639 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1640 #define F_DB_DBG_EN V_DB_DBG_EN(1U)
1642 #define S_GTS_DBG_TIMER_REG 1
1643 #define M_GTS_DBG_TIMER_REG 0x7U
1644 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1645 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1647 #define S_GTS_DBG_EN 0
1648 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1649 #define F_GTS_DBG_EN V_GTS_DBG_EN(1U)
1651 #define A_SGE_DROPPED_DOORBELL 0x10ac
1652 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1654 #define S_THROTTLE_COUNT 1
1655 #define M_THROTTLE_COUNT 0xfffU
1656 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1657 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1659 #define S_THROTTLE_ENABLE 0
1660 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1661 #define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U)
1663 #define S_BAR2THROTTLECOUNT 16
1664 #define M_BAR2THROTTLECOUNT 0xffU
1665 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1666 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1668 #define S_CLRCOALESCEDISABLE 15
1669 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1670 #define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U)
1672 #define S_OPENBAR2GATEONCE 14
1673 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1674 #define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U)
1676 #define S_FORCEOPENBAR2GATE 13
1677 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1678 #define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U)
1680 #define A_SGE_ITP_CONTROL 0x10b4
1682 #define S_CRITICAL_TIME 10
1683 #define M_CRITICAL_TIME 0x7fffU
1684 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1685 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1687 #define S_LL_EMPTY 4
1688 #define M_LL_EMPTY 0x3fU
1689 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1690 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1692 #define S_LL_READ_WAIT_DISABLE 0
1693 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1694 #define F_LL_READ_WAIT_DISABLE V_LL_READ_WAIT_DISABLE(1U)
1697 #define M_TSCALE 0xfU
1698 #define V_TSCALE(x) ((x) << S_TSCALE)
1699 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1701 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1703 #define S_TIMERVALUE0 16
1704 #define M_TIMERVALUE0 0xffffU
1705 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1706 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1708 #define S_TIMERVALUE1 0
1709 #define M_TIMERVALUE1 0xffffU
1710 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1711 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1713 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1715 #define S_TIMERVALUE2 16
1716 #define M_TIMERVALUE2 0xffffU
1717 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1718 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1720 #define S_TIMERVALUE3 0
1721 #define M_TIMERVALUE3 0xffffU
1722 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1723 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1725 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1727 #define S_TIMERVALUE4 16
1728 #define M_TIMERVALUE4 0xffffU
1729 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1730 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1732 #define S_TIMERVALUE5 0
1733 #define M_TIMERVALUE5 0xffffU
1734 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1735 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1737 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1739 #define S_RSPCREDITEN0 31
1740 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1741 #define F_RSPCREDITEN0 V_RSPCREDITEN0(1U)
1743 #define S_MAXTAG0 24
1744 #define M_MAXTAG0 0x7fU
1745 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1746 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1748 #define S_MAXRSPCNT0 16
1749 #define M_MAXRSPCNT0 0xffU
1750 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1751 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1753 #define S_RSPCREDITEN1 15
1754 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1755 #define F_RSPCREDITEN1 V_RSPCREDITEN1(1U)
1758 #define M_MAXTAG1 0x7fU
1759 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1760 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1762 #define S_MAXRSPCNT1 0
1763 #define M_MAXRSPCNT1 0xffU
1764 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1765 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1767 #define A_SGE_GK_CONTROL 0x10c4
1769 #define S_EN_FLM_FIFTH 29
1770 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1771 #define F_EN_FLM_FIFTH V_EN_FLM_FIFTH(1U)
1773 #define S_FL_PROG_THRESH 20
1774 #define M_FL_PROG_THRESH 0x1ffU
1775 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1776 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1778 #define S_COAL_ALL_THREAD 19
1779 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1780 #define F_COAL_ALL_THREAD V_COAL_ALL_THREAD(1U)
1782 #define S_EN_PSHB 18
1783 #define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1784 #define F_EN_PSHB V_EN_PSHB(1U)
1786 #define S_EN_DB_FIFTH 17
1787 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1788 #define F_EN_DB_FIFTH V_EN_DB_FIFTH(1U)
1790 #define S_DB_PROG_THRESH 8
1791 #define M_DB_PROG_THRESH 0x1ffU
1792 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1793 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1795 #define S_100NS_TIMER 0
1796 #define M_100NS_TIMER 0xffU
1797 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1798 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1800 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1802 #define S_RSPCREDITEN2 31
1803 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1804 #define F_RSPCREDITEN2 V_RSPCREDITEN2(1U)
1806 #define S_MAXTAG2 24
1807 #define M_MAXTAG2 0x7fU
1808 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1809 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1811 #define S_MAXRSPCNT2 16
1812 #define M_MAXRSPCNT2 0xffU
1813 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1814 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1816 #define S_RSPCREDITEN3 15
1817 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1818 #define F_RSPCREDITEN3 V_RSPCREDITEN3(1U)
1821 #define M_MAXTAG3 0x7fU
1822 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1823 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1825 #define S_MAXRSPCNT3 0
1826 #define M_MAXRSPCNT3 0xffU
1827 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1828 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1830 #define A_SGE_GK_CONTROL2 0x10c8
1832 #define S_DBQ_TIMER_TICK 16
1833 #define M_DBQ_TIMER_TICK 0xffffU
1834 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1835 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1837 #define S_FL_MERGE_CNT_THRESH 8
1838 #define M_FL_MERGE_CNT_THRESH 0xfU
1839 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1840 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1842 #define S_MERGE_CNT_THRESH 0
1843 #define M_MERGE_CNT_THRESH 0x3fU
1844 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1845 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1847 #define A_SGE_DEBUG_INDEX 0x10cc
1848 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1849 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1850 #define A_SGE_REVISION 0x10d8
1851 #define A_SGE_INT_CAUSE4 0x10dc
1853 #define S_ERR_BAD_UPFL_INC_CREDIT3 8
1854 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1855 #define F_ERR_BAD_UPFL_INC_CREDIT3 V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1857 #define S_ERR_BAD_UPFL_INC_CREDIT2 7
1858 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1859 #define F_ERR_BAD_UPFL_INC_CREDIT2 V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1861 #define S_ERR_BAD_UPFL_INC_CREDIT1 6
1862 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1863 #define F_ERR_BAD_UPFL_INC_CREDIT1 V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1865 #define S_ERR_BAD_UPFL_INC_CREDIT0 5
1866 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1867 #define F_ERR_BAD_UPFL_INC_CREDIT0 V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1869 #define S_ERR_PHYSADDR_LEN0_IDMA1 4
1870 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1871 #define F_ERR_PHYSADDR_LEN0_IDMA1 V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1873 #define S_ERR_PHYSADDR_LEN0_IDMA0 3
1874 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1875 #define F_ERR_PHYSADDR_LEN0_IDMA0 V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1877 #define S_ERR_FLM_INVALID_PKT_DROP1 2
1878 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1879 #define F_ERR_FLM_INVALID_PKT_DROP1 V_ERR_FLM_INVALID_PKT_DROP1(1U)
1881 #define S_ERR_FLM_INVALID_PKT_DROP0 1
1882 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1883 #define F_ERR_FLM_INVALID_PKT_DROP0 V_ERR_FLM_INVALID_PKT_DROP0(1U)
1885 #define S_ERR_UNEXPECTED_TIMER 0
1886 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1887 #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U)
1889 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29
1890 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
1891 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
1893 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28
1894 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
1895 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
1897 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27
1898 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
1899 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
1901 #define S_ERR_WR_LEN_TOO_LARGE3 26
1902 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
1903 #define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U)
1905 #define S_ERR_WR_LEN_TOO_LARGE2 25
1906 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
1907 #define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U)
1909 #define S_ERR_WR_LEN_TOO_LARGE1 24
1910 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
1911 #define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U)
1913 #define S_ERR_WR_LEN_TOO_LARGE0 23
1914 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
1915 #define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U)
1917 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22
1918 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
1919 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
1921 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21
1922 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
1923 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
1925 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20
1926 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
1927 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
1929 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19
1930 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
1931 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
1933 #define S_COAL_WITH_HP_DISABLE_ERR 18
1934 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
1935 #define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U)
1937 #define S_BAR2_EGRESS_COAL0_ERR 17
1938 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
1939 #define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U)
1941 #define S_BAR2_EGRESS_SIZE_ERR 16
1942 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
1943 #define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U)
1945 #define S_FLM_PC_RSP_ERR 15
1946 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
1947 #define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U)
1949 #define S_DBFIFO_HP_INT_LOW 14
1950 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
1951 #define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U)
1953 #define S_DBFIFO_LP_INT_LOW 13
1954 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
1955 #define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U)
1957 #define S_DBFIFO_FL_INT_LOW 12
1958 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
1959 #define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U)
1961 #define S_DBFIFO_FL_INT 11
1962 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
1963 #define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U)
1965 #define S_ERR_RX_CPL_PACKET_SIZE1 10
1966 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
1967 #define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U)
1969 #define S_ERR_RX_CPL_PACKET_SIZE0 9
1970 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
1971 #define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U)
1973 #define S_ERR_ISHIFT_UR1 31
1974 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
1975 #define F_ERR_ISHIFT_UR1 V_ERR_ISHIFT_UR1(1U)
1977 #define S_ERR_ISHIFT_UR0 30
1978 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
1979 #define F_ERR_ISHIFT_UR0 V_ERR_ISHIFT_UR0(1U)
1981 #define S_ERR_TH3_MAX_FETCH 14
1982 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
1983 #define F_ERR_TH3_MAX_FETCH V_ERR_TH3_MAX_FETCH(1U)
1985 #define S_ERR_TH2_MAX_FETCH 13
1986 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
1987 #define F_ERR_TH2_MAX_FETCH V_ERR_TH2_MAX_FETCH(1U)
1989 #define S_ERR_TH1_MAX_FETCH 12
1990 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
1991 #define F_ERR_TH1_MAX_FETCH V_ERR_TH1_MAX_FETCH(1U)
1993 #define S_ERR_TH0_MAX_FETCH 11
1994 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
1995 #define F_ERR_TH0_MAX_FETCH V_ERR_TH0_MAX_FETCH(1U)
1997 #define A_SGE_INT_ENABLE4 0x10e0
1998 #define A_SGE_STAT_TOTAL 0x10e4
1999 #define A_SGE_STAT_MATCH 0x10e8
2000 #define A_SGE_STAT_CFG 0x10ec
2002 #define S_ITPOPMODE 8
2003 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
2004 #define F_ITPOPMODE V_ITPOPMODE(1U)
2006 #define S_EGRCTXTOPMODE 6
2007 #define M_EGRCTXTOPMODE 0x3U
2008 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
2009 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
2011 #define S_INGCTXTOPMODE 4
2012 #define M_INGCTXTOPMODE 0x3U
2013 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
2014 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
2016 #define S_STATMODE 2
2017 #define M_STATMODE 0x3U
2018 #define V_STATMODE(x) ((x) << S_STATMODE)
2019 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
2021 #define S_STATSOURCE 0
2022 #define M_STATSOURCE 0x3U
2023 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
2024 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
2026 #define S_STATSOURCE_T5 9
2027 #define M_STATSOURCE_T5 0xfU
2028 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
2029 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
2031 #define S_T6_STATMODE 0
2032 #define M_T6_STATMODE 0xfU
2033 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
2034 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
2036 #define A_SGE_HINT_CFG 0x10f0
2038 #define S_HINTSALLOWEDNOHDR 6
2039 #define M_HINTSALLOWEDNOHDR 0x3fU
2040 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
2041 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
2043 #define S_HINTSALLOWEDHDR 0
2044 #define M_HINTSALLOWEDHDR 0x3fU
2045 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
2046 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
2048 #define S_UPCUTOFFTHRESHLP 12
2049 #define M_UPCUTOFFTHRESHLP 0x7ffU
2050 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
2051 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
2053 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
2054 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
2055 #define A_SGE_PD_WRR_CONFIG 0x10fc
2057 #define S_EDMA_WEIGHT 0
2058 #define M_EDMA_WEIGHT 0x3fU
2059 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
2060 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
2062 #define A_SGE_ERROR_STATS 0x1100
2064 #define S_UNCAPTURED_ERROR 18
2065 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
2066 #define F_UNCAPTURED_ERROR V_UNCAPTURED_ERROR(1U)
2068 #define S_ERROR_QID_VALID 17
2069 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
2070 #define F_ERROR_QID_VALID V_ERROR_QID_VALID(1U)
2072 #define S_ERROR_QID 0
2073 #define M_ERROR_QID 0x1ffffU
2074 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
2075 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
2077 #define S_CAUSE_REGISTER 24
2078 #define M_CAUSE_REGISTER 0x7U
2079 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
2080 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
2082 #define S_CAUSE_BIT 19
2083 #define M_CAUSE_BIT 0x1fU
2084 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
2085 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
2087 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
2089 #define S_MINTAG3 24
2090 #define M_MINTAG3 0xffU
2091 #define V_MINTAG3(x) ((x) << S_MINTAG3)
2092 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
2094 #define S_MINTAG2 16
2095 #define M_MINTAG2 0xffU
2096 #define V_MINTAG2(x) ((x) << S_MINTAG2)
2097 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
2100 #define M_MINTAG1 0xffU
2101 #define V_MINTAG1(x) ((x) << S_MINTAG1)
2102 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
2105 #define M_MINTAG0 0xffU
2106 #define V_MINTAG0(x) ((x) << S_MINTAG0)
2107 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
2109 #define A_SGE_IDMA0_DROP_CNT 0x1104
2110 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
2112 #define S_TAGPOOLTOTAL 0
2113 #define M_TAGPOOLTOTAL 0xffU
2114 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
2115 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
2117 #define A_SGE_IDMA1_DROP_CNT 0x1108
2118 #define A_SGE_INT_CAUSE5 0x110c
2120 #define S_ERR_T_RXCRC 31
2121 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
2122 #define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U)
2124 #define S_PERR_MC_RSPDATA 30
2125 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
2126 #define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U)
2128 #define S_PERR_PC_RSPDATA 29
2129 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
2130 #define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U)
2132 #define S_PERR_PD_RDRSPDATA 28
2133 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
2134 #define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U)
2136 #define S_PERR_U_RXDATA 27
2137 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
2138 #define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U)
2140 #define S_PERR_UD_RXDATA 26
2141 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
2142 #define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U)
2144 #define S_PERR_UP_DATA 25
2145 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
2146 #define F_PERR_UP_DATA V_PERR_UP_DATA(1U)
2148 #define S_PERR_CIM2SGE_RXDATA 24
2149 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
2150 #define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U)
2152 #define S_PERR_HINT_DELAY_FIFO1_T5 23
2153 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
2154 #define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U)
2156 #define S_PERR_HINT_DELAY_FIFO0_T5 22
2157 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2158 #define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U)
2160 #define S_PERR_IMSG_PD_FIFO_T5 21
2161 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2162 #define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U)
2164 #define S_PERR_ULPTX_FIFO1_T5 20
2165 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2166 #define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U)
2168 #define S_PERR_ULPTX_FIFO0_T5 19
2169 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2170 #define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U)
2172 #define S_PERR_IDMA2IMSG_FIFO1_T5 18
2173 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2174 #define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2176 #define S_PERR_IDMA2IMSG_FIFO0_T5 17
2177 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2178 #define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2180 #define S_PERR_POINTER_DATA_FIFO0 16
2181 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2182 #define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U)
2184 #define S_PERR_POINTER_DATA_FIFO1 15
2185 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2186 #define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U)
2188 #define S_PERR_POINTER_HDR_FIFO0 14
2189 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2190 #define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U)
2192 #define S_PERR_POINTER_HDR_FIFO1 13
2193 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2194 #define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U)
2196 #define S_PERR_PAYLOAD_FIFO0 12
2197 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2198 #define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U)
2200 #define S_PERR_PAYLOAD_FIFO1 11
2201 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2202 #define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U)
2204 #define S_PERR_EDMA_INPUT_FIFO3 10
2205 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2206 #define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U)
2208 #define S_PERR_EDMA_INPUT_FIFO2 9
2209 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2210 #define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U)
2212 #define S_PERR_EDMA_INPUT_FIFO1 8
2213 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2214 #define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U)
2216 #define S_PERR_EDMA_INPUT_FIFO0 7
2217 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2218 #define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U)
2220 #define S_PERR_MGT_BAR2_FIFO 6
2221 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2222 #define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U)
2224 #define S_PERR_HEADERSPLIT_FIFO1_T5 5
2225 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2226 #define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2228 #define S_PERR_HEADERSPLIT_FIFO0_T5 4
2229 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2230 #define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2232 #define S_PERR_CIM_FIFO1 3
2233 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2234 #define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U)
2236 #define S_PERR_CIM_FIFO0 2
2237 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2238 #define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U)
2240 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1
2241 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2242 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2244 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0
2245 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2246 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2248 #define A_SGE_INT_ENABLE5 0x1110
2249 #define A_SGE_PERR_ENABLE5 0x1114
2250 #define A_SGE_DBFIFO_STATUS2 0x1118
2252 #define S_FL_INT_THRESH 24
2253 #define M_FL_INT_THRESH 0xfU
2254 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2255 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2257 #define S_FL_COUNT 14
2258 #define M_FL_COUNT 0x3ffU
2259 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2260 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2262 #define S_HP_INT_THRESH_T5 10
2263 #define M_HP_INT_THRESH_T5 0xfU
2264 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2265 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2267 #define S_HP_COUNT_T5 0
2268 #define M_HP_COUNT_T5 0x3ffU
2269 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2270 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2272 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2274 #define S_FETCHBURSTMAX0 16
2275 #define M_FETCHBURSTMAX0 0x3ffU
2276 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2277 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2279 #define S_FETCHBURSTMAX1 0
2280 #define M_FETCHBURSTMAX1 0x3ffU
2281 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2282 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2284 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2286 #define S_FETCHBURSTMAX2 16
2287 #define M_FETCHBURSTMAX2 0x3ffU
2288 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2289 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2291 #define S_FETCHBURSTMAX3 0
2292 #define M_FETCHBURSTMAX3 0x3ffU
2293 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2294 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2296 #define A_SGE_CONTROL2 0x1124
2298 #define S_UPFLCUTOFFDIS 21
2299 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2300 #define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U)
2302 #define S_RXCPLSIZEAUTOCORRECT 20
2303 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2304 #define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U)
2306 #define S_IDMAARBROUNDROBIN 19
2307 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2308 #define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U)
2310 #define S_INGPACKBOUNDARY 16
2311 #define M_INGPACKBOUNDARY 0x7U
2312 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2313 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2315 #define S_CGEN_EGRESS_CONTEXT 15
2316 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2317 #define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U)
2319 #define S_CGEN_INGRESS_CONTEXT 14
2320 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2321 #define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U)
2323 #define S_CGEN_IDMA 13
2324 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2325 #define F_CGEN_IDMA V_CGEN_IDMA(1U)
2327 #define S_CGEN_DBP 12
2328 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2329 #define F_CGEN_DBP V_CGEN_DBP(1U)
2331 #define S_CGEN_EDMA 11
2332 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2333 #define F_CGEN_EDMA V_CGEN_EDMA(1U)
2335 #define S_VFIFO_ENABLE 10
2336 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2337 #define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U)
2339 #define S_FLM_RESCHEDULE_MODE 9
2340 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2341 #define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U)
2343 #define S_HINTDEPTHCTLFL 4
2344 #define M_HINTDEPTHCTLFL 0x1fU
2345 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2346 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2348 #define S_FORCE_ORDERING 3
2349 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2350 #define F_FORCE_ORDERING V_FORCE_ORDERING(1U)
2352 #define S_TX_COALESCE_SIZE 2
2353 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2354 #define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U)
2356 #define S_COAL_STRICT_CIM_PRI 1
2357 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2358 #define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U)
2360 #define S_TX_COALESCE_PRI 0
2361 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2362 #define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U)
2364 #define A_SGE_DEEP_SLEEP 0x1128
2366 #define S_IDMA1_SLEEP_STATUS 11
2367 #define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
2368 #define F_IDMA1_SLEEP_STATUS V_IDMA1_SLEEP_STATUS(1U)
2370 #define S_IDMA0_SLEEP_STATUS 10
2371 #define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
2372 #define F_IDMA0_SLEEP_STATUS V_IDMA0_SLEEP_STATUS(1U)
2374 #define S_IDMA1_SLEEP_REQ 9
2375 #define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
2376 #define F_IDMA1_SLEEP_REQ V_IDMA1_SLEEP_REQ(1U)
2378 #define S_IDMA0_SLEEP_REQ 8
2379 #define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
2380 #define F_IDMA0_SLEEP_REQ V_IDMA0_SLEEP_REQ(1U)
2382 #define S_EDMA3_SLEEP_STATUS 7
2383 #define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
2384 #define F_EDMA3_SLEEP_STATUS V_EDMA3_SLEEP_STATUS(1U)
2386 #define S_EDMA2_SLEEP_STATUS 6
2387 #define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
2388 #define F_EDMA2_SLEEP_STATUS V_EDMA2_SLEEP_STATUS(1U)
2390 #define S_EDMA1_SLEEP_STATUS 5
2391 #define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
2392 #define F_EDMA1_SLEEP_STATUS V_EDMA1_SLEEP_STATUS(1U)
2394 #define S_EDMA0_SLEEP_STATUS 4
2395 #define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
2396 #define F_EDMA0_SLEEP_STATUS V_EDMA0_SLEEP_STATUS(1U)
2398 #define S_EDMA3_SLEEP_REQ 3
2399 #define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
2400 #define F_EDMA3_SLEEP_REQ V_EDMA3_SLEEP_REQ(1U)
2402 #define S_EDMA2_SLEEP_REQ 2
2403 #define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
2404 #define F_EDMA2_SLEEP_REQ V_EDMA2_SLEEP_REQ(1U)
2406 #define S_EDMA1_SLEEP_REQ 1
2407 #define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
2408 #define F_EDMA1_SLEEP_REQ V_EDMA1_SLEEP_REQ(1U)
2410 #define S_EDMA0_SLEEP_REQ 0
2411 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
2412 #define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U)
2414 #define A_SGE_INT_CAUSE6 0x1128
2416 #define S_ERR_DB_SYNC 21
2417 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2418 #define F_ERR_DB_SYNC V_ERR_DB_SYNC(1U)
2420 #define S_ERR_GTS_SYNC 20
2421 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2422 #define F_ERR_GTS_SYNC V_ERR_GTS_SYNC(1U)
2424 #define S_FATAL_LARGE_COAL 19
2425 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2426 #define F_FATAL_LARGE_COAL V_FATAL_LARGE_COAL(1U)
2428 #define S_PL_BAR2_FRM_ERR 18
2429 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2430 #define F_PL_BAR2_FRM_ERR V_PL_BAR2_FRM_ERR(1U)
2432 #define S_SILENT_DROP_TX_COAL 17
2433 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2434 #define F_SILENT_DROP_TX_COAL V_SILENT_DROP_TX_COAL(1U)
2436 #define S_ERR_INV_CTXT4 16
2437 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2438 #define F_ERR_INV_CTXT4 V_ERR_INV_CTXT4(1U)
2440 #define S_ERR_BAD_DB_PIDX4 15
2441 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2442 #define F_ERR_BAD_DB_PIDX4 V_ERR_BAD_DB_PIDX4(1U)
2444 #define S_ERR_BAD_UPFL_INC_CREDIT4 14
2445 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2446 #define F_ERR_BAD_UPFL_INC_CREDIT4 V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2448 #define S_FATAL_TAG_MISMATCH 13
2449 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2450 #define F_FATAL_TAG_MISMATCH V_FATAL_TAG_MISMATCH(1U)
2452 #define S_FATAL_ENQ_CTL_RDY 12
2453 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2454 #define F_FATAL_ENQ_CTL_RDY V_FATAL_ENQ_CTL_RDY(1U)
2456 #define S_ERR_PC_RSP_LEN3 11
2457 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2458 #define F_ERR_PC_RSP_LEN3 V_ERR_PC_RSP_LEN3(1U)
2460 #define S_ERR_PC_RSP_LEN2 10
2461 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2462 #define F_ERR_PC_RSP_LEN2 V_ERR_PC_RSP_LEN2(1U)
2464 #define S_ERR_PC_RSP_LEN1 9
2465 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2466 #define F_ERR_PC_RSP_LEN1 V_ERR_PC_RSP_LEN1(1U)
2468 #define S_ERR_PC_RSP_LEN0 8
2469 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2470 #define F_ERR_PC_RSP_LEN0 V_ERR_PC_RSP_LEN0(1U)
2472 #define S_FATAL_ENQ2LL_VLD 7
2473 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2474 #define F_FATAL_ENQ2LL_VLD V_FATAL_ENQ2LL_VLD(1U)
2476 #define S_FATAL_LL_EMPTY 6
2477 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2478 #define F_FATAL_LL_EMPTY V_FATAL_LL_EMPTY(1U)
2480 #define S_FATAL_OFF_WDENQ 5
2481 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2482 #define F_FATAL_OFF_WDENQ V_FATAL_OFF_WDENQ(1U)
2484 #define S_FATAL_DEQ_DRDY 3
2485 #define M_FATAL_DEQ_DRDY 0x3U
2486 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2487 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2489 #define S_FATAL_OUTP_DRDY 1
2490 #define M_FATAL_OUTP_DRDY 0x3U
2491 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2492 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2494 #define S_FATAL_DEQ 0
2495 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2496 #define F_FATAL_DEQ V_FATAL_DEQ(1U)
2498 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
2500 #define S_THROTTLE_THRESHOLD_FL 16
2501 #define M_THROTTLE_THRESHOLD_FL 0xfU
2502 #define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
2503 #define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
2505 #define S_THROTTLE_THRESHOLD_HP 12
2506 #define M_THROTTLE_THRESHOLD_HP 0xfU
2507 #define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
2508 #define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
2510 #define S_THROTTLE_THRESHOLD_LP 0
2511 #define M_THROTTLE_THRESHOLD_LP 0xfffU
2512 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
2513 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
2515 #define A_SGE_INT_ENABLE6 0x112c
2516 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2518 #define S_DBP_FETCH_THRESHOLD_FL 21
2519 #define M_DBP_FETCH_THRESHOLD_FL 0xfU
2520 #define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
2521 #define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
2523 #define S_DBP_FETCH_THRESHOLD_HP 17
2524 #define M_DBP_FETCH_THRESHOLD_HP 0xfU
2525 #define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
2526 #define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
2528 #define S_DBP_FETCH_THRESHOLD_LP 5
2529 #define M_DBP_FETCH_THRESHOLD_LP 0xfffU
2530 #define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
2531 #define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
2533 #define S_DBP_FETCH_THRESHOLD_MODE 4
2534 #define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
2535 #define F_DBP_FETCH_THRESHOLD_MODE V_DBP_FETCH_THRESHOLD_MODE(1U)
2537 #define S_DBP_FETCH_THRESHOLD_EN3 3
2538 #define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
2539 #define F_DBP_FETCH_THRESHOLD_EN3 V_DBP_FETCH_THRESHOLD_EN3(1U)
2541 #define S_DBP_FETCH_THRESHOLD_EN2 2
2542 #define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
2543 #define F_DBP_FETCH_THRESHOLD_EN2 V_DBP_FETCH_THRESHOLD_EN2(1U)
2545 #define S_DBP_FETCH_THRESHOLD_EN1 1
2546 #define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
2547 #define F_DBP_FETCH_THRESHOLD_EN1 V_DBP_FETCH_THRESHOLD_EN1(1U)
2549 #define S_DBP_FETCH_THRESHOLD_EN0 0
2550 #define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
2551 #define F_DBP_FETCH_THRESHOLD_EN0 V_DBP_FETCH_THRESHOLD_EN0(1U)
2553 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2555 #define S_DBP_FETCH_THRESHOLD_IQ1 16
2556 #define M_DBP_FETCH_THRESHOLD_IQ1 0xffffU
2557 #define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
2558 #define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
2560 #define S_DBP_FETCH_THRESHOLD_IQ0 0
2561 #define M_DBP_FETCH_THRESHOLD_IQ0 0xffffU
2562 #define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
2563 #define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
2565 #define A_SGE_DBVFIFO_BADDR 0x1138
2566 #define A_SGE_DBVFIFO_SIZE 0x113c
2568 #define S_DBVFIFO_SIZE 6
2569 #define M_DBVFIFO_SIZE 0xfffU
2570 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2571 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2573 #define S_T6_DBVFIFO_SIZE 0
2574 #define M_T6_DBVFIFO_SIZE 0x1fffU
2575 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2576 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2578 #define A_SGE_DBFIFO_STATUS3 0x1140
2580 #define S_LP_PTRS_EQUAL 21
2581 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2582 #define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U)
2584 #define S_LP_SNAPHOT 20
2585 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2586 #define F_LP_SNAPHOT V_LP_SNAPHOT(1U)
2588 #define S_FL_INT_THRESH_LOW 16
2589 #define M_FL_INT_THRESH_LOW 0xfU
2590 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2591 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2593 #define S_HP_INT_THRESH_LOW 12
2594 #define M_HP_INT_THRESH_LOW 0xfU
2595 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2596 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2598 #define S_LP_INT_THRESH_LOW 0
2599 #define M_LP_INT_THRESH_LOW 0xfffU
2600 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2601 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2603 #define A_SGE_CHANGESET 0x1144
2604 #define A_SGE_PC_RSP_ERROR 0x1148
2605 #define A_SGE_TBUF_CONTROL 0x114c
2607 #define S_DBPTBUFRSV1 9
2608 #define M_DBPTBUFRSV1 0x1ffU
2609 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2610 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2612 #define S_DBPTBUFRSV0 0
2613 #define M_DBPTBUFRSV0 0x1ffU
2614 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2615 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2617 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2618 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2619 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2620 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2621 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2622 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2623 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2624 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2625 #define A_SGE_CTXT_CMD 0x11fc
2628 #define V_BUSY(x) ((x) << S_BUSY)
2629 #define F_BUSY V_BUSY(1U)
2632 #define M_CTXTOP 0x3U
2633 #define V_CTXTOP(x) ((x) << S_CTXTOP)
2634 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
2636 #define S_CTXTTYPE 24
2637 #define M_CTXTTYPE 0x3U
2638 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
2639 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
2642 #define M_CTXTQID 0x1ffffU
2643 #define V_CTXTQID(x) ((x) << S_CTXTQID)
2644 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
2646 #define A_SGE_CTXT_DATA0 0x1200
2647 #define A_SGE_CTXT_DATA1 0x1204
2648 #define A_SGE_CTXT_DATA2 0x1208
2649 #define A_SGE_CTXT_DATA3 0x120c
2650 #define A_SGE_CTXT_DATA4 0x1210
2651 #define A_SGE_CTXT_DATA5 0x1214
2652 #define A_SGE_CTXT_DATA6 0x1218
2653 #define A_SGE_CTXT_DATA7 0x121c
2654 #define A_SGE_CTXT_MASK0 0x1220
2655 #define A_SGE_CTXT_MASK1 0x1224
2656 #define A_SGE_CTXT_MASK2 0x1228
2657 #define A_SGE_CTXT_MASK3 0x122c
2658 #define A_SGE_CTXT_MASK4 0x1230
2659 #define A_SGE_CTXT_MASK5 0x1234
2660 #define A_SGE_CTXT_MASK6 0x1238
2661 #define A_SGE_CTXT_MASK7 0x123c
2662 #define A_SGE_QBASE_MAP0 0x1240
2664 #define S_EGRESS0_SIZE 24
2665 #define M_EGRESS0_SIZE 0x1fU
2666 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
2667 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
2669 #define S_EGRESS1_SIZE 16
2670 #define M_EGRESS1_SIZE 0x1fU
2671 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
2672 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
2674 #define S_INGRESS0_SIZE 8
2675 #define M_INGRESS0_SIZE 0x1fU
2676 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
2677 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
2679 #define A_SGE_QBASE_MAP1 0x1244
2681 #define S_EGRESS0_BASE 0
2682 #define M_EGRESS0_BASE 0x1ffffU
2683 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
2684 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
2686 #define A_SGE_QBASE_MAP2 0x1248
2688 #define S_EGRESS1_BASE 0
2689 #define M_EGRESS1_BASE 0x1ffffU
2690 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
2691 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
2693 #define A_SGE_QBASE_MAP3 0x124c
2695 #define S_INGRESS1_BASE_256VF 16
2696 #define M_INGRESS1_BASE_256VF 0xffffU
2697 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
2698 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
2700 #define S_INGRESS0_BASE 0
2701 #define M_INGRESS0_BASE 0xffffU
2702 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
2703 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
2705 #define A_SGE_QBASE_INDEX 0x1250
2708 #define M_QIDX 0x1ffU
2709 #define V_QIDX(x) ((x) << S_QIDX)
2710 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
2712 #define A_SGE_CONM_CTRL2 0x1254
2714 #define S_FLMTHRESHPACK 8
2715 #define M_FLMTHRESHPACK 0x7fU
2716 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
2717 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
2719 #define S_FLMTHRESH 0
2720 #define M_FLMTHRESH 0x7fU
2721 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
2722 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
2724 #define A_SGE_DEBUG_CONM 0x1258
2726 #define S_MPS_CH_CNG 16
2727 #define M_MPS_CH_CNG 0xffffU
2728 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
2729 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
2731 #define S_TP_CH_CNG 14
2732 #define M_TP_CH_CNG 0x3U
2733 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
2734 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
2736 #define S_ST_CONG 12
2737 #define M_ST_CONG 0x3U
2738 #define V_ST_CONG(x) ((x) << S_ST_CONG)
2739 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
2741 #define S_LAST_XOFF 10
2742 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
2743 #define F_LAST_XOFF V_LAST_XOFF(1U)
2745 #define S_LAST_QID 0
2746 #define M_LAST_QID 0x3ffU
2747 #define V_LAST_QID(x) ((x) << S_LAST_QID)
2748 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
2750 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
2752 #define S_IMSG_GTS_SEL 18
2753 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
2754 #define F_IMSG_GTS_SEL V_IMSG_GTS_SEL(1U)
2756 #define S_MGT_SEL 17
2757 #define V_MGT_SEL(x) ((x) << S_MGT_SEL)
2758 #define F_MGT_SEL V_MGT_SEL(1U)
2760 #define S_DB_GTS_QID 0
2761 #define M_DB_GTS_QID 0x1ffffU
2762 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
2763 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
2765 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
2766 #define A_SGE_DBG_QUEUE_STAT0 0x1264
2767 #define A_SGE_DBG_QUEUE_STAT1 0x1268
2768 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
2769 #define A_SGE_DBG_DB_PKT_CNT 0x1270
2770 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
2771 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2774 #define M_CIM_WM 0x3U
2775 #define V_CIM_WM(x) ((x) << S_CIM_WM)
2776 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
2778 #define S_DEBUG_UP_SOP_CNT 20
2779 #define M_DEBUG_UP_SOP_CNT 0xfU
2780 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
2781 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
2783 #define S_DEBUG_UP_EOP_CNT 16
2784 #define M_DEBUG_UP_EOP_CNT 0xfU
2785 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
2786 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
2788 #define S_DEBUG_CIM_SOP1_CNT 12
2789 #define M_DEBUG_CIM_SOP1_CNT 0xfU
2790 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
2791 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
2793 #define S_DEBUG_CIM_EOP1_CNT 8
2794 #define M_DEBUG_CIM_EOP1_CNT 0xfU
2795 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
2796 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
2798 #define S_DEBUG_CIM_SOP0_CNT 4
2799 #define M_DEBUG_CIM_SOP0_CNT 0xfU
2800 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
2801 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
2803 #define S_DEBUG_CIM_EOP0_CNT 0
2804 #define M_DEBUG_CIM_EOP0_CNT 0xfU
2805 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
2806 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
2808 #define S_DEBUG_BAR2_SOP_CNT 28
2809 #define M_DEBUG_BAR2_SOP_CNT 0xfU
2810 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
2811 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
2813 #define S_DEBUG_BAR2_EOP_CNT 24
2814 #define M_DEBUG_BAR2_EOP_CNT 0xfU
2815 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
2816 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
2818 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2820 #define S_DEBUG_T_RX_SOP1_CNT 28
2821 #define M_DEBUG_T_RX_SOP1_CNT 0xfU
2822 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
2823 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
2825 #define S_DEBUG_T_RX_EOP1_CNT 24
2826 #define M_DEBUG_T_RX_EOP1_CNT 0xfU
2827 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
2828 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
2830 #define S_DEBUG_T_RX_SOP0_CNT 20
2831 #define M_DEBUG_T_RX_SOP0_CNT 0xfU
2832 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
2833 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
2835 #define S_DEBUG_T_RX_EOP0_CNT 16
2836 #define M_DEBUG_T_RX_EOP0_CNT 0xfU
2837 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
2838 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
2840 #define S_DEBUG_U_RX_SOP1_CNT 12
2841 #define M_DEBUG_U_RX_SOP1_CNT 0xfU
2842 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
2843 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
2845 #define S_DEBUG_U_RX_EOP1_CNT 8
2846 #define M_DEBUG_U_RX_EOP1_CNT 0xfU
2847 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
2848 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
2850 #define S_DEBUG_U_RX_SOP0_CNT 4
2851 #define M_DEBUG_U_RX_SOP0_CNT 0xfU
2852 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
2853 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
2855 #define S_DEBUG_U_RX_EOP0_CNT 0
2856 #define M_DEBUG_U_RX_EOP0_CNT 0xfU
2857 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
2858 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
2860 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2862 #define S_DEBUG_UD_RX_SOP3_CNT 28
2863 #define M_DEBUG_UD_RX_SOP3_CNT 0xfU
2864 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
2865 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
2867 #define S_DEBUG_UD_RX_EOP3_CNT 24
2868 #define M_DEBUG_UD_RX_EOP3_CNT 0xfU
2869 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
2870 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
2872 #define S_DEBUG_UD_RX_SOP2_CNT 20
2873 #define M_DEBUG_UD_RX_SOP2_CNT 0xfU
2874 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
2875 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
2877 #define S_DEBUG_UD_RX_EOP2_CNT 16
2878 #define M_DEBUG_UD_RX_EOP2_CNT 0xfU
2879 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
2880 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
2882 #define S_DEBUG_UD_RX_SOP1_CNT 12
2883 #define M_DEBUG_UD_RX_SOP1_CNT 0xfU
2884 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
2885 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
2887 #define S_DEBUG_UD_RX_EOP1_CNT 8
2888 #define M_DEBUG_UD_RX_EOP1_CNT 0xfU
2889 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
2890 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
2892 #define S_DEBUG_UD_RX_SOP0_CNT 4
2893 #define M_DEBUG_UD_RX_SOP0_CNT 0xfU
2894 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
2895 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
2897 #define S_DEBUG_UD_RX_EOP0_CNT 0
2898 #define M_DEBUG_UD_RX_EOP0_CNT 0xfU
2899 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
2900 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
2902 #define S_DBG_TBUF_USED1 9
2903 #define M_DBG_TBUF_USED1 0x1ffU
2904 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
2905 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
2907 #define S_DBG_TBUF_USED0 0
2908 #define M_DBG_TBUF_USED0 0x1ffU
2909 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
2910 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
2912 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2914 #define S_DEBUG_U_TX_SOP3_CNT 28
2915 #define M_DEBUG_U_TX_SOP3_CNT 0xfU
2916 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
2917 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
2919 #define S_DEBUG_U_TX_EOP3_CNT 24
2920 #define M_DEBUG_U_TX_EOP3_CNT 0xfU
2921 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
2922 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
2924 #define S_DEBUG_U_TX_SOP2_CNT 20
2925 #define M_DEBUG_U_TX_SOP2_CNT 0xfU
2926 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
2927 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
2929 #define S_DEBUG_U_TX_EOP2_CNT 16
2930 #define M_DEBUG_U_TX_EOP2_CNT 0xfU
2931 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
2932 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
2934 #define S_DEBUG_U_TX_SOP1_CNT 12
2935 #define M_DEBUG_U_TX_SOP1_CNT 0xfU
2936 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
2937 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
2939 #define S_DEBUG_U_TX_EOP1_CNT 8
2940 #define M_DEBUG_U_TX_EOP1_CNT 0xfU
2941 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
2942 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
2944 #define S_DEBUG_U_TX_SOP0_CNT 4
2945 #define M_DEBUG_U_TX_SOP0_CNT 0xfU
2946 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
2947 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
2949 #define S_DEBUG_U_TX_EOP0_CNT 0
2950 #define M_DEBUG_U_TX_EOP0_CNT 0xfU
2951 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
2952 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
2954 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
2956 #define S_WR_DEQ_CNT 12
2957 #define M_WR_DEQ_CNT 0xfU
2958 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
2959 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
2961 #define S_WR_ENQ_CNT 8
2962 #define M_WR_ENQ_CNT 0xfU
2963 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
2964 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
2966 #define S_FL_DEQ_CNT 4
2967 #define M_FL_DEQ_CNT 0xfU
2968 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
2969 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
2971 #define S_FL_ENQ_CNT 0
2972 #define M_FL_ENQ_CNT 0xfU
2973 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
2974 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
2976 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2978 #define S_DEBUG_PC_RSP_SOP1_CNT 28
2979 #define M_DEBUG_PC_RSP_SOP1_CNT 0xfU
2980 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
2981 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
2983 #define S_DEBUG_PC_RSP_EOP1_CNT 24
2984 #define M_DEBUG_PC_RSP_EOP1_CNT 0xfU
2985 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
2986 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
2988 #define S_DEBUG_PC_RSP_SOP0_CNT 20
2989 #define M_DEBUG_PC_RSP_SOP0_CNT 0xfU
2990 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
2991 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
2993 #define S_DEBUG_PC_RSP_EOP0_CNT 16
2994 #define M_DEBUG_PC_RSP_EOP0_CNT 0xfU
2995 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
2996 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
2998 #define S_DEBUG_PC_REQ_SOP1_CNT 12
2999 #define M_DEBUG_PC_REQ_SOP1_CNT 0xfU
3000 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
3001 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
3003 #define S_DEBUG_PC_REQ_EOP1_CNT 8
3004 #define M_DEBUG_PC_REQ_EOP1_CNT 0xfU
3005 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
3006 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
3008 #define S_DEBUG_PC_REQ_SOP0_CNT 4
3009 #define M_DEBUG_PC_REQ_SOP0_CNT 0xfU
3010 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
3011 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
3013 #define S_DEBUG_PC_REQ_EOP0_CNT 0
3014 #define M_DEBUG_PC_REQ_EOP0_CNT 0xfU
3015 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
3016 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
3018 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
3020 #define S_DEBUG_PD_RDREQ_SOP3_CNT 28
3021 #define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU
3022 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
3023 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
3025 #define S_DEBUG_PD_RDREQ_EOP3_CNT 24
3026 #define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU
3027 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
3028 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
3030 #define S_DEBUG_PD_RDREQ_SOP2_CNT 20
3031 #define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU
3032 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
3033 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
3035 #define S_DEBUG_PD_RDREQ_EOP2_CNT 16
3036 #define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU
3037 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
3038 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
3040 #define S_DEBUG_PD_RDREQ_SOP1_CNT 12
3041 #define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU
3042 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
3043 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
3045 #define S_DEBUG_PD_RDREQ_EOP1_CNT 8
3046 #define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU
3047 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
3048 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
3050 #define S_DEBUG_PD_RDREQ_SOP0_CNT 4
3051 #define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU
3052 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
3053 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
3055 #define S_DEBUG_PD_RDREQ_EOP0_CNT 0
3056 #define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU
3057 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
3058 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
3060 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
3062 #define S_DEBUG_PD_RDRSP_SOP3_CNT 28
3063 #define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU
3064 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
3065 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
3067 #define S_DEBUG_PD_RDRSP_EOP3_CNT 24
3068 #define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU
3069 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
3070 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
3072 #define S_DEBUG_PD_RDRSP_SOP2_CNT 20
3073 #define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU
3074 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
3075 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
3077 #define S_DEBUG_PD_RDRSP_EOP2_CNT 16
3078 #define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU
3079 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
3080 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
3082 #define S_DEBUG_PD_RDRSP_SOP1_CNT 12
3083 #define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU
3084 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
3085 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
3087 #define S_DEBUG_PD_RDRSP_EOP1_CNT 8
3088 #define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU
3089 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
3090 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
3092 #define S_DEBUG_PD_RDRSP_SOP0_CNT 4
3093 #define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU
3094 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
3095 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
3097 #define S_DEBUG_PD_RDRSP_EOP0_CNT 0
3098 #define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU
3099 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
3100 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
3102 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
3104 #define S_DEBUG_PD_WRREQ_SOP3_CNT 28
3105 #define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU
3106 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
3107 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
3109 #define S_DEBUG_PD_WRREQ_EOP3_CNT 24
3110 #define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU
3111 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
3112 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
3114 #define S_DEBUG_PD_WRREQ_SOP2_CNT 20
3115 #define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU
3116 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
3117 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
3119 #define S_DEBUG_PD_WRREQ_EOP2_CNT 16
3120 #define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU
3121 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
3122 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
3124 #define S_DEBUG_PD_WRREQ_SOP1_CNT 12
3125 #define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU
3126 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
3127 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
3129 #define S_DEBUG_PD_WRREQ_EOP1_CNT 8
3130 #define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU
3131 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
3132 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
3134 #define S_DEBUG_PD_WRREQ_SOP0_CNT 4
3135 #define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU
3136 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
3137 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
3139 #define S_DEBUG_PD_WRREQ_EOP0_CNT 0
3140 #define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU
3141 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
3142 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
3144 #define S_DEBUG_PC_RSP_SOP_CNT 28
3145 #define M_DEBUG_PC_RSP_SOP_CNT 0xfU
3146 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
3147 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
3149 #define S_DEBUG_PC_RSP_EOP_CNT 24
3150 #define M_DEBUG_PC_RSP_EOP_CNT 0xfU
3151 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
3152 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
3154 #define S_DEBUG_PC_REQ_SOP_CNT 20
3155 #define M_DEBUG_PC_REQ_SOP_CNT 0xfU
3156 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
3157 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
3159 #define S_DEBUG_PC_REQ_EOP_CNT 16
3160 #define M_DEBUG_PC_REQ_EOP_CNT 0xfU
3161 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
3162 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
3164 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
3166 #define S_GLOBALENABLE_OFF 29
3167 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
3168 #define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U)
3170 #define S_DEBUG_CIM2SGE_RXAFULL_D 27
3171 #define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U
3172 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
3173 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
3175 #define S_DEBUG_CPLSW_CIM_TXAFULL_D 25
3176 #define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U
3177 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
3178 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
3180 #define S_DEBUG_UP_FULL 24
3181 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
3182 #define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U)
3184 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23
3185 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
3186 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
3188 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22
3189 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
3190 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
3192 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21
3193 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
3194 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
3196 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20
3197 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
3198 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
3200 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19
3201 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
3202 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
3204 #define S_DEBUG_M_REQVLD 18
3205 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
3206 #define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U)
3208 #define S_DEBUG_M_REQRDY 17
3209 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
3210 #define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U)
3212 #define S_DEBUG_M_RSPVLD 16
3213 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
3214 #define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U)
3216 #define S_DEBUG_PD_WRREQ_INT3_CNT 12
3217 #define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU
3218 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
3219 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
3221 #define S_DEBUG_PD_WRREQ_INT2_CNT 8
3222 #define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU
3223 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
3224 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
3226 #define S_DEBUG_PD_WRREQ_INT1_CNT 4
3227 #define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU
3228 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
3229 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
3231 #define S_DEBUG_PD_WRREQ_INT0_CNT 0
3232 #define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU
3233 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
3234 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
3236 #define S_DEBUG_PL_BAR2_REQVLD 31
3237 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
3238 #define F_DEBUG_PL_BAR2_REQVLD V_DEBUG_PL_BAR2_REQVLD(1U)
3240 #define S_DEBUG_PL_BAR2_REQFULL 30
3241 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
3242 #define F_DEBUG_PL_BAR2_REQFULL V_DEBUG_PL_BAR2_REQFULL(1U)
3244 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
3246 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28
3247 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU
3248 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3249 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3251 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24
3252 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU
3253 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3254 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3256 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20
3257 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU
3258 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3259 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3261 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16
3262 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU
3263 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3264 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3266 #define S_DEBUG_CPLSW_CIM_SOP1_CNT 12
3267 #define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU
3268 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3269 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3271 #define S_DEBUG_CPLSW_CIM_EOP1_CNT 8
3272 #define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU
3273 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3274 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3276 #define S_DEBUG_CPLSW_CIM_SOP0_CNT 4
3277 #define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU
3278 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3279 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3281 #define S_DEBUG_CPLSW_CIM_EOP0_CNT 0
3282 #define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU
3283 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3284 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3286 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3288 #define S_DEBUG_T_RXAFULL_D 30
3289 #define M_DEBUG_T_RXAFULL_D 0x3U
3290 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3291 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3293 #define S_DEBUG_PD_RDRSPAFULL_D 26
3294 #define M_DEBUG_PD_RDRSPAFULL_D 0xfU
3295 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3296 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3298 #define S_DEBUG_PD_RDREQAFULL_D 22
3299 #define M_DEBUG_PD_RDREQAFULL_D 0xfU
3300 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3301 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3303 #define S_DEBUG_PD_WRREQAFULL_D 18
3304 #define M_DEBUG_PD_WRREQAFULL_D 0xfU
3305 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3306 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3308 #define S_DEBUG_PC_RSPAFULL_D 15
3309 #define M_DEBUG_PC_RSPAFULL_D 0x7U
3310 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3311 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3313 #define S_DEBUG_PC_REQAFULL_D 12
3314 #define M_DEBUG_PC_REQAFULL_D 0x7U
3315 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3316 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3318 #define S_DEBUG_U_TXAFULL_D 8
3319 #define M_DEBUG_U_TXAFULL_D 0xfU
3320 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3321 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3323 #define S_DEBUG_UD_RXAFULL_D 4
3324 #define M_DEBUG_UD_RXAFULL_D 0xfU
3325 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3326 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3328 #define S_DEBUG_U_RXAFULL_D 2
3329 #define M_DEBUG_U_RXAFULL_D 0x3U
3330 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3331 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3333 #define S_DEBUG_CIM_AFULL_D 0
3334 #define M_DEBUG_CIM_AFULL_D 0x3U
3335 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3336 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3338 #define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING 28
3339 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING 0xfU
3340 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3341 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3343 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY 27
3344 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3345 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3347 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS 26
3348 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3349 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3351 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL 25
3352 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3353 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3355 #define S_DEBUG_IDMA1_IDMA2IMSG_FULL 24
3356 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3357 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3359 #define S_DEBUG_IDMA1_IDMA2IMSG_EOP 23
3360 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3361 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3363 #define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY 22
3364 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3365 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3367 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY 21
3368 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3369 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3371 #define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING 17
3372 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING 0xfU
3373 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3374 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3376 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY 16
3377 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3378 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3380 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS 15
3381 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3382 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3384 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL 14
3385 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3386 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3388 #define S_DEBUG_IDMA0_IDMA2IMSG_FULL 13
3389 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3390 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3392 #define S_DEBUG_IDMA0_IDMA2IMSG_EOP 12
3393 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3394 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3396 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY 11
3397 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3398 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3400 #define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY 10
3401 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3402 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3404 #define S_T6_DEBUG_T_RXAFULL_D 8
3405 #define M_T6_DEBUG_T_RXAFULL_D 0x3U
3406 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3407 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3409 #define S_T6_DEBUG_PD_WRREQAFULL_D 6
3410 #define M_T6_DEBUG_PD_WRREQAFULL_D 0x3U
3411 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3412 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3414 #define S_T6_DEBUG_PC_RSPAFULL_D 5
3415 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3416 #define F_T6_DEBUG_PC_RSPAFULL_D V_T6_DEBUG_PC_RSPAFULL_D(1U)
3418 #define S_T6_DEBUG_PC_REQAFULL_D 4
3419 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3420 #define F_T6_DEBUG_PC_REQAFULL_D V_T6_DEBUG_PC_REQAFULL_D(1U)
3422 #define S_T6_DEBUG_CIM_AFULL_D 0
3423 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3424 #define F_T6_DEBUG_CIM_AFULL_D V_T6_DEBUG_CIM_AFULL_D(1U)
3426 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3428 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24
3429 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3430 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3432 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23
3433 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3434 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3436 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22
3437 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3438 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3440 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21
3441 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3442 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3444 #define S_DEBUG_ST_FLM_IDMA1_CACHE 19
3445 #define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U
3446 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3447 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3449 #define S_DEBUG_ST_FLM_IDMA1_CTXT 16
3450 #define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U
3451 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3452 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3454 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8
3455 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3456 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3458 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7
3459 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3460 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3462 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6
3463 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3464 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3466 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5
3467 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3468 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3470 #define S_DEBUG_ST_FLM_IDMA0_CACHE 3
3471 #define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U
3472 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3473 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3475 #define S_DEBUG_ST_FLM_IDMA0_CTXT 0
3476 #define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U
3477 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3478 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3480 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3482 #define S_DEBUG_CPLSW_SOP1_CNT 28
3483 #define M_DEBUG_CPLSW_SOP1_CNT 0xfU
3484 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3485 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3487 #define S_DEBUG_CPLSW_EOP1_CNT 24
3488 #define M_DEBUG_CPLSW_EOP1_CNT 0xfU
3489 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3490 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3492 #define S_DEBUG_CPLSW_SOP0_CNT 20
3493 #define M_DEBUG_CPLSW_SOP0_CNT 0xfU
3494 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3495 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3497 #define S_DEBUG_CPLSW_EOP0_CNT 16
3498 #define M_DEBUG_CPLSW_EOP0_CNT 0xfU
3499 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3500 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3502 #define S_DEBUG_PC_RSP_SOP2_CNT 12
3503 #define M_DEBUG_PC_RSP_SOP2_CNT 0xfU
3504 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3505 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3507 #define S_DEBUG_PC_RSP_EOP2_CNT 8
3508 #define M_DEBUG_PC_RSP_EOP2_CNT 0xfU
3509 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3510 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3512 #define S_DEBUG_PC_REQ_SOP2_CNT 4
3513 #define M_DEBUG_PC_REQ_SOP2_CNT 0xfU
3514 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3515 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3517 #define S_DEBUG_PC_REQ_EOP2_CNT 0
3518 #define M_DEBUG_PC_REQ_EOP2_CNT 0xfU
3519 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3520 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3522 #define S_DEBUG_IDMA1_ISHIFT_TX_SIZE 8
3523 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE 0x7fU
3524 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3525 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3527 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE 0
3528 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE 0x7fU
3529 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3530 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3532 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3533 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3534 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3535 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3537 #define S_DEBUG_ST_IDMA1_FLM_REQ 29
3538 #define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U
3539 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3540 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3542 #define S_DEBUG_ST_IDMA0_FLM_REQ 26
3543 #define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U
3544 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3545 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3547 #define S_DEBUG_ST_IMSG_CTXT 23
3548 #define M_DEBUG_ST_IMSG_CTXT 0x7U
3549 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3550 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3552 #define S_DEBUG_ST_IMSG 18
3553 #define M_DEBUG_ST_IMSG 0x1fU
3554 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3555 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3557 #define S_DEBUG_ST_IDMA1_IALN 16
3558 #define M_DEBUG_ST_IDMA1_IALN 0x3U
3559 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3560 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3562 #define S_DEBUG_ST_IDMA1_IDMA_SM 9
3563 #define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU
3564 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3565 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3567 #define S_DEBUG_ST_IDMA0_IALN 7
3568 #define M_DEBUG_ST_IDMA0_IALN 0x3U
3569 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
3570 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
3572 #define S_DEBUG_ST_IDMA0_IDMA_SM 0
3573 #define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU
3574 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
3575 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
3577 #define S_DEBUG_ST_IDMA1_IDMA2IMSG 15
3578 #define V_DEBUG_ST_IDMA1_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA1_IDMA2IMSG)
3579 #define F_DEBUG_ST_IDMA1_IDMA2IMSG V_DEBUG_ST_IDMA1_IDMA2IMSG(1U)
3581 #define S_DEBUG_ST_IDMA0_IDMA2IMSG 6
3582 #define V_DEBUG_ST_IDMA0_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA0_IDMA2IMSG)
3583 #define F_DEBUG_ST_IDMA0_IDMA2IMSG V_DEBUG_ST_IDMA0_IDMA2IMSG(1U)
3585 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
3587 #define S_DEBUG_ITP_EMPTY 12
3588 #define M_DEBUG_ITP_EMPTY 0x3fU
3589 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
3590 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
3592 #define S_DEBUG_ITP_EXPIRED 6
3593 #define M_DEBUG_ITP_EXPIRED 0x3fU
3594 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
3595 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
3597 #define S_DEBUG_ITP_PAUSE 5
3598 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
3599 #define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U)
3601 #define S_DEBUG_ITP_DEL_DONE 4
3602 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
3603 #define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U)
3605 #define S_DEBUG_ITP_ADD_DONE 3
3606 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
3607 #define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U)
3609 #define S_DEBUG_ITP_EVR_STATE 0
3610 #define M_DEBUG_ITP_EVR_STATE 0x7U
3611 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
3612 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
3614 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
3616 #define S_DEBUG_ST_DBP_THREAD2_CIMFL 25
3617 #define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU
3618 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
3619 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
3621 #define S_DEBUG_ST_DBP_THREAD2_MAIN 20
3622 #define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU
3623 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
3624 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
3626 #define S_DEBUG_ST_DBP_THREAD1_CIMFL 15
3627 #define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU
3628 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
3629 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
3631 #define S_DEBUG_ST_DBP_THREAD1_MAIN 10
3632 #define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU
3633 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
3634 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
3636 #define S_DEBUG_ST_DBP_THREAD0_CIMFL 5
3637 #define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU
3638 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
3639 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
3641 #define S_DEBUG_ST_DBP_THREAD0_MAIN 0
3642 #define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU
3643 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
3644 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
3646 #define S_T6_DEBUG_ST_DBP_UPCP_MAIN 14
3647 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN 0x7U
3648 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
3649 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
3651 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
3653 #define S_DEBUG_ST_DBP_UPCP_MAIN 14
3654 #define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU
3655 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
3656 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
3658 #define S_DEBUG_ST_DBP_DBFIFO_MAIN 13
3659 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
3660 #define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
3662 #define S_DEBUG_ST_DBP_CTXT 10
3663 #define M_DEBUG_ST_DBP_CTXT 0x7U
3664 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
3665 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
3667 #define S_DEBUG_ST_DBP_THREAD3_CIMFL 5
3668 #define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU
3669 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
3670 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
3672 #define S_DEBUG_ST_DBP_THREAD3_MAIN 0
3673 #define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU
3674 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
3675 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
3677 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
3679 #define S_DEBUG_ST_EDMA3_ALIGN_SUB 29
3680 #define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U
3681 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
3682 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
3684 #define S_DEBUG_ST_EDMA3_ALIGN 27
3685 #define M_DEBUG_ST_EDMA3_ALIGN 0x3U
3686 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
3687 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
3689 #define S_DEBUG_ST_EDMA3_REQ 24
3690 #define M_DEBUG_ST_EDMA3_REQ 0x7U
3691 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
3692 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
3694 #define S_DEBUG_ST_EDMA2_ALIGN_SUB 21
3695 #define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U
3696 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
3697 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
3699 #define S_DEBUG_ST_EDMA2_ALIGN 19
3700 #define M_DEBUG_ST_EDMA2_ALIGN 0x3U
3701 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
3702 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
3704 #define S_DEBUG_ST_EDMA2_REQ 16
3705 #define M_DEBUG_ST_EDMA2_REQ 0x7U
3706 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
3707 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
3709 #define S_DEBUG_ST_EDMA1_ALIGN_SUB 13
3710 #define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U
3711 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
3712 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
3714 #define S_DEBUG_ST_EDMA1_ALIGN 11
3715 #define M_DEBUG_ST_EDMA1_ALIGN 0x3U
3716 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
3717 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
3719 #define S_DEBUG_ST_EDMA1_REQ 8
3720 #define M_DEBUG_ST_EDMA1_REQ 0x7U
3721 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
3722 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
3724 #define S_DEBUG_ST_EDMA0_ALIGN_SUB 5
3725 #define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U
3726 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
3727 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
3729 #define S_DEBUG_ST_EDMA0_ALIGN 3
3730 #define M_DEBUG_ST_EDMA0_ALIGN 0x3U
3731 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
3732 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
3734 #define S_DEBUG_ST_EDMA0_REQ 0
3735 #define M_DEBUG_ST_EDMA0_REQ 0x7U
3736 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
3737 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
3739 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
3741 #define S_DEBUG_ST_FLM_DBPTR 30
3742 #define M_DEBUG_ST_FLM_DBPTR 0x3U
3743 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
3744 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
3746 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23
3747 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU
3748 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
3749 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
3751 #define S_DEBUG_FLM_CACHE_AGENT 20
3752 #define M_DEBUG_FLM_CACHE_AGENT 0x7U
3753 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
3754 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
3756 #define S_DEBUG_ST_FLM_CACHE 16
3757 #define M_DEBUG_ST_FLM_CACHE 0xfU
3758 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
3759 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
3761 #define S_DEBUG_FLM_DBPTR_CIDX_STALL 12
3762 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
3763 #define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
3765 #define S_DEBUG_FLM_DBPTR_QID 0
3766 #define M_DEBUG_FLM_DBPTR_QID 0xfffU
3767 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
3768 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
3770 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
3772 #define S_THREAD_ST_MAIN 25
3773 #define M_THREAD_ST_MAIN 0x3fU
3774 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
3775 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
3777 #define S_THREAD_ST_CIMFL 21
3778 #define M_THREAD_ST_CIMFL 0xfU
3779 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
3780 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
3782 #define S_THREAD_CMDOP 17
3783 #define M_THREAD_CMDOP 0xfU
3784 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
3785 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
3787 #define S_THREAD_QID 0
3788 #define M_THREAD_QID 0x1ffffU
3789 #define V_THREAD_QID(x) ((x) << S_THREAD_QID)
3790 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
3792 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
3794 #define S_DEBUG_DBP_THREAD0_QID 0
3795 #define M_DEBUG_DBP_THREAD0_QID 0x1ffffU
3796 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
3797 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
3799 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
3801 #define S_DEBUG_DBP_THREAD1_QID 0
3802 #define M_DEBUG_DBP_THREAD1_QID 0x1ffffU
3803 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
3804 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
3806 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
3808 #define S_DEBUG_DBP_THREAD2_QID 0
3809 #define M_DEBUG_DBP_THREAD2_QID 0x1ffffU
3810 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
3811 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
3813 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
3815 #define S_DEBUG_DBP_THREAD3_QID 0
3816 #define M_DEBUG_DBP_THREAD3_QID 0x1ffffU
3817 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
3818 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
3820 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
3822 #define S_DEBUG_IMSG_CPL 16
3823 #define M_DEBUG_IMSG_CPL 0xffU
3824 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
3825 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
3827 #define S_DEBUG_IMSG_QID 0
3828 #define M_DEBUG_IMSG_QID 0xffffU
3829 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
3830 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
3832 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
3834 #define S_DEBUG_IDMA1_QID 16
3835 #define M_DEBUG_IDMA1_QID 0xffffU
3836 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
3837 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
3839 #define S_DEBUG_IDMA0_QID 0
3840 #define M_DEBUG_IDMA0_QID 0xffffU
3841 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
3842 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
3844 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
3846 #define S_DEBUG_IDMA1_FLM_REQ_QID 16
3847 #define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU
3848 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
3849 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
3851 #define S_DEBUG_IDMA0_FLM_REQ_QID 0
3852 #define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU
3853 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
3854 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
3856 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
3857 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
3858 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
3859 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
3861 #define S_EGRESS_LOG2SIZE 27
3862 #define M_EGRESS_LOG2SIZE 0x1fU
3863 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
3864 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
3866 #define S_EGRESS_BASE 10
3867 #define M_EGRESS_BASE 0x1ffffU
3868 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
3869 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
3871 #define S_INGRESS2_LOG2SIZE 5
3872 #define M_INGRESS2_LOG2SIZE 0x1fU
3873 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
3874 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
3876 #define S_INGRESS1_LOG2SIZE 0
3877 #define M_INGRESS1_LOG2SIZE 0x1fU
3878 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
3879 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
3881 #define S_EGRESS_SIZE 27
3882 #define M_EGRESS_SIZE 0x1fU
3883 #define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
3884 #define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
3886 #define S_INGRESS2_SIZE 5
3887 #define M_INGRESS2_SIZE 0x1fU
3888 #define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
3889 #define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
3891 #define S_INGRESS1_SIZE 0
3892 #define M_INGRESS1_SIZE 0x1fU
3893 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
3894 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
3896 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
3898 #define S_PFIQSPERPAGE 28
3899 #define M_PFIQSPERPAGE 0xfU
3900 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
3901 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
3903 #define S_PFEQSPERPAGE 24
3904 #define M_PFEQSPERPAGE 0xfU
3905 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
3906 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
3908 #define S_PFWCQSPERPAGE 20
3909 #define M_PFWCQSPERPAGE 0xfU
3910 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
3911 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
3913 #define S_PFWCOFFEN 19
3914 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
3915 #define F_PFWCOFFEN V_PFWCOFFEN(1U)
3917 #define S_PFMAXWCSIZE 17
3918 #define M_PFMAXWCSIZE 0x3U
3919 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
3920 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
3922 #define S_PFWCOFFSET 0
3923 #define M_PFWCOFFSET 0x1ffffU
3924 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
3925 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
3927 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
3929 #define S_INGRESS2_BASE 16
3930 #define M_INGRESS2_BASE 0xffffU
3931 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
3932 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
3934 #define S_INGRESS1_BASE 0
3935 #define M_INGRESS1_BASE 0xffffU
3936 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
3937 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
3939 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
3941 #define S_VFIQSPERPAGE 28
3942 #define M_VFIQSPERPAGE 0xfU
3943 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
3944 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
3946 #define S_VFEQSPERPAGE 24
3947 #define M_VFEQSPERPAGE 0xfU
3948 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
3949 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
3951 #define S_VFWCQSPERPAGE 20
3952 #define M_VFWCQSPERPAGE 0xfU
3953 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
3954 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
3956 #define S_VFWCOFFEN 19
3957 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
3958 #define F_VFWCOFFEN V_VFWCOFFEN(1U)
3960 #define S_VFMAXWCSIZE 17
3961 #define M_VFMAXWCSIZE 0x3U
3962 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
3963 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
3965 #define S_VFWCOFFSET 0
3966 #define M_VFWCOFFSET 0x1ffffU
3967 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
3968 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
3970 #define A_SGE_LA_RDPTR_0 0x1800
3971 #define A_SGE_LA_RDDATA_0 0x1804
3972 #define A_SGE_LA_WRPTR_0 0x1808
3973 #define A_SGE_LA_RESERVED_0 0x180c
3974 #define A_SGE_LA_RDPTR_1 0x1810
3975 #define A_SGE_LA_RDDATA_1 0x1814
3976 #define A_SGE_LA_WRPTR_1 0x1818
3977 #define A_SGE_LA_RESERVED_1 0x181c
3978 #define A_SGE_LA_RDPTR_2 0x1820
3979 #define A_SGE_LA_RDDATA_2 0x1824
3980 #define A_SGE_LA_WRPTR_2 0x1828
3981 #define A_SGE_LA_RESERVED_2 0x182c
3982 #define A_SGE_LA_RDPTR_3 0x1830
3983 #define A_SGE_LA_RDDATA_3 0x1834
3984 #define A_SGE_LA_WRPTR_3 0x1838
3985 #define A_SGE_LA_RESERVED_3 0x183c
3986 #define A_SGE_LA_RDPTR_4 0x1840
3987 #define A_SGE_LA_RDDATA_4 0x1844
3988 #define A_SGE_LA_WRPTR_4 0x1848
3989 #define A_SGE_LA_RESERVED_4 0x184c
3990 #define A_SGE_LA_RDPTR_5 0x1850
3991 #define A_SGE_LA_RDDATA_5 0x1854
3992 #define A_SGE_LA_WRPTR_5 0x1858
3993 #define A_SGE_LA_RESERVED_5 0x185c
3994 #define A_SGE_LA_RDPTR_6 0x1860
3995 #define A_SGE_LA_RDDATA_6 0x1864
3996 #define A_SGE_LA_WRPTR_6 0x1868
3997 #define A_SGE_LA_RESERVED_6 0x186c
3998 #define A_SGE_LA_RDPTR_7 0x1870
3999 #define A_SGE_LA_RDDATA_7 0x1874
4000 #define A_SGE_LA_WRPTR_7 0x1878
4001 #define A_SGE_LA_RESERVED_7 0x187c
4002 #define A_SGE_LA_RDPTR_8 0x1880
4003 #define A_SGE_LA_RDDATA_8 0x1884
4004 #define A_SGE_LA_WRPTR_8 0x1888
4005 #define A_SGE_LA_RESERVED_8 0x188c
4006 #define A_SGE_LA_RDPTR_9 0x1890
4007 #define A_SGE_LA_RDDATA_9 0x1894
4008 #define A_SGE_LA_WRPTR_9 0x1898
4009 #define A_SGE_LA_RESERVED_9 0x189c
4010 #define A_SGE_LA_RDPTR_10 0x18a0
4011 #define A_SGE_LA_RDDATA_10 0x18a4
4012 #define A_SGE_LA_WRPTR_10 0x18a8
4013 #define A_SGE_LA_RESERVED_10 0x18ac
4014 #define A_SGE_LA_RDPTR_11 0x18b0
4015 #define A_SGE_LA_RDDATA_11 0x18b4
4016 #define A_SGE_LA_WRPTR_11 0x18b8
4017 #define A_SGE_LA_RESERVED_11 0x18bc
4018 #define A_SGE_LA_RDPTR_12 0x18c0
4019 #define A_SGE_LA_RDDATA_12 0x18c4
4020 #define A_SGE_LA_WRPTR_12 0x18c8
4021 #define A_SGE_LA_RESERVED_12 0x18cc
4022 #define A_SGE_LA_RDPTR_13 0x18d0
4023 #define A_SGE_LA_RDDATA_13 0x18d4
4024 #define A_SGE_LA_WRPTR_13 0x18d8
4025 #define A_SGE_LA_RESERVED_13 0x18dc
4026 #define A_SGE_LA_RDPTR_14 0x18e0
4027 #define A_SGE_LA_RDDATA_14 0x18e4
4028 #define A_SGE_LA_WRPTR_14 0x18e8
4029 #define A_SGE_LA_RESERVED_14 0x18ec
4030 #define A_SGE_LA_RDPTR_15 0x18f0
4031 #define A_SGE_LA_RDDATA_15 0x18f4
4032 #define A_SGE_LA_WRPTR_15 0x18f8
4033 #define A_SGE_LA_RESERVED_15 0x18fc
4035 /* registers for module PCIE */
4036 #define PCIE_BASE_ADDR 0x3000
4038 #define A_PCIE_PF_CFG 0x40
4040 #define S_INTXSTAT 16
4041 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
4042 #define F_INTXSTAT V_INTXSTAT(1U)
4044 #define S_AUXPWRPMEN 15
4045 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
4046 #define F_AUXPWRPMEN V_AUXPWRPMEN(1U)
4048 #define S_NOSOFTRESET 14
4049 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
4050 #define F_NOSOFTRESET V_NOSOFTRESET(1U)
4053 #define M_AIVEC 0x3ffU
4054 #define V_AIVEC(x) ((x) << S_AIVEC)
4055 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
4057 #define S_INTXTYPE 2
4058 #define M_INTXTYPE 0x3U
4059 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
4060 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
4063 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
4064 #define F_D3HOTEN V_D3HOTEN(1U)
4066 #define S_CLIDECEN 0
4067 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
4068 #define F_CLIDECEN V_CLIDECEN(1U)
4070 #define A_PCIE_PF_CLI 0x44
4071 #define A_PCIE_PF_GEN_MSG 0x48
4074 #define M_MSGTYPE 0xffU
4075 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
4076 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
4078 #define A_PCIE_PF_EXPROM_OFST 0x4c
4081 #define M_OFFSET 0x3fffU
4082 #define V_OFFSET(x) ((x) << S_OFFSET)
4083 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
4085 #define A_PCIE_INT_ENABLE 0x3000
4087 #define S_NONFATALERR 30
4088 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
4089 #define F_NONFATALERR V_NONFATALERR(1U)
4091 #define S_UNXSPLCPLERR 29
4092 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
4093 #define F_UNXSPLCPLERR V_UNXSPLCPLERR(1U)
4095 #define S_PCIEPINT 28
4096 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
4097 #define F_PCIEPINT V_PCIEPINT(1U)
4099 #define S_PCIESINT 27
4100 #define V_PCIESINT(x) ((x) << S_PCIESINT)
4101 #define F_PCIESINT V_PCIESINT(1U)
4103 #define S_RPLPERR 26
4104 #define V_RPLPERR(x) ((x) << S_RPLPERR)
4105 #define F_RPLPERR V_RPLPERR(1U)
4107 #define S_RXWRPERR 25
4108 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
4109 #define F_RXWRPERR V_RXWRPERR(1U)
4111 #define S_RXCPLPERR 24
4112 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
4113 #define F_RXCPLPERR V_RXCPLPERR(1U)
4115 #define S_PIOTAGPERR 23
4116 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
4117 #define F_PIOTAGPERR V_PIOTAGPERR(1U)
4119 #define S_MATAGPERR 22
4120 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
4121 #define F_MATAGPERR V_MATAGPERR(1U)
4123 #define S_INTXCLRPERR 21
4124 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
4125 #define F_INTXCLRPERR V_INTXCLRPERR(1U)
4127 #define S_FIDPERR 20
4128 #define V_FIDPERR(x) ((x) << S_FIDPERR)
4129 #define F_FIDPERR V_FIDPERR(1U)
4131 #define S_CFGSNPPERR 19
4132 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
4133 #define F_CFGSNPPERR V_CFGSNPPERR(1U)
4135 #define S_HRSPPERR 18
4136 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
4137 #define F_HRSPPERR V_HRSPPERR(1U)
4139 #define S_HREQPERR 17
4140 #define V_HREQPERR(x) ((x) << S_HREQPERR)
4141 #define F_HREQPERR V_HREQPERR(1U)
4143 #define S_HCNTPERR 16
4144 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
4145 #define F_HCNTPERR V_HCNTPERR(1U)
4147 #define S_DRSPPERR 15
4148 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
4149 #define F_DRSPPERR V_DRSPPERR(1U)
4151 #define S_DREQPERR 14
4152 #define V_DREQPERR(x) ((x) << S_DREQPERR)
4153 #define F_DREQPERR V_DREQPERR(1U)
4155 #define S_DCNTPERR 13
4156 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
4157 #define F_DCNTPERR V_DCNTPERR(1U)
4159 #define S_CRSPPERR 12
4160 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
4161 #define F_CRSPPERR V_CRSPPERR(1U)
4163 #define S_CREQPERR 11
4164 #define V_CREQPERR(x) ((x) << S_CREQPERR)
4165 #define F_CREQPERR V_CREQPERR(1U)
4167 #define S_CCNTPERR 10
4168 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
4169 #define F_CCNTPERR V_CCNTPERR(1U)
4171 #define S_TARTAGPERR 9
4172 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
4173 #define F_TARTAGPERR V_TARTAGPERR(1U)
4175 #define S_PIOREQPERR 8
4176 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
4177 #define F_PIOREQPERR V_PIOREQPERR(1U)
4179 #define S_PIOCPLPERR 7
4180 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
4181 #define F_PIOCPLPERR V_PIOCPLPERR(1U)
4183 #define S_MSIXDIPERR 6
4184 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
4185 #define F_MSIXDIPERR V_MSIXDIPERR(1U)
4187 #define S_MSIXDATAPERR 5
4188 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
4189 #define F_MSIXDATAPERR V_MSIXDATAPERR(1U)
4191 #define S_MSIXADDRHPERR 4
4192 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
4193 #define F_MSIXADDRHPERR V_MSIXADDRHPERR(1U)
4195 #define S_MSIXADDRLPERR 3
4196 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
4197 #define F_MSIXADDRLPERR V_MSIXADDRLPERR(1U)
4199 #define S_MSIDATAPERR 2
4200 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
4201 #define F_MSIDATAPERR V_MSIDATAPERR(1U)
4203 #define S_MSIADDRHPERR 1
4204 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
4205 #define F_MSIADDRHPERR V_MSIADDRHPERR(1U)
4207 #define S_MSIADDRLPERR 0
4208 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
4209 #define F_MSIADDRLPERR V_MSIADDRLPERR(1U)
4211 #define S_IPGRPPERR 31
4212 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
4213 #define F_IPGRPPERR V_IPGRPPERR(1U)
4215 #define S_READRSPERR 29
4216 #define V_READRSPERR(x) ((x) << S_READRSPERR)
4217 #define F_READRSPERR V_READRSPERR(1U)
4219 #define S_TRGT1GRPPERR 28
4220 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
4221 #define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U)
4223 #define S_IPSOTPERR 27
4224 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
4225 #define F_IPSOTPERR V_IPSOTPERR(1U)
4227 #define S_IPRETRYPERR 26
4228 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
4229 #define F_IPRETRYPERR V_IPRETRYPERR(1U)
4231 #define S_IPRXDATAGRPPERR 25
4232 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
4233 #define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U)
4235 #define S_IPRXHDRGRPPERR 24
4236 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
4237 #define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U)
4239 #define S_PIOTAGQPERR 23
4240 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
4241 #define F_PIOTAGQPERR V_PIOTAGQPERR(1U)
4243 #define S_MAGRPPERR 22
4244 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
4245 #define F_MAGRPPERR V_MAGRPPERR(1U)
4247 #define S_VFIDPERR 21
4248 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
4249 #define F_VFIDPERR V_VFIDPERR(1U)
4251 #define S_HREQRDPERR 17
4252 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
4253 #define F_HREQRDPERR V_HREQRDPERR(1U)
4255 #define S_HREQWRPERR 16
4256 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
4257 #define F_HREQWRPERR V_HREQWRPERR(1U)
4259 #define S_DREQRDPERR 14
4260 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
4261 #define F_DREQRDPERR V_DREQRDPERR(1U)
4263 #define S_DREQWRPERR 13
4264 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
4265 #define F_DREQWRPERR V_DREQWRPERR(1U)
4267 #define S_CREQRDPERR 11
4268 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
4269 #define F_CREQRDPERR V_CREQRDPERR(1U)
4271 #define S_MSTTAGQPERR 10
4272 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
4273 #define F_MSTTAGQPERR V_MSTTAGQPERR(1U)
4275 #define S_TGTTAGQPERR 9
4276 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
4277 #define F_TGTTAGQPERR V_TGTTAGQPERR(1U)
4279 #define S_PIOREQGRPPERR 8
4280 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
4281 #define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U)
4283 #define S_PIOCPLGRPPERR 7
4284 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
4285 #define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U)
4287 #define S_MSIXSTIPERR 2
4288 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
4289 #define F_MSIXSTIPERR V_MSIXSTIPERR(1U)
4291 #define S_MSTTIMEOUTPERR 1
4292 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
4293 #define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U)
4295 #define S_MSTGRPPERR 0
4296 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
4297 #define F_MSTGRPPERR V_MSTGRPPERR(1U)
4299 #define A_PCIE_INT_CAUSE 0x3004
4300 #define A_PCIE_PERR_ENABLE 0x3008
4301 #define A_PCIE_PERR_INJECT 0x300c
4304 #define V_IDE(x) ((x) << S_IDE)
4305 #define F_IDE V_IDE(1U)
4307 #define S_MEMSEL_PCIE 1
4308 #define M_MEMSEL_PCIE 0x1fU
4309 #define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE)
4310 #define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE)
4312 #define A_PCIE_NONFAT_ERR 0x3010
4314 #define S_RDRSPERR 9
4315 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
4316 #define F_RDRSPERR V_RDRSPERR(1U)
4318 #define S_VPDRSPERR 8
4319 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
4320 #define F_VPDRSPERR V_VPDRSPERR(1U)
4323 #define V_POPD(x) ((x) << S_POPD)
4324 #define F_POPD V_POPD(1U)
4327 #define V_POPH(x) ((x) << S_POPH)
4328 #define F_POPH V_POPH(1U)
4331 #define V_POPC(x) ((x) << S_POPC)
4332 #define F_POPC V_POPC(1U)
4335 #define V_MEMREQ(x) ((x) << S_MEMREQ)
4336 #define F_MEMREQ V_MEMREQ(1U)
4339 #define V_PIOREQ(x) ((x) << S_PIOREQ)
4340 #define F_PIOREQ V_PIOREQ(1U)
4343 #define V_TAGDROP(x) ((x) << S_TAGDROP)
4344 #define F_TAGDROP V_TAGDROP(1U)
4347 #define V_TAGCPL(x) ((x) << S_TAGCPL)
4348 #define F_TAGCPL V_TAGCPL(1U)
4351 #define V_CFGSNP(x) ((x) << S_CFGSNP)
4352 #define F_CFGSNP V_CFGSNP(1U)
4354 #define S_MAREQTIMEOUT 29
4355 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
4356 #define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U)
4358 #define S_TRGT1BARTYPEERR 28
4359 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
4360 #define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U)
4362 #define S_MAEXTRARSPERR 27
4363 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
4364 #define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U)
4366 #define S_MARSPTIMEOUT 26
4367 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
4368 #define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U)
4370 #define S_INTVFALLMSIDISERR 25
4371 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
4372 #define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U)
4374 #define S_INTVFRANGEERR 24
4375 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
4376 #define F_INTVFRANGEERR V_INTVFRANGEERR(1U)
4378 #define S_INTPLIRSPERR 23
4379 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
4380 #define F_INTPLIRSPERR V_INTPLIRSPERR(1U)
4382 #define S_MEMREQRDTAGERR 22
4383 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
4384 #define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U)
4386 #define S_CFGINITDONEERR 21
4387 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
4388 #define F_CFGINITDONEERR V_CFGINITDONEERR(1U)
4390 #define S_BAR2TIMEOUT 20
4391 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
4392 #define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U)
4394 #define S_VPDTIMEOUT 19
4395 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
4396 #define F_VPDTIMEOUT V_VPDTIMEOUT(1U)
4398 #define S_MEMRSPRDTAGERR 18
4399 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
4400 #define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U)
4402 #define S_MEMRSPWRTAGERR 17
4403 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
4404 #define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U)
4406 #define S_PIORSPRDTAGERR 16
4407 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
4408 #define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U)
4410 #define S_PIORSPWRTAGERR 15
4411 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
4412 #define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U)
4414 #define S_DBITIMEOUT 14
4415 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
4416 #define F_DBITIMEOUT V_DBITIMEOUT(1U)
4418 #define S_PIOUNALINDWR 13
4419 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
4420 #define F_PIOUNALINDWR V_PIOUNALINDWR(1U)
4422 #define S_BAR2RDERR 12
4423 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
4424 #define F_BAR2RDERR V_BAR2RDERR(1U)
4426 #define S_MAWREOPERR 11
4427 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
4428 #define F_MAWREOPERR V_MAWREOPERR(1U)
4430 #define S_MARDEOPERR 10
4431 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
4432 #define F_MARDEOPERR V_MARDEOPERR(1U)
4435 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
4436 #define F_BAR2REQ V_BAR2REQ(1U)
4438 #define S_MARSPUE 30
4439 #define V_MARSPUE(x) ((x) << S_MARSPUE)
4440 #define F_MARSPUE V_MARSPUE(1U)
4442 #define S_KDBEOPERR 7
4443 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
4444 #define F_KDBEOPERR V_KDBEOPERR(1U)
4446 #define A_PCIE_CFG 0x3014
4448 #define S_CFGDMAXPYLDSZRX 26
4449 #define M_CFGDMAXPYLDSZRX 0x7U
4450 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
4451 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
4453 #define S_CFGDMAXPYLDSZTX 23
4454 #define M_CFGDMAXPYLDSZTX 0x7U
4455 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
4456 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
4458 #define S_CFGDMAXRDREQSZ 20
4459 #define M_CFGDMAXRDREQSZ 0x7U
4460 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
4461 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
4463 #define S_MASYNCEN 19
4464 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
4465 #define F_MASYNCEN V_MASYNCEN(1U)
4467 #define S_DCAENDMA 18
4468 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
4469 #define F_DCAENDMA V_DCAENDMA(1U)
4471 #define S_DCAENCMD 17
4472 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
4473 #define F_DCAENCMD V_DCAENCMD(1U)
4475 #define S_VFMSIPNDEN 16
4476 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
4477 #define F_VFMSIPNDEN V_VFMSIPNDEN(1U)
4479 #define S_FORCETXERROR 15
4480 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
4481 #define F_FORCETXERROR V_FORCETXERROR(1U)
4483 #define S_VPDREQPROTECT 14
4484 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
4485 #define F_VPDREQPROTECT V_VPDREQPROTECT(1U)
4487 #define S_FIDTABLEINVALID 13
4488 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
4489 #define F_FIDTABLEINVALID V_FIDTABLEINVALID(1U)
4491 #define S_BYPASSMSIXCACHE 12
4492 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
4493 #define F_BYPASSMSIXCACHE V_BYPASSMSIXCACHE(1U)
4495 #define S_BYPASSMSICACHE 11
4496 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
4497 #define F_BYPASSMSICACHE V_BYPASSMSICACHE(1U)
4499 #define S_SIMSPEED 10
4500 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
4501 #define F_SIMSPEED V_SIMSPEED(1U)
4503 #define S_TC0_STAMP 9
4504 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
4505 #define F_TC0_STAMP V_TC0_STAMP(1U)
4507 #define S_AI_TCVAL 6
4508 #define M_AI_TCVAL 0x7U
4509 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
4510 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
4512 #define S_DMASTOPEN 5
4513 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
4514 #define F_DMASTOPEN V_DMASTOPEN(1U)
4516 #define S_DEVSTATERSTMODE 4
4517 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
4518 #define F_DEVSTATERSTMODE V_DEVSTATERSTMODE(1U)
4520 #define S_HOTRSTPCIECRSTMODE 3
4521 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
4522 #define F_HOTRSTPCIECRSTMODE V_HOTRSTPCIECRSTMODE(1U)
4524 #define S_DLDNPCIECRSTMODE 2
4525 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
4526 #define F_DLDNPCIECRSTMODE V_DLDNPCIECRSTMODE(1U)
4528 #define S_DLDNPCIEPRECRSTMODE 1
4529 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
4530 #define F_DLDNPCIEPRECRSTMODE V_DLDNPCIEPRECRSTMODE(1U)
4532 #define S_LINKDNRSTEN 0
4533 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
4534 #define F_LINKDNRSTEN V_LINKDNRSTEN(1U)
4536 #define S_T5_PIOSTOPEN 31
4537 #define V_T5_PIOSTOPEN(x) ((x) << S_T5_PIOSTOPEN)
4538 #define F_T5_PIOSTOPEN V_T5_PIOSTOPEN(1U)
4540 #define S_DIAGCTRLBUS 28
4541 #define M_DIAGCTRLBUS 0x7U
4542 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
4543 #define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
4545 #define S_IPPERREN 27
4546 #define V_IPPERREN(x) ((x) << S_IPPERREN)
4547 #define F_IPPERREN V_IPPERREN(1U)
4549 #define S_CFGDEXTTAGEN 26
4550 #define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
4551 #define F_CFGDEXTTAGEN V_CFGDEXTTAGEN(1U)
4553 #define S_CFGDMAXPYLDSZ 23
4554 #define M_CFGDMAXPYLDSZ 0x7U
4555 #define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
4556 #define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
4559 #define V_DCAEN(x) ((x) << S_DCAEN)
4560 #define F_DCAEN V_DCAEN(1U)
4562 #define S_T5CMDREQPRIORITY 16
4563 #define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
4564 #define F_T5CMDREQPRIORITY V_T5CMDREQPRIORITY(1U)
4566 #define S_T5VPDREQPROTECT 14
4567 #define M_T5VPDREQPROTECT 0x3U
4568 #define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
4569 #define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
4571 #define S_DROPPEDRDRSPDATA 12
4572 #define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
4573 #define F_DROPPEDRDRSPDATA V_DROPPEDRDRSPDATA(1U)
4575 #define S_AI_INTX_REASSERTEN 11
4576 #define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
4577 #define F_AI_INTX_REASSERTEN V_AI_INTX_REASSERTEN(1U)
4579 #define S_AUTOTXNDISABLE 10
4580 #define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
4581 #define F_AUTOTXNDISABLE V_AUTOTXNDISABLE(1U)
4583 #define S_LINKREQRSTPCIECRSTMODE 3
4584 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
4585 #define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U)
4587 #define S_T6_PIOSTOPEN 31
4588 #define V_T6_PIOSTOPEN(x) ((x) << S_T6_PIOSTOPEN)
4589 #define F_T6_PIOSTOPEN V_T6_PIOSTOPEN(1U)
4591 #define A_PCIE_DMA_CTRL 0x3018
4593 #define S_LITTLEENDIAN 7
4594 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
4595 #define F_LITTLEENDIAN V_LITTLEENDIAN(1U)
4597 #define A_PCIE_CFG2 0x3018
4599 #define S_VPDTIMER 16
4600 #define M_VPDTIMER 0xffffU
4601 #define V_VPDTIMER(x) ((x) << S_VPDTIMER)
4602 #define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
4604 #define S_BAR2TIMER 4
4605 #define M_BAR2TIMER 0xfffU
4606 #define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
4607 #define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
4609 #define S_MSTREQRDRRASIMPLE 3
4610 #define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
4611 #define F_MSTREQRDRRASIMPLE V_MSTREQRDRRASIMPLE(1U)
4613 #define S_TOTMAXTAG 0
4614 #define M_TOTMAXTAG 0x3U
4615 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
4616 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
4618 #define S_T6_TOTMAXTAG 0
4619 #define M_T6_TOTMAXTAG 0x7U
4620 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
4621 #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
4623 #define A_PCIE_DMA_CFG 0x301c
4625 #define S_MAXPYLDSIZE 28
4626 #define M_MAXPYLDSIZE 0x7U
4627 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
4628 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
4630 #define S_MAXRDREQSIZE 25
4631 #define M_MAXRDREQSIZE 0x7U
4632 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
4633 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
4635 #define S_DMA_MAXRSPCNT 16
4636 #define M_DMA_MAXRSPCNT 0x1ffU
4637 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
4638 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
4640 #define S_DMA_MAXREQCNT 8
4641 #define M_DMA_MAXREQCNT 0xffU
4642 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
4643 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
4646 #define M_MAXTAG 0x7fU
4647 #define V_MAXTAG(x) ((x) << S_MAXTAG)
4648 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
4650 #define A_PCIE_CFG3 0x301c
4652 #define S_AUTOPIOCOOKIEMATCH 6
4653 #define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
4654 #define F_AUTOPIOCOOKIEMATCH V_AUTOPIOCOOKIEMATCH(1U)
4656 #define S_FLRPNDCPLMODE 4
4657 #define M_FLRPNDCPLMODE 0x3U
4658 #define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
4659 #define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
4661 #define S_HMADCASTFIRSTONLY 2
4662 #define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
4663 #define F_HMADCASTFIRSTONLY V_HMADCASTFIRSTONLY(1U)
4665 #define S_CMDDCASTFIRSTONLY 1
4666 #define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
4667 #define F_CMDDCASTFIRSTONLY V_CMDDCASTFIRSTONLY(1U)
4669 #define S_DMADCASTFIRSTONLY 0
4670 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
4671 #define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U)
4673 #define A_PCIE_DMA_STAT 0x3020
4675 #define S_STATEREQ 28
4676 #define M_STATEREQ 0xfU
4677 #define V_STATEREQ(x) ((x) << S_STATEREQ)
4678 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
4680 #define S_DMA_RSPCNT 16
4681 #define M_DMA_RSPCNT 0xfffU
4682 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
4683 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
4685 #define S_STATEAREQ 13
4686 #define M_STATEAREQ 0x7U
4687 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
4688 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
4690 #define S_TAGFREE 12
4691 #define V_TAGFREE(x) ((x) << S_TAGFREE)
4692 #define F_TAGFREE V_TAGFREE(1U)
4694 #define S_DMA_REQCNT 0
4695 #define M_DMA_REQCNT 0x7ffU
4696 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
4697 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
4699 #define A_PCIE_CFG4 0x3020
4701 #define S_L1CLKREMOVALEN 17
4702 #define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
4703 #define F_L1CLKREMOVALEN V_L1CLKREMOVALEN(1U)
4705 #define S_READYENTERL23 16
4706 #define V_READYENTERL23(x) ((x) << S_READYENTERL23)
4707 #define F_READYENTERL23 V_READYENTERL23(1U)
4710 #define V_EXITL1(x) ((x) << S_EXITL1)
4711 #define F_EXITL1 V_EXITL1(1U)
4714 #define V_ENTERL1(x) ((x) << S_ENTERL1)
4715 #define F_ENTERL1 V_ENTERL1(1U)
4718 #define M_GENPME 0xffU
4719 #define V_GENPME(x) ((x) << S_GENPME)
4720 #define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
4722 #define A_PCIE_CFG5 0x3024
4724 #define S_ENABLESKPPARITYFIX 2
4725 #define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
4726 #define F_ENABLESKPPARITYFIX V_ENABLESKPPARITYFIX(1U)
4728 #define S_ENABLEL2ENTRYINL1 1
4729 #define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
4730 #define F_ENABLEL2ENTRYINL1 V_ENABLEL2ENTRYINL1(1U)
4732 #define S_HOLDCPLENTERINGL1 0
4733 #define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
4734 #define F_HOLDCPLENTERINGL1 V_HOLDCPLENTERINGL1(1U)
4736 #define A_PCIE_CFG6 0x3028
4738 #define S_PERSTTIMERCOUNT 12
4739 #define M_PERSTTIMERCOUNT 0x3fffU
4740 #define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
4741 #define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
4743 #define S_PERSTTIMEOUT 8
4744 #define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
4745 #define F_PERSTTIMEOUT V_PERSTTIMEOUT(1U)
4747 #define S_PERSTTIMER 0
4748 #define M_PERSTTIMER 0xfU
4749 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
4750 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
4752 #define A_PCIE_CFG7 0x302c
4753 #define A_PCIE_CMD_CTRL 0x303c
4754 #define A_PCIE_CMD_CFG 0x3040
4756 #define S_MAXRSPCNT 16
4757 #define M_MAXRSPCNT 0xfU
4758 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
4759 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
4761 #define S_MAXREQCNT 8
4762 #define M_MAXREQCNT 0x1fU
4763 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
4764 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
4766 #define A_PCIE_CMD_STAT 0x3044
4769 #define M_RSPCNT 0x7fU
4770 #define V_RSPCNT(x) ((x) << S_RSPCNT)
4771 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
4774 #define M_REQCNT 0xffU
4775 #define V_REQCNT(x) ((x) << S_REQCNT)
4776 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
4778 #define A_PCIE_HMA_CTRL 0x3050
4780 #define S_IPLTSSM 12
4781 #define M_IPLTSSM 0xfU
4782 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
4783 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
4785 #define S_IPCONFIGDOWN 8
4786 #define M_IPCONFIGDOWN 0x7U
4787 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
4788 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
4790 #define A_PCIE_HMA_CFG 0x3054
4792 #define S_HMA_MAXRSPCNT 16
4793 #define M_HMA_MAXRSPCNT 0x1fU
4794 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
4795 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
4797 #define A_PCIE_HMA_STAT 0x3058
4799 #define S_HMA_RSPCNT 16
4800 #define M_HMA_RSPCNT 0xffU
4801 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
4802 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
4804 #define A_PCIE_PIO_FIFO_CFG 0x305c
4806 #define S_CPLCONFIG 16
4807 #define M_CPLCONFIG 0xffffU
4808 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
4809 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
4811 #define S_PIOSTOPEN 12
4812 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
4813 #define F_PIOSTOPEN V_PIOSTOPEN(1U)
4815 #define S_IPLANESWAP 11
4816 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
4817 #define F_IPLANESWAP V_IPLANESWAP(1U)
4819 #define S_FORCESTRICTTS1 10
4820 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
4821 #define F_FORCESTRICTTS1 V_FORCESTRICTTS1(1U)
4823 #define S_FORCEPROGRESSCNT 0
4824 #define M_FORCEPROGRESSCNT 0x3ffU
4825 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
4826 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
4828 #define A_PCIE_CFG_SPACE_REQ 0x3060
4831 #define V_ENABLE(x) ((x) << S_ENABLE)
4832 #define F_ENABLE V_ENABLE(1U)
4835 #define V_AI(x) ((x) << S_AI)
4836 #define F_AI V_AI(1U)
4838 #define S_LOCALCFG 28
4839 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
4840 #define F_LOCALCFG V_LOCALCFG(1U)
4844 #define V_BUS(x) ((x) << S_BUS)
4845 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
4848 #define M_DEVICE 0x1fU
4849 #define V_DEVICE(x) ((x) << S_DEVICE)
4850 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
4852 #define S_FUNCTION 12
4853 #define M_FUNCTION 0x7U
4854 #define V_FUNCTION(x) ((x) << S_FUNCTION)
4855 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
4857 #define S_EXTREGISTER 8
4858 #define M_EXTREGISTER 0xfU
4859 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
4860 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
4862 #define S_REGISTER 0
4863 #define M_REGISTER 0xffU
4864 #define V_REGISTER(x) ((x) << S_REGISTER)
4865 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
4868 #define V_CS2(x) ((x) << S_CS2)
4869 #define F_CS2 V_CS2(1U)
4873 #define V_WRBE(x) ((x) << S_WRBE)
4874 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
4876 #define S_CFG_SPACE_VFVLD 23
4877 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
4878 #define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U)
4880 #define S_CFG_SPACE_RVF 16
4881 #define M_CFG_SPACE_RVF 0x7fU
4882 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
4883 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
4885 #define S_CFG_SPACE_PF 12
4886 #define M_CFG_SPACE_PF 0x7U
4887 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
4888 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
4890 #define S_T6_ENABLE 31
4891 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
4892 #define F_T6_ENABLE V_T6_ENABLE(1U)
4895 #define V_T6_AI(x) ((x) << S_T6_AI)
4896 #define F_T6_AI V_T6_AI(1U)
4899 #define V_T6_CS2(x) ((x) << S_T6_CS2)
4900 #define F_T6_CS2 V_T6_CS2(1U)
4902 #define S_T6_WRBE 25
4903 #define M_T6_WRBE 0xfU
4904 #define V_T6_WRBE(x) ((x) << S_T6_WRBE)
4905 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
4907 #define S_T6_CFG_SPACE_VFVLD 24
4908 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
4909 #define F_T6_CFG_SPACE_VFVLD V_T6_CFG_SPACE_VFVLD(1U)
4911 #define S_T6_CFG_SPACE_RVF 16
4912 #define M_T6_CFG_SPACE_RVF 0xffU
4913 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
4914 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
4916 #define A_PCIE_CFG_SPACE_DATA 0x3064
4917 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
4919 #define S_PCIEOFST 10
4920 #define M_PCIEOFST 0x3fffffU
4921 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
4922 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
4926 #define V_BIR(x) ((x) << S_BIR)
4927 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
4930 #define M_WINDOW 0xffU
4931 #define V_WINDOW(x) ((x) << S_WINDOW)
4932 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
4934 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
4937 #define M_MEMOFST 0x1ffffffU
4938 #define V_MEMOFST(x) ((x) << S_MEMOFST)
4939 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
4941 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
4943 #define S_MBOXPCIEOFST 6
4944 #define M_MBOXPCIEOFST 0x3ffffffU
4945 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
4946 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
4949 #define M_MBOXBIR 0x3U
4950 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
4951 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
4954 #define M_MBOXWIN 0x3U
4955 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
4956 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
4958 #define A_PCIE_MAILBOX_OFFSET 0x30ac
4959 #define A_PCIE_MA_CTRL 0x30b0
4961 #define S_MA_TAGFREE 29
4962 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
4963 #define F_MA_TAGFREE V_MA_TAGFREE(1U)
4965 #define S_MA_MAXRSPCNT 24
4966 #define M_MA_MAXRSPCNT 0x1fU
4967 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
4968 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
4970 #define S_MA_MAXREQCNT 16
4971 #define M_MA_MAXREQCNT 0x1fU
4972 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
4973 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
4976 #define V_MA_LE(x) ((x) << S_MA_LE)
4977 #define F_MA_LE V_MA_LE(1U)
4979 #define S_MA_MAXPYLDSIZE 12
4980 #define M_MA_MAXPYLDSIZE 0x7U
4981 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
4982 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
4984 #define S_MA_MAXRDREQSIZE 8
4985 #define M_MA_MAXRDREQSIZE 0x7U
4986 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
4987 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
4989 #define S_MA_MAXTAG 0
4990 #define M_MA_MAXTAG 0x1fU
4991 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
4992 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
4994 #define S_T5_MA_MAXREQCNT 16
4995 #define M_T5_MA_MAXREQCNT 0x7fU
4996 #define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
4997 #define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
4999 #define S_MA_MAXREQSIZE 8
5000 #define M_MA_MAXREQSIZE 0x7U
5001 #define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
5002 #define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
5004 #define A_PCIE_MA_SYNC 0x30b4
5005 #define A_PCIE_FW 0x30b8
5006 #define A_PCIE_FW_PF 0x30bc
5007 #define A_PCIE_PIO_PAUSE 0x30dc
5009 #define S_PIOPAUSEDONE 31
5010 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
5011 #define F_PIOPAUSEDONE V_PIOPAUSEDONE(1U)
5013 #define S_PIOPAUSETIME 4
5014 #define M_PIOPAUSETIME 0xffffffU
5015 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
5016 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
5018 #define S_PIOPAUSE 0
5019 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
5020 #define F_PIOPAUSE V_PIOPAUSE(1U)
5022 #define S_MSTPAUSEDONE 30
5023 #define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
5024 #define F_MSTPAUSEDONE V_MSTPAUSEDONE(1U)
5026 #define S_MSTPAUSE 1
5027 #define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
5028 #define F_MSTPAUSE V_MSTPAUSE(1U)
5030 #define A_PCIE_SYS_CFG_READY 0x30e0
5031 #define A_PCIE_MA_STAT 0x30e0
5032 #define A_PCIE_STATIC_CFG1 0x30e4
5034 #define S_LINKDOWN_RESET_EN 26
5035 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
5036 #define F_LINKDOWN_RESET_EN V_LINKDOWN_RESET_EN(1U)
5038 #define S_IN_WR_DISCONTIG 25
5039 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
5040 #define F_IN_WR_DISCONTIG V_IN_WR_DISCONTIG(1U)
5042 #define S_IN_RD_CPLSIZE 22
5043 #define M_IN_RD_CPLSIZE 0x7U
5044 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
5045 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
5047 #define S_IN_RD_BUFMODE 20
5048 #define M_IN_RD_BUFMODE 0x3U
5049 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
5050 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
5052 #define S_GBIF_NPTRANS_TOT 18
5053 #define M_GBIF_NPTRANS_TOT 0x3U
5054 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
5055 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
5057 #define S_IN_PDAT_TOT 15
5058 #define M_IN_PDAT_TOT 0x7U
5059 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
5060 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
5062 #define S_PCIE_NPTRANS_TOT 12
5063 #define M_PCIE_NPTRANS_TOT 0x7U
5064 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
5065 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
5067 #define S_OUT_PDAT_TOT 9
5068 #define M_OUT_PDAT_TOT 0x7U
5069 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
5070 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
5072 #define S_GBIF_MAX_WRSIZE 6
5073 #define M_GBIF_MAX_WRSIZE 0x7U
5074 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
5075 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
5077 #define S_GBIF_MAX_RDSIZE 3
5078 #define M_GBIF_MAX_RDSIZE 0x7U
5079 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
5080 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
5082 #define S_PCIE_MAX_RDSIZE 0
5083 #define M_PCIE_MAX_RDSIZE 0x7U
5084 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
5085 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
5087 #define S_AUXPOWER_DETECTED 27
5088 #define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
5089 #define F_AUXPOWER_DETECTED V_AUXPOWER_DETECTED(1U)
5091 #define A_PCIE_STATIC_CFG2 0x30e8
5093 #define S_PL_CONTROL 16
5094 #define M_PL_CONTROL 0xffffU
5095 #define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
5096 #define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
5098 #define S_STATIC_SPARE3 0
5099 #define M_STATIC_SPARE3 0x3fffU
5100 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
5101 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
5103 #define A_PCIE_DBG_INDIR_REQ 0x30ec
5105 #define S_DBGENABLE 31
5106 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
5107 #define F_DBGENABLE V_DBGENABLE(1U)
5109 #define S_DBGAUTOINC 30
5110 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
5111 #define F_DBGAUTOINC V_DBGAUTOINC(1U)
5114 #define M_POINTER 0xffffU
5115 #define V_POINTER(x) ((x) << S_POINTER)
5116 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
5119 #define M_SELECT 0xfU
5120 #define V_SELECT(x) ((x) << S_SELECT)
5121 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
5123 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
5124 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
5125 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
5126 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
5127 #define A_PCIE_FUNC_INT_CFG 0x3100
5129 #define S_PBAOFST 28
5130 #define M_PBAOFST 0xfU
5131 #define V_PBAOFST(x) ((x) << S_PBAOFST)
5132 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
5134 #define S_TABOFST 24
5135 #define M_TABOFST 0xfU
5136 #define V_TABOFST(x) ((x) << S_TABOFST)
5137 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
5140 #define M_VECNUM 0x3ffU
5141 #define V_VECNUM(x) ((x) << S_VECNUM)
5142 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
5145 #define M_VECBASE 0x7ffU
5146 #define V_VECBASE(x) ((x) << S_VECBASE)
5147 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
5149 #define A_PCIE_FUNC_CTL_STAT 0x3104
5151 #define S_SENDFLRRSP 31
5152 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
5153 #define F_SENDFLRRSP V_SENDFLRRSP(1U)
5155 #define S_IMMFLRRSP 24
5156 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
5157 #define F_IMMFLRRSP V_IMMFLRRSP(1U)
5159 #define S_TXNDISABLE 20
5160 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
5161 #define F_TXNDISABLE V_TXNDISABLE(1U)
5164 #define M_PNDTXNS 0x3ffU
5165 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
5166 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
5169 #define V_VFVLD(x) ((x) << S_VFVLD)
5170 #define F_VFVLD V_VFVLD(1U)
5173 #define M_PFNUM 0x7U
5174 #define V_PFNUM(x) ((x) << S_PFNUM)
5175 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
5177 #define A_PCIE_PF_INT_CFG 0x3140
5178 #define A_PCIE_PF_INT_CFG2 0x3144
5179 #define A_PCIE_VF_INT_CFG 0x3180
5180 #define A_PCIE_VF_INT_CFG2 0x3184
5181 #define A_PCIE_PF_MSI_EN 0x35a8
5183 #define S_PFMSIEN_7_0 0
5184 #define M_PFMSIEN_7_0 0xffU
5185 #define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
5186 #define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
5188 #define A_PCIE_VF_MSI_EN_0 0x35ac
5189 #define A_PCIE_VF_MSI_EN_1 0x35b0
5190 #define A_PCIE_VF_MSI_EN_2 0x35b4
5191 #define A_PCIE_VF_MSI_EN_3 0x35b8
5192 #define A_PCIE_PF_MSIX_EN 0x35bc
5194 #define S_PFMSIXEN_7_0 0
5195 #define M_PFMSIXEN_7_0 0xffU
5196 #define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
5197 #define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
5199 #define A_PCIE_VF_MSIX_EN_0 0x35c0
5200 #define A_PCIE_VF_MSIX_EN_1 0x35c4
5201 #define A_PCIE_VF_MSIX_EN_2 0x35c8
5202 #define A_PCIE_VF_MSIX_EN_3 0x35cc
5203 #define A_PCIE_FID_VFID_SEL 0x35ec
5205 #define S_FID_VFID_SEL_SELECT 0
5206 #define M_FID_VFID_SEL_SELECT 0x3U
5207 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
5208 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
5210 #define A_PCIE_FID_VFID 0x3600
5212 #define S_FID_VFID_SELECT 30
5213 #define M_FID_VFID_SELECT 0x3U
5214 #define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
5215 #define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
5218 #define V_IDO(x) ((x) << S_IDO)
5219 #define F_IDO V_IDO(1U)
5221 #define S_FID_VFID_VFID 16
5222 #define M_FID_VFID_VFID 0xffU
5223 #define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
5224 #define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
5226 #define S_FID_VFID_TC 11
5227 #define M_FID_VFID_TC 0x7U
5228 #define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
5229 #define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
5231 #define S_FID_VFID_VFVLD 10
5232 #define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
5233 #define F_FID_VFID_VFVLD V_FID_VFID_VFVLD(1U)
5235 #define S_FID_VFID_PF 7
5236 #define M_FID_VFID_PF 0x7U
5237 #define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
5238 #define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
5240 #define S_FID_VFID_RVF 0
5241 #define M_FID_VFID_RVF 0x7fU
5242 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
5243 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
5245 #define S_T6_FID_VFID_VFID 15
5246 #define M_T6_FID_VFID_VFID 0x1ffU
5247 #define V_T6_FID_VFID_VFID(x) ((x) << S_T6_FID_VFID_VFID)
5248 #define G_T6_FID_VFID_VFID(x) (((x) >> S_T6_FID_VFID_VFID) & M_T6_FID_VFID_VFID)
5250 #define S_T6_FID_VFID_TC 12
5251 #define M_T6_FID_VFID_TC 0x7U
5252 #define V_T6_FID_VFID_TC(x) ((x) << S_T6_FID_VFID_TC)
5253 #define G_T6_FID_VFID_TC(x) (((x) >> S_T6_FID_VFID_TC) & M_T6_FID_VFID_TC)
5255 #define S_T6_FID_VFID_VFVLD 11
5256 #define V_T6_FID_VFID_VFVLD(x) ((x) << S_T6_FID_VFID_VFVLD)
5257 #define F_T6_FID_VFID_VFVLD V_T6_FID_VFID_VFVLD(1U)
5259 #define S_T6_FID_VFID_PF 8
5260 #define M_T6_FID_VFID_PF 0x7U
5261 #define V_T6_FID_VFID_PF(x) ((x) << S_T6_FID_VFID_PF)
5262 #define G_T6_FID_VFID_PF(x) (((x) >> S_T6_FID_VFID_PF) & M_T6_FID_VFID_PF)
5264 #define S_T6_FID_VFID_RVF 0
5265 #define M_T6_FID_VFID_RVF 0xffU
5266 #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
5267 #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
5269 #define A_PCIE_FID 0x3900
5272 #define V_PAD(x) ((x) << S_PAD)
5273 #define F_PAD V_PAD(1U)
5277 #define V_TC(x) ((x) << S_TC)
5278 #define G_TC(x) (((x) >> S_TC) & M_TC)
5281 #define M_FUNC 0xffU
5282 #define V_FUNC(x) ((x) << S_FUNC)
5283 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
5285 #define A_PCIE_COOKIE_STAT 0x5600
5287 #define S_COOKIEB 16
5288 #define M_COOKIEB 0x3ffU
5289 #define V_COOKIEB(x) ((x) << S_COOKIEB)
5290 #define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
5293 #define M_COOKIEA 0x3ffU
5294 #define V_COOKIEA(x) ((x) << S_COOKIEA)
5295 #define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
5297 #define A_PCIE_FLR_PIO 0x5620
5299 #define S_RCVDBAR2COOKIE 24
5300 #define M_RCVDBAR2COOKIE 0xffU
5301 #define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
5302 #define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
5304 #define S_RCVDMARSPCOOKIE 16
5305 #define M_RCVDMARSPCOOKIE 0xffU
5306 #define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
5307 #define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
5309 #define S_RCVDPIORSPCOOKIE 8
5310 #define M_RCVDPIORSPCOOKIE 0xffU
5311 #define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
5312 #define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
5314 #define S_EXPDCOOKIE 0
5315 #define M_EXPDCOOKIE 0xffU
5316 #define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
5317 #define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
5319 #define A_PCIE_FLR_PIO2 0x5624
5321 #define S_RCVDMAREQCOOKIE 16
5322 #define M_RCVDMAREQCOOKIE 0xffU
5323 #define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
5324 #define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
5326 #define S_RCVDPIOREQCOOKIE 8
5327 #define M_RCVDPIOREQCOOKIE 0xffU
5328 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
5329 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
5331 #define S_RCVDVDMRXCOOKIE 24
5332 #define M_RCVDVDMRXCOOKIE 0xffU
5333 #define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE)
5334 #define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE)
5336 #define S_RCVDVDMTXCOOKIE 16
5337 #define M_RCVDVDMTXCOOKIE 0xffU
5338 #define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE)
5339 #define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE)
5341 #define S_T6_RCVDMAREQCOOKIE 8
5342 #define M_T6_RCVDMAREQCOOKIE 0xffU
5343 #define V_T6_RCVDMAREQCOOKIE(x) ((x) << S_T6_RCVDMAREQCOOKIE)
5344 #define G_T6_RCVDMAREQCOOKIE(x) (((x) >> S_T6_RCVDMAREQCOOKIE) & M_T6_RCVDMAREQCOOKIE)
5346 #define S_T6_RCVDPIOREQCOOKIE 0
5347 #define M_T6_RCVDPIOREQCOOKIE 0xffU
5348 #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
5349 #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
5351 #define A_PCIE_VC0_CDTS0 0x56cc
5354 #define M_CPLD0 0xfffU
5355 #define V_CPLD0(x) ((x) << S_CPLD0)
5356 #define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
5360 #define V_PH0(x) ((x) << S_PH0)
5361 #define G_PH0(x) (((x) >> S_PH0) & M_PH0)
5364 #define M_PD0 0xfffU
5365 #define V_PD0(x) ((x) << S_PD0)
5366 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
5368 #define A_PCIE_VC0_CDTS1 0x56d0
5371 #define M_CPLH0 0xffU
5372 #define V_CPLH0(x) ((x) << S_CPLH0)
5373 #define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
5376 #define M_NPH0 0xffU
5377 #define V_NPH0(x) ((x) << S_NPH0)
5378 #define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
5381 #define M_NPD0 0xfffU
5382 #define V_NPD0(x) ((x) << S_NPD0)
5383 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
5385 #define A_PCIE_VC1_CDTS0 0x56d4
5388 #define M_CPLD1 0xfffU
5389 #define V_CPLD1(x) ((x) << S_CPLD1)
5390 #define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
5394 #define V_PH1(x) ((x) << S_PH1)
5395 #define G_PH1(x) (((x) >> S_PH1) & M_PH1)
5398 #define M_PD1 0xfffU
5399 #define V_PD1(x) ((x) << S_PD1)
5400 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
5402 #define A_PCIE_VC1_CDTS1 0x56d8
5405 #define M_CPLH1 0xffU
5406 #define V_CPLH1(x) ((x) << S_CPLH1)
5407 #define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
5410 #define M_NPH1 0xffU
5411 #define V_NPH1(x) ((x) << S_NPH1)
5412 #define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
5415 #define M_NPD1 0xfffU
5416 #define V_NPD1(x) ((x) << S_NPD1)
5417 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
5419 #define A_PCIE_FLR_PF_STATUS 0x56dc
5420 #define A_PCIE_FLR_VF0_STATUS 0x56e0
5421 #define A_PCIE_FLR_VF1_STATUS 0x56e4
5422 #define A_PCIE_FLR_VF2_STATUS 0x56e8
5423 #define A_PCIE_FLR_VF3_STATUS 0x56ec
5424 #define A_PCIE_STAT 0x56f4
5426 #define S_PM_STATUS 24
5427 #define M_PM_STATUS 0xffU
5428 #define V_PM_STATUS(x) ((x) << S_PM_STATUS)
5429 #define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
5431 #define S_PM_CURRENTSTATE 20
5432 #define M_PM_CURRENTSTATE 0x7U
5433 #define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
5434 #define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
5436 #define S_LTSSMENABLE 12
5437 #define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
5438 #define F_LTSSMENABLE V_LTSSMENABLE(1U)
5440 #define S_STATECFGINITF 4
5441 #define M_STATECFGINITF 0x7fU
5442 #define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
5443 #define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
5445 #define S_STATECFGINIT 0
5446 #define M_STATECFGINIT 0xfU
5447 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
5448 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
5450 #define S_LTSSMENABLE_PCIE 12
5451 #define V_LTSSMENABLE_PCIE(x) ((x) << S_LTSSMENABLE_PCIE)
5452 #define F_LTSSMENABLE_PCIE V_LTSSMENABLE_PCIE(1U)
5454 #define S_STATECFGINITF_PCIE 4
5455 #define M_STATECFGINITF_PCIE 0xffU
5456 #define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE)
5457 #define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE)
5459 #define S_STATECFGINIT_PCIE 0
5460 #define M_STATECFGINIT_PCIE 0xfU
5461 #define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE)
5462 #define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE)
5464 #define A_PCIE_CRS 0x56f8
5466 #define S_CRS_ENABLE 0
5467 #define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
5468 #define F_CRS_ENABLE V_CRS_ENABLE(1U)
5470 #define A_PCIE_LTSSM 0x56fc
5472 #define S_LTSSM_ENABLE 0
5473 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
5474 #define F_LTSSM_ENABLE V_LTSSM_ENABLE(1U)
5476 #define S_LTSSM_STALL_DISABLE 1
5477 #define V_LTSSM_STALL_DISABLE(x) ((x) << S_LTSSM_STALL_DISABLE)
5478 #define F_LTSSM_STALL_DISABLE V_LTSSM_STALL_DISABLE(1U)
5480 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
5482 #define S_REPLAY_TIME_LIMIT 16
5483 #define M_REPLAY_TIME_LIMIT 0xffffU
5484 #define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
5485 #define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
5487 #define S_ACK_LATENCY_TIMER_LIMIT 0
5488 #define M_ACK_LATENCY_TIMER_LIMIT 0xffffU
5489 #define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
5490 #define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
5492 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
5493 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
5495 #define S_LOW_POWER_ENTRANCE_COUNT 24
5496 #define M_LOW_POWER_ENTRANCE_COUNT 0xffU
5497 #define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
5498 #define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
5500 #define S_LINK_STATE 16
5501 #define M_LINK_STATE 0x3fU
5502 #define V_LINK_STATE(x) ((x) << S_LINK_STATE)
5503 #define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
5505 #define S_FORCE_LINK 15
5506 #define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
5507 #define F_FORCE_LINK V_FORCE_LINK(1U)
5509 #define S_LINK_NUMBER 0
5510 #define M_LINK_NUMBER 0xffU
5511 #define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
5512 #define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
5514 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
5516 #define S_ENTER_ASPM_L1_WO_L0S 30
5517 #define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
5518 #define F_ENTER_ASPM_L1_WO_L0S V_ENTER_ASPM_L1_WO_L0S(1U)
5520 #define S_L1_ENTRANCE_LATENCY 27
5521 #define M_L1_ENTRANCE_LATENCY 0x7U
5522 #define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
5523 #define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
5525 #define S_L0S_ENTRANCE_LATENCY 24
5526 #define M_L0S_ENTRANCE_LATENCY 0x7U
5527 #define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
5528 #define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
5530 #define S_COMMON_CLOCK_N_FTS 16
5531 #define M_COMMON_CLOCK_N_FTS 0xffU
5532 #define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
5533 #define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
5536 #define M_N_FTS 0xffU
5537 #define V_N_FTS(x) ((x) << S_N_FTS)
5538 #define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
5540 #define S_ACK_FREQUENCY 0
5541 #define M_ACK_FREQUENCY 0xffU
5542 #define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
5543 #define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
5545 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
5547 #define S_CROSSLINK_ACTIVE 23
5548 #define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
5549 #define F_CROSSLINK_ACTIVE V_CROSSLINK_ACTIVE(1U)
5551 #define S_CROSSLINK_ENABLE 22
5552 #define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
5553 #define F_CROSSLINK_ENABLE V_CROSSLINK_ENABLE(1U)
5555 #define S_LINK_MODE_ENABLE 16
5556 #define M_LINK_MODE_ENABLE 0x3fU
5557 #define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
5558 #define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
5560 #define S_FAST_LINK_MODE 7
5561 #define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
5562 #define F_FAST_LINK_MODE V_FAST_LINK_MODE(1U)
5564 #define S_DLL_LINK_ENABLE 5
5565 #define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
5566 #define F_DLL_LINK_ENABLE V_DLL_LINK_ENABLE(1U)
5568 #define S_RESET_ASSERT 3
5569 #define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
5570 #define F_RESET_ASSERT V_RESET_ASSERT(1U)
5572 #define S_LOOPBACK_ENABLE 2
5573 #define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
5574 #define F_LOOPBACK_ENABLE V_LOOPBACK_ENABLE(1U)
5576 #define S_SCRAMBLE_DISABLE 1
5577 #define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
5578 #define F_SCRAMBLE_DISABLE V_SCRAMBLE_DISABLE(1U)
5580 #define S_VENDOR_SPECIFIC_DLLP_REQUEST 0
5581 #define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
5582 #define F_VENDOR_SPECIFIC_DLLP_REQUEST V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
5584 #define A_PCIE_CORE_LANE_SKEW 0x5714
5586 #define S_DISABLE_DESKEW 31
5587 #define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
5588 #define F_DISABLE_DESKEW V_DISABLE_DESKEW(1U)
5590 #define S_ACK_NAK_DISABLE 25
5591 #define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
5592 #define F_ACK_NAK_DISABLE V_ACK_NAK_DISABLE(1U)
5594 #define S_FLOW_CONTROL_DISABLE 24
5595 #define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
5596 #define F_FLOW_CONTROL_DISABLE V_FLOW_CONTROL_DISABLE(1U)
5598 #define S_INSERT_TXSKEW 0
5599 #define M_INSERT_TXSKEW 0xffffffU
5600 #define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
5601 #define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
5603 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
5605 #define S_FLOW_CONTROL_TIMER_MODIFIER 24
5606 #define M_FLOW_CONTROL_TIMER_MODIFIER 0x1fU
5607 #define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
5608 #define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
5610 #define S_ACK_NAK_TIMER_MODIFIER 19
5611 #define M_ACK_NAK_TIMER_MODIFIER 0x1fU
5612 #define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
5613 #define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
5615 #define S_REPLAY_TIMER_MODIFIER 14
5616 #define M_REPLAY_TIMER_MODIFIER 0x1fU
5617 #define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
5618 #define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
5621 #define M_MAXFUNC 0x7U
5622 #define V_MAXFUNC(x) ((x) << S_MAXFUNC)
5623 #define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
5625 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
5627 #define S_MASK_RADM_FILTER 16
5628 #define M_MASK_RADM_FILTER 0xffffU
5629 #define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
5630 #define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
5632 #define S_DISABLE_FC_WATCHDOG 15
5633 #define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
5634 #define F_DISABLE_FC_WATCHDOG V_DISABLE_FC_WATCHDOG(1U)
5636 #define S_SKP_INTERVAL 0
5637 #define M_SKP_INTERVAL 0x7ffU
5638 #define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
5639 #define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
5641 #define A_PCIE_CORE_FILTER_MASK2 0x5720
5642 #define A_PCIE_CORE_DEBUG_0 0x5728
5643 #define A_PCIE_CORE_DEBUG_1 0x572c
5644 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
5646 #define S_TXPH_FC 12
5647 #define M_TXPH_FC 0xffU
5648 #define V_TXPH_FC(x) ((x) << S_TXPH_FC)
5649 #define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
5652 #define M_TXPD_FC 0xfffU
5653 #define V_TXPD_FC(x) ((x) << S_TXPD_FC)
5654 #define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
5656 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
5658 #define S_TXNPH_FC 12
5659 #define M_TXNPH_FC 0xffU
5660 #define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
5661 #define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
5663 #define S_TXNPD_FC 0
5664 #define M_TXNPD_FC 0xfffU
5665 #define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
5666 #define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
5668 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
5670 #define S_TXCPLH_FC 12
5671 #define M_TXCPLH_FC 0xffU
5672 #define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
5673 #define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
5675 #define S_TXCPLD_FC 0
5676 #define M_TXCPLD_FC 0xfffU
5677 #define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
5678 #define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
5680 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
5682 #define S_RXQUEUE_NOT_EMPTY 2
5683 #define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
5684 #define F_RXQUEUE_NOT_EMPTY V_RXQUEUE_NOT_EMPTY(1U)
5686 #define S_TXRETRYBUF_NOT_EMPTY 1
5687 #define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
5688 #define F_TXRETRYBUF_NOT_EMPTY V_TXRETRYBUF_NOT_EMPTY(1U)
5690 #define S_RXTLP_FC_NOT_RETURNED 0
5691 #define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
5692 #define F_RXTLP_FC_NOT_RETURNED V_RXTLP_FC_NOT_RETURNED(1U)
5694 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
5696 #define S_VC3_WRR 24
5697 #define M_VC3_WRR 0xffU
5698 #define V_VC3_WRR(x) ((x) << S_VC3_WRR)
5699 #define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
5701 #define S_VC2_WRR 16
5702 #define M_VC2_WRR 0xffU
5703 #define V_VC2_WRR(x) ((x) << S_VC2_WRR)
5704 #define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
5707 #define M_VC1_WRR 0xffU
5708 #define V_VC1_WRR(x) ((x) << S_VC1_WRR)
5709 #define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
5712 #define M_VC0_WRR 0xffU
5713 #define V_VC0_WRR(x) ((x) << S_VC0_WRR)
5714 #define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
5716 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
5718 #define S_VC7_WRR 24
5719 #define M_VC7_WRR 0xffU
5720 #define V_VC7_WRR(x) ((x) << S_VC7_WRR)
5721 #define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
5723 #define S_VC6_WRR 16
5724 #define M_VC6_WRR 0xffU
5725 #define V_VC6_WRR(x) ((x) << S_VC6_WRR)
5726 #define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
5729 #define M_VC5_WRR 0xffU
5730 #define V_VC5_WRR(x) ((x) << S_VC5_WRR)
5731 #define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
5734 #define M_VC4_WRR 0xffU
5735 #define V_VC4_WRR(x) ((x) << S_VC4_WRR)
5736 #define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
5738 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
5740 #define S_VC0_RX_ORDERING 31
5741 #define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
5742 #define F_VC0_RX_ORDERING V_VC0_RX_ORDERING(1U)
5744 #define S_VC0_TLP_ORDERING 30
5745 #define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
5746 #define F_VC0_TLP_ORDERING V_VC0_TLP_ORDERING(1U)
5748 #define S_VC0_PTLP_QUEUE_MODE 21
5749 #define M_VC0_PTLP_QUEUE_MODE 0x7U
5750 #define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
5751 #define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
5753 #define S_VC0_PH_CREDITS 12
5754 #define M_VC0_PH_CREDITS 0xffU
5755 #define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
5756 #define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
5758 #define S_VC0_PD_CREDITS 0
5759 #define M_VC0_PD_CREDITS 0xfffU
5760 #define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
5761 #define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
5763 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
5765 #define S_VC0_NPTLP_QUEUE_MODE 21
5766 #define M_VC0_NPTLP_QUEUE_MODE 0x7U
5767 #define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
5768 #define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
5770 #define S_VC0_NPH_CREDITS 12
5771 #define M_VC0_NPH_CREDITS 0xffU
5772 #define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
5773 #define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
5775 #define S_VC0_NPD_CREDITS 0
5776 #define M_VC0_NPD_CREDITS 0xfffU
5777 #define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
5778 #define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
5780 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
5782 #define S_VC0_CPLTLP_QUEUE_MODE 21
5783 #define M_VC0_CPLTLP_QUEUE_MODE 0x7U
5784 #define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
5785 #define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
5787 #define S_VC0_CPLH_CREDITS 12
5788 #define M_VC0_CPLH_CREDITS 0xffU
5789 #define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
5790 #define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
5792 #define S_VC0_CPLD_CREDITS 0
5793 #define M_VC0_CPLD_CREDITS 0xfffU
5794 #define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
5795 #define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
5797 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
5799 #define S_VC1_TLP_ORDERING 30
5800 #define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
5801 #define F_VC1_TLP_ORDERING V_VC1_TLP_ORDERING(1U)
5803 #define S_VC1_PTLP_QUEUE_MODE 21
5804 #define M_VC1_PTLP_QUEUE_MODE 0x7U
5805 #define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
5806 #define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
5808 #define S_VC1_PH_CREDITS 12
5809 #define M_VC1_PH_CREDITS 0xffU
5810 #define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
5811 #define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
5813 #define S_VC1_PD_CREDITS 0
5814 #define M_VC1_PD_CREDITS 0xfffU
5815 #define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
5816 #define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
5818 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
5820 #define S_VC1_NPTLP_QUEUE_MODE 21
5821 #define M_VC1_NPTLP_QUEUE_MODE 0x7U
5822 #define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
5823 #define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
5825 #define S_VC1_NPH_CREDITS 12
5826 #define M_VC1_NPH_CREDITS 0xffU
5827 #define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
5828 #define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
5830 #define S_VC1_NPD_CREDITS 0
5831 #define M_VC1_NPD_CREDITS 0xfffU
5832 #define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
5833 #define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
5835 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
5837 #define S_VC1_CPLTLP_QUEUE_MODE 21
5838 #define M_VC1_CPLTLP_QUEUE_MODE 0x7U
5839 #define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
5840 #define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
5842 #define S_VC1_CPLH_CREDITS 12
5843 #define M_VC1_CPLH_CREDITS 0xffU
5844 #define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
5845 #define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
5847 #define S_VC1_CPLD_CREDITS 0
5848 #define M_VC1_CPLD_CREDITS 0xfffU
5849 #define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
5850 #define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
5852 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
5854 #define S_SEL_DEEMPHASIS 20
5855 #define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
5856 #define F_SEL_DEEMPHASIS V_SEL_DEEMPHASIS(1U)
5858 #define S_TXCMPLRCV 19
5859 #define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
5860 #define F_TXCMPLRCV V_TXCMPLRCV(1U)
5862 #define S_PHYTXSWING 18
5863 #define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
5864 #define F_PHYTXSWING V_PHYTXSWING(1U)
5866 #define S_DIRSPDCHANGE 17
5867 #define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
5868 #define F_DIRSPDCHANGE V_DIRSPDCHANGE(1U)
5870 #define S_NUM_LANES 8
5871 #define M_NUM_LANES 0x1ffU
5872 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
5873 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
5875 #define S_NFTS_GEN2_3 0
5876 #define M_NFTS_GEN2_3 0xffU
5877 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
5878 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
5880 #define S_AUTO_LANE_FLIP_CTRL_EN 16
5881 #define V_AUTO_LANE_FLIP_CTRL_EN(x) ((x) << S_AUTO_LANE_FLIP_CTRL_EN)
5882 #define F_AUTO_LANE_FLIP_CTRL_EN V_AUTO_LANE_FLIP_CTRL_EN(1U)
5884 #define S_T6_NUM_LANES 8
5885 #define M_T6_NUM_LANES 0x1fU
5886 #define V_T6_NUM_LANES(x) ((x) << S_T6_NUM_LANES)
5887 #define G_T6_NUM_LANES(x) (((x) >> S_T6_NUM_LANES) & M_T6_NUM_LANES)
5889 #define A_PCIE_CORE_PHY_STATUS 0x5810
5890 #define A_PCIE_CORE_PHY_CONTROL 0x5814
5891 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
5893 #define S_DC_BALANCE_DISABLE 18
5894 #define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
5895 #define F_DC_BALANCE_DISABLE V_DC_BALANCE_DISABLE(1U)
5897 #define S_DLLP_DELAY_DISABLE 17
5898 #define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
5899 #define F_DLLP_DELAY_DISABLE V_DLLP_DELAY_DISABLE(1U)
5901 #define S_EQL_DISABLE 16
5902 #define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
5903 #define F_EQL_DISABLE V_EQL_DISABLE(1U)
5905 #define S_EQL_REDO_DISABLE 11
5906 #define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
5907 #define F_EQL_REDO_DISABLE V_EQL_REDO_DISABLE(1U)
5909 #define S_EQL_EIEOS_CNTRST_DISABLE 10
5910 #define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
5911 #define F_EQL_EIEOS_CNTRST_DISABLE V_EQL_EIEOS_CNTRST_DISABLE(1U)
5913 #define S_EQL_PH2_PH3_DISABLE 9
5914 #define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
5915 #define F_EQL_PH2_PH3_DISABLE V_EQL_PH2_PH3_DISABLE(1U)
5917 #define S_DISABLE_SCRAMBLER 8
5918 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
5919 #define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U)
5921 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
5923 #define S_FULL_SWING 6
5924 #define M_FULL_SWING 0x3fU
5925 #define V_FULL_SWING(x) ((x) << S_FULL_SWING)
5926 #define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
5928 #define S_LOW_FREQUENCY 0
5929 #define M_LOW_FREQUENCY 0x3fU
5930 #define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
5931 #define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
5933 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
5935 #define S_POSTCURSOR 12
5936 #define M_POSTCURSOR 0x3fU
5937 #define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
5938 #define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
5941 #define M_CURSOR 0x3fU
5942 #define V_CURSOR(x) ((x) << S_CURSOR)
5943 #define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
5945 #define S_PRECURSOR 0
5946 #define M_PRECURSOR 0x3fU
5947 #define V_PRECURSOR(x) ((x) << S_PRECURSOR)
5948 #define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
5950 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
5953 #define M_INDEX 0xfU
5954 #define V_INDEX(x) ((x) << S_INDEX)
5955 #define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
5957 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
5959 #define S_LEGALITY_STATUS 0
5960 #define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
5961 #define F_LEGALITY_STATUS V_LEGALITY_STATUS(1U)
5963 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
5965 #define S_INCLUDE_INITIAL_FOM 24
5966 #define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
5967 #define F_INCLUDE_INITIAL_FOM V_INCLUDE_INITIAL_FOM(1U)
5969 #define S_PRESET_REQUEST_VECTOR 8
5970 #define M_PRESET_REQUEST_VECTOR 0xffffU
5971 #define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
5972 #define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
5974 #define S_PHASE23_2MS_TIMEOUT_DISABLE 5
5975 #define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
5976 #define F_PHASE23_2MS_TIMEOUT_DISABLE V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
5978 #define S_AFTER24MS 4
5979 #define V_AFTER24MS(x) ((x) << S_AFTER24MS)
5980 #define F_AFTER24MS V_AFTER24MS(1U)
5982 #define S_FEEDBACK_MODE 0
5983 #define M_FEEDBACK_MODE 0xfU
5984 #define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
5985 #define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
5987 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
5989 #define S_WINAPERTURE_CPLUS1 14
5990 #define M_WINAPERTURE_CPLUS1 0xfU
5991 #define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
5992 #define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
5994 #define S_WINAPERTURE_CMINS1 10
5995 #define M_WINAPERTURE_CMINS1 0xfU
5996 #define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
5997 #define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
5999 #define S_CONVERGENCE_WINDEPTH 5
6000 #define M_CONVERGENCE_WINDEPTH 0x1fU
6001 #define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
6002 #define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
6004 #define S_EQMASTERPHASE_MINTIME 0
6005 #define M_EQMASTERPHASE_MINTIME 0x1fU
6006 #define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
6007 #define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
6009 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
6011 #define S_PIPE_LOOPBACK_EN 0
6012 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
6013 #define F_PIPE_LOOPBACK_EN V_PIPE_LOOPBACK_EN(1U)
6015 #define S_T6_PIPE_LOOPBACK_EN 31
6016 #define V_T6_PIPE_LOOPBACK_EN(x) ((x) << S_T6_PIPE_LOOPBACK_EN)
6017 #define F_T6_PIPE_LOOPBACK_EN V_T6_PIPE_LOOPBACK_EN(1U)
6019 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
6021 #define S_READONLY_WRITEEN 0
6022 #define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
6023 #define F_READONLY_WRITEEN V_READONLY_WRITEEN(1U)
6025 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
6028 #define V_SMTD(x) ((x) << S_SMTD)
6029 #define F_SMTD V_SMTD(1U)
6032 #define V_SSTD(x) ((x) << S_SSTD)
6033 #define F_SSTD V_SSTD(1U)
6036 #define V_SWD0(x) ((x) << S_SWD0)
6037 #define F_SWD0 V_SWD0(1U)
6040 #define V_SWD1(x) ((x) << S_SWD1)
6041 #define F_SWD1 V_SWD1(1U)
6044 #define V_SWD2(x) ((x) << S_SWD2)
6045 #define F_SWD2 V_SWD2(1U)
6048 #define V_SWD3(x) ((x) << S_SWD3)
6049 #define F_SWD3 V_SWD3(1U)
6052 #define V_SWD4(x) ((x) << S_SWD4)
6053 #define F_SWD4 V_SWD4(1U)
6056 #define V_SWD5(x) ((x) << S_SWD5)
6057 #define F_SWD5 V_SWD5(1U)
6060 #define V_SWD6(x) ((x) << S_SWD6)
6061 #define F_SWD6 V_SWD6(1U)
6064 #define V_SWD7(x) ((x) << S_SWD7)
6065 #define F_SWD7 V_SWD7(1U)
6068 #define V_SWD8(x) ((x) << S_SWD8)
6069 #define F_SWD8 V_SWD8(1U)
6072 #define V_SRD0(x) ((x) << S_SRD0)
6073 #define F_SRD0 V_SRD0(1U)
6076 #define V_SRD1(x) ((x) << S_SRD1)
6077 #define F_SRD1 V_SRD1(1U)
6080 #define V_SRD2(x) ((x) << S_SRD2)
6081 #define F_SRD2 V_SRD2(1U)
6084 #define V_SRD3(x) ((x) << S_SRD3)
6085 #define F_SRD3 V_SRD3(1U)
6088 #define V_SRD4(x) ((x) << S_SRD4)
6089 #define F_SRD4 V_SRD4(1U)
6092 #define V_SRD5(x) ((x) << S_SRD5)
6093 #define F_SRD5 V_SRD5(1U)
6096 #define V_SRD6(x) ((x) << S_SRD6)
6097 #define F_SRD6 V_SRD6(1U)
6100 #define V_SRD7(x) ((x) << S_SRD7)
6101 #define F_SRD7 V_SRD7(1U)
6104 #define V_SRD8(x) ((x) << S_SRD8)
6105 #define F_SRD8 V_SRD8(1U)
6108 #define V_CRRE(x) ((x) << S_CRRE)
6109 #define F_CRRE V_CRRE(1U)
6113 #define V_CRMC(x) ((x) << S_CRMC)
6114 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
6116 #define A_PCIE_CORE_UTL_STATUS 0x5904
6119 #define V_USBP(x) ((x) << S_USBP)
6120 #define F_USBP V_USBP(1U)
6123 #define V_UPEP(x) ((x) << S_UPEP)
6124 #define F_UPEP V_UPEP(1U)
6127 #define V_RCEP(x) ((x) << S_RCEP)
6128 #define F_RCEP V_RCEP(1U)
6131 #define V_EPEP(x) ((x) << S_EPEP)
6132 #define F_EPEP V_EPEP(1U)
6135 #define V_USBS(x) ((x) << S_USBS)
6136 #define F_USBS V_USBS(1U)
6139 #define V_UPES(x) ((x) << S_UPES)
6140 #define F_UPES V_UPES(1U)
6143 #define V_RCES(x) ((x) << S_RCES)
6144 #define F_RCES V_RCES(1U)
6147 #define V_EPES(x) ((x) << S_EPES)
6148 #define F_EPES V_EPES(1U)
6150 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
6153 #define V_RNPP(x) ((x) << S_RNPP)
6154 #define F_RNPP V_RNPP(1U)
6157 #define V_RPCP(x) ((x) << S_RPCP)
6158 #define F_RPCP V_RPCP(1U)
6161 #define V_RCIP(x) ((x) << S_RCIP)
6162 #define F_RCIP V_RCIP(1U)
6165 #define V_RCCP(x) ((x) << S_RCCP)
6166 #define F_RCCP V_RCCP(1U)
6169 #define V_RFTP(x) ((x) << S_RFTP)
6170 #define F_RFTP V_RFTP(1U)
6173 #define V_PTRP(x) ((x) << S_PTRP)
6174 #define F_PTRP V_PTRP(1U)
6176 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
6179 #define V_RNPS(x) ((x) << S_RNPS)
6180 #define F_RNPS V_RNPS(1U)
6183 #define V_RPCS(x) ((x) << S_RPCS)
6184 #define F_RPCS V_RPCS(1U)
6187 #define V_RCIS(x) ((x) << S_RCIS)
6188 #define F_RCIS V_RCIS(1U)
6191 #define V_RCCS(x) ((x) << S_RCCS)
6192 #define F_RCCS V_RCCS(1U)
6195 #define V_RFTS(x) ((x) << S_RFTS)
6196 #define F_RFTS V_RFTS(1U)
6198 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
6201 #define V_RNPI(x) ((x) << S_RNPI)
6202 #define F_RNPI V_RNPI(1U)
6205 #define V_RPCI(x) ((x) << S_RPCI)
6206 #define F_RPCI V_RPCI(1U)
6209 #define V_RCII(x) ((x) << S_RCII)
6210 #define F_RCII V_RCII(1U)
6213 #define V_RCCI(x) ((x) << S_RCCI)
6214 #define F_RCCI V_RCCI(1U)
6217 #define V_RFTI(x) ((x) << S_RFTI)
6218 #define F_RFTI V_RFTI(1U)
6220 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
6224 #define V_SBRS(x) ((x) << S_SBRS)
6225 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
6229 #define V_OTWS(x) ((x) << S_OTWS)
6230 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
6232 #define A_PCIE_CORE_REVISION_ID 0x5924
6235 #define M_RVID 0xfffU
6236 #define V_RVID(x) ((x) << S_RVID)
6237 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
6240 #define M_BRVN 0xffU
6241 #define V_BRVN(x) ((x) << S_BRVN)
6242 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
6244 #define A_PCIE_T5_DMA_CFG 0x5940
6246 #define S_T5_DMA_MAXREQCNT 20
6247 #define M_T5_DMA_MAXREQCNT 0xffU
6248 #define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
6249 #define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
6251 #define S_T5_DMA_MAXRDREQSIZE 17
6252 #define M_T5_DMA_MAXRDREQSIZE 0x7U
6253 #define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
6254 #define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
6256 #define S_T5_DMA_MAXRSPCNT 8
6257 #define M_T5_DMA_MAXRSPCNT 0x1ffU
6258 #define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
6259 #define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
6261 #define S_SEQCHKDIS 7
6262 #define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
6263 #define F_SEQCHKDIS V_SEQCHKDIS(1U)
6266 #define M_MINTAG 0x7fU
6267 #define V_MINTAG(x) ((x) << S_MINTAG)
6268 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
6270 #define S_T6_T5_DMA_MAXREQCNT 20
6271 #define M_T6_T5_DMA_MAXREQCNT 0x7fU
6272 #define V_T6_T5_DMA_MAXREQCNT(x) ((x) << S_T6_T5_DMA_MAXREQCNT)
6273 #define G_T6_T5_DMA_MAXREQCNT(x) (((x) >> S_T6_T5_DMA_MAXREQCNT) & M_T6_T5_DMA_MAXREQCNT)
6275 #define S_T6_T5_DMA_MAXRSPCNT 9
6276 #define M_T6_T5_DMA_MAXRSPCNT 0xffU
6277 #define V_T6_T5_DMA_MAXRSPCNT(x) ((x) << S_T6_T5_DMA_MAXRSPCNT)
6278 #define G_T6_T5_DMA_MAXRSPCNT(x) (((x) >> S_T6_T5_DMA_MAXRSPCNT) & M_T6_T5_DMA_MAXRSPCNT)
6280 #define S_T6_SEQCHKDIS 8
6281 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
6282 #define F_T6_SEQCHKDIS V_T6_SEQCHKDIS(1U)
6284 #define S_T6_MINTAG 0
6285 #define M_T6_MINTAG 0xffU
6286 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6287 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6289 #define A_PCIE_T5_DMA_STAT 0x5944
6291 #define S_DMA_RESPCNT 20
6292 #define M_DMA_RESPCNT 0xfffU
6293 #define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
6294 #define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
6296 #define S_DMA_RDREQCNT 12
6297 #define M_DMA_RDREQCNT 0xffU
6298 #define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
6299 #define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
6301 #define S_DMA_WRREQCNT 0
6302 #define M_DMA_WRREQCNT 0x7ffU
6303 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
6304 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
6306 #define S_T6_DMA_RESPCNT 20
6307 #define M_T6_DMA_RESPCNT 0x3ffU
6308 #define V_T6_DMA_RESPCNT(x) ((x) << S_T6_DMA_RESPCNT)
6309 #define G_T6_DMA_RESPCNT(x) (((x) >> S_T6_DMA_RESPCNT) & M_T6_DMA_RESPCNT)
6311 #define S_T6_DMA_RDREQCNT 12
6312 #define M_T6_DMA_RDREQCNT 0x3fU
6313 #define V_T6_DMA_RDREQCNT(x) ((x) << S_T6_DMA_RDREQCNT)
6314 #define G_T6_DMA_RDREQCNT(x) (((x) >> S_T6_DMA_RDREQCNT) & M_T6_DMA_RDREQCNT)
6316 #define S_T6_DMA_WRREQCNT 0
6317 #define M_T6_DMA_WRREQCNT 0x1ffU
6318 #define V_T6_DMA_WRREQCNT(x) ((x) << S_T6_DMA_WRREQCNT)
6319 #define G_T6_DMA_WRREQCNT(x) (((x) >> S_T6_DMA_WRREQCNT) & M_T6_DMA_WRREQCNT)
6321 #define A_PCIE_T5_DMA_STAT2 0x5948
6323 #define S_COOKIECNT 24
6324 #define M_COOKIECNT 0xfU
6325 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
6326 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
6328 #define S_RDSEQNUMUPDCNT 20
6329 #define M_RDSEQNUMUPDCNT 0xfU
6330 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
6331 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
6333 #define S_SIREQCNT 16
6334 #define M_SIREQCNT 0xfU
6335 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
6336 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
6338 #define S_WREOPMATCHSOP 12
6339 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
6340 #define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U)
6342 #define S_WRSOPCNT 8
6343 #define M_WRSOPCNT 0xfU
6344 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
6345 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
6347 #define S_RDSOPCNT 0
6348 #define M_RDSOPCNT 0xffU
6349 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
6350 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
6352 #define A_PCIE_T5_DMA_STAT3 0x594c
6354 #define S_ATMREQSOPCNT 24
6355 #define M_ATMREQSOPCNT 0xffU
6356 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
6357 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
6359 #define S_ATMEOPMATCHSOP 17
6360 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
6361 #define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U)
6363 #define S_RSPEOPMATCHSOP 16
6364 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
6365 #define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U)
6367 #define S_RSPERRCNT 8
6368 #define M_RSPERRCNT 0xffU
6369 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
6370 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
6372 #define S_RSPSOPCNT 0
6373 #define M_RSPSOPCNT 0xffU
6374 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
6375 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
6377 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
6381 #define V_OP0H(x) ((x) << S_OP0H)
6382 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
6386 #define V_OP1H(x) ((x) << S_OP1H)
6387 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
6391 #define V_OP2H(x) ((x) << S_OP2H)
6392 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
6396 #define V_OP3H(x) ((x) << S_OP3H)
6397 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
6399 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
6402 #define M_OP0D 0x7fU
6403 #define V_OP0D(x) ((x) << S_OP0D)
6404 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
6407 #define M_OP1D 0x7fU
6408 #define V_OP1D(x) ((x) << S_OP1D)
6409 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
6412 #define M_OP2D 0x7fU
6413 #define V_OP2D(x) ((x) << S_OP2D)
6414 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
6417 #define M_OP3D 0x7fU
6418 #define V_OP3D(x) ((x) << S_OP3D)
6419 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
6421 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
6424 #define M_IP0H 0x3fU
6425 #define V_IP0H(x) ((x) << S_IP0H)
6426 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
6429 #define M_IP1H 0x3fU
6430 #define V_IP1H(x) ((x) << S_IP1H)
6431 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
6434 #define M_IP2H 0x3fU
6435 #define V_IP2H(x) ((x) << S_IP2H)
6436 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
6439 #define M_IP3H 0x3fU
6440 #define V_IP3H(x) ((x) << S_IP3H)
6441 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
6443 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
6446 #define M_IP0D 0xffU
6447 #define V_IP0D(x) ((x) << S_IP0D)
6448 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
6451 #define M_IP1D 0xffU
6452 #define V_IP1D(x) ((x) << S_IP1D)
6453 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
6456 #define M_IP2D 0xffU
6457 #define V_IP2D(x) ((x) << S_IP2D)
6458 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
6461 #define M_IP3D 0xffU
6462 #define V_IP3D(x) ((x) << S_IP3D)
6463 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
6465 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
6469 #define V_ON0H(x) ((x) << S_ON0H)
6470 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
6474 #define V_ON1H(x) ((x) << S_ON1H)
6475 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
6479 #define V_ON2H(x) ((x) << S_ON2H)
6480 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
6484 #define V_ON3H(x) ((x) << S_ON3H)
6485 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
6487 #define A_PCIE_T5_CMD_CFG 0x5980
6489 #define S_T5_CMD_MAXRDREQSIZE 17
6490 #define M_T5_CMD_MAXRDREQSIZE 0x7U
6491 #define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
6492 #define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
6494 #define S_T5_CMD_MAXRSPCNT 8
6495 #define M_T5_CMD_MAXRSPCNT 0xffU
6496 #define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
6497 #define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
6499 #define S_USECMDPOOL 7
6500 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
6501 #define F_USECMDPOOL V_USECMDPOOL(1U)
6503 #define S_T6_T5_CMD_MAXRSPCNT 9
6504 #define M_T6_T5_CMD_MAXRSPCNT 0x3fU
6505 #define V_T6_T5_CMD_MAXRSPCNT(x) ((x) << S_T6_T5_CMD_MAXRSPCNT)
6506 #define G_T6_T5_CMD_MAXRSPCNT(x) (((x) >> S_T6_T5_CMD_MAXRSPCNT) & M_T6_T5_CMD_MAXRSPCNT)
6508 #define S_T6_USECMDPOOL 8
6509 #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
6510 #define F_T6_USECMDPOOL V_T6_USECMDPOOL(1U)
6512 #define S_T6_MINTAG 0
6513 #define M_T6_MINTAG 0xffU
6514 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6515 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6517 #define A_PCIE_T5_CMD_STAT 0x5984
6519 #define S_T5_STAT_RSPCNT 20
6520 #define M_T5_STAT_RSPCNT 0x7ffU
6521 #define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
6522 #define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
6524 #define S_RDREQCNT 12
6525 #define M_RDREQCNT 0x1fU
6526 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
6527 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
6529 #define S_T6_T5_STAT_RSPCNT 20
6530 #define M_T6_T5_STAT_RSPCNT 0xffU
6531 #define V_T6_T5_STAT_RSPCNT(x) ((x) << S_T6_T5_STAT_RSPCNT)
6532 #define G_T6_T5_STAT_RSPCNT(x) (((x) >> S_T6_T5_STAT_RSPCNT) & M_T6_T5_STAT_RSPCNT)
6534 #define S_T6_RDREQCNT 12
6535 #define M_T6_RDREQCNT 0xfU
6536 #define V_T6_RDREQCNT(x) ((x) << S_T6_RDREQCNT)
6537 #define G_T6_RDREQCNT(x) (((x) >> S_T6_RDREQCNT) & M_T6_RDREQCNT)
6539 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
6542 #define M_IN0H 0x3fU
6543 #define V_IN0H(x) ((x) << S_IN0H)
6544 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
6547 #define M_IN1H 0x3fU
6548 #define V_IN1H(x) ((x) << S_IN1H)
6549 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
6552 #define M_IN2H 0x3fU
6553 #define V_IN2H(x) ((x) << S_IN2H)
6554 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
6557 #define M_IN3H 0x3fU
6558 #define V_IN3H(x) ((x) << S_IN3H)
6559 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
6561 #define A_PCIE_T5_CMD_STAT2 0x5988
6562 #define A_PCIE_T5_CMD_STAT3 0x598c
6563 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
6566 #define M_OC0T 0xffU
6567 #define V_OC0T(x) ((x) << S_OC0T)
6568 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
6571 #define M_OC1T 0xffU
6572 #define V_OC1T(x) ((x) << S_OC1T)
6573 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
6576 #define M_OC2T 0xffU
6577 #define V_OC2T(x) ((x) << S_OC2T)
6578 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
6581 #define M_OC3T 0xffU
6582 #define V_OC3T(x) ((x) << S_OC3T)
6583 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
6585 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
6588 #define M_IC0T 0x3fU
6589 #define V_IC0T(x) ((x) << S_IC0T)
6590 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
6593 #define M_IC1T 0x3fU
6594 #define V_IC1T(x) ((x) << S_IC1T)
6595 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
6598 #define M_IC2T 0x3fU
6599 #define V_IC2T(x) ((x) << S_IC2T)
6600 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
6603 #define M_IC3T 0x3fU
6604 #define V_IC3T(x) ((x) << S_IC3T)
6605 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
6607 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
6610 #define V_VRB0(x) ((x) << S_VRB0)
6611 #define F_VRB0 V_VRB0(1U)
6614 #define V_VRB1(x) ((x) << S_VRB1)
6615 #define F_VRB1 V_VRB1(1U)
6618 #define V_VRB2(x) ((x) << S_VRB2)
6619 #define F_VRB2 V_VRB2(1U)
6622 #define V_VRB3(x) ((x) << S_VRB3)
6623 #define F_VRB3 V_VRB3(1U)
6626 #define V_PSFE(x) ((x) << S_PSFE)
6627 #define F_PSFE V_PSFE(1U)
6630 #define V_RVDE(x) ((x) << S_RVDE)
6631 #define F_RVDE V_RVDE(1U)
6634 #define V_TXE0(x) ((x) << S_TXE0)
6635 #define F_TXE0 V_TXE0(1U)
6638 #define V_TXE1(x) ((x) << S_TXE1)
6639 #define F_TXE1 V_TXE1(1U)
6642 #define V_TXE2(x) ((x) << S_TXE2)
6643 #define F_TXE2 V_TXE2(1U)
6646 #define V_TXE3(x) ((x) << S_TXE3)
6647 #define F_TXE3 V_TXE3(1U)
6650 #define V_RPAM(x) ((x) << S_RPAM)
6651 #define F_RPAM V_RPAM(1U)
6655 #define V_RTOS(x) ((x) << S_RTOS)
6656 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
6658 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
6661 #define V_TPCP(x) ((x) << S_TPCP)
6662 #define F_TPCP V_TPCP(1U)
6665 #define V_TNPP(x) ((x) << S_TNPP)
6666 #define F_TNPP V_TNPP(1U)
6669 #define V_TFTP(x) ((x) << S_TFTP)
6670 #define F_TFTP V_TFTP(1U)
6673 #define V_TCAP(x) ((x) << S_TCAP)
6674 #define F_TCAP V_TCAP(1U)
6677 #define V_TCIP(x) ((x) << S_TCIP)
6678 #define F_TCIP V_TCIP(1U)
6681 #define V_RCAP(x) ((x) << S_RCAP)
6682 #define F_RCAP V_RCAP(1U)
6685 #define V_PLUP(x) ((x) << S_PLUP)
6686 #define F_PLUP V_PLUP(1U)
6689 #define V_PLDN(x) ((x) << S_PLDN)
6690 #define F_PLDN V_PLDN(1U)
6693 #define V_OTDD(x) ((x) << S_OTDD)
6694 #define F_OTDD V_OTDD(1U)
6697 #define V_GTRP(x) ((x) << S_GTRP)
6698 #define F_GTRP V_GTRP(1U)
6701 #define V_RDPE(x) ((x) << S_RDPE)
6702 #define F_RDPE V_RDPE(1U)
6705 #define V_TDCE(x) ((x) << S_TDCE)
6706 #define F_TDCE V_TDCE(1U)
6709 #define V_TDUE(x) ((x) << S_TDUE)
6710 #define F_TDUE V_TDUE(1U)
6712 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
6715 #define V_TPCS(x) ((x) << S_TPCS)
6716 #define F_TPCS V_TPCS(1U)
6719 #define V_TNPS(x) ((x) << S_TNPS)
6720 #define F_TNPS V_TNPS(1U)
6723 #define V_TFTS(x) ((x) << S_TFTS)
6724 #define F_TFTS V_TFTS(1U)
6727 #define V_TCAS(x) ((x) << S_TCAS)
6728 #define F_TCAS V_TCAS(1U)
6731 #define V_TCIS(x) ((x) << S_TCIS)
6732 #define F_TCIS V_TCIS(1U)
6735 #define V_RCAS(x) ((x) << S_RCAS)
6736 #define F_RCAS V_RCAS(1U)
6739 #define V_PLUS(x) ((x) << S_PLUS)
6740 #define F_PLUS V_PLUS(1U)
6743 #define V_PLDS(x) ((x) << S_PLDS)
6744 #define F_PLDS V_PLDS(1U)
6747 #define V_OTDS(x) ((x) << S_OTDS)
6748 #define F_OTDS V_OTDS(1U)
6751 #define V_RDPS(x) ((x) << S_RDPS)
6752 #define F_RDPS V_RDPS(1U)
6755 #define V_TDCS(x) ((x) << S_TDCS)
6756 #define F_TDCS V_TDCS(1U)
6759 #define V_TDUS(x) ((x) << S_TDUS)
6760 #define F_TDUS V_TDUS(1U)
6762 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
6765 #define V_TPCI(x) ((x) << S_TPCI)
6766 #define F_TPCI V_TPCI(1U)
6769 #define V_TNPI(x) ((x) << S_TNPI)
6770 #define F_TNPI V_TNPI(1U)
6773 #define V_TFTI(x) ((x) << S_TFTI)
6774 #define F_TFTI V_TFTI(1U)
6777 #define V_TCAI(x) ((x) << S_TCAI)
6778 #define F_TCAI V_TCAI(1U)
6781 #define V_TCII(x) ((x) << S_TCII)
6782 #define F_TCII V_TCII(1U)
6785 #define V_RCAI(x) ((x) << S_RCAI)
6786 #define F_RCAI V_RCAI(1U)
6789 #define V_PLUI(x) ((x) << S_PLUI)
6790 #define F_PLUI V_PLUI(1U)
6793 #define V_PLDI(x) ((x) << S_PLDI)
6794 #define F_PLDI V_PLDI(1U)
6797 #define V_OTDI(x) ((x) << S_OTDI)
6798 #define F_OTDI V_OTDI(1U)
6800 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
6803 #define V_RLCE(x) ((x) << S_RLCE)
6804 #define F_RLCE V_RLCE(1U)
6807 #define V_RLNE(x) ((x) << S_RLNE)
6808 #define F_RLNE V_RLNE(1U)
6811 #define V_RLFE(x) ((x) << S_RLFE)
6812 #define F_RLFE V_RLFE(1U)
6815 #define V_RCPE(x) ((x) << S_RCPE)
6816 #define F_RCPE V_RCPE(1U)
6819 #define V_RCTO(x) ((x) << S_RCTO)
6820 #define F_RCTO V_RCTO(1U)
6823 #define V_PINA(x) ((x) << S_PINA)
6824 #define F_PINA V_PINA(1U)
6827 #define V_PINB(x) ((x) << S_PINB)
6828 #define F_PINB V_PINB(1U)
6831 #define V_PINC(x) ((x) << S_PINC)
6832 #define F_PINC V_PINC(1U)
6835 #define V_PIND(x) ((x) << S_PIND)
6836 #define F_PIND V_PIND(1U)
6839 #define V_ALER(x) ((x) << S_ALER)
6840 #define F_ALER V_ALER(1U)
6843 #define V_CRSE(x) ((x) << S_CRSE)
6844 #define F_CRSE V_CRSE(1U)
6846 #define A_PCIE_T5_HMA_CFG 0x59b0
6848 #define S_HMA_MAXREQCNT 20
6849 #define M_HMA_MAXREQCNT 0x1fU
6850 #define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
6851 #define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
6853 #define S_T5_HMA_MAXRDREQSIZE 17
6854 #define M_T5_HMA_MAXRDREQSIZE 0x7U
6855 #define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
6856 #define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
6858 #define S_T5_HMA_MAXRSPCNT 8
6859 #define M_T5_HMA_MAXRSPCNT 0x1fU
6860 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
6861 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
6863 #define S_T6_HMA_MAXREQCNT 20
6864 #define M_T6_HMA_MAXREQCNT 0x7fU
6865 #define V_T6_HMA_MAXREQCNT(x) ((x) << S_T6_HMA_MAXREQCNT)
6866 #define G_T6_HMA_MAXREQCNT(x) (((x) >> S_T6_HMA_MAXREQCNT) & M_T6_HMA_MAXREQCNT)
6868 #define S_T6_T5_HMA_MAXRSPCNT 9
6869 #define M_T6_T5_HMA_MAXRSPCNT 0xffU
6870 #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
6871 #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
6873 #define S_T6_SEQCHKDIS 8
6874 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
6875 #define F_T6_SEQCHKDIS V_T6_SEQCHKDIS(1U)
6877 #define S_T6_MINTAG 0
6878 #define M_T6_MINTAG 0xffU
6879 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6880 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6882 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
6885 #define V_RLCS(x) ((x) << S_RLCS)
6886 #define F_RLCS V_RLCS(1U)
6889 #define V_RLNS(x) ((x) << S_RLNS)
6890 #define F_RLNS V_RLNS(1U)
6893 #define V_RLFS(x) ((x) << S_RLFS)
6894 #define F_RLFS V_RLFS(1U)
6897 #define V_RCPS(x) ((x) << S_RCPS)
6898 #define F_RCPS V_RCPS(1U)
6901 #define V_RCTS(x) ((x) << S_RCTS)
6902 #define F_RCTS V_RCTS(1U)
6905 #define V_PAAS(x) ((x) << S_PAAS)
6906 #define F_PAAS V_PAAS(1U)
6909 #define V_PABS(x) ((x) << S_PABS)
6910 #define F_PABS V_PABS(1U)
6913 #define V_PACS(x) ((x) << S_PACS)
6914 #define F_PACS V_PACS(1U)
6917 #define V_PADS(x) ((x) << S_PADS)
6918 #define F_PADS V_PADS(1U)
6921 #define V_ALES(x) ((x) << S_ALES)
6922 #define F_ALES V_ALES(1U)
6925 #define V_CRSS(x) ((x) << S_CRSS)
6926 #define F_CRSS V_CRSS(1U)
6928 #define A_PCIE_T5_HMA_STAT 0x59b4
6930 #define S_HMA_RESPCNT 20
6931 #define M_HMA_RESPCNT 0x1ffU
6932 #define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
6933 #define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
6935 #define S_HMA_RDREQCNT 12
6936 #define M_HMA_RDREQCNT 0x3fU
6937 #define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
6938 #define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
6940 #define S_HMA_WRREQCNT 0
6941 #define M_HMA_WRREQCNT 0x1ffU
6942 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
6943 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
6945 #define S_T6_HMA_RESPCNT 20
6946 #define M_T6_HMA_RESPCNT 0x3ffU
6947 #define V_T6_HMA_RESPCNT(x) ((x) << S_T6_HMA_RESPCNT)
6948 #define G_T6_HMA_RESPCNT(x) (((x) >> S_T6_HMA_RESPCNT) & M_T6_HMA_RESPCNT)
6950 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
6953 #define V_RLCI(x) ((x) << S_RLCI)
6954 #define F_RLCI V_RLCI(1U)
6957 #define V_RLNI(x) ((x) << S_RLNI)
6958 #define F_RLNI V_RLNI(1U)
6961 #define V_RLFI(x) ((x) << S_RLFI)
6962 #define F_RLFI V_RLFI(1U)
6965 #define V_RCPI(x) ((x) << S_RCPI)
6966 #define F_RCPI V_RCPI(1U)
6969 #define V_RCTI(x) ((x) << S_RCTI)
6970 #define F_RCTI V_RCTI(1U)
6973 #define V_PAAI(x) ((x) << S_PAAI)
6974 #define F_PAAI V_PAAI(1U)
6977 #define V_PABI(x) ((x) << S_PABI)
6978 #define F_PABI V_PABI(1U)
6981 #define V_PACI(x) ((x) << S_PACI)
6982 #define F_PACI V_PACI(1U)
6985 #define V_PADI(x) ((x) << S_PADI)
6986 #define F_PADI V_PADI(1U)
6989 #define V_ALEI(x) ((x) << S_ALEI)
6990 #define F_ALEI V_ALEI(1U)
6993 #define V_CRSI(x) ((x) << S_CRSI)
6994 #define F_CRSI V_CRSI(1U)
6996 #define A_PCIE_T5_HMA_STAT2 0x59b8
6997 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
7000 #define V_PTOM(x) ((x) << S_PTOM)
7001 #define F_PTOM V_PTOM(1U)
7004 #define V_ALEA(x) ((x) << S_ALEA)
7005 #define F_ALEA V_ALEA(1U)
7008 #define V_PMC0(x) ((x) << S_PMC0)
7009 #define F_PMC0 V_PMC0(1U)
7012 #define V_PMC1(x) ((x) << S_PMC1)
7013 #define F_PMC1 V_PMC1(1U)
7016 #define V_PMC2(x) ((x) << S_PMC2)
7017 #define F_PMC2 V_PMC2(1U)
7020 #define V_PMC3(x) ((x) << S_PMC3)
7021 #define F_PMC3 V_PMC3(1U)
7024 #define V_PMC4(x) ((x) << S_PMC4)
7025 #define F_PMC4 V_PMC4(1U)
7028 #define V_PMC5(x) ((x) << S_PMC5)
7029 #define F_PMC5 V_PMC5(1U)
7032 #define V_PMC6(x) ((x) << S_PMC6)
7033 #define F_PMC6 V_PMC6(1U)
7036 #define V_PMC7(x) ((x) << S_PMC7)
7037 #define F_PMC7 V_PMC7(1U)
7039 #define A_PCIE_T5_HMA_STAT3 0x59bc
7040 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
7043 #define V_PTOS(x) ((x) << S_PTOS)
7044 #define F_PTOS V_PTOS(1U)
7047 #define V_AENS(x) ((x) << S_AENS)
7048 #define F_AENS V_AENS(1U)
7051 #define V_PC0S(x) ((x) << S_PC0S)
7052 #define F_PC0S V_PC0S(1U)
7055 #define V_PC1S(x) ((x) << S_PC1S)
7056 #define F_PC1S V_PC1S(1U)
7059 #define V_PC2S(x) ((x) << S_PC2S)
7060 #define F_PC2S V_PC2S(1U)
7063 #define V_PC3S(x) ((x) << S_PC3S)
7064 #define F_PC3S V_PC3S(1U)
7067 #define V_PC4S(x) ((x) << S_PC4S)
7068 #define F_PC4S V_PC4S(1U)
7071 #define V_PC5S(x) ((x) << S_PC5S)
7072 #define F_PC5S V_PC5S(1U)
7075 #define V_PC6S(x) ((x) << S_PC6S)
7076 #define F_PC6S V_PC6S(1U)
7079 #define V_PC7S(x) ((x) << S_PC7S)
7080 #define F_PC7S V_PC7S(1U)
7083 #define V_PME0(x) ((x) << S_PME0)
7084 #define F_PME0 V_PME0(1U)
7087 #define V_PME1(x) ((x) << S_PME1)
7088 #define F_PME1 V_PME1(1U)
7091 #define V_PME2(x) ((x) << S_PME2)
7092 #define F_PME2 V_PME2(1U)
7095 #define V_PME3(x) ((x) << S_PME3)
7096 #define F_PME3 V_PME3(1U)
7099 #define V_PME4(x) ((x) << S_PME4)
7100 #define F_PME4 V_PME4(1U)
7103 #define V_PME5(x) ((x) << S_PME5)
7104 #define F_PME5 V_PME5(1U)
7107 #define V_PME6(x) ((x) << S_PME6)
7108 #define F_PME6 V_PME6(1U)
7111 #define V_PME7(x) ((x) << S_PME7)
7112 #define F_PME7 V_PME7(1U)
7114 #define A_PCIE_CGEN 0x59c0
7116 #define S_VPD_DYNAMIC_CGEN 26
7117 #define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
7118 #define F_VPD_DYNAMIC_CGEN V_VPD_DYNAMIC_CGEN(1U)
7120 #define S_MA_DYNAMIC_CGEN 25
7121 #define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
7122 #define F_MA_DYNAMIC_CGEN V_MA_DYNAMIC_CGEN(1U)
7124 #define S_TAGQ_DYNAMIC_CGEN 24
7125 #define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
7126 #define F_TAGQ_DYNAMIC_CGEN V_TAGQ_DYNAMIC_CGEN(1U)
7128 #define S_REQCTL_DYNAMIC_CGEN 23
7129 #define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
7130 #define F_REQCTL_DYNAMIC_CGEN V_REQCTL_DYNAMIC_CGEN(1U)
7132 #define S_RSPDATAPROC_DYNAMIC_CGEN 22
7133 #define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
7134 #define F_RSPDATAPROC_DYNAMIC_CGEN V_RSPDATAPROC_DYNAMIC_CGEN(1U)
7136 #define S_RSPRDQ_DYNAMIC_CGEN 21
7137 #define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
7138 #define F_RSPRDQ_DYNAMIC_CGEN V_RSPRDQ_DYNAMIC_CGEN(1U)
7140 #define S_RSPIPIF_DYNAMIC_CGEN 20
7141 #define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
7142 #define F_RSPIPIF_DYNAMIC_CGEN V_RSPIPIF_DYNAMIC_CGEN(1U)
7144 #define S_HMA_STATIC_CGEN 19
7145 #define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
7146 #define F_HMA_STATIC_CGEN V_HMA_STATIC_CGEN(1U)
7148 #define S_HMA_DYNAMIC_CGEN 18
7149 #define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
7150 #define F_HMA_DYNAMIC_CGEN V_HMA_DYNAMIC_CGEN(1U)
7152 #define S_CMD_STATIC_CGEN 16
7153 #define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
7154 #define F_CMD_STATIC_CGEN V_CMD_STATIC_CGEN(1U)
7156 #define S_CMD_DYNAMIC_CGEN 15
7157 #define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
7158 #define F_CMD_DYNAMIC_CGEN V_CMD_DYNAMIC_CGEN(1U)
7160 #define S_DMA_STATIC_CGEN 13
7161 #define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
7162 #define F_DMA_STATIC_CGEN V_DMA_STATIC_CGEN(1U)
7164 #define S_DMA_DYNAMIC_CGEN 12
7165 #define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
7166 #define F_DMA_DYNAMIC_CGEN V_DMA_DYNAMIC_CGEN(1U)
7168 #define S_VFID_SLEEPSTATUS 10
7169 #define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
7170 #define F_VFID_SLEEPSTATUS V_VFID_SLEEPSTATUS(1U)
7172 #define S_VC1_SLEEPSTATUS 9
7173 #define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
7174 #define F_VC1_SLEEPSTATUS V_VC1_SLEEPSTATUS(1U)
7176 #define S_STI_SLEEPSTATUS 8
7177 #define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
7178 #define F_STI_SLEEPSTATUS V_STI_SLEEPSTATUS(1U)
7180 #define S_VFID_SLEEPREQ 2
7181 #define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
7182 #define F_VFID_SLEEPREQ V_VFID_SLEEPREQ(1U)
7184 #define S_VC1_SLEEPREQ 1
7185 #define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
7186 #define F_VC1_SLEEPREQ V_VC1_SLEEPREQ(1U)
7188 #define S_STI_SLEEPREQ 0
7189 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
7190 #define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U)
7192 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
7195 #define V_PTOI(x) ((x) << S_PTOI)
7196 #define F_PTOI V_PTOI(1U)
7199 #define V_AENI(x) ((x) << S_AENI)
7200 #define F_AENI V_AENI(1U)
7203 #define V_PC0I(x) ((x) << S_PC0I)
7204 #define F_PC0I V_PC0I(1U)
7207 #define V_PC1I(x) ((x) << S_PC1I)
7208 #define F_PC1I V_PC1I(1U)
7211 #define V_PC2I(x) ((x) << S_PC2I)
7212 #define F_PC2I V_PC2I(1U)
7215 #define V_PC3I(x) ((x) << S_PC3I)
7216 #define F_PC3I V_PC3I(1U)
7219 #define V_PC4I(x) ((x) << S_PC4I)
7220 #define F_PC4I V_PC4I(1U)
7223 #define V_PC5I(x) ((x) << S_PC5I)
7224 #define F_PC5I V_PC5I(1U)
7227 #define V_PC6I(x) ((x) << S_PC6I)
7228 #define F_PC6I V_PC6I(1U)
7231 #define V_PC7I(x) ((x) << S_PC7I)
7232 #define F_PC7I V_PC7I(1U)
7234 #define A_PCIE_MA_RSP 0x59c4
7236 #define S_TIMERVALUE 8
7237 #define M_TIMERVALUE 0xffffffU
7238 #define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
7239 #define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
7241 #define S_MAREQTIMEREN 1
7242 #define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
7243 #define F_MAREQTIMEREN V_MAREQTIMEREN(1U)
7245 #define S_MARSPTIMEREN 0
7246 #define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
7247 #define F_MARSPTIMEREN V_MARSPTIMEREN(1U)
7249 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
7252 #define V_TOAK(x) ((x) << S_TOAK)
7253 #define F_TOAK V_TOAK(1U)
7256 #define V_L1RS(x) ((x) << S_L1RS)
7257 #define F_L1RS V_L1RS(1U)
7260 #define V_L23S(x) ((x) << S_L23S)
7261 #define F_L23S V_L23S(1U)
7264 #define V_AL1S(x) ((x) << S_AL1S)
7265 #define F_AL1S V_AL1S(1U)
7268 #define V_ALET(x) ((x) << S_ALET)
7269 #define F_ALET V_ALET(1U)
7271 #define A_PCIE_HPRD 0x59c8
7273 #define S_NPH_CREDITSAVAILVC0 19
7274 #define M_NPH_CREDITSAVAILVC0 0x3U
7275 #define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
7276 #define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
7278 #define S_NPD_CREDITSAVAILVC0 17
7279 #define M_NPD_CREDITSAVAILVC0 0x3U
7280 #define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
7281 #define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
7283 #define S_NPH_CREDITSAVAILVC1 15
7284 #define M_NPH_CREDITSAVAILVC1 0x3U
7285 #define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
7286 #define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
7288 #define S_NPD_CREDITSAVAILVC1 13
7289 #define M_NPD_CREDITSAVAILVC1 0x3U
7290 #define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
7291 #define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
7293 #define S_NPH_CREDITSREQUIRED 11
7294 #define M_NPH_CREDITSREQUIRED 0x3U
7295 #define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
7296 #define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
7298 #define S_NPD_CREDITSREQUIRED 9
7299 #define M_NPD_CREDITSREQUIRED 0x3U
7300 #define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
7301 #define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
7303 #define S_REQBURSTCOUNT 5
7304 #define M_REQBURSTCOUNT 0xfU
7305 #define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
7306 #define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
7308 #define S_REQBURSTFREQUENCY 1
7309 #define M_REQBURSTFREQUENCY 0xfU
7310 #define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
7311 #define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
7313 #define S_ENABLEVC1 0
7314 #define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
7315 #define F_ENABLEVC1 V_ENABLEVC1(1U)
7317 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
7321 #define V_CPM0(x) ((x) << S_CPM0)
7322 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
7326 #define V_CPM1(x) ((x) << S_CPM1)
7327 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
7331 #define V_CPM2(x) ((x) << S_CPM2)
7332 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
7336 #define V_CPM3(x) ((x) << S_CPM3)
7337 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
7341 #define V_CPM4(x) ((x) << S_CPM4)
7342 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
7346 #define V_CPM5(x) ((x) << S_CPM5)
7347 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
7351 #define V_CPM6(x) ((x) << S_CPM6)
7352 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
7356 #define V_CPM7(x) ((x) << S_CPM7)
7357 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
7361 #define V_OPM0(x) ((x) << S_OPM0)
7362 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
7366 #define V_OPM1(x) ((x) << S_OPM1)
7367 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
7371 #define V_OPM2(x) ((x) << S_OPM2)
7372 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
7376 #define V_OPM3(x) ((x) << S_OPM3)
7377 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
7381 #define V_OPM4(x) ((x) << S_OPM4)
7382 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
7386 #define V_OPM5(x) ((x) << S_OPM5)
7387 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
7391 #define V_OPM6(x) ((x) << S_OPM6)
7392 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
7396 #define V_OPM7(x) ((x) << S_OPM7)
7397 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
7399 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
7400 #define A_PCIE_PERR_GROUP 0x59d0
7402 #define S_MST_DATAPATHPERR 25
7403 #define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
7404 #define F_MST_DATAPATHPERR V_MST_DATAPATHPERR(1U)
7406 #define S_MST_RSPRDQPERR 24
7407 #define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
7408 #define F_MST_RSPRDQPERR V_MST_RSPRDQPERR(1U)
7410 #define S_IP_RXPERR 23
7411 #define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
7412 #define F_IP_RXPERR V_IP_RXPERR(1U)
7414 #define S_IP_BACKTXPERR 22
7415 #define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
7416 #define F_IP_BACKTXPERR V_IP_BACKTXPERR(1U)
7418 #define S_IP_FRONTTXPERR 21
7419 #define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
7420 #define F_IP_FRONTTXPERR V_IP_FRONTTXPERR(1U)
7422 #define S_TRGT1_FIDLKUPHDRPERR 20
7423 #define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
7424 #define F_TRGT1_FIDLKUPHDRPERR V_TRGT1_FIDLKUPHDRPERR(1U)
7426 #define S_TRGT1_ALINDDATAPERR 19
7427 #define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
7428 #define F_TRGT1_ALINDDATAPERR V_TRGT1_ALINDDATAPERR(1U)
7430 #define S_TRGT1_UNALINDATAPERR 18
7431 #define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
7432 #define F_TRGT1_UNALINDATAPERR V_TRGT1_UNALINDATAPERR(1U)
7434 #define S_TRGT1_REQDATAPERR 17
7435 #define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
7436 #define F_TRGT1_REQDATAPERR V_TRGT1_REQDATAPERR(1U)
7438 #define S_TRGT1_REQHDRPERR 16
7439 #define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
7440 #define F_TRGT1_REQHDRPERR V_TRGT1_REQHDRPERR(1U)
7442 #define S_IPRXDATA_VC1PERR 15
7443 #define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
7444 #define F_IPRXDATA_VC1PERR V_IPRXDATA_VC1PERR(1U)
7446 #define S_IPRXDATA_VC0PERR 14
7447 #define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
7448 #define F_IPRXDATA_VC0PERR V_IPRXDATA_VC0PERR(1U)
7450 #define S_IPRXHDR_VC1PERR 13
7451 #define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
7452 #define F_IPRXHDR_VC1PERR V_IPRXHDR_VC1PERR(1U)
7454 #define S_IPRXHDR_VC0PERR 12
7455 #define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
7456 #define F_IPRXHDR_VC0PERR V_IPRXHDR_VC0PERR(1U)
7458 #define S_MA_RSPDATAPERR 11
7459 #define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
7460 #define F_MA_RSPDATAPERR V_MA_RSPDATAPERR(1U)
7462 #define S_MA_CPLTAGQPERR 10
7463 #define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
7464 #define F_MA_CPLTAGQPERR V_MA_CPLTAGQPERR(1U)
7466 #define S_MA_REQTAGQPERR 9
7467 #define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
7468 #define F_MA_REQTAGQPERR V_MA_REQTAGQPERR(1U)
7470 #define S_PIOREQ_BAR2CTLPERR 8
7471 #define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
7472 #define F_PIOREQ_BAR2CTLPERR V_PIOREQ_BAR2CTLPERR(1U)
7474 #define S_PIOREQ_MEMCTLPERR 7
7475 #define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
7476 #define F_PIOREQ_MEMCTLPERR V_PIOREQ_MEMCTLPERR(1U)
7478 #define S_PIOREQ_PLMCTLPERR 6
7479 #define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
7480 #define F_PIOREQ_PLMCTLPERR V_PIOREQ_PLMCTLPERR(1U)
7482 #define S_PIOREQ_BAR2DATAPERR 5
7483 #define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
7484 #define F_PIOREQ_BAR2DATAPERR V_PIOREQ_BAR2DATAPERR(1U)
7486 #define S_PIOREQ_MEMDATAPERR 4
7487 #define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
7488 #define F_PIOREQ_MEMDATAPERR V_PIOREQ_MEMDATAPERR(1U)
7490 #define S_PIOREQ_PLMDATAPERR 3
7491 #define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
7492 #define F_PIOREQ_PLMDATAPERR V_PIOREQ_PLMDATAPERR(1U)
7494 #define S_PIOCPL_CTLPERR 2
7495 #define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
7496 #define F_PIOCPL_CTLPERR V_PIOCPL_CTLPERR(1U)
7498 #define S_PIOCPL_DATAPERR 1
7499 #define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
7500 #define F_PIOCPL_DATAPERR V_PIOCPL_DATAPERR(1U)
7502 #define S_PIOCPL_PLMRSPPERR 0
7503 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
7504 #define F_PIOCPL_PLMRSPPERR V_PIOCPL_PLMRSPPERR(1U)
7506 #define S_MA_RSPCTLPERR 26
7507 #define V_MA_RSPCTLPERR(x) ((x) << S_MA_RSPCTLPERR)
7508 #define F_MA_RSPCTLPERR V_MA_RSPCTLPERR(1U)
7510 #define S_T6_IPRXDATA_VC0PERR 15
7511 #define V_T6_IPRXDATA_VC0PERR(x) ((x) << S_T6_IPRXDATA_VC0PERR)
7512 #define F_T6_IPRXDATA_VC0PERR V_T6_IPRXDATA_VC0PERR(1U)
7514 #define S_T6_IPRXHDR_VC0PERR 14
7515 #define V_T6_IPRXHDR_VC0PERR(x) ((x) << S_T6_IPRXHDR_VC0PERR)
7516 #define F_T6_IPRXHDR_VC0PERR V_T6_IPRXHDR_VC0PERR(1U)
7518 #define S_PIOCPL_VDMTXCTLPERR 13
7519 #define V_PIOCPL_VDMTXCTLPERR(x) ((x) << S_PIOCPL_VDMTXCTLPERR)
7520 #define F_PIOCPL_VDMTXCTLPERR V_PIOCPL_VDMTXCTLPERR(1U)
7522 #define S_PIOCPL_VDMTXDATAPERR 12
7523 #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
7524 #define F_PIOCPL_VDMTXDATAPERR V_PIOCPL_VDMTXDATAPERR(1U)
7526 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
7527 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
7529 #define S_CPLSTATUSINTEN 12
7530 #define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
7531 #define F_CPLSTATUSINTEN V_CPLSTATUSINTEN(1U)
7533 #define S_REQTIMEOUTINTEN 11
7534 #define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
7535 #define F_REQTIMEOUTINTEN V_REQTIMEOUTINTEN(1U)
7537 #define S_DISABLEDINTEN 10
7538 #define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
7539 #define F_DISABLEDINTEN V_DISABLEDINTEN(1U)
7541 #define S_RSPDROPFLRINTEN 9
7542 #define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
7543 #define F_RSPDROPFLRINTEN V_RSPDROPFLRINTEN(1U)
7545 #define S_REQUNDERFLRINTEN 8
7546 #define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
7547 #define F_REQUNDERFLRINTEN V_REQUNDERFLRINTEN(1U)
7549 #define S_CPLSTATUSLOGEN 4
7550 #define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
7551 #define F_CPLSTATUSLOGEN V_CPLSTATUSLOGEN(1U)
7553 #define S_TIMEOUTLOGEN 3
7554 #define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
7555 #define F_TIMEOUTLOGEN V_TIMEOUTLOGEN(1U)
7557 #define S_DISABLEDLOGEN 2
7558 #define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
7559 #define F_DISABLEDLOGEN V_DISABLEDLOGEN(1U)
7561 #define S_RSPDROPFLRLOGEN 1
7562 #define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
7563 #define F_RSPDROPFLRLOGEN V_RSPDROPFLRLOGEN(1U)
7565 #define S_REQUNDERFLRLOGEN 0
7566 #define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
7567 #define F_REQUNDERFLRLOGEN V_REQUNDERFLRLOGEN(1U)
7569 #define A_PCIE_RSP_ERR_LOG1 0x59d8
7572 #define M_REQTAG 0x7fU
7573 #define V_REQTAG(x) ((x) << S_REQTAG)
7574 #define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
7578 #define V_CID(x) ((x) << S_CID)
7579 #define G_CID(x) (((x) >> S_CID) & M_CID)
7582 #define M_CHNUM 0x7U
7583 #define V_CHNUM(x) ((x) << S_CHNUM)
7584 #define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
7587 #define M_BYTELEN 0x1fffU
7588 #define V_BYTELEN(x) ((x) << S_BYTELEN)
7589 #define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
7592 #define M_REASON 0x7U
7593 #define V_REASON(x) ((x) << S_REASON)
7594 #define G_REASON(x) (((x) >> S_REASON) & M_REASON)
7596 #define S_CPLSTATUS 0
7597 #define M_CPLSTATUS 0x7U
7598 #define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
7599 #define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
7601 #define A_PCIE_RSP_ERR_LOG2 0x59dc
7603 #define S_LOGVALID 31
7604 #define V_LOGVALID(x) ((x) << S_LOGVALID)
7605 #define F_LOGVALID V_LOGVALID(1U)
7608 #define M_ADDR10B 0x3ffU
7609 #define V_ADDR10B(x) ((x) << S_ADDR10B)
7610 #define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
7613 #define M_REQVFID 0xffU
7614 #define V_REQVFID(x) ((x) << S_REQVFID)
7615 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
7617 #define S_T6_ADDR10B 9
7618 #define M_T6_ADDR10B 0x3ffU
7619 #define V_T6_ADDR10B(x) ((x) << S_T6_ADDR10B)
7620 #define G_T6_ADDR10B(x) (((x) >> S_T6_ADDR10B) & M_T6_ADDR10B)
7622 #define S_T6_REQVFID 0
7623 #define M_T6_REQVFID 0x1ffU
7624 #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
7625 #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
7627 #define A_PCIE_CHANGESET 0x59fc
7628 #define A_PCIE_REVISION 0x5a00
7629 #define A_PCIE_PDEBUG_INDEX 0x5a04
7631 #define S_PDEBUGSELH 16
7632 #define M_PDEBUGSELH 0x3fU
7633 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
7634 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
7636 #define S_PDEBUGSELL 0
7637 #define M_PDEBUGSELL 0x3fU
7638 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
7639 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
7641 #define S_T6_PDEBUGSELH 16
7642 #define M_T6_PDEBUGSELH 0x7fU
7643 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
7644 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
7646 #define S_T6_PDEBUGSELL 0
7647 #define M_T6_PDEBUGSELL 0x7fU
7648 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
7649 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
7651 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
7652 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
7653 #define A_PCIE_CDEBUG_INDEX 0x5a10
7655 #define S_CDEBUGSELH 16
7656 #define M_CDEBUGSELH 0xffU
7657 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
7658 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
7660 #define S_CDEBUGSELL 0
7661 #define M_CDEBUGSELL 0xffU
7662 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
7663 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
7665 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
7666 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
7667 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
7671 #define V_CH3(x) ((x) << S_CH3)
7672 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
7676 #define V_CH2(x) ((x) << S_CH2)
7677 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
7681 #define V_CH1(x) ((x) << S_CH1)
7682 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
7686 #define V_CH0(x) ((x) << S_CH0)
7687 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
7689 #define A_PCIE_DMAW_EOP_CNT 0x5a20
7690 #define A_PCIE_DMAR_REQ_CNT 0x5a24
7691 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
7692 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
7693 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
7694 #define A_PCIE_DMAI_CNT 0x5a34
7695 #define A_PCIE_CMDW_CNT 0x5a38
7697 #define S_CH1_EOP 24
7698 #define M_CH1_EOP 0xffU
7699 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
7700 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
7702 #define S_CH1_SOP 16
7703 #define M_CH1_SOP 0xffU
7704 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
7705 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
7708 #define M_CH0_EOP 0xffU
7709 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
7710 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
7713 #define M_CH0_SOP 0xffU
7714 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
7715 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
7717 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
7718 #define A_PCIE_CMDR_RSP_CNT 0x5a40
7719 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
7720 #define A_PCIE_HMA_REQ_CNT 0x5a48
7722 #define S_CH0_READ 16
7723 #define M_CH0_READ 0xffU
7724 #define V_CH0_READ(x) ((x) << S_CH0_READ)
7725 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
7727 #define S_CH0_WEOP 8
7728 #define M_CH0_WEOP 0xffU
7729 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
7730 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
7732 #define S_CH0_WSOP 0
7733 #define M_CH0_WSOP 0xffU
7734 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
7735 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
7737 #define A_PCIE_HMA_RSP_CNT 0x5a4c
7738 #define A_PCIE_DMA10_RSP_FREE 0x5a50
7740 #define S_CH1_RSP_FREE 16
7741 #define M_CH1_RSP_FREE 0xfffU
7742 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
7743 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
7745 #define S_CH0_RSP_FREE 0
7746 #define M_CH0_RSP_FREE 0xfffU
7747 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
7748 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
7750 #define A_PCIE_DMA32_RSP_FREE 0x5a54
7752 #define S_CH3_RSP_FREE 16
7753 #define M_CH3_RSP_FREE 0xfffU
7754 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
7755 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
7757 #define S_CH2_RSP_FREE 0
7758 #define M_CH2_RSP_FREE 0xfffU
7759 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
7760 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
7762 #define A_PCIE_CMD_RSP_FREE 0x5a58
7764 #define S_CMD_CH1_RSP_FREE 16
7765 #define M_CMD_CH1_RSP_FREE 0x7fU
7766 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
7767 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
7769 #define S_CMD_CH0_RSP_FREE 0
7770 #define M_CMD_CH0_RSP_FREE 0x7fU
7771 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
7772 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
7774 #define A_PCIE_HMA_RSP_FREE 0x5a5c
7775 #define A_PCIE_BUS_MST_STAT_0 0x5a60
7776 #define A_PCIE_BUS_MST_STAT_1 0x5a64
7777 #define A_PCIE_BUS_MST_STAT_2 0x5a68
7778 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
7779 #define A_PCIE_BUS_MST_STAT_4 0x5a70
7781 #define S_BUSMST_135_128 0
7782 #define M_BUSMST_135_128 0xffU
7783 #define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
7784 #define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
7786 #define A_PCIE_BUS_MST_STAT_5 0x5a74
7787 #define A_PCIE_BUS_MST_STAT_6 0x5a78
7788 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
7789 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
7790 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
7791 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
7792 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
7793 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
7795 #define S_RSPERR_135_128 0
7796 #define M_RSPERR_135_128 0xffU
7797 #define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
7798 #define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
7800 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
7801 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
7803 #define S_DBI_TIMER 0
7804 #define M_DBI_TIMER 0xffffU
7805 #define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
7806 #define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
7808 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
7809 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
7810 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
7811 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
7814 #define M_SOURCE 0x3U
7815 #define V_SOURCE(x) ((x) << S_SOURCE)
7816 #define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
7818 #define S_DBI_WRITE 12
7819 #define M_DBI_WRITE 0xfU
7820 #define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
7821 #define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
7823 #define S_DBI_CS2 11
7824 #define V_DBI_CS2(x) ((x) << S_DBI_CS2)
7825 #define F_DBI_CS2 V_DBI_CS2(1U)
7828 #define M_DBI_PF 0x7U
7829 #define V_DBI_PF(x) ((x) << S_DBI_PF)
7830 #define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
7832 #define S_PL_TOVFVLD 7
7833 #define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
7834 #define F_PL_TOVFVLD V_PL_TOVFVLD(1U)
7837 #define M_PL_TOVF 0x7fU
7838 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
7839 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
7841 #define S_T6_SOURCE 17
7842 #define M_T6_SOURCE 0x3U
7843 #define V_T6_SOURCE(x) ((x) << S_T6_SOURCE)
7844 #define G_T6_SOURCE(x) (((x) >> S_T6_SOURCE) & M_T6_SOURCE)
7846 #define S_T6_DBI_WRITE 13
7847 #define M_T6_DBI_WRITE 0xfU
7848 #define V_T6_DBI_WRITE(x) ((x) << S_T6_DBI_WRITE)
7849 #define G_T6_DBI_WRITE(x) (((x) >> S_T6_DBI_WRITE) & M_T6_DBI_WRITE)
7851 #define S_T6_DBI_CS2 12
7852 #define V_T6_DBI_CS2(x) ((x) << S_T6_DBI_CS2)
7853 #define F_T6_DBI_CS2 V_T6_DBI_CS2(1U)
7855 #define S_T6_DBI_PF 9
7856 #define M_T6_DBI_PF 0x7U
7857 #define V_T6_DBI_PF(x) ((x) << S_T6_DBI_PF)
7858 #define G_T6_DBI_PF(x) (((x) >> S_T6_DBI_PF) & M_T6_DBI_PF)
7860 #define S_T6_PL_TOVFVLD 8
7861 #define V_T6_PL_TOVFVLD(x) ((x) << S_T6_PL_TOVFVLD)
7862 #define F_T6_PL_TOVFVLD V_T6_PL_TOVFVLD(1U)
7864 #define S_T6_PL_TOVF 0
7865 #define M_T6_PL_TOVF 0xffU
7866 #define V_T6_PL_TOVF(x) ((x) << S_T6_PL_TOVF)
7867 #define G_T6_PL_TOVF(x) (((x) >> S_T6_PL_TOVF) & M_T6_PL_TOVF)
7869 #define A_PCIE_MSI_EN_0 0x5aa0
7870 #define A_PCIE_MSI_EN_1 0x5aa4
7871 #define A_PCIE_MSI_EN_2 0x5aa8
7872 #define A_PCIE_MSI_EN_3 0x5aac
7873 #define A_PCIE_MSI_EN_4 0x5ab0
7874 #define A_PCIE_MSI_EN_5 0x5ab4
7875 #define A_PCIE_MSI_EN_6 0x5ab8
7876 #define A_PCIE_MSI_EN_7 0x5abc
7877 #define A_PCIE_MSIX_EN_0 0x5ac0
7878 #define A_PCIE_MSIX_EN_1 0x5ac4
7879 #define A_PCIE_MSIX_EN_2 0x5ac8
7880 #define A_PCIE_MSIX_EN_3 0x5acc
7881 #define A_PCIE_MSIX_EN_4 0x5ad0
7882 #define A_PCIE_MSIX_EN_5 0x5ad4
7883 #define A_PCIE_MSIX_EN_6 0x5ad8
7884 #define A_PCIE_MSIX_EN_7 0x5adc
7885 #define A_PCIE_DMA_BUF_CTL 0x5ae0
7887 #define S_BUFRDCNT 18
7888 #define M_BUFRDCNT 0x3fffU
7889 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
7890 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
7892 #define S_BUFWRCNT 9
7893 #define M_BUFWRCNT 0x1ffU
7894 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
7895 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
7897 #define S_MAXBUFWRREQ 0
7898 #define M_MAXBUFWRREQ 0x1ffU
7899 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
7900 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
7902 #define A_PCIE_PB_CTL 0x5b94
7905 #define M_PB_SEL 0xffU
7906 #define V_PB_SEL(x) ((x) << S_PB_SEL)
7907 #define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
7909 #define S_PB_SELREG 8
7910 #define M_PB_SELREG 0xffU
7911 #define V_PB_SELREG(x) ((x) << S_PB_SELREG)
7912 #define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
7915 #define M_PB_FUNC 0x7U
7916 #define V_PB_FUNC(x) ((x) << S_PB_FUNC)
7917 #define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
7919 #define A_PCIE_PB_DATA 0x5b98
7920 #define A_PCIE_CUR_LINK 0x5b9c
7922 #define S_CFGINITCOEFFDONESEEN 22
7923 #define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
7924 #define F_CFGINITCOEFFDONESEEN V_CFGINITCOEFFDONESEEN(1U)
7926 #define S_CFGINITCOEFFDONE 21
7927 #define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
7928 #define F_CFGINITCOEFFDONE V_CFGINITCOEFFDONE(1U)
7930 #define S_XMLH_LINK_UP 20
7931 #define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
7932 #define F_XMLH_LINK_UP V_XMLH_LINK_UP(1U)
7934 #define S_PM_LINKST_IN_L0S 19
7935 #define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
7936 #define F_PM_LINKST_IN_L0S V_PM_LINKST_IN_L0S(1U)
7938 #define S_PM_LINKST_IN_L1 18
7939 #define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
7940 #define F_PM_LINKST_IN_L1 V_PM_LINKST_IN_L1(1U)
7942 #define S_PM_LINKST_IN_L2 17
7943 #define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
7944 #define F_PM_LINKST_IN_L2 V_PM_LINKST_IN_L2(1U)
7946 #define S_PM_LINKST_L2_EXIT 16
7947 #define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
7948 #define F_PM_LINKST_L2_EXIT V_PM_LINKST_L2_EXIT(1U)
7950 #define S_XMLH_IN_RL0S 15
7951 #define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
7952 #define F_XMLH_IN_RL0S V_XMLH_IN_RL0S(1U)
7954 #define S_XMLH_LTSSM_STATE_RCVRY_EQ 14
7955 #define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
7956 #define F_XMLH_LTSSM_STATE_RCVRY_EQ V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
7958 #define S_NEGOTIATEDWIDTH 8
7959 #define M_NEGOTIATEDWIDTH 0x3fU
7960 #define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
7961 #define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
7963 #define S_ACTIVELANES 0
7964 #define M_ACTIVELANES 0xffU
7965 #define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
7966 #define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
7968 #define A_PCIE_PHY_REQRXPWR 0x5ba0
7970 #define S_LNH_RXSTATEDONE 31
7971 #define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
7972 #define F_LNH_RXSTATEDONE V_LNH_RXSTATEDONE(1U)
7974 #define S_LNH_RXSTATEREQ 30
7975 #define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
7976 #define F_LNH_RXSTATEREQ V_LNH_RXSTATEREQ(1U)
7978 #define S_LNH_RXPWRSTATE 28
7979 #define M_LNH_RXPWRSTATE 0x3U
7980 #define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
7981 #define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
7983 #define S_LNG_RXSTATEDONE 27
7984 #define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
7985 #define F_LNG_RXSTATEDONE V_LNG_RXSTATEDONE(1U)
7987 #define S_LNG_RXSTATEREQ 26
7988 #define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
7989 #define F_LNG_RXSTATEREQ V_LNG_RXSTATEREQ(1U)
7991 #define S_LNG_RXPWRSTATE 24
7992 #define M_LNG_RXPWRSTATE 0x3U
7993 #define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
7994 #define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
7996 #define S_LNF_RXSTATEDONE 23
7997 #define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
7998 #define F_LNF_RXSTATEDONE V_LNF_RXSTATEDONE(1U)
8000 #define S_LNF_RXSTATEREQ 22
8001 #define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
8002 #define F_LNF_RXSTATEREQ V_LNF_RXSTATEREQ(1U)
8004 #define S_LNF_RXPWRSTATE 20
8005 #define M_LNF_RXPWRSTATE 0x3U
8006 #define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
8007 #define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
8009 #define S_LNE_RXSTATEDONE 19
8010 #define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
8011 #define F_LNE_RXSTATEDONE V_LNE_RXSTATEDONE(1U)
8013 #define S_LNE_RXSTATEREQ 18
8014 #define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
8015 #define F_LNE_RXSTATEREQ V_LNE_RXSTATEREQ(1U)
8017 #define S_LNE_RXPWRSTATE 16
8018 #define M_LNE_RXPWRSTATE 0x3U
8019 #define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
8020 #define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
8022 #define S_LND_RXSTATEDONE 15
8023 #define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
8024 #define F_LND_RXSTATEDONE V_LND_RXSTATEDONE(1U)
8026 #define S_LND_RXSTATEREQ 14
8027 #define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
8028 #define F_LND_RXSTATEREQ V_LND_RXSTATEREQ(1U)
8030 #define S_LND_RXPWRSTATE 12
8031 #define M_LND_RXPWRSTATE 0x3U
8032 #define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
8033 #define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
8035 #define S_LNC_RXSTATEDONE 11
8036 #define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
8037 #define F_LNC_RXSTATEDONE V_LNC_RXSTATEDONE(1U)
8039 #define S_LNC_RXSTATEREQ 10
8040 #define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
8041 #define F_LNC_RXSTATEREQ V_LNC_RXSTATEREQ(1U)
8043 #define S_LNC_RXPWRSTATE 8
8044 #define M_LNC_RXPWRSTATE 0x3U
8045 #define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
8046 #define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
8048 #define S_LNB_RXSTATEDONE 7
8049 #define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
8050 #define F_LNB_RXSTATEDONE V_LNB_RXSTATEDONE(1U)
8052 #define S_LNB_RXSTATEREQ 6
8053 #define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
8054 #define F_LNB_RXSTATEREQ V_LNB_RXSTATEREQ(1U)
8056 #define S_LNB_RXPWRSTATE 4
8057 #define M_LNB_RXPWRSTATE 0x3U
8058 #define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
8059 #define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
8061 #define S_LNA_RXSTATEDONE 3
8062 #define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
8063 #define F_LNA_RXSTATEDONE V_LNA_RXSTATEDONE(1U)
8065 #define S_LNA_RXSTATEREQ 2
8066 #define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
8067 #define F_LNA_RXSTATEREQ V_LNA_RXSTATEREQ(1U)
8069 #define S_LNA_RXPWRSTATE 0
8070 #define M_LNA_RXPWRSTATE 0x3U
8071 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
8072 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
8074 #define S_REQ_LNH_RXSTATEDONE 31
8075 #define V_REQ_LNH_RXSTATEDONE(x) ((x) << S_REQ_LNH_RXSTATEDONE)
8076 #define F_REQ_LNH_RXSTATEDONE V_REQ_LNH_RXSTATEDONE(1U)
8078 #define S_REQ_LNH_RXSTATEREQ 30
8079 #define V_REQ_LNH_RXSTATEREQ(x) ((x) << S_REQ_LNH_RXSTATEREQ)
8080 #define F_REQ_LNH_RXSTATEREQ V_REQ_LNH_RXSTATEREQ(1U)
8082 #define S_REQ_LNH_RXPWRSTATE 28
8083 #define M_REQ_LNH_RXPWRSTATE 0x3U
8084 #define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE)
8085 #define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE)
8087 #define S_REQ_LNG_RXSTATEDONE 27
8088 #define V_REQ_LNG_RXSTATEDONE(x) ((x) << S_REQ_LNG_RXSTATEDONE)
8089 #define F_REQ_LNG_RXSTATEDONE V_REQ_LNG_RXSTATEDONE(1U)
8091 #define S_REQ_LNG_RXSTATEREQ 26
8092 #define V_REQ_LNG_RXSTATEREQ(x) ((x) << S_REQ_LNG_RXSTATEREQ)
8093 #define F_REQ_LNG_RXSTATEREQ V_REQ_LNG_RXSTATEREQ(1U)
8095 #define S_REQ_LNG_RXPWRSTATE 24
8096 #define M_REQ_LNG_RXPWRSTATE 0x3U
8097 #define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE)
8098 #define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE)
8100 #define S_REQ_LNF_RXSTATEDONE 23
8101 #define V_REQ_LNF_RXSTATEDONE(x) ((x) << S_REQ_LNF_RXSTATEDONE)
8102 #define F_REQ_LNF_RXSTATEDONE V_REQ_LNF_RXSTATEDONE(1U)
8104 #define S_REQ_LNF_RXSTATEREQ 22
8105 #define V_REQ_LNF_RXSTATEREQ(x) ((x) << S_REQ_LNF_RXSTATEREQ)
8106 #define F_REQ_LNF_RXSTATEREQ V_REQ_LNF_RXSTATEREQ(1U)
8108 #define S_REQ_LNF_RXPWRSTATE 20
8109 #define M_REQ_LNF_RXPWRSTATE 0x3U
8110 #define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE)
8111 #define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE)
8113 #define S_REQ_LNE_RXSTATEDONE 19
8114 #define V_REQ_LNE_RXSTATEDONE(x) ((x) << S_REQ_LNE_RXSTATEDONE)
8115 #define F_REQ_LNE_RXSTATEDONE V_REQ_LNE_RXSTATEDONE(1U)
8117 #define S_REQ_LNE_RXSTATEREQ 18
8118 #define V_REQ_LNE_RXSTATEREQ(x) ((x) << S_REQ_LNE_RXSTATEREQ)
8119 #define F_REQ_LNE_RXSTATEREQ V_REQ_LNE_RXSTATEREQ(1U)
8121 #define S_REQ_LNE_RXPWRSTATE 16
8122 #define M_REQ_LNE_RXPWRSTATE 0x3U
8123 #define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE)
8124 #define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE)
8126 #define S_REQ_LND_RXSTATEDONE 15
8127 #define V_REQ_LND_RXSTATEDONE(x) ((x) << S_REQ_LND_RXSTATEDONE)
8128 #define F_REQ_LND_RXSTATEDONE V_REQ_LND_RXSTATEDONE(1U)
8130 #define S_REQ_LND_RXSTATEREQ 14
8131 #define V_REQ_LND_RXSTATEREQ(x) ((x) << S_REQ_LND_RXSTATEREQ)
8132 #define F_REQ_LND_RXSTATEREQ V_REQ_LND_RXSTATEREQ(1U)
8134 #define S_REQ_LND_RXPWRSTATE 12
8135 #define M_REQ_LND_RXPWRSTATE 0x3U
8136 #define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE)
8137 #define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE)
8139 #define S_REQ_LNC_RXSTATEDONE 11
8140 #define V_REQ_LNC_RXSTATEDONE(x) ((x) << S_REQ_LNC_RXSTATEDONE)
8141 #define F_REQ_LNC_RXSTATEDONE V_REQ_LNC_RXSTATEDONE(1U)
8143 #define S_REQ_LNC_RXSTATEREQ 10
8144 #define V_REQ_LNC_RXSTATEREQ(x) ((x) << S_REQ_LNC_RXSTATEREQ)
8145 #define F_REQ_LNC_RXSTATEREQ V_REQ_LNC_RXSTATEREQ(1U)
8147 #define S_REQ_LNC_RXPWRSTATE 8
8148 #define M_REQ_LNC_RXPWRSTATE 0x3U
8149 #define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE)
8150 #define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE)
8152 #define S_REQ_LNB_RXSTATEDONE 7
8153 #define V_REQ_LNB_RXSTATEDONE(x) ((x) << S_REQ_LNB_RXSTATEDONE)
8154 #define F_REQ_LNB_RXSTATEDONE V_REQ_LNB_RXSTATEDONE(1U)
8156 #define S_REQ_LNB_RXSTATEREQ 6
8157 #define V_REQ_LNB_RXSTATEREQ(x) ((x) << S_REQ_LNB_RXSTATEREQ)
8158 #define F_REQ_LNB_RXSTATEREQ V_REQ_LNB_RXSTATEREQ(1U)
8160 #define S_REQ_LNB_RXPWRSTATE 4
8161 #define M_REQ_LNB_RXPWRSTATE 0x3U
8162 #define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE)
8163 #define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE)
8165 #define S_REQ_LNA_RXSTATEDONE 3
8166 #define V_REQ_LNA_RXSTATEDONE(x) ((x) << S_REQ_LNA_RXSTATEDONE)
8167 #define F_REQ_LNA_RXSTATEDONE V_REQ_LNA_RXSTATEDONE(1U)
8169 #define S_REQ_LNA_RXSTATEREQ 2
8170 #define V_REQ_LNA_RXSTATEREQ(x) ((x) << S_REQ_LNA_RXSTATEREQ)
8171 #define F_REQ_LNA_RXSTATEREQ V_REQ_LNA_RXSTATEREQ(1U)
8173 #define S_REQ_LNA_RXPWRSTATE 0
8174 #define M_REQ_LNA_RXPWRSTATE 0x3U
8175 #define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE)
8176 #define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE)
8178 #define A_PCIE_PHY_CURRXPWR 0x5ba4
8180 #define S_T5_LNH_RXPWRSTATE 28
8181 #define M_T5_LNH_RXPWRSTATE 0x7U
8182 #define V_T5_LNH_RXPWRSTATE(x) ((x) << S_T5_LNH_RXPWRSTATE)
8183 #define G_T5_LNH_RXPWRSTATE(x) (((x) >> S_T5_LNH_RXPWRSTATE) & M_T5_LNH_RXPWRSTATE)
8185 #define S_T5_LNG_RXPWRSTATE 24
8186 #define M_T5_LNG_RXPWRSTATE 0x7U
8187 #define V_T5_LNG_RXPWRSTATE(x) ((x) << S_T5_LNG_RXPWRSTATE)
8188 #define G_T5_LNG_RXPWRSTATE(x) (((x) >> S_T5_LNG_RXPWRSTATE) & M_T5_LNG_RXPWRSTATE)
8190 #define S_T5_LNF_RXPWRSTATE 20
8191 #define M_T5_LNF_RXPWRSTATE 0x7U
8192 #define V_T5_LNF_RXPWRSTATE(x) ((x) << S_T5_LNF_RXPWRSTATE)
8193 #define G_T5_LNF_RXPWRSTATE(x) (((x) >> S_T5_LNF_RXPWRSTATE) & M_T5_LNF_RXPWRSTATE)
8195 #define S_T5_LNE_RXPWRSTATE 16
8196 #define M_T5_LNE_RXPWRSTATE 0x7U
8197 #define V_T5_LNE_RXPWRSTATE(x) ((x) << S_T5_LNE_RXPWRSTATE)
8198 #define G_T5_LNE_RXPWRSTATE(x) (((x) >> S_T5_LNE_RXPWRSTATE) & M_T5_LNE_RXPWRSTATE)
8200 #define S_T5_LND_RXPWRSTATE 12
8201 #define M_T5_LND_RXPWRSTATE 0x7U
8202 #define V_T5_LND_RXPWRSTATE(x) ((x) << S_T5_LND_RXPWRSTATE)
8203 #define G_T5_LND_RXPWRSTATE(x) (((x) >> S_T5_LND_RXPWRSTATE) & M_T5_LND_RXPWRSTATE)
8205 #define S_T5_LNC_RXPWRSTATE 8
8206 #define M_T5_LNC_RXPWRSTATE 0x7U
8207 #define V_T5_LNC_RXPWRSTATE(x) ((x) << S_T5_LNC_RXPWRSTATE)
8208 #define G_T5_LNC_RXPWRSTATE(x) (((x) >> S_T5_LNC_RXPWRSTATE) & M_T5_LNC_RXPWRSTATE)
8210 #define S_T5_LNB_RXPWRSTATE 4
8211 #define M_T5_LNB_RXPWRSTATE 0x7U
8212 #define V_T5_LNB_RXPWRSTATE(x) ((x) << S_T5_LNB_RXPWRSTATE)
8213 #define G_T5_LNB_RXPWRSTATE(x) (((x) >> S_T5_LNB_RXPWRSTATE) & M_T5_LNB_RXPWRSTATE)
8215 #define S_T5_LNA_RXPWRSTATE 0
8216 #define M_T5_LNA_RXPWRSTATE 0x7U
8217 #define V_T5_LNA_RXPWRSTATE(x) ((x) << S_T5_LNA_RXPWRSTATE)
8218 #define G_T5_LNA_RXPWRSTATE(x) (((x) >> S_T5_LNA_RXPWRSTATE) & M_T5_LNA_RXPWRSTATE)
8220 #define S_CUR_LNH_RXPWRSTATE 28
8221 #define M_CUR_LNH_RXPWRSTATE 0x7U
8222 #define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE)
8223 #define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE)
8225 #define S_CUR_LNG_RXPWRSTATE 24
8226 #define M_CUR_LNG_RXPWRSTATE 0x7U
8227 #define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE)
8228 #define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE)
8230 #define S_CUR_LNF_RXPWRSTATE 20
8231 #define M_CUR_LNF_RXPWRSTATE 0x7U
8232 #define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE)
8233 #define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE)
8235 #define S_CUR_LNE_RXPWRSTATE 16
8236 #define M_CUR_LNE_RXPWRSTATE 0x7U
8237 #define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE)
8238 #define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE)
8240 #define S_CUR_LND_RXPWRSTATE 12
8241 #define M_CUR_LND_RXPWRSTATE 0x7U
8242 #define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE)
8243 #define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE)
8245 #define S_CUR_LNC_RXPWRSTATE 8
8246 #define M_CUR_LNC_RXPWRSTATE 0x7U
8247 #define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE)
8248 #define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE)
8250 #define S_CUR_LNB_RXPWRSTATE 4
8251 #define M_CUR_LNB_RXPWRSTATE 0x7U
8252 #define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE)
8253 #define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE)
8255 #define S_CUR_LNA_RXPWRSTATE 0
8256 #define M_CUR_LNA_RXPWRSTATE 0x7U
8257 #define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE)
8258 #define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE)
8260 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
8262 #define S_LND_STAT 28
8263 #define M_LND_STAT 0x7U
8264 #define V_LND_STAT(x) ((x) << S_LND_STAT)
8265 #define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
8267 #define S_LND_CMD 24
8268 #define M_LND_CMD 0x7U
8269 #define V_LND_CMD(x) ((x) << S_LND_CMD)
8270 #define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
8272 #define S_LNC_STAT 20
8273 #define M_LNC_STAT 0x7U
8274 #define V_LNC_STAT(x) ((x) << S_LNC_STAT)
8275 #define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
8277 #define S_LNC_CMD 16
8278 #define M_LNC_CMD 0x7U
8279 #define V_LNC_CMD(x) ((x) << S_LNC_CMD)
8280 #define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
8282 #define S_LNB_STAT 12
8283 #define M_LNB_STAT 0x7U
8284 #define V_LNB_STAT(x) ((x) << S_LNB_STAT)
8285 #define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
8288 #define M_LNB_CMD 0x7U
8289 #define V_LNB_CMD(x) ((x) << S_LNB_CMD)
8290 #define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
8292 #define S_LNA_STAT 4
8293 #define M_LNA_STAT 0x7U
8294 #define V_LNA_STAT(x) ((x) << S_LNA_STAT)
8295 #define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
8298 #define M_LNA_CMD 0x7U
8299 #define V_LNA_CMD(x) ((x) << S_LNA_CMD)
8300 #define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
8302 #define A_PCIE_PHY_GEN3_AE1 0x5bac
8304 #define S_LNH_STAT 28
8305 #define M_LNH_STAT 0x7U
8306 #define V_LNH_STAT(x) ((x) << S_LNH_STAT)
8307 #define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
8309 #define S_LNH_CMD 24
8310 #define M_LNH_CMD 0x7U
8311 #define V_LNH_CMD(x) ((x) << S_LNH_CMD)
8312 #define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
8314 #define S_LNG_STAT 20
8315 #define M_LNG_STAT 0x7U
8316 #define V_LNG_STAT(x) ((x) << S_LNG_STAT)
8317 #define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
8319 #define S_LNG_CMD 16
8320 #define M_LNG_CMD 0x7U
8321 #define V_LNG_CMD(x) ((x) << S_LNG_CMD)
8322 #define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
8324 #define S_LNF_STAT 12
8325 #define M_LNF_STAT 0x7U
8326 #define V_LNF_STAT(x) ((x) << S_LNF_STAT)
8327 #define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
8330 #define M_LNF_CMD 0x7U
8331 #define V_LNF_CMD(x) ((x) << S_LNF_CMD)
8332 #define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
8334 #define S_LNE_STAT 4
8335 #define M_LNE_STAT 0x7U
8336 #define V_LNE_STAT(x) ((x) << S_LNE_STAT)
8337 #define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
8340 #define M_LNE_CMD 0x7U
8341 #define V_LNE_CMD(x) ((x) << S_LNE_CMD)
8342 #define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
8344 #define A_PCIE_PHY_FS_LF0 0x5bb0
8346 #define S_LANE1LF 24
8347 #define M_LANE1LF 0x3fU
8348 #define V_LANE1LF(x) ((x) << S_LANE1LF)
8349 #define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
8351 #define S_LANE1FS 16
8352 #define M_LANE1FS 0x3fU
8353 #define V_LANE1FS(x) ((x) << S_LANE1FS)
8354 #define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
8357 #define M_LANE0LF 0x3fU
8358 #define V_LANE0LF(x) ((x) << S_LANE0LF)
8359 #define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
8362 #define M_LANE0FS 0x3fU
8363 #define V_LANE0FS(x) ((x) << S_LANE0FS)
8364 #define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
8366 #define A_PCIE_PHY_FS_LF1 0x5bb4
8368 #define S_LANE3LF 24
8369 #define M_LANE3LF 0x3fU
8370 #define V_LANE3LF(x) ((x) << S_LANE3LF)
8371 #define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
8373 #define S_LANE3FS 16
8374 #define M_LANE3FS 0x3fU
8375 #define V_LANE3FS(x) ((x) << S_LANE3FS)
8376 #define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
8379 #define M_LANE2LF 0x3fU
8380 #define V_LANE2LF(x) ((x) << S_LANE2LF)
8381 #define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
8384 #define M_LANE2FS 0x3fU
8385 #define V_LANE2FS(x) ((x) << S_LANE2FS)
8386 #define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
8388 #define A_PCIE_PHY_FS_LF2 0x5bb8
8390 #define S_LANE5LF 24
8391 #define M_LANE5LF 0x3fU
8392 #define V_LANE5LF(x) ((x) << S_LANE5LF)
8393 #define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
8395 #define S_LANE5FS 16
8396 #define M_LANE5FS 0x3fU
8397 #define V_LANE5FS(x) ((x) << S_LANE5FS)
8398 #define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
8401 #define M_LANE4LF 0x3fU
8402 #define V_LANE4LF(x) ((x) << S_LANE4LF)
8403 #define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
8406 #define M_LANE4FS 0x3fU
8407 #define V_LANE4FS(x) ((x) << S_LANE4FS)
8408 #define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
8410 #define A_PCIE_PHY_FS_LF3 0x5bbc
8412 #define S_LANE7LF 24
8413 #define M_LANE7LF 0x3fU
8414 #define V_LANE7LF(x) ((x) << S_LANE7LF)
8415 #define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
8417 #define S_LANE7FS 16
8418 #define M_LANE7FS 0x3fU
8419 #define V_LANE7FS(x) ((x) << S_LANE7FS)
8420 #define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
8423 #define M_LANE6LF 0x3fU
8424 #define V_LANE6LF(x) ((x) << S_LANE6LF)
8425 #define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
8428 #define M_LANE6FS 0x3fU
8429 #define V_LANE6FS(x) ((x) << S_LANE6FS)
8430 #define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
8432 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
8434 #define S_COEFFDONE 16
8435 #define V_COEFFDONE(x) ((x) << S_COEFFDONE)
8436 #define F_COEFFDONE V_COEFFDONE(1U)
8438 #define S_COEFFLANE 8
8439 #define M_COEFFLANE 0x7U
8440 #define V_COEFFLANE(x) ((x) << S_COEFFLANE)
8441 #define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
8443 #define S_COEFFSTART 0
8444 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
8445 #define F_COEFFSTART V_COEFFSTART(1U)
8447 #define S_T6_COEFFLANE 8
8448 #define M_T6_COEFFLANE 0xfU
8449 #define V_T6_COEFFLANE(x) ((x) << S_T6_COEFFLANE)
8450 #define G_T6_COEFFLANE(x) (((x) >> S_T6_COEFFLANE) & M_T6_COEFFLANE)
8452 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
8455 #define M_COEFF 0x3ffffU
8456 #define V_COEFF(x) ((x) << S_COEFF)
8457 #define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
8459 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
8461 #define S_PHYENABLE 31
8462 #define V_PHYENABLE(x) ((x) << S_PHYENABLE)
8463 #define F_PHYENABLE V_PHYENABLE(1U)
8465 #define S_PCIE_PHY_REGADDR 0
8466 #define M_PCIE_PHY_REGADDR 0xffffU
8467 #define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
8468 #define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
8470 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
8471 #define A_PCIE_STATIC_SPARE1 0x5bf8
8472 #define A_PCIE_STATIC_SPARE2 0x5bfc
8473 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
8475 #define S_KDB_PF_LEN 24
8476 #define M_KDB_PF_LEN 0x1fU
8477 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
8478 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
8480 #define S_KDB_PF_BASEADDR 0
8481 #define M_KDB_PF_BASEADDR 0xfffffU
8482 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
8483 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
8485 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
8487 #define S_KDB_VF_LEN 24
8488 #define M_KDB_VF_LEN 0x1fU
8489 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
8490 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
8492 #define S_KDB_VF_BASEADDR 0
8493 #define M_KDB_VF_BASEADDR 0xfffffU
8494 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
8495 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
8497 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
8499 #define S_KDB_VF_MODOFST 0
8500 #define M_KDB_VF_MODOFST 0xfffU
8501 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
8502 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
8504 #define A_PCIE_PHY_REQRXPWR1 0x5c1c
8506 #define S_REQ_LNP_RXSTATEDONE 31
8507 #define V_REQ_LNP_RXSTATEDONE(x) ((x) << S_REQ_LNP_RXSTATEDONE)
8508 #define F_REQ_LNP_RXSTATEDONE V_REQ_LNP_RXSTATEDONE(1U)
8510 #define S_REQ_LNP_RXSTATEREQ 30
8511 #define V_REQ_LNP_RXSTATEREQ(x) ((x) << S_REQ_LNP_RXSTATEREQ)
8512 #define F_REQ_LNP_RXSTATEREQ V_REQ_LNP_RXSTATEREQ(1U)
8514 #define S_REQ_LNP_RXPWRSTATE 28
8515 #define M_REQ_LNP_RXPWRSTATE 0x3U
8516 #define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE)
8517 #define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE)
8519 #define S_REQ_LNO_RXSTATEDONE 27
8520 #define V_REQ_LNO_RXSTATEDONE(x) ((x) << S_REQ_LNO_RXSTATEDONE)
8521 #define F_REQ_LNO_RXSTATEDONE V_REQ_LNO_RXSTATEDONE(1U)
8523 #define S_REQ_LNO_RXSTATEREQ 26
8524 #define V_REQ_LNO_RXSTATEREQ(x) ((x) << S_REQ_LNO_RXSTATEREQ)
8525 #define F_REQ_LNO_RXSTATEREQ V_REQ_LNO_RXSTATEREQ(1U)
8527 #define S_REQ_LNO_RXPWRSTATE 24
8528 #define M_REQ_LNO_RXPWRSTATE 0x3U
8529 #define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE)
8530 #define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE)
8532 #define S_REQ_LNN_RXSTATEDONE 23
8533 #define V_REQ_LNN_RXSTATEDONE(x) ((x) << S_REQ_LNN_RXSTATEDONE)
8534 #define F_REQ_LNN_RXSTATEDONE V_REQ_LNN_RXSTATEDONE(1U)
8536 #define S_REQ_LNN_RXSTATEREQ 22
8537 #define V_REQ_LNN_RXSTATEREQ(x) ((x) << S_REQ_LNN_RXSTATEREQ)
8538 #define F_REQ_LNN_RXSTATEREQ V_REQ_LNN_RXSTATEREQ(1U)
8540 #define S_REQ_LNN_RXPWRSTATE 20
8541 #define M_REQ_LNN_RXPWRSTATE 0x3U
8542 #define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE)
8543 #define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE)
8545 #define S_REQ_LNM_RXSTATEDONE 19
8546 #define V_REQ_LNM_RXSTATEDONE(x) ((x) << S_REQ_LNM_RXSTATEDONE)
8547 #define F_REQ_LNM_RXSTATEDONE V_REQ_LNM_RXSTATEDONE(1U)
8549 #define S_REQ_LNM_RXSTATEREQ 18
8550 #define V_REQ_LNM_RXSTATEREQ(x) ((x) << S_REQ_LNM_RXSTATEREQ)
8551 #define F_REQ_LNM_RXSTATEREQ V_REQ_LNM_RXSTATEREQ(1U)
8553 #define S_REQ_LNM_RXPWRSTATE 16
8554 #define M_REQ_LNM_RXPWRSTATE 0x3U
8555 #define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE)
8556 #define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE)
8558 #define S_REQ_LNL_RXSTATEDONE 15
8559 #define V_REQ_LNL_RXSTATEDONE(x) ((x) << S_REQ_LNL_RXSTATEDONE)
8560 #define F_REQ_LNL_RXSTATEDONE V_REQ_LNL_RXSTATEDONE(1U)
8562 #define S_REQ_LNL_RXSTATEREQ 14
8563 #define V_REQ_LNL_RXSTATEREQ(x) ((x) << S_REQ_LNL_RXSTATEREQ)
8564 #define F_REQ_LNL_RXSTATEREQ V_REQ_LNL_RXSTATEREQ(1U)
8566 #define S_REQ_LNL_RXPWRSTATE 12
8567 #define M_REQ_LNL_RXPWRSTATE 0x3U
8568 #define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE)
8569 #define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE)
8571 #define S_REQ_LNK_RXSTATEDONE 11
8572 #define V_REQ_LNK_RXSTATEDONE(x) ((x) << S_REQ_LNK_RXSTATEDONE)
8573 #define F_REQ_LNK_RXSTATEDONE V_REQ_LNK_RXSTATEDONE(1U)
8575 #define S_REQ_LNK_RXSTATEREQ 10
8576 #define V_REQ_LNK_RXSTATEREQ(x) ((x) << S_REQ_LNK_RXSTATEREQ)
8577 #define F_REQ_LNK_RXSTATEREQ V_REQ_LNK_RXSTATEREQ(1U)
8579 #define S_REQ_LNK_RXPWRSTATE 8
8580 #define M_REQ_LNK_RXPWRSTATE 0x3U
8581 #define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE)
8582 #define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE)
8584 #define S_REQ_LNJ_RXSTATEDONE 7
8585 #define V_REQ_LNJ_RXSTATEDONE(x) ((x) << S_REQ_LNJ_RXSTATEDONE)
8586 #define F_REQ_LNJ_RXSTATEDONE V_REQ_LNJ_RXSTATEDONE(1U)
8588 #define S_REQ_LNJ_RXSTATEREQ 6
8589 #define V_REQ_LNJ_RXSTATEREQ(x) ((x) << S_REQ_LNJ_RXSTATEREQ)
8590 #define F_REQ_LNJ_RXSTATEREQ V_REQ_LNJ_RXSTATEREQ(1U)
8592 #define S_REQ_LNJ_RXPWRSTATE 4
8593 #define M_REQ_LNJ_RXPWRSTATE 0x3U
8594 #define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE)
8595 #define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE)
8597 #define S_REQ_LNI_RXSTATEDONE 3
8598 #define V_REQ_LNI_RXSTATEDONE(x) ((x) << S_REQ_LNI_RXSTATEDONE)
8599 #define F_REQ_LNI_RXSTATEDONE V_REQ_LNI_RXSTATEDONE(1U)
8601 #define S_REQ_LNI_RXSTATEREQ 2
8602 #define V_REQ_LNI_RXSTATEREQ(x) ((x) << S_REQ_LNI_RXSTATEREQ)
8603 #define F_REQ_LNI_RXSTATEREQ V_REQ_LNI_RXSTATEREQ(1U)
8605 #define S_REQ_LNI_RXPWRSTATE 0
8606 #define M_REQ_LNI_RXPWRSTATE 0x3U
8607 #define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE)
8608 #define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE)
8610 #define A_PCIE_PHY_CURRXPWR1 0x5c20
8612 #define S_CUR_LNP_RXPWRSTATE 28
8613 #define M_CUR_LNP_RXPWRSTATE 0x7U
8614 #define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE)
8615 #define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE)
8617 #define S_CUR_LNO_RXPWRSTATE 24
8618 #define M_CUR_LNO_RXPWRSTATE 0x7U
8619 #define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE)
8620 #define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE)
8622 #define S_CUR_LNN_RXPWRSTATE 20
8623 #define M_CUR_LNN_RXPWRSTATE 0x7U
8624 #define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE)
8625 #define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE)
8627 #define S_CUR_LNM_RXPWRSTATE 16
8628 #define M_CUR_LNM_RXPWRSTATE 0x7U
8629 #define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE)
8630 #define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE)
8632 #define S_CUR_LNL_RXPWRSTATE 12
8633 #define M_CUR_LNL_RXPWRSTATE 0x7U
8634 #define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE)
8635 #define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE)
8637 #define S_CUR_LNK_RXPWRSTATE 8
8638 #define M_CUR_LNK_RXPWRSTATE 0x7U
8639 #define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE)
8640 #define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE)
8642 #define S_CUR_LNJ_RXPWRSTATE 4
8643 #define M_CUR_LNJ_RXPWRSTATE 0x7U
8644 #define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE)
8645 #define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE)
8647 #define S_CUR_LNI_RXPWRSTATE 0
8648 #define M_CUR_LNI_RXPWRSTATE 0x7U
8649 #define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE)
8650 #define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE)
8652 #define A_PCIE_PHY_GEN3_AE2 0x5c24
8654 #define S_LNL_STAT 28
8655 #define M_LNL_STAT 0x7U
8656 #define V_LNL_STAT(x) ((x) << S_LNL_STAT)
8657 #define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT)
8659 #define S_LNL_CMD 24
8660 #define M_LNL_CMD 0x7U
8661 #define V_LNL_CMD(x) ((x) << S_LNL_CMD)
8662 #define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD)
8664 #define S_LNK_STAT 20
8665 #define M_LNK_STAT 0x7U
8666 #define V_LNK_STAT(x) ((x) << S_LNK_STAT)
8667 #define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT)
8669 #define S_LNK_CMD 16
8670 #define M_LNK_CMD 0x7U
8671 #define V_LNK_CMD(x) ((x) << S_LNK_CMD)
8672 #define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD)
8674 #define S_LNJ_STAT 12
8675 #define M_LNJ_STAT 0x7U
8676 #define V_LNJ_STAT(x) ((x) << S_LNJ_STAT)
8677 #define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT)
8680 #define M_LNJ_CMD 0x7U
8681 #define V_LNJ_CMD(x) ((x) << S_LNJ_CMD)
8682 #define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD)
8684 #define S_LNI_STAT 4
8685 #define M_LNI_STAT 0x7U
8686 #define V_LNI_STAT(x) ((x) << S_LNI_STAT)
8687 #define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT)
8690 #define M_LNI_CMD 0x7U
8691 #define V_LNI_CMD(x) ((x) << S_LNI_CMD)
8692 #define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD)
8694 #define A_PCIE_PHY_GEN3_AE3 0x5c28
8696 #define S_LNP_STAT 28
8697 #define M_LNP_STAT 0x7U
8698 #define V_LNP_STAT(x) ((x) << S_LNP_STAT)
8699 #define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT)
8701 #define S_LNP_CMD 24
8702 #define M_LNP_CMD 0x7U
8703 #define V_LNP_CMD(x) ((x) << S_LNP_CMD)
8704 #define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD)
8706 #define S_LNO_STAT 20
8707 #define M_LNO_STAT 0x7U
8708 #define V_LNO_STAT(x) ((x) << S_LNO_STAT)
8709 #define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT)
8711 #define S_LNO_CMD 16
8712 #define M_LNO_CMD 0x7U
8713 #define V_LNO_CMD(x) ((x) << S_LNO_CMD)
8714 #define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD)
8716 #define S_LNN_STAT 12
8717 #define M_LNN_STAT 0x7U
8718 #define V_LNN_STAT(x) ((x) << S_LNN_STAT)
8719 #define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT)
8722 #define M_LNN_CMD 0x7U
8723 #define V_LNN_CMD(x) ((x) << S_LNN_CMD)
8724 #define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD)
8726 #define S_LNM_STAT 4
8727 #define M_LNM_STAT 0x7U
8728 #define V_LNM_STAT(x) ((x) << S_LNM_STAT)
8729 #define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT)
8732 #define M_LNM_CMD 0x7U
8733 #define V_LNM_CMD(x) ((x) << S_LNM_CMD)
8734 #define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD)
8736 #define A_PCIE_PHY_FS_LF4 0x5c2c
8738 #define S_LANE9LF 24
8739 #define M_LANE9LF 0x3fU
8740 #define V_LANE9LF(x) ((x) << S_LANE9LF)
8741 #define G_LANE9LF(x) (((x) >> S_LANE9LF) & M_LANE9LF)
8743 #define S_LANE9FS 16
8744 #define M_LANE9FS 0x3fU
8745 #define V_LANE9FS(x) ((x) << S_LANE9FS)
8746 #define G_LANE9FS(x) (((x) >> S_LANE9FS) & M_LANE9FS)
8749 #define M_LANE8LF 0x3fU
8750 #define V_LANE8LF(x) ((x) << S_LANE8LF)
8751 #define G_LANE8LF(x) (((x) >> S_LANE8LF) & M_LANE8LF)
8754 #define M_LANE8FS 0x3fU
8755 #define V_LANE8FS(x) ((x) << S_LANE8FS)
8756 #define G_LANE8FS(x) (((x) >> S_LANE8FS) & M_LANE8FS)
8758 #define A_PCIE_PHY_FS_LF5 0x5c30
8760 #define S_LANE11LF 24
8761 #define M_LANE11LF 0x3fU
8762 #define V_LANE11LF(x) ((x) << S_LANE11LF)
8763 #define G_LANE11LF(x) (((x) >> S_LANE11LF) & M_LANE11LF)
8765 #define S_LANE11FS 16
8766 #define M_LANE11FS 0x3fU
8767 #define V_LANE11FS(x) ((x) << S_LANE11FS)
8768 #define G_LANE11FS(x) (((x) >> S_LANE11FS) & M_LANE11FS)
8770 #define S_LANE10LF 8
8771 #define M_LANE10LF 0x3fU
8772 #define V_LANE10LF(x) ((x) << S_LANE10LF)
8773 #define G_LANE10LF(x) (((x) >> S_LANE10LF) & M_LANE10LF)
8775 #define S_LANE10FS 0
8776 #define M_LANE10FS 0x3fU
8777 #define V_LANE10FS(x) ((x) << S_LANE10FS)
8778 #define G_LANE10FS(x) (((x) >> S_LANE10FS) & M_LANE10FS)
8780 #define A_PCIE_PHY_FS_LF6 0x5c34
8782 #define S_LANE13LF 24
8783 #define M_LANE13LF 0x3fU
8784 #define V_LANE13LF(x) ((x) << S_LANE13LF)
8785 #define G_LANE13LF(x) (((x) >> S_LANE13LF) & M_LANE13LF)
8787 #define S_LANE13FS 16
8788 #define M_LANE13FS 0x3fU
8789 #define V_LANE13FS(x) ((x) << S_LANE13FS)
8790 #define G_LANE13FS(x) (((x) >> S_LANE13FS) & M_LANE13FS)
8792 #define S_LANE12LF 8
8793 #define M_LANE12LF 0x3fU
8794 #define V_LANE12LF(x) ((x) << S_LANE12LF)
8795 #define G_LANE12LF(x) (((x) >> S_LANE12LF) & M_LANE12LF)
8797 #define S_LANE12FS 0
8798 #define M_LANE12FS 0x3fU
8799 #define V_LANE12FS(x) ((x) << S_LANE12FS)
8800 #define G_LANE12FS(x) (((x) >> S_LANE12FS) & M_LANE12FS)
8802 #define A_PCIE_PHY_FS_LF7 0x5c38
8804 #define S_LANE15LF 24
8805 #define M_LANE15LF 0x3fU
8806 #define V_LANE15LF(x) ((x) << S_LANE15LF)
8807 #define G_LANE15LF(x) (((x) >> S_LANE15LF) & M_LANE15LF)
8809 #define S_LANE15FS 16
8810 #define M_LANE15FS 0x3fU
8811 #define V_LANE15FS(x) ((x) << S_LANE15FS)
8812 #define G_LANE15FS(x) (((x) >> S_LANE15FS) & M_LANE15FS)
8814 #define S_LANE14LF 8
8815 #define M_LANE14LF 0x3fU
8816 #define V_LANE14LF(x) ((x) << S_LANE14LF)
8817 #define G_LANE14LF(x) (((x) >> S_LANE14LF) & M_LANE14LF)
8819 #define S_LANE14FS 0
8820 #define M_LANE14FS 0x3fU
8821 #define V_LANE14FS(x) ((x) << S_LANE14FS)
8822 #define G_LANE14FS(x) (((x) >> S_LANE14FS) & M_LANE14FS)
8824 #define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
8826 #define S_PHY_REG_ENABLE 31
8827 #define V_PHY_REG_ENABLE(x) ((x) << S_PHY_REG_ENABLE)
8828 #define F_PHY_REG_ENABLE V_PHY_REG_ENABLE(1U)
8830 #define S_PHY_REG_SELECT 22
8831 #define M_PHY_REG_SELECT 0x3U
8832 #define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT)
8833 #define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT)
8835 #define S_PHY_REG_REGADDR 0
8836 #define M_PHY_REG_REGADDR 0xffffU
8837 #define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR)
8838 #define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR)
8840 #define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
8842 #define S_PHY_REG_DATA 0
8843 #define M_PHY_REG_DATA 0xffffU
8844 #define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA)
8845 #define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA)
8847 #define A_PCIE_VF_INT_INDIR_REQ 0x5c44
8849 #define S_ENABLE_VF 24
8850 #define V_ENABLE_VF(x) ((x) << S_ENABLE_VF)
8851 #define F_ENABLE_VF V_ENABLE_VF(1U)
8854 #define V_AI_VF(x) ((x) << S_AI_VF)
8855 #define F_AI_VF V_AI_VF(1U)
8857 #define S_VFID_PCIE 0
8858 #define M_VFID_PCIE 0x3ffU
8859 #define V_VFID_PCIE(x) ((x) << S_VFID_PCIE)
8860 #define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
8862 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
8863 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
8864 #define A_PCIE_VF_MSI_EN_4 0x5e50
8865 #define A_PCIE_VF_MSI_EN_5 0x5e54
8866 #define A_PCIE_VF_MSI_EN_6 0x5e58
8867 #define A_PCIE_VF_MSI_EN_7 0x5e5c
8868 #define A_PCIE_VF_MSIX_EN_4 0x5e60
8869 #define A_PCIE_VF_MSIX_EN_5 0x5e64
8870 #define A_PCIE_VF_MSIX_EN_6 0x5e68
8871 #define A_PCIE_VF_MSIX_EN_7 0x5e6c
8872 #define A_PCIE_FLR_VF4_STATUS 0x5e70
8873 #define A_PCIE_FLR_VF5_STATUS 0x5e74
8874 #define A_PCIE_FLR_VF6_STATUS 0x5e78
8875 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
8876 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
8877 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
8878 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
8879 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
8880 #define A_PCIE_BUS_MST_STAT_8 0x5e90
8882 #define S_BUSMST_263_256 0
8883 #define M_BUSMST_263_256 0xffU
8884 #define V_BUSMST_263_256(x) ((x) << S_BUSMST_263_256)
8885 #define G_BUSMST_263_256(x) (((x) >> S_BUSMST_263_256) & M_BUSMST_263_256)
8887 #define A_PCIE_TGT_SKID_FIFO 0x5e94
8889 #define S_HDRFREECNT 16
8890 #define M_HDRFREECNT 0xfffU
8891 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
8892 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
8894 #define S_DATAFREECNT 0
8895 #define M_DATAFREECNT 0xfffU
8896 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
8897 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
8899 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
8900 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
8901 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
8902 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
8903 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
8905 #define S_RSPERR_263_256 0
8906 #define M_RSPERR_263_256 0xffU
8907 #define V_RSPERR_263_256(x) ((x) << S_RSPERR_263_256)
8908 #define G_RSPERR_263_256(x) (((x) >> S_RSPERR_263_256) & M_RSPERR_263_256)
8910 #define A_PCIE_PHY_STAT1 0x5ec0
8912 #define S_PHY0_RTUNE_ACK 31
8913 #define V_PHY0_RTUNE_ACK(x) ((x) << S_PHY0_RTUNE_ACK)
8914 #define F_PHY0_RTUNE_ACK V_PHY0_RTUNE_ACK(1U)
8916 #define S_PHY1_RTUNE_ACK 30
8917 #define V_PHY1_RTUNE_ACK(x) ((x) << S_PHY1_RTUNE_ACK)
8918 #define F_PHY1_RTUNE_ACK V_PHY1_RTUNE_ACK(1U)
8920 #define A_PCIE_PHY_CTRL1 0x5ec4
8922 #define S_PHY0_RTUNE_REQ 31
8923 #define V_PHY0_RTUNE_REQ(x) ((x) << S_PHY0_RTUNE_REQ)
8924 #define F_PHY0_RTUNE_REQ V_PHY0_RTUNE_REQ(1U)
8926 #define S_PHY1_RTUNE_REQ 30
8927 #define V_PHY1_RTUNE_REQ(x) ((x) << S_PHY1_RTUNE_REQ)
8928 #define F_PHY1_RTUNE_REQ V_PHY1_RTUNE_REQ(1U)
8930 #define S_TXDEEMPH_GEN1 16
8931 #define M_TXDEEMPH_GEN1 0xffU
8932 #define V_TXDEEMPH_GEN1(x) ((x) << S_TXDEEMPH_GEN1)
8933 #define G_TXDEEMPH_GEN1(x) (((x) >> S_TXDEEMPH_GEN1) & M_TXDEEMPH_GEN1)
8935 #define S_TXDEEMPH_GEN2_3P5DB 8
8936 #define M_TXDEEMPH_GEN2_3P5DB 0xffU
8937 #define V_TXDEEMPH_GEN2_3P5DB(x) ((x) << S_TXDEEMPH_GEN2_3P5DB)
8938 #define G_TXDEEMPH_GEN2_3P5DB(x) (((x) >> S_TXDEEMPH_GEN2_3P5DB) & M_TXDEEMPH_GEN2_3P5DB)
8940 #define S_TXDEEMPH_GEN2_6DB 0
8941 #define M_TXDEEMPH_GEN2_6DB 0xffU
8942 #define V_TXDEEMPH_GEN2_6DB(x) ((x) << S_TXDEEMPH_GEN2_6DB)
8943 #define G_TXDEEMPH_GEN2_6DB(x) (((x) >> S_TXDEEMPH_GEN2_6DB) & M_TXDEEMPH_GEN2_6DB)
8945 #define A_PCIE_PCIE_SPARE0 0x5ec8
8946 #define A_PCIE_RESET_STAT 0x5ecc
8948 #define S_PON_RST_STATE_FLAG 11
8949 #define V_PON_RST_STATE_FLAG(x) ((x) << S_PON_RST_STATE_FLAG)
8950 #define F_PON_RST_STATE_FLAG V_PON_RST_STATE_FLAG(1U)
8952 #define S_BUS_RST_STATE_FLAG 10
8953 #define V_BUS_RST_STATE_FLAG(x) ((x) << S_BUS_RST_STATE_FLAG)
8954 #define F_BUS_RST_STATE_FLAG V_BUS_RST_STATE_FLAG(1U)
8956 #define S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG 9
8957 #define V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG)
8958 #define F_DL_DOWN_PCIECRST_MODE0_STATE_FLAG V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(1U)
8960 #define S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG 8
8961 #define V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG)
8962 #define F_DL_DOWN_PCIECRST_MODE1_STATE_FLAG V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(1U)
8964 #define S_PCIE_WARM_RST_MODE0_STATE_FLAG 7
8965 #define V_PCIE_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE0_STATE_FLAG)
8966 #define F_PCIE_WARM_RST_MODE0_STATE_FLAG V_PCIE_WARM_RST_MODE0_STATE_FLAG(1U)
8968 #define S_PCIE_WARM_RST_MODE1_STATE_FLAG 6
8969 #define V_PCIE_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE1_STATE_FLAG)
8970 #define F_PCIE_WARM_RST_MODE1_STATE_FLAG V_PCIE_WARM_RST_MODE1_STATE_FLAG(1U)
8972 #define S_PIO_WARM_RST_MODE0_STATE_FLAG 5
8973 #define V_PIO_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE0_STATE_FLAG)
8974 #define F_PIO_WARM_RST_MODE0_STATE_FLAG V_PIO_WARM_RST_MODE0_STATE_FLAG(1U)
8976 #define S_PIO_WARM_RST_MODE1_STATE_FLAG 4
8977 #define V_PIO_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE1_STATE_FLAG)
8978 #define F_PIO_WARM_RST_MODE1_STATE_FLAG V_PIO_WARM_RST_MODE1_STATE_FLAG(1U)
8980 #define S_LASTRESETSTATE 0
8981 #define M_LASTRESETSTATE 0x7U
8982 #define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE)
8983 #define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE)
8985 #define A_PCIE_FUNC_DSTATE 0x5ed0
8987 #define S_PF7_DSTATE 21
8988 #define M_PF7_DSTATE 0x7U
8989 #define V_PF7_DSTATE(x) ((x) << S_PF7_DSTATE)
8990 #define G_PF7_DSTATE(x) (((x) >> S_PF7_DSTATE) & M_PF7_DSTATE)
8992 #define S_PF6_DSTATE 18
8993 #define M_PF6_DSTATE 0x7U
8994 #define V_PF6_DSTATE(x) ((x) << S_PF6_DSTATE)
8995 #define G_PF6_DSTATE(x) (((x) >> S_PF6_DSTATE) & M_PF6_DSTATE)
8997 #define S_PF5_DSTATE 15
8998 #define M_PF5_DSTATE 0x7U
8999 #define V_PF5_DSTATE(x) ((x) << S_PF5_DSTATE)
9000 #define G_PF5_DSTATE(x) (((x) >> S_PF5_DSTATE) & M_PF5_DSTATE)
9002 #define S_PF4_DSTATE 12
9003 #define M_PF4_DSTATE 0x7U
9004 #define V_PF4_DSTATE(x) ((x) << S_PF4_DSTATE)
9005 #define G_PF4_DSTATE(x) (((x) >> S_PF4_DSTATE) & M_PF4_DSTATE)
9007 #define S_PF3_DSTATE 9
9008 #define M_PF3_DSTATE 0x7U
9009 #define V_PF3_DSTATE(x) ((x) << S_PF3_DSTATE)
9010 #define G_PF3_DSTATE(x) (((x) >> S_PF3_DSTATE) & M_PF3_DSTATE)
9012 #define S_PF2_DSTATE 6
9013 #define M_PF2_DSTATE 0x7U
9014 #define V_PF2_DSTATE(x) ((x) << S_PF2_DSTATE)
9015 #define G_PF2_DSTATE(x) (((x) >> S_PF2_DSTATE) & M_PF2_DSTATE)
9017 #define S_PF1_DSTATE 3
9018 #define M_PF1_DSTATE 0x7U
9019 #define V_PF1_DSTATE(x) ((x) << S_PF1_DSTATE)
9020 #define G_PF1_DSTATE(x) (((x) >> S_PF1_DSTATE) & M_PF1_DSTATE)
9022 #define S_PF0_DSTATE 0
9023 #define M_PF0_DSTATE 0x7U
9024 #define V_PF0_DSTATE(x) ((x) << S_PF0_DSTATE)
9025 #define G_PF0_DSTATE(x) (((x) >> S_PF0_DSTATE) & M_PF0_DSTATE)
9027 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
9028 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
9029 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
9030 #define A_PCIE_PDEBUG_REG_0X0 0x0
9031 #define A_PCIE_PDEBUG_REG_0X1 0x1
9032 #define A_PCIE_PDEBUG_REG_0X2 0x2
9034 #define S_TAGQ_CH0_TAGS_USED 11
9035 #define M_TAGQ_CH0_TAGS_USED 0xffU
9036 #define V_TAGQ_CH0_TAGS_USED(x) ((x) << S_TAGQ_CH0_TAGS_USED)
9037 #define G_TAGQ_CH0_TAGS_USED(x) (((x) >> S_TAGQ_CH0_TAGS_USED) & M_TAGQ_CH0_TAGS_USED)
9039 #define S_REQ_CH0_DATA_EMPTY 10
9040 #define V_REQ_CH0_DATA_EMPTY(x) ((x) << S_REQ_CH0_DATA_EMPTY)
9041 #define F_REQ_CH0_DATA_EMPTY V_REQ_CH0_DATA_EMPTY(1U)
9043 #define S_RDQ_CH0_REQ_EMPTY 9
9044 #define V_RDQ_CH0_REQ_EMPTY(x) ((x) << S_RDQ_CH0_REQ_EMPTY)
9045 #define F_RDQ_CH0_REQ_EMPTY V_RDQ_CH0_REQ_EMPTY(1U)
9047 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ 8
9048 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ)
9049 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(1U)
9051 #define S_REQ_CTL_RD_CH0_WAIT_FOR_CMD 7
9052 #define V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_CMD)
9053 #define F_REQ_CTL_RD_CH0_WAIT_FOR_CMD V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(1U)
9055 #define S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM 6
9056 #define V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM)
9057 #define F_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(1U)
9059 #define S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ 5
9060 #define V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ)
9061 #define F_REQ_CTL_RD_CH0_WAIT_FOR_RDQ V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(1U)
9063 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO 4
9064 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO)
9065 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9067 #define S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED 3
9068 #define V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED)
9069 #define F_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(1U)
9071 #define S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED 2
9072 #define V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED)
9073 #define F_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(1U)
9075 #define S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE 1
9076 #define V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE)
9077 #define F_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(1U)
9079 #define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA 0
9080 #define V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA)
9081 #define F_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(1U)
9083 #define A_PCIE_PDEBUG_REG_0X3 0x3
9085 #define S_TAGQ_CH1_TAGS_USED 11
9086 #define M_TAGQ_CH1_TAGS_USED 0xffU
9087 #define V_TAGQ_CH1_TAGS_USED(x) ((x) << S_TAGQ_CH1_TAGS_USED)
9088 #define G_TAGQ_CH1_TAGS_USED(x) (((x) >> S_TAGQ_CH1_TAGS_USED) & M_TAGQ_CH1_TAGS_USED)
9090 #define S_REQ_CH1_DATA_EMPTY 10
9091 #define V_REQ_CH1_DATA_EMPTY(x) ((x) << S_REQ_CH1_DATA_EMPTY)
9092 #define F_REQ_CH1_DATA_EMPTY V_REQ_CH1_DATA_EMPTY(1U)
9094 #define S_RDQ_CH1_REQ_EMPTY 9
9095 #define V_RDQ_CH1_REQ_EMPTY(x) ((x) << S_RDQ_CH1_REQ_EMPTY)
9096 #define F_RDQ_CH1_REQ_EMPTY V_RDQ_CH1_REQ_EMPTY(1U)
9098 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ 8
9099 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ)
9100 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(1U)
9102 #define S_REQ_CTL_RD_CH1_WAIT_FOR_CMD 7
9103 #define V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_CMD)
9104 #define F_REQ_CTL_RD_CH1_WAIT_FOR_CMD V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(1U)
9106 #define S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM 6
9107 #define V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM)
9108 #define F_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(1U)
9110 #define S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ 5
9111 #define V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ)
9112 #define F_REQ_CTL_RD_CH1_WAIT_FOR_RDQ V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(1U)
9114 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO 4
9115 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO)
9116 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9118 #define S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED 3
9119 #define V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED)
9120 #define F_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(1U)
9122 #define S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED 2
9123 #define V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED)
9124 #define F_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(1U)
9126 #define S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE 1
9127 #define V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE)
9128 #define F_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(1U)
9130 #define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA 0
9131 #define V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA)
9132 #define F_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(1U)
9134 #define A_PCIE_PDEBUG_REG_0X4 0x4
9136 #define S_TAGQ_CH2_TAGS_USED 11
9137 #define M_TAGQ_CH2_TAGS_USED 0xffU
9138 #define V_TAGQ_CH2_TAGS_USED(x) ((x) << S_TAGQ_CH2_TAGS_USED)
9139 #define G_TAGQ_CH2_TAGS_USED(x) (((x) >> S_TAGQ_CH2_TAGS_USED) & M_TAGQ_CH2_TAGS_USED)
9141 #define S_REQ_CH2_DATA_EMPTY 10
9142 #define V_REQ_CH2_DATA_EMPTY(x) ((x) << S_REQ_CH2_DATA_EMPTY)
9143 #define F_REQ_CH2_DATA_EMPTY V_REQ_CH2_DATA_EMPTY(1U)
9145 #define S_RDQ_CH2_REQ_EMPTY 9
9146 #define V_RDQ_CH2_REQ_EMPTY(x) ((x) << S_RDQ_CH2_REQ_EMPTY)
9147 #define F_RDQ_CH2_REQ_EMPTY V_RDQ_CH2_REQ_EMPTY(1U)
9149 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ 8
9150 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ)
9151 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(1U)
9153 #define S_REQ_CTL_RD_CH2_WAIT_FOR_CMD 7
9154 #define V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_CMD)
9155 #define F_REQ_CTL_RD_CH2_WAIT_FOR_CMD V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(1U)
9157 #define S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM 6
9158 #define V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM)
9159 #define F_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(1U)
9161 #define S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ 5
9162 #define V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ)
9163 #define F_REQ_CTL_RD_CH2_WAIT_FOR_RDQ V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(1U)
9165 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO 4
9166 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO)
9167 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9169 #define S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED 3
9170 #define V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED)
9171 #define F_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(1U)
9173 #define S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED 2
9174 #define V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED)
9175 #define F_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(1U)
9177 #define S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE 1
9178 #define V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE)
9179 #define F_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(1U)
9181 #define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA 0
9182 #define V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA)
9183 #define F_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(1U)
9185 #define A_PCIE_PDEBUG_REG_0X5 0x5
9187 #define S_TAGQ_CH3_TAGS_USED 11
9188 #define M_TAGQ_CH3_TAGS_USED 0xffU
9189 #define V_TAGQ_CH3_TAGS_USED(x) ((x) << S_TAGQ_CH3_TAGS_USED)
9190 #define G_TAGQ_CH3_TAGS_USED(x) (((x) >> S_TAGQ_CH3_TAGS_USED) & M_TAGQ_CH3_TAGS_USED)
9192 #define S_REQ_CH3_DATA_EMPTY 10
9193 #define V_REQ_CH3_DATA_EMPTY(x) ((x) << S_REQ_CH3_DATA_EMPTY)
9194 #define F_REQ_CH3_DATA_EMPTY V_REQ_CH3_DATA_EMPTY(1U)
9196 #define S_RDQ_CH3_REQ_EMPTY 9
9197 #define V_RDQ_CH3_REQ_EMPTY(x) ((x) << S_RDQ_CH3_REQ_EMPTY)
9198 #define F_RDQ_CH3_REQ_EMPTY V_RDQ_CH3_REQ_EMPTY(1U)
9200 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ 8
9201 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ)
9202 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(1U)
9204 #define S_REQ_CTL_RD_CH3_WAIT_FOR_CMD 7
9205 #define V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_CMD)
9206 #define F_REQ_CTL_RD_CH3_WAIT_FOR_CMD V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(1U)
9208 #define S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM 6
9209 #define V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM)
9210 #define F_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(1U)
9212 #define S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ 5
9213 #define V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ)
9214 #define F_REQ_CTL_RD_CH3_WAIT_FOR_RDQ V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(1U)
9216 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO 4
9217 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO)
9218 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9220 #define S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED 3
9221 #define V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED)
9222 #define F_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(1U)
9224 #define S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED 2
9225 #define V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED)
9226 #define F_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(1U)
9228 #define S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE 1
9229 #define V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE)
9230 #define F_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(1U)
9232 #define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA 0
9233 #define V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA)
9234 #define F_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(1U)
9236 #define A_PCIE_PDEBUG_REG_0X6 0x6
9238 #define S_TAGQ_CH4_TAGS_USED 11
9239 #define M_TAGQ_CH4_TAGS_USED 0xffU
9240 #define V_TAGQ_CH4_TAGS_USED(x) ((x) << S_TAGQ_CH4_TAGS_USED)
9241 #define G_TAGQ_CH4_TAGS_USED(x) (((x) >> S_TAGQ_CH4_TAGS_USED) & M_TAGQ_CH4_TAGS_USED)
9243 #define S_REQ_CH4_DATA_EMPTY 10
9244 #define V_REQ_CH4_DATA_EMPTY(x) ((x) << S_REQ_CH4_DATA_EMPTY)
9245 #define F_REQ_CH4_DATA_EMPTY V_REQ_CH4_DATA_EMPTY(1U)
9247 #define S_RDQ_CH4_REQ_EMPTY 9
9248 #define V_RDQ_CH4_REQ_EMPTY(x) ((x) << S_RDQ_CH4_REQ_EMPTY)
9249 #define F_RDQ_CH4_REQ_EMPTY V_RDQ_CH4_REQ_EMPTY(1U)
9251 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ 8
9252 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ)
9253 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(1U)
9255 #define S_REQ_CTL_RD_CH4_WAIT_FOR_CMD 7
9256 #define V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_CMD)
9257 #define F_REQ_CTL_RD_CH4_WAIT_FOR_CMD V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(1U)
9259 #define S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM 6
9260 #define V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM)
9261 #define F_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(1U)
9263 #define S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ 5
9264 #define V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ)
9265 #define F_REQ_CTL_RD_CH4_WAIT_FOR_RDQ V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(1U)
9267 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO 4
9268 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO)
9269 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9271 #define S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED 3
9272 #define V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED)
9273 #define F_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(1U)
9275 #define S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED 2
9276 #define V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED)
9277 #define F_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(1U)
9279 #define S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE 1
9280 #define V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE)
9281 #define F_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(1U)
9283 #define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA 0
9284 #define V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA)
9285 #define F_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(1U)
9287 #define A_PCIE_PDEBUG_REG_0X7 0x7
9289 #define S_TAGQ_CH5_TAGS_USED 11
9290 #define M_TAGQ_CH5_TAGS_USED 0xffU
9291 #define V_TAGQ_CH5_TAGS_USED(x) ((x) << S_TAGQ_CH5_TAGS_USED)
9292 #define G_TAGQ_CH5_TAGS_USED(x) (((x) >> S_TAGQ_CH5_TAGS_USED) & M_TAGQ_CH5_TAGS_USED)
9294 #define S_REQ_CH5_DATA_EMPTY 10
9295 #define V_REQ_CH5_DATA_EMPTY(x) ((x) << S_REQ_CH5_DATA_EMPTY)
9296 #define F_REQ_CH5_DATA_EMPTY V_REQ_CH5_DATA_EMPTY(1U)
9298 #define S_RDQ_CH5_REQ_EMPTY 9
9299 #define V_RDQ_CH5_REQ_EMPTY(x) ((x) << S_RDQ_CH5_REQ_EMPTY)
9300 #define F_RDQ_CH5_REQ_EMPTY V_RDQ_CH5_REQ_EMPTY(1U)
9302 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ 8
9303 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ)
9304 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(1U)
9306 #define S_REQ_CTL_RD_CH5_WAIT_FOR_CMD 7
9307 #define V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_CMD)
9308 #define F_REQ_CTL_RD_CH5_WAIT_FOR_CMD V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(1U)
9310 #define S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM 6
9311 #define V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM)
9312 #define F_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(1U)
9314 #define S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ 5
9315 #define V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ)
9316 #define F_REQ_CTL_RD_CH5_WAIT_FOR_RDQ V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(1U)
9318 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO 4
9319 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO)
9320 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9322 #define S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED 3
9323 #define V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED)
9324 #define F_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(1U)
9326 #define S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED 2
9327 #define V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED)
9328 #define F_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(1U)
9330 #define S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE 1
9331 #define V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE)
9332 #define F_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(1U)
9334 #define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA 0
9335 #define V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA)
9336 #define F_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(1U)
9338 #define A_PCIE_PDEBUG_REG_0X8 0x8
9340 #define S_TAGQ_CH6_TAGS_USED 11
9341 #define M_TAGQ_CH6_TAGS_USED 0xffU
9342 #define V_TAGQ_CH6_TAGS_USED(x) ((x) << S_TAGQ_CH6_TAGS_USED)
9343 #define G_TAGQ_CH6_TAGS_USED(x) (((x) >> S_TAGQ_CH6_TAGS_USED) & M_TAGQ_CH6_TAGS_USED)
9345 #define S_REQ_CH6_DATA_EMPTY 10
9346 #define V_REQ_CH6_DATA_EMPTY(x) ((x) << S_REQ_CH6_DATA_EMPTY)
9347 #define F_REQ_CH6_DATA_EMPTY V_REQ_CH6_DATA_EMPTY(1U)
9349 #define S_RDQ_CH6_REQ_EMPTY 9
9350 #define V_RDQ_CH6_REQ_EMPTY(x) ((x) << S_RDQ_CH6_REQ_EMPTY)
9351 #define F_RDQ_CH6_REQ_EMPTY V_RDQ_CH6_REQ_EMPTY(1U)
9353 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ 8
9354 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ)
9355 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(1U)
9357 #define S_REQ_CTL_RD_CH6_WAIT_FOR_CMD 7
9358 #define V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_CMD)
9359 #define F_REQ_CTL_RD_CH6_WAIT_FOR_CMD V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(1U)
9361 #define S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM 6
9362 #define V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM)
9363 #define F_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(1U)
9365 #define S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ 5
9366 #define V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ)
9367 #define F_REQ_CTL_RD_CH6_WAIT_FOR_RDQ V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(1U)
9369 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO 4
9370 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO)
9371 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9373 #define S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED 3
9374 #define V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED)
9375 #define F_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(1U)
9377 #define S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED 2
9378 #define V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED)
9379 #define F_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(1U)
9381 #define S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE 1
9382 #define V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE)
9383 #define F_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(1U)
9385 #define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA 0
9386 #define V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA)
9387 #define F_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(1U)
9389 #define A_PCIE_PDEBUG_REG_0X9 0x9
9391 #define S_TAGQ_CH7_TAGS_USED 11
9392 #define M_TAGQ_CH7_TAGS_USED 0xffU
9393 #define V_TAGQ_CH7_TAGS_USED(x) ((x) << S_TAGQ_CH7_TAGS_USED)
9394 #define G_TAGQ_CH7_TAGS_USED(x) (((x) >> S_TAGQ_CH7_TAGS_USED) & M_TAGQ_CH7_TAGS_USED)
9396 #define S_REQ_CH7_DATA_EMPTY 10
9397 #define V_REQ_CH7_DATA_EMPTY(x) ((x) << S_REQ_CH7_DATA_EMPTY)
9398 #define F_REQ_CH7_DATA_EMPTY V_REQ_CH7_DATA_EMPTY(1U)
9400 #define S_RDQ_CH7_REQ_EMPTY 9
9401 #define V_RDQ_CH7_REQ_EMPTY(x) ((x) << S_RDQ_CH7_REQ_EMPTY)
9402 #define F_RDQ_CH7_REQ_EMPTY V_RDQ_CH7_REQ_EMPTY(1U)
9404 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ 8
9405 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ)
9406 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(1U)
9408 #define S_REQ_CTL_RD_CH7_WAIT_FOR_CMD 7
9409 #define V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_CMD)
9410 #define F_REQ_CTL_RD_CH7_WAIT_FOR_CMD V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(1U)
9412 #define S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM 6
9413 #define V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM)
9414 #define F_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(1U)
9416 #define S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ 5
9417 #define V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ)
9418 #define F_REQ_CTL_RD_CH7_WAIT_FOR_RDQ V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(1U)
9420 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO 4
9421 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO)
9422 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9424 #define S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED 3
9425 #define V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED)
9426 #define F_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(1U)
9428 #define S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED 2
9429 #define V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED)
9430 #define F_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(1U)
9432 #define S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE 1
9433 #define V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE)
9434 #define F_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(1U)
9436 #define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA 0
9437 #define V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA)
9438 #define F_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(1U)
9440 #define A_PCIE_PDEBUG_REG_0XA 0xa
9442 #define S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM 27
9443 #define V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM)
9444 #define F_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(1U)
9446 #define S_REQ_CTL_WR_CH0_SEQNUM 19
9447 #define M_REQ_CTL_WR_CH0_SEQNUM 0xffU
9448 #define V_REQ_CTL_WR_CH0_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH0_SEQNUM)
9449 #define G_REQ_CTL_WR_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH0_SEQNUM) & M_REQ_CTL_WR_CH0_SEQNUM)
9451 #define S_REQ_CTL_RD_CH0_SEQNUM 11
9452 #define M_REQ_CTL_RD_CH0_SEQNUM 0xffU
9453 #define V_REQ_CTL_RD_CH0_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_SEQNUM)
9454 #define G_REQ_CTL_RD_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH0_SEQNUM) & M_REQ_CTL_RD_CH0_SEQNUM)
9456 #define S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO 4
9457 #define V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO)
9458 #define F_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(1U)
9460 #define S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED 3
9461 #define V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED)
9462 #define F_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(1U)
9464 #define S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED 2
9465 #define V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED)
9466 #define F_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(1U)
9468 #define S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE 1
9469 #define V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE)
9470 #define F_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(1U)
9472 #define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA 0
9473 #define V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA)
9474 #define F_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(1U)
9476 #define A_PCIE_PDEBUG_REG_0XB 0xb
9478 #define S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM 27
9479 #define V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM)
9480 #define F_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(1U)
9482 #define S_REQ_CTL_WR_CH1_SEQNUM 19
9483 #define M_REQ_CTL_WR_CH1_SEQNUM 0xffU
9484 #define V_REQ_CTL_WR_CH1_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH1_SEQNUM)
9485 #define G_REQ_CTL_WR_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH1_SEQNUM) & M_REQ_CTL_WR_CH1_SEQNUM)
9487 #define S_REQ_CTL_RD_CH1_SEQNUM 11
9488 #define M_REQ_CTL_RD_CH1_SEQNUM 0xffU
9489 #define V_REQ_CTL_RD_CH1_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_SEQNUM)
9490 #define G_REQ_CTL_RD_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH1_SEQNUM) & M_REQ_CTL_RD_CH1_SEQNUM)
9492 #define S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO 4
9493 #define V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO)
9494 #define F_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(1U)
9496 #define S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED 3
9497 #define V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED)
9498 #define F_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(1U)
9500 #define S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED 2
9501 #define V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED)
9502 #define F_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(1U)
9504 #define S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE 1
9505 #define V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE)
9506 #define F_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(1U)
9508 #define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA 0
9509 #define V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA)
9510 #define F_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(1U)
9512 #define A_PCIE_PDEBUG_REG_0XC 0xc
9514 #define S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM 27
9515 #define V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM)
9516 #define F_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(1U)
9518 #define S_REQ_CTL_WR_CH2_SEQNUM 19
9519 #define M_REQ_CTL_WR_CH2_SEQNUM 0xffU
9520 #define V_REQ_CTL_WR_CH2_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH2_SEQNUM)
9521 #define G_REQ_CTL_WR_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH2_SEQNUM) & M_REQ_CTL_WR_CH2_SEQNUM)
9523 #define S_REQ_CTL_RD_CH2_SEQNUM 11
9524 #define M_REQ_CTL_RD_CH2_SEQNUM 0xffU
9525 #define V_REQ_CTL_RD_CH2_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_SEQNUM)
9526 #define G_REQ_CTL_RD_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH2_SEQNUM) & M_REQ_CTL_RD_CH2_SEQNUM)
9528 #define S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO 4
9529 #define V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO)
9530 #define F_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(1U)
9532 #define S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED 3
9533 #define V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED)
9534 #define F_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(1U)
9536 #define S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED 2
9537 #define V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED)
9538 #define F_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(1U)
9540 #define S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE 1
9541 #define V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE)
9542 #define F_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(1U)
9544 #define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA 0
9545 #define V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA)
9546 #define F_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(1U)
9548 #define A_PCIE_PDEBUG_REG_0XD 0xd
9550 #define S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM 27
9551 #define V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM)
9552 #define F_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(1U)
9554 #define S_REQ_CTL_WR_CH3_SEQNUM 19
9555 #define M_REQ_CTL_WR_CH3_SEQNUM 0xffU
9556 #define V_REQ_CTL_WR_CH3_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH3_SEQNUM)
9557 #define G_REQ_CTL_WR_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH3_SEQNUM) & M_REQ_CTL_WR_CH3_SEQNUM)
9559 #define S_REQ_CTL_RD_CH3_SEQNUM 11
9560 #define M_REQ_CTL_RD_CH3_SEQNUM 0xffU
9561 #define V_REQ_CTL_RD_CH3_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_SEQNUM)
9562 #define G_REQ_CTL_RD_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH3_SEQNUM) & M_REQ_CTL_RD_CH3_SEQNUM)
9564 #define S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO 4
9565 #define V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO)
9566 #define F_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(1U)
9568 #define S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED 3
9569 #define V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED)
9570 #define F_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(1U)
9572 #define S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED 2
9573 #define V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED)
9574 #define F_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(1U)
9576 #define S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE 1
9577 #define V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE)
9578 #define F_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(1U)
9580 #define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA 0
9581 #define V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA)
9582 #define F_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(1U)
9584 #define A_PCIE_PDEBUG_REG_0XE 0xe
9586 #define S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM 27
9587 #define V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM)
9588 #define F_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(1U)
9590 #define S_REQ_CTL_WR_CH4_SEQNUM 19
9591 #define M_REQ_CTL_WR_CH4_SEQNUM 0xffU
9592 #define V_REQ_CTL_WR_CH4_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH4_SEQNUM)
9593 #define G_REQ_CTL_WR_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH4_SEQNUM) & M_REQ_CTL_WR_CH4_SEQNUM)
9595 #define S_REQ_CTL_RD_CH4_SEQNUM 11
9596 #define M_REQ_CTL_RD_CH4_SEQNUM 0xffU
9597 #define V_REQ_CTL_RD_CH4_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_SEQNUM)
9598 #define G_REQ_CTL_RD_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH4_SEQNUM) & M_REQ_CTL_RD_CH4_SEQNUM)
9600 #define S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO 4
9601 #define V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO)
9602 #define F_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(1U)
9604 #define S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED 3
9605 #define V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED)
9606 #define F_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(1U)
9608 #define S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED 2
9609 #define V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED)
9610 #define F_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(1U)
9612 #define S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE 1
9613 #define V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE)
9614 #define F_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(1U)
9616 #define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA 0
9617 #define V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA)
9618 #define F_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(1U)
9620 #define A_PCIE_PDEBUG_REG_0XF 0xf
9621 #define A_PCIE_PDEBUG_REG_0X10 0x10
9623 #define S_PIPE0_TX3_DATAK_0 31
9624 #define V_PIPE0_TX3_DATAK_0(x) ((x) << S_PIPE0_TX3_DATAK_0)
9625 #define F_PIPE0_TX3_DATAK_0 V_PIPE0_TX3_DATAK_0(1U)
9627 #define S_PIPE0_TX3_DATA_6_0 24
9628 #define M_PIPE0_TX3_DATA_6_0 0x7fU
9629 #define V_PIPE0_TX3_DATA_6_0(x) ((x) << S_PIPE0_TX3_DATA_6_0)
9630 #define G_PIPE0_TX3_DATA_6_0(x) (((x) >> S_PIPE0_TX3_DATA_6_0) & M_PIPE0_TX3_DATA_6_0)
9632 #define S_PIPE0_TX2_DATA_7_0 16
9633 #define M_PIPE0_TX2_DATA_7_0 0xffU
9634 #define V_PIPE0_TX2_DATA_7_0(x) ((x) << S_PIPE0_TX2_DATA_7_0)
9635 #define G_PIPE0_TX2_DATA_7_0(x) (((x) >> S_PIPE0_TX2_DATA_7_0) & M_PIPE0_TX2_DATA_7_0)
9637 #define S_PIPE0_TX1_DATA_7_0 8
9638 #define M_PIPE0_TX1_DATA_7_0 0xffU
9639 #define V_PIPE0_TX1_DATA_7_0(x) ((x) << S_PIPE0_TX1_DATA_7_0)
9640 #define G_PIPE0_TX1_DATA_7_0(x) (((x) >> S_PIPE0_TX1_DATA_7_0) & M_PIPE0_TX1_DATA_7_0)
9642 #define S_PIPE0_TX0_DATAK_0 7
9643 #define V_PIPE0_TX0_DATAK_0(x) ((x) << S_PIPE0_TX0_DATAK_0)
9644 #define F_PIPE0_TX0_DATAK_0 V_PIPE0_TX0_DATAK_0(1U)
9646 #define S_PIPE0_TX0_DATA_6_0 0
9647 #define M_PIPE0_TX0_DATA_6_0 0x7fU
9648 #define V_PIPE0_TX0_DATA_6_0(x) ((x) << S_PIPE0_TX0_DATA_6_0)
9649 #define G_PIPE0_TX0_DATA_6_0(x) (((x) >> S_PIPE0_TX0_DATA_6_0) & M_PIPE0_TX0_DATA_6_0)
9651 #define A_PCIE_PDEBUG_REG_0X11 0x11
9653 #define S_PIPE0_TX3_DATAK_1 31
9654 #define V_PIPE0_TX3_DATAK_1(x) ((x) << S_PIPE0_TX3_DATAK_1)
9655 #define F_PIPE0_TX3_DATAK_1 V_PIPE0_TX3_DATAK_1(1U)
9657 #define S_PIPE0_TX3_DATA_14_8 24
9658 #define M_PIPE0_TX3_DATA_14_8 0x7fU
9659 #define V_PIPE0_TX3_DATA_14_8(x) ((x) << S_PIPE0_TX3_DATA_14_8)
9660 #define G_PIPE0_TX3_DATA_14_8(x) (((x) >> S_PIPE0_TX3_DATA_14_8) & M_PIPE0_TX3_DATA_14_8)
9662 #define S_PIPE0_TX2_DATA_15_8 16
9663 #define M_PIPE0_TX2_DATA_15_8 0xffU
9664 #define V_PIPE0_TX2_DATA_15_8(x) ((x) << S_PIPE0_TX2_DATA_15_8)
9665 #define G_PIPE0_TX2_DATA_15_8(x) (((x) >> S_PIPE0_TX2_DATA_15_8) & M_PIPE0_TX2_DATA_15_8)
9667 #define S_PIPE0_TX1_DATA_15_8 8
9668 #define M_PIPE0_TX1_DATA_15_8 0xffU
9669 #define V_PIPE0_TX1_DATA_15_8(x) ((x) << S_PIPE0_TX1_DATA_15_8)
9670 #define G_PIPE0_TX1_DATA_15_8(x) (((x) >> S_PIPE0_TX1_DATA_15_8) & M_PIPE0_TX1_DATA_15_8)
9672 #define S_PIPE0_TX0_DATAK_1 7
9673 #define V_PIPE0_TX0_DATAK_1(x) ((x) << S_PIPE0_TX0_DATAK_1)
9674 #define F_PIPE0_TX0_DATAK_1 V_PIPE0_TX0_DATAK_1(1U)
9676 #define S_PIPE0_TX0_DATA_14_8 0
9677 #define M_PIPE0_TX0_DATA_14_8 0x7fU
9678 #define V_PIPE0_TX0_DATA_14_8(x) ((x) << S_PIPE0_TX0_DATA_14_8)
9679 #define G_PIPE0_TX0_DATA_14_8(x) (((x) >> S_PIPE0_TX0_DATA_14_8) & M_PIPE0_TX0_DATA_14_8)
9681 #define A_PCIE_PDEBUG_REG_0X12 0x12
9683 #define S_PIPE0_TX7_DATAK_0 31
9684 #define V_PIPE0_TX7_DATAK_0(x) ((x) << S_PIPE0_TX7_DATAK_0)
9685 #define F_PIPE0_TX7_DATAK_0 V_PIPE0_TX7_DATAK_0(1U)
9687 #define S_PIPE0_TX7_DATA_6_0 24
9688 #define M_PIPE0_TX7_DATA_6_0 0x7fU
9689 #define V_PIPE0_TX7_DATA_6_0(x) ((x) << S_PIPE0_TX7_DATA_6_0)
9690 #define G_PIPE0_TX7_DATA_6_0(x) (((x) >> S_PIPE0_TX7_DATA_6_0) & M_PIPE0_TX7_DATA_6_0)
9692 #define S_PIPE0_TX6_DATA_7_0 16
9693 #define M_PIPE0_TX6_DATA_7_0 0xffU
9694 #define V_PIPE0_TX6_DATA_7_0(x) ((x) << S_PIPE0_TX6_DATA_7_0)
9695 #define G_PIPE0_TX6_DATA_7_0(x) (((x) >> S_PIPE0_TX6_DATA_7_0) & M_PIPE0_TX6_DATA_7_0)
9697 #define S_PIPE0_TX5_DATA_7_0 8
9698 #define M_PIPE0_TX5_DATA_7_0 0xffU
9699 #define V_PIPE0_TX5_DATA_7_0(x) ((x) << S_PIPE0_TX5_DATA_7_0)
9700 #define G_PIPE0_TX5_DATA_7_0(x) (((x) >> S_PIPE0_TX5_DATA_7_0) & M_PIPE0_TX5_DATA_7_0)
9702 #define S_PIPE0_TX4_DATAK_0 7
9703 #define V_PIPE0_TX4_DATAK_0(x) ((x) << S_PIPE0_TX4_DATAK_0)
9704 #define F_PIPE0_TX4_DATAK_0 V_PIPE0_TX4_DATAK_0(1U)
9706 #define S_PIPE0_TX4_DATA_6_0 0
9707 #define M_PIPE0_TX4_DATA_6_0 0x7fU
9708 #define V_PIPE0_TX4_DATA_6_0(x) ((x) << S_PIPE0_TX4_DATA_6_0)
9709 #define G_PIPE0_TX4_DATA_6_0(x) (((x) >> S_PIPE0_TX4_DATA_6_0) & M_PIPE0_TX4_DATA_6_0)
9711 #define A_PCIE_PDEBUG_REG_0X13 0x13
9713 #define S_PIPE0_TX7_DATAK_1 31
9714 #define V_PIPE0_TX7_DATAK_1(x) ((x) << S_PIPE0_TX7_DATAK_1)
9715 #define F_PIPE0_TX7_DATAK_1 V_PIPE0_TX7_DATAK_1(1U)
9717 #define S_PIPE0_TX7_DATA_14_8 24
9718 #define M_PIPE0_TX7_DATA_14_8 0x7fU
9719 #define V_PIPE0_TX7_DATA_14_8(x) ((x) << S_PIPE0_TX7_DATA_14_8)
9720 #define G_PIPE0_TX7_DATA_14_8(x) (((x) >> S_PIPE0_TX7_DATA_14_8) & M_PIPE0_TX7_DATA_14_8)
9722 #define S_PIPE0_TX6_DATA_15_8 16
9723 #define M_PIPE0_TX6_DATA_15_8 0xffU
9724 #define V_PIPE0_TX6_DATA_15_8(x) ((x) << S_PIPE0_TX6_DATA_15_8)
9725 #define G_PIPE0_TX6_DATA_15_8(x) (((x) >> S_PIPE0_TX6_DATA_15_8) & M_PIPE0_TX6_DATA_15_8)
9727 #define S_PIPE0_TX5_DATA_15_8 8
9728 #define M_PIPE0_TX5_DATA_15_8 0xffU
9729 #define V_PIPE0_TX5_DATA_15_8(x) ((x) << S_PIPE0_TX5_DATA_15_8)
9730 #define G_PIPE0_TX5_DATA_15_8(x) (((x) >> S_PIPE0_TX5_DATA_15_8) & M_PIPE0_TX5_DATA_15_8)
9732 #define S_PIPE0_TX4_DATAK_1 7
9733 #define V_PIPE0_TX4_DATAK_1(x) ((x) << S_PIPE0_TX4_DATAK_1)
9734 #define F_PIPE0_TX4_DATAK_1 V_PIPE0_TX4_DATAK_1(1U)
9736 #define S_PIPE0_TX4_DATA_14_8 0
9737 #define M_PIPE0_TX4_DATA_14_8 0x7fU
9738 #define V_PIPE0_TX4_DATA_14_8(x) ((x) << S_PIPE0_TX4_DATA_14_8)
9739 #define G_PIPE0_TX4_DATA_14_8(x) (((x) >> S_PIPE0_TX4_DATA_14_8) & M_PIPE0_TX4_DATA_14_8)
9741 #define A_PCIE_PDEBUG_REG_0X14 0x14
9743 #define S_PIPE0_RX3_VALID_14 31
9744 #define V_PIPE0_RX3_VALID_14(x) ((x) << S_PIPE0_RX3_VALID_14)
9745 #define F_PIPE0_RX3_VALID_14 V_PIPE0_RX3_VALID_14(1U)
9747 #define S_PIPE0_RX3_VALID2_14 24
9748 #define M_PIPE0_RX3_VALID2_14 0x7fU
9749 #define V_PIPE0_RX3_VALID2_14(x) ((x) << S_PIPE0_RX3_VALID2_14)
9750 #define G_PIPE0_RX3_VALID2_14(x) (((x) >> S_PIPE0_RX3_VALID2_14) & M_PIPE0_RX3_VALID2_14)
9752 #define S_PIPE0_RX2_VALID_14 16
9753 #define M_PIPE0_RX2_VALID_14 0xffU
9754 #define V_PIPE0_RX2_VALID_14(x) ((x) << S_PIPE0_RX2_VALID_14)
9755 #define G_PIPE0_RX2_VALID_14(x) (((x) >> S_PIPE0_RX2_VALID_14) & M_PIPE0_RX2_VALID_14)
9757 #define S_PIPE0_RX1_VALID_14 8
9758 #define M_PIPE0_RX1_VALID_14 0xffU
9759 #define V_PIPE0_RX1_VALID_14(x) ((x) << S_PIPE0_RX1_VALID_14)
9760 #define G_PIPE0_RX1_VALID_14(x) (((x) >> S_PIPE0_RX1_VALID_14) & M_PIPE0_RX1_VALID_14)
9762 #define S_PIPE0_RX0_VALID_14 7
9763 #define V_PIPE0_RX0_VALID_14(x) ((x) << S_PIPE0_RX0_VALID_14)
9764 #define F_PIPE0_RX0_VALID_14 V_PIPE0_RX0_VALID_14(1U)
9766 #define S_PIPE0_RX0_VALID2_14 0
9767 #define M_PIPE0_RX0_VALID2_14 0x7fU
9768 #define V_PIPE0_RX0_VALID2_14(x) ((x) << S_PIPE0_RX0_VALID2_14)
9769 #define G_PIPE0_RX0_VALID2_14(x) (((x) >> S_PIPE0_RX0_VALID2_14) & M_PIPE0_RX0_VALID2_14)
9771 #define A_PCIE_PDEBUG_REG_0X15 0x15
9773 #define S_PIPE0_RX3_VALID_15 31
9774 #define V_PIPE0_RX3_VALID_15(x) ((x) << S_PIPE0_RX3_VALID_15)
9775 #define F_PIPE0_RX3_VALID_15 V_PIPE0_RX3_VALID_15(1U)
9777 #define S_PIPE0_RX3_VALID2_15 24
9778 #define M_PIPE0_RX3_VALID2_15 0x7fU
9779 #define V_PIPE0_RX3_VALID2_15(x) ((x) << S_PIPE0_RX3_VALID2_15)
9780 #define G_PIPE0_RX3_VALID2_15(x) (((x) >> S_PIPE0_RX3_VALID2_15) & M_PIPE0_RX3_VALID2_15)
9782 #define S_PIPE0_RX2_VALID_15 16
9783 #define M_PIPE0_RX2_VALID_15 0xffU
9784 #define V_PIPE0_RX2_VALID_15(x) ((x) << S_PIPE0_RX2_VALID_15)
9785 #define G_PIPE0_RX2_VALID_15(x) (((x) >> S_PIPE0_RX2_VALID_15) & M_PIPE0_RX2_VALID_15)
9787 #define S_PIPE0_RX1_VALID_15 8
9788 #define M_PIPE0_RX1_VALID_15 0xffU
9789 #define V_PIPE0_RX1_VALID_15(x) ((x) << S_PIPE0_RX1_VALID_15)
9790 #define G_PIPE0_RX1_VALID_15(x) (((x) >> S_PIPE0_RX1_VALID_15) & M_PIPE0_RX1_VALID_15)
9792 #define S_PIPE0_RX0_VALID_15 7
9793 #define V_PIPE0_RX0_VALID_15(x) ((x) << S_PIPE0_RX0_VALID_15)
9794 #define F_PIPE0_RX0_VALID_15 V_PIPE0_RX0_VALID_15(1U)
9796 #define S_PIPE0_RX0_VALID2_15 0
9797 #define M_PIPE0_RX0_VALID2_15 0x7fU
9798 #define V_PIPE0_RX0_VALID2_15(x) ((x) << S_PIPE0_RX0_VALID2_15)
9799 #define G_PIPE0_RX0_VALID2_15(x) (((x) >> S_PIPE0_RX0_VALID2_15) & M_PIPE0_RX0_VALID2_15)
9801 #define A_PCIE_PDEBUG_REG_0X16 0x16
9803 #define S_PIPE0_RX7_VALID_16 31
9804 #define V_PIPE0_RX7_VALID_16(x) ((x) << S_PIPE0_RX7_VALID_16)
9805 #define F_PIPE0_RX7_VALID_16 V_PIPE0_RX7_VALID_16(1U)
9807 #define S_PIPE0_RX7_VALID2_16 24
9808 #define M_PIPE0_RX7_VALID2_16 0x7fU
9809 #define V_PIPE0_RX7_VALID2_16(x) ((x) << S_PIPE0_RX7_VALID2_16)
9810 #define G_PIPE0_RX7_VALID2_16(x) (((x) >> S_PIPE0_RX7_VALID2_16) & M_PIPE0_RX7_VALID2_16)
9812 #define S_PIPE0_RX6_VALID_16 16
9813 #define M_PIPE0_RX6_VALID_16 0xffU
9814 #define V_PIPE0_RX6_VALID_16(x) ((x) << S_PIPE0_RX6_VALID_16)
9815 #define G_PIPE0_RX6_VALID_16(x) (((x) >> S_PIPE0_RX6_VALID_16) & M_PIPE0_RX6_VALID_16)
9817 #define S_PIPE0_RX5_VALID_16 8
9818 #define M_PIPE0_RX5_VALID_16 0xffU
9819 #define V_PIPE0_RX5_VALID_16(x) ((x) << S_PIPE0_RX5_VALID_16)
9820 #define G_PIPE0_RX5_VALID_16(x) (((x) >> S_PIPE0_RX5_VALID_16) & M_PIPE0_RX5_VALID_16)
9822 #define S_PIPE0_RX4_VALID_16 7
9823 #define V_PIPE0_RX4_VALID_16(x) ((x) << S_PIPE0_RX4_VALID_16)
9824 #define F_PIPE0_RX4_VALID_16 V_PIPE0_RX4_VALID_16(1U)
9826 #define S_PIPE0_RX4_VALID2_16 0
9827 #define M_PIPE0_RX4_VALID2_16 0x7fU
9828 #define V_PIPE0_RX4_VALID2_16(x) ((x) << S_PIPE0_RX4_VALID2_16)
9829 #define G_PIPE0_RX4_VALID2_16(x) (((x) >> S_PIPE0_RX4_VALID2_16) & M_PIPE0_RX4_VALID2_16)
9831 #define A_PCIE_PDEBUG_REG_0X17 0x17
9833 #define S_PIPE0_RX7_VALID_17 31
9834 #define V_PIPE0_RX7_VALID_17(x) ((x) << S_PIPE0_RX7_VALID_17)
9835 #define F_PIPE0_RX7_VALID_17 V_PIPE0_RX7_VALID_17(1U)
9837 #define S_PIPE0_RX7_VALID2_17 24
9838 #define M_PIPE0_RX7_VALID2_17 0x7fU
9839 #define V_PIPE0_RX7_VALID2_17(x) ((x) << S_PIPE0_RX7_VALID2_17)
9840 #define G_PIPE0_RX7_VALID2_17(x) (((x) >> S_PIPE0_RX7_VALID2_17) & M_PIPE0_RX7_VALID2_17)
9842 #define S_PIPE0_RX6_VALID_17 16
9843 #define M_PIPE0_RX6_VALID_17 0xffU
9844 #define V_PIPE0_RX6_VALID_17(x) ((x) << S_PIPE0_RX6_VALID_17)
9845 #define G_PIPE0_RX6_VALID_17(x) (((x) >> S_PIPE0_RX6_VALID_17) & M_PIPE0_RX6_VALID_17)
9847 #define S_PIPE0_RX5_VALID_17 8
9848 #define M_PIPE0_RX5_VALID_17 0xffU
9849 #define V_PIPE0_RX5_VALID_17(x) ((x) << S_PIPE0_RX5_VALID_17)
9850 #define G_PIPE0_RX5_VALID_17(x) (((x) >> S_PIPE0_RX5_VALID_17) & M_PIPE0_RX5_VALID_17)
9852 #define S_PIPE0_RX4_VALID_17 7
9853 #define V_PIPE0_RX4_VALID_17(x) ((x) << S_PIPE0_RX4_VALID_17)
9854 #define F_PIPE0_RX4_VALID_17 V_PIPE0_RX4_VALID_17(1U)
9856 #define S_PIPE0_RX4_VALID2_17 0
9857 #define M_PIPE0_RX4_VALID2_17 0x7fU
9858 #define V_PIPE0_RX4_VALID2_17(x) ((x) << S_PIPE0_RX4_VALID2_17)
9859 #define G_PIPE0_RX4_VALID2_17(x) (((x) >> S_PIPE0_RX4_VALID2_17) & M_PIPE0_RX4_VALID2_17)
9861 #define A_PCIE_PDEBUG_REG_0X18 0x18
9863 #define S_PIPE0_RX7_POLARITY 31
9864 #define V_PIPE0_RX7_POLARITY(x) ((x) << S_PIPE0_RX7_POLARITY)
9865 #define F_PIPE0_RX7_POLARITY V_PIPE0_RX7_POLARITY(1U)
9867 #define S_PIPE0_RX7_STATUS 28
9868 #define M_PIPE0_RX7_STATUS 0x7U
9869 #define V_PIPE0_RX7_STATUS(x) ((x) << S_PIPE0_RX7_STATUS)
9870 #define G_PIPE0_RX7_STATUS(x) (((x) >> S_PIPE0_RX7_STATUS) & M_PIPE0_RX7_STATUS)
9872 #define S_PIPE0_RX6_POLARITY 27
9873 #define V_PIPE0_RX6_POLARITY(x) ((x) << S_PIPE0_RX6_POLARITY)
9874 #define F_PIPE0_RX6_POLARITY V_PIPE0_RX6_POLARITY(1U)
9876 #define S_PIPE0_RX6_STATUS 24
9877 #define M_PIPE0_RX6_STATUS 0x7U
9878 #define V_PIPE0_RX6_STATUS(x) ((x) << S_PIPE0_RX6_STATUS)
9879 #define G_PIPE0_RX6_STATUS(x) (((x) >> S_PIPE0_RX6_STATUS) & M_PIPE0_RX6_STATUS)
9881 #define S_PIPE0_RX5_POLARITY 23
9882 #define V_PIPE0_RX5_POLARITY(x) ((x) << S_PIPE0_RX5_POLARITY)
9883 #define F_PIPE0_RX5_POLARITY V_PIPE0_RX5_POLARITY(1U)
9885 #define S_PIPE0_RX5_STATUS 20
9886 #define M_PIPE0_RX5_STATUS 0x7U
9887 #define V_PIPE0_RX5_STATUS(x) ((x) << S_PIPE0_RX5_STATUS)
9888 #define G_PIPE0_RX5_STATUS(x) (((x) >> S_PIPE0_RX5_STATUS) & M_PIPE0_RX5_STATUS)
9890 #define S_PIPE0_RX4_POLARITY 19
9891 #define V_PIPE0_RX4_POLARITY(x) ((x) << S_PIPE0_RX4_POLARITY)
9892 #define F_PIPE0_RX4_POLARITY V_PIPE0_RX4_POLARITY(1U)
9894 #define S_PIPE0_RX4_STATUS 16
9895 #define M_PIPE0_RX4_STATUS 0x7U
9896 #define V_PIPE0_RX4_STATUS(x) ((x) << S_PIPE0_RX4_STATUS)
9897 #define G_PIPE0_RX4_STATUS(x) (((x) >> S_PIPE0_RX4_STATUS) & M_PIPE0_RX4_STATUS)
9899 #define S_PIPE0_RX3_POLARITY 15
9900 #define V_PIPE0_RX3_POLARITY(x) ((x) << S_PIPE0_RX3_POLARITY)
9901 #define F_PIPE0_RX3_POLARITY V_PIPE0_RX3_POLARITY(1U)
9903 #define S_PIPE0_RX3_STATUS 12
9904 #define M_PIPE0_RX3_STATUS 0x7U
9905 #define V_PIPE0_RX3_STATUS(x) ((x) << S_PIPE0_RX3_STATUS)
9906 #define G_PIPE0_RX3_STATUS(x) (((x) >> S_PIPE0_RX3_STATUS) & M_PIPE0_RX3_STATUS)
9908 #define S_PIPE0_RX2_POLARITY 11
9909 #define V_PIPE0_RX2_POLARITY(x) ((x) << S_PIPE0_RX2_POLARITY)
9910 #define F_PIPE0_RX2_POLARITY V_PIPE0_RX2_POLARITY(1U)
9912 #define S_PIPE0_RX2_STATUS 8
9913 #define M_PIPE0_RX2_STATUS 0x7U
9914 #define V_PIPE0_RX2_STATUS(x) ((x) << S_PIPE0_RX2_STATUS)
9915 #define G_PIPE0_RX2_STATUS(x) (((x) >> S_PIPE0_RX2_STATUS) & M_PIPE0_RX2_STATUS)
9917 #define S_PIPE0_RX1_POLARITY 7
9918 #define V_PIPE0_RX1_POLARITY(x) ((x) << S_PIPE0_RX1_POLARITY)
9919 #define F_PIPE0_RX1_POLARITY V_PIPE0_RX1_POLARITY(1U)
9921 #define S_PIPE0_RX1_STATUS 4
9922 #define M_PIPE0_RX1_STATUS 0x7U
9923 #define V_PIPE0_RX1_STATUS(x) ((x) << S_PIPE0_RX1_STATUS)
9924 #define G_PIPE0_RX1_STATUS(x) (((x) >> S_PIPE0_RX1_STATUS) & M_PIPE0_RX1_STATUS)
9926 #define S_PIPE0_RX0_POLARITY 3
9927 #define V_PIPE0_RX0_POLARITY(x) ((x) << S_PIPE0_RX0_POLARITY)
9928 #define F_PIPE0_RX0_POLARITY V_PIPE0_RX0_POLARITY(1U)
9930 #define S_PIPE0_RX0_STATUS 0
9931 #define M_PIPE0_RX0_STATUS 0x7U
9932 #define V_PIPE0_RX0_STATUS(x) ((x) << S_PIPE0_RX0_STATUS)
9933 #define G_PIPE0_RX0_STATUS(x) (((x) >> S_PIPE0_RX0_STATUS) & M_PIPE0_RX0_STATUS)
9935 #define A_PCIE_PDEBUG_REG_0X19 0x19
9937 #define S_PIPE0_TX7_COMPLIANCE 31
9938 #define V_PIPE0_TX7_COMPLIANCE(x) ((x) << S_PIPE0_TX7_COMPLIANCE)
9939 #define F_PIPE0_TX7_COMPLIANCE V_PIPE0_TX7_COMPLIANCE(1U)
9941 #define S_PIPE0_TX6_COMPLIANCE 30
9942 #define V_PIPE0_TX6_COMPLIANCE(x) ((x) << S_PIPE0_TX6_COMPLIANCE)
9943 #define F_PIPE0_TX6_COMPLIANCE V_PIPE0_TX6_COMPLIANCE(1U)
9945 #define S_PIPE0_TX5_COMPLIANCE 29
9946 #define V_PIPE0_TX5_COMPLIANCE(x) ((x) << S_PIPE0_TX5_COMPLIANCE)
9947 #define F_PIPE0_TX5_COMPLIANCE V_PIPE0_TX5_COMPLIANCE(1U)
9949 #define S_PIPE0_TX4_COMPLIANCE 28
9950 #define V_PIPE0_TX4_COMPLIANCE(x) ((x) << S_PIPE0_TX4_COMPLIANCE)
9951 #define F_PIPE0_TX4_COMPLIANCE V_PIPE0_TX4_COMPLIANCE(1U)
9953 #define S_PIPE0_TX3_COMPLIANCE 27
9954 #define V_PIPE0_TX3_COMPLIANCE(x) ((x) << S_PIPE0_TX3_COMPLIANCE)
9955 #define F_PIPE0_TX3_COMPLIANCE V_PIPE0_TX3_COMPLIANCE(1U)
9957 #define S_PIPE0_TX2_COMPLIANCE 26
9958 #define V_PIPE0_TX2_COMPLIANCE(x) ((x) << S_PIPE0_TX2_COMPLIANCE)
9959 #define F_PIPE0_TX2_COMPLIANCE V_PIPE0_TX2_COMPLIANCE(1U)
9961 #define S_PIPE0_TX1_COMPLIANCE 25
9962 #define V_PIPE0_TX1_COMPLIANCE(x) ((x) << S_PIPE0_TX1_COMPLIANCE)
9963 #define F_PIPE0_TX1_COMPLIANCE V_PIPE0_TX1_COMPLIANCE(1U)
9965 #define S_PIPE0_TX0_COMPLIANCE 24
9966 #define V_PIPE0_TX0_COMPLIANCE(x) ((x) << S_PIPE0_TX0_COMPLIANCE)
9967 #define F_PIPE0_TX0_COMPLIANCE V_PIPE0_TX0_COMPLIANCE(1U)
9969 #define S_PIPE0_TX7_ELECIDLE 23
9970 #define V_PIPE0_TX7_ELECIDLE(x) ((x) << S_PIPE0_TX7_ELECIDLE)
9971 #define F_PIPE0_TX7_ELECIDLE V_PIPE0_TX7_ELECIDLE(1U)
9973 #define S_PIPE0_TX6_ELECIDLE 22
9974 #define V_PIPE0_TX6_ELECIDLE(x) ((x) << S_PIPE0_TX6_ELECIDLE)
9975 #define F_PIPE0_TX6_ELECIDLE V_PIPE0_TX6_ELECIDLE(1U)
9977 #define S_PIPE0_TX5_ELECIDLE 21
9978 #define V_PIPE0_TX5_ELECIDLE(x) ((x) << S_PIPE0_TX5_ELECIDLE)
9979 #define F_PIPE0_TX5_ELECIDLE V_PIPE0_TX5_ELECIDLE(1U)
9981 #define S_PIPE0_TX4_ELECIDLE 20
9982 #define V_PIPE0_TX4_ELECIDLE(x) ((x) << S_PIPE0_TX4_ELECIDLE)
9983 #define F_PIPE0_TX4_ELECIDLE V_PIPE0_TX4_ELECIDLE(1U)
9985 #define S_PIPE0_TX3_ELECIDLE 19
9986 #define V_PIPE0_TX3_ELECIDLE(x) ((x) << S_PIPE0_TX3_ELECIDLE)
9987 #define F_PIPE0_TX3_ELECIDLE V_PIPE0_TX3_ELECIDLE(1U)
9989 #define S_PIPE0_TX2_ELECIDLE 18
9990 #define V_PIPE0_TX2_ELECIDLE(x) ((x) << S_PIPE0_TX2_ELECIDLE)
9991 #define F_PIPE0_TX2_ELECIDLE V_PIPE0_TX2_ELECIDLE(1U)
9993 #define S_PIPE0_TX1_ELECIDLE 17
9994 #define V_PIPE0_TX1_ELECIDLE(x) ((x) << S_PIPE0_TX1_ELECIDLE)
9995 #define F_PIPE0_TX1_ELECIDLE V_PIPE0_TX1_ELECIDLE(1U)
9997 #define S_PIPE0_TX0_ELECIDLE 16
9998 #define V_PIPE0_TX0_ELECIDLE(x) ((x) << S_PIPE0_TX0_ELECIDLE)
9999 #define F_PIPE0_TX0_ELECIDLE V_PIPE0_TX0_ELECIDLE(1U)
10001 #define S_PIPE0_RX7_POLARITY_19 15
10002 #define V_PIPE0_RX7_POLARITY_19(x) ((x) << S_PIPE0_RX7_POLARITY_19)
10003 #define F_PIPE0_RX7_POLARITY_19 V_PIPE0_RX7_POLARITY_19(1U)
10005 #define S_PIPE0_RX6_POLARITY_19 14
10006 #define V_PIPE0_RX6_POLARITY_19(x) ((x) << S_PIPE0_RX6_POLARITY_19)
10007 #define F_PIPE0_RX6_POLARITY_19 V_PIPE0_RX6_POLARITY_19(1U)
10009 #define S_PIPE0_RX5_POLARITY_19 13
10010 #define V_PIPE0_RX5_POLARITY_19(x) ((x) << S_PIPE0_RX5_POLARITY_19)
10011 #define F_PIPE0_RX5_POLARITY_19 V_PIPE0_RX5_POLARITY_19(1U)
10013 #define S_PIPE0_RX4_POLARITY_19 12
10014 #define V_PIPE0_RX4_POLARITY_19(x) ((x) << S_PIPE0_RX4_POLARITY_19)
10015 #define F_PIPE0_RX4_POLARITY_19 V_PIPE0_RX4_POLARITY_19(1U)
10017 #define S_PIPE0_RX3_POLARITY_19 11
10018 #define V_PIPE0_RX3_POLARITY_19(x) ((x) << S_PIPE0_RX3_POLARITY_19)
10019 #define F_PIPE0_RX3_POLARITY_19 V_PIPE0_RX3_POLARITY_19(1U)
10021 #define S_PIPE0_RX2_POLARITY_19 10
10022 #define V_PIPE0_RX2_POLARITY_19(x) ((x) << S_PIPE0_RX2_POLARITY_19)
10023 #define F_PIPE0_RX2_POLARITY_19 V_PIPE0_RX2_POLARITY_19(1U)
10025 #define S_PIPE0_RX1_POLARITY_19 9
10026 #define V_PIPE0_RX1_POLARITY_19(x) ((x) << S_PIPE0_RX1_POLARITY_19)
10027 #define F_PIPE0_RX1_POLARITY_19 V_PIPE0_RX1_POLARITY_19(1U)
10029 #define S_PIPE0_RX0_POLARITY_19 8
10030 #define V_PIPE0_RX0_POLARITY_19(x) ((x) << S_PIPE0_RX0_POLARITY_19)
10031 #define F_PIPE0_RX0_POLARITY_19 V_PIPE0_RX0_POLARITY_19(1U)
10033 #define S_PIPE0_RX7_ELECIDLE 7
10034 #define V_PIPE0_RX7_ELECIDLE(x) ((x) << S_PIPE0_RX7_ELECIDLE)
10035 #define F_PIPE0_RX7_ELECIDLE V_PIPE0_RX7_ELECIDLE(1U)
10037 #define S_PIPE0_RX6_ELECIDLE 6
10038 #define V_PIPE0_RX6_ELECIDLE(x) ((x) << S_PIPE0_RX6_ELECIDLE)
10039 #define F_PIPE0_RX6_ELECIDLE V_PIPE0_RX6_ELECIDLE(1U)
10041 #define S_PIPE0_RX5_ELECIDLE 5
10042 #define V_PIPE0_RX5_ELECIDLE(x) ((x) << S_PIPE0_RX5_ELECIDLE)
10043 #define F_PIPE0_RX5_ELECIDLE V_PIPE0_RX5_ELECIDLE(1U)
10045 #define S_PIPE0_RX4_ELECIDLE 4
10046 #define V_PIPE0_RX4_ELECIDLE(x) ((x) << S_PIPE0_RX4_ELECIDLE)
10047 #define F_PIPE0_RX4_ELECIDLE V_PIPE0_RX4_ELECIDLE(1U)
10049 #define S_PIPE0_RX3_ELECIDLE 3
10050 #define V_PIPE0_RX3_ELECIDLE(x) ((x) << S_PIPE0_RX3_ELECIDLE)
10051 #define F_PIPE0_RX3_ELECIDLE V_PIPE0_RX3_ELECIDLE(1U)
10053 #define S_PIPE0_RX2_ELECIDLE 2
10054 #define V_PIPE0_RX2_ELECIDLE(x) ((x) << S_PIPE0_RX2_ELECIDLE)
10055 #define F_PIPE0_RX2_ELECIDLE V_PIPE0_RX2_ELECIDLE(1U)
10057 #define S_PIPE0_RX1_ELECIDLE 1
10058 #define V_PIPE0_RX1_ELECIDLE(x) ((x) << S_PIPE0_RX1_ELECIDLE)
10059 #define F_PIPE0_RX1_ELECIDLE V_PIPE0_RX1_ELECIDLE(1U)
10061 #define S_PIPE0_RX0_ELECIDLE 0
10062 #define V_PIPE0_RX0_ELECIDLE(x) ((x) << S_PIPE0_RX0_ELECIDLE)
10063 #define F_PIPE0_RX0_ELECIDLE V_PIPE0_RX0_ELECIDLE(1U)
10065 #define A_PCIE_PDEBUG_REG_0X1A 0x1a
10067 #define S_PIPE0_RESET_N 21
10068 #define V_PIPE0_RESET_N(x) ((x) << S_PIPE0_RESET_N)
10069 #define F_PIPE0_RESET_N V_PIPE0_RESET_N(1U)
10071 #define S_PCS_COMMON_CLOCKS 20
10072 #define V_PCS_COMMON_CLOCKS(x) ((x) << S_PCS_COMMON_CLOCKS)
10073 #define F_PCS_COMMON_CLOCKS V_PCS_COMMON_CLOCKS(1U)
10075 #define S_PCS_CLK_REQ 19
10076 #define V_PCS_CLK_REQ(x) ((x) << S_PCS_CLK_REQ)
10077 #define F_PCS_CLK_REQ V_PCS_CLK_REQ(1U)
10079 #define S_PIPE_CLKREQ_N 18
10080 #define V_PIPE_CLKREQ_N(x) ((x) << S_PIPE_CLKREQ_N)
10081 #define F_PIPE_CLKREQ_N V_PIPE_CLKREQ_N(1U)
10083 #define S_MAC_CLKREQ_N_TO_MUX 17
10084 #define V_MAC_CLKREQ_N_TO_MUX(x) ((x) << S_MAC_CLKREQ_N_TO_MUX)
10085 #define F_MAC_CLKREQ_N_TO_MUX V_MAC_CLKREQ_N_TO_MUX(1U)
10087 #define S_PIPE0_TX2RX_LOOPBK 16
10088 #define V_PIPE0_TX2RX_LOOPBK(x) ((x) << S_PIPE0_TX2RX_LOOPBK)
10089 #define F_PIPE0_TX2RX_LOOPBK V_PIPE0_TX2RX_LOOPBK(1U)
10091 #define S_PIPE0_TX_SWING 15
10092 #define V_PIPE0_TX_SWING(x) ((x) << S_PIPE0_TX_SWING)
10093 #define F_PIPE0_TX_SWING V_PIPE0_TX_SWING(1U)
10095 #define S_PIPE0_TX_MARGIN 12
10096 #define M_PIPE0_TX_MARGIN 0x7U
10097 #define V_PIPE0_TX_MARGIN(x) ((x) << S_PIPE0_TX_MARGIN)
10098 #define G_PIPE0_TX_MARGIN(x) (((x) >> S_PIPE0_TX_MARGIN) & M_PIPE0_TX_MARGIN)
10100 #define S_PIPE0_TX_DEEMPH 11
10101 #define V_PIPE0_TX_DEEMPH(x) ((x) << S_PIPE0_TX_DEEMPH)
10102 #define F_PIPE0_TX_DEEMPH V_PIPE0_TX_DEEMPH(1U)
10104 #define S_PIPE0_TX_DETECTRX 10
10105 #define V_PIPE0_TX_DETECTRX(x) ((x) << S_PIPE0_TX_DETECTRX)
10106 #define F_PIPE0_TX_DETECTRX V_PIPE0_TX_DETECTRX(1U)
10108 #define S_PIPE0_POWERDOWN 8
10109 #define M_PIPE0_POWERDOWN 0x3U
10110 #define V_PIPE0_POWERDOWN(x) ((x) << S_PIPE0_POWERDOWN)
10111 #define G_PIPE0_POWERDOWN(x) (((x) >> S_PIPE0_POWERDOWN) & M_PIPE0_POWERDOWN)
10113 #define S_PHY_MAC_PHYSTATUS 0
10114 #define M_PHY_MAC_PHYSTATUS 0xffU
10115 #define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS)
10116 #define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS)
10118 #define A_PCIE_PDEBUG_REG_0X1B 0x1b
10120 #define S_PIPE0_RX7_EQ_IN_PROG 31
10121 #define V_PIPE0_RX7_EQ_IN_PROG(x) ((x) << S_PIPE0_RX7_EQ_IN_PROG)
10122 #define F_PIPE0_RX7_EQ_IN_PROG V_PIPE0_RX7_EQ_IN_PROG(1U)
10124 #define S_PIPE0_RX7_EQ_INVLD_REQ 30
10125 #define V_PIPE0_RX7_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX7_EQ_INVLD_REQ)
10126 #define F_PIPE0_RX7_EQ_INVLD_REQ V_PIPE0_RX7_EQ_INVLD_REQ(1U)
10128 #define S_PIPE0_RX7_SYNCHEADER 28
10129 #define M_PIPE0_RX7_SYNCHEADER 0x3U
10130 #define V_PIPE0_RX7_SYNCHEADER(x) ((x) << S_PIPE0_RX7_SYNCHEADER)
10131 #define G_PIPE0_RX7_SYNCHEADER(x) (((x) >> S_PIPE0_RX7_SYNCHEADER) & M_PIPE0_RX7_SYNCHEADER)
10133 #define S_PIPE0_RX6_EQ_IN_PROG 27
10134 #define V_PIPE0_RX6_EQ_IN_PROG(x) ((x) << S_PIPE0_RX6_EQ_IN_PROG)
10135 #define F_PIPE0_RX6_EQ_IN_PROG V_PIPE0_RX6_EQ_IN_PROG(1U)
10137 #define S_PIPE0_RX6_EQ_INVLD_REQ 26
10138 #define V_PIPE0_RX6_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX6_EQ_INVLD_REQ)
10139 #define F_PIPE0_RX6_EQ_INVLD_REQ V_PIPE0_RX6_EQ_INVLD_REQ(1U)
10141 #define S_PIPE0_RX6_SYNCHEADER 24
10142 #define M_PIPE0_RX6_SYNCHEADER 0x3U
10143 #define V_PIPE0_RX6_SYNCHEADER(x) ((x) << S_PIPE0_RX6_SYNCHEADER)
10144 #define G_PIPE0_RX6_SYNCHEADER(x) (((x) >> S_PIPE0_RX6_SYNCHEADER) & M_PIPE0_RX6_SYNCHEADER)
10146 #define S_PIPE0_RX5_EQ_IN_PROG 23
10147 #define V_PIPE0_RX5_EQ_IN_PROG(x) ((x) << S_PIPE0_RX5_EQ_IN_PROG)
10148 #define F_PIPE0_RX5_EQ_IN_PROG V_PIPE0_RX5_EQ_IN_PROG(1U)
10150 #define S_PIPE0_RX5_EQ_INVLD_REQ 22
10151 #define V_PIPE0_RX5_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX5_EQ_INVLD_REQ)
10152 #define F_PIPE0_RX5_EQ_INVLD_REQ V_PIPE0_RX5_EQ_INVLD_REQ(1U)
10154 #define S_PIPE0_RX5_SYNCHEADER 20
10155 #define M_PIPE0_RX5_SYNCHEADER 0x3U
10156 #define V_PIPE0_RX5_SYNCHEADER(x) ((x) << S_PIPE0_RX5_SYNCHEADER)
10157 #define G_PIPE0_RX5_SYNCHEADER(x) (((x) >> S_PIPE0_RX5_SYNCHEADER) & M_PIPE0_RX5_SYNCHEADER)
10159 #define S_PIPE0_RX4_EQ_IN_PROG 19
10160 #define V_PIPE0_RX4_EQ_IN_PROG(x) ((x) << S_PIPE0_RX4_EQ_IN_PROG)
10161 #define F_PIPE0_RX4_EQ_IN_PROG V_PIPE0_RX4_EQ_IN_PROG(1U)
10163 #define S_PIPE0_RX4_EQ_INVLD_REQ 18
10164 #define V_PIPE0_RX4_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX4_EQ_INVLD_REQ)
10165 #define F_PIPE0_RX4_EQ_INVLD_REQ V_PIPE0_RX4_EQ_INVLD_REQ(1U)
10167 #define S_PIPE0_RX4_SYNCHEADER 16
10168 #define M_PIPE0_RX4_SYNCHEADER 0x3U
10169 #define V_PIPE0_RX4_SYNCHEADER(x) ((x) << S_PIPE0_RX4_SYNCHEADER)
10170 #define G_PIPE0_RX4_SYNCHEADER(x) (((x) >> S_PIPE0_RX4_SYNCHEADER) & M_PIPE0_RX4_SYNCHEADER)
10172 #define S_PIPE0_RX3_EQ_IN_PROG 15
10173 #define V_PIPE0_RX3_EQ_IN_PROG(x) ((x) << S_PIPE0_RX3_EQ_IN_PROG)
10174 #define F_PIPE0_RX3_EQ_IN_PROG V_PIPE0_RX3_EQ_IN_PROG(1U)
10176 #define S_PIPE0_RX3_EQ_INVLD_REQ 14
10177 #define V_PIPE0_RX3_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX3_EQ_INVLD_REQ)
10178 #define F_PIPE0_RX3_EQ_INVLD_REQ V_PIPE0_RX3_EQ_INVLD_REQ(1U)
10180 #define S_PIPE0_RX3_SYNCHEADER 12
10181 #define M_PIPE0_RX3_SYNCHEADER 0x3U
10182 #define V_PIPE0_RX3_SYNCHEADER(x) ((x) << S_PIPE0_RX3_SYNCHEADER)
10183 #define G_PIPE0_RX3_SYNCHEADER(x) (((x) >> S_PIPE0_RX3_SYNCHEADER) & M_PIPE0_RX3_SYNCHEADER)
10185 #define S_PIPE0_RX2_EQ_IN_PROG 11
10186 #define V_PIPE0_RX2_EQ_IN_PROG(x) ((x) << S_PIPE0_RX2_EQ_IN_PROG)
10187 #define F_PIPE0_RX2_EQ_IN_PROG V_PIPE0_RX2_EQ_IN_PROG(1U)
10189 #define S_PIPE0_RX2_EQ_INVLD_REQ 10
10190 #define V_PIPE0_RX2_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX2_EQ_INVLD_REQ)
10191 #define F_PIPE0_RX2_EQ_INVLD_REQ V_PIPE0_RX2_EQ_INVLD_REQ(1U)
10193 #define S_PIPE0_RX2_SYNCHEADER 8
10194 #define M_PIPE0_RX2_SYNCHEADER 0x3U
10195 #define V_PIPE0_RX2_SYNCHEADER(x) ((x) << S_PIPE0_RX2_SYNCHEADER)
10196 #define G_PIPE0_RX2_SYNCHEADER(x) (((x) >> S_PIPE0_RX2_SYNCHEADER) & M_PIPE0_RX2_SYNCHEADER)
10198 #define S_PIPE0_RX1_EQ_IN_PROG 7
10199 #define V_PIPE0_RX1_EQ_IN_PROG(x) ((x) << S_PIPE0_RX1_EQ_IN_PROG)
10200 #define F_PIPE0_RX1_EQ_IN_PROG V_PIPE0_RX1_EQ_IN_PROG(1U)
10202 #define S_PIPE0_RX1_EQ_INVLD_REQ 6
10203 #define V_PIPE0_RX1_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX1_EQ_INVLD_REQ)
10204 #define F_PIPE0_RX1_EQ_INVLD_REQ V_PIPE0_RX1_EQ_INVLD_REQ(1U)
10206 #define S_PIPE0_RX1_SYNCHEADER 4
10207 #define M_PIPE0_RX1_SYNCHEADER 0x3U
10208 #define V_PIPE0_RX1_SYNCHEADER(x) ((x) << S_PIPE0_RX1_SYNCHEADER)
10209 #define G_PIPE0_RX1_SYNCHEADER(x) (((x) >> S_PIPE0_RX1_SYNCHEADER) & M_PIPE0_RX1_SYNCHEADER)
10211 #define S_PIPE0_RX0_EQ_IN_PROG 3
10212 #define V_PIPE0_RX0_EQ_IN_PROG(x) ((x) << S_PIPE0_RX0_EQ_IN_PROG)
10213 #define F_PIPE0_RX0_EQ_IN_PROG V_PIPE0_RX0_EQ_IN_PROG(1U)
10215 #define S_PIPE0_RX0_EQ_INVLD_REQ 2
10216 #define V_PIPE0_RX0_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX0_EQ_INVLD_REQ)
10217 #define F_PIPE0_RX0_EQ_INVLD_REQ V_PIPE0_RX0_EQ_INVLD_REQ(1U)
10219 #define S_PIPE0_RX0_SYNCHEADER 0
10220 #define M_PIPE0_RX0_SYNCHEADER 0x3U
10221 #define V_PIPE0_RX0_SYNCHEADER(x) ((x) << S_PIPE0_RX0_SYNCHEADER)
10222 #define G_PIPE0_RX0_SYNCHEADER(x) (((x) >> S_PIPE0_RX0_SYNCHEADER) & M_PIPE0_RX0_SYNCHEADER)
10224 #define A_PCIE_PDEBUG_REG_0X1C 0x1c
10226 #define S_SI_REQVFID 24
10227 #define M_SI_REQVFID 0xffU
10228 #define V_SI_REQVFID(x) ((x) << S_SI_REQVFID)
10229 #define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID)
10231 #define S_SI_REQVEC 13
10232 #define M_SI_REQVEC 0x7ffU
10233 #define V_SI_REQVEC(x) ((x) << S_SI_REQVEC)
10234 #define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC)
10236 #define S_SI_REQTCVAL 10
10237 #define M_SI_REQTCVAL 0x7U
10238 #define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL)
10239 #define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL)
10241 #define S_SI_REQRDY 9
10242 #define V_SI_REQRDY(x) ((x) << S_SI_REQRDY)
10243 #define F_SI_REQRDY V_SI_REQRDY(1U)
10245 #define S_SI_REQVLD 8
10246 #define V_SI_REQVLD(x) ((x) << S_SI_REQVLD)
10247 #define F_SI_REQVLD V_SI_REQVLD(1U)
10250 #define M_T5_AI 0xffU
10251 #define V_T5_AI(x) ((x) << S_T5_AI)
10252 #define G_T5_AI(x) (((x) >> S_T5_AI) & M_T5_AI)
10254 #define A_PCIE_PDEBUG_REG_0X1D 0x1d
10257 #define V_GNTSI(x) ((x) << S_GNTSI)
10258 #define F_GNTSI V_GNTSI(1U)
10260 #define S_DROPINTFORFLR 30
10261 #define V_DROPINTFORFLR(x) ((x) << S_DROPINTFORFLR)
10262 #define F_DROPINTFORFLR V_DROPINTFORFLR(1U)
10265 #define M_SMARB 0x7U
10266 #define V_SMARB(x) ((x) << S_SMARB)
10267 #define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB)
10269 #define S_SMDEFR 24
10270 #define M_SMDEFR 0x7U
10271 #define V_SMDEFR(x) ((x) << S_SMDEFR)
10272 #define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR)
10274 #define S_SYS_INT 16
10275 #define M_SYS_INT 0xffU
10276 #define V_SYS_INT(x) ((x) << S_SYS_INT)
10277 #define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT)
10279 #define S_CFG_INTXCLR 8
10280 #define M_CFG_INTXCLR 0xffU
10281 #define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR)
10282 #define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR)
10284 #define S_PIO_INTXCLR 0
10285 #define M_PIO_INTXCLR 0xffU
10286 #define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR)
10287 #define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR)
10289 #define A_PCIE_PDEBUG_REG_0X1E 0x1e
10291 #define S_PLI_TABDATWREN 31
10292 #define V_PLI_TABDATWREN(x) ((x) << S_PLI_TABDATWREN)
10293 #define F_PLI_TABDATWREN V_PLI_TABDATWREN(1U)
10295 #define S_TAB_RDENA 30
10296 #define V_TAB_RDENA(x) ((x) << S_TAB_RDENA)
10297 #define F_TAB_RDENA V_TAB_RDENA(1U)
10299 #define S_TAB_RDENA2 19
10300 #define M_TAB_RDENA2 0x7ffU
10301 #define V_TAB_RDENA2(x) ((x) << S_TAB_RDENA2)
10302 #define G_TAB_RDENA2(x) (((x) >> S_TAB_RDENA2) & M_TAB_RDENA2)
10304 #define S_PLI_REQADDR 10
10305 #define M_PLI_REQADDR 0x1ffU
10306 #define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR)
10307 #define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR)
10309 #define S_PLI_REQVFID 2
10310 #define M_PLI_REQVFID 0xffU
10311 #define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID)
10312 #define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID)
10314 #define S_PLI_REQTABHIT 1
10315 #define V_PLI_REQTABHIT(x) ((x) << S_PLI_REQTABHIT)
10316 #define F_PLI_REQTABHIT V_PLI_REQTABHIT(1U)
10318 #define S_PLI_REQRDVLD 0
10319 #define V_PLI_REQRDVLD(x) ((x) << S_PLI_REQRDVLD)
10320 #define F_PLI_REQRDVLD V_PLI_REQRDVLD(1U)
10322 #define A_PCIE_PDEBUG_REG_0X1F 0x1f
10323 #define A_PCIE_PDEBUG_REG_0X20 0x20
10324 #define A_PCIE_PDEBUG_REG_0X21 0x21
10326 #define S_PLI_REQPBASTART 20
10327 #define M_PLI_REQPBASTART 0xfffU
10328 #define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART)
10329 #define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART)
10331 #define S_PLI_REQPBAEND 9
10332 #define M_PLI_REQPBAEND 0x7ffU
10333 #define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND)
10334 #define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND)
10336 #define S_T5_PLI_REQVFID 2
10337 #define M_T5_PLI_REQVFID 0x7fU
10338 #define V_T5_PLI_REQVFID(x) ((x) << S_T5_PLI_REQVFID)
10339 #define G_T5_PLI_REQVFID(x) (((x) >> S_T5_PLI_REQVFID) & M_T5_PLI_REQVFID)
10341 #define S_PLI_REQPBAHIT 1
10342 #define V_PLI_REQPBAHIT(x) ((x) << S_PLI_REQPBAHIT)
10343 #define F_PLI_REQPBAHIT V_PLI_REQPBAHIT(1U)
10345 #define A_PCIE_PDEBUG_REG_0X22 0x22
10347 #define S_GNTSI1 31
10348 #define V_GNTSI1(x) ((x) << S_GNTSI1)
10349 #define F_GNTSI1 V_GNTSI1(1U)
10351 #define S_GNTSI2 30
10352 #define V_GNTSI2(x) ((x) << S_GNTSI2)
10353 #define F_GNTSI2 V_GNTSI2(1U)
10355 #define S_GNTSI3 27
10356 #define M_GNTSI3 0x7U
10357 #define V_GNTSI3(x) ((x) << S_GNTSI3)
10358 #define G_GNTSI3(x) (((x) >> S_GNTSI3) & M_GNTSI3)
10360 #define S_GNTSI4 16
10361 #define M_GNTSI4 0x7ffU
10362 #define V_GNTSI4(x) ((x) << S_GNTSI4)
10363 #define G_GNTSI4(x) (((x) >> S_GNTSI4) & M_GNTSI4)
10366 #define M_GNTSI5 0xffU
10367 #define V_GNTSI5(x) ((x) << S_GNTSI5)
10368 #define G_GNTSI5(x) (((x) >> S_GNTSI5) & M_GNTSI5)
10371 #define V_GNTSI6(x) ((x) << S_GNTSI6)
10372 #define F_GNTSI6 V_GNTSI6(1U)
10375 #define V_GNTSI7(x) ((x) << S_GNTSI7)
10376 #define F_GNTSI7 V_GNTSI7(1U)
10379 #define V_GNTSI8(x) ((x) << S_GNTSI8)
10380 #define F_GNTSI8 V_GNTSI8(1U)
10383 #define V_GNTSI9(x) ((x) << S_GNTSI9)
10384 #define F_GNTSI9 V_GNTSI9(1U)
10387 #define V_GNTSIA(x) ((x) << S_GNTSIA)
10388 #define F_GNTSIA V_GNTSIA(1U)
10391 #define V_GNTAI(x) ((x) << S_GNTAI)
10392 #define F_GNTAI V_GNTAI(1U)
10395 #define V_GNTDB(x) ((x) << S_GNTDB)
10396 #define F_GNTDB V_GNTDB(1U)
10399 #define V_GNTDI(x) ((x) << S_GNTDI)
10400 #define F_GNTDI V_GNTDI(1U)
10402 #define A_PCIE_PDEBUG_REG_0X23 0x23
10404 #define S_DI_REQVLD 31
10405 #define V_DI_REQVLD(x) ((x) << S_DI_REQVLD)
10406 #define F_DI_REQVLD V_DI_REQVLD(1U)
10408 #define S_DI_REQRDY 30
10409 #define V_DI_REQRDY(x) ((x) << S_DI_REQRDY)
10410 #define F_DI_REQRDY V_DI_REQRDY(1U)
10412 #define S_DI_REQWREN 19
10413 #define M_DI_REQWREN 0x7ffU
10414 #define V_DI_REQWREN(x) ((x) << S_DI_REQWREN)
10415 #define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN)
10417 #define S_DI_REQMSIEN 18
10418 #define V_DI_REQMSIEN(x) ((x) << S_DI_REQMSIEN)
10419 #define F_DI_REQMSIEN V_DI_REQMSIEN(1U)
10421 #define S_DI_REQMSXEN 17
10422 #define V_DI_REQMSXEN(x) ((x) << S_DI_REQMSXEN)
10423 #define F_DI_REQMSXEN V_DI_REQMSXEN(1U)
10425 #define S_DI_REQMSXVFIDMSK 16
10426 #define V_DI_REQMSXVFIDMSK(x) ((x) << S_DI_REQMSXVFIDMSK)
10427 #define F_DI_REQMSXVFIDMSK V_DI_REQMSXVFIDMSK(1U)
10429 #define S_DI_REQWREN2 2
10430 #define M_DI_REQWREN2 0x3fffU
10431 #define V_DI_REQWREN2(x) ((x) << S_DI_REQWREN2)
10432 #define G_DI_REQWREN2(x) (((x) >> S_DI_REQWREN2) & M_DI_REQWREN2)
10434 #define S_DI_REQRDEN 1
10435 #define V_DI_REQRDEN(x) ((x) << S_DI_REQRDEN)
10436 #define F_DI_REQRDEN V_DI_REQRDEN(1U)
10438 #define S_DI_REQWREN3 0
10439 #define V_DI_REQWREN3(x) ((x) << S_DI_REQWREN3)
10440 #define F_DI_REQWREN3 V_DI_REQWREN3(1U)
10442 #define A_PCIE_PDEBUG_REG_0X24 0x24
10443 #define A_PCIE_PDEBUG_REG_0X25 0x25
10444 #define A_PCIE_PDEBUG_REG_0X26 0x26
10445 #define A_PCIE_PDEBUG_REG_0X27 0x27
10447 #define S_FID_STI_RSPVLD 31
10448 #define V_FID_STI_RSPVLD(x) ((x) << S_FID_STI_RSPVLD)
10449 #define F_FID_STI_RSPVLD V_FID_STI_RSPVLD(1U)
10451 #define S_TAB_STIRDENA 30
10452 #define V_TAB_STIRDENA(x) ((x) << S_TAB_STIRDENA)
10453 #define F_TAB_STIRDENA V_TAB_STIRDENA(1U)
10455 #define S_TAB_STIWRENA 29
10456 #define V_TAB_STIWRENA(x) ((x) << S_TAB_STIWRENA)
10457 #define F_TAB_STIWRENA V_TAB_STIWRENA(1U)
10459 #define S_TAB_STIRDENA2 18
10460 #define M_TAB_STIRDENA2 0x7ffU
10461 #define V_TAB_STIRDENA2(x) ((x) << S_TAB_STIRDENA2)
10462 #define G_TAB_STIRDENA2(x) (((x) >> S_TAB_STIRDENA2) & M_TAB_STIRDENA2)
10464 #define S_T5_PLI_REQTABHIT 7
10465 #define M_T5_PLI_REQTABHIT 0x7ffU
10466 #define V_T5_PLI_REQTABHIT(x) ((x) << S_T5_PLI_REQTABHIT)
10467 #define G_T5_PLI_REQTABHIT(x) (((x) >> S_T5_PLI_REQTABHIT) & M_T5_PLI_REQTABHIT)
10469 #define S_T5_GNTSI 0
10470 #define M_T5_GNTSI 0x7fU
10471 #define V_T5_GNTSI(x) ((x) << S_T5_GNTSI)
10472 #define G_T5_GNTSI(x) (((x) >> S_T5_GNTSI) & M_T5_GNTSI)
10474 #define A_PCIE_PDEBUG_REG_0X28 0x28
10476 #define S_PLI_REQWRVLD 31
10477 #define V_PLI_REQWRVLD(x) ((x) << S_PLI_REQWRVLD)
10478 #define F_PLI_REQWRVLD V_PLI_REQWRVLD(1U)
10480 #define S_T5_PLI_REQPBAHIT 30
10481 #define V_T5_PLI_REQPBAHIT(x) ((x) << S_T5_PLI_REQPBAHIT)
10482 #define F_T5_PLI_REQPBAHIT V_T5_PLI_REQPBAHIT(1U)
10484 #define S_PLI_TABADDRLWREN 29
10485 #define V_PLI_TABADDRLWREN(x) ((x) << S_PLI_TABADDRLWREN)
10486 #define F_PLI_TABADDRLWREN V_PLI_TABADDRLWREN(1U)
10488 #define S_PLI_TABADDRHWREN 28
10489 #define V_PLI_TABADDRHWREN(x) ((x) << S_PLI_TABADDRHWREN)
10490 #define F_PLI_TABADDRHWREN V_PLI_TABADDRHWREN(1U)
10492 #define S_T5_PLI_TABDATWREN 27
10493 #define V_T5_PLI_TABDATWREN(x) ((x) << S_T5_PLI_TABDATWREN)
10494 #define F_T5_PLI_TABDATWREN V_T5_PLI_TABDATWREN(1U)
10496 #define S_PLI_TABMSKWREN 26
10497 #define V_PLI_TABMSKWREN(x) ((x) << S_PLI_TABMSKWREN)
10498 #define F_PLI_TABMSKWREN V_PLI_TABMSKWREN(1U)
10500 #define S_AI_REQVLD 23
10501 #define M_AI_REQVLD 0x7U
10502 #define V_AI_REQVLD(x) ((x) << S_AI_REQVLD)
10503 #define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD)
10505 #define S_AI_REQVLD2 22
10506 #define V_AI_REQVLD2(x) ((x) << S_AI_REQVLD2)
10507 #define F_AI_REQVLD2 V_AI_REQVLD2(1U)
10509 #define S_AI_REQRDY 21
10510 #define V_AI_REQRDY(x) ((x) << S_AI_REQRDY)
10511 #define F_AI_REQRDY V_AI_REQRDY(1U)
10513 #define S_VEN_MSI_REQ_28 18
10514 #define M_VEN_MSI_REQ_28 0x7U
10515 #define V_VEN_MSI_REQ_28(x) ((x) << S_VEN_MSI_REQ_28)
10516 #define G_VEN_MSI_REQ_28(x) (((x) >> S_VEN_MSI_REQ_28) & M_VEN_MSI_REQ_28)
10518 #define S_VEN_MSI_REQ2 11
10519 #define M_VEN_MSI_REQ2 0x7fU
10520 #define V_VEN_MSI_REQ2(x) ((x) << S_VEN_MSI_REQ2)
10521 #define G_VEN_MSI_REQ2(x) (((x) >> S_VEN_MSI_REQ2) & M_VEN_MSI_REQ2)
10523 #define S_VEN_MSI_REQ3 6
10524 #define M_VEN_MSI_REQ3 0x1fU
10525 #define V_VEN_MSI_REQ3(x) ((x) << S_VEN_MSI_REQ3)
10526 #define G_VEN_MSI_REQ3(x) (((x) >> S_VEN_MSI_REQ3) & M_VEN_MSI_REQ3)
10528 #define S_VEN_MSI_REQ4 3
10529 #define M_VEN_MSI_REQ4 0x7U
10530 #define V_VEN_MSI_REQ4(x) ((x) << S_VEN_MSI_REQ4)
10531 #define G_VEN_MSI_REQ4(x) (((x) >> S_VEN_MSI_REQ4) & M_VEN_MSI_REQ4)
10533 #define S_VEN_MSI_REQ5 2
10534 #define V_VEN_MSI_REQ5(x) ((x) << S_VEN_MSI_REQ5)
10535 #define F_VEN_MSI_REQ5 V_VEN_MSI_REQ5(1U)
10537 #define S_VEN_MSI_GRANT 1
10538 #define V_VEN_MSI_GRANT(x) ((x) << S_VEN_MSI_GRANT)
10539 #define F_VEN_MSI_GRANT V_VEN_MSI_GRANT(1U)
10541 #define S_VEN_MSI_REQ6 0
10542 #define V_VEN_MSI_REQ6(x) ((x) << S_VEN_MSI_REQ6)
10543 #define F_VEN_MSI_REQ6 V_VEN_MSI_REQ6(1U)
10545 #define A_PCIE_PDEBUG_REG_0X29 0x29
10547 #define S_TRGT1_REQDATAVLD 16
10548 #define M_TRGT1_REQDATAVLD 0xffffU
10549 #define V_TRGT1_REQDATAVLD(x) ((x) << S_TRGT1_REQDATAVLD)
10550 #define G_TRGT1_REQDATAVLD(x) (((x) >> S_TRGT1_REQDATAVLD) & M_TRGT1_REQDATAVLD)
10552 #define S_TRGT1_REQDATAVLD2 12
10553 #define M_TRGT1_REQDATAVLD2 0xfU
10554 #define V_TRGT1_REQDATAVLD2(x) ((x) << S_TRGT1_REQDATAVLD2)
10555 #define G_TRGT1_REQDATAVLD2(x) (((x) >> S_TRGT1_REQDATAVLD2) & M_TRGT1_REQDATAVLD2)
10557 #define S_TRGT1_REQDATAVLD3 11
10558 #define V_TRGT1_REQDATAVLD3(x) ((x) << S_TRGT1_REQDATAVLD3)
10559 #define F_TRGT1_REQDATAVLD3 V_TRGT1_REQDATAVLD3(1U)
10561 #define S_TRGT1_REQDATAVLD4 10
10562 #define V_TRGT1_REQDATAVLD4(x) ((x) << S_TRGT1_REQDATAVLD4)
10563 #define F_TRGT1_REQDATAVLD4 V_TRGT1_REQDATAVLD4(1U)
10565 #define S_TRGT1_REQDATAVLD5 9
10566 #define V_TRGT1_REQDATAVLD5(x) ((x) << S_TRGT1_REQDATAVLD5)
10567 #define F_TRGT1_REQDATAVLD5 V_TRGT1_REQDATAVLD5(1U)
10569 #define S_TRGT1_REQDATAVLD6 8
10570 #define V_TRGT1_REQDATAVLD6(x) ((x) << S_TRGT1_REQDATAVLD6)
10571 #define F_TRGT1_REQDATAVLD6 V_TRGT1_REQDATAVLD6(1U)
10573 #define S_TRGT1_REQDATAVLD7 4
10574 #define M_TRGT1_REQDATAVLD7 0xfU
10575 #define V_TRGT1_REQDATAVLD7(x) ((x) << S_TRGT1_REQDATAVLD7)
10576 #define G_TRGT1_REQDATAVLD7(x) (((x) >> S_TRGT1_REQDATAVLD7) & M_TRGT1_REQDATAVLD7)
10578 #define S_TRGT1_REQDATAVLD8 2
10579 #define M_TRGT1_REQDATAVLD8 0x3U
10580 #define V_TRGT1_REQDATAVLD8(x) ((x) << S_TRGT1_REQDATAVLD8)
10581 #define G_TRGT1_REQDATAVLD8(x) (((x) >> S_TRGT1_REQDATAVLD8) & M_TRGT1_REQDATAVLD8)
10583 #define S_TRGT1_REQDATARDY 1
10584 #define V_TRGT1_REQDATARDY(x) ((x) << S_TRGT1_REQDATARDY)
10585 #define F_TRGT1_REQDATARDY V_TRGT1_REQDATARDY(1U)
10587 #define S_TRGT1_REQDATAVLD0 0
10588 #define V_TRGT1_REQDATAVLD0(x) ((x) << S_TRGT1_REQDATAVLD0)
10589 #define F_TRGT1_REQDATAVLD0 V_TRGT1_REQDATAVLD0(1U)
10591 #define A_PCIE_PDEBUG_REG_0X2A 0x2a
10592 #define A_PCIE_PDEBUG_REG_0X2B 0x2b
10594 #define S_RADM_TRGT1_ADDR 20
10595 #define M_RADM_TRGT1_ADDR 0xfffU
10596 #define V_RADM_TRGT1_ADDR(x) ((x) << S_RADM_TRGT1_ADDR)
10597 #define G_RADM_TRGT1_ADDR(x) (((x) >> S_RADM_TRGT1_ADDR) & M_RADM_TRGT1_ADDR)
10599 #define S_RADM_TRGT1_DWEN 16
10600 #define M_RADM_TRGT1_DWEN 0xfU
10601 #define V_RADM_TRGT1_DWEN(x) ((x) << S_RADM_TRGT1_DWEN)
10602 #define G_RADM_TRGT1_DWEN(x) (((x) >> S_RADM_TRGT1_DWEN) & M_RADM_TRGT1_DWEN)
10604 #define S_RADM_TRGT1_FMT 14
10605 #define M_RADM_TRGT1_FMT 0x3U
10606 #define V_RADM_TRGT1_FMT(x) ((x) << S_RADM_TRGT1_FMT)
10607 #define G_RADM_TRGT1_FMT(x) (((x) >> S_RADM_TRGT1_FMT) & M_RADM_TRGT1_FMT)
10609 #define S_RADM_TRGT1_TYPE 9
10610 #define M_RADM_TRGT1_TYPE 0x1fU
10611 #define V_RADM_TRGT1_TYPE(x) ((x) << S_RADM_TRGT1_TYPE)
10612 #define G_RADM_TRGT1_TYPE(x) (((x) >> S_RADM_TRGT1_TYPE) & M_RADM_TRGT1_TYPE)
10614 #define S_RADM_TRGT1_IN_MEMBAR_RANGE 6
10615 #define M_RADM_TRGT1_IN_MEMBAR_RANGE 0x7U
10616 #define V_RADM_TRGT1_IN_MEMBAR_RANGE(x) ((x) << S_RADM_TRGT1_IN_MEMBAR_RANGE)
10617 #define G_RADM_TRGT1_IN_MEMBAR_RANGE(x) (((x) >> S_RADM_TRGT1_IN_MEMBAR_RANGE) & M_RADM_TRGT1_IN_MEMBAR_RANGE)
10619 #define S_RADM_TRGT1_ECRC_ERR 5
10620 #define V_RADM_TRGT1_ECRC_ERR(x) ((x) << S_RADM_TRGT1_ECRC_ERR)
10621 #define F_RADM_TRGT1_ECRC_ERR V_RADM_TRGT1_ECRC_ERR(1U)
10623 #define S_RADM_TRGT1_DLLP_ABORT 4
10624 #define V_RADM_TRGT1_DLLP_ABORT(x) ((x) << S_RADM_TRGT1_DLLP_ABORT)
10625 #define F_RADM_TRGT1_DLLP_ABORT V_RADM_TRGT1_DLLP_ABORT(1U)
10627 #define S_RADM_TRGT1_TLP_ABORT 3
10628 #define V_RADM_TRGT1_TLP_ABORT(x) ((x) << S_RADM_TRGT1_TLP_ABORT)
10629 #define F_RADM_TRGT1_TLP_ABORT V_RADM_TRGT1_TLP_ABORT(1U)
10631 #define S_RADM_TRGT1_EOT 2
10632 #define V_RADM_TRGT1_EOT(x) ((x) << S_RADM_TRGT1_EOT)
10633 #define F_RADM_TRGT1_EOT V_RADM_TRGT1_EOT(1U)
10635 #define S_RADM_TRGT1_DV_2B 1
10636 #define V_RADM_TRGT1_DV_2B(x) ((x) << S_RADM_TRGT1_DV_2B)
10637 #define F_RADM_TRGT1_DV_2B V_RADM_TRGT1_DV_2B(1U)
10639 #define S_RADM_TRGT1_HV_2B 0
10640 #define V_RADM_TRGT1_HV_2B(x) ((x) << S_RADM_TRGT1_HV_2B)
10641 #define F_RADM_TRGT1_HV_2B V_RADM_TRGT1_HV_2B(1U)
10643 #define A_PCIE_PDEBUG_REG_0X2C 0x2c
10645 #define S_STATEMPIO 29
10646 #define M_STATEMPIO 0x7U
10647 #define V_STATEMPIO(x) ((x) << S_STATEMPIO)
10648 #define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO)
10650 #define S_STATECPL 25
10651 #define M_STATECPL 0xfU
10652 #define V_STATECPL(x) ((x) << S_STATECPL)
10653 #define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL)
10655 #define S_STATEALIN 22
10656 #define M_STATEALIN 0x7U
10657 #define V_STATEALIN(x) ((x) << S_STATEALIN)
10658 #define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN)
10660 #define S_STATEPL 19
10661 #define M_STATEPL 0x7U
10662 #define V_STATEPL(x) ((x) << S_STATEPL)
10663 #define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL)
10665 #define S_STATEMARSP 18
10666 #define V_STATEMARSP(x) ((x) << S_STATEMARSP)
10667 #define F_STATEMARSP V_STATEMARSP(1U)
10669 #define S_MA_TAGSINUSE 11
10670 #define M_MA_TAGSINUSE 0x7fU
10671 #define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE)
10672 #define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE)
10674 #define S_RADM_TRGT1_HSRDY 10
10675 #define V_RADM_TRGT1_HSRDY(x) ((x) << S_RADM_TRGT1_HSRDY)
10676 #define F_RADM_TRGT1_HSRDY V_RADM_TRGT1_HSRDY(1U)
10678 #define S_RADM_TRGT1_DSRDY 9
10679 #define V_RADM_TRGT1_DSRDY(x) ((x) << S_RADM_TRGT1_DSRDY)
10680 #define F_RADM_TRGT1_DSRDY V_RADM_TRGT1_DSRDY(1U)
10682 #define S_ALIND_REQWRDATAVLD 8
10683 #define V_ALIND_REQWRDATAVLD(x) ((x) << S_ALIND_REQWRDATAVLD)
10684 #define F_ALIND_REQWRDATAVLD V_ALIND_REQWRDATAVLD(1U)
10686 #define S_FID_LKUPWRHDRVLD 7
10687 #define V_FID_LKUPWRHDRVLD(x) ((x) << S_FID_LKUPWRHDRVLD)
10688 #define F_FID_LKUPWRHDRVLD V_FID_LKUPWRHDRVLD(1U)
10690 #define S_MPIO_WRVLD 6
10691 #define V_MPIO_WRVLD(x) ((x) << S_MPIO_WRVLD)
10692 #define F_MPIO_WRVLD V_MPIO_WRVLD(1U)
10694 #define S_TRGT1_RADM_HALT 5
10695 #define V_TRGT1_RADM_HALT(x) ((x) << S_TRGT1_RADM_HALT)
10696 #define F_TRGT1_RADM_HALT V_TRGT1_RADM_HALT(1U)
10698 #define S_RADM_TRGT1_DV_2C 4
10699 #define V_RADM_TRGT1_DV_2C(x) ((x) << S_RADM_TRGT1_DV_2C)
10700 #define F_RADM_TRGT1_DV_2C V_RADM_TRGT1_DV_2C(1U)
10702 #define S_RADM_TRGT1_DV_2C_2 3
10703 #define V_RADM_TRGT1_DV_2C_2(x) ((x) << S_RADM_TRGT1_DV_2C_2)
10704 #define F_RADM_TRGT1_DV_2C_2 V_RADM_TRGT1_DV_2C_2(1U)
10706 #define S_RADM_TRGT1_TLP_ABORT_2C 2
10707 #define V_RADM_TRGT1_TLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_TLP_ABORT_2C)
10708 #define F_RADM_TRGT1_TLP_ABORT_2C V_RADM_TRGT1_TLP_ABORT_2C(1U)
10710 #define S_RADM_TRGT1_DLLP_ABORT_2C 1
10711 #define V_RADM_TRGT1_DLLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_DLLP_ABORT_2C)
10712 #define F_RADM_TRGT1_DLLP_ABORT_2C V_RADM_TRGT1_DLLP_ABORT_2C(1U)
10714 #define S_RADM_TRGT1_ECRC_ERR_2C 0
10715 #define V_RADM_TRGT1_ECRC_ERR_2C(x) ((x) << S_RADM_TRGT1_ECRC_ERR_2C)
10716 #define F_RADM_TRGT1_ECRC_ERR_2C V_RADM_TRGT1_ECRC_ERR_2C(1U)
10718 #define A_PCIE_PDEBUG_REG_0X2D 0x2d
10720 #define S_RADM_TRGT1_HV_2D 31
10721 #define V_RADM_TRGT1_HV_2D(x) ((x) << S_RADM_TRGT1_HV_2D)
10722 #define F_RADM_TRGT1_HV_2D V_RADM_TRGT1_HV_2D(1U)
10724 #define S_RADM_TRGT1_DV_2D 30
10725 #define V_RADM_TRGT1_DV_2D(x) ((x) << S_RADM_TRGT1_DV_2D)
10726 #define F_RADM_TRGT1_DV_2D V_RADM_TRGT1_DV_2D(1U)
10728 #define S_RADM_TRGT1_HV2 23
10729 #define M_RADM_TRGT1_HV2 0x7fU
10730 #define V_RADM_TRGT1_HV2(x) ((x) << S_RADM_TRGT1_HV2)
10731 #define G_RADM_TRGT1_HV2(x) (((x) >> S_RADM_TRGT1_HV2) & M_RADM_TRGT1_HV2)
10733 #define S_RADM_TRGT1_HV3 20
10734 #define M_RADM_TRGT1_HV3 0x7U
10735 #define V_RADM_TRGT1_HV3(x) ((x) << S_RADM_TRGT1_HV3)
10736 #define G_RADM_TRGT1_HV3(x) (((x) >> S_RADM_TRGT1_HV3) & M_RADM_TRGT1_HV3)
10738 #define S_RADM_TRGT1_HV4 16
10739 #define M_RADM_TRGT1_HV4 0xfU
10740 #define V_RADM_TRGT1_HV4(x) ((x) << S_RADM_TRGT1_HV4)
10741 #define G_RADM_TRGT1_HV4(x) (((x) >> S_RADM_TRGT1_HV4) & M_RADM_TRGT1_HV4)
10743 #define S_RADM_TRGT1_HV5 12
10744 #define M_RADM_TRGT1_HV5 0xfU
10745 #define V_RADM_TRGT1_HV5(x) ((x) << S_RADM_TRGT1_HV5)
10746 #define G_RADM_TRGT1_HV5(x) (((x) >> S_RADM_TRGT1_HV5) & M_RADM_TRGT1_HV5)
10748 #define S_RADM_TRGT1_HV6 11
10749 #define V_RADM_TRGT1_HV6(x) ((x) << S_RADM_TRGT1_HV6)
10750 #define F_RADM_TRGT1_HV6 V_RADM_TRGT1_HV6(1U)
10752 #define S_RADM_TRGT1_HV7 10
10753 #define V_RADM_TRGT1_HV7(x) ((x) << S_RADM_TRGT1_HV7)
10754 #define F_RADM_TRGT1_HV7 V_RADM_TRGT1_HV7(1U)
10756 #define S_RADM_TRGT1_HV8 7
10757 #define M_RADM_TRGT1_HV8 0x7U
10758 #define V_RADM_TRGT1_HV8(x) ((x) << S_RADM_TRGT1_HV8)
10759 #define G_RADM_TRGT1_HV8(x) (((x) >> S_RADM_TRGT1_HV8) & M_RADM_TRGT1_HV8)
10761 #define S_RADM_TRGT1_HV9 6
10762 #define V_RADM_TRGT1_HV9(x) ((x) << S_RADM_TRGT1_HV9)
10763 #define F_RADM_TRGT1_HV9 V_RADM_TRGT1_HV9(1U)
10765 #define S_RADM_TRGT1_HVA 5
10766 #define V_RADM_TRGT1_HVA(x) ((x) << S_RADM_TRGT1_HVA)
10767 #define F_RADM_TRGT1_HVA V_RADM_TRGT1_HVA(1U)
10769 #define S_RADM_TRGT1_DSRDY_2D 4
10770 #define V_RADM_TRGT1_DSRDY_2D(x) ((x) << S_RADM_TRGT1_DSRDY_2D)
10771 #define F_RADM_TRGT1_DSRDY_2D V_RADM_TRGT1_DSRDY_2D(1U)
10773 #define S_RADM_TRGT1_WRCNT 0
10774 #define M_RADM_TRGT1_WRCNT 0xfU
10775 #define V_RADM_TRGT1_WRCNT(x) ((x) << S_RADM_TRGT1_WRCNT)
10776 #define G_RADM_TRGT1_WRCNT(x) (((x) >> S_RADM_TRGT1_WRCNT) & M_RADM_TRGT1_WRCNT)
10778 #define A_PCIE_PDEBUG_REG_0X2E 0x2e
10780 #define S_RADM_TRGT1_HV_2E 30
10781 #define M_RADM_TRGT1_HV_2E 0x3U
10782 #define V_RADM_TRGT1_HV_2E(x) ((x) << S_RADM_TRGT1_HV_2E)
10783 #define G_RADM_TRGT1_HV_2E(x) (((x) >> S_RADM_TRGT1_HV_2E) & M_RADM_TRGT1_HV_2E)
10785 #define S_RADM_TRGT1_HV_2E_2 20
10786 #define M_RADM_TRGT1_HV_2E_2 0x3ffU
10787 #define V_RADM_TRGT1_HV_2E_2(x) ((x) << S_RADM_TRGT1_HV_2E_2)
10788 #define G_RADM_TRGT1_HV_2E_2(x) (((x) >> S_RADM_TRGT1_HV_2E_2) & M_RADM_TRGT1_HV_2E_2)
10790 #define S_RADM_TRGT1_HV_WE_3 12
10791 #define M_RADM_TRGT1_HV_WE_3 0xffU
10792 #define V_RADM_TRGT1_HV_WE_3(x) ((x) << S_RADM_TRGT1_HV_WE_3)
10793 #define G_RADM_TRGT1_HV_WE_3(x) (((x) >> S_RADM_TRGT1_HV_WE_3) & M_RADM_TRGT1_HV_WE_3)
10795 #define S_ALIN_REQDATAVLD4 8
10796 #define M_ALIN_REQDATAVLD4 0xfU
10797 #define V_ALIN_REQDATAVLD4(x) ((x) << S_ALIN_REQDATAVLD4)
10798 #define G_ALIN_REQDATAVLD4(x) (((x) >> S_ALIN_REQDATAVLD4) & M_ALIN_REQDATAVLD4)
10800 #define S_ALIN_REQDATAVLD5 7
10801 #define V_ALIN_REQDATAVLD5(x) ((x) << S_ALIN_REQDATAVLD5)
10802 #define F_ALIN_REQDATAVLD5 V_ALIN_REQDATAVLD5(1U)
10804 #define S_ALIN_REQDATAVLD6 6
10805 #define V_ALIN_REQDATAVLD6(x) ((x) << S_ALIN_REQDATAVLD6)
10806 #define F_ALIN_REQDATAVLD6 V_ALIN_REQDATAVLD6(1U)
10808 #define S_ALIN_REQDATAVLD7 4
10809 #define M_ALIN_REQDATAVLD7 0x3U
10810 #define V_ALIN_REQDATAVLD7(x) ((x) << S_ALIN_REQDATAVLD7)
10811 #define G_ALIN_REQDATAVLD7(x) (((x) >> S_ALIN_REQDATAVLD7) & M_ALIN_REQDATAVLD7)
10813 #define S_ALIN_REQDATAVLD8 3
10814 #define V_ALIN_REQDATAVLD8(x) ((x) << S_ALIN_REQDATAVLD8)
10815 #define F_ALIN_REQDATAVLD8 V_ALIN_REQDATAVLD8(1U)
10817 #define S_ALIN_REQDATAVLD9 2
10818 #define V_ALIN_REQDATAVLD9(x) ((x) << S_ALIN_REQDATAVLD9)
10819 #define F_ALIN_REQDATAVLD9 V_ALIN_REQDATAVLD9(1U)
10821 #define S_ALIN_REQDATARDY 1
10822 #define V_ALIN_REQDATARDY(x) ((x) << S_ALIN_REQDATARDY)
10823 #define F_ALIN_REQDATARDY V_ALIN_REQDATARDY(1U)
10825 #define S_ALIN_REQDATAVLDA 0
10826 #define V_ALIN_REQDATAVLDA(x) ((x) << S_ALIN_REQDATAVLDA)
10827 #define F_ALIN_REQDATAVLDA V_ALIN_REQDATAVLDA(1U)
10829 #define A_PCIE_PDEBUG_REG_0X2F 0x2f
10830 #define A_PCIE_PDEBUG_REG_0X30 0x30
10832 #define S_RADM_TRGT1_HV_30 25
10833 #define M_RADM_TRGT1_HV_30 0x7fU
10834 #define V_RADM_TRGT1_HV_30(x) ((x) << S_RADM_TRGT1_HV_30)
10835 #define G_RADM_TRGT1_HV_30(x) (((x) >> S_RADM_TRGT1_HV_30) & M_RADM_TRGT1_HV_30)
10837 #define S_PIO_WRCNT 15
10838 #define M_PIO_WRCNT 0x3ffU
10839 #define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT)
10840 #define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT)
10842 #define S_ALIND_REQWRCNT 12
10843 #define M_ALIND_REQWRCNT 0x7U
10844 #define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT)
10845 #define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT)
10847 #define S_FID_LKUPWRCNT 9
10848 #define M_FID_LKUPWRCNT 0x7U
10849 #define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT)
10850 #define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT)
10852 #define S_ALIND_REQRDDATAVLD 8
10853 #define V_ALIND_REQRDDATAVLD(x) ((x) << S_ALIND_REQRDDATAVLD)
10854 #define F_ALIND_REQRDDATAVLD V_ALIND_REQRDDATAVLD(1U)
10856 #define S_ALIND_REQRDDATARDY 7
10857 #define V_ALIND_REQRDDATARDY(x) ((x) << S_ALIND_REQRDDATARDY)
10858 #define F_ALIND_REQRDDATARDY V_ALIND_REQRDDATARDY(1U)
10860 #define S_ALIND_REQRDDATAVLD2 6
10861 #define V_ALIND_REQRDDATAVLD2(x) ((x) << S_ALIND_REQRDDATAVLD2)
10862 #define F_ALIND_REQRDDATAVLD2 V_ALIND_REQRDDATAVLD2(1U)
10864 #define S_ALIND_REQWRDATAVLD3 3
10865 #define M_ALIND_REQWRDATAVLD3 0x7U
10866 #define V_ALIND_REQWRDATAVLD3(x) ((x) << S_ALIND_REQWRDATAVLD3)
10867 #define G_ALIND_REQWRDATAVLD3(x) (((x) >> S_ALIND_REQWRDATAVLD3) & M_ALIND_REQWRDATAVLD3)
10869 #define S_ALIND_REQWRDATAVLD4 2
10870 #define V_ALIND_REQWRDATAVLD4(x) ((x) << S_ALIND_REQWRDATAVLD4)
10871 #define F_ALIND_REQWRDATAVLD4 V_ALIND_REQWRDATAVLD4(1U)
10873 #define S_ALIND_REQWRDATARDYOPEN 1
10874 #define V_ALIND_REQWRDATARDYOPEN(x) ((x) << S_ALIND_REQWRDATARDYOPEN)
10875 #define F_ALIND_REQWRDATARDYOPEN V_ALIND_REQWRDATARDYOPEN(1U)
10877 #define S_ALIND_REQWRDATAVLD5 0
10878 #define V_ALIND_REQWRDATAVLD5(x) ((x) << S_ALIND_REQWRDATAVLD5)
10879 #define F_ALIND_REQWRDATAVLD5 V_ALIND_REQWRDATAVLD5(1U)
10881 #define A_PCIE_PDEBUG_REG_0X31 0x31
10882 #define A_PCIE_PDEBUG_REG_0X32 0x32
10883 #define A_PCIE_PDEBUG_REG_0X33 0x33
10884 #define A_PCIE_PDEBUG_REG_0X34 0x34
10885 #define A_PCIE_PDEBUG_REG_0X35 0x35
10887 #define S_T5_MPIO_WRVLD 19
10888 #define M_T5_MPIO_WRVLD 0x1fffU
10889 #define V_T5_MPIO_WRVLD(x) ((x) << S_T5_MPIO_WRVLD)
10890 #define G_T5_MPIO_WRVLD(x) (((x) >> S_T5_MPIO_WRVLD) & M_T5_MPIO_WRVLD)
10892 #define S_FID_LKUPRDHDRVLD 18
10893 #define V_FID_LKUPRDHDRVLD(x) ((x) << S_FID_LKUPRDHDRVLD)
10894 #define F_FID_LKUPRDHDRVLD V_FID_LKUPRDHDRVLD(1U)
10896 #define S_FID_LKUPRDHDRVLD2 17
10897 #define V_FID_LKUPRDHDRVLD2(x) ((x) << S_FID_LKUPRDHDRVLD2)
10898 #define F_FID_LKUPRDHDRVLD2 V_FID_LKUPRDHDRVLD2(1U)
10900 #define S_FID_LKUPRDHDRVLD3 16
10901 #define V_FID_LKUPRDHDRVLD3(x) ((x) << S_FID_LKUPRDHDRVLD3)
10902 #define F_FID_LKUPRDHDRVLD3 V_FID_LKUPRDHDRVLD3(1U)
10904 #define S_FID_LKUPRDHDRVLD4 15
10905 #define V_FID_LKUPRDHDRVLD4(x) ((x) << S_FID_LKUPRDHDRVLD4)
10906 #define F_FID_LKUPRDHDRVLD4 V_FID_LKUPRDHDRVLD4(1U)
10908 #define S_FID_LKUPRDHDRVLD5 14
10909 #define V_FID_LKUPRDHDRVLD5(x) ((x) << S_FID_LKUPRDHDRVLD5)
10910 #define F_FID_LKUPRDHDRVLD5 V_FID_LKUPRDHDRVLD5(1U)
10912 #define S_FID_LKUPRDHDRVLD6 13
10913 #define V_FID_LKUPRDHDRVLD6(x) ((x) << S_FID_LKUPRDHDRVLD6)
10914 #define F_FID_LKUPRDHDRVLD6 V_FID_LKUPRDHDRVLD6(1U)
10916 #define S_FID_LKUPRDHDRVLD7 12
10917 #define V_FID_LKUPRDHDRVLD7(x) ((x) << S_FID_LKUPRDHDRVLD7)
10918 #define F_FID_LKUPRDHDRVLD7 V_FID_LKUPRDHDRVLD7(1U)
10920 #define S_FID_LKUPRDHDRVLD8 11
10921 #define V_FID_LKUPRDHDRVLD8(x) ((x) << S_FID_LKUPRDHDRVLD8)
10922 #define F_FID_LKUPRDHDRVLD8 V_FID_LKUPRDHDRVLD8(1U)
10924 #define S_FID_LKUPRDHDRVLD9 10
10925 #define V_FID_LKUPRDHDRVLD9(x) ((x) << S_FID_LKUPRDHDRVLD9)
10926 #define F_FID_LKUPRDHDRVLD9 V_FID_LKUPRDHDRVLD9(1U)
10928 #define S_FID_LKUPRDHDRVLDA 9
10929 #define V_FID_LKUPRDHDRVLDA(x) ((x) << S_FID_LKUPRDHDRVLDA)
10930 #define F_FID_LKUPRDHDRVLDA V_FID_LKUPRDHDRVLDA(1U)
10932 #define S_FID_LKUPRDHDRVLDB 8
10933 #define V_FID_LKUPRDHDRVLDB(x) ((x) << S_FID_LKUPRDHDRVLDB)
10934 #define F_FID_LKUPRDHDRVLDB V_FID_LKUPRDHDRVLDB(1U)
10936 #define S_FID_LKUPRDHDRVLDC 7
10937 #define V_FID_LKUPRDHDRVLDC(x) ((x) << S_FID_LKUPRDHDRVLDC)
10938 #define F_FID_LKUPRDHDRVLDC V_FID_LKUPRDHDRVLDC(1U)
10940 #define S_MPIO_WRVLD1 6
10941 #define V_MPIO_WRVLD1(x) ((x) << S_MPIO_WRVLD1)
10942 #define F_MPIO_WRVLD1 V_MPIO_WRVLD1(1U)
10944 #define S_MPIO_WRVLD2 5
10945 #define V_MPIO_WRVLD2(x) ((x) << S_MPIO_WRVLD2)
10946 #define F_MPIO_WRVLD2 V_MPIO_WRVLD2(1U)
10948 #define S_MPIO_WRVLD3 4
10949 #define V_MPIO_WRVLD3(x) ((x) << S_MPIO_WRVLD3)
10950 #define F_MPIO_WRVLD3 V_MPIO_WRVLD3(1U)
10952 #define S_MPIO_WRVLD4 0
10953 #define M_MPIO_WRVLD4 0xfU
10954 #define V_MPIO_WRVLD4(x) ((x) << S_MPIO_WRVLD4)
10955 #define G_MPIO_WRVLD4(x) (((x) >> S_MPIO_WRVLD4) & M_MPIO_WRVLD4)
10957 #define A_PCIE_PDEBUG_REG_0X36 0x36
10958 #define A_PCIE_PDEBUG_REG_0X37 0x37
10959 #define A_PCIE_PDEBUG_REG_0X38 0x38
10960 #define A_PCIE_PDEBUG_REG_0X39 0x39
10961 #define A_PCIE_PDEBUG_REG_0X3A 0x3a
10963 #define S_CLIENT0_TLP_VFUNC_ACTIVE 31
10964 #define V_CLIENT0_TLP_VFUNC_ACTIVE(x) ((x) << S_CLIENT0_TLP_VFUNC_ACTIVE)
10965 #define F_CLIENT0_TLP_VFUNC_ACTIVE V_CLIENT0_TLP_VFUNC_ACTIVE(1U)
10967 #define S_CLIENT0_TLP_VFUNC_NUM 24
10968 #define M_CLIENT0_TLP_VFUNC_NUM 0x7fU
10969 #define V_CLIENT0_TLP_VFUNC_NUM(x) ((x) << S_CLIENT0_TLP_VFUNC_NUM)
10970 #define G_CLIENT0_TLP_VFUNC_NUM(x) (((x) >> S_CLIENT0_TLP_VFUNC_NUM) & M_CLIENT0_TLP_VFUNC_NUM)
10972 #define S_CLIENT0_TLP_FUNC_NUM 21
10973 #define M_CLIENT0_TLP_FUNC_NUM 0x7U
10974 #define V_CLIENT0_TLP_FUNC_NUM(x) ((x) << S_CLIENT0_TLP_FUNC_NUM)
10975 #define G_CLIENT0_TLP_FUNC_NUM(x) (((x) >> S_CLIENT0_TLP_FUNC_NUM) & M_CLIENT0_TLP_FUNC_NUM)
10977 #define S_CLIENT0_TLP_BYTE_EN 13
10978 #define M_CLIENT0_TLP_BYTE_EN 0xffU
10979 #define V_CLIENT0_TLP_BYTE_EN(x) ((x) << S_CLIENT0_TLP_BYTE_EN)
10980 #define G_CLIENT0_TLP_BYTE_EN(x) (((x) >> S_CLIENT0_TLP_BYTE_EN) & M_CLIENT0_TLP_BYTE_EN)
10982 #define S_CLIENT0_TLP_BYTE_LEN 0
10983 #define M_CLIENT0_TLP_BYTE_LEN 0x1fffU
10984 #define V_CLIENT0_TLP_BYTE_LEN(x) ((x) << S_CLIENT0_TLP_BYTE_LEN)
10985 #define G_CLIENT0_TLP_BYTE_LEN(x) (((x) >> S_CLIENT0_TLP_BYTE_LEN) & M_CLIENT0_TLP_BYTE_LEN)
10987 #define A_PCIE_PDEBUG_REG_0X3B 0x3b
10989 #define S_XADM_CLIENT0_HALT 31
10990 #define V_XADM_CLIENT0_HALT(x) ((x) << S_XADM_CLIENT0_HALT)
10991 #define F_XADM_CLIENT0_HALT V_XADM_CLIENT0_HALT(1U)
10993 #define S_CLIENT0_TLP_DV 30
10994 #define V_CLIENT0_TLP_DV(x) ((x) << S_CLIENT0_TLP_DV)
10995 #define F_CLIENT0_TLP_DV V_CLIENT0_TLP_DV(1U)
10997 #define S_CLIENT0_ADDR_ALIGN_EN 29
10998 #define V_CLIENT0_ADDR_ALIGN_EN(x) ((x) << S_CLIENT0_ADDR_ALIGN_EN)
10999 #define F_CLIENT0_ADDR_ALIGN_EN V_CLIENT0_ADDR_ALIGN_EN(1U)
11001 #define S_CLIENT0_CPL_BCM 28
11002 #define V_CLIENT0_CPL_BCM(x) ((x) << S_CLIENT0_CPL_BCM)
11003 #define F_CLIENT0_CPL_BCM V_CLIENT0_CPL_BCM(1U)
11005 #define S_CLIENT0_TLP_EP 27
11006 #define V_CLIENT0_TLP_EP(x) ((x) << S_CLIENT0_TLP_EP)
11007 #define F_CLIENT0_TLP_EP V_CLIENT0_TLP_EP(1U)
11009 #define S_CLIENT0_CPL_STATUS 24
11010 #define M_CLIENT0_CPL_STATUS 0x7U
11011 #define V_CLIENT0_CPL_STATUS(x) ((x) << S_CLIENT0_CPL_STATUS)
11012 #define G_CLIENT0_CPL_STATUS(x) (((x) >> S_CLIENT0_CPL_STATUS) & M_CLIENT0_CPL_STATUS)
11014 #define S_CLIENT0_TLP_TD 23
11015 #define V_CLIENT0_TLP_TD(x) ((x) << S_CLIENT0_TLP_TD)
11016 #define F_CLIENT0_TLP_TD V_CLIENT0_TLP_TD(1U)
11018 #define S_CLIENT0_TLP_TYPE 18
11019 #define M_CLIENT0_TLP_TYPE 0x1fU
11020 #define V_CLIENT0_TLP_TYPE(x) ((x) << S_CLIENT0_TLP_TYPE)
11021 #define G_CLIENT0_TLP_TYPE(x) (((x) >> S_CLIENT0_TLP_TYPE) & M_CLIENT0_TLP_TYPE)
11023 #define S_CLIENT0_TLP_FMT 16
11024 #define M_CLIENT0_TLP_FMT 0x3U
11025 #define V_CLIENT0_TLP_FMT(x) ((x) << S_CLIENT0_TLP_FMT)
11026 #define G_CLIENT0_TLP_FMT(x) (((x) >> S_CLIENT0_TLP_FMT) & M_CLIENT0_TLP_FMT)
11028 #define S_CLIENT0_TLP_BAD_EOT 15
11029 #define V_CLIENT0_TLP_BAD_EOT(x) ((x) << S_CLIENT0_TLP_BAD_EOT)
11030 #define F_CLIENT0_TLP_BAD_EOT V_CLIENT0_TLP_BAD_EOT(1U)
11032 #define S_CLIENT0_TLP_EOT 14
11033 #define V_CLIENT0_TLP_EOT(x) ((x) << S_CLIENT0_TLP_EOT)
11034 #define F_CLIENT0_TLP_EOT V_CLIENT0_TLP_EOT(1U)
11036 #define S_CLIENT0_TLP_ATTR 11
11037 #define M_CLIENT0_TLP_ATTR 0x7U
11038 #define V_CLIENT0_TLP_ATTR(x) ((x) << S_CLIENT0_TLP_ATTR)
11039 #define G_CLIENT0_TLP_ATTR(x) (((x) >> S_CLIENT0_TLP_ATTR) & M_CLIENT0_TLP_ATTR)
11041 #define S_CLIENT0_TLP_TC 8
11042 #define M_CLIENT0_TLP_TC 0x7U
11043 #define V_CLIENT0_TLP_TC(x) ((x) << S_CLIENT0_TLP_TC)
11044 #define G_CLIENT0_TLP_TC(x) (((x) >> S_CLIENT0_TLP_TC) & M_CLIENT0_TLP_TC)
11046 #define S_CLIENT0_TLP_TID 0
11047 #define M_CLIENT0_TLP_TID 0xffU
11048 #define V_CLIENT0_TLP_TID(x) ((x) << S_CLIENT0_TLP_TID)
11049 #define G_CLIENT0_TLP_TID(x) (((x) >> S_CLIENT0_TLP_TID) & M_CLIENT0_TLP_TID)
11051 #define A_PCIE_PDEBUG_REG_0X3C 0x3c
11053 #define S_MEM_RSPRRAVLD 31
11054 #define V_MEM_RSPRRAVLD(x) ((x) << S_MEM_RSPRRAVLD)
11055 #define F_MEM_RSPRRAVLD V_MEM_RSPRRAVLD(1U)
11057 #define S_MEM_RSPRRARDY 30
11058 #define V_MEM_RSPRRARDY(x) ((x) << S_MEM_RSPRRARDY)
11059 #define F_MEM_RSPRRARDY V_MEM_RSPRRARDY(1U)
11061 #define S_PIO_RSPRRAVLD 29
11062 #define V_PIO_RSPRRAVLD(x) ((x) << S_PIO_RSPRRAVLD)
11063 #define F_PIO_RSPRRAVLD V_PIO_RSPRRAVLD(1U)
11065 #define S_PIO_RSPRRARDY 28
11066 #define V_PIO_RSPRRARDY(x) ((x) << S_PIO_RSPRRARDY)
11067 #define F_PIO_RSPRRARDY V_PIO_RSPRRARDY(1U)
11069 #define S_MEM_RSPRDVLD 27
11070 #define V_MEM_RSPRDVLD(x) ((x) << S_MEM_RSPRDVLD)
11071 #define F_MEM_RSPRDVLD V_MEM_RSPRDVLD(1U)
11073 #define S_MEM_RSPRDRRARDY 26
11074 #define V_MEM_RSPRDRRARDY(x) ((x) << S_MEM_RSPRDRRARDY)
11075 #define F_MEM_RSPRDRRARDY V_MEM_RSPRDRRARDY(1U)
11077 #define S_PIO_RSPRDVLD 25
11078 #define V_PIO_RSPRDVLD(x) ((x) << S_PIO_RSPRDVLD)
11079 #define F_PIO_RSPRDVLD V_PIO_RSPRDVLD(1U)
11081 #define S_PIO_RSPRDRRARDY 24
11082 #define V_PIO_RSPRDRRARDY(x) ((x) << S_PIO_RSPRDRRARDY)
11083 #define F_PIO_RSPRDRRARDY V_PIO_RSPRDRRARDY(1U)
11085 #define S_TGT_TAGQ_RDVLD 16
11086 #define M_TGT_TAGQ_RDVLD 0xffU
11087 #define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD)
11088 #define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD)
11090 #define S_CPLTXNDISABLE 8
11091 #define M_CPLTXNDISABLE 0xffU
11092 #define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE)
11093 #define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE)
11095 #define S_CPLTXNDISABLE2 7
11096 #define V_CPLTXNDISABLE2(x) ((x) << S_CPLTXNDISABLE2)
11097 #define F_CPLTXNDISABLE2 V_CPLTXNDISABLE2(1U)
11099 #define S_CLIENT0_TLP_HV 0
11100 #define M_CLIENT0_TLP_HV 0x7fU
11101 #define V_CLIENT0_TLP_HV(x) ((x) << S_CLIENT0_TLP_HV)
11102 #define G_CLIENT0_TLP_HV(x) (((x) >> S_CLIENT0_TLP_HV) & M_CLIENT0_TLP_HV)
11104 #define A_PCIE_PDEBUG_REG_0X3D 0x3d
11105 #define A_PCIE_PDEBUG_REG_0X3E 0x3e
11106 #define A_PCIE_PDEBUG_REG_0X3F 0x3f
11107 #define A_PCIE_PDEBUG_REG_0X40 0x40
11108 #define A_PCIE_PDEBUG_REG_0X41 0x41
11109 #define A_PCIE_PDEBUG_REG_0X42 0x42
11110 #define A_PCIE_PDEBUG_REG_0X43 0x43
11111 #define A_PCIE_PDEBUG_REG_0X44 0x44
11112 #define A_PCIE_PDEBUG_REG_0X45 0x45
11113 #define A_PCIE_PDEBUG_REG_0X46 0x46
11114 #define A_PCIE_PDEBUG_REG_0X47 0x47
11115 #define A_PCIE_PDEBUG_REG_0X48 0x48
11116 #define A_PCIE_PDEBUG_REG_0X49 0x49
11117 #define A_PCIE_PDEBUG_REG_0X4A 0x4a
11118 #define A_PCIE_PDEBUG_REG_0X4B 0x4b
11119 #define A_PCIE_PDEBUG_REG_0X4C 0x4c
11120 #define A_PCIE_PDEBUG_REG_0X4D 0x4d
11121 #define A_PCIE_PDEBUG_REG_0X4E 0x4e
11122 #define A_PCIE_PDEBUG_REG_0X4F 0x4f
11123 #define A_PCIE_PDEBUG_REG_0X50 0x50
11124 #define A_PCIE_CDEBUG_REG_0X0 0x0
11125 #define A_PCIE_CDEBUG_REG_0X1 0x1
11126 #define A_PCIE_CDEBUG_REG_0X2 0x2
11128 #define S_FLR_REQVLD 31
11129 #define V_FLR_REQVLD(x) ((x) << S_FLR_REQVLD)
11130 #define F_FLR_REQVLD V_FLR_REQVLD(1U)
11132 #define S_D_RSPVLD 28
11133 #define M_D_RSPVLD 0x7U
11134 #define V_D_RSPVLD(x) ((x) << S_D_RSPVLD)
11135 #define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD)
11137 #define S_D_RSPVLD2 27
11138 #define V_D_RSPVLD2(x) ((x) << S_D_RSPVLD2)
11139 #define F_D_RSPVLD2 V_D_RSPVLD2(1U)
11141 #define S_D_RSPVLD3 26
11142 #define V_D_RSPVLD3(x) ((x) << S_D_RSPVLD3)
11143 #define F_D_RSPVLD3 V_D_RSPVLD3(1U)
11145 #define S_D_RSPVLD4 25
11146 #define V_D_RSPVLD4(x) ((x) << S_D_RSPVLD4)
11147 #define F_D_RSPVLD4 V_D_RSPVLD4(1U)
11149 #define S_D_RSPVLD5 24
11150 #define V_D_RSPVLD5(x) ((x) << S_D_RSPVLD5)
11151 #define F_D_RSPVLD5 V_D_RSPVLD5(1U)
11153 #define S_D_RSPVLD6 20
11154 #define M_D_RSPVLD6 0xfU
11155 #define V_D_RSPVLD6(x) ((x) << S_D_RSPVLD6)
11156 #define G_D_RSPVLD6(x) (((x) >> S_D_RSPVLD6) & M_D_RSPVLD6)
11158 #define S_D_RSPAFULL 16
11159 #define M_D_RSPAFULL 0xfU
11160 #define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL)
11161 #define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL)
11163 #define S_D_RDREQVLD 12
11164 #define M_D_RDREQVLD 0xfU
11165 #define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD)
11166 #define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD)
11168 #define S_D_RDREQAFULL 8
11169 #define M_D_RDREQAFULL 0xfU
11170 #define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL)
11171 #define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL)
11173 #define S_D_WRREQVLD 4
11174 #define M_D_WRREQVLD 0xfU
11175 #define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD)
11176 #define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD)
11178 #define S_D_WRREQAFULL 0
11179 #define M_D_WRREQAFULL 0xfU
11180 #define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL)
11181 #define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL)
11183 #define A_PCIE_CDEBUG_REG_0X3 0x3
11185 #define S_C_REQVLD 19
11186 #define M_C_REQVLD 0x1fffU
11187 #define V_C_REQVLD(x) ((x) << S_C_REQVLD)
11188 #define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD)
11190 #define S_C_RSPVLD2 16
11191 #define M_C_RSPVLD2 0x7U
11192 #define V_C_RSPVLD2(x) ((x) << S_C_RSPVLD2)
11193 #define G_C_RSPVLD2(x) (((x) >> S_C_RSPVLD2) & M_C_RSPVLD2)
11195 #define S_C_RSPVLD3 15
11196 #define V_C_RSPVLD3(x) ((x) << S_C_RSPVLD3)
11197 #define F_C_RSPVLD3 V_C_RSPVLD3(1U)
11199 #define S_C_RSPVLD4 14
11200 #define V_C_RSPVLD4(x) ((x) << S_C_RSPVLD4)
11201 #define F_C_RSPVLD4 V_C_RSPVLD4(1U)
11203 #define S_C_RSPVLD5 13
11204 #define V_C_RSPVLD5(x) ((x) << S_C_RSPVLD5)
11205 #define F_C_RSPVLD5 V_C_RSPVLD5(1U)
11207 #define S_C_RSPVLD6 12
11208 #define V_C_RSPVLD6(x) ((x) << S_C_RSPVLD6)
11209 #define F_C_RSPVLD6 V_C_RSPVLD6(1U)
11211 #define S_C_RSPVLD7 9
11212 #define M_C_RSPVLD7 0x7U
11213 #define V_C_RSPVLD7(x) ((x) << S_C_RSPVLD7)
11214 #define G_C_RSPVLD7(x) (((x) >> S_C_RSPVLD7) & M_C_RSPVLD7)
11216 #define S_C_RSPAFULL 6
11217 #define M_C_RSPAFULL 0x7U
11218 #define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL)
11219 #define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL)
11221 #define S_C_REQVLD8 3
11222 #define M_C_REQVLD8 0x7U
11223 #define V_C_REQVLD8(x) ((x) << S_C_REQVLD8)
11224 #define G_C_REQVLD8(x) (((x) >> S_C_REQVLD8) & M_C_REQVLD8)
11226 #define S_C_REQAFULL 0
11227 #define M_C_REQAFULL 0x7U
11228 #define V_C_REQAFULL(x) ((x) << S_C_REQAFULL)
11229 #define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL)
11231 #define A_PCIE_CDEBUG_REG_0X4 0x4
11233 #define S_H_REQVLD 7
11234 #define M_H_REQVLD 0x1ffffffU
11235 #define V_H_REQVLD(x) ((x) << S_H_REQVLD)
11236 #define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD)
11238 #define S_H_RSPVLD 6
11239 #define V_H_RSPVLD(x) ((x) << S_H_RSPVLD)
11240 #define F_H_RSPVLD V_H_RSPVLD(1U)
11242 #define S_H_RSPVLD2 5
11243 #define V_H_RSPVLD2(x) ((x) << S_H_RSPVLD2)
11244 #define F_H_RSPVLD2 V_H_RSPVLD2(1U)
11246 #define S_H_RSPVLD3 4
11247 #define V_H_RSPVLD3(x) ((x) << S_H_RSPVLD3)
11248 #define F_H_RSPVLD3 V_H_RSPVLD3(1U)
11250 #define S_H_RSPVLD4 3
11251 #define V_H_RSPVLD4(x) ((x) << S_H_RSPVLD4)
11252 #define F_H_RSPVLD4 V_H_RSPVLD4(1U)
11254 #define S_H_RSPAFULL 2
11255 #define V_H_RSPAFULL(x) ((x) << S_H_RSPAFULL)
11256 #define F_H_RSPAFULL V_H_RSPAFULL(1U)
11258 #define S_H_REQVLD2 1
11259 #define V_H_REQVLD2(x) ((x) << S_H_REQVLD2)
11260 #define F_H_REQVLD2 V_H_REQVLD2(1U)
11262 #define S_H_REQAFULL 0
11263 #define V_H_REQAFULL(x) ((x) << S_H_REQAFULL)
11264 #define F_H_REQAFULL V_H_REQAFULL(1U)
11266 #define A_PCIE_CDEBUG_REG_0X5 0x5
11268 #define S_ER_RSPVLD 16
11269 #define M_ER_RSPVLD 0xffffU
11270 #define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD)
11271 #define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD)
11273 #define S_ER_REQVLD2 5
11274 #define M_ER_REQVLD2 0x7ffU
11275 #define V_ER_REQVLD2(x) ((x) << S_ER_REQVLD2)
11276 #define G_ER_REQVLD2(x) (((x) >> S_ER_REQVLD2) & M_ER_REQVLD2)
11278 #define S_ER_REQVLD3 2
11279 #define M_ER_REQVLD3 0x7U
11280 #define V_ER_REQVLD3(x) ((x) << S_ER_REQVLD3)
11281 #define G_ER_REQVLD3(x) (((x) >> S_ER_REQVLD3) & M_ER_REQVLD3)
11283 #define S_ER_RSPVLD4 1
11284 #define V_ER_RSPVLD4(x) ((x) << S_ER_RSPVLD4)
11285 #define F_ER_RSPVLD4 V_ER_RSPVLD4(1U)
11287 #define S_ER_REQVLD5 0
11288 #define V_ER_REQVLD5(x) ((x) << S_ER_REQVLD5)
11289 #define F_ER_REQVLD5 V_ER_REQVLD5(1U)
11291 #define A_PCIE_CDEBUG_REG_0X6 0x6
11293 #define S_PL_BAR2_REQVLD 4
11294 #define M_PL_BAR2_REQVLD 0xfffffffU
11295 #define V_PL_BAR2_REQVLD(x) ((x) << S_PL_BAR2_REQVLD)
11296 #define G_PL_BAR2_REQVLD(x) (((x) >> S_PL_BAR2_REQVLD) & M_PL_BAR2_REQVLD)
11298 #define S_PL_BAR2_REQVLD2 3
11299 #define V_PL_BAR2_REQVLD2(x) ((x) << S_PL_BAR2_REQVLD2)
11300 #define F_PL_BAR2_REQVLD2 V_PL_BAR2_REQVLD2(1U)
11302 #define S_PL_BAR2_REQVLDE 2
11303 #define V_PL_BAR2_REQVLDE(x) ((x) << S_PL_BAR2_REQVLDE)
11304 #define F_PL_BAR2_REQVLDE V_PL_BAR2_REQVLDE(1U)
11306 #define S_PL_BAR2_REQFULL 1
11307 #define V_PL_BAR2_REQFULL(x) ((x) << S_PL_BAR2_REQFULL)
11308 #define F_PL_BAR2_REQFULL V_PL_BAR2_REQFULL(1U)
11310 #define S_PL_BAR2_REQVLD4 0
11311 #define V_PL_BAR2_REQVLD4(x) ((x) << S_PL_BAR2_REQVLD4)
11312 #define F_PL_BAR2_REQVLD4 V_PL_BAR2_REQVLD4(1U)
11314 #define A_PCIE_CDEBUG_REG_0X7 0x7
11315 #define A_PCIE_CDEBUG_REG_0X8 0x8
11316 #define A_PCIE_CDEBUG_REG_0X9 0x9
11317 #define A_PCIE_CDEBUG_REG_0XA 0xa
11319 #define S_VPD_RSPVLD 20
11320 #define M_VPD_RSPVLD 0xfffU
11321 #define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD)
11322 #define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD)
11324 #define S_VPD_REQVLD2 9
11325 #define M_VPD_REQVLD2 0x7ffU
11326 #define V_VPD_REQVLD2(x) ((x) << S_VPD_REQVLD2)
11327 #define G_VPD_REQVLD2(x) (((x) >> S_VPD_REQVLD2) & M_VPD_REQVLD2)
11329 #define S_VPD_REQVLD3 6
11330 #define M_VPD_REQVLD3 0x7U
11331 #define V_VPD_REQVLD3(x) ((x) << S_VPD_REQVLD3)
11332 #define G_VPD_REQVLD3(x) (((x) >> S_VPD_REQVLD3) & M_VPD_REQVLD3)
11334 #define S_VPD_REQVLD4 5
11335 #define V_VPD_REQVLD4(x) ((x) << S_VPD_REQVLD4)
11336 #define F_VPD_REQVLD4 V_VPD_REQVLD4(1U)
11338 #define S_VPD_REQVLD5 3
11339 #define M_VPD_REQVLD5 0x3U
11340 #define V_VPD_REQVLD5(x) ((x) << S_VPD_REQVLD5)
11341 #define G_VPD_REQVLD5(x) (((x) >> S_VPD_REQVLD5) & M_VPD_REQVLD5)
11343 #define S_VPD_RSPVLD2 2
11344 #define V_VPD_RSPVLD2(x) ((x) << S_VPD_RSPVLD2)
11345 #define F_VPD_RSPVLD2 V_VPD_RSPVLD2(1U)
11347 #define S_VPD_RSPVLD3 1
11348 #define V_VPD_RSPVLD3(x) ((x) << S_VPD_RSPVLD3)
11349 #define F_VPD_RSPVLD3 V_VPD_RSPVLD3(1U)
11351 #define S_VPD_REQVLD6 0
11352 #define V_VPD_REQVLD6(x) ((x) << S_VPD_REQVLD6)
11353 #define F_VPD_REQVLD6 V_VPD_REQVLD6(1U)
11355 #define A_PCIE_CDEBUG_REG_0XB 0xb
11357 #define S_MA_REQDATAVLD 28
11358 #define M_MA_REQDATAVLD 0xfU
11359 #define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD)
11360 #define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD)
11362 #define S_MA_REQADDRVLD 27
11363 #define V_MA_REQADDRVLD(x) ((x) << S_MA_REQADDRVLD)
11364 #define F_MA_REQADDRVLD V_MA_REQADDRVLD(1U)
11366 #define S_MA_REQADDRVLD2 26
11367 #define V_MA_REQADDRVLD2(x) ((x) << S_MA_REQADDRVLD2)
11368 #define F_MA_REQADDRVLD2 V_MA_REQADDRVLD2(1U)
11370 #define S_MA_RSPDATAVLD2 22
11371 #define M_MA_RSPDATAVLD2 0xfU
11372 #define V_MA_RSPDATAVLD2(x) ((x) << S_MA_RSPDATAVLD2)
11373 #define G_MA_RSPDATAVLD2(x) (((x) >> S_MA_RSPDATAVLD2) & M_MA_RSPDATAVLD2)
11375 #define S_MA_REQADDRVLD3 20
11376 #define M_MA_REQADDRVLD3 0x3U
11377 #define V_MA_REQADDRVLD3(x) ((x) << S_MA_REQADDRVLD3)
11378 #define G_MA_REQADDRVLD3(x) (((x) >> S_MA_REQADDRVLD3) & M_MA_REQADDRVLD3)
11380 #define S_MA_REQADDRVLD4 4
11381 #define M_MA_REQADDRVLD4 0xffffU
11382 #define V_MA_REQADDRVLD4(x) ((x) << S_MA_REQADDRVLD4)
11383 #define G_MA_REQADDRVLD4(x) (((x) >> S_MA_REQADDRVLD4) & M_MA_REQADDRVLD4)
11385 #define S_MA_REQADDRVLD5 3
11386 #define V_MA_REQADDRVLD5(x) ((x) << S_MA_REQADDRVLD5)
11387 #define F_MA_REQADDRVLD5 V_MA_REQADDRVLD5(1U)
11389 #define S_MA_REQADDRVLD6 2
11390 #define V_MA_REQADDRVLD6(x) ((x) << S_MA_REQADDRVLD6)
11391 #define F_MA_REQADDRVLD6 V_MA_REQADDRVLD6(1U)
11393 #define S_MA_REQADDRRDY 1
11394 #define V_MA_REQADDRRDY(x) ((x) << S_MA_REQADDRRDY)
11395 #define F_MA_REQADDRRDY V_MA_REQADDRRDY(1U)
11397 #define S_MA_REQADDRVLD7 0
11398 #define V_MA_REQADDRVLD7(x) ((x) << S_MA_REQADDRVLD7)
11399 #define F_MA_REQADDRVLD7 V_MA_REQADDRVLD7(1U)
11401 #define A_PCIE_CDEBUG_REG_0XC 0xc
11402 #define A_PCIE_CDEBUG_REG_0XD 0xd
11403 #define A_PCIE_CDEBUG_REG_0XE 0xe
11404 #define A_PCIE_CDEBUG_REG_0XF 0xf
11405 #define A_PCIE_CDEBUG_REG_0X10 0x10
11406 #define A_PCIE_CDEBUG_REG_0X11 0x11
11407 #define A_PCIE_CDEBUG_REG_0X12 0x12
11408 #define A_PCIE_CDEBUG_REG_0X13 0x13
11409 #define A_PCIE_CDEBUG_REG_0X14 0x14
11410 #define A_PCIE_CDEBUG_REG_0X15 0x15
11412 #define S_PLM_REQVLD 19
11413 #define M_PLM_REQVLD 0x1fffU
11414 #define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD)
11415 #define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD)
11417 #define S_PLM_REQVLD2 18
11418 #define V_PLM_REQVLD2(x) ((x) << S_PLM_REQVLD2)
11419 #define F_PLM_REQVLD2 V_PLM_REQVLD2(1U)
11421 #define S_PLM_RSPVLD3 17
11422 #define V_PLM_RSPVLD3(x) ((x) << S_PLM_RSPVLD3)
11423 #define F_PLM_RSPVLD3 V_PLM_RSPVLD3(1U)
11425 #define S_PLM_REQVLD4 16
11426 #define V_PLM_REQVLD4(x) ((x) << S_PLM_REQVLD4)
11427 #define F_PLM_REQVLD4 V_PLM_REQVLD4(1U)
11429 #define S_PLM_REQVLD5 15
11430 #define V_PLM_REQVLD5(x) ((x) << S_PLM_REQVLD5)
11431 #define F_PLM_REQVLD5 V_PLM_REQVLD5(1U)
11433 #define S_PLM_REQVLD6 14
11434 #define V_PLM_REQVLD6(x) ((x) << S_PLM_REQVLD6)
11435 #define F_PLM_REQVLD6 V_PLM_REQVLD6(1U)
11437 #define S_PLM_REQVLD7 13
11438 #define V_PLM_REQVLD7(x) ((x) << S_PLM_REQVLD7)
11439 #define F_PLM_REQVLD7 V_PLM_REQVLD7(1U)
11441 #define S_PLM_REQVLD8 12
11442 #define V_PLM_REQVLD8(x) ((x) << S_PLM_REQVLD8)
11443 #define F_PLM_REQVLD8 V_PLM_REQVLD8(1U)
11445 #define S_PLM_REQVLD9 4
11446 #define M_PLM_REQVLD9 0xffU
11447 #define V_PLM_REQVLD9(x) ((x) << S_PLM_REQVLD9)
11448 #define G_PLM_REQVLD9(x) (((x) >> S_PLM_REQVLD9) & M_PLM_REQVLD9)
11450 #define S_PLM_REQVLDA 1
11451 #define M_PLM_REQVLDA 0x7U
11452 #define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA)
11453 #define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA)
11455 #define S_PLM_REQVLDB 0
11456 #define V_PLM_REQVLDB(x) ((x) << S_PLM_REQVLDB)
11457 #define F_PLM_REQVLDB V_PLM_REQVLDB(1U)
11459 #define A_PCIE_CDEBUG_REG_0X16 0x16
11460 #define A_PCIE_CDEBUG_REG_0X17 0x17
11461 #define A_PCIE_CDEBUG_REG_0X18 0x18
11462 #define A_PCIE_CDEBUG_REG_0X19 0x19
11463 #define A_PCIE_CDEBUG_REG_0X1A 0x1a
11464 #define A_PCIE_CDEBUG_REG_0X1B 0x1b
11465 #define A_PCIE_CDEBUG_REG_0X1C 0x1c
11466 #define A_PCIE_CDEBUG_REG_0X1D 0x1d
11467 #define A_PCIE_CDEBUG_REG_0X1E 0x1e
11468 #define A_PCIE_CDEBUG_REG_0X1F 0x1f
11469 #define A_PCIE_CDEBUG_REG_0X20 0x20
11470 #define A_PCIE_CDEBUG_REG_0X21 0x21
11471 #define A_PCIE_CDEBUG_REG_0X22 0x22
11472 #define A_PCIE_CDEBUG_REG_0X23 0x23
11473 #define A_PCIE_CDEBUG_REG_0X24 0x24
11474 #define A_PCIE_CDEBUG_REG_0X25 0x25
11475 #define A_PCIE_CDEBUG_REG_0X26 0x26
11476 #define A_PCIE_CDEBUG_REG_0X27 0x27
11477 #define A_PCIE_CDEBUG_REG_0X28 0x28
11478 #define A_PCIE_CDEBUG_REG_0X29 0x29
11479 #define A_PCIE_CDEBUG_REG_0X2A 0x2a
11480 #define A_PCIE_CDEBUG_REG_0X2B 0x2b
11481 #define A_PCIE_CDEBUG_REG_0X2C 0x2c
11482 #define A_PCIE_CDEBUG_REG_0X2D 0x2d
11483 #define A_PCIE_CDEBUG_REG_0X2E 0x2e
11484 #define A_PCIE_CDEBUG_REG_0X2F 0x2f
11485 #define A_PCIE_CDEBUG_REG_0X30 0x30
11486 #define A_PCIE_CDEBUG_REG_0X31 0x31
11487 #define A_PCIE_CDEBUG_REG_0X32 0x32
11488 #define A_PCIE_CDEBUG_REG_0X33 0x33
11489 #define A_PCIE_CDEBUG_REG_0X34 0x34
11490 #define A_PCIE_CDEBUG_REG_0X35 0x35
11491 #define A_PCIE_CDEBUG_REG_0X36 0x36
11492 #define A_PCIE_CDEBUG_REG_0X37 0x37
11494 /* registers for module DBG */
11495 #define DBG_BASE_ADDR 0x6000
11497 #define A_DBG_DBG0_CFG 0x6000
11499 #define S_MODULESELECT 12
11500 #define M_MODULESELECT 0xffU
11501 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
11502 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
11504 #define S_REGSELECT 4
11505 #define M_REGSELECT 0xffU
11506 #define V_REGSELECT(x) ((x) << S_REGSELECT)
11507 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
11509 #define S_CLKSELECT 0
11510 #define M_CLKSELECT 0xfU
11511 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
11512 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
11514 #define A_DBG_DBG0_EN 0x6004
11516 #define S_PORTEN_PONR 16
11517 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
11518 #define F_PORTEN_PONR V_PORTEN_PONR(1U)
11520 #define S_PORTEN_POND 12
11521 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
11522 #define F_PORTEN_POND V_PORTEN_POND(1U)
11524 #define S_SDRHALFWORD0 8
11525 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
11526 #define F_SDRHALFWORD0 V_SDRHALFWORD0(1U)
11529 #define V_DDREN(x) ((x) << S_DDREN)
11530 #define F_DDREN V_DDREN(1U)
11532 #define S_DBG_PORTEN 0
11533 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
11534 #define F_DBG_PORTEN V_DBG_PORTEN(1U)
11536 #define A_DBG_DBG1_CFG 0x6008
11537 #define A_DBG_DBG1_EN 0x600c
11539 #define S_CLK_EN_ON_DBG1 20
11540 #define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
11541 #define F_CLK_EN_ON_DBG1 V_CLK_EN_ON_DBG1(1U)
11543 #define A_DBG_GPIO_EN 0x6010
11545 #define S_GPIO15_OEN 31
11546 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
11547 #define F_GPIO15_OEN V_GPIO15_OEN(1U)
11549 #define S_GPIO14_OEN 30
11550 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
11551 #define F_GPIO14_OEN V_GPIO14_OEN(1U)
11553 #define S_GPIO13_OEN 29
11554 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
11555 #define F_GPIO13_OEN V_GPIO13_OEN(1U)
11557 #define S_GPIO12_OEN 28
11558 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
11559 #define F_GPIO12_OEN V_GPIO12_OEN(1U)
11561 #define S_GPIO11_OEN 27
11562 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
11563 #define F_GPIO11_OEN V_GPIO11_OEN(1U)
11565 #define S_GPIO10_OEN 26
11566 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
11567 #define F_GPIO10_OEN V_GPIO10_OEN(1U)
11569 #define S_GPIO9_OEN 25
11570 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
11571 #define F_GPIO9_OEN V_GPIO9_OEN(1U)
11573 #define S_GPIO8_OEN 24
11574 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
11575 #define F_GPIO8_OEN V_GPIO8_OEN(1U)
11577 #define S_GPIO7_OEN 23
11578 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
11579 #define F_GPIO7_OEN V_GPIO7_OEN(1U)
11581 #define S_GPIO6_OEN 22
11582 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
11583 #define F_GPIO6_OEN V_GPIO6_OEN(1U)
11585 #define S_GPIO5_OEN 21
11586 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
11587 #define F_GPIO5_OEN V_GPIO5_OEN(1U)
11589 #define S_GPIO4_OEN 20
11590 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
11591 #define F_GPIO4_OEN V_GPIO4_OEN(1U)
11593 #define S_GPIO3_OEN 19
11594 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
11595 #define F_GPIO3_OEN V_GPIO3_OEN(1U)
11597 #define S_GPIO2_OEN 18
11598 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
11599 #define F_GPIO2_OEN V_GPIO2_OEN(1U)
11601 #define S_GPIO1_OEN 17
11602 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
11603 #define F_GPIO1_OEN V_GPIO1_OEN(1U)
11605 #define S_GPIO0_OEN 16
11606 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
11607 #define F_GPIO0_OEN V_GPIO0_OEN(1U)
11609 #define S_GPIO15_OUT_VAL 15
11610 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
11611 #define F_GPIO15_OUT_VAL V_GPIO15_OUT_VAL(1U)
11613 #define S_GPIO14_OUT_VAL 14
11614 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
11615 #define F_GPIO14_OUT_VAL V_GPIO14_OUT_VAL(1U)
11617 #define S_GPIO13_OUT_VAL 13
11618 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
11619 #define F_GPIO13_OUT_VAL V_GPIO13_OUT_VAL(1U)
11621 #define S_GPIO12_OUT_VAL 12
11622 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
11623 #define F_GPIO12_OUT_VAL V_GPIO12_OUT_VAL(1U)
11625 #define S_GPIO11_OUT_VAL 11
11626 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
11627 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U)
11629 #define S_GPIO10_OUT_VAL 10
11630 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
11631 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
11633 #define S_GPIO9_OUT_VAL 9
11634 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
11635 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U)
11637 #define S_GPIO8_OUT_VAL 8
11638 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
11639 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U)
11641 #define S_GPIO7_OUT_VAL 7
11642 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
11643 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
11645 #define S_GPIO6_OUT_VAL 6
11646 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
11647 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
11649 #define S_GPIO5_OUT_VAL 5
11650 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
11651 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
11653 #define S_GPIO4_OUT_VAL 4
11654 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
11655 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
11657 #define S_GPIO3_OUT_VAL 3
11658 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
11659 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U)
11661 #define S_GPIO2_OUT_VAL 2
11662 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
11663 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
11665 #define S_GPIO1_OUT_VAL 1
11666 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
11667 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
11669 #define S_GPIO0_OUT_VAL 0
11670 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
11671 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
11673 #define A_DBG_GPIO_IN 0x6014
11675 #define S_GPIO15_CHG_DET 31
11676 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
11677 #define F_GPIO15_CHG_DET V_GPIO15_CHG_DET(1U)
11679 #define S_GPIO14_CHG_DET 30
11680 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
11681 #define F_GPIO14_CHG_DET V_GPIO14_CHG_DET(1U)
11683 #define S_GPIO13_CHG_DET 29
11684 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
11685 #define F_GPIO13_CHG_DET V_GPIO13_CHG_DET(1U)
11687 #define S_GPIO12_CHG_DET 28
11688 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
11689 #define F_GPIO12_CHG_DET V_GPIO12_CHG_DET(1U)
11691 #define S_GPIO11_CHG_DET 27
11692 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
11693 #define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U)
11695 #define S_GPIO10_CHG_DET 26
11696 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
11697 #define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U)
11699 #define S_GPIO9_CHG_DET 25
11700 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
11701 #define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U)
11703 #define S_GPIO8_CHG_DET 24
11704 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
11705 #define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U)
11707 #define S_GPIO7_CHG_DET 23
11708 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
11709 #define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U)
11711 #define S_GPIO6_CHG_DET 22
11712 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
11713 #define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U)
11715 #define S_GPIO5_CHG_DET 21
11716 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
11717 #define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U)
11719 #define S_GPIO4_CHG_DET 20
11720 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
11721 #define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U)
11723 #define S_GPIO3_CHG_DET 19
11724 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
11725 #define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U)
11727 #define S_GPIO2_CHG_DET 18
11728 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
11729 #define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U)
11731 #define S_GPIO1_CHG_DET 17
11732 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
11733 #define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U)
11735 #define S_GPIO0_CHG_DET 16
11736 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
11737 #define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U)
11739 #define S_GPIO15_IN 15
11740 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
11741 #define F_GPIO15_IN V_GPIO15_IN(1U)
11743 #define S_GPIO14_IN 14
11744 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
11745 #define F_GPIO14_IN V_GPIO14_IN(1U)
11747 #define S_GPIO13_IN 13
11748 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
11749 #define F_GPIO13_IN V_GPIO13_IN(1U)
11751 #define S_GPIO12_IN 12
11752 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
11753 #define F_GPIO12_IN V_GPIO12_IN(1U)
11755 #define S_GPIO11_IN 11
11756 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
11757 #define F_GPIO11_IN V_GPIO11_IN(1U)
11759 #define S_GPIO10_IN 10
11760 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
11761 #define F_GPIO10_IN V_GPIO10_IN(1U)
11763 #define S_GPIO9_IN 9
11764 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
11765 #define F_GPIO9_IN V_GPIO9_IN(1U)
11767 #define S_GPIO8_IN 8
11768 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
11769 #define F_GPIO8_IN V_GPIO8_IN(1U)
11771 #define S_GPIO7_IN 7
11772 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
11773 #define F_GPIO7_IN V_GPIO7_IN(1U)
11775 #define S_GPIO6_IN 6
11776 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
11777 #define F_GPIO6_IN V_GPIO6_IN(1U)
11779 #define S_GPIO5_IN 5
11780 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
11781 #define F_GPIO5_IN V_GPIO5_IN(1U)
11783 #define S_GPIO4_IN 4
11784 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
11785 #define F_GPIO4_IN V_GPIO4_IN(1U)
11787 #define S_GPIO3_IN 3
11788 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
11789 #define F_GPIO3_IN V_GPIO3_IN(1U)
11791 #define S_GPIO2_IN 2
11792 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
11793 #define F_GPIO2_IN V_GPIO2_IN(1U)
11795 #define S_GPIO1_IN 1
11796 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
11797 #define F_GPIO1_IN V_GPIO1_IN(1U)
11799 #define S_GPIO0_IN 0
11800 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
11801 #define F_GPIO0_IN V_GPIO0_IN(1U)
11803 #define A_DBG_INT_ENABLE 0x6018
11805 #define S_IBM_FDL_FAIL_INT_ENBL 25
11806 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
11807 #define F_IBM_FDL_FAIL_INT_ENBL V_IBM_FDL_FAIL_INT_ENBL(1U)
11809 #define S_ARM_FAIL_INT_ENBL 24
11810 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
11811 #define F_ARM_FAIL_INT_ENBL V_ARM_FAIL_INT_ENBL(1U)
11813 #define S_ARM_ERROR_OUT_INT_ENBL 23
11814 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
11815 #define F_ARM_ERROR_OUT_INT_ENBL V_ARM_ERROR_OUT_INT_ENBL(1U)
11817 #define S_PLL_LOCK_LOST_INT_ENBL 22
11818 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
11819 #define F_PLL_LOCK_LOST_INT_ENBL V_PLL_LOCK_LOST_INT_ENBL(1U)
11821 #define S_C_LOCK 21
11822 #define V_C_LOCK(x) ((x) << S_C_LOCK)
11823 #define F_C_LOCK V_C_LOCK(1U)
11825 #define S_M_LOCK 20
11826 #define V_M_LOCK(x) ((x) << S_M_LOCK)
11827 #define F_M_LOCK V_M_LOCK(1U)
11829 #define S_U_LOCK 19
11830 #define V_U_LOCK(x) ((x) << S_U_LOCK)
11831 #define F_U_LOCK V_U_LOCK(1U)
11833 #define S_PCIE_LOCK 18
11834 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
11835 #define F_PCIE_LOCK V_PCIE_LOCK(1U)
11837 #define S_KX_LOCK 17
11838 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
11839 #define F_KX_LOCK V_KX_LOCK(1U)
11841 #define S_KR_LOCK 16
11842 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
11843 #define F_KR_LOCK V_KR_LOCK(1U)
11845 #define S_GPIO15 15
11846 #define V_GPIO15(x) ((x) << S_GPIO15)
11847 #define F_GPIO15 V_GPIO15(1U)
11849 #define S_GPIO14 14
11850 #define V_GPIO14(x) ((x) << S_GPIO14)
11851 #define F_GPIO14 V_GPIO14(1U)
11853 #define S_GPIO13 13
11854 #define V_GPIO13(x) ((x) << S_GPIO13)
11855 #define F_GPIO13 V_GPIO13(1U)
11857 #define S_GPIO12 12
11858 #define V_GPIO12(x) ((x) << S_GPIO12)
11859 #define F_GPIO12 V_GPIO12(1U)
11861 #define S_GPIO11 11
11862 #define V_GPIO11(x) ((x) << S_GPIO11)
11863 #define F_GPIO11 V_GPIO11(1U)
11865 #define S_GPIO10 10
11866 #define V_GPIO10(x) ((x) << S_GPIO10)
11867 #define F_GPIO10 V_GPIO10(1U)
11870 #define V_GPIO9(x) ((x) << S_GPIO9)
11871 #define F_GPIO9 V_GPIO9(1U)
11874 #define V_GPIO8(x) ((x) << S_GPIO8)
11875 #define F_GPIO8 V_GPIO8(1U)
11878 #define V_GPIO7(x) ((x) << S_GPIO7)
11879 #define F_GPIO7 V_GPIO7(1U)
11882 #define V_GPIO6(x) ((x) << S_GPIO6)
11883 #define F_GPIO6 V_GPIO6(1U)
11886 #define V_GPIO5(x) ((x) << S_GPIO5)
11887 #define F_GPIO5 V_GPIO5(1U)
11890 #define V_GPIO4(x) ((x) << S_GPIO4)
11891 #define F_GPIO4 V_GPIO4(1U)
11894 #define V_GPIO3(x) ((x) << S_GPIO3)
11895 #define F_GPIO3 V_GPIO3(1U)
11898 #define V_GPIO2(x) ((x) << S_GPIO2)
11899 #define F_GPIO2 V_GPIO2(1U)
11902 #define V_GPIO1(x) ((x) << S_GPIO1)
11903 #define F_GPIO1 V_GPIO1(1U)
11906 #define V_GPIO0(x) ((x) << S_GPIO0)
11907 #define F_GPIO0 V_GPIO0(1U)
11909 #define S_GPIO19 29
11910 #define V_GPIO19(x) ((x) << S_GPIO19)
11911 #define F_GPIO19 V_GPIO19(1U)
11913 #define S_GPIO18 28
11914 #define V_GPIO18(x) ((x) << S_GPIO18)
11915 #define F_GPIO18 V_GPIO18(1U)
11917 #define S_GPIO17 27
11918 #define V_GPIO17(x) ((x) << S_GPIO17)
11919 #define F_GPIO17 V_GPIO17(1U)
11921 #define S_GPIO16 26
11922 #define V_GPIO16(x) ((x) << S_GPIO16)
11923 #define F_GPIO16 V_GPIO16(1U)
11925 #define A_DBG_INT_CAUSE 0x601c
11927 #define S_IBM_FDL_FAIL_INT_CAUSE 25
11928 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
11929 #define F_IBM_FDL_FAIL_INT_CAUSE V_IBM_FDL_FAIL_INT_CAUSE(1U)
11931 #define S_ARM_FAIL_INT_CAUSE 24
11932 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
11933 #define F_ARM_FAIL_INT_CAUSE V_ARM_FAIL_INT_CAUSE(1U)
11935 #define S_ARM_ERROR_OUT_INT_CAUSE 23
11936 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
11937 #define F_ARM_ERROR_OUT_INT_CAUSE V_ARM_ERROR_OUT_INT_CAUSE(1U)
11939 #define S_PLL_LOCK_LOST_INT_CAUSE 22
11940 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
11941 #define F_PLL_LOCK_LOST_INT_CAUSE V_PLL_LOCK_LOST_INT_CAUSE(1U)
11943 #define A_DBG_DBG0_RST_VALUE 0x6020
11945 #define S_DEBUGDATA 0
11946 #define M_DEBUGDATA 0xffffU
11947 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
11948 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
11950 #define A_DBG_OVERWRSERCFG_EN 0x6024
11952 #define S_OVERWRSERCFG_EN 0
11953 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
11954 #define F_OVERWRSERCFG_EN V_OVERWRSERCFG_EN(1U)
11956 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
11958 #define S_PCIE_OCLK_EN 20
11959 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
11960 #define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U)
11962 #define S_KX_OCLK_EN 16
11963 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
11964 #define F_KX_OCLK_EN V_KX_OCLK_EN(1U)
11966 #define S_U_OCLK_EN 12
11967 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
11968 #define F_U_OCLK_EN V_U_OCLK_EN(1U)
11970 #define S_KR_OCLK_EN 8
11971 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
11972 #define F_KR_OCLK_EN V_KR_OCLK_EN(1U)
11974 #define S_M_OCLK_EN 4
11975 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
11976 #define F_M_OCLK_EN V_M_OCLK_EN(1U)
11978 #define S_C_OCLK_EN 0
11979 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
11980 #define F_C_OCLK_EN V_C_OCLK_EN(1U)
11982 #define A_DBG_PLL_LOCK 0x602c
11984 #define S_PLL_P_LOCK 20
11985 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
11986 #define F_PLL_P_LOCK V_PLL_P_LOCK(1U)
11988 #define S_PLL_KX_LOCK 16
11989 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
11990 #define F_PLL_KX_LOCK V_PLL_KX_LOCK(1U)
11992 #define S_PLL_U_LOCK 12
11993 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
11994 #define F_PLL_U_LOCK V_PLL_U_LOCK(1U)
11996 #define S_PLL_KR_LOCK 8
11997 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
11998 #define F_PLL_KR_LOCK V_PLL_KR_LOCK(1U)
12000 #define S_PLL_M_LOCK 4
12001 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
12002 #define F_PLL_M_LOCK V_PLL_M_LOCK(1U)
12004 #define S_PLL_C_LOCK 0
12005 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
12006 #define F_PLL_C_LOCK V_PLL_C_LOCK(1U)
12008 #define A_DBG_GPIO_ACT_LOW 0x6030
12010 #define S_P_LOCK_ACT_LOW 21
12011 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
12012 #define F_P_LOCK_ACT_LOW V_P_LOCK_ACT_LOW(1U)
12014 #define S_C_LOCK_ACT_LOW 20
12015 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
12016 #define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U)
12018 #define S_M_LOCK_ACT_LOW 19
12019 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
12020 #define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U)
12022 #define S_U_LOCK_ACT_LOW 18
12023 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
12024 #define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U)
12026 #define S_KR_LOCK_ACT_LOW 17
12027 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
12028 #define F_KR_LOCK_ACT_LOW V_KR_LOCK_ACT_LOW(1U)
12030 #define S_KX_LOCK_ACT_LOW 16
12031 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
12032 #define F_KX_LOCK_ACT_LOW V_KX_LOCK_ACT_LOW(1U)
12034 #define S_GPIO15_ACT_LOW 15
12035 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
12036 #define F_GPIO15_ACT_LOW V_GPIO15_ACT_LOW(1U)
12038 #define S_GPIO14_ACT_LOW 14
12039 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
12040 #define F_GPIO14_ACT_LOW V_GPIO14_ACT_LOW(1U)
12042 #define S_GPIO13_ACT_LOW 13
12043 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
12044 #define F_GPIO13_ACT_LOW V_GPIO13_ACT_LOW(1U)
12046 #define S_GPIO12_ACT_LOW 12
12047 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
12048 #define F_GPIO12_ACT_LOW V_GPIO12_ACT_LOW(1U)
12050 #define S_GPIO11_ACT_LOW 11
12051 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
12052 #define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U)
12054 #define S_GPIO10_ACT_LOW 10
12055 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
12056 #define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U)
12058 #define S_GPIO9_ACT_LOW 9
12059 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
12060 #define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U)
12062 #define S_GPIO8_ACT_LOW 8
12063 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
12064 #define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U)
12066 #define S_GPIO7_ACT_LOW 7
12067 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
12068 #define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U)
12070 #define S_GPIO6_ACT_LOW 6
12071 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
12072 #define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U)
12074 #define S_GPIO5_ACT_LOW 5
12075 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
12076 #define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U)
12078 #define S_GPIO4_ACT_LOW 4
12079 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
12080 #define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U)
12082 #define S_GPIO3_ACT_LOW 3
12083 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
12084 #define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U)
12086 #define S_GPIO2_ACT_LOW 2
12087 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
12088 #define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U)
12090 #define S_GPIO1_ACT_LOW 1
12091 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
12092 #define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U)
12094 #define S_GPIO0_ACT_LOW 0
12095 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
12096 #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U)
12098 #define S_GPIO19_ACT_LOW 25
12099 #define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
12100 #define F_GPIO19_ACT_LOW V_GPIO19_ACT_LOW(1U)
12102 #define S_GPIO18_ACT_LOW 24
12103 #define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
12104 #define F_GPIO18_ACT_LOW V_GPIO18_ACT_LOW(1U)
12106 #define S_GPIO17_ACT_LOW 23
12107 #define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
12108 #define F_GPIO17_ACT_LOW V_GPIO17_ACT_LOW(1U)
12110 #define S_GPIO16_ACT_LOW 22
12111 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
12112 #define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U)
12114 #define A_DBG_EFUSE_BYTE0_3 0x6034
12115 #define A_DBG_EFUSE_BYTE4_7 0x6038
12116 #define A_DBG_EFUSE_BYTE8_11 0x603c
12117 #define A_DBG_EFUSE_BYTE12_15 0x6040
12118 #define A_DBG_STATIC_U_PLL_CONF 0x6044
12120 #define S_STATIC_U_PLL_MULT 23
12121 #define M_STATIC_U_PLL_MULT 0x1ffU
12122 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
12123 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
12125 #define S_STATIC_U_PLL_PREDIV 18
12126 #define M_STATIC_U_PLL_PREDIV 0x1fU
12127 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
12128 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
12130 #define S_STATIC_U_PLL_RANGEA 14
12131 #define M_STATIC_U_PLL_RANGEA 0xfU
12132 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
12133 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
12135 #define S_STATIC_U_PLL_RANGEB 10
12136 #define M_STATIC_U_PLL_RANGEB 0xfU
12137 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
12138 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
12140 #define S_STATIC_U_PLL_TUNE 0
12141 #define M_STATIC_U_PLL_TUNE 0x3ffU
12142 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
12143 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
12145 #define A_DBG_STATIC_C_PLL_CONF 0x6048
12147 #define S_STATIC_C_PLL_MULT 23
12148 #define M_STATIC_C_PLL_MULT 0x1ffU
12149 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
12150 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
12152 #define S_STATIC_C_PLL_PREDIV 18
12153 #define M_STATIC_C_PLL_PREDIV 0x1fU
12154 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
12155 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
12157 #define S_STATIC_C_PLL_RANGEA 14
12158 #define M_STATIC_C_PLL_RANGEA 0xfU
12159 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
12160 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
12162 #define S_STATIC_C_PLL_RANGEB 10
12163 #define M_STATIC_C_PLL_RANGEB 0xfU
12164 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
12165 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
12167 #define S_STATIC_C_PLL_TUNE 0
12168 #define M_STATIC_C_PLL_TUNE 0x3ffU
12169 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
12170 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
12172 #define A_DBG_STATIC_M_PLL_CONF 0x604c
12174 #define S_STATIC_M_PLL_MULT 23
12175 #define M_STATIC_M_PLL_MULT 0x1ffU
12176 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
12177 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
12179 #define S_STATIC_M_PLL_PREDIV 18
12180 #define M_STATIC_M_PLL_PREDIV 0x1fU
12181 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
12182 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
12184 #define S_STATIC_M_PLL_RANGEA 14
12185 #define M_STATIC_M_PLL_RANGEA 0xfU
12186 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
12187 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
12189 #define S_STATIC_M_PLL_RANGEB 10
12190 #define M_STATIC_M_PLL_RANGEB 0xfU
12191 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
12192 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
12194 #define S_STATIC_M_PLL_TUNE 0
12195 #define M_STATIC_M_PLL_TUNE 0x3ffU
12196 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
12197 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
12199 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
12201 #define S_STATIC_KX_PLL_C 21
12202 #define M_STATIC_KX_PLL_C 0xffU
12203 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
12204 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
12206 #define S_STATIC_KX_PLL_M 15
12207 #define M_STATIC_KX_PLL_M 0x3fU
12208 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
12209 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
12211 #define S_STATIC_KX_PLL_N1 11
12212 #define M_STATIC_KX_PLL_N1 0xfU
12213 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
12214 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
12216 #define S_STATIC_KX_PLL_N2 7
12217 #define M_STATIC_KX_PLL_N2 0xfU
12218 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
12219 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
12221 #define S_STATIC_KX_PLL_N3 3
12222 #define M_STATIC_KX_PLL_N3 0xfU
12223 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
12224 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
12226 #define S_STATIC_KX_PLL_P 0
12227 #define M_STATIC_KX_PLL_P 0x7U
12228 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
12229 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
12231 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
12233 #define S_STATIC_KR_PLL_C 21
12234 #define M_STATIC_KR_PLL_C 0xffU
12235 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
12236 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
12238 #define S_STATIC_KR_PLL_M 15
12239 #define M_STATIC_KR_PLL_M 0x3fU
12240 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
12241 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
12243 #define S_STATIC_KR_PLL_N1 11
12244 #define M_STATIC_KR_PLL_N1 0xfU
12245 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
12246 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
12248 #define S_STATIC_KR_PLL_N2 7
12249 #define M_STATIC_KR_PLL_N2 0xfU
12250 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
12251 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
12253 #define S_STATIC_KR_PLL_N3 3
12254 #define M_STATIC_KR_PLL_N3 0xfU
12255 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
12256 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
12258 #define S_STATIC_KR_PLL_P 0
12259 #define M_STATIC_KR_PLL_P 0x7U
12260 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
12261 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
12263 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
12265 #define S_STATIC_M_PLL_RESET 30
12266 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
12267 #define F_STATIC_M_PLL_RESET V_STATIC_M_PLL_RESET(1U)
12269 #define S_STATIC_M_PLL_SLEEP 29
12270 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
12271 #define F_STATIC_M_PLL_SLEEP V_STATIC_M_PLL_SLEEP(1U)
12273 #define S_STATIC_M_PLL_BYPASS 28
12274 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
12275 #define F_STATIC_M_PLL_BYPASS V_STATIC_M_PLL_BYPASS(1U)
12277 #define S_STATIC_MPLL_CLK_SEL 27
12278 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
12279 #define F_STATIC_MPLL_CLK_SEL V_STATIC_MPLL_CLK_SEL(1U)
12281 #define S_STATIC_U_PLL_SLEEP 26
12282 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
12283 #define F_STATIC_U_PLL_SLEEP V_STATIC_U_PLL_SLEEP(1U)
12285 #define S_STATIC_C_PLL_SLEEP 25
12286 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
12287 #define F_STATIC_C_PLL_SLEEP V_STATIC_C_PLL_SLEEP(1U)
12289 #define S_STATIC_LVDS_CLKOUT_SEL 23
12290 #define M_STATIC_LVDS_CLKOUT_SEL 0x3U
12291 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
12292 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
12294 #define S_STATIC_LVDS_CLKOUT_EN 22
12295 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
12296 #define F_STATIC_LVDS_CLKOUT_EN V_STATIC_LVDS_CLKOUT_EN(1U)
12298 #define S_STATIC_CCLK_FREQ_SEL 20
12299 #define M_STATIC_CCLK_FREQ_SEL 0x3U
12300 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
12301 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
12303 #define S_STATIC_UCLK_FREQ_SEL 18
12304 #define M_STATIC_UCLK_FREQ_SEL 0x3U
12305 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
12306 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
12308 #define S_EXPHYCLK_SEL_EN 17
12309 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
12310 #define F_EXPHYCLK_SEL_EN V_EXPHYCLK_SEL_EN(1U)
12312 #define S_EXPHYCLK_SEL 15
12313 #define M_EXPHYCLK_SEL 0x3U
12314 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
12315 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
12317 #define S_STATIC_U_PLL_BYPASS 14
12318 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
12319 #define F_STATIC_U_PLL_BYPASS V_STATIC_U_PLL_BYPASS(1U)
12321 #define S_STATIC_C_PLL_BYPASS 13
12322 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
12323 #define F_STATIC_C_PLL_BYPASS V_STATIC_C_PLL_BYPASS(1U)
12325 #define S_STATIC_KR_PLL_BYPASS 12
12326 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
12327 #define F_STATIC_KR_PLL_BYPASS V_STATIC_KR_PLL_BYPASS(1U)
12329 #define S_STATIC_KX_PLL_BYPASS 11
12330 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
12331 #define F_STATIC_KX_PLL_BYPASS V_STATIC_KX_PLL_BYPASS(1U)
12333 #define S_STATIC_KX_PLL_V 7
12334 #define M_STATIC_KX_PLL_V 0xfU
12335 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
12336 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
12338 #define S_STATIC_KR_PLL_V 3
12339 #define M_STATIC_KR_PLL_V 0xfU
12340 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
12341 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
12343 #define S_PSRO_SEL 0
12344 #define M_PSRO_SEL 0x7U
12345 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
12346 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
12348 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
12350 #define S_M_OCLK_MUXSEL 12
12351 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
12352 #define F_M_OCLK_MUXSEL V_M_OCLK_MUXSEL(1U)
12354 #define S_C_OCLK_MUXSEL 10
12355 #define M_C_OCLK_MUXSEL 0x3U
12356 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
12357 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
12359 #define S_U_OCLK_MUXSEL 8
12360 #define M_U_OCLK_MUXSEL 0x3U
12361 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
12362 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
12364 #define S_P_OCLK_MUXSEL 6
12365 #define M_P_OCLK_MUXSEL 0x3U
12366 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
12367 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
12369 #define S_KX_OCLK_MUXSEL 3
12370 #define M_KX_OCLK_MUXSEL 0x7U
12371 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
12372 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
12374 #define S_KR_OCLK_MUXSEL 0
12375 #define M_KR_OCLK_MUXSEL 0x7U
12376 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
12377 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
12379 #define S_T5_P_OCLK_MUXSEL 13
12380 #define M_T5_P_OCLK_MUXSEL 0xfU
12381 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
12382 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
12384 #define S_T6_P_OCLK_MUXSEL 13
12385 #define M_T6_P_OCLK_MUXSEL 0xfU
12386 #define V_T6_P_OCLK_MUXSEL(x) ((x) << S_T6_P_OCLK_MUXSEL)
12387 #define G_T6_P_OCLK_MUXSEL(x) (((x) >> S_T6_P_OCLK_MUXSEL) & M_T6_P_OCLK_MUXSEL)
12389 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
12390 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
12391 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
12392 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
12393 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
12394 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
12395 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
12396 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
12397 #define A_DBG_TRACE_COUNTER 0x6080
12399 #define S_COUNTER1 16
12400 #define M_COUNTER1 0xffffU
12401 #define V_COUNTER1(x) ((x) << S_COUNTER1)
12402 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
12404 #define S_COUNTER0 0
12405 #define M_COUNTER0 0xffffU
12406 #define V_COUNTER0(x) ((x) << S_COUNTER0)
12407 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
12409 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
12411 #define S_STATIC_REFCLK_PERIOD 0
12412 #define M_STATIC_REFCLK_PERIOD 0xffffU
12413 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
12414 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
12416 #define A_DBG_TRACE_CONF 0x6088
12418 #define S_DBG_TRACE_OPERATE_WITH_TRG 5
12419 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
12420 #define F_DBG_TRACE_OPERATE_WITH_TRG V_DBG_TRACE_OPERATE_WITH_TRG(1U)
12422 #define S_DBG_TRACE_OPERATE_EN 4
12423 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
12424 #define F_DBG_TRACE_OPERATE_EN V_DBG_TRACE_OPERATE_EN(1U)
12426 #define S_DBG_OPERATE_INDV_COMBINED 3
12427 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
12428 #define F_DBG_OPERATE_INDV_COMBINED V_DBG_OPERATE_INDV_COMBINED(1U)
12430 #define S_DBG_OPERATE_ORDER_OF_TRIGGER 2
12431 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
12432 #define F_DBG_OPERATE_ORDER_OF_TRIGGER V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
12434 #define S_DBG_OPERATE_SGL_DBL_TRIGGER 1
12435 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
12436 #define F_DBG_OPERATE_SGL_DBL_TRIGGER V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
12438 #define S_DBG_OPERATE0_OR_1 0
12439 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
12440 #define F_DBG_OPERATE0_OR_1 V_DBG_OPERATE0_OR_1(1U)
12442 #define A_DBG_TRACE_RDEN 0x608c
12444 #define S_RD_ADDR1 10
12445 #define M_RD_ADDR1 0xffU
12446 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
12447 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
12449 #define S_RD_ADDR0 2
12450 #define M_RD_ADDR0 0xffU
12451 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
12452 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
12455 #define V_RD_EN1(x) ((x) << S_RD_EN1)
12456 #define F_RD_EN1 V_RD_EN1(1U)
12459 #define V_RD_EN0(x) ((x) << S_RD_EN0)
12460 #define F_RD_EN0 V_RD_EN0(1U)
12462 #define S_T5_RD_ADDR1 11
12463 #define M_T5_RD_ADDR1 0x1ffU
12464 #define V_T5_RD_ADDR1(x) ((x) << S_T5_RD_ADDR1)
12465 #define G_T5_RD_ADDR1(x) (((x) >> S_T5_RD_ADDR1) & M_T5_RD_ADDR1)
12467 #define S_T5_RD_ADDR0 2
12468 #define M_T5_RD_ADDR0 0x1ffU
12469 #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
12470 #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
12472 #define S_T6_RD_ADDR1 11
12473 #define M_T6_RD_ADDR1 0x1ffU
12474 #define V_T6_RD_ADDR1(x) ((x) << S_T6_RD_ADDR1)
12475 #define G_T6_RD_ADDR1(x) (((x) >> S_T6_RD_ADDR1) & M_T6_RD_ADDR1)
12477 #define S_T6_RD_ADDR0 2
12478 #define M_T6_RD_ADDR0 0x1ffU
12479 #define V_T6_RD_ADDR0(x) ((x) << S_T6_RD_ADDR0)
12480 #define G_T6_RD_ADDR0(x) (((x) >> S_T6_RD_ADDR0) & M_T6_RD_ADDR0)
12482 #define A_DBG_TRACE_WRADDR 0x6090
12484 #define S_WR_POINTER_ADDR1 16
12485 #define M_WR_POINTER_ADDR1 0xffU
12486 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
12487 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
12489 #define S_WR_POINTER_ADDR0 0
12490 #define M_WR_POINTER_ADDR0 0xffU
12491 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
12492 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
12494 #define S_T5_WR_POINTER_ADDR1 16
12495 #define M_T5_WR_POINTER_ADDR1 0x1ffU
12496 #define V_T5_WR_POINTER_ADDR1(x) ((x) << S_T5_WR_POINTER_ADDR1)
12497 #define G_T5_WR_POINTER_ADDR1(x) (((x) >> S_T5_WR_POINTER_ADDR1) & M_T5_WR_POINTER_ADDR1)
12499 #define S_T5_WR_POINTER_ADDR0 0
12500 #define M_T5_WR_POINTER_ADDR0 0x1ffU
12501 #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
12502 #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
12504 #define S_T6_WR_POINTER_ADDR1 16
12505 #define M_T6_WR_POINTER_ADDR1 0x1ffU
12506 #define V_T6_WR_POINTER_ADDR1(x) ((x) << S_T6_WR_POINTER_ADDR1)
12507 #define G_T6_WR_POINTER_ADDR1(x) (((x) >> S_T6_WR_POINTER_ADDR1) & M_T6_WR_POINTER_ADDR1)
12509 #define S_T6_WR_POINTER_ADDR0 0
12510 #define M_T6_WR_POINTER_ADDR0 0x1ffU
12511 #define V_T6_WR_POINTER_ADDR0(x) ((x) << S_T6_WR_POINTER_ADDR0)
12512 #define G_T6_WR_POINTER_ADDR0(x) (((x) >> S_T6_WR_POINTER_ADDR0) & M_T6_WR_POINTER_ADDR0)
12514 #define A_DBG_TRACE0_DATA_OUT 0x6094
12515 #define A_DBG_TRACE1_DATA_OUT 0x6098
12516 #define A_DBG_FUSE_SENSE_DONE 0x609c
12518 #define S_STATIC_JTAG_VERSIONNR 5
12519 #define M_STATIC_JTAG_VERSIONNR 0xfU
12520 #define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
12521 #define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
12524 #define M_UNQ0 0xfU
12525 #define V_UNQ0(x) ((x) << S_UNQ0)
12526 #define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
12528 #define S_FUSE_DONE_SENSE 0
12529 #define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
12530 #define F_FUSE_DONE_SENSE V_FUSE_DONE_SENSE(1U)
12532 #define A_DBG_TVSENSE_EN 0x60a8
12534 #define S_MCIMPED1_OUT 29
12535 #define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
12536 #define F_MCIMPED1_OUT V_MCIMPED1_OUT(1U)
12538 #define S_MCIMPED2_OUT 28
12539 #define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
12540 #define F_MCIMPED2_OUT V_MCIMPED2_OUT(1U)
12542 #define S_TVSENSE_SNSOUT 17
12543 #define M_TVSENSE_SNSOUT 0x1ffU
12544 #define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
12545 #define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
12547 #define S_TVSENSE_OUTPUTVALID 16
12548 #define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
12549 #define F_TVSENSE_OUTPUTVALID V_TVSENSE_OUTPUTVALID(1U)
12551 #define S_TVSENSE_SLEEP 10
12552 #define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
12553 #define F_TVSENSE_SLEEP V_TVSENSE_SLEEP(1U)
12555 #define S_TVSENSE_SENSV 9
12556 #define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
12557 #define F_TVSENSE_SENSV V_TVSENSE_SENSV(1U)
12559 #define S_TVSENSE_RST 8
12560 #define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
12561 #define F_TVSENSE_RST V_TVSENSE_RST(1U)
12563 #define S_TVSENSE_RATIO 0
12564 #define M_TVSENSE_RATIO 0xffU
12565 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
12566 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
12568 #define S_T6_TVSENSE_SLEEP 11
12569 #define V_T6_TVSENSE_SLEEP(x) ((x) << S_T6_TVSENSE_SLEEP)
12570 #define F_T6_TVSENSE_SLEEP V_T6_TVSENSE_SLEEP(1U)
12572 #define S_T6_TVSENSE_SENSV 10
12573 #define V_T6_TVSENSE_SENSV(x) ((x) << S_T6_TVSENSE_SENSV)
12574 #define F_T6_TVSENSE_SENSV V_T6_TVSENSE_SENSV(1U)
12576 #define S_T6_TVSENSE_RST 9
12577 #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
12578 #define F_T6_TVSENSE_RST V_T6_TVSENSE_RST(1U)
12580 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
12581 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
12582 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
12584 #define S_DBG_FEENABLE 29
12585 #define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
12586 #define F_DBG_FEENABLE V_DBG_FEENABLE(1U)
12588 #define S_DBG_FEF 23
12589 #define M_DBG_FEF 0x3fU
12590 #define V_DBG_FEF(x) ((x) << S_DBG_FEF)
12591 #define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
12593 #define S_DBG_FEMIMICN 22
12594 #define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
12595 #define F_DBG_FEMIMICN V_DBG_FEMIMICN(1U)
12597 #define S_DBG_FEGATEC 21
12598 #define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
12599 #define F_DBG_FEGATEC V_DBG_FEGATEC(1U)
12601 #define S_DBG_FEPROGP 20
12602 #define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
12603 #define F_DBG_FEPROGP V_DBG_FEPROGP(1U)
12605 #define S_DBG_FEREADCLK 19
12606 #define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
12607 #define F_DBG_FEREADCLK V_DBG_FEREADCLK(1U)
12609 #define S_DBG_FERSEL 3
12610 #define M_DBG_FERSEL 0xffffU
12611 #define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
12612 #define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
12614 #define S_DBG_FETIME 0
12615 #define M_DBG_FETIME 0x7U
12616 #define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
12617 #define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
12619 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
12621 #define S_T5_STATIC_M_PLL_MULTFRAC 8
12622 #define M_T5_STATIC_M_PLL_MULTFRAC 0xffffffU
12623 #define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
12624 #define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
12626 #define S_T5_STATIC_M_PLL_FFSLEWRATE 0
12627 #define M_T5_STATIC_M_PLL_FFSLEWRATE 0xffU
12628 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
12629 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
12631 #define A_DBG_STATIC_M_PLL_CONF1 0x60b8
12633 #define S_STATIC_M_PLL_MULTFRAC 8
12634 #define M_STATIC_M_PLL_MULTFRAC 0xffffffU
12635 #define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC)
12636 #define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC)
12638 #define S_STATIC_M_PLL_FFSLEWRATE 0
12639 #define M_STATIC_M_PLL_FFSLEWRATE 0xffU
12640 #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
12641 #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
12643 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
12645 #define S_T5_STATIC_M_PLL_DCO_BYPASS 23
12646 #define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
12647 #define F_T5_STATIC_M_PLL_DCO_BYPASS V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
12649 #define S_T5_STATIC_M_PLL_SDORDER 21
12650 #define M_T5_STATIC_M_PLL_SDORDER 0x3U
12651 #define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
12652 #define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
12654 #define S_T5_STATIC_M_PLL_FFENABLE 20
12655 #define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
12656 #define F_T5_STATIC_M_PLL_FFENABLE V_T5_STATIC_M_PLL_FFENABLE(1U)
12658 #define S_T5_STATIC_M_PLL_STOPCLKB 19
12659 #define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
12660 #define F_T5_STATIC_M_PLL_STOPCLKB V_T5_STATIC_M_PLL_STOPCLKB(1U)
12662 #define S_T5_STATIC_M_PLL_STOPCLKA 18
12663 #define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
12664 #define F_T5_STATIC_M_PLL_STOPCLKA V_T5_STATIC_M_PLL_STOPCLKA(1U)
12666 #define S_T5_STATIC_M_PLL_SLEEP 17
12667 #define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
12668 #define F_T5_STATIC_M_PLL_SLEEP V_T5_STATIC_M_PLL_SLEEP(1U)
12670 #define S_T5_STATIC_M_PLL_BYPASS 16
12671 #define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
12672 #define F_T5_STATIC_M_PLL_BYPASS V_T5_STATIC_M_PLL_BYPASS(1U)
12674 #define S_T5_STATIC_M_PLL_LOCKTUNE 0
12675 #define M_T5_STATIC_M_PLL_LOCKTUNE 0xffffU
12676 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
12677 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
12679 #define A_DBG_STATIC_M_PLL_CONF2 0x60bc
12681 #define S_T6_STATIC_M_PLL_PREDIV 24
12682 #define M_T6_STATIC_M_PLL_PREDIV 0x3fU
12683 #define V_T6_STATIC_M_PLL_PREDIV(x) ((x) << S_T6_STATIC_M_PLL_PREDIV)
12684 #define G_T6_STATIC_M_PLL_PREDIV(x) (((x) >> S_T6_STATIC_M_PLL_PREDIV) & M_T6_STATIC_M_PLL_PREDIV)
12686 #define S_STATIC_M_PLL_DCO_BYPASS 23
12687 #define V_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_STATIC_M_PLL_DCO_BYPASS)
12688 #define F_STATIC_M_PLL_DCO_BYPASS V_STATIC_M_PLL_DCO_BYPASS(1U)
12690 #define S_STATIC_M_PLL_SDORDER 21
12691 #define M_STATIC_M_PLL_SDORDER 0x3U
12692 #define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER)
12693 #define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER)
12695 #define S_STATIC_M_PLL_FFENABLE 20
12696 #define V_STATIC_M_PLL_FFENABLE(x) ((x) << S_STATIC_M_PLL_FFENABLE)
12697 #define F_STATIC_M_PLL_FFENABLE V_STATIC_M_PLL_FFENABLE(1U)
12699 #define S_STATIC_M_PLL_STOPCLKB 19
12700 #define V_STATIC_M_PLL_STOPCLKB(x) ((x) << S_STATIC_M_PLL_STOPCLKB)
12701 #define F_STATIC_M_PLL_STOPCLKB V_STATIC_M_PLL_STOPCLKB(1U)
12703 #define S_STATIC_M_PLL_STOPCLKA 18
12704 #define V_STATIC_M_PLL_STOPCLKA(x) ((x) << S_STATIC_M_PLL_STOPCLKA)
12705 #define F_STATIC_M_PLL_STOPCLKA V_STATIC_M_PLL_STOPCLKA(1U)
12707 #define S_T6_STATIC_M_PLL_SLEEP 17
12708 #define V_T6_STATIC_M_PLL_SLEEP(x) ((x) << S_T6_STATIC_M_PLL_SLEEP)
12709 #define F_T6_STATIC_M_PLL_SLEEP V_T6_STATIC_M_PLL_SLEEP(1U)
12711 #define S_T6_STATIC_M_PLL_BYPASS 16
12712 #define V_T6_STATIC_M_PLL_BYPASS(x) ((x) << S_T6_STATIC_M_PLL_BYPASS)
12713 #define F_T6_STATIC_M_PLL_BYPASS V_T6_STATIC_M_PLL_BYPASS(1U)
12715 #define S_STATIC_M_PLL_LOCKTUNE 0
12716 #define M_STATIC_M_PLL_LOCKTUNE 0x1fU
12717 #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
12718 #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
12720 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
12722 #define S_T5_STATIC_M_PLL_MULTPRE 30
12723 #define M_T5_STATIC_M_PLL_MULTPRE 0x3U
12724 #define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
12725 #define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
12727 #define S_T5_STATIC_M_PLL_LOCKSEL 28
12728 #define M_T5_STATIC_M_PLL_LOCKSEL 0x3U
12729 #define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
12730 #define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
12732 #define S_T5_STATIC_M_PLL_FFTUNE 12
12733 #define M_T5_STATIC_M_PLL_FFTUNE 0xffffU
12734 #define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
12735 #define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
12737 #define S_T5_STATIC_M_PLL_RANGEPRE 10
12738 #define M_T5_STATIC_M_PLL_RANGEPRE 0x3U
12739 #define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
12740 #define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
12742 #define S_T5_STATIC_M_PLL_RANGEB 5
12743 #define M_T5_STATIC_M_PLL_RANGEB 0x1fU
12744 #define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
12745 #define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
12747 #define S_T5_STATIC_M_PLL_RANGEA 0
12748 #define M_T5_STATIC_M_PLL_RANGEA 0x1fU
12749 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
12750 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
12752 #define A_DBG_STATIC_M_PLL_CONF3 0x60c0
12754 #define S_STATIC_M_PLL_MULTPRE 30
12755 #define M_STATIC_M_PLL_MULTPRE 0x3U
12756 #define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE)
12757 #define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE)
12759 #define S_STATIC_M_PLL_LOCKSEL 28
12760 #define V_STATIC_M_PLL_LOCKSEL(x) ((x) << S_STATIC_M_PLL_LOCKSEL)
12761 #define F_STATIC_M_PLL_LOCKSEL V_STATIC_M_PLL_LOCKSEL(1U)
12763 #define S_STATIC_M_PLL_FFTUNE 12
12764 #define M_STATIC_M_PLL_FFTUNE 0xffffU
12765 #define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE)
12766 #define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE)
12768 #define S_STATIC_M_PLL_RANGEPRE 10
12769 #define M_STATIC_M_PLL_RANGEPRE 0x3U
12770 #define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE)
12771 #define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE)
12773 #define S_T6_STATIC_M_PLL_RANGEB 5
12774 #define M_T6_STATIC_M_PLL_RANGEB 0x1fU
12775 #define V_T6_STATIC_M_PLL_RANGEB(x) ((x) << S_T6_STATIC_M_PLL_RANGEB)
12776 #define G_T6_STATIC_M_PLL_RANGEB(x) (((x) >> S_T6_STATIC_M_PLL_RANGEB) & M_T6_STATIC_M_PLL_RANGEB)
12778 #define S_T6_STATIC_M_PLL_RANGEA 0
12779 #define M_T6_STATIC_M_PLL_RANGEA 0x1fU
12780 #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
12781 #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
12783 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
12784 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
12785 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
12787 #define S_T5_STATIC_M_PLL_VCVTUNE 24
12788 #define M_T5_STATIC_M_PLL_VCVTUNE 0x7U
12789 #define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
12790 #define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
12792 #define S_T5_STATIC_M_PLL_RESET 23
12793 #define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
12794 #define F_T5_STATIC_M_PLL_RESET V_T5_STATIC_M_PLL_RESET(1U)
12796 #define S_T5_STATIC_MPLL_REFCLK_SEL 22
12797 #define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
12798 #define F_T5_STATIC_MPLL_REFCLK_SEL V_T5_STATIC_MPLL_REFCLK_SEL(1U)
12800 #define S_T5_STATIC_M_PLL_LFTUNE_32_40 13
12801 #define M_T5_STATIC_M_PLL_LFTUNE_32_40 0x1ffU
12802 #define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
12803 #define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
12805 #define S_T5_STATIC_M_PLL_PREDIV 8
12806 #define M_T5_STATIC_M_PLL_PREDIV 0x1fU
12807 #define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
12808 #define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
12810 #define S_T5_STATIC_M_PLL_MULT 0
12811 #define M_T5_STATIC_M_PLL_MULT 0xffU
12812 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
12813 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
12815 #define A_DBG_STATIC_M_PLL_CONF5 0x60c8
12817 #define S_STATIC_M_PLL_VCVTUNE 24
12818 #define M_STATIC_M_PLL_VCVTUNE 0x7U
12819 #define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE)
12820 #define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE)
12822 #define S_T6_STATIC_M_PLL_RESET 23
12823 #define V_T6_STATIC_M_PLL_RESET(x) ((x) << S_T6_STATIC_M_PLL_RESET)
12824 #define F_T6_STATIC_M_PLL_RESET V_T6_STATIC_M_PLL_RESET(1U)
12826 #define S_STATIC_MPLL_REFCLK_SEL 22
12827 #define V_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_STATIC_MPLL_REFCLK_SEL)
12828 #define F_STATIC_MPLL_REFCLK_SEL V_STATIC_MPLL_REFCLK_SEL(1U)
12830 #define S_STATIC_M_PLL_LFTUNE_32_40 13
12831 #define M_STATIC_M_PLL_LFTUNE_32_40 0x1ffU
12832 #define V_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_M_PLL_LFTUNE_32_40)
12833 #define G_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_M_PLL_LFTUNE_32_40) & M_STATIC_M_PLL_LFTUNE_32_40)
12835 #define S_T6_STATIC_M_PLL_MULT 0
12836 #define M_T6_STATIC_M_PLL_MULT 0xffU
12837 #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
12838 #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
12840 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
12842 #define S_T5_STATIC_PHY0RECRST_ 5
12843 #define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
12844 #define F_T5_STATIC_PHY0RECRST_ V_T5_STATIC_PHY0RECRST_(1U)
12846 #define S_T5_STATIC_PHY1RECRST_ 4
12847 #define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
12848 #define F_T5_STATIC_PHY1RECRST_ V_T5_STATIC_PHY1RECRST_(1U)
12850 #define S_T5_STATIC_SWMC0RST_ 3
12851 #define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
12852 #define F_T5_STATIC_SWMC0RST_ V_T5_STATIC_SWMC0RST_(1U)
12854 #define S_T5_STATIC_SWMC0CFGRST_ 2
12855 #define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
12856 #define F_T5_STATIC_SWMC0CFGRST_ V_T5_STATIC_SWMC0CFGRST_(1U)
12858 #define S_T5_STATIC_SWMC1RST_ 1
12859 #define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
12860 #define F_T5_STATIC_SWMC1RST_ V_T5_STATIC_SWMC1RST_(1U)
12862 #define S_T5_STATIC_SWMC1CFGRST_ 0
12863 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
12864 #define F_T5_STATIC_SWMC1CFGRST_ V_T5_STATIC_SWMC1CFGRST_(1U)
12866 #define A_DBG_STATIC_M_PLL_CONF6 0x60cc
12868 #define S_STATIC_M_PLL_DIVCHANGE 30
12869 #define V_STATIC_M_PLL_DIVCHANGE(x) ((x) << S_STATIC_M_PLL_DIVCHANGE)
12870 #define F_STATIC_M_PLL_DIVCHANGE V_STATIC_M_PLL_DIVCHANGE(1U)
12872 #define S_STATIC_M_PLL_FRAMESTOP 29
12873 #define V_STATIC_M_PLL_FRAMESTOP(x) ((x) << S_STATIC_M_PLL_FRAMESTOP)
12874 #define F_STATIC_M_PLL_FRAMESTOP V_STATIC_M_PLL_FRAMESTOP(1U)
12876 #define S_STATIC_M_PLL_FASTSTOP 28
12877 #define V_STATIC_M_PLL_FASTSTOP(x) ((x) << S_STATIC_M_PLL_FASTSTOP)
12878 #define F_STATIC_M_PLL_FASTSTOP V_STATIC_M_PLL_FASTSTOP(1U)
12880 #define S_STATIC_M_PLL_FFBYPASS 27
12881 #define V_STATIC_M_PLL_FFBYPASS(x) ((x) << S_STATIC_M_PLL_FFBYPASS)
12882 #define F_STATIC_M_PLL_FFBYPASS V_STATIC_M_PLL_FFBYPASS(1U)
12884 #define S_STATIC_M_PLL_STARTUP 25
12885 #define M_STATIC_M_PLL_STARTUP 0x3U
12886 #define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP)
12887 #define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP)
12889 #define S_STATIC_M_PLL_VREGTUNE 6
12890 #define M_STATIC_M_PLL_VREGTUNE 0x7ffffU
12891 #define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE)
12892 #define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE)
12894 #define S_STATIC_PHY0RECRST_ 5
12895 #define V_STATIC_PHY0RECRST_(x) ((x) << S_STATIC_PHY0RECRST_)
12896 #define F_STATIC_PHY0RECRST_ V_STATIC_PHY0RECRST_(1U)
12898 #define S_STATIC_PHY1RECRST_ 4
12899 #define V_STATIC_PHY1RECRST_(x) ((x) << S_STATIC_PHY1RECRST_)
12900 #define F_STATIC_PHY1RECRST_ V_STATIC_PHY1RECRST_(1U)
12902 #define S_STATIC_SWMC0RST_ 3
12903 #define V_STATIC_SWMC0RST_(x) ((x) << S_STATIC_SWMC0RST_)
12904 #define F_STATIC_SWMC0RST_ V_STATIC_SWMC0RST_(1U)
12906 #define S_STATIC_SWMC0CFGRST_ 2
12907 #define V_STATIC_SWMC0CFGRST_(x) ((x) << S_STATIC_SWMC0CFGRST_)
12908 #define F_STATIC_SWMC0CFGRST_ V_STATIC_SWMC0CFGRST_(1U)
12910 #define S_STATIC_SWMC1RST_ 1
12911 #define V_STATIC_SWMC1RST_(x) ((x) << S_STATIC_SWMC1RST_)
12912 #define F_STATIC_SWMC1RST_ V_STATIC_SWMC1RST_(1U)
12914 #define S_STATIC_SWMC1CFGRST_ 0
12915 #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
12916 #define F_STATIC_SWMC1CFGRST_ V_STATIC_SWMC1CFGRST_(1U)
12918 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
12920 #define S_T5_STATIC_C_PLL_MULTFRAC 8
12921 #define M_T5_STATIC_C_PLL_MULTFRAC 0xffffffU
12922 #define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
12923 #define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
12925 #define S_T5_STATIC_C_PLL_FFSLEWRATE 0
12926 #define M_T5_STATIC_C_PLL_FFSLEWRATE 0xffU
12927 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
12928 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
12930 #define A_DBG_STATIC_C_PLL_CONF1 0x60d0
12932 #define S_STATIC_C_PLL_MULTFRAC 8
12933 #define M_STATIC_C_PLL_MULTFRAC 0xffffffU
12934 #define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC)
12935 #define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC)
12937 #define S_STATIC_C_PLL_FFSLEWRATE 0
12938 #define M_STATIC_C_PLL_FFSLEWRATE 0xffU
12939 #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
12940 #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
12942 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
12944 #define S_T5_STATIC_C_PLL_DCO_BYPASS 23
12945 #define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
12946 #define F_T5_STATIC_C_PLL_DCO_BYPASS V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
12948 #define S_T5_STATIC_C_PLL_SDORDER 21
12949 #define M_T5_STATIC_C_PLL_SDORDER 0x3U
12950 #define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
12951 #define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
12953 #define S_T5_STATIC_C_PLL_FFENABLE 20
12954 #define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
12955 #define F_T5_STATIC_C_PLL_FFENABLE V_T5_STATIC_C_PLL_FFENABLE(1U)
12957 #define S_T5_STATIC_C_PLL_STOPCLKB 19
12958 #define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
12959 #define F_T5_STATIC_C_PLL_STOPCLKB V_T5_STATIC_C_PLL_STOPCLKB(1U)
12961 #define S_T5_STATIC_C_PLL_STOPCLKA 18
12962 #define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
12963 #define F_T5_STATIC_C_PLL_STOPCLKA V_T5_STATIC_C_PLL_STOPCLKA(1U)
12965 #define S_T5_STATIC_C_PLL_SLEEP 17
12966 #define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
12967 #define F_T5_STATIC_C_PLL_SLEEP V_T5_STATIC_C_PLL_SLEEP(1U)
12969 #define S_T5_STATIC_C_PLL_BYPASS 16
12970 #define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
12971 #define F_T5_STATIC_C_PLL_BYPASS V_T5_STATIC_C_PLL_BYPASS(1U)
12973 #define S_T5_STATIC_C_PLL_LOCKTUNE 0
12974 #define M_T5_STATIC_C_PLL_LOCKTUNE 0xffffU
12975 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
12976 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
12978 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
12980 #define S_T6_STATIC_C_PLL_PREDIV 26
12981 #define M_T6_STATIC_C_PLL_PREDIV 0x3fU
12982 #define V_T6_STATIC_C_PLL_PREDIV(x) ((x) << S_T6_STATIC_C_PLL_PREDIV)
12983 #define G_T6_STATIC_C_PLL_PREDIV(x) (((x) >> S_T6_STATIC_C_PLL_PREDIV) & M_T6_STATIC_C_PLL_PREDIV)
12985 #define S_STATIC_C_PLL_STARTUP 24
12986 #define M_STATIC_C_PLL_STARTUP 0x3U
12987 #define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP)
12988 #define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP)
12990 #define S_STATIC_C_PLL_DCO_BYPASS 23
12991 #define V_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_STATIC_C_PLL_DCO_BYPASS)
12992 #define F_STATIC_C_PLL_DCO_BYPASS V_STATIC_C_PLL_DCO_BYPASS(1U)
12994 #define S_STATIC_C_PLL_SDORDER 21
12995 #define M_STATIC_C_PLL_SDORDER 0x3U
12996 #define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER)
12997 #define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER)
12999 #define S_STATIC_C_PLL_DIVCHANGE 20
13000 #define V_STATIC_C_PLL_DIVCHANGE(x) ((x) << S_STATIC_C_PLL_DIVCHANGE)
13001 #define F_STATIC_C_PLL_DIVCHANGE V_STATIC_C_PLL_DIVCHANGE(1U)
13003 #define S_STATIC_C_PLL_STOPCLKB 19
13004 #define V_STATIC_C_PLL_STOPCLKB(x) ((x) << S_STATIC_C_PLL_STOPCLKB)
13005 #define F_STATIC_C_PLL_STOPCLKB V_STATIC_C_PLL_STOPCLKB(1U)
13007 #define S_STATIC_C_PLL_STOPCLKA 18
13008 #define V_STATIC_C_PLL_STOPCLKA(x) ((x) << S_STATIC_C_PLL_STOPCLKA)
13009 #define F_STATIC_C_PLL_STOPCLKA V_STATIC_C_PLL_STOPCLKA(1U)
13011 #define S_T6_STATIC_C_PLL_SLEEP 17
13012 #define V_T6_STATIC_C_PLL_SLEEP(x) ((x) << S_T6_STATIC_C_PLL_SLEEP)
13013 #define F_T6_STATIC_C_PLL_SLEEP V_T6_STATIC_C_PLL_SLEEP(1U)
13015 #define S_T6_STATIC_C_PLL_BYPASS 16
13016 #define V_T6_STATIC_C_PLL_BYPASS(x) ((x) << S_T6_STATIC_C_PLL_BYPASS)
13017 #define F_T6_STATIC_C_PLL_BYPASS V_T6_STATIC_C_PLL_BYPASS(1U)
13019 #define S_STATIC_C_PLL_LOCKTUNE 0
13020 #define M_STATIC_C_PLL_LOCKTUNE 0x1fU
13021 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
13022 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
13024 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
13026 #define S_T5_STATIC_C_PLL_MULTPRE 30
13027 #define M_T5_STATIC_C_PLL_MULTPRE 0x3U
13028 #define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
13029 #define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
13031 #define S_T5_STATIC_C_PLL_LOCKSEL 28
13032 #define M_T5_STATIC_C_PLL_LOCKSEL 0x3U
13033 #define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
13034 #define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
13036 #define S_T5_STATIC_C_PLL_FFTUNE 12
13037 #define M_T5_STATIC_C_PLL_FFTUNE 0xffffU
13038 #define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
13039 #define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
13041 #define S_T5_STATIC_C_PLL_RANGEPRE 10
13042 #define M_T5_STATIC_C_PLL_RANGEPRE 0x3U
13043 #define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
13044 #define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
13046 #define S_T5_STATIC_C_PLL_RANGEB 5
13047 #define M_T5_STATIC_C_PLL_RANGEB 0x1fU
13048 #define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
13049 #define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
13051 #define S_T5_STATIC_C_PLL_RANGEA 0
13052 #define M_T5_STATIC_C_PLL_RANGEA 0x1fU
13053 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
13054 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
13056 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
13058 #define S_STATIC_C_PLL_MULTPRE 30
13059 #define M_STATIC_C_PLL_MULTPRE 0x3U
13060 #define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE)
13061 #define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE)
13063 #define S_STATIC_C_PLL_LOCKSEL 28
13064 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
13065 #define F_STATIC_C_PLL_LOCKSEL V_STATIC_C_PLL_LOCKSEL(1U)
13067 #define S_STATIC_C_PLL_FFTUNE 12
13068 #define M_STATIC_C_PLL_FFTUNE 0xffffU
13069 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
13070 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
13072 #define S_STATIC_C_PLL_RANGEPRE 10
13073 #define M_STATIC_C_PLL_RANGEPRE 0x3U
13074 #define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE)
13075 #define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE)
13077 #define S_T6_STATIC_C_PLL_RANGEB 5
13078 #define M_T6_STATIC_C_PLL_RANGEB 0x1fU
13079 #define V_T6_STATIC_C_PLL_RANGEB(x) ((x) << S_T6_STATIC_C_PLL_RANGEB)
13080 #define G_T6_STATIC_C_PLL_RANGEB(x) (((x) >> S_T6_STATIC_C_PLL_RANGEB) & M_T6_STATIC_C_PLL_RANGEB)
13082 #define S_T6_STATIC_C_PLL_RANGEA 0
13083 #define M_T6_STATIC_C_PLL_RANGEA 0x1fU
13084 #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
13085 #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
13087 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
13088 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
13089 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
13091 #define S_T5_STATIC_C_PLL_VCVTUNE 22
13092 #define M_T5_STATIC_C_PLL_VCVTUNE 0x7U
13093 #define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
13094 #define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
13096 #define S_T5_STATIC_C_PLL_LFTUNE_32_40 13
13097 #define M_T5_STATIC_C_PLL_LFTUNE_32_40 0x1ffU
13098 #define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
13099 #define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
13101 #define S_T5_STATIC_C_PLL_PREDIV 8
13102 #define M_T5_STATIC_C_PLL_PREDIV 0x1fU
13103 #define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
13104 #define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
13106 #define S_T5_STATIC_C_PLL_MULT 0
13107 #define M_T5_STATIC_C_PLL_MULT 0xffU
13108 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
13109 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
13111 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
13113 #define S_STATIC_C_PLL_FFBYPASS 27
13114 #define V_STATIC_C_PLL_FFBYPASS(x) ((x) << S_STATIC_C_PLL_FFBYPASS)
13115 #define F_STATIC_C_PLL_FFBYPASS V_STATIC_C_PLL_FFBYPASS(1U)
13117 #define S_STATIC_C_PLL_FASTSTOP 26
13118 #define V_STATIC_C_PLL_FASTSTOP(x) ((x) << S_STATIC_C_PLL_FASTSTOP)
13119 #define F_STATIC_C_PLL_FASTSTOP V_STATIC_C_PLL_FASTSTOP(1U)
13121 #define S_STATIC_C_PLL_FRAMESTOP 25
13122 #define V_STATIC_C_PLL_FRAMESTOP(x) ((x) << S_STATIC_C_PLL_FRAMESTOP)
13123 #define F_STATIC_C_PLL_FRAMESTOP V_STATIC_C_PLL_FRAMESTOP(1U)
13125 #define S_STATIC_C_PLL_VCVTUNE 22
13126 #define M_STATIC_C_PLL_VCVTUNE 0x7U
13127 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
13128 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
13130 #define S_STATIC_C_PLL_LFTUNE_32_40 13
13131 #define M_STATIC_C_PLL_LFTUNE_32_40 0x1ffU
13132 #define V_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_C_PLL_LFTUNE_32_40)
13133 #define G_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_C_PLL_LFTUNE_32_40) & M_STATIC_C_PLL_LFTUNE_32_40)
13135 #define S_STATIC_C_PLL_PREDIV_CNF5 8
13136 #define M_STATIC_C_PLL_PREDIV_CNF5 0x1fU
13137 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
13138 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
13140 #define S_T6_STATIC_C_PLL_MULT 0
13141 #define M_T6_STATIC_C_PLL_MULT 0xffU
13142 #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
13143 #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
13145 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
13147 #define S_T5_STATIC_U_PLL_MULTFRAC 8
13148 #define M_T5_STATIC_U_PLL_MULTFRAC 0xffffffU
13149 #define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
13150 #define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
13152 #define S_T5_STATIC_U_PLL_FFSLEWRATE 0
13153 #define M_T5_STATIC_U_PLL_FFSLEWRATE 0xffU
13154 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
13155 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
13157 #define A_DBG_STATIC_U_PLL_CONF1 0x60e4
13159 #define S_STATIC_U_PLL_MULTFRAC 8
13160 #define M_STATIC_U_PLL_MULTFRAC 0xffffffU
13161 #define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC)
13162 #define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC)
13164 #define S_STATIC_U_PLL_FFSLEWRATE 0
13165 #define M_STATIC_U_PLL_FFSLEWRATE 0xffU
13166 #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
13167 #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
13169 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
13171 #define S_T5_STATIC_U_PLL_DCO_BYPASS 23
13172 #define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
13173 #define F_T5_STATIC_U_PLL_DCO_BYPASS V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
13175 #define S_T5_STATIC_U_PLL_SDORDER 21
13176 #define M_T5_STATIC_U_PLL_SDORDER 0x3U
13177 #define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
13178 #define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
13180 #define S_T5_STATIC_U_PLL_FFENABLE 20
13181 #define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
13182 #define F_T5_STATIC_U_PLL_FFENABLE V_T5_STATIC_U_PLL_FFENABLE(1U)
13184 #define S_T5_STATIC_U_PLL_STOPCLKB 19
13185 #define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
13186 #define F_T5_STATIC_U_PLL_STOPCLKB V_T5_STATIC_U_PLL_STOPCLKB(1U)
13188 #define S_T5_STATIC_U_PLL_STOPCLKA 18
13189 #define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
13190 #define F_T5_STATIC_U_PLL_STOPCLKA V_T5_STATIC_U_PLL_STOPCLKA(1U)
13192 #define S_T5_STATIC_U_PLL_SLEEP 17
13193 #define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
13194 #define F_T5_STATIC_U_PLL_SLEEP V_T5_STATIC_U_PLL_SLEEP(1U)
13196 #define S_T5_STATIC_U_PLL_BYPASS 16
13197 #define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
13198 #define F_T5_STATIC_U_PLL_BYPASS V_T5_STATIC_U_PLL_BYPASS(1U)
13200 #define S_T5_STATIC_U_PLL_LOCKTUNE 0
13201 #define M_T5_STATIC_U_PLL_LOCKTUNE 0xffffU
13202 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
13203 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
13205 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
13207 #define S_T6_STATIC_U_PLL_PREDIV 26
13208 #define M_T6_STATIC_U_PLL_PREDIV 0x3fU
13209 #define V_T6_STATIC_U_PLL_PREDIV(x) ((x) << S_T6_STATIC_U_PLL_PREDIV)
13210 #define G_T6_STATIC_U_PLL_PREDIV(x) (((x) >> S_T6_STATIC_U_PLL_PREDIV) & M_T6_STATIC_U_PLL_PREDIV)
13212 #define S_STATIC_U_PLL_STARTUP 24
13213 #define M_STATIC_U_PLL_STARTUP 0x3U
13214 #define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP)
13215 #define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP)
13217 #define S_STATIC_U_PLL_DCO_BYPASS 23
13218 #define V_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_STATIC_U_PLL_DCO_BYPASS)
13219 #define F_STATIC_U_PLL_DCO_BYPASS V_STATIC_U_PLL_DCO_BYPASS(1U)
13221 #define S_STATIC_U_PLL_SDORDER 21
13222 #define M_STATIC_U_PLL_SDORDER 0x3U
13223 #define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER)
13224 #define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER)
13226 #define S_STATIC_U_PLL_DIVCHANGE 20
13227 #define V_STATIC_U_PLL_DIVCHANGE(x) ((x) << S_STATIC_U_PLL_DIVCHANGE)
13228 #define F_STATIC_U_PLL_DIVCHANGE V_STATIC_U_PLL_DIVCHANGE(1U)
13230 #define S_STATIC_U_PLL_STOPCLKB 19
13231 #define V_STATIC_U_PLL_STOPCLKB(x) ((x) << S_STATIC_U_PLL_STOPCLKB)
13232 #define F_STATIC_U_PLL_STOPCLKB V_STATIC_U_PLL_STOPCLKB(1U)
13234 #define S_STATIC_U_PLL_STOPCLKA 18
13235 #define V_STATIC_U_PLL_STOPCLKA(x) ((x) << S_STATIC_U_PLL_STOPCLKA)
13236 #define F_STATIC_U_PLL_STOPCLKA V_STATIC_U_PLL_STOPCLKA(1U)
13238 #define S_T6_STATIC_U_PLL_SLEEP 17
13239 #define V_T6_STATIC_U_PLL_SLEEP(x) ((x) << S_T6_STATIC_U_PLL_SLEEP)
13240 #define F_T6_STATIC_U_PLL_SLEEP V_T6_STATIC_U_PLL_SLEEP(1U)
13242 #define S_T6_STATIC_U_PLL_BYPASS 16
13243 #define V_T6_STATIC_U_PLL_BYPASS(x) ((x) << S_T6_STATIC_U_PLL_BYPASS)
13244 #define F_T6_STATIC_U_PLL_BYPASS V_T6_STATIC_U_PLL_BYPASS(1U)
13246 #define S_STATIC_U_PLL_LOCKTUNE 0
13247 #define M_STATIC_U_PLL_LOCKTUNE 0x1fU
13248 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
13249 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
13251 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
13253 #define S_T5_STATIC_U_PLL_MULTPRE 30
13254 #define M_T5_STATIC_U_PLL_MULTPRE 0x3U
13255 #define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
13256 #define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
13258 #define S_T5_STATIC_U_PLL_LOCKSEL 28
13259 #define M_T5_STATIC_U_PLL_LOCKSEL 0x3U
13260 #define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
13261 #define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
13263 #define S_T5_STATIC_U_PLL_FFTUNE 12
13264 #define M_T5_STATIC_U_PLL_FFTUNE 0xffffU
13265 #define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
13266 #define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
13268 #define S_T5_STATIC_U_PLL_RANGEPRE 10
13269 #define M_T5_STATIC_U_PLL_RANGEPRE 0x3U
13270 #define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
13271 #define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
13273 #define S_T5_STATIC_U_PLL_RANGEB 5
13274 #define M_T5_STATIC_U_PLL_RANGEB 0x1fU
13275 #define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
13276 #define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
13278 #define S_T5_STATIC_U_PLL_RANGEA 0
13279 #define M_T5_STATIC_U_PLL_RANGEA 0x1fU
13280 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
13281 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
13283 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
13285 #define S_STATIC_U_PLL_MULTPRE 30
13286 #define M_STATIC_U_PLL_MULTPRE 0x3U
13287 #define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE)
13288 #define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE)
13290 #define S_STATIC_U_PLL_LOCKSEL 28
13291 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
13292 #define F_STATIC_U_PLL_LOCKSEL V_STATIC_U_PLL_LOCKSEL(1U)
13294 #define S_STATIC_U_PLL_FFTUNE 12
13295 #define M_STATIC_U_PLL_FFTUNE 0xffffU
13296 #define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE)
13297 #define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE)
13299 #define S_STATIC_U_PLL_RANGEPRE 10
13300 #define M_STATIC_U_PLL_RANGEPRE 0x3U
13301 #define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE)
13302 #define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE)
13304 #define S_T6_STATIC_U_PLL_RANGEB 5
13305 #define M_T6_STATIC_U_PLL_RANGEB 0x1fU
13306 #define V_T6_STATIC_U_PLL_RANGEB(x) ((x) << S_T6_STATIC_U_PLL_RANGEB)
13307 #define G_T6_STATIC_U_PLL_RANGEB(x) (((x) >> S_T6_STATIC_U_PLL_RANGEB) & M_T6_STATIC_U_PLL_RANGEB)
13309 #define S_T6_STATIC_U_PLL_RANGEA 0
13310 #define M_T6_STATIC_U_PLL_RANGEA 0x1fU
13311 #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
13312 #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
13314 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
13315 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
13316 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
13318 #define S_T5_STATIC_U_PLL_VCVTUNE 22
13319 #define M_T5_STATIC_U_PLL_VCVTUNE 0x7U
13320 #define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
13321 #define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
13323 #define S_T5_STATIC_U_PLL_LFTUNE_32_40 13
13324 #define M_T5_STATIC_U_PLL_LFTUNE_32_40 0x1ffU
13325 #define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
13326 #define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
13328 #define S_T5_STATIC_U_PLL_PREDIV 8
13329 #define M_T5_STATIC_U_PLL_PREDIV 0x1fU
13330 #define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
13331 #define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
13333 #define S_T5_STATIC_U_PLL_MULT 0
13334 #define M_T5_STATIC_U_PLL_MULT 0xffU
13335 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
13336 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
13338 #define A_DBG_STATIC_U_PLL_CONF5 0x60f4
13340 #define S_STATIC_U_PLL_FFBYPASS 27
13341 #define V_STATIC_U_PLL_FFBYPASS(x) ((x) << S_STATIC_U_PLL_FFBYPASS)
13342 #define F_STATIC_U_PLL_FFBYPASS V_STATIC_U_PLL_FFBYPASS(1U)
13344 #define S_STATIC_U_PLL_FASTSTOP 26
13345 #define V_STATIC_U_PLL_FASTSTOP(x) ((x) << S_STATIC_U_PLL_FASTSTOP)
13346 #define F_STATIC_U_PLL_FASTSTOP V_STATIC_U_PLL_FASTSTOP(1U)
13348 #define S_STATIC_U_PLL_FRAMESTOP 25
13349 #define V_STATIC_U_PLL_FRAMESTOP(x) ((x) << S_STATIC_U_PLL_FRAMESTOP)
13350 #define F_STATIC_U_PLL_FRAMESTOP V_STATIC_U_PLL_FRAMESTOP(1U)
13352 #define S_STATIC_U_PLL_VCVTUNE 22
13353 #define M_STATIC_U_PLL_VCVTUNE 0x7U
13354 #define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE)
13355 #define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE)
13357 #define S_STATIC_U_PLL_LFTUNE_32_40 13
13358 #define M_STATIC_U_PLL_LFTUNE_32_40 0x1ffU
13359 #define V_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_U_PLL_LFTUNE_32_40)
13360 #define G_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_U_PLL_LFTUNE_32_40) & M_STATIC_U_PLL_LFTUNE_32_40)
13362 #define S_STATIC_U_PLL_PREDIV_CNF5 8
13363 #define M_STATIC_U_PLL_PREDIV_CNF5 0x1fU
13364 #define V_STATIC_U_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_U_PLL_PREDIV_CNF5)
13365 #define G_STATIC_U_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_U_PLL_PREDIV_CNF5) & M_STATIC_U_PLL_PREDIV_CNF5)
13367 #define S_T6_STATIC_U_PLL_MULT 0
13368 #define M_T6_STATIC_U_PLL_MULT 0xffU
13369 #define V_T6_STATIC_U_PLL_MULT(x) ((x) << S_T6_STATIC_U_PLL_MULT)
13370 #define G_T6_STATIC_U_PLL_MULT(x) (((x) >> S_T6_STATIC_U_PLL_MULT) & M_T6_STATIC_U_PLL_MULT)
13372 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
13374 #define S_T5_STATIC_KR_PLL_BYPASS 30
13375 #define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
13376 #define F_T5_STATIC_KR_PLL_BYPASS V_T5_STATIC_KR_PLL_BYPASS(1U)
13378 #define S_T5_STATIC_KR_PLL_VBOOSTDIV 27
13379 #define M_T5_STATIC_KR_PLL_VBOOSTDIV 0x7U
13380 #define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
13381 #define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
13383 #define S_T5_STATIC_KR_PLL_CPISEL 24
13384 #define M_T5_STATIC_KR_PLL_CPISEL 0x7U
13385 #define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
13386 #define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
13388 #define S_T5_STATIC_KR_PLL_CCALMETHOD 23
13389 #define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
13390 #define F_T5_STATIC_KR_PLL_CCALMETHOD V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
13392 #define S_T5_STATIC_KR_PLL_CCALLOAD 22
13393 #define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
13394 #define F_T5_STATIC_KR_PLL_CCALLOAD V_T5_STATIC_KR_PLL_CCALLOAD(1U)
13396 #define S_T5_STATIC_KR_PLL_CCALFMIN 21
13397 #define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
13398 #define F_T5_STATIC_KR_PLL_CCALFMIN V_T5_STATIC_KR_PLL_CCALFMIN(1U)
13400 #define S_T5_STATIC_KR_PLL_CCALFMAX 20
13401 #define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
13402 #define F_T5_STATIC_KR_PLL_CCALFMAX V_T5_STATIC_KR_PLL_CCALFMAX(1U)
13404 #define S_T5_STATIC_KR_PLL_CCALCVHOLD 19
13405 #define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
13406 #define F_T5_STATIC_KR_PLL_CCALCVHOLD V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
13408 #define S_T5_STATIC_KR_PLL_CCALBANDSEL 15
13409 #define M_T5_STATIC_KR_PLL_CCALBANDSEL 0xfU
13410 #define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
13411 #define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
13413 #define S_T5_STATIC_KR_PLL_BGOFFSET 11
13414 #define M_T5_STATIC_KR_PLL_BGOFFSET 0xfU
13415 #define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
13416 #define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
13418 #define S_T5_STATIC_KR_PLL_P 8
13419 #define M_T5_STATIC_KR_PLL_P 0x7U
13420 #define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
13421 #define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
13423 #define S_T5_STATIC_KR_PLL_N2 4
13424 #define M_T5_STATIC_KR_PLL_N2 0xfU
13425 #define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
13426 #define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
13428 #define S_T5_STATIC_KR_PLL_N1 0
13429 #define M_T5_STATIC_KR_PLL_N1 0xfU
13430 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
13431 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
13433 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
13435 #define S_T6_STATIC_KR_PLL_BYPASS 30
13436 #define V_T6_STATIC_KR_PLL_BYPASS(x) ((x) << S_T6_STATIC_KR_PLL_BYPASS)
13437 #define F_T6_STATIC_KR_PLL_BYPASS V_T6_STATIC_KR_PLL_BYPASS(1U)
13439 #define S_STATIC_KR_PLL_VBOOSTDIV 27
13440 #define M_STATIC_KR_PLL_VBOOSTDIV 0x7U
13441 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
13442 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
13444 #define S_STATIC_KR_PLL_CPISEL 24
13445 #define M_STATIC_KR_PLL_CPISEL 0x7U
13446 #define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL)
13447 #define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL)
13449 #define S_STATIC_KR_PLL_CCALMETHOD 23
13450 #define V_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_STATIC_KR_PLL_CCALMETHOD)
13451 #define F_STATIC_KR_PLL_CCALMETHOD V_STATIC_KR_PLL_CCALMETHOD(1U)
13453 #define S_STATIC_KR_PLL_CCALLOAD 22
13454 #define V_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_STATIC_KR_PLL_CCALLOAD)
13455 #define F_STATIC_KR_PLL_CCALLOAD V_STATIC_KR_PLL_CCALLOAD(1U)
13457 #define S_STATIC_KR_PLL_CCALFMIN 21
13458 #define V_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_STATIC_KR_PLL_CCALFMIN)
13459 #define F_STATIC_KR_PLL_CCALFMIN V_STATIC_KR_PLL_CCALFMIN(1U)
13461 #define S_STATIC_KR_PLL_CCALFMAX 20
13462 #define V_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_STATIC_KR_PLL_CCALFMAX)
13463 #define F_STATIC_KR_PLL_CCALFMAX V_STATIC_KR_PLL_CCALFMAX(1U)
13465 #define S_STATIC_KR_PLL_CCALCVHOLD 19
13466 #define V_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KR_PLL_CCALCVHOLD)
13467 #define F_STATIC_KR_PLL_CCALCVHOLD V_STATIC_KR_PLL_CCALCVHOLD(1U)
13469 #define S_STATIC_KR_PLL_CCALBANDSEL 15
13470 #define M_STATIC_KR_PLL_CCALBANDSEL 0xfU
13471 #define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL)
13472 #define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL)
13474 #define S_STATIC_KR_PLL_BGOFFSET 11
13475 #define M_STATIC_KR_PLL_BGOFFSET 0xfU
13476 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
13477 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
13479 #define S_T6_STATIC_KR_PLL_P 8
13480 #define M_T6_STATIC_KR_PLL_P 0x7U
13481 #define V_T6_STATIC_KR_PLL_P(x) ((x) << S_T6_STATIC_KR_PLL_P)
13482 #define G_T6_STATIC_KR_PLL_P(x) (((x) >> S_T6_STATIC_KR_PLL_P) & M_T6_STATIC_KR_PLL_P)
13484 #define S_T6_STATIC_KR_PLL_N2 4
13485 #define M_T6_STATIC_KR_PLL_N2 0xfU
13486 #define V_T6_STATIC_KR_PLL_N2(x) ((x) << S_T6_STATIC_KR_PLL_N2)
13487 #define G_T6_STATIC_KR_PLL_N2(x) (((x) >> S_T6_STATIC_KR_PLL_N2) & M_T6_STATIC_KR_PLL_N2)
13489 #define S_T6_STATIC_KR_PLL_N1 0
13490 #define M_T6_STATIC_KR_PLL_N1 0xfU
13491 #define V_T6_STATIC_KR_PLL_N1(x) ((x) << S_T6_STATIC_KR_PLL_N1)
13492 #define G_T6_STATIC_KR_PLL_N1(x) (((x) >> S_T6_STATIC_KR_PLL_N1) & M_T6_STATIC_KR_PLL_N1)
13494 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
13496 #define S_T5_STATIC_KR_PLL_M 11
13497 #define M_T5_STATIC_KR_PLL_M 0x1ffU
13498 #define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
13499 #define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
13501 #define S_T5_STATIC_KR_PLL_ANALOGTUNE 0
13502 #define M_T5_STATIC_KR_PLL_ANALOGTUNE 0x7ffU
13503 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
13504 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
13506 #define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
13508 #define S_T6_STATIC_KR_PLL_M 11
13509 #define M_T6_STATIC_KR_PLL_M 0x1ffU
13510 #define V_T6_STATIC_KR_PLL_M(x) ((x) << S_T6_STATIC_KR_PLL_M)
13511 #define G_T6_STATIC_KR_PLL_M(x) (((x) >> S_T6_STATIC_KR_PLL_M) & M_T6_STATIC_KR_PLL_M)
13513 #define S_STATIC_KR_PLL_ANALOGTUNE 0
13514 #define M_STATIC_KR_PLL_ANALOGTUNE 0x7ffU
13515 #define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE)
13516 #define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE)
13518 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
13520 #define S_HALT_CALIBRATE 1
13521 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
13522 #define F_HALT_CALIBRATE V_HALT_CALIBRATE(1U)
13524 #define S_RESET_CALIBRATE 0
13525 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
13526 #define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U)
13528 #define A_DBG_GPIO_EN_NEW 0x6100
13530 #define S_GPIO16_OEN 7
13531 #define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
13532 #define F_GPIO16_OEN V_GPIO16_OEN(1U)
13534 #define S_GPIO17_OEN 6
13535 #define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
13536 #define F_GPIO17_OEN V_GPIO17_OEN(1U)
13538 #define S_GPIO18_OEN 5
13539 #define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
13540 #define F_GPIO18_OEN V_GPIO18_OEN(1U)
13542 #define S_GPIO19_OEN 4
13543 #define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
13544 #define F_GPIO19_OEN V_GPIO19_OEN(1U)
13546 #define S_GPIO16_OUT_VAL 3
13547 #define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
13548 #define F_GPIO16_OUT_VAL V_GPIO16_OUT_VAL(1U)
13550 #define S_GPIO17_OUT_VAL 2
13551 #define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
13552 #define F_GPIO17_OUT_VAL V_GPIO17_OUT_VAL(1U)
13554 #define S_GPIO18_OUT_VAL 1
13555 #define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
13556 #define F_GPIO18_OUT_VAL V_GPIO18_OUT_VAL(1U)
13558 #define S_GPIO19_OUT_VAL 0
13559 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
13560 #define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U)
13562 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
13564 #define S_FAST_UPDATE 8
13565 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
13566 #define F_FAST_UPDATE V_FAST_UPDATE(1U)
13568 #define S_FORCE_REG_IN_VALUE 2
13569 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
13570 #define F_FORCE_REG_IN_VALUE V_FORCE_REG_IN_VALUE(1U)
13572 #define S_HALT_UPDATE 1
13573 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
13574 #define F_HALT_UPDATE V_HALT_UPDATE(1U)
13576 #define A_DBG_GPIO_IN_NEW 0x6104
13578 #define S_GPIO16_CHG_DET 7
13579 #define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
13580 #define F_GPIO16_CHG_DET V_GPIO16_CHG_DET(1U)
13582 #define S_GPIO17_CHG_DET 6
13583 #define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
13584 #define F_GPIO17_CHG_DET V_GPIO17_CHG_DET(1U)
13586 #define S_GPIO18_CHG_DET 5
13587 #define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
13588 #define F_GPIO18_CHG_DET V_GPIO18_CHG_DET(1U)
13590 #define S_GPIO19_CHG_DET 4
13591 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
13592 #define F_GPIO19_CHG_DET V_GPIO19_CHG_DET(1U)
13594 #define S_GPIO19_IN 3
13595 #define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
13596 #define F_GPIO19_IN V_GPIO19_IN(1U)
13598 #define S_GPIO18_IN 2
13599 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
13600 #define F_GPIO18_IN V_GPIO18_IN(1U)
13602 #define S_GPIO17_IN 1
13603 #define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
13604 #define F_GPIO17_IN V_GPIO17_IN(1U)
13606 #define S_GPIO16_IN 0
13607 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
13608 #define F_GPIO16_IN V_GPIO16_IN(1U)
13610 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
13612 #define S_LAST_MEASUREMENT_SELECT 8
13613 #define M_LAST_MEASUREMENT_SELECT 0x3U
13614 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
13615 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
13617 #define S_LAST_MEASUREMENT_RESULT_BANK_B 4
13618 #define M_LAST_MEASUREMENT_RESULT_BANK_B 0xfU
13619 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
13620 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
13622 #define S_LAST_MEASUREMENT_RESULT_BANK_A 0
13623 #define M_LAST_MEASUREMENT_RESULT_BANK_A 0xfU
13624 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
13625 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
13627 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
13629 #define S_T5_STATIC_KX_PLL_BYPASS 30
13630 #define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
13631 #define F_T5_STATIC_KX_PLL_BYPASS V_T5_STATIC_KX_PLL_BYPASS(1U)
13633 #define S_T5_STATIC_KX_PLL_VBOOSTDIV 27
13634 #define M_T5_STATIC_KX_PLL_VBOOSTDIV 0x7U
13635 #define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
13636 #define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
13638 #define S_T5_STATIC_KX_PLL_CPISEL 24
13639 #define M_T5_STATIC_KX_PLL_CPISEL 0x7U
13640 #define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
13641 #define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
13643 #define S_T5_STATIC_KX_PLL_CCALMETHOD 23
13644 #define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
13645 #define F_T5_STATIC_KX_PLL_CCALMETHOD V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
13647 #define S_T5_STATIC_KX_PLL_CCALLOAD 22
13648 #define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
13649 #define F_T5_STATIC_KX_PLL_CCALLOAD V_T5_STATIC_KX_PLL_CCALLOAD(1U)
13651 #define S_T5_STATIC_KX_PLL_CCALFMIN 21
13652 #define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
13653 #define F_T5_STATIC_KX_PLL_CCALFMIN V_T5_STATIC_KX_PLL_CCALFMIN(1U)
13655 #define S_T5_STATIC_KX_PLL_CCALFMAX 20
13656 #define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
13657 #define F_T5_STATIC_KX_PLL_CCALFMAX V_T5_STATIC_KX_PLL_CCALFMAX(1U)
13659 #define S_T5_STATIC_KX_PLL_CCALCVHOLD 19
13660 #define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
13661 #define F_T5_STATIC_KX_PLL_CCALCVHOLD V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
13663 #define S_T5_STATIC_KX_PLL_CCALBANDSEL 15
13664 #define M_T5_STATIC_KX_PLL_CCALBANDSEL 0xfU
13665 #define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
13666 #define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
13668 #define S_T5_STATIC_KX_PLL_BGOFFSET 11
13669 #define M_T5_STATIC_KX_PLL_BGOFFSET 0xfU
13670 #define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
13671 #define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
13673 #define S_T5_STATIC_KX_PLL_P 8
13674 #define M_T5_STATIC_KX_PLL_P 0x7U
13675 #define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
13676 #define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
13678 #define S_T5_STATIC_KX_PLL_N2 4
13679 #define M_T5_STATIC_KX_PLL_N2 0xfU
13680 #define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
13681 #define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
13683 #define S_T5_STATIC_KX_PLL_N1 0
13684 #define M_T5_STATIC_KX_PLL_N1 0xfU
13685 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
13686 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
13688 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
13690 #define S_T6_STATIC_KX_PLL_BYPASS 30
13691 #define V_T6_STATIC_KX_PLL_BYPASS(x) ((x) << S_T6_STATIC_KX_PLL_BYPASS)
13692 #define F_T6_STATIC_KX_PLL_BYPASS V_T6_STATIC_KX_PLL_BYPASS(1U)
13694 #define S_STATIC_KX_PLL_VBOOSTDIV 27
13695 #define M_STATIC_KX_PLL_VBOOSTDIV 0x7U
13696 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
13697 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
13699 #define S_STATIC_KX_PLL_CPISEL 24
13700 #define M_STATIC_KX_PLL_CPISEL 0x7U
13701 #define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL)
13702 #define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL)
13704 #define S_STATIC_KX_PLL_CCALMETHOD 23
13705 #define V_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_STATIC_KX_PLL_CCALMETHOD)
13706 #define F_STATIC_KX_PLL_CCALMETHOD V_STATIC_KX_PLL_CCALMETHOD(1U)
13708 #define S_STATIC_KX_PLL_CCALLOAD 22
13709 #define V_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_STATIC_KX_PLL_CCALLOAD)
13710 #define F_STATIC_KX_PLL_CCALLOAD V_STATIC_KX_PLL_CCALLOAD(1U)
13712 #define S_STATIC_KX_PLL_CCALFMIN 21
13713 #define V_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_STATIC_KX_PLL_CCALFMIN)
13714 #define F_STATIC_KX_PLL_CCALFMIN V_STATIC_KX_PLL_CCALFMIN(1U)
13716 #define S_STATIC_KX_PLL_CCALFMAX 20
13717 #define V_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_STATIC_KX_PLL_CCALFMAX)
13718 #define F_STATIC_KX_PLL_CCALFMAX V_STATIC_KX_PLL_CCALFMAX(1U)
13720 #define S_STATIC_KX_PLL_CCALCVHOLD 19
13721 #define V_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KX_PLL_CCALCVHOLD)
13722 #define F_STATIC_KX_PLL_CCALCVHOLD V_STATIC_KX_PLL_CCALCVHOLD(1U)
13724 #define S_STATIC_KX_PLL_CCALBANDSEL 15
13725 #define M_STATIC_KX_PLL_CCALBANDSEL 0xfU
13726 #define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL)
13727 #define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL)
13729 #define S_STATIC_KX_PLL_BGOFFSET 11
13730 #define M_STATIC_KX_PLL_BGOFFSET 0xfU
13731 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
13732 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
13734 #define S_T6_STATIC_KX_PLL_P 8
13735 #define M_T6_STATIC_KX_PLL_P 0x7U
13736 #define V_T6_STATIC_KX_PLL_P(x) ((x) << S_T6_STATIC_KX_PLL_P)
13737 #define G_T6_STATIC_KX_PLL_P(x) (((x) >> S_T6_STATIC_KX_PLL_P) & M_T6_STATIC_KX_PLL_P)
13739 #define S_T6_STATIC_KX_PLL_N2 4
13740 #define M_T6_STATIC_KX_PLL_N2 0xfU
13741 #define V_T6_STATIC_KX_PLL_N2(x) ((x) << S_T6_STATIC_KX_PLL_N2)
13742 #define G_T6_STATIC_KX_PLL_N2(x) (((x) >> S_T6_STATIC_KX_PLL_N2) & M_T6_STATIC_KX_PLL_N2)
13744 #define S_T6_STATIC_KX_PLL_N1 0
13745 #define M_T6_STATIC_KX_PLL_N1 0xfU
13746 #define V_T6_STATIC_KX_PLL_N1(x) ((x) << S_T6_STATIC_KX_PLL_N1)
13747 #define G_T6_STATIC_KX_PLL_N1(x) (((x) >> S_T6_STATIC_KX_PLL_N1) & M_T6_STATIC_KX_PLL_N1)
13749 #define A_DBG_PVT_REG_DRVN 0x610c
13751 #define S_PVT_REG_DRVN_EN 8
13752 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
13753 #define F_PVT_REG_DRVN_EN V_PVT_REG_DRVN_EN(1U)
13755 #define S_PVT_REG_DRVN_B 4
13756 #define M_PVT_REG_DRVN_B 0xfU
13757 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
13758 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
13760 #define S_PVT_REG_DRVN_A 0
13761 #define M_PVT_REG_DRVN_A 0xfU
13762 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
13763 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
13765 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
13767 #define S_T5_STATIC_KX_PLL_M 11
13768 #define M_T5_STATIC_KX_PLL_M 0x1ffU
13769 #define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
13770 #define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
13772 #define S_T5_STATIC_KX_PLL_ANALOGTUNE 0
13773 #define M_T5_STATIC_KX_PLL_ANALOGTUNE 0x7ffU
13774 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
13775 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
13777 #define A_DBG_STATIC_KX_PLL_CONF2 0x610c
13779 #define S_T6_STATIC_KX_PLL_M 11
13780 #define M_T6_STATIC_KX_PLL_M 0x1ffU
13781 #define V_T6_STATIC_KX_PLL_M(x) ((x) << S_T6_STATIC_KX_PLL_M)
13782 #define G_T6_STATIC_KX_PLL_M(x) (((x) >> S_T6_STATIC_KX_PLL_M) & M_T6_STATIC_KX_PLL_M)
13784 #define S_STATIC_KX_PLL_ANALOGTUNE 0
13785 #define M_STATIC_KX_PLL_ANALOGTUNE 0x7ffU
13786 #define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE)
13787 #define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE)
13789 #define A_DBG_PVT_REG_DRVP 0x6110
13791 #define S_PVT_REG_DRVP_EN 8
13792 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
13793 #define F_PVT_REG_DRVP_EN V_PVT_REG_DRVP_EN(1U)
13795 #define S_PVT_REG_DRVP_B 4
13796 #define M_PVT_REG_DRVP_B 0xfU
13797 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
13798 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
13800 #define S_PVT_REG_DRVP_A 0
13801 #define M_PVT_REG_DRVP_A 0xfU
13802 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
13803 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
13805 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
13807 #define S_STATIC_C_DFS_RANGEA 8
13808 #define M_STATIC_C_DFS_RANGEA 0x1fU
13809 #define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
13810 #define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
13812 #define S_STATIC_C_DFS_RANGEB 3
13813 #define M_STATIC_C_DFS_RANGEB 0x1fU
13814 #define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
13815 #define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
13817 #define S_STATIC_C_DFS_FFTUNE4 2
13818 #define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
13819 #define F_STATIC_C_DFS_FFTUNE4 V_STATIC_C_DFS_FFTUNE4(1U)
13821 #define S_STATIC_C_DFS_FFTUNE5 1
13822 #define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
13823 #define F_STATIC_C_DFS_FFTUNE5 V_STATIC_C_DFS_FFTUNE5(1U)
13825 #define S_STATIC_C_DFS_ENABLE 0
13826 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
13827 #define F_STATIC_C_DFS_ENABLE V_STATIC_C_DFS_ENABLE(1U)
13829 #define A_DBG_STATIC_C_DFS_CONF 0x6110
13830 #define A_DBG_PVT_REG_TERMN 0x6114
13832 #define S_PVT_REG_TERMN_EN 8
13833 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
13834 #define F_PVT_REG_TERMN_EN V_PVT_REG_TERMN_EN(1U)
13836 #define S_PVT_REG_TERMN_B 4
13837 #define M_PVT_REG_TERMN_B 0xfU
13838 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
13839 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
13841 #define S_PVT_REG_TERMN_A 0
13842 #define M_PVT_REG_TERMN_A 0xfU
13843 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
13844 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
13846 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
13848 #define S_STATIC_U_DFS_RANGEA 8
13849 #define M_STATIC_U_DFS_RANGEA 0x1fU
13850 #define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
13851 #define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
13853 #define S_STATIC_U_DFS_RANGEB 3
13854 #define M_STATIC_U_DFS_RANGEB 0x1fU
13855 #define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
13856 #define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
13858 #define S_STATIC_U_DFS_FFTUNE4 2
13859 #define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
13860 #define F_STATIC_U_DFS_FFTUNE4 V_STATIC_U_DFS_FFTUNE4(1U)
13862 #define S_STATIC_U_DFS_FFTUNE5 1
13863 #define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
13864 #define F_STATIC_U_DFS_FFTUNE5 V_STATIC_U_DFS_FFTUNE5(1U)
13866 #define S_STATIC_U_DFS_ENABLE 0
13867 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
13868 #define F_STATIC_U_DFS_ENABLE V_STATIC_U_DFS_ENABLE(1U)
13870 #define A_DBG_STATIC_U_DFS_CONF 0x6114
13871 #define A_DBG_PVT_REG_TERMP 0x6118
13873 #define S_PVT_REG_TERMP_EN 8
13874 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
13875 #define F_PVT_REG_TERMP_EN V_PVT_REG_TERMP_EN(1U)
13877 #define S_PVT_REG_TERMP_B 4
13878 #define M_PVT_REG_TERMP_B 0xfU
13879 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
13880 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
13882 #define S_PVT_REG_TERMP_A 0
13883 #define M_PVT_REG_TERMP_A 0xfU
13884 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
13885 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
13887 #define A_DBG_GPIO_PE_EN 0x6118
13889 #define S_GPIO19_PE_EN 19
13890 #define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
13891 #define F_GPIO19_PE_EN V_GPIO19_PE_EN(1U)
13893 #define S_GPIO18_PE_EN 18
13894 #define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
13895 #define F_GPIO18_PE_EN V_GPIO18_PE_EN(1U)
13897 #define S_GPIO17_PE_EN 17
13898 #define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
13899 #define F_GPIO17_PE_EN V_GPIO17_PE_EN(1U)
13901 #define S_GPIO16_PE_EN 16
13902 #define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
13903 #define F_GPIO16_PE_EN V_GPIO16_PE_EN(1U)
13905 #define S_GPIO15_PE_EN 15
13906 #define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
13907 #define F_GPIO15_PE_EN V_GPIO15_PE_EN(1U)
13909 #define S_GPIO14_PE_EN 14
13910 #define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
13911 #define F_GPIO14_PE_EN V_GPIO14_PE_EN(1U)
13913 #define S_GPIO13_PE_EN 13
13914 #define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
13915 #define F_GPIO13_PE_EN V_GPIO13_PE_EN(1U)
13917 #define S_GPIO12_PE_EN 12
13918 #define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
13919 #define F_GPIO12_PE_EN V_GPIO12_PE_EN(1U)
13921 #define S_GPIO11_PE_EN 11
13922 #define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
13923 #define F_GPIO11_PE_EN V_GPIO11_PE_EN(1U)
13925 #define S_GPIO10_PE_EN 10
13926 #define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
13927 #define F_GPIO10_PE_EN V_GPIO10_PE_EN(1U)
13929 #define S_GPIO9_PE_EN 9
13930 #define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
13931 #define F_GPIO9_PE_EN V_GPIO9_PE_EN(1U)
13933 #define S_GPIO8_PE_EN 8
13934 #define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
13935 #define F_GPIO8_PE_EN V_GPIO8_PE_EN(1U)
13937 #define S_GPIO7_PE_EN 7
13938 #define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
13939 #define F_GPIO7_PE_EN V_GPIO7_PE_EN(1U)
13941 #define S_GPIO6_PE_EN 6
13942 #define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
13943 #define F_GPIO6_PE_EN V_GPIO6_PE_EN(1U)
13945 #define S_GPIO5_PE_EN 5
13946 #define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
13947 #define F_GPIO5_PE_EN V_GPIO5_PE_EN(1U)
13949 #define S_GPIO4_PE_EN 4
13950 #define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
13951 #define F_GPIO4_PE_EN V_GPIO4_PE_EN(1U)
13953 #define S_GPIO3_PE_EN 3
13954 #define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
13955 #define F_GPIO3_PE_EN V_GPIO3_PE_EN(1U)
13957 #define S_GPIO2_PE_EN 2
13958 #define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
13959 #define F_GPIO2_PE_EN V_GPIO2_PE_EN(1U)
13961 #define S_GPIO1_PE_EN 1
13962 #define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
13963 #define F_GPIO1_PE_EN V_GPIO1_PE_EN(1U)
13965 #define S_GPIO0_PE_EN 0
13966 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
13967 #define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U)
13969 #define A_DBG_PVT_REG_THRESHOLD 0x611c
13971 #define S_PVT_CALIBRATION_DONE 8
13972 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
13973 #define F_PVT_CALIBRATION_DONE V_PVT_CALIBRATION_DONE(1U)
13975 #define S_THRESHOLD_TERMP_MAX_SYNC 7
13976 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
13977 #define F_THRESHOLD_TERMP_MAX_SYNC V_THRESHOLD_TERMP_MAX_SYNC(1U)
13979 #define S_THRESHOLD_TERMP_MIN_SYNC 6
13980 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
13981 #define F_THRESHOLD_TERMP_MIN_SYNC V_THRESHOLD_TERMP_MIN_SYNC(1U)
13983 #define S_THRESHOLD_TERMN_MAX_SYNC 5
13984 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
13985 #define F_THRESHOLD_TERMN_MAX_SYNC V_THRESHOLD_TERMN_MAX_SYNC(1U)
13987 #define S_THRESHOLD_TERMN_MIN_SYNC 4
13988 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
13989 #define F_THRESHOLD_TERMN_MIN_SYNC V_THRESHOLD_TERMN_MIN_SYNC(1U)
13991 #define S_THRESHOLD_DRVP_MAX_SYNC 3
13992 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
13993 #define F_THRESHOLD_DRVP_MAX_SYNC V_THRESHOLD_DRVP_MAX_SYNC(1U)
13995 #define S_THRESHOLD_DRVP_MIN_SYNC 2
13996 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
13997 #define F_THRESHOLD_DRVP_MIN_SYNC V_THRESHOLD_DRVP_MIN_SYNC(1U)
13999 #define S_THRESHOLD_DRVN_MAX_SYNC 1
14000 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
14001 #define F_THRESHOLD_DRVN_MAX_SYNC V_THRESHOLD_DRVN_MAX_SYNC(1U)
14003 #define S_THRESHOLD_DRVN_MIN_SYNC 0
14004 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
14005 #define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U)
14007 #define A_DBG_GPIO_PS_EN 0x611c
14009 #define S_GPIO19_PS_EN 19
14010 #define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
14011 #define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U)
14013 #define S_GPIO18_PS_EN 18
14014 #define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
14015 #define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U)
14017 #define S_GPIO17_PS_EN 17
14018 #define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
14019 #define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U)
14021 #define S_GPIO16_PS_EN 16
14022 #define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
14023 #define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U)
14025 #define S_GPIO15_PS_EN 15
14026 #define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
14027 #define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U)
14029 #define S_GPIO14_PS_EN 14
14030 #define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
14031 #define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U)
14033 #define S_GPIO13_PS_EN 13
14034 #define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
14035 #define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U)
14037 #define S_GPIO12_PS_EN 12
14038 #define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
14039 #define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U)
14041 #define S_GPIO11_PS_EN 11
14042 #define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
14043 #define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U)
14045 #define S_GPIO10_PS_EN 10
14046 #define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
14047 #define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U)
14049 #define S_GPIO9_PS_EN 9
14050 #define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
14051 #define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U)
14053 #define S_GPIO8_PS_EN 8
14054 #define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
14055 #define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U)
14057 #define S_GPIO7_PS_EN 7
14058 #define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
14059 #define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U)
14061 #define S_GPIO6_PS_EN 6
14062 #define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
14063 #define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U)
14065 #define S_GPIO5_PS_EN 5
14066 #define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
14067 #define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U)
14069 #define S_GPIO4_PS_EN 4
14070 #define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
14071 #define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U)
14073 #define S_GPIO3_PS_EN 3
14074 #define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
14075 #define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U)
14077 #define S_GPIO2_PS_EN 2
14078 #define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
14079 #define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U)
14081 #define S_GPIO1_PS_EN 1
14082 #define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
14083 #define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U)
14085 #define S_GPIO0_PS_EN 0
14086 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
14087 #define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U)
14089 #define A_DBG_PVT_REG_IN_TERMP 0x6120
14091 #define S_REG_IN_TERMP_B 4
14092 #define M_REG_IN_TERMP_B 0xfU
14093 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
14094 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
14096 #define S_REG_IN_TERMP_A 0
14097 #define M_REG_IN_TERMP_A 0xfU
14098 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
14099 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
14101 #define A_DBG_EFUSE_BYTE16_19 0x6120
14102 #define A_DBG_PVT_REG_IN_TERMN 0x6124
14104 #define S_REG_IN_TERMN_B 4
14105 #define M_REG_IN_TERMN_B 0xfU
14106 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
14107 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
14109 #define S_REG_IN_TERMN_A 0
14110 #define M_REG_IN_TERMN_A 0xfU
14111 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
14112 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
14114 #define A_DBG_EFUSE_BYTE20_23 0x6124
14115 #define A_DBG_PVT_REG_IN_DRVP 0x6128
14117 #define S_REG_IN_DRVP_B 4
14118 #define M_REG_IN_DRVP_B 0xfU
14119 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
14120 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
14122 #define S_REG_IN_DRVP_A 0
14123 #define M_REG_IN_DRVP_A 0xfU
14124 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
14125 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
14127 #define A_DBG_EFUSE_BYTE24_27 0x6128
14128 #define A_DBG_PVT_REG_IN_DRVN 0x612c
14130 #define S_REG_IN_DRVN_B 4
14131 #define M_REG_IN_DRVN_B 0xfU
14132 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
14133 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
14135 #define S_REG_IN_DRVN_A 0
14136 #define M_REG_IN_DRVN_A 0xfU
14137 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
14138 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
14140 #define A_DBG_EFUSE_BYTE28_31 0x612c
14141 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
14143 #define S_REG_OUT_TERMP_B 4
14144 #define M_REG_OUT_TERMP_B 0xfU
14145 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
14146 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
14148 #define S_REG_OUT_TERMP_A 0
14149 #define M_REG_OUT_TERMP_A 0xfU
14150 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
14151 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
14153 #define A_DBG_EFUSE_BYTE32_35 0x6130
14154 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
14156 #define S_REG_OUT_TERMN_B 4
14157 #define M_REG_OUT_TERMN_B 0xfU
14158 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
14159 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
14161 #define S_REG_OUT_TERMN_A 0
14162 #define M_REG_OUT_TERMN_A 0xfU
14163 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
14164 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
14166 #define A_DBG_EFUSE_BYTE36_39 0x6134
14167 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
14169 #define S_REG_OUT_DRVP_B 4
14170 #define M_REG_OUT_DRVP_B 0xfU
14171 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
14172 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
14174 #define S_REG_OUT_DRVP_A 0
14175 #define M_REG_OUT_DRVP_A 0xfU
14176 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
14177 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
14179 #define A_DBG_EFUSE_BYTE40_43 0x6138
14180 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
14182 #define S_REG_OUT_DRVN_B 4
14183 #define M_REG_OUT_DRVN_B 0xfU
14184 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
14185 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
14187 #define S_REG_OUT_DRVN_A 0
14188 #define M_REG_OUT_DRVN_A 0xfU
14189 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
14190 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
14192 #define A_DBG_EFUSE_BYTE44_47 0x613c
14193 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
14195 #define S_TERMP_B_HISTORY 4
14196 #define M_TERMP_B_HISTORY 0xfU
14197 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
14198 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
14200 #define S_TERMP_A_HISTORY 0
14201 #define M_TERMP_A_HISTORY 0xfU
14202 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
14203 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
14205 #define A_DBG_EFUSE_BYTE48_51 0x6140
14206 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
14208 #define S_TERMN_B_HISTORY 4
14209 #define M_TERMN_B_HISTORY 0xfU
14210 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
14211 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
14213 #define S_TERMN_A_HISTORY 0
14214 #define M_TERMN_A_HISTORY 0xfU
14215 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
14216 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
14218 #define A_DBG_EFUSE_BYTE52_55 0x6144
14219 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
14221 #define S_DRVP_B_HISTORY 4
14222 #define M_DRVP_B_HISTORY 0xfU
14223 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
14224 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
14226 #define S_DRVP_A_HISTORY 0
14227 #define M_DRVP_A_HISTORY 0xfU
14228 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
14229 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
14231 #define A_DBG_EFUSE_BYTE56_59 0x6148
14232 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
14234 #define S_DRVN_B_HISTORY 4
14235 #define M_DRVN_B_HISTORY 0xfU
14236 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
14237 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
14239 #define S_DRVN_A_HISTORY 0
14240 #define M_DRVN_A_HISTORY 0xfU
14241 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
14242 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
14244 #define A_DBG_EFUSE_BYTE60_63 0x614c
14245 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
14247 #define S_SAMPLE_WAIT_CLKS 0
14248 #define M_SAMPLE_WAIT_CLKS 0x1fU
14249 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
14250 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
14252 #define A_DBG_STATIC_U_PLL_CONF6 0x6150
14254 #define S_STATIC_U_PLL_VREGTUNE 0
14255 #define M_STATIC_U_PLL_VREGTUNE 0x7ffffU
14256 #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
14257 #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
14259 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
14261 #define S_STATIC_C_PLL_VREGTUNE 0
14262 #define M_STATIC_C_PLL_VREGTUNE 0x7ffffU
14263 #define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE)
14264 #define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE)
14266 #define A_DBG_CUST_EFUSE_PROGRAM 0x6158
14268 #define S_EFUSE_PROG_PERIOD 16
14269 #define M_EFUSE_PROG_PERIOD 0xffffU
14270 #define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD)
14271 #define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD)
14273 #define S_EFUSE_OPER_TYP 14
14274 #define M_EFUSE_OPER_TYP 0x3U
14275 #define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP)
14276 #define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP)
14278 #define S_EFUSE_ADDR 8
14279 #define M_EFUSE_ADDR 0x3fU
14280 #define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR)
14281 #define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR)
14283 #define S_EFUSE_DIN 0
14284 #define M_EFUSE_DIN 0xffU
14285 #define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN)
14286 #define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN)
14288 #define A_DBG_CUST_EFUSE_OUT 0x615c
14290 #define S_EFUSE_OPER_DONE 8
14291 #define V_EFUSE_OPER_DONE(x) ((x) << S_EFUSE_OPER_DONE)
14292 #define F_EFUSE_OPER_DONE V_EFUSE_OPER_DONE(1U)
14294 #define S_EFUSE_DOUT 0
14295 #define M_EFUSE_DOUT 0xffU
14296 #define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT)
14297 #define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT)
14299 #define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
14300 #define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
14301 #define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
14302 #define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
14303 #define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
14304 #define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
14305 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
14306 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
14307 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
14308 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
14309 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
14310 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
14311 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
14312 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
14313 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
14314 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
14316 /* registers for module MC */
14317 #define MC_BASE_ADDR 0x6200
14319 #define A_MC_PCTL_SCFG 0x6200
14321 #define S_RKINF_EN 5
14322 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
14323 #define F_RKINF_EN V_RKINF_EN(1U)
14325 #define S_DUAL_PCTL_EN 4
14326 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
14327 #define F_DUAL_PCTL_EN V_DUAL_PCTL_EN(1U)
14329 #define S_SLAVE_MODE 3
14330 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
14331 #define F_SLAVE_MODE V_SLAVE_MODE(1U)
14333 #define S_LOOPBACK_EN 1
14334 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
14335 #define F_LOOPBACK_EN V_LOOPBACK_EN(1U)
14337 #define S_HW_LOW_POWER_EN 0
14338 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
14339 #define F_HW_LOW_POWER_EN V_HW_LOW_POWER_EN(1U)
14341 #define A_MC_PCTL_SCTL 0x6204
14343 #define S_STATE_CMD 0
14344 #define M_STATE_CMD 0x7U
14345 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
14346 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
14348 #define A_MC_PCTL_STAT 0x6208
14350 #define S_CTL_STAT 0
14351 #define M_CTL_STAT 0x7U
14352 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
14353 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
14355 #define A_MC_PCTL_MCMD 0x6240
14357 #define S_START_CMD 31
14358 #define V_START_CMD(x) ((x) << S_START_CMD)
14359 #define F_START_CMD V_START_CMD(1U)
14361 #define S_CMD_ADD_DEL 24
14362 #define M_CMD_ADD_DEL 0xfU
14363 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
14364 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
14366 #define S_RANK_SEL 20
14367 #define M_RANK_SEL 0xfU
14368 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
14369 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
14371 #define S_BANK_ADDR 17
14372 #define M_BANK_ADDR 0x7U
14373 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
14374 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
14376 #define S_CMD_ADDR 4
14377 #define M_CMD_ADDR 0x1fffU
14378 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
14379 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
14381 #define S_CMD_OPCODE 0
14382 #define M_CMD_OPCODE 0x7U
14383 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
14384 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
14386 #define A_MC_PCTL_POWCTL 0x6244
14388 #define S_POWER_UP_START 0
14389 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
14390 #define F_POWER_UP_START V_POWER_UP_START(1U)
14392 #define A_MC_PCTL_POWSTAT 0x6248
14394 #define S_PHY_CALIBDONE 1
14395 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
14396 #define F_PHY_CALIBDONE V_PHY_CALIBDONE(1U)
14398 #define S_POWER_UP_DONE 0
14399 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
14400 #define F_POWER_UP_DONE V_POWER_UP_DONE(1U)
14402 #define A_MC_PCTL_MCFG 0x6280
14404 #define S_TFAW_CFG 18
14405 #define M_TFAW_CFG 0x3U
14406 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
14407 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
14409 #define S_PD_EXIT_MODE 17
14410 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
14411 #define F_PD_EXIT_MODE V_PD_EXIT_MODE(1U)
14413 #define S_PD_TYPE 16
14414 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
14415 #define F_PD_TYPE V_PD_TYPE(1U)
14417 #define S_PD_IDLE 8
14418 #define M_PD_IDLE 0xffU
14419 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
14420 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
14422 #define S_PAGE_POLICY 6
14423 #define M_PAGE_POLICY 0x3U
14424 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
14425 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
14427 #define S_DDR3_EN 5
14428 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
14429 #define F_DDR3_EN V_DDR3_EN(1U)
14431 #define S_TWO_T_EN 3
14432 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
14433 #define F_TWO_T_EN V_TWO_T_EN(1U)
14435 #define S_BL8INT_EN 2
14436 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
14437 #define F_BL8INT_EN V_BL8INT_EN(1U)
14440 #define V_MEM_BL(x) ((x) << S_MEM_BL)
14441 #define F_MEM_BL V_MEM_BL(1U)
14443 #define A_MC_PCTL_PPCFG 0x6284
14445 #define S_RPMEM_DIS 1
14446 #define M_RPMEM_DIS 0xffU
14447 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
14448 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
14450 #define S_PPMEM_EN 0
14451 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
14452 #define F_PPMEM_EN V_PPMEM_EN(1U)
14454 #define A_MC_PCTL_MSTAT 0x6288
14456 #define S_POWER_DOWN 0
14457 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
14458 #define F_POWER_DOWN V_POWER_DOWN(1U)
14460 #define A_MC_PCTL_ODTCFG 0x628c
14462 #define S_RANK3_ODT_DEFAULT 28
14463 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
14464 #define F_RANK3_ODT_DEFAULT V_RANK3_ODT_DEFAULT(1U)
14466 #define S_RANK3_ODT_WRITE_SEL 27
14467 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
14468 #define F_RANK3_ODT_WRITE_SEL V_RANK3_ODT_WRITE_SEL(1U)
14470 #define S_RANK3_ODT_WRITE_NSE 26
14471 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
14472 #define F_RANK3_ODT_WRITE_NSE V_RANK3_ODT_WRITE_NSE(1U)
14474 #define S_RANK3_ODT_READ_SEL 25
14475 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
14476 #define F_RANK3_ODT_READ_SEL V_RANK3_ODT_READ_SEL(1U)
14478 #define S_RANK3_ODT_READ_NSEL 24
14479 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
14480 #define F_RANK3_ODT_READ_NSEL V_RANK3_ODT_READ_NSEL(1U)
14482 #define S_RANK2_ODT_DEFAULT 20
14483 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
14484 #define F_RANK2_ODT_DEFAULT V_RANK2_ODT_DEFAULT(1U)
14486 #define S_RANK2_ODT_WRITE_SEL 19
14487 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
14488 #define F_RANK2_ODT_WRITE_SEL V_RANK2_ODT_WRITE_SEL(1U)
14490 #define S_RANK2_ODT_WRITE_NSEL 18
14491 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
14492 #define F_RANK2_ODT_WRITE_NSEL V_RANK2_ODT_WRITE_NSEL(1U)
14494 #define S_RANK2_ODT_READ_SEL 17
14495 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
14496 #define F_RANK2_ODT_READ_SEL V_RANK2_ODT_READ_SEL(1U)
14498 #define S_RANK2_ODT_READ_NSEL 16
14499 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
14500 #define F_RANK2_ODT_READ_NSEL V_RANK2_ODT_READ_NSEL(1U)
14502 #define S_RANK1_ODT_DEFAULT 12
14503 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
14504 #define F_RANK1_ODT_DEFAULT V_RANK1_ODT_DEFAULT(1U)
14506 #define S_RANK1_ODT_WRITE_SEL 11
14507 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
14508 #define F_RANK1_ODT_WRITE_SEL V_RANK1_ODT_WRITE_SEL(1U)
14510 #define S_RANK1_ODT_WRITE_NSEL 10
14511 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
14512 #define F_RANK1_ODT_WRITE_NSEL V_RANK1_ODT_WRITE_NSEL(1U)
14514 #define S_RANK1_ODT_READ_SEL 9
14515 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
14516 #define F_RANK1_ODT_READ_SEL V_RANK1_ODT_READ_SEL(1U)
14518 #define S_RANK1_ODT_READ_NSEL 8
14519 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
14520 #define F_RANK1_ODT_READ_NSEL V_RANK1_ODT_READ_NSEL(1U)
14522 #define S_RANK0_ODT_DEFAULT 4
14523 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
14524 #define F_RANK0_ODT_DEFAULT V_RANK0_ODT_DEFAULT(1U)
14526 #define S_RANK0_ODT_WRITE_SEL 3
14527 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
14528 #define F_RANK0_ODT_WRITE_SEL V_RANK0_ODT_WRITE_SEL(1U)
14530 #define S_RANK0_ODT_WRITE_NSEL 2
14531 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
14532 #define F_RANK0_ODT_WRITE_NSEL V_RANK0_ODT_WRITE_NSEL(1U)
14534 #define S_RANK0_ODT_READ_SEL 1
14535 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
14536 #define F_RANK0_ODT_READ_SEL V_RANK0_ODT_READ_SEL(1U)
14538 #define S_RANK0_ODT_READ_NSEL 0
14539 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
14540 #define F_RANK0_ODT_READ_NSEL V_RANK0_ODT_READ_NSEL(1U)
14542 #define A_MC_PCTL_DQSECFG 0x6290
14544 #define S_DV_ALAT 20
14545 #define M_DV_ALAT 0xfU
14546 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
14547 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
14549 #define S_DV_ALEN 16
14550 #define M_DV_ALEN 0x3U
14551 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
14552 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
14554 #define S_DSE_ALAT 12
14555 #define M_DSE_ALAT 0xfU
14556 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
14557 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
14559 #define S_DSE_ALEN 8
14560 #define M_DSE_ALEN 0x3U
14561 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
14562 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
14564 #define S_QSE_ALAT 4
14565 #define M_QSE_ALAT 0xfU
14566 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
14567 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
14569 #define S_QSE_ALEN 0
14570 #define M_QSE_ALEN 0x3U
14571 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
14572 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
14574 #define A_MC_PCTL_DTUPDES 0x6294
14576 #define S_DTU_RD_MISSING 13
14577 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
14578 #define F_DTU_RD_MISSING V_DTU_RD_MISSING(1U)
14580 #define S_DTU_EAFFL 9
14581 #define M_DTU_EAFFL 0xfU
14582 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
14583 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
14585 #define S_DTU_RANDOM_ERROR 8
14586 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
14587 #define F_DTU_RANDOM_ERROR V_DTU_RANDOM_ERROR(1U)
14589 #define S_DTU_ERROR_B7 7
14590 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
14591 #define F_DTU_ERROR_B7 V_DTU_ERROR_B7(1U)
14593 #define S_DTU_ERR_B6 6
14594 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
14595 #define F_DTU_ERR_B6 V_DTU_ERR_B6(1U)
14597 #define S_DTU_ERR_B5 5
14598 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
14599 #define F_DTU_ERR_B5 V_DTU_ERR_B5(1U)
14601 #define S_DTU_ERR_B4 4
14602 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
14603 #define F_DTU_ERR_B4 V_DTU_ERR_B4(1U)
14605 #define S_DTU_ERR_B3 3
14606 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
14607 #define F_DTU_ERR_B3 V_DTU_ERR_B3(1U)
14609 #define S_DTU_ERR_B2 2
14610 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
14611 #define F_DTU_ERR_B2 V_DTU_ERR_B2(1U)
14613 #define S_DTU_ERR_B1 1
14614 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
14615 #define F_DTU_ERR_B1 V_DTU_ERR_B1(1U)
14617 #define S_DTU_ERR_B0 0
14618 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
14619 #define F_DTU_ERR_B0 V_DTU_ERR_B0(1U)
14621 #define A_MC_PCTL_DTUNA 0x6298
14622 #define A_MC_PCTL_DTUNE 0x629c
14623 #define A_MC_PCTL_DTUPRDO 0x62a0
14625 #define S_DTU_ALLBITS_1 16
14626 #define M_DTU_ALLBITS_1 0xffffU
14627 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
14628 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
14630 #define S_DTU_ALLBITS_0 0
14631 #define M_DTU_ALLBITS_0 0xffffU
14632 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
14633 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
14635 #define A_MC_PCTL_DTUPRD1 0x62a4
14637 #define S_DTU_ALLBITS_3 16
14638 #define M_DTU_ALLBITS_3 0xffffU
14639 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
14640 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
14642 #define S_DTU_ALLBITS_2 0
14643 #define M_DTU_ALLBITS_2 0xffffU
14644 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
14645 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
14647 #define A_MC_PCTL_DTUPRD2 0x62a8
14649 #define S_DTU_ALLBITS_5 16
14650 #define M_DTU_ALLBITS_5 0xffffU
14651 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
14652 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
14654 #define S_DTU_ALLBITS_4 0
14655 #define M_DTU_ALLBITS_4 0xffffU
14656 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
14657 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
14659 #define A_MC_PCTL_DTUPRD3 0x62ac
14661 #define S_DTU_ALLBITS_7 16
14662 #define M_DTU_ALLBITS_7 0xffffU
14663 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
14664 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
14666 #define S_DTU_ALLBITS_6 0
14667 #define M_DTU_ALLBITS_6 0xffffU
14668 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
14669 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
14671 #define A_MC_PCTL_DTUAWDT 0x62b0
14673 #define S_NUMBER_RANKS 9
14674 #define M_NUMBER_RANKS 0x3U
14675 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
14676 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
14678 #define S_ROW_ADDR_WIDTH 6
14679 #define M_ROW_ADDR_WIDTH 0x3U
14680 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
14681 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
14683 #define S_BANK_ADDR_WIDTH 3
14684 #define M_BANK_ADDR_WIDTH 0x3U
14685 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
14686 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
14688 #define S_COLUMN_ADDR_WIDTH 0
14689 #define M_COLUMN_ADDR_WIDTH 0x3U
14690 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
14691 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
14693 #define A_MC_PCTL_TOGCNT1U 0x62c0
14695 #define S_TOGGLE_COUNTER_1U 0
14696 #define M_TOGGLE_COUNTER_1U 0x3ffU
14697 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
14698 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
14700 #define A_MC_PCTL_TINIT 0x62c4
14703 #define M_T_INIT 0x1ffU
14704 #define V_T_INIT(x) ((x) << S_T_INIT)
14705 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
14707 #define A_MC_PCTL_TRSTH 0x62c8
14710 #define M_T_RSTH 0x3ffU
14711 #define V_T_RSTH(x) ((x) << S_T_RSTH)
14712 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
14714 #define A_MC_PCTL_TOGCNT100N 0x62cc
14716 #define S_TOGGLE_COUNTER_100N 0
14717 #define M_TOGGLE_COUNTER_100N 0x7fU
14718 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
14719 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
14721 #define A_MC_PCTL_TREFI 0x62d0
14724 #define M_T_REFI 0xffU
14725 #define V_T_REFI(x) ((x) << S_T_REFI)
14726 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
14728 #define A_MC_PCTL_TMRD 0x62d4
14731 #define M_T_MRD 0x7U
14732 #define V_T_MRD(x) ((x) << S_T_MRD)
14733 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
14735 #define A_MC_PCTL_TRFC 0x62d8
14738 #define M_T_RFC 0xffU
14739 #define V_T_RFC(x) ((x) << S_T_RFC)
14740 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
14742 #define A_MC_PCTL_TRP 0x62dc
14745 #define M_T_RP 0xfU
14746 #define V_T_RP(x) ((x) << S_T_RP)
14747 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
14749 #define A_MC_PCTL_TRTW 0x62e0
14752 #define M_T_RTW 0x7U
14753 #define V_T_RTW(x) ((x) << S_T_RTW)
14754 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
14756 #define A_MC_PCTL_TAL 0x62e4
14759 #define M_T_AL 0xfU
14760 #define V_T_AL(x) ((x) << S_T_AL)
14761 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
14763 #define A_MC_PCTL_TCL 0x62e8
14766 #define M_T_CL 0xfU
14767 #define V_T_CL(x) ((x) << S_T_CL)
14768 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
14770 #define A_MC_PCTL_TCWL 0x62ec
14773 #define M_T_CWL 0xfU
14774 #define V_T_CWL(x) ((x) << S_T_CWL)
14775 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
14777 #define A_MC_PCTL_TRAS 0x62f0
14780 #define M_T_RAS 0x3fU
14781 #define V_T_RAS(x) ((x) << S_T_RAS)
14782 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
14784 #define A_MC_PCTL_TRC 0x62f4
14787 #define M_T_RC 0x3fU
14788 #define V_T_RC(x) ((x) << S_T_RC)
14789 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
14791 #define A_MC_PCTL_TRCD 0x62f8
14794 #define M_T_RCD 0xfU
14795 #define V_T_RCD(x) ((x) << S_T_RCD)
14796 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
14798 #define A_MC_PCTL_TRRD 0x62fc
14801 #define M_T_RRD 0xfU
14802 #define V_T_RRD(x) ((x) << S_T_RRD)
14803 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
14805 #define A_MC_PCTL_TRTP 0x6300
14808 #define M_T_RTP 0x7U
14809 #define V_T_RTP(x) ((x) << S_T_RTP)
14810 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
14812 #define A_MC_PCTL_TWR 0x6304
14815 #define M_T_WR 0x7U
14816 #define V_T_WR(x) ((x) << S_T_WR)
14817 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
14819 #define A_MC_PCTL_TWTR 0x6308
14822 #define M_T_WTR 0x7U
14823 #define V_T_WTR(x) ((x) << S_T_WTR)
14824 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
14826 #define A_MC_PCTL_TEXSR 0x630c
14829 #define M_T_EXSR 0x3ffU
14830 #define V_T_EXSR(x) ((x) << S_T_EXSR)
14831 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
14833 #define A_MC_PCTL_TXP 0x6310
14836 #define M_T_XP 0x7U
14837 #define V_T_XP(x) ((x) << S_T_XP)
14838 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
14840 #define A_MC_PCTL_TXPDLL 0x6314
14842 #define S_T_XPDLL 0
14843 #define M_T_XPDLL 0x3fU
14844 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
14845 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
14847 #define A_MC_PCTL_TZQCS 0x6318
14850 #define M_T_ZQCS 0x7fU
14851 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
14852 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
14854 #define A_MC_PCTL_TZQCSI 0x631c
14856 #define S_T_ZQCSI 0
14857 #define M_T_ZQCSI 0xfffU
14858 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
14859 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
14861 #define A_MC_PCTL_TDQS 0x6320
14864 #define M_T_DQS 0x7U
14865 #define V_T_DQS(x) ((x) << S_T_DQS)
14866 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
14868 #define A_MC_PCTL_TCKSRE 0x6324
14870 #define S_T_CKSRE 0
14871 #define M_T_CKSRE 0xfU
14872 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
14873 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
14875 #define A_MC_PCTL_TCKSRX 0x6328
14877 #define S_T_CKSRX 0
14878 #define M_T_CKSRX 0xfU
14879 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
14880 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
14882 #define A_MC_PCTL_TCKE 0x632c
14885 #define M_T_CKE 0x7U
14886 #define V_T_CKE(x) ((x) << S_T_CKE)
14887 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
14889 #define A_MC_PCTL_TMOD 0x6330
14892 #define M_T_MOD 0xfU
14893 #define V_T_MOD(x) ((x) << S_T_MOD)
14894 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
14896 #define A_MC_PCTL_TRSTL 0x6334
14898 #define S_RSTHOLD 0
14899 #define M_RSTHOLD 0x7fU
14900 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
14901 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
14903 #define A_MC_PCTL_TZQCL 0x6338
14906 #define M_T_ZQCL 0x3ffU
14907 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
14908 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
14910 #define A_MC_PCTL_DWLCFG0 0x6370
14912 #define S_T_ADWL_VEC 0
14913 #define M_T_ADWL_VEC 0x1ffU
14914 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
14915 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
14917 #define A_MC_PCTL_DWLCFG1 0x6374
14918 #define A_MC_PCTL_DWLCFG2 0x6378
14919 #define A_MC_PCTL_DWLCFG3 0x637c
14920 #define A_MC_PCTL_ECCCFG 0x6380
14922 #define S_INLINE_SYN_EN 4
14923 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
14924 #define F_INLINE_SYN_EN V_INLINE_SYN_EN(1U)
14927 #define V_ECC_EN(x) ((x) << S_ECC_EN)
14928 #define F_ECC_EN V_ECC_EN(1U)
14930 #define S_ECC_INTR_EN 2
14931 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
14932 #define F_ECC_INTR_EN V_ECC_INTR_EN(1U)
14934 #define A_MC_PCTL_ECCTST 0x6384
14936 #define S_ECC_TEST_MASK 0
14937 #define M_ECC_TEST_MASK 0xffU
14938 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
14939 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
14941 #define A_MC_PCTL_ECCCLR 0x6388
14943 #define S_CLR_ECC_LOG 1
14944 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
14945 #define F_CLR_ECC_LOG V_CLR_ECC_LOG(1U)
14947 #define S_CLR_ECC_INTR 0
14948 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
14949 #define F_CLR_ECC_INTR V_CLR_ECC_INTR(1U)
14951 #define A_MC_PCTL_ECCLOG 0x638c
14952 #define A_MC_PCTL_DTUWACTL 0x6400
14954 #define S_DTU_WR_RANK 30
14955 #define M_DTU_WR_RANK 0x3U
14956 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
14957 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
14959 #define S_DTU_WR_ROW 13
14960 #define M_DTU_WR_ROW 0x1ffffU
14961 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
14962 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
14964 #define S_DTU_WR_BANK 10
14965 #define M_DTU_WR_BANK 0x7U
14966 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
14967 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
14969 #define S_DTU_WR_COL 0
14970 #define M_DTU_WR_COL 0x3ffU
14971 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
14972 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
14974 #define A_MC_PCTL_DTURACTL 0x6404
14976 #define S_DTU_RD_RANK 30
14977 #define M_DTU_RD_RANK 0x3U
14978 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
14979 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
14981 #define S_DTU_RD_ROW 13
14982 #define M_DTU_RD_ROW 0x1ffffU
14983 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
14984 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
14986 #define S_DTU_RD_BANK 10
14987 #define M_DTU_RD_BANK 0x7U
14988 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
14989 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
14991 #define S_DTU_RD_COL 0
14992 #define M_DTU_RD_COL 0x3ffU
14993 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
14994 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
14996 #define A_MC_PCTL_DTUCFG 0x6408
14998 #define S_DTU_ROW_INCREMENTS 16
14999 #define M_DTU_ROW_INCREMENTS 0x7fU
15000 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
15001 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
15003 #define S_DTU_WR_MULTI_RD 15
15004 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
15005 #define F_DTU_WR_MULTI_RD V_DTU_WR_MULTI_RD(1U)
15007 #define S_DTU_DATA_MASK_EN 14
15008 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
15009 #define F_DTU_DATA_MASK_EN V_DTU_DATA_MASK_EN(1U)
15011 #define S_DTU_TARGET_LANE 10
15012 #define M_DTU_TARGET_LANE 0xfU
15013 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
15014 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
15016 #define S_DTU_GENERATE_RANDOM 9
15017 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
15018 #define F_DTU_GENERATE_RANDOM V_DTU_GENERATE_RANDOM(1U)
15020 #define S_DTU_INCR_BANKS 8
15021 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
15022 #define F_DTU_INCR_BANKS V_DTU_INCR_BANKS(1U)
15024 #define S_DTU_INCR_COLS 7
15025 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
15026 #define F_DTU_INCR_COLS V_DTU_INCR_COLS(1U)
15028 #define S_DTU_NALEN 1
15029 #define M_DTU_NALEN 0x3fU
15030 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
15031 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
15033 #define S_DTU_ENABLE 0
15034 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
15035 #define F_DTU_ENABLE V_DTU_ENABLE(1U)
15037 #define A_MC_PCTL_DTUECTL 0x640c
15039 #define S_WR_MULTI_RD_RST 2
15040 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
15041 #define F_WR_MULTI_RD_RST V_WR_MULTI_RD_RST(1U)
15043 #define S_RUN_ERROR_REPORTS 1
15044 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
15045 #define F_RUN_ERROR_REPORTS V_RUN_ERROR_REPORTS(1U)
15047 #define S_RUN_DTU 0
15048 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
15049 #define F_RUN_DTU V_RUN_DTU(1U)
15051 #define A_MC_PCTL_DTUWD0 0x6410
15053 #define S_DTU_WR_BYTE3 24
15054 #define M_DTU_WR_BYTE3 0xffU
15055 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
15056 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
15058 #define S_DTU_WR_BYTE2 16
15059 #define M_DTU_WR_BYTE2 0xffU
15060 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
15061 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
15063 #define S_DTU_WR_BYTE1 8
15064 #define M_DTU_WR_BYTE1 0xffU
15065 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
15066 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
15068 #define S_DTU_WR_BYTE0 0
15069 #define M_DTU_WR_BYTE0 0xffU
15070 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
15071 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
15073 #define A_MC_PCTL_DTUWD1 0x6414
15075 #define S_DTU_WR_BYTE7 24
15076 #define M_DTU_WR_BYTE7 0xffU
15077 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
15078 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
15080 #define S_DTU_WR_BYTE6 16
15081 #define M_DTU_WR_BYTE6 0xffU
15082 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
15083 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
15085 #define S_DTU_WR_BYTE5 8
15086 #define M_DTU_WR_BYTE5 0xffU
15087 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
15088 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
15090 #define S_DTU_WR_BYTE4 0
15091 #define M_DTU_WR_BYTE4 0xffU
15092 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
15093 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
15095 #define A_MC_PCTL_DTUWD2 0x6418
15097 #define S_DTU_WR_BYTE11 24
15098 #define M_DTU_WR_BYTE11 0xffU
15099 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
15100 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
15102 #define S_DTU_WR_BYTE10 16
15103 #define M_DTU_WR_BYTE10 0xffU
15104 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
15105 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
15107 #define S_DTU_WR_BYTE9 8
15108 #define M_DTU_WR_BYTE9 0xffU
15109 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
15110 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
15112 #define S_DTU_WR_BYTE8 0
15113 #define M_DTU_WR_BYTE8 0xffU
15114 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
15115 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
15117 #define A_MC_PCTL_DTUWD3 0x641c
15119 #define S_DTU_WR_BYTE15 24
15120 #define M_DTU_WR_BYTE15 0xffU
15121 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
15122 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
15124 #define S_DTU_WR_BYTE14 16
15125 #define M_DTU_WR_BYTE14 0xffU
15126 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
15127 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
15129 #define S_DTU_WR_BYTE13 8
15130 #define M_DTU_WR_BYTE13 0xffU
15131 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
15132 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
15134 #define S_DTU_WR_BYTE12 0
15135 #define M_DTU_WR_BYTE12 0xffU
15136 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
15137 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
15139 #define A_MC_PCTL_DTUWDM 0x6420
15141 #define S_DM_WR_BYTE0 0
15142 #define M_DM_WR_BYTE0 0xffffU
15143 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
15144 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
15146 #define A_MC_PCTL_DTURD0 0x6424
15148 #define S_DTU_RD_BYTE3 24
15149 #define M_DTU_RD_BYTE3 0xffU
15150 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
15151 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
15153 #define S_DTU_RD_BYTE2 16
15154 #define M_DTU_RD_BYTE2 0xffU
15155 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
15156 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
15158 #define S_DTU_RD_BYTE1 8
15159 #define M_DTU_RD_BYTE1 0xffU
15160 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
15161 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
15163 #define S_DTU_RD_BYTE0 0
15164 #define M_DTU_RD_BYTE0 0xffU
15165 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
15166 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
15168 #define A_MC_PCTL_DTURD1 0x6428
15170 #define S_DTU_RD_BYTE7 24
15171 #define M_DTU_RD_BYTE7 0xffU
15172 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
15173 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
15175 #define S_DTU_RD_BYTE6 16
15176 #define M_DTU_RD_BYTE6 0xffU
15177 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
15178 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
15180 #define S_DTU_RD_BYTE5 8
15181 #define M_DTU_RD_BYTE5 0xffU
15182 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
15183 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
15185 #define S_DTU_RD_BYTE4 0
15186 #define M_DTU_RD_BYTE4 0xffU
15187 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
15188 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
15190 #define A_MC_PCTL_DTURD2 0x642c
15192 #define S_DTU_RD_BYTE11 24
15193 #define M_DTU_RD_BYTE11 0xffU
15194 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
15195 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
15197 #define S_DTU_RD_BYTE10 16
15198 #define M_DTU_RD_BYTE10 0xffU
15199 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
15200 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
15202 #define S_DTU_RD_BYTE9 8
15203 #define M_DTU_RD_BYTE9 0xffU
15204 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
15205 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
15207 #define S_DTU_RD_BYTE8 0
15208 #define M_DTU_RD_BYTE8 0xffU
15209 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
15210 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
15212 #define A_MC_PCTL_DTURD3 0x6430
15214 #define S_DTU_RD_BYTE15 24
15215 #define M_DTU_RD_BYTE15 0xffU
15216 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
15217 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
15219 #define S_DTU_RD_BYTE14 16
15220 #define M_DTU_RD_BYTE14 0xffU
15221 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
15222 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
15224 #define S_DTU_RD_BYTE13 8
15225 #define M_DTU_RD_BYTE13 0xffU
15226 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
15227 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
15229 #define S_DTU_RD_BYTE12 0
15230 #define M_DTU_RD_BYTE12 0xffU
15231 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
15232 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
15234 #define A_MC_DTULFSRWD 0x6434
15235 #define A_MC_PCTL_DTULFSRRD 0x6438
15236 #define A_MC_PCTL_DTUEAF 0x643c
15238 #define S_EA_RANK 30
15239 #define M_EA_RANK 0x3U
15240 #define V_EA_RANK(x) ((x) << S_EA_RANK)
15241 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
15243 #define S_EA_ROW 13
15244 #define M_EA_ROW 0x1ffffU
15245 #define V_EA_ROW(x) ((x) << S_EA_ROW)
15246 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
15248 #define S_EA_BANK 10
15249 #define M_EA_BANK 0x7U
15250 #define V_EA_BANK(x) ((x) << S_EA_BANK)
15251 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
15253 #define S_EA_COLUMN 0
15254 #define M_EA_COLUMN 0x3ffU
15255 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
15256 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
15258 #define A_MC_PCTL_PHYPVTCFG 0x6500
15260 #define S_PVT_UPD_REQ_EN 15
15261 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
15262 #define F_PVT_UPD_REQ_EN V_PVT_UPD_REQ_EN(1U)
15264 #define S_PVT_UPD_TRIG_POL 14
15265 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
15266 #define F_PVT_UPD_TRIG_POL V_PVT_UPD_TRIG_POL(1U)
15268 #define S_PVT_UPD_TRIG_TYPE 12
15269 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
15270 #define F_PVT_UPD_TRIG_TYPE V_PVT_UPD_TRIG_TYPE(1U)
15272 #define S_PVT_UPD_DONE_POL 10
15273 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
15274 #define F_PVT_UPD_DONE_POL V_PVT_UPD_DONE_POL(1U)
15276 #define S_PVT_UPD_DONE_TYPE 8
15277 #define M_PVT_UPD_DONE_TYPE 0x3U
15278 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
15279 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
15281 #define S_PHY_UPD_REQ_EN 7
15282 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
15283 #define F_PHY_UPD_REQ_EN V_PHY_UPD_REQ_EN(1U)
15285 #define S_PHY_UPD_TRIG_POL 6
15286 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
15287 #define F_PHY_UPD_TRIG_POL V_PHY_UPD_TRIG_POL(1U)
15289 #define S_PHY_UPD_TRIG_TYPE 4
15290 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
15291 #define F_PHY_UPD_TRIG_TYPE V_PHY_UPD_TRIG_TYPE(1U)
15293 #define S_PHY_UPD_DONE_POL 2
15294 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
15295 #define F_PHY_UPD_DONE_POL V_PHY_UPD_DONE_POL(1U)
15297 #define S_PHY_UPD_DONE_TYPE 0
15298 #define M_PHY_UPD_DONE_TYPE 0x3U
15299 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
15300 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
15302 #define A_MC_PCTL_PHYPVTSTAT 0x6504
15304 #define S_I_PVT_UPD_TRIG 5
15305 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
15306 #define F_I_PVT_UPD_TRIG V_I_PVT_UPD_TRIG(1U)
15308 #define S_I_PVT_UPD_DONE 4
15309 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
15310 #define F_I_PVT_UPD_DONE V_I_PVT_UPD_DONE(1U)
15312 #define S_I_PHY_UPD_TRIG 1
15313 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
15314 #define F_I_PHY_UPD_TRIG V_I_PHY_UPD_TRIG(1U)
15316 #define S_I_PHY_UPD_DONE 0
15317 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
15318 #define F_I_PHY_UPD_DONE V_I_PHY_UPD_DONE(1U)
15320 #define A_MC_PCTL_PHYTUPDON 0x6508
15322 #define S_PHY_T_UPDON 0
15323 #define M_PHY_T_UPDON 0xffU
15324 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
15325 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
15327 #define A_MC_PCTL_PHYTUPDDLY 0x650c
15329 #define S_PHY_T_UPDDLY 0
15330 #define M_PHY_T_UPDDLY 0xfU
15331 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
15332 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
15334 #define A_MC_PCTL_PVTTUPON 0x6510
15336 #define S_PVT_T_UPDON 0
15337 #define M_PVT_T_UPDON 0xffU
15338 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
15339 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
15341 #define A_MC_PCTL_PVTTUPDDLY 0x6514
15343 #define S_PVT_T_UPDDLY 0
15344 #define M_PVT_T_UPDDLY 0xfU
15345 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
15346 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
15348 #define A_MC_PCTL_PHYPVTUPDI 0x6518
15350 #define S_PHYPVT_T_UPDI 0
15351 #define M_PHYPVT_T_UPDI 0xffU
15352 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
15353 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
15355 #define A_MC_PCTL_PHYIOCRV1 0x651c
15357 #define S_BYTE_OE_CTL 16
15358 #define M_BYTE_OE_CTL 0x3U
15359 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
15360 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
15362 #define S_DYN_SOC_ODT_ALAT 12
15363 #define M_DYN_SOC_ODT_ALAT 0xfU
15364 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
15365 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
15367 #define S_DYN_SOC_ODT_ATEN 8
15368 #define M_DYN_SOC_ODT_ATEN 0x3U
15369 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
15370 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
15372 #define S_DYN_SOC_ODT 2
15373 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
15374 #define F_DYN_SOC_ODT V_DYN_SOC_ODT(1U)
15376 #define S_SOC_ODT_EN 0
15377 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
15378 #define F_SOC_ODT_EN V_SOC_ODT_EN(1U)
15380 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
15382 #define S_PHY_T_UPDWAIT 0
15383 #define M_PHY_T_UPDWAIT 0x3fU
15384 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
15385 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
15387 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
15389 #define S_PVT_T_UPDWAIT 0
15390 #define M_PVT_T_UPDWAIT 0x3fU
15391 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
15392 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
15394 #define A_MC_DDR3PHYAC_GCR 0x6a00
15397 #define M_WLRANK 0x3U
15398 #define V_WLRANK(x) ((x) << S_WLRANK)
15399 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
15402 #define M_FDEPTH 0x3U
15403 #define V_FDEPTH(x) ((x) << S_FDEPTH)
15404 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
15406 #define S_LPFDEPTH 4
15407 #define M_LPFDEPTH 0x3U
15408 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
15409 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
15412 #define V_LPFEN(x) ((x) << S_LPFEN)
15413 #define F_LPFEN V_LPFEN(1U)
15416 #define V_WL(x) ((x) << S_WL)
15417 #define F_WL V_WL(1U)
15420 #define V_CAL(x) ((x) << S_CAL)
15421 #define F_CAL V_CAL(1U)
15424 #define V_MDLEN(x) ((x) << S_MDLEN)
15425 #define F_MDLEN V_MDLEN(1U)
15427 #define A_MC_DDR3PHYAC_RCR0 0x6a04
15430 #define V_OCPONR(x) ((x) << S_OCPONR)
15431 #define F_OCPONR V_OCPONR(1U)
15434 #define V_OCPOND(x) ((x) << S_OCPOND)
15435 #define F_OCPOND V_OCPOND(1U)
15438 #define V_OCOEN(x) ((x) << S_OCOEN)
15439 #define F_OCOEN V_OCOEN(1U)
15441 #define S_CKEPONR 5
15442 #define V_CKEPONR(x) ((x) << S_CKEPONR)
15443 #define F_CKEPONR V_CKEPONR(1U)
15445 #define S_CKEPOND 4
15446 #define V_CKEPOND(x) ((x) << S_CKEPOND)
15447 #define F_CKEPOND V_CKEPOND(1U)
15450 #define V_CKEOEN(x) ((x) << S_CKEOEN)
15451 #define F_CKEOEN V_CKEOEN(1U)
15454 #define V_CKPONR(x) ((x) << S_CKPONR)
15455 #define F_CKPONR V_CKPONR(1U)
15458 #define V_CKPOND(x) ((x) << S_CKPOND)
15459 #define F_CKPOND V_CKPOND(1U)
15462 #define V_CKOEN(x) ((x) << S_CKOEN)
15463 #define F_CKOEN V_CKOEN(1U)
15465 #define A_MC_DDR3PHYAC_ACCR 0x6a14
15468 #define V_ACPONR(x) ((x) << S_ACPONR)
15469 #define F_ACPONR V_ACPONR(1U)
15472 #define V_ACPOND(x) ((x) << S_ACPOND)
15473 #define F_ACPOND V_ACPOND(1U)
15476 #define V_ACOEN(x) ((x) << S_ACOEN)
15477 #define F_ACOEN V_ACOEN(1U)
15479 #define S_CK5PONR 5
15480 #define V_CK5PONR(x) ((x) << S_CK5PONR)
15481 #define F_CK5PONR V_CK5PONR(1U)
15483 #define S_CK5POND 4
15484 #define V_CK5POND(x) ((x) << S_CK5POND)
15485 #define F_CK5POND V_CK5POND(1U)
15488 #define V_CK5OEN(x) ((x) << S_CK5OEN)
15489 #define F_CK5OEN V_CK5OEN(1U)
15491 #define S_CK4PONR 2
15492 #define V_CK4PONR(x) ((x) << S_CK4PONR)
15493 #define F_CK4PONR V_CK4PONR(1U)
15495 #define S_CK4POND 1
15496 #define V_CK4POND(x) ((x) << S_CK4POND)
15497 #define F_CK4POND V_CK4POND(1U)
15500 #define V_CK4OEN(x) ((x) << S_CK4OEN)
15501 #define F_CK4OEN V_CK4OEN(1U)
15503 #define A_MC_DDR3PHYAC_GSR 0x6a18
15506 #define V_WLERR(x) ((x) << S_WLERR)
15507 #define F_WLERR V_WLERR(1U)
15510 #define V_INIT(x) ((x) << S_INIT)
15511 #define F_INIT V_INIT(1U)
15514 #define V_ACCAL(x) ((x) << S_ACCAL)
15515 #define F_ACCAL V_ACCAL(1U)
15517 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
15520 #define V_WLDEC(x) ((x) << S_WLDEC)
15521 #define F_WLDEC V_WLDEC(1U)
15524 #define V_WLINC(x) ((x) << S_WLINC)
15525 #define F_WLINC V_WLINC(1U)
15527 #define A_MC_DDR3PHYAC_OCSR 0x6a20
15528 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
15531 #define M_PRD 0x3ffU
15532 #define V_PRD(x) ((x) << S_PRD)
15533 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
15535 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
15536 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
15537 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
15538 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
15540 #define S_DFLTDLY 0
15541 #define M_DFLTDLY 0x7fU
15542 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
15543 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
15545 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
15546 #define A_MC_DDR3PHYAC_ACR 0x6a60
15549 #define V_TSEL(x) ((x) << S_TSEL)
15550 #define F_TSEL V_TSEL(1U)
15553 #define M_ISEL 0x3U
15554 #define V_ISEL(x) ((x) << S_ISEL)
15555 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
15558 #define V_CALBYP(x) ((x) << S_CALBYP)
15559 #define F_CALBYP V_CALBYP(1U)
15561 #define S_SDRSELINV 1
15562 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
15563 #define F_SDRSELINV V_SDRSELINV(1U)
15566 #define V_CKINV(x) ((x) << S_CKINV)
15567 #define F_CKINV V_CKINV(1U)
15569 #define A_MC_DDR3PHYAC_PSCR 0x6a64
15572 #define M_PSCALE 0x3ffU
15573 #define V_PSCALE(x) ((x) << S_PSCALE)
15574 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
15576 #define A_MC_DDR3PHYAC_PRCR 0x6a68
15578 #define S_PHYINIT 9
15579 #define V_PHYINIT(x) ((x) << S_PHYINIT)
15580 #define F_PHYINIT V_PHYINIT(1U)
15582 #define S_PHYHRST 7
15583 #define V_PHYHRST(x) ((x) << S_PHYHRST)
15584 #define F_PHYHRST V_PHYHRST(1U)
15586 #define S_RSTCLKS 3
15587 #define M_RSTCLKS 0xfU
15588 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
15589 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
15592 #define V_PLLPD(x) ((x) << S_PLLPD)
15593 #define F_PLLPD V_PLLPD(1U)
15596 #define V_PLLRST(x) ((x) << S_PLLRST)
15597 #define F_PLLRST V_PLLRST(1U)
15600 #define V_PHYRST(x) ((x) << S_PHYRST)
15601 #define F_PHYRST V_PHYRST(1U)
15603 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
15605 #define S_RSTCXKS 4
15606 #define M_RSTCXKS 0x1fU
15607 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
15608 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
15611 #define V_ICPSEL(x) ((x) << S_ICPSEL)
15612 #define F_ICPSEL V_ICPSEL(1U)
15615 #define M_TESTA 0x7U
15616 #define V_TESTA(x) ((x) << S_TESTA)
15617 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
15619 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
15622 #define V_BYPASS(x) ((x) << S_BYPASS)
15623 #define F_BYPASS V_BYPASS(1U)
15626 #define M_BDIV 0x3U
15627 #define V_BDIV(x) ((x) << S_BDIV)
15628 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
15631 #define M_TESTD 0x7U
15632 #define V_TESTD(x) ((x) << S_TESTD)
15633 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
15635 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
15637 #define S_CKCLKEN 3
15638 #define M_CKCLKEN 0x3fU
15639 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
15640 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
15642 #define S_HDRCLKEN 2
15643 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
15644 #define F_HDRCLKEN V_HDRCLKEN(1U)
15646 #define S_SDRCLKEN 1
15647 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
15648 #define F_SDRCLKEN V_SDRCLKEN(1U)
15650 #define S_DDRCLKEN 0
15651 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
15652 #define F_DDRCLKEN V_DDRCLKEN(1U)
15654 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
15657 #define V_PONR(x) ((x) << S_PONR)
15658 #define F_PONR V_PONR(1U)
15661 #define V_POND(x) ((x) << S_POND)
15662 #define F_POND V_POND(1U)
15665 #define V_RDBDVT(x) ((x) << S_RDBDVT)
15666 #define F_RDBDVT V_RDBDVT(1U)
15669 #define V_WDBDVT(x) ((x) << S_WDBDVT)
15670 #define F_WDBDVT V_WDBDVT(1U)
15673 #define V_RDSDVT(x) ((x) << S_RDSDVT)
15674 #define F_RDSDVT V_RDSDVT(1U)
15677 #define V_WDSDVT(x) ((x) << S_WDSDVT)
15678 #define F_WDSDVT V_WDSDVT(1U)
15681 #define V_WLSDVT(x) ((x) << S_WLSDVT)
15682 #define F_WLSDVT V_WLSDVT(1U)
15684 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
15686 #define S_WDSDR_DLY 0
15687 #define M_WDSDR_DLY 0x3ffU
15688 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
15689 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
15691 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
15692 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
15695 #define M_WL_DLY 0x3ffU
15696 #define V_WL_DLY(x) ((x) << S_WL_DLY)
15697 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
15699 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
15702 #define M_DLY 0x7fU
15703 #define V_DLY(x) ((x) << S_DLY)
15704 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
15706 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
15707 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
15708 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
15709 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
15710 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
15711 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
15712 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
15713 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
15714 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
15717 #define M_MAXDLY 0x7fU
15718 #define V_MAXDLY(x) ((x) << S_MAXDLY)
15719 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
15721 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
15723 #define S_RDSDR_DLY 0
15724 #define M_RDSDR_DLY 0x3ffU
15725 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
15726 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
15728 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
15729 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
15730 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
15731 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
15732 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
15733 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
15734 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
15735 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
15736 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
15737 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
15738 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
15739 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
15740 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
15741 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
15744 #define M_DP_DLY 0x1ffU
15745 #define V_DP_DLY(x) ((x) << S_DP_DLY)
15746 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
15748 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
15749 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
15752 #define V_WLDONE(x) ((x) << S_WLDONE)
15753 #define F_WLDONE V_WLDONE(1U)
15756 #define V_WLCAL(x) ((x) << S_WLCAL)
15757 #define F_WLCAL V_WLCAL(1U)
15760 #define V_READ(x) ((x) << S_READ)
15761 #define F_READ V_READ(1U)
15763 #define S_RDQSCAL 0
15764 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
15765 #define F_RDQSCAL V_RDQSCAL(1U)
15767 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
15769 #define S_PHYHSRST 9
15770 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
15771 #define F_PHYHSRST V_PHYHSRST(1U)
15774 #define V_WLSTEP(x) ((x) << S_WLSTEP)
15775 #define F_WLSTEP V_WLSTEP(1U)
15777 #define S_SDR_SEL_INV 2
15778 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
15779 #define F_SDR_SEL_INV V_SDR_SEL_INV(1U)
15781 #define S_DDRSELINV 1
15782 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
15783 #define F_DDRSELINV V_DDRSELINV(1U)
15786 #define V_DSINV(x) ((x) << S_DSINV)
15787 #define F_DSINV V_DSINV(1U)
15789 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
15791 #define S_WLRANKSEL 9
15792 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
15793 #define F_WLRANKSEL V_WLRANKSEL(1U)
15796 #define M_RANK 0x3U
15797 #define V_RANK(x) ((x) << S_RANK)
15798 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
15800 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
15803 #define M_DTOSEL 0x3U
15804 #define V_DTOSEL(x) ((x) << S_DTOSEL)
15805 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
15807 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
15808 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
15809 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
15810 #define A_MC_PVT_REG_DRVN 0x740c
15811 #define A_MC_PVT_REG_DRVP 0x7410
15812 #define A_MC_PVT_REG_TERMN 0x7414
15813 #define A_MC_PVT_REG_TERMP 0x7418
15814 #define A_MC_PVT_REG_THRESHOLD 0x741c
15815 #define A_MC_PVT_REG_IN_TERMP 0x7420
15816 #define A_MC_PVT_REG_IN_TERMN 0x7424
15817 #define A_MC_PVT_REG_IN_DRVP 0x7428
15818 #define A_MC_PVT_REG_IN_DRVN 0x742c
15819 #define A_MC_PVT_REG_OUT_TERMP 0x7430
15820 #define A_MC_PVT_REG_OUT_TERMN 0x7434
15821 #define A_MC_PVT_REG_OUT_DRVP 0x7438
15822 #define A_MC_PVT_REG_OUT_DRVN 0x743c
15823 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
15824 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
15825 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
15826 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
15827 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
15828 #define A_MC_DDRPHY_RST_CTRL 0x7500
15830 #define S_DDRIO_ENABLE 1
15831 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
15832 #define F_DDRIO_ENABLE V_DDRIO_ENABLE(1U)
15834 #define S_PHY_RST_N 0
15835 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
15836 #define F_PHY_RST_N V_PHY_RST_N(1U)
15838 #define A_MC_PERFORMANCE_CTRL 0x7504
15840 #define S_STALL_CHK_BIT 2
15841 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
15842 #define F_STALL_CHK_BIT V_STALL_CHK_BIT(1U)
15844 #define S_DDR3_BRC_MODE 1
15845 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
15846 #define F_DDR3_BRC_MODE V_DDR3_BRC_MODE(1U)
15848 #define S_RMW_PERF_CTRL 0
15849 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
15850 #define F_RMW_PERF_CTRL V_RMW_PERF_CTRL(1U)
15852 #define A_MC_ECC_CTRL 0x7508
15854 #define S_ECC_BYPASS_BIST 1
15855 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
15856 #define F_ECC_BYPASS_BIST V_ECC_BYPASS_BIST(1U)
15858 #define S_ECC_DISABLE 0
15859 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
15860 #define F_ECC_DISABLE V_ECC_DISABLE(1U)
15862 #define A_MC_PAR_ENABLE 0x750c
15864 #define S_ECC_UE_PAR_ENABLE 3
15865 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
15866 #define F_ECC_UE_PAR_ENABLE V_ECC_UE_PAR_ENABLE(1U)
15868 #define S_ECC_CE_PAR_ENABLE 2
15869 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
15870 #define F_ECC_CE_PAR_ENABLE V_ECC_CE_PAR_ENABLE(1U)
15872 #define S_PERR_REG_INT_ENABLE 1
15873 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
15874 #define F_PERR_REG_INT_ENABLE V_PERR_REG_INT_ENABLE(1U)
15876 #define S_PERR_BLK_INT_ENABLE 0
15877 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
15878 #define F_PERR_BLK_INT_ENABLE V_PERR_BLK_INT_ENABLE(1U)
15880 #define A_MC_PAR_CAUSE 0x7510
15882 #define S_ECC_UE_PAR_CAUSE 3
15883 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
15884 #define F_ECC_UE_PAR_CAUSE V_ECC_UE_PAR_CAUSE(1U)
15886 #define S_ECC_CE_PAR_CAUSE 2
15887 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
15888 #define F_ECC_CE_PAR_CAUSE V_ECC_CE_PAR_CAUSE(1U)
15890 #define S_FIFOR_PAR_CAUSE 1
15891 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
15892 #define F_FIFOR_PAR_CAUSE V_FIFOR_PAR_CAUSE(1U)
15894 #define S_RDATA_FIFOR_PAR_CAUSE 0
15895 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
15896 #define F_RDATA_FIFOR_PAR_CAUSE V_RDATA_FIFOR_PAR_CAUSE(1U)
15898 #define A_MC_INT_ENABLE 0x7514
15900 #define S_ECC_UE_INT_ENABLE 2
15901 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
15902 #define F_ECC_UE_INT_ENABLE V_ECC_UE_INT_ENABLE(1U)
15904 #define S_ECC_CE_INT_ENABLE 1
15905 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
15906 #define F_ECC_CE_INT_ENABLE V_ECC_CE_INT_ENABLE(1U)
15908 #define S_PERR_INT_ENABLE 0
15909 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
15910 #define F_PERR_INT_ENABLE V_PERR_INT_ENABLE(1U)
15912 #define A_MC_INT_CAUSE 0x7518
15914 #define S_ECC_UE_INT_CAUSE 2
15915 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
15916 #define F_ECC_UE_INT_CAUSE V_ECC_UE_INT_CAUSE(1U)
15918 #define S_ECC_CE_INT_CAUSE 1
15919 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
15920 #define F_ECC_CE_INT_CAUSE V_ECC_CE_INT_CAUSE(1U)
15922 #define S_PERR_INT_CAUSE 0
15923 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
15924 #define F_PERR_INT_CAUSE V_PERR_INT_CAUSE(1U)
15926 #define A_MC_ECC_STATUS 0x751c
15928 #define S_ECC_CECNT 16
15929 #define M_ECC_CECNT 0xffffU
15930 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
15931 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
15933 #define S_ECC_UECNT 0
15934 #define M_ECC_UECNT 0xffffU
15935 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
15936 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
15938 #define A_MC_PHY_CTRL 0x7520
15940 #define S_CTLPHYRR 0
15941 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
15942 #define F_CTLPHYRR V_CTLPHYRR(1U)
15944 #define A_MC_STATIC_CFG_STATUS 0x7524
15946 #define S_STATIC_MODE 9
15947 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
15948 #define F_STATIC_MODE V_STATIC_MODE(1U)
15950 #define S_STATIC_DEN 6
15951 #define M_STATIC_DEN 0x7U
15952 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
15953 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
15955 #define S_STATIC_ORG 5
15956 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
15957 #define F_STATIC_ORG V_STATIC_ORG(1U)
15959 #define S_STATIC_RKS 4
15960 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
15961 #define F_STATIC_RKS V_STATIC_RKS(1U)
15963 #define S_STATIC_WIDTH 1
15964 #define M_STATIC_WIDTH 0x7U
15965 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
15966 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
15968 #define S_STATIC_SLOW 0
15969 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
15970 #define F_STATIC_SLOW V_STATIC_SLOW(1U)
15972 #define A_MC_CORE_PCTL_STAT 0x7528
15974 #define S_PCTL_ACCESS_STAT 0
15975 #define M_PCTL_ACCESS_STAT 0x7U
15976 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
15977 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
15979 #define A_MC_DEBUG_CNT 0x752c
15981 #define S_WDATA_OCNT 8
15982 #define M_WDATA_OCNT 0x1fU
15983 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
15984 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
15986 #define S_RDATA_OCNT 0
15987 #define M_RDATA_OCNT 0x1fU
15988 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
15989 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
15991 #define A_MC_BONUS 0x7530
15992 #define A_MC_BIST_CMD 0x7600
15994 #define S_START_BIST 31
15995 #define V_START_BIST(x) ((x) << S_START_BIST)
15996 #define F_START_BIST V_START_BIST(1U)
15998 #define S_BIST_CMD_GAP 8
15999 #define M_BIST_CMD_GAP 0xffU
16000 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
16001 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
16003 #define S_BIST_OPCODE 0
16004 #define M_BIST_OPCODE 0x3U
16005 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
16006 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
16008 #define A_MC_BIST_CMD_ADDR 0x7604
16009 #define A_MC_BIST_CMD_LEN 0x7608
16010 #define A_MC_BIST_DATA_PATTERN 0x760c
16012 #define S_BIST_DATA_TYPE 0
16013 #define M_BIST_DATA_TYPE 0xfU
16014 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
16015 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
16017 #define A_MC_BIST_USER_WDATA0 0x7614
16018 #define A_MC_BIST_USER_WDATA1 0x7618
16019 #define A_MC_BIST_USER_WDATA2 0x761c
16021 #define S_USER_DATA2 0
16022 #define M_USER_DATA2 0xffU
16023 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
16024 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
16026 #define A_MC_BIST_NUM_ERR 0x7680
16027 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
16028 #define A_MC_BIST_STATUS_RDATA 0x7688
16030 /* registers for module MA */
16031 #define MA_BASE_ADDR 0x7700
16033 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
16035 #define S_THRESHOLD1 17
16036 #define M_THRESHOLD1 0x7fffU
16037 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
16038 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
16040 #define S_THRESHOLD1_EN 16
16041 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
16042 #define F_THRESHOLD1_EN V_THRESHOLD1_EN(1U)
16044 #define S_THRESHOLD0 1
16045 #define M_THRESHOLD0 0x7fffU
16046 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
16047 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
16049 #define S_THRESHOLD0_EN 0
16050 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
16051 #define F_THRESHOLD0_EN V_THRESHOLD0_EN(1U)
16053 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
16054 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
16055 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
16056 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
16057 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
16058 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
16059 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
16060 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
16061 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
16062 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
16063 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
16064 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
16065 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
16066 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
16067 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
16068 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
16069 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
16070 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
16071 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
16072 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
16073 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
16074 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
16075 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
16076 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
16077 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
16078 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
16080 #define S_DBG_READ_DATA_CNT 24
16081 #define M_DBG_READ_DATA_CNT 0xffU
16082 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
16083 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
16085 #define S_DBG_READ_REQ_CNT 16
16086 #define M_DBG_READ_REQ_CNT 0xffU
16087 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
16088 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
16090 #define S_DBG_WRITE_DATA_CNT 8
16091 #define M_DBG_WRITE_DATA_CNT 0xffU
16092 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
16093 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
16095 #define S_DBG_WRITE_REQ_CNT 0
16096 #define M_DBG_WRITE_REQ_CNT 0xffU
16097 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
16098 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
16100 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
16101 #define A_MA_ULPTX_DEBUG_CNT 0x7770
16102 #define A_MA_ULPRX_DEBUG_CNT 0x7774
16103 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
16104 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
16105 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
16106 #define A_MA_LE_DEBUG_CNT 0x7784
16107 #define A_MA_CIM_DEBUG_CNT 0x7788
16108 #define A_MA_PCIE_DEBUG_CNT 0x778c
16109 #define A_MA_PMTX_DEBUG_CNT 0x7790
16110 #define A_MA_PMRX_DEBUG_CNT 0x7794
16111 #define A_MA_HMA_DEBUG_CNT 0x7798
16112 #define A_MA_EDRAM0_BAR 0x77c0
16114 #define S_EDRAM0_BASE 16
16115 #define M_EDRAM0_BASE 0xfffU
16116 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
16117 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
16119 #define S_EDRAM0_SIZE 0
16120 #define M_EDRAM0_SIZE 0xfffU
16121 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
16122 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
16124 #define A_MA_EDRAM1_BAR 0x77c4
16126 #define S_EDRAM1_BASE 16
16127 #define M_EDRAM1_BASE 0xfffU
16128 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
16129 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
16131 #define S_EDRAM1_SIZE 0
16132 #define M_EDRAM1_SIZE 0xfffU
16133 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
16134 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
16136 #define A_MA_EXT_MEMORY_BAR 0x77c8
16138 #define S_EXT_MEM_BASE 16
16139 #define M_EXT_MEM_BASE 0xfffU
16140 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
16141 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
16143 #define S_EXT_MEM_SIZE 0
16144 #define M_EXT_MEM_SIZE 0xfffU
16145 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
16146 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
16148 #define A_MA_EXT_MEMORY0_BAR 0x77c8
16150 #define S_EXT_MEM0_BASE 16
16151 #define M_EXT_MEM0_BASE 0xfffU
16152 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
16153 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
16155 #define S_EXT_MEM0_SIZE 0
16156 #define M_EXT_MEM0_SIZE 0xfffU
16157 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
16158 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
16160 #define A_MA_HOST_MEMORY_BAR 0x77cc
16162 #define S_HMA_BASE 16
16163 #define M_HMA_BASE 0xfffU
16164 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
16165 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
16167 #define S_HMA_SIZE 0
16168 #define M_HMA_SIZE 0xfffU
16169 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
16170 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
16172 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
16174 #define S_BRC_MODE 2
16175 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
16176 #define F_BRC_MODE V_BRC_MODE(1U)
16178 #define S_EXT_MEM_PAGE_SIZE 0
16179 #define M_EXT_MEM_PAGE_SIZE 0x3U
16180 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
16181 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
16183 #define S_BRC_MODE1 6
16184 #define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
16185 #define F_BRC_MODE1 V_BRC_MODE1(1U)
16187 #define S_EXT_MEM_PAGE_SIZE1 4
16188 #define M_EXT_MEM_PAGE_SIZE1 0x3U
16189 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
16190 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
16192 #define S_BRBC_MODE 4
16193 #define V_BRBC_MODE(x) ((x) << S_BRBC_MODE)
16194 #define F_BRBC_MODE V_BRBC_MODE(1U)
16196 #define S_T6_BRC_MODE 3
16197 #define V_T6_BRC_MODE(x) ((x) << S_T6_BRC_MODE)
16198 #define F_T6_BRC_MODE V_T6_BRC_MODE(1U)
16200 #define S_T6_EXT_MEM_PAGE_SIZE 0
16201 #define M_T6_EXT_MEM_PAGE_SIZE 0x7U
16202 #define V_T6_EXT_MEM_PAGE_SIZE(x) ((x) << S_T6_EXT_MEM_PAGE_SIZE)
16203 #define G_T6_EXT_MEM_PAGE_SIZE(x) (((x) >> S_T6_EXT_MEM_PAGE_SIZE) & M_T6_EXT_MEM_PAGE_SIZE)
16205 #define A_MA_ARB_CTRL 0x77d4
16207 #define S_DIS_PAGE_HINT 1
16208 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
16209 #define F_DIS_PAGE_HINT V_DIS_PAGE_HINT(1U)
16211 #define S_DIS_ADV_ARB 0
16212 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
16213 #define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U)
16215 #define S_DIS_BANK_FAIR 2
16216 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
16217 #define F_DIS_BANK_FAIR V_DIS_BANK_FAIR(1U)
16219 #define S_HMA_WRT_EN 26
16220 #define V_HMA_WRT_EN(x) ((x) << S_HMA_WRT_EN)
16221 #define F_HMA_WRT_EN V_HMA_WRT_EN(1U)
16223 #define S_HMA_NUM_PG_128B_FDBK 21
16224 #define M_HMA_NUM_PG_128B_FDBK 0x1fU
16225 #define V_HMA_NUM_PG_128B_FDBK(x) ((x) << S_HMA_NUM_PG_128B_FDBK)
16226 #define G_HMA_NUM_PG_128B_FDBK(x) (((x) >> S_HMA_NUM_PG_128B_FDBK) & M_HMA_NUM_PG_128B_FDBK)
16228 #define S_HMA_DIS_128B_PG_CNT_FDBK 20
16229 #define V_HMA_DIS_128B_PG_CNT_FDBK(x) ((x) << S_HMA_DIS_128B_PG_CNT_FDBK)
16230 #define F_HMA_DIS_128B_PG_CNT_FDBK V_HMA_DIS_128B_PG_CNT_FDBK(1U)
16232 #define S_HMA_DIS_BG_ARB 19
16233 #define V_HMA_DIS_BG_ARB(x) ((x) << S_HMA_DIS_BG_ARB)
16234 #define F_HMA_DIS_BG_ARB V_HMA_DIS_BG_ARB(1U)
16236 #define S_HMA_DIS_BANK_FAIR 18
16237 #define V_HMA_DIS_BANK_FAIR(x) ((x) << S_HMA_DIS_BANK_FAIR)
16238 #define F_HMA_DIS_BANK_FAIR V_HMA_DIS_BANK_FAIR(1U)
16240 #define S_HMA_DIS_PAGE_HINT 17
16241 #define V_HMA_DIS_PAGE_HINT(x) ((x) << S_HMA_DIS_PAGE_HINT)
16242 #define F_HMA_DIS_PAGE_HINT V_HMA_DIS_PAGE_HINT(1U)
16244 #define S_HMA_DIS_ADV_ARB 16
16245 #define V_HMA_DIS_ADV_ARB(x) ((x) << S_HMA_DIS_ADV_ARB)
16246 #define F_HMA_DIS_ADV_ARB V_HMA_DIS_ADV_ARB(1U)
16248 #define S_NUM_PG_128B_FDBK 5
16249 #define M_NUM_PG_128B_FDBK 0x1fU
16250 #define V_NUM_PG_128B_FDBK(x) ((x) << S_NUM_PG_128B_FDBK)
16251 #define G_NUM_PG_128B_FDBK(x) (((x) >> S_NUM_PG_128B_FDBK) & M_NUM_PG_128B_FDBK)
16253 #define S_DIS_128B_PG_CNT_FDBK 4
16254 #define V_DIS_128B_PG_CNT_FDBK(x) ((x) << S_DIS_128B_PG_CNT_FDBK)
16255 #define F_DIS_128B_PG_CNT_FDBK V_DIS_128B_PG_CNT_FDBK(1U)
16257 #define S_DIS_BG_ARB 3
16258 #define V_DIS_BG_ARB(x) ((x) << S_DIS_BG_ARB)
16259 #define F_DIS_BG_ARB V_DIS_BG_ARB(1U)
16261 #define A_MA_TARGET_MEM_ENABLE 0x77d8
16263 #define S_HMA_ENABLE 3
16264 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
16265 #define F_HMA_ENABLE V_HMA_ENABLE(1U)
16267 #define S_EXT_MEM_ENABLE 2
16268 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
16269 #define F_EXT_MEM_ENABLE V_EXT_MEM_ENABLE(1U)
16271 #define S_EDRAM1_ENABLE 1
16272 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
16273 #define F_EDRAM1_ENABLE V_EDRAM1_ENABLE(1U)
16275 #define S_EDRAM0_ENABLE 0
16276 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
16277 #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U)
16279 #define S_HMA_MUX 5
16280 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
16281 #define F_HMA_MUX V_HMA_MUX(1U)
16283 #define S_EXT_MEM1_ENABLE 4
16284 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
16285 #define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U)
16287 #define S_EXT_MEM0_ENABLE 2
16288 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
16289 #define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U)
16291 #define S_MC_SPLIT 6
16292 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
16293 #define F_MC_SPLIT V_MC_SPLIT(1U)
16295 #define A_MA_INT_ENABLE 0x77dc
16297 #define S_MEM_PERR_INT_ENABLE 1
16298 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
16299 #define F_MEM_PERR_INT_ENABLE V_MEM_PERR_INT_ENABLE(1U)
16301 #define S_MEM_WRAP_INT_ENABLE 0
16302 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
16303 #define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U)
16305 #define S_MEM_TO_INT_ENABLE 2
16306 #define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
16307 #define F_MEM_TO_INT_ENABLE V_MEM_TO_INT_ENABLE(1U)
16309 #define A_MA_INT_CAUSE 0x77e0
16311 #define S_MEM_PERR_INT_CAUSE 1
16312 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
16313 #define F_MEM_PERR_INT_CAUSE V_MEM_PERR_INT_CAUSE(1U)
16315 #define S_MEM_WRAP_INT_CAUSE 0
16316 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
16317 #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U)
16319 #define S_MEM_TO_INT_CAUSE 2
16320 #define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
16321 #define F_MEM_TO_INT_CAUSE V_MEM_TO_INT_CAUSE(1U)
16323 #define A_MA_INT_WRAP_STATUS 0x77e4
16325 #define S_MEM_WRAP_ADDRESS 4
16326 #define M_MEM_WRAP_ADDRESS 0xfffffffU
16327 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
16328 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
16330 #define S_MEM_WRAP_CLIENT_NUM 0
16331 #define M_MEM_WRAP_CLIENT_NUM 0xfU
16332 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
16333 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
16335 #define A_MA_TP_THREAD1_MAPPER 0x77e8
16337 #define S_TP_THREAD1_EN 0
16338 #define M_TP_THREAD1_EN 0xffU
16339 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
16340 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
16342 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
16344 #define S_SGE_THREAD1_EN 0
16345 #define M_SGE_THREAD1_EN 0xffU
16346 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
16347 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
16349 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
16351 #define S_TP_DMARBT_PAR_ERROR_EN 31
16352 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
16353 #define F_TP_DMARBT_PAR_ERROR_EN V_TP_DMARBT_PAR_ERROR_EN(1U)
16355 #define S_LOGIC_FIFO_PAR_ERROR_EN 30
16356 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
16357 #define F_LOGIC_FIFO_PAR_ERROR_EN V_LOGIC_FIFO_PAR_ERROR_EN(1U)
16359 #define S_ARB3_PAR_WRQUEUE_ERROR_EN 29
16360 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
16361 #define F_ARB3_PAR_WRQUEUE_ERROR_EN V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
16363 #define S_ARB2_PAR_WRQUEUE_ERROR_EN 28
16364 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
16365 #define F_ARB2_PAR_WRQUEUE_ERROR_EN V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
16367 #define S_ARB1_PAR_WRQUEUE_ERROR_EN 27
16368 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
16369 #define F_ARB1_PAR_WRQUEUE_ERROR_EN V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
16371 #define S_ARB0_PAR_WRQUEUE_ERROR_EN 26
16372 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
16373 #define F_ARB0_PAR_WRQUEUE_ERROR_EN V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
16375 #define S_ARB3_PAR_RDQUEUE_ERROR_EN 25
16376 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
16377 #define F_ARB3_PAR_RDQUEUE_ERROR_EN V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
16379 #define S_ARB2_PAR_RDQUEUE_ERROR_EN 24
16380 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
16381 #define F_ARB2_PAR_RDQUEUE_ERROR_EN V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
16383 #define S_ARB1_PAR_RDQUEUE_ERROR_EN 23
16384 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
16385 #define F_ARB1_PAR_RDQUEUE_ERROR_EN V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
16387 #define S_ARB0_PAR_RDQUEUE_ERROR_EN 22
16388 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
16389 #define F_ARB0_PAR_RDQUEUE_ERROR_EN V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
16391 #define S_CL10_PAR_WRQUEUE_ERROR_EN 21
16392 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
16393 #define F_CL10_PAR_WRQUEUE_ERROR_EN V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
16395 #define S_CL9_PAR_WRQUEUE_ERROR_EN 20
16396 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
16397 #define F_CL9_PAR_WRQUEUE_ERROR_EN V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
16399 #define S_CL8_PAR_WRQUEUE_ERROR_EN 19
16400 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
16401 #define F_CL8_PAR_WRQUEUE_ERROR_EN V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
16403 #define S_CL7_PAR_WRQUEUE_ERROR_EN 18
16404 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
16405 #define F_CL7_PAR_WRQUEUE_ERROR_EN V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
16407 #define S_CL6_PAR_WRQUEUE_ERROR_EN 17
16408 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
16409 #define F_CL6_PAR_WRQUEUE_ERROR_EN V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
16411 #define S_CL5_PAR_WRQUEUE_ERROR_EN 16
16412 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
16413 #define F_CL5_PAR_WRQUEUE_ERROR_EN V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
16415 #define S_CL4_PAR_WRQUEUE_ERROR_EN 15
16416 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
16417 #define F_CL4_PAR_WRQUEUE_ERROR_EN V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
16419 #define S_CL3_PAR_WRQUEUE_ERROR_EN 14
16420 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
16421 #define F_CL3_PAR_WRQUEUE_ERROR_EN V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
16423 #define S_CL2_PAR_WRQUEUE_ERROR_EN 13
16424 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
16425 #define F_CL2_PAR_WRQUEUE_ERROR_EN V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
16427 #define S_CL1_PAR_WRQUEUE_ERROR_EN 12
16428 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
16429 #define F_CL1_PAR_WRQUEUE_ERROR_EN V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
16431 #define S_CL0_PAR_WRQUEUE_ERROR_EN 11
16432 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
16433 #define F_CL0_PAR_WRQUEUE_ERROR_EN V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
16435 #define S_CL10_PAR_RDQUEUE_ERROR_EN 10
16436 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
16437 #define F_CL10_PAR_RDQUEUE_ERROR_EN V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
16439 #define S_CL9_PAR_RDQUEUE_ERROR_EN 9
16440 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
16441 #define F_CL9_PAR_RDQUEUE_ERROR_EN V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
16443 #define S_CL8_PAR_RDQUEUE_ERROR_EN 8
16444 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
16445 #define F_CL8_PAR_RDQUEUE_ERROR_EN V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
16447 #define S_CL7_PAR_RDQUEUE_ERROR_EN 7
16448 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
16449 #define F_CL7_PAR_RDQUEUE_ERROR_EN V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
16451 #define S_CL6_PAR_RDQUEUE_ERROR_EN 6
16452 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
16453 #define F_CL6_PAR_RDQUEUE_ERROR_EN V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
16455 #define S_CL5_PAR_RDQUEUE_ERROR_EN 5
16456 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
16457 #define F_CL5_PAR_RDQUEUE_ERROR_EN V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
16459 #define S_CL4_PAR_RDQUEUE_ERROR_EN 4
16460 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
16461 #define F_CL4_PAR_RDQUEUE_ERROR_EN V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
16463 #define S_CL3_PAR_RDQUEUE_ERROR_EN 3
16464 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
16465 #define F_CL3_PAR_RDQUEUE_ERROR_EN V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
16467 #define S_CL2_PAR_RDQUEUE_ERROR_EN 2
16468 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
16469 #define F_CL2_PAR_RDQUEUE_ERROR_EN V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
16471 #define S_CL1_PAR_RDQUEUE_ERROR_EN 1
16472 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
16473 #define F_CL1_PAR_RDQUEUE_ERROR_EN V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
16475 #define S_CL0_PAR_RDQUEUE_ERROR_EN 0
16476 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
16477 #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
16479 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
16480 #define A_MA_PARITY_ERROR_STATUS 0x77f4
16482 #define S_TP_DMARBT_PAR_ERROR 31
16483 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
16484 #define F_TP_DMARBT_PAR_ERROR V_TP_DMARBT_PAR_ERROR(1U)
16486 #define S_LOGIC_FIFO_PAR_ERROR 30
16487 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
16488 #define F_LOGIC_FIFO_PAR_ERROR V_LOGIC_FIFO_PAR_ERROR(1U)
16490 #define S_ARB3_PAR_WRQUEUE_ERROR 29
16491 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
16492 #define F_ARB3_PAR_WRQUEUE_ERROR V_ARB3_PAR_WRQUEUE_ERROR(1U)
16494 #define S_ARB2_PAR_WRQUEUE_ERROR 28
16495 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
16496 #define F_ARB2_PAR_WRQUEUE_ERROR V_ARB2_PAR_WRQUEUE_ERROR(1U)
16498 #define S_ARB1_PAR_WRQUEUE_ERROR 27
16499 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
16500 #define F_ARB1_PAR_WRQUEUE_ERROR V_ARB1_PAR_WRQUEUE_ERROR(1U)
16502 #define S_ARB0_PAR_WRQUEUE_ERROR 26
16503 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
16504 #define F_ARB0_PAR_WRQUEUE_ERROR V_ARB0_PAR_WRQUEUE_ERROR(1U)
16506 #define S_ARB3_PAR_RDQUEUE_ERROR 25
16507 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
16508 #define F_ARB3_PAR_RDQUEUE_ERROR V_ARB3_PAR_RDQUEUE_ERROR(1U)
16510 #define S_ARB2_PAR_RDQUEUE_ERROR 24
16511 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
16512 #define F_ARB2_PAR_RDQUEUE_ERROR V_ARB2_PAR_RDQUEUE_ERROR(1U)
16514 #define S_ARB1_PAR_RDQUEUE_ERROR 23
16515 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
16516 #define F_ARB1_PAR_RDQUEUE_ERROR V_ARB1_PAR_RDQUEUE_ERROR(1U)
16518 #define S_ARB0_PAR_RDQUEUE_ERROR 22
16519 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
16520 #define F_ARB0_PAR_RDQUEUE_ERROR V_ARB0_PAR_RDQUEUE_ERROR(1U)
16522 #define S_CL10_PAR_WRQUEUE_ERROR 21
16523 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
16524 #define F_CL10_PAR_WRQUEUE_ERROR V_CL10_PAR_WRQUEUE_ERROR(1U)
16526 #define S_CL9_PAR_WRQUEUE_ERROR 20
16527 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
16528 #define F_CL9_PAR_WRQUEUE_ERROR V_CL9_PAR_WRQUEUE_ERROR(1U)
16530 #define S_CL8_PAR_WRQUEUE_ERROR 19
16531 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
16532 #define F_CL8_PAR_WRQUEUE_ERROR V_CL8_PAR_WRQUEUE_ERROR(1U)
16534 #define S_CL7_PAR_WRQUEUE_ERROR 18
16535 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
16536 #define F_CL7_PAR_WRQUEUE_ERROR V_CL7_PAR_WRQUEUE_ERROR(1U)
16538 #define S_CL6_PAR_WRQUEUE_ERROR 17
16539 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
16540 #define F_CL6_PAR_WRQUEUE_ERROR V_CL6_PAR_WRQUEUE_ERROR(1U)
16542 #define S_CL5_PAR_WRQUEUE_ERROR 16
16543 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
16544 #define F_CL5_PAR_WRQUEUE_ERROR V_CL5_PAR_WRQUEUE_ERROR(1U)
16546 #define S_CL4_PAR_WRQUEUE_ERROR 15
16547 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
16548 #define F_CL4_PAR_WRQUEUE_ERROR V_CL4_PAR_WRQUEUE_ERROR(1U)
16550 #define S_CL3_PAR_WRQUEUE_ERROR 14
16551 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
16552 #define F_CL3_PAR_WRQUEUE_ERROR V_CL3_PAR_WRQUEUE_ERROR(1U)
16554 #define S_CL2_PAR_WRQUEUE_ERROR 13
16555 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
16556 #define F_CL2_PAR_WRQUEUE_ERROR V_CL2_PAR_WRQUEUE_ERROR(1U)
16558 #define S_CL1_PAR_WRQUEUE_ERROR 12
16559 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
16560 #define F_CL1_PAR_WRQUEUE_ERROR V_CL1_PAR_WRQUEUE_ERROR(1U)
16562 #define S_CL0_PAR_WRQUEUE_ERROR 11
16563 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
16564 #define F_CL0_PAR_WRQUEUE_ERROR V_CL0_PAR_WRQUEUE_ERROR(1U)
16566 #define S_CL10_PAR_RDQUEUE_ERROR 10
16567 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
16568 #define F_CL10_PAR_RDQUEUE_ERROR V_CL10_PAR_RDQUEUE_ERROR(1U)
16570 #define S_CL9_PAR_RDQUEUE_ERROR 9
16571 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
16572 #define F_CL9_PAR_RDQUEUE_ERROR V_CL9_PAR_RDQUEUE_ERROR(1U)
16574 #define S_CL8_PAR_RDQUEUE_ERROR 8
16575 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
16576 #define F_CL8_PAR_RDQUEUE_ERROR V_CL8_PAR_RDQUEUE_ERROR(1U)
16578 #define S_CL7_PAR_RDQUEUE_ERROR 7
16579 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
16580 #define F_CL7_PAR_RDQUEUE_ERROR V_CL7_PAR_RDQUEUE_ERROR(1U)
16582 #define S_CL6_PAR_RDQUEUE_ERROR 6
16583 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
16584 #define F_CL6_PAR_RDQUEUE_ERROR V_CL6_PAR_RDQUEUE_ERROR(1U)
16586 #define S_CL5_PAR_RDQUEUE_ERROR 5
16587 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
16588 #define F_CL5_PAR_RDQUEUE_ERROR V_CL5_PAR_RDQUEUE_ERROR(1U)
16590 #define S_CL4_PAR_RDQUEUE_ERROR 4
16591 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
16592 #define F_CL4_PAR_RDQUEUE_ERROR V_CL4_PAR_RDQUEUE_ERROR(1U)
16594 #define S_CL3_PAR_RDQUEUE_ERROR 3
16595 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
16596 #define F_CL3_PAR_RDQUEUE_ERROR V_CL3_PAR_RDQUEUE_ERROR(1U)
16598 #define S_CL2_PAR_RDQUEUE_ERROR 2
16599 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
16600 #define F_CL2_PAR_RDQUEUE_ERROR V_CL2_PAR_RDQUEUE_ERROR(1U)
16602 #define S_CL1_PAR_RDQUEUE_ERROR 1
16603 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
16604 #define F_CL1_PAR_RDQUEUE_ERROR V_CL1_PAR_RDQUEUE_ERROR(1U)
16606 #define S_CL0_PAR_RDQUEUE_ERROR 0
16607 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
16608 #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U)
16610 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
16611 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
16613 #define S_BONUS_REG 6
16614 #define M_BONUS_REG 0x3ffffffU
16615 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
16616 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
16618 #define S_COHERANCY_CMD_TYPE 4
16619 #define M_COHERANCY_CMD_TYPE 0x3U
16620 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
16621 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
16623 #define S_COHERANCY_THREAD_NUM 1
16624 #define M_COHERANCY_THREAD_NUM 0x7U
16625 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
16626 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
16628 #define S_COHERANCY_ENABLE 0
16629 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
16630 #define F_COHERANCY_ENABLE V_COHERANCY_ENABLE(1U)
16632 #define A_MA_ERROR_ENABLE 0x77fc
16634 #define S_UE_ENABLE 0
16635 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
16636 #define F_UE_ENABLE V_UE_ENABLE(1U)
16638 #define S_FUTURE_EXPANSION 1
16639 #define M_FUTURE_EXPANSION 0x7fffffffU
16640 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
16641 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
16643 #define S_FUTURE_EXPANSION_EE 1
16644 #define M_FUTURE_EXPANSION_EE 0x7fffffffU
16645 #define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE)
16646 #define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE)
16648 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
16650 #define S_ARB4_PAR_WRQUEUE_ERROR_EN 1
16651 #define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
16652 #define F_ARB4_PAR_WRQUEUE_ERROR_EN V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
16654 #define S_ARB4_PAR_RDQUEUE_ERROR_EN 0
16655 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
16656 #define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
16658 #define A_MA_PARITY_ERROR_STATUS2 0x7804
16660 #define S_ARB4_PAR_WRQUEUE_ERROR 1
16661 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
16662 #define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U)
16664 #define S_ARB4_PAR_RDQUEUE_ERROR 0
16665 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
16666 #define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U)
16668 #define A_MA_EXT_MEMORY1_BAR 0x7808
16670 #define S_EXT_MEM1_BASE 16
16671 #define M_EXT_MEM1_BASE 0xfffU
16672 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
16673 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
16675 #define S_EXT_MEM1_SIZE 0
16676 #define M_EXT_MEM1_SIZE 0xfffU
16677 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
16678 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
16680 #define A_MA_PMTX_THROTTLE 0x780c
16682 #define S_FL_ENABLE 31
16683 #define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
16684 #define F_FL_ENABLE V_FL_ENABLE(1U)
16686 #define S_FL_LIMIT 0
16687 #define M_FL_LIMIT 0xffU
16688 #define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
16689 #define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
16691 #define A_MA_PMRX_THROTTLE 0x7810
16692 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
16693 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
16694 #define A_MA_ULPTX_WRDATA_CNT 0x781c
16695 #define A_MA_ULPRX_WRDATA_CNT 0x7820
16696 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
16697 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
16698 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
16699 #define A_MA_LE_WRDATA_CNT 0x7830
16700 #define A_MA_CIM_WRDATA_CNT 0x7834
16701 #define A_MA_PCIE_WRDATA_CNT 0x7838
16702 #define A_MA_PMTX_WRDATA_CNT 0x783c
16703 #define A_MA_PMRX_WRDATA_CNT 0x7840
16704 #define A_MA_HMA_WRDATA_CNT 0x7844
16705 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
16706 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
16707 #define A_MA_ULPTX_RDDATA_CNT 0x7850
16708 #define A_MA_ULPRX_RDDATA_CNT 0x7854
16709 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
16710 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
16711 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
16712 #define A_MA_LE_RDDATA_CNT 0x7864
16713 #define A_MA_CIM_RDDATA_CNT 0x7868
16714 #define A_MA_PCIE_RDDATA_CNT 0x786c
16715 #define A_MA_PMTX_RDDATA_CNT 0x7870
16716 #define A_MA_PMRX_RDDATA_CNT 0x7874
16717 #define A_MA_HMA_RDDATA_CNT 0x7878
16718 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
16719 #define A_MA_EXIT_ADDR_FAULT 0x787c
16721 #define S_EXIT_ADDR_FAULT 0
16722 #define V_EXIT_ADDR_FAULT(x) ((x) << S_EXIT_ADDR_FAULT)
16723 #define F_EXIT_ADDR_FAULT V_EXIT_ADDR_FAULT(1U)
16725 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
16726 #define A_MA_DDR_DEVICE_CFG 0x7880
16728 #define S_MEM_WIDTH 1
16729 #define M_MEM_WIDTH 0x7U
16730 #define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH)
16731 #define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH)
16733 #define S_DDR_MODE 0
16734 #define V_DDR_MODE(x) ((x) << S_DDR_MODE)
16735 #define F_DDR_MODE V_DDR_MODE(1U)
16737 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
16738 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
16739 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
16740 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
16741 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
16742 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
16743 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
16744 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
16745 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
16746 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
16747 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
16748 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
16749 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
16750 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
16751 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
16752 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
16753 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
16754 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
16755 #define A_MA_TIMEOUT_CFG 0x78cc
16758 #define V_CLR(x) ((x) << S_CLR)
16759 #define F_CLR V_CLR(1U)
16761 #define S_CNT_LOCK 30
16762 #define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
16763 #define F_CNT_LOCK V_CNT_LOCK(1U)
16766 #define V_WRN(x) ((x) << S_WRN)
16767 #define F_WRN V_WRN(1U)
16770 #define V_DIR(x) ((x) << S_DIR)
16771 #define F_DIR V_DIR(1U)
16773 #define S_TO_BUS 22
16774 #define V_TO_BUS(x) ((x) << S_TO_BUS)
16775 #define F_TO_BUS V_TO_BUS(1U)
16777 #define S_CLIENT 16
16778 #define M_CLIENT 0xfU
16779 #define V_CLIENT(x) ((x) << S_CLIENT)
16780 #define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
16783 #define M_DELAY 0xffffU
16784 #define V_DELAY(x) ((x) << S_DELAY)
16785 #define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
16787 #define A_MA_TIMEOUT_CNT 0x78d0
16789 #define S_CNT_VAL 0
16790 #define M_CNT_VAL 0xffffU
16791 #define V_CNT_VAL(x) ((x) << S_CNT_VAL)
16792 #define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
16794 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
16796 #define S_FUTURE_CEXPANSION 29
16797 #define M_FUTURE_CEXPANSION 0x7U
16798 #define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
16799 #define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
16801 #define S_CL12_WR_CMD_TO_EN 28
16802 #define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
16803 #define F_CL12_WR_CMD_TO_EN V_CL12_WR_CMD_TO_EN(1U)
16805 #define S_CL11_WR_CMD_TO_EN 27
16806 #define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
16807 #define F_CL11_WR_CMD_TO_EN V_CL11_WR_CMD_TO_EN(1U)
16809 #define S_CL10_WR_CMD_TO_EN 26
16810 #define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
16811 #define F_CL10_WR_CMD_TO_EN V_CL10_WR_CMD_TO_EN(1U)
16813 #define S_CL9_WR_CMD_TO_EN 25
16814 #define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
16815 #define F_CL9_WR_CMD_TO_EN V_CL9_WR_CMD_TO_EN(1U)
16817 #define S_CL8_WR_CMD_TO_EN 24
16818 #define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
16819 #define F_CL8_WR_CMD_TO_EN V_CL8_WR_CMD_TO_EN(1U)
16821 #define S_CL7_WR_CMD_TO_EN 23
16822 #define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
16823 #define F_CL7_WR_CMD_TO_EN V_CL7_WR_CMD_TO_EN(1U)
16825 #define S_CL6_WR_CMD_TO_EN 22
16826 #define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
16827 #define F_CL6_WR_CMD_TO_EN V_CL6_WR_CMD_TO_EN(1U)
16829 #define S_CL5_WR_CMD_TO_EN 21
16830 #define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
16831 #define F_CL5_WR_CMD_TO_EN V_CL5_WR_CMD_TO_EN(1U)
16833 #define S_CL4_WR_CMD_TO_EN 20
16834 #define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
16835 #define F_CL4_WR_CMD_TO_EN V_CL4_WR_CMD_TO_EN(1U)
16837 #define S_CL3_WR_CMD_TO_EN 19
16838 #define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
16839 #define F_CL3_WR_CMD_TO_EN V_CL3_WR_CMD_TO_EN(1U)
16841 #define S_CL2_WR_CMD_TO_EN 18
16842 #define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
16843 #define F_CL2_WR_CMD_TO_EN V_CL2_WR_CMD_TO_EN(1U)
16845 #define S_CL1_WR_CMD_TO_EN 17
16846 #define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
16847 #define F_CL1_WR_CMD_TO_EN V_CL1_WR_CMD_TO_EN(1U)
16849 #define S_CL0_WR_CMD_TO_EN 16
16850 #define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
16851 #define F_CL0_WR_CMD_TO_EN V_CL0_WR_CMD_TO_EN(1U)
16853 #define S_FUTURE_DEXPANSION 13
16854 #define M_FUTURE_DEXPANSION 0x7U
16855 #define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
16856 #define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
16858 #define S_CL12_WR_DATA_TO_EN 12
16859 #define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
16860 #define F_CL12_WR_DATA_TO_EN V_CL12_WR_DATA_TO_EN(1U)
16862 #define S_CL11_WR_DATA_TO_EN 11
16863 #define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
16864 #define F_CL11_WR_DATA_TO_EN V_CL11_WR_DATA_TO_EN(1U)
16866 #define S_CL10_WR_DATA_TO_EN 10
16867 #define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
16868 #define F_CL10_WR_DATA_TO_EN V_CL10_WR_DATA_TO_EN(1U)
16870 #define S_CL9_WR_DATA_TO_EN 9
16871 #define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
16872 #define F_CL9_WR_DATA_TO_EN V_CL9_WR_DATA_TO_EN(1U)
16874 #define S_CL8_WR_DATA_TO_EN 8
16875 #define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
16876 #define F_CL8_WR_DATA_TO_EN V_CL8_WR_DATA_TO_EN(1U)
16878 #define S_CL7_WR_DATA_TO_EN 7
16879 #define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
16880 #define F_CL7_WR_DATA_TO_EN V_CL7_WR_DATA_TO_EN(1U)
16882 #define S_CL6_WR_DATA_TO_EN 6
16883 #define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
16884 #define F_CL6_WR_DATA_TO_EN V_CL6_WR_DATA_TO_EN(1U)
16886 #define S_CL5_WR_DATA_TO_EN 5
16887 #define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
16888 #define F_CL5_WR_DATA_TO_EN V_CL5_WR_DATA_TO_EN(1U)
16890 #define S_CL4_WR_DATA_TO_EN 4
16891 #define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
16892 #define F_CL4_WR_DATA_TO_EN V_CL4_WR_DATA_TO_EN(1U)
16894 #define S_CL3_WR_DATA_TO_EN 3
16895 #define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
16896 #define F_CL3_WR_DATA_TO_EN V_CL3_WR_DATA_TO_EN(1U)
16898 #define S_CL2_WR_DATA_TO_EN 2
16899 #define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
16900 #define F_CL2_WR_DATA_TO_EN V_CL2_WR_DATA_TO_EN(1U)
16902 #define S_CL1_WR_DATA_TO_EN 1
16903 #define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
16904 #define F_CL1_WR_DATA_TO_EN V_CL1_WR_DATA_TO_EN(1U)
16906 #define S_CL0_WR_DATA_TO_EN 0
16907 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
16908 #define F_CL0_WR_DATA_TO_EN V_CL0_WR_DATA_TO_EN(1U)
16910 #define S_FUTURE_CEXPANSION_WTE 29
16911 #define M_FUTURE_CEXPANSION_WTE 0x7U
16912 #define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE)
16913 #define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE)
16915 #define S_FUTURE_DEXPANSION_WTE 13
16916 #define M_FUTURE_DEXPANSION_WTE 0x7U
16917 #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
16918 #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
16920 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
16922 #define S_CL12_WR_CMD_TO_ERROR 28
16923 #define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
16924 #define F_CL12_WR_CMD_TO_ERROR V_CL12_WR_CMD_TO_ERROR(1U)
16926 #define S_CL11_WR_CMD_TO_ERROR 27
16927 #define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
16928 #define F_CL11_WR_CMD_TO_ERROR V_CL11_WR_CMD_TO_ERROR(1U)
16930 #define S_CL10_WR_CMD_TO_ERROR 26
16931 #define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
16932 #define F_CL10_WR_CMD_TO_ERROR V_CL10_WR_CMD_TO_ERROR(1U)
16934 #define S_CL9_WR_CMD_TO_ERROR 25
16935 #define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
16936 #define F_CL9_WR_CMD_TO_ERROR V_CL9_WR_CMD_TO_ERROR(1U)
16938 #define S_CL8_WR_CMD_TO_ERROR 24
16939 #define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
16940 #define F_CL8_WR_CMD_TO_ERROR V_CL8_WR_CMD_TO_ERROR(1U)
16942 #define S_CL7_WR_CMD_TO_ERROR 23
16943 #define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
16944 #define F_CL7_WR_CMD_TO_ERROR V_CL7_WR_CMD_TO_ERROR(1U)
16946 #define S_CL6_WR_CMD_TO_ERROR 22
16947 #define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
16948 #define F_CL6_WR_CMD_TO_ERROR V_CL6_WR_CMD_TO_ERROR(1U)
16950 #define S_CL5_WR_CMD_TO_ERROR 21
16951 #define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
16952 #define F_CL5_WR_CMD_TO_ERROR V_CL5_WR_CMD_TO_ERROR(1U)
16954 #define S_CL4_WR_CMD_TO_ERROR 20
16955 #define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
16956 #define F_CL4_WR_CMD_TO_ERROR V_CL4_WR_CMD_TO_ERROR(1U)
16958 #define S_CL3_WR_CMD_TO_ERROR 19
16959 #define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
16960 #define F_CL3_WR_CMD_TO_ERROR V_CL3_WR_CMD_TO_ERROR(1U)
16962 #define S_CL2_WR_CMD_TO_ERROR 18
16963 #define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
16964 #define F_CL2_WR_CMD_TO_ERROR V_CL2_WR_CMD_TO_ERROR(1U)
16966 #define S_CL1_WR_CMD_TO_ERROR 17
16967 #define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
16968 #define F_CL1_WR_CMD_TO_ERROR V_CL1_WR_CMD_TO_ERROR(1U)
16970 #define S_CL0_WR_CMD_TO_ERROR 16
16971 #define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
16972 #define F_CL0_WR_CMD_TO_ERROR V_CL0_WR_CMD_TO_ERROR(1U)
16974 #define S_CL12_WR_DATA_TO_ERROR 12
16975 #define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
16976 #define F_CL12_WR_DATA_TO_ERROR V_CL12_WR_DATA_TO_ERROR(1U)
16978 #define S_CL11_WR_DATA_TO_ERROR 11
16979 #define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
16980 #define F_CL11_WR_DATA_TO_ERROR V_CL11_WR_DATA_TO_ERROR(1U)
16982 #define S_CL10_WR_DATA_TO_ERROR 10
16983 #define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
16984 #define F_CL10_WR_DATA_TO_ERROR V_CL10_WR_DATA_TO_ERROR(1U)
16986 #define S_CL9_WR_DATA_TO_ERROR 9
16987 #define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
16988 #define F_CL9_WR_DATA_TO_ERROR V_CL9_WR_DATA_TO_ERROR(1U)
16990 #define S_CL8_WR_DATA_TO_ERROR 8
16991 #define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
16992 #define F_CL8_WR_DATA_TO_ERROR V_CL8_WR_DATA_TO_ERROR(1U)
16994 #define S_CL7_WR_DATA_TO_ERROR 7
16995 #define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
16996 #define F_CL7_WR_DATA_TO_ERROR V_CL7_WR_DATA_TO_ERROR(1U)
16998 #define S_CL6_WR_DATA_TO_ERROR 6
16999 #define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
17000 #define F_CL6_WR_DATA_TO_ERROR V_CL6_WR_DATA_TO_ERROR(1U)
17002 #define S_CL5_WR_DATA_TO_ERROR 5
17003 #define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
17004 #define F_CL5_WR_DATA_TO_ERROR V_CL5_WR_DATA_TO_ERROR(1U)
17006 #define S_CL4_WR_DATA_TO_ERROR 4
17007 #define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
17008 #define F_CL4_WR_DATA_TO_ERROR V_CL4_WR_DATA_TO_ERROR(1U)
17010 #define S_CL3_WR_DATA_TO_ERROR 3
17011 #define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
17012 #define F_CL3_WR_DATA_TO_ERROR V_CL3_WR_DATA_TO_ERROR(1U)
17014 #define S_CL2_WR_DATA_TO_ERROR 2
17015 #define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
17016 #define F_CL2_WR_DATA_TO_ERROR V_CL2_WR_DATA_TO_ERROR(1U)
17018 #define S_CL1_WR_DATA_TO_ERROR 1
17019 #define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
17020 #define F_CL1_WR_DATA_TO_ERROR V_CL1_WR_DATA_TO_ERROR(1U)
17022 #define S_CL0_WR_DATA_TO_ERROR 0
17023 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
17024 #define F_CL0_WR_DATA_TO_ERROR V_CL0_WR_DATA_TO_ERROR(1U)
17026 #define S_FUTURE_CEXPANSION_WTS 29
17027 #define M_FUTURE_CEXPANSION_WTS 0x7U
17028 #define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS)
17029 #define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS)
17031 #define S_FUTURE_DEXPANSION_WTS 13
17032 #define M_FUTURE_DEXPANSION_WTS 0x7U
17033 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
17034 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
17036 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
17038 #define S_CL12_RD_CMD_TO_EN 28
17039 #define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
17040 #define F_CL12_RD_CMD_TO_EN V_CL12_RD_CMD_TO_EN(1U)
17042 #define S_CL11_RD_CMD_TO_EN 27
17043 #define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
17044 #define F_CL11_RD_CMD_TO_EN V_CL11_RD_CMD_TO_EN(1U)
17046 #define S_CL10_RD_CMD_TO_EN 26
17047 #define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
17048 #define F_CL10_RD_CMD_TO_EN V_CL10_RD_CMD_TO_EN(1U)
17050 #define S_CL9_RD_CMD_TO_EN 25
17051 #define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
17052 #define F_CL9_RD_CMD_TO_EN V_CL9_RD_CMD_TO_EN(1U)
17054 #define S_CL8_RD_CMD_TO_EN 24
17055 #define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
17056 #define F_CL8_RD_CMD_TO_EN V_CL8_RD_CMD_TO_EN(1U)
17058 #define S_CL7_RD_CMD_TO_EN 23
17059 #define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
17060 #define F_CL7_RD_CMD_TO_EN V_CL7_RD_CMD_TO_EN(1U)
17062 #define S_CL6_RD_CMD_TO_EN 22
17063 #define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
17064 #define F_CL6_RD_CMD_TO_EN V_CL6_RD_CMD_TO_EN(1U)
17066 #define S_CL5_RD_CMD_TO_EN 21
17067 #define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
17068 #define F_CL5_RD_CMD_TO_EN V_CL5_RD_CMD_TO_EN(1U)
17070 #define S_CL4_RD_CMD_TO_EN 20
17071 #define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
17072 #define F_CL4_RD_CMD_TO_EN V_CL4_RD_CMD_TO_EN(1U)
17074 #define S_CL3_RD_CMD_TO_EN 19
17075 #define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
17076 #define F_CL3_RD_CMD_TO_EN V_CL3_RD_CMD_TO_EN(1U)
17078 #define S_CL2_RD_CMD_TO_EN 18
17079 #define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
17080 #define F_CL2_RD_CMD_TO_EN V_CL2_RD_CMD_TO_EN(1U)
17082 #define S_CL1_RD_CMD_TO_EN 17
17083 #define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
17084 #define F_CL1_RD_CMD_TO_EN V_CL1_RD_CMD_TO_EN(1U)
17086 #define S_CL0_RD_CMD_TO_EN 16
17087 #define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
17088 #define F_CL0_RD_CMD_TO_EN V_CL0_RD_CMD_TO_EN(1U)
17090 #define S_CL12_RD_DATA_TO_EN 12
17091 #define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
17092 #define F_CL12_RD_DATA_TO_EN V_CL12_RD_DATA_TO_EN(1U)
17094 #define S_CL11_RD_DATA_TO_EN 11
17095 #define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
17096 #define F_CL11_RD_DATA_TO_EN V_CL11_RD_DATA_TO_EN(1U)
17098 #define S_CL10_RD_DATA_TO_EN 10
17099 #define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
17100 #define F_CL10_RD_DATA_TO_EN V_CL10_RD_DATA_TO_EN(1U)
17102 #define S_CL9_RD_DATA_TO_EN 9
17103 #define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
17104 #define F_CL9_RD_DATA_TO_EN V_CL9_RD_DATA_TO_EN(1U)
17106 #define S_CL8_RD_DATA_TO_EN 8
17107 #define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
17108 #define F_CL8_RD_DATA_TO_EN V_CL8_RD_DATA_TO_EN(1U)
17110 #define S_CL7_RD_DATA_TO_EN 7
17111 #define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
17112 #define F_CL7_RD_DATA_TO_EN V_CL7_RD_DATA_TO_EN(1U)
17114 #define S_CL6_RD_DATA_TO_EN 6
17115 #define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
17116 #define F_CL6_RD_DATA_TO_EN V_CL6_RD_DATA_TO_EN(1U)
17118 #define S_CL5_RD_DATA_TO_EN 5
17119 #define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
17120 #define F_CL5_RD_DATA_TO_EN V_CL5_RD_DATA_TO_EN(1U)
17122 #define S_CL4_RD_DATA_TO_EN 4
17123 #define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
17124 #define F_CL4_RD_DATA_TO_EN V_CL4_RD_DATA_TO_EN(1U)
17126 #define S_CL3_RD_DATA_TO_EN 3
17127 #define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
17128 #define F_CL3_RD_DATA_TO_EN V_CL3_RD_DATA_TO_EN(1U)
17130 #define S_CL2_RD_DATA_TO_EN 2
17131 #define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
17132 #define F_CL2_RD_DATA_TO_EN V_CL2_RD_DATA_TO_EN(1U)
17134 #define S_CL1_RD_DATA_TO_EN 1
17135 #define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
17136 #define F_CL1_RD_DATA_TO_EN V_CL1_RD_DATA_TO_EN(1U)
17138 #define S_CL0_RD_DATA_TO_EN 0
17139 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
17140 #define F_CL0_RD_DATA_TO_EN V_CL0_RD_DATA_TO_EN(1U)
17142 #define S_FUTURE_CEXPANSION_RTE 29
17143 #define M_FUTURE_CEXPANSION_RTE 0x7U
17144 #define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE)
17145 #define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE)
17147 #define S_FUTURE_DEXPANSION_RTE 13
17148 #define M_FUTURE_DEXPANSION_RTE 0x7U
17149 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
17150 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
17152 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
17154 #define S_CL12_RD_CMD_TO_ERROR 28
17155 #define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
17156 #define F_CL12_RD_CMD_TO_ERROR V_CL12_RD_CMD_TO_ERROR(1U)
17158 #define S_CL11_RD_CMD_TO_ERROR 27
17159 #define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
17160 #define F_CL11_RD_CMD_TO_ERROR V_CL11_RD_CMD_TO_ERROR(1U)
17162 #define S_CL10_RD_CMD_TO_ERROR 26
17163 #define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
17164 #define F_CL10_RD_CMD_TO_ERROR V_CL10_RD_CMD_TO_ERROR(1U)
17166 #define S_CL9_RD_CMD_TO_ERROR 25
17167 #define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
17168 #define F_CL9_RD_CMD_TO_ERROR V_CL9_RD_CMD_TO_ERROR(1U)
17170 #define S_CL8_RD_CMD_TO_ERROR 24
17171 #define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
17172 #define F_CL8_RD_CMD_TO_ERROR V_CL8_RD_CMD_TO_ERROR(1U)
17174 #define S_CL7_RD_CMD_TO_ERROR 23
17175 #define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
17176 #define F_CL7_RD_CMD_TO_ERROR V_CL7_RD_CMD_TO_ERROR(1U)
17178 #define S_CL6_RD_CMD_TO_ERROR 22
17179 #define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
17180 #define F_CL6_RD_CMD_TO_ERROR V_CL6_RD_CMD_TO_ERROR(1U)
17182 #define S_CL5_RD_CMD_TO_ERROR 21
17183 #define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
17184 #define F_CL5_RD_CMD_TO_ERROR V_CL5_RD_CMD_TO_ERROR(1U)
17186 #define S_CL4_RD_CMD_TO_ERROR 20
17187 #define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
17188 #define F_CL4_RD_CMD_TO_ERROR V_CL4_RD_CMD_TO_ERROR(1U)
17190 #define S_CL3_RD_CMD_TO_ERROR 19
17191 #define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
17192 #define F_CL3_RD_CMD_TO_ERROR V_CL3_RD_CMD_TO_ERROR(1U)
17194 #define S_CL2_RD_CMD_TO_ERROR 18
17195 #define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
17196 #define F_CL2_RD_CMD_TO_ERROR V_CL2_RD_CMD_TO_ERROR(1U)
17198 #define S_CL1_RD_CMD_TO_ERROR 17
17199 #define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
17200 #define F_CL1_RD_CMD_TO_ERROR V_CL1_RD_CMD_TO_ERROR(1U)
17202 #define S_CL0_RD_CMD_TO_ERROR 16
17203 #define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
17204 #define F_CL0_RD_CMD_TO_ERROR V_CL0_RD_CMD_TO_ERROR(1U)
17206 #define S_CL12_RD_DATA_TO_ERROR 12
17207 #define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
17208 #define F_CL12_RD_DATA_TO_ERROR V_CL12_RD_DATA_TO_ERROR(1U)
17210 #define S_CL11_RD_DATA_TO_ERROR 11
17211 #define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
17212 #define F_CL11_RD_DATA_TO_ERROR V_CL11_RD_DATA_TO_ERROR(1U)
17214 #define S_CL10_RD_DATA_TO_ERROR 10
17215 #define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
17216 #define F_CL10_RD_DATA_TO_ERROR V_CL10_RD_DATA_TO_ERROR(1U)
17218 #define S_CL9_RD_DATA_TO_ERROR 9
17219 #define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
17220 #define F_CL9_RD_DATA_TO_ERROR V_CL9_RD_DATA_TO_ERROR(1U)
17222 #define S_CL8_RD_DATA_TO_ERROR 8
17223 #define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
17224 #define F_CL8_RD_DATA_TO_ERROR V_CL8_RD_DATA_TO_ERROR(1U)
17226 #define S_CL7_RD_DATA_TO_ERROR 7
17227 #define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
17228 #define F_CL7_RD_DATA_TO_ERROR V_CL7_RD_DATA_TO_ERROR(1U)
17230 #define S_CL6_RD_DATA_TO_ERROR 6
17231 #define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
17232 #define F_CL6_RD_DATA_TO_ERROR V_CL6_RD_DATA_TO_ERROR(1U)
17234 #define S_CL5_RD_DATA_TO_ERROR 5
17235 #define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
17236 #define F_CL5_RD_DATA_TO_ERROR V_CL5_RD_DATA_TO_ERROR(1U)
17238 #define S_CL4_RD_DATA_TO_ERROR 4
17239 #define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
17240 #define F_CL4_RD_DATA_TO_ERROR V_CL4_RD_DATA_TO_ERROR(1U)
17242 #define S_CL3_RD_DATA_TO_ERROR 3
17243 #define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
17244 #define F_CL3_RD_DATA_TO_ERROR V_CL3_RD_DATA_TO_ERROR(1U)
17246 #define S_CL2_RD_DATA_TO_ERROR 2
17247 #define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
17248 #define F_CL2_RD_DATA_TO_ERROR V_CL2_RD_DATA_TO_ERROR(1U)
17250 #define S_CL1_RD_DATA_TO_ERROR 1
17251 #define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
17252 #define F_CL1_RD_DATA_TO_ERROR V_CL1_RD_DATA_TO_ERROR(1U)
17254 #define S_CL0_RD_DATA_TO_ERROR 0
17255 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
17256 #define F_CL0_RD_DATA_TO_ERROR V_CL0_RD_DATA_TO_ERROR(1U)
17258 #define S_FUTURE_CEXPANSION_RTS 29
17259 #define M_FUTURE_CEXPANSION_RTS 0x7U
17260 #define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS)
17261 #define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS)
17263 #define S_FUTURE_DEXPANSION_RTS 13
17264 #define M_FUTURE_DEXPANSION_RTS 0x7U
17265 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
17266 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
17268 #define A_MA_BKP_CNT_SEL 0x78e4
17270 #define S_BKP_CNT_TYPE 30
17271 #define M_BKP_CNT_TYPE 0x3U
17272 #define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
17273 #define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
17275 #define S_BKP_CLIENT 24
17276 #define M_BKP_CLIENT 0xfU
17277 #define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
17278 #define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
17280 #define A_MA_BKP_CNT 0x78e8
17281 #define A_MA_WRT_ARB 0x78ec
17283 #define S_WRT_EN 31
17284 #define V_WRT_EN(x) ((x) << S_WRT_EN)
17285 #define F_WRT_EN V_WRT_EN(1U)
17287 #define S_WR_TIM 16
17288 #define M_WR_TIM 0xffU
17289 #define V_WR_TIM(x) ((x) << S_WR_TIM)
17290 #define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
17293 #define M_RD_WIN 0xffU
17294 #define V_RD_WIN(x) ((x) << S_RD_WIN)
17295 #define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
17298 #define M_WR_WIN 0xffU
17299 #define V_WR_WIN(x) ((x) << S_WR_WIN)
17300 #define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
17302 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
17304 #define S_T5_FUTURE_DEXPANSION 13
17305 #define M_T5_FUTURE_DEXPANSION 0x7ffffU
17306 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
17307 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
17309 #define S_CL12_IF_PAR_EN 12
17310 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
17311 #define F_CL12_IF_PAR_EN V_CL12_IF_PAR_EN(1U)
17313 #define S_CL11_IF_PAR_EN 11
17314 #define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
17315 #define F_CL11_IF_PAR_EN V_CL11_IF_PAR_EN(1U)
17317 #define S_CL10_IF_PAR_EN 10
17318 #define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
17319 #define F_CL10_IF_PAR_EN V_CL10_IF_PAR_EN(1U)
17321 #define S_CL9_IF_PAR_EN 9
17322 #define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
17323 #define F_CL9_IF_PAR_EN V_CL9_IF_PAR_EN(1U)
17325 #define S_CL8_IF_PAR_EN 8
17326 #define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
17327 #define F_CL8_IF_PAR_EN V_CL8_IF_PAR_EN(1U)
17329 #define S_CL7_IF_PAR_EN 7
17330 #define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
17331 #define F_CL7_IF_PAR_EN V_CL7_IF_PAR_EN(1U)
17333 #define S_CL6_IF_PAR_EN 6
17334 #define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
17335 #define F_CL6_IF_PAR_EN V_CL6_IF_PAR_EN(1U)
17337 #define S_CL5_IF_PAR_EN 5
17338 #define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
17339 #define F_CL5_IF_PAR_EN V_CL5_IF_PAR_EN(1U)
17341 #define S_CL4_IF_PAR_EN 4
17342 #define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
17343 #define F_CL4_IF_PAR_EN V_CL4_IF_PAR_EN(1U)
17345 #define S_CL3_IF_PAR_EN 3
17346 #define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
17347 #define F_CL3_IF_PAR_EN V_CL3_IF_PAR_EN(1U)
17349 #define S_CL2_IF_PAR_EN 2
17350 #define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
17351 #define F_CL2_IF_PAR_EN V_CL2_IF_PAR_EN(1U)
17353 #define S_CL1_IF_PAR_EN 1
17354 #define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
17355 #define F_CL1_IF_PAR_EN V_CL1_IF_PAR_EN(1U)
17357 #define S_CL0_IF_PAR_EN 0
17358 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
17359 #define F_CL0_IF_PAR_EN V_CL0_IF_PAR_EN(1U)
17361 #define S_FUTURE_DEXPANSION_IPE 13
17362 #define M_FUTURE_DEXPANSION_IPE 0x7ffffU
17363 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
17364 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
17366 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
17368 #define S_T5_FUTURE_DEXPANSION 13
17369 #define M_T5_FUTURE_DEXPANSION 0x7ffffU
17370 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
17371 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
17373 #define S_CL12_IF_PAR_ERROR 12
17374 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
17375 #define F_CL12_IF_PAR_ERROR V_CL12_IF_PAR_ERROR(1U)
17377 #define S_CL11_IF_PAR_ERROR 11
17378 #define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
17379 #define F_CL11_IF_PAR_ERROR V_CL11_IF_PAR_ERROR(1U)
17381 #define S_CL10_IF_PAR_ERROR 10
17382 #define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
17383 #define F_CL10_IF_PAR_ERROR V_CL10_IF_PAR_ERROR(1U)
17385 #define S_CL9_IF_PAR_ERROR 9
17386 #define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
17387 #define F_CL9_IF_PAR_ERROR V_CL9_IF_PAR_ERROR(1U)
17389 #define S_CL8_IF_PAR_ERROR 8
17390 #define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
17391 #define F_CL8_IF_PAR_ERROR V_CL8_IF_PAR_ERROR(1U)
17393 #define S_CL7_IF_PAR_ERROR 7
17394 #define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
17395 #define F_CL7_IF_PAR_ERROR V_CL7_IF_PAR_ERROR(1U)
17397 #define S_CL6_IF_PAR_ERROR 6
17398 #define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
17399 #define F_CL6_IF_PAR_ERROR V_CL6_IF_PAR_ERROR(1U)
17401 #define S_CL5_IF_PAR_ERROR 5
17402 #define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
17403 #define F_CL5_IF_PAR_ERROR V_CL5_IF_PAR_ERROR(1U)
17405 #define S_CL4_IF_PAR_ERROR 4
17406 #define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
17407 #define F_CL4_IF_PAR_ERROR V_CL4_IF_PAR_ERROR(1U)
17409 #define S_CL3_IF_PAR_ERROR 3
17410 #define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
17411 #define F_CL3_IF_PAR_ERROR V_CL3_IF_PAR_ERROR(1U)
17413 #define S_CL2_IF_PAR_ERROR 2
17414 #define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
17415 #define F_CL2_IF_PAR_ERROR V_CL2_IF_PAR_ERROR(1U)
17417 #define S_CL1_IF_PAR_ERROR 1
17418 #define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
17419 #define F_CL1_IF_PAR_ERROR V_CL1_IF_PAR_ERROR(1U)
17421 #define S_CL0_IF_PAR_ERROR 0
17422 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
17423 #define F_CL0_IF_PAR_ERROR V_CL0_IF_PAR_ERROR(1U)
17425 #define S_FUTURE_DEXPANSION_IPS 13
17426 #define M_FUTURE_DEXPANSION_IPS 0x7ffffU
17427 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
17428 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
17430 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
17432 #define S_DEBUG_OR 15
17433 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
17434 #define F_DEBUG_OR V_DEBUG_OR(1U)
17436 #define S_DEBUG_HI 14
17437 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
17438 #define F_DEBUG_HI V_DEBUG_HI(1U)
17440 #define S_DEBUG_RPT 13
17441 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
17442 #define F_DEBUG_RPT V_DEBUG_RPT(1U)
17444 #define S_DEBUGPAGE 10
17445 #define M_DEBUGPAGE 0x7U
17446 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
17447 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
17449 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
17450 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
17452 #define S_CMDVLD0 31
17453 #define V_CMDVLD0(x) ((x) << S_CMDVLD0)
17454 #define F_CMDVLD0 V_CMDVLD0(1U)
17456 #define S_CMDRDY0 30
17457 #define V_CMDRDY0(x) ((x) << S_CMDRDY0)
17458 #define F_CMDRDY0 V_CMDRDY0(1U)
17460 #define S_CMDTYPE0 29
17461 #define V_CMDTYPE0(x) ((x) << S_CMDTYPE0)
17462 #define F_CMDTYPE0 V_CMDTYPE0(1U)
17464 #define S_CMDLEN0 21
17465 #define M_CMDLEN0 0xffU
17466 #define V_CMDLEN0(x) ((x) << S_CMDLEN0)
17467 #define G_CMDLEN0(x) (((x) >> S_CMDLEN0) & M_CMDLEN0)
17469 #define S_CMDADDR0 8
17470 #define M_CMDADDR0 0x1fffU
17471 #define V_CMDADDR0(x) ((x) << S_CMDADDR0)
17472 #define G_CMDADDR0(x) (((x) >> S_CMDADDR0) & M_CMDADDR0)
17474 #define S_WRDATAVLD0 7
17475 #define V_WRDATAVLD0(x) ((x) << S_WRDATAVLD0)
17476 #define F_WRDATAVLD0 V_WRDATAVLD0(1U)
17478 #define S_WRDATARDY0 6
17479 #define V_WRDATARDY0(x) ((x) << S_WRDATARDY0)
17480 #define F_WRDATARDY0 V_WRDATARDY0(1U)
17482 #define S_RDDATARDY0 5
17483 #define V_RDDATARDY0(x) ((x) << S_RDDATARDY0)
17484 #define F_RDDATARDY0 V_RDDATARDY0(1U)
17486 #define S_RDDATAVLD0 4
17487 #define V_RDDATAVLD0(x) ((x) << S_RDDATAVLD0)
17488 #define F_RDDATAVLD0 V_RDDATAVLD0(1U)
17490 #define S_RDDATA0 0
17491 #define M_RDDATA0 0xfU
17492 #define V_RDDATA0(x) ((x) << S_RDDATA0)
17493 #define G_RDDATA0(x) (((x) >> S_RDDATA0) & M_RDDATA0)
17495 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
17497 #define S_CMDVLD1 31
17498 #define V_CMDVLD1(x) ((x) << S_CMDVLD1)
17499 #define F_CMDVLD1 V_CMDVLD1(1U)
17501 #define S_CMDRDY1 30
17502 #define V_CMDRDY1(x) ((x) << S_CMDRDY1)
17503 #define F_CMDRDY1 V_CMDRDY1(1U)
17505 #define S_CMDTYPE1 29
17506 #define V_CMDTYPE1(x) ((x) << S_CMDTYPE1)
17507 #define F_CMDTYPE1 V_CMDTYPE1(1U)
17509 #define S_CMDLEN1 21
17510 #define M_CMDLEN1 0xffU
17511 #define V_CMDLEN1(x) ((x) << S_CMDLEN1)
17512 #define G_CMDLEN1(x) (((x) >> S_CMDLEN1) & M_CMDLEN1)
17514 #define S_CMDADDR1 8
17515 #define M_CMDADDR1 0x1fffU
17516 #define V_CMDADDR1(x) ((x) << S_CMDADDR1)
17517 #define G_CMDADDR1(x) (((x) >> S_CMDADDR1) & M_CMDADDR1)
17519 #define S_WRDATAVLD1 7
17520 #define V_WRDATAVLD1(x) ((x) << S_WRDATAVLD1)
17521 #define F_WRDATAVLD1 V_WRDATAVLD1(1U)
17523 #define S_WRDATARDY1 6
17524 #define V_WRDATARDY1(x) ((x) << S_WRDATARDY1)
17525 #define F_WRDATARDY1 V_WRDATARDY1(1U)
17527 #define S_RDDATARDY1 5
17528 #define V_RDDATARDY1(x) ((x) << S_RDDATARDY1)
17529 #define F_RDDATARDY1 V_RDDATARDY1(1U)
17531 #define S_RDDATAVLD1 4
17532 #define V_RDDATAVLD1(x) ((x) << S_RDDATAVLD1)
17533 #define F_RDDATAVLD1 V_RDDATAVLD1(1U)
17535 #define S_RDDATA1 0
17536 #define M_RDDATA1 0xfU
17537 #define V_RDDATA1(x) ((x) << S_RDDATA1)
17538 #define G_RDDATA1(x) (((x) >> S_RDDATA1) & M_RDDATA1)
17540 #define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
17542 #define S_CMDVLD2 31
17543 #define V_CMDVLD2(x) ((x) << S_CMDVLD2)
17544 #define F_CMDVLD2 V_CMDVLD2(1U)
17546 #define S_CMDRDY2 30
17547 #define V_CMDRDY2(x) ((x) << S_CMDRDY2)
17548 #define F_CMDRDY2 V_CMDRDY2(1U)
17550 #define S_CMDTYPE2 29
17551 #define V_CMDTYPE2(x) ((x) << S_CMDTYPE2)
17552 #define F_CMDTYPE2 V_CMDTYPE2(1U)
17554 #define S_CMDLEN2 21
17555 #define M_CMDLEN2 0xffU
17556 #define V_CMDLEN2(x) ((x) << S_CMDLEN2)
17557 #define G_CMDLEN2(x) (((x) >> S_CMDLEN2) & M_CMDLEN2)
17559 #define S_CMDADDR2 8
17560 #define M_CMDADDR2 0x1fffU
17561 #define V_CMDADDR2(x) ((x) << S_CMDADDR2)
17562 #define G_CMDADDR2(x) (((x) >> S_CMDADDR2) & M_CMDADDR2)
17564 #define S_WRDATAVLD2 7
17565 #define V_WRDATAVLD2(x) ((x) << S_WRDATAVLD2)
17566 #define F_WRDATAVLD2 V_WRDATAVLD2(1U)
17568 #define S_WRDATARDY2 6
17569 #define V_WRDATARDY2(x) ((x) << S_WRDATARDY2)
17570 #define F_WRDATARDY2 V_WRDATARDY2(1U)
17572 #define S_RDDATARDY2 5
17573 #define V_RDDATARDY2(x) ((x) << S_RDDATARDY2)
17574 #define F_RDDATARDY2 V_RDDATARDY2(1U)
17576 #define S_RDDATAVLD2 4
17577 #define V_RDDATAVLD2(x) ((x) << S_RDDATAVLD2)
17578 #define F_RDDATAVLD2 V_RDDATAVLD2(1U)
17580 #define S_RDDATA2 0
17581 #define M_RDDATA2 0xfU
17582 #define V_RDDATA2(x) ((x) << S_RDDATA2)
17583 #define G_RDDATA2(x) (((x) >> S_RDDATA2) & M_RDDATA2)
17585 #define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
17587 #define S_CMDVLD3 31
17588 #define V_CMDVLD3(x) ((x) << S_CMDVLD3)
17589 #define F_CMDVLD3 V_CMDVLD3(1U)
17591 #define S_CMDRDY3 30
17592 #define V_CMDRDY3(x) ((x) << S_CMDRDY3)
17593 #define F_CMDRDY3 V_CMDRDY3(1U)
17595 #define S_CMDTYPE3 29
17596 #define V_CMDTYPE3(x) ((x) << S_CMDTYPE3)
17597 #define F_CMDTYPE3 V_CMDTYPE3(1U)
17599 #define S_CMDLEN3 21
17600 #define M_CMDLEN3 0xffU
17601 #define V_CMDLEN3(x) ((x) << S_CMDLEN3)
17602 #define G_CMDLEN3(x) (((x) >> S_CMDLEN3) & M_CMDLEN3)
17604 #define S_CMDADDR3 8
17605 #define M_CMDADDR3 0x1fffU
17606 #define V_CMDADDR3(x) ((x) << S_CMDADDR3)
17607 #define G_CMDADDR3(x) (((x) >> S_CMDADDR3) & M_CMDADDR3)
17609 #define S_WRDATAVLD3 7
17610 #define V_WRDATAVLD3(x) ((x) << S_WRDATAVLD3)
17611 #define F_WRDATAVLD3 V_WRDATAVLD3(1U)
17613 #define S_WRDATARDY3 6
17614 #define V_WRDATARDY3(x) ((x) << S_WRDATARDY3)
17615 #define F_WRDATARDY3 V_WRDATARDY3(1U)
17617 #define S_RDDATARDY3 5
17618 #define V_RDDATARDY3(x) ((x) << S_RDDATARDY3)
17619 #define F_RDDATARDY3 V_RDDATARDY3(1U)
17621 #define S_RDDATAVLD3 4
17622 #define V_RDDATAVLD3(x) ((x) << S_RDDATAVLD3)
17623 #define F_RDDATAVLD3 V_RDDATAVLD3(1U)
17625 #define S_RDDATA3 0
17626 #define M_RDDATA3 0xfU
17627 #define V_RDDATA3(x) ((x) << S_RDDATA3)
17628 #define G_RDDATA3(x) (((x) >> S_RDDATA3) & M_RDDATA3)
17630 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
17632 #define S_CMDVLD4 31
17633 #define V_CMDVLD4(x) ((x) << S_CMDVLD4)
17634 #define F_CMDVLD4 V_CMDVLD4(1U)
17636 #define S_CMDRDY4 30
17637 #define V_CMDRDY4(x) ((x) << S_CMDRDY4)
17638 #define F_CMDRDY4 V_CMDRDY4(1U)
17640 #define S_CMDTYPE4 29
17641 #define V_CMDTYPE4(x) ((x) << S_CMDTYPE4)
17642 #define F_CMDTYPE4 V_CMDTYPE4(1U)
17644 #define S_CMDLEN4 21
17645 #define M_CMDLEN4 0xffU
17646 #define V_CMDLEN4(x) ((x) << S_CMDLEN4)
17647 #define G_CMDLEN4(x) (((x) >> S_CMDLEN4) & M_CMDLEN4)
17649 #define S_CMDADDR4 8
17650 #define M_CMDADDR4 0x1fffU
17651 #define V_CMDADDR4(x) ((x) << S_CMDADDR4)
17652 #define G_CMDADDR4(x) (((x) >> S_CMDADDR4) & M_CMDADDR4)
17654 #define S_WRDATAVLD4 7
17655 #define V_WRDATAVLD4(x) ((x) << S_WRDATAVLD4)
17656 #define F_WRDATAVLD4 V_WRDATAVLD4(1U)
17658 #define S_WRDATARDY4 6
17659 #define V_WRDATARDY4(x) ((x) << S_WRDATARDY4)
17660 #define F_WRDATARDY4 V_WRDATARDY4(1U)
17662 #define S_RDDATARDY4 5
17663 #define V_RDDATARDY4(x) ((x) << S_RDDATARDY4)
17664 #define F_RDDATARDY4 V_RDDATARDY4(1U)
17666 #define S_RDDATAVLD4 4
17667 #define V_RDDATAVLD4(x) ((x) << S_RDDATAVLD4)
17668 #define F_RDDATAVLD4 V_RDDATAVLD4(1U)
17670 #define S_RDDATA4 0
17671 #define M_RDDATA4 0xfU
17672 #define V_RDDATA4(x) ((x) << S_RDDATA4)
17673 #define G_RDDATA4(x) (((x) >> S_RDDATA4) & M_RDDATA4)
17675 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
17677 #define S_CMDVLD5 31
17678 #define V_CMDVLD5(x) ((x) << S_CMDVLD5)
17679 #define F_CMDVLD5 V_CMDVLD5(1U)
17681 #define S_CMDRDY5 30
17682 #define V_CMDRDY5(x) ((x) << S_CMDRDY5)
17683 #define F_CMDRDY5 V_CMDRDY5(1U)
17685 #define S_CMDTYPE5 29
17686 #define V_CMDTYPE5(x) ((x) << S_CMDTYPE5)
17687 #define F_CMDTYPE5 V_CMDTYPE5(1U)
17689 #define S_CMDLEN5 21
17690 #define M_CMDLEN5 0xffU
17691 #define V_CMDLEN5(x) ((x) << S_CMDLEN5)
17692 #define G_CMDLEN5(x) (((x) >> S_CMDLEN5) & M_CMDLEN5)
17694 #define S_CMDADDR5 8
17695 #define M_CMDADDR5 0x1fffU
17696 #define V_CMDADDR5(x) ((x) << S_CMDADDR5)
17697 #define G_CMDADDR5(x) (((x) >> S_CMDADDR5) & M_CMDADDR5)
17699 #define S_WRDATAVLD5 7
17700 #define V_WRDATAVLD5(x) ((x) << S_WRDATAVLD5)
17701 #define F_WRDATAVLD5 V_WRDATAVLD5(1U)
17703 #define S_WRDATARDY5 6
17704 #define V_WRDATARDY5(x) ((x) << S_WRDATARDY5)
17705 #define F_WRDATARDY5 V_WRDATARDY5(1U)
17707 #define S_RDDATARDY5 5
17708 #define V_RDDATARDY5(x) ((x) << S_RDDATARDY5)
17709 #define F_RDDATARDY5 V_RDDATARDY5(1U)
17711 #define S_RDDATAVLD5 4
17712 #define V_RDDATAVLD5(x) ((x) << S_RDDATAVLD5)
17713 #define F_RDDATAVLD5 V_RDDATAVLD5(1U)
17715 #define S_RDDATA5 0
17716 #define M_RDDATA5 0xfU
17717 #define V_RDDATA5(x) ((x) << S_RDDATA5)
17718 #define G_RDDATA5(x) (((x) >> S_RDDATA5) & M_RDDATA5)
17720 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
17722 #define S_CMDVLD6 31
17723 #define V_CMDVLD6(x) ((x) << S_CMDVLD6)
17724 #define F_CMDVLD6 V_CMDVLD6(1U)
17726 #define S_CMDRDY6 30
17727 #define V_CMDRDY6(x) ((x) << S_CMDRDY6)
17728 #define F_CMDRDY6 V_CMDRDY6(1U)
17730 #define S_CMDTYPE6 29
17731 #define V_CMDTYPE6(x) ((x) << S_CMDTYPE6)
17732 #define F_CMDTYPE6 V_CMDTYPE6(1U)
17734 #define S_CMDLEN6 21
17735 #define M_CMDLEN6 0xffU
17736 #define V_CMDLEN6(x) ((x) << S_CMDLEN6)
17737 #define G_CMDLEN6(x) (((x) >> S_CMDLEN6) & M_CMDLEN6)
17739 #define S_CMDADDR6 8
17740 #define M_CMDADDR6 0x1fffU
17741 #define V_CMDADDR6(x) ((x) << S_CMDADDR6)
17742 #define G_CMDADDR6(x) (((x) >> S_CMDADDR6) & M_CMDADDR6)
17744 #define S_WRDATAVLD6 7
17745 #define V_WRDATAVLD6(x) ((x) << S_WRDATAVLD6)
17746 #define F_WRDATAVLD6 V_WRDATAVLD6(1U)
17748 #define S_WRDATARDY6 6
17749 #define V_WRDATARDY6(x) ((x) << S_WRDATARDY6)
17750 #define F_WRDATARDY6 V_WRDATARDY6(1U)
17752 #define S_RDDATARDY6 5
17753 #define V_RDDATARDY6(x) ((x) << S_RDDATARDY6)
17754 #define F_RDDATARDY6 V_RDDATARDY6(1U)
17756 #define S_RDDATAVLD6 4
17757 #define V_RDDATAVLD6(x) ((x) << S_RDDATAVLD6)
17758 #define F_RDDATAVLD6 V_RDDATAVLD6(1U)
17760 #define S_RDDATA6 0
17761 #define M_RDDATA6 0xfU
17762 #define V_RDDATA6(x) ((x) << S_RDDATA6)
17763 #define G_RDDATA6(x) (((x) >> S_RDDATA6) & M_RDDATA6)
17765 #define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
17767 #define S_CMDVLD7 31
17768 #define V_CMDVLD7(x) ((x) << S_CMDVLD7)
17769 #define F_CMDVLD7 V_CMDVLD7(1U)
17771 #define S_CMDRDY7 30
17772 #define V_CMDRDY7(x) ((x) << S_CMDRDY7)
17773 #define F_CMDRDY7 V_CMDRDY7(1U)
17775 #define S_CMDTYPE7 29
17776 #define V_CMDTYPE7(x) ((x) << S_CMDTYPE7)
17777 #define F_CMDTYPE7 V_CMDTYPE7(1U)
17779 #define S_CMDLEN7 21
17780 #define M_CMDLEN7 0xffU
17781 #define V_CMDLEN7(x) ((x) << S_CMDLEN7)
17782 #define G_CMDLEN7(x) (((x) >> S_CMDLEN7) & M_CMDLEN7)
17784 #define S_CMDADDR7 8
17785 #define M_CMDADDR7 0x1fffU
17786 #define V_CMDADDR7(x) ((x) << S_CMDADDR7)
17787 #define G_CMDADDR7(x) (((x) >> S_CMDADDR7) & M_CMDADDR7)
17789 #define S_WRDATAVLD7 7
17790 #define V_WRDATAVLD7(x) ((x) << S_WRDATAVLD7)
17791 #define F_WRDATAVLD7 V_WRDATAVLD7(1U)
17793 #define S_WRDATARDY7 6
17794 #define V_WRDATARDY7(x) ((x) << S_WRDATARDY7)
17795 #define F_WRDATARDY7 V_WRDATARDY7(1U)
17797 #define S_RDDATARDY7 5
17798 #define V_RDDATARDY7(x) ((x) << S_RDDATARDY7)
17799 #define F_RDDATARDY7 V_RDDATARDY7(1U)
17801 #define S_RDDATAVLD7 4
17802 #define V_RDDATAVLD7(x) ((x) << S_RDDATAVLD7)
17803 #define F_RDDATAVLD7 V_RDDATAVLD7(1U)
17805 #define S_RDDATA7 0
17806 #define M_RDDATA7 0xfU
17807 #define V_RDDATA7(x) ((x) << S_RDDATA7)
17808 #define G_RDDATA7(x) (((x) >> S_RDDATA7) & M_RDDATA7)
17810 #define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
17812 #define S_CMDVLD8 31
17813 #define V_CMDVLD8(x) ((x) << S_CMDVLD8)
17814 #define F_CMDVLD8 V_CMDVLD8(1U)
17816 #define S_CMDRDY8 30
17817 #define V_CMDRDY8(x) ((x) << S_CMDRDY8)
17818 #define F_CMDRDY8 V_CMDRDY8(1U)
17820 #define S_CMDTYPE8 29
17821 #define V_CMDTYPE8(x) ((x) << S_CMDTYPE8)
17822 #define F_CMDTYPE8 V_CMDTYPE8(1U)
17824 #define S_CMDLEN8 21
17825 #define M_CMDLEN8 0xffU
17826 #define V_CMDLEN8(x) ((x) << S_CMDLEN8)
17827 #define G_CMDLEN8(x) (((x) >> S_CMDLEN8) & M_CMDLEN8)
17829 #define S_CMDADDR8 8
17830 #define M_CMDADDR8 0x1fffU
17831 #define V_CMDADDR8(x) ((x) << S_CMDADDR8)
17832 #define G_CMDADDR8(x) (((x) >> S_CMDADDR8) & M_CMDADDR8)
17834 #define S_WRDATAVLD8 7
17835 #define V_WRDATAVLD8(x) ((x) << S_WRDATAVLD8)
17836 #define F_WRDATAVLD8 V_WRDATAVLD8(1U)
17838 #define S_WRDATARDY8 6
17839 #define V_WRDATARDY8(x) ((x) << S_WRDATARDY8)
17840 #define F_WRDATARDY8 V_WRDATARDY8(1U)
17842 #define S_RDDATARDY8 5
17843 #define V_RDDATARDY8(x) ((x) << S_RDDATARDY8)
17844 #define F_RDDATARDY8 V_RDDATARDY8(1U)
17846 #define S_RDDATAVLD8 4
17847 #define V_RDDATAVLD8(x) ((x) << S_RDDATAVLD8)
17848 #define F_RDDATAVLD8 V_RDDATAVLD8(1U)
17850 #define S_RDDATA8 0
17851 #define M_RDDATA8 0xfU
17852 #define V_RDDATA8(x) ((x) << S_RDDATA8)
17853 #define G_RDDATA8(x) (((x) >> S_RDDATA8) & M_RDDATA8)
17855 #define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
17857 #define S_CMDVLD9 31
17858 #define V_CMDVLD9(x) ((x) << S_CMDVLD9)
17859 #define F_CMDVLD9 V_CMDVLD9(1U)
17861 #define S_CMDRDY9 30
17862 #define V_CMDRDY9(x) ((x) << S_CMDRDY9)
17863 #define F_CMDRDY9 V_CMDRDY9(1U)
17865 #define S_CMDTYPE9 29
17866 #define V_CMDTYPE9(x) ((x) << S_CMDTYPE9)
17867 #define F_CMDTYPE9 V_CMDTYPE9(1U)
17869 #define S_CMDLEN9 21
17870 #define M_CMDLEN9 0xffU
17871 #define V_CMDLEN9(x) ((x) << S_CMDLEN9)
17872 #define G_CMDLEN9(x) (((x) >> S_CMDLEN9) & M_CMDLEN9)
17874 #define S_CMDADDR9 8
17875 #define M_CMDADDR9 0x1fffU
17876 #define V_CMDADDR9(x) ((x) << S_CMDADDR9)
17877 #define G_CMDADDR9(x) (((x) >> S_CMDADDR9) & M_CMDADDR9)
17879 #define S_WRDATAVLD9 7
17880 #define V_WRDATAVLD9(x) ((x) << S_WRDATAVLD9)
17881 #define F_WRDATAVLD9 V_WRDATAVLD9(1U)
17883 #define S_WRDATARDY9 6
17884 #define V_WRDATARDY9(x) ((x) << S_WRDATARDY9)
17885 #define F_WRDATARDY9 V_WRDATARDY9(1U)
17887 #define S_RDDATARDY9 5
17888 #define V_RDDATARDY9(x) ((x) << S_RDDATARDY9)
17889 #define F_RDDATARDY9 V_RDDATARDY9(1U)
17891 #define S_RDDATAVLD9 4
17892 #define V_RDDATAVLD9(x) ((x) << S_RDDATAVLD9)
17893 #define F_RDDATAVLD9 V_RDDATAVLD9(1U)
17895 #define S_RDDATA9 0
17896 #define M_RDDATA9 0xfU
17897 #define V_RDDATA9(x) ((x) << S_RDDATA9)
17898 #define G_RDDATA9(x) (((x) >> S_RDDATA9) & M_RDDATA9)
17900 #define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
17902 #define S_CMDVLD10 31
17903 #define V_CMDVLD10(x) ((x) << S_CMDVLD10)
17904 #define F_CMDVLD10 V_CMDVLD10(1U)
17906 #define S_CMDRDY10 30
17907 #define V_CMDRDY10(x) ((x) << S_CMDRDY10)
17908 #define F_CMDRDY10 V_CMDRDY10(1U)
17910 #define S_CMDTYPE10 29
17911 #define V_CMDTYPE10(x) ((x) << S_CMDTYPE10)
17912 #define F_CMDTYPE10 V_CMDTYPE10(1U)
17914 #define S_CMDLEN10 21
17915 #define M_CMDLEN10 0xffU
17916 #define V_CMDLEN10(x) ((x) << S_CMDLEN10)
17917 #define G_CMDLEN10(x) (((x) >> S_CMDLEN10) & M_CMDLEN10)
17919 #define S_CMDADDR10 8
17920 #define M_CMDADDR10 0x1fffU
17921 #define V_CMDADDR10(x) ((x) << S_CMDADDR10)
17922 #define G_CMDADDR10(x) (((x) >> S_CMDADDR10) & M_CMDADDR10)
17924 #define S_WRDATAVLD10 7
17925 #define V_WRDATAVLD10(x) ((x) << S_WRDATAVLD10)
17926 #define F_WRDATAVLD10 V_WRDATAVLD10(1U)
17928 #define S_WRDATARDY10 6
17929 #define V_WRDATARDY10(x) ((x) << S_WRDATARDY10)
17930 #define F_WRDATARDY10 V_WRDATARDY10(1U)
17932 #define S_RDDATARDY10 5
17933 #define V_RDDATARDY10(x) ((x) << S_RDDATARDY10)
17934 #define F_RDDATARDY10 V_RDDATARDY10(1U)
17936 #define S_RDDATAVLD10 4
17937 #define V_RDDATAVLD10(x) ((x) << S_RDDATAVLD10)
17938 #define F_RDDATAVLD10 V_RDDATAVLD10(1U)
17940 #define S_RDDATA10 0
17941 #define M_RDDATA10 0xfU
17942 #define V_RDDATA10(x) ((x) << S_RDDATA10)
17943 #define G_RDDATA10(x) (((x) >> S_RDDATA10) & M_RDDATA10)
17945 #define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
17947 #define S_CMDVLD11 31
17948 #define V_CMDVLD11(x) ((x) << S_CMDVLD11)
17949 #define F_CMDVLD11 V_CMDVLD11(1U)
17951 #define S_CMDRDY11 30
17952 #define V_CMDRDY11(x) ((x) << S_CMDRDY11)
17953 #define F_CMDRDY11 V_CMDRDY11(1U)
17955 #define S_CMDTYPE11 29
17956 #define V_CMDTYPE11(x) ((x) << S_CMDTYPE11)
17957 #define F_CMDTYPE11 V_CMDTYPE11(1U)
17959 #define S_CMDLEN11 21
17960 #define M_CMDLEN11 0xffU
17961 #define V_CMDLEN11(x) ((x) << S_CMDLEN11)
17962 #define G_CMDLEN11(x) (((x) >> S_CMDLEN11) & M_CMDLEN11)
17964 #define S_CMDADDR11 8
17965 #define M_CMDADDR11 0x1fffU
17966 #define V_CMDADDR11(x) ((x) << S_CMDADDR11)
17967 #define G_CMDADDR11(x) (((x) >> S_CMDADDR11) & M_CMDADDR11)
17969 #define S_WRDATAVLD11 7
17970 #define V_WRDATAVLD11(x) ((x) << S_WRDATAVLD11)
17971 #define F_WRDATAVLD11 V_WRDATAVLD11(1U)
17973 #define S_WRDATARDY11 6
17974 #define V_WRDATARDY11(x) ((x) << S_WRDATARDY11)
17975 #define F_WRDATARDY11 V_WRDATARDY11(1U)
17977 #define S_RDDATARDY11 5
17978 #define V_RDDATARDY11(x) ((x) << S_RDDATARDY11)
17979 #define F_RDDATARDY11 V_RDDATARDY11(1U)
17981 #define S_RDDATAVLD11 4
17982 #define V_RDDATAVLD11(x) ((x) << S_RDDATAVLD11)
17983 #define F_RDDATAVLD11 V_RDDATAVLD11(1U)
17985 #define S_RDDATA11 0
17986 #define M_RDDATA11 0xfU
17987 #define V_RDDATA11(x) ((x) << S_RDDATA11)
17988 #define G_RDDATA11(x) (((x) >> S_RDDATA11) & M_RDDATA11)
17990 #define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
17992 #define S_CMDVLD12 31
17993 #define V_CMDVLD12(x) ((x) << S_CMDVLD12)
17994 #define F_CMDVLD12 V_CMDVLD12(1U)
17996 #define S_CMDRDY12 30
17997 #define V_CMDRDY12(x) ((x) << S_CMDRDY12)
17998 #define F_CMDRDY12 V_CMDRDY12(1U)
18000 #define S_CMDTYPE12 29
18001 #define V_CMDTYPE12(x) ((x) << S_CMDTYPE12)
18002 #define F_CMDTYPE12 V_CMDTYPE12(1U)
18004 #define S_CMDLEN12 21
18005 #define M_CMDLEN12 0xffU
18006 #define V_CMDLEN12(x) ((x) << S_CMDLEN12)
18007 #define G_CMDLEN12(x) (((x) >> S_CMDLEN12) & M_CMDLEN12)
18009 #define S_CMDADDR12 8
18010 #define M_CMDADDR12 0x1fffU
18011 #define V_CMDADDR12(x) ((x) << S_CMDADDR12)
18012 #define G_CMDADDR12(x) (((x) >> S_CMDADDR12) & M_CMDADDR12)
18014 #define S_WRDATAVLD12 7
18015 #define V_WRDATAVLD12(x) ((x) << S_WRDATAVLD12)
18016 #define F_WRDATAVLD12 V_WRDATAVLD12(1U)
18018 #define S_WRDATARDY12 6
18019 #define V_WRDATARDY12(x) ((x) << S_WRDATARDY12)
18020 #define F_WRDATARDY12 V_WRDATARDY12(1U)
18022 #define S_RDDATARDY12 5
18023 #define V_RDDATARDY12(x) ((x) << S_RDDATARDY12)
18024 #define F_RDDATARDY12 V_RDDATARDY12(1U)
18026 #define S_RDDATAVLD12 4
18027 #define V_RDDATAVLD12(x) ((x) << S_RDDATAVLD12)
18028 #define F_RDDATAVLD12 V_RDDATAVLD12(1U)
18030 #define S_RDDATA12 0
18031 #define M_RDDATA12 0xfU
18032 #define V_RDDATA12(x) ((x) << S_RDDATA12)
18033 #define G_RDDATA12(x) (((x) >> S_RDDATA12) & M_RDDATA12)
18035 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
18037 #define S_CI0_ARB0_REQ 31
18038 #define V_CI0_ARB0_REQ(x) ((x) << S_CI0_ARB0_REQ)
18039 #define F_CI0_ARB0_REQ V_CI0_ARB0_REQ(1U)
18041 #define S_ARB0_CI0_GNT 30
18042 #define V_ARB0_CI0_GNT(x) ((x) << S_ARB0_CI0_GNT)
18043 #define F_ARB0_CI0_GNT V_ARB0_CI0_GNT(1U)
18045 #define S_CI0_DM0_WDATA_VLD 29
18046 #define V_CI0_DM0_WDATA_VLD(x) ((x) << S_CI0_DM0_WDATA_VLD)
18047 #define F_CI0_DM0_WDATA_VLD V_CI0_DM0_WDATA_VLD(1U)
18049 #define S_DM0_CI0_RDATA_VLD 28
18050 #define V_DM0_CI0_RDATA_VLD(x) ((x) << S_DM0_CI0_RDATA_VLD)
18051 #define F_DM0_CI0_RDATA_VLD V_DM0_CI0_RDATA_VLD(1U)
18053 #define S_CI1_ARB0_REQ 27
18054 #define V_CI1_ARB0_REQ(x) ((x) << S_CI1_ARB0_REQ)
18055 #define F_CI1_ARB0_REQ V_CI1_ARB0_REQ(1U)
18057 #define S_ARB0_CI1_GNT 26
18058 #define V_ARB0_CI1_GNT(x) ((x) << S_ARB0_CI1_GNT)
18059 #define F_ARB0_CI1_GNT V_ARB0_CI1_GNT(1U)
18061 #define S_CI1_DM0_WDATA_VLD 25
18062 #define V_CI1_DM0_WDATA_VLD(x) ((x) << S_CI1_DM0_WDATA_VLD)
18063 #define F_CI1_DM0_WDATA_VLD V_CI1_DM0_WDATA_VLD(1U)
18065 #define S_DM0_CI1_RDATA_VLD 24
18066 #define V_DM0_CI1_RDATA_VLD(x) ((x) << S_DM0_CI1_RDATA_VLD)
18067 #define F_DM0_CI1_RDATA_VLD V_DM0_CI1_RDATA_VLD(1U)
18069 #define S_CI2_ARB0_REQ 23
18070 #define V_CI2_ARB0_REQ(x) ((x) << S_CI2_ARB0_REQ)
18071 #define F_CI2_ARB0_REQ V_CI2_ARB0_REQ(1U)
18073 #define S_ARB0_CI2_GNT 22
18074 #define V_ARB0_CI2_GNT(x) ((x) << S_ARB0_CI2_GNT)
18075 #define F_ARB0_CI2_GNT V_ARB0_CI2_GNT(1U)
18077 #define S_CI2_DM0_WDATA_VLD 21
18078 #define V_CI2_DM0_WDATA_VLD(x) ((x) << S_CI2_DM0_WDATA_VLD)
18079 #define F_CI2_DM0_WDATA_VLD V_CI2_DM0_WDATA_VLD(1U)
18081 #define S_DM0_CI2_RDATA_VLD 20
18082 #define V_DM0_CI2_RDATA_VLD(x) ((x) << S_DM0_CI2_RDATA_VLD)
18083 #define F_DM0_CI2_RDATA_VLD V_DM0_CI2_RDATA_VLD(1U)
18085 #define S_CI3_ARB0_REQ 19
18086 #define V_CI3_ARB0_REQ(x) ((x) << S_CI3_ARB0_REQ)
18087 #define F_CI3_ARB0_REQ V_CI3_ARB0_REQ(1U)
18089 #define S_ARB0_CI3_GNT 18
18090 #define V_ARB0_CI3_GNT(x) ((x) << S_ARB0_CI3_GNT)
18091 #define F_ARB0_CI3_GNT V_ARB0_CI3_GNT(1U)
18093 #define S_CI3_DM0_WDATA_VLD 17
18094 #define V_CI3_DM0_WDATA_VLD(x) ((x) << S_CI3_DM0_WDATA_VLD)
18095 #define F_CI3_DM0_WDATA_VLD V_CI3_DM0_WDATA_VLD(1U)
18097 #define S_DM0_CI3_RDATA_VLD 16
18098 #define V_DM0_CI3_RDATA_VLD(x) ((x) << S_DM0_CI3_RDATA_VLD)
18099 #define F_DM0_CI3_RDATA_VLD V_DM0_CI3_RDATA_VLD(1U)
18101 #define S_CI4_ARB0_REQ 15
18102 #define V_CI4_ARB0_REQ(x) ((x) << S_CI4_ARB0_REQ)
18103 #define F_CI4_ARB0_REQ V_CI4_ARB0_REQ(1U)
18105 #define S_ARB0_CI4_GNT 14
18106 #define V_ARB0_CI4_GNT(x) ((x) << S_ARB0_CI4_GNT)
18107 #define F_ARB0_CI4_GNT V_ARB0_CI4_GNT(1U)
18109 #define S_CI4_DM0_WDATA_VLD 13
18110 #define V_CI4_DM0_WDATA_VLD(x) ((x) << S_CI4_DM0_WDATA_VLD)
18111 #define F_CI4_DM0_WDATA_VLD V_CI4_DM0_WDATA_VLD(1U)
18113 #define S_DM0_CI4_RDATA_VLD 12
18114 #define V_DM0_CI4_RDATA_VLD(x) ((x) << S_DM0_CI4_RDATA_VLD)
18115 #define F_DM0_CI4_RDATA_VLD V_DM0_CI4_RDATA_VLD(1U)
18117 #define S_CI5_ARB0_REQ 11
18118 #define V_CI5_ARB0_REQ(x) ((x) << S_CI5_ARB0_REQ)
18119 #define F_CI5_ARB0_REQ V_CI5_ARB0_REQ(1U)
18121 #define S_ARB0_CI5_GNT 10
18122 #define V_ARB0_CI5_GNT(x) ((x) << S_ARB0_CI5_GNT)
18123 #define F_ARB0_CI5_GNT V_ARB0_CI5_GNT(1U)
18125 #define S_CI5_DM0_WDATA_VLD 9
18126 #define V_CI5_DM0_WDATA_VLD(x) ((x) << S_CI5_DM0_WDATA_VLD)
18127 #define F_CI5_DM0_WDATA_VLD V_CI5_DM0_WDATA_VLD(1U)
18129 #define S_DM0_CI5_RDATA_VLD 8
18130 #define V_DM0_CI5_RDATA_VLD(x) ((x) << S_DM0_CI5_RDATA_VLD)
18131 #define F_DM0_CI5_RDATA_VLD V_DM0_CI5_RDATA_VLD(1U)
18133 #define S_CI6_ARB0_REQ 7
18134 #define V_CI6_ARB0_REQ(x) ((x) << S_CI6_ARB0_REQ)
18135 #define F_CI6_ARB0_REQ V_CI6_ARB0_REQ(1U)
18137 #define S_ARB0_CI6_GNT 6
18138 #define V_ARB0_CI6_GNT(x) ((x) << S_ARB0_CI6_GNT)
18139 #define F_ARB0_CI6_GNT V_ARB0_CI6_GNT(1U)
18141 #define S_CI6_DM0_WDATA_VLD 5
18142 #define V_CI6_DM0_WDATA_VLD(x) ((x) << S_CI6_DM0_WDATA_VLD)
18143 #define F_CI6_DM0_WDATA_VLD V_CI6_DM0_WDATA_VLD(1U)
18145 #define S_DM0_CI6_RDATA_VLD 4
18146 #define V_DM0_CI6_RDATA_VLD(x) ((x) << S_DM0_CI6_RDATA_VLD)
18147 #define F_DM0_CI6_RDATA_VLD V_DM0_CI6_RDATA_VLD(1U)
18149 #define S_CI7_ARB0_REQ 3
18150 #define V_CI7_ARB0_REQ(x) ((x) << S_CI7_ARB0_REQ)
18151 #define F_CI7_ARB0_REQ V_CI7_ARB0_REQ(1U)
18153 #define S_ARB0_CI7_GNT 2
18154 #define V_ARB0_CI7_GNT(x) ((x) << S_ARB0_CI7_GNT)
18155 #define F_ARB0_CI7_GNT V_ARB0_CI7_GNT(1U)
18157 #define S_CI7_DM0_WDATA_VLD 1
18158 #define V_CI7_DM0_WDATA_VLD(x) ((x) << S_CI7_DM0_WDATA_VLD)
18159 #define F_CI7_DM0_WDATA_VLD V_CI7_DM0_WDATA_VLD(1U)
18161 #define S_DM0_CI7_RDATA_VLD 0
18162 #define V_DM0_CI7_RDATA_VLD(x) ((x) << S_DM0_CI7_RDATA_VLD)
18163 #define F_DM0_CI7_RDATA_VLD V_DM0_CI7_RDATA_VLD(1U)
18165 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
18167 #define S_CI0_ARB1_REQ 31
18168 #define V_CI0_ARB1_REQ(x) ((x) << S_CI0_ARB1_REQ)
18169 #define F_CI0_ARB1_REQ V_CI0_ARB1_REQ(1U)
18171 #define S_ARB1_CI0_GNT 30
18172 #define V_ARB1_CI0_GNT(x) ((x) << S_ARB1_CI0_GNT)
18173 #define F_ARB1_CI0_GNT V_ARB1_CI0_GNT(1U)
18175 #define S_CI0_DM1_WDATA_VLD 29
18176 #define V_CI0_DM1_WDATA_VLD(x) ((x) << S_CI0_DM1_WDATA_VLD)
18177 #define F_CI0_DM1_WDATA_VLD V_CI0_DM1_WDATA_VLD(1U)
18179 #define S_DM1_CI0_RDATA_VLD 28
18180 #define V_DM1_CI0_RDATA_VLD(x) ((x) << S_DM1_CI0_RDATA_VLD)
18181 #define F_DM1_CI0_RDATA_VLD V_DM1_CI0_RDATA_VLD(1U)
18183 #define S_CI1_ARB1_REQ 27
18184 #define V_CI1_ARB1_REQ(x) ((x) << S_CI1_ARB1_REQ)
18185 #define F_CI1_ARB1_REQ V_CI1_ARB1_REQ(1U)
18187 #define S_ARB1_CI1_GNT 26
18188 #define V_ARB1_CI1_GNT(x) ((x) << S_ARB1_CI1_GNT)
18189 #define F_ARB1_CI1_GNT V_ARB1_CI1_GNT(1U)
18191 #define S_CI1_DM1_WDATA_VLD 25
18192 #define V_CI1_DM1_WDATA_VLD(x) ((x) << S_CI1_DM1_WDATA_VLD)
18193 #define F_CI1_DM1_WDATA_VLD V_CI1_DM1_WDATA_VLD(1U)
18195 #define S_DM1_CI1_RDATA_VLD 24
18196 #define V_DM1_CI1_RDATA_VLD(x) ((x) << S_DM1_CI1_RDATA_VLD)
18197 #define F_DM1_CI1_RDATA_VLD V_DM1_CI1_RDATA_VLD(1U)
18199 #define S_CI2_ARB1_REQ 23
18200 #define V_CI2_ARB1_REQ(x) ((x) << S_CI2_ARB1_REQ)
18201 #define F_CI2_ARB1_REQ V_CI2_ARB1_REQ(1U)
18203 #define S_ARB1_CI2_GNT 22
18204 #define V_ARB1_CI2_GNT(x) ((x) << S_ARB1_CI2_GNT)
18205 #define F_ARB1_CI2_GNT V_ARB1_CI2_GNT(1U)
18207 #define S_CI2_DM1_WDATA_VLD 21
18208 #define V_CI2_DM1_WDATA_VLD(x) ((x) << S_CI2_DM1_WDATA_VLD)
18209 #define F_CI2_DM1_WDATA_VLD V_CI2_DM1_WDATA_VLD(1U)
18211 #define S_DM1_CI2_RDATA_VLD 20
18212 #define V_DM1_CI2_RDATA_VLD(x) ((x) << S_DM1_CI2_RDATA_VLD)
18213 #define F_DM1_CI2_RDATA_VLD V_DM1_CI2_RDATA_VLD(1U)
18215 #define S_CI3_ARB1_REQ 19
18216 #define V_CI3_ARB1_REQ(x) ((x) << S_CI3_ARB1_REQ)
18217 #define F_CI3_ARB1_REQ V_CI3_ARB1_REQ(1U)
18219 #define S_ARB1_CI3_GNT 18
18220 #define V_ARB1_CI3_GNT(x) ((x) << S_ARB1_CI3_GNT)
18221 #define F_ARB1_CI3_GNT V_ARB1_CI3_GNT(1U)
18223 #define S_CI3_DM1_WDATA_VLD 17
18224 #define V_CI3_DM1_WDATA_VLD(x) ((x) << S_CI3_DM1_WDATA_VLD)
18225 #define F_CI3_DM1_WDATA_VLD V_CI3_DM1_WDATA_VLD(1U)
18227 #define S_DM1_CI3_RDATA_VLD 16
18228 #define V_DM1_CI3_RDATA_VLD(x) ((x) << S_DM1_CI3_RDATA_VLD)
18229 #define F_DM1_CI3_RDATA_VLD V_DM1_CI3_RDATA_VLD(1U)
18231 #define S_CI4_ARB1_REQ 15
18232 #define V_CI4_ARB1_REQ(x) ((x) << S_CI4_ARB1_REQ)
18233 #define F_CI4_ARB1_REQ V_CI4_ARB1_REQ(1U)
18235 #define S_ARB1_CI4_GNT 14
18236 #define V_ARB1_CI4_GNT(x) ((x) << S_ARB1_CI4_GNT)
18237 #define F_ARB1_CI4_GNT V_ARB1_CI4_GNT(1U)
18239 #define S_CI4_DM1_WDATA_VLD 13
18240 #define V_CI4_DM1_WDATA_VLD(x) ((x) << S_CI4_DM1_WDATA_VLD)
18241 #define F_CI4_DM1_WDATA_VLD V_CI4_DM1_WDATA_VLD(1U)
18243 #define S_DM1_CI4_RDATA_VLD 12
18244 #define V_DM1_CI4_RDATA_VLD(x) ((x) << S_DM1_CI4_RDATA_VLD)
18245 #define F_DM1_CI4_RDATA_VLD V_DM1_CI4_RDATA_VLD(1U)
18247 #define S_CI5_ARB1_REQ 11
18248 #define V_CI5_ARB1_REQ(x) ((x) << S_CI5_ARB1_REQ)
18249 #define F_CI5_ARB1_REQ V_CI5_ARB1_REQ(1U)
18251 #define S_ARB1_CI5_GNT 10
18252 #define V_ARB1_CI5_GNT(x) ((x) << S_ARB1_CI5_GNT)
18253 #define F_ARB1_CI5_GNT V_ARB1_CI5_GNT(1U)
18255 #define S_CI5_DM1_WDATA_VLD 9
18256 #define V_CI5_DM1_WDATA_VLD(x) ((x) << S_CI5_DM1_WDATA_VLD)
18257 #define F_CI5_DM1_WDATA_VLD V_CI5_DM1_WDATA_VLD(1U)
18259 #define S_DM1_CI5_RDATA_VLD 8
18260 #define V_DM1_CI5_RDATA_VLD(x) ((x) << S_DM1_CI5_RDATA_VLD)
18261 #define F_DM1_CI5_RDATA_VLD V_DM1_CI5_RDATA_VLD(1U)
18263 #define S_CI6_ARB1_REQ 7
18264 #define V_CI6_ARB1_REQ(x) ((x) << S_CI6_ARB1_REQ)
18265 #define F_CI6_ARB1_REQ V_CI6_ARB1_REQ(1U)
18267 #define S_ARB1_CI6_GNT 6
18268 #define V_ARB1_CI6_GNT(x) ((x) << S_ARB1_CI6_GNT)
18269 #define F_ARB1_CI6_GNT V_ARB1_CI6_GNT(1U)
18271 #define S_CI6_DM1_WDATA_VLD 5
18272 #define V_CI6_DM1_WDATA_VLD(x) ((x) << S_CI6_DM1_WDATA_VLD)
18273 #define F_CI6_DM1_WDATA_VLD V_CI6_DM1_WDATA_VLD(1U)
18275 #define S_DM1_CI6_RDATA_VLD 4
18276 #define V_DM1_CI6_RDATA_VLD(x) ((x) << S_DM1_CI6_RDATA_VLD)
18277 #define F_DM1_CI6_RDATA_VLD V_DM1_CI6_RDATA_VLD(1U)
18279 #define S_CI7_ARB1_REQ 3
18280 #define V_CI7_ARB1_REQ(x) ((x) << S_CI7_ARB1_REQ)
18281 #define F_CI7_ARB1_REQ V_CI7_ARB1_REQ(1U)
18283 #define S_ARB1_CI7_GNT 2
18284 #define V_ARB1_CI7_GNT(x) ((x) << S_ARB1_CI7_GNT)
18285 #define F_ARB1_CI7_GNT V_ARB1_CI7_GNT(1U)
18287 #define S_CI7_DM1_WDATA_VLD 1
18288 #define V_CI7_DM1_WDATA_VLD(x) ((x) << S_CI7_DM1_WDATA_VLD)
18289 #define F_CI7_DM1_WDATA_VLD V_CI7_DM1_WDATA_VLD(1U)
18291 #define S_DM1_CI7_RDATA_VLD 0
18292 #define V_DM1_CI7_RDATA_VLD(x) ((x) << S_DM1_CI7_RDATA_VLD)
18293 #define F_DM1_CI7_RDATA_VLD V_DM1_CI7_RDATA_VLD(1U)
18295 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
18297 #define S_CI0_ARB2_REQ 31
18298 #define V_CI0_ARB2_REQ(x) ((x) << S_CI0_ARB2_REQ)
18299 #define F_CI0_ARB2_REQ V_CI0_ARB2_REQ(1U)
18301 #define S_ARB2_CI0_GNT 30
18302 #define V_ARB2_CI0_GNT(x) ((x) << S_ARB2_CI0_GNT)
18303 #define F_ARB2_CI0_GNT V_ARB2_CI0_GNT(1U)
18305 #define S_CI0_DM2_WDATA_VLD 29
18306 #define V_CI0_DM2_WDATA_VLD(x) ((x) << S_CI0_DM2_WDATA_VLD)
18307 #define F_CI0_DM2_WDATA_VLD V_CI0_DM2_WDATA_VLD(1U)
18309 #define S_DM2_CI0_RDATA_VLD 28
18310 #define V_DM2_CI0_RDATA_VLD(x) ((x) << S_DM2_CI0_RDATA_VLD)
18311 #define F_DM2_CI0_RDATA_VLD V_DM2_CI0_RDATA_VLD(1U)
18313 #define S_CI1_ARB2_REQ 27
18314 #define V_CI1_ARB2_REQ(x) ((x) << S_CI1_ARB2_REQ)
18315 #define F_CI1_ARB2_REQ V_CI1_ARB2_REQ(1U)
18317 #define S_ARB2_CI1_GNT 26
18318 #define V_ARB2_CI1_GNT(x) ((x) << S_ARB2_CI1_GNT)
18319 #define F_ARB2_CI1_GNT V_ARB2_CI1_GNT(1U)
18321 #define S_CI1_DM2_WDATA_VLD 25
18322 #define V_CI1_DM2_WDATA_VLD(x) ((x) << S_CI1_DM2_WDATA_VLD)
18323 #define F_CI1_DM2_WDATA_VLD V_CI1_DM2_WDATA_VLD(1U)
18325 #define S_DM2_CI1_RDATA_VLD 24
18326 #define V_DM2_CI1_RDATA_VLD(x) ((x) << S_DM2_CI1_RDATA_VLD)
18327 #define F_DM2_CI1_RDATA_VLD V_DM2_CI1_RDATA_VLD(1U)
18329 #define S_CI2_ARB2_REQ 23
18330 #define V_CI2_ARB2_REQ(x) ((x) << S_CI2_ARB2_REQ)
18331 #define F_CI2_ARB2_REQ V_CI2_ARB2_REQ(1U)
18333 #define S_ARB2_CI2_GNT 22
18334 #define V_ARB2_CI2_GNT(x) ((x) << S_ARB2_CI2_GNT)
18335 #define F_ARB2_CI2_GNT V_ARB2_CI2_GNT(1U)
18337 #define S_CI2_DM2_WDATA_VLD 21
18338 #define V_CI2_DM2_WDATA_VLD(x) ((x) << S_CI2_DM2_WDATA_VLD)
18339 #define F_CI2_DM2_WDATA_VLD V_CI2_DM2_WDATA_VLD(1U)
18341 #define S_DM2_CI2_RDATA_VLD 20
18342 #define V_DM2_CI2_RDATA_VLD(x) ((x) << S_DM2_CI2_RDATA_VLD)
18343 #define F_DM2_CI2_RDATA_VLD V_DM2_CI2_RDATA_VLD(1U)
18345 #define S_CI3_ARB2_REQ 19
18346 #define V_CI3_ARB2_REQ(x) ((x) << S_CI3_ARB2_REQ)
18347 #define F_CI3_ARB2_REQ V_CI3_ARB2_REQ(1U)
18349 #define S_ARB2_CI3_GNT 18
18350 #define V_ARB2_CI3_GNT(x) ((x) << S_ARB2_CI3_GNT)
18351 #define F_ARB2_CI3_GNT V_ARB2_CI3_GNT(1U)
18353 #define S_CI3_DM2_WDATA_VLD 17
18354 #define V_CI3_DM2_WDATA_VLD(x) ((x) << S_CI3_DM2_WDATA_VLD)
18355 #define F_CI3_DM2_WDATA_VLD V_CI3_DM2_WDATA_VLD(1U)
18357 #define S_DM2_CI3_RDATA_VLD 16
18358 #define V_DM2_CI3_RDATA_VLD(x) ((x) << S_DM2_CI3_RDATA_VLD)
18359 #define F_DM2_CI3_RDATA_VLD V_DM2_CI3_RDATA_VLD(1U)
18361 #define S_CI4_ARB2_REQ 15
18362 #define V_CI4_ARB2_REQ(x) ((x) << S_CI4_ARB2_REQ)
18363 #define F_CI4_ARB2_REQ V_CI4_ARB2_REQ(1U)
18365 #define S_ARB2_CI4_GNT 14
18366 #define V_ARB2_CI4_GNT(x) ((x) << S_ARB2_CI4_GNT)
18367 #define F_ARB2_CI4_GNT V_ARB2_CI4_GNT(1U)
18369 #define S_CI4_DM2_WDATA_VLD 13
18370 #define V_CI4_DM2_WDATA_VLD(x) ((x) << S_CI4_DM2_WDATA_VLD)
18371 #define F_CI4_DM2_WDATA_VLD V_CI4_DM2_WDATA_VLD(1U)
18373 #define S_DM2_CI4_RDATA_VLD 12
18374 #define V_DM2_CI4_RDATA_VLD(x) ((x) << S_DM2_CI4_RDATA_VLD)
18375 #define F_DM2_CI4_RDATA_VLD V_DM2_CI4_RDATA_VLD(1U)
18377 #define S_CI5_ARB2_REQ 11
18378 #define V_CI5_ARB2_REQ(x) ((x) << S_CI5_ARB2_REQ)
18379 #define F_CI5_ARB2_REQ V_CI5_ARB2_REQ(1U)
18381 #define S_ARB2_CI5_GNT 10
18382 #define V_ARB2_CI5_GNT(x) ((x) << S_ARB2_CI5_GNT)
18383 #define F_ARB2_CI5_GNT V_ARB2_CI5_GNT(1U)
18385 #define S_CI5_DM2_WDATA_VLD 9
18386 #define V_CI5_DM2_WDATA_VLD(x) ((x) << S_CI5_DM2_WDATA_VLD)
18387 #define F_CI5_DM2_WDATA_VLD V_CI5_DM2_WDATA_VLD(1U)
18389 #define S_DM2_CI5_RDATA_VLD 8
18390 #define V_DM2_CI5_RDATA_VLD(x) ((x) << S_DM2_CI5_RDATA_VLD)
18391 #define F_DM2_CI5_RDATA_VLD V_DM2_CI5_RDATA_VLD(1U)
18393 #define S_CI6_ARB2_REQ 7
18394 #define V_CI6_ARB2_REQ(x) ((x) << S_CI6_ARB2_REQ)
18395 #define F_CI6_ARB2_REQ V_CI6_ARB2_REQ(1U)
18397 #define S_ARB2_CI6_GNT 6
18398 #define V_ARB2_CI6_GNT(x) ((x) << S_ARB2_CI6_GNT)
18399 #define F_ARB2_CI6_GNT V_ARB2_CI6_GNT(1U)
18401 #define S_CI6_DM2_WDATA_VLD 5
18402 #define V_CI6_DM2_WDATA_VLD(x) ((x) << S_CI6_DM2_WDATA_VLD)
18403 #define F_CI6_DM2_WDATA_VLD V_CI6_DM2_WDATA_VLD(1U)
18405 #define S_DM2_CI6_RDATA_VLD 4
18406 #define V_DM2_CI6_RDATA_VLD(x) ((x) << S_DM2_CI6_RDATA_VLD)
18407 #define F_DM2_CI6_RDATA_VLD V_DM2_CI6_RDATA_VLD(1U)
18409 #define S_CI7_ARB2_REQ 3
18410 #define V_CI7_ARB2_REQ(x) ((x) << S_CI7_ARB2_REQ)
18411 #define F_CI7_ARB2_REQ V_CI7_ARB2_REQ(1U)
18413 #define S_ARB2_CI7_GNT 2
18414 #define V_ARB2_CI7_GNT(x) ((x) << S_ARB2_CI7_GNT)
18415 #define F_ARB2_CI7_GNT V_ARB2_CI7_GNT(1U)
18417 #define S_CI7_DM2_WDATA_VLD 1
18418 #define V_CI7_DM2_WDATA_VLD(x) ((x) << S_CI7_DM2_WDATA_VLD)
18419 #define F_CI7_DM2_WDATA_VLD V_CI7_DM2_WDATA_VLD(1U)
18421 #define S_DM2_CI7_RDATA_VLD 0
18422 #define V_DM2_CI7_RDATA_VLD(x) ((x) << S_DM2_CI7_RDATA_VLD)
18423 #define F_DM2_CI7_RDATA_VLD V_DM2_CI7_RDATA_VLD(1U)
18425 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
18427 #define S_CI0_ARB3_REQ 31
18428 #define V_CI0_ARB3_REQ(x) ((x) << S_CI0_ARB3_REQ)
18429 #define F_CI0_ARB3_REQ V_CI0_ARB3_REQ(1U)
18431 #define S_ARB3_CI0_GNT 30
18432 #define V_ARB3_CI0_GNT(x) ((x) << S_ARB3_CI0_GNT)
18433 #define F_ARB3_CI0_GNT V_ARB3_CI0_GNT(1U)
18435 #define S_CI0_DM3_WDATA_VLD 29
18436 #define V_CI0_DM3_WDATA_VLD(x) ((x) << S_CI0_DM3_WDATA_VLD)
18437 #define F_CI0_DM3_WDATA_VLD V_CI0_DM3_WDATA_VLD(1U)
18439 #define S_DM3_CI0_RDATA_VLD 28
18440 #define V_DM3_CI0_RDATA_VLD(x) ((x) << S_DM3_CI0_RDATA_VLD)
18441 #define F_DM3_CI0_RDATA_VLD V_DM3_CI0_RDATA_VLD(1U)
18443 #define S_CI1_ARB3_REQ 27
18444 #define V_CI1_ARB3_REQ(x) ((x) << S_CI1_ARB3_REQ)
18445 #define F_CI1_ARB3_REQ V_CI1_ARB3_REQ(1U)
18447 #define S_ARB3_CI1_GNT 26
18448 #define V_ARB3_CI1_GNT(x) ((x) << S_ARB3_CI1_GNT)
18449 #define F_ARB3_CI1_GNT V_ARB3_CI1_GNT(1U)
18451 #define S_CI1_DM3_WDATA_VLD 25
18452 #define V_CI1_DM3_WDATA_VLD(x) ((x) << S_CI1_DM3_WDATA_VLD)
18453 #define F_CI1_DM3_WDATA_VLD V_CI1_DM3_WDATA_VLD(1U)
18455 #define S_DM3_CI1_RDATA_VLD 24
18456 #define V_DM3_CI1_RDATA_VLD(x) ((x) << S_DM3_CI1_RDATA_VLD)
18457 #define F_DM3_CI1_RDATA_VLD V_DM3_CI1_RDATA_VLD(1U)
18459 #define S_CI2_ARB3_REQ 23
18460 #define V_CI2_ARB3_REQ(x) ((x) << S_CI2_ARB3_REQ)
18461 #define F_CI2_ARB3_REQ V_CI2_ARB3_REQ(1U)
18463 #define S_ARB3_CI2_GNT 22
18464 #define V_ARB3_CI2_GNT(x) ((x) << S_ARB3_CI2_GNT)
18465 #define F_ARB3_CI2_GNT V_ARB3_CI2_GNT(1U)
18467 #define S_CI2_DM3_WDATA_VLD 21
18468 #define V_CI2_DM3_WDATA_VLD(x) ((x) << S_CI2_DM3_WDATA_VLD)
18469 #define F_CI2_DM3_WDATA_VLD V_CI2_DM3_WDATA_VLD(1U)
18471 #define S_DM3_CI2_RDATA_VLD 20
18472 #define V_DM3_CI2_RDATA_VLD(x) ((x) << S_DM3_CI2_RDATA_VLD)
18473 #define F_DM3_CI2_RDATA_VLD V_DM3_CI2_RDATA_VLD(1U)
18475 #define S_CI3_ARB3_REQ 19
18476 #define V_CI3_ARB3_REQ(x) ((x) << S_CI3_ARB3_REQ)
18477 #define F_CI3_ARB3_REQ V_CI3_ARB3_REQ(1U)
18479 #define S_ARB3_CI3_GNT 18
18480 #define V_ARB3_CI3_GNT(x) ((x) << S_ARB3_CI3_GNT)
18481 #define F_ARB3_CI3_GNT V_ARB3_CI3_GNT(1U)
18483 #define S_CI3_DM3_WDATA_VLD 17
18484 #define V_CI3_DM3_WDATA_VLD(x) ((x) << S_CI3_DM3_WDATA_VLD)
18485 #define F_CI3_DM3_WDATA_VLD V_CI3_DM3_WDATA_VLD(1U)
18487 #define S_DM3_CI3_RDATA_VLD 16
18488 #define V_DM3_CI3_RDATA_VLD(x) ((x) << S_DM3_CI3_RDATA_VLD)
18489 #define F_DM3_CI3_RDATA_VLD V_DM3_CI3_RDATA_VLD(1U)
18491 #define S_CI4_ARB3_REQ 15
18492 #define V_CI4_ARB3_REQ(x) ((x) << S_CI4_ARB3_REQ)
18493 #define F_CI4_ARB3_REQ V_CI4_ARB3_REQ(1U)
18495 #define S_ARB3_CI4_GNT 14
18496 #define V_ARB3_CI4_GNT(x) ((x) << S_ARB3_CI4_GNT)
18497 #define F_ARB3_CI4_GNT V_ARB3_CI4_GNT(1U)
18499 #define S_CI4_DM3_WDATA_VLD 13
18500 #define V_CI4_DM3_WDATA_VLD(x) ((x) << S_CI4_DM3_WDATA_VLD)
18501 #define F_CI4_DM3_WDATA_VLD V_CI4_DM3_WDATA_VLD(1U)
18503 #define S_DM3_CI4_RDATA_VLD 12
18504 #define V_DM3_CI4_RDATA_VLD(x) ((x) << S_DM3_CI4_RDATA_VLD)
18505 #define F_DM3_CI4_RDATA_VLD V_DM3_CI4_RDATA_VLD(1U)
18507 #define S_CI5_ARB3_REQ 11
18508 #define V_CI5_ARB3_REQ(x) ((x) << S_CI5_ARB3_REQ)
18509 #define F_CI5_ARB3_REQ V_CI5_ARB3_REQ(1U)
18511 #define S_ARB3_CI5_GNT 10
18512 #define V_ARB3_CI5_GNT(x) ((x) << S_ARB3_CI5_GNT)
18513 #define F_ARB3_CI5_GNT V_ARB3_CI5_GNT(1U)
18515 #define S_CI5_DM3_WDATA_VLD 9
18516 #define V_CI5_DM3_WDATA_VLD(x) ((x) << S_CI5_DM3_WDATA_VLD)
18517 #define F_CI5_DM3_WDATA_VLD V_CI5_DM3_WDATA_VLD(1U)
18519 #define S_DM3_CI5_RDATA_VLD 8
18520 #define V_DM3_CI5_RDATA_VLD(x) ((x) << S_DM3_CI5_RDATA_VLD)
18521 #define F_DM3_CI5_RDATA_VLD V_DM3_CI5_RDATA_VLD(1U)
18523 #define S_CI6_ARB3_REQ 7
18524 #define V_CI6_ARB3_REQ(x) ((x) << S_CI6_ARB3_REQ)
18525 #define F_CI6_ARB3_REQ V_CI6_ARB3_REQ(1U)
18527 #define S_ARB3_CI6_GNT 6
18528 #define V_ARB3_CI6_GNT(x) ((x) << S_ARB3_CI6_GNT)
18529 #define F_ARB3_CI6_GNT V_ARB3_CI6_GNT(1U)
18531 #define S_CI6_DM3_WDATA_VLD 5
18532 #define V_CI6_DM3_WDATA_VLD(x) ((x) << S_CI6_DM3_WDATA_VLD)
18533 #define F_CI6_DM3_WDATA_VLD V_CI6_DM3_WDATA_VLD(1U)
18535 #define S_DM3_CI6_RDATA_VLD 4
18536 #define V_DM3_CI6_RDATA_VLD(x) ((x) << S_DM3_CI6_RDATA_VLD)
18537 #define F_DM3_CI6_RDATA_VLD V_DM3_CI6_RDATA_VLD(1U)
18539 #define S_CI7_ARB3_REQ 3
18540 #define V_CI7_ARB3_REQ(x) ((x) << S_CI7_ARB3_REQ)
18541 #define F_CI7_ARB3_REQ V_CI7_ARB3_REQ(1U)
18543 #define S_ARB3_CI7_GNT 2
18544 #define V_ARB3_CI7_GNT(x) ((x) << S_ARB3_CI7_GNT)
18545 #define F_ARB3_CI7_GNT V_ARB3_CI7_GNT(1U)
18547 #define S_CI7_DM3_WDATA_VLD 1
18548 #define V_CI7_DM3_WDATA_VLD(x) ((x) << S_CI7_DM3_WDATA_VLD)
18549 #define F_CI7_DM3_WDATA_VLD V_CI7_DM3_WDATA_VLD(1U)
18551 #define S_DM3_CI7_RDATA_VLD 0
18552 #define V_DM3_CI7_RDATA_VLD(x) ((x) << S_DM3_CI7_RDATA_VLD)
18553 #define F_DM3_CI7_RDATA_VLD V_DM3_CI7_RDATA_VLD(1U)
18555 #define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
18556 #define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
18557 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
18559 #define S_CI8_ARB0_REQ 31
18560 #define V_CI8_ARB0_REQ(x) ((x) << S_CI8_ARB0_REQ)
18561 #define F_CI8_ARB0_REQ V_CI8_ARB0_REQ(1U)
18563 #define S_ARB0_CI8_GNT 30
18564 #define V_ARB0_CI8_GNT(x) ((x) << S_ARB0_CI8_GNT)
18565 #define F_ARB0_CI8_GNT V_ARB0_CI8_GNT(1U)
18567 #define S_CI8_DM0_WDATA_VLD 29
18568 #define V_CI8_DM0_WDATA_VLD(x) ((x) << S_CI8_DM0_WDATA_VLD)
18569 #define F_CI8_DM0_WDATA_VLD V_CI8_DM0_WDATA_VLD(1U)
18571 #define S_DM0_CI8_RDATA_VLD 28
18572 #define V_DM0_CI8_RDATA_VLD(x) ((x) << S_DM0_CI8_RDATA_VLD)
18573 #define F_DM0_CI8_RDATA_VLD V_DM0_CI8_RDATA_VLD(1U)
18575 #define S_CI9_ARB0_REQ 27
18576 #define V_CI9_ARB0_REQ(x) ((x) << S_CI9_ARB0_REQ)
18577 #define F_CI9_ARB0_REQ V_CI9_ARB0_REQ(1U)
18579 #define S_ARB0_CI9_GNT 26
18580 #define V_ARB0_CI9_GNT(x) ((x) << S_ARB0_CI9_GNT)
18581 #define F_ARB0_CI9_GNT V_ARB0_CI9_GNT(1U)
18583 #define S_CI9_DM0_WDATA_VLD 25
18584 #define V_CI9_DM0_WDATA_VLD(x) ((x) << S_CI9_DM0_WDATA_VLD)
18585 #define F_CI9_DM0_WDATA_VLD V_CI9_DM0_WDATA_VLD(1U)
18587 #define S_DM0_CI9_RDATA_VLD 24
18588 #define V_DM0_CI9_RDATA_VLD(x) ((x) << S_DM0_CI9_RDATA_VLD)
18589 #define F_DM0_CI9_RDATA_VLD V_DM0_CI9_RDATA_VLD(1U)
18591 #define S_CI10_ARB0_REQ 23
18592 #define V_CI10_ARB0_REQ(x) ((x) << S_CI10_ARB0_REQ)
18593 #define F_CI10_ARB0_REQ V_CI10_ARB0_REQ(1U)
18595 #define S_ARB0_CI10_GNT 22
18596 #define V_ARB0_CI10_GNT(x) ((x) << S_ARB0_CI10_GNT)
18597 #define F_ARB0_CI10_GNT V_ARB0_CI10_GNT(1U)
18599 #define S_CI10_DM0_WDATA_VLD 21
18600 #define V_CI10_DM0_WDATA_VLD(x) ((x) << S_CI10_DM0_WDATA_VLD)
18601 #define F_CI10_DM0_WDATA_VLD V_CI10_DM0_WDATA_VLD(1U)
18603 #define S_DM0_CI10_RDATA_VLD 20
18604 #define V_DM0_CI10_RDATA_VLD(x) ((x) << S_DM0_CI10_RDATA_VLD)
18605 #define F_DM0_CI10_RDATA_VLD V_DM0_CI10_RDATA_VLD(1U)
18607 #define S_CI11_ARB0_REQ 19
18608 #define V_CI11_ARB0_REQ(x) ((x) << S_CI11_ARB0_REQ)
18609 #define F_CI11_ARB0_REQ V_CI11_ARB0_REQ(1U)
18611 #define S_ARB0_CI11_GNT 18
18612 #define V_ARB0_CI11_GNT(x) ((x) << S_ARB0_CI11_GNT)
18613 #define F_ARB0_CI11_GNT V_ARB0_CI11_GNT(1U)
18615 #define S_CI11_DM0_WDATA_VLD 17
18616 #define V_CI11_DM0_WDATA_VLD(x) ((x) << S_CI11_DM0_WDATA_VLD)
18617 #define F_CI11_DM0_WDATA_VLD V_CI11_DM0_WDATA_VLD(1U)
18619 #define S_DM0_CI11_RDATA_VLD 16
18620 #define V_DM0_CI11_RDATA_VLD(x) ((x) << S_DM0_CI11_RDATA_VLD)
18621 #define F_DM0_CI11_RDATA_VLD V_DM0_CI11_RDATA_VLD(1U)
18623 #define S_CI12_ARB0_REQ 15
18624 #define V_CI12_ARB0_REQ(x) ((x) << S_CI12_ARB0_REQ)
18625 #define F_CI12_ARB0_REQ V_CI12_ARB0_REQ(1U)
18627 #define S_ARB0_CI12_GNT 14
18628 #define V_ARB0_CI12_GNT(x) ((x) << S_ARB0_CI12_GNT)
18629 #define F_ARB0_CI12_GNT V_ARB0_CI12_GNT(1U)
18631 #define S_CI12_DM0_WDATA_VLD 13
18632 #define V_CI12_DM0_WDATA_VLD(x) ((x) << S_CI12_DM0_WDATA_VLD)
18633 #define F_CI12_DM0_WDATA_VLD V_CI12_DM0_WDATA_VLD(1U)
18635 #define S_DM0_CI12_RDATA_VLD 12
18636 #define V_DM0_CI12_RDATA_VLD(x) ((x) << S_DM0_CI12_RDATA_VLD)
18637 #define F_DM0_CI12_RDATA_VLD V_DM0_CI12_RDATA_VLD(1U)
18639 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
18641 #define S_CI8_ARB1_REQ 31
18642 #define V_CI8_ARB1_REQ(x) ((x) << S_CI8_ARB1_REQ)
18643 #define F_CI8_ARB1_REQ V_CI8_ARB1_REQ(1U)
18645 #define S_ARB1_CI8_GNT 30
18646 #define V_ARB1_CI8_GNT(x) ((x) << S_ARB1_CI8_GNT)
18647 #define F_ARB1_CI8_GNT V_ARB1_CI8_GNT(1U)
18649 #define S_CI8_DM1_WDATA_VLD 29
18650 #define V_CI8_DM1_WDATA_VLD(x) ((x) << S_CI8_DM1_WDATA_VLD)
18651 #define F_CI8_DM1_WDATA_VLD V_CI8_DM1_WDATA_VLD(1U)
18653 #define S_DM1_CI8_RDATA_VLD 28
18654 #define V_DM1_CI8_RDATA_VLD(x) ((x) << S_DM1_CI8_RDATA_VLD)
18655 #define F_DM1_CI8_RDATA_VLD V_DM1_CI8_RDATA_VLD(1U)
18657 #define S_CI9_ARB1_REQ 27
18658 #define V_CI9_ARB1_REQ(x) ((x) << S_CI9_ARB1_REQ)
18659 #define F_CI9_ARB1_REQ V_CI9_ARB1_REQ(1U)
18661 #define S_ARB1_CI9_GNT 26
18662 #define V_ARB1_CI9_GNT(x) ((x) << S_ARB1_CI9_GNT)
18663 #define F_ARB1_CI9_GNT V_ARB1_CI9_GNT(1U)
18665 #define S_CI9_DM1_WDATA_VLD 25
18666 #define V_CI9_DM1_WDATA_VLD(x) ((x) << S_CI9_DM1_WDATA_VLD)
18667 #define F_CI9_DM1_WDATA_VLD V_CI9_DM1_WDATA_VLD(1U)
18669 #define S_DM1_CI9_RDATA_VLD 24
18670 #define V_DM1_CI9_RDATA_VLD(x) ((x) << S_DM1_CI9_RDATA_VLD)
18671 #define F_DM1_CI9_RDATA_VLD V_DM1_CI9_RDATA_VLD(1U)
18673 #define S_CI10_ARB1_REQ 23
18674 #define V_CI10_ARB1_REQ(x) ((x) << S_CI10_ARB1_REQ)
18675 #define F_CI10_ARB1_REQ V_CI10_ARB1_REQ(1U)
18677 #define S_ARB1_CI10_GNT 22
18678 #define V_ARB1_CI10_GNT(x) ((x) << S_ARB1_CI10_GNT)
18679 #define F_ARB1_CI10_GNT V_ARB1_CI10_GNT(1U)
18681 #define S_CI10_DM1_WDATA_VLD 21
18682 #define V_CI10_DM1_WDATA_VLD(x) ((x) << S_CI10_DM1_WDATA_VLD)
18683 #define F_CI10_DM1_WDATA_VLD V_CI10_DM1_WDATA_VLD(1U)
18685 #define S_DM1_CI10_RDATA_VLD 20
18686 #define V_DM1_CI10_RDATA_VLD(x) ((x) << S_DM1_CI10_RDATA_VLD)
18687 #define F_DM1_CI10_RDATA_VLD V_DM1_CI10_RDATA_VLD(1U)
18689 #define S_CI11_ARB1_REQ 19
18690 #define V_CI11_ARB1_REQ(x) ((x) << S_CI11_ARB1_REQ)
18691 #define F_CI11_ARB1_REQ V_CI11_ARB1_REQ(1U)
18693 #define S_ARB1_CI11_GNT 18
18694 #define V_ARB1_CI11_GNT(x) ((x) << S_ARB1_CI11_GNT)
18695 #define F_ARB1_CI11_GNT V_ARB1_CI11_GNT(1U)
18697 #define S_CI11_DM1_WDATA_VLD 17
18698 #define V_CI11_DM1_WDATA_VLD(x) ((x) << S_CI11_DM1_WDATA_VLD)
18699 #define F_CI11_DM1_WDATA_VLD V_CI11_DM1_WDATA_VLD(1U)
18701 #define S_DM1_CI11_RDATA_VLD 16
18702 #define V_DM1_CI11_RDATA_VLD(x) ((x) << S_DM1_CI11_RDATA_VLD)
18703 #define F_DM1_CI11_RDATA_VLD V_DM1_CI11_RDATA_VLD(1U)
18705 #define S_CI12_ARB1_REQ 15
18706 #define V_CI12_ARB1_REQ(x) ((x) << S_CI12_ARB1_REQ)
18707 #define F_CI12_ARB1_REQ V_CI12_ARB1_REQ(1U)
18709 #define S_ARB1_CI12_GNT 14
18710 #define V_ARB1_CI12_GNT(x) ((x) << S_ARB1_CI12_GNT)
18711 #define F_ARB1_CI12_GNT V_ARB1_CI12_GNT(1U)
18713 #define S_CI12_DM1_WDATA_VLD 13
18714 #define V_CI12_DM1_WDATA_VLD(x) ((x) << S_CI12_DM1_WDATA_VLD)
18715 #define F_CI12_DM1_WDATA_VLD V_CI12_DM1_WDATA_VLD(1U)
18717 #define S_DM1_CI12_RDATA_VLD 12
18718 #define V_DM1_CI12_RDATA_VLD(x) ((x) << S_DM1_CI12_RDATA_VLD)
18719 #define F_DM1_CI12_RDATA_VLD V_DM1_CI12_RDATA_VLD(1U)
18721 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
18723 #define S_CI8_ARB2_REQ 31
18724 #define V_CI8_ARB2_REQ(x) ((x) << S_CI8_ARB2_REQ)
18725 #define F_CI8_ARB2_REQ V_CI8_ARB2_REQ(1U)
18727 #define S_ARB2_CI8_GNT 30
18728 #define V_ARB2_CI8_GNT(x) ((x) << S_ARB2_CI8_GNT)
18729 #define F_ARB2_CI8_GNT V_ARB2_CI8_GNT(1U)
18731 #define S_CI8_DM2_WDATA_VLD 29
18732 #define V_CI8_DM2_WDATA_VLD(x) ((x) << S_CI8_DM2_WDATA_VLD)
18733 #define F_CI8_DM2_WDATA_VLD V_CI8_DM2_WDATA_VLD(1U)
18735 #define S_DM2_CI8_RDATA_VLD 28
18736 #define V_DM2_CI8_RDATA_VLD(x) ((x) << S_DM2_CI8_RDATA_VLD)
18737 #define F_DM2_CI8_RDATA_VLD V_DM2_CI8_RDATA_VLD(1U)
18739 #define S_CI9_ARB2_REQ 27
18740 #define V_CI9_ARB2_REQ(x) ((x) << S_CI9_ARB2_REQ)
18741 #define F_CI9_ARB2_REQ V_CI9_ARB2_REQ(1U)
18743 #define S_ARB2_CI9_GNT 26
18744 #define V_ARB2_CI9_GNT(x) ((x) << S_ARB2_CI9_GNT)
18745 #define F_ARB2_CI9_GNT V_ARB2_CI9_GNT(1U)
18747 #define S_CI9_DM2_WDATA_VLD 25
18748 #define V_CI9_DM2_WDATA_VLD(x) ((x) << S_CI9_DM2_WDATA_VLD)
18749 #define F_CI9_DM2_WDATA_VLD V_CI9_DM2_WDATA_VLD(1U)
18751 #define S_DM2_CI9_RDATA_VLD 24
18752 #define V_DM2_CI9_RDATA_VLD(x) ((x) << S_DM2_CI9_RDATA_VLD)
18753 #define F_DM2_CI9_RDATA_VLD V_DM2_CI9_RDATA_VLD(1U)
18755 #define S_CI10_ARB2_REQ 23
18756 #define V_CI10_ARB2_REQ(x) ((x) << S_CI10_ARB2_REQ)
18757 #define F_CI10_ARB2_REQ V_CI10_ARB2_REQ(1U)
18759 #define S_ARB2_CI10_GNT 22
18760 #define V_ARB2_CI10_GNT(x) ((x) << S_ARB2_CI10_GNT)
18761 #define F_ARB2_CI10_GNT V_ARB2_CI10_GNT(1U)
18763 #define S_CI10_DM2_WDATA_VLD 21
18764 #define V_CI10_DM2_WDATA_VLD(x) ((x) << S_CI10_DM2_WDATA_VLD)
18765 #define F_CI10_DM2_WDATA_VLD V_CI10_DM2_WDATA_VLD(1U)
18767 #define S_DM2_CI10_RDATA_VLD 20
18768 #define V_DM2_CI10_RDATA_VLD(x) ((x) << S_DM2_CI10_RDATA_VLD)
18769 #define F_DM2_CI10_RDATA_VLD V_DM2_CI10_RDATA_VLD(1U)
18771 #define S_CI11_ARB2_REQ 19
18772 #define V_CI11_ARB2_REQ(x) ((x) << S_CI11_ARB2_REQ)
18773 #define F_CI11_ARB2_REQ V_CI11_ARB2_REQ(1U)
18775 #define S_ARB2_CI11_GNT 18
18776 #define V_ARB2_CI11_GNT(x) ((x) << S_ARB2_CI11_GNT)
18777 #define F_ARB2_CI11_GNT V_ARB2_CI11_GNT(1U)
18779 #define S_CI11_DM2_WDATA_VLD 17
18780 #define V_CI11_DM2_WDATA_VLD(x) ((x) << S_CI11_DM2_WDATA_VLD)
18781 #define F_CI11_DM2_WDATA_VLD V_CI11_DM2_WDATA_VLD(1U)
18783 #define S_DM2_CI11_RDATA_VLD 16
18784 #define V_DM2_CI11_RDATA_VLD(x) ((x) << S_DM2_CI11_RDATA_VLD)
18785 #define F_DM2_CI11_RDATA_VLD V_DM2_CI11_RDATA_VLD(1U)
18787 #define S_CI12_ARB2_REQ 15
18788 #define V_CI12_ARB2_REQ(x) ((x) << S_CI12_ARB2_REQ)
18789 #define F_CI12_ARB2_REQ V_CI12_ARB2_REQ(1U)
18791 #define S_ARB2_CI12_GNT 14
18792 #define V_ARB2_CI12_GNT(x) ((x) << S_ARB2_CI12_GNT)
18793 #define F_ARB2_CI12_GNT V_ARB2_CI12_GNT(1U)
18795 #define S_CI12_DM2_WDATA_VLD 13
18796 #define V_CI12_DM2_WDATA_VLD(x) ((x) << S_CI12_DM2_WDATA_VLD)
18797 #define F_CI12_DM2_WDATA_VLD V_CI12_DM2_WDATA_VLD(1U)
18799 #define S_DM2_CI12_RDATA_VLD 12
18800 #define V_DM2_CI12_RDATA_VLD(x) ((x) << S_DM2_CI12_RDATA_VLD)
18801 #define F_DM2_CI12_RDATA_VLD V_DM2_CI12_RDATA_VLD(1U)
18803 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
18805 #define S_CI8_ARB3_REQ 31
18806 #define V_CI8_ARB3_REQ(x) ((x) << S_CI8_ARB3_REQ)
18807 #define F_CI8_ARB3_REQ V_CI8_ARB3_REQ(1U)
18809 #define S_ARB3_CI8_GNT 30
18810 #define V_ARB3_CI8_GNT(x) ((x) << S_ARB3_CI8_GNT)
18811 #define F_ARB3_CI8_GNT V_ARB3_CI8_GNT(1U)
18813 #define S_CI8_DM3_WDATA_VLD 29
18814 #define V_CI8_DM3_WDATA_VLD(x) ((x) << S_CI8_DM3_WDATA_VLD)
18815 #define F_CI8_DM3_WDATA_VLD V_CI8_DM3_WDATA_VLD(1U)
18817 #define S_DM3_CI8_RDATA_VLD 28
18818 #define V_DM3_CI8_RDATA_VLD(x) ((x) << S_DM3_CI8_RDATA_VLD)
18819 #define F_DM3_CI8_RDATA_VLD V_DM3_CI8_RDATA_VLD(1U)
18821 #define S_CI9_ARB3_REQ 27
18822 #define V_CI9_ARB3_REQ(x) ((x) << S_CI9_ARB3_REQ)
18823 #define F_CI9_ARB3_REQ V_CI9_ARB3_REQ(1U)
18825 #define S_ARB3_CI9_GNT 26
18826 #define V_ARB3_CI9_GNT(x) ((x) << S_ARB3_CI9_GNT)
18827 #define F_ARB3_CI9_GNT V_ARB3_CI9_GNT(1U)
18829 #define S_CI9_DM3_WDATA_VLD 25
18830 #define V_CI9_DM3_WDATA_VLD(x) ((x) << S_CI9_DM3_WDATA_VLD)
18831 #define F_CI9_DM3_WDATA_VLD V_CI9_DM3_WDATA_VLD(1U)
18833 #define S_DM3_CI9_RDATA_VLD 24
18834 #define V_DM3_CI9_RDATA_VLD(x) ((x) << S_DM3_CI9_RDATA_VLD)
18835 #define F_DM3_CI9_RDATA_VLD V_DM3_CI9_RDATA_VLD(1U)
18837 #define S_CI10_ARB3_REQ 23
18838 #define V_CI10_ARB3_REQ(x) ((x) << S_CI10_ARB3_REQ)
18839 #define F_CI10_ARB3_REQ V_CI10_ARB3_REQ(1U)
18841 #define S_ARB3_CI10_GNT 22
18842 #define V_ARB3_CI10_GNT(x) ((x) << S_ARB3_CI10_GNT)
18843 #define F_ARB3_CI10_GNT V_ARB3_CI10_GNT(1U)
18845 #define S_CI10_DM3_WDATA_VLD 21
18846 #define V_CI10_DM3_WDATA_VLD(x) ((x) << S_CI10_DM3_WDATA_VLD)
18847 #define F_CI10_DM3_WDATA_VLD V_CI10_DM3_WDATA_VLD(1U)
18849 #define S_DM3_CI10_RDATA_VLD 20
18850 #define V_DM3_CI10_RDATA_VLD(x) ((x) << S_DM3_CI10_RDATA_VLD)
18851 #define F_DM3_CI10_RDATA_VLD V_DM3_CI10_RDATA_VLD(1U)
18853 #define S_CI11_ARB3_REQ 19
18854 #define V_CI11_ARB3_REQ(x) ((x) << S_CI11_ARB3_REQ)
18855 #define F_CI11_ARB3_REQ V_CI11_ARB3_REQ(1U)
18857 #define S_ARB3_CI11_GNT 18
18858 #define V_ARB3_CI11_GNT(x) ((x) << S_ARB3_CI11_GNT)
18859 #define F_ARB3_CI11_GNT V_ARB3_CI11_GNT(1U)
18861 #define S_CI11_DM3_WDATA_VLD 17
18862 #define V_CI11_DM3_WDATA_VLD(x) ((x) << S_CI11_DM3_WDATA_VLD)
18863 #define F_CI11_DM3_WDATA_VLD V_CI11_DM3_WDATA_VLD(1U)
18865 #define S_DM3_CI11_RDATA_VLD 16
18866 #define V_DM3_CI11_RDATA_VLD(x) ((x) << S_DM3_CI11_RDATA_VLD)
18867 #define F_DM3_CI11_RDATA_VLD V_DM3_CI11_RDATA_VLD(1U)
18869 #define S_CI12_ARB3_REQ 15
18870 #define V_CI12_ARB3_REQ(x) ((x) << S_CI12_ARB3_REQ)
18871 #define F_CI12_ARB3_REQ V_CI12_ARB3_REQ(1U)
18873 #define S_ARB3_CI12_GNT 14
18874 #define V_ARB3_CI12_GNT(x) ((x) << S_ARB3_CI12_GNT)
18875 #define F_ARB3_CI12_GNT V_ARB3_CI12_GNT(1U)
18877 #define S_CI12_DM3_WDATA_VLD 13
18878 #define V_CI12_DM3_WDATA_VLD(x) ((x) << S_CI12_DM3_WDATA_VLD)
18879 #define F_CI12_DM3_WDATA_VLD V_CI12_DM3_WDATA_VLD(1U)
18881 #define S_DM3_CI12_RDATA_VLD 12
18882 #define V_DM3_CI12_RDATA_VLD(x) ((x) << S_DM3_CI12_RDATA_VLD)
18883 #define F_DM3_CI12_RDATA_VLD V_DM3_CI12_RDATA_VLD(1U)
18885 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
18887 #define S_CMD_IN_FIFO_CNT0 30
18888 #define M_CMD_IN_FIFO_CNT0 0x3U
18889 #define V_CMD_IN_FIFO_CNT0(x) ((x) << S_CMD_IN_FIFO_CNT0)
18890 #define G_CMD_IN_FIFO_CNT0(x) (((x) >> S_CMD_IN_FIFO_CNT0) & M_CMD_IN_FIFO_CNT0)
18892 #define S_CMD_SPLIT_FIFO_CNT0 28
18893 #define M_CMD_SPLIT_FIFO_CNT0 0x3U
18894 #define V_CMD_SPLIT_FIFO_CNT0(x) ((x) << S_CMD_SPLIT_FIFO_CNT0)
18895 #define G_CMD_SPLIT_FIFO_CNT0(x) (((x) >> S_CMD_SPLIT_FIFO_CNT0) & M_CMD_SPLIT_FIFO_CNT0)
18897 #define S_CMD_THROTTLE_FIFO_CNT0 22
18898 #define M_CMD_THROTTLE_FIFO_CNT0 0x3fU
18899 #define V_CMD_THROTTLE_FIFO_CNT0(x) ((x) << S_CMD_THROTTLE_FIFO_CNT0)
18900 #define G_CMD_THROTTLE_FIFO_CNT0(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT0) & M_CMD_THROTTLE_FIFO_CNT0)
18902 #define S_RD_CHNL_FIFO_CNT0 15
18903 #define M_RD_CHNL_FIFO_CNT0 0x7fU
18904 #define V_RD_CHNL_FIFO_CNT0(x) ((x) << S_RD_CHNL_FIFO_CNT0)
18905 #define G_RD_CHNL_FIFO_CNT0(x) (((x) >> S_RD_CHNL_FIFO_CNT0) & M_RD_CHNL_FIFO_CNT0)
18907 #define S_RD_DATA_EXT_FIFO_CNT0 13
18908 #define M_RD_DATA_EXT_FIFO_CNT0 0x3U
18909 #define V_RD_DATA_EXT_FIFO_CNT0(x) ((x) << S_RD_DATA_EXT_FIFO_CNT0)
18910 #define G_RD_DATA_EXT_FIFO_CNT0(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT0) & M_RD_DATA_EXT_FIFO_CNT0)
18912 #define S_RD_DATA_512B_FIFO_CNT0 5
18913 #define M_RD_DATA_512B_FIFO_CNT0 0xffU
18914 #define V_RD_DATA_512B_FIFO_CNT0(x) ((x) << S_RD_DATA_512B_FIFO_CNT0)
18915 #define G_RD_DATA_512B_FIFO_CNT0(x) (((x) >> S_RD_DATA_512B_FIFO_CNT0) & M_RD_DATA_512B_FIFO_CNT0)
18917 #define S_RD_REQ_TAG_FIFO_CNT0 1
18918 #define M_RD_REQ_TAG_FIFO_CNT0 0xfU
18919 #define V_RD_REQ_TAG_FIFO_CNT0(x) ((x) << S_RD_REQ_TAG_FIFO_CNT0)
18920 #define G_RD_REQ_TAG_FIFO_CNT0(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT0) & M_RD_REQ_TAG_FIFO_CNT0)
18922 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
18924 #define S_CMD_IN_FIFO_CNT1 30
18925 #define M_CMD_IN_FIFO_CNT1 0x3U
18926 #define V_CMD_IN_FIFO_CNT1(x) ((x) << S_CMD_IN_FIFO_CNT1)
18927 #define G_CMD_IN_FIFO_CNT1(x) (((x) >> S_CMD_IN_FIFO_CNT1) & M_CMD_IN_FIFO_CNT1)
18929 #define S_CMD_SPLIT_FIFO_CNT1 28
18930 #define M_CMD_SPLIT_FIFO_CNT1 0x3U
18931 #define V_CMD_SPLIT_FIFO_CNT1(x) ((x) << S_CMD_SPLIT_FIFO_CNT1)
18932 #define G_CMD_SPLIT_FIFO_CNT1(x) (((x) >> S_CMD_SPLIT_FIFO_CNT1) & M_CMD_SPLIT_FIFO_CNT1)
18934 #define S_CMD_THROTTLE_FIFO_CNT1 22
18935 #define M_CMD_THROTTLE_FIFO_CNT1 0x3fU
18936 #define V_CMD_THROTTLE_FIFO_CNT1(x) ((x) << S_CMD_THROTTLE_FIFO_CNT1)
18937 #define G_CMD_THROTTLE_FIFO_CNT1(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT1) & M_CMD_THROTTLE_FIFO_CNT1)
18939 #define S_RD_CHNL_FIFO_CNT1 15
18940 #define M_RD_CHNL_FIFO_CNT1 0x7fU
18941 #define V_RD_CHNL_FIFO_CNT1(x) ((x) << S_RD_CHNL_FIFO_CNT1)
18942 #define G_RD_CHNL_FIFO_CNT1(x) (((x) >> S_RD_CHNL_FIFO_CNT1) & M_RD_CHNL_FIFO_CNT1)
18944 #define S_RD_DATA_EXT_FIFO_CNT1 13
18945 #define M_RD_DATA_EXT_FIFO_CNT1 0x3U
18946 #define V_RD_DATA_EXT_FIFO_CNT1(x) ((x) << S_RD_DATA_EXT_FIFO_CNT1)
18947 #define G_RD_DATA_EXT_FIFO_CNT1(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT1) & M_RD_DATA_EXT_FIFO_CNT1)
18949 #define S_RD_DATA_512B_FIFO_CNT1 5
18950 #define M_RD_DATA_512B_FIFO_CNT1 0xffU
18951 #define V_RD_DATA_512B_FIFO_CNT1(x) ((x) << S_RD_DATA_512B_FIFO_CNT1)
18952 #define G_RD_DATA_512B_FIFO_CNT1(x) (((x) >> S_RD_DATA_512B_FIFO_CNT1) & M_RD_DATA_512B_FIFO_CNT1)
18954 #define S_RD_REQ_TAG_FIFO_CNT1 1
18955 #define M_RD_REQ_TAG_FIFO_CNT1 0xfU
18956 #define V_RD_REQ_TAG_FIFO_CNT1(x) ((x) << S_RD_REQ_TAG_FIFO_CNT1)
18957 #define G_RD_REQ_TAG_FIFO_CNT1(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT1) & M_RD_REQ_TAG_FIFO_CNT1)
18959 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
18961 #define S_CMD_IN_FIFO_CNT2 30
18962 #define M_CMD_IN_FIFO_CNT2 0x3U
18963 #define V_CMD_IN_FIFO_CNT2(x) ((x) << S_CMD_IN_FIFO_CNT2)
18964 #define G_CMD_IN_FIFO_CNT2(x) (((x) >> S_CMD_IN_FIFO_CNT2) & M_CMD_IN_FIFO_CNT2)
18966 #define S_CMD_SPLIT_FIFO_CNT2 28
18967 #define M_CMD_SPLIT_FIFO_CNT2 0x3U
18968 #define V_CMD_SPLIT_FIFO_CNT2(x) ((x) << S_CMD_SPLIT_FIFO_CNT2)
18969 #define G_CMD_SPLIT_FIFO_CNT2(x) (((x) >> S_CMD_SPLIT_FIFO_CNT2) & M_CMD_SPLIT_FIFO_CNT2)
18971 #define S_CMD_THROTTLE_FIFO_CNT2 22
18972 #define M_CMD_THROTTLE_FIFO_CNT2 0x3fU
18973 #define V_CMD_THROTTLE_FIFO_CNT2(x) ((x) << S_CMD_THROTTLE_FIFO_CNT2)
18974 #define G_CMD_THROTTLE_FIFO_CNT2(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT2) & M_CMD_THROTTLE_FIFO_CNT2)
18976 #define S_RD_CHNL_FIFO_CNT2 15
18977 #define M_RD_CHNL_FIFO_CNT2 0x7fU
18978 #define V_RD_CHNL_FIFO_CNT2(x) ((x) << S_RD_CHNL_FIFO_CNT2)
18979 #define G_RD_CHNL_FIFO_CNT2(x) (((x) >> S_RD_CHNL_FIFO_CNT2) & M_RD_CHNL_FIFO_CNT2)
18981 #define S_RD_DATA_EXT_FIFO_CNT2 13
18982 #define M_RD_DATA_EXT_FIFO_CNT2 0x3U
18983 #define V_RD_DATA_EXT_FIFO_CNT2(x) ((x) << S_RD_DATA_EXT_FIFO_CNT2)
18984 #define G_RD_DATA_EXT_FIFO_CNT2(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT2) & M_RD_DATA_EXT_FIFO_CNT2)
18986 #define S_RD_DATA_512B_FIFO_CNT2 5
18987 #define M_RD_DATA_512B_FIFO_CNT2 0xffU
18988 #define V_RD_DATA_512B_FIFO_CNT2(x) ((x) << S_RD_DATA_512B_FIFO_CNT2)
18989 #define G_RD_DATA_512B_FIFO_CNT2(x) (((x) >> S_RD_DATA_512B_FIFO_CNT2) & M_RD_DATA_512B_FIFO_CNT2)
18991 #define S_RD_REQ_TAG_FIFO_CNT2 1
18992 #define M_RD_REQ_TAG_FIFO_CNT2 0xfU
18993 #define V_RD_REQ_TAG_FIFO_CNT2(x) ((x) << S_RD_REQ_TAG_FIFO_CNT2)
18994 #define G_RD_REQ_TAG_FIFO_CNT2(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT2) & M_RD_REQ_TAG_FIFO_CNT2)
18996 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
18998 #define S_CMD_IN_FIFO_CNT3 30
18999 #define M_CMD_IN_FIFO_CNT3 0x3U
19000 #define V_CMD_IN_FIFO_CNT3(x) ((x) << S_CMD_IN_FIFO_CNT3)
19001 #define G_CMD_IN_FIFO_CNT3(x) (((x) >> S_CMD_IN_FIFO_CNT3) & M_CMD_IN_FIFO_CNT3)
19003 #define S_CMD_SPLIT_FIFO_CNT3 28
19004 #define M_CMD_SPLIT_FIFO_CNT3 0x3U
19005 #define V_CMD_SPLIT_FIFO_CNT3(x) ((x) << S_CMD_SPLIT_FIFO_CNT3)
19006 #define G_CMD_SPLIT_FIFO_CNT3(x) (((x) >> S_CMD_SPLIT_FIFO_CNT3) & M_CMD_SPLIT_FIFO_CNT3)
19008 #define S_CMD_THROTTLE_FIFO_CNT3 22
19009 #define M_CMD_THROTTLE_FIFO_CNT3 0x3fU
19010 #define V_CMD_THROTTLE_FIFO_CNT3(x) ((x) << S_CMD_THROTTLE_FIFO_CNT3)
19011 #define G_CMD_THROTTLE_FIFO_CNT3(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT3) & M_CMD_THROTTLE_FIFO_CNT3)
19013 #define S_RD_CHNL_FIFO_CNT3 15
19014 #define M_RD_CHNL_FIFO_CNT3 0x7fU
19015 #define V_RD_CHNL_FIFO_CNT3(x) ((x) << S_RD_CHNL_FIFO_CNT3)
19016 #define G_RD_CHNL_FIFO_CNT3(x) (((x) >> S_RD_CHNL_FIFO_CNT3) & M_RD_CHNL_FIFO_CNT3)
19018 #define S_RD_DATA_EXT_FIFO_CNT3 13
19019 #define M_RD_DATA_EXT_FIFO_CNT3 0x3U
19020 #define V_RD_DATA_EXT_FIFO_CNT3(x) ((x) << S_RD_DATA_EXT_FIFO_CNT3)
19021 #define G_RD_DATA_EXT_FIFO_CNT3(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT3) & M_RD_DATA_EXT_FIFO_CNT3)
19023 #define S_RD_DATA_512B_FIFO_CNT3 5
19024 #define M_RD_DATA_512B_FIFO_CNT3 0xffU
19025 #define V_RD_DATA_512B_FIFO_CNT3(x) ((x) << S_RD_DATA_512B_FIFO_CNT3)
19026 #define G_RD_DATA_512B_FIFO_CNT3(x) (((x) >> S_RD_DATA_512B_FIFO_CNT3) & M_RD_DATA_512B_FIFO_CNT3)
19028 #define S_RD_REQ_TAG_FIFO_CNT3 1
19029 #define M_RD_REQ_TAG_FIFO_CNT3 0xfU
19030 #define V_RD_REQ_TAG_FIFO_CNT3(x) ((x) << S_RD_REQ_TAG_FIFO_CNT3)
19031 #define G_RD_REQ_TAG_FIFO_CNT3(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT3) & M_RD_REQ_TAG_FIFO_CNT3)
19033 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
19035 #define S_CMD_IN_FIFO_CNT4 30
19036 #define M_CMD_IN_FIFO_CNT4 0x3U
19037 #define V_CMD_IN_FIFO_CNT4(x) ((x) << S_CMD_IN_FIFO_CNT4)
19038 #define G_CMD_IN_FIFO_CNT4(x) (((x) >> S_CMD_IN_FIFO_CNT4) & M_CMD_IN_FIFO_CNT4)
19040 #define S_CMD_SPLIT_FIFO_CNT4 28
19041 #define M_CMD_SPLIT_FIFO_CNT4 0x3U
19042 #define V_CMD_SPLIT_FIFO_CNT4(x) ((x) << S_CMD_SPLIT_FIFO_CNT4)
19043 #define G_CMD_SPLIT_FIFO_CNT4(x) (((x) >> S_CMD_SPLIT_FIFO_CNT4) & M_CMD_SPLIT_FIFO_CNT4)
19045 #define S_CMD_THROTTLE_FIFO_CNT4 22
19046 #define M_CMD_THROTTLE_FIFO_CNT4 0x3fU
19047 #define V_CMD_THROTTLE_FIFO_CNT4(x) ((x) << S_CMD_THROTTLE_FIFO_CNT4)
19048 #define G_CMD_THROTTLE_FIFO_CNT4(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT4) & M_CMD_THROTTLE_FIFO_CNT4)
19050 #define S_RD_CHNL_FIFO_CNT4 15
19051 #define M_RD_CHNL_FIFO_CNT4 0x7fU
19052 #define V_RD_CHNL_FIFO_CNT4(x) ((x) << S_RD_CHNL_FIFO_CNT4)
19053 #define G_RD_CHNL_FIFO_CNT4(x) (((x) >> S_RD_CHNL_FIFO_CNT4) & M_RD_CHNL_FIFO_CNT4)
19055 #define S_RD_DATA_EXT_FIFO_CNT4 13
19056 #define M_RD_DATA_EXT_FIFO_CNT4 0x3U
19057 #define V_RD_DATA_EXT_FIFO_CNT4(x) ((x) << S_RD_DATA_EXT_FIFO_CNT4)
19058 #define G_RD_DATA_EXT_FIFO_CNT4(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT4) & M_RD_DATA_EXT_FIFO_CNT4)
19060 #define S_RD_DATA_512B_FIFO_CNT4 5
19061 #define M_RD_DATA_512B_FIFO_CNT4 0xffU
19062 #define V_RD_DATA_512B_FIFO_CNT4(x) ((x) << S_RD_DATA_512B_FIFO_CNT4)
19063 #define G_RD_DATA_512B_FIFO_CNT4(x) (((x) >> S_RD_DATA_512B_FIFO_CNT4) & M_RD_DATA_512B_FIFO_CNT4)
19065 #define S_RD_REQ_TAG_FIFO_CNT4 1
19066 #define M_RD_REQ_TAG_FIFO_CNT4 0xfU
19067 #define V_RD_REQ_TAG_FIFO_CNT4(x) ((x) << S_RD_REQ_TAG_FIFO_CNT4)
19068 #define G_RD_REQ_TAG_FIFO_CNT4(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT4) & M_RD_REQ_TAG_FIFO_CNT4)
19070 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
19072 #define S_CMD_IN_FIFO_CNT5 30
19073 #define M_CMD_IN_FIFO_CNT5 0x3U
19074 #define V_CMD_IN_FIFO_CNT5(x) ((x) << S_CMD_IN_FIFO_CNT5)
19075 #define G_CMD_IN_FIFO_CNT5(x) (((x) >> S_CMD_IN_FIFO_CNT5) & M_CMD_IN_FIFO_CNT5)
19077 #define S_CMD_SPLIT_FIFO_CNT5 28
19078 #define M_CMD_SPLIT_FIFO_CNT5 0x3U
19079 #define V_CMD_SPLIT_FIFO_CNT5(x) ((x) << S_CMD_SPLIT_FIFO_CNT5)
19080 #define G_CMD_SPLIT_FIFO_CNT5(x) (((x) >> S_CMD_SPLIT_FIFO_CNT5) & M_CMD_SPLIT_FIFO_CNT5)
19082 #define S_CMD_THROTTLE_FIFO_CNT5 22
19083 #define M_CMD_THROTTLE_FIFO_CNT5 0x3fU
19084 #define V_CMD_THROTTLE_FIFO_CNT5(x) ((x) << S_CMD_THROTTLE_FIFO_CNT5)
19085 #define G_CMD_THROTTLE_FIFO_CNT5(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT5) & M_CMD_THROTTLE_FIFO_CNT5)
19087 #define S_RD_CHNL_FIFO_CNT5 15
19088 #define M_RD_CHNL_FIFO_CNT5 0x7fU
19089 #define V_RD_CHNL_FIFO_CNT5(x) ((x) << S_RD_CHNL_FIFO_CNT5)
19090 #define G_RD_CHNL_FIFO_CNT5(x) (((x) >> S_RD_CHNL_FIFO_CNT5) & M_RD_CHNL_FIFO_CNT5)
19092 #define S_RD_DATA_EXT_FIFO_CNT5 13
19093 #define M_RD_DATA_EXT_FIFO_CNT5 0x3U
19094 #define V_RD_DATA_EXT_FIFO_CNT5(x) ((x) << S_RD_DATA_EXT_FIFO_CNT5)
19095 #define G_RD_DATA_EXT_FIFO_CNT5(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT5) & M_RD_DATA_EXT_FIFO_CNT5)
19097 #define S_RD_DATA_512B_FIFO_CNT5 5
19098 #define M_RD_DATA_512B_FIFO_CNT5 0xffU
19099 #define V_RD_DATA_512B_FIFO_CNT5(x) ((x) << S_RD_DATA_512B_FIFO_CNT5)
19100 #define G_RD_DATA_512B_FIFO_CNT5(x) (((x) >> S_RD_DATA_512B_FIFO_CNT5) & M_RD_DATA_512B_FIFO_CNT5)
19102 #define S_RD_REQ_TAG_FIFO_CNT5 1
19103 #define M_RD_REQ_TAG_FIFO_CNT5 0xfU
19104 #define V_RD_REQ_TAG_FIFO_CNT5(x) ((x) << S_RD_REQ_TAG_FIFO_CNT5)
19105 #define G_RD_REQ_TAG_FIFO_CNT5(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT5) & M_RD_REQ_TAG_FIFO_CNT5)
19107 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
19109 #define S_CMD_IN_FIFO_CNT6 30
19110 #define M_CMD_IN_FIFO_CNT6 0x3U
19111 #define V_CMD_IN_FIFO_CNT6(x) ((x) << S_CMD_IN_FIFO_CNT6)
19112 #define G_CMD_IN_FIFO_CNT6(x) (((x) >> S_CMD_IN_FIFO_CNT6) & M_CMD_IN_FIFO_CNT6)
19114 #define S_CMD_SPLIT_FIFO_CNT6 28
19115 #define M_CMD_SPLIT_FIFO_CNT6 0x3U
19116 #define V_CMD_SPLIT_FIFO_CNT6(x) ((x) << S_CMD_SPLIT_FIFO_CNT6)
19117 #define G_CMD_SPLIT_FIFO_CNT6(x) (((x) >> S_CMD_SPLIT_FIFO_CNT6) & M_CMD_SPLIT_FIFO_CNT6)
19119 #define S_CMD_THROTTLE_FIFO_CNT6 22
19120 #define M_CMD_THROTTLE_FIFO_CNT6 0x3fU
19121 #define V_CMD_THROTTLE_FIFO_CNT6(x) ((x) << S_CMD_THROTTLE_FIFO_CNT6)
19122 #define G_CMD_THROTTLE_FIFO_CNT6(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT6) & M_CMD_THROTTLE_FIFO_CNT6)
19124 #define S_RD_CHNL_FIFO_CNT6 15
19125 #define M_RD_CHNL_FIFO_CNT6 0x7fU
19126 #define V_RD_CHNL_FIFO_CNT6(x) ((x) << S_RD_CHNL_FIFO_CNT6)
19127 #define G_RD_CHNL_FIFO_CNT6(x) (((x) >> S_RD_CHNL_FIFO_CNT6) & M_RD_CHNL_FIFO_CNT6)
19129 #define S_RD_DATA_EXT_FIFO_CNT6 13
19130 #define M_RD_DATA_EXT_FIFO_CNT6 0x3U
19131 #define V_RD_DATA_EXT_FIFO_CNT6(x) ((x) << S_RD_DATA_EXT_FIFO_CNT6)
19132 #define G_RD_DATA_EXT_FIFO_CNT6(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT6) & M_RD_DATA_EXT_FIFO_CNT6)
19134 #define S_RD_DATA_512B_FIFO_CNT6 5
19135 #define M_RD_DATA_512B_FIFO_CNT6 0xffU
19136 #define V_RD_DATA_512B_FIFO_CNT6(x) ((x) << S_RD_DATA_512B_FIFO_CNT6)
19137 #define G_RD_DATA_512B_FIFO_CNT6(x) (((x) >> S_RD_DATA_512B_FIFO_CNT6) & M_RD_DATA_512B_FIFO_CNT6)
19139 #define S_RD_REQ_TAG_FIFO_CNT6 1
19140 #define M_RD_REQ_TAG_FIFO_CNT6 0xfU
19141 #define V_RD_REQ_TAG_FIFO_CNT6(x) ((x) << S_RD_REQ_TAG_FIFO_CNT6)
19142 #define G_RD_REQ_TAG_FIFO_CNT6(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT6) & M_RD_REQ_TAG_FIFO_CNT6)
19144 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
19146 #define S_CMD_IN_FIFO_CNT7 30
19147 #define M_CMD_IN_FIFO_CNT7 0x3U
19148 #define V_CMD_IN_FIFO_CNT7(x) ((x) << S_CMD_IN_FIFO_CNT7)
19149 #define G_CMD_IN_FIFO_CNT7(x) (((x) >> S_CMD_IN_FIFO_CNT7) & M_CMD_IN_FIFO_CNT7)
19151 #define S_CMD_SPLIT_FIFO_CNT7 28
19152 #define M_CMD_SPLIT_FIFO_CNT7 0x3U
19153 #define V_CMD_SPLIT_FIFO_CNT7(x) ((x) << S_CMD_SPLIT_FIFO_CNT7)
19154 #define G_CMD_SPLIT_FIFO_CNT7(x) (((x) >> S_CMD_SPLIT_FIFO_CNT7) & M_CMD_SPLIT_FIFO_CNT7)
19156 #define S_CMD_THROTTLE_FIFO_CNT7 22
19157 #define M_CMD_THROTTLE_FIFO_CNT7 0x3fU
19158 #define V_CMD_THROTTLE_FIFO_CNT7(x) ((x) << S_CMD_THROTTLE_FIFO_CNT7)
19159 #define G_CMD_THROTTLE_FIFO_CNT7(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT7) & M_CMD_THROTTLE_FIFO_CNT7)
19161 #define S_RD_CHNL_FIFO_CNT7 15
19162 #define M_RD_CHNL_FIFO_CNT7 0x7fU
19163 #define V_RD_CHNL_FIFO_CNT7(x) ((x) << S_RD_CHNL_FIFO_CNT7)
19164 #define G_RD_CHNL_FIFO_CNT7(x) (((x) >> S_RD_CHNL_FIFO_CNT7) & M_RD_CHNL_FIFO_CNT7)
19166 #define S_RD_DATA_EXT_FIFO_CNT7 13
19167 #define M_RD_DATA_EXT_FIFO_CNT7 0x3U
19168 #define V_RD_DATA_EXT_FIFO_CNT7(x) ((x) << S_RD_DATA_EXT_FIFO_CNT7)
19169 #define G_RD_DATA_EXT_FIFO_CNT7(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT7) & M_RD_DATA_EXT_FIFO_CNT7)
19171 #define S_RD_DATA_512B_FIFO_CNT7 5
19172 #define M_RD_DATA_512B_FIFO_CNT7 0xffU
19173 #define V_RD_DATA_512B_FIFO_CNT7(x) ((x) << S_RD_DATA_512B_FIFO_CNT7)
19174 #define G_RD_DATA_512B_FIFO_CNT7(x) (((x) >> S_RD_DATA_512B_FIFO_CNT7) & M_RD_DATA_512B_FIFO_CNT7)
19176 #define S_RD_REQ_TAG_FIFO_CNT7 1
19177 #define M_RD_REQ_TAG_FIFO_CNT7 0xfU
19178 #define V_RD_REQ_TAG_FIFO_CNT7(x) ((x) << S_RD_REQ_TAG_FIFO_CNT7)
19179 #define G_RD_REQ_TAG_FIFO_CNT7(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT7) & M_RD_REQ_TAG_FIFO_CNT7)
19181 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
19183 #define S_CMD_IN_FIFO_CNT8 30
19184 #define M_CMD_IN_FIFO_CNT8 0x3U
19185 #define V_CMD_IN_FIFO_CNT8(x) ((x) << S_CMD_IN_FIFO_CNT8)
19186 #define G_CMD_IN_FIFO_CNT8(x) (((x) >> S_CMD_IN_FIFO_CNT8) & M_CMD_IN_FIFO_CNT8)
19188 #define S_CMD_SPLIT_FIFO_CNT8 28
19189 #define M_CMD_SPLIT_FIFO_CNT8 0x3U
19190 #define V_CMD_SPLIT_FIFO_CNT8(x) ((x) << S_CMD_SPLIT_FIFO_CNT8)
19191 #define G_CMD_SPLIT_FIFO_CNT8(x) (((x) >> S_CMD_SPLIT_FIFO_CNT8) & M_CMD_SPLIT_FIFO_CNT8)
19193 #define S_CMD_THROTTLE_FIFO_CNT8 22
19194 #define M_CMD_THROTTLE_FIFO_CNT8 0x3fU
19195 #define V_CMD_THROTTLE_FIFO_CNT8(x) ((x) << S_CMD_THROTTLE_FIFO_CNT8)
19196 #define G_CMD_THROTTLE_FIFO_CNT8(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT8) & M_CMD_THROTTLE_FIFO_CNT8)
19198 #define S_RD_CHNL_FIFO_CNT8 15
19199 #define M_RD_CHNL_FIFO_CNT8 0x7fU
19200 #define V_RD_CHNL_FIFO_CNT8(x) ((x) << S_RD_CHNL_FIFO_CNT8)
19201 #define G_RD_CHNL_FIFO_CNT8(x) (((x) >> S_RD_CHNL_FIFO_CNT8) & M_RD_CHNL_FIFO_CNT8)
19203 #define S_RD_DATA_EXT_FIFO_CNT8 13
19204 #define M_RD_DATA_EXT_FIFO_CNT8 0x3U
19205 #define V_RD_DATA_EXT_FIFO_CNT8(x) ((x) << S_RD_DATA_EXT_FIFO_CNT8)
19206 #define G_RD_DATA_EXT_FIFO_CNT8(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT8) & M_RD_DATA_EXT_FIFO_CNT8)
19208 #define S_RD_DATA_512B_FIFO_CNT8 5
19209 #define M_RD_DATA_512B_FIFO_CNT8 0xffU
19210 #define V_RD_DATA_512B_FIFO_CNT8(x) ((x) << S_RD_DATA_512B_FIFO_CNT8)
19211 #define G_RD_DATA_512B_FIFO_CNT8(x) (((x) >> S_RD_DATA_512B_FIFO_CNT8) & M_RD_DATA_512B_FIFO_CNT8)
19213 #define S_RD_REQ_TAG_FIFO_CNT8 1
19214 #define M_RD_REQ_TAG_FIFO_CNT8 0xfU
19215 #define V_RD_REQ_TAG_FIFO_CNT8(x) ((x) << S_RD_REQ_TAG_FIFO_CNT8)
19216 #define G_RD_REQ_TAG_FIFO_CNT8(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT8) & M_RD_REQ_TAG_FIFO_CNT8)
19218 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
19220 #define S_CMD_IN_FIFO_CNT9 30
19221 #define M_CMD_IN_FIFO_CNT9 0x3U
19222 #define V_CMD_IN_FIFO_CNT9(x) ((x) << S_CMD_IN_FIFO_CNT9)
19223 #define G_CMD_IN_FIFO_CNT9(x) (((x) >> S_CMD_IN_FIFO_CNT9) & M_CMD_IN_FIFO_CNT9)
19225 #define S_CMD_SPLIT_FIFO_CNT9 28
19226 #define M_CMD_SPLIT_FIFO_CNT9 0x3U
19227 #define V_CMD_SPLIT_FIFO_CNT9(x) ((x) << S_CMD_SPLIT_FIFO_CNT9)
19228 #define G_CMD_SPLIT_FIFO_CNT9(x) (((x) >> S_CMD_SPLIT_FIFO_CNT9) & M_CMD_SPLIT_FIFO_CNT9)
19230 #define S_CMD_THROTTLE_FIFO_CNT9 22
19231 #define M_CMD_THROTTLE_FIFO_CNT9 0x3fU
19232 #define V_CMD_THROTTLE_FIFO_CNT9(x) ((x) << S_CMD_THROTTLE_FIFO_CNT9)
19233 #define G_CMD_THROTTLE_FIFO_CNT9(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT9) & M_CMD_THROTTLE_FIFO_CNT9)
19235 #define S_RD_CHNL_FIFO_CNT9 15
19236 #define M_RD_CHNL_FIFO_CNT9 0x7fU
19237 #define V_RD_CHNL_FIFO_CNT9(x) ((x) << S_RD_CHNL_FIFO_CNT9)
19238 #define G_RD_CHNL_FIFO_CNT9(x) (((x) >> S_RD_CHNL_FIFO_CNT9) & M_RD_CHNL_FIFO_CNT9)
19240 #define S_RD_DATA_EXT_FIFO_CNT9 13
19241 #define M_RD_DATA_EXT_FIFO_CNT9 0x3U
19242 #define V_RD_DATA_EXT_FIFO_CNT9(x) ((x) << S_RD_DATA_EXT_FIFO_CNT9)
19243 #define G_RD_DATA_EXT_FIFO_CNT9(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT9) & M_RD_DATA_EXT_FIFO_CNT9)
19245 #define S_RD_DATA_512B_FIFO_CNT9 5
19246 #define M_RD_DATA_512B_FIFO_CNT9 0xffU
19247 #define V_RD_DATA_512B_FIFO_CNT9(x) ((x) << S_RD_DATA_512B_FIFO_CNT9)
19248 #define G_RD_DATA_512B_FIFO_CNT9(x) (((x) >> S_RD_DATA_512B_FIFO_CNT9) & M_RD_DATA_512B_FIFO_CNT9)
19250 #define S_RD_REQ_TAG_FIFO_CNT9 1
19251 #define M_RD_REQ_TAG_FIFO_CNT9 0xfU
19252 #define V_RD_REQ_TAG_FIFO_CNT9(x) ((x) << S_RD_REQ_TAG_FIFO_CNT9)
19253 #define G_RD_REQ_TAG_FIFO_CNT9(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT9) & M_RD_REQ_TAG_FIFO_CNT9)
19255 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
19257 #define S_CMD_IN_FIFO_CNT10 30
19258 #define M_CMD_IN_FIFO_CNT10 0x3U
19259 #define V_CMD_IN_FIFO_CNT10(x) ((x) << S_CMD_IN_FIFO_CNT10)
19260 #define G_CMD_IN_FIFO_CNT10(x) (((x) >> S_CMD_IN_FIFO_CNT10) & M_CMD_IN_FIFO_CNT10)
19262 #define S_CMD_SPLIT_FIFO_CNT10 28
19263 #define M_CMD_SPLIT_FIFO_CNT10 0x3U
19264 #define V_CMD_SPLIT_FIFO_CNT10(x) ((x) << S_CMD_SPLIT_FIFO_CNT10)
19265 #define G_CMD_SPLIT_FIFO_CNT10(x) (((x) >> S_CMD_SPLIT_FIFO_CNT10) & M_CMD_SPLIT_FIFO_CNT10)
19267 #define S_CMD_THROTTLE_FIFO_CNT10 22
19268 #define M_CMD_THROTTLE_FIFO_CNT10 0x3fU
19269 #define V_CMD_THROTTLE_FIFO_CNT10(x) ((x) << S_CMD_THROTTLE_FIFO_CNT10)
19270 #define G_CMD_THROTTLE_FIFO_CNT10(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT10) & M_CMD_THROTTLE_FIFO_CNT10)
19272 #define S_RD_CHNL_FIFO_CNT10 15
19273 #define M_RD_CHNL_FIFO_CNT10 0x7fU
19274 #define V_RD_CHNL_FIFO_CNT10(x) ((x) << S_RD_CHNL_FIFO_CNT10)
19275 #define G_RD_CHNL_FIFO_CNT10(x) (((x) >> S_RD_CHNL_FIFO_CNT10) & M_RD_CHNL_FIFO_CNT10)
19277 #define S_RD_DATA_EXT_FIFO_CNT10 13
19278 #define M_RD_DATA_EXT_FIFO_CNT10 0x3U
19279 #define V_RD_DATA_EXT_FIFO_CNT10(x) ((x) << S_RD_DATA_EXT_FIFO_CNT10)
19280 #define G_RD_DATA_EXT_FIFO_CNT10(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT10) & M_RD_DATA_EXT_FIFO_CNT10)
19282 #define S_RD_DATA_512B_FIFO_CNT10 5
19283 #define M_RD_DATA_512B_FIFO_CNT10 0xffU
19284 #define V_RD_DATA_512B_FIFO_CNT10(x) ((x) << S_RD_DATA_512B_FIFO_CNT10)
19285 #define G_RD_DATA_512B_FIFO_CNT10(x) (((x) >> S_RD_DATA_512B_FIFO_CNT10) & M_RD_DATA_512B_FIFO_CNT10)
19287 #define S_RD_REQ_TAG_FIFO_CNT10 1
19288 #define M_RD_REQ_TAG_FIFO_CNT10 0xfU
19289 #define V_RD_REQ_TAG_FIFO_CNT10(x) ((x) << S_RD_REQ_TAG_FIFO_CNT10)
19290 #define G_RD_REQ_TAG_FIFO_CNT10(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT10) & M_RD_REQ_TAG_FIFO_CNT10)
19292 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
19294 #define S_CMD_IN_FIFO_CNT11 30
19295 #define M_CMD_IN_FIFO_CNT11 0x3U
19296 #define V_CMD_IN_FIFO_CNT11(x) ((x) << S_CMD_IN_FIFO_CNT11)
19297 #define G_CMD_IN_FIFO_CNT11(x) (((x) >> S_CMD_IN_FIFO_CNT11) & M_CMD_IN_FIFO_CNT11)
19299 #define S_CMD_SPLIT_FIFO_CNT11 28
19300 #define M_CMD_SPLIT_FIFO_CNT11 0x3U
19301 #define V_CMD_SPLIT_FIFO_CNT11(x) ((x) << S_CMD_SPLIT_FIFO_CNT11)
19302 #define G_CMD_SPLIT_FIFO_CNT11(x) (((x) >> S_CMD_SPLIT_FIFO_CNT11) & M_CMD_SPLIT_FIFO_CNT11)
19304 #define S_CMD_THROTTLE_FIFO_CNT11 22
19305 #define M_CMD_THROTTLE_FIFO_CNT11 0x3fU
19306 #define V_CMD_THROTTLE_FIFO_CNT11(x) ((x) << S_CMD_THROTTLE_FIFO_CNT11)
19307 #define G_CMD_THROTTLE_FIFO_CNT11(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT11) & M_CMD_THROTTLE_FIFO_CNT11)
19309 #define S_RD_CHNL_FIFO_CNT11 15
19310 #define M_RD_CHNL_FIFO_CNT11 0x7fU
19311 #define V_RD_CHNL_FIFO_CNT11(x) ((x) << S_RD_CHNL_FIFO_CNT11)
19312 #define G_RD_CHNL_FIFO_CNT11(x) (((x) >> S_RD_CHNL_FIFO_CNT11) & M_RD_CHNL_FIFO_CNT11)
19314 #define S_RD_DATA_EXT_FIFO_CNT11 13
19315 #define M_RD_DATA_EXT_FIFO_CNT11 0x3U
19316 #define V_RD_DATA_EXT_FIFO_CNT11(x) ((x) << S_RD_DATA_EXT_FIFO_CNT11)
19317 #define G_RD_DATA_EXT_FIFO_CNT11(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT11) & M_RD_DATA_EXT_FIFO_CNT11)
19319 #define S_RD_DATA_512B_FIFO_CNT11 5
19320 #define M_RD_DATA_512B_FIFO_CNT11 0xffU
19321 #define V_RD_DATA_512B_FIFO_CNT11(x) ((x) << S_RD_DATA_512B_FIFO_CNT11)
19322 #define G_RD_DATA_512B_FIFO_CNT11(x) (((x) >> S_RD_DATA_512B_FIFO_CNT11) & M_RD_DATA_512B_FIFO_CNT11)
19324 #define S_RD_REQ_TAG_FIFO_CNT11 1
19325 #define M_RD_REQ_TAG_FIFO_CNT11 0xfU
19326 #define V_RD_REQ_TAG_FIFO_CNT11(x) ((x) << S_RD_REQ_TAG_FIFO_CNT11)
19327 #define G_RD_REQ_TAG_FIFO_CNT11(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT11) & M_RD_REQ_TAG_FIFO_CNT11)
19329 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
19331 #define S_CMD_IN_FIFO_CNT12 30
19332 #define M_CMD_IN_FIFO_CNT12 0x3U
19333 #define V_CMD_IN_FIFO_CNT12(x) ((x) << S_CMD_IN_FIFO_CNT12)
19334 #define G_CMD_IN_FIFO_CNT12(x) (((x) >> S_CMD_IN_FIFO_CNT12) & M_CMD_IN_FIFO_CNT12)
19336 #define S_CMD_SPLIT_FIFO_CNT12 28
19337 #define M_CMD_SPLIT_FIFO_CNT12 0x3U
19338 #define V_CMD_SPLIT_FIFO_CNT12(x) ((x) << S_CMD_SPLIT_FIFO_CNT12)
19339 #define G_CMD_SPLIT_FIFO_CNT12(x) (((x) >> S_CMD_SPLIT_FIFO_CNT12) & M_CMD_SPLIT_FIFO_CNT12)
19341 #define S_CMD_THROTTLE_FIFO_CNT12 22
19342 #define M_CMD_THROTTLE_FIFO_CNT12 0x3fU
19343 #define V_CMD_THROTTLE_FIFO_CNT12(x) ((x) << S_CMD_THROTTLE_FIFO_CNT12)
19344 #define G_CMD_THROTTLE_FIFO_CNT12(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT12) & M_CMD_THROTTLE_FIFO_CNT12)
19346 #define S_RD_CHNL_FIFO_CNT12 15
19347 #define M_RD_CHNL_FIFO_CNT12 0x7fU
19348 #define V_RD_CHNL_FIFO_CNT12(x) ((x) << S_RD_CHNL_FIFO_CNT12)
19349 #define G_RD_CHNL_FIFO_CNT12(x) (((x) >> S_RD_CHNL_FIFO_CNT12) & M_RD_CHNL_FIFO_CNT12)
19351 #define S_RD_DATA_EXT_FIFO_CNT12 13
19352 #define M_RD_DATA_EXT_FIFO_CNT12 0x3U
19353 #define V_RD_DATA_EXT_FIFO_CNT12(x) ((x) << S_RD_DATA_EXT_FIFO_CNT12)
19354 #define G_RD_DATA_EXT_FIFO_CNT12(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT12) & M_RD_DATA_EXT_FIFO_CNT12)
19356 #define S_RD_DATA_512B_FIFO_CNT12 5
19357 #define M_RD_DATA_512B_FIFO_CNT12 0xffU
19358 #define V_RD_DATA_512B_FIFO_CNT12(x) ((x) << S_RD_DATA_512B_FIFO_CNT12)
19359 #define G_RD_DATA_512B_FIFO_CNT12(x) (((x) >> S_RD_DATA_512B_FIFO_CNT12) & M_RD_DATA_512B_FIFO_CNT12)
19361 #define S_RD_REQ_TAG_FIFO_CNT12 1
19362 #define M_RD_REQ_TAG_FIFO_CNT12 0xfU
19363 #define V_RD_REQ_TAG_FIFO_CNT12(x) ((x) << S_RD_REQ_TAG_FIFO_CNT12)
19364 #define G_RD_REQ_TAG_FIFO_CNT12(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT12) & M_RD_REQ_TAG_FIFO_CNT12)
19366 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
19368 #define S_WR_DATA_FSM0 23
19369 #define V_WR_DATA_FSM0(x) ((x) << S_WR_DATA_FSM0)
19370 #define F_WR_DATA_FSM0 V_WR_DATA_FSM0(1U)
19372 #define S_RD_DATA_FSM0 22
19373 #define V_RD_DATA_FSM0(x) ((x) << S_RD_DATA_FSM0)
19374 #define F_RD_DATA_FSM0 V_RD_DATA_FSM0(1U)
19376 #define S_TGT_CMD_FIFO_CNT0 19
19377 #define M_TGT_CMD_FIFO_CNT0 0x7U
19378 #define V_TGT_CMD_FIFO_CNT0(x) ((x) << S_TGT_CMD_FIFO_CNT0)
19379 #define G_TGT_CMD_FIFO_CNT0(x) (((x) >> S_TGT_CMD_FIFO_CNT0) & M_TGT_CMD_FIFO_CNT0)
19381 #define S_CLNT_NUM_FIFO_CNT0 16
19382 #define M_CLNT_NUM_FIFO_CNT0 0x7U
19383 #define V_CLNT_NUM_FIFO_CNT0(x) ((x) << S_CLNT_NUM_FIFO_CNT0)
19384 #define G_CLNT_NUM_FIFO_CNT0(x) (((x) >> S_CLNT_NUM_FIFO_CNT0) & M_CLNT_NUM_FIFO_CNT0)
19386 #define S_WR_CMD_TAG_FIFO_CNT_TGT0 8
19387 #define M_WR_CMD_TAG_FIFO_CNT_TGT0 0xffU
19388 #define V_WR_CMD_TAG_FIFO_CNT_TGT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT0)
19389 #define G_WR_CMD_TAG_FIFO_CNT_TGT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT0) & M_WR_CMD_TAG_FIFO_CNT_TGT0)
19391 #define S_WR_DATA_512B_FIFO_CNT_TGT0 0
19392 #define M_WR_DATA_512B_FIFO_CNT_TGT0 0xffU
19393 #define V_WR_DATA_512B_FIFO_CNT_TGT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT0)
19394 #define G_WR_DATA_512B_FIFO_CNT_TGT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT0) & M_WR_DATA_512B_FIFO_CNT_TGT0)
19396 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
19398 #define S_WR_DATA_FSM1 23
19399 #define V_WR_DATA_FSM1(x) ((x) << S_WR_DATA_FSM1)
19400 #define F_WR_DATA_FSM1 V_WR_DATA_FSM1(1U)
19402 #define S_RD_DATA_FSM1 22
19403 #define V_RD_DATA_FSM1(x) ((x) << S_RD_DATA_FSM1)
19404 #define F_RD_DATA_FSM1 V_RD_DATA_FSM1(1U)
19406 #define S_TGT_CMD_FIFO_CNT1 19
19407 #define M_TGT_CMD_FIFO_CNT1 0x7U
19408 #define V_TGT_CMD_FIFO_CNT1(x) ((x) << S_TGT_CMD_FIFO_CNT1)
19409 #define G_TGT_CMD_FIFO_CNT1(x) (((x) >> S_TGT_CMD_FIFO_CNT1) & M_TGT_CMD_FIFO_CNT1)
19411 #define S_CLNT_NUM_FIFO_CNT1 16
19412 #define M_CLNT_NUM_FIFO_CNT1 0x7U
19413 #define V_CLNT_NUM_FIFO_CNT1(x) ((x) << S_CLNT_NUM_FIFO_CNT1)
19414 #define G_CLNT_NUM_FIFO_CNT1(x) (((x) >> S_CLNT_NUM_FIFO_CNT1) & M_CLNT_NUM_FIFO_CNT1)
19416 #define S_WR_CMD_TAG_FIFO_CNT_TGT1 8
19417 #define M_WR_CMD_TAG_FIFO_CNT_TGT1 0xffU
19418 #define V_WR_CMD_TAG_FIFO_CNT_TGT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT1)
19419 #define G_WR_CMD_TAG_FIFO_CNT_TGT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT1) & M_WR_CMD_TAG_FIFO_CNT_TGT1)
19421 #define S_WR_DATA_512B_FIFO_CNT_TGT1 0
19422 #define M_WR_DATA_512B_FIFO_CNT_TGT1 0xffU
19423 #define V_WR_DATA_512B_FIFO_CNT_TGT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT1)
19424 #define G_WR_DATA_512B_FIFO_CNT_TGT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT1) & M_WR_DATA_512B_FIFO_CNT_TGT1)
19426 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
19428 #define S_WR_DATA_FSM2 23
19429 #define V_WR_DATA_FSM2(x) ((x) << S_WR_DATA_FSM2)
19430 #define F_WR_DATA_FSM2 V_WR_DATA_FSM2(1U)
19432 #define S_RD_DATA_FSM2 22
19433 #define V_RD_DATA_FSM2(x) ((x) << S_RD_DATA_FSM2)
19434 #define F_RD_DATA_FSM2 V_RD_DATA_FSM2(1U)
19436 #define S_TGT_CMD_FIFO_CNT2 19
19437 #define M_TGT_CMD_FIFO_CNT2 0x7U
19438 #define V_TGT_CMD_FIFO_CNT2(x) ((x) << S_TGT_CMD_FIFO_CNT2)
19439 #define G_TGT_CMD_FIFO_CNT2(x) (((x) >> S_TGT_CMD_FIFO_CNT2) & M_TGT_CMD_FIFO_CNT2)
19441 #define S_CLNT_NUM_FIFO_CNT2 16
19442 #define M_CLNT_NUM_FIFO_CNT2 0x7U
19443 #define V_CLNT_NUM_FIFO_CNT2(x) ((x) << S_CLNT_NUM_FIFO_CNT2)
19444 #define G_CLNT_NUM_FIFO_CNT2(x) (((x) >> S_CLNT_NUM_FIFO_CNT2) & M_CLNT_NUM_FIFO_CNT2)
19446 #define S_WR_CMD_TAG_FIFO_CNT_TGT2 8
19447 #define M_WR_CMD_TAG_FIFO_CNT_TGT2 0xffU
19448 #define V_WR_CMD_TAG_FIFO_CNT_TGT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT2)
19449 #define G_WR_CMD_TAG_FIFO_CNT_TGT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT2) & M_WR_CMD_TAG_FIFO_CNT_TGT2)
19451 #define S_WR_DATA_512B_FIFO_CNT_TGT2 0
19452 #define M_WR_DATA_512B_FIFO_CNT_TGT2 0xffU
19453 #define V_WR_DATA_512B_FIFO_CNT_TGT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT2)
19454 #define G_WR_DATA_512B_FIFO_CNT_TGT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT2) & M_WR_DATA_512B_FIFO_CNT_TGT2)
19456 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
19458 #define S_WR_DATA_FSM3 23
19459 #define V_WR_DATA_FSM3(x) ((x) << S_WR_DATA_FSM3)
19460 #define F_WR_DATA_FSM3 V_WR_DATA_FSM3(1U)
19462 #define S_RD_DATA_FSM3 22
19463 #define V_RD_DATA_FSM3(x) ((x) << S_RD_DATA_FSM3)
19464 #define F_RD_DATA_FSM3 V_RD_DATA_FSM3(1U)
19466 #define S_TGT_CMD_FIFO_CNT3 19
19467 #define M_TGT_CMD_FIFO_CNT3 0x7U
19468 #define V_TGT_CMD_FIFO_CNT3(x) ((x) << S_TGT_CMD_FIFO_CNT3)
19469 #define G_TGT_CMD_FIFO_CNT3(x) (((x) >> S_TGT_CMD_FIFO_CNT3) & M_TGT_CMD_FIFO_CNT3)
19471 #define S_CLNT_NUM_FIFO_CNT3 16
19472 #define M_CLNT_NUM_FIFO_CNT3 0x7U
19473 #define V_CLNT_NUM_FIFO_CNT3(x) ((x) << S_CLNT_NUM_FIFO_CNT3)
19474 #define G_CLNT_NUM_FIFO_CNT3(x) (((x) >> S_CLNT_NUM_FIFO_CNT3) & M_CLNT_NUM_FIFO_CNT3)
19476 #define S_WR_CMD_TAG_FIFO_CNT_TGT3 8
19477 #define M_WR_CMD_TAG_FIFO_CNT_TGT3 0xffU
19478 #define V_WR_CMD_TAG_FIFO_CNT_TGT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT3)
19479 #define G_WR_CMD_TAG_FIFO_CNT_TGT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT3) & M_WR_CMD_TAG_FIFO_CNT_TGT3)
19481 #define S_WR_DATA_512B_FIFO_CNT_TGT 0
19482 #define M_WR_DATA_512B_FIFO_CNT_TGT 0xffU
19483 #define V_WR_DATA_512B_FIFO_CNT_TGT(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT)
19484 #define G_WR_DATA_512B_FIFO_CNT_TGT(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT) & M_WR_DATA_512B_FIFO_CNT_TGT)
19486 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
19487 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
19488 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
19489 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
19490 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
19491 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
19492 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
19493 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
19494 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
19495 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
19496 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
19497 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
19498 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
19499 #define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
19500 #define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
19501 #define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
19502 #define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
19503 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
19504 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
19505 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
19506 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
19507 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
19508 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
19509 #define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
19510 #define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
19511 #define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
19512 #define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
19513 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
19514 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
19515 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
19516 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
19517 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
19518 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
19519 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
19520 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
19521 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
19522 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
19523 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
19524 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
19525 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
19526 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
19527 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
19528 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
19529 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
19530 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
19531 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
19532 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
19533 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
19534 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
19535 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
19536 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
19537 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
19538 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
19539 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
19540 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
19541 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
19542 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
19543 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
19544 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
19545 #define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
19546 #define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
19547 #define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
19548 #define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
19549 #define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
19550 #define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
19551 #define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
19552 #define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
19553 #define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
19554 #define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
19555 #define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
19556 #define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
19557 #define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
19558 #define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
19559 #define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
19560 #define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
19561 #define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
19562 #define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
19563 #define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
19564 #define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
19565 #define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
19566 #define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
19567 #define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
19568 #define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
19569 #define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
19570 #define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
19571 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
19572 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
19573 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
19574 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
19575 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
19576 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
19577 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
19578 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
19579 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
19580 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
19581 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
19582 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
19583 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
19584 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
19585 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
19586 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
19587 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
19588 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
19589 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
19590 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
19591 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
19592 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
19593 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
19594 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
19595 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
19596 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
19597 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
19599 #define S_WR_DATA_EXT_FIFO_CNT0 30
19600 #define M_WR_DATA_EXT_FIFO_CNT0 0x3U
19601 #define V_WR_DATA_EXT_FIFO_CNT0(x) ((x) << S_WR_DATA_EXT_FIFO_CNT0)
19602 #define G_WR_DATA_EXT_FIFO_CNT0(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT0) & M_WR_DATA_EXT_FIFO_CNT0)
19604 #define S_WR_CMD_TAG_FIFO_CNT0 26
19605 #define M_WR_CMD_TAG_FIFO_CNT0 0xfU
19606 #define V_WR_CMD_TAG_FIFO_CNT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT0)
19607 #define G_WR_CMD_TAG_FIFO_CNT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT0) & M_WR_CMD_TAG_FIFO_CNT0)
19609 #define S_WR_DATA_512B_FIFO_CNT0 18
19610 #define M_WR_DATA_512B_FIFO_CNT0 0xffU
19611 #define V_WR_DATA_512B_FIFO_CNT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT0)
19612 #define G_WR_DATA_512B_FIFO_CNT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT0) & M_WR_DATA_512B_FIFO_CNT0)
19614 #define S_RD_DATA_ALIGN_FSM0 17
19615 #define V_RD_DATA_ALIGN_FSM0(x) ((x) << S_RD_DATA_ALIGN_FSM0)
19616 #define F_RD_DATA_ALIGN_FSM0 V_RD_DATA_ALIGN_FSM0(1U)
19618 #define S_RD_DATA_FETCH_FSM0 16
19619 #define V_RD_DATA_FETCH_FSM0(x) ((x) << S_RD_DATA_FETCH_FSM0)
19620 #define F_RD_DATA_FETCH_FSM0 V_RD_DATA_FETCH_FSM0(1U)
19622 #define S_COHERENCY_TX_FSM0 15
19623 #define V_COHERENCY_TX_FSM0(x) ((x) << S_COHERENCY_TX_FSM0)
19624 #define F_COHERENCY_TX_FSM0 V_COHERENCY_TX_FSM0(1U)
19626 #define S_COHERENCY_RX_FSM0 14
19627 #define V_COHERENCY_RX_FSM0(x) ((x) << S_COHERENCY_RX_FSM0)
19628 #define F_COHERENCY_RX_FSM0 V_COHERENCY_RX_FSM0(1U)
19630 #define S_ARB_REQ_FSM0 13
19631 #define V_ARB_REQ_FSM0(x) ((x) << S_ARB_REQ_FSM0)
19632 #define F_ARB_REQ_FSM0 V_ARB_REQ_FSM0(1U)
19634 #define S_CMD_SPLIT_FSM0 10
19635 #define M_CMD_SPLIT_FSM0 0x7U
19636 #define V_CMD_SPLIT_FSM0(x) ((x) << S_CMD_SPLIT_FSM0)
19637 #define G_CMD_SPLIT_FSM0(x) (((x) >> S_CMD_SPLIT_FSM0) & M_CMD_SPLIT_FSM0)
19639 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
19641 #define S_WR_DATA_EXT_FIFO_CNT1 30
19642 #define M_WR_DATA_EXT_FIFO_CNT1 0x3U
19643 #define V_WR_DATA_EXT_FIFO_CNT1(x) ((x) << S_WR_DATA_EXT_FIFO_CNT1)
19644 #define G_WR_DATA_EXT_FIFO_CNT1(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT1) & M_WR_DATA_EXT_FIFO_CNT1)
19646 #define S_WR_CMD_TAG_FIFO_CNT1 26
19647 #define M_WR_CMD_TAG_FIFO_CNT1 0xfU
19648 #define V_WR_CMD_TAG_FIFO_CNT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT1)
19649 #define G_WR_CMD_TAG_FIFO_CNT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT1) & M_WR_CMD_TAG_FIFO_CNT1)
19651 #define S_WR_DATA_512B_FIFO_CNT1 18
19652 #define M_WR_DATA_512B_FIFO_CNT1 0xffU
19653 #define V_WR_DATA_512B_FIFO_CNT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT1)
19654 #define G_WR_DATA_512B_FIFO_CNT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT1) & M_WR_DATA_512B_FIFO_CNT1)
19656 #define S_RD_DATA_ALIGN_FSM1 17
19657 #define V_RD_DATA_ALIGN_FSM1(x) ((x) << S_RD_DATA_ALIGN_FSM1)
19658 #define F_RD_DATA_ALIGN_FSM1 V_RD_DATA_ALIGN_FSM1(1U)
19660 #define S_RD_DATA_FETCH_FSM1 16
19661 #define V_RD_DATA_FETCH_FSM1(x) ((x) << S_RD_DATA_FETCH_FSM1)
19662 #define F_RD_DATA_FETCH_FSM1 V_RD_DATA_FETCH_FSM1(1U)
19664 #define S_COHERENCY_TX_FSM1 15
19665 #define V_COHERENCY_TX_FSM1(x) ((x) << S_COHERENCY_TX_FSM1)
19666 #define F_COHERENCY_TX_FSM1 V_COHERENCY_TX_FSM1(1U)
19668 #define S_COHERENCY_RX_FSM1 14
19669 #define V_COHERENCY_RX_FSM1(x) ((x) << S_COHERENCY_RX_FSM1)
19670 #define F_COHERENCY_RX_FSM1 V_COHERENCY_RX_FSM1(1U)
19672 #define S_ARB_REQ_FSM1 13
19673 #define V_ARB_REQ_FSM1(x) ((x) << S_ARB_REQ_FSM1)
19674 #define F_ARB_REQ_FSM1 V_ARB_REQ_FSM1(1U)
19676 #define S_CMD_SPLIT_FSM1 10
19677 #define M_CMD_SPLIT_FSM1 0x7U
19678 #define V_CMD_SPLIT_FSM1(x) ((x) << S_CMD_SPLIT_FSM1)
19679 #define G_CMD_SPLIT_FSM1(x) (((x) >> S_CMD_SPLIT_FSM1) & M_CMD_SPLIT_FSM1)
19681 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
19683 #define S_WR_DATA_EXT_FIFO_CNT2 30
19684 #define M_WR_DATA_EXT_FIFO_CNT2 0x3U
19685 #define V_WR_DATA_EXT_FIFO_CNT2(x) ((x) << S_WR_DATA_EXT_FIFO_CNT2)
19686 #define G_WR_DATA_EXT_FIFO_CNT2(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT2) & M_WR_DATA_EXT_FIFO_CNT2)
19688 #define S_WR_CMD_TAG_FIFO_CNT2 26
19689 #define M_WR_CMD_TAG_FIFO_CNT2 0xfU
19690 #define V_WR_CMD_TAG_FIFO_CNT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT2)
19691 #define G_WR_CMD_TAG_FIFO_CNT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT2) & M_WR_CMD_TAG_FIFO_CNT2)
19693 #define S_WR_DATA_512B_FIFO_CNT2 18
19694 #define M_WR_DATA_512B_FIFO_CNT2 0xffU
19695 #define V_WR_DATA_512B_FIFO_CNT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT2)
19696 #define G_WR_DATA_512B_FIFO_CNT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT2) & M_WR_DATA_512B_FIFO_CNT2)
19698 #define S_RD_DATA_ALIGN_FSM2 17
19699 #define V_RD_DATA_ALIGN_FSM2(x) ((x) << S_RD_DATA_ALIGN_FSM2)
19700 #define F_RD_DATA_ALIGN_FSM2 V_RD_DATA_ALIGN_FSM2(1U)
19702 #define S_RD_DATA_FETCH_FSM2 16
19703 #define V_RD_DATA_FETCH_FSM2(x) ((x) << S_RD_DATA_FETCH_FSM2)
19704 #define F_RD_DATA_FETCH_FSM2 V_RD_DATA_FETCH_FSM2(1U)
19706 #define S_COHERENCY_TX_FSM2 15
19707 #define V_COHERENCY_TX_FSM2(x) ((x) << S_COHERENCY_TX_FSM2)
19708 #define F_COHERENCY_TX_FSM2 V_COHERENCY_TX_FSM2(1U)
19710 #define S_COHERENCY_RX_FSM2 14
19711 #define V_COHERENCY_RX_FSM2(x) ((x) << S_COHERENCY_RX_FSM2)
19712 #define F_COHERENCY_RX_FSM2 V_COHERENCY_RX_FSM2(1U)
19714 #define S_ARB_REQ_FSM2 13
19715 #define V_ARB_REQ_FSM2(x) ((x) << S_ARB_REQ_FSM2)
19716 #define F_ARB_REQ_FSM2 V_ARB_REQ_FSM2(1U)
19718 #define S_CMD_SPLIT_FSM2 10
19719 #define M_CMD_SPLIT_FSM2 0x7U
19720 #define V_CMD_SPLIT_FSM2(x) ((x) << S_CMD_SPLIT_FSM2)
19721 #define G_CMD_SPLIT_FSM2(x) (((x) >> S_CMD_SPLIT_FSM2) & M_CMD_SPLIT_FSM2)
19723 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
19725 #define S_WR_DATA_EXT_FIFO_CNT3 30
19726 #define M_WR_DATA_EXT_FIFO_CNT3 0x3U
19727 #define V_WR_DATA_EXT_FIFO_CNT3(x) ((x) << S_WR_DATA_EXT_FIFO_CNT3)
19728 #define G_WR_DATA_EXT_FIFO_CNT3(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT3) & M_WR_DATA_EXT_FIFO_CNT3)
19730 #define S_WR_CMD_TAG_FIFO_CNT3 26
19731 #define M_WR_CMD_TAG_FIFO_CNT3 0xfU
19732 #define V_WR_CMD_TAG_FIFO_CNT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT3)
19733 #define G_WR_CMD_TAG_FIFO_CNT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT3) & M_WR_CMD_TAG_FIFO_CNT3)
19735 #define S_WR_DATA_512B_FIFO_CNT3 18
19736 #define M_WR_DATA_512B_FIFO_CNT3 0xffU
19737 #define V_WR_DATA_512B_FIFO_CNT3(x) ((x) << S_WR_DATA_512B_FIFO_CNT3)
19738 #define G_WR_DATA_512B_FIFO_CNT3(x) (((x) >> S_WR_DATA_512B_FIFO_CNT3) & M_WR_DATA_512B_FIFO_CNT3)
19740 #define S_RD_DATA_ALIGN_FSM3 17
19741 #define V_RD_DATA_ALIGN_FSM3(x) ((x) << S_RD_DATA_ALIGN_FSM3)
19742 #define F_RD_DATA_ALIGN_FSM3 V_RD_DATA_ALIGN_FSM3(1U)
19744 #define S_RD_DATA_FETCH_FSM3 16
19745 #define V_RD_DATA_FETCH_FSM3(x) ((x) << S_RD_DATA_FETCH_FSM3)
19746 #define F_RD_DATA_FETCH_FSM3 V_RD_DATA_FETCH_FSM3(1U)
19748 #define S_COHERENCY_TX_FSM3 15
19749 #define V_COHERENCY_TX_FSM3(x) ((x) << S_COHERENCY_TX_FSM3)
19750 #define F_COHERENCY_TX_FSM3 V_COHERENCY_TX_FSM3(1U)
19752 #define S_COHERENCY_RX_FSM3 14
19753 #define V_COHERENCY_RX_FSM3(x) ((x) << S_COHERENCY_RX_FSM3)
19754 #define F_COHERENCY_RX_FSM3 V_COHERENCY_RX_FSM3(1U)
19756 #define S_ARB_REQ_FSM3 13
19757 #define V_ARB_REQ_FSM3(x) ((x) << S_ARB_REQ_FSM3)
19758 #define F_ARB_REQ_FSM3 V_ARB_REQ_FSM3(1U)
19760 #define S_CMD_SPLIT_FSM3 10
19761 #define M_CMD_SPLIT_FSM3 0x7U
19762 #define V_CMD_SPLIT_FSM3(x) ((x) << S_CMD_SPLIT_FSM3)
19763 #define G_CMD_SPLIT_FSM3(x) (((x) >> S_CMD_SPLIT_FSM3) & M_CMD_SPLIT_FSM3)
19765 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
19767 #define S_WR_DATA_EXT_FIFO_CNT4 30
19768 #define M_WR_DATA_EXT_FIFO_CNT4 0x3U
19769 #define V_WR_DATA_EXT_FIFO_CNT4(x) ((x) << S_WR_DATA_EXT_FIFO_CNT4)
19770 #define G_WR_DATA_EXT_FIFO_CNT4(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT4) & M_WR_DATA_EXT_FIFO_CNT4)
19772 #define S_WR_CMD_TAG_FIFO_CNT4 26
19773 #define M_WR_CMD_TAG_FIFO_CNT4 0xfU
19774 #define V_WR_CMD_TAG_FIFO_CNT4(x) ((x) << S_WR_CMD_TAG_FIFO_CNT4)
19775 #define G_WR_CMD_TAG_FIFO_CNT4(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT4) & M_WR_CMD_TAG_FIFO_CNT4)
19777 #define S_WR_DATA_512B_FIFO_CNT4 18
19778 #define M_WR_DATA_512B_FIFO_CNT4 0xffU
19779 #define V_WR_DATA_512B_FIFO_CNT4(x) ((x) << S_WR_DATA_512B_FIFO_CNT4)
19780 #define G_WR_DATA_512B_FIFO_CNT4(x) (((x) >> S_WR_DATA_512B_FIFO_CNT4) & M_WR_DATA_512B_FIFO_CNT4)
19782 #define S_RD_DATA_ALIGN_FSM4 17
19783 #define V_RD_DATA_ALIGN_FSM4(x) ((x) << S_RD_DATA_ALIGN_FSM4)
19784 #define F_RD_DATA_ALIGN_FSM4 V_RD_DATA_ALIGN_FSM4(1U)
19786 #define S_RD_DATA_FETCH_FSM4 16
19787 #define V_RD_DATA_FETCH_FSM4(x) ((x) << S_RD_DATA_FETCH_FSM4)
19788 #define F_RD_DATA_FETCH_FSM4 V_RD_DATA_FETCH_FSM4(1U)
19790 #define S_COHERENCY_TX_FSM4 15
19791 #define V_COHERENCY_TX_FSM4(x) ((x) << S_COHERENCY_TX_FSM4)
19792 #define F_COHERENCY_TX_FSM4 V_COHERENCY_TX_FSM4(1U)
19794 #define S_COHERENCY_RX_FSM4 14
19795 #define V_COHERENCY_RX_FSM4(x) ((x) << S_COHERENCY_RX_FSM4)
19796 #define F_COHERENCY_RX_FSM4 V_COHERENCY_RX_FSM4(1U)
19798 #define S_ARB_REQ_FSM4 13
19799 #define V_ARB_REQ_FSM4(x) ((x) << S_ARB_REQ_FSM4)
19800 #define F_ARB_REQ_FSM4 V_ARB_REQ_FSM4(1U)
19802 #define S_CMD_SPLIT_FSM4 10
19803 #define M_CMD_SPLIT_FSM4 0x7U
19804 #define V_CMD_SPLIT_FSM4(x) ((x) << S_CMD_SPLIT_FSM4)
19805 #define G_CMD_SPLIT_FSM4(x) (((x) >> S_CMD_SPLIT_FSM4) & M_CMD_SPLIT_FSM4)
19807 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
19809 #define S_WR_DATA_EXT_FIFO_CNT5 30
19810 #define M_WR_DATA_EXT_FIFO_CNT5 0x3U
19811 #define V_WR_DATA_EXT_FIFO_CNT5(x) ((x) << S_WR_DATA_EXT_FIFO_CNT5)
19812 #define G_WR_DATA_EXT_FIFO_CNT5(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT5) & M_WR_DATA_EXT_FIFO_CNT5)
19814 #define S_WR_CMD_TAG_FIFO_CNT5 26
19815 #define M_WR_CMD_TAG_FIFO_CNT5 0xfU
19816 #define V_WR_CMD_TAG_FIFO_CNT5(x) ((x) << S_WR_CMD_TAG_FIFO_CNT5)
19817 #define G_WR_CMD_TAG_FIFO_CNT5(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT5) & M_WR_CMD_TAG_FIFO_CNT5)
19819 #define S_WR_DATA_512B_FIFO_CNT5 18
19820 #define M_WR_DATA_512B_FIFO_CNT5 0xffU
19821 #define V_WR_DATA_512B_FIFO_CNT5(x) ((x) << S_WR_DATA_512B_FIFO_CNT5)
19822 #define G_WR_DATA_512B_FIFO_CNT5(x) (((x) >> S_WR_DATA_512B_FIFO_CNT5) & M_WR_DATA_512B_FIFO_CNT5)
19824 #define S_RD_DATA_ALIGN_FSM5 17
19825 #define V_RD_DATA_ALIGN_FSM5(x) ((x) << S_RD_DATA_ALIGN_FSM5)
19826 #define F_RD_DATA_ALIGN_FSM5 V_RD_DATA_ALIGN_FSM5(1U)
19828 #define S_RD_DATA_FETCH_FSM5 16
19829 #define V_RD_DATA_FETCH_FSM5(x) ((x) << S_RD_DATA_FETCH_FSM5)
19830 #define F_RD_DATA_FETCH_FSM5 V_RD_DATA_FETCH_FSM5(1U)
19832 #define S_COHERENCY_TX_FSM5 15
19833 #define V_COHERENCY_TX_FSM5(x) ((x) << S_COHERENCY_TX_FSM5)
19834 #define F_COHERENCY_TX_FSM5 V_COHERENCY_TX_FSM5(1U)
19836 #define S_COHERENCY_RX_FSM5 14
19837 #define V_COHERENCY_RX_FSM5(x) ((x) << S_COHERENCY_RX_FSM5)
19838 #define F_COHERENCY_RX_FSM5 V_COHERENCY_RX_FSM5(1U)
19840 #define S_ARB_REQ_FSM5 13
19841 #define V_ARB_REQ_FSM5(x) ((x) << S_ARB_REQ_FSM5)
19842 #define F_ARB_REQ_FSM5 V_ARB_REQ_FSM5(1U)
19844 #define S_CMD_SPLIT_FSM5 10
19845 #define M_CMD_SPLIT_FSM5 0x7U
19846 #define V_CMD_SPLIT_FSM5(x) ((x) << S_CMD_SPLIT_FSM5)
19847 #define G_CMD_SPLIT_FSM5(x) (((x) >> S_CMD_SPLIT_FSM5) & M_CMD_SPLIT_FSM5)
19849 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
19851 #define S_WR_DATA_EXT_FIFO_CNT6 30
19852 #define M_WR_DATA_EXT_FIFO_CNT6 0x3U
19853 #define V_WR_DATA_EXT_FIFO_CNT6(x) ((x) << S_WR_DATA_EXT_FIFO_CNT6)
19854 #define G_WR_DATA_EXT_FIFO_CNT6(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT6) & M_WR_DATA_EXT_FIFO_CNT6)
19856 #define S_WR_CMD_TAG_FIFO_CNT6 26
19857 #define M_WR_CMD_TAG_FIFO_CNT6 0xfU
19858 #define V_WR_CMD_TAG_FIFO_CNT6(x) ((x) << S_WR_CMD_TAG_FIFO_CNT6)
19859 #define G_WR_CMD_TAG_FIFO_CNT6(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT6) & M_WR_CMD_TAG_FIFO_CNT6)
19861 #define S_WR_DATA_512B_FIFO_CNT6 18
19862 #define M_WR_DATA_512B_FIFO_CNT6 0xffU
19863 #define V_WR_DATA_512B_FIFO_CNT6(x) ((x) << S_WR_DATA_512B_FIFO_CNT6)
19864 #define G_WR_DATA_512B_FIFO_CNT6(x) (((x) >> S_WR_DATA_512B_FIFO_CNT6) & M_WR_DATA_512B_FIFO_CNT6)
19866 #define S_RD_DATA_ALIGN_FSM6 17
19867 #define V_RD_DATA_ALIGN_FSM6(x) ((x) << S_RD_DATA_ALIGN_FSM6)
19868 #define F_RD_DATA_ALIGN_FSM6 V_RD_DATA_ALIGN_FSM6(1U)
19870 #define S_RD_DATA_FETCH_FSM6 16
19871 #define V_RD_DATA_FETCH_FSM6(x) ((x) << S_RD_DATA_FETCH_FSM6)
19872 #define F_RD_DATA_FETCH_FSM6 V_RD_DATA_FETCH_FSM6(1U)
19874 #define S_COHERENCY_TX_FSM6 15
19875 #define V_COHERENCY_TX_FSM6(x) ((x) << S_COHERENCY_TX_FSM6)
19876 #define F_COHERENCY_TX_FSM6 V_COHERENCY_TX_FSM6(1U)
19878 #define S_COHERENCY_RX_FSM6 14
19879 #define V_COHERENCY_RX_FSM6(x) ((x) << S_COHERENCY_RX_FSM6)
19880 #define F_COHERENCY_RX_FSM6 V_COHERENCY_RX_FSM6(1U)
19882 #define S_ARB_REQ_FSM6 13
19883 #define V_ARB_REQ_FSM6(x) ((x) << S_ARB_REQ_FSM6)
19884 #define F_ARB_REQ_FSM6 V_ARB_REQ_FSM6(1U)
19886 #define S_CMD_SPLIT_FSM6 10
19887 #define M_CMD_SPLIT_FSM6 0x7U
19888 #define V_CMD_SPLIT_FSM6(x) ((x) << S_CMD_SPLIT_FSM6)
19889 #define G_CMD_SPLIT_FSM6(x) (((x) >> S_CMD_SPLIT_FSM6) & M_CMD_SPLIT_FSM6)
19891 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
19893 #define S_WR_DATA_EXT_FIFO_CNT7 30
19894 #define M_WR_DATA_EXT_FIFO_CNT7 0x3U
19895 #define V_WR_DATA_EXT_FIFO_CNT7(x) ((x) << S_WR_DATA_EXT_FIFO_CNT7)
19896 #define G_WR_DATA_EXT_FIFO_CNT7(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT7) & M_WR_DATA_EXT_FIFO_CNT7)
19898 #define S_WR_CMD_TAG_FIFO_CNT7 26
19899 #define M_WR_CMD_TAG_FIFO_CNT7 0xfU
19900 #define V_WR_CMD_TAG_FIFO_CNT7(x) ((x) << S_WR_CMD_TAG_FIFO_CNT7)
19901 #define G_WR_CMD_TAG_FIFO_CNT7(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT7) & M_WR_CMD_TAG_FIFO_CNT7)
19903 #define S_WR_DATA_512B_FIFO_CNT7 18
19904 #define M_WR_DATA_512B_FIFO_CNT7 0xffU
19905 #define V_WR_DATA_512B_FIFO_CNT7(x) ((x) << S_WR_DATA_512B_FIFO_CNT7)
19906 #define G_WR_DATA_512B_FIFO_CNT7(x) (((x) >> S_WR_DATA_512B_FIFO_CNT7) & M_WR_DATA_512B_FIFO_CNT7)
19908 #define S_RD_DATA_ALIGN_FSM7 17
19909 #define V_RD_DATA_ALIGN_FSM7(x) ((x) << S_RD_DATA_ALIGN_FSM7)
19910 #define F_RD_DATA_ALIGN_FSM7 V_RD_DATA_ALIGN_FSM7(1U)
19912 #define S_RD_DATA_FETCH_FSM7 16
19913 #define V_RD_DATA_FETCH_FSM7(x) ((x) << S_RD_DATA_FETCH_FSM7)
19914 #define F_RD_DATA_FETCH_FSM7 V_RD_DATA_FETCH_FSM7(1U)
19916 #define S_COHERENCY_TX_FSM7 15
19917 #define V_COHERENCY_TX_FSM7(x) ((x) << S_COHERENCY_TX_FSM7)
19918 #define F_COHERENCY_TX_FSM7 V_COHERENCY_TX_FSM7(1U)
19920 #define S_COHERENCY_RX_FSM7 14
19921 #define V_COHERENCY_RX_FSM7(x) ((x) << S_COHERENCY_RX_FSM7)
19922 #define F_COHERENCY_RX_FSM7 V_COHERENCY_RX_FSM7(1U)
19924 #define S_ARB_REQ_FSM7 13
19925 #define V_ARB_REQ_FSM7(x) ((x) << S_ARB_REQ_FSM7)
19926 #define F_ARB_REQ_FSM7 V_ARB_REQ_FSM7(1U)
19928 #define S_CMD_SPLIT_FSM7 10
19929 #define M_CMD_SPLIT_FSM7 0x7U
19930 #define V_CMD_SPLIT_FSM7(x) ((x) << S_CMD_SPLIT_FSM7)
19931 #define G_CMD_SPLIT_FSM7(x) (((x) >> S_CMD_SPLIT_FSM7) & M_CMD_SPLIT_FSM7)
19933 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
19935 #define S_WR_DATA_EXT_FIFO_CNT8 30
19936 #define M_WR_DATA_EXT_FIFO_CNT8 0x3U
19937 #define V_WR_DATA_EXT_FIFO_CNT8(x) ((x) << S_WR_DATA_EXT_FIFO_CNT8)
19938 #define G_WR_DATA_EXT_FIFO_CNT8(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT8) & M_WR_DATA_EXT_FIFO_CNT8)
19940 #define S_WR_CMD_TAG_FIFO_CNT8 26
19941 #define M_WR_CMD_TAG_FIFO_CNT8 0xfU
19942 #define V_WR_CMD_TAG_FIFO_CNT8(x) ((x) << S_WR_CMD_TAG_FIFO_CNT8)
19943 #define G_WR_CMD_TAG_FIFO_CNT8(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT8) & M_WR_CMD_TAG_FIFO_CNT8)
19945 #define S_WR_DATA_512B_FIFO_CNT8 18
19946 #define M_WR_DATA_512B_FIFO_CNT8 0xffU
19947 #define V_WR_DATA_512B_FIFO_CNT8(x) ((x) << S_WR_DATA_512B_FIFO_CNT8)
19948 #define G_WR_DATA_512B_FIFO_CNT8(x) (((x) >> S_WR_DATA_512B_FIFO_CNT8) & M_WR_DATA_512B_FIFO_CNT8)
19950 #define S_RD_DATA_ALIGN_FSM8 17
19951 #define V_RD_DATA_ALIGN_FSM8(x) ((x) << S_RD_DATA_ALIGN_FSM8)
19952 #define F_RD_DATA_ALIGN_FSM8 V_RD_DATA_ALIGN_FSM8(1U)
19954 #define S_RD_DATA_FETCH_FSM8 16
19955 #define V_RD_DATA_FETCH_FSM8(x) ((x) << S_RD_DATA_FETCH_FSM8)
19956 #define F_RD_DATA_FETCH_FSM8 V_RD_DATA_FETCH_FSM8(1U)
19958 #define S_COHERENCY_TX_FSM8 15
19959 #define V_COHERENCY_TX_FSM8(x) ((x) << S_COHERENCY_TX_FSM8)
19960 #define F_COHERENCY_TX_FSM8 V_COHERENCY_TX_FSM8(1U)
19962 #define S_COHERENCY_RX_FSM8 14
19963 #define V_COHERENCY_RX_FSM8(x) ((x) << S_COHERENCY_RX_FSM8)
19964 #define F_COHERENCY_RX_FSM8 V_COHERENCY_RX_FSM8(1U)
19966 #define S_ARB_REQ_FSM8 13
19967 #define V_ARB_REQ_FSM8(x) ((x) << S_ARB_REQ_FSM8)
19968 #define F_ARB_REQ_FSM8 V_ARB_REQ_FSM8(1U)
19970 #define S_CMD_SPLIT_FSM8 10
19971 #define M_CMD_SPLIT_FSM8 0x7U
19972 #define V_CMD_SPLIT_FSM8(x) ((x) << S_CMD_SPLIT_FSM8)
19973 #define G_CMD_SPLIT_FSM8(x) (((x) >> S_CMD_SPLIT_FSM8) & M_CMD_SPLIT_FSM8)
19975 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
19977 #define S_WR_DATA_EXT_FIFO_CNT9 30
19978 #define M_WR_DATA_EXT_FIFO_CNT9 0x3U
19979 #define V_WR_DATA_EXT_FIFO_CNT9(x) ((x) << S_WR_DATA_EXT_FIFO_CNT9)
19980 #define G_WR_DATA_EXT_FIFO_CNT9(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT9) & M_WR_DATA_EXT_FIFO_CNT9)
19982 #define S_WR_CMD_TAG_FIFO_CNT9 26
19983 #define M_WR_CMD_TAG_FIFO_CNT9 0xfU
19984 #define V_WR_CMD_TAG_FIFO_CNT9(x) ((x) << S_WR_CMD_TAG_FIFO_CNT9)
19985 #define G_WR_CMD_TAG_FIFO_CNT9(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT9) & M_WR_CMD_TAG_FIFO_CNT9)
19987 #define S_WR_DATA_512B_FIFO_CNT9 18
19988 #define M_WR_DATA_512B_FIFO_CNT9 0xffU
19989 #define V_WR_DATA_512B_FIFO_CNT9(x) ((x) << S_WR_DATA_512B_FIFO_CNT9)
19990 #define G_WR_DATA_512B_FIFO_CNT9(x) (((x) >> S_WR_DATA_512B_FIFO_CNT9) & M_WR_DATA_512B_FIFO_CNT9)
19992 #define S_RD_DATA_ALIGN_FSM9 17
19993 #define V_RD_DATA_ALIGN_FSM9(x) ((x) << S_RD_DATA_ALIGN_FSM9)
19994 #define F_RD_DATA_ALIGN_FSM9 V_RD_DATA_ALIGN_FSM9(1U)
19996 #define S_RD_DATA_FETCH_FSM9 16
19997 #define V_RD_DATA_FETCH_FSM9(x) ((x) << S_RD_DATA_FETCH_FSM9)
19998 #define F_RD_DATA_FETCH_FSM9 V_RD_DATA_FETCH_FSM9(1U)
20000 #define S_COHERENCY_TX_FSM9 15
20001 #define V_COHERENCY_TX_FSM9(x) ((x) << S_COHERENCY_TX_FSM9)
20002 #define F_COHERENCY_TX_FSM9 V_COHERENCY_TX_FSM9(1U)
20004 #define S_COHERENCY_RX_FSM9 14
20005 #define V_COHERENCY_RX_FSM9(x) ((x) << S_COHERENCY_RX_FSM9)
20006 #define F_COHERENCY_RX_FSM9 V_COHERENCY_RX_FSM9(1U)
20008 #define S_ARB_REQ_FSM9 13
20009 #define V_ARB_REQ_FSM9(x) ((x) << S_ARB_REQ_FSM9)
20010 #define F_ARB_REQ_FSM9 V_ARB_REQ_FSM9(1U)
20012 #define S_CMD_SPLIT_FSM9 10
20013 #define M_CMD_SPLIT_FSM9 0x7U
20014 #define V_CMD_SPLIT_FSM9(x) ((x) << S_CMD_SPLIT_FSM9)
20015 #define G_CMD_SPLIT_FSM9(x) (((x) >> S_CMD_SPLIT_FSM9) & M_CMD_SPLIT_FSM9)
20017 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
20019 #define S_WR_DATA_EXT_FIFO_CNT10 30
20020 #define M_WR_DATA_EXT_FIFO_CNT10 0x3U
20021 #define V_WR_DATA_EXT_FIFO_CNT10(x) ((x) << S_WR_DATA_EXT_FIFO_CNT10)
20022 #define G_WR_DATA_EXT_FIFO_CNT10(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT10) & M_WR_DATA_EXT_FIFO_CNT10)
20024 #define S_WR_CMD_TAG_FIFO_CNT10 26
20025 #define M_WR_CMD_TAG_FIFO_CNT10 0xfU
20026 #define V_WR_CMD_TAG_FIFO_CNT10(x) ((x) << S_WR_CMD_TAG_FIFO_CNT10)
20027 #define G_WR_CMD_TAG_FIFO_CNT10(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT10) & M_WR_CMD_TAG_FIFO_CNT10)
20029 #define S_WR_DATA_512B_FIFO_CNT10 18
20030 #define M_WR_DATA_512B_FIFO_CNT10 0xffU
20031 #define V_WR_DATA_512B_FIFO_CNT10(x) ((x) << S_WR_DATA_512B_FIFO_CNT10)
20032 #define G_WR_DATA_512B_FIFO_CNT10(x) (((x) >> S_WR_DATA_512B_FIFO_CNT10) & M_WR_DATA_512B_FIFO_CNT10)
20034 #define S_RD_DATA_ALIGN_FSM10 17
20035 #define V_RD_DATA_ALIGN_FSM10(x) ((x) << S_RD_DATA_ALIGN_FSM10)
20036 #define F_RD_DATA_ALIGN_FSM10 V_RD_DATA_ALIGN_FSM10(1U)
20038 #define S_RD_DATA_FETCH_FSM10 16
20039 #define V_RD_DATA_FETCH_FSM10(x) ((x) << S_RD_DATA_FETCH_FSM10)
20040 #define F_RD_DATA_FETCH_FSM10 V_RD_DATA_FETCH_FSM10(1U)
20042 #define S_COHERENCY_TX_FSM10 15
20043 #define V_COHERENCY_TX_FSM10(x) ((x) << S_COHERENCY_TX_FSM10)
20044 #define F_COHERENCY_TX_FSM10 V_COHERENCY_TX_FSM10(1U)
20046 #define S_COHERENCY_RX_FSM10 14
20047 #define V_COHERENCY_RX_FSM10(x) ((x) << S_COHERENCY_RX_FSM10)
20048 #define F_COHERENCY_RX_FSM10 V_COHERENCY_RX_FSM10(1U)
20050 #define S_ARB_REQ_FSM10 13
20051 #define V_ARB_REQ_FSM10(x) ((x) << S_ARB_REQ_FSM10)
20052 #define F_ARB_REQ_FSM10 V_ARB_REQ_FSM10(1U)
20054 #define S_CMD_SPLIT_FSM10 10
20055 #define M_CMD_SPLIT_FSM10 0x7U
20056 #define V_CMD_SPLIT_FSM10(x) ((x) << S_CMD_SPLIT_FSM10)
20057 #define G_CMD_SPLIT_FSM10(x) (((x) >> S_CMD_SPLIT_FSM10) & M_CMD_SPLIT_FSM10)
20059 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
20061 #define S_WR_DATA_EXT_FIFO_CNT11 30
20062 #define M_WR_DATA_EXT_FIFO_CNT11 0x3U
20063 #define V_WR_DATA_EXT_FIFO_CNT11(x) ((x) << S_WR_DATA_EXT_FIFO_CNT11)
20064 #define G_WR_DATA_EXT_FIFO_CNT11(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT11) & M_WR_DATA_EXT_FIFO_CNT11)
20066 #define S_WR_CMD_TAG_FIFO_CNT11 26
20067 #define M_WR_CMD_TAG_FIFO_CNT11 0xfU
20068 #define V_WR_CMD_TAG_FIFO_CNT11(x) ((x) << S_WR_CMD_TAG_FIFO_CNT11)
20069 #define G_WR_CMD_TAG_FIFO_CNT11(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT11) & M_WR_CMD_TAG_FIFO_CNT11)
20071 #define S_WR_DATA_512B_FIFO_CNT11 18
20072 #define M_WR_DATA_512B_FIFO_CNT11 0xffU
20073 #define V_WR_DATA_512B_FIFO_CNT11(x) ((x) << S_WR_DATA_512B_FIFO_CNT11)
20074 #define G_WR_DATA_512B_FIFO_CNT11(x) (((x) >> S_WR_DATA_512B_FIFO_CNT11) & M_WR_DATA_512B_FIFO_CNT11)
20076 #define S_RD_DATA_ALIGN_FSM11 17
20077 #define V_RD_DATA_ALIGN_FSM11(x) ((x) << S_RD_DATA_ALIGN_FSM11)
20078 #define F_RD_DATA_ALIGN_FSM11 V_RD_DATA_ALIGN_FSM11(1U)
20080 #define S_RD_DATA_FETCH_FSM11 16
20081 #define V_RD_DATA_FETCH_FSM11(x) ((x) << S_RD_DATA_FETCH_FSM11)
20082 #define F_RD_DATA_FETCH_FSM11 V_RD_DATA_FETCH_FSM11(1U)
20084 #define S_COHERENCY_TX_FSM11 15
20085 #define V_COHERENCY_TX_FSM11(x) ((x) << S_COHERENCY_TX_FSM11)
20086 #define F_COHERENCY_TX_FSM11 V_COHERENCY_TX_FSM11(1U)
20088 #define S_COHERENCY_RX_FSM11 14
20089 #define V_COHERENCY_RX_FSM11(x) ((x) << S_COHERENCY_RX_FSM11)
20090 #define F_COHERENCY_RX_FSM11 V_COHERENCY_RX_FSM11(1U)
20092 #define S_ARB_REQ_FSM11 13
20093 #define V_ARB_REQ_FSM11(x) ((x) << S_ARB_REQ_FSM11)
20094 #define F_ARB_REQ_FSM11 V_ARB_REQ_FSM11(1U)
20096 #define S_CMD_SPLIT_FSM11 10
20097 #define M_CMD_SPLIT_FSM11 0x7U
20098 #define V_CMD_SPLIT_FSM11(x) ((x) << S_CMD_SPLIT_FSM11)
20099 #define G_CMD_SPLIT_FSM11(x) (((x) >> S_CMD_SPLIT_FSM11) & M_CMD_SPLIT_FSM11)
20101 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
20103 #define S_WR_DATA_EXT_FIFO_CNT12 30
20104 #define M_WR_DATA_EXT_FIFO_CNT12 0x3U
20105 #define V_WR_DATA_EXT_FIFO_CNT12(x) ((x) << S_WR_DATA_EXT_FIFO_CNT12)
20106 #define G_WR_DATA_EXT_FIFO_CNT12(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT12) & M_WR_DATA_EXT_FIFO_CNT12)
20108 #define S_WR_CMD_TAG_FIFO_CNT12 26
20109 #define M_WR_CMD_TAG_FIFO_CNT12 0xfU
20110 #define V_WR_CMD_TAG_FIFO_CNT12(x) ((x) << S_WR_CMD_TAG_FIFO_CNT12)
20111 #define G_WR_CMD_TAG_FIFO_CNT12(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT12) & M_WR_CMD_TAG_FIFO_CNT12)
20113 #define S_WR_DATA_512B_FIFO_CNT12 18
20114 #define M_WR_DATA_512B_FIFO_CNT12 0xffU
20115 #define V_WR_DATA_512B_FIFO_CNT12(x) ((x) << S_WR_DATA_512B_FIFO_CNT12)
20116 #define G_WR_DATA_512B_FIFO_CNT12(x) (((x) >> S_WR_DATA_512B_FIFO_CNT12) & M_WR_DATA_512B_FIFO_CNT12)
20118 #define S_RD_DATA_ALIGN_FSM12 17
20119 #define V_RD_DATA_ALIGN_FSM12(x) ((x) << S_RD_DATA_ALIGN_FSM12)
20120 #define F_RD_DATA_ALIGN_FSM12 V_RD_DATA_ALIGN_FSM12(1U)
20122 #define S_RD_DATA_FETCH_FSM12 16
20123 #define V_RD_DATA_FETCH_FSM12(x) ((x) << S_RD_DATA_FETCH_FSM12)
20124 #define F_RD_DATA_FETCH_FSM12 V_RD_DATA_FETCH_FSM12(1U)
20126 #define S_COHERENCY_TX_FSM12 15
20127 #define V_COHERENCY_TX_FSM12(x) ((x) << S_COHERENCY_TX_FSM12)
20128 #define F_COHERENCY_TX_FSM12 V_COHERENCY_TX_FSM12(1U)
20130 #define S_COHERENCY_RX_FSM12 14
20131 #define V_COHERENCY_RX_FSM12(x) ((x) << S_COHERENCY_RX_FSM12)
20132 #define F_COHERENCY_RX_FSM12 V_COHERENCY_RX_FSM12(1U)
20134 #define S_ARB_REQ_FSM12 13
20135 #define V_ARB_REQ_FSM12(x) ((x) << S_ARB_REQ_FSM12)
20136 #define F_ARB_REQ_FSM12 V_ARB_REQ_FSM12(1U)
20138 #define S_CMD_SPLIT_FSM12 10
20139 #define M_CMD_SPLIT_FSM12 0x7U
20140 #define V_CMD_SPLIT_FSM12(x) ((x) << S_CMD_SPLIT_FSM12)
20141 #define G_CMD_SPLIT_FSM12(x) (((x) >> S_CMD_SPLIT_FSM12) & M_CMD_SPLIT_FSM12)
20143 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
20145 #define S_RD_CMD_TAG_FIFO_CNT0 8
20146 #define M_RD_CMD_TAG_FIFO_CNT0 0xffU
20147 #define V_RD_CMD_TAG_FIFO_CNT0(x) ((x) << S_RD_CMD_TAG_FIFO_CNT0)
20148 #define G_RD_CMD_TAG_FIFO_CNT0(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT0) & M_RD_CMD_TAG_FIFO_CNT0)
20150 #define S_RD_DATA_FIFO_CNT0 0
20151 #define M_RD_DATA_FIFO_CNT0 0xffU
20152 #define V_RD_DATA_FIFO_CNT0(x) ((x) << S_RD_DATA_FIFO_CNT0)
20153 #define G_RD_DATA_FIFO_CNT0(x) (((x) >> S_RD_DATA_FIFO_CNT0) & M_RD_DATA_FIFO_CNT0)
20155 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
20157 #define S_RD_CMD_TAG_FIFO_CNT1 8
20158 #define M_RD_CMD_TAG_FIFO_CNT1 0xffU
20159 #define V_RD_CMD_TAG_FIFO_CNT1(x) ((x) << S_RD_CMD_TAG_FIFO_CNT1)
20160 #define G_RD_CMD_TAG_FIFO_CNT1(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT1) & M_RD_CMD_TAG_FIFO_CNT1)
20162 #define S_RD_DATA_FIFO_CNT1 0
20163 #define M_RD_DATA_FIFO_CNT1 0xffU
20164 #define V_RD_DATA_FIFO_CNT1(x) ((x) << S_RD_DATA_FIFO_CNT1)
20165 #define G_RD_DATA_FIFO_CNT1(x) (((x) >> S_RD_DATA_FIFO_CNT1) & M_RD_DATA_FIFO_CNT1)
20167 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
20169 #define S_RD_CMD_TAG_FIFO_CNT2 8
20170 #define M_RD_CMD_TAG_FIFO_CNT2 0xffU
20171 #define V_RD_CMD_TAG_FIFO_CNT2(x) ((x) << S_RD_CMD_TAG_FIFO_CNT2)
20172 #define G_RD_CMD_TAG_FIFO_CNT2(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT2) & M_RD_CMD_TAG_FIFO_CNT2)
20174 #define S_RD_DATA_FIFO_CNT2 0
20175 #define M_RD_DATA_FIFO_CNT2 0xffU
20176 #define V_RD_DATA_FIFO_CNT2(x) ((x) << S_RD_DATA_FIFO_CNT2)
20177 #define G_RD_DATA_FIFO_CNT2(x) (((x) >> S_RD_DATA_FIFO_CNT2) & M_RD_DATA_FIFO_CNT2)
20179 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
20181 #define S_RD_CMD_TAG_FIFO_CNT3 8
20182 #define M_RD_CMD_TAG_FIFO_CNT3 0xffU
20183 #define V_RD_CMD_TAG_FIFO_CNT3(x) ((x) << S_RD_CMD_TAG_FIFO_CNT3)
20184 #define G_RD_CMD_TAG_FIFO_CNT3(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT3) & M_RD_CMD_TAG_FIFO_CNT3)
20186 #define S_RD_DATA_FIFO_CNT3 0
20187 #define M_RD_DATA_FIFO_CNT3 0xffU
20188 #define V_RD_DATA_FIFO_CNT3(x) ((x) << S_RD_DATA_FIFO_CNT3)
20189 #define G_RD_DATA_FIFO_CNT3(x) (((x) >> S_RD_DATA_FIFO_CNT3) & M_RD_DATA_FIFO_CNT3)
20191 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
20192 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
20193 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
20194 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
20195 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
20196 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
20197 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
20198 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
20199 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
20200 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
20201 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
20202 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
20203 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
20204 #define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
20205 #define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
20206 #define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
20207 #define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
20208 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
20209 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
20210 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
20211 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
20212 #define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
20213 #define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
20214 #define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
20215 #define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
20216 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
20217 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
20218 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
20219 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
20220 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
20221 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
20222 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
20223 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
20224 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
20225 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
20226 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
20227 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
20228 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
20229 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
20230 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
20231 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
20232 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
20233 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
20234 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
20235 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
20236 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
20237 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
20238 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
20239 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
20240 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
20241 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
20242 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
20243 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
20244 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
20245 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
20246 #define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
20248 #define S_PTMAXTRANS 16
20249 #define V_PTMAXTRANS(x) ((x) << S_PTMAXTRANS)
20250 #define F_PTMAXTRANS V_PTMAXTRANS(1U)
20252 #define S_PTFLITCNT 0
20253 #define M_PTFLITCNT 0xffU
20254 #define V_PTFLITCNT(x) ((x) << S_PTFLITCNT)
20255 #define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT)
20257 #define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
20259 #define S_PRMAXTRANS 16
20260 #define V_PRMAXTRANS(x) ((x) << S_PRMAXTRANS)
20261 #define F_PRMAXTRANS V_PRMAXTRANS(1U)
20263 #define S_PRFLITCNT 0
20264 #define M_PRFLITCNT 0xffU
20265 #define V_PRFLITCNT(x) ((x) << S_PRFLITCNT)
20266 #define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT)
20268 /* registers for module EDC_0 */
20269 #define EDC_0_BASE_ADDR 0x7900
20271 #define A_EDC_REF 0x7900
20273 #define S_EDC_INST_NUM 18
20274 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
20275 #define F_EDC_INST_NUM V_EDC_INST_NUM(1U)
20277 #define S_ENABLE_PERF 17
20278 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
20279 #define F_ENABLE_PERF V_ENABLE_PERF(1U)
20281 #define S_ECC_BYPASS 16
20282 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
20283 #define F_ECC_BYPASS V_ECC_BYPASS(1U)
20285 #define S_REFFREQ 0
20286 #define M_REFFREQ 0xffffU
20287 #define V_REFFREQ(x) ((x) << S_REFFREQ)
20288 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
20290 #define A_EDC_BIST_CMD 0x7904
20291 #define A_EDC_BIST_CMD_ADDR 0x7908
20292 #define A_EDC_BIST_CMD_LEN 0x790c
20293 #define A_EDC_BIST_DATA_PATTERN 0x7910
20294 #define A_EDC_BIST_USER_WDATA0 0x7914
20295 #define A_EDC_BIST_USER_WDATA1 0x7918
20296 #define A_EDC_BIST_USER_WDATA2 0x791c
20297 #define A_EDC_BIST_NUM_ERR 0x7920
20298 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
20299 #define A_EDC_BIST_STATUS_RDATA 0x7928
20300 #define A_EDC_PAR_ENABLE 0x7970
20303 #define V_ECC_UE(x) ((x) << S_ECC_UE)
20304 #define F_ECC_UE V_ECC_UE(1U)
20307 #define V_ECC_CE(x) ((x) << S_ECC_CE)
20308 #define F_ECC_CE V_ECC_CE(1U)
20310 #define A_EDC_INT_ENABLE 0x7974
20311 #define A_EDC_INT_CAUSE 0x7978
20313 #define S_ECC_UE_PAR 5
20314 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
20315 #define F_ECC_UE_PAR V_ECC_UE_PAR(1U)
20317 #define S_ECC_CE_PAR 4
20318 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
20319 #define F_ECC_CE_PAR V_ECC_CE_PAR(1U)
20321 #define S_PERR_PAR_CAUSE 3
20322 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
20323 #define F_PERR_PAR_CAUSE V_PERR_PAR_CAUSE(1U)
20325 #define A_EDC_ECC_STATUS 0x797c
20327 /* registers for module EDC_1 */
20328 #define EDC_1_BASE_ADDR 0x7980
20330 /* registers for module HMA */
20331 #define HMA_BASE_ADDR 0x7a00
20333 /* registers for module CIM */
20334 #define CIM_BASE_ADDR 0x7b00
20336 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
20338 #define S_VFMBGENERIC 4
20339 #define M_VFMBGENERIC 0xfU
20340 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
20341 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
20343 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
20345 #define S_MBVFREADY 0
20346 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
20347 #define F_MBVFREADY V_MBVFREADY(1U)
20349 #define A_CIM_PF_MAILBOX_DATA 0x240
20350 #define A_CIM_PF_MAILBOX_CTRL 0x280
20352 #define S_MBGENERIC 4
20353 #define M_MBGENERIC 0xfffffffU
20354 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
20355 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
20357 #define S_MBMSGVALID 3
20358 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
20359 #define F_MBMSGVALID V_MBMSGVALID(1U)
20361 #define S_MBINTREQ 2
20362 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
20363 #define F_MBINTREQ V_MBINTREQ(1U)
20365 #define S_MBOWNER 0
20366 #define M_MBOWNER 0x3U
20367 #define V_MBOWNER(x) ((x) << S_MBOWNER)
20368 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
20370 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
20372 #define S_MBWRBUSY 31
20373 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
20374 #define F_MBWRBUSY V_MBWRBUSY(1U)
20376 #define A_CIM_PF_HOST_INT_ENABLE 0x288
20378 #define S_MBMSGRDYINTEN 19
20379 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
20380 #define F_MBMSGRDYINTEN V_MBMSGRDYINTEN(1U)
20382 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
20384 #define S_MBMSGRDYINT 19
20385 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
20386 #define F_MBMSGRDYINT V_MBMSGRDYINT(1U)
20388 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
20389 #define A_CIM_BOOT_CFG 0x7b00
20391 #define S_BOOTADDR 8
20392 #define M_BOOTADDR 0xffffffU
20393 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
20394 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
20397 #define M_UPGEN 0x3fU
20398 #define V_UPGEN(x) ((x) << S_UPGEN)
20399 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
20401 #define S_BOOTSDRAM 1
20402 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
20403 #define F_BOOTSDRAM V_BOOTSDRAM(1U)
20406 #define V_UPCRST(x) ((x) << S_UPCRST)
20407 #define F_UPCRST V_UPCRST(1U)
20409 #define A_CIM_FLASH_BASE_ADDR 0x7b04
20411 #define S_FLASHBASEADDR 6
20412 #define M_FLASHBASEADDR 0x3ffffU
20413 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
20414 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
20416 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
20418 #define S_FLASHADDRSIZE 4
20419 #define M_FLASHADDRSIZE 0xfffffU
20420 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
20421 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
20423 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
20425 #define S_EEPROMBASEADDR 6
20426 #define M_EEPROMBASEADDR 0x3ffffU
20427 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
20428 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
20430 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
20432 #define S_EEPROMADDRSIZE 4
20433 #define M_EEPROMADDRSIZE 0xfffffU
20434 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
20435 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
20437 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
20439 #define S_SDRAMBASEADDR 6
20440 #define M_SDRAMBASEADDR 0x3ffffffU
20441 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
20442 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
20444 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
20446 #define S_SDRAMADDRSIZE 4
20447 #define M_SDRAMADDRSIZE 0xfffffffU
20448 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
20449 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
20451 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
20453 #define S_EXTMEM2BASEADDR 6
20454 #define M_EXTMEM2BASEADDR 0x3ffffffU
20455 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
20456 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
20458 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
20460 #define S_EXTMEM2ADDRSIZE 4
20461 #define M_EXTMEM2ADDRSIZE 0xfffffffU
20462 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
20463 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
20465 #define A_CIM_UP_SPARE_INT 0x7b24
20467 #define S_TDEBUGINT 4
20468 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
20469 #define F_TDEBUGINT V_TDEBUGINT(1U)
20471 #define S_BOOTVECSEL 3
20472 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
20473 #define F_BOOTVECSEL V_BOOTVECSEL(1U)
20475 #define S_UPSPAREINT 0
20476 #define M_UPSPAREINT 0x7U
20477 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
20478 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
20480 #define A_CIM_HOST_INT_ENABLE 0x7b28
20482 #define S_TIEQOUTPARERRINTEN 20
20483 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
20484 #define F_TIEQOUTPARERRINTEN V_TIEQOUTPARERRINTEN(1U)
20486 #define S_TIEQINPARERRINTEN 19
20487 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
20488 #define F_TIEQINPARERRINTEN V_TIEQINPARERRINTEN(1U)
20490 #define S_MBHOSTPARERR 18
20491 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
20492 #define F_MBHOSTPARERR V_MBHOSTPARERR(1U)
20494 #define S_MBUPPARERR 17
20495 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
20496 #define F_MBUPPARERR V_MBUPPARERR(1U)
20498 #define S_IBQTP0PARERR 16
20499 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
20500 #define F_IBQTP0PARERR V_IBQTP0PARERR(1U)
20502 #define S_IBQTP1PARERR 15
20503 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
20504 #define F_IBQTP1PARERR V_IBQTP1PARERR(1U)
20506 #define S_IBQULPPARERR 14
20507 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
20508 #define F_IBQULPPARERR V_IBQULPPARERR(1U)
20510 #define S_IBQSGELOPARERR 13
20511 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
20512 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U)
20514 #define S_IBQSGEHIPARERR 12
20515 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
20516 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U)
20518 #define S_IBQNCSIPARERR 11
20519 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
20520 #define F_IBQNCSIPARERR V_IBQNCSIPARERR(1U)
20522 #define S_OBQULP0PARERR 10
20523 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
20524 #define F_OBQULP0PARERR V_OBQULP0PARERR(1U)
20526 #define S_OBQULP1PARERR 9
20527 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
20528 #define F_OBQULP1PARERR V_OBQULP1PARERR(1U)
20530 #define S_OBQULP2PARERR 8
20531 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
20532 #define F_OBQULP2PARERR V_OBQULP2PARERR(1U)
20534 #define S_OBQULP3PARERR 7
20535 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
20536 #define F_OBQULP3PARERR V_OBQULP3PARERR(1U)
20538 #define S_OBQSGEPARERR 6
20539 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
20540 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U)
20542 #define S_OBQNCSIPARERR 5
20543 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
20544 #define F_OBQNCSIPARERR V_OBQNCSIPARERR(1U)
20546 #define S_TIMER1INTEN 3
20547 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
20548 #define F_TIMER1INTEN V_TIMER1INTEN(1U)
20550 #define S_TIMER0INTEN 2
20551 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
20552 #define F_TIMER0INTEN V_TIMER0INTEN(1U)
20554 #define S_PREFDROPINTEN 1
20555 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
20556 #define F_PREFDROPINTEN V_PREFDROPINTEN(1U)
20558 #define S_MA_CIM_INTFPERR 28
20559 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
20560 #define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U)
20562 #define S_PLCIM_MSTRSPDATAPARERR 27
20563 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
20564 #define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U)
20566 #define S_NCSI2CIMINTFPARERR 26
20567 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
20568 #define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U)
20570 #define S_SGE2CIMINTFPARERR 25
20571 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
20572 #define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U)
20574 #define S_ULP2CIMINTFPARERR 24
20575 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
20576 #define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U)
20578 #define S_TP2CIMINTFPARERR 23
20579 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
20580 #define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U)
20582 #define S_OBQSGERX1PARERR 22
20583 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
20584 #define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U)
20586 #define S_OBQSGERX0PARERR 21
20587 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
20588 #define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U)
20590 #define S_PCIE2CIMINTFPARERR 29
20591 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
20592 #define F_PCIE2CIMINTFPARERR V_PCIE2CIMINTFPARERR(1U)
20594 #define S_IBQPCIEPARERR 12
20595 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
20596 #define F_IBQPCIEPARERR V_IBQPCIEPARERR(1U)
20598 #define A_CIM_HOST_INT_CAUSE 0x7b2c
20600 #define S_TIEQOUTPARERRINT 20
20601 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
20602 #define F_TIEQOUTPARERRINT V_TIEQOUTPARERRINT(1U)
20604 #define S_TIEQINPARERRINT 19
20605 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
20606 #define F_TIEQINPARERRINT V_TIEQINPARERRINT(1U)
20608 #define S_TIMER1INT 3
20609 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
20610 #define F_TIMER1INT V_TIMER1INT(1U)
20612 #define S_TIMER0INT 2
20613 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
20614 #define F_TIMER0INT V_TIMER0INT(1U)
20616 #define S_PREFDROPINT 1
20617 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
20618 #define F_PREFDROPINT V_PREFDROPINT(1U)
20620 #define S_UPACCNONZERO 0
20621 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
20622 #define F_UPACCNONZERO V_UPACCNONZERO(1U)
20624 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
20626 #define S_EEPROMWRINTEN 30
20627 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
20628 #define F_EEPROMWRINTEN V_EEPROMWRINTEN(1U)
20630 #define S_TIMEOUTMAINTEN 29
20631 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
20632 #define F_TIMEOUTMAINTEN V_TIMEOUTMAINTEN(1U)
20634 #define S_TIMEOUTINTEN 28
20635 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
20636 #define F_TIMEOUTINTEN V_TIMEOUTINTEN(1U)
20638 #define S_RSPOVRLOOKUPINTEN 27
20639 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
20640 #define F_RSPOVRLOOKUPINTEN V_RSPOVRLOOKUPINTEN(1U)
20642 #define S_REQOVRLOOKUPINTEN 26
20643 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
20644 #define F_REQOVRLOOKUPINTEN V_REQOVRLOOKUPINTEN(1U)
20646 #define S_BLKWRPLINTEN 25
20647 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
20648 #define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U)
20650 #define S_BLKRDPLINTEN 24
20651 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
20652 #define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U)
20654 #define S_SGLWRPLINTEN 23
20655 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
20656 #define F_SGLWRPLINTEN V_SGLWRPLINTEN(1U)
20658 #define S_SGLRDPLINTEN 22
20659 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
20660 #define F_SGLRDPLINTEN V_SGLRDPLINTEN(1U)
20662 #define S_BLKWRCTLINTEN 21
20663 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
20664 #define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U)
20666 #define S_BLKRDCTLINTEN 20
20667 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
20668 #define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U)
20670 #define S_SGLWRCTLINTEN 19
20671 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
20672 #define F_SGLWRCTLINTEN V_SGLWRCTLINTEN(1U)
20674 #define S_SGLRDCTLINTEN 18
20675 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
20676 #define F_SGLRDCTLINTEN V_SGLRDCTLINTEN(1U)
20678 #define S_BLKWREEPROMINTEN 17
20679 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
20680 #define F_BLKWREEPROMINTEN V_BLKWREEPROMINTEN(1U)
20682 #define S_BLKRDEEPROMINTEN 16
20683 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
20684 #define F_BLKRDEEPROMINTEN V_BLKRDEEPROMINTEN(1U)
20686 #define S_SGLWREEPROMINTEN 15
20687 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
20688 #define F_SGLWREEPROMINTEN V_SGLWREEPROMINTEN(1U)
20690 #define S_SGLRDEEPROMINTEN 14
20691 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
20692 #define F_SGLRDEEPROMINTEN V_SGLRDEEPROMINTEN(1U)
20694 #define S_BLKWRFLASHINTEN 13
20695 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
20696 #define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U)
20698 #define S_BLKRDFLASHINTEN 12
20699 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
20700 #define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U)
20702 #define S_SGLWRFLASHINTEN 11
20703 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
20704 #define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U)
20706 #define S_SGLRDFLASHINTEN 10
20707 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
20708 #define F_SGLRDFLASHINTEN V_SGLRDFLASHINTEN(1U)
20710 #define S_BLKWRBOOTINTEN 9
20711 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
20712 #define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U)
20714 #define S_BLKRDBOOTINTEN 8
20715 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
20716 #define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U)
20718 #define S_SGLWRBOOTINTEN 7
20719 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
20720 #define F_SGLWRBOOTINTEN V_SGLWRBOOTINTEN(1U)
20722 #define S_SGLRDBOOTINTEN 6
20723 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
20724 #define F_SGLRDBOOTINTEN V_SGLRDBOOTINTEN(1U)
20726 #define S_ILLWRBEINTEN 5
20727 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
20728 #define F_ILLWRBEINTEN V_ILLWRBEINTEN(1U)
20730 #define S_ILLRDBEINTEN 4
20731 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
20732 #define F_ILLRDBEINTEN V_ILLRDBEINTEN(1U)
20734 #define S_ILLRDINTEN 3
20735 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
20736 #define F_ILLRDINTEN V_ILLRDINTEN(1U)
20738 #define S_ILLWRINTEN 2
20739 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
20740 #define F_ILLWRINTEN V_ILLWRINTEN(1U)
20742 #define S_ILLTRANSINTEN 1
20743 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
20744 #define F_ILLTRANSINTEN V_ILLTRANSINTEN(1U)
20746 #define S_RSVDSPACEINTEN 0
20747 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
20748 #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U)
20750 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
20752 #define S_EEPROMWRINT 30
20753 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
20754 #define F_EEPROMWRINT V_EEPROMWRINT(1U)
20756 #define S_TIMEOUTMAINT 29
20757 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
20758 #define F_TIMEOUTMAINT V_TIMEOUTMAINT(1U)
20760 #define S_TIMEOUTINT 28
20761 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
20762 #define F_TIMEOUTINT V_TIMEOUTINT(1U)
20764 #define S_RSPOVRLOOKUPINT 27
20765 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
20766 #define F_RSPOVRLOOKUPINT V_RSPOVRLOOKUPINT(1U)
20768 #define S_REQOVRLOOKUPINT 26
20769 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
20770 #define F_REQOVRLOOKUPINT V_REQOVRLOOKUPINT(1U)
20772 #define S_BLKWRPLINT 25
20773 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
20774 #define F_BLKWRPLINT V_BLKWRPLINT(1U)
20776 #define S_BLKRDPLINT 24
20777 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
20778 #define F_BLKRDPLINT V_BLKRDPLINT(1U)
20780 #define S_SGLWRPLINT 23
20781 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
20782 #define F_SGLWRPLINT V_SGLWRPLINT(1U)
20784 #define S_SGLRDPLINT 22
20785 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
20786 #define F_SGLRDPLINT V_SGLRDPLINT(1U)
20788 #define S_BLKWRCTLINT 21
20789 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
20790 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
20792 #define S_BLKRDCTLINT 20
20793 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
20794 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
20796 #define S_SGLWRCTLINT 19
20797 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
20798 #define F_SGLWRCTLINT V_SGLWRCTLINT(1U)
20800 #define S_SGLRDCTLINT 18
20801 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
20802 #define F_SGLRDCTLINT V_SGLRDCTLINT(1U)
20804 #define S_BLKWREEPROMINT 17
20805 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
20806 #define F_BLKWREEPROMINT V_BLKWREEPROMINT(1U)
20808 #define S_BLKRDEEPROMINT 16
20809 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
20810 #define F_BLKRDEEPROMINT V_BLKRDEEPROMINT(1U)
20812 #define S_SGLWREEPROMINT 15
20813 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
20814 #define F_SGLWREEPROMINT V_SGLWREEPROMINT(1U)
20816 #define S_SGLRDEEPROMINT 14
20817 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
20818 #define F_SGLRDEEPROMINT V_SGLRDEEPROMINT(1U)
20820 #define S_BLKWRFLASHINT 13
20821 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
20822 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
20824 #define S_BLKRDFLASHINT 12
20825 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
20826 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
20828 #define S_SGLWRFLASHINT 11
20829 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
20830 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
20832 #define S_SGLRDFLASHINT 10
20833 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
20834 #define F_SGLRDFLASHINT V_SGLRDFLASHINT(1U)
20836 #define S_BLKWRBOOTINT 9
20837 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
20838 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
20840 #define S_BLKRDBOOTINT 8
20841 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
20842 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U)
20844 #define S_SGLWRBOOTINT 7
20845 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
20846 #define F_SGLWRBOOTINT V_SGLWRBOOTINT(1U)
20848 #define S_SGLRDBOOTINT 6
20849 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
20850 #define F_SGLRDBOOTINT V_SGLRDBOOTINT(1U)
20852 #define S_ILLWRBEINT 5
20853 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
20854 #define F_ILLWRBEINT V_ILLWRBEINT(1U)
20856 #define S_ILLRDBEINT 4
20857 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
20858 #define F_ILLRDBEINT V_ILLRDBEINT(1U)
20860 #define S_ILLRDINT 3
20861 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
20862 #define F_ILLRDINT V_ILLRDINT(1U)
20864 #define S_ILLWRINT 2
20865 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
20866 #define F_ILLWRINT V_ILLWRINT(1U)
20868 #define S_ILLTRANSINT 1
20869 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
20870 #define F_ILLTRANSINT V_ILLTRANSINT(1U)
20872 #define S_RSVDSPACEINT 0
20873 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
20874 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
20876 #define A_CIM_UP_INT_ENABLE 0x7b38
20878 #define S_MSTPLINTEN 4
20879 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
20880 #define F_MSTPLINTEN V_MSTPLINTEN(1U)
20882 #define A_CIM_UP_INT_CAUSE 0x7b3c
20884 #define S_MSTPLINT 4
20885 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
20886 #define F_MSTPLINT V_MSTPLINT(1U)
20888 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
20889 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
20890 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
20892 #define S_OBQSELECT 4
20893 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
20894 #define F_OBQSELECT V_OBQSELECT(1U)
20896 #define S_IBQSELECT 3
20897 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
20898 #define F_IBQSELECT V_IBQSELECT(1U)
20900 #define S_QUENUMSELECT 0
20901 #define M_QUENUMSELECT 0x7U
20902 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
20903 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
20905 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
20907 #define S_CIMQSIZE 24
20908 #define M_CIMQSIZE 0x3fU
20909 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
20910 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
20912 #define S_CIMQBASE 16
20913 #define M_CIMQBASE 0x3fU
20914 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
20915 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
20917 #define S_CIMQDBG8BEN 9
20918 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
20919 #define F_CIMQDBG8BEN V_CIMQDBG8BEN(1U)
20921 #define S_QUEFULLTHRSH 0
20922 #define M_QUEFULLTHRSH 0x1ffU
20923 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
20924 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
20926 #define S_CIMQ1KEN 30
20927 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
20928 #define F_CIMQ1KEN V_CIMQ1KEN(1U)
20930 #define A_CIM_HOST_ACC_CTRL 0x7b50
20932 #define S_HOSTBUSY 17
20933 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
20934 #define F_HOSTBUSY V_HOSTBUSY(1U)
20936 #define S_HOSTWRITE 16
20937 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
20938 #define F_HOSTWRITE V_HOSTWRITE(1U)
20940 #define S_HOSTADDR 0
20941 #define M_HOSTADDR 0xffffU
20942 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
20943 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
20945 #define A_CIM_HOST_ACC_DATA 0x7b54
20946 #define A_CIM_CDEBUGDATA 0x7b58
20948 #define S_CDEBUGDATAH 16
20949 #define M_CDEBUGDATAH 0xffffU
20950 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
20951 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
20953 #define S_CDEBUGDATAL 0
20954 #define M_CDEBUGDATAL 0xffffU
20955 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
20956 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
20958 #define A_CIM_IBQ_DBG_CFG 0x7b60
20960 #define S_IBQDBGADDR 16
20961 #define M_IBQDBGADDR 0xfffU
20962 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
20963 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
20965 #define S_IBQDBGWR 2
20966 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
20967 #define F_IBQDBGWR V_IBQDBGWR(1U)
20969 #define S_IBQDBGBUSY 1
20970 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
20971 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U)
20973 #define S_IBQDBGEN 0
20974 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
20975 #define F_IBQDBGEN V_IBQDBGEN(1U)
20977 #define A_CIM_OBQ_DBG_CFG 0x7b64
20979 #define S_OBQDBGADDR 16
20980 #define M_OBQDBGADDR 0xfffU
20981 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
20982 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
20984 #define S_OBQDBGWR 2
20985 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
20986 #define F_OBQDBGWR V_OBQDBGWR(1U)
20988 #define S_OBQDBGBUSY 1
20989 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
20990 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U)
20992 #define S_OBQDBGEN 0
20993 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
20994 #define F_OBQDBGEN V_OBQDBGEN(1U)
20996 #define A_CIM_IBQ_DBG_DATA 0x7b68
20997 #define A_CIM_OBQ_DBG_DATA 0x7b6c
20998 #define A_CIM_DEBUGCFG 0x7b70
21000 #define S_POLADBGRDPTR 23
21001 #define M_POLADBGRDPTR 0x1ffU
21002 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
21003 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
21005 #define S_PILADBGRDPTR 14
21006 #define M_PILADBGRDPTR 0x1ffU
21007 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
21008 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
21010 #define S_LAMASKTRIG 13
21011 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
21012 #define F_LAMASKTRIG V_LAMASKTRIG(1U)
21014 #define S_LADBGEN 12
21015 #define V_LADBGEN(x) ((x) << S_LADBGEN)
21016 #define F_LADBGEN V_LADBGEN(1U)
21018 #define S_LAFILLONCE 11
21019 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
21020 #define F_LAFILLONCE V_LAFILLONCE(1U)
21022 #define S_LAMASKSTOP 10
21023 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
21024 #define F_LAMASKSTOP V_LAMASKSTOP(1U)
21026 #define S_DEBUGSELH 5
21027 #define M_DEBUGSELH 0x1fU
21028 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
21029 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
21031 #define S_DEBUGSELL 0
21032 #define M_DEBUGSELL 0x1fU
21033 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
21034 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
21036 #define A_CIM_DEBUGSTS 0x7b74
21038 #define S_LARESET 31
21039 #define V_LARESET(x) ((x) << S_LARESET)
21040 #define F_LARESET V_LARESET(1U)
21042 #define S_POLADBGWRPTR 16
21043 #define M_POLADBGWRPTR 0x1ffU
21044 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
21045 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
21047 #define S_PILADBGWRPTR 0
21048 #define M_PILADBGWRPTR 0x1ffU
21049 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
21050 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
21052 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
21053 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
21054 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
21055 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
21056 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
21057 #define A_CIM_MEM_ZONE0_VA 0x7b90
21059 #define S_MEM_ZONE_VA 4
21060 #define M_MEM_ZONE_VA 0xfffffffU
21061 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
21062 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
21064 #define A_CIM_MEM_ZONE0_BA 0x7b94
21066 #define S_MEM_ZONE_BA 6
21067 #define M_MEM_ZONE_BA 0x3ffffffU
21068 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
21069 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
21071 #define S_PBT_ENABLE 5
21072 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
21073 #define F_PBT_ENABLE V_PBT_ENABLE(1U)
21075 #define S_ZONE_DST 0
21076 #define M_ZONE_DST 0x3U
21077 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
21078 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
21080 #define A_CIM_MEM_ZONE0_LEN 0x7b98
21082 #define S_MEM_ZONE_LEN 4
21083 #define M_MEM_ZONE_LEN 0xfffffffU
21084 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
21085 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
21087 #define A_CIM_MEM_ZONE1_VA 0x7b9c
21088 #define A_CIM_MEM_ZONE1_BA 0x7ba0
21089 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
21090 #define A_CIM_MEM_ZONE2_VA 0x7ba8
21091 #define A_CIM_MEM_ZONE2_BA 0x7bac
21092 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
21093 #define A_CIM_MEM_ZONE3_VA 0x7bb4
21094 #define A_CIM_MEM_ZONE3_BA 0x7bb8
21095 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
21096 #define A_CIM_MEM_ZONE4_VA 0x7bc0
21097 #define A_CIM_MEM_ZONE4_BA 0x7bc4
21098 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
21099 #define A_CIM_MEM_ZONE5_VA 0x7bcc
21100 #define A_CIM_MEM_ZONE5_BA 0x7bd0
21101 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
21102 #define A_CIM_MEM_ZONE6_VA 0x7bd8
21103 #define A_CIM_MEM_ZONE6_BA 0x7bdc
21104 #define A_CIM_MEM_ZONE6_LEN 0x7be0
21105 #define A_CIM_MEM_ZONE7_VA 0x7be4
21106 #define A_CIM_MEM_ZONE7_BA 0x7be8
21107 #define A_CIM_MEM_ZONE7_LEN 0x7bec
21108 #define A_CIM_BOOT_LEN 0x7bf0
21110 #define S_BOOTLEN 4
21111 #define M_BOOTLEN 0xfffffffU
21112 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
21113 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
21115 #define A_CIM_GLB_TIMER_CTL 0x7bf4
21117 #define S_TIMER1EN 4
21118 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
21119 #define F_TIMER1EN V_TIMER1EN(1U)
21121 #define S_TIMER0EN 3
21122 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
21123 #define F_TIMER0EN V_TIMER0EN(1U)
21125 #define S_TIMEREN 1
21126 #define V_TIMEREN(x) ((x) << S_TIMEREN)
21127 #define F_TIMEREN V_TIMEREN(1U)
21129 #define A_CIM_GLB_TIMER 0x7bf8
21130 #define A_CIM_GLB_TIMER_TICK 0x7bfc
21132 #define S_GLBLTTICK 0
21133 #define M_GLBLTTICK 0xffffU
21134 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
21135 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
21137 #define A_CIM_TIMER0 0x7c00
21138 #define A_CIM_TIMER1 0x7c04
21139 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
21141 #define S_DADDRTIMEOUT 2
21142 #define M_DADDRTIMEOUT 0x3fffffffU
21143 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
21144 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
21146 #define S_DADDRTIMEOUTTYPE 0
21147 #define M_DADDRTIMEOUTTYPE 0x3U
21148 #define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE)
21149 #define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE)
21151 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
21153 #define S_DADDRILLEGAL 2
21154 #define M_DADDRILLEGAL 0x3fffffffU
21155 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
21156 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
21158 #define S_DADDRILLEGALTYPE 0
21159 #define M_DADDRILLEGALTYPE 0x3U
21160 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
21161 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
21163 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
21165 #define S_DPIFHOSTMASK 0
21166 #define M_DPIFHOSTMASK 0x1fffffU
21167 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
21168 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
21170 #define S_T5_DPIFHOSTMASK 0
21171 #define M_T5_DPIFHOSTMASK 0x1fffffffU
21172 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
21173 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
21175 #define S_T6_T5_DPIFHOSTMASK 0
21176 #define M_T6_T5_DPIFHOSTMASK 0x3fffffffU
21177 #define V_T6_T5_DPIFHOSTMASK(x) ((x) << S_T6_T5_DPIFHOSTMASK)
21178 #define G_T6_T5_DPIFHOSTMASK(x) (((x) >> S_T6_T5_DPIFHOSTMASK) & M_T6_T5_DPIFHOSTMASK)
21180 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
21182 #define S_DPIFHUPAMASK 0
21183 #define M_DPIFHUPAMASK 0x7fffffffU
21184 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
21185 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
21187 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
21189 #define S_DUPMASK 0
21190 #define M_DUPMASK 0x1fffffU
21191 #define V_DUPMASK(x) ((x) << S_DUPMASK)
21192 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
21194 #define S_T5_DUPMASK 0
21195 #define M_T5_DUPMASK 0x1fffffffU
21196 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
21197 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
21199 #define S_T6_T5_DUPMASK 0
21200 #define M_T6_T5_DUPMASK 0x3fffffffU
21201 #define V_T6_T5_DUPMASK(x) ((x) << S_T6_T5_DUPMASK)
21202 #define G_T6_T5_DUPMASK(x) (((x) >> S_T6_T5_DUPMASK) & M_T6_T5_DUPMASK)
21204 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
21206 #define S_DUPUACCMASK 0
21207 #define M_DUPUACCMASK 0x7fffffffU
21208 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
21209 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
21211 #define A_CIM_PERR_INJECT 0x7c20
21212 #define A_CIM_PERR_ENABLE 0x7c24
21215 #define M_PERREN 0x1fffffU
21216 #define V_PERREN(x) ((x) << S_PERREN)
21217 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
21219 #define S_T5_PERREN 0
21220 #define M_T5_PERREN 0x1fffffffU
21221 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
21222 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
21224 #define S_T6_T5_PERREN 0
21225 #define M_T6_T5_PERREN 0x3fffffffU
21226 #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
21227 #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
21229 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
21231 #define S_EEPROMBUSY 0
21232 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
21233 #define F_EEPROMBUSY V_EEPROMBUSY(1U)
21235 #define A_CIM_MA_TIMER_EN 0x7c2c
21237 #define S_MA_TIMER_ENABLE 0
21238 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
21239 #define F_MA_TIMER_ENABLE V_MA_TIMER_ENABLE(1U)
21241 #define S_SLOW_TIMER_ENABLE 1
21242 #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
21243 #define F_SLOW_TIMER_ENABLE V_SLOW_TIMER_ENABLE(1U)
21245 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
21247 #define S_UP_PO_SINGLE_OUTSTANDING 0
21248 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
21249 #define F_UP_PO_SINGLE_OUTSTANDING V_UP_PO_SINGLE_OUTSTANDING(1U)
21251 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
21252 #define A_CIM_UP_OPERATION_FREQ 0x7c38
21253 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
21255 #define S_CIM_ULP_TX_PKT_ERR_CODE 16
21256 #define M_CIM_ULP_TX_PKT_ERR_CODE 0xffU
21257 #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
21258 #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
21260 #define S_CIM_SGE1_PKT_ERR_CODE 8
21261 #define M_CIM_SGE1_PKT_ERR_CODE 0xffU
21262 #define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
21263 #define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
21265 #define S_CIM_SGE0_PKT_ERR_CODE 0
21266 #define M_CIM_SGE0_PKT_ERR_CODE 0xffU
21267 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
21268 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
21270 #define S_CIM_PCIE_PKT_ERR_CODE 8
21271 #define M_CIM_PCIE_PKT_ERR_CODE 0xffU
21272 #define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE)
21273 #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
21275 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
21276 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
21278 #define S_PIO_UP_MST_CFG_SEL 0
21279 #define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
21280 #define F_PIO_UP_MST_CFG_SEL V_PIO_UP_MST_CFG_SEL(1U)
21282 #define A_CIM_CGEN 0x7c48
21284 #define S_TSCH_CGEN 0
21285 #define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
21286 #define F_TSCH_CGEN V_TSCH_CGEN(1U)
21288 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
21290 #define S_OBQ_THROUTTLE_ON_EOP 4
21291 #define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
21292 #define F_OBQ_THROUTTLE_ON_EOP V_OBQ_THROUTTLE_ON_EOP(1U)
21294 #define S_OBQ_READ_CTL_PERF_MODE_DISABLE 3
21295 #define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
21296 #define F_OBQ_READ_CTL_PERF_MODE_DISABLE V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
21298 #define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE 2
21299 #define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
21300 #define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
21302 #define S_IBQ_RRA_DSBL 1
21303 #define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
21304 #define F_IBQ_RRA_DSBL V_IBQ_RRA_DSBL(1U)
21306 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL 0
21307 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
21308 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
21310 #define S_PCIE_OBQ_IF_DISABLE 5
21311 #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
21312 #define F_PCIE_OBQ_IF_DISABLE V_PCIE_OBQ_IF_DISABLE(1U)
21314 #define A_CIM_CGEN_GLOBAL 0x7c50
21316 #define S_CGEN_GLOBAL 0
21317 #define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
21318 #define F_CGEN_GLOBAL V_CGEN_GLOBAL(1U)
21320 #define A_CIM_DPSLP_EN 0x7c54
21322 #define S_PIFDBGLA_DPSLP_EN 0
21323 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
21324 #define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U)
21326 /* registers for module TP */
21327 #define TP_BASE_ADDR 0x7d00
21329 #define A_TP_IN_CONFIG 0x7d00
21331 #define S_TCPOPTPARSERDISCH3 27
21332 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
21333 #define F_TCPOPTPARSERDISCH3 V_TCPOPTPARSERDISCH3(1U)
21335 #define S_TCPOPTPARSERDISCH2 26
21336 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
21337 #define F_TCPOPTPARSERDISCH2 V_TCPOPTPARSERDISCH2(1U)
21339 #define S_TCPOPTPARSERDISCH1 25
21340 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
21341 #define F_TCPOPTPARSERDISCH1 V_TCPOPTPARSERDISCH1(1U)
21343 #define S_TCPOPTPARSERDISCH0 24
21344 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
21345 #define F_TCPOPTPARSERDISCH0 V_TCPOPTPARSERDISCH0(1U)
21347 #define S_CRCPASSPRT3 23
21348 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
21349 #define F_CRCPASSPRT3 V_CRCPASSPRT3(1U)
21351 #define S_CRCPASSPRT2 22
21352 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
21353 #define F_CRCPASSPRT2 V_CRCPASSPRT2(1U)
21355 #define S_CRCPASSPRT1 21
21356 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
21357 #define F_CRCPASSPRT1 V_CRCPASSPRT1(1U)
21359 #define S_CRCPASSPRT0 20
21360 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
21361 #define F_CRCPASSPRT0 V_CRCPASSPRT0(1U)
21363 #define S_VEPAMODE 19
21364 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
21365 #define F_VEPAMODE V_VEPAMODE(1U)
21367 #define S_FIPUPEN 18
21368 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
21369 #define F_FIPUPEN V_FIPUPEN(1U)
21371 #define S_FCOEUPEN 17
21372 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
21373 #define F_FCOEUPEN V_FCOEUPEN(1U)
21375 #define S_FCOEENABLE 16
21376 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
21377 #define F_FCOEENABLE V_FCOEENABLE(1U)
21379 #define S_IPV6ENABLE 15
21380 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
21381 #define F_IPV6ENABLE V_IPV6ENABLE(1U)
21383 #define S_NICMODE 14
21384 #define V_NICMODE(x) ((x) << S_NICMODE)
21385 #define F_NICMODE V_NICMODE(1U)
21387 #define S_ECHECKSUMCHECKTCP 13
21388 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
21389 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U)
21391 #define S_ECHECKSUMCHECKIP 12
21392 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
21393 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U)
21395 #define S_EREPORTUDPHDRLEN 11
21396 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
21397 #define F_EREPORTUDPHDRLEN V_EREPORTUDPHDRLEN(1U)
21399 #define S_IN_ECPL 10
21400 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
21401 #define F_IN_ECPL V_IN_ECPL(1U)
21403 #define S_VNTAGENABLE 9
21404 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
21405 #define F_VNTAGENABLE V_VNTAGENABLE(1U)
21407 #define S_IN_EETH 8
21408 #define V_IN_EETH(x) ((x) << S_IN_EETH)
21409 #define F_IN_EETH V_IN_EETH(1U)
21411 #define S_CCHECKSUMCHECKTCP 6
21412 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
21413 #define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U)
21415 #define S_CCHECKSUMCHECKIP 5
21416 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
21417 #define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U)
21420 #define V_CTAG(x) ((x) << S_CTAG)
21421 #define F_CTAG V_CTAG(1U)
21423 #define S_IN_CCPL 3
21424 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
21425 #define F_IN_CCPL V_IN_CCPL(1U)
21427 #define S_IN_CETH 1
21428 #define V_IN_CETH(x) ((x) << S_IN_CETH)
21429 #define F_IN_CETH V_IN_CETH(1U)
21431 #define S_CTUNNEL 0
21432 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
21433 #define F_CTUNNEL V_CTUNNEL(1U)
21435 #define S_VLANEXTENPORT3 31
21436 #define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
21437 #define F_VLANEXTENPORT3 V_VLANEXTENPORT3(1U)
21439 #define S_VLANEXTENPORT2 30
21440 #define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
21441 #define F_VLANEXTENPORT2 V_VLANEXTENPORT2(1U)
21443 #define S_VLANEXTENPORT1 29
21444 #define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
21445 #define F_VLANEXTENPORT1 V_VLANEXTENPORT1(1U)
21447 #define S_VLANEXTENPORT0 28
21448 #define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
21449 #define F_VLANEXTENPORT0 V_VLANEXTENPORT0(1U)
21451 #define S_VNTAGDEFAULTVAL 13
21452 #define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
21453 #define F_VNTAGDEFAULTVAL V_VNTAGDEFAULTVAL(1U)
21455 #define S_ECHECKUDPLEN 12
21456 #define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
21457 #define F_ECHECKUDPLEN V_ECHECKUDPLEN(1U)
21459 #define S_FCOEFPMA 10
21460 #define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
21461 #define F_FCOEFPMA V_FCOEFPMA(1U)
21463 #define S_VNTAGETHENABLE 8
21464 #define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
21465 #define F_VNTAGETHENABLE V_VNTAGETHENABLE(1U)
21467 #define S_IP_CCSM 7
21468 #define V_IP_CCSM(x) ((x) << S_IP_CCSM)
21469 #define F_IP_CCSM V_IP_CCSM(1U)
21471 #define S_CCHECKSUMCHECKUDP 6
21472 #define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
21473 #define F_CCHECKSUMCHECKUDP V_CCHECKSUMCHECKUDP(1U)
21475 #define S_TCP_CCSM 5
21476 #define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
21477 #define F_TCP_CCSM V_TCP_CCSM(1U)
21480 #define V_CDEMUX(x) ((x) << S_CDEMUX)
21481 #define F_CDEMUX V_CDEMUX(1U)
21483 #define S_ETHUPEN 2
21484 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
21485 #define F_ETHUPEN V_ETHUPEN(1U)
21487 #define S_CXOFFOVERRIDE 3
21488 #define V_CXOFFOVERRIDE(x) ((x) << S_CXOFFOVERRIDE)
21489 #define F_CXOFFOVERRIDE V_CXOFFOVERRIDE(1U)
21491 #define S_EGREDROPEN 1
21492 #define V_EGREDROPEN(x) ((x) << S_EGREDROPEN)
21493 #define F_EGREDROPEN V_EGREDROPEN(1U)
21495 #define S_CFASTDEMUXEN 0
21496 #define V_CFASTDEMUXEN(x) ((x) << S_CFASTDEMUXEN)
21497 #define F_CFASTDEMUXEN V_CFASTDEMUXEN(1U)
21499 #define A_TP_OUT_CONFIG 0x7d04
21501 #define S_PORTQFCEN 28
21502 #define M_PORTQFCEN 0xfU
21503 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
21504 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
21506 #define S_EPKTDISTCHN3 23
21507 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
21508 #define F_EPKTDISTCHN3 V_EPKTDISTCHN3(1U)
21510 #define S_EPKTDISTCHN2 22
21511 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
21512 #define F_EPKTDISTCHN2 V_EPKTDISTCHN2(1U)
21514 #define S_EPKTDISTCHN1 21
21515 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
21516 #define F_EPKTDISTCHN1 V_EPKTDISTCHN1(1U)
21518 #define S_EPKTDISTCHN0 20
21519 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
21520 #define F_EPKTDISTCHN0 V_EPKTDISTCHN0(1U)
21522 #define S_TTLMODE 19
21523 #define V_TTLMODE(x) ((x) << S_TTLMODE)
21524 #define F_TTLMODE V_TTLMODE(1U)
21526 #define S_EQFCDMAC 18
21527 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
21528 #define F_EQFCDMAC V_EQFCDMAC(1U)
21530 #define S_ELPBKINCMPSSTAT 17
21531 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
21532 #define F_ELPBKINCMPSSTAT V_ELPBKINCMPSSTAT(1U)
21534 #define S_IPIDSPLITMODE 16
21535 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
21536 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U)
21538 #define S_VLANEXTENABLEPORT3 15
21539 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
21540 #define F_VLANEXTENABLEPORT3 V_VLANEXTENABLEPORT3(1U)
21542 #define S_VLANEXTENABLEPORT2 14
21543 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
21544 #define F_VLANEXTENABLEPORT2 V_VLANEXTENABLEPORT2(1U)
21546 #define S_VLANEXTENABLEPORT1 13
21547 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
21548 #define F_VLANEXTENABLEPORT1 V_VLANEXTENABLEPORT1(1U)
21550 #define S_VLANEXTENABLEPORT0 12
21551 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
21552 #define F_VLANEXTENABLEPORT0 V_VLANEXTENABLEPORT0(1U)
21554 #define S_ECHECKSUMINSERTTCP 11
21555 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
21556 #define F_ECHECKSUMINSERTTCP V_ECHECKSUMINSERTTCP(1U)
21558 #define S_ECHECKSUMINSERTIP 10
21559 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
21560 #define F_ECHECKSUMINSERTIP V_ECHECKSUMINSERTIP(1U)
21563 #define V_ECPL(x) ((x) << S_ECPL)
21564 #define F_ECPL V_ECPL(1U)
21566 #define S_EPRIORITY 7
21567 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
21568 #define F_EPRIORITY V_EPRIORITY(1U)
21570 #define S_EETHERNET 6
21571 #define V_EETHERNET(x) ((x) << S_EETHERNET)
21572 #define F_EETHERNET V_EETHERNET(1U)
21574 #define S_CCHECKSUMINSERTTCP 5
21575 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
21576 #define F_CCHECKSUMINSERTTCP V_CCHECKSUMINSERTTCP(1U)
21578 #define S_CCHECKSUMINSERTIP 4
21579 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
21580 #define F_CCHECKSUMINSERTIP V_CCHECKSUMINSERTIP(1U)
21583 #define V_CCPL(x) ((x) << S_CCPL)
21584 #define F_CCPL V_CCPL(1U)
21586 #define S_CETHERNET 0
21587 #define V_CETHERNET(x) ((x) << S_CETHERNET)
21588 #define F_CETHERNET V_CETHERNET(1U)
21590 #define S_EVNTAGEN 9
21591 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
21592 #define F_EVNTAGEN V_EVNTAGEN(1U)
21594 #define S_CCPLACKMODE 13
21595 #define V_CCPLACKMODE(x) ((x) << S_CCPLACKMODE)
21596 #define F_CCPLACKMODE V_CCPLACKMODE(1U)
21598 #define S_RMWHINTENABLE 12
21599 #define V_RMWHINTENABLE(x) ((x) << S_RMWHINTENABLE)
21600 #define F_RMWHINTENABLE V_RMWHINTENABLE(1U)
21602 #define S_EV6FLWEN 8
21603 #define V_EV6FLWEN(x) ((x) << S_EV6FLWEN)
21604 #define F_EV6FLWEN V_EV6FLWEN(1U)
21606 #define S_EVLANPRIO 6
21607 #define V_EVLANPRIO(x) ((x) << S_EVLANPRIO)
21608 #define F_EVLANPRIO V_EVLANPRIO(1U)
21610 #define S_CRXPKTENC 3
21611 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
21612 #define F_CRXPKTENC V_CRXPKTENC(1U)
21614 #define S_CRXPKTXT 1
21615 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
21616 #define F_CRXPKTXT V_CRXPKTXT(1U)
21618 #define A_TP_GLOBAL_CONFIG 0x7d08
21620 #define S_SYNCOOKIEPARAMS 26
21621 #define M_SYNCOOKIEPARAMS 0x3fU
21622 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
21623 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
21625 #define S_RXFLOWCONTROLDISABLE 25
21626 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
21627 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U)
21629 #define S_TXPACINGENABLE 24
21630 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
21631 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
21633 #define S_ATTACKFILTERENABLE 23
21634 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
21635 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U)
21637 #define S_SYNCOOKIENOOPTIONS 22
21638 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
21639 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U)
21641 #define S_PROTECTEDMODE 21
21642 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
21643 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U)
21645 #define S_PINGDROP 20
21646 #define V_PINGDROP(x) ((x) << S_PINGDROP)
21647 #define F_PINGDROP V_PINGDROP(1U)
21649 #define S_FRAGMENTDROP 19
21650 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
21651 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U)
21653 #define S_FIVETUPLELOOKUP 17
21654 #define M_FIVETUPLELOOKUP 0x3U
21655 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
21656 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
21658 #define S_OFDMPSSTATS 16
21659 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
21660 #define F_OFDMPSSTATS V_OFDMPSSTATS(1U)
21662 #define S_DONTFRAGMENT 15
21663 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
21664 #define F_DONTFRAGMENT V_DONTFRAGMENT(1U)
21666 #define S_IPIDENTSPLIT 14
21667 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
21668 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U)
21670 #define S_IPCHECKSUMOFFLOAD 13
21671 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
21672 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
21674 #define S_UDPCHECKSUMOFFLOAD 12
21675 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
21676 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
21678 #define S_TCPCHECKSUMOFFLOAD 11
21679 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
21680 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
21682 #define S_RSSLOOPBACKENABLE 10
21683 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
21684 #define F_RSSLOOPBACKENABLE V_RSSLOOPBACKENABLE(1U)
21686 #define S_TCAMSERVERUSE 8
21687 #define M_TCAMSERVERUSE 0x3U
21688 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
21689 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
21692 #define M_IPTTL 0xffU
21693 #define V_IPTTL(x) ((x) << S_IPTTL)
21694 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
21696 #define S_RSSSYNSTEERENABLE 12
21697 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
21698 #define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U)
21700 #define S_ISSFROMCPLENABLE 11
21701 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
21702 #define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U)
21704 #define S_ACTIVEFILTERCOUNTS 22
21705 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
21706 #define F_ACTIVEFILTERCOUNTS V_ACTIVEFILTERCOUNTS(1U)
21708 #define A_TP_DB_CONFIG 0x7d0c
21710 #define S_DBMAXOPCNT 24
21711 #define M_DBMAXOPCNT 0xffU
21712 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
21713 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
21715 #define S_CXMAXOPCNTDISABLE 23
21716 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
21717 #define F_CXMAXOPCNTDISABLE V_CXMAXOPCNTDISABLE(1U)
21719 #define S_CXMAXOPCNT 16
21720 #define M_CXMAXOPCNT 0x7fU
21721 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
21722 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
21724 #define S_TXMAXOPCNTDISABLE 15
21725 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
21726 #define F_TXMAXOPCNTDISABLE V_TXMAXOPCNTDISABLE(1U)
21728 #define S_TXMAXOPCNT 8
21729 #define M_TXMAXOPCNT 0x7fU
21730 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
21731 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
21733 #define S_RXMAXOPCNTDISABLE 7
21734 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
21735 #define F_RXMAXOPCNTDISABLE V_RXMAXOPCNTDISABLE(1U)
21737 #define S_RXMAXOPCNT 0
21738 #define M_RXMAXOPCNT 0x7fU
21739 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
21740 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
21742 #define A_TP_CMM_TCB_BASE 0x7d10
21743 #define A_TP_CMM_MM_BASE 0x7d14
21744 #define A_TP_CMM_TIMER_BASE 0x7d18
21745 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
21747 #define S_RXPOOLSIZE 16
21748 #define M_RXPOOLSIZE 0xffffU
21749 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
21750 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
21752 #define S_TXPOOLSIZE 0
21753 #define M_TXPOOLSIZE 0xffffU
21754 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
21755 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
21757 #define A_TP_PMM_TX_BASE 0x7d20
21758 #define A_TP_PMM_DEFRAG_BASE 0x7d24
21759 #define A_TP_PMM_RX_BASE 0x7d28
21760 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
21761 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
21763 #define S_PMRXNUMCHN 31
21764 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
21765 #define F_PMRXNUMCHN V_PMRXNUMCHN(1U)
21767 #define S_PMRXMAXPAGE 0
21768 #define M_PMRXMAXPAGE 0x1fffffU
21769 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
21770 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
21772 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
21773 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
21775 #define S_PMTXNUMCHN 30
21776 #define M_PMTXNUMCHN 0x3U
21777 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
21778 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
21780 #define S_PMTXMAXPAGE 0
21781 #define M_PMTXMAXPAGE 0x1fffffU
21782 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
21783 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
21785 #define A_TP_TCP_OPTIONS 0x7d40
21787 #define S_MTUDEFAULT 16
21788 #define M_MTUDEFAULT 0xffffU
21789 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
21790 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
21792 #define S_MTUENABLE 10
21793 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
21794 #define F_MTUENABLE V_MTUENABLE(1U)
21797 #define V_SACKTX(x) ((x) << S_SACKTX)
21798 #define F_SACKTX V_SACKTX(1U)
21801 #define V_SACKRX(x) ((x) << S_SACKRX)
21802 #define F_SACKRX V_SACKRX(1U)
21804 #define S_SACKMODE 4
21805 #define M_SACKMODE 0x3U
21806 #define V_SACKMODE(x) ((x) << S_SACKMODE)
21807 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
21809 #define S_WINDOWSCALEMODE 2
21810 #define M_WINDOWSCALEMODE 0x3U
21811 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
21812 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
21814 #define S_TIMESTAMPSMODE 0
21815 #define M_TIMESTAMPSMODE 0x3U
21816 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
21817 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
21819 #define A_TP_DACK_CONFIG 0x7d44
21821 #define S_AUTOSTATE3 30
21822 #define M_AUTOSTATE3 0x3U
21823 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
21824 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
21826 #define S_AUTOSTATE2 28
21827 #define M_AUTOSTATE2 0x3U
21828 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
21829 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
21831 #define S_AUTOSTATE1 26
21832 #define M_AUTOSTATE1 0x3U
21833 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
21834 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
21836 #define S_BYTETHRESHOLD 8
21837 #define M_BYTETHRESHOLD 0x3ffffU
21838 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
21839 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
21841 #define S_MSSTHRESHOLD 4
21842 #define M_MSSTHRESHOLD 0x7U
21843 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
21844 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
21846 #define S_AUTOCAREFUL 2
21847 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
21848 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
21850 #define S_AUTOENABLE 1
21851 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
21852 #define F_AUTOENABLE V_AUTOENABLE(1U)
21855 #define V_MODE(x) ((x) << S_MODE)
21856 #define F_MODE V_MODE(1U)
21858 #define A_TP_PC_CONFIG 0x7d48
21860 #define S_CMCACHEDISABLE 31
21861 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
21862 #define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U)
21864 #define S_ENABLEOCSPIFULL 30
21865 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
21866 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
21868 #define S_ENABLEFLMERRORDDP 29
21869 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
21870 #define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U)
21872 #define S_LOCKTID 28
21873 #define V_LOCKTID(x) ((x) << S_LOCKTID)
21874 #define F_LOCKTID V_LOCKTID(1U)
21876 #define S_DISABLEINVPEND 27
21877 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
21878 #define F_DISABLEINVPEND V_DISABLEINVPEND(1U)
21880 #define S_ENABLEFILTERCOUNT 26
21881 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
21882 #define F_ENABLEFILTERCOUNT V_ENABLEFILTERCOUNT(1U)
21884 #define S_RDDPCONGEN 25
21885 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
21886 #define F_RDDPCONGEN V_RDDPCONGEN(1U)
21888 #define S_ENABLEONFLYPDU 24
21889 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
21890 #define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U)
21892 #define S_ENABLEMINRCVWND 23
21893 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
21894 #define F_ENABLEMINRCVWND V_ENABLEMINRCVWND(1U)
21896 #define S_ENABLEMAXRCVWND 22
21897 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
21898 #define F_ENABLEMAXRCVWND V_ENABLEMAXRCVWND(1U)
21900 #define S_TXDATAACKRATEENABLE 21
21901 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
21902 #define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U)
21904 #define S_TXDEFERENABLE 20
21905 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
21906 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
21908 #define S_RXCONGESTIONMODE 19
21909 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
21910 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
21912 #define S_HEARBEATONCEDACK 18
21913 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
21914 #define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U)
21916 #define S_HEARBEATONCEHEAP 17
21917 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
21918 #define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U)
21920 #define S_HEARBEATDACK 16
21921 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
21922 #define F_HEARBEATDACK V_HEARBEATDACK(1U)
21924 #define S_TXCONGESTIONMODE 15
21925 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
21926 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
21928 #define S_ACCEPTLATESTRCVADV 14
21929 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
21930 #define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U)
21932 #define S_DISABLESYNDATA 13
21933 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
21934 #define F_DISABLESYNDATA V_DISABLESYNDATA(1U)
21936 #define S_DISABLEWINDOWPSH 12
21937 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
21938 #define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U)
21940 #define S_DISABLEFINOLDDATA 11
21941 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
21942 #define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U)
21944 #define S_ENABLEFLMERROR 10
21945 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
21946 #define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U)
21948 #define S_ENABLEOPTMTU 9
21949 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
21950 #define F_ENABLEOPTMTU V_ENABLEOPTMTU(1U)
21952 #define S_FILTERPEERFIN 8
21953 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
21954 #define F_FILTERPEERFIN V_FILTERPEERFIN(1U)
21956 #define S_ENABLEFEEDBACKSEND 7
21957 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
21958 #define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U)
21960 #define S_ENABLERDMAERROR 6
21961 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
21962 #define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U)
21964 #define S_ENABLEDDPFLOWCONTROL 5
21965 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
21966 #define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U)
21968 #define S_DISABLEHELDFIN 4
21969 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
21970 #define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U)
21972 #define S_ENABLEOFDOVLAN 3
21973 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
21974 #define F_ENABLEOFDOVLAN V_ENABLEOFDOVLAN(1U)
21976 #define S_DISABLETIMEWAIT 2
21977 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
21978 #define F_DISABLETIMEWAIT V_DISABLETIMEWAIT(1U)
21980 #define S_ENABLEVLANCHECK 1
21981 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
21982 #define F_ENABLEVLANCHECK V_ENABLEVLANCHECK(1U)
21984 #define S_TXDATAACKPAGEENABLE 0
21985 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
21986 #define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U)
21988 #define S_ENABLEFILTERNAT 5
21989 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
21990 #define F_ENABLEFILTERNAT V_ENABLEFILTERNAT(1U)
21992 #define S_ENABLEFINCHECK 31
21993 #define V_ENABLEFINCHECK(x) ((x) << S_ENABLEFINCHECK)
21994 #define F_ENABLEFINCHECK V_ENABLEFINCHECK(1U)
21996 #define S_ENABLEMIBVFPLD 21
21997 #define V_ENABLEMIBVFPLD(x) ((x) << S_ENABLEMIBVFPLD)
21998 #define F_ENABLEMIBVFPLD V_ENABLEMIBVFPLD(1U)
22000 #define S_DISABLESEPPSHFLAG 4
22001 #define V_DISABLESEPPSHFLAG(x) ((x) << S_DISABLESEPPSHFLAG)
22002 #define F_DISABLESEPPSHFLAG V_DISABLESEPPSHFLAG(1U)
22004 #define A_TP_PC_CONFIG2 0x7d4c
22006 #define S_ENABLEMTUVFMODE 31
22007 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
22008 #define F_ENABLEMTUVFMODE V_ENABLEMTUVFMODE(1U)
22010 #define S_ENABLEMIBVFMODE 30
22011 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
22012 #define F_ENABLEMIBVFMODE V_ENABLEMIBVFMODE(1U)
22014 #define S_DISABLELBKCHECK 29
22015 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
22016 #define F_DISABLELBKCHECK V_DISABLELBKCHECK(1U)
22018 #define S_ENABLEURGDDPOFF 28
22019 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
22020 #define F_ENABLEURGDDPOFF V_ENABLEURGDDPOFF(1U)
22022 #define S_ENABLEFILTERLPBK 27
22023 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
22024 #define F_ENABLEFILTERLPBK V_ENABLEFILTERLPBK(1U)
22026 #define S_DISABLETBLMMGR 26
22027 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
22028 #define F_DISABLETBLMMGR V_DISABLETBLMMGR(1U)
22030 #define S_CNGRECSNDNXT 25
22031 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
22032 #define F_CNGRECSNDNXT V_CNGRECSNDNXT(1U)
22034 #define S_ENABLELBKCHN 24
22035 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
22036 #define F_ENABLELBKCHN V_ENABLELBKCHN(1U)
22038 #define S_ENABLELROECN 23
22039 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
22040 #define F_ENABLELROECN V_ENABLELROECN(1U)
22042 #define S_ENABLEPCMDCHECK 22
22043 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
22044 #define F_ENABLEPCMDCHECK V_ENABLEPCMDCHECK(1U)
22046 #define S_ENABLEELBKAFULL 21
22047 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
22048 #define F_ENABLEELBKAFULL V_ENABLEELBKAFULL(1U)
22050 #define S_ENABLECLBKAFULL 20
22051 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
22052 #define F_ENABLECLBKAFULL V_ENABLECLBKAFULL(1U)
22054 #define S_ENABLEOESPIFULL 19
22055 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
22056 #define F_ENABLEOESPIFULL V_ENABLEOESPIFULL(1U)
22058 #define S_DISABLEHITCHECK 18
22059 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
22060 #define F_DISABLEHITCHECK V_DISABLEHITCHECK(1U)
22062 #define S_ENABLERSSERRCHECK 17
22063 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
22064 #define F_ENABLERSSERRCHECK V_ENABLERSSERRCHECK(1U)
22066 #define S_DISABLENEWPSHFLAG 16
22067 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
22068 #define F_DISABLENEWPSHFLAG V_DISABLENEWPSHFLAG(1U)
22070 #define S_ENABLERDDPRCVADVCLR 15
22071 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
22072 #define F_ENABLERDDPRCVADVCLR V_ENABLERDDPRCVADVCLR(1U)
22074 #define S_ENABLETXDATAARPMISS 14
22075 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
22076 #define F_ENABLETXDATAARPMISS V_ENABLETXDATAARPMISS(1U)
22078 #define S_ENABLEARPMISS 13
22079 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
22080 #define F_ENABLEARPMISS V_ENABLEARPMISS(1U)
22082 #define S_ENABLERSTPAWS 12
22083 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
22084 #define F_ENABLERSTPAWS V_ENABLERSTPAWS(1U)
22086 #define S_ENABLEIPV6RSS 11
22087 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
22088 #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U)
22090 #define S_ENABLENONOFDHYBRSS 10
22091 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
22092 #define F_ENABLENONOFDHYBRSS V_ENABLENONOFDHYBRSS(1U)
22094 #define S_ENABLEUDP4TUPRSS 9
22095 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
22096 #define F_ENABLEUDP4TUPRSS V_ENABLEUDP4TUPRSS(1U)
22098 #define S_ENABLERXPKTTMSTPRSS 8
22099 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
22100 #define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U)
22102 #define S_ENABLEEPCMDAFULL 7
22103 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
22104 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
22106 #define S_ENABLECPCMDAFULL 6
22107 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
22108 #define F_ENABLECPCMDAFULL V_ENABLECPCMDAFULL(1U)
22110 #define S_ENABLEEHDRAFULL 5
22111 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
22112 #define F_ENABLEEHDRAFULL V_ENABLEEHDRAFULL(1U)
22114 #define S_ENABLECHDRAFULL 4
22115 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
22116 #define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U)
22118 #define S_ENABLEEMACAFULL 3
22119 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
22120 #define F_ENABLEEMACAFULL V_ENABLEEMACAFULL(1U)
22122 #define S_ENABLENONOFDTIDRSS 2
22123 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
22124 #define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U)
22126 #define S_ENABLENONOFDTCBRSS 1
22127 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
22128 #define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U)
22130 #define S_ENABLETNLOFDCLOSED 0
22131 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
22132 #define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U)
22134 #define S_ENABLEFINDDPOFF 14
22135 #define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
22136 #define F_ENABLEFINDDPOFF V_ENABLEFINDDPOFF(1U)
22138 #define A_TP_TCP_BACKOFF_REG0 0x7d50
22140 #define S_TIMERBACKOFFINDEX3 24
22141 #define M_TIMERBACKOFFINDEX3 0xffU
22142 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
22143 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
22145 #define S_TIMERBACKOFFINDEX2 16
22146 #define M_TIMERBACKOFFINDEX2 0xffU
22147 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
22148 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
22150 #define S_TIMERBACKOFFINDEX1 8
22151 #define M_TIMERBACKOFFINDEX1 0xffU
22152 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
22153 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
22155 #define S_TIMERBACKOFFINDEX0 0
22156 #define M_TIMERBACKOFFINDEX0 0xffU
22157 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
22158 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
22160 #define A_TP_TCP_BACKOFF_REG1 0x7d54
22162 #define S_TIMERBACKOFFINDEX7 24
22163 #define M_TIMERBACKOFFINDEX7 0xffU
22164 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
22165 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
22167 #define S_TIMERBACKOFFINDEX6 16
22168 #define M_TIMERBACKOFFINDEX6 0xffU
22169 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
22170 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
22172 #define S_TIMERBACKOFFINDEX5 8
22173 #define M_TIMERBACKOFFINDEX5 0xffU
22174 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
22175 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
22177 #define S_TIMERBACKOFFINDEX4 0
22178 #define M_TIMERBACKOFFINDEX4 0xffU
22179 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
22180 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
22182 #define A_TP_TCP_BACKOFF_REG2 0x7d58
22184 #define S_TIMERBACKOFFINDEX11 24
22185 #define M_TIMERBACKOFFINDEX11 0xffU
22186 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
22187 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
22189 #define S_TIMERBACKOFFINDEX10 16
22190 #define M_TIMERBACKOFFINDEX10 0xffU
22191 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
22192 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
22194 #define S_TIMERBACKOFFINDEX9 8
22195 #define M_TIMERBACKOFFINDEX9 0xffU
22196 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
22197 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
22199 #define S_TIMERBACKOFFINDEX8 0
22200 #define M_TIMERBACKOFFINDEX8 0xffU
22201 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
22202 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
22204 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
22206 #define S_TIMERBACKOFFINDEX15 24
22207 #define M_TIMERBACKOFFINDEX15 0xffU
22208 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
22209 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
22211 #define S_TIMERBACKOFFINDEX14 16
22212 #define M_TIMERBACKOFFINDEX14 0xffU
22213 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
22214 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
22216 #define S_TIMERBACKOFFINDEX13 8
22217 #define M_TIMERBACKOFFINDEX13 0xffU
22218 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
22219 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
22221 #define S_TIMERBACKOFFINDEX12 0
22222 #define M_TIMERBACKOFFINDEX12 0xffU
22223 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
22224 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
22226 #define A_TP_PARA_REG0 0x7d60
22228 #define S_INITCWNDIDLE 27
22229 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
22230 #define F_INITCWNDIDLE V_INITCWNDIDLE(1U)
22232 #define S_INITCWND 24
22233 #define M_INITCWND 0x7U
22234 #define V_INITCWND(x) ((x) << S_INITCWND)
22235 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
22237 #define S_DUPACKTHRESH 20
22238 #define M_DUPACKTHRESH 0xfU
22239 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
22240 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
22242 #define S_CPLERRENABLE 12
22243 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
22244 #define F_CPLERRENABLE V_CPLERRENABLE(1U)
22246 #define S_FASTTNLCNT 11
22247 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
22248 #define F_FASTTNLCNT V_FASTTNLCNT(1U)
22250 #define S_FASTTBLCNT 10
22251 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
22252 #define F_FASTTBLCNT V_FASTTBLCNT(1U)
22254 #define S_TPTCAMKEY 9
22255 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
22256 #define F_TPTCAMKEY V_TPTCAMKEY(1U)
22258 #define S_SWSMODE 8
22259 #define V_SWSMODE(x) ((x) << S_SWSMODE)
22260 #define F_SWSMODE V_SWSMODE(1U)
22262 #define S_TSMPMODE 6
22263 #define M_TSMPMODE 0x3U
22264 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
22265 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
22267 #define S_BYTECOUNTLIMIT 4
22268 #define M_BYTECOUNTLIMIT 0x3U
22269 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
22270 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
22272 #define S_SWSSHOVE 3
22273 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
22274 #define F_SWSSHOVE V_SWSSHOVE(1U)
22276 #define S_TBLTIMER 2
22277 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
22278 #define F_TBLTIMER V_TBLTIMER(1U)
22280 #define S_RXTPACE 1
22281 #define V_RXTPACE(x) ((x) << S_RXTPACE)
22282 #define F_RXTPACE V_RXTPACE(1U)
22284 #define S_SWSTIMER 0
22285 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
22286 #define F_SWSTIMER V_SWSTIMER(1U)
22288 #define S_LIMTXTHRESH 28
22289 #define M_LIMTXTHRESH 0xfU
22290 #define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
22291 #define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
22293 #define S_CHNERRENABLE 14
22294 #define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
22295 #define F_CHNERRENABLE V_CHNERRENABLE(1U)
22297 #define S_SETTIMEENABLE 13
22298 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
22299 #define F_SETTIMEENABLE V_SETTIMEENABLE(1U)
22301 #define S_ECNCNGFIFO 19
22302 #define V_ECNCNGFIFO(x) ((x) << S_ECNCNGFIFO)
22303 #define F_ECNCNGFIFO V_ECNCNGFIFO(1U)
22305 #define S_ECNSYNACK 18
22306 #define V_ECNSYNACK(x) ((x) << S_ECNSYNACK)
22307 #define F_ECNSYNACK V_ECNSYNACK(1U)
22309 #define S_ECNTHRESH 16
22310 #define M_ECNTHRESH 0x3U
22311 #define V_ECNTHRESH(x) ((x) << S_ECNTHRESH)
22312 #define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH)
22314 #define S_ECNMODE 15
22315 #define V_ECNMODE(x) ((x) << S_ECNMODE)
22316 #define F_ECNMODE V_ECNMODE(1U)
22318 #define S_ECNMODECWR 14
22319 #define V_ECNMODECWR(x) ((x) << S_ECNMODECWR)
22320 #define F_ECNMODECWR V_ECNMODECWR(1U)
22322 #define S_FORCESHOVE 10
22323 #define V_FORCESHOVE(x) ((x) << S_FORCESHOVE)
22324 #define F_FORCESHOVE V_FORCESHOVE(1U)
22326 #define A_TP_PARA_REG1 0x7d64
22328 #define S_INITRWND 16
22329 #define M_INITRWND 0xffffU
22330 #define V_INITRWND(x) ((x) << S_INITRWND)
22331 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
22333 #define S_INITIALSSTHRESH 0
22334 #define M_INITIALSSTHRESH 0xffffU
22335 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
22336 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
22338 #define A_TP_PARA_REG2 0x7d68
22340 #define S_MAXRXDATA 16
22341 #define M_MAXRXDATA 0xffffU
22342 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
22343 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
22345 #define S_RXCOALESCESIZE 0
22346 #define M_RXCOALESCESIZE 0xffffU
22347 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
22348 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
22350 #define A_TP_PARA_REG3 0x7d6c
22352 #define S_ENABLETNLCNGLPBK 31
22353 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
22354 #define F_ENABLETNLCNGLPBK V_ENABLETNLCNGLPBK(1U)
22356 #define S_ENABLETNLCNGFIFO 30
22357 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
22358 #define F_ENABLETNLCNGFIFO V_ENABLETNLCNGFIFO(1U)
22360 #define S_ENABLETNLCNGHDR 29
22361 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
22362 #define F_ENABLETNLCNGHDR V_ENABLETNLCNGHDR(1U)
22364 #define S_ENABLETNLCNGSGE 28
22365 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
22366 #define F_ENABLETNLCNGSGE V_ENABLETNLCNGSGE(1U)
22368 #define S_RXMACCHECK 27
22369 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
22370 #define F_RXMACCHECK V_RXMACCHECK(1U)
22372 #define S_RXSYNFILTER 26
22373 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
22374 #define F_RXSYNFILTER V_RXSYNFILTER(1U)
22376 #define S_CNGCTRLECN 25
22377 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
22378 #define F_CNGCTRLECN V_CNGCTRLECN(1U)
22380 #define S_RXDDPOFFINIT 24
22381 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
22382 #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U)
22384 #define S_TUNNELCNGDROP3 23
22385 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
22386 #define F_TUNNELCNGDROP3 V_TUNNELCNGDROP3(1U)
22388 #define S_TUNNELCNGDROP2 22
22389 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
22390 #define F_TUNNELCNGDROP2 V_TUNNELCNGDROP2(1U)
22392 #define S_TUNNELCNGDROP1 21
22393 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
22394 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U)
22396 #define S_TUNNELCNGDROP0 20
22397 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
22398 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U)
22400 #define S_TXDATAACKIDX 16
22401 #define M_TXDATAACKIDX 0xfU
22402 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
22403 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
22405 #define S_RXFRAGENABLE 12
22406 #define M_RXFRAGENABLE 0x7U
22407 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
22408 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
22410 #define S_TXPACEFIXEDSTRICT 11
22411 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
22412 #define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U)
22414 #define S_TXPACEAUTOSTRICT 10
22415 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
22416 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
22418 #define S_TXPACEFIXED 9
22419 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
22420 #define F_TXPACEFIXED V_TXPACEFIXED(1U)
22422 #define S_TXPACEAUTO 8
22423 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
22424 #define F_TXPACEAUTO V_TXPACEAUTO(1U)
22426 #define S_RXCHNTUNNEL 7
22427 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
22428 #define F_RXCHNTUNNEL V_RXCHNTUNNEL(1U)
22430 #define S_RXURGTUNNEL 6
22431 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
22432 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U)
22434 #define S_RXURGMODE 5
22435 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
22436 #define F_RXURGMODE V_RXURGMODE(1U)
22438 #define S_TXURGMODE 4
22439 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
22440 #define F_TXURGMODE V_TXURGMODE(1U)
22442 #define S_CNGCTRLMODE 2
22443 #define M_CNGCTRLMODE 0x3U
22444 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
22445 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
22447 #define S_RXCOALESCEENABLE 1
22448 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
22449 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
22451 #define S_RXCOALESCEPSHEN 0
22452 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
22453 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
22455 #define A_TP_PARA_REG4 0x7d70
22457 #define S_HIGHSPEEDCFG 24
22458 #define M_HIGHSPEEDCFG 0xffU
22459 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
22460 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
22462 #define S_NEWRENOCFG 16
22463 #define M_NEWRENOCFG 0xffU
22464 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
22465 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
22467 #define S_TAHOECFG 8
22468 #define M_TAHOECFG 0xffU
22469 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
22470 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
22472 #define S_RENOCFG 0
22473 #define M_RENOCFG 0xffU
22474 #define V_RENOCFG(x) ((x) << S_RENOCFG)
22475 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
22477 #define S_IDLECWNDHIGHSPEED 28
22478 #define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
22479 #define F_IDLECWNDHIGHSPEED V_IDLECWNDHIGHSPEED(1U)
22481 #define S_RXMTCWNDHIGHSPEED 27
22482 #define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
22483 #define F_RXMTCWNDHIGHSPEED V_RXMTCWNDHIGHSPEED(1U)
22485 #define S_OVERDRIVEHIGHSPEED 25
22486 #define M_OVERDRIVEHIGHSPEED 0x3U
22487 #define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
22488 #define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
22490 #define S_BYTECOUNTHIGHSPEED 24
22491 #define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
22492 #define F_BYTECOUNTHIGHSPEED V_BYTECOUNTHIGHSPEED(1U)
22494 #define S_IDLECWNDNEWRENO 20
22495 #define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
22496 #define F_IDLECWNDNEWRENO V_IDLECWNDNEWRENO(1U)
22498 #define S_RXMTCWNDNEWRENO 19
22499 #define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
22500 #define F_RXMTCWNDNEWRENO V_RXMTCWNDNEWRENO(1U)
22502 #define S_OVERDRIVENEWRENO 17
22503 #define M_OVERDRIVENEWRENO 0x3U
22504 #define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
22505 #define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
22507 #define S_BYTECOUNTNEWRENO 16
22508 #define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
22509 #define F_BYTECOUNTNEWRENO V_BYTECOUNTNEWRENO(1U)
22511 #define S_IDLECWNDTAHOE 12
22512 #define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
22513 #define F_IDLECWNDTAHOE V_IDLECWNDTAHOE(1U)
22515 #define S_RXMTCWNDTAHOE 11
22516 #define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
22517 #define F_RXMTCWNDTAHOE V_RXMTCWNDTAHOE(1U)
22519 #define S_OVERDRIVETAHOE 9
22520 #define M_OVERDRIVETAHOE 0x3U
22521 #define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
22522 #define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
22524 #define S_BYTECOUNTTAHOE 8
22525 #define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
22526 #define F_BYTECOUNTTAHOE V_BYTECOUNTTAHOE(1U)
22528 #define S_IDLECWNDRENO 4
22529 #define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
22530 #define F_IDLECWNDRENO V_IDLECWNDRENO(1U)
22532 #define S_RXMTCWNDRENO 3
22533 #define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
22534 #define F_RXMTCWNDRENO V_RXMTCWNDRENO(1U)
22536 #define S_OVERDRIVERENO 1
22537 #define M_OVERDRIVERENO 0x3U
22538 #define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
22539 #define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
22541 #define S_BYTECOUNTRENO 0
22542 #define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
22543 #define F_BYTECOUNTRENO V_BYTECOUNTRENO(1U)
22545 #define A_TP_PARA_REG5 0x7d74
22547 #define S_INDICATESIZE 16
22548 #define M_INDICATESIZE 0xffffU
22549 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
22550 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
22552 #define S_MAXPROXYSIZE 12
22553 #define M_MAXPROXYSIZE 0xfU
22554 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
22555 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
22557 #define S_ENABLEREADPDU 11
22558 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
22559 #define F_ENABLEREADPDU V_ENABLEREADPDU(1U)
22561 #define S_RXREADAHEAD 10
22562 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
22563 #define F_RXREADAHEAD V_RXREADAHEAD(1U)
22565 #define S_EMPTYRQENABLE 9
22566 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
22567 #define F_EMPTYRQENABLE V_EMPTYRQENABLE(1U)
22569 #define S_SCHDENABLE 8
22570 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
22571 #define F_SCHDENABLE V_SCHDENABLE(1U)
22573 #define S_REARMDDPOFFSET 4
22574 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
22575 #define F_REARMDDPOFFSET V_REARMDDPOFFSET(1U)
22577 #define S_RESETDDPOFFSET 3
22578 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
22579 #define F_RESETDDPOFFSET V_RESETDDPOFFSET(1U)
22581 #define S_ONFLYDDPENABLE 2
22582 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
22583 #define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U)
22585 #define S_DACKTIMERSPIN 1
22586 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
22587 #define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U)
22589 #define S_PUSHTIMERENABLE 0
22590 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
22591 #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U)
22593 #define S_ENABLEXOFFPDU 7
22594 #define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
22595 #define F_ENABLEXOFFPDU V_ENABLEXOFFPDU(1U)
22597 #define S_ENABLENEWFAR 6
22598 #define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
22599 #define F_ENABLENEWFAR V_ENABLENEWFAR(1U)
22601 #define S_ENABLEFRAGCHECK 5
22602 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
22603 #define F_ENABLEFRAGCHECK V_ENABLEFRAGCHECK(1U)
22605 #define S_ENABLEFCOECHECK 6
22606 #define V_ENABLEFCOECHECK(x) ((x) << S_ENABLEFCOECHECK)
22607 #define F_ENABLEFCOECHECK V_ENABLEFCOECHECK(1U)
22609 #define S_ENABLERDMAFIX 1
22610 #define V_ENABLERDMAFIX(x) ((x) << S_ENABLERDMAFIX)
22611 #define F_ENABLERDMAFIX V_ENABLERDMAFIX(1U)
22613 #define A_TP_PARA_REG6 0x7d78
22615 #define S_TXPDUSIZEADJ 24
22616 #define M_TXPDUSIZEADJ 0xffU
22617 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
22618 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
22620 #define S_LIMITEDTRANSMIT 20
22621 #define M_LIMITEDTRANSMIT 0xfU
22622 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
22623 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
22625 #define S_ENABLECSAV 19
22626 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
22627 #define F_ENABLECSAV V_ENABLECSAV(1U)
22629 #define S_ENABLEDEFERPDU 18
22630 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
22631 #define F_ENABLEDEFERPDU V_ENABLEDEFERPDU(1U)
22633 #define S_ENABLEFLUSH 17
22634 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
22635 #define F_ENABLEFLUSH V_ENABLEFLUSH(1U)
22637 #define S_ENABLEBYTEPERSIST 16
22638 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
22639 #define F_ENABLEBYTEPERSIST V_ENABLEBYTEPERSIST(1U)
22641 #define S_DISABLETMOCNG 15
22642 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
22643 #define F_DISABLETMOCNG V_DISABLETMOCNG(1U)
22645 #define S_TXREADAHEAD 14
22646 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
22647 #define F_TXREADAHEAD V_TXREADAHEAD(1U)
22649 #define S_ALLOWEXEPTION 13
22650 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
22651 #define F_ALLOWEXEPTION V_ALLOWEXEPTION(1U)
22653 #define S_ENABLEDEFERACK 12
22654 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
22655 #define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U)
22657 #define S_ENABLEESND 11
22658 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
22659 #define F_ENABLEESND V_ENABLEESND(1U)
22661 #define S_ENABLECSND 10
22662 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
22663 #define F_ENABLECSND V_ENABLECSND(1U)
22665 #define S_ENABLEPDUE 9
22666 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
22667 #define F_ENABLEPDUE V_ENABLEPDUE(1U)
22669 #define S_ENABLEPDUC 8
22670 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
22671 #define F_ENABLEPDUC V_ENABLEPDUC(1U)
22673 #define S_ENABLEBUFI 7
22674 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
22675 #define F_ENABLEBUFI V_ENABLEBUFI(1U)
22677 #define S_ENABLEBUFE 6
22678 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
22679 #define F_ENABLEBUFE V_ENABLEBUFE(1U)
22681 #define S_ENABLEDEFER 5
22682 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
22683 #define F_ENABLEDEFER V_ENABLEDEFER(1U)
22685 #define S_ENABLECLEARRXMTOOS 4
22686 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
22687 #define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U)
22689 #define S_DISABLEPDUCNG 3
22690 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
22691 #define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U)
22693 #define S_DISABLEPDUTIMEOUT 2
22694 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
22695 #define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U)
22697 #define S_DISABLEPDURXMT 1
22698 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
22699 #define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U)
22701 #define S_DISABLEPDUXMT 0
22702 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
22703 #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U)
22705 #define S_DISABLEPDUACK 20
22706 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
22707 #define F_DISABLEPDUACK V_DISABLEPDUACK(1U)
22709 #define S_TXTCAMKEY 22
22710 #define V_TXTCAMKEY(x) ((x) << S_TXTCAMKEY)
22711 #define F_TXTCAMKEY V_TXTCAMKEY(1U)
22713 #define S_ENABLECBYP 21
22714 #define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
22715 #define F_ENABLECBYP V_ENABLECBYP(1U)
22717 #define A_TP_PARA_REG7 0x7d7c
22719 #define S_PMMAXXFERLEN1 16
22720 #define M_PMMAXXFERLEN1 0xffffU
22721 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
22722 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
22724 #define S_PMMAXXFERLEN0 0
22725 #define M_PMMAXXFERLEN0 0xffffU
22726 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
22727 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
22729 #define A_TP_ENG_CONFIG 0x7d80
22731 #define S_TABLELATENCYDONE 28
22732 #define M_TABLELATENCYDONE 0xfU
22733 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
22734 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
22736 #define S_TABLELATENCYSTART 24
22737 #define M_TABLELATENCYSTART 0xfU
22738 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
22739 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
22741 #define S_ENGINELATENCYDELTA 16
22742 #define M_ENGINELATENCYDELTA 0xfU
22743 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
22744 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
22746 #define S_ENGINELATENCYMMGR 12
22747 #define M_ENGINELATENCYMMGR 0xfU
22748 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
22749 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
22751 #define S_ENGINELATENCYWIREIP6 8
22752 #define M_ENGINELATENCYWIREIP6 0xfU
22753 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
22754 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
22756 #define S_ENGINELATENCYWIRE 4
22757 #define M_ENGINELATENCYWIRE 0xfU
22758 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
22759 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
22761 #define S_ENGINELATENCYBASE 0
22762 #define M_ENGINELATENCYBASE 0xfU
22763 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
22764 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
22766 #define A_TP_PARA_REG8 0x7d84
22768 #define S_ECNACKECT 2
22769 #define V_ECNACKECT(x) ((x) << S_ECNACKECT)
22770 #define F_ECNACKECT V_ECNACKECT(1U)
22772 #define S_ECNFINECT 1
22773 #define V_ECNFINECT(x) ((x) << S_ECNFINECT)
22774 #define F_ECNFINECT V_ECNFINECT(1U)
22776 #define S_ECNSYNECT 0
22777 #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
22778 #define F_ECNSYNECT V_ECNSYNECT(1U)
22780 #define A_TP_ERR_CONFIG 0x7d8c
22782 #define S_TNLERRORPING 30
22783 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
22784 #define F_TNLERRORPING V_TNLERRORPING(1U)
22786 #define S_TNLERRORCSUM 29
22787 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
22788 #define F_TNLERRORCSUM V_TNLERRORCSUM(1U)
22790 #define S_TNLERRORCSUMIP 28
22791 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
22792 #define F_TNLERRORCSUMIP V_TNLERRORCSUMIP(1U)
22794 #define S_TNLERRORTCPOPT 25
22795 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
22796 #define F_TNLERRORTCPOPT V_TNLERRORTCPOPT(1U)
22798 #define S_TNLERRORPKTLEN 24
22799 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
22800 #define F_TNLERRORPKTLEN V_TNLERRORPKTLEN(1U)
22802 #define S_TNLERRORTCPHDRLEN 23
22803 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
22804 #define F_TNLERRORTCPHDRLEN V_TNLERRORTCPHDRLEN(1U)
22806 #define S_TNLERRORIPHDRLEN 22
22807 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
22808 #define F_TNLERRORIPHDRLEN V_TNLERRORIPHDRLEN(1U)
22810 #define S_TNLERRORETHHDRLEN 21
22811 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
22812 #define F_TNLERRORETHHDRLEN V_TNLERRORETHHDRLEN(1U)
22814 #define S_TNLERRORATTACK 20
22815 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
22816 #define F_TNLERRORATTACK V_TNLERRORATTACK(1U)
22818 #define S_TNLERRORFRAG 19
22819 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
22820 #define F_TNLERRORFRAG V_TNLERRORFRAG(1U)
22822 #define S_TNLERRORIPVER 18
22823 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
22824 #define F_TNLERRORIPVER V_TNLERRORIPVER(1U)
22826 #define S_TNLERRORMAC 17
22827 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
22828 #define F_TNLERRORMAC V_TNLERRORMAC(1U)
22830 #define S_TNLERRORANY 16
22831 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
22832 #define F_TNLERRORANY V_TNLERRORANY(1U)
22834 #define S_DROPERRORPING 14
22835 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
22836 #define F_DROPERRORPING V_DROPERRORPING(1U)
22838 #define S_DROPERRORCSUM 13
22839 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
22840 #define F_DROPERRORCSUM V_DROPERRORCSUM(1U)
22842 #define S_DROPERRORCSUMIP 12
22843 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
22844 #define F_DROPERRORCSUMIP V_DROPERRORCSUMIP(1U)
22846 #define S_DROPERRORTCPOPT 9
22847 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
22848 #define F_DROPERRORTCPOPT V_DROPERRORTCPOPT(1U)
22850 #define S_DROPERRORPKTLEN 8
22851 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
22852 #define F_DROPERRORPKTLEN V_DROPERRORPKTLEN(1U)
22854 #define S_DROPERRORTCPHDRLEN 7
22855 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
22856 #define F_DROPERRORTCPHDRLEN V_DROPERRORTCPHDRLEN(1U)
22858 #define S_DROPERRORIPHDRLEN 6
22859 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
22860 #define F_DROPERRORIPHDRLEN V_DROPERRORIPHDRLEN(1U)
22862 #define S_DROPERRORETHHDRLEN 5
22863 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
22864 #define F_DROPERRORETHHDRLEN V_DROPERRORETHHDRLEN(1U)
22866 #define S_DROPERRORATTACK 4
22867 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
22868 #define F_DROPERRORATTACK V_DROPERRORATTACK(1U)
22870 #define S_DROPERRORFRAG 3
22871 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
22872 #define F_DROPERRORFRAG V_DROPERRORFRAG(1U)
22874 #define S_DROPERRORIPVER 2
22875 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
22876 #define F_DROPERRORIPVER V_DROPERRORIPVER(1U)
22878 #define S_DROPERRORMAC 1
22879 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
22880 #define F_DROPERRORMAC V_DROPERRORMAC(1U)
22882 #define S_DROPERRORANY 0
22883 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
22884 #define F_DROPERRORANY V_DROPERRORANY(1U)
22886 #define S_TNLERRORFPMA 31
22887 #define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
22888 #define F_TNLERRORFPMA V_TNLERRORFPMA(1U)
22890 #define S_DROPERRORFPMA 15
22891 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
22892 #define F_DROPERRORFPMA V_DROPERRORFPMA(1U)
22894 #define S_TNLERROROPAQUE 27
22895 #define V_TNLERROROPAQUE(x) ((x) << S_TNLERROROPAQUE)
22896 #define F_TNLERROROPAQUE V_TNLERROROPAQUE(1U)
22898 #define S_TNLERRORIP6OPT 26
22899 #define V_TNLERRORIP6OPT(x) ((x) << S_TNLERRORIP6OPT)
22900 #define F_TNLERRORIP6OPT V_TNLERRORIP6OPT(1U)
22902 #define S_DROPERROROPAQUE 11
22903 #define V_DROPERROROPAQUE(x) ((x) << S_DROPERROROPAQUE)
22904 #define F_DROPERROROPAQUE V_DROPERROROPAQUE(1U)
22906 #define S_DROPERRORIP6OPT 10
22907 #define V_DROPERRORIP6OPT(x) ((x) << S_DROPERRORIP6OPT)
22908 #define F_DROPERRORIP6OPT V_DROPERRORIP6OPT(1U)
22910 #define A_TP_TIMER_RESOLUTION 0x7d90
22912 #define S_TIMERRESOLUTION 16
22913 #define M_TIMERRESOLUTION 0xffU
22914 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
22915 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
22917 #define S_TIMESTAMPRESOLUTION 8
22918 #define M_TIMESTAMPRESOLUTION 0xffU
22919 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
22920 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
22922 #define S_DELAYEDACKRESOLUTION 0
22923 #define M_DELAYEDACKRESOLUTION 0xffU
22924 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
22925 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
22927 #define A_TP_MSL 0x7d94
22930 #define M_MSL 0x3fffffffU
22931 #define V_MSL(x) ((x) << S_MSL)
22932 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
22934 #define A_TP_RXT_MIN 0x7d98
22937 #define M_RXTMIN 0x3fffffffU
22938 #define V_RXTMIN(x) ((x) << S_RXTMIN)
22939 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
22941 #define A_TP_RXT_MAX 0x7d9c
22944 #define M_RXTMAX 0x3fffffffU
22945 #define V_RXTMAX(x) ((x) << S_RXTMAX)
22946 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
22948 #define A_TP_PERS_MIN 0x7da0
22950 #define S_PERSMIN 0
22951 #define M_PERSMIN 0x3fffffffU
22952 #define V_PERSMIN(x) ((x) << S_PERSMIN)
22953 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
22955 #define A_TP_PERS_MAX 0x7da4
22957 #define S_PERSMAX 0
22958 #define M_PERSMAX 0x3fffffffU
22959 #define V_PERSMAX(x) ((x) << S_PERSMAX)
22960 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
22962 #define A_TP_KEEP_IDLE 0x7da8
22964 #define S_KEEPALIVEIDLE 0
22965 #define M_KEEPALIVEIDLE 0x3fffffffU
22966 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
22967 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
22969 #define A_TP_KEEP_INTVL 0x7dac
22971 #define S_KEEPALIVEINTVL 0
22972 #define M_KEEPALIVEINTVL 0x3fffffffU
22973 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
22974 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
22976 #define A_TP_INIT_SRTT 0x7db0
22978 #define S_MAXRTT 16
22979 #define M_MAXRTT 0xffffU
22980 #define V_MAXRTT(x) ((x) << S_MAXRTT)
22981 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
22983 #define S_INITSRTT 0
22984 #define M_INITSRTT 0xffffU
22985 #define V_INITSRTT(x) ((x) << S_INITSRTT)
22986 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
22988 #define A_TP_DACK_TIMER 0x7db4
22990 #define S_DACKTIME 0
22991 #define M_DACKTIME 0xfffU
22992 #define V_DACKTIME(x) ((x) << S_DACKTIME)
22993 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
22995 #define A_TP_FINWAIT2_TIMER 0x7db8
22997 #define S_FINWAIT2TIME 0
22998 #define M_FINWAIT2TIME 0x3fffffffU
22999 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
23000 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
23002 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
23004 #define S_FASTFINWAIT2TIME 0
23005 #define M_FASTFINWAIT2TIME 0x3fffffffU
23006 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
23007 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
23009 #define A_TP_SHIFT_CNT 0x7dc0
23011 #define S_SYNSHIFTMAX 24
23012 #define M_SYNSHIFTMAX 0xffU
23013 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
23014 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
23016 #define S_RXTSHIFTMAXR1 20
23017 #define M_RXTSHIFTMAXR1 0xfU
23018 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
23019 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
23021 #define S_RXTSHIFTMAXR2 16
23022 #define M_RXTSHIFTMAXR2 0xfU
23023 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
23024 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
23026 #define S_PERSHIFTBACKOFFMAX 12
23027 #define M_PERSHIFTBACKOFFMAX 0xfU
23028 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
23029 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
23031 #define S_PERSHIFTMAX 8
23032 #define M_PERSHIFTMAX 0xfU
23033 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
23034 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
23036 #define S_KEEPALIVEMAXR1 4
23037 #define M_KEEPALIVEMAXR1 0xfU
23038 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
23039 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
23041 #define S_KEEPALIVEMAXR2 0
23042 #define M_KEEPALIVEMAXR2 0xfU
23043 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
23044 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
23046 #define S_T6_SYNSHIFTMAX 24
23047 #define M_T6_SYNSHIFTMAX 0xfU
23048 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
23049 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
23051 #define A_TP_TM_CONFIG 0x7dc4
23053 #define S_CMTIMERMAXNUM 0
23054 #define M_CMTIMERMAXNUM 0x7U
23055 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
23056 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
23058 #define A_TP_TIME_LO 0x7dc8
23059 #define A_TP_TIME_HI 0x7dcc
23060 #define A_TP_PORT_MTU_0 0x7dd0
23062 #define S_PORT1MTUVALUE 16
23063 #define M_PORT1MTUVALUE 0xffffU
23064 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
23065 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
23067 #define S_PORT0MTUVALUE 0
23068 #define M_PORT0MTUVALUE 0xffffU
23069 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
23070 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
23072 #define A_TP_PORT_MTU_1 0x7dd4
23074 #define S_PORT3MTUVALUE 16
23075 #define M_PORT3MTUVALUE 0xffffU
23076 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
23077 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
23079 #define S_PORT2MTUVALUE 0
23080 #define M_PORT2MTUVALUE 0xffffU
23081 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
23082 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
23084 #define A_TP_PACE_TABLE 0x7dd8
23085 #define A_TP_CCTRL_TABLE 0x7ddc
23087 #define S_ROWINDEX 16
23088 #define M_ROWINDEX 0xffffU
23089 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
23090 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
23092 #define S_ROWVALUE 0
23093 #define M_ROWVALUE 0xffffU
23094 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
23095 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
23097 #define A_TP_MTU_TABLE 0x7de4
23099 #define S_MTUINDEX 24
23100 #define M_MTUINDEX 0xffU
23101 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
23102 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
23104 #define S_MTUWIDTH 16
23105 #define M_MTUWIDTH 0xfU
23106 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
23107 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
23109 #define S_MTUVALUE 0
23110 #define M_MTUVALUE 0x3fffU
23111 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
23112 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
23114 #define A_TP_ULP_TABLE 0x7de8
23116 #define S_ULPTYPE7FIELD 28
23117 #define M_ULPTYPE7FIELD 0xfU
23118 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
23119 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
23121 #define S_ULPTYPE6FIELD 24
23122 #define M_ULPTYPE6FIELD 0xfU
23123 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
23124 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
23126 #define S_ULPTYPE5FIELD 20
23127 #define M_ULPTYPE5FIELD 0xfU
23128 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
23129 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
23131 #define S_ULPTYPE4FIELD 16
23132 #define M_ULPTYPE4FIELD 0xfU
23133 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
23134 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
23136 #define S_ULPTYPE3FIELD 12
23137 #define M_ULPTYPE3FIELD 0xfU
23138 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
23139 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
23141 #define S_ULPTYPE2FIELD 8
23142 #define M_ULPTYPE2FIELD 0xfU
23143 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
23144 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
23146 #define S_ULPTYPE1FIELD 4
23147 #define M_ULPTYPE1FIELD 0xfU
23148 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
23149 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
23151 #define S_ULPTYPE0FIELD 0
23152 #define M_ULPTYPE0FIELD 0xfU
23153 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
23154 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
23156 #define S_ULPTYPE7LENGTH 31
23157 #define V_ULPTYPE7LENGTH(x) ((x) << S_ULPTYPE7LENGTH)
23158 #define F_ULPTYPE7LENGTH V_ULPTYPE7LENGTH(1U)
23160 #define S_ULPTYPE7OFFSET 28
23161 #define M_ULPTYPE7OFFSET 0x7U
23162 #define V_ULPTYPE7OFFSET(x) ((x) << S_ULPTYPE7OFFSET)
23163 #define G_ULPTYPE7OFFSET(x) (((x) >> S_ULPTYPE7OFFSET) & M_ULPTYPE7OFFSET)
23165 #define S_ULPTYPE6LENGTH 27
23166 #define V_ULPTYPE6LENGTH(x) ((x) << S_ULPTYPE6LENGTH)
23167 #define F_ULPTYPE6LENGTH V_ULPTYPE6LENGTH(1U)
23169 #define S_ULPTYPE6OFFSET 24
23170 #define M_ULPTYPE6OFFSET 0x7U
23171 #define V_ULPTYPE6OFFSET(x) ((x) << S_ULPTYPE6OFFSET)
23172 #define G_ULPTYPE6OFFSET(x) (((x) >> S_ULPTYPE6OFFSET) & M_ULPTYPE6OFFSET)
23174 #define S_ULPTYPE5LENGTH 23
23175 #define V_ULPTYPE5LENGTH(x) ((x) << S_ULPTYPE5LENGTH)
23176 #define F_ULPTYPE5LENGTH V_ULPTYPE5LENGTH(1U)
23178 #define S_ULPTYPE5OFFSET 20
23179 #define M_ULPTYPE5OFFSET 0x7U
23180 #define V_ULPTYPE5OFFSET(x) ((x) << S_ULPTYPE5OFFSET)
23181 #define G_ULPTYPE5OFFSET(x) (((x) >> S_ULPTYPE5OFFSET) & M_ULPTYPE5OFFSET)
23183 #define S_ULPTYPE4LENGTH 19
23184 #define V_ULPTYPE4LENGTH(x) ((x) << S_ULPTYPE4LENGTH)
23185 #define F_ULPTYPE4LENGTH V_ULPTYPE4LENGTH(1U)
23187 #define S_ULPTYPE4OFFSET 16
23188 #define M_ULPTYPE4OFFSET 0x7U
23189 #define V_ULPTYPE4OFFSET(x) ((x) << S_ULPTYPE4OFFSET)
23190 #define G_ULPTYPE4OFFSET(x) (((x) >> S_ULPTYPE4OFFSET) & M_ULPTYPE4OFFSET)
23192 #define S_ULPTYPE3LENGTH 15
23193 #define V_ULPTYPE3LENGTH(x) ((x) << S_ULPTYPE3LENGTH)
23194 #define F_ULPTYPE3LENGTH V_ULPTYPE3LENGTH(1U)
23196 #define S_ULPTYPE3OFFSET 12
23197 #define M_ULPTYPE3OFFSET 0x7U
23198 #define V_ULPTYPE3OFFSET(x) ((x) << S_ULPTYPE3OFFSET)
23199 #define G_ULPTYPE3OFFSET(x) (((x) >> S_ULPTYPE3OFFSET) & M_ULPTYPE3OFFSET)
23201 #define S_ULPTYPE2LENGTH 11
23202 #define V_ULPTYPE2LENGTH(x) ((x) << S_ULPTYPE2LENGTH)
23203 #define F_ULPTYPE2LENGTH V_ULPTYPE2LENGTH(1U)
23205 #define S_ULPTYPE2OFFSET 8
23206 #define M_ULPTYPE2OFFSET 0x7U
23207 #define V_ULPTYPE2OFFSET(x) ((x) << S_ULPTYPE2OFFSET)
23208 #define G_ULPTYPE2OFFSET(x) (((x) >> S_ULPTYPE2OFFSET) & M_ULPTYPE2OFFSET)
23210 #define S_ULPTYPE1LENGTH 7
23211 #define V_ULPTYPE1LENGTH(x) ((x) << S_ULPTYPE1LENGTH)
23212 #define F_ULPTYPE1LENGTH V_ULPTYPE1LENGTH(1U)
23214 #define S_ULPTYPE1OFFSET 4
23215 #define M_ULPTYPE1OFFSET 0x7U
23216 #define V_ULPTYPE1OFFSET(x) ((x) << S_ULPTYPE1OFFSET)
23217 #define G_ULPTYPE1OFFSET(x) (((x) >> S_ULPTYPE1OFFSET) & M_ULPTYPE1OFFSET)
23219 #define S_ULPTYPE0LENGTH 3
23220 #define V_ULPTYPE0LENGTH(x) ((x) << S_ULPTYPE0LENGTH)
23221 #define F_ULPTYPE0LENGTH V_ULPTYPE0LENGTH(1U)
23223 #define S_ULPTYPE0OFFSET 0
23224 #define M_ULPTYPE0OFFSET 0x7U
23225 #define V_ULPTYPE0OFFSET(x) ((x) << S_ULPTYPE0OFFSET)
23226 #define G_ULPTYPE0OFFSET(x) (((x) >> S_ULPTYPE0OFFSET) & M_ULPTYPE0OFFSET)
23228 #define A_TP_RSS_LKP_TABLE 0x7dec
23230 #define S_LKPTBLROWVLD 31
23231 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
23232 #define F_LKPTBLROWVLD V_LKPTBLROWVLD(1U)
23234 #define S_LKPTBLROWIDX 20
23235 #define M_LKPTBLROWIDX 0x3ffU
23236 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
23237 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
23239 #define S_LKPTBLQUEUE1 10
23240 #define M_LKPTBLQUEUE1 0x3ffU
23241 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
23242 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
23244 #define S_LKPTBLQUEUE0 0
23245 #define M_LKPTBLQUEUE0 0x3ffU
23246 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
23247 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
23249 #define S_T6_LKPTBLROWIDX 20
23250 #define M_T6_LKPTBLROWIDX 0x7ffU
23251 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
23252 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
23254 #define A_TP_RSS_CONFIG 0x7df0
23256 #define S_TNL4TUPENIPV6 31
23257 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
23258 #define F_TNL4TUPENIPV6 V_TNL4TUPENIPV6(1U)
23260 #define S_TNL2TUPENIPV6 30
23261 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
23262 #define F_TNL2TUPENIPV6 V_TNL2TUPENIPV6(1U)
23264 #define S_TNL4TUPENIPV4 29
23265 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
23266 #define F_TNL4TUPENIPV4 V_TNL4TUPENIPV4(1U)
23268 #define S_TNL2TUPENIPV4 28
23269 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
23270 #define F_TNL2TUPENIPV4 V_TNL2TUPENIPV4(1U)
23272 #define S_TNLTCPSEL 27
23273 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
23274 #define F_TNLTCPSEL V_TNLTCPSEL(1U)
23276 #define S_TNLIP6SEL 26
23277 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
23278 #define F_TNLIP6SEL V_TNLIP6SEL(1U)
23280 #define S_TNLVRTSEL 25
23281 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
23282 #define F_TNLVRTSEL V_TNLVRTSEL(1U)
23284 #define S_TNLMAPEN 24
23285 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
23286 #define F_TNLMAPEN V_TNLMAPEN(1U)
23288 #define S_OFDHASHSAVE 19
23289 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
23290 #define F_OFDHASHSAVE V_OFDHASHSAVE(1U)
23292 #define S_OFDVRTSEL 18
23293 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
23294 #define F_OFDVRTSEL V_OFDVRTSEL(1U)
23296 #define S_OFDMAPEN 17
23297 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
23298 #define F_OFDMAPEN V_OFDMAPEN(1U)
23300 #define S_OFDLKPEN 16
23301 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
23302 #define F_OFDLKPEN V_OFDLKPEN(1U)
23304 #define S_SYN4TUPENIPV6 15
23305 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
23306 #define F_SYN4TUPENIPV6 V_SYN4TUPENIPV6(1U)
23308 #define S_SYN2TUPENIPV6 14
23309 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
23310 #define F_SYN2TUPENIPV6 V_SYN2TUPENIPV6(1U)
23312 #define S_SYN4TUPENIPV4 13
23313 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
23314 #define F_SYN4TUPENIPV4 V_SYN4TUPENIPV4(1U)
23316 #define S_SYN2TUPENIPV4 12
23317 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
23318 #define F_SYN2TUPENIPV4 V_SYN2TUPENIPV4(1U)
23320 #define S_SYNIP6SEL 11
23321 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
23322 #define F_SYNIP6SEL V_SYNIP6SEL(1U)
23324 #define S_SYNVRTSEL 10
23325 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
23326 #define F_SYNVRTSEL V_SYNVRTSEL(1U)
23328 #define S_SYNMAPEN 9
23329 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
23330 #define F_SYNMAPEN V_SYNMAPEN(1U)
23332 #define S_SYNLKPEN 8
23333 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
23334 #define F_SYNLKPEN V_SYNLKPEN(1U)
23336 #define S_CHANNELENABLE 7
23337 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
23338 #define F_CHANNELENABLE V_CHANNELENABLE(1U)
23340 #define S_PORTENABLE 6
23341 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
23342 #define F_PORTENABLE V_PORTENABLE(1U)
23344 #define S_TNLALLLOOKUP 5
23345 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
23346 #define F_TNLALLLOOKUP V_TNLALLLOOKUP(1U)
23348 #define S_VIRTENABLE 4
23349 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
23350 #define F_VIRTENABLE V_VIRTENABLE(1U)
23352 #define S_CONGESTIONENABLE 3
23353 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
23354 #define F_CONGESTIONENABLE V_CONGESTIONENABLE(1U)
23356 #define S_HASHTOEPLITZ 2
23357 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
23358 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
23360 #define S_UDPENABLE 1
23361 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
23362 #define F_UDPENABLE V_UDPENABLE(1U)
23364 #define S_DISABLE 0
23365 #define V_DISABLE(x) ((x) << S_DISABLE)
23366 #define F_DISABLE V_DISABLE(1U)
23368 #define S_TNLFCOEMODE 23
23369 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
23370 #define F_TNLFCOEMODE V_TNLFCOEMODE(1U)
23372 #define S_TNLFCOEEN 21
23373 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
23374 #define F_TNLFCOEEN V_TNLFCOEEN(1U)
23376 #define S_HASHXOR 20
23377 #define V_HASHXOR(x) ((x) << S_HASHXOR)
23378 #define F_HASHXOR V_HASHXOR(1U)
23380 #define S_TNLFCOESID 22
23381 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
23382 #define F_TNLFCOESID V_TNLFCOESID(1U)
23384 #define A_TP_RSS_CONFIG_TNL 0x7df4
23386 #define S_MASKSIZE 28
23387 #define M_MASKSIZE 0xfU
23388 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
23389 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
23391 #define S_MASKFILTER 16
23392 #define M_MASKFILTER 0x7ffU
23393 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
23394 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
23396 #define S_USEWIRECH 0
23397 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
23398 #define F_USEWIRECH V_USEWIRECH(1U)
23400 #define S_HASHALL 2
23401 #define V_HASHALL(x) ((x) << S_HASHALL)
23402 #define F_HASHALL V_HASHALL(1U)
23404 #define S_HASHETH 1
23405 #define V_HASHETH(x) ((x) << S_HASHETH)
23406 #define F_HASHETH V_HASHETH(1U)
23408 #define A_TP_RSS_CONFIG_OFD 0x7df8
23410 #define S_RRCPLMAPEN 20
23411 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
23412 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U)
23414 #define S_RRCPLQUEWIDTH 16
23415 #define M_RRCPLQUEWIDTH 0xfU
23416 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
23417 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
23419 #define S_FRMWRQUEMASK 12
23420 #define M_FRMWRQUEMASK 0xfU
23421 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
23422 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
23424 #define A_TP_RSS_CONFIG_SYN 0x7dfc
23425 #define A_TP_RSS_CONFIG_VRT 0x7e00
23427 #define S_VFRDRG 25
23428 #define V_VFRDRG(x) ((x) << S_VFRDRG)
23429 #define F_VFRDRG V_VFRDRG(1U)
23431 #define S_VFRDEN 24
23432 #define V_VFRDEN(x) ((x) << S_VFRDEN)
23433 #define F_VFRDEN V_VFRDEN(1U)
23435 #define S_VFPERREN 23
23436 #define V_VFPERREN(x) ((x) << S_VFPERREN)
23437 #define F_VFPERREN V_VFPERREN(1U)
23439 #define S_KEYPERREN 22
23440 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
23441 #define F_KEYPERREN V_KEYPERREN(1U)
23443 #define S_DISABLEVLAN 21
23444 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
23445 #define F_DISABLEVLAN V_DISABLEVLAN(1U)
23447 #define S_ENABLEUP0 20
23448 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
23449 #define F_ENABLEUP0 V_ENABLEUP0(1U)
23451 #define S_HASHDELAY 16
23452 #define M_HASHDELAY 0xfU
23453 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
23454 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
23456 #define S_VFWRADDR 8
23457 #define M_VFWRADDR 0x7fU
23458 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
23459 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
23461 #define S_KEYMODE 6
23462 #define M_KEYMODE 0x3U
23463 #define V_KEYMODE(x) ((x) << S_KEYMODE)
23464 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
23467 #define V_VFWREN(x) ((x) << S_VFWREN)
23468 #define F_VFWREN V_VFWREN(1U)
23470 #define S_KEYWREN 4
23471 #define V_KEYWREN(x) ((x) << S_KEYWREN)
23472 #define F_KEYWREN V_KEYWREN(1U)
23474 #define S_KEYWRADDR 0
23475 #define M_KEYWRADDR 0xfU
23476 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
23477 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
23479 #define S_VFVLANEN 21
23480 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
23481 #define F_VFVLANEN V_VFVLANEN(1U)
23483 #define S_VFFWEN 20
23484 #define V_VFFWEN(x) ((x) << S_VFFWEN)
23485 #define F_VFFWEN V_VFFWEN(1U)
23487 #define S_KEYWRADDRX 30
23488 #define M_KEYWRADDRX 0x3U
23489 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
23490 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
23492 #define S_KEYEXTEND 26
23493 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
23494 #define F_KEYEXTEND V_KEYEXTEND(1U)
23496 #define S_T6_VFWRADDR 8
23497 #define M_T6_VFWRADDR 0xffU
23498 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
23499 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
23501 #define A_TP_RSS_CONFIG_CNG 0x7e04
23503 #define S_CHNCOUNT3 31
23504 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
23505 #define F_CHNCOUNT3 V_CHNCOUNT3(1U)
23507 #define S_CHNCOUNT2 30
23508 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
23509 #define F_CHNCOUNT2 V_CHNCOUNT2(1U)
23511 #define S_CHNCOUNT1 29
23512 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
23513 #define F_CHNCOUNT1 V_CHNCOUNT1(1U)
23515 #define S_CHNCOUNT0 28
23516 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
23517 #define F_CHNCOUNT0 V_CHNCOUNT0(1U)
23519 #define S_CHNUNDFLOW3 27
23520 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
23521 #define F_CHNUNDFLOW3 V_CHNUNDFLOW3(1U)
23523 #define S_CHNUNDFLOW2 26
23524 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
23525 #define F_CHNUNDFLOW2 V_CHNUNDFLOW2(1U)
23527 #define S_CHNUNDFLOW1 25
23528 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
23529 #define F_CHNUNDFLOW1 V_CHNUNDFLOW1(1U)
23531 #define S_CHNUNDFLOW0 24
23532 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
23533 #define F_CHNUNDFLOW0 V_CHNUNDFLOW0(1U)
23535 #define S_CHNOVRFLOW3 23
23536 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
23537 #define F_CHNOVRFLOW3 V_CHNOVRFLOW3(1U)
23539 #define S_CHNOVRFLOW2 22
23540 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
23541 #define F_CHNOVRFLOW2 V_CHNOVRFLOW2(1U)
23543 #define S_CHNOVRFLOW1 21
23544 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
23545 #define F_CHNOVRFLOW1 V_CHNOVRFLOW1(1U)
23547 #define S_CHNOVRFLOW0 20
23548 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
23549 #define F_CHNOVRFLOW0 V_CHNOVRFLOW0(1U)
23551 #define S_RSTCHN3 19
23552 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
23553 #define F_RSTCHN3 V_RSTCHN3(1U)
23555 #define S_RSTCHN2 18
23556 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
23557 #define F_RSTCHN2 V_RSTCHN2(1U)
23559 #define S_RSTCHN1 17
23560 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
23561 #define F_RSTCHN1 V_RSTCHN1(1U)
23563 #define S_RSTCHN0 16
23564 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
23565 #define F_RSTCHN0 V_RSTCHN0(1U)
23567 #define S_UPDVLD 15
23568 #define V_UPDVLD(x) ((x) << S_UPDVLD)
23569 #define F_UPDVLD V_UPDVLD(1U)
23572 #define V_XOFF(x) ((x) << S_XOFF)
23573 #define F_XOFF V_XOFF(1U)
23575 #define S_UPDCHN3 13
23576 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
23577 #define F_UPDCHN3 V_UPDCHN3(1U)
23579 #define S_UPDCHN2 12
23580 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
23581 #define F_UPDCHN2 V_UPDCHN2(1U)
23583 #define S_UPDCHN1 11
23584 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
23585 #define F_UPDCHN1 V_UPDCHN1(1U)
23587 #define S_UPDCHN0 10
23588 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
23589 #define F_UPDCHN0 V_UPDCHN0(1U)
23592 #define M_QUEUE 0x3ffU
23593 #define V_QUEUE(x) ((x) << S_QUEUE)
23594 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
23596 #define A_TP_LA_TABLE_0 0x7e10
23598 #define S_VIRTPORT1TABLE 16
23599 #define M_VIRTPORT1TABLE 0xffffU
23600 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
23601 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
23603 #define S_VIRTPORT0TABLE 0
23604 #define M_VIRTPORT0TABLE 0xffffU
23605 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
23606 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
23608 #define A_TP_LA_TABLE_1 0x7e14
23610 #define S_VIRTPORT3TABLE 16
23611 #define M_VIRTPORT3TABLE 0xffffU
23612 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
23613 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
23615 #define S_VIRTPORT2TABLE 0
23616 #define M_VIRTPORT2TABLE 0xffffU
23617 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
23618 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
23620 #define A_TP_TM_PIO_ADDR 0x7e18
23621 #define A_TP_TM_PIO_DATA 0x7e1c
23622 #define A_TP_MOD_CONFIG 0x7e24
23624 #define S_RXCHANNELWEIGHT1 24
23625 #define M_RXCHANNELWEIGHT1 0xffU
23626 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
23627 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
23629 #define S_RXCHANNELWEIGHT0 16
23630 #define M_RXCHANNELWEIGHT0 0xffU
23631 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
23632 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
23634 #define S_TIMERMODE 8
23635 #define M_TIMERMODE 0xffU
23636 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
23637 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
23639 #define S_TXCHANNELXOFFEN 0
23640 #define M_TXCHANNELXOFFEN 0xfU
23641 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
23642 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
23644 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
23646 #define S_RX_MOD_WEIGHT 24
23647 #define M_RX_MOD_WEIGHT 0xffU
23648 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
23649 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
23651 #define S_TX_MOD_WEIGHT 16
23652 #define M_TX_MOD_WEIGHT 0xffU
23653 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
23654 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
23656 #define S_TX_MOD_QUEUE_REQ_MAP 0
23657 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
23658 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
23659 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
23661 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
23663 #define S_TX_MODQ_WEIGHT7 24
23664 #define M_TX_MODQ_WEIGHT7 0xffU
23665 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
23666 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
23668 #define S_TX_MODQ_WEIGHT6 16
23669 #define M_TX_MODQ_WEIGHT6 0xffU
23670 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
23671 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
23673 #define S_TX_MODQ_WEIGHT5 8
23674 #define M_TX_MODQ_WEIGHT5 0xffU
23675 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
23676 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
23678 #define S_TX_MODQ_WEIGHT4 0
23679 #define M_TX_MODQ_WEIGHT4 0xffU
23680 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
23681 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
23683 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
23685 #define S_TX_MODQ_WEIGHT3 24
23686 #define M_TX_MODQ_WEIGHT3 0xffU
23687 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
23688 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
23690 #define S_TX_MODQ_WEIGHT2 16
23691 #define M_TX_MODQ_WEIGHT2 0xffU
23692 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
23693 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
23695 #define S_TX_MODQ_WEIGHT1 8
23696 #define M_TX_MODQ_WEIGHT1 0xffU
23697 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
23698 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
23700 #define S_TX_MODQ_WEIGHT0 0
23701 #define M_TX_MODQ_WEIGHT0 0xffU
23702 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
23703 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
23705 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
23706 #define A_TP_MOD_RATE_LIMIT 0x7e38
23708 #define S_RX_MOD_RATE_LIMIT_INC 24
23709 #define M_RX_MOD_RATE_LIMIT_INC 0xffU
23710 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
23711 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
23713 #define S_RX_MOD_RATE_LIMIT_TICK 16
23714 #define M_RX_MOD_RATE_LIMIT_TICK 0xffU
23715 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
23716 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
23718 #define S_TX_MOD_RATE_LIMIT_INC 8
23719 #define M_TX_MOD_RATE_LIMIT_INC 0xffU
23720 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
23721 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
23723 #define S_TX_MOD_RATE_LIMIT_TICK 0
23724 #define M_TX_MOD_RATE_LIMIT_TICK 0xffU
23725 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
23726 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
23728 #define A_TP_PIO_ADDR 0x7e40
23729 #define A_TP_PIO_DATA 0x7e44
23730 #define A_TP_RESET 0x7e4c
23732 #define S_FLSTINITENABLE 1
23733 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
23734 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
23736 #define S_TPRESET 0
23737 #define V_TPRESET(x) ((x) << S_TPRESET)
23738 #define F_TPRESET V_TPRESET(1U)
23740 #define A_TP_MIB_INDEX 0x7e50
23741 #define A_TP_MIB_DATA 0x7e54
23742 #define A_TP_SYNC_TIME_HI 0x7e58
23743 #define A_TP_SYNC_TIME_LO 0x7e5c
23744 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
23745 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
23746 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
23747 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
23749 #define S_CMMAXPSTRUCT 0
23750 #define M_CMMAXPSTRUCT 0x1fffffU
23751 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
23752 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
23754 #define A_TP_INT_ENABLE 0x7e70
23756 #define S_FLMTXFLSTEMPTY 30
23757 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
23758 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
23760 #define S_RSSLKPPERR 29
23761 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
23762 #define F_RSSLKPPERR V_RSSLKPPERR(1U)
23764 #define S_FLMPERRSET 28
23765 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
23766 #define F_FLMPERRSET V_FLMPERRSET(1U)
23768 #define S_PROTOCOLSRAMPERR 27
23769 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
23770 #define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U)
23772 #define S_ARPLUTPERR 26
23773 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
23774 #define F_ARPLUTPERR V_ARPLUTPERR(1U)
23776 #define S_CMRCFOPPERR 25
23777 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
23778 #define F_CMRCFOPPERR V_CMRCFOPPERR(1U)
23780 #define S_CMCACHEPERR 24
23781 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
23782 #define F_CMCACHEPERR V_CMCACHEPERR(1U)
23784 #define S_CMRCFDATAPERR 23
23785 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
23786 #define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U)
23788 #define S_DBL2TLUTPERR 22
23789 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
23790 #define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U)
23792 #define S_DBTXTIDPERR 21
23793 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
23794 #define F_DBTXTIDPERR V_DBTXTIDPERR(1U)
23796 #define S_DBEXTPERR 20
23797 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
23798 #define F_DBEXTPERR V_DBEXTPERR(1U)
23800 #define S_DBOPPERR 19
23801 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
23802 #define F_DBOPPERR V_DBOPPERR(1U)
23804 #define S_TMCACHEPERR 18
23805 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
23806 #define F_TMCACHEPERR V_TMCACHEPERR(1U)
23808 #define S_ETPOUTCPLFIFOPERR 17
23809 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
23810 #define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U)
23812 #define S_ETPOUTTCPFIFOPERR 16
23813 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
23814 #define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U)
23816 #define S_ETPOUTIPFIFOPERR 15
23817 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
23818 #define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U)
23820 #define S_ETPOUTETHFIFOPERR 14
23821 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
23822 #define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U)
23824 #define S_ETPINCPLFIFOPERR 13
23825 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
23826 #define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U)
23828 #define S_ETPINTCPOPTFIFOPERR 12
23829 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
23830 #define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U)
23832 #define S_ETPINTCPFIFOPERR 11
23833 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
23834 #define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U)
23836 #define S_ETPINIPFIFOPERR 10
23837 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
23838 #define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U)
23840 #define S_ETPINETHFIFOPERR 9
23841 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
23842 #define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U)
23844 #define S_CTPOUTCPLFIFOPERR 8
23845 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
23846 #define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U)
23848 #define S_CTPOUTTCPFIFOPERR 7
23849 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
23850 #define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U)
23852 #define S_CTPOUTIPFIFOPERR 6
23853 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
23854 #define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U)
23856 #define S_CTPOUTETHFIFOPERR 5
23857 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
23858 #define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U)
23860 #define S_CTPINCPLFIFOPERR 4
23861 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
23862 #define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U)
23864 #define S_CTPINTCPOPFIFOPERR 3
23865 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
23866 #define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U)
23868 #define S_PDUFBKFIFOPERR 2
23869 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
23870 #define F_PDUFBKFIFOPERR V_PDUFBKFIFOPERR(1U)
23872 #define S_CMOPEXTFIFOPERR 1
23873 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
23874 #define F_CMOPEXTFIFOPERR V_CMOPEXTFIFOPERR(1U)
23876 #define S_DELINVFIFOPERR 0
23877 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
23878 #define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U)
23880 #define S_CTPOUTPLDFIFOPERR 7
23881 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
23882 #define F_CTPOUTPLDFIFOPERR V_CTPOUTPLDFIFOPERR(1U)
23884 #define S_SRQTABLEPERR 1
23885 #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
23886 #define F_SRQTABLEPERR V_SRQTABLEPERR(1U)
23888 #define A_TP_INT_CAUSE 0x7e74
23889 #define A_TP_PER_ENABLE 0x7e78
23890 #define A_TP_FLM_FREE_PS_CNT 0x7e80
23892 #define S_FREEPSTRUCTCOUNT 0
23893 #define M_FREEPSTRUCTCOUNT 0x1fffffU
23894 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
23895 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
23897 #define A_TP_FLM_FREE_RX_CNT 0x7e84
23899 #define S_FREERXPAGECHN 28
23900 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
23901 #define F_FREERXPAGECHN V_FREERXPAGECHN(1U)
23903 #define S_FREERXPAGECOUNT 0
23904 #define M_FREERXPAGECOUNT 0x1fffffU
23905 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
23906 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
23908 #define A_TP_FLM_FREE_TX_CNT 0x7e88
23910 #define S_FREETXPAGECHN 28
23911 #define M_FREETXPAGECHN 0x3U
23912 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
23913 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
23915 #define S_FREETXPAGECOUNT 0
23916 #define M_FREETXPAGECOUNT 0x1fffffU
23917 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
23918 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
23920 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
23921 #define A_TP_TM_HEAP_POP_CNT 0x7e90
23922 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
23923 #define A_TP_TM_DACK_POP_CNT 0x7e98
23924 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
23925 #define A_TP_MOD_POP_CNT 0x7ea0
23926 #define A_TP_TIMER_SEPARATOR 0x7ea4
23928 #define S_TIMERSEPARATOR 16
23929 #define M_TIMERSEPARATOR 0xffffU
23930 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
23931 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
23933 #define S_DISABLETIMEFREEZE 0
23934 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
23935 #define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U)
23937 #define A_TP_STAMP_TIME 0x7ea8
23938 #define A_TP_DEBUG_FLAGS 0x7eac
23940 #define S_RXTIMERDACKFIRST 26
23941 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
23942 #define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U)
23944 #define S_RXTIMERDACK 25
23945 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
23946 #define F_RXTIMERDACK V_RXTIMERDACK(1U)
23948 #define S_RXTIMERHEARTBEAT 24
23949 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
23950 #define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U)
23952 #define S_RXPAWSDROP 23
23953 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
23954 #define F_RXPAWSDROP V_RXPAWSDROP(1U)
23956 #define S_RXURGDATADROP 22
23957 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
23958 #define F_RXURGDATADROP V_RXURGDATADROP(1U)
23960 #define S_RXFUTUREDATA 21
23961 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
23962 #define F_RXFUTUREDATA V_RXFUTUREDATA(1U)
23964 #define S_RXRCVRXMDATA 20
23965 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
23966 #define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U)
23968 #define S_RXRCVOOODATAFIN 19
23969 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
23970 #define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U)
23972 #define S_RXRCVOOODATA 18
23973 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
23974 #define F_RXRCVOOODATA V_RXRCVOOODATA(1U)
23976 #define S_RXRCVWNDZERO 17
23977 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
23978 #define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U)
23980 #define S_RXRCVWNDLTMSS 16
23981 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
23982 #define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U)
23984 #define S_TXDUPACKINC 11
23985 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
23986 #define F_TXDUPACKINC V_TXDUPACKINC(1U)
23988 #define S_TXRXMURG 10
23989 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
23990 #define F_TXRXMURG V_TXRXMURG(1U)
23992 #define S_TXRXMFIN 9
23993 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
23994 #define F_TXRXMFIN V_TXRXMFIN(1U)
23996 #define S_TXRXMSYN 8
23997 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
23998 #define F_TXRXMSYN V_TXRXMSYN(1U)
24000 #define S_TXRXMNEWRENO 7
24001 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
24002 #define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U)
24004 #define S_TXRXMFAST 6
24005 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
24006 #define F_TXRXMFAST V_TXRXMFAST(1U)
24008 #define S_TXRXMTIMER 5
24009 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
24010 #define F_TXRXMTIMER V_TXRXMTIMER(1U)
24012 #define S_TXRXMTIMERKEEPALIVE 4
24013 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
24014 #define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U)
24016 #define S_TXRXMTIMERPERSIST 3
24017 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
24018 #define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U)
24020 #define S_TXRCVADVSHRUNK 2
24021 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
24022 #define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U)
24024 #define S_TXRCVADVZERO 1
24025 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
24026 #define F_TXRCVADVZERO V_TXRCVADVZERO(1U)
24028 #define S_TXRCVADVLTMSS 0
24029 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
24030 #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U)
24032 #define S_RXTIMERCOMPBUFFER 27
24033 #define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
24034 #define F_RXTIMERCOMPBUFFER V_RXTIMERCOMPBUFFER(1U)
24036 #define S_TXDFRFAST 13
24037 #define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
24038 #define F_TXDFRFAST V_TXDFRFAST(1U)
24040 #define S_TXRXMMISC 12
24041 #define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
24042 #define F_TXRXMMISC V_TXRXMMISC(1U)
24044 #define A_TP_RX_SCHED 0x7eb0
24046 #define S_RXCOMMITRESET1 31
24047 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
24048 #define F_RXCOMMITRESET1 V_RXCOMMITRESET1(1U)
24050 #define S_RXCOMMITRESET0 30
24051 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
24052 #define F_RXCOMMITRESET0 V_RXCOMMITRESET0(1U)
24054 #define S_RXFORCECONG1 29
24055 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
24056 #define F_RXFORCECONG1 V_RXFORCECONG1(1U)
24058 #define S_RXFORCECONG0 28
24059 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
24060 #define F_RXFORCECONG0 V_RXFORCECONG0(1U)
24062 #define S_ENABLELPBKFULL1 26
24063 #define M_ENABLELPBKFULL1 0x3U
24064 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
24065 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
24067 #define S_ENABLELPBKFULL0 24
24068 #define M_ENABLELPBKFULL0 0x3U
24069 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
24070 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
24072 #define S_ENABLEFIFOFULL1 22
24073 #define M_ENABLEFIFOFULL1 0x3U
24074 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
24075 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
24077 #define S_ENABLEPCMDFULL1 20
24078 #define M_ENABLEPCMDFULL1 0x3U
24079 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
24080 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
24082 #define S_ENABLEHDRFULL1 18
24083 #define M_ENABLEHDRFULL1 0x3U
24084 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
24085 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
24087 #define S_ENABLEFIFOFULL0 16
24088 #define M_ENABLEFIFOFULL0 0x3U
24089 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
24090 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
24092 #define S_ENABLEPCMDFULL0 14
24093 #define M_ENABLEPCMDFULL0 0x3U
24094 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
24095 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
24097 #define S_ENABLEHDRFULL0 12
24098 #define M_ENABLEHDRFULL0 0x3U
24099 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
24100 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
24102 #define S_COMMITLIMIT1 6
24103 #define M_COMMITLIMIT1 0x3fU
24104 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
24105 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
24107 #define S_COMMITLIMIT0 0
24108 #define M_COMMITLIMIT0 0x3fU
24109 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
24110 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
24112 #define A_TP_TX_SCHED 0x7eb4
24114 #define S_COMMITRESET3 31
24115 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
24116 #define F_COMMITRESET3 V_COMMITRESET3(1U)
24118 #define S_COMMITRESET2 30
24119 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
24120 #define F_COMMITRESET2 V_COMMITRESET2(1U)
24122 #define S_COMMITRESET1 29
24123 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
24124 #define F_COMMITRESET1 V_COMMITRESET1(1U)
24126 #define S_COMMITRESET0 28
24127 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
24128 #define F_COMMITRESET0 V_COMMITRESET0(1U)
24130 #define S_FORCECONG3 27
24131 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
24132 #define F_FORCECONG3 V_FORCECONG3(1U)
24134 #define S_FORCECONG2 26
24135 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
24136 #define F_FORCECONG2 V_FORCECONG2(1U)
24138 #define S_FORCECONG1 25
24139 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
24140 #define F_FORCECONG1 V_FORCECONG1(1U)
24142 #define S_FORCECONG0 24
24143 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
24144 #define F_FORCECONG0 V_FORCECONG0(1U)
24146 #define S_COMMITLIMIT3 18
24147 #define M_COMMITLIMIT3 0x3fU
24148 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
24149 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
24151 #define S_COMMITLIMIT2 12
24152 #define M_COMMITLIMIT2 0x3fU
24153 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
24154 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
24156 #define A_TP_FX_SCHED 0x7eb8
24158 #define S_TXCHNXOFF3 19
24159 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
24160 #define F_TXCHNXOFF3 V_TXCHNXOFF3(1U)
24162 #define S_TXCHNXOFF2 18
24163 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
24164 #define F_TXCHNXOFF2 V_TXCHNXOFF2(1U)
24166 #define S_TXCHNXOFF1 17
24167 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
24168 #define F_TXCHNXOFF1 V_TXCHNXOFF1(1U)
24170 #define S_TXCHNXOFF0 16
24171 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
24172 #define F_TXCHNXOFF0 V_TXCHNXOFF0(1U)
24174 #define S_TXMODXOFF7 15
24175 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
24176 #define F_TXMODXOFF7 V_TXMODXOFF7(1U)
24178 #define S_TXMODXOFF6 14
24179 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
24180 #define F_TXMODXOFF6 V_TXMODXOFF6(1U)
24182 #define S_TXMODXOFF5 13
24183 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
24184 #define F_TXMODXOFF5 V_TXMODXOFF5(1U)
24186 #define S_TXMODXOFF4 12
24187 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
24188 #define F_TXMODXOFF4 V_TXMODXOFF4(1U)
24190 #define S_TXMODXOFF3 11
24191 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
24192 #define F_TXMODXOFF3 V_TXMODXOFF3(1U)
24194 #define S_TXMODXOFF2 10
24195 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
24196 #define F_TXMODXOFF2 V_TXMODXOFF2(1U)
24198 #define S_TXMODXOFF1 9
24199 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
24200 #define F_TXMODXOFF1 V_TXMODXOFF1(1U)
24202 #define S_TXMODXOFF0 8
24203 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
24204 #define F_TXMODXOFF0 V_TXMODXOFF0(1U)
24206 #define S_RXCHNXOFF3 7
24207 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
24208 #define F_RXCHNXOFF3 V_RXCHNXOFF3(1U)
24210 #define S_RXCHNXOFF2 6
24211 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
24212 #define F_RXCHNXOFF2 V_RXCHNXOFF2(1U)
24214 #define S_RXCHNXOFF1 5
24215 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
24216 #define F_RXCHNXOFF1 V_RXCHNXOFF1(1U)
24218 #define S_RXCHNXOFF0 4
24219 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
24220 #define F_RXCHNXOFF0 V_RXCHNXOFF0(1U)
24222 #define S_RXMODXOFF1 1
24223 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
24224 #define F_RXMODXOFF1 V_RXMODXOFF1(1U)
24226 #define S_RXMODXOFF0 0
24227 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
24228 #define F_RXMODXOFF0 V_RXMODXOFF0(1U)
24230 #define A_TP_TX_ORATE 0x7ebc
24232 #define S_OFDRATE3 24
24233 #define M_OFDRATE3 0xffU
24234 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
24235 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
24237 #define S_OFDRATE2 16
24238 #define M_OFDRATE2 0xffU
24239 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
24240 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
24242 #define S_OFDRATE1 8
24243 #define M_OFDRATE1 0xffU
24244 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
24245 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
24247 #define S_OFDRATE0 0
24248 #define M_OFDRATE0 0xffU
24249 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
24250 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
24252 #define A_TP_IX_SCHED0 0x7ec0
24253 #define A_TP_IX_SCHED1 0x7ec4
24254 #define A_TP_IX_SCHED2 0x7ec8
24255 #define A_TP_IX_SCHED3 0x7ecc
24256 #define A_TP_TX_TRATE 0x7ed0
24258 #define S_TNLRATE3 24
24259 #define M_TNLRATE3 0xffU
24260 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
24261 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
24263 #define S_TNLRATE2 16
24264 #define M_TNLRATE2 0xffU
24265 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
24266 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
24268 #define S_TNLRATE1 8
24269 #define M_TNLRATE1 0xffU
24270 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
24271 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
24273 #define S_TNLRATE0 0
24274 #define M_TNLRATE0 0xffU
24275 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
24276 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
24278 #define A_TP_DBG_LA_CONFIG 0x7ed4
24280 #define S_DBGLAOPCENABLE 24
24281 #define M_DBGLAOPCENABLE 0xffU
24282 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
24283 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
24285 #define S_DBGLAWHLF 23
24286 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
24287 #define F_DBGLAWHLF V_DBGLAWHLF(1U)
24289 #define S_DBGLAWPTR 16
24290 #define M_DBGLAWPTR 0x7fU
24291 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
24292 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
24294 #define S_DBGLAMODE 14
24295 #define M_DBGLAMODE 0x3U
24296 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
24297 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
24299 #define S_DBGLAFATALFREEZE 13
24300 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
24301 #define F_DBGLAFATALFREEZE V_DBGLAFATALFREEZE(1U)
24303 #define S_DBGLAENABLE 12
24304 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
24305 #define F_DBGLAENABLE V_DBGLAENABLE(1U)
24307 #define S_DBGLARPTR 0
24308 #define M_DBGLARPTR 0x7fU
24309 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
24310 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
24312 #define A_TP_DBG_LA_DATAL 0x7ed8
24313 #define A_TP_DBG_LA_DATAH 0x7edc
24314 #define A_TP_PROTOCOL_CNTRL 0x7ee8
24316 #define S_WRITEENABLE 31
24317 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
24318 #define F_WRITEENABLE V_WRITEENABLE(1U)
24320 #define S_TCAMENABLE 10
24321 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
24322 #define F_TCAMENABLE V_TCAMENABLE(1U)
24324 #define S_BLOCKSELECT 8
24325 #define M_BLOCKSELECT 0x3U
24326 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
24327 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
24329 #define S_LINEADDRESS 1
24330 #define M_LINEADDRESS 0x7fU
24331 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
24332 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
24334 #define S_REQUESTDONE 0
24335 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
24336 #define F_REQUESTDONE V_REQUESTDONE(1U)
24338 #define A_TP_PROTOCOL_DATA0 0x7eec
24339 #define A_TP_PROTOCOL_DATA1 0x7ef0
24340 #define A_TP_PROTOCOL_DATA2 0x7ef4
24341 #define A_TP_PROTOCOL_DATA3 0x7ef8
24342 #define A_TP_PROTOCOL_DATA4 0x7efc
24344 #define S_PROTOCOLDATAFIELD 0
24345 #define M_PROTOCOLDATAFIELD 0xfU
24346 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
24347 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
24349 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
24351 #define S_TXTIMERSEPQ7 16
24352 #define M_TXTIMERSEPQ7 0xffffU
24353 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
24354 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
24356 #define S_TXTIMERSEPQ6 0
24357 #define M_TXTIMERSEPQ6 0xffffU
24358 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
24359 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
24361 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
24363 #define S_TXTIMERSEPQ5 16
24364 #define M_TXTIMERSEPQ5 0xffffU
24365 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
24366 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
24368 #define S_TXTIMERSEPQ4 0
24369 #define M_TXTIMERSEPQ4 0xffffU
24370 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
24371 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
24373 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
24375 #define S_TXTIMERSEPQ3 16
24376 #define M_TXTIMERSEPQ3 0xffffU
24377 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
24378 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
24380 #define S_TXTIMERSEPQ2 0
24381 #define M_TXTIMERSEPQ2 0xffffU
24382 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
24383 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
24385 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
24387 #define S_TXTIMERSEPQ1 16
24388 #define M_TXTIMERSEPQ1 0xffffU
24389 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
24390 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
24392 #define S_TXTIMERSEPQ0 0
24393 #define M_TXTIMERSEPQ0 0xffffU
24394 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
24395 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
24397 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
24399 #define S_RXTIMERSEPQ1 16
24400 #define M_RXTIMERSEPQ1 0xffffU
24401 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
24402 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
24404 #define S_RXTIMERSEPQ0 0
24405 #define M_RXTIMERSEPQ0 0xffffU
24406 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
24407 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
24409 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
24411 #define S_TXRATEINCQ7 24
24412 #define M_TXRATEINCQ7 0xffU
24413 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
24414 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
24416 #define S_TXRATETCKQ7 16
24417 #define M_TXRATETCKQ7 0xffU
24418 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
24419 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
24421 #define S_TXRATEINCQ6 8
24422 #define M_TXRATEINCQ6 0xffU
24423 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
24424 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
24426 #define S_TXRATETCKQ6 0
24427 #define M_TXRATETCKQ6 0xffU
24428 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
24429 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
24431 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
24433 #define S_TXRATEINCQ5 24
24434 #define M_TXRATEINCQ5 0xffU
24435 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
24436 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
24438 #define S_TXRATETCKQ5 16
24439 #define M_TXRATETCKQ5 0xffU
24440 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
24441 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
24443 #define S_TXRATEINCQ4 8
24444 #define M_TXRATEINCQ4 0xffU
24445 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
24446 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
24448 #define S_TXRATETCKQ4 0
24449 #define M_TXRATETCKQ4 0xffU
24450 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
24451 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
24453 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
24455 #define S_TXRATEINCQ3 24
24456 #define M_TXRATEINCQ3 0xffU
24457 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
24458 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
24460 #define S_TXRATETCKQ3 16
24461 #define M_TXRATETCKQ3 0xffU
24462 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
24463 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
24465 #define S_TXRATEINCQ2 8
24466 #define M_TXRATEINCQ2 0xffU
24467 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
24468 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
24470 #define S_TXRATETCKQ2 0
24471 #define M_TXRATETCKQ2 0xffU
24472 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
24473 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
24475 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
24477 #define S_TXRATEINCQ1 24
24478 #define M_TXRATEINCQ1 0xffU
24479 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
24480 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
24482 #define S_TXRATETCKQ1 16
24483 #define M_TXRATETCKQ1 0xffU
24484 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
24485 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
24487 #define S_TXRATEINCQ0 8
24488 #define M_TXRATEINCQ0 0xffU
24489 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
24490 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
24492 #define S_TXRATETCKQ0 0
24493 #define M_TXRATETCKQ0 0xffU
24494 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
24495 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
24497 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
24499 #define S_RXRATEINCQ1 24
24500 #define M_RXRATEINCQ1 0xffU
24501 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
24502 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
24504 #define S_RXRATETCKQ1 16
24505 #define M_RXRATETCKQ1 0xffU
24506 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
24507 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
24509 #define S_RXRATEINCQ0 8
24510 #define M_RXRATEINCQ0 0xffU
24511 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
24512 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
24514 #define S_RXRATETCKQ0 0
24515 #define M_RXRATETCKQ0 0xffU
24516 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
24517 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
24519 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
24520 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
24521 #define A_TP_RX_SCHED_MAP 0x20
24523 #define S_RXMAPCHANNEL3 24
24524 #define M_RXMAPCHANNEL3 0xffU
24525 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
24526 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
24528 #define S_RXMAPCHANNEL2 16
24529 #define M_RXMAPCHANNEL2 0xffU
24530 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
24531 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
24533 #define S_RXMAPCHANNEL1 8
24534 #define M_RXMAPCHANNEL1 0xffU
24535 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
24536 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
24538 #define S_RXMAPCHANNEL0 0
24539 #define M_RXMAPCHANNEL0 0xffU
24540 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
24541 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
24543 #define A_TP_RX_SCHED_SGE 0x21
24545 #define S_RXSGEMOD1 12
24546 #define M_RXSGEMOD1 0xfU
24547 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
24548 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
24550 #define S_RXSGEMOD0 8
24551 #define M_RXSGEMOD0 0xfU
24552 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
24553 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
24555 #define S_RXSGECHANNEL3 3
24556 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
24557 #define F_RXSGECHANNEL3 V_RXSGECHANNEL3(1U)
24559 #define S_RXSGECHANNEL2 2
24560 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
24561 #define F_RXSGECHANNEL2 V_RXSGECHANNEL2(1U)
24563 #define S_RXSGECHANNEL1 1
24564 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
24565 #define F_RXSGECHANNEL1 V_RXSGECHANNEL1(1U)
24567 #define S_RXSGECHANNEL0 0
24568 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
24569 #define F_RXSGECHANNEL0 V_RXSGECHANNEL0(1U)
24571 #define A_TP_TX_SCHED_MAP 0x22
24573 #define S_TXMAPCHANNEL3 12
24574 #define M_TXMAPCHANNEL3 0xfU
24575 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
24576 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
24578 #define S_TXMAPCHANNEL2 8
24579 #define M_TXMAPCHANNEL2 0xfU
24580 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
24581 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
24583 #define S_TXMAPCHANNEL1 4
24584 #define M_TXMAPCHANNEL1 0xfU
24585 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
24586 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
24588 #define S_TXMAPCHANNEL0 0
24589 #define M_TXMAPCHANNEL0 0xfU
24590 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
24591 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
24593 #define S_TXLPKCHANNEL1 17
24594 #define V_TXLPKCHANNEL1(x) ((x) << S_TXLPKCHANNEL1)
24595 #define F_TXLPKCHANNEL1 V_TXLPKCHANNEL1(1U)
24597 #define S_TXLPKCHANNEL0 16
24598 #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
24599 #define F_TXLPKCHANNEL0 V_TXLPKCHANNEL0(1U)
24601 #define A_TP_TX_SCHED_HDR 0x23
24603 #define S_TXMAPHDRCHANNEL7 28
24604 #define M_TXMAPHDRCHANNEL7 0xfU
24605 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
24606 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
24608 #define S_TXMAPHDRCHANNEL6 24
24609 #define M_TXMAPHDRCHANNEL6 0xfU
24610 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
24611 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
24613 #define S_TXMAPHDRCHANNEL5 20
24614 #define M_TXMAPHDRCHANNEL5 0xfU
24615 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
24616 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
24618 #define S_TXMAPHDRCHANNEL4 16
24619 #define M_TXMAPHDRCHANNEL4 0xfU
24620 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
24621 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
24623 #define S_TXMAPHDRCHANNEL3 12
24624 #define M_TXMAPHDRCHANNEL3 0xfU
24625 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
24626 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
24628 #define S_TXMAPHDRCHANNEL2 8
24629 #define M_TXMAPHDRCHANNEL2 0xfU
24630 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
24631 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
24633 #define S_TXMAPHDRCHANNEL1 4
24634 #define M_TXMAPHDRCHANNEL1 0xfU
24635 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
24636 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
24638 #define S_TXMAPHDRCHANNEL0 0
24639 #define M_TXMAPHDRCHANNEL0 0xfU
24640 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
24641 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
24643 #define A_TP_TX_SCHED_FIFO 0x24
24645 #define S_TXMAPFIFOCHANNEL7 28
24646 #define M_TXMAPFIFOCHANNEL7 0xfU
24647 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
24648 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
24650 #define S_TXMAPFIFOCHANNEL6 24
24651 #define M_TXMAPFIFOCHANNEL6 0xfU
24652 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
24653 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
24655 #define S_TXMAPFIFOCHANNEL5 20
24656 #define M_TXMAPFIFOCHANNEL5 0xfU
24657 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
24658 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
24660 #define S_TXMAPFIFOCHANNEL4 16
24661 #define M_TXMAPFIFOCHANNEL4 0xfU
24662 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
24663 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
24665 #define S_TXMAPFIFOCHANNEL3 12
24666 #define M_TXMAPFIFOCHANNEL3 0xfU
24667 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
24668 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
24670 #define S_TXMAPFIFOCHANNEL2 8
24671 #define M_TXMAPFIFOCHANNEL2 0xfU
24672 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
24673 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
24675 #define S_TXMAPFIFOCHANNEL1 4
24676 #define M_TXMAPFIFOCHANNEL1 0xfU
24677 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
24678 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
24680 #define S_TXMAPFIFOCHANNEL0 0
24681 #define M_TXMAPFIFOCHANNEL0 0xfU
24682 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
24683 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
24685 #define A_TP_TX_SCHED_PCMD 0x25
24687 #define S_TXMAPPCMDCHANNEL7 28
24688 #define M_TXMAPPCMDCHANNEL7 0xfU
24689 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
24690 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
24692 #define S_TXMAPPCMDCHANNEL6 24
24693 #define M_TXMAPPCMDCHANNEL6 0xfU
24694 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
24695 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
24697 #define S_TXMAPPCMDCHANNEL5 20
24698 #define M_TXMAPPCMDCHANNEL5 0xfU
24699 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
24700 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
24702 #define S_TXMAPPCMDCHANNEL4 16
24703 #define M_TXMAPPCMDCHANNEL4 0xfU
24704 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
24705 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
24707 #define S_TXMAPPCMDCHANNEL3 12
24708 #define M_TXMAPPCMDCHANNEL3 0xfU
24709 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
24710 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
24712 #define S_TXMAPPCMDCHANNEL2 8
24713 #define M_TXMAPPCMDCHANNEL2 0xfU
24714 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
24715 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
24717 #define S_TXMAPPCMDCHANNEL1 4
24718 #define M_TXMAPPCMDCHANNEL1 0xfU
24719 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
24720 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
24722 #define S_TXMAPPCMDCHANNEL0 0
24723 #define M_TXMAPPCMDCHANNEL0 0xfU
24724 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
24725 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
24727 #define A_TP_TX_SCHED_LPBK 0x26
24729 #define S_TXMAPLPBKCHANNEL7 28
24730 #define M_TXMAPLPBKCHANNEL7 0xfU
24731 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
24732 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
24734 #define S_TXMAPLPBKCHANNEL6 24
24735 #define M_TXMAPLPBKCHANNEL6 0xfU
24736 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
24737 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
24739 #define S_TXMAPLPBKCHANNEL5 20
24740 #define M_TXMAPLPBKCHANNEL5 0xfU
24741 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
24742 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
24744 #define S_TXMAPLPBKCHANNEL4 16
24745 #define M_TXMAPLPBKCHANNEL4 0xfU
24746 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
24747 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
24749 #define S_TXMAPLPBKCHANNEL3 12
24750 #define M_TXMAPLPBKCHANNEL3 0xfU
24751 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
24752 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
24754 #define S_TXMAPLPBKCHANNEL2 8
24755 #define M_TXMAPLPBKCHANNEL2 0xfU
24756 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
24757 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
24759 #define S_TXMAPLPBKCHANNEL1 4
24760 #define M_TXMAPLPBKCHANNEL1 0xfU
24761 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
24762 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
24764 #define S_TXMAPLPBKCHANNEL0 0
24765 #define M_TXMAPLPBKCHANNEL0 0xfU
24766 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
24767 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
24769 #define A_TP_CHANNEL_MAP 0x27
24771 #define S_RXMAPCHANNELELN 16
24772 #define M_RXMAPCHANNELELN 0xfU
24773 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
24774 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
24776 #define S_RXMAPE2LCHANNEL3 14
24777 #define M_RXMAPE2LCHANNEL3 0x3U
24778 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
24779 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
24781 #define S_RXMAPE2LCHANNEL2 12
24782 #define M_RXMAPE2LCHANNEL2 0x3U
24783 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
24784 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
24786 #define S_RXMAPE2LCHANNEL1 10
24787 #define M_RXMAPE2LCHANNEL1 0x3U
24788 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
24789 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
24791 #define S_RXMAPE2LCHANNEL0 8
24792 #define M_RXMAPE2LCHANNEL0 0x3U
24793 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
24794 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
24796 #define S_RXMAPC2CCHANNEL3 7
24797 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
24798 #define F_RXMAPC2CCHANNEL3 V_RXMAPC2CCHANNEL3(1U)
24800 #define S_RXMAPC2CCHANNEL2 6
24801 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
24802 #define F_RXMAPC2CCHANNEL2 V_RXMAPC2CCHANNEL2(1U)
24804 #define S_RXMAPC2CCHANNEL1 5
24805 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
24806 #define F_RXMAPC2CCHANNEL1 V_RXMAPC2CCHANNEL1(1U)
24808 #define S_RXMAPC2CCHANNEL0 4
24809 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
24810 #define F_RXMAPC2CCHANNEL0 V_RXMAPC2CCHANNEL0(1U)
24812 #define S_RXMAPE2CCHANNEL3 3
24813 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
24814 #define F_RXMAPE2CCHANNEL3 V_RXMAPE2CCHANNEL3(1U)
24816 #define S_RXMAPE2CCHANNEL2 2
24817 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
24818 #define F_RXMAPE2CCHANNEL2 V_RXMAPE2CCHANNEL2(1U)
24820 #define S_RXMAPE2CCHANNEL1 1
24821 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
24822 #define F_RXMAPE2CCHANNEL1 V_RXMAPE2CCHANNEL1(1U)
24824 #define S_RXMAPE2CCHANNEL0 0
24825 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
24826 #define F_RXMAPE2CCHANNEL0 V_RXMAPE2CCHANNEL0(1U)
24828 #define A_TP_RX_LPBK 0x28
24829 #define A_TP_TX_LPBK 0x29
24830 #define A_TP_TX_SCHED_PPP 0x2a
24832 #define S_TXPPPENPORT3 24
24833 #define M_TXPPPENPORT3 0xffU
24834 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
24835 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
24837 #define S_TXPPPENPORT2 16
24838 #define M_TXPPPENPORT2 0xffU
24839 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
24840 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
24842 #define S_TXPPPENPORT1 8
24843 #define M_TXPPPENPORT1 0xffU
24844 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
24845 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
24847 #define S_TXPPPENPORT0 0
24848 #define M_TXPPPENPORT0 0xffU
24849 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
24850 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
24852 #define A_TP_RX_SCHED_FIFO 0x2b
24854 #define S_COMMITLIMIT1H 24
24855 #define M_COMMITLIMIT1H 0xffU
24856 #define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
24857 #define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
24859 #define S_COMMITLIMIT1L 16
24860 #define M_COMMITLIMIT1L 0xffU
24861 #define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
24862 #define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
24864 #define S_COMMITLIMIT0H 8
24865 #define M_COMMITLIMIT0H 0xffU
24866 #define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
24867 #define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
24869 #define S_COMMITLIMIT0L 0
24870 #define M_COMMITLIMIT0L 0xffU
24871 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
24872 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
24874 #define A_TP_IPMI_CFG1 0x2e
24876 #define S_VLANENABLE 31
24877 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
24878 #define F_VLANENABLE V_VLANENABLE(1U)
24880 #define S_PRIMARYPORTENABLE 30
24881 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
24882 #define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U)
24884 #define S_SECUREPORTENABLE 29
24885 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
24886 #define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U)
24888 #define S_ARPENABLE 28
24889 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
24890 #define F_ARPENABLE V_ARPENABLE(1U)
24892 #define S_IPMI_VLAN 0
24893 #define M_IPMI_VLAN 0xffffU
24894 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
24895 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
24897 #define A_TP_IPMI_CFG2 0x2f
24899 #define S_SECUREPORT 16
24900 #define M_SECUREPORT 0xffffU
24901 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
24902 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
24904 #define S_PRIMARYPORT 0
24905 #define M_PRIMARYPORT 0xffffU
24906 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
24907 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
24909 #define A_TP_RSS_PF0_CONFIG 0x30
24911 #define S_MAPENABLE 31
24912 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
24913 #define F_MAPENABLE V_MAPENABLE(1U)
24915 #define S_CHNENABLE 30
24916 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
24917 #define F_CHNENABLE V_CHNENABLE(1U)
24919 #define S_PRTENABLE 29
24920 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
24921 #define F_PRTENABLE V_PRTENABLE(1U)
24923 #define S_UDPFOURTUPEN 28
24924 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
24925 #define F_UDPFOURTUPEN V_UDPFOURTUPEN(1U)
24927 #define S_IP6FOURTUPEN 27
24928 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
24929 #define F_IP6FOURTUPEN V_IP6FOURTUPEN(1U)
24931 #define S_IP6TWOTUPEN 26
24932 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
24933 #define F_IP6TWOTUPEN V_IP6TWOTUPEN(1U)
24935 #define S_IP4FOURTUPEN 25
24936 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
24937 #define F_IP4FOURTUPEN V_IP4FOURTUPEN(1U)
24939 #define S_IP4TWOTUPEN 24
24940 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
24941 #define F_IP4TWOTUPEN V_IP4TWOTUPEN(1U)
24943 #define S_IVFWIDTH 20
24944 #define M_IVFWIDTH 0xfU
24945 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
24946 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
24948 #define S_CH1DEFAULTQUEUE 10
24949 #define M_CH1DEFAULTQUEUE 0x3ffU
24950 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
24951 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
24953 #define S_CH0DEFAULTQUEUE 0
24954 #define M_CH0DEFAULTQUEUE 0x3ffU
24955 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
24956 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
24958 #define S_PRIENABLE 30
24959 #define V_PRIENABLE(x) ((x) << S_PRIENABLE)
24960 #define F_PRIENABLE V_PRIENABLE(1U)
24962 #define S_T6_CHNENABLE 29
24963 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24964 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24966 #define A_TP_RSS_PF1_CONFIG 0x31
24968 #define S_T6_CHNENABLE 29
24969 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24970 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24972 #define A_TP_RSS_PF2_CONFIG 0x32
24974 #define S_T6_CHNENABLE 29
24975 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24976 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24978 #define A_TP_RSS_PF3_CONFIG 0x33
24980 #define S_T6_CHNENABLE 29
24981 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24982 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24984 #define A_TP_RSS_PF4_CONFIG 0x34
24986 #define S_T6_CHNENABLE 29
24987 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24988 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24990 #define A_TP_RSS_PF5_CONFIG 0x35
24992 #define S_T6_CHNENABLE 29
24993 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24994 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
24996 #define A_TP_RSS_PF6_CONFIG 0x36
24998 #define S_T6_CHNENABLE 29
24999 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
25000 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
25002 #define A_TP_RSS_PF7_CONFIG 0x37
25004 #define S_T6_CHNENABLE 29
25005 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
25006 #define F_T6_CHNENABLE V_T6_CHNENABLE(1U)
25008 #define A_TP_RSS_PF_MAP 0x38
25010 #define S_LKPIDXSIZE 24
25011 #define M_LKPIDXSIZE 0x3U
25012 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
25013 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
25015 #define S_PF7LKPIDX 21
25016 #define M_PF7LKPIDX 0x7U
25017 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
25018 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
25020 #define S_PF6LKPIDX 18
25021 #define M_PF6LKPIDX 0x7U
25022 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
25023 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
25025 #define S_PF5LKPIDX 15
25026 #define M_PF5LKPIDX 0x7U
25027 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
25028 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
25030 #define S_PF4LKPIDX 12
25031 #define M_PF4LKPIDX 0x7U
25032 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
25033 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
25035 #define S_PF3LKPIDX 9
25036 #define M_PF3LKPIDX 0x7U
25037 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
25038 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
25040 #define S_PF2LKPIDX 6
25041 #define M_PF2LKPIDX 0x7U
25042 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
25043 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
25045 #define S_PF1LKPIDX 3
25046 #define M_PF1LKPIDX 0x7U
25047 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
25048 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
25050 #define S_PF0LKPIDX 0
25051 #define M_PF0LKPIDX 0x7U
25052 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
25053 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
25055 #define A_TP_RSS_PF_MSK 0x39
25057 #define S_PF7MSKSIZE 28
25058 #define M_PF7MSKSIZE 0xfU
25059 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
25060 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
25062 #define S_PF6MSKSIZE 24
25063 #define M_PF6MSKSIZE 0xfU
25064 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
25065 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
25067 #define S_PF5MSKSIZE 20
25068 #define M_PF5MSKSIZE 0xfU
25069 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
25070 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
25072 #define S_PF4MSKSIZE 16
25073 #define M_PF4MSKSIZE 0xfU
25074 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
25075 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
25077 #define S_PF3MSKSIZE 12
25078 #define M_PF3MSKSIZE 0xfU
25079 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
25080 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
25082 #define S_PF2MSKSIZE 8
25083 #define M_PF2MSKSIZE 0xfU
25084 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
25085 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
25087 #define S_PF1MSKSIZE 4
25088 #define M_PF1MSKSIZE 0xfU
25089 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
25090 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
25092 #define S_PF0MSKSIZE 0
25093 #define M_PF0MSKSIZE 0xfU
25094 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
25095 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
25097 #define A_TP_RSS_VFL_CONFIG 0x3a
25098 #define A_TP_RSS_VFH_CONFIG 0x3b
25100 #define S_ENABLEUDPHASH 31
25101 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
25102 #define F_ENABLEUDPHASH V_ENABLEUDPHASH(1U)
25104 #define S_VFUPEN 30
25105 #define V_VFUPEN(x) ((x) << S_VFUPEN)
25106 #define F_VFUPEN V_VFUPEN(1U)
25108 #define S_VFVLNEX 28
25109 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
25110 #define F_VFVLNEX V_VFVLNEX(1U)
25112 #define S_VFPRTEN 27
25113 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
25114 #define F_VFPRTEN V_VFPRTEN(1U)
25116 #define S_VFCHNEN 26
25117 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
25118 #define F_VFCHNEN V_VFCHNEN(1U)
25120 #define S_DEFAULTQUEUE 16
25121 #define M_DEFAULTQUEUE 0x3ffU
25122 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
25123 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
25125 #define S_VFLKPIDX 8
25126 #define M_VFLKPIDX 0xffU
25127 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
25128 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
25130 #define S_VFIP6FOURTUPEN 7
25131 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
25132 #define F_VFIP6FOURTUPEN V_VFIP6FOURTUPEN(1U)
25134 #define S_VFIP6TWOTUPEN 6
25135 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
25136 #define F_VFIP6TWOTUPEN V_VFIP6TWOTUPEN(1U)
25138 #define S_VFIP4FOURTUPEN 5
25139 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
25140 #define F_VFIP4FOURTUPEN V_VFIP4FOURTUPEN(1U)
25142 #define S_VFIP4TWOTUPEN 4
25143 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
25144 #define F_VFIP4TWOTUPEN V_VFIP4TWOTUPEN(1U)
25146 #define S_KEYINDEX 0
25147 #define M_KEYINDEX 0xfU
25148 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
25149 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
25151 #define A_TP_RSS_SECRET_KEY0 0x40
25152 #define A_TP_RSS_SECRET_KEY1 0x41
25153 #define A_TP_RSS_SECRET_KEY2 0x42
25154 #define A_TP_RSS_SECRET_KEY3 0x43
25155 #define A_TP_RSS_SECRET_KEY4 0x44
25156 #define A_TP_RSS_SECRET_KEY5 0x45
25157 #define A_TP_RSS_SECRET_KEY6 0x46
25158 #define A_TP_RSS_SECRET_KEY7 0x47
25159 #define A_TP_RSS_SECRET_KEY8 0x48
25160 #define A_TP_RSS_SECRET_KEY9 0x49
25161 #define A_TP_ETHER_TYPE_VL 0x50
25163 #define S_CQFCTYPE 16
25164 #define M_CQFCTYPE 0xffffU
25165 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
25166 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
25168 #define S_VLANTYPE 0
25169 #define M_VLANTYPE 0xffffU
25170 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
25171 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
25173 #define A_TP_ETHER_TYPE_IP 0x51
25175 #define S_IPV6TYPE 16
25176 #define M_IPV6TYPE 0xffffU
25177 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
25178 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
25180 #define S_IPV4TYPE 0
25181 #define M_IPV4TYPE 0xffffU
25182 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
25183 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
25185 #define A_TP_ETHER_TYPE_FW 0x52
25187 #define S_ETHTYPE1 16
25188 #define M_ETHTYPE1 0xffffU
25189 #define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
25190 #define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
25192 #define S_ETHTYPE0 0
25193 #define M_ETHTYPE0 0xffffU
25194 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
25195 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
25197 #define A_TP_VXLAN_HEADER 0x53
25199 #define S_VXLANPORT 0
25200 #define M_VXLANPORT 0xffffU
25201 #define V_VXLANPORT(x) ((x) << S_VXLANPORT)
25202 #define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT)
25204 #define A_TP_CORE_POWER 0x54
25206 #define S_SLEEPRDYVNT 12
25207 #define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
25208 #define F_SLEEPRDYVNT V_SLEEPRDYVNT(1U)
25210 #define S_SLEEPRDYTBL 11
25211 #define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
25212 #define F_SLEEPRDYTBL V_SLEEPRDYTBL(1U)
25214 #define S_SLEEPRDYMIB 10
25215 #define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
25216 #define F_SLEEPRDYMIB V_SLEEPRDYMIB(1U)
25218 #define S_SLEEPRDYARP 9
25219 #define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
25220 #define F_SLEEPRDYARP V_SLEEPRDYARP(1U)
25222 #define S_SLEEPRDYRSS 8
25223 #define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
25224 #define F_SLEEPRDYRSS V_SLEEPRDYRSS(1U)
25226 #define S_SLEEPREQVNT 4
25227 #define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
25228 #define F_SLEEPREQVNT V_SLEEPREQVNT(1U)
25230 #define S_SLEEPREQTBL 3
25231 #define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
25232 #define F_SLEEPREQTBL V_SLEEPREQTBL(1U)
25234 #define S_SLEEPREQMIB 2
25235 #define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
25236 #define F_SLEEPREQMIB V_SLEEPREQMIB(1U)
25238 #define S_SLEEPREQARP 1
25239 #define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
25240 #define F_SLEEPREQARP V_SLEEPREQARP(1U)
25242 #define S_SLEEPREQRSS 0
25243 #define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
25244 #define F_SLEEPREQRSS V_SLEEPREQRSS(1U)
25246 #define A_TP_CORE_RDMA 0x55
25248 #define S_IMMEDIATEOP 20
25249 #define M_IMMEDIATEOP 0xfU
25250 #define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
25251 #define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
25253 #define S_IMMEDIATESE 16
25254 #define M_IMMEDIATESE 0xfU
25255 #define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
25256 #define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
25258 #define S_ATOMICREQOP 12
25259 #define M_ATOMICREQOP 0xfU
25260 #define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
25261 #define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
25263 #define S_ATOMICRSPOP 8
25264 #define M_ATOMICRSPOP 0xfU
25265 #define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
25266 #define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
25268 #define S_IMMEDIASEEN 1
25269 #define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
25270 #define F_IMMEDIASEEN V_IMMEDIASEEN(1U)
25272 #define S_IMMEDIATEEN 0
25273 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
25274 #define F_IMMEDIATEEN V_IMMEDIATEEN(1U)
25276 #define S_SHAREDRQEN 31
25277 #define V_SHAREDRQEN(x) ((x) << S_SHAREDRQEN)
25278 #define F_SHAREDRQEN V_SHAREDRQEN(1U)
25280 #define S_SHAREDXRC 30
25281 #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
25282 #define F_SHAREDXRC V_SHAREDXRC(1U)
25284 #define A_TP_FRAG_CONFIG 0x56
25286 #define S_TLSMODE 16
25287 #define M_TLSMODE 0x3U
25288 #define V_TLSMODE(x) ((x) << S_TLSMODE)
25289 #define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE)
25291 #define S_USERMODE 14
25292 #define M_USERMODE 0x3U
25293 #define V_USERMODE(x) ((x) << S_USERMODE)
25294 #define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE)
25296 #define S_FCOEMODE 12
25297 #define M_FCOEMODE 0x3U
25298 #define V_FCOEMODE(x) ((x) << S_FCOEMODE)
25299 #define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE)
25301 #define S_IANDPMODE 10
25302 #define M_IANDPMODE 0x3U
25303 #define V_IANDPMODE(x) ((x) << S_IANDPMODE)
25304 #define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE)
25306 #define S_RDDPMODE 8
25307 #define M_RDDPMODE 0x3U
25308 #define V_RDDPMODE(x) ((x) << S_RDDPMODE)
25309 #define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE)
25311 #define S_IWARPMODE 6
25312 #define M_IWARPMODE 0x3U
25313 #define V_IWARPMODE(x) ((x) << S_IWARPMODE)
25314 #define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE)
25316 #define S_ISCSIMODE 4
25317 #define M_ISCSIMODE 0x3U
25318 #define V_ISCSIMODE(x) ((x) << S_ISCSIMODE)
25319 #define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE)
25321 #define S_DDPMODE 2
25322 #define M_DDPMODE 0x3U
25323 #define V_DDPMODE(x) ((x) << S_DDPMODE)
25324 #define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE)
25326 #define S_PASSMODE 0
25327 #define M_PASSMODE 0x3U
25328 #define V_PASSMODE(x) ((x) << S_PASSMODE)
25329 #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
25331 #define A_TP_CMM_CONFIG 0x57
25333 #define S_WRCNTIDLE 16
25334 #define M_WRCNTIDLE 0xffffU
25335 #define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE)
25336 #define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE)
25338 #define S_RDTHRESHOLD 8
25339 #define M_RDTHRESHOLD 0x3fU
25340 #define V_RDTHRESHOLD(x) ((x) << S_RDTHRESHOLD)
25341 #define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD)
25343 #define S_WRTHRLEVEL2 7
25344 #define V_WRTHRLEVEL2(x) ((x) << S_WRTHRLEVEL2)
25345 #define F_WRTHRLEVEL2 V_WRTHRLEVEL2(1U)
25347 #define S_WRTHRLEVEL1 6
25348 #define V_WRTHRLEVEL1(x) ((x) << S_WRTHRLEVEL1)
25349 #define F_WRTHRLEVEL1 V_WRTHRLEVEL1(1U)
25351 #define S_WRTHRTHRESHEN 5
25352 #define V_WRTHRTHRESHEN(x) ((x) << S_WRTHRTHRESHEN)
25353 #define F_WRTHRTHRESHEN V_WRTHRTHRESHEN(1U)
25355 #define S_WRTHRTHRESH 0
25356 #define M_WRTHRTHRESH 0x1fU
25357 #define V_WRTHRTHRESH(x) ((x) << S_WRTHRTHRESH)
25358 #define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH)
25360 #define A_TP_VXLAN_CONFIG 0x58
25362 #define S_VXLANFLAGS 16
25363 #define M_VXLANFLAGS 0xffffU
25364 #define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS)
25365 #define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS)
25367 #define S_VXLANTYPE 0
25368 #define M_VXLANTYPE 0xffffU
25369 #define V_VXLANTYPE(x) ((x) << S_VXLANTYPE)
25370 #define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE)
25372 #define A_TP_NVGRE_CONFIG 0x59
25374 #define S_GREFLAGS 16
25375 #define M_GREFLAGS 0xffffU
25376 #define V_GREFLAGS(x) ((x) << S_GREFLAGS)
25377 #define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS)
25379 #define S_GRETYPE 0
25380 #define M_GRETYPE 0xffffU
25381 #define V_GRETYPE(x) ((x) << S_GRETYPE)
25382 #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
25384 #define A_TP_DBG_CLEAR 0x60
25385 #define A_TP_DBG_CORE_HDR0 0x61
25387 #define S_E_TCP_OP_SRDY 16
25388 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
25389 #define F_E_TCP_OP_SRDY V_E_TCP_OP_SRDY(1U)
25391 #define S_E_PLD_TXZEROP_SRDY 15
25392 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
25393 #define F_E_PLD_TXZEROP_SRDY V_E_PLD_TXZEROP_SRDY(1U)
25395 #define S_E_PLD_RX_SRDY 14
25396 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
25397 #define F_E_PLD_RX_SRDY V_E_PLD_RX_SRDY(1U)
25399 #define S_E_RX_ERROR_SRDY 13
25400 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
25401 #define F_E_RX_ERROR_SRDY V_E_RX_ERROR_SRDY(1U)
25403 #define S_E_RX_ISS_SRDY 12
25404 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
25405 #define F_E_RX_ISS_SRDY V_E_RX_ISS_SRDY(1U)
25407 #define S_C_TCP_OP_SRDY 11
25408 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
25409 #define F_C_TCP_OP_SRDY V_C_TCP_OP_SRDY(1U)
25411 #define S_C_PLD_TXZEROP_SRDY 10
25412 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
25413 #define F_C_PLD_TXZEROP_SRDY V_C_PLD_TXZEROP_SRDY(1U)
25415 #define S_C_PLD_RX_SRDY 9
25416 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
25417 #define F_C_PLD_RX_SRDY V_C_PLD_RX_SRDY(1U)
25419 #define S_C_RX_ERROR_SRDY 8
25420 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
25421 #define F_C_RX_ERROR_SRDY V_C_RX_ERROR_SRDY(1U)
25423 #define S_C_RX_ISS_SRDY 7
25424 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
25425 #define F_C_RX_ISS_SRDY V_C_RX_ISS_SRDY(1U)
25427 #define S_E_CPL5_TXVALID 6
25428 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
25429 #define F_E_CPL5_TXVALID V_E_CPL5_TXVALID(1U)
25431 #define S_E_ETH_TXVALID 5
25432 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
25433 #define F_E_ETH_TXVALID V_E_ETH_TXVALID(1U)
25435 #define S_E_IP_TXVALID 4
25436 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
25437 #define F_E_IP_TXVALID V_E_IP_TXVALID(1U)
25439 #define S_E_TCP_TXVALID 3
25440 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
25441 #define F_E_TCP_TXVALID V_E_TCP_TXVALID(1U)
25443 #define S_C_CPL5_RXVALID 2
25444 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
25445 #define F_C_CPL5_RXVALID V_C_CPL5_RXVALID(1U)
25447 #define S_C_CPL5_TXVALID 1
25448 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
25449 #define F_C_CPL5_TXVALID V_C_CPL5_TXVALID(1U)
25451 #define S_E_TCP_OPT_RXVALID 0
25452 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
25453 #define F_E_TCP_OPT_RXVALID V_E_TCP_OPT_RXVALID(1U)
25455 #define A_TP_DBG_CORE_HDR1 0x62
25457 #define S_E_CPL5_TXFULL 6
25458 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
25459 #define F_E_CPL5_TXFULL V_E_CPL5_TXFULL(1U)
25461 #define S_E_ETH_TXFULL 5
25462 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
25463 #define F_E_ETH_TXFULL V_E_ETH_TXFULL(1U)
25465 #define S_E_IP_TXFULL 4
25466 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
25467 #define F_E_IP_TXFULL V_E_IP_TXFULL(1U)
25469 #define S_E_TCP_TXFULL 3
25470 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
25471 #define F_E_TCP_TXFULL V_E_TCP_TXFULL(1U)
25473 #define S_C_CPL5_RXFULL 2
25474 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
25475 #define F_C_CPL5_RXFULL V_C_CPL5_RXFULL(1U)
25477 #define S_C_CPL5_TXFULL 1
25478 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
25479 #define F_C_CPL5_TXFULL V_C_CPL5_TXFULL(1U)
25481 #define S_E_TCP_OPT_RXFULL 0
25482 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
25483 #define F_E_TCP_OPT_RXFULL V_E_TCP_OPT_RXFULL(1U)
25485 #define A_TP_DBG_CORE_FATAL 0x63
25487 #define S_EMSGFATAL 31
25488 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
25489 #define F_EMSGFATAL V_EMSGFATAL(1U)
25491 #define S_CMSGFATAL 30
25492 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
25493 #define F_CMSGFATAL V_CMSGFATAL(1U)
25495 #define S_PAWSFATAL 29
25496 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
25497 #define F_PAWSFATAL V_PAWSFATAL(1U)
25499 #define S_SRAMFATAL 28
25500 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
25501 #define F_SRAMFATAL V_SRAMFATAL(1U)
25503 #define S_CPCMDCONG 24
25504 #define M_CPCMDCONG 0xfU
25505 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
25506 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
25508 #define S_EPCMDCONG 22
25509 #define M_EPCMDCONG 0x3U
25510 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
25511 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
25513 #define S_CPCMDLENFATAL 21
25514 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
25515 #define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U)
25517 #define S_EPCMDLENFATAL 20
25518 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
25519 #define F_EPCMDLENFATAL V_EPCMDLENFATAL(1U)
25521 #define S_CPCMDVALID 16
25522 #define M_CPCMDVALID 0xfU
25523 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
25524 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
25526 #define S_CPCMDAFULL 12
25527 #define M_CPCMDAFULL 0xfU
25528 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
25529 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
25531 #define S_EPCMDVALID 10
25532 #define M_EPCMDVALID 0x3U
25533 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
25534 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
25536 #define S_EPCMDAFULL 8
25537 #define M_EPCMDAFULL 0x3U
25538 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
25539 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
25541 #define S_CPCMDEOIFATAL 7
25542 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
25543 #define F_CPCMDEOIFATAL V_CPCMDEOIFATAL(1U)
25545 #define S_CMDBRQFATAL 4
25546 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
25547 #define F_CMDBRQFATAL V_CMDBRQFATAL(1U)
25549 #define S_CNONZEROPPOPCNT 2
25550 #define M_CNONZEROPPOPCNT 0x3U
25551 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
25552 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
25554 #define S_CPCMDEOICNT 0
25555 #define M_CPCMDEOICNT 0x3U
25556 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
25557 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
25559 #define S_CPCMDTTLFATAL 6
25560 #define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
25561 #define F_CPCMDTTLFATAL V_CPCMDTTLFATAL(1U)
25563 #define S_CDATACHNFATAL 5
25564 #define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
25565 #define F_CDATACHNFATAL V_CDATACHNFATAL(1U)
25567 #define A_TP_DBG_CORE_OUT 0x64
25569 #define S_CCPLENC 26
25570 #define V_CCPLENC(x) ((x) << S_CCPLENC)
25571 #define F_CCPLENC V_CCPLENC(1U)
25573 #define S_CWRCPLPKT 25
25574 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
25575 #define F_CWRCPLPKT V_CWRCPLPKT(1U)
25577 #define S_CWRETHPKT 24
25578 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
25579 #define F_CWRETHPKT V_CWRETHPKT(1U)
25581 #define S_CWRIPPKT 23
25582 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
25583 #define F_CWRIPPKT V_CWRIPPKT(1U)
25585 #define S_CWRTCPPKT 22
25586 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
25587 #define F_CWRTCPPKT V_CWRTCPPKT(1U)
25589 #define S_CWRZEROP 21
25590 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
25591 #define F_CWRZEROP V_CWRZEROP(1U)
25593 #define S_CCPLTXFULL 20
25594 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
25595 #define F_CCPLTXFULL V_CCPLTXFULL(1U)
25597 #define S_CETHTXFULL 19
25598 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
25599 #define F_CETHTXFULL V_CETHTXFULL(1U)
25601 #define S_CIPTXFULL 18
25602 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
25603 #define F_CIPTXFULL V_CIPTXFULL(1U)
25605 #define S_CTCPTXFULL 17
25606 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
25607 #define F_CTCPTXFULL V_CTCPTXFULL(1U)
25609 #define S_CPLDTXZEROPDRDY 16
25610 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
25611 #define F_CPLDTXZEROPDRDY V_CPLDTXZEROPDRDY(1U)
25613 #define S_ECPLENC 10
25614 #define V_ECPLENC(x) ((x) << S_ECPLENC)
25615 #define F_ECPLENC V_ECPLENC(1U)
25617 #define S_EWRCPLPKT 9
25618 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
25619 #define F_EWRCPLPKT V_EWRCPLPKT(1U)
25621 #define S_EWRETHPKT 8
25622 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
25623 #define F_EWRETHPKT V_EWRETHPKT(1U)
25625 #define S_EWRIPPKT 7
25626 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
25627 #define F_EWRIPPKT V_EWRIPPKT(1U)
25629 #define S_EWRTCPPKT 6
25630 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
25631 #define F_EWRTCPPKT V_EWRTCPPKT(1U)
25633 #define S_EWRZEROP 5
25634 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
25635 #define F_EWRZEROP V_EWRZEROP(1U)
25637 #define S_ECPLTXFULL 4
25638 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
25639 #define F_ECPLTXFULL V_ECPLTXFULL(1U)
25641 #define S_EETHTXFULL 3
25642 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
25643 #define F_EETHTXFULL V_EETHTXFULL(1U)
25645 #define S_EIPTXFULL 2
25646 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
25647 #define F_EIPTXFULL V_EIPTXFULL(1U)
25649 #define S_ETCPTXFULL 1
25650 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
25651 #define F_ETCPTXFULL V_ETCPTXFULL(1U)
25653 #define S_EPLDTXZEROPDRDY 0
25654 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
25655 #define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U)
25657 #define S_CRXBUSYOUT 31
25658 #define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
25659 #define F_CRXBUSYOUT V_CRXBUSYOUT(1U)
25661 #define S_CTXBUSYOUT 30
25662 #define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
25663 #define F_CTXBUSYOUT V_CTXBUSYOUT(1U)
25665 #define S_CRDCPLPKT 29
25666 #define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
25667 #define F_CRDCPLPKT V_CRDCPLPKT(1U)
25669 #define S_CRDTCPPKT 28
25670 #define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
25671 #define F_CRDTCPPKT V_CRDTCPPKT(1U)
25673 #define S_CNEWMSG 27
25674 #define V_CNEWMSG(x) ((x) << S_CNEWMSG)
25675 #define F_CNEWMSG V_CNEWMSG(1U)
25677 #define S_ERXBUSYOUT 15
25678 #define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
25679 #define F_ERXBUSYOUT V_ERXBUSYOUT(1U)
25681 #define S_ETXBUSYOUT 14
25682 #define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
25683 #define F_ETXBUSYOUT V_ETXBUSYOUT(1U)
25685 #define S_ERDCPLPKT 13
25686 #define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
25687 #define F_ERDCPLPKT V_ERDCPLPKT(1U)
25689 #define S_ERDTCPPKT 12
25690 #define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
25691 #define F_ERDTCPPKT V_ERDTCPPKT(1U)
25693 #define S_ENEWMSG 11
25694 #define V_ENEWMSG(x) ((x) << S_ENEWMSG)
25695 #define F_ENEWMSG V_ENEWMSG(1U)
25697 #define A_TP_DBG_CORE_TID 0x65
25699 #define S_LINENUMBER 24
25700 #define M_LINENUMBER 0x7fU
25701 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
25702 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
25704 #define S_SPURIOUSMSG 23
25705 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
25706 #define F_SPURIOUSMSG V_SPURIOUSMSG(1U)
25708 #define S_SYNLEARNED 20
25709 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
25710 #define F_SYNLEARNED V_SYNLEARNED(1U)
25712 #define S_TIDVALUE 0
25713 #define M_TIDVALUE 0xfffffU
25714 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
25715 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
25719 #define V_SRC(x) ((x) << S_SRC)
25720 #define G_SRC(x) (((x) >> S_SRC) & M_SRC)
25722 #define A_TP_DBG_ENG_RES0 0x66
25724 #define S_RESOURCESREADY 31
25725 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
25726 #define F_RESOURCESREADY V_RESOURCESREADY(1U)
25728 #define S_RCFOPCODEOUTSRDY 30
25729 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
25730 #define F_RCFOPCODEOUTSRDY V_RCFOPCODEOUTSRDY(1U)
25732 #define S_RCFDATAOUTSRDY 29
25733 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
25734 #define F_RCFDATAOUTSRDY V_RCFDATAOUTSRDY(1U)
25736 #define S_FLUSHINPUTMSG 28
25737 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
25738 #define F_FLUSHINPUTMSG V_FLUSHINPUTMSG(1U)
25740 #define S_RCFOPSRCOUT 26
25741 #define M_RCFOPSRCOUT 0x3U
25742 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
25743 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
25746 #define V_C_MSG(x) ((x) << S_C_MSG)
25747 #define F_C_MSG V_C_MSG(1U)
25750 #define V_E_MSG(x) ((x) << S_E_MSG)
25751 #define F_E_MSG V_E_MSG(1U)
25753 #define S_RCFOPCODEOUT 20
25754 #define M_RCFOPCODEOUT 0xfU
25755 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
25756 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
25758 #define S_EFFRCFOPCODEOUT 16
25759 #define M_EFFRCFOPCODEOUT 0xfU
25760 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
25761 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
25763 #define S_SEENRESOURCESREADY 15
25764 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
25765 #define F_SEENRESOURCESREADY V_SEENRESOURCESREADY(1U)
25767 #define S_RESOURCESREADYCOPY 14
25768 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
25769 #define F_RESOURCESREADYCOPY V_RESOURCESREADYCOPY(1U)
25771 #define S_OPCODEWAITSFORDATA 13
25772 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
25773 #define F_OPCODEWAITSFORDATA V_OPCODEWAITSFORDATA(1U)
25775 #define S_CPLDRXSRDY 12
25776 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
25777 #define F_CPLDRXSRDY V_CPLDRXSRDY(1U)
25779 #define S_CPLDRXZEROPSRDY 11
25780 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
25781 #define F_CPLDRXZEROPSRDY V_CPLDRXZEROPSRDY(1U)
25783 #define S_EPLDRXZEROPSRDY 10
25784 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
25785 #define F_EPLDRXZEROPSRDY V_EPLDRXZEROPSRDY(1U)
25787 #define S_ERXERRORSRDY 9
25788 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
25789 #define F_ERXERRORSRDY V_ERXERRORSRDY(1U)
25791 #define S_EPLDRXSRDY 8
25792 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
25793 #define F_EPLDRXSRDY V_EPLDRXSRDY(1U)
25795 #define S_CRXBUSY 7
25796 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
25797 #define F_CRXBUSY V_CRXBUSY(1U)
25799 #define S_ERXBUSY 6
25800 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
25801 #define F_ERXBUSY V_ERXBUSY(1U)
25803 #define S_TIMERINSERTBUSY 5
25804 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
25805 #define F_TIMERINSERTBUSY V_TIMERINSERTBUSY(1U)
25807 #define S_WCFBUSY 4
25808 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
25809 #define F_WCFBUSY V_WCFBUSY(1U)
25811 #define S_CTXBUSY 3
25812 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
25813 #define F_CTXBUSY V_CTXBUSY(1U)
25815 #define S_CPCMDBUSY 2
25816 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
25817 #define F_CPCMDBUSY V_CPCMDBUSY(1U)
25819 #define S_EPCMDBUSY 1
25820 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
25821 #define F_EPCMDBUSY V_EPCMDBUSY(1U)
25823 #define S_ETXBUSY 0
25824 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
25825 #define F_ETXBUSY V_ETXBUSY(1U)
25827 #define S_EFFOPCODEOUT 16
25828 #define M_EFFOPCODEOUT 0xfU
25829 #define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
25830 #define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
25832 #define S_DELDRDY 14
25833 #define V_DELDRDY(x) ((x) << S_DELDRDY)
25834 #define F_DELDRDY V_DELDRDY(1U)
25836 #define S_T5_ETXBUSY 1
25837 #define V_T5_ETXBUSY(x) ((x) << S_T5_ETXBUSY)
25838 #define F_T5_ETXBUSY V_T5_ETXBUSY(1U)
25840 #define S_T5_EPCMDBUSY 0
25841 #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
25842 #define F_T5_EPCMDBUSY V_T5_EPCMDBUSY(1U)
25844 #define S_T6_ETXBUSY 1
25845 #define V_T6_ETXBUSY(x) ((x) << S_T6_ETXBUSY)
25846 #define F_T6_ETXBUSY V_T6_ETXBUSY(1U)
25848 #define S_T6_EPCMDBUSY 0
25849 #define V_T6_EPCMDBUSY(x) ((x) << S_T6_EPCMDBUSY)
25850 #define F_T6_EPCMDBUSY V_T6_EPCMDBUSY(1U)
25852 #define A_TP_DBG_ENG_RES1 0x67
25854 #define S_RXCPLSRDY 31
25855 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
25856 #define F_RXCPLSRDY V_RXCPLSRDY(1U)
25858 #define S_RXOPTSRDY 30
25859 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
25860 #define F_RXOPTSRDY V_RXOPTSRDY(1U)
25862 #define S_RXPLDLENSRDY 29
25863 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
25864 #define F_RXPLDLENSRDY V_RXPLDLENSRDY(1U)
25866 #define S_RXNOTBUSY 28
25867 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
25868 #define F_RXNOTBUSY V_RXNOTBUSY(1U)
25870 #define S_CPLCMDIN 20
25871 #define M_CPLCMDIN 0xffU
25872 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
25873 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
25875 #define S_RCFPTIDSRDY 19
25876 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
25877 #define F_RCFPTIDSRDY V_RCFPTIDSRDY(1U)
25879 #define S_EPDUHDRSRDY 18
25880 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
25881 #define F_EPDUHDRSRDY V_EPDUHDRSRDY(1U)
25883 #define S_TUNNELPKTREG 17
25884 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
25885 #define F_TUNNELPKTREG V_TUNNELPKTREG(1U)
25887 #define S_TXPKTCSUMSRDY 16
25888 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
25889 #define F_TXPKTCSUMSRDY V_TXPKTCSUMSRDY(1U)
25891 #define S_TABLEACCESSLATENCY 12
25892 #define M_TABLEACCESSLATENCY 0xfU
25893 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
25894 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
25896 #define S_MMGRDONE 11
25897 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
25898 #define F_MMGRDONE V_MMGRDONE(1U)
25900 #define S_SEENMMGRDONE 10
25901 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
25902 #define F_SEENMMGRDONE V_SEENMMGRDONE(1U)
25904 #define S_RXERRORSRDY 9
25905 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
25906 #define F_RXERRORSRDY V_RXERRORSRDY(1U)
25908 #define S_RCFOPTIONSTCPSRDY 8
25909 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
25910 #define F_RCFOPTIONSTCPSRDY V_RCFOPTIONSTCPSRDY(1U)
25912 #define S_ENGINESTATE 6
25913 #define M_ENGINESTATE 0x3U
25914 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
25915 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
25917 #define S_TABLEACCESINCREMENT 5
25918 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
25919 #define F_TABLEACCESINCREMENT V_TABLEACCESINCREMENT(1U)
25921 #define S_TABLEACCESCOMPLETE 4
25922 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
25923 #define F_TABLEACCESCOMPLETE V_TABLEACCESCOMPLETE(1U)
25925 #define S_RCFOPCODEOUTUSABLE 3
25926 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
25927 #define F_RCFOPCODEOUTUSABLE V_RCFOPCODEOUTUSABLE(1U)
25929 #define S_RCFDATAOUTUSABLE 2
25930 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
25931 #define F_RCFDATAOUTUSABLE V_RCFDATAOUTUSABLE(1U)
25933 #define S_RCFDATAWAITAFTERRD 1
25934 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
25935 #define F_RCFDATAWAITAFTERRD V_RCFDATAWAITAFTERRD(1U)
25937 #define S_RCFDATACMRDY 0
25938 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
25939 #define F_RCFDATACMRDY V_RCFDATACMRDY(1U)
25941 #define S_RXISSSRDY 28
25942 #define V_RXISSSRDY(x) ((x) << S_RXISSSRDY)
25943 #define F_RXISSSRDY V_RXISSSRDY(1U)
25945 #define A_TP_DBG_ENG_RES2 0x68
25947 #define S_CPLCMDRAW 24
25948 #define M_CPLCMDRAW 0xffU
25949 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
25950 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
25952 #define S_RXMACPORT 20
25953 #define M_RXMACPORT 0xfU
25954 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
25955 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
25957 #define S_TXECHANNEL 18
25958 #define M_TXECHANNEL 0x3U
25959 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
25960 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
25962 #define S_RXECHANNEL 16
25963 #define M_RXECHANNEL 0x3U
25964 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
25965 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
25967 #define S_CDATAOUT 15
25968 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
25969 #define F_CDATAOUT V_CDATAOUT(1U)
25971 #define S_CREADPDU 14
25972 #define V_CREADPDU(x) ((x) << S_CREADPDU)
25973 #define F_CREADPDU V_CREADPDU(1U)
25975 #define S_EDATAOUT 13
25976 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
25977 #define F_EDATAOUT V_EDATAOUT(1U)
25979 #define S_EREADPDU 12
25980 #define V_EREADPDU(x) ((x) << S_EREADPDU)
25981 #define F_EREADPDU V_EREADPDU(1U)
25983 #define S_ETCPOPSRDY 11
25984 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
25985 #define F_ETCPOPSRDY V_ETCPOPSRDY(1U)
25987 #define S_CTCPOPSRDY 10
25988 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
25989 #define F_CTCPOPSRDY V_CTCPOPSRDY(1U)
25991 #define S_CPKTOUT 9
25992 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
25993 #define F_CPKTOUT V_CPKTOUT(1U)
25995 #define S_CMDBRSPSRDY 8
25996 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
25997 #define F_CMDBRSPSRDY V_CMDBRSPSRDY(1U)
25999 #define S_RXPSTRUCTSFULL 6
26000 #define M_RXPSTRUCTSFULL 0x3U
26001 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
26002 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
26004 #define S_RXPAGEPOOLFULL 4
26005 #define M_RXPAGEPOOLFULL 0x3U
26006 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
26007 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
26009 #define S_RCFREASONOUT 0
26010 #define M_RCFREASONOUT 0xfU
26011 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
26012 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
26014 #define A_TP_DBG_CORE_PCMD 0x69
26016 #define S_CPCMDEOPCNT 30
26017 #define M_CPCMDEOPCNT 0x3U
26018 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
26019 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
26021 #define S_CPCMDLENSAVE 16
26022 #define M_CPCMDLENSAVE 0x3fffU
26023 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
26024 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
26026 #define S_EPCMDEOPCNT 14
26027 #define M_EPCMDEOPCNT 0x3U
26028 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
26029 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
26031 #define S_EPCMDLENSAVE 0
26032 #define M_EPCMDLENSAVE 0x3fffU
26033 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
26034 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
26036 #define A_TP_DBG_SCHED_TX 0x6a
26038 #define S_TXCHNXOFF 28
26039 #define M_TXCHNXOFF 0xfU
26040 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
26041 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
26043 #define S_TXFIFOCNG 24
26044 #define M_TXFIFOCNG 0xfU
26045 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
26046 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
26048 #define S_TXPCMDCNG 20
26049 #define M_TXPCMDCNG 0xfU
26050 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
26051 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
26053 #define S_TXLPBKCNG 16
26054 #define M_TXLPBKCNG 0xfU
26055 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
26056 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
26058 #define S_TXHDRCNG 8
26059 #define M_TXHDRCNG 0xffU
26060 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
26061 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
26063 #define S_TXMODXOFF 0
26064 #define M_TXMODXOFF 0xffU
26065 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
26066 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
26068 #define A_TP_DBG_SCHED_RX 0x6b
26070 #define S_RXCHNXOFF 28
26071 #define M_RXCHNXOFF 0xfU
26072 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
26073 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
26075 #define S_RXSGECNG 24
26076 #define M_RXSGECNG 0xfU
26077 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
26078 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
26080 #define S_RXFIFOCNG 22
26081 #define M_RXFIFOCNG 0x3U
26082 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
26083 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
26085 #define S_RXPCMDCNG 20
26086 #define M_RXPCMDCNG 0x3U
26087 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
26088 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
26090 #define S_RXLPBKCNG 16
26091 #define M_RXLPBKCNG 0xfU
26092 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
26093 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
26095 #define S_RXHDRCNG 8
26096 #define M_RXHDRCNG 0xfU
26097 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
26098 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
26100 #define S_RXMODXOFF 0
26101 #define M_RXMODXOFF 0x3U
26102 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
26103 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
26105 #define S_T5_RXFIFOCNG 20
26106 #define M_T5_RXFIFOCNG 0xfU
26107 #define V_T5_RXFIFOCNG(x) ((x) << S_T5_RXFIFOCNG)
26108 #define G_T5_RXFIFOCNG(x) (((x) >> S_T5_RXFIFOCNG) & M_T5_RXFIFOCNG)
26110 #define S_T5_RXPCMDCNG 14
26111 #define M_T5_RXPCMDCNG 0x3U
26112 #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
26113 #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
26115 #define S_T6_RXFIFOCNG 20
26116 #define M_T6_RXFIFOCNG 0xfU
26117 #define V_T6_RXFIFOCNG(x) ((x) << S_T6_RXFIFOCNG)
26118 #define G_T6_RXFIFOCNG(x) (((x) >> S_T6_RXFIFOCNG) & M_T6_RXFIFOCNG)
26120 #define S_T6_RXPCMDCNG 14
26121 #define M_T6_RXPCMDCNG 0x3U
26122 #define V_T6_RXPCMDCNG(x) ((x) << S_T6_RXPCMDCNG)
26123 #define G_T6_RXPCMDCNG(x) (((x) >> S_T6_RXPCMDCNG) & M_T6_RXPCMDCNG)
26125 #define A_TP_DBG_ERROR_CNT 0x6c
26126 #define A_TP_DBG_CORE_CPL 0x6d
26128 #define S_CPLCMDOUT3 24
26129 #define M_CPLCMDOUT3 0xffU
26130 #define V_CPLCMDOUT3(x) ((x) << S_CPLCMDOUT3)
26131 #define G_CPLCMDOUT3(x) (((x) >> S_CPLCMDOUT3) & M_CPLCMDOUT3)
26133 #define S_CPLCMDOUT2 16
26134 #define M_CPLCMDOUT2 0xffU
26135 #define V_CPLCMDOUT2(x) ((x) << S_CPLCMDOUT2)
26136 #define G_CPLCMDOUT2(x) (((x) >> S_CPLCMDOUT2) & M_CPLCMDOUT2)
26138 #define S_CPLCMDOUT1 8
26139 #define M_CPLCMDOUT1 0xffU
26140 #define V_CPLCMDOUT1(x) ((x) << S_CPLCMDOUT1)
26141 #define G_CPLCMDOUT1(x) (((x) >> S_CPLCMDOUT1) & M_CPLCMDOUT1)
26143 #define S_CPLCMDOUT0 0
26144 #define M_CPLCMDOUT0 0xffU
26145 #define V_CPLCMDOUT0(x) ((x) << S_CPLCMDOUT0)
26146 #define G_CPLCMDOUT0(x) (((x) >> S_CPLCMDOUT0) & M_CPLCMDOUT0)
26148 #define A_TP_MIB_DEBUG 0x6f
26151 #define V_SRC3(x) ((x) << S_SRC3)
26152 #define F_SRC3 V_SRC3(1U)
26154 #define S_LINENUM3 24
26155 #define M_LINENUM3 0x7fU
26156 #define V_LINENUM3(x) ((x) << S_LINENUM3)
26157 #define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
26160 #define V_SRC2(x) ((x) << S_SRC2)
26161 #define F_SRC2 V_SRC2(1U)
26163 #define S_LINENUM2 16
26164 #define M_LINENUM2 0x7fU
26165 #define V_LINENUM2(x) ((x) << S_LINENUM2)
26166 #define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
26169 #define V_SRC1(x) ((x) << S_SRC1)
26170 #define F_SRC1 V_SRC1(1U)
26172 #define S_LINENUM1 8
26173 #define M_LINENUM1 0x7fU
26174 #define V_LINENUM1(x) ((x) << S_LINENUM1)
26175 #define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
26178 #define V_SRC0(x) ((x) << S_SRC0)
26179 #define F_SRC0 V_SRC0(1U)
26181 #define S_LINENUM0 0
26182 #define M_LINENUM0 0x7fU
26183 #define V_LINENUM0(x) ((x) << S_LINENUM0)
26184 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
26186 #define A_TP_DBG_CACHE_WR_ALL 0x70
26187 #define A_TP_DBG_CACHE_WR_HIT 0x71
26188 #define A_TP_DBG_CACHE_RD_ALL 0x72
26189 #define A_TP_DBG_CACHE_RD_HIT 0x73
26190 #define A_TP_DBG_CACHE_MC_REQ 0x74
26191 #define A_TP_DBG_CACHE_MC_RSP 0x75
26192 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
26193 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
26194 #define A_TP_TX_DROP_CNT_CH2 0x122
26195 #define A_TP_TX_DROP_CNT_CH3 0x123
26196 #define A_TP_TX_DROP_CFG_CH0 0x12b
26198 #define S_TIMERENABLED 31
26199 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
26200 #define F_TIMERENABLED V_TIMERENABLED(1U)
26202 #define S_TIMERERRORENABLE 30
26203 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
26204 #define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U)
26206 #define S_TIMERTHRESHOLD 4
26207 #define M_TIMERTHRESHOLD 0x3ffffffU
26208 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
26209 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
26211 #define S_PACKETDROPS 0
26212 #define M_PACKETDROPS 0xfU
26213 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
26214 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
26216 #define A_TP_TX_DROP_CFG_CH1 0x12c
26217 #define A_TP_TX_DROP_CNT_CH0 0x12d
26219 #define S_TXDROPCNTCH0SENT 16
26220 #define M_TXDROPCNTCH0SENT 0xffffU
26221 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
26222 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
26224 #define S_TXDROPCNTCH0RCVD 0
26225 #define M_TXDROPCNTCH0RCVD 0xffffU
26226 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
26227 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
26229 #define A_TP_TX_DROP_CNT_CH1 0x12e
26231 #define S_TXDROPCNTCH1SENT 16
26232 #define M_TXDROPCNTCH1SENT 0xffffU
26233 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
26234 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
26236 #define S_TXDROPCNTCH1RCVD 0
26237 #define M_TXDROPCNTCH1RCVD 0xffffU
26238 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
26239 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
26241 #define A_TP_TX_DROP_MODE 0x12f
26243 #define S_TXDROPMODECH3 3
26244 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
26245 #define F_TXDROPMODECH3 V_TXDROPMODECH3(1U)
26247 #define S_TXDROPMODECH2 2
26248 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
26249 #define F_TXDROPMODECH2 V_TXDROPMODECH2(1U)
26251 #define S_TXDROPMODECH1 1
26252 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
26253 #define F_TXDROPMODECH1 V_TXDROPMODECH1(1U)
26255 #define S_TXDROPMODECH0 0
26256 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
26257 #define F_TXDROPMODECH0 V_TXDROPMODECH0(1U)
26259 #define A_TP_DBG_ESIDE_PKT0 0x130
26261 #define S_ETXSOPCNT 28
26262 #define M_ETXSOPCNT 0xfU
26263 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
26264 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
26266 #define S_ETXEOPCNT 24
26267 #define M_ETXEOPCNT 0xfU
26268 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
26269 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
26271 #define S_ETXPLDSOPCNT 20
26272 #define M_ETXPLDSOPCNT 0xfU
26273 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
26274 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
26276 #define S_ETXPLDEOPCNT 16
26277 #define M_ETXPLDEOPCNT 0xfU
26278 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
26279 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
26281 #define S_ERXSOPCNT 12
26282 #define M_ERXSOPCNT 0xfU
26283 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
26284 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
26286 #define S_ERXEOPCNT 8
26287 #define M_ERXEOPCNT 0xfU
26288 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
26289 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
26291 #define S_ERXPLDSOPCNT 4
26292 #define M_ERXPLDSOPCNT 0xfU
26293 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
26294 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
26296 #define S_ERXPLDEOPCNT 0
26297 #define M_ERXPLDEOPCNT 0xfU
26298 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
26299 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
26301 #define A_TP_DBG_ESIDE_PKT1 0x131
26302 #define A_TP_DBG_ESIDE_PKT2 0x132
26303 #define A_TP_DBG_ESIDE_PKT3 0x133
26304 #define A_TP_DBG_ESIDE_FIFO0 0x134
26306 #define S_PLDRXCSUMVALID1 31
26307 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
26308 #define F_PLDRXCSUMVALID1 V_PLDRXCSUMVALID1(1U)
26310 #define S_PLDRXZEROPSRDY1 30
26311 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
26312 #define F_PLDRXZEROPSRDY1 V_PLDRXZEROPSRDY1(1U)
26314 #define S_PLDRXVALID1 29
26315 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
26316 #define F_PLDRXVALID1 V_PLDRXVALID1(1U)
26318 #define S_TCPRXVALID1 28
26319 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
26320 #define F_TCPRXVALID1 V_TCPRXVALID1(1U)
26322 #define S_IPRXVALID1 27
26323 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
26324 #define F_IPRXVALID1 V_IPRXVALID1(1U)
26326 #define S_ETHRXVALID1 26
26327 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
26328 #define F_ETHRXVALID1 V_ETHRXVALID1(1U)
26330 #define S_CPLRXVALID1 25
26331 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
26332 #define F_CPLRXVALID1 V_CPLRXVALID1(1U)
26334 #define S_FSTATIC1 24
26335 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
26336 #define F_FSTATIC1 V_FSTATIC1(1U)
26338 #define S_ERRORSRDY1 23
26339 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
26340 #define F_ERRORSRDY1 V_ERRORSRDY1(1U)
26342 #define S_PLDTXSRDY1 22
26343 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
26344 #define F_PLDTXSRDY1 V_PLDTXSRDY1(1U)
26346 #define S_DBVLD1 21
26347 #define V_DBVLD1(x) ((x) << S_DBVLD1)
26348 #define F_DBVLD1 V_DBVLD1(1U)
26350 #define S_PLDTXVALID1 20
26351 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
26352 #define F_PLDTXVALID1 V_PLDTXVALID1(1U)
26354 #define S_ETXVALID1 19
26355 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
26356 #define F_ETXVALID1 V_ETXVALID1(1U)
26358 #define S_ETXFULL1 18
26359 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
26360 #define F_ETXFULL1 V_ETXFULL1(1U)
26362 #define S_ERXVALID1 17
26363 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
26364 #define F_ERXVALID1 V_ERXVALID1(1U)
26366 #define S_ERXFULL1 16
26367 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
26368 #define F_ERXFULL1 V_ERXFULL1(1U)
26370 #define S_PLDRXCSUMVALID0 15
26371 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
26372 #define F_PLDRXCSUMVALID0 V_PLDRXCSUMVALID0(1U)
26374 #define S_PLDRXZEROPSRDY0 14
26375 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
26376 #define F_PLDRXZEROPSRDY0 V_PLDRXZEROPSRDY0(1U)
26378 #define S_PLDRXVALID0 13
26379 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
26380 #define F_PLDRXVALID0 V_PLDRXVALID0(1U)
26382 #define S_TCPRXVALID0 12
26383 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
26384 #define F_TCPRXVALID0 V_TCPRXVALID0(1U)
26386 #define S_IPRXVALID0 11
26387 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
26388 #define F_IPRXVALID0 V_IPRXVALID0(1U)
26390 #define S_ETHRXVALID0 10
26391 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
26392 #define F_ETHRXVALID0 V_ETHRXVALID0(1U)
26394 #define S_CPLRXVALID0 9
26395 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
26396 #define F_CPLRXVALID0 V_CPLRXVALID0(1U)
26398 #define S_FSTATIC0 8
26399 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
26400 #define F_FSTATIC0 V_FSTATIC0(1U)
26402 #define S_ERRORSRDY0 7
26403 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
26404 #define F_ERRORSRDY0 V_ERRORSRDY0(1U)
26406 #define S_PLDTXSRDY0 6
26407 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
26408 #define F_PLDTXSRDY0 V_PLDTXSRDY0(1U)
26411 #define V_DBVLD0(x) ((x) << S_DBVLD0)
26412 #define F_DBVLD0 V_DBVLD0(1U)
26414 #define S_PLDTXVALID0 4
26415 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
26416 #define F_PLDTXVALID0 V_PLDTXVALID0(1U)
26418 #define S_ETXVALID0 3
26419 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
26420 #define F_ETXVALID0 V_ETXVALID0(1U)
26422 #define S_ETXFULL0 2
26423 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
26424 #define F_ETXFULL0 V_ETXFULL0(1U)
26426 #define S_ERXVALID0 1
26427 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
26428 #define F_ERXVALID0 V_ERXVALID0(1U)
26430 #define S_ERXFULL0 0
26431 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
26432 #define F_ERXFULL0 V_ERXFULL0(1U)
26434 #define A_TP_DBG_ESIDE_FIFO1 0x135
26436 #define S_PLDRXCSUMVALID3 31
26437 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
26438 #define F_PLDRXCSUMVALID3 V_PLDRXCSUMVALID3(1U)
26440 #define S_PLDRXZEROPSRDY3 30
26441 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
26442 #define F_PLDRXZEROPSRDY3 V_PLDRXZEROPSRDY3(1U)
26444 #define S_PLDRXVALID3 29
26445 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
26446 #define F_PLDRXVALID3 V_PLDRXVALID3(1U)
26448 #define S_TCPRXVALID3 28
26449 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
26450 #define F_TCPRXVALID3 V_TCPRXVALID3(1U)
26452 #define S_IPRXVALID3 27
26453 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
26454 #define F_IPRXVALID3 V_IPRXVALID3(1U)
26456 #define S_ETHRXVALID3 26
26457 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
26458 #define F_ETHRXVALID3 V_ETHRXVALID3(1U)
26460 #define S_CPLRXVALID3 25
26461 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
26462 #define F_CPLRXVALID3 V_CPLRXVALID3(1U)
26464 #define S_FSTATIC3 24
26465 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
26466 #define F_FSTATIC3 V_FSTATIC3(1U)
26468 #define S_ERRORSRDY3 23
26469 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
26470 #define F_ERRORSRDY3 V_ERRORSRDY3(1U)
26472 #define S_PLDTXSRDY3 22
26473 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
26474 #define F_PLDTXSRDY3 V_PLDTXSRDY3(1U)
26476 #define S_DBVLD3 21
26477 #define V_DBVLD3(x) ((x) << S_DBVLD3)
26478 #define F_DBVLD3 V_DBVLD3(1U)
26480 #define S_PLDTXVALID3 20
26481 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
26482 #define F_PLDTXVALID3 V_PLDTXVALID3(1U)
26484 #define S_ETXVALID3 19
26485 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
26486 #define F_ETXVALID3 V_ETXVALID3(1U)
26488 #define S_ETXFULL3 18
26489 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
26490 #define F_ETXFULL3 V_ETXFULL3(1U)
26492 #define S_ERXVALID3 17
26493 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
26494 #define F_ERXVALID3 V_ERXVALID3(1U)
26496 #define S_ERXFULL3 16
26497 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
26498 #define F_ERXFULL3 V_ERXFULL3(1U)
26500 #define S_PLDRXCSUMVALID2 15
26501 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
26502 #define F_PLDRXCSUMVALID2 V_PLDRXCSUMVALID2(1U)
26504 #define S_PLDRXZEROPSRDY2 14
26505 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
26506 #define F_PLDRXZEROPSRDY2 V_PLDRXZEROPSRDY2(1U)
26508 #define S_PLDRXVALID2 13
26509 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
26510 #define F_PLDRXVALID2 V_PLDRXVALID2(1U)
26512 #define S_TCPRXVALID2 12
26513 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
26514 #define F_TCPRXVALID2 V_TCPRXVALID2(1U)
26516 #define S_IPRXVALID2 11
26517 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
26518 #define F_IPRXVALID2 V_IPRXVALID2(1U)
26520 #define S_ETHRXVALID2 10
26521 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
26522 #define F_ETHRXVALID2 V_ETHRXVALID2(1U)
26524 #define S_CPLRXVALID2 9
26525 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
26526 #define F_CPLRXVALID2 V_CPLRXVALID2(1U)
26528 #define S_FSTATIC2 8
26529 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
26530 #define F_FSTATIC2 V_FSTATIC2(1U)
26532 #define S_ERRORSRDY2 7
26533 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
26534 #define F_ERRORSRDY2 V_ERRORSRDY2(1U)
26536 #define S_PLDTXSRDY2 6
26537 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
26538 #define F_PLDTXSRDY2 V_PLDTXSRDY2(1U)
26541 #define V_DBVLD2(x) ((x) << S_DBVLD2)
26542 #define F_DBVLD2 V_DBVLD2(1U)
26544 #define S_PLDTXVALID2 4
26545 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
26546 #define F_PLDTXVALID2 V_PLDTXVALID2(1U)
26548 #define S_ETXVALID2 3
26549 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
26550 #define F_ETXVALID2 V_ETXVALID2(1U)
26552 #define S_ETXFULL2 2
26553 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
26554 #define F_ETXFULL2 V_ETXFULL2(1U)
26556 #define S_ERXVALID2 1
26557 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
26558 #define F_ERXVALID2 V_ERXVALID2(1U)
26560 #define S_ERXFULL2 0
26561 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
26562 #define F_ERXFULL2 V_ERXFULL2(1U)
26564 #define A_TP_DBG_ESIDE_DISP0 0x136
26566 #define S_RESRDY 31
26567 #define V_RESRDY(x) ((x) << S_RESRDY)
26568 #define F_RESRDY V_RESRDY(1U)
26571 #define M_STATE 0x7U
26572 #define V_STATE(x) ((x) << S_STATE)
26573 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
26575 #define S_FIFOCPL5RXVALID 27
26576 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
26577 #define F_FIFOCPL5RXVALID V_FIFOCPL5RXVALID(1U)
26579 #define S_FIFOETHRXVALID 26
26580 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
26581 #define F_FIFOETHRXVALID V_FIFOETHRXVALID(1U)
26583 #define S_FIFOETHRXSOCP 25
26584 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
26585 #define F_FIFOETHRXSOCP V_FIFOETHRXSOCP(1U)
26587 #define S_FIFOPLDRXZEROP 24
26588 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
26589 #define F_FIFOPLDRXZEROP V_FIFOPLDRXZEROP(1U)
26591 #define S_PLDRXVALID 23
26592 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
26593 #define F_PLDRXVALID V_PLDRXVALID(1U)
26595 #define S_FIFOPLDRXZEROP_SRDY 22
26596 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
26597 #define F_FIFOPLDRXZEROP_SRDY V_FIFOPLDRXZEROP_SRDY(1U)
26599 #define S_FIFOIPRXVALID 21
26600 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
26601 #define F_FIFOIPRXVALID V_FIFOIPRXVALID(1U)
26603 #define S_FIFOTCPRXVALID 20
26604 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
26605 #define F_FIFOTCPRXVALID V_FIFOTCPRXVALID(1U)
26607 #define S_PLDRXCSUMVALID 19
26608 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
26609 #define F_PLDRXCSUMVALID V_PLDRXCSUMVALID(1U)
26611 #define S_FIFOIPCSUMSRDY 18
26612 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
26613 #define F_FIFOIPCSUMSRDY V_FIFOIPCSUMSRDY(1U)
26615 #define S_FIFOIPPSEUDOCSUMSRDY 17
26616 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
26617 #define F_FIFOIPPSEUDOCSUMSRDY V_FIFOIPPSEUDOCSUMSRDY(1U)
26619 #define S_FIFOTCPCSUMSRDY 16
26620 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
26621 #define F_FIFOTCPCSUMSRDY V_FIFOTCPCSUMSRDY(1U)
26623 #define S_ESTATIC4 12
26624 #define M_ESTATIC4 0xfU
26625 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
26626 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
26628 #define S_FIFOCPLSOCPCNT 10
26629 #define M_FIFOCPLSOCPCNT 0x3U
26630 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
26631 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
26633 #define S_FIFOETHSOCPCNT 8
26634 #define M_FIFOETHSOCPCNT 0x3U
26635 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
26636 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
26638 #define S_FIFOIPSOCPCNT 6
26639 #define M_FIFOIPSOCPCNT 0x3U
26640 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
26641 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
26643 #define S_FIFOTCPSOCPCNT 4
26644 #define M_FIFOTCPSOCPCNT 0x3U
26645 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
26646 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
26648 #define S_PLD_RXZEROP_CNT 2
26649 #define M_PLD_RXZEROP_CNT 0x3U
26650 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
26651 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
26653 #define S_ESTATIC6 1
26654 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
26655 #define F_ESTATIC6 V_ESTATIC6(1U)
26658 #define V_TXFULL(x) ((x) << S_TXFULL)
26659 #define F_TXFULL V_TXFULL(1U)
26661 #define S_FIFOGRERXVALID 15
26662 #define V_FIFOGRERXVALID(x) ((x) << S_FIFOGRERXVALID)
26663 #define F_FIFOGRERXVALID V_FIFOGRERXVALID(1U)
26665 #define S_FIFOGRERXREADY 14
26666 #define V_FIFOGRERXREADY(x) ((x) << S_FIFOGRERXREADY)
26667 #define F_FIFOGRERXREADY V_FIFOGRERXREADY(1U)
26669 #define S_FIFOGRERXSOCP 13
26670 #define V_FIFOGRERXSOCP(x) ((x) << S_FIFOGRERXSOCP)
26671 #define F_FIFOGRERXSOCP V_FIFOGRERXSOCP(1U)
26673 #define S_T6_ESTATIC4 12
26674 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26675 #define F_T6_ESTATIC4 V_T6_ESTATIC4(1U)
26677 #define S_TXFULL_ESIDE0 0
26678 #define V_TXFULL_ESIDE0(x) ((x) << S_TXFULL_ESIDE0)
26679 #define F_TXFULL_ESIDE0 V_TXFULL_ESIDE0(1U)
26681 #define A_TP_DBG_ESIDE_DISP1 0x137
26683 #define S_T6_ESTATIC4 12
26684 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26685 #define F_T6_ESTATIC4 V_T6_ESTATIC4(1U)
26687 #define S_TXFULL_ESIDE1 0
26688 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
26689 #define F_TXFULL_ESIDE1 V_TXFULL_ESIDE1(1U)
26691 #define A_TP_MAC_MATCH_MAP0 0x138
26693 #define S_MAPVALUEWR 16
26694 #define M_MAPVALUEWR 0xffU
26695 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
26696 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
26698 #define S_MAPINDEX 2
26699 #define M_MAPINDEX 0x1ffU
26700 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
26701 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
26703 #define S_MAPREAD 1
26704 #define V_MAPREAD(x) ((x) << S_MAPREAD)
26705 #define F_MAPREAD V_MAPREAD(1U)
26707 #define S_MAPWRITE 0
26708 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
26709 #define F_MAPWRITE V_MAPWRITE(1U)
26711 #define A_TP_MAC_MATCH_MAP1 0x139
26713 #define S_MAPVALUERD 0
26714 #define M_MAPVALUERD 0x1ffU
26715 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
26716 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
26718 #define A_TP_DBG_ESIDE_DISP2 0x13a
26720 #define S_T6_ESTATIC4 12
26721 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26722 #define F_T6_ESTATIC4 V_T6_ESTATIC4(1U)
26724 #define S_TXFULL_ESIDE2 0
26725 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
26726 #define F_TXFULL_ESIDE2 V_TXFULL_ESIDE2(1U)
26728 #define A_TP_DBG_ESIDE_DISP3 0x13b
26730 #define S_T6_ESTATIC4 12
26731 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26732 #define F_T6_ESTATIC4 V_T6_ESTATIC4(1U)
26734 #define S_TXFULL_ESIDE3 0
26735 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
26736 #define F_TXFULL_ESIDE3 V_TXFULL_ESIDE3(1U)
26738 #define A_TP_DBG_ESIDE_HDR0 0x13c
26740 #define S_TCPSOPCNT 28
26741 #define M_TCPSOPCNT 0xfU
26742 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
26743 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
26745 #define S_TCPEOPCNT 24
26746 #define M_TCPEOPCNT 0xfU
26747 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
26748 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
26750 #define S_IPSOPCNT 20
26751 #define M_IPSOPCNT 0xfU
26752 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
26753 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
26755 #define S_IPEOPCNT 16
26756 #define M_IPEOPCNT 0xfU
26757 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
26758 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
26760 #define S_ETHSOPCNT 12
26761 #define M_ETHSOPCNT 0xfU
26762 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
26763 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
26765 #define S_ETHEOPCNT 8
26766 #define M_ETHEOPCNT 0xfU
26767 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
26768 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
26770 #define S_CPLSOPCNT 4
26771 #define M_CPLSOPCNT 0xfU
26772 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
26773 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
26775 #define S_CPLEOPCNT 0
26776 #define M_CPLEOPCNT 0xfU
26777 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
26778 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
26780 #define A_TP_DBG_ESIDE_HDR1 0x13d
26781 #define A_TP_DBG_ESIDE_HDR2 0x13e
26782 #define A_TP_DBG_ESIDE_HDR3 0x13f
26783 #define A_TP_VLAN_PRI_MAP 0x140
26785 #define S_FRAGMENTATION 9
26786 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
26787 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
26789 #define S_MPSHITTYPE 8
26790 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
26791 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
26793 #define S_MACMATCH 7
26794 #define V_MACMATCH(x) ((x) << S_MACMATCH)
26795 #define F_MACMATCH V_MACMATCH(1U)
26797 #define S_ETHERTYPE 6
26798 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
26799 #define F_ETHERTYPE V_ETHERTYPE(1U)
26801 #define S_PROTOCOL 5
26802 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
26803 #define F_PROTOCOL V_PROTOCOL(1U)
26806 #define V_TOS(x) ((x) << S_TOS)
26807 #define F_TOS V_TOS(1U)
26810 #define V_VLAN(x) ((x) << S_VLAN)
26811 #define F_VLAN V_VLAN(1U)
26813 #define S_VNIC_ID 2
26814 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
26815 #define F_VNIC_ID V_VNIC_ID(1U)
26818 #define V_PORT(x) ((x) << S_PORT)
26819 #define F_PORT V_PORT(1U)
26822 #define V_FCOE(x) ((x) << S_FCOE)
26823 #define F_FCOE V_FCOE(1U)
26825 #define S_FILTERMODE 15
26826 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
26827 #define F_FILTERMODE V_FILTERMODE(1U)
26829 #define S_FCOEMASK 14
26830 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
26831 #define F_FCOEMASK V_FCOEMASK(1U)
26833 #define S_SRVRSRAM 13
26834 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
26835 #define F_SRVRSRAM V_SRVRSRAM(1U)
26837 #define A_TP_INGRESS_CONFIG 0x141
26839 #define S_OPAQUE_TYPE 16
26840 #define M_OPAQUE_TYPE 0xffffU
26841 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
26842 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
26844 #define S_OPAQUE_RM 15
26845 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
26846 #define F_OPAQUE_RM V_OPAQUE_RM(1U)
26848 #define S_OPAQUE_HDR_SIZE 14
26849 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
26850 #define F_OPAQUE_HDR_SIZE V_OPAQUE_HDR_SIZE(1U)
26852 #define S_OPAQUE_RM_MAC_IN_MAC 13
26853 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
26854 #define F_OPAQUE_RM_MAC_IN_MAC V_OPAQUE_RM_MAC_IN_MAC(1U)
26856 #define S_FCOE_TARGET 12
26857 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
26858 #define F_FCOE_TARGET V_FCOE_TARGET(1U)
26861 #define V_VNIC(x) ((x) << S_VNIC)
26862 #define F_VNIC V_VNIC(1U)
26864 #define S_CSUM_HAS_PSEUDO_HDR 10
26865 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
26866 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
26868 #define S_RM_OVLAN 9
26869 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
26870 #define F_RM_OVLAN V_RM_OVLAN(1U)
26872 #define S_LOOKUPEVERYPKT 8
26873 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
26874 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U)
26876 #define S_IPV6_EXT_HDR_SKIP 0
26877 #define M_IPV6_EXT_HDR_SKIP 0xffU
26878 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
26879 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
26881 #define S_FRAG_LEN_MOD8_COMPAT 12
26882 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
26883 #define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U)
26885 #define S_USE_ENC_IDX 13
26886 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
26887 #define F_USE_ENC_IDX V_USE_ENC_IDX(1U)
26889 #define A_TP_TX_DROP_CFG_CH2 0x142
26890 #define A_TP_TX_DROP_CFG_CH3 0x143
26891 #define A_TP_EGRESS_CONFIG 0x145
26893 #define S_REWRITEFORCETOSIZE 0
26894 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
26895 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
26897 #define A_TP_INGRESS_CONFIG2 0x145
26899 #define S_IPV6_UDP_CSUM_COMPAT 31
26900 #define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
26901 #define F_IPV6_UDP_CSUM_COMPAT V_IPV6_UDP_CSUM_COMPAT(1U)
26903 #define S_VNTAGPLDENABLE 30
26904 #define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
26905 #define F_VNTAGPLDENABLE V_VNTAGPLDENABLE(1U)
26907 #define S_TCP_PLD_FILTER_OFFSET 20
26908 #define M_TCP_PLD_FILTER_OFFSET 0x3ffU
26909 #define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
26910 #define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
26912 #define S_UDP_PLD_FILTER_OFFSET 10
26913 #define M_UDP_PLD_FILTER_OFFSET 0x3ffU
26914 #define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
26915 #define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
26917 #define S_TNL_PLD_FILTER_OFFSET 0
26918 #define M_TNL_PLD_FILTER_OFFSET 0x3ffU
26919 #define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
26920 #define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
26922 #define A_TP_EHDR_CONFIG_LO 0x146
26924 #define S_CPLLIMIT 24
26925 #define M_CPLLIMIT 0xffU
26926 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
26927 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
26929 #define S_ETHLIMIT 16
26930 #define M_ETHLIMIT 0xffU
26931 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
26932 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
26934 #define S_IPLIMIT 8
26935 #define M_IPLIMIT 0xffU
26936 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
26937 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
26939 #define S_TCPLIMIT 0
26940 #define M_TCPLIMIT 0xffU
26941 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
26942 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
26944 #define A_TP_EHDR_CONFIG_HI 0x147
26945 #define A_TP_DBG_ESIDE_INT 0x148
26947 #define S_ERXSOP2X 28
26948 #define M_ERXSOP2X 0xfU
26949 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
26950 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
26952 #define S_ERXEOP2X 24
26953 #define M_ERXEOP2X 0xfU
26954 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
26955 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
26957 #define S_ERXVALID2X 20
26958 #define M_ERXVALID2X 0xfU
26959 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
26960 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
26962 #define S_ERXAFULL2X 16
26963 #define M_ERXAFULL2X 0xfU
26964 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
26965 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
26967 #define S_PLD2XTXVALID 12
26968 #define M_PLD2XTXVALID 0xfU
26969 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
26970 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
26972 #define S_PLD2XTXAFULL 8
26973 #define M_PLD2XTXAFULL 0xfU
26974 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
26975 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
26977 #define S_ERRORSRDY 7
26978 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
26979 #define F_ERRORSRDY V_ERRORSRDY(1U)
26981 #define S_ERRORDRDY 6
26982 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
26983 #define F_ERRORDRDY V_ERRORDRDY(1U)
26985 #define S_TCPOPSRDY 5
26986 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
26987 #define F_TCPOPSRDY V_TCPOPSRDY(1U)
26989 #define S_TCPOPDRDY 4
26990 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
26991 #define F_TCPOPDRDY V_TCPOPDRDY(1U)
26993 #define S_PLDTXSRDY 3
26994 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
26995 #define F_PLDTXSRDY V_PLDTXSRDY(1U)
26997 #define S_PLDTXDRDY 2
26998 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
26999 #define F_PLDTXDRDY V_PLDTXDRDY(1U)
27001 #define S_TCPOPTTXVALID 1
27002 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
27003 #define F_TCPOPTTXVALID V_TCPOPTTXVALID(1U)
27005 #define S_TCPOPTTXFULL 0
27006 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
27007 #define F_TCPOPTTXFULL V_TCPOPTTXFULL(1U)
27009 #define S_PKTATTRSRDY 3
27010 #define V_PKTATTRSRDY(x) ((x) << S_PKTATTRSRDY)
27011 #define F_PKTATTRSRDY V_PKTATTRSRDY(1U)
27013 #define S_PKTATTRDRDY 2
27014 #define V_PKTATTRDRDY(x) ((x) << S_PKTATTRDRDY)
27015 #define F_PKTATTRDRDY V_PKTATTRDRDY(1U)
27017 #define A_TP_DBG_ESIDE_DEMUX 0x149
27019 #define S_EALLDONE 28
27020 #define M_EALLDONE 0xfU
27021 #define V_EALLDONE(x) ((x) << S_EALLDONE)
27022 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
27024 #define S_EFIFOPLDDONE 24
27025 #define M_EFIFOPLDDONE 0xfU
27026 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
27027 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
27029 #define S_EDBDONE 20
27030 #define M_EDBDONE 0xfU
27031 #define V_EDBDONE(x) ((x) << S_EDBDONE)
27032 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
27034 #define S_EISSFIFODONE 16
27035 #define M_EISSFIFODONE 0xfU
27036 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
27037 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
27039 #define S_EACKERRFIFODONE 12
27040 #define M_EACKERRFIFODONE 0xfU
27041 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
27042 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
27044 #define S_EFIFOERRORDONE 8
27045 #define M_EFIFOERRORDONE 0xfU
27046 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
27047 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
27049 #define S_ERXPKTATTRFIFOFDONE 4
27050 #define M_ERXPKTATTRFIFOFDONE 0xfU
27051 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
27052 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
27054 #define S_ETCPOPDONE 0
27055 #define M_ETCPOPDONE 0xfU
27056 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
27057 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
27059 #define A_TP_DBG_ESIDE_IN0 0x14a
27061 #define S_RXVALID 31
27062 #define V_RXVALID(x) ((x) << S_RXVALID)
27063 #define F_RXVALID V_RXVALID(1U)
27065 #define S_RXFULL 30
27066 #define V_RXFULL(x) ((x) << S_RXFULL)
27067 #define F_RXFULL V_RXFULL(1U)
27069 #define S_RXSOCP 29
27070 #define V_RXSOCP(x) ((x) << S_RXSOCP)
27071 #define F_RXSOCP V_RXSOCP(1U)
27074 #define V_RXEOP(x) ((x) << S_RXEOP)
27075 #define F_RXEOP V_RXEOP(1U)
27077 #define S_RXVALID_I 27
27078 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
27079 #define F_RXVALID_I V_RXVALID_I(1U)
27081 #define S_RXFULL_I 26
27082 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
27083 #define F_RXFULL_I V_RXFULL_I(1U)
27085 #define S_RXSOCP_I 25
27086 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
27087 #define F_RXSOCP_I V_RXSOCP_I(1U)
27089 #define S_RXEOP_I 24
27090 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
27091 #define F_RXEOP_I V_RXEOP_I(1U)
27093 #define S_RXVALID_I2 23
27094 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
27095 #define F_RXVALID_I2 V_RXVALID_I2(1U)
27097 #define S_RXFULL_I2 22
27098 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
27099 #define F_RXFULL_I2 V_RXFULL_I2(1U)
27101 #define S_RXSOCP_I2 21
27102 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
27103 #define F_RXSOCP_I2 V_RXSOCP_I2(1U)
27105 #define S_RXEOP_I2 20
27106 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
27107 #define F_RXEOP_I2 V_RXEOP_I2(1U)
27109 #define S_CT_MPA_TXVALID_FIFO 19
27110 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
27111 #define F_CT_MPA_TXVALID_FIFO V_CT_MPA_TXVALID_FIFO(1U)
27113 #define S_CT_MPA_TXFULL_FIFO 18
27114 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
27115 #define F_CT_MPA_TXFULL_FIFO V_CT_MPA_TXFULL_FIFO(1U)
27117 #define S_CT_MPA_TXVALID 17
27118 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
27119 #define F_CT_MPA_TXVALID V_CT_MPA_TXVALID(1U)
27121 #define S_CT_MPA_TXFULL 16
27122 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
27123 #define F_CT_MPA_TXFULL V_CT_MPA_TXFULL(1U)
27125 #define S_RXVALID_BUF 15
27126 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
27127 #define F_RXVALID_BUF V_RXVALID_BUF(1U)
27129 #define S_RXFULL_BUF 14
27130 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
27131 #define F_RXFULL_BUF V_RXFULL_BUF(1U)
27133 #define S_PLD_TXVALID 13
27134 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
27135 #define F_PLD_TXVALID V_PLD_TXVALID(1U)
27137 #define S_PLD_TXFULL 12
27138 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
27139 #define F_PLD_TXFULL V_PLD_TXFULL(1U)
27141 #define S_ISS_FIFO_SRDY 11
27142 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
27143 #define F_ISS_FIFO_SRDY V_ISS_FIFO_SRDY(1U)
27145 #define S_ISS_FIFO_DRDY 10
27146 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
27147 #define F_ISS_FIFO_DRDY V_ISS_FIFO_DRDY(1U)
27149 #define S_CT_TCP_OP_ISS_SRDY 9
27150 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
27151 #define F_CT_TCP_OP_ISS_SRDY V_CT_TCP_OP_ISS_SRDY(1U)
27153 #define S_CT_TCP_OP_ISS_DRDY 8
27154 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
27155 #define F_CT_TCP_OP_ISS_DRDY V_CT_TCP_OP_ISS_DRDY(1U)
27157 #define S_P2CSUMERROR_SRDY 7
27158 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
27159 #define F_P2CSUMERROR_SRDY V_P2CSUMERROR_SRDY(1U)
27161 #define S_P2CSUMERROR_DRDY 6
27162 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
27163 #define F_P2CSUMERROR_DRDY V_P2CSUMERROR_DRDY(1U)
27165 #define S_FIFO_ERROR_SRDY 5
27166 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
27167 #define F_FIFO_ERROR_SRDY V_FIFO_ERROR_SRDY(1U)
27169 #define S_FIFO_ERROR_DRDY 4
27170 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
27171 #define F_FIFO_ERROR_DRDY V_FIFO_ERROR_DRDY(1U)
27173 #define S_PLD_SRDY 3
27174 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
27175 #define F_PLD_SRDY V_PLD_SRDY(1U)
27177 #define S_PLD_DRDY 2
27178 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
27179 #define F_PLD_DRDY V_PLD_DRDY(1U)
27181 #define S_RX_PKT_ATTR_SRDY 1
27182 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
27183 #define F_RX_PKT_ATTR_SRDY V_RX_PKT_ATTR_SRDY(1U)
27185 #define S_RX_PKT_ATTR_DRDY 0
27186 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
27187 #define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U)
27189 #define S_RXRUNT 25
27190 #define V_RXRUNT(x) ((x) << S_RXRUNT)
27191 #define F_RXRUNT V_RXRUNT(1U)
27193 #define S_RXRUNTPARSER 24
27194 #define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
27195 #define F_RXRUNTPARSER V_RXRUNTPARSER(1U)
27197 #define S_ERROR_SRDY 5
27198 #define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
27199 #define F_ERROR_SRDY V_ERROR_SRDY(1U)
27201 #define S_ERROR_DRDY 4
27202 #define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
27203 #define F_ERROR_DRDY V_ERROR_DRDY(1U)
27205 #define A_TP_DBG_ESIDE_IN1 0x14b
27206 #define A_TP_DBG_ESIDE_IN2 0x14c
27207 #define A_TP_DBG_ESIDE_IN3 0x14d
27208 #define A_TP_DBG_ESIDE_FRM 0x14e
27210 #define S_ERX2XERROR 28
27211 #define M_ERX2XERROR 0xfU
27212 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
27213 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
27215 #define S_EPLDTX2XERROR 24
27216 #define M_EPLDTX2XERROR 0xfU
27217 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
27218 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
27220 #define S_ETXERROR 20
27221 #define M_ETXERROR 0xfU
27222 #define V_ETXERROR(x) ((x) << S_ETXERROR)
27223 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
27225 #define S_EPLDRXERROR 16
27226 #define M_EPLDRXERROR 0xfU
27227 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
27228 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
27230 #define S_ERXSIZEERROR3 12
27231 #define M_ERXSIZEERROR3 0xfU
27232 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
27233 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
27235 #define S_ERXSIZEERROR2 8
27236 #define M_ERXSIZEERROR2 0xfU
27237 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
27238 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
27240 #define S_ERXSIZEERROR1 4
27241 #define M_ERXSIZEERROR1 0xfU
27242 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
27243 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
27245 #define S_ERXSIZEERROR0 0
27246 #define M_ERXSIZEERROR0 0xfU
27247 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
27248 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
27250 #define A_TP_DBG_ESIDE_DRP 0x14f
27252 #define S_RXDROP3 24
27253 #define M_RXDROP3 0xffU
27254 #define V_RXDROP3(x) ((x) << S_RXDROP3)
27255 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
27257 #define S_RXDROP2 16
27258 #define M_RXDROP2 0xffU
27259 #define V_RXDROP2(x) ((x) << S_RXDROP2)
27260 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
27262 #define S_RXDROP1 8
27263 #define M_RXDROP1 0xffU
27264 #define V_RXDROP1(x) ((x) << S_RXDROP1)
27265 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
27267 #define S_RXDROP0 0
27268 #define M_RXDROP0 0xffU
27269 #define V_RXDROP0(x) ((x) << S_RXDROP0)
27270 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
27272 #define A_TP_DBG_ESIDE_TX 0x150
27274 #define S_ETXVALID 4
27275 #define M_ETXVALID 0xfU
27276 #define V_ETXVALID(x) ((x) << S_ETXVALID)
27277 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
27279 #define S_ETXFULL 0
27280 #define M_ETXFULL 0xfU
27281 #define V_ETXFULL(x) ((x) << S_ETXFULL)
27282 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
27284 #define S_TXERRORCNT 8
27285 #define M_TXERRORCNT 0xffffffU
27286 #define V_TXERRORCNT(x) ((x) << S_TXERRORCNT)
27287 #define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT)
27289 #define A_TP_ESIDE_SVID_MASK 0x151
27290 #define A_TP_ESIDE_DVID_MASK 0x152
27291 #define A_TP_ESIDE_ALIGN_MASK 0x153
27293 #define S_USE_LOOP_BIT 24
27294 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
27295 #define F_USE_LOOP_BIT V_USE_LOOP_BIT(1U)
27297 #define S_LOOP_OFFSET 16
27298 #define M_LOOP_OFFSET 0xffU
27299 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
27300 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
27302 #define S_DVID_ID_OFFSET 8
27303 #define M_DVID_ID_OFFSET 0xffU
27304 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
27305 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
27307 #define S_SVID_ID_OFFSET 0
27308 #define M_SVID_ID_OFFSET 0xffU
27309 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
27310 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
27312 #define A_TP_DBG_ESIDE_OP 0x154
27314 #define S_OPT_PARSER_FATAL_CHANNEL0 29
27315 #define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
27316 #define F_OPT_PARSER_FATAL_CHANNEL0 V_OPT_PARSER_FATAL_CHANNEL0(1U)
27318 #define S_OPT_PARSER_BUSY_CHANNEL0 28
27319 #define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
27320 #define F_OPT_PARSER_BUSY_CHANNEL0 V_OPT_PARSER_BUSY_CHANNEL0(1U)
27322 #define S_OPT_PARSER_ITCP_STATE_CHANNEL0 26
27323 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0 0x3U
27324 #define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
27325 #define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
27327 #define S_OPT_PARSER_OTK_STATE_CHANNEL0 24
27328 #define M_OPT_PARSER_OTK_STATE_CHANNEL0 0x3U
27329 #define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
27330 #define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
27332 #define S_OPT_PARSER_FATAL_CHANNEL1 21
27333 #define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
27334 #define F_OPT_PARSER_FATAL_CHANNEL1 V_OPT_PARSER_FATAL_CHANNEL1(1U)
27336 #define S_OPT_PARSER_BUSY_CHANNEL1 20
27337 #define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
27338 #define F_OPT_PARSER_BUSY_CHANNEL1 V_OPT_PARSER_BUSY_CHANNEL1(1U)
27340 #define S_OPT_PARSER_ITCP_STATE_CHANNEL1 18
27341 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1 0x3U
27342 #define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
27343 #define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
27345 #define S_OPT_PARSER_OTK_STATE_CHANNEL1 16
27346 #define M_OPT_PARSER_OTK_STATE_CHANNEL1 0x3U
27347 #define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
27348 #define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
27350 #define S_OPT_PARSER_FATAL_CHANNEL2 13
27351 #define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
27352 #define F_OPT_PARSER_FATAL_CHANNEL2 V_OPT_PARSER_FATAL_CHANNEL2(1U)
27354 #define S_OPT_PARSER_BUSY_CHANNEL2 12
27355 #define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
27356 #define F_OPT_PARSER_BUSY_CHANNEL2 V_OPT_PARSER_BUSY_CHANNEL2(1U)
27358 #define S_OPT_PARSER_ITCP_STATE_CHANNEL2 10
27359 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2 0x3U
27360 #define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
27361 #define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
27363 #define S_OPT_PARSER_OTK_STATE_CHANNEL2 8
27364 #define M_OPT_PARSER_OTK_STATE_CHANNEL2 0x3U
27365 #define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
27366 #define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
27368 #define S_OPT_PARSER_FATAL_CHANNEL3 5
27369 #define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
27370 #define F_OPT_PARSER_FATAL_CHANNEL3 V_OPT_PARSER_FATAL_CHANNEL3(1U)
27372 #define S_OPT_PARSER_BUSY_CHANNEL3 4
27373 #define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
27374 #define F_OPT_PARSER_BUSY_CHANNEL3 V_OPT_PARSER_BUSY_CHANNEL3(1U)
27376 #define S_OPT_PARSER_ITCP_STATE_CHANNEL3 2
27377 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3 0x3U
27378 #define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
27379 #define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
27381 #define S_OPT_PARSER_OTK_STATE_CHANNEL3 0
27382 #define M_OPT_PARSER_OTK_STATE_CHANNEL3 0x3U
27383 #define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
27384 #define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
27386 #define A_TP_DBG_ESIDE_OP_ALT 0x155
27388 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0 29
27389 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
27390 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0 V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
27392 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 24
27393 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 0x1fU
27394 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
27395 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
27397 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1 21
27398 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
27399 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1 V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
27401 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 16
27402 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 0x1fU
27403 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
27404 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
27406 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2 13
27407 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
27408 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2 V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
27410 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 8
27411 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 0x1fU
27412 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
27413 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
27415 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3 5
27416 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
27417 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3 V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
27419 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0
27420 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0x1fU
27421 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
27422 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
27424 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
27426 #define S_OPT_PARSER_BUSY_VEC_CHANNEL3 24
27427 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3 0xffU
27428 #define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
27429 #define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
27431 #define S_OPT_PARSER_BUSY_VEC_CHANNEL2 16
27432 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2 0xffU
27433 #define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
27434 #define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
27436 #define S_OPT_PARSER_BUSY_VEC_CHANNEL1 8
27437 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1 0xffU
27438 #define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
27439 #define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
27441 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0 0
27442 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0 0xffU
27443 #define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
27444 #define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
27446 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
27448 #define S_OPT_PARSER_COOKIE_CHANNEL3 24
27449 #define M_OPT_PARSER_COOKIE_CHANNEL3 0xffU
27450 #define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
27451 #define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
27453 #define S_OPT_PARSER_COOKIE_CHANNEL2 16
27454 #define M_OPT_PARSER_COOKIE_CHANNEL2 0xffU
27455 #define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
27456 #define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
27458 #define S_OPT_PARSER_COOKIE_CHANNEL1 8
27459 #define M_OPT_PARSER_COOKIE_CHANNEL1 0xffU
27460 #define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
27461 #define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
27463 #define S_OPT_PARSER_COOKIE_CHANNEL0 0
27464 #define M_OPT_PARSER_COOKIE_CHANNEL0 0xffU
27465 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
27466 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
27468 #define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
27469 #define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
27470 #define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
27471 #define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
27472 #define A_TP_ESIDE_CONFIG 0x160
27474 #define S_VNI_EN 26
27475 #define V_VNI_EN(x) ((x) << S_VNI_EN)
27476 #define F_VNI_EN V_VNI_EN(1U)
27478 #define S_ENC_RX_EN 25
27479 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
27480 #define F_ENC_RX_EN V_ENC_RX_EN(1U)
27482 #define S_TNL_LKP_INNER_SEL 24
27483 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
27484 #define F_TNL_LKP_INNER_SEL V_TNL_LKP_INNER_SEL(1U)
27486 #define S_ROCEV2UDPPORT 0
27487 #define M_ROCEV2UDPPORT 0xffffU
27488 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
27489 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
27491 #define A_TP_DBG_CSIDE_RX0 0x230
27493 #define S_CRXSOPCNT 28
27494 #define M_CRXSOPCNT 0xfU
27495 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
27496 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
27498 #define S_CRXEOPCNT 24
27499 #define M_CRXEOPCNT 0xfU
27500 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
27501 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
27503 #define S_CRXPLDSOPCNT 20
27504 #define M_CRXPLDSOPCNT 0xfU
27505 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
27506 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
27508 #define S_CRXPLDEOPCNT 16
27509 #define M_CRXPLDEOPCNT 0xfU
27510 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
27511 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
27513 #define S_CRXARBSOPCNT 12
27514 #define M_CRXARBSOPCNT 0xfU
27515 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
27516 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
27518 #define S_CRXARBEOPCNT 8
27519 #define M_CRXARBEOPCNT 0xfU
27520 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
27521 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
27523 #define S_CRXCPLSOPCNT 4
27524 #define M_CRXCPLSOPCNT 0xfU
27525 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
27526 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
27528 #define S_CRXCPLEOPCNT 0
27529 #define M_CRXCPLEOPCNT 0xfU
27530 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
27531 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
27533 #define A_TP_DBG_CSIDE_RX1 0x231
27534 #define A_TP_DBG_CSIDE_RX2 0x232
27535 #define A_TP_DBG_CSIDE_RX3 0x233
27536 #define A_TP_DBG_CSIDE_TX0 0x234
27538 #define S_TXSOPCNT 28
27539 #define M_TXSOPCNT 0xfU
27540 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
27541 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
27543 #define S_TXEOPCNT 24
27544 #define M_TXEOPCNT 0xfU
27545 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
27546 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
27548 #define S_TXPLDSOPCNT 20
27549 #define M_TXPLDSOPCNT 0xfU
27550 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
27551 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
27553 #define S_TXPLDEOPCNT 16
27554 #define M_TXPLDEOPCNT 0xfU
27555 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
27556 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
27558 #define S_TXARBSOPCNT 12
27559 #define M_TXARBSOPCNT 0xfU
27560 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
27561 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
27563 #define S_TXARBEOPCNT 8
27564 #define M_TXARBEOPCNT 0xfU
27565 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
27566 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
27568 #define S_TXCPLSOPCNT 4
27569 #define M_TXCPLSOPCNT 0xfU
27570 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
27571 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
27573 #define S_TXCPLEOPCNT 0
27574 #define M_TXCPLEOPCNT 0xfU
27575 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
27576 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
27578 #define A_TP_DBG_CSIDE_TX1 0x235
27579 #define A_TP_DBG_CSIDE_TX2 0x236
27580 #define A_TP_DBG_CSIDE_TX3 0x237
27581 #define A_TP_DBG_CSIDE_FIFO0 0x238
27583 #define S_PLD_RXZEROP_SRDY1 31
27584 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
27585 #define F_PLD_RXZEROP_SRDY1 V_PLD_RXZEROP_SRDY1(1U)
27587 #define S_PLD_RXZEROP_DRDY1 30
27588 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
27589 #define F_PLD_RXZEROP_DRDY1 V_PLD_RXZEROP_DRDY1(1U)
27591 #define S_PLD_TXZEROP_SRDY1 29
27592 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
27593 #define F_PLD_TXZEROP_SRDY1 V_PLD_TXZEROP_SRDY1(1U)
27595 #define S_PLD_TXZEROP_DRDY1 28
27596 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
27597 #define F_PLD_TXZEROP_DRDY1 V_PLD_TXZEROP_DRDY1(1U)
27599 #define S_PLD_TX_SRDY1 27
27600 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
27601 #define F_PLD_TX_SRDY1 V_PLD_TX_SRDY1(1U)
27603 #define S_PLD_TX_DRDY1 26
27604 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
27605 #define F_PLD_TX_DRDY1 V_PLD_TX_DRDY1(1U)
27607 #define S_ERROR_SRDY1 25
27608 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
27609 #define F_ERROR_SRDY1 V_ERROR_SRDY1(1U)
27611 #define S_ERROR_DRDY1 24
27612 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
27613 #define F_ERROR_DRDY1 V_ERROR_DRDY1(1U)
27615 #define S_DB_VLD1 23
27616 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
27617 #define F_DB_VLD1 V_DB_VLD1(1U)
27619 #define S_DB_GT1 22
27620 #define V_DB_GT1(x) ((x) << S_DB_GT1)
27621 #define F_DB_GT1 V_DB_GT1(1U)
27623 #define S_TXVALID1 21
27624 #define V_TXVALID1(x) ((x) << S_TXVALID1)
27625 #define F_TXVALID1 V_TXVALID1(1U)
27627 #define S_TXFULL1 20
27628 #define V_TXFULL1(x) ((x) << S_TXFULL1)
27629 #define F_TXFULL1 V_TXFULL1(1U)
27631 #define S_PLD_TXVALID1 19
27632 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
27633 #define F_PLD_TXVALID1 V_PLD_TXVALID1(1U)
27635 #define S_PLD_TXFULL1 18
27636 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
27637 #define F_PLD_TXFULL1 V_PLD_TXFULL1(1U)
27639 #define S_CPL5_TXVALID1 17
27640 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
27641 #define F_CPL5_TXVALID1 V_CPL5_TXVALID1(1U)
27643 #define S_CPL5_TXFULL1 16
27644 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
27645 #define F_CPL5_TXFULL1 V_CPL5_TXFULL1(1U)
27647 #define S_PLD_RXZEROP_SRDY0 15
27648 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
27649 #define F_PLD_RXZEROP_SRDY0 V_PLD_RXZEROP_SRDY0(1U)
27651 #define S_PLD_RXZEROP_DRDY0 14
27652 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
27653 #define F_PLD_RXZEROP_DRDY0 V_PLD_RXZEROP_DRDY0(1U)
27655 #define S_PLD_TXZEROP_SRDY0 13
27656 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
27657 #define F_PLD_TXZEROP_SRDY0 V_PLD_TXZEROP_SRDY0(1U)
27659 #define S_PLD_TXZEROP_DRDY0 12
27660 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
27661 #define F_PLD_TXZEROP_DRDY0 V_PLD_TXZEROP_DRDY0(1U)
27663 #define S_PLD_TX_SRDY0 11
27664 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
27665 #define F_PLD_TX_SRDY0 V_PLD_TX_SRDY0(1U)
27667 #define S_PLD_TX_DRDY0 10
27668 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
27669 #define F_PLD_TX_DRDY0 V_PLD_TX_DRDY0(1U)
27671 #define S_ERROR_SRDY0 9
27672 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
27673 #define F_ERROR_SRDY0 V_ERROR_SRDY0(1U)
27675 #define S_ERROR_DRDY0 8
27676 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
27677 #define F_ERROR_DRDY0 V_ERROR_DRDY0(1U)
27679 #define S_DB_VLD0 7
27680 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
27681 #define F_DB_VLD0 V_DB_VLD0(1U)
27684 #define V_DB_GT0(x) ((x) << S_DB_GT0)
27685 #define F_DB_GT0 V_DB_GT0(1U)
27687 #define S_TXVALID0 5
27688 #define V_TXVALID0(x) ((x) << S_TXVALID0)
27689 #define F_TXVALID0 V_TXVALID0(1U)
27691 #define S_TXFULL0 4
27692 #define V_TXFULL0(x) ((x) << S_TXFULL0)
27693 #define F_TXFULL0 V_TXFULL0(1U)
27695 #define S_PLD_TXVALID0 3
27696 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
27697 #define F_PLD_TXVALID0 V_PLD_TXVALID0(1U)
27699 #define S_PLD_TXFULL0 2
27700 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
27701 #define F_PLD_TXFULL0 V_PLD_TXFULL0(1U)
27703 #define S_CPL5_TXVALID0 1
27704 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
27705 #define F_CPL5_TXVALID0 V_CPL5_TXVALID0(1U)
27707 #define S_CPL5_TXFULL0 0
27708 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
27709 #define F_CPL5_TXFULL0 V_CPL5_TXFULL0(1U)
27711 #define A_TP_DBG_CSIDE_FIFO1 0x239
27713 #define S_PLD_RXZEROP_SRDY3 31
27714 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
27715 #define F_PLD_RXZEROP_SRDY3 V_PLD_RXZEROP_SRDY3(1U)
27717 #define S_PLD_RXZEROP_DRDY3 30
27718 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
27719 #define F_PLD_RXZEROP_DRDY3 V_PLD_RXZEROP_DRDY3(1U)
27721 #define S_PLD_TXZEROP_SRDY3 29
27722 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
27723 #define F_PLD_TXZEROP_SRDY3 V_PLD_TXZEROP_SRDY3(1U)
27725 #define S_PLD_TXZEROP_DRDY3 28
27726 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
27727 #define F_PLD_TXZEROP_DRDY3 V_PLD_TXZEROP_DRDY3(1U)
27729 #define S_PLD_TX_SRDY3 27
27730 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
27731 #define F_PLD_TX_SRDY3 V_PLD_TX_SRDY3(1U)
27733 #define S_PLD_TX_DRDY3 26
27734 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
27735 #define F_PLD_TX_DRDY3 V_PLD_TX_DRDY3(1U)
27737 #define S_ERROR_SRDY3 25
27738 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
27739 #define F_ERROR_SRDY3 V_ERROR_SRDY3(1U)
27741 #define S_ERROR_DRDY3 24
27742 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
27743 #define F_ERROR_DRDY3 V_ERROR_DRDY3(1U)
27745 #define S_DB_VLD3 23
27746 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
27747 #define F_DB_VLD3 V_DB_VLD3(1U)
27749 #define S_DB_GT3 22
27750 #define V_DB_GT3(x) ((x) << S_DB_GT3)
27751 #define F_DB_GT3 V_DB_GT3(1U)
27753 #define S_TXVALID3 21
27754 #define V_TXVALID3(x) ((x) << S_TXVALID3)
27755 #define F_TXVALID3 V_TXVALID3(1U)
27757 #define S_TXFULL3 20
27758 #define V_TXFULL3(x) ((x) << S_TXFULL3)
27759 #define F_TXFULL3 V_TXFULL3(1U)
27761 #define S_PLD_TXVALID3 19
27762 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
27763 #define F_PLD_TXVALID3 V_PLD_TXVALID3(1U)
27765 #define S_PLD_TXFULL3 18
27766 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
27767 #define F_PLD_TXFULL3 V_PLD_TXFULL3(1U)
27769 #define S_CPL5_TXVALID3 17
27770 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
27771 #define F_CPL5_TXVALID3 V_CPL5_TXVALID3(1U)
27773 #define S_CPL5_TXFULL3 16
27774 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
27775 #define F_CPL5_TXFULL3 V_CPL5_TXFULL3(1U)
27777 #define S_PLD_RXZEROP_SRDY2 15
27778 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
27779 #define F_PLD_RXZEROP_SRDY2 V_PLD_RXZEROP_SRDY2(1U)
27781 #define S_PLD_RXZEROP_DRDY2 14
27782 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
27783 #define F_PLD_RXZEROP_DRDY2 V_PLD_RXZEROP_DRDY2(1U)
27785 #define S_PLD_TXZEROP_SRDY2 13
27786 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
27787 #define F_PLD_TXZEROP_SRDY2 V_PLD_TXZEROP_SRDY2(1U)
27789 #define S_PLD_TXZEROP_DRDY2 12
27790 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
27791 #define F_PLD_TXZEROP_DRDY2 V_PLD_TXZEROP_DRDY2(1U)
27793 #define S_PLD_TX_SRDY2 11
27794 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
27795 #define F_PLD_TX_SRDY2 V_PLD_TX_SRDY2(1U)
27797 #define S_PLD_TX_DRDY2 10
27798 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
27799 #define F_PLD_TX_DRDY2 V_PLD_TX_DRDY2(1U)
27801 #define S_ERROR_SRDY2 9
27802 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
27803 #define F_ERROR_SRDY2 V_ERROR_SRDY2(1U)
27805 #define S_ERROR_DRDY2 8
27806 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
27807 #define F_ERROR_DRDY2 V_ERROR_DRDY2(1U)
27809 #define S_DB_VLD2 7
27810 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
27811 #define F_DB_VLD2 V_DB_VLD2(1U)
27814 #define V_DB_GT2(x) ((x) << S_DB_GT2)
27815 #define F_DB_GT2 V_DB_GT2(1U)
27817 #define S_TXVALID2 5
27818 #define V_TXVALID2(x) ((x) << S_TXVALID2)
27819 #define F_TXVALID2 V_TXVALID2(1U)
27821 #define S_TXFULL2 4
27822 #define V_TXFULL2(x) ((x) << S_TXFULL2)
27823 #define F_TXFULL2 V_TXFULL2(1U)
27825 #define S_PLD_TXVALID2 3
27826 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
27827 #define F_PLD_TXVALID2 V_PLD_TXVALID2(1U)
27829 #define S_PLD_TXFULL2 2
27830 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
27831 #define F_PLD_TXFULL2 V_PLD_TXFULL2(1U)
27833 #define S_CPL5_TXVALID2 1
27834 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
27835 #define F_CPL5_TXVALID2 V_CPL5_TXVALID2(1U)
27837 #define S_CPL5_TXFULL2 0
27838 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
27839 #define F_CPL5_TXFULL2 V_CPL5_TXFULL2(1U)
27841 #define A_TP_DBG_CSIDE_DISP0 0x23a
27843 #define S_CPL5RXVALID 27
27844 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
27845 #define F_CPL5RXVALID V_CPL5RXVALID(1U)
27847 #define S_CSTATIC1 26
27848 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
27849 #define F_CSTATIC1 V_CSTATIC1(1U)
27851 #define S_CSTATIC2 25
27852 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
27853 #define F_CSTATIC2 V_CSTATIC2(1U)
27855 #define S_PLD_RXZEROP 24
27856 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
27857 #define F_PLD_RXZEROP V_PLD_RXZEROP(1U)
27859 #define S_DDP_IN_PROGRESS 23
27860 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
27861 #define F_DDP_IN_PROGRESS V_DDP_IN_PROGRESS(1U)
27863 #define S_PLD_RXZEROP_SRDY 22
27864 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
27865 #define F_PLD_RXZEROP_SRDY V_PLD_RXZEROP_SRDY(1U)
27867 #define S_CSTATIC3 21
27868 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
27869 #define F_CSTATIC3 V_CSTATIC3(1U)
27871 #define S_DDP_DRDY 20
27872 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
27873 #define F_DDP_DRDY V_DDP_DRDY(1U)
27875 #define S_DDP_PRE_STATE 17
27876 #define M_DDP_PRE_STATE 0x7U
27877 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
27878 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
27880 #define S_DDP_SRDY 16
27881 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
27882 #define F_DDP_SRDY V_DDP_SRDY(1U)
27884 #define S_DDP_MSG_CODE 12
27885 #define M_DDP_MSG_CODE 0xfU
27886 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
27887 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
27889 #define S_CPL5_SOCP_CNT 10
27890 #define M_CPL5_SOCP_CNT 0x3U
27891 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
27892 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
27894 #define S_CSTATIC4 4
27895 #define M_CSTATIC4 0x3fU
27896 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
27897 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
27899 #define S_CMD_SEL 1
27900 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
27901 #define F_CMD_SEL V_CMD_SEL(1U)
27903 #define S_T5_TXFULL 31
27904 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
27905 #define F_T5_TXFULL V_T5_TXFULL(1U)
27907 #define S_CPL5RXFULL 26
27908 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
27909 #define F_CPL5RXFULL V_CPL5RXFULL(1U)
27911 #define S_T5_PLD_RXZEROP_SRDY 25
27912 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
27913 #define F_T5_PLD_RXZEROP_SRDY V_T5_PLD_RXZEROP_SRDY(1U)
27915 #define S_PLD2XRXVALID 23
27916 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
27917 #define F_PLD2XRXVALID V_PLD2XRXVALID(1U)
27919 #define S_T5_DDP_SRDY 22
27920 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
27921 #define F_T5_DDP_SRDY V_T5_DDP_SRDY(1U)
27923 #define S_T5_DDP_DRDY 21
27924 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
27925 #define F_T5_DDP_DRDY V_T5_DDP_DRDY(1U)
27927 #define S_DDPSTATE 16
27928 #define M_DDPSTATE 0x1fU
27929 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
27930 #define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
27932 #define S_DDPMSGCODE 12
27933 #define M_DDPMSGCODE 0xfU
27934 #define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
27935 #define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
27937 #define S_CPL5SOCPCNT 8
27938 #define M_CPL5SOCPCNT 0xfU
27939 #define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
27940 #define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
27942 #define S_PLDRXZEROPCNT 4
27943 #define M_PLDRXZEROPCNT 0xfU
27944 #define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
27945 #define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
27947 #define S_TXFRMERR2 3
27948 #define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
27949 #define F_TXFRMERR2 V_TXFRMERR2(1U)
27951 #define S_TXFRMERR1 2
27952 #define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
27953 #define F_TXFRMERR1 V_TXFRMERR1(1U)
27955 #define S_TXVALID2X 1
27956 #define V_TXVALID2X(x) ((x) << S_TXVALID2X)
27957 #define F_TXVALID2X V_TXVALID2X(1U)
27959 #define S_TXFULL2X 0
27960 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
27961 #define F_TXFULL2X V_TXFULL2X(1U)
27963 #define S_T6_TXFULL 31
27964 #define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
27965 #define F_T6_TXFULL V_T6_TXFULL(1U)
27967 #define S_T6_PLD_RXZEROP_SRDY 25
27968 #define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
27969 #define F_T6_PLD_RXZEROP_SRDY V_T6_PLD_RXZEROP_SRDY(1U)
27971 #define S_T6_DDP_SRDY 22
27972 #define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
27973 #define F_T6_DDP_SRDY V_T6_DDP_SRDY(1U)
27975 #define S_T6_DDP_DRDY 21
27976 #define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
27977 #define F_T6_DDP_DRDY V_T6_DDP_DRDY(1U)
27979 #define A_TP_DBG_CSIDE_DISP1 0x23b
27981 #define S_T5_TXFULL 31
27982 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
27983 #define F_T5_TXFULL V_T5_TXFULL(1U)
27985 #define S_T5_PLD_RXZEROP_SRDY 25
27986 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
27987 #define F_T5_PLD_RXZEROP_SRDY V_T5_PLD_RXZEROP_SRDY(1U)
27989 #define S_T5_DDP_SRDY 22
27990 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
27991 #define F_T5_DDP_SRDY V_T5_DDP_SRDY(1U)
27993 #define S_T5_DDP_DRDY 21
27994 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
27995 #define F_T5_DDP_DRDY V_T5_DDP_DRDY(1U)
27997 #define S_T6_TXFULL 31
27998 #define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
27999 #define F_T6_TXFULL V_T6_TXFULL(1U)
28001 #define S_T6_PLD_RXZEROP_SRDY 25
28002 #define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
28003 #define F_T6_PLD_RXZEROP_SRDY V_T6_PLD_RXZEROP_SRDY(1U)
28005 #define S_T6_DDP_SRDY 22
28006 #define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
28007 #define F_T6_DDP_SRDY V_T6_DDP_SRDY(1U)
28009 #define S_T6_DDP_DRDY 21
28010 #define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
28011 #define F_T6_DDP_DRDY V_T6_DDP_DRDY(1U)
28013 #define A_TP_DBG_CSIDE_DDP0 0x23c
28015 #define S_DDPMSGLATEST7 28
28016 #define M_DDPMSGLATEST7 0xfU
28017 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
28018 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
28020 #define S_DDPMSGLATEST6 24
28021 #define M_DDPMSGLATEST6 0xfU
28022 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
28023 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
28025 #define S_DDPMSGLATEST5 20
28026 #define M_DDPMSGLATEST5 0xfU
28027 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
28028 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
28030 #define S_DDPMSGLATEST4 16
28031 #define M_DDPMSGLATEST4 0xfU
28032 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
28033 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
28035 #define S_DDPMSGLATEST3 12
28036 #define M_DDPMSGLATEST3 0xfU
28037 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
28038 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
28040 #define S_DDPMSGLATEST2 8
28041 #define M_DDPMSGLATEST2 0xfU
28042 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
28043 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
28045 #define S_DDPMSGLATEST1 4
28046 #define M_DDPMSGLATEST1 0xfU
28047 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
28048 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
28050 #define S_DDPMSGLATEST0 0
28051 #define M_DDPMSGLATEST0 0xfU
28052 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
28053 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
28055 #define A_TP_DBG_CSIDE_DDP1 0x23d
28056 #define A_TP_DBG_CSIDE_FRM 0x23e
28058 #define S_CRX2XERROR 28
28059 #define M_CRX2XERROR 0xfU
28060 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
28061 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
28063 #define S_CPLDTX2XERROR 24
28064 #define M_CPLDTX2XERROR 0xfU
28065 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
28066 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
28068 #define S_CTXERROR 22
28069 #define M_CTXERROR 0x3U
28070 #define V_CTXERROR(x) ((x) << S_CTXERROR)
28071 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
28073 #define S_CPLDRXERROR 20
28074 #define M_CPLDRXERROR 0x3U
28075 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
28076 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
28078 #define S_CPLRXERROR 18
28079 #define M_CPLRXERROR 0x3U
28080 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
28081 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
28083 #define S_CPLTXERROR 16
28084 #define M_CPLTXERROR 0x3U
28085 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
28086 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
28088 #define S_CPRSERROR 0
28089 #define M_CPRSERROR 0xfU
28090 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
28091 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
28093 #define A_TP_DBG_CSIDE_INT 0x23f
28095 #define S_CRXVALID2X 28
28096 #define M_CRXVALID2X 0xfU
28097 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
28098 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
28100 #define S_CRXAFULL2X 24
28101 #define M_CRXAFULL2X 0xfU
28102 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
28103 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
28105 #define S_CTXVALID2X 22
28106 #define M_CTXVALID2X 0x3U
28107 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
28108 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
28110 #define S_CTXAFULL2X 20
28111 #define M_CTXAFULL2X 0x3U
28112 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
28113 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
28115 #define S_PLD2X_RXVALID 18
28116 #define M_PLD2X_RXVALID 0x3U
28117 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
28118 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
28120 #define S_PLD2X_RXAFULL 16
28121 #define M_PLD2X_RXAFULL 0x3U
28122 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
28123 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
28125 #define S_CSIDE_DDP_VALID 14
28126 #define M_CSIDE_DDP_VALID 0x3U
28127 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
28128 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
28130 #define S_DDP_AFULL 12
28131 #define M_DDP_AFULL 0x3U
28132 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
28133 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
28135 #define S_TRC_RXVALID 11
28136 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
28137 #define F_TRC_RXVALID V_TRC_RXVALID(1U)
28139 #define S_TRC_RXFULL 10
28140 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
28141 #define F_TRC_RXFULL V_TRC_RXFULL(1U)
28143 #define S_CPL5_TXVALID 9
28144 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
28145 #define F_CPL5_TXVALID V_CPL5_TXVALID(1U)
28147 #define S_CPL5_TXFULL 8
28148 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
28149 #define F_CPL5_TXFULL V_CPL5_TXFULL(1U)
28151 #define S_PLD2X_TXVALID 4
28152 #define M_PLD2X_TXVALID 0xfU
28153 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
28154 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
28156 #define S_PLD2X_TXAFULL 0
28157 #define M_PLD2X_TXAFULL 0xfU
28158 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
28159 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
28161 #define A_TP_CHDR_CONFIG 0x240
28163 #define S_CH1HIGH 24
28164 #define M_CH1HIGH 0xffU
28165 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
28166 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
28168 #define S_CH1LOW 16
28169 #define M_CH1LOW 0xffU
28170 #define V_CH1LOW(x) ((x) << S_CH1LOW)
28171 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
28173 #define S_CH0HIGH 8
28174 #define M_CH0HIGH 0xffU
28175 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
28176 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
28179 #define M_CH0LOW 0xffU
28180 #define V_CH0LOW(x) ((x) << S_CH0LOW)
28181 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
28183 #define A_TP_UTRN_CONFIG 0x241
28185 #define S_CH2FIFOLIMIT 16
28186 #define M_CH2FIFOLIMIT 0xffU
28187 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
28188 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
28190 #define S_CH1FIFOLIMIT 8
28191 #define M_CH1FIFOLIMIT 0xffU
28192 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
28193 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
28195 #define S_CH0FIFOLIMIT 0
28196 #define M_CH0FIFOLIMIT 0xffU
28197 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
28198 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
28200 #define A_TP_CDSP_CONFIG 0x242
28202 #define S_WRITEZEROEN 4
28203 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
28204 #define F_WRITEZEROEN V_WRITEZEROEN(1U)
28206 #define S_WRITEZEROOP 0
28207 #define M_WRITEZEROOP 0xfU
28208 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
28209 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
28211 #define S_STARTSKIPPLD 7
28212 #define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
28213 #define F_STARTSKIPPLD V_STARTSKIPPLD(1U)
28215 #define S_ATOMICCMDEN 5
28216 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
28217 #define F_ATOMICCMDEN V_ATOMICCMDEN(1U)
28219 #define S_ISCSICMDMODE 28
28220 #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
28221 #define F_ISCSICMDMODE V_ISCSICMDMODE(1U)
28223 #define A_TP_CSPI_POWER 0x243
28225 #define S_GATECHNTX3 11
28226 #define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
28227 #define F_GATECHNTX3 V_GATECHNTX3(1U)
28229 #define S_GATECHNTX2 10
28230 #define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
28231 #define F_GATECHNTX2 V_GATECHNTX2(1U)
28233 #define S_GATECHNTX1 9
28234 #define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
28235 #define F_GATECHNTX1 V_GATECHNTX1(1U)
28237 #define S_GATECHNTX0 8
28238 #define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
28239 #define F_GATECHNTX0 V_GATECHNTX0(1U)
28241 #define S_GATECHNRX1 7
28242 #define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
28243 #define F_GATECHNRX1 V_GATECHNRX1(1U)
28245 #define S_GATECHNRX0 6
28246 #define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
28247 #define F_GATECHNRX0 V_GATECHNRX0(1U)
28249 #define S_SLEEPRDYUTRN 4
28250 #define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
28251 #define F_SLEEPRDYUTRN V_SLEEPRDYUTRN(1U)
28253 #define S_SLEEPREQUTRN 0
28254 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
28255 #define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U)
28257 #define A_TP_TRC_CONFIG 0x244
28260 #define V_TRCRR(x) ((x) << S_TRCRR)
28261 #define F_TRCRR V_TRCRR(1U)
28264 #define V_TRCCH(x) ((x) << S_TRCCH)
28265 #define F_TRCCH V_TRCCH(1U)
28267 #define A_TP_TAG_CONFIG 0x245
28269 #define S_ETAGTYPE 16
28270 #define M_ETAGTYPE 0xffffU
28271 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
28272 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
28274 #define A_TP_DBG_CSIDE_PRS 0x246
28276 #define S_CPRSSTATE3 24
28277 #define M_CPRSSTATE3 0x7U
28278 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
28279 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
28281 #define S_CPRSSTATE2 16
28282 #define M_CPRSSTATE2 0x7U
28283 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
28284 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
28286 #define S_CPRSSTATE1 8
28287 #define M_CPRSSTATE1 0x7U
28288 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
28289 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
28291 #define S_CPRSSTATE0 0
28292 #define M_CPRSSTATE0 0x7U
28293 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
28294 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
28296 #define S_C4TUPBUSY3 31
28297 #define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
28298 #define F_C4TUPBUSY3 V_C4TUPBUSY3(1U)
28300 #define S_CDBVALID3 30
28301 #define V_CDBVALID3(x) ((x) << S_CDBVALID3)
28302 #define F_CDBVALID3 V_CDBVALID3(1U)
28304 #define S_CRXVALID3 29
28305 #define V_CRXVALID3(x) ((x) << S_CRXVALID3)
28306 #define F_CRXVALID3 V_CRXVALID3(1U)
28308 #define S_CRXFULL3 28
28309 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
28310 #define F_CRXFULL3 V_CRXFULL3(1U)
28312 #define S_T5_CPRSSTATE3 24
28313 #define M_T5_CPRSSTATE3 0xfU
28314 #define V_T5_CPRSSTATE3(x) ((x) << S_T5_CPRSSTATE3)
28315 #define G_T5_CPRSSTATE3(x) (((x) >> S_T5_CPRSSTATE3) & M_T5_CPRSSTATE3)
28317 #define S_C4TUPBUSY2 23
28318 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
28319 #define F_C4TUPBUSY2 V_C4TUPBUSY2(1U)
28321 #define S_CDBVALID2 22
28322 #define V_CDBVALID2(x) ((x) << S_CDBVALID2)
28323 #define F_CDBVALID2 V_CDBVALID2(1U)
28325 #define S_CRXVALID2 21
28326 #define V_CRXVALID2(x) ((x) << S_CRXVALID2)
28327 #define F_CRXVALID2 V_CRXVALID2(1U)
28329 #define S_CRXFULL2 20
28330 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
28331 #define F_CRXFULL2 V_CRXFULL2(1U)
28333 #define S_T5_CPRSSTATE2 16
28334 #define M_T5_CPRSSTATE2 0xfU
28335 #define V_T5_CPRSSTATE2(x) ((x) << S_T5_CPRSSTATE2)
28336 #define G_T5_CPRSSTATE2(x) (((x) >> S_T5_CPRSSTATE2) & M_T5_CPRSSTATE2)
28338 #define S_C4TUPBUSY1 15
28339 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
28340 #define F_C4TUPBUSY1 V_C4TUPBUSY1(1U)
28342 #define S_CDBVALID1 14
28343 #define V_CDBVALID1(x) ((x) << S_CDBVALID1)
28344 #define F_CDBVALID1 V_CDBVALID1(1U)
28346 #define S_CRXVALID1 13
28347 #define V_CRXVALID1(x) ((x) << S_CRXVALID1)
28348 #define F_CRXVALID1 V_CRXVALID1(1U)
28350 #define S_CRXFULL1 12
28351 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
28352 #define F_CRXFULL1 V_CRXFULL1(1U)
28354 #define S_T5_CPRSSTATE1 8
28355 #define M_T5_CPRSSTATE1 0xfU
28356 #define V_T5_CPRSSTATE1(x) ((x) << S_T5_CPRSSTATE1)
28357 #define G_T5_CPRSSTATE1(x) (((x) >> S_T5_CPRSSTATE1) & M_T5_CPRSSTATE1)
28359 #define S_C4TUPBUSY0 7
28360 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
28361 #define F_C4TUPBUSY0 V_C4TUPBUSY0(1U)
28363 #define S_CDBVALID0 6
28364 #define V_CDBVALID0(x) ((x) << S_CDBVALID0)
28365 #define F_CDBVALID0 V_CDBVALID0(1U)
28367 #define S_CRXVALID0 5
28368 #define V_CRXVALID0(x) ((x) << S_CRXVALID0)
28369 #define F_CRXVALID0 V_CRXVALID0(1U)
28371 #define S_CRXFULL0 4
28372 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
28373 #define F_CRXFULL0 V_CRXFULL0(1U)
28375 #define S_T5_CPRSSTATE0 0
28376 #define M_T5_CPRSSTATE0 0xfU
28377 #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
28378 #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
28380 #define S_T6_CPRSSTATE3 24
28381 #define M_T6_CPRSSTATE3 0xfU
28382 #define V_T6_CPRSSTATE3(x) ((x) << S_T6_CPRSSTATE3)
28383 #define G_T6_CPRSSTATE3(x) (((x) >> S_T6_CPRSSTATE3) & M_T6_CPRSSTATE3)
28385 #define S_T6_CPRSSTATE2 16
28386 #define M_T6_CPRSSTATE2 0xfU
28387 #define V_T6_CPRSSTATE2(x) ((x) << S_T6_CPRSSTATE2)
28388 #define G_T6_CPRSSTATE2(x) (((x) >> S_T6_CPRSSTATE2) & M_T6_CPRSSTATE2)
28390 #define S_T6_CPRSSTATE1 8
28391 #define M_T6_CPRSSTATE1 0xfU
28392 #define V_T6_CPRSSTATE1(x) ((x) << S_T6_CPRSSTATE1)
28393 #define G_T6_CPRSSTATE1(x) (((x) >> S_T6_CPRSSTATE1) & M_T6_CPRSSTATE1)
28395 #define S_T6_CPRSSTATE0 0
28396 #define M_T6_CPRSSTATE0 0xfU
28397 #define V_T6_CPRSSTATE0(x) ((x) << S_T6_CPRSSTATE0)
28398 #define G_T6_CPRSSTATE0(x) (((x) >> S_T6_CPRSSTATE0) & M_T6_CPRSSTATE0)
28400 #define A_TP_DBG_CSIDE_DEMUX 0x247
28402 #define S_CALLDONE 28
28403 #define M_CALLDONE 0xfU
28404 #define V_CALLDONE(x) ((x) << S_CALLDONE)
28405 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
28407 #define S_CTCPL5DONE 24
28408 #define M_CTCPL5DONE 0xfU
28409 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
28410 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
28412 #define S_CTXZEROPDONE 20
28413 #define M_CTXZEROPDONE 0xfU
28414 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
28415 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
28417 #define S_CPLDDONE 16
28418 #define M_CPLDDONE 0xfU
28419 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
28420 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
28422 #define S_CTTCPOPDONE 12
28423 #define M_CTTCPOPDONE 0xfU
28424 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
28425 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
28427 #define S_CDBDONE 8
28428 #define M_CDBDONE 0xfU
28429 #define V_CDBDONE(x) ((x) << S_CDBDONE)
28430 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
28432 #define S_CISSFIFODONE 4
28433 #define M_CISSFIFODONE 0xfU
28434 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
28435 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
28437 #define S_CTXPKTCSUMDONE 0
28438 #define M_CTXPKTCSUMDONE 0xfU
28439 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
28440 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
28442 #define S_CARBVALID 28
28443 #define M_CARBVALID 0xfU
28444 #define V_CARBVALID(x) ((x) << S_CARBVALID)
28445 #define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
28447 #define S_CCPL5DONE 24
28448 #define M_CCPL5DONE 0xfU
28449 #define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
28450 #define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
28452 #define S_CTCPOPDONE 12
28453 #define M_CTCPOPDONE 0xfU
28454 #define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
28455 #define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
28457 #define A_TP_DBG_CSIDE_ARBIT 0x248
28459 #define S_CPLVALID3 31
28460 #define V_CPLVALID3(x) ((x) << S_CPLVALID3)
28461 #define F_CPLVALID3 V_CPLVALID3(1U)
28463 #define S_PLDVALID3 30
28464 #define V_PLDVALID3(x) ((x) << S_PLDVALID3)
28465 #define F_PLDVALID3 V_PLDVALID3(1U)
28467 #define S_CRCVALID3 29
28468 #define V_CRCVALID3(x) ((x) << S_CRCVALID3)
28469 #define F_CRCVALID3 V_CRCVALID3(1U)
28471 #define S_ISSVALID3 28
28472 #define V_ISSVALID3(x) ((x) << S_ISSVALID3)
28473 #define F_ISSVALID3 V_ISSVALID3(1U)
28475 #define S_DBVALID3 27
28476 #define V_DBVALID3(x) ((x) << S_DBVALID3)
28477 #define F_DBVALID3 V_DBVALID3(1U)
28479 #define S_CHKVALID3 26
28480 #define V_CHKVALID3(x) ((x) << S_CHKVALID3)
28481 #define F_CHKVALID3 V_CHKVALID3(1U)
28483 #define S_ZRPVALID3 25
28484 #define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
28485 #define F_ZRPVALID3 V_ZRPVALID3(1U)
28487 #define S_ERRVALID3 24
28488 #define V_ERRVALID3(x) ((x) << S_ERRVALID3)
28489 #define F_ERRVALID3 V_ERRVALID3(1U)
28491 #define S_CPLVALID2 23
28492 #define V_CPLVALID2(x) ((x) << S_CPLVALID2)
28493 #define F_CPLVALID2 V_CPLVALID2(1U)
28495 #define S_PLDVALID2 22
28496 #define V_PLDVALID2(x) ((x) << S_PLDVALID2)
28497 #define F_PLDVALID2 V_PLDVALID2(1U)
28499 #define S_CRCVALID2 21
28500 #define V_CRCVALID2(x) ((x) << S_CRCVALID2)
28501 #define F_CRCVALID2 V_CRCVALID2(1U)
28503 #define S_ISSVALID2 20
28504 #define V_ISSVALID2(x) ((x) << S_ISSVALID2)
28505 #define F_ISSVALID2 V_ISSVALID2(1U)
28507 #define S_DBVALID2 19
28508 #define V_DBVALID2(x) ((x) << S_DBVALID2)
28509 #define F_DBVALID2 V_DBVALID2(1U)
28511 #define S_CHKVALID2 18
28512 #define V_CHKVALID2(x) ((x) << S_CHKVALID2)
28513 #define F_CHKVALID2 V_CHKVALID2(1U)
28515 #define S_ZRPVALID2 17
28516 #define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
28517 #define F_ZRPVALID2 V_ZRPVALID2(1U)
28519 #define S_ERRVALID2 16
28520 #define V_ERRVALID2(x) ((x) << S_ERRVALID2)
28521 #define F_ERRVALID2 V_ERRVALID2(1U)
28523 #define S_CPLVALID1 15
28524 #define V_CPLVALID1(x) ((x) << S_CPLVALID1)
28525 #define F_CPLVALID1 V_CPLVALID1(1U)
28527 #define S_PLDVALID1 14
28528 #define V_PLDVALID1(x) ((x) << S_PLDVALID1)
28529 #define F_PLDVALID1 V_PLDVALID1(1U)
28531 #define S_CRCVALID1 13
28532 #define V_CRCVALID1(x) ((x) << S_CRCVALID1)
28533 #define F_CRCVALID1 V_CRCVALID1(1U)
28535 #define S_ISSVALID1 12
28536 #define V_ISSVALID1(x) ((x) << S_ISSVALID1)
28537 #define F_ISSVALID1 V_ISSVALID1(1U)
28539 #define S_DBVALID1 11
28540 #define V_DBVALID1(x) ((x) << S_DBVALID1)
28541 #define F_DBVALID1 V_DBVALID1(1U)
28543 #define S_CHKVALID1 10
28544 #define V_CHKVALID1(x) ((x) << S_CHKVALID1)
28545 #define F_CHKVALID1 V_CHKVALID1(1U)
28547 #define S_ZRPVALID1 9
28548 #define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
28549 #define F_ZRPVALID1 V_ZRPVALID1(1U)
28551 #define S_ERRVALID1 8
28552 #define V_ERRVALID1(x) ((x) << S_ERRVALID1)
28553 #define F_ERRVALID1 V_ERRVALID1(1U)
28555 #define S_CPLVALID0 7
28556 #define V_CPLVALID0(x) ((x) << S_CPLVALID0)
28557 #define F_CPLVALID0 V_CPLVALID0(1U)
28559 #define S_PLDVALID0 6
28560 #define V_PLDVALID0(x) ((x) << S_PLDVALID0)
28561 #define F_PLDVALID0 V_PLDVALID0(1U)
28563 #define S_CRCVALID0 5
28564 #define V_CRCVALID0(x) ((x) << S_CRCVALID0)
28565 #define F_CRCVALID0 V_CRCVALID0(1U)
28567 #define S_ISSVALID0 4
28568 #define V_ISSVALID0(x) ((x) << S_ISSVALID0)
28569 #define F_ISSVALID0 V_ISSVALID0(1U)
28571 #define S_DBVALID0 3
28572 #define V_DBVALID0(x) ((x) << S_DBVALID0)
28573 #define F_DBVALID0 V_DBVALID0(1U)
28575 #define S_CHKVALID0 2
28576 #define V_CHKVALID0(x) ((x) << S_CHKVALID0)
28577 #define F_CHKVALID0 V_CHKVALID0(1U)
28579 #define S_ZRPVALID0 1
28580 #define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
28581 #define F_ZRPVALID0 V_ZRPVALID0(1U)
28583 #define S_ERRVALID0 0
28584 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
28585 #define F_ERRVALID0 V_ERRVALID0(1U)
28587 #define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
28589 #define S_TRCSOPCNT 24
28590 #define M_TRCSOPCNT 0xffU
28591 #define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT)
28592 #define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT)
28594 #define S_TRCEOPCNT 16
28595 #define M_TRCEOPCNT 0xffU
28596 #define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT)
28597 #define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT)
28599 #define S_TRCFLTHIT 12
28600 #define M_TRCFLTHIT 0xfU
28601 #define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT)
28602 #define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT)
28604 #define S_TRCRNTPKT 8
28605 #define M_TRCRNTPKT 0xfU
28606 #define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT)
28607 #define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT)
28609 #define S_TRCPKTLEN 0
28610 #define M_TRCPKTLEN 0xffU
28611 #define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN)
28612 #define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN)
28614 #define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
28615 #define A_TP_VLN_CONFIG 0x24c
28617 #define S_ETHTYPEQINQ 16
28618 #define M_ETHTYPEQINQ 0xffffU
28619 #define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ)
28620 #define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ)
28622 #define S_ETHTYPEVLAN 0
28623 #define M_ETHTYPEVLAN 0xffffU
28624 #define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN)
28625 #define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN)
28627 #define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
28628 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
28629 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
28630 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
28631 #define A_TP_FIFO_CONFIG 0x8c0
28633 #define S_CH1_OUTPUT 27
28634 #define M_CH1_OUTPUT 0x1fU
28635 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
28636 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
28638 #define S_CH2_OUTPUT 22
28639 #define M_CH2_OUTPUT 0x1fU
28640 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
28641 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
28643 #define S_STROBE1 16
28644 #define V_STROBE1(x) ((x) << S_STROBE1)
28645 #define F_STROBE1 V_STROBE1(1U)
28647 #define S_CH1_INPUT 11
28648 #define M_CH1_INPUT 0x1fU
28649 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
28650 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
28652 #define S_CH2_INPUT 6
28653 #define M_CH2_INPUT 0x1fU
28654 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
28655 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
28657 #define S_CH3_INPUT 1
28658 #define M_CH3_INPUT 0x1fU
28659 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
28660 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
28662 #define S_STROBE0 0
28663 #define V_STROBE0(x) ((x) << S_STROBE0)
28664 #define F_STROBE0 V_STROBE0(1U)
28666 #define A_TP_MIB_MAC_IN_ERR_0 0x0
28667 #define A_TP_MIB_MAC_IN_ERR_1 0x1
28668 #define A_TP_MIB_MAC_IN_ERR_2 0x2
28669 #define A_TP_MIB_MAC_IN_ERR_3 0x3
28670 #define A_TP_MIB_HDR_IN_ERR_0 0x4
28671 #define A_TP_MIB_HDR_IN_ERR_1 0x5
28672 #define A_TP_MIB_HDR_IN_ERR_2 0x6
28673 #define A_TP_MIB_HDR_IN_ERR_3 0x7
28674 #define A_TP_MIB_TCP_IN_ERR_0 0x8
28675 #define A_TP_MIB_TCP_IN_ERR_1 0x9
28676 #define A_TP_MIB_TCP_IN_ERR_2 0xa
28677 #define A_TP_MIB_TCP_IN_ERR_3 0xb
28678 #define A_TP_MIB_TCP_OUT_RST 0xc
28679 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
28680 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
28681 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
28682 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
28683 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
28684 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
28685 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
28686 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
28687 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
28688 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
28689 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
28690 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
28691 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
28692 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
28693 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
28694 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
28695 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
28696 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
28697 #define A_TP_MIB_TNL_IN_PKT_0 0x24
28698 #define A_TP_MIB_TNL_IN_PKT_1 0x25
28699 #define A_TP_MIB_TNL_IN_PKT_2 0x26
28700 #define A_TP_MIB_TNL_IN_PKT_3 0x27
28701 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
28702 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
28703 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
28704 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
28705 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
28706 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
28707 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
28708 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
28709 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
28710 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
28711 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
28712 #define A_TP_MIB_OFD_ARP_DROP 0x36
28713 #define A_TP_MIB_OFD_DFR_DROP 0x37
28714 #define A_TP_MIB_CPL_IN_REQ_0 0x38
28715 #define A_TP_MIB_CPL_IN_REQ_1 0x39
28716 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
28717 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
28718 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
28719 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
28720 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
28721 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
28722 #define A_TP_MIB_TNL_LPBK_0 0x40
28723 #define A_TP_MIB_TNL_LPBK_1 0x41
28724 #define A_TP_MIB_TNL_LPBK_2 0x42
28725 #define A_TP_MIB_TNL_LPBK_3 0x43
28726 #define A_TP_MIB_TNL_DROP_0 0x44
28727 #define A_TP_MIB_TNL_DROP_1 0x45
28728 #define A_TP_MIB_TNL_DROP_2 0x46
28729 #define A_TP_MIB_TNL_DROP_3 0x47
28730 #define A_TP_MIB_FCOE_DDP_0 0x48
28731 #define A_TP_MIB_FCOE_DDP_1 0x49
28732 #define A_TP_MIB_FCOE_DDP_2 0x4a
28733 #define A_TP_MIB_FCOE_DDP_3 0x4b
28734 #define A_TP_MIB_FCOE_DROP_0 0x4c
28735 #define A_TP_MIB_FCOE_DROP_1 0x4d
28736 #define A_TP_MIB_FCOE_DROP_2 0x4e
28737 #define A_TP_MIB_FCOE_DROP_3 0x4f
28738 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
28739 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
28740 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
28741 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
28742 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
28743 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
28744 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
28745 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
28746 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
28747 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
28748 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
28749 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
28750 #define A_TP_MIB_USM_PKTS 0x5c
28751 #define A_TP_MIB_USM_DROP 0x5d
28752 #define A_TP_MIB_USM_BYTES_HI 0x5e
28753 #define A_TP_MIB_USM_BYTES_LO 0x5f
28754 #define A_TP_MIB_TID_DEL 0x60
28755 #define A_TP_MIB_TID_INV 0x61
28756 #define A_TP_MIB_TID_ACT 0x62
28757 #define A_TP_MIB_TID_PAS 0x63
28758 #define A_TP_MIB_RQE_DFR_PKT 0x64
28759 #define A_TP_MIB_RQE_DFR_MOD 0x65
28760 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
28761 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
28762 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
28763 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
28764 #define A_TP_MIB_ENG_LINE_0 0x6c
28765 #define A_TP_MIB_ENG_LINE_1 0x6d
28766 #define A_TP_MIB_ENG_LINE_2 0x6e
28767 #define A_TP_MIB_ENG_LINE_3 0x6f
28768 #define A_TP_MIB_TNL_ERR_0 0x70
28769 #define A_TP_MIB_TNL_ERR_1 0x71
28770 #define A_TP_MIB_TNL_ERR_2 0x72
28771 #define A_TP_MIB_TNL_ERR_3 0x73
28773 /* registers for module ULP_TX */
28774 #define ULP_TX_BASE_ADDR 0x8dc0
28776 #define A_ULP_TX_CONFIG 0x8dc0
28778 #define S_STAG_MIX_ENABLE 2
28779 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
28780 #define F_STAG_MIX_ENABLE V_STAG_MIX_ENABLE(1U)
28782 #define S_STAGF_FIX_DISABLE 1
28783 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
28784 #define F_STAGF_FIX_DISABLE V_STAGF_FIX_DISABLE(1U)
28786 #define S_EXTRA_TAG_INSERTION_ENABLE 0
28787 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
28788 #define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U)
28790 #define S_PHYS_ADDR_RESP_EN 6
28791 #define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
28792 #define F_PHYS_ADDR_RESP_EN V_PHYS_ADDR_RESP_EN(1U)
28794 #define S_ENDIANESS_CHANGE 5
28795 #define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
28796 #define F_ENDIANESS_CHANGE V_ENDIANESS_CHANGE(1U)
28798 #define S_ERR_RTAG_EN 4
28799 #define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
28800 #define F_ERR_RTAG_EN V_ERR_RTAG_EN(1U)
28802 #define S_TSO_ETHLEN_EN 3
28803 #define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
28804 #define F_TSO_ETHLEN_EN V_TSO_ETHLEN_EN(1U)
28806 #define S_EMSG_MORE_INFO 2
28807 #define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
28808 #define F_EMSG_MORE_INFO V_EMSG_MORE_INFO(1U)
28811 #define V_LOSDR(x) ((x) << S_LOSDR)
28812 #define F_LOSDR V_LOSDR(1U)
28814 #define S_ULIMIT_EXCLUSIVE_FIX 16
28815 #define V_ULIMIT_EXCLUSIVE_FIX(x) ((x) << S_ULIMIT_EXCLUSIVE_FIX)
28816 #define F_ULIMIT_EXCLUSIVE_FIX V_ULIMIT_EXCLUSIVE_FIX(1U)
28818 #define S_ISO_A_FLAG_EN 15
28819 #define V_ISO_A_FLAG_EN(x) ((x) << S_ISO_A_FLAG_EN)
28820 #define F_ISO_A_FLAG_EN V_ISO_A_FLAG_EN(1U)
28822 #define S_IWARP_SEQ_FLIT_DIS 14
28823 #define V_IWARP_SEQ_FLIT_DIS(x) ((x) << S_IWARP_SEQ_FLIT_DIS)
28824 #define F_IWARP_SEQ_FLIT_DIS V_IWARP_SEQ_FLIT_DIS(1U)
28826 #define S_MR_SIZE_FIX_EN 13
28827 #define V_MR_SIZE_FIX_EN(x) ((x) << S_MR_SIZE_FIX_EN)
28828 #define F_MR_SIZE_FIX_EN V_MR_SIZE_FIX_EN(1U)
28830 #define S_T10_ISO_FIX_EN 12
28831 #define V_T10_ISO_FIX_EN(x) ((x) << S_T10_ISO_FIX_EN)
28832 #define F_T10_ISO_FIX_EN V_T10_ISO_FIX_EN(1U)
28834 #define S_CPL_FLAGS_UPDATE_EN 11
28835 #define V_CPL_FLAGS_UPDATE_EN(x) ((x) << S_CPL_FLAGS_UPDATE_EN)
28836 #define F_CPL_FLAGS_UPDATE_EN V_CPL_FLAGS_UPDATE_EN(1U)
28838 #define S_IWARP_SEQ_UPDATE_EN 10
28839 #define V_IWARP_SEQ_UPDATE_EN(x) ((x) << S_IWARP_SEQ_UPDATE_EN)
28840 #define F_IWARP_SEQ_UPDATE_EN V_IWARP_SEQ_UPDATE_EN(1U)
28842 #define S_SEQ_UPDATE_EN 9
28843 #define V_SEQ_UPDATE_EN(x) ((x) << S_SEQ_UPDATE_EN)
28844 #define F_SEQ_UPDATE_EN V_SEQ_UPDATE_EN(1U)
28846 #define S_ERR_ITT_EN 8
28847 #define V_ERR_ITT_EN(x) ((x) << S_ERR_ITT_EN)
28848 #define F_ERR_ITT_EN V_ERR_ITT_EN(1U)
28850 #define S_ATOMIC_FIX_DIS 7
28851 #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
28852 #define F_ATOMIC_FIX_DIS V_ATOMIC_FIX_DIS(1U)
28854 #define A_ULP_TX_PERR_INJECT 0x8dc4
28855 #define A_ULP_TX_INT_ENABLE 0x8dc8
28857 #define S_PBL_BOUND_ERR_CH3 31
28858 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
28859 #define F_PBL_BOUND_ERR_CH3 V_PBL_BOUND_ERR_CH3(1U)
28861 #define S_PBL_BOUND_ERR_CH2 30
28862 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
28863 #define F_PBL_BOUND_ERR_CH2 V_PBL_BOUND_ERR_CH2(1U)
28865 #define S_PBL_BOUND_ERR_CH1 29
28866 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
28867 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
28869 #define S_PBL_BOUND_ERR_CH0 28
28870 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
28871 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
28873 #define S_SGE2ULP_FIFO_PERR_SET3 27
28874 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
28875 #define F_SGE2ULP_FIFO_PERR_SET3 V_SGE2ULP_FIFO_PERR_SET3(1U)
28877 #define S_SGE2ULP_FIFO_PERR_SET2 26
28878 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
28879 #define F_SGE2ULP_FIFO_PERR_SET2 V_SGE2ULP_FIFO_PERR_SET2(1U)
28881 #define S_SGE2ULP_FIFO_PERR_SET1 25
28882 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
28883 #define F_SGE2ULP_FIFO_PERR_SET1 V_SGE2ULP_FIFO_PERR_SET1(1U)
28885 #define S_SGE2ULP_FIFO_PERR_SET0 24
28886 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
28887 #define F_SGE2ULP_FIFO_PERR_SET0 V_SGE2ULP_FIFO_PERR_SET0(1U)
28889 #define S_CIM2ULP_FIFO_PERR_SET3 23
28890 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
28891 #define F_CIM2ULP_FIFO_PERR_SET3 V_CIM2ULP_FIFO_PERR_SET3(1U)
28893 #define S_CIM2ULP_FIFO_PERR_SET2 22
28894 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
28895 #define F_CIM2ULP_FIFO_PERR_SET2 V_CIM2ULP_FIFO_PERR_SET2(1U)
28897 #define S_CIM2ULP_FIFO_PERR_SET1 21
28898 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
28899 #define F_CIM2ULP_FIFO_PERR_SET1 V_CIM2ULP_FIFO_PERR_SET1(1U)
28901 #define S_CIM2ULP_FIFO_PERR_SET0 20
28902 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
28903 #define F_CIM2ULP_FIFO_PERR_SET0 V_CIM2ULP_FIFO_PERR_SET0(1U)
28905 #define S_CQE_FIFO_PERR_SET3 19
28906 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
28907 #define F_CQE_FIFO_PERR_SET3 V_CQE_FIFO_PERR_SET3(1U)
28909 #define S_CQE_FIFO_PERR_SET2 18
28910 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
28911 #define F_CQE_FIFO_PERR_SET2 V_CQE_FIFO_PERR_SET2(1U)
28913 #define S_CQE_FIFO_PERR_SET1 17
28914 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
28915 #define F_CQE_FIFO_PERR_SET1 V_CQE_FIFO_PERR_SET1(1U)
28917 #define S_CQE_FIFO_PERR_SET0 16
28918 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
28919 #define F_CQE_FIFO_PERR_SET0 V_CQE_FIFO_PERR_SET0(1U)
28921 #define S_PBL_FIFO_PERR_SET3 15
28922 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
28923 #define F_PBL_FIFO_PERR_SET3 V_PBL_FIFO_PERR_SET3(1U)
28925 #define S_PBL_FIFO_PERR_SET2 14
28926 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
28927 #define F_PBL_FIFO_PERR_SET2 V_PBL_FIFO_PERR_SET2(1U)
28929 #define S_PBL_FIFO_PERR_SET1 13
28930 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
28931 #define F_PBL_FIFO_PERR_SET1 V_PBL_FIFO_PERR_SET1(1U)
28933 #define S_PBL_FIFO_PERR_SET0 12
28934 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
28935 #define F_PBL_FIFO_PERR_SET0 V_PBL_FIFO_PERR_SET0(1U)
28937 #define S_CMD_FIFO_PERR_SET3 11
28938 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
28939 #define F_CMD_FIFO_PERR_SET3 V_CMD_FIFO_PERR_SET3(1U)
28941 #define S_CMD_FIFO_PERR_SET2 10
28942 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
28943 #define F_CMD_FIFO_PERR_SET2 V_CMD_FIFO_PERR_SET2(1U)
28945 #define S_CMD_FIFO_PERR_SET1 9
28946 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
28947 #define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U)
28949 #define S_CMD_FIFO_PERR_SET0 8
28950 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
28951 #define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U)
28953 #define S_LSO_HDR_SRAM_PERR_SET3 7
28954 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
28955 #define F_LSO_HDR_SRAM_PERR_SET3 V_LSO_HDR_SRAM_PERR_SET3(1U)
28957 #define S_LSO_HDR_SRAM_PERR_SET2 6
28958 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
28959 #define F_LSO_HDR_SRAM_PERR_SET2 V_LSO_HDR_SRAM_PERR_SET2(1U)
28961 #define S_LSO_HDR_SRAM_PERR_SET1 5
28962 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
28963 #define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U)
28965 #define S_LSO_HDR_SRAM_PERR_SET0 4
28966 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
28967 #define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U)
28969 #define S_IMM_DATA_PERR_SET_CH3 3
28970 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
28971 #define F_IMM_DATA_PERR_SET_CH3 V_IMM_DATA_PERR_SET_CH3(1U)
28973 #define S_IMM_DATA_PERR_SET_CH2 2
28974 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
28975 #define F_IMM_DATA_PERR_SET_CH2 V_IMM_DATA_PERR_SET_CH2(1U)
28977 #define S_IMM_DATA_PERR_SET_CH1 1
28978 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
28979 #define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U)
28981 #define S_IMM_DATA_PERR_SET_CH0 0
28982 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
28983 #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U)
28985 #define A_ULP_TX_INT_CAUSE 0x8dcc
28986 #define A_ULP_TX_PERR_ENABLE 0x8dd0
28987 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
28988 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
28989 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
28990 #define A_ULP_TX_PBL_ULIMIT 0x8de0
28991 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
28992 #define A_ULP_TX_TLS_CTL 0x8de4
28994 #define S_TLSPERREN 4
28995 #define V_TLSPERREN(x) ((x) << S_TLSPERREN)
28996 #define F_TLSPERREN V_TLSPERREN(1U)
28998 #define S_TLSPATHCTL 3
28999 #define V_TLSPATHCTL(x) ((x) << S_TLSPATHCTL)
29000 #define F_TLSPATHCTL V_TLSPATHCTL(1U)
29002 #define S_TLSDISABLEIFUSE 2
29003 #define V_TLSDISABLEIFUSE(x) ((x) << S_TLSDISABLEIFUSE)
29004 #define F_TLSDISABLEIFUSE V_TLSDISABLEIFUSE(1U)
29006 #define S_TLSDISABLECFUSE 1
29007 #define V_TLSDISABLECFUSE(x) ((x) << S_TLSDISABLECFUSE)
29008 #define F_TLSDISABLECFUSE V_TLSDISABLECFUSE(1U)
29010 #define S_TLSDISABLE 0
29011 #define V_TLSDISABLE(x) ((x) << S_TLSDISABLE)
29012 #define F_TLSDISABLE V_TLSDISABLE(1U)
29014 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
29015 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
29016 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
29017 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
29018 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
29020 #define S_CH3SIZE1 24
29021 #define M_CH3SIZE1 0xffU
29022 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
29023 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
29025 #define S_CH2SIZE1 16
29026 #define M_CH2SIZE1 0xffU
29027 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
29028 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
29030 #define S_CH1SIZE1 8
29031 #define M_CH1SIZE1 0xffU
29032 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
29033 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
29035 #define S_CH0SIZE1 0
29036 #define M_CH0SIZE1 0xffU
29037 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
29038 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
29040 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
29042 #define S_CH3SIZE2 24
29043 #define M_CH3SIZE2 0xffU
29044 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
29045 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
29047 #define S_CH2SIZE2 16
29048 #define M_CH2SIZE2 0xffU
29049 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
29050 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
29052 #define S_CH1SIZE2 8
29053 #define M_CH1SIZE2 0xffU
29054 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
29055 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
29057 #define S_CH0SIZE2 0
29058 #define M_CH0SIZE2 0xffU
29059 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
29060 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
29062 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
29063 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
29064 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
29066 #define S_ERR_CNT0 0
29067 #define M_ERR_CNT0 0xfffffU
29068 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
29069 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
29071 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
29073 #define S_ERR_CNT1 0
29074 #define M_ERR_CNT1 0xfffffU
29075 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
29076 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
29078 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
29080 #define S_ERR_CNT2 0
29081 #define M_ERR_CNT2 0xfffffU
29082 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
29083 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
29085 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
29087 #define S_ERR_CNT3 0
29088 #define M_ERR_CNT3 0xfffffU
29089 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
29090 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
29092 #define A_ULP_TX_FC_SOF 0x8e20
29094 #define S_SOF_FS3 24
29095 #define M_SOF_FS3 0xffU
29096 #define V_SOF_FS3(x) ((x) << S_SOF_FS3)
29097 #define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
29099 #define S_SOF_FS2 16
29100 #define M_SOF_FS2 0xffU
29101 #define V_SOF_FS2(x) ((x) << S_SOF_FS2)
29102 #define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
29105 #define M_SOF_3 0xffU
29106 #define V_SOF_3(x) ((x) << S_SOF_3)
29107 #define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
29110 #define M_SOF_2 0xffU
29111 #define V_SOF_2(x) ((x) << S_SOF_2)
29112 #define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
29114 #define A_ULP_TX_FC_EOF 0x8e24
29116 #define S_EOF_LS3 24
29117 #define M_EOF_LS3 0xffU
29118 #define V_EOF_LS3(x) ((x) << S_EOF_LS3)
29119 #define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
29121 #define S_EOF_LS2 16
29122 #define M_EOF_LS2 0xffU
29123 #define V_EOF_LS2(x) ((x) << S_EOF_LS2)
29124 #define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
29127 #define M_EOF_3 0xffU
29128 #define V_EOF_3(x) ((x) << S_EOF_3)
29129 #define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
29132 #define M_EOF_2 0xffU
29133 #define V_EOF_2(x) ((x) << S_EOF_2)
29134 #define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
29136 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
29138 #define S_ULP_TX_GLOBAL_CGEN 0
29139 #define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
29140 #define F_ULP_TX_GLOBAL_CGEN V_ULP_TX_GLOBAL_CGEN(1U)
29142 #define A_ULP_TX_CGEN 0x8e2c
29144 #define S_ULP_TX_CGEN_STORAGE 8
29145 #define M_ULP_TX_CGEN_STORAGE 0xfU
29146 #define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
29147 #define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
29149 #define S_ULP_TX_CGEN_RDMA 4
29150 #define M_ULP_TX_CGEN_RDMA 0xfU
29151 #define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
29152 #define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
29154 #define S_ULP_TX_CGEN_CHANNEL 0
29155 #define M_ULP_TX_CGEN_CHANNEL 0xfU
29156 #define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
29157 #define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
29159 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
29160 #define A_ULP_TX_MEM_CFG 0x8e30
29162 #define S_WRREQ_SZ 0
29163 #define M_WRREQ_SZ 0x7U
29164 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
29165 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
29167 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
29168 #define A_ULP_TX_PERR_INJECT_2 0x8e34
29170 #define S_T5_MEMSEL 1
29171 #define M_T5_MEMSEL 0x7U
29172 #define V_T5_MEMSEL(x) ((x) << S_T5_MEMSEL)
29173 #define G_T5_MEMSEL(x) (((x) >> S_T5_MEMSEL) & M_T5_MEMSEL)
29175 #define S_MEMSEL_ULPTX 1
29176 #define M_MEMSEL_ULPTX 0x1fU
29177 #define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX)
29178 #define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX)
29180 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
29181 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
29183 #define S_CHANNEL_SEL 12
29184 #define M_CHANNEL_SEL 0x3U
29185 #define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
29186 #define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
29188 #define S_INTF_SEL 4
29189 #define M_INTF_SEL 0xfU
29190 #define V_INTF_SEL(x) ((x) << S_INTF_SEL)
29191 #define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
29193 #define S_NUM_FLITS 1
29194 #define M_NUM_FLITS 0x7U
29195 #define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
29196 #define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
29198 #define S_CMD_GEN_EN 0
29199 #define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
29200 #define F_CMD_GEN_EN V_CMD_GEN_EN(1U)
29202 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
29203 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
29204 #define A_ULP_TX_FPGA_CMD_1 0x8e40
29205 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
29206 #define A_ULP_TX_FPGA_CMD_2 0x8e44
29207 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
29208 #define A_ULP_TX_FPGA_CMD_3 0x8e48
29209 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
29210 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
29211 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
29212 #define A_ULP_TX_FPGA_CMD_5 0x8e50
29213 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
29214 #define A_ULP_TX_FPGA_CMD_6 0x8e54
29215 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
29216 #define A_ULP_TX_FPGA_CMD_7 0x8e58
29217 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
29218 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
29219 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
29220 #define A_ULP_TX_FPGA_CMD_9 0x8e60
29221 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
29222 #define A_ULP_TX_FPGA_CMD_10 0x8e64
29223 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
29224 #define A_ULP_TX_FPGA_CMD_11 0x8e68
29225 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
29226 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
29227 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
29228 #define A_ULP_TX_FPGA_CMD_13 0x8e70
29229 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
29230 #define A_ULP_TX_FPGA_CMD_14 0x8e74
29231 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
29232 #define A_ULP_TX_FPGA_CMD_15 0x8e78
29233 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
29234 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
29236 #define S_SMARBT2ULP_DATA_PERR_SET 12
29237 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
29238 #define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U)
29240 #define S_ULP2TP_DATA_PERR_SET 11
29241 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
29242 #define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U)
29244 #define S_MA2ULP_DATA_PERR_SET 10
29245 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
29246 #define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U)
29248 #define S_SGE2ULP_DATA_PERR_SET 9
29249 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
29250 #define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U)
29252 #define S_CIM2ULP_DATA_PERR_SET 8
29253 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
29254 #define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U)
29256 #define S_FSO_HDR_SRAM_PERR_SET3 7
29257 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
29258 #define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U)
29260 #define S_FSO_HDR_SRAM_PERR_SET2 6
29261 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
29262 #define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U)
29264 #define S_FSO_HDR_SRAM_PERR_SET1 5
29265 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
29266 #define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U)
29268 #define S_FSO_HDR_SRAM_PERR_SET0 4
29269 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
29270 #define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U)
29272 #define S_T10_PI_SRAM_PERR_SET3 3
29273 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
29274 #define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U)
29276 #define S_T10_PI_SRAM_PERR_SET2 2
29277 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
29278 #define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U)
29280 #define S_T10_PI_SRAM_PERR_SET1 1
29281 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
29282 #define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U)
29284 #define S_T10_PI_SRAM_PERR_SET0 0
29285 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
29286 #define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U)
29288 #define S_EDMA_IN_FIFO_PERR_SET3 31
29289 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
29290 #define F_EDMA_IN_FIFO_PERR_SET3 V_EDMA_IN_FIFO_PERR_SET3(1U)
29292 #define S_EDMA_IN_FIFO_PERR_SET2 30
29293 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
29294 #define F_EDMA_IN_FIFO_PERR_SET2 V_EDMA_IN_FIFO_PERR_SET2(1U)
29296 #define S_EDMA_IN_FIFO_PERR_SET1 29
29297 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
29298 #define F_EDMA_IN_FIFO_PERR_SET1 V_EDMA_IN_FIFO_PERR_SET1(1U)
29300 #define S_EDMA_IN_FIFO_PERR_SET0 28
29301 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
29302 #define F_EDMA_IN_FIFO_PERR_SET0 V_EDMA_IN_FIFO_PERR_SET0(1U)
29304 #define S_ALIGN_CTL_FIFO_PERR_SET3 27
29305 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
29306 #define F_ALIGN_CTL_FIFO_PERR_SET3 V_ALIGN_CTL_FIFO_PERR_SET3(1U)
29308 #define S_ALIGN_CTL_FIFO_PERR_SET2 26
29309 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
29310 #define F_ALIGN_CTL_FIFO_PERR_SET2 V_ALIGN_CTL_FIFO_PERR_SET2(1U)
29312 #define S_ALIGN_CTL_FIFO_PERR_SET1 25
29313 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
29314 #define F_ALIGN_CTL_FIFO_PERR_SET1 V_ALIGN_CTL_FIFO_PERR_SET1(1U)
29316 #define S_ALIGN_CTL_FIFO_PERR_SET0 24
29317 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
29318 #define F_ALIGN_CTL_FIFO_PERR_SET0 V_ALIGN_CTL_FIFO_PERR_SET0(1U)
29320 #define S_SGE_FIFO_PERR_SET3 23
29321 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
29322 #define F_SGE_FIFO_PERR_SET3 V_SGE_FIFO_PERR_SET3(1U)
29324 #define S_SGE_FIFO_PERR_SET2 22
29325 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
29326 #define F_SGE_FIFO_PERR_SET2 V_SGE_FIFO_PERR_SET2(1U)
29328 #define S_SGE_FIFO_PERR_SET1 21
29329 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
29330 #define F_SGE_FIFO_PERR_SET1 V_SGE_FIFO_PERR_SET1(1U)
29332 #define S_SGE_FIFO_PERR_SET0 20
29333 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
29334 #define F_SGE_FIFO_PERR_SET0 V_SGE_FIFO_PERR_SET0(1U)
29336 #define S_STAG_FIFO_PERR_SET3 19
29337 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
29338 #define F_STAG_FIFO_PERR_SET3 V_STAG_FIFO_PERR_SET3(1U)
29340 #define S_STAG_FIFO_PERR_SET2 18
29341 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
29342 #define F_STAG_FIFO_PERR_SET2 V_STAG_FIFO_PERR_SET2(1U)
29344 #define S_STAG_FIFO_PERR_SET1 17
29345 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
29346 #define F_STAG_FIFO_PERR_SET1 V_STAG_FIFO_PERR_SET1(1U)
29348 #define S_STAG_FIFO_PERR_SET0 16
29349 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
29350 #define F_STAG_FIFO_PERR_SET0 V_STAG_FIFO_PERR_SET0(1U)
29352 #define S_MAP_FIFO_PERR_SET3 15
29353 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
29354 #define F_MAP_FIFO_PERR_SET3 V_MAP_FIFO_PERR_SET3(1U)
29356 #define S_MAP_FIFO_PERR_SET2 14
29357 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
29358 #define F_MAP_FIFO_PERR_SET2 V_MAP_FIFO_PERR_SET2(1U)
29360 #define S_MAP_FIFO_PERR_SET1 13
29361 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
29362 #define F_MAP_FIFO_PERR_SET1 V_MAP_FIFO_PERR_SET1(1U)
29364 #define S_MAP_FIFO_PERR_SET0 12
29365 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
29366 #define F_MAP_FIFO_PERR_SET0 V_MAP_FIFO_PERR_SET0(1U)
29368 #define S_DMA_FIFO_PERR_SET3 11
29369 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
29370 #define F_DMA_FIFO_PERR_SET3 V_DMA_FIFO_PERR_SET3(1U)
29372 #define S_DMA_FIFO_PERR_SET2 10
29373 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
29374 #define F_DMA_FIFO_PERR_SET2 V_DMA_FIFO_PERR_SET2(1U)
29376 #define S_DMA_FIFO_PERR_SET1 9
29377 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
29378 #define F_DMA_FIFO_PERR_SET1 V_DMA_FIFO_PERR_SET1(1U)
29380 #define S_DMA_FIFO_PERR_SET0 8
29381 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
29382 #define F_DMA_FIFO_PERR_SET0 V_DMA_FIFO_PERR_SET0(1U)
29384 #define A_ULP_TX_INT_CAUSE_2 0x8e80
29385 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
29386 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
29388 #define S_ERR_CH3 12
29389 #define M_ERR_CH3 0xfU
29390 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
29391 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
29393 #define S_ERR_CH2 8
29394 #define M_ERR_CH2 0xfU
29395 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
29396 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
29398 #define S_ERR_CH1 4
29399 #define M_ERR_CH1 0xfU
29400 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
29401 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
29403 #define S_ERR_CH0 0
29404 #define M_ERR_CH0 0xfU
29405 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
29406 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
29408 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
29409 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
29411 #define S_CLR_DROP 16
29412 #define M_CLR_DROP 0xfU
29413 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
29414 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
29416 #define S_CLR_CH3 12
29417 #define M_CLR_CH3 0xfU
29418 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
29419 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
29421 #define S_CLR_CH2 8
29422 #define M_CLR_CH2 0xfU
29423 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
29424 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
29426 #define S_CLR_CH1 4
29427 #define M_CLR_CH1 0xfU
29428 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
29429 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
29431 #define S_CLR_CH0 0
29432 #define M_CLR_CH0 0xfU
29433 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
29434 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
29436 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
29437 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
29439 #define S_SOP_CNT_ULP2TP 28
29440 #define M_SOP_CNT_ULP2TP 0xfU
29441 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
29442 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
29444 #define S_EOP_CNT_ULP2TP 24
29445 #define M_EOP_CNT_ULP2TP 0xfU
29446 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
29447 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
29449 #define S_SOP_CNT_LSO_IN 20
29450 #define M_SOP_CNT_LSO_IN 0xfU
29451 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
29452 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
29454 #define S_EOP_CNT_LSO_IN 16
29455 #define M_EOP_CNT_LSO_IN 0xfU
29456 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
29457 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
29459 #define S_SOP_CNT_ALG_IN 12
29460 #define M_SOP_CNT_ALG_IN 0xfU
29461 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
29462 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
29464 #define S_EOP_CNT_ALG_IN 8
29465 #define M_EOP_CNT_ALG_IN 0xfU
29466 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
29467 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
29469 #define S_SOP_CNT_CIM2ULP 4
29470 #define M_SOP_CNT_CIM2ULP 0xfU
29471 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
29472 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
29474 #define S_EOP_CNT_CIM2ULP 0
29475 #define M_EOP_CNT_CIM2ULP 0xfU
29476 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
29477 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
29479 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
29480 #define A_ULP_TX_SE_CNT_CH1 0x8eac
29481 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
29482 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
29483 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
29484 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
29485 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
29486 #define A_ULP_TX_DROP_CNT 0x8eb8
29488 #define S_DROP_CH3 12
29489 #define M_DROP_CH3 0xfU
29490 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
29491 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
29493 #define S_DROP_CH2 8
29494 #define M_DROP_CH2 0xfU
29495 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
29496 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
29498 #define S_DROP_CH1 4
29499 #define M_DROP_CH1 0xfU
29500 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
29501 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
29503 #define S_DROP_CH0 0
29504 #define M_DROP_CH0 0xfU
29505 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
29506 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
29508 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
29510 #define S_DROP_INVLD_MC_CH3 28
29511 #define M_DROP_INVLD_MC_CH3 0xfU
29512 #define V_DROP_INVLD_MC_CH3(x) ((x) << S_DROP_INVLD_MC_CH3)
29513 #define G_DROP_INVLD_MC_CH3(x) (((x) >> S_DROP_INVLD_MC_CH3) & M_DROP_INVLD_MC_CH3)
29515 #define S_DROP_INVLD_MC_CH2 24
29516 #define M_DROP_INVLD_MC_CH2 0xfU
29517 #define V_DROP_INVLD_MC_CH2(x) ((x) << S_DROP_INVLD_MC_CH2)
29518 #define G_DROP_INVLD_MC_CH2(x) (((x) >> S_DROP_INVLD_MC_CH2) & M_DROP_INVLD_MC_CH2)
29520 #define S_DROP_INVLD_MC_CH1 20
29521 #define M_DROP_INVLD_MC_CH1 0xfU
29522 #define V_DROP_INVLD_MC_CH1(x) ((x) << S_DROP_INVLD_MC_CH1)
29523 #define G_DROP_INVLD_MC_CH1(x) (((x) >> S_DROP_INVLD_MC_CH1) & M_DROP_INVLD_MC_CH1)
29525 #define S_DROP_INVLD_MC_CH0 16
29526 #define M_DROP_INVLD_MC_CH0 0xfU
29527 #define V_DROP_INVLD_MC_CH0(x) ((x) << S_DROP_INVLD_MC_CH0)
29528 #define G_DROP_INVLD_MC_CH0(x) (((x) >> S_DROP_INVLD_MC_CH0) & M_DROP_INVLD_MC_CH0)
29530 #define A_ULP_TX_CSU_REVISION 0x8ebc
29531 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
29532 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
29533 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
29534 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
29535 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
29536 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
29537 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
29538 #define A_ULP_TX_LA_RESERVED_1 0x8edc
29539 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
29540 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
29541 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
29542 #define A_ULP_TX_LA_RESERVED_2 0x8eec
29543 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
29544 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
29545 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
29546 #define A_ULP_TX_LA_RESERVED_3 0x8efc
29547 #define A_ULP_TX_LA_RDPTR_4 0x8f00
29548 #define A_ULP_TX_LA_RDDATA_4 0x8f04
29549 #define A_ULP_TX_LA_WRPTR_4 0x8f08
29550 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
29551 #define A_ULP_TX_LA_RDPTR_5 0x8f10
29552 #define A_ULP_TX_LA_RDDATA_5 0x8f14
29553 #define A_ULP_TX_LA_WRPTR_5 0x8f18
29554 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
29555 #define A_ULP_TX_LA_RDPTR_6 0x8f20
29556 #define A_ULP_TX_LA_RDDATA_6 0x8f24
29557 #define A_ULP_TX_LA_WRPTR_6 0x8f28
29558 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
29559 #define A_ULP_TX_LA_RDPTR_7 0x8f30
29560 #define A_ULP_TX_LA_RDDATA_7 0x8f34
29561 #define A_ULP_TX_LA_WRPTR_7 0x8f38
29562 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
29563 #define A_ULP_TX_LA_RDPTR_8 0x8f40
29564 #define A_ULP_TX_LA_RDDATA_8 0x8f44
29565 #define A_ULP_TX_LA_WRPTR_8 0x8f48
29566 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
29567 #define A_ULP_TX_LA_RDPTR_9 0x8f50
29568 #define A_ULP_TX_LA_RDDATA_9 0x8f54
29569 #define A_ULP_TX_LA_WRPTR_9 0x8f58
29570 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
29571 #define A_ULP_TX_LA_RDPTR_10 0x8f60
29572 #define A_ULP_TX_LA_RDDATA_10 0x8f64
29573 #define A_ULP_TX_LA_WRPTR_10 0x8f68
29574 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
29575 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
29578 #define V_LA_WR0(x) ((x) << S_LA_WR0)
29579 #define F_LA_WR0 V_LA_WR0(1U)
29581 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
29582 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
29583 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
29584 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
29585 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
29586 #define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
29588 #define S_BYPASS_FIRST 26
29589 #define V_BYPASS_FIRST(x) ((x) << S_BYPASS_FIRST)
29590 #define F_BYPASS_FIRST V_BYPASS_FIRST(1U)
29592 #define S_BYPASS_MIDDLE 25
29593 #define V_BYPASS_MIDDLE(x) ((x) << S_BYPASS_MIDDLE)
29594 #define F_BYPASS_MIDDLE V_BYPASS_MIDDLE(1U)
29596 #define S_BYPASS_LAST 24
29597 #define V_BYPASS_LAST(x) ((x) << S_BYPASS_LAST)
29598 #define F_BYPASS_LAST V_BYPASS_LAST(1U)
29600 #define S_PUSH_FIRST 22
29601 #define V_PUSH_FIRST(x) ((x) << S_PUSH_FIRST)
29602 #define F_PUSH_FIRST V_PUSH_FIRST(1U)
29604 #define S_PUSH_MIDDLE 21
29605 #define V_PUSH_MIDDLE(x) ((x) << S_PUSH_MIDDLE)
29606 #define F_PUSH_MIDDLE V_PUSH_MIDDLE(1U)
29608 #define S_PUSH_LAST 20
29609 #define V_PUSH_LAST(x) ((x) << S_PUSH_LAST)
29610 #define F_PUSH_LAST V_PUSH_LAST(1U)
29612 #define S_SAVE_FIRST 18
29613 #define V_SAVE_FIRST(x) ((x) << S_SAVE_FIRST)
29614 #define F_SAVE_FIRST V_SAVE_FIRST(1U)
29616 #define S_SAVE_MIDDLE 17
29617 #define V_SAVE_MIDDLE(x) ((x) << S_SAVE_MIDDLE)
29618 #define F_SAVE_MIDDLE V_SAVE_MIDDLE(1U)
29620 #define S_SAVE_LAST 16
29621 #define V_SAVE_LAST(x) ((x) << S_SAVE_LAST)
29622 #define F_SAVE_LAST V_SAVE_LAST(1U)
29624 #define S_FLUSH_FIRST 14
29625 #define V_FLUSH_FIRST(x) ((x) << S_FLUSH_FIRST)
29626 #define F_FLUSH_FIRST V_FLUSH_FIRST(1U)
29628 #define S_FLUSH_MIDDLE 13
29629 #define V_FLUSH_MIDDLE(x) ((x) << S_FLUSH_MIDDLE)
29630 #define F_FLUSH_MIDDLE V_FLUSH_MIDDLE(1U)
29632 #define S_FLUSH_LAST 12
29633 #define V_FLUSH_LAST(x) ((x) << S_FLUSH_LAST)
29634 #define F_FLUSH_LAST V_FLUSH_LAST(1U)
29636 #define S_URGENT_FIRST 10
29637 #define V_URGENT_FIRST(x) ((x) << S_URGENT_FIRST)
29638 #define F_URGENT_FIRST V_URGENT_FIRST(1U)
29640 #define S_URGENT_MIDDLE 9
29641 #define V_URGENT_MIDDLE(x) ((x) << S_URGENT_MIDDLE)
29642 #define F_URGENT_MIDDLE V_URGENT_MIDDLE(1U)
29644 #define S_URGENT_LAST 8
29645 #define V_URGENT_LAST(x) ((x) << S_URGENT_LAST)
29646 #define F_URGENT_LAST V_URGENT_LAST(1U)
29648 #define S_MORE_FIRST 6
29649 #define V_MORE_FIRST(x) ((x) << S_MORE_FIRST)
29650 #define F_MORE_FIRST V_MORE_FIRST(1U)
29652 #define S_MORE_MIDDLE 5
29653 #define V_MORE_MIDDLE(x) ((x) << S_MORE_MIDDLE)
29654 #define F_MORE_MIDDLE V_MORE_MIDDLE(1U)
29656 #define S_MORE_LAST 4
29657 #define V_MORE_LAST(x) ((x) << S_MORE_LAST)
29658 #define F_MORE_LAST V_MORE_LAST(1U)
29660 #define S_SHOVE_FIRST 2
29661 #define V_SHOVE_FIRST(x) ((x) << S_SHOVE_FIRST)
29662 #define F_SHOVE_FIRST V_SHOVE_FIRST(1U)
29664 #define S_SHOVE_MIDDLE 1
29665 #define V_SHOVE_MIDDLE(x) ((x) << S_SHOVE_MIDDLE)
29666 #define F_SHOVE_MIDDLE V_SHOVE_MIDDLE(1U)
29668 #define S_SHOVE_LAST 0
29669 #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
29670 #define F_SHOVE_LAST V_SHOVE_LAST(1U)
29672 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
29674 #define S_TLS_TX_REG_OFF_ADDR 0
29675 #define M_TLS_TX_REG_OFF_ADDR 0x3ffU
29676 #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
29677 #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
29679 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
29681 /* registers for module PM_RX */
29682 #define PM_RX_BASE_ADDR 0x8fc0
29684 #define A_PM_RX_CFG 0x8fc0
29685 #define A_PM_RX_MODE 0x8fc4
29687 #define S_RX_USE_BUNDLE_LEN 4
29688 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
29689 #define F_RX_USE_BUNDLE_LEN V_RX_USE_BUNDLE_LEN(1U)
29691 #define S_STAT_TO_CH 3
29692 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
29693 #define F_STAT_TO_CH V_STAT_TO_CH(1U)
29695 #define S_STAT_FROM_CH 1
29696 #define M_STAT_FROM_CH 0x3U
29697 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
29698 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
29700 #define S_PREFETCH_ENABLE 0
29701 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
29702 #define F_PREFETCH_ENABLE V_PREFETCH_ENABLE(1U)
29704 #define A_PM_RX_STAT_CONFIG 0x8fc8
29705 #define A_PM_RX_STAT_COUNT 0x8fcc
29706 #define A_PM_RX_STAT_LSB 0x8fd0
29707 #define A_PM_RX_DBG_CTRL 0x8fd0
29709 #define S_OSPIWRBUSY_T5 21
29710 #define M_OSPIWRBUSY_T5 0x3U
29711 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
29712 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
29714 #define S_ISPIWRBUSY 17
29715 #define M_ISPIWRBUSY 0xfU
29716 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
29717 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
29719 #define S_PMDBGADDR 0
29720 #define M_PMDBGADDR 0x1ffffU
29721 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
29722 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
29724 #define A_PM_RX_STAT_MSB 0x8fd4
29725 #define A_PM_RX_DBG_DATA 0x8fd4
29726 #define A_PM_RX_INT_ENABLE 0x8fd8
29728 #define S_ZERO_E_CMD_ERROR 22
29729 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
29730 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
29732 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 21
29733 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
29734 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
29736 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 20
29737 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
29738 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
29740 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR 19
29741 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
29742 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
29744 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR 18
29745 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
29746 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
29748 #define S_IESPI0_RX_FRAMING_ERROR 17
29749 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
29750 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
29752 #define S_IESPI1_RX_FRAMING_ERROR 16
29753 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
29754 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
29756 #define S_IESPI2_RX_FRAMING_ERROR 15
29757 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
29758 #define F_IESPI2_RX_FRAMING_ERROR V_IESPI2_RX_FRAMING_ERROR(1U)
29760 #define S_IESPI3_RX_FRAMING_ERROR 14
29761 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
29762 #define F_IESPI3_RX_FRAMING_ERROR V_IESPI3_RX_FRAMING_ERROR(1U)
29764 #define S_IESPI0_TX_FRAMING_ERROR 13
29765 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
29766 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
29768 #define S_IESPI1_TX_FRAMING_ERROR 12
29769 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
29770 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
29772 #define S_IESPI2_TX_FRAMING_ERROR 11
29773 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
29774 #define F_IESPI2_TX_FRAMING_ERROR V_IESPI2_TX_FRAMING_ERROR(1U)
29776 #define S_IESPI3_TX_FRAMING_ERROR 10
29777 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
29778 #define F_IESPI3_TX_FRAMING_ERROR V_IESPI3_TX_FRAMING_ERROR(1U)
29780 #define S_OCSPI0_RX_FRAMING_ERROR 9
29781 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
29782 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
29784 #define S_OCSPI1_RX_FRAMING_ERROR 8
29785 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
29786 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
29788 #define S_OCSPI0_TX_FRAMING_ERROR 7
29789 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
29790 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
29792 #define S_OCSPI1_TX_FRAMING_ERROR 6
29793 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
29794 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
29796 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 5
29797 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
29798 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
29800 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 4
29801 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
29802 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
29804 #define S_OCSPI_PAR_ERROR 3
29805 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
29806 #define F_OCSPI_PAR_ERROR V_OCSPI_PAR_ERROR(1U)
29808 #define S_DB_OPTIONS_PAR_ERROR 2
29809 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
29810 #define F_DB_OPTIONS_PAR_ERROR V_DB_OPTIONS_PAR_ERROR(1U)
29812 #define S_IESPI_PAR_ERROR 1
29813 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
29814 #define F_IESPI_PAR_ERROR V_IESPI_PAR_ERROR(1U)
29816 #define S_E_PCMD_PAR_ERROR 0
29817 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
29818 #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U)
29820 #define S_OSPI_OVERFLOW1 28
29821 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
29822 #define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U)
29824 #define S_OSPI_OVERFLOW0 27
29825 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
29826 #define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U)
29828 #define S_MA_INTF_SDC_ERR 26
29829 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
29830 #define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U)
29832 #define S_BUNDLE_LEN_PARERR 25
29833 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
29834 #define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U)
29836 #define S_BUNDLE_LEN_OVFL 24
29837 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
29838 #define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U)
29840 #define S_SDC_ERR 23
29841 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
29842 #define F_SDC_ERR V_SDC_ERR(1U)
29844 #define A_PM_RX_INT_CAUSE 0x8fdc
29845 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
29846 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
29847 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
29848 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
29849 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
29850 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
29851 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
29852 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
29853 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
29854 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
29855 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
29856 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
29857 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
29858 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
29859 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
29860 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
29861 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
29862 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
29863 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
29864 #define A_PM_RX_DBG_STAT_MSB 0x10013
29865 #define A_PM_RX_DBG_STAT_LSB 0x10014
29866 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
29868 #define S_I_TO_O_PATH_RSVD_FLIT_BACKUP 12
29869 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP 0xfU
29870 #define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
29871 #define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
29873 #define S_I_TO_O_PATH_RSVD_FLIT 8
29874 #define M_I_TO_O_PATH_RSVD_FLIT 0xfU
29875 #define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
29876 #define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
29878 #define S_PRFCH_RSVD_FLIT 4
29879 #define M_PRFCH_RSVD_FLIT 0xfU
29880 #define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
29881 #define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
29883 #define S_OSPI_RSVD_FLIT 0
29884 #define M_OSPI_RSVD_FLIT 0xfU
29885 #define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
29886 #define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
29888 #define A_PM_RX_SDC_EN 0x10016
29891 #define V_SDC_EN(x) ((x) << S_SDC_EN)
29892 #define F_SDC_EN V_SDC_EN(1U)
29894 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
29896 #define S_CHNL_3_SEL 3
29897 #define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
29898 #define F_CHNL_3_SEL V_CHNL_3_SEL(1U)
29900 #define S_CHNL_2_SEL 2
29901 #define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
29902 #define F_CHNL_2_SEL V_CHNL_2_SEL(1U)
29904 #define S_CHNL_1_SEL 1
29905 #define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
29906 #define F_CHNL_1_SEL V_CHNL_1_SEL(1U)
29908 #define S_CHNL_0_SEL 0
29909 #define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
29910 #define F_CHNL_0_SEL V_CHNL_0_SEL(1U)
29912 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
29914 #define S_O_FIFO_WRITE 3
29915 #define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
29916 #define F_O_FIFO_WRITE V_O_FIFO_WRITE(1U)
29918 #define S_I_FIFO_WRITE 2
29919 #define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
29920 #define F_I_FIFO_WRITE V_I_FIFO_WRITE(1U)
29922 #define S_O_FIFO_READ 1
29923 #define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
29924 #define F_O_FIFO_READ V_O_FIFO_READ(1U)
29926 #define S_I_FIFO_READ 0
29927 #define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
29928 #define F_I_FIFO_READ V_I_FIFO_READ(1U)
29930 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
29932 #define S_ISPI_STR_FWD_EN 0
29933 #define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
29934 #define F_ISPI_STR_FWD_EN V_ISPI_STR_FWD_EN(1U)
29936 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
29938 #define S_PRFTCH_ACROSS_BNDLE_EN 0
29939 #define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
29940 #define F_PRFTCH_ACROSS_BNDLE_EN V_PRFTCH_ACROSS_BNDLE_EN(1U)
29942 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
29944 #define S_PRFTCH_WRR_ENABLE 0
29945 #define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
29946 #define F_PRFTCH_WRR_ENABLE V_PRFTCH_WRR_ENABLE(1U)
29948 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
29950 #define S_CHNL1_MAX_DEFICIT_CNT 16
29951 #define M_CHNL1_MAX_DEFICIT_CNT 0xffffU
29952 #define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
29953 #define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
29955 #define S_CHNL0_MAX_DEFICIT_CNT 0
29956 #define M_CHNL0_MAX_DEFICIT_CNT 0xffffU
29957 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
29958 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
29960 #define A_PM_RX_FEATURE_EN 0x1001d
29962 #define S_PIO_CH_DEFICIT_CTL_EN_RX 0
29963 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
29964 #define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
29966 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
29968 #define S_CH0_OSPI_DEFICIT_THRSHLD 0
29969 #define M_CH0_OSPI_DEFICIT_THRSHLD 0xfffU
29970 #define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
29971 #define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
29973 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
29975 #define S_CH1_OSPI_DEFICIT_THRSHLD 0
29976 #define M_CH1_OSPI_DEFICIT_THRSHLD 0xfffU
29977 #define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
29978 #define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
29980 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
29981 #define A_PM_RX_DBG_STAT0 0x10021
29983 #define S_RX_RD_I_BUSY 29
29984 #define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
29985 #define F_RX_RD_I_BUSY V_RX_RD_I_BUSY(1U)
29987 #define S_RX_WR_TO_O_BUSY 28
29988 #define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
29989 #define F_RX_WR_TO_O_BUSY V_RX_WR_TO_O_BUSY(1U)
29991 #define S_RX_M_TO_O_BUSY 27
29992 #define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
29993 #define F_RX_M_TO_O_BUSY V_RX_M_TO_O_BUSY(1U)
29995 #define S_RX_I_TO_M_BUSY 26
29996 #define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
29997 #define F_RX_I_TO_M_BUSY V_RX_I_TO_M_BUSY(1U)
29999 #define S_RX_PCMD_FB_ONLY 25
30000 #define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
30001 #define F_RX_PCMD_FB_ONLY V_RX_PCMD_FB_ONLY(1U)
30003 #define S_RX_PCMD_MEM 24
30004 #define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
30005 #define F_RX_PCMD_MEM V_RX_PCMD_MEM(1U)
30007 #define S_RX_PCMD_BYPASS 23
30008 #define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
30009 #define F_RX_PCMD_BYPASS V_RX_PCMD_BYPASS(1U)
30011 #define S_RX_PCMD_EOP 22
30012 #define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
30013 #define F_RX_PCMD_EOP V_RX_PCMD_EOP(1U)
30015 #define S_RX_DUMPLICATE_PCMD_EOP 21
30016 #define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
30017 #define F_RX_DUMPLICATE_PCMD_EOP V_RX_DUMPLICATE_PCMD_EOP(1U)
30019 #define S_RX_PCMD_EOB 20
30020 #define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
30021 #define F_RX_PCMD_EOB V_RX_PCMD_EOB(1U)
30023 #define S_RX_PCMD_FB 16
30024 #define M_RX_PCMD_FB 0xfU
30025 #define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
30026 #define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
30028 #define S_RX_PCMD_LEN 0
30029 #define M_RX_PCMD_LEN 0xffffU
30030 #define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
30031 #define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
30033 #define A_PM_RX_DBG_STAT1 0x10022
30035 #define S_RX_PCMD0_MEM 30
30036 #define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
30037 #define F_RX_PCMD0_MEM V_RX_PCMD0_MEM(1U)
30039 #define S_RX_FREE_OSPI_CNT0 18
30040 #define M_RX_FREE_OSPI_CNT0 0xfffU
30041 #define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
30042 #define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
30044 #define S_RX_PCMD0_FLIT_LEN 6
30045 #define M_RX_PCMD0_FLIT_LEN 0xfffU
30046 #define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
30047 #define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
30049 #define S_RX_PCMD0_CMD 2
30050 #define M_RX_PCMD0_CMD 0xfU
30051 #define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
30052 #define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
30054 #define S_RX_OFIFO_FULL0 1
30055 #define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
30056 #define F_RX_OFIFO_FULL0 V_RX_OFIFO_FULL0(1U)
30058 #define S_RX_PCMD0_BYPASS 0
30059 #define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
30060 #define F_RX_PCMD0_BYPASS V_RX_PCMD0_BYPASS(1U)
30062 #define A_PM_RX_DBG_STAT2 0x10023
30064 #define S_RX_PCMD1_MEM 30
30065 #define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
30066 #define F_RX_PCMD1_MEM V_RX_PCMD1_MEM(1U)
30068 #define S_RX_FREE_OSPI_CNT1 18
30069 #define M_RX_FREE_OSPI_CNT1 0xfffU
30070 #define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
30071 #define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
30073 #define S_RX_PCMD1_FLIT_LEN 6
30074 #define M_RX_PCMD1_FLIT_LEN 0xfffU
30075 #define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
30076 #define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
30078 #define S_RX_PCMD1_CMD 2
30079 #define M_RX_PCMD1_CMD 0xfU
30080 #define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
30081 #define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
30083 #define S_RX_OFIFO_FULL1 1
30084 #define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
30085 #define F_RX_OFIFO_FULL1 V_RX_OFIFO_FULL1(1U)
30087 #define S_RX_PCMD1_BYPASS 0
30088 #define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
30089 #define F_RX_PCMD1_BYPASS V_RX_PCMD1_BYPASS(1U)
30091 #define A_PM_RX_DBG_STAT3 0x10024
30093 #define S_RX_SET_PCMD_RES_RDY_RD 10
30094 #define M_RX_SET_PCMD_RES_RDY_RD 0x3U
30095 #define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
30096 #define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
30098 #define S_RX_ISSUED_PREFETCH_RD_E_CLR 8
30099 #define M_RX_ISSUED_PREFETCH_RD_E_CLR 0x3U
30100 #define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
30101 #define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
30103 #define S_RX_ISSUED_PREFETCH_RD 6
30104 #define M_RX_ISSUED_PREFETCH_RD 0x3U
30105 #define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
30106 #define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
30108 #define S_RX_PCMD_RES_RDY 4
30109 #define M_RX_PCMD_RES_RDY 0x3U
30110 #define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
30111 #define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
30113 #define S_RX_DB_VLD 3
30114 #define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
30115 #define F_RX_DB_VLD V_RX_DB_VLD(1U)
30117 #define S_RX_FIRST_BUNDLE 1
30118 #define M_RX_FIRST_BUNDLE 0x3U
30119 #define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
30120 #define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
30122 #define S_RX_SDC_DRDY 0
30123 #define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
30124 #define F_RX_SDC_DRDY V_RX_SDC_DRDY(1U)
30126 #define A_PM_RX_DBG_STAT4 0x10025
30128 #define S_RX_PCMD_VLD 26
30129 #define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
30130 #define F_RX_PCMD_VLD V_RX_PCMD_VLD(1U)
30132 #define S_RX_PCMD_TO_CH 25
30133 #define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
30134 #define F_RX_PCMD_TO_CH V_RX_PCMD_TO_CH(1U)
30136 #define S_RX_PCMD_FROM_CH 23
30137 #define M_RX_PCMD_FROM_CH 0x3U
30138 #define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
30139 #define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
30141 #define S_RX_LINE 18
30142 #define M_RX_LINE 0x1fU
30143 #define V_RX_LINE(x) ((x) << S_RX_LINE)
30144 #define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
30146 #define S_RX_IESPI_TXVALID 14
30147 #define M_RX_IESPI_TXVALID 0xfU
30148 #define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
30149 #define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
30151 #define S_RX_IESPI_TXFULL 10
30152 #define M_RX_IESPI_TXFULL 0xfU
30153 #define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
30154 #define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
30156 #define S_RX_PCMD_SRDY 8
30157 #define M_RX_PCMD_SRDY 0x3U
30158 #define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
30159 #define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
30161 #define S_RX_PCMD_DRDY 6
30162 #define M_RX_PCMD_DRDY 0x3U
30163 #define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
30164 #define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
30166 #define S_RX_PCMD_CMD 2
30167 #define M_RX_PCMD_CMD 0xfU
30168 #define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
30169 #define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
30171 #define S_DUPLICATE 0
30172 #define M_DUPLICATE 0x3U
30173 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
30174 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
30176 #define S_RX_PCMD_SRDY_STAT4 8
30177 #define M_RX_PCMD_SRDY_STAT4 0x3U
30178 #define V_RX_PCMD_SRDY_STAT4(x) ((x) << S_RX_PCMD_SRDY_STAT4)
30179 #define G_RX_PCMD_SRDY_STAT4(x) (((x) >> S_RX_PCMD_SRDY_STAT4) & M_RX_PCMD_SRDY_STAT4)
30181 #define S_RX_PCMD_DRDY_STAT4 6
30182 #define M_RX_PCMD_DRDY_STAT4 0x3U
30183 #define V_RX_PCMD_DRDY_STAT4(x) ((x) << S_RX_PCMD_DRDY_STAT4)
30184 #define G_RX_PCMD_DRDY_STAT4(x) (((x) >> S_RX_PCMD_DRDY_STAT4) & M_RX_PCMD_DRDY_STAT4)
30186 #define A_PM_RX_DBG_STAT5 0x10026
30188 #define S_RX_ATLST_1_PCMD_CH1 29
30189 #define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
30190 #define F_RX_ATLST_1_PCMD_CH1 V_RX_ATLST_1_PCMD_CH1(1U)
30192 #define S_RX_ATLST_1_PCMD_CH0 28
30193 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
30194 #define F_RX_ATLST_1_PCMD_CH0 V_RX_ATLST_1_PCMD_CH0(1U)
30196 #define S_T5_RX_PCMD_DRDY 26
30197 #define M_T5_RX_PCMD_DRDY 0x3U
30198 #define V_T5_RX_PCMD_DRDY(x) ((x) << S_T5_RX_PCMD_DRDY)
30199 #define G_T5_RX_PCMD_DRDY(x) (((x) >> S_T5_RX_PCMD_DRDY) & M_T5_RX_PCMD_DRDY)
30201 #define S_T5_RX_PCMD_SRDY 24
30202 #define M_T5_RX_PCMD_SRDY 0x3U
30203 #define V_T5_RX_PCMD_SRDY(x) ((x) << S_T5_RX_PCMD_SRDY)
30204 #define G_T5_RX_PCMD_SRDY(x) (((x) >> S_T5_RX_PCMD_SRDY) & M_T5_RX_PCMD_SRDY)
30206 #define S_RX_ISPI_TXVALID 20
30207 #define M_RX_ISPI_TXVALID 0xfU
30208 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
30209 #define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
30211 #define S_RX_ISPI_FULL 16
30212 #define M_RX_ISPI_FULL 0xfU
30213 #define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
30214 #define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
30216 #define S_RX_OSPI_TXVALID 14
30217 #define M_RX_OSPI_TXVALID 0x3U
30218 #define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
30219 #define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
30221 #define S_RX_OSPI_FULL 12
30222 #define M_RX_OSPI_FULL 0x3U
30223 #define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
30224 #define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
30226 #define S_RX_E_RXVALID 8
30227 #define M_RX_E_RXVALID 0xfU
30228 #define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
30229 #define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
30231 #define S_RX_E_RXAFULL 4
30232 #define M_RX_E_RXAFULL 0xfU
30233 #define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
30234 #define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
30236 #define S_RX_C_TXVALID 2
30237 #define M_RX_C_TXVALID 0x3U
30238 #define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
30239 #define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
30241 #define S_RX_C_TXAFULL 0
30242 #define M_RX_C_TXAFULL 0x3U
30243 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
30244 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
30246 #define S_T6_RX_PCMD_DRDY 26
30247 #define M_T6_RX_PCMD_DRDY 0x3U
30248 #define V_T6_RX_PCMD_DRDY(x) ((x) << S_T6_RX_PCMD_DRDY)
30249 #define G_T6_RX_PCMD_DRDY(x) (((x) >> S_T6_RX_PCMD_DRDY) & M_T6_RX_PCMD_DRDY)
30251 #define S_T6_RX_PCMD_SRDY 24
30252 #define M_T6_RX_PCMD_SRDY 0x3U
30253 #define V_T6_RX_PCMD_SRDY(x) ((x) << S_T6_RX_PCMD_SRDY)
30254 #define G_T6_RX_PCMD_SRDY(x) (((x) >> S_T6_RX_PCMD_SRDY) & M_T6_RX_PCMD_SRDY)
30256 #define A_PM_RX_DBG_STAT6 0x10027
30258 #define S_RX_M_INTRNL_FIFO_CNT 4
30259 #define M_RX_M_INTRNL_FIFO_CNT 0x3U
30260 #define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
30261 #define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
30263 #define S_RX_M_REQADDRRDY 3
30264 #define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
30265 #define F_RX_M_REQADDRRDY V_RX_M_REQADDRRDY(1U)
30267 #define S_RX_M_REQWRITE 2
30268 #define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
30269 #define F_RX_M_REQWRITE V_RX_M_REQWRITE(1U)
30271 #define S_RX_M_REQDATAVLD 1
30272 #define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
30273 #define F_RX_M_REQDATAVLD V_RX_M_REQDATAVLD(1U)
30275 #define S_RX_M_REQDATARDY 0
30276 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
30277 #define F_RX_M_REQDATARDY V_RX_M_REQDATARDY(1U)
30279 #define S_T6_RX_M_INTRNL_FIFO_CNT 7
30280 #define M_T6_RX_M_INTRNL_FIFO_CNT 0x3U
30281 #define V_T6_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_T6_RX_M_INTRNL_FIFO_CNT)
30282 #define G_T6_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_T6_RX_M_INTRNL_FIFO_CNT) & M_T6_RX_M_INTRNL_FIFO_CNT)
30284 #define S_RX_M_RSPVLD 6
30285 #define V_RX_M_RSPVLD(x) ((x) << S_RX_M_RSPVLD)
30286 #define F_RX_M_RSPVLD V_RX_M_RSPVLD(1U)
30288 #define S_RX_M_RSPRDY 5
30289 #define V_RX_M_RSPRDY(x) ((x) << S_RX_M_RSPRDY)
30290 #define F_RX_M_RSPRDY V_RX_M_RSPRDY(1U)
30292 #define S_RX_M_REQADDRVLD 4
30293 #define V_RX_M_REQADDRVLD(x) ((x) << S_RX_M_REQADDRVLD)
30294 #define F_RX_M_REQADDRVLD V_RX_M_REQADDRVLD(1U)
30296 #define A_PM_RX_DBG_STAT7 0x10028
30298 #define S_RX_PCMD1_FREE_CNT 7
30299 #define M_RX_PCMD1_FREE_CNT 0x7fU
30300 #define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
30301 #define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
30303 #define S_RX_PCMD0_FREE_CNT 0
30304 #define M_RX_PCMD0_FREE_CNT 0x7fU
30305 #define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
30306 #define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
30308 #define A_PM_RX_DBG_STAT8 0x10029
30310 #define S_RX_IN_EOP_CNT3 28
30311 #define M_RX_IN_EOP_CNT3 0xfU
30312 #define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
30313 #define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
30315 #define S_RX_IN_EOP_CNT2 24
30316 #define M_RX_IN_EOP_CNT2 0xfU
30317 #define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
30318 #define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
30320 #define S_RX_IN_EOP_CNT1 20
30321 #define M_RX_IN_EOP_CNT1 0xfU
30322 #define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
30323 #define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
30325 #define S_RX_IN_EOP_CNT0 16
30326 #define M_RX_IN_EOP_CNT0 0xfU
30327 #define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
30328 #define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
30330 #define S_RX_IN_SOP_CNT3 12
30331 #define M_RX_IN_SOP_CNT3 0xfU
30332 #define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
30333 #define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
30335 #define S_RX_IN_SOP_CNT2 8
30336 #define M_RX_IN_SOP_CNT2 0xfU
30337 #define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
30338 #define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
30340 #define S_RX_IN_SOP_CNT1 4
30341 #define M_RX_IN_SOP_CNT1 0xfU
30342 #define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
30343 #define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
30345 #define S_RX_IN_SOP_CNT0 0
30346 #define M_RX_IN_SOP_CNT0 0xfU
30347 #define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
30348 #define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
30350 #define A_PM_RX_DBG_STAT9 0x1002a
30352 #define S_RX_RSVD0 28
30353 #define M_RX_RSVD0 0xfU
30354 #define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
30355 #define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
30357 #define S_RX_RSVD1 24
30358 #define M_RX_RSVD1 0xfU
30359 #define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
30360 #define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
30362 #define S_RX_OUT_EOP_CNT1 20
30363 #define M_RX_OUT_EOP_CNT1 0xfU
30364 #define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
30365 #define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
30367 #define S_RX_OUT_EOP_CNT0 16
30368 #define M_RX_OUT_EOP_CNT0 0xfU
30369 #define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
30370 #define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
30372 #define S_RX_RSVD2 12
30373 #define M_RX_RSVD2 0xfU
30374 #define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
30375 #define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
30377 #define S_RX_RSVD3 8
30378 #define M_RX_RSVD3 0xfU
30379 #define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
30380 #define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
30382 #define S_RX_OUT_SOP_CNT1 4
30383 #define M_RX_OUT_SOP_CNT1 0xfU
30384 #define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
30385 #define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
30387 #define S_RX_OUT_SOP_CNT0 0
30388 #define M_RX_OUT_SOP_CNT0 0xfU
30389 #define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
30390 #define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
30392 #define A_PM_RX_DBG_STAT10 0x1002b
30394 #define S_RX_CH_DEFICIT_BLOWED 24
30395 #define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
30396 #define F_RX_CH_DEFICIT_BLOWED V_RX_CH_DEFICIT_BLOWED(1U)
30398 #define S_RX_CH1_DEFICIT 12
30399 #define M_RX_CH1_DEFICIT 0xfffU
30400 #define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
30401 #define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
30403 #define S_RX_CH0_DEFICIT 0
30404 #define M_RX_CH0_DEFICIT 0xfffU
30405 #define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
30406 #define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
30408 #define A_PM_RX_DBG_STAT11 0x1002c
30410 #define S_RX_BUNDLE_LEN_SRDY 30
30411 #define M_RX_BUNDLE_LEN_SRDY 0x3U
30412 #define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
30413 #define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
30415 #define S_RX_RSVD11_1 28
30416 #define M_RX_RSVD11_1 0x3U
30417 #define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
30418 #define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
30420 #define S_RX_BUNDLE_LEN1 16
30421 #define M_RX_BUNDLE_LEN1 0xfffU
30422 #define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
30423 #define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
30425 #define S_RX_RSVD11 12
30426 #define M_RX_RSVD11 0xfU
30427 #define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
30428 #define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
30430 #define S_RX_BUNDLE_LEN0 0
30431 #define M_RX_BUNDLE_LEN0 0xfffU
30432 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
30433 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
30435 /* registers for module PM_TX */
30436 #define PM_TX_BASE_ADDR 0x8fe0
30438 #define A_PM_TX_CFG 0x8fe0
30440 #define S_CH3_OUTPUT 17
30441 #define M_CH3_OUTPUT 0x1fU
30442 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
30443 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
30445 #define A_PM_TX_MODE 0x8fe4
30447 #define S_CONG_THRESH3 25
30448 #define M_CONG_THRESH3 0x7fU
30449 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
30450 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
30452 #define S_CONG_THRESH2 18
30453 #define M_CONG_THRESH2 0x7fU
30454 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
30455 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
30457 #define S_CONG_THRESH1 11
30458 #define M_CONG_THRESH1 0x7fU
30459 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
30460 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
30462 #define S_CONG_THRESH0 4
30463 #define M_CONG_THRESH0 0x7fU
30464 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
30465 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
30467 #define S_TX_USE_BUNDLE_LEN 3
30468 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
30469 #define F_TX_USE_BUNDLE_LEN V_TX_USE_BUNDLE_LEN(1U)
30471 #define S_STAT_CHANNEL 1
30472 #define M_STAT_CHANNEL 0x3U
30473 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
30474 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
30476 #define A_PM_TX_STAT_CONFIG 0x8fe8
30477 #define A_PM_TX_STAT_COUNT 0x8fec
30478 #define A_PM_TX_STAT_LSB 0x8ff0
30479 #define A_PM_TX_DBG_CTRL 0x8ff0
30481 #define S_OSPIWRBUSY 21
30482 #define M_OSPIWRBUSY 0xfU
30483 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
30484 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
30486 #define A_PM_TX_STAT_MSB 0x8ff4
30487 #define A_PM_TX_DBG_DATA 0x8ff4
30488 #define A_PM_TX_INT_ENABLE 0x8ff8
30490 #define S_PCMD_LEN_OVFL0 31
30491 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
30492 #define F_PCMD_LEN_OVFL0 V_PCMD_LEN_OVFL0(1U)
30494 #define S_PCMD_LEN_OVFL1 30
30495 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
30496 #define F_PCMD_LEN_OVFL1 V_PCMD_LEN_OVFL1(1U)
30498 #define S_PCMD_LEN_OVFL2 29
30499 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
30500 #define F_PCMD_LEN_OVFL2 V_PCMD_LEN_OVFL2(1U)
30502 #define S_ZERO_C_CMD_ERRO 28
30503 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
30504 #define F_ZERO_C_CMD_ERRO V_ZERO_C_CMD_ERRO(1U)
30506 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 27
30507 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
30508 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
30510 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 26
30511 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
30512 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
30514 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR 25
30515 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
30516 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
30518 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR 24
30519 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
30520 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
30522 #define S_ICSPI0_RX_FRAMING_ERROR 23
30523 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
30524 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
30526 #define S_ICSPI1_RX_FRAMING_ERROR 22
30527 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
30528 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
30530 #define S_ICSPI2_RX_FRAMING_ERROR 21
30531 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
30532 #define F_ICSPI2_RX_FRAMING_ERROR V_ICSPI2_RX_FRAMING_ERROR(1U)
30534 #define S_ICSPI3_RX_FRAMING_ERROR 20
30535 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
30536 #define F_ICSPI3_RX_FRAMING_ERROR V_ICSPI3_RX_FRAMING_ERROR(1U)
30538 #define S_ICSPI0_TX_FRAMING_ERROR 19
30539 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
30540 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
30542 #define S_ICSPI1_TX_FRAMING_ERROR 18
30543 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
30544 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
30546 #define S_ICSPI2_TX_FRAMING_ERROR 17
30547 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
30548 #define F_ICSPI2_TX_FRAMING_ERROR V_ICSPI2_TX_FRAMING_ERROR(1U)
30550 #define S_ICSPI3_TX_FRAMING_ERROR 16
30551 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
30552 #define F_ICSPI3_TX_FRAMING_ERROR V_ICSPI3_TX_FRAMING_ERROR(1U)
30554 #define S_OESPI0_RX_FRAMING_ERROR 15
30555 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
30556 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
30558 #define S_OESPI1_RX_FRAMING_ERROR 14
30559 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
30560 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
30562 #define S_OESPI2_RX_FRAMING_ERROR 13
30563 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
30564 #define F_OESPI2_RX_FRAMING_ERROR V_OESPI2_RX_FRAMING_ERROR(1U)
30566 #define S_OESPI3_RX_FRAMING_ERROR 12
30567 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
30568 #define F_OESPI3_RX_FRAMING_ERROR V_OESPI3_RX_FRAMING_ERROR(1U)
30570 #define S_OESPI0_TX_FRAMING_ERROR 11
30571 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
30572 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
30574 #define S_OESPI1_TX_FRAMING_ERROR 10
30575 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
30576 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
30578 #define S_OESPI2_TX_FRAMING_ERROR 9
30579 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
30580 #define F_OESPI2_TX_FRAMING_ERROR V_OESPI2_TX_FRAMING_ERROR(1U)
30582 #define S_OESPI3_TX_FRAMING_ERROR 8
30583 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
30584 #define F_OESPI3_TX_FRAMING_ERROR V_OESPI3_TX_FRAMING_ERROR(1U)
30586 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
30587 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
30588 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
30590 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
30591 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
30592 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
30594 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR 5
30595 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
30596 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
30598 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR 4
30599 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
30600 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
30602 #define S_OESPI_PAR_ERROR 3
30603 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
30604 #define F_OESPI_PAR_ERROR V_OESPI_PAR_ERROR(1U)
30606 #define S_ICSPI_PAR_ERROR 1
30607 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
30608 #define F_ICSPI_PAR_ERROR V_ICSPI_PAR_ERROR(1U)
30610 #define S_C_PCMD_PAR_ERROR 0
30611 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
30612 #define F_C_PCMD_PAR_ERROR V_C_PCMD_PAR_ERROR(1U)
30614 #define A_PM_TX_INT_CAUSE 0x8ffc
30616 #define S_ZERO_C_CMD_ERROR 28
30617 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
30618 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
30620 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3
30621 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
30622 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
30624 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
30625 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
30626 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
30627 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
30628 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
30629 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
30630 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
30631 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
30632 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
30633 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
30634 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
30635 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
30636 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
30637 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
30638 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
30639 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
30640 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
30641 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
30642 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
30643 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
30644 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
30645 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
30646 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
30647 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
30648 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
30649 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
30650 #define A_PM_TX_DBG_STAT_MSB 0x1001a
30651 #define A_PM_TX_DBG_STAT_LSB 0x1001b
30652 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
30653 #define A_PM_TX_SDC_EN 0x1001d
30654 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
30655 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
30656 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
30657 #define A_PM_TX_FEATURE_EN 0x10021
30659 #define S_PIO_CH_DEFICIT_CTL_EN 2
30660 #define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
30661 #define F_PIO_CH_DEFICIT_CTL_EN V_PIO_CH_DEFICIT_CTL_EN(1U)
30663 #define S_PIO_WRR_BASED_PRFTCH_EN 1
30664 #define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
30665 #define F_PIO_WRR_BASED_PRFTCH_EN V_PIO_WRR_BASED_PRFTCH_EN(1U)
30667 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
30669 #define S_OSPI_OVERFLOW3 7
30670 #define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
30671 #define F_OSPI_OVERFLOW3 V_OSPI_OVERFLOW3(1U)
30673 #define S_OSPI_OVERFLOW2 6
30674 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
30675 #define F_OSPI_OVERFLOW2 V_OSPI_OVERFLOW2(1U)
30677 #define S_T5_OSPI_OVERFLOW1 5
30678 #define V_T5_OSPI_OVERFLOW1(x) ((x) << S_T5_OSPI_OVERFLOW1)
30679 #define F_T5_OSPI_OVERFLOW1 V_T5_OSPI_OVERFLOW1(1U)
30681 #define S_T5_OSPI_OVERFLOW0 4
30682 #define V_T5_OSPI_OVERFLOW0(x) ((x) << S_T5_OSPI_OVERFLOW0)
30683 #define F_T5_OSPI_OVERFLOW0 V_T5_OSPI_OVERFLOW0(1U)
30685 #define S_M_INTFPERREN 3
30686 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
30687 #define F_M_INTFPERREN V_M_INTFPERREN(1U)
30689 #define S_BUNDLE_LEN_PARERR_EN 2
30690 #define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
30691 #define F_BUNDLE_LEN_PARERR_EN V_BUNDLE_LEN_PARERR_EN(1U)
30693 #define S_BUNDLE_LEN_OVFL_EN 1
30694 #define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
30695 #define F_BUNDLE_LEN_OVFL_EN V_BUNDLE_LEN_OVFL_EN(1U)
30697 #define S_SDC_ERR_EN 0
30698 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
30699 #define F_SDC_ERR_EN V_SDC_ERR_EN(1U)
30701 #define S_OSPI_OVERFLOW3_T5 7
30702 #define V_OSPI_OVERFLOW3_T5(x) ((x) << S_OSPI_OVERFLOW3_T5)
30703 #define F_OSPI_OVERFLOW3_T5 V_OSPI_OVERFLOW3_T5(1U)
30705 #define S_OSPI_OVERFLOW2_T5 6
30706 #define V_OSPI_OVERFLOW2_T5(x) ((x) << S_OSPI_OVERFLOW2_T5)
30707 #define F_OSPI_OVERFLOW2_T5 V_OSPI_OVERFLOW2_T5(1U)
30709 #define S_OSPI_OVERFLOW1_T5 5
30710 #define V_OSPI_OVERFLOW1_T5(x) ((x) << S_OSPI_OVERFLOW1_T5)
30711 #define F_OSPI_OVERFLOW1_T5 V_OSPI_OVERFLOW1_T5(1U)
30713 #define S_OSPI_OVERFLOW0_T5 4
30714 #define V_OSPI_OVERFLOW0_T5(x) ((x) << S_OSPI_OVERFLOW0_T5)
30715 #define F_OSPI_OVERFLOW0_T5 V_OSPI_OVERFLOW0_T5(1U)
30717 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
30718 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
30719 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
30720 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
30721 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
30722 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
30723 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
30725 #define S_CH2_OSPI_DEFICIT_THRSHLD 0
30726 #define M_CH2_OSPI_DEFICIT_THRSHLD 0xfffU
30727 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
30728 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
30730 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
30732 #define S_CH3_OSPI_DEFICIT_THRSHLD 0
30733 #define M_CH3_OSPI_DEFICIT_THRSHLD 0xfffU
30734 #define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
30735 #define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
30737 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
30738 #define A_PM_TX_DBG_STAT0 0x1002c
30740 #define S_RD_I_BUSY 29
30741 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
30742 #define F_RD_I_BUSY V_RD_I_BUSY(1U)
30744 #define S_WR_O_BUSY 28
30745 #define V_WR_O_BUSY(x) ((x) << S_WR_O_BUSY)
30746 #define F_WR_O_BUSY V_WR_O_BUSY(1U)
30748 #define S_M_TO_O_BUSY 27
30749 #define V_M_TO_O_BUSY(x) ((x) << S_M_TO_O_BUSY)
30750 #define F_M_TO_O_BUSY V_M_TO_O_BUSY(1U)
30752 #define S_I_TO_M_BUSY 26
30753 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
30754 #define F_I_TO_M_BUSY V_I_TO_M_BUSY(1U)
30756 #define S_PCMD_FB_ONLY 25
30757 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
30758 #define F_PCMD_FB_ONLY V_PCMD_FB_ONLY(1U)
30760 #define S_PCMD_MEM 24
30761 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
30762 #define F_PCMD_MEM V_PCMD_MEM(1U)
30764 #define S_PCMD_BYPASS 23
30765 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
30766 #define F_PCMD_BYPASS V_PCMD_BYPASS(1U)
30768 #define S_PCMD_EOP2 22
30769 #define V_PCMD_EOP2(x) ((x) << S_PCMD_EOP2)
30770 #define F_PCMD_EOP2 V_PCMD_EOP2(1U)
30772 #define S_PCMD_EOP 21
30773 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
30774 #define F_PCMD_EOP V_PCMD_EOP(1U)
30776 #define S_PCMD_END_BUNDLE 20
30777 #define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
30778 #define F_PCMD_END_BUNDLE V_PCMD_END_BUNDLE(1U)
30780 #define S_PCMD_FB_CMD 16
30781 #define M_PCMD_FB_CMD 0xfU
30782 #define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
30783 #define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
30785 #define S_CUR_PCMD_LEN 0
30786 #define M_CUR_PCMD_LEN 0xffffU
30787 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
30788 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
30790 #define S_T6_RD_I_BUSY 28
30791 #define V_T6_RD_I_BUSY(x) ((x) << S_T6_RD_I_BUSY)
30792 #define F_T6_RD_I_BUSY V_T6_RD_I_BUSY(1U)
30794 #define S_T6_WR_O_BUSY 27
30795 #define V_T6_WR_O_BUSY(x) ((x) << S_T6_WR_O_BUSY)
30796 #define F_T6_WR_O_BUSY V_T6_WR_O_BUSY(1U)
30798 #define S_T6_M_TO_O_BUSY 26
30799 #define V_T6_M_TO_O_BUSY(x) ((x) << S_T6_M_TO_O_BUSY)
30800 #define F_T6_M_TO_O_BUSY V_T6_M_TO_O_BUSY(1U)
30802 #define S_T6_I_TO_M_BUSY 25
30803 #define V_T6_I_TO_M_BUSY(x) ((x) << S_T6_I_TO_M_BUSY)
30804 #define F_T6_I_TO_M_BUSY V_T6_I_TO_M_BUSY(1U)
30806 #define S_T6_PCMD_FB_ONLY 24
30807 #define V_T6_PCMD_FB_ONLY(x) ((x) << S_T6_PCMD_FB_ONLY)
30808 #define F_T6_PCMD_FB_ONLY V_T6_PCMD_FB_ONLY(1U)
30810 #define S_T6_PCMD_MEM 23
30811 #define V_T6_PCMD_MEM(x) ((x) << S_T6_PCMD_MEM)
30812 #define F_T6_PCMD_MEM V_T6_PCMD_MEM(1U)
30814 #define S_T6_PCMD_BYPASS 22
30815 #define V_T6_PCMD_BYPASS(x) ((x) << S_T6_PCMD_BYPASS)
30816 #define F_T6_PCMD_BYPASS V_T6_PCMD_BYPASS(1U)
30818 #define A_PM_TX_DBG_STAT1 0x1002d
30820 #define S_PCMD_MEM0 31
30821 #define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
30822 #define F_PCMD_MEM0 V_PCMD_MEM0(1U)
30824 #define S_FREE_OESPI_CNT0 19
30825 #define M_FREE_OESPI_CNT0 0xfffU
30826 #define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
30827 #define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
30829 #define S_PCMD_FLIT_LEN0 7
30830 #define M_PCMD_FLIT_LEN0 0xfffU
30831 #define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
30832 #define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
30834 #define S_PCMD_CMD0 3
30835 #define M_PCMD_CMD0 0xfU
30836 #define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
30837 #define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
30839 #define S_OFIFO_FULL0 2
30840 #define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
30841 #define F_OFIFO_FULL0 V_OFIFO_FULL0(1U)
30843 #define S_GCSUM_DRDY0 1
30844 #define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
30845 #define F_GCSUM_DRDY0 V_GCSUM_DRDY0(1U)
30847 #define S_BYPASS0 0
30848 #define V_BYPASS0(x) ((x) << S_BYPASS0)
30849 #define F_BYPASS0 V_BYPASS0(1U)
30851 #define A_PM_TX_DBG_STAT2 0x1002e
30853 #define S_PCMD_MEM1 31
30854 #define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
30855 #define F_PCMD_MEM1 V_PCMD_MEM1(1U)
30857 #define S_FREE_OESPI_CNT1 19
30858 #define M_FREE_OESPI_CNT1 0xfffU
30859 #define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
30860 #define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
30862 #define S_PCMD_FLIT_LEN1 7
30863 #define M_PCMD_FLIT_LEN1 0xfffU
30864 #define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
30865 #define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
30867 #define S_PCMD_CMD1 3
30868 #define M_PCMD_CMD1 0xfU
30869 #define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
30870 #define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
30872 #define S_OFIFO_FULL1 2
30873 #define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
30874 #define F_OFIFO_FULL1 V_OFIFO_FULL1(1U)
30876 #define S_GCSUM_DRDY1 1
30877 #define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
30878 #define F_GCSUM_DRDY1 V_GCSUM_DRDY1(1U)
30880 #define S_BYPASS1 0
30881 #define V_BYPASS1(x) ((x) << S_BYPASS1)
30882 #define F_BYPASS1 V_BYPASS1(1U)
30884 #define A_PM_TX_DBG_STAT3 0x1002f
30886 #define S_PCMD_MEM2 31
30887 #define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
30888 #define F_PCMD_MEM2 V_PCMD_MEM2(1U)
30890 #define S_FREE_OESPI_CNT2 19
30891 #define M_FREE_OESPI_CNT2 0xfffU
30892 #define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
30893 #define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
30895 #define S_PCMD_FLIT_LEN2 7
30896 #define M_PCMD_FLIT_LEN2 0xfffU
30897 #define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
30898 #define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
30900 #define S_PCMD_CMD2 3
30901 #define M_PCMD_CMD2 0xfU
30902 #define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
30903 #define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
30905 #define S_OFIFO_FULL2 2
30906 #define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
30907 #define F_OFIFO_FULL2 V_OFIFO_FULL2(1U)
30909 #define S_GCSUM_DRDY2 1
30910 #define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
30911 #define F_GCSUM_DRDY2 V_GCSUM_DRDY2(1U)
30913 #define S_BYPASS2 0
30914 #define V_BYPASS2(x) ((x) << S_BYPASS2)
30915 #define F_BYPASS2 V_BYPASS2(1U)
30917 #define A_PM_TX_DBG_STAT4 0x10030
30919 #define S_PCMD_MEM3 31
30920 #define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
30921 #define F_PCMD_MEM3 V_PCMD_MEM3(1U)
30923 #define S_FREE_OESPI_CNT3 19
30924 #define M_FREE_OESPI_CNT3 0xfffU
30925 #define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
30926 #define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
30928 #define S_PCMD_FLIT_LEN3 7
30929 #define M_PCMD_FLIT_LEN3 0xfffU
30930 #define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
30931 #define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
30933 #define S_PCMD_CMD3 3
30934 #define M_PCMD_CMD3 0xfU
30935 #define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
30936 #define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
30938 #define S_OFIFO_FULL3 2
30939 #define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
30940 #define F_OFIFO_FULL3 V_OFIFO_FULL3(1U)
30942 #define S_GCSUM_DRDY3 1
30943 #define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
30944 #define F_GCSUM_DRDY3 V_GCSUM_DRDY3(1U)
30946 #define S_BYPASS3 0
30947 #define V_BYPASS3(x) ((x) << S_BYPASS3)
30948 #define F_BYPASS3 V_BYPASS3(1U)
30950 #define A_PM_TX_DBG_STAT5 0x10031
30952 #define S_SET_PCMD_RES_RDY_RD 24
30953 #define M_SET_PCMD_RES_RDY_RD 0xfU
30954 #define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
30955 #define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
30957 #define S_ISSUED_PREF_RD_ER_CLR 20
30958 #define M_ISSUED_PREF_RD_ER_CLR 0xfU
30959 #define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
30960 #define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
30962 #define S_ISSUED_PREF_RD 16
30963 #define M_ISSUED_PREF_RD 0xfU
30964 #define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
30965 #define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
30967 #define S_PCMD_RES_RDY 12
30968 #define M_PCMD_RES_RDY 0xfU
30969 #define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
30970 #define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
30972 #define S_DB_VLD 11
30973 #define V_DB_VLD(x) ((x) << S_DB_VLD)
30974 #define F_DB_VLD V_DB_VLD(1U)
30976 #define S_INJECT0_DRDY 10
30977 #define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
30978 #define F_INJECT0_DRDY V_INJECT0_DRDY(1U)
30980 #define S_INJECT1_DRDY 9
30981 #define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
30982 #define F_INJECT1_DRDY V_INJECT1_DRDY(1U)
30984 #define S_FIRST_BUNDLE 5
30985 #define M_FIRST_BUNDLE 0xfU
30986 #define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
30987 #define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
30989 #define S_GCSUM_MORE_THAN_2_LEFT 1
30990 #define M_GCSUM_MORE_THAN_2_LEFT 0xfU
30991 #define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
30992 #define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
30994 #define S_SDC_DRDY 0
30995 #define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
30996 #define F_SDC_DRDY V_SDC_DRDY(1U)
30998 #define A_PM_TX_DBG_STAT6 0x10032
31000 #define S_PCMD_VLD 31
31001 #define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
31002 #define F_PCMD_VLD V_PCMD_VLD(1U)
31004 #define S_PCMD_CH 29
31005 #define M_PCMD_CH 0x3U
31006 #define V_PCMD_CH(x) ((x) << S_PCMD_CH)
31007 #define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
31009 #define S_STATE_MACHINE_LOC 24
31010 #define M_STATE_MACHINE_LOC 0x1fU
31011 #define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
31012 #define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
31014 #define S_ICSPI_TXVALID 20
31015 #define M_ICSPI_TXVALID 0xfU
31016 #define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
31017 #define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
31019 #define S_ICSPI_TXFULL 16
31020 #define M_ICSPI_TXFULL 0xfU
31021 #define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
31022 #define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
31024 #define S_PCMD_SRDY 12
31025 #define M_PCMD_SRDY 0xfU
31026 #define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
31027 #define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
31029 #define S_PCMD_DRDY 8
31030 #define M_PCMD_DRDY 0xfU
31031 #define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
31032 #define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
31034 #define S_PCMD_CMD 4
31035 #define M_PCMD_CMD 0xfU
31036 #define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
31037 #define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
31039 #define S_OEFIFO_FULL3 3
31040 #define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
31041 #define F_OEFIFO_FULL3 V_OEFIFO_FULL3(1U)
31043 #define S_OEFIFO_FULL2 2
31044 #define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
31045 #define F_OEFIFO_FULL2 V_OEFIFO_FULL2(1U)
31047 #define S_OEFIFO_FULL1 1
31048 #define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
31049 #define F_OEFIFO_FULL1 V_OEFIFO_FULL1(1U)
31051 #define S_OEFIFO_FULL0 0
31052 #define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
31053 #define F_OEFIFO_FULL0 V_OEFIFO_FULL0(1U)
31055 #define A_PM_TX_DBG_STAT7 0x10033
31057 #define S_ICSPI_RXVALID 28
31058 #define M_ICSPI_RXVALID 0xfU
31059 #define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
31060 #define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
31062 #define S_ICSPI_RXFULL 24
31063 #define M_ICSPI_RXFULL 0xfU
31064 #define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
31065 #define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
31067 #define S_OESPI_VALID 20
31068 #define M_OESPI_VALID 0xfU
31069 #define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
31070 #define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
31072 #define S_OESPI_FULL 16
31073 #define M_OESPI_FULL 0xfU
31074 #define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
31075 #define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
31077 #define S_C_RXVALID 12
31078 #define M_C_RXVALID 0xfU
31079 #define V_C_RXVALID(x) ((x) << S_C_RXVALID)
31080 #define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
31082 #define S_C_RXAFULL 8
31083 #define M_C_RXAFULL 0xfU
31084 #define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
31085 #define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
31087 #define S_E_TXVALID3 7
31088 #define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
31089 #define F_E_TXVALID3 V_E_TXVALID3(1U)
31091 #define S_E_TXVALID2 6
31092 #define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
31093 #define F_E_TXVALID2 V_E_TXVALID2(1U)
31095 #define S_E_TXVALID1 5
31096 #define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
31097 #define F_E_TXVALID1 V_E_TXVALID1(1U)
31099 #define S_E_TXVALID0 4
31100 #define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
31101 #define F_E_TXVALID0 V_E_TXVALID0(1U)
31103 #define S_E_TXFULL3 3
31104 #define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
31105 #define F_E_TXFULL3 V_E_TXFULL3(1U)
31107 #define S_E_TXFULL2 2
31108 #define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
31109 #define F_E_TXFULL2 V_E_TXFULL2(1U)
31111 #define S_E_TXFULL1 1
31112 #define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
31113 #define F_E_TXFULL1 V_E_TXFULL1(1U)
31115 #define S_E_TXFULL0 0
31116 #define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
31117 #define F_E_TXFULL0 V_E_TXFULL0(1U)
31119 #define A_PM_TX_DBG_STAT8 0x10034
31121 #define S_MC_RSP_FIFO_CNT 24
31122 #define M_MC_RSP_FIFO_CNT 0x3U
31123 #define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
31124 #define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
31126 #define S_PCMD_FREE_CNT0 14
31127 #define M_PCMD_FREE_CNT0 0x3ffU
31128 #define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
31129 #define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
31131 #define S_PCMD_FREE_CNT1 4
31132 #define M_PCMD_FREE_CNT1 0x3ffU
31133 #define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
31134 #define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
31136 #define S_M_REQADDRRDY 3
31137 #define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
31138 #define F_M_REQADDRRDY V_M_REQADDRRDY(1U)
31140 #define S_M_REQWRITE 2
31141 #define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
31142 #define F_M_REQWRITE V_M_REQWRITE(1U)
31144 #define S_M_REQDATAVLD 1
31145 #define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
31146 #define F_M_REQDATAVLD V_M_REQDATAVLD(1U)
31148 #define S_M_REQDATARDY 0
31149 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
31150 #define F_M_REQDATARDY V_M_REQDATARDY(1U)
31152 #define S_T6_MC_RSP_FIFO_CNT 27
31153 #define M_T6_MC_RSP_FIFO_CNT 0x3U
31154 #define V_T6_MC_RSP_FIFO_CNT(x) ((x) << S_T6_MC_RSP_FIFO_CNT)
31155 #define G_T6_MC_RSP_FIFO_CNT(x) (((x) >> S_T6_MC_RSP_FIFO_CNT) & M_T6_MC_RSP_FIFO_CNT)
31157 #define S_T6_PCMD_FREE_CNT0 17
31158 #define M_T6_PCMD_FREE_CNT0 0x3ffU
31159 #define V_T6_PCMD_FREE_CNT0(x) ((x) << S_T6_PCMD_FREE_CNT0)
31160 #define G_T6_PCMD_FREE_CNT0(x) (((x) >> S_T6_PCMD_FREE_CNT0) & M_T6_PCMD_FREE_CNT0)
31162 #define S_T6_PCMD_FREE_CNT1 7
31163 #define M_T6_PCMD_FREE_CNT1 0x3ffU
31164 #define V_T6_PCMD_FREE_CNT1(x) ((x) << S_T6_PCMD_FREE_CNT1)
31165 #define G_T6_PCMD_FREE_CNT1(x) (((x) >> S_T6_PCMD_FREE_CNT1) & M_T6_PCMD_FREE_CNT1)
31167 #define S_M_RSPVLD 6
31168 #define V_M_RSPVLD(x) ((x) << S_M_RSPVLD)
31169 #define F_M_RSPVLD V_M_RSPVLD(1U)
31171 #define S_M_RSPRDY 5
31172 #define V_M_RSPRDY(x) ((x) << S_M_RSPRDY)
31173 #define F_M_RSPRDY V_M_RSPRDY(1U)
31175 #define S_M_REQADDRVLD 4
31176 #define V_M_REQADDRVLD(x) ((x) << S_M_REQADDRVLD)
31177 #define F_M_REQADDRVLD V_M_REQADDRVLD(1U)
31179 #define A_PM_TX_DBG_STAT9 0x10035
31181 #define S_PCMD_FREE_CNT2 10
31182 #define M_PCMD_FREE_CNT2 0x3ffU
31183 #define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
31184 #define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
31186 #define S_PCMD_FREE_CNT3 0
31187 #define M_PCMD_FREE_CNT3 0x3ffU
31188 #define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
31189 #define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
31191 #define A_PM_TX_DBG_STAT10 0x10036
31193 #define S_IN_EOP_CNT3 28
31194 #define M_IN_EOP_CNT3 0xfU
31195 #define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
31196 #define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
31198 #define S_IN_EOP_CNT2 24
31199 #define M_IN_EOP_CNT2 0xfU
31200 #define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
31201 #define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
31203 #define S_IN_EOP_CNT1 20
31204 #define M_IN_EOP_CNT1 0xfU
31205 #define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
31206 #define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
31208 #define S_IN_EOP_CNT0 16
31209 #define M_IN_EOP_CNT0 0xfU
31210 #define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
31211 #define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
31213 #define S_IN_SOP_CNT3 12
31214 #define M_IN_SOP_CNT3 0xfU
31215 #define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
31216 #define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
31218 #define S_IN_SOP_CNT2 8
31219 #define M_IN_SOP_CNT2 0xfU
31220 #define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
31221 #define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
31223 #define S_IN_SOP_CNT1 4
31224 #define M_IN_SOP_CNT1 0xfU
31225 #define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
31226 #define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
31228 #define S_IN_SOP_CNT0 0
31229 #define M_IN_SOP_CNT0 0xfU
31230 #define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
31231 #define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
31233 #define A_PM_TX_DBG_STAT11 0x10037
31235 #define S_OUT_EOP_CNT3 28
31236 #define M_OUT_EOP_CNT3 0xfU
31237 #define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
31238 #define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
31240 #define S_OUT_EOP_CNT2 24
31241 #define M_OUT_EOP_CNT2 0xfU
31242 #define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
31243 #define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
31245 #define S_OUT_EOP_CNT1 20
31246 #define M_OUT_EOP_CNT1 0xfU
31247 #define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
31248 #define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
31250 #define S_OUT_EOP_CNT0 16
31251 #define M_OUT_EOP_CNT0 0xfU
31252 #define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
31253 #define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
31255 #define S_OUT_SOP_CNT3 12
31256 #define M_OUT_SOP_CNT3 0xfU
31257 #define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
31258 #define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
31260 #define S_OUT_SOP_CNT2 8
31261 #define M_OUT_SOP_CNT2 0xfU
31262 #define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
31263 #define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
31265 #define S_OUT_SOP_CNT1 4
31266 #define M_OUT_SOP_CNT1 0xfU
31267 #define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
31268 #define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
31270 #define S_OUT_SOP_CNT0 0
31271 #define M_OUT_SOP_CNT0 0xfU
31272 #define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
31273 #define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
31275 #define A_PM_TX_DBG_STAT12 0x10038
31276 #define A_PM_TX_DBG_STAT13 0x10039
31278 #define S_CH_DEFICIT_BLOWED 31
31279 #define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
31280 #define F_CH_DEFICIT_BLOWED V_CH_DEFICIT_BLOWED(1U)
31282 #define S_CH1_DEFICIT 16
31283 #define M_CH1_DEFICIT 0xfffU
31284 #define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
31285 #define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
31287 #define S_CH0_DEFICIT 0
31288 #define M_CH0_DEFICIT 0xfffU
31289 #define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
31290 #define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
31292 #define A_PM_TX_DBG_STAT14 0x1003a
31294 #define S_CH3_DEFICIT 16
31295 #define M_CH3_DEFICIT 0xfffU
31296 #define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
31297 #define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
31299 #define S_CH2_DEFICIT 0
31300 #define M_CH2_DEFICIT 0xfffU
31301 #define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
31302 #define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
31304 #define A_PM_TX_DBG_STAT15 0x1003b
31306 #define S_BUNDLE_LEN_SRDY 28
31307 #define M_BUNDLE_LEN_SRDY 0xfU
31308 #define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
31309 #define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
31311 #define S_BUNDLE_LEN1 16
31312 #define M_BUNDLE_LEN1 0xfffU
31313 #define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
31314 #define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
31316 #define S_BUNDLE_LEN0 0
31317 #define M_BUNDLE_LEN0 0xfffU
31318 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
31319 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
31321 #define S_T6_BUNDLE_LEN_SRDY 24
31322 #define M_T6_BUNDLE_LEN_SRDY 0x3U
31323 #define V_T6_BUNDLE_LEN_SRDY(x) ((x) << S_T6_BUNDLE_LEN_SRDY)
31324 #define G_T6_BUNDLE_LEN_SRDY(x) (((x) >> S_T6_BUNDLE_LEN_SRDY) & M_T6_BUNDLE_LEN_SRDY)
31326 #define S_T6_BUNDLE_LEN1 12
31327 #define M_T6_BUNDLE_LEN1 0xfffU
31328 #define V_T6_BUNDLE_LEN1(x) ((x) << S_T6_BUNDLE_LEN1)
31329 #define G_T6_BUNDLE_LEN1(x) (((x) >> S_T6_BUNDLE_LEN1) & M_T6_BUNDLE_LEN1)
31331 #define A_PM_TX_DBG_STAT16 0x1003c
31333 #define S_BUNDLE_LEN3 16
31334 #define M_BUNDLE_LEN3 0xfffU
31335 #define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
31336 #define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
31338 #define S_BUNDLE_LEN2 0
31339 #define M_BUNDLE_LEN2 0xfffU
31340 #define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
31341 #define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
31343 /* registers for module MPS */
31344 #define MPS_BASE_ADDR 0x9000
31346 #define A_MPS_PORT_CTL 0x0
31348 #define S_LPBKEN 31
31349 #define V_LPBKEN(x) ((x) << S_LPBKEN)
31350 #define F_LPBKEN V_LPBKEN(1U)
31352 #define S_PORTTXEN 30
31353 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
31354 #define F_PORTTXEN V_PORTTXEN(1U)
31356 #define S_PORTRXEN 29
31357 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
31358 #define F_PORTRXEN V_PORTRXEN(1U)
31361 #define V_PPPEN(x) ((x) << S_PPPEN)
31362 #define F_PPPEN V_PPPEN(1U)
31364 #define S_FCSSTRIPEN 27
31365 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
31366 #define F_FCSSTRIPEN V_FCSSTRIPEN(1U)
31368 #define S_PPPANDPAUSE 26
31369 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
31370 #define F_PPPANDPAUSE V_PPPANDPAUSE(1U)
31372 #define S_PRIOPPPENMAP 16
31373 #define M_PRIOPPPENMAP 0xffU
31374 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
31375 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
31377 #define A_MPS_VF_CTL 0x0
31378 #define A_MPS_PORT_PAUSE_CTL 0x4
31380 #define S_TIMEUNIT 0
31381 #define M_TIMEUNIT 0xffffU
31382 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
31383 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
31385 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
31387 #define S_REGSENDOFF 24
31388 #define M_REGSENDOFF 0xffU
31389 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
31390 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
31392 #define S_REGSENDON 16
31393 #define M_REGSENDON 0xffU
31394 #define V_REGSENDON(x) ((x) << S_REGSENDON)
31395 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
31397 #define S_SGESENDEN 8
31398 #define M_SGESENDEN 0xffU
31399 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
31400 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
31402 #define S_RXSENDEN 0
31403 #define M_RXSENDEN 0xffU
31404 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
31405 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
31407 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
31409 #define S_XOFFDISABLE 0
31410 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
31411 #define F_XOFFDISABLE V_XOFFDISABLE(1U)
31413 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
31415 #define S_REGHALTON 8
31416 #define M_REGHALTON 0xffU
31417 #define V_REGHALTON(x) ((x) << S_REGHALTON)
31418 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
31420 #define S_RXHALTEN 0
31421 #define M_RXHALTEN 0xffU
31422 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
31423 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
31425 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
31427 #define S_REGSENDING 16
31428 #define M_REGSENDING 0xffU
31429 #define V_REGSENDING(x) ((x) << S_REGSENDING)
31430 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
31432 #define S_SGESENDING 8
31433 #define M_SGESENDING 0xffU
31434 #define V_SGESENDING(x) ((x) << S_SGESENDING)
31435 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
31437 #define S_RXSENDING 0
31438 #define M_RXSENDING 0xffU
31439 #define V_RXSENDING(x) ((x) << S_RXSENDING)
31440 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
31442 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
31444 #define S_REGHALTED 8
31445 #define M_REGHALTED 0xffU
31446 #define V_REGHALTED(x) ((x) << S_REGHALTED)
31447 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
31449 #define S_RXHALTED 0
31450 #define M_RXHALTED 0xffU
31451 #define V_RXHALTED(x) ((x) << S_RXHALTED)
31452 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
31454 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
31455 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
31458 #define M_ADDR 0xffffU
31459 #define V_ADDR(x) ((x) << S_ADDR)
31460 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
31462 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
31463 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
31464 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
31467 #define M_PRTY7 0x3U
31468 #define V_PRTY7(x) ((x) << S_PRTY7)
31469 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
31472 #define M_PRTY6 0x3U
31473 #define V_PRTY6(x) ((x) << S_PRTY6)
31474 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
31477 #define M_PRTY5 0x3U
31478 #define V_PRTY5(x) ((x) << S_PRTY5)
31479 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
31482 #define M_PRTY4 0x3U
31483 #define V_PRTY4(x) ((x) << S_PRTY4)
31484 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
31487 #define M_PRTY3 0x3U
31488 #define V_PRTY3(x) ((x) << S_PRTY3)
31489 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
31492 #define M_PRTY2 0x3U
31493 #define V_PRTY2(x) ((x) << S_PRTY2)
31494 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
31497 #define M_PRTY1 0x3U
31498 #define V_PRTY1(x) ((x) << S_PRTY1)
31499 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
31502 #define M_PRTY0 0x3U
31503 #define V_PRTY0(x) ((x) << S_PRTY0)
31504 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
31506 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
31508 #define S_TXPRTY7 28
31509 #define M_TXPRTY7 0xfU
31510 #define V_TXPRTY7(x) ((x) << S_TXPRTY7)
31511 #define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
31513 #define S_TXPRTY6 24
31514 #define M_TXPRTY6 0xfU
31515 #define V_TXPRTY6(x) ((x) << S_TXPRTY6)
31516 #define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
31518 #define S_TXPRTY5 20
31519 #define M_TXPRTY5 0xfU
31520 #define V_TXPRTY5(x) ((x) << S_TXPRTY5)
31521 #define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
31523 #define S_TXPRTY4 16
31524 #define M_TXPRTY4 0xfU
31525 #define V_TXPRTY4(x) ((x) << S_TXPRTY4)
31526 #define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
31528 #define S_TXPRTY3 12
31529 #define M_TXPRTY3 0xfU
31530 #define V_TXPRTY3(x) ((x) << S_TXPRTY3)
31531 #define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
31533 #define S_TXPRTY2 8
31534 #define M_TXPRTY2 0xfU
31535 #define V_TXPRTY2(x) ((x) << S_TXPRTY2)
31536 #define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
31538 #define S_TXPRTY1 4
31539 #define M_TXPRTY1 0xfU
31540 #define V_TXPRTY1(x) ((x) << S_TXPRTY1)
31541 #define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
31543 #define S_TXPRTY0 0
31544 #define M_TXPRTY0 0xfU
31545 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
31546 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
31548 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
31549 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
31550 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
31551 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
31552 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
31553 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
31554 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
31555 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
31556 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
31557 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
31558 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
31559 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
31560 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
31561 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
31562 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
31563 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
31564 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
31565 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
31566 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
31567 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
31568 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
31569 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
31570 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
31571 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
31572 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
31573 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
31574 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
31575 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
31576 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
31577 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
31578 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
31579 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
31580 #define A_MPS_PORT_RX_CTL 0x100
31582 #define S_NO_RPLCT_M 20
31583 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
31584 #define F_NO_RPLCT_M V_NO_RPLCT_M(1U)
31586 #define S_RPLCT_SEL_L 18
31587 #define M_RPLCT_SEL_L 0x3U
31588 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
31589 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
31591 #define S_FLTR_VLAN_SEL 17
31592 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
31593 #define F_FLTR_VLAN_SEL V_FLTR_VLAN_SEL(1U)
31595 #define S_PRIO_VLAN_SEL 16
31596 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
31597 #define F_PRIO_VLAN_SEL V_PRIO_VLAN_SEL(1U)
31599 #define S_CHK_8023_LEN_M 15
31600 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
31601 #define F_CHK_8023_LEN_M V_CHK_8023_LEN_M(1U)
31603 #define S_CHK_8023_LEN_L 14
31604 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
31605 #define F_CHK_8023_LEN_L V_CHK_8023_LEN_L(1U)
31607 #define S_NIV_DROP 13
31608 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
31609 #define F_NIV_DROP V_NIV_DROP(1U)
31611 #define S_NOV_DROP 12
31612 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
31613 #define F_NOV_DROP V_NOV_DROP(1U)
31615 #define S_CLS_PRT 11
31616 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
31617 #define F_CLS_PRT V_CLS_PRT(1U)
31619 #define S_RX_QFC_EN 10
31620 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
31621 #define F_RX_QFC_EN V_RX_QFC_EN(1U)
31623 #define S_QFC_FWD_UP 9
31624 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
31625 #define F_QFC_FWD_UP V_QFC_FWD_UP(1U)
31627 #define S_PPP_FWD_UP 8
31628 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
31629 #define F_PPP_FWD_UP V_PPP_FWD_UP(1U)
31631 #define S_PAUSE_FWD_UP 7
31632 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
31633 #define F_PAUSE_FWD_UP V_PAUSE_FWD_UP(1U)
31635 #define S_LPBK_BP 6
31636 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
31637 #define F_LPBK_BP V_LPBK_BP(1U)
31639 #define S_PASS_NO_MATCH 5
31640 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
31641 #define F_PASS_NO_MATCH V_PASS_NO_MATCH(1U)
31643 #define S_IVLAN_EN 4
31644 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
31645 #define F_IVLAN_EN V_IVLAN_EN(1U)
31647 #define S_OVLAN_EN3 3
31648 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
31649 #define F_OVLAN_EN3 V_OVLAN_EN3(1U)
31651 #define S_OVLAN_EN2 2
31652 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
31653 #define F_OVLAN_EN2 V_OVLAN_EN2(1U)
31655 #define S_OVLAN_EN1 1
31656 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
31657 #define F_OVLAN_EN1 V_OVLAN_EN1(1U)
31659 #define S_OVLAN_EN0 0
31660 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
31661 #define F_OVLAN_EN0 V_OVLAN_EN0(1U)
31663 #define S_PTP_FWD_UP 21
31664 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
31665 #define F_PTP_FWD_UP V_PTP_FWD_UP(1U)
31667 #define S_HASH_PRIO_SEL_LPBK 25
31668 #define V_HASH_PRIO_SEL_LPBK(x) ((x) << S_HASH_PRIO_SEL_LPBK)
31669 #define F_HASH_PRIO_SEL_LPBK V_HASH_PRIO_SEL_LPBK(1U)
31671 #define S_HASH_PRIO_SEL_MAC 24
31672 #define V_HASH_PRIO_SEL_MAC(x) ((x) << S_HASH_PRIO_SEL_MAC)
31673 #define F_HASH_PRIO_SEL_MAC V_HASH_PRIO_SEL_MAC(1U)
31675 #define S_HASH_EN_LPBK 23
31676 #define V_HASH_EN_LPBK(x) ((x) << S_HASH_EN_LPBK)
31677 #define F_HASH_EN_LPBK V_HASH_EN_LPBK(1U)
31679 #define S_HASH_EN_MAC 22
31680 #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
31681 #define F_HASH_EN_MAC V_HASH_EN_MAC(1U)
31683 #define A_MPS_PORT_RX_MTU 0x104
31684 #define A_MPS_PORT_RX_PF_MAP 0x108
31685 #define A_MPS_PORT_RX_VF_MAP0 0x10c
31686 #define A_MPS_PORT_RX_VF_MAP1 0x110
31687 #define A_MPS_PORT_RX_VF_MAP2 0x114
31688 #define A_MPS_PORT_RX_VF_MAP3 0x118
31689 #define A_MPS_PORT_RX_IVLAN 0x11c
31691 #define S_IVLAN_ETYPE 0
31692 #define M_IVLAN_ETYPE 0xffffU
31693 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
31694 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
31696 #define A_MPS_PORT_RX_OVLAN0 0x120
31698 #define S_OVLAN_MASK 16
31699 #define M_OVLAN_MASK 0xffffU
31700 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
31701 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
31703 #define S_OVLAN_ETYPE 0
31704 #define M_OVLAN_ETYPE 0xffffU
31705 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
31706 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
31708 #define A_MPS_PORT_RX_OVLAN1 0x124
31709 #define A_MPS_PORT_RX_OVLAN2 0x128
31710 #define A_MPS_PORT_RX_OVLAN3 0x12c
31711 #define A_MPS_PORT_RX_RSS_HASH 0x130
31712 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
31714 #define S_RSS_CTRL 16
31715 #define M_RSS_CTRL 0xffU
31716 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
31717 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
31719 #define S_QUE_NUM 0
31720 #define M_QUE_NUM 0xffffU
31721 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
31722 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
31724 #define A_MPS_PORT_RX_CTL1 0x138
31726 #define S_FIXED_PFVF_MAC 13
31727 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
31728 #define F_FIXED_PFVF_MAC V_FIXED_PFVF_MAC(1U)
31730 #define S_FIXED_PFVF_LPBK 12
31731 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
31732 #define F_FIXED_PFVF_LPBK V_FIXED_PFVF_LPBK(1U)
31734 #define S_FIXED_PFVF_LPBK_OV 11
31735 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
31736 #define F_FIXED_PFVF_LPBK_OV V_FIXED_PFVF_LPBK_OV(1U)
31738 #define S_FIXED_PF 8
31739 #define M_FIXED_PF 0x7U
31740 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
31741 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
31743 #define S_FIXED_VF_VLD 7
31744 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
31745 #define F_FIXED_VF_VLD V_FIXED_VF_VLD(1U)
31747 #define S_FIXED_VF 0
31748 #define M_FIXED_VF 0x7fU
31749 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
31750 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
31752 #define S_T6_FIXED_PFVF_MAC 14
31753 #define V_T6_FIXED_PFVF_MAC(x) ((x) << S_T6_FIXED_PFVF_MAC)
31754 #define F_T6_FIXED_PFVF_MAC V_T6_FIXED_PFVF_MAC(1U)
31756 #define S_T6_FIXED_PFVF_LPBK 13
31757 #define V_T6_FIXED_PFVF_LPBK(x) ((x) << S_T6_FIXED_PFVF_LPBK)
31758 #define F_T6_FIXED_PFVF_LPBK V_T6_FIXED_PFVF_LPBK(1U)
31760 #define S_T6_FIXED_PFVF_LPBK_OV 12
31761 #define V_T6_FIXED_PFVF_LPBK_OV(x) ((x) << S_T6_FIXED_PFVF_LPBK_OV)
31762 #define F_T6_FIXED_PFVF_LPBK_OV V_T6_FIXED_PFVF_LPBK_OV(1U)
31764 #define S_T6_FIXED_PF 9
31765 #define M_T6_FIXED_PF 0x7U
31766 #define V_T6_FIXED_PF(x) ((x) << S_T6_FIXED_PF)
31767 #define G_T6_FIXED_PF(x) (((x) >> S_T6_FIXED_PF) & M_T6_FIXED_PF)
31769 #define S_T6_FIXED_VF_VLD 8
31770 #define V_T6_FIXED_VF_VLD(x) ((x) << S_T6_FIXED_VF_VLD)
31771 #define F_T6_FIXED_VF_VLD V_T6_FIXED_VF_VLD(1U)
31773 #define S_T6_FIXED_VF 0
31774 #define M_T6_FIXED_VF 0xffU
31775 #define V_T6_FIXED_VF(x) ((x) << S_T6_FIXED_VF)
31776 #define G_T6_FIXED_VF(x) (((x) >> S_T6_FIXED_VF) & M_T6_FIXED_VF)
31778 #define A_MPS_PORT_RX_SPARE 0x13c
31779 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
31780 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
31781 #define A_MPS_PORT_RX_TS_VLD 0x148
31784 #define M_TS_VLD 0x3U
31785 #define V_TS_VLD(x) ((x) << S_TS_VLD)
31786 #define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD)
31788 #define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
31790 #define S_LKP_SEL 0
31791 #define V_LKP_SEL(x) ((x) << S_LKP_SEL)
31792 #define F_LKP_SEL V_LKP_SEL(1U)
31794 #define A_MPS_PORT_RX_VF_MAP4 0x150
31795 #define A_MPS_PORT_RX_VF_MAP5 0x154
31796 #define A_MPS_PORT_RX_VF_MAP6 0x158
31797 #define A_MPS_PORT_RX_VF_MAP7 0x15c
31798 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
31800 #define S_OUTER_IPV4_N_INNER_IPV4 31
31801 #define V_OUTER_IPV4_N_INNER_IPV4(x) ((x) << S_OUTER_IPV4_N_INNER_IPV4)
31802 #define F_OUTER_IPV4_N_INNER_IPV4 V_OUTER_IPV4_N_INNER_IPV4(1U)
31804 #define S_OUTER_IPV4_N_INNER_IPV6 30
31805 #define V_OUTER_IPV4_N_INNER_IPV6(x) ((x) << S_OUTER_IPV4_N_INNER_IPV6)
31806 #define F_OUTER_IPV4_N_INNER_IPV6 V_OUTER_IPV4_N_INNER_IPV6(1U)
31808 #define S_OUTER_IPV6_N_INNER_IPV4 29
31809 #define V_OUTER_IPV6_N_INNER_IPV4(x) ((x) << S_OUTER_IPV6_N_INNER_IPV4)
31810 #define F_OUTER_IPV6_N_INNER_IPV4 V_OUTER_IPV6_N_INNER_IPV4(1U)
31812 #define S_OUTER_IPV6_N_INNER_IPV6 28
31813 #define V_OUTER_IPV6_N_INNER_IPV6(x) ((x) << S_OUTER_IPV6_N_INNER_IPV6)
31814 #define F_OUTER_IPV6_N_INNER_IPV6 V_OUTER_IPV6_N_INNER_IPV6(1U)
31816 #define S_OUTER_IPV4_N_VLAN_NVGRE 27
31817 #define V_OUTER_IPV4_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_VLAN_NVGRE)
31818 #define F_OUTER_IPV4_N_VLAN_NVGRE V_OUTER_IPV4_N_VLAN_NVGRE(1U)
31820 #define S_OUTER_IPV6_N_VLAN_NVGRE 26
31821 #define V_OUTER_IPV6_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_VLAN_NVGRE)
31822 #define F_OUTER_IPV6_N_VLAN_NVGRE V_OUTER_IPV6_N_VLAN_NVGRE(1U)
31824 #define S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE 25
31825 #define V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE)
31826 #define F_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(1U)
31828 #define S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE 24
31829 #define V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE)
31830 #define F_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(1U)
31832 #define S_OUTER_IPV4_N_VLAN_GRE 23
31833 #define V_OUTER_IPV4_N_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_VLAN_GRE)
31834 #define F_OUTER_IPV4_N_VLAN_GRE V_OUTER_IPV4_N_VLAN_GRE(1U)
31836 #define S_OUTER_IPV6_N_VLAN_GRE 22
31837 #define V_OUTER_IPV6_N_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_VLAN_GRE)
31838 #define F_OUTER_IPV6_N_VLAN_GRE V_OUTER_IPV6_N_VLAN_GRE(1U)
31840 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GRE 21
31841 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GRE)
31842 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GRE V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(1U)
31844 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GRE 20
31845 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GRE)
31846 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GRE V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(1U)
31848 #define S_OUTER_IPV4_N_VLAN_VXLAN 19
31849 #define V_OUTER_IPV4_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_VLAN_VXLAN)
31850 #define F_OUTER_IPV4_N_VLAN_VXLAN V_OUTER_IPV4_N_VLAN_VXLAN(1U)
31852 #define S_OUTER_IPV6_N_VLAN_VXLAN 18
31853 #define V_OUTER_IPV6_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_VLAN_VXLAN)
31854 #define F_OUTER_IPV6_N_VLAN_VXLAN V_OUTER_IPV6_N_VLAN_VXLAN(1U)
31856 #define S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN 17
31857 #define V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN)
31858 #define F_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(1U)
31860 #define S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN 16
31861 #define V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN)
31862 #define F_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(1U)
31864 #define S_OUTER_IPV4_N_VLAN_GENEVE 15
31865 #define V_OUTER_IPV4_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_VLAN_GENEVE)
31866 #define F_OUTER_IPV4_N_VLAN_GENEVE V_OUTER_IPV4_N_VLAN_GENEVE(1U)
31868 #define S_OUTER_IPV6_N_VLAN_GENEVE 14
31869 #define V_OUTER_IPV6_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_VLAN_GENEVE)
31870 #define F_OUTER_IPV6_N_VLAN_GENEVE V_OUTER_IPV6_N_VLAN_GENEVE(1U)
31872 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE 13
31873 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE)
31874 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(1U)
31876 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE 12
31877 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE)
31878 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(1U)
31880 #define S_ERR_TNL_HDR_LEN 11
31881 #define V_ERR_TNL_HDR_LEN(x) ((x) << S_ERR_TNL_HDR_LEN)
31882 #define F_ERR_TNL_HDR_LEN V_ERR_TNL_HDR_LEN(1U)
31884 #define S_NON_RUNT_FRAME 10
31885 #define V_NON_RUNT_FRAME(x) ((x) << S_NON_RUNT_FRAME)
31886 #define F_NON_RUNT_FRAME V_NON_RUNT_FRAME(1U)
31888 #define S_INNER_VLAN_VLD 9
31889 #define V_INNER_VLAN_VLD(x) ((x) << S_INNER_VLAN_VLD)
31890 #define F_INNER_VLAN_VLD V_INNER_VLAN_VLD(1U)
31892 #define S_ERR_IP_PAYLOAD_LEN 8
31893 #define V_ERR_IP_PAYLOAD_LEN(x) ((x) << S_ERR_IP_PAYLOAD_LEN)
31894 #define F_ERR_IP_PAYLOAD_LEN V_ERR_IP_PAYLOAD_LEN(1U)
31896 #define S_ERR_UDP_PAYLOAD_LEN 7
31897 #define V_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_ERR_UDP_PAYLOAD_LEN)
31898 #define F_ERR_UDP_PAYLOAD_LEN V_ERR_UDP_PAYLOAD_LEN(1U)
31900 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
31902 #define S_T6_INNER_VLAN_VLD 10
31903 #define V_T6_INNER_VLAN_VLD(x) ((x) << S_T6_INNER_VLAN_VLD)
31904 #define F_T6_INNER_VLAN_VLD V_T6_INNER_VLAN_VLD(1U)
31906 #define S_T6_ERR_IP_PAYLOAD_LEN 9
31907 #define V_T6_ERR_IP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_IP_PAYLOAD_LEN)
31908 #define F_T6_ERR_IP_PAYLOAD_LEN V_T6_ERR_IP_PAYLOAD_LEN(1U)
31910 #define S_T6_ERR_UDP_PAYLOAD_LEN 8
31911 #define V_T6_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_UDP_PAYLOAD_LEN)
31912 #define F_T6_ERR_UDP_PAYLOAD_LEN V_T6_ERR_UDP_PAYLOAD_LEN(1U)
31914 #define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
31916 #define S_DIS_REPL_VECT_SEL 4
31917 #define V_DIS_REPL_VECT_SEL(x) ((x) << S_DIS_REPL_VECT_SEL)
31918 #define F_DIS_REPL_VECT_SEL V_DIS_REPL_VECT_SEL(1U)
31920 #define S_REPL_VECT_SEL 0
31921 #define M_REPL_VECT_SEL 0xfU
31922 #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
31923 #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
31925 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
31928 #define M_CREDIT 0xffffU
31929 #define V_CREDIT(x) ((x) << S_CREDIT)
31930 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
31932 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
31933 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
31934 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
31935 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
31936 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
31937 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
31938 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
31939 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
31940 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
31941 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
31944 #define M_FIFOTH 0x1ffU
31945 #define V_FIFOTH(x) ((x) << S_FIFOTH)
31946 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
31949 #define V_FIFOEN(x) ((x) << S_FIFOEN)
31950 #define F_FIFOEN V_FIFOEN(1U)
31952 #define S_MAXPKTCNT 0
31953 #define M_MAXPKTCNT 0xfU
31954 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
31955 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
31957 #define S_OUT_TH 22
31958 #define M_OUT_TH 0xffU
31959 #define V_OUT_TH(x) ((x) << S_OUT_TH)
31960 #define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH)
31963 #define M_IN_TH 0xffU
31964 #define V_IN_TH(x) ((x) << S_IN_TH)
31965 #define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH)
31967 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
31969 #define S_FPGAPAUSEEN 0
31970 #define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
31971 #define F_FPGAPAUSEEN V_FPGAPAUSEEN(1U)
31973 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
31975 #define S_OFF_PENDING 8
31976 #define M_OFF_PENDING 0xffU
31977 #define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
31978 #define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
31980 #define S_ON_PENDING 0
31981 #define M_ON_PENDING 0xffU
31982 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
31983 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
31985 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
31988 #define V_VALID(x) ((x) << S_VALID)
31989 #define F_VALID V_VALID(1U)
31991 #define S_HASHPORTMAP 16
31992 #define M_HASHPORTMAP 0xfU
31993 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
31994 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
31996 #define S_MULTILISTEN 15
31997 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
31998 #define F_MULTILISTEN V_MULTILISTEN(1U)
32000 #define S_PRIORITY 12
32001 #define M_PRIORITY 0x7U
32002 #define V_PRIORITY(x) ((x) << S_PRIORITY)
32003 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
32005 #define S_REPLICATE 11
32006 #define V_REPLICATE(x) ((x) << S_REPLICATE)
32007 #define F_REPLICATE V_REPLICATE(1U)
32011 #define V_PF(x) ((x) << S_PF)
32012 #define G_PF(x) (((x) >> S_PF) & M_PF)
32014 #define S_VF_VALID 7
32015 #define V_VF_VALID(x) ((x) << S_VF_VALID)
32016 #define F_VF_VALID V_VF_VALID(1U)
32020 #define V_VF(x) ((x) << S_VF)
32021 #define G_VF(x) (((x) >> S_VF) & M_VF)
32023 #define S_DISENCAPOUTERRPLCT 23
32024 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
32025 #define F_DISENCAPOUTERRPLCT V_DISENCAPOUTERRPLCT(1U)
32027 #define S_DISENCAP 22
32028 #define V_DISENCAP(x) ((x) << S_DISENCAP)
32029 #define F_DISENCAP V_DISENCAP(1U)
32031 #define S_T6_VALID 21
32032 #define V_T6_VALID(x) ((x) << S_T6_VALID)
32033 #define F_T6_VALID V_T6_VALID(1U)
32035 #define S_T6_HASHPORTMAP 17
32036 #define M_T6_HASHPORTMAP 0xfU
32037 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
32038 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
32040 #define S_T6_MULTILISTEN 16
32041 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
32042 #define F_T6_MULTILISTEN V_T6_MULTILISTEN(1U)
32044 #define S_T6_PRIORITY 13
32045 #define M_T6_PRIORITY 0x7U
32046 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
32047 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
32049 #define S_T6_REPLICATE 12
32050 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
32051 #define F_T6_REPLICATE V_T6_REPLICATE(1U)
32054 #define M_T6_PF 0x7U
32055 #define V_T6_PF(x) ((x) << S_T6_PF)
32056 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
32058 #define S_T6_VF_VALID 8
32059 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
32060 #define F_T6_VF_VALID V_T6_VF_VALID(1U)
32063 #define M_T6_VF 0xffU
32064 #define V_T6_VF(x) ((x) << S_T6_VF)
32065 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
32067 #define A_MPS_PF_CTL 0x2c0
32070 #define V_TXEN(x) ((x) << S_TXEN)
32071 #define F_TXEN V_TXEN(1U)
32074 #define V_RXEN(x) ((x) << S_RXEN)
32075 #define F_RXEN V_RXEN(1U)
32077 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
32079 #define S_PROTOCOLID 16
32080 #define M_PROTOCOLID 0xffffU
32081 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
32082 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
32084 #define S_VLAN_PRIO 13
32085 #define M_VLAN_PRIO 0x7U
32086 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
32087 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
32090 #define V_CFI(x) ((x) << S_CFI)
32091 #define F_CFI V_CFI(1U)
32094 #define M_TAG 0xfffU
32095 #define V_TAG(x) ((x) << S_TAG)
32096 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
32098 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
32099 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
32100 #define A_MPS_PORT_CLS_HASH_CTL 0x304
32102 #define S_UNICASTENABLE 31
32103 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
32104 #define F_UNICASTENABLE V_UNICASTENABLE(1U)
32106 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
32107 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
32109 #define S_PROMISCEN 31
32110 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
32111 #define F_PROMISCEN V_PROMISCEN(1U)
32113 #define S_T6_MULTILISTEN 16
32114 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
32115 #define F_T6_MULTILISTEN V_T6_MULTILISTEN(1U)
32117 #define S_T6_PRIORITY 13
32118 #define M_T6_PRIORITY 0x7U
32119 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
32120 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
32122 #define S_T6_REPLICATE 12
32123 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
32124 #define F_T6_REPLICATE V_T6_REPLICATE(1U)
32127 #define M_T6_PF 0x7U
32128 #define V_T6_PF(x) ((x) << S_T6_PF)
32129 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
32131 #define S_T6_VF_VALID 8
32132 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
32133 #define F_T6_VF_VALID V_T6_VF_VALID(1U)
32136 #define M_T6_VF 0xffU
32137 #define V_T6_VF(x) ((x) << S_T6_VF)
32138 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
32140 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
32141 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
32142 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
32143 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
32145 #define S_MATCHBOTH 17
32146 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
32147 #define F_MATCHBOTH V_MATCHBOTH(1U)
32149 #define S_BMC_VLD 16
32150 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
32151 #define F_BMC_VLD V_BMC_VLD(1U)
32153 #define S_MATCHALL 18
32154 #define V_MATCHALL(x) ((x) << S_MATCHALL)
32155 #define F_MATCHALL V_MATCHALL(1U)
32157 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
32158 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
32160 #define S_BMC_VLAN_SEL 13
32161 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
32162 #define F_BMC_VLAN_SEL V_BMC_VLAN_SEL(1U)
32164 #define S_VLAN_VLD 12
32165 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
32166 #define F_VLAN_VLD V_VLAN_VLD(1U)
32168 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
32169 #define A_MPS_PORT_CLS_CTL 0x318
32171 #define S_PF_VLAN_SEL 0
32172 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
32173 #define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U)
32175 #define S_LPBK_TCAM1_HIT_PRIORITY 14
32176 #define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
32177 #define F_LPBK_TCAM1_HIT_PRIORITY V_LPBK_TCAM1_HIT_PRIORITY(1U)
32179 #define S_LPBK_TCAM0_HIT_PRIORITY 13
32180 #define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
32181 #define F_LPBK_TCAM0_HIT_PRIORITY V_LPBK_TCAM0_HIT_PRIORITY(1U)
32183 #define S_LPBK_TCAM_PRIORITY 12
32184 #define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
32185 #define F_LPBK_TCAM_PRIORITY V_LPBK_TCAM_PRIORITY(1U)
32187 #define S_LPBK_SMAC_TCAM_SEL 10
32188 #define M_LPBK_SMAC_TCAM_SEL 0x3U
32189 #define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
32190 #define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
32192 #define S_LPBK_DMAC_TCAM_SEL 8
32193 #define M_LPBK_DMAC_TCAM_SEL 0x3U
32194 #define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
32195 #define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
32197 #define S_TCAM1_HIT_PRIORITY 7
32198 #define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
32199 #define F_TCAM1_HIT_PRIORITY V_TCAM1_HIT_PRIORITY(1U)
32201 #define S_TCAM0_HIT_PRIORITY 6
32202 #define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
32203 #define F_TCAM0_HIT_PRIORITY V_TCAM0_HIT_PRIORITY(1U)
32205 #define S_TCAM_PRIORITY 5
32206 #define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
32207 #define F_TCAM_PRIORITY V_TCAM_PRIORITY(1U)
32209 #define S_SMAC_TCAM_SEL 3
32210 #define M_SMAC_TCAM_SEL 0x3U
32211 #define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
32212 #define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
32214 #define S_DMAC_TCAM_SEL 1
32215 #define M_DMAC_TCAM_SEL 0x3U
32216 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
32217 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
32219 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
32220 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
32222 #define S_ETHTYPE2 0
32223 #define M_ETHTYPE2 0xffffU
32224 #define V_ETHTYPE2(x) ((x) << S_ETHTYPE2)
32225 #define G_ETHTYPE2(x) (((x) >> S_ETHTYPE2) & M_ETHTYPE2)
32227 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
32228 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
32231 #define V_EN1(x) ((x) << S_EN1)
32232 #define F_EN1 V_EN1(1U)
32235 #define V_EN2(x) ((x) << S_EN2)
32236 #define F_EN2 V_EN2(1U)
32238 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
32239 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
32240 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
32241 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
32242 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
32243 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
32244 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
32245 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
32246 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
32247 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
32248 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
32249 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
32250 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
32251 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
32252 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
32253 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
32254 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
32255 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
32256 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
32257 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
32258 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
32259 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
32260 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
32261 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
32262 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
32263 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
32264 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
32265 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
32266 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
32267 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
32268 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
32269 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
32270 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
32271 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
32272 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
32273 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
32274 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
32275 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
32276 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
32277 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
32278 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
32279 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
32280 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
32281 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
32282 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
32283 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
32284 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
32285 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
32286 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
32287 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
32288 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
32289 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
32290 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
32291 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
32292 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
32293 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
32294 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
32295 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
32296 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
32297 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
32298 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
32299 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
32300 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
32301 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
32302 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
32303 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
32304 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
32305 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
32306 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
32307 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
32308 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
32309 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
32310 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
32311 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
32312 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
32313 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
32314 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
32315 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
32316 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
32317 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
32318 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
32319 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
32320 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
32321 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
32322 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
32323 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
32324 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
32325 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
32326 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
32327 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
32328 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
32329 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
32330 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
32331 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
32332 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
32333 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
32334 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
32335 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
32336 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
32337 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
32338 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
32339 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
32340 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
32341 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
32342 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
32343 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
32344 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
32345 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
32346 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
32347 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
32348 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
32349 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
32350 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
32351 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
32352 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
32353 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
32354 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
32355 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
32356 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
32357 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
32358 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
32359 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
32360 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
32361 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
32362 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
32363 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
32364 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
32365 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
32366 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
32367 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
32368 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
32369 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
32370 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
32371 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
32372 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
32373 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
32374 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
32375 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
32376 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
32377 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
32378 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
32379 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
32380 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
32381 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
32382 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
32383 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
32384 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
32385 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
32386 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
32387 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
32388 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
32389 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
32390 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
32391 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
32392 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
32393 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
32394 #define A_MPS_CMN_CTL 0x9000
32396 #define S_DETECT8023 3
32397 #define V_DETECT8023(x) ((x) << S_DETECT8023)
32398 #define F_DETECT8023 V_DETECT8023(1U)
32400 #define S_VFDIRECTACCESS 2
32401 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
32402 #define F_VFDIRECTACCESS V_VFDIRECTACCESS(1U)
32404 #define S_NUMPORTS 0
32405 #define M_NUMPORTS 0x3U
32406 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
32407 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
32409 #define S_LPBKCRDTCTRL 4
32410 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
32411 #define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U)
32413 #define S_TX_PORT_STATS_MODE 8
32414 #define V_TX_PORT_STATS_MODE(x) ((x) << S_TX_PORT_STATS_MODE)
32415 #define F_TX_PORT_STATS_MODE V_TX_PORT_STATS_MODE(1U)
32418 #define V_T5MODE(x) ((x) << S_T5MODE)
32419 #define F_T5MODE V_T5MODE(1U)
32421 #define S_SPEEDMODE 5
32422 #define M_SPEEDMODE 0x3U
32423 #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
32424 #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
32426 #define A_MPS_INT_ENABLE 0x9004
32428 #define S_STATINTENB 5
32429 #define V_STATINTENB(x) ((x) << S_STATINTENB)
32430 #define F_STATINTENB V_STATINTENB(1U)
32432 #define S_TXINTENB 4
32433 #define V_TXINTENB(x) ((x) << S_TXINTENB)
32434 #define F_TXINTENB V_TXINTENB(1U)
32436 #define S_RXINTENB 3
32437 #define V_RXINTENB(x) ((x) << S_RXINTENB)
32438 #define F_RXINTENB V_RXINTENB(1U)
32440 #define S_TRCINTENB 2
32441 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
32442 #define F_TRCINTENB V_TRCINTENB(1U)
32444 #define S_CLSINTENB 1
32445 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
32446 #define F_CLSINTENB V_CLSINTENB(1U)
32448 #define S_PLINTENB 0
32449 #define V_PLINTENB(x) ((x) << S_PLINTENB)
32450 #define F_PLINTENB V_PLINTENB(1U)
32452 #define A_MPS_INT_CAUSE 0x9008
32454 #define S_STATINT 5
32455 #define V_STATINT(x) ((x) << S_STATINT)
32456 #define F_STATINT V_STATINT(1U)
32459 #define V_TXINT(x) ((x) << S_TXINT)
32460 #define F_TXINT V_TXINT(1U)
32463 #define V_RXINT(x) ((x) << S_RXINT)
32464 #define F_RXINT V_RXINT(1U)
32467 #define V_TRCINT(x) ((x) << S_TRCINT)
32468 #define F_TRCINT V_TRCINT(1U)
32471 #define V_CLSINT(x) ((x) << S_CLSINT)
32472 #define F_CLSINT V_CLSINT(1U)
32475 #define V_PLINT(x) ((x) << S_PLINT)
32476 #define F_PLINT V_PLINT(1U)
32478 #define A_MPS_CGEN_GLOBAL 0x900c
32480 #define S_MPS_GLOBAL_CGEN 0
32481 #define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
32482 #define F_MPS_GLOBAL_CGEN V_MPS_GLOBAL_CGEN(1U)
32484 #define A_MPS_VF_TX_CTL_31_0 0x9010
32485 #define A_MPS_VF_TX_CTL_63_32 0x9014
32486 #define A_MPS_VF_TX_CTL_95_64 0x9018
32487 #define A_MPS_VF_TX_CTL_127_96 0x901c
32488 #define A_MPS_VF_RX_CTL_31_0 0x9020
32489 #define A_MPS_VF_RX_CTL_63_32 0x9024
32490 #define A_MPS_VF_RX_CTL_95_64 0x9028
32491 #define A_MPS_VF_RX_CTL_127_96 0x902c
32492 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
32495 #define M_VALUE 0xffffU
32496 #define V_VALUE(x) ((x) << S_VALUE)
32497 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
32499 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
32500 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
32501 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
32502 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
32503 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
32504 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
32505 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
32506 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
32509 #define M_WEIGHT 0xfffU
32510 #define V_WEIGHT(x) ((x) << S_WEIGHT)
32511 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
32513 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
32514 #define A_MPS_WOL_CTL_MODE 0x9058
32516 #define S_WOL_MODE 0
32517 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
32518 #define F_WOL_MODE V_WOL_MODE(1U)
32520 #define A_MPS_FPGA_DEBUG 0x9060
32522 #define S_LPBK_EN 8
32523 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
32524 #define F_LPBK_EN V_LPBK_EN(1U)
32526 #define S_CH_MAP3 6
32527 #define M_CH_MAP3 0x3U
32528 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
32529 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
32531 #define S_CH_MAP2 4
32532 #define M_CH_MAP2 0x3U
32533 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
32534 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
32536 #define S_CH_MAP1 2
32537 #define M_CH_MAP1 0x3U
32538 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
32539 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
32541 #define S_CH_MAP0 0
32542 #define M_CH_MAP0 0x3U
32543 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
32544 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
32546 #define S_FPGA_PTP_PORT 9
32547 #define M_FPGA_PTP_PORT 0x3U
32548 #define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
32549 #define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
32551 #define A_MPS_DEBUG_CTL 0x9068
32553 #define S_DBGMODECTL_H 11
32554 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
32555 #define F_DBGMODECTL_H V_DBGMODECTL_H(1U)
32557 #define S_DBGSEL_H 6
32558 #define M_DBGSEL_H 0x1fU
32559 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
32560 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
32562 #define S_DBGMODECTL_L 5
32563 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
32564 #define F_DBGMODECTL_L V_DBGMODECTL_L(1U)
32566 #define S_DBGSEL_L 0
32567 #define M_DBGSEL_L 0x1fU
32568 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
32569 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
32571 #define A_MPS_DEBUG_DATA_REG_L 0x906c
32572 #define A_MPS_DEBUG_DATA_REG_H 0x9070
32573 #define A_MPS_TOP_SPARE 0x9074
32575 #define S_TOPSPARE 8
32576 #define M_TOPSPARE 0xffffffU
32577 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
32578 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
32580 #define S_OVLANSELLPBK3 7
32581 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
32582 #define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U)
32584 #define S_OVLANSELLPBK2 6
32585 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
32586 #define F_OVLANSELLPBK2 V_OVLANSELLPBK2(1U)
32588 #define S_OVLANSELLPBK1 5
32589 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
32590 #define F_OVLANSELLPBK1 V_OVLANSELLPBK1(1U)
32592 #define S_OVLANSELLPBK0 4
32593 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
32594 #define F_OVLANSELLPBK0 V_OVLANSELLPBK0(1U)
32596 #define S_OVLANSELMAC3 3
32597 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
32598 #define F_OVLANSELMAC3 V_OVLANSELMAC3(1U)
32600 #define S_OVLANSELMAC2 2
32601 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
32602 #define F_OVLANSELMAC2 V_OVLANSELMAC2(1U)
32604 #define S_OVLANSELMAC1 1
32605 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
32606 #define F_OVLANSELMAC1 V_OVLANSELMAC1(1U)
32608 #define S_OVLANSELMAC0 0
32609 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
32610 #define F_OVLANSELMAC0 V_OVLANSELMAC0(1U)
32612 #define S_T5_TOPSPARE 8
32613 #define M_T5_TOPSPARE 0xffffffU
32614 #define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
32615 #define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
32617 #define A_MPS_T5_BUILD_REVISION 0x9078
32618 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
32619 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
32620 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
32621 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
32622 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
32623 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
32624 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
32625 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
32626 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
32627 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
32628 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
32629 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
32630 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
32631 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
32632 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
32633 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
32634 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
32635 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
32636 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
32637 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
32638 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
32639 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
32640 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
32641 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
32642 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
32643 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
32644 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
32645 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
32646 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
32647 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
32648 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
32649 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
32650 #define A_MPS_BUILD_REVISION 0x90fc
32651 #define A_MPS_VF_TX_CTL_159_128 0x9100
32652 #define A_MPS_VF_TX_CTL_191_160 0x9104
32653 #define A_MPS_VF_TX_CTL_223_192 0x9108
32654 #define A_MPS_VF_TX_CTL_255_224 0x910c
32655 #define A_MPS_VF_RX_CTL_159_128 0x9110
32656 #define A_MPS_VF_RX_CTL_191_160 0x9114
32657 #define A_MPS_VF_RX_CTL_223_192 0x9118
32658 #define A_MPS_VF_RX_CTL_255_224 0x911c
32659 #define A_MPS_FPGA_BIST_CFG_P0 0x9120
32661 #define S_ADDRMASK 16
32662 #define M_ADDRMASK 0xffffU
32663 #define V_ADDRMASK(x) ((x) << S_ADDRMASK)
32664 #define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK)
32666 #define S_T6_BASEADDR 0
32667 #define M_T6_BASEADDR 0xffffU
32668 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
32669 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
32671 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
32673 #define S_T6_BASEADDR 0
32674 #define M_T6_BASEADDR 0xffffU
32675 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
32676 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
32678 #define A_MPS_TX_PRTY_SEL 0x9400
32680 #define S_CH4_PRTY 20
32681 #define M_CH4_PRTY 0x7U
32682 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
32683 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
32685 #define S_CH3_PRTY 16
32686 #define M_CH3_PRTY 0x7U
32687 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
32688 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
32690 #define S_CH2_PRTY 12
32691 #define M_CH2_PRTY 0x7U
32692 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
32693 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
32695 #define S_CH1_PRTY 8
32696 #define M_CH1_PRTY 0x7U
32697 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
32698 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
32700 #define S_CH0_PRTY 4
32701 #define M_CH0_PRTY 0x7U
32702 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
32703 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
32705 #define S_TP_SOURCE 2
32706 #define M_TP_SOURCE 0x3U
32707 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
32708 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
32710 #define S_NCSI_SOURCE 0
32711 #define M_NCSI_SOURCE 0x3U
32712 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
32713 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
32715 #define A_MPS_TX_INT_ENABLE 0x9404
32717 #define S_PORTERR 16
32718 #define V_PORTERR(x) ((x) << S_PORTERR)
32719 #define F_PORTERR V_PORTERR(1U)
32721 #define S_FRMERR 15
32722 #define V_FRMERR(x) ((x) << S_FRMERR)
32723 #define F_FRMERR V_FRMERR(1U)
32725 #define S_SECNTERR 14
32726 #define V_SECNTERR(x) ((x) << S_SECNTERR)
32727 #define F_SECNTERR V_SECNTERR(1U)
32729 #define S_BUBBLE 13
32730 #define V_BUBBLE(x) ((x) << S_BUBBLE)
32731 #define F_BUBBLE V_BUBBLE(1U)
32733 #define S_TXDESCFIFO 9
32734 #define M_TXDESCFIFO 0xfU
32735 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
32736 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
32738 #define S_TXDATAFIFO 5
32739 #define M_TXDATAFIFO 0xfU
32740 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
32741 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
32743 #define S_NCSIFIFO 4
32744 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
32745 #define F_NCSIFIFO V_NCSIFIFO(1U)
32748 #define M_TPFIFO 0xfU
32749 #define V_TPFIFO(x) ((x) << S_TPFIFO)
32750 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
32752 #define A_MPS_TX_INT_CAUSE 0x9408
32753 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
32754 #define A_MPS_TX_PERR_ENABLE 0x9410
32755 #define A_MPS_TX_PERR_INJECT 0x9414
32757 #define S_MPSTXMEMSEL 1
32758 #define M_MPSTXMEMSEL 0x1fU
32759 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
32760 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
32762 #define A_MPS_TX_SE_CNT_TP01 0x9418
32763 #define A_MPS_TX_SE_CNT_TP23 0x941c
32764 #define A_MPS_TX_SE_CNT_MAC01 0x9420
32765 #define A_MPS_TX_SE_CNT_MAC23 0x9424
32766 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
32768 #define S_BUBBLEERR 16
32769 #define M_BUBBLEERR 0xffU
32770 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
32771 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
32774 #define M_SPI 0xffU
32775 #define V_SPI(x) ((x) << S_SPI)
32776 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
32779 #define M_SECNT 0xffU
32780 #define V_SECNT(x) ((x) << S_SECNT)
32781 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
32783 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
32785 #define S_BUBBLECLR 8
32786 #define M_BUBBLECLR 0xffU
32787 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
32788 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
32790 #define S_NCSISECNT 20
32791 #define V_NCSISECNT(x) ((x) << S_NCSISECNT)
32792 #define F_NCSISECNT V_NCSISECNT(1U)
32794 #define S_LPBKSECNT 16
32795 #define M_LPBKSECNT 0xfU
32796 #define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
32797 #define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
32799 #define A_MPS_TX_PORT_ERR 0x9430
32801 #define S_LPBKPT3 7
32802 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
32803 #define F_LPBKPT3 V_LPBKPT3(1U)
32805 #define S_LPBKPT2 6
32806 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
32807 #define F_LPBKPT2 V_LPBKPT2(1U)
32809 #define S_LPBKPT1 5
32810 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
32811 #define F_LPBKPT1 V_LPBKPT1(1U)
32813 #define S_LPBKPT0 4
32814 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
32815 #define F_LPBKPT0 V_LPBKPT0(1U)
32818 #define V_PT3(x) ((x) << S_PT3)
32819 #define F_PT3 V_PT3(1U)
32822 #define V_PT2(x) ((x) << S_PT2)
32823 #define F_PT2 V_PT2(1U)
32826 #define V_PT1(x) ((x) << S_PT1)
32827 #define F_PT1 V_PT1(1U)
32830 #define V_PT0(x) ((x) << S_PT0)
32831 #define F_PT0 V_PT0(1U)
32833 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
32836 #define V_BPEN(x) ((x) << S_BPEN)
32837 #define F_BPEN V_BPEN(1U)
32840 #define V_DROPEN(x) ((x) << S_DROPEN)
32841 #define F_DROPEN V_DROPEN(1U)
32843 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
32844 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
32845 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
32846 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
32848 #define S_SOPCH1 31
32849 #define V_SOPCH1(x) ((x) << S_SOPCH1)
32850 #define F_SOPCH1 V_SOPCH1(1U)
32852 #define S_EOPCH1 30
32853 #define V_EOPCH1(x) ((x) << S_EOPCH1)
32854 #define F_EOPCH1 V_EOPCH1(1U)
32856 #define S_SIZECH1 27
32857 #define M_SIZECH1 0x7U
32858 #define V_SIZECH1(x) ((x) << S_SIZECH1)
32859 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
32861 #define S_ERRCH1 26
32862 #define V_ERRCH1(x) ((x) << S_ERRCH1)
32863 #define F_ERRCH1 V_ERRCH1(1U)
32865 #define S_FULLCH1 25
32866 #define V_FULLCH1(x) ((x) << S_FULLCH1)
32867 #define F_FULLCH1 V_FULLCH1(1U)
32869 #define S_VALIDCH1 24
32870 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
32871 #define F_VALIDCH1 V_VALIDCH1(1U)
32873 #define S_DATACH1 16
32874 #define M_DATACH1 0xffU
32875 #define V_DATACH1(x) ((x) << S_DATACH1)
32876 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
32878 #define S_SOPCH0 15
32879 #define V_SOPCH0(x) ((x) << S_SOPCH0)
32880 #define F_SOPCH0 V_SOPCH0(1U)
32882 #define S_EOPCH0 14
32883 #define V_EOPCH0(x) ((x) << S_EOPCH0)
32884 #define F_EOPCH0 V_EOPCH0(1U)
32886 #define S_SIZECH0 11
32887 #define M_SIZECH0 0x7U
32888 #define V_SIZECH0(x) ((x) << S_SIZECH0)
32889 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
32891 #define S_ERRCH0 10
32892 #define V_ERRCH0(x) ((x) << S_ERRCH0)
32893 #define F_ERRCH0 V_ERRCH0(1U)
32895 #define S_FULLCH0 9
32896 #define V_FULLCH0(x) ((x) << S_FULLCH0)
32897 #define F_FULLCH0 V_FULLCH0(1U)
32899 #define S_VALIDCH0 8
32900 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
32901 #define F_VALIDCH0 V_VALIDCH0(1U)
32903 #define S_DATACH0 0
32904 #define M_DATACH0 0xffU
32905 #define V_DATACH0(x) ((x) << S_DATACH0)
32906 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
32908 #define S_T5_SIZECH1 26
32909 #define M_T5_SIZECH1 0xfU
32910 #define V_T5_SIZECH1(x) ((x) << S_T5_SIZECH1)
32911 #define G_T5_SIZECH1(x) (((x) >> S_T5_SIZECH1) & M_T5_SIZECH1)
32913 #define S_T5_ERRCH1 25
32914 #define V_T5_ERRCH1(x) ((x) << S_T5_ERRCH1)
32915 #define F_T5_ERRCH1 V_T5_ERRCH1(1U)
32917 #define S_T5_FULLCH1 24
32918 #define V_T5_FULLCH1(x) ((x) << S_T5_FULLCH1)
32919 #define F_T5_FULLCH1 V_T5_FULLCH1(1U)
32921 #define S_T5_VALIDCH1 23
32922 #define V_T5_VALIDCH1(x) ((x) << S_T5_VALIDCH1)
32923 #define F_T5_VALIDCH1 V_T5_VALIDCH1(1U)
32925 #define S_T5_DATACH1 16
32926 #define M_T5_DATACH1 0x7fU
32927 #define V_T5_DATACH1(x) ((x) << S_T5_DATACH1)
32928 #define G_T5_DATACH1(x) (((x) >> S_T5_DATACH1) & M_T5_DATACH1)
32930 #define S_T5_SIZECH0 10
32931 #define M_T5_SIZECH0 0xfU
32932 #define V_T5_SIZECH0(x) ((x) << S_T5_SIZECH0)
32933 #define G_T5_SIZECH0(x) (((x) >> S_T5_SIZECH0) & M_T5_SIZECH0)
32935 #define S_T5_ERRCH0 9
32936 #define V_T5_ERRCH0(x) ((x) << S_T5_ERRCH0)
32937 #define F_T5_ERRCH0 V_T5_ERRCH0(1U)
32939 #define S_T5_FULLCH0 8
32940 #define V_T5_FULLCH0(x) ((x) << S_T5_FULLCH0)
32941 #define F_T5_FULLCH0 V_T5_FULLCH0(1U)
32943 #define S_T5_VALIDCH0 7
32944 #define V_T5_VALIDCH0(x) ((x) << S_T5_VALIDCH0)
32945 #define F_T5_VALIDCH0 V_T5_VALIDCH0(1U)
32947 #define S_T5_DATACH0 0
32948 #define M_T5_DATACH0 0x7fU
32949 #define V_T5_DATACH0(x) ((x) << S_T5_DATACH0)
32950 #define G_T5_DATACH0(x) (((x) >> S_T5_DATACH0) & M_T5_DATACH0)
32952 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
32954 #define S_SOPCH3 31
32955 #define V_SOPCH3(x) ((x) << S_SOPCH3)
32956 #define F_SOPCH3 V_SOPCH3(1U)
32958 #define S_EOPCH3 30
32959 #define V_EOPCH3(x) ((x) << S_EOPCH3)
32960 #define F_EOPCH3 V_EOPCH3(1U)
32962 #define S_SIZECH3 27
32963 #define M_SIZECH3 0x7U
32964 #define V_SIZECH3(x) ((x) << S_SIZECH3)
32965 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
32967 #define S_ERRCH3 26
32968 #define V_ERRCH3(x) ((x) << S_ERRCH3)
32969 #define F_ERRCH3 V_ERRCH3(1U)
32971 #define S_FULLCH3 25
32972 #define V_FULLCH3(x) ((x) << S_FULLCH3)
32973 #define F_FULLCH3 V_FULLCH3(1U)
32975 #define S_VALIDCH3 24
32976 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
32977 #define F_VALIDCH3 V_VALIDCH3(1U)
32979 #define S_DATACH3 16
32980 #define M_DATACH3 0xffU
32981 #define V_DATACH3(x) ((x) << S_DATACH3)
32982 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
32984 #define S_SOPCH2 15
32985 #define V_SOPCH2(x) ((x) << S_SOPCH2)
32986 #define F_SOPCH2 V_SOPCH2(1U)
32988 #define S_EOPCH2 14
32989 #define V_EOPCH2(x) ((x) << S_EOPCH2)
32990 #define F_EOPCH2 V_EOPCH2(1U)
32992 #define S_SIZECH2 11
32993 #define M_SIZECH2 0x7U
32994 #define V_SIZECH2(x) ((x) << S_SIZECH2)
32995 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
32997 #define S_ERRCH2 10
32998 #define V_ERRCH2(x) ((x) << S_ERRCH2)
32999 #define F_ERRCH2 V_ERRCH2(1U)
33001 #define S_FULLCH2 9
33002 #define V_FULLCH2(x) ((x) << S_FULLCH2)
33003 #define F_FULLCH2 V_FULLCH2(1U)
33005 #define S_VALIDCH2 8
33006 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
33007 #define F_VALIDCH2 V_VALIDCH2(1U)
33009 #define S_DATACH2 0
33010 #define M_DATACH2 0xffU
33011 #define V_DATACH2(x) ((x) << S_DATACH2)
33012 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
33014 #define S_T5_SIZECH3 26
33015 #define M_T5_SIZECH3 0xfU
33016 #define V_T5_SIZECH3(x) ((x) << S_T5_SIZECH3)
33017 #define G_T5_SIZECH3(x) (((x) >> S_T5_SIZECH3) & M_T5_SIZECH3)
33019 #define S_T5_ERRCH3 25
33020 #define V_T5_ERRCH3(x) ((x) << S_T5_ERRCH3)
33021 #define F_T5_ERRCH3 V_T5_ERRCH3(1U)
33023 #define S_T5_FULLCH3 24
33024 #define V_T5_FULLCH3(x) ((x) << S_T5_FULLCH3)
33025 #define F_T5_FULLCH3 V_T5_FULLCH3(1U)
33027 #define S_T5_VALIDCH3 23
33028 #define V_T5_VALIDCH3(x) ((x) << S_T5_VALIDCH3)
33029 #define F_T5_VALIDCH3 V_T5_VALIDCH3(1U)
33031 #define S_T5_DATACH3 16
33032 #define M_T5_DATACH3 0x7fU
33033 #define V_T5_DATACH3(x) ((x) << S_T5_DATACH3)
33034 #define G_T5_DATACH3(x) (((x) >> S_T5_DATACH3) & M_T5_DATACH3)
33036 #define S_T5_SIZECH2 10
33037 #define M_T5_SIZECH2 0xfU
33038 #define V_T5_SIZECH2(x) ((x) << S_T5_SIZECH2)
33039 #define G_T5_SIZECH2(x) (((x) >> S_T5_SIZECH2) & M_T5_SIZECH2)
33041 #define S_T5_ERRCH2 9
33042 #define V_T5_ERRCH2(x) ((x) << S_T5_ERRCH2)
33043 #define F_T5_ERRCH2 V_T5_ERRCH2(1U)
33045 #define S_T5_FULLCH2 8
33046 #define V_T5_FULLCH2(x) ((x) << S_T5_FULLCH2)
33047 #define F_T5_FULLCH2 V_T5_FULLCH2(1U)
33049 #define S_T5_VALIDCH2 7
33050 #define V_T5_VALIDCH2(x) ((x) << S_T5_VALIDCH2)
33051 #define F_T5_VALIDCH2 V_T5_VALIDCH2(1U)
33053 #define S_T5_DATACH2 0
33054 #define M_T5_DATACH2 0x7fU
33055 #define V_T5_DATACH2(x) ((x) << S_T5_DATACH2)
33056 #define G_T5_DATACH2(x) (((x) >> S_T5_DATACH2) & M_T5_DATACH2)
33058 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
33060 #define S_SOPPT1 31
33061 #define V_SOPPT1(x) ((x) << S_SOPPT1)
33062 #define F_SOPPT1 V_SOPPT1(1U)
33064 #define S_EOPPT1 30
33065 #define V_EOPPT1(x) ((x) << S_EOPPT1)
33066 #define F_EOPPT1 V_EOPPT1(1U)
33068 #define S_SIZEPT1 27
33069 #define M_SIZEPT1 0x7U
33070 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
33071 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
33073 #define S_ERRPT1 26
33074 #define V_ERRPT1(x) ((x) << S_ERRPT1)
33075 #define F_ERRPT1 V_ERRPT1(1U)
33077 #define S_FULLPT1 25
33078 #define V_FULLPT1(x) ((x) << S_FULLPT1)
33079 #define F_FULLPT1 V_FULLPT1(1U)
33081 #define S_VALIDPT1 24
33082 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
33083 #define F_VALIDPT1 V_VALIDPT1(1U)
33085 #define S_DATAPT1 16
33086 #define M_DATAPT1 0xffU
33087 #define V_DATAPT1(x) ((x) << S_DATAPT1)
33088 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
33090 #define S_SOPPT0 15
33091 #define V_SOPPT0(x) ((x) << S_SOPPT0)
33092 #define F_SOPPT0 V_SOPPT0(1U)
33094 #define S_EOPPT0 14
33095 #define V_EOPPT0(x) ((x) << S_EOPPT0)
33096 #define F_EOPPT0 V_EOPPT0(1U)
33098 #define S_SIZEPT0 11
33099 #define M_SIZEPT0 0x7U
33100 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
33101 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
33103 #define S_ERRPT0 10
33104 #define V_ERRPT0(x) ((x) << S_ERRPT0)
33105 #define F_ERRPT0 V_ERRPT0(1U)
33107 #define S_FULLPT0 9
33108 #define V_FULLPT0(x) ((x) << S_FULLPT0)
33109 #define F_FULLPT0 V_FULLPT0(1U)
33111 #define S_VALIDPT0 8
33112 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
33113 #define F_VALIDPT0 V_VALIDPT0(1U)
33115 #define S_DATAPT0 0
33116 #define M_DATAPT0 0xffU
33117 #define V_DATAPT0(x) ((x) << S_DATAPT0)
33118 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
33120 #define S_T5_SIZEPT1 26
33121 #define M_T5_SIZEPT1 0xfU
33122 #define V_T5_SIZEPT1(x) ((x) << S_T5_SIZEPT1)
33123 #define G_T5_SIZEPT1(x) (((x) >> S_T5_SIZEPT1) & M_T5_SIZEPT1)
33125 #define S_T5_ERRPT1 25
33126 #define V_T5_ERRPT1(x) ((x) << S_T5_ERRPT1)
33127 #define F_T5_ERRPT1 V_T5_ERRPT1(1U)
33129 #define S_T5_FULLPT1 24
33130 #define V_T5_FULLPT1(x) ((x) << S_T5_FULLPT1)
33131 #define F_T5_FULLPT1 V_T5_FULLPT1(1U)
33133 #define S_T5_VALIDPT1 23
33134 #define V_T5_VALIDPT1(x) ((x) << S_T5_VALIDPT1)
33135 #define F_T5_VALIDPT1 V_T5_VALIDPT1(1U)
33137 #define S_T5_DATAPT1 16
33138 #define M_T5_DATAPT1 0x7fU
33139 #define V_T5_DATAPT1(x) ((x) << S_T5_DATAPT1)
33140 #define G_T5_DATAPT1(x) (((x) >> S_T5_DATAPT1) & M_T5_DATAPT1)
33142 #define S_T5_SIZEPT0 10
33143 #define M_T5_SIZEPT0 0xfU
33144 #define V_T5_SIZEPT0(x) ((x) << S_T5_SIZEPT0)
33145 #define G_T5_SIZEPT0(x) (((x) >> S_T5_SIZEPT0) & M_T5_SIZEPT0)
33147 #define S_T5_ERRPT0 9
33148 #define V_T5_ERRPT0(x) ((x) << S_T5_ERRPT0)
33149 #define F_T5_ERRPT0 V_T5_ERRPT0(1U)
33151 #define S_T5_FULLPT0 8
33152 #define V_T5_FULLPT0(x) ((x) << S_T5_FULLPT0)
33153 #define F_T5_FULLPT0 V_T5_FULLPT0(1U)
33155 #define S_T5_VALIDPT0 7
33156 #define V_T5_VALIDPT0(x) ((x) << S_T5_VALIDPT0)
33157 #define F_T5_VALIDPT0 V_T5_VALIDPT0(1U)
33159 #define S_T5_DATAPT0 0
33160 #define M_T5_DATAPT0 0x7fU
33161 #define V_T5_DATAPT0(x) ((x) << S_T5_DATAPT0)
33162 #define G_T5_DATAPT0(x) (((x) >> S_T5_DATAPT0) & M_T5_DATAPT0)
33164 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
33166 #define S_SOPPT3 31
33167 #define V_SOPPT3(x) ((x) << S_SOPPT3)
33168 #define F_SOPPT3 V_SOPPT3(1U)
33170 #define S_EOPPT3 30
33171 #define V_EOPPT3(x) ((x) << S_EOPPT3)
33172 #define F_EOPPT3 V_EOPPT3(1U)
33174 #define S_SIZEPT3 27
33175 #define M_SIZEPT3 0x7U
33176 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
33177 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
33179 #define S_ERRPT3 26
33180 #define V_ERRPT3(x) ((x) << S_ERRPT3)
33181 #define F_ERRPT3 V_ERRPT3(1U)
33183 #define S_FULLPT3 25
33184 #define V_FULLPT3(x) ((x) << S_FULLPT3)
33185 #define F_FULLPT3 V_FULLPT3(1U)
33187 #define S_VALIDPT3 24
33188 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
33189 #define F_VALIDPT3 V_VALIDPT3(1U)
33191 #define S_DATAPT3 16
33192 #define M_DATAPT3 0xffU
33193 #define V_DATAPT3(x) ((x) << S_DATAPT3)
33194 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
33196 #define S_SOPPT2 15
33197 #define V_SOPPT2(x) ((x) << S_SOPPT2)
33198 #define F_SOPPT2 V_SOPPT2(1U)
33200 #define S_EOPPT2 14
33201 #define V_EOPPT2(x) ((x) << S_EOPPT2)
33202 #define F_EOPPT2 V_EOPPT2(1U)
33204 #define S_SIZEPT2 11
33205 #define M_SIZEPT2 0x7U
33206 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
33207 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
33209 #define S_ERRPT2 10
33210 #define V_ERRPT2(x) ((x) << S_ERRPT2)
33211 #define F_ERRPT2 V_ERRPT2(1U)
33213 #define S_FULLPT2 9
33214 #define V_FULLPT2(x) ((x) << S_FULLPT2)
33215 #define F_FULLPT2 V_FULLPT2(1U)
33217 #define S_VALIDPT2 8
33218 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
33219 #define F_VALIDPT2 V_VALIDPT2(1U)
33221 #define S_DATAPT2 0
33222 #define M_DATAPT2 0xffU
33223 #define V_DATAPT2(x) ((x) << S_DATAPT2)
33224 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
33226 #define S_T5_SIZEPT3 26
33227 #define M_T5_SIZEPT3 0xfU
33228 #define V_T5_SIZEPT3(x) ((x) << S_T5_SIZEPT3)
33229 #define G_T5_SIZEPT3(x) (((x) >> S_T5_SIZEPT3) & M_T5_SIZEPT3)
33231 #define S_T5_ERRPT3 25
33232 #define V_T5_ERRPT3(x) ((x) << S_T5_ERRPT3)
33233 #define F_T5_ERRPT3 V_T5_ERRPT3(1U)
33235 #define S_T5_FULLPT3 24
33236 #define V_T5_FULLPT3(x) ((x) << S_T5_FULLPT3)
33237 #define F_T5_FULLPT3 V_T5_FULLPT3(1U)
33239 #define S_T5_VALIDPT3 23
33240 #define V_T5_VALIDPT3(x) ((x) << S_T5_VALIDPT3)
33241 #define F_T5_VALIDPT3 V_T5_VALIDPT3(1U)
33243 #define S_T5_DATAPT3 16
33244 #define M_T5_DATAPT3 0x7fU
33245 #define V_T5_DATAPT3(x) ((x) << S_T5_DATAPT3)
33246 #define G_T5_DATAPT3(x) (((x) >> S_T5_DATAPT3) & M_T5_DATAPT3)
33248 #define S_T5_SIZEPT2 10
33249 #define M_T5_SIZEPT2 0xfU
33250 #define V_T5_SIZEPT2(x) ((x) << S_T5_SIZEPT2)
33251 #define G_T5_SIZEPT2(x) (((x) >> S_T5_SIZEPT2) & M_T5_SIZEPT2)
33253 #define S_T5_ERRPT2 9
33254 #define V_T5_ERRPT2(x) ((x) << S_T5_ERRPT2)
33255 #define F_T5_ERRPT2 V_T5_ERRPT2(1U)
33257 #define S_T5_FULLPT2 8
33258 #define V_T5_FULLPT2(x) ((x) << S_T5_FULLPT2)
33259 #define F_T5_FULLPT2 V_T5_FULLPT2(1U)
33261 #define S_T5_VALIDPT2 7
33262 #define V_T5_VALIDPT2(x) ((x) << S_T5_VALIDPT2)
33263 #define F_T5_VALIDPT2 V_T5_VALIDPT2(1U)
33265 #define S_T5_DATAPT2 0
33266 #define M_T5_DATAPT2 0x7fU
33267 #define V_T5_DATAPT2(x) ((x) << S_T5_DATAPT2)
33268 #define G_T5_DATAPT2(x) (((x) >> S_T5_DATAPT2) & M_T5_DATAPT2)
33270 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
33272 #define S_SGEPAUSEIGNR 0
33273 #define M_SGEPAUSEIGNR 0xfU
33274 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
33275 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
33277 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
33279 #define S_T5SGEPAUSEIGNR 0
33280 #define M_T5SGEPAUSEIGNR 0xffffU
33281 #define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
33282 #define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
33284 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
33286 #define S_SUBPRTH 11
33287 #define M_SUBPRTH 0x1fU
33288 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
33289 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
33292 #define M_PORTH 0x7U
33293 #define V_PORTH(x) ((x) << S_PORTH)
33294 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
33296 #define S_SUBPRTL 3
33297 #define M_SUBPRTL 0x1fU
33298 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
33299 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
33302 #define M_PORTL 0x7U
33303 #define V_PORTL(x) ((x) << S_PORTL)
33304 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
33306 #define A_MPS_TX_PAD_CTL 0x945c
33308 #define S_LPBKPADENPT3 7
33309 #define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
33310 #define F_LPBKPADENPT3 V_LPBKPADENPT3(1U)
33312 #define S_LPBKPADENPT2 6
33313 #define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
33314 #define F_LPBKPADENPT2 V_LPBKPADENPT2(1U)
33316 #define S_LPBKPADENPT1 5
33317 #define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
33318 #define F_LPBKPADENPT1 V_LPBKPADENPT1(1U)
33320 #define S_LPBKPADENPT0 4
33321 #define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
33322 #define F_LPBKPADENPT0 V_LPBKPADENPT0(1U)
33324 #define S_MACPADENPT3 3
33325 #define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
33326 #define F_MACPADENPT3 V_MACPADENPT3(1U)
33328 #define S_MACPADENPT2 2
33329 #define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
33330 #define F_MACPADENPT2 V_MACPADENPT2(1U)
33332 #define S_MACPADENPT1 1
33333 #define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
33334 #define F_MACPADENPT1 V_MACPADENPT1(1U)
33336 #define S_MACPADENPT0 0
33337 #define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
33338 #define F_MACPADENPT0 V_MACPADENPT0(1U)
33340 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
33342 #define S_TP2MPS_CH3 24
33343 #define M_TP2MPS_CH3 0xffU
33344 #define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
33345 #define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
33347 #define S_TP2MPS_CH2 16
33348 #define M_TP2MPS_CH2 0xffU
33349 #define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
33350 #define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
33352 #define S_TP2MPS_CH1 8
33353 #define M_TP2MPS_CH1 0xffU
33354 #define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
33355 #define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
33357 #define S_TP2MPS_CH0 0
33358 #define M_TP2MPS_CH0 0xffU
33359 #define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
33360 #define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
33362 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
33364 #define S_NCSI_CH4 0
33365 #define M_NCSI_CH4 0xffU
33366 #define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
33367 #define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
33369 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
33371 #define S_PFNOVFDROP 5
33372 #define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
33373 #define F_PFNOVFDROP V_PFNOVFDROP(1U)
33375 #define S_NCSI_CH4_CLR 4
33376 #define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
33377 #define F_NCSI_CH4_CLR V_NCSI_CH4_CLR(1U)
33379 #define S_TP2MPS_CH3_CLR 3
33380 #define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
33381 #define F_TP2MPS_CH3_CLR V_TP2MPS_CH3_CLR(1U)
33383 #define S_TP2MPS_CH2_CLR 2
33384 #define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
33385 #define F_TP2MPS_CH2_CLR V_TP2MPS_CH2_CLR(1U)
33387 #define S_TP2MPS_CH1_CLR 1
33388 #define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
33389 #define F_TP2MPS_CH1_CLR V_TP2MPS_CH1_CLR(1U)
33391 #define S_TP2MPS_CH0_CLR 0
33392 #define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
33393 #define F_TP2MPS_CH0_CLR V_TP2MPS_CH0_CLR(1U)
33395 #define A_MPS_TX_CGEN 0x946c
33397 #define S_TXOUTLPBK3_CGEN 31
33398 #define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
33399 #define F_TXOUTLPBK3_CGEN V_TXOUTLPBK3_CGEN(1U)
33401 #define S_TXOUTLPBK2_CGEN 30
33402 #define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
33403 #define F_TXOUTLPBK2_CGEN V_TXOUTLPBK2_CGEN(1U)
33405 #define S_TXOUTLPBK1_CGEN 29
33406 #define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
33407 #define F_TXOUTLPBK1_CGEN V_TXOUTLPBK1_CGEN(1U)
33409 #define S_TXOUTLPBK0_CGEN 28
33410 #define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
33411 #define F_TXOUTLPBK0_CGEN V_TXOUTLPBK0_CGEN(1U)
33413 #define S_TXOUTMAC3_CGEN 27
33414 #define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
33415 #define F_TXOUTMAC3_CGEN V_TXOUTMAC3_CGEN(1U)
33417 #define S_TXOUTMAC2_CGEN 26
33418 #define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
33419 #define F_TXOUTMAC2_CGEN V_TXOUTMAC2_CGEN(1U)
33421 #define S_TXOUTMAC1_CGEN 25
33422 #define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
33423 #define F_TXOUTMAC1_CGEN V_TXOUTMAC1_CGEN(1U)
33425 #define S_TXOUTMAC0_CGEN 24
33426 #define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
33427 #define F_TXOUTMAC0_CGEN V_TXOUTMAC0_CGEN(1U)
33429 #define S_TXSCHLPBK3_CGEN 23
33430 #define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
33431 #define F_TXSCHLPBK3_CGEN V_TXSCHLPBK3_CGEN(1U)
33433 #define S_TXSCHLPBK2_CGEN 22
33434 #define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
33435 #define F_TXSCHLPBK2_CGEN V_TXSCHLPBK2_CGEN(1U)
33437 #define S_TXSCHLPBK1_CGEN 21
33438 #define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
33439 #define F_TXSCHLPBK1_CGEN V_TXSCHLPBK1_CGEN(1U)
33441 #define S_TXSCHLPBK0_CGEN 20
33442 #define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
33443 #define F_TXSCHLPBK0_CGEN V_TXSCHLPBK0_CGEN(1U)
33445 #define S_TXSCHMAC3_CGEN 19
33446 #define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
33447 #define F_TXSCHMAC3_CGEN V_TXSCHMAC3_CGEN(1U)
33449 #define S_TXSCHMAC2_CGEN 18
33450 #define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
33451 #define F_TXSCHMAC2_CGEN V_TXSCHMAC2_CGEN(1U)
33453 #define S_TXSCHMAC1_CGEN 17
33454 #define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
33455 #define F_TXSCHMAC1_CGEN V_TXSCHMAC1_CGEN(1U)
33457 #define S_TXSCHMAC0_CGEN 16
33458 #define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
33459 #define F_TXSCHMAC0_CGEN V_TXSCHMAC0_CGEN(1U)
33461 #define S_TXINCH4_CGEN 15
33462 #define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
33463 #define F_TXINCH4_CGEN V_TXINCH4_CGEN(1U)
33465 #define S_TXINCH3_CGEN 14
33466 #define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
33467 #define F_TXINCH3_CGEN V_TXINCH3_CGEN(1U)
33469 #define S_TXINCH2_CGEN 13
33470 #define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
33471 #define F_TXINCH2_CGEN V_TXINCH2_CGEN(1U)
33473 #define S_TXINCH1_CGEN 12
33474 #define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
33475 #define F_TXINCH1_CGEN V_TXINCH1_CGEN(1U)
33477 #define S_TXINCH0_CGEN 11
33478 #define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
33479 #define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U)
33481 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
33482 #define A_MPS_STAT_CTL 0x9600
33484 #define S_COUNTVFINPF 1
33485 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
33486 #define F_COUNTVFINPF V_COUNTVFINPF(1U)
33488 #define S_LPBKERRSTAT 0
33489 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
33490 #define F_LPBKERRSTAT V_LPBKERRSTAT(1U)
33492 #define S_STATSTOPCTRL 10
33493 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
33494 #define F_STATSTOPCTRL V_STATSTOPCTRL(1U)
33496 #define S_STOPSTAT 9
33497 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
33498 #define F_STOPSTAT V_STOPSTAT(1U)
33500 #define S_STATWRITECTRL 8
33501 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
33502 #define F_STATWRITECTRL V_STATWRITECTRL(1U)
33504 #define S_COUNTLBPF 7
33505 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
33506 #define F_COUNTLBPF V_COUNTLBPF(1U)
33508 #define S_COUNTLBVF 6
33509 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
33510 #define F_COUNTLBVF V_COUNTLBVF(1U)
33512 #define S_COUNTPAUSEMCRX 5
33513 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
33514 #define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U)
33516 #define S_COUNTPAUSESTATRX 4
33517 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
33518 #define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U)
33520 #define S_COUNTPAUSEMCTX 3
33521 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
33522 #define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U)
33524 #define S_COUNTPAUSESTATTX 2
33525 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
33526 #define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U)
33528 #define A_MPS_STAT_INT_ENABLE 0x9608
33530 #define S_PLREADSYNCERR 0
33531 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
33532 #define F_PLREADSYNCERR V_PLREADSYNCERR(1U)
33534 #define A_MPS_STAT_INT_CAUSE 0x960c
33535 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
33538 #define V_RXBG(x) ((x) << S_RXBG)
33539 #define F_RXBG V_RXBG(1U)
33542 #define M_RXVF 0x3U
33543 #define V_RXVF(x) ((x) << S_RXVF)
33544 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
33547 #define M_TXVF 0x3U
33548 #define V_TXVF(x) ((x) << S_TXVF)
33549 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
33552 #define M_RXPF 0x7U
33553 #define V_RXPF(x) ((x) << S_RXPF)
33554 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
33557 #define M_TXPF 0x3U
33558 #define V_TXPF(x) ((x) << S_TXPF)
33559 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
33562 #define M_RXPORT 0xfU
33563 #define V_RXPORT(x) ((x) << S_RXPORT)
33564 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
33567 #define M_LBPORT 0x7U
33568 #define V_LBPORT(x) ((x) << S_LBPORT)
33569 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
33572 #define M_TXPORT 0xfU
33573 #define V_TXPORT(x) ((x) << S_TXPORT)
33574 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
33576 #define S_T5_RXBG 27
33577 #define M_T5_RXBG 0x3U
33578 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
33579 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
33581 #define S_T5_RXPF 22
33582 #define M_T5_RXPF 0x1fU
33583 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
33584 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
33586 #define S_T5_TXPF 18
33587 #define M_T5_TXPF 0xfU
33588 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
33589 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
33591 #define S_T5_RXPORT 11
33592 #define M_T5_RXPORT 0x7fU
33593 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
33594 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
33596 #define S_T5_LBPORT 6
33597 #define M_T5_LBPORT 0x1fU
33598 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
33599 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
33601 #define S_T5_TXPORT 0
33602 #define M_T5_TXPORT 0x3fU
33603 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
33604 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
33606 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
33607 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
33608 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
33612 #define V_TX(x) ((x) << S_TX)
33613 #define G_TX(x) (((x) >> S_TX) & M_TX)
33615 #define S_TXPAUSEFIFO 8
33616 #define M_TXPAUSEFIFO 0xfU
33617 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
33618 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
33621 #define M_DROP 0xffU
33622 #define V_DROP(x) ((x) << S_DROP)
33623 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
33626 #define M_TXCH 0xfU
33627 #define V_TXCH(x) ((x) << S_TXCH)
33628 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
33630 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
33631 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
33632 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
33634 #define S_PAUSEFIFO 20
33635 #define M_PAUSEFIFO 0xfU
33636 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
33637 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
33640 #define M_LPBK 0xfU
33641 #define V_LPBK(x) ((x) << S_LPBK)
33642 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
33646 #define V_NQ(x) ((x) << S_NQ)
33647 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
33651 #define V_PV(x) ((x) << S_PV)
33652 #define G_PV(x) (((x) >> S_PV) & M_PV)
33656 #define V_MAC(x) ((x) << S_MAC)
33657 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
33659 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
33660 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
33661 #define A_MPS_STAT_PERR_INJECT 0x9634
33663 #define S_STATMEMSEL 1
33664 #define M_STATMEMSEL 0x7fU
33665 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
33666 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
33668 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
33670 #define S_STATSSUBPRTH 5
33671 #define M_STATSSUBPRTH 0x1fU
33672 #define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
33673 #define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
33675 #define S_STATSSUBPRTL 0
33676 #define M_STATSSUBPRTL 0x1fU
33677 #define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
33678 #define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
33680 #define S_STATSUBPRTH 5
33681 #define M_STATSUBPRTH 0x1fU
33682 #define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
33683 #define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
33685 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
33686 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
33687 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
33688 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
33689 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
33690 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
33691 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
33692 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
33693 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
33694 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
33695 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
33696 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
33697 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
33698 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
33699 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
33700 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
33701 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
33702 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
33703 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
33704 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
33705 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
33706 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
33707 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
33708 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
33709 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
33710 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
33711 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
33712 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
33713 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
33714 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
33715 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
33716 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
33717 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
33719 #define S_T5_RXVF 5
33720 #define M_T5_RXVF 0x7U
33721 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
33722 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
33724 #define S_T5_TXVF 0
33725 #define M_T5_TXVF 0x1fU
33726 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
33727 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
33729 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
33730 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
33731 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
33734 #define M_BGRX 0xfU
33735 #define V_BGRX(x) ((x) << S_BGRX)
33736 #define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
33738 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
33741 #define M_PTLPBK 0xfU
33742 #define V_PTLPBK(x) ((x) << S_PTLPBK)
33743 #define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
33746 #define M_PTTX 0xfU
33747 #define V_PTTX(x) ((x) << S_PTTX)
33748 #define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
33751 #define M_PTRX 0xfU
33752 #define V_PTRX(x) ((x) << S_PTRX)
33753 #define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
33755 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
33758 #define M_PFTX 0xffU
33759 #define V_PFTX(x) ((x) << S_PFTX)
33760 #define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
33763 #define M_PFRX 0xffU
33764 #define V_PFRX(x) ((x) << S_PFRX)
33765 #define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
33767 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
33768 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
33769 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
33770 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
33771 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
33772 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
33773 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
33774 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
33775 #define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
33776 #define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
33777 #define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
33778 #define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
33779 #define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
33780 #define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
33781 #define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
33782 #define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
33783 #define A_MPS_TRC_CFG 0x9800
33785 #define S_TRCFIFOEMPTY 4
33786 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
33787 #define F_TRCFIFOEMPTY V_TRCFIFOEMPTY(1U)
33789 #define S_TRCIGNOREDROPINPUT 3
33790 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
33791 #define F_TRCIGNOREDROPINPUT V_TRCIGNOREDROPINPUT(1U)
33793 #define S_TRCKEEPDUPLICATES 2
33794 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
33795 #define F_TRCKEEPDUPLICATES V_TRCKEEPDUPLICATES(1U)
33798 #define V_TRCEN(x) ((x) << S_TRCEN)
33799 #define F_TRCEN V_TRCEN(1U)
33801 #define S_TRCMULTIFILTER 0
33802 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
33803 #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U)
33805 #define S_TRCMULTIRSSFILTER 5
33806 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
33807 #define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U)
33809 #define A_MPS_TRC_RSS_HASH 0x9804
33810 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
33811 #define A_MPS_TRC_RSS_CONTROL 0x9808
33813 #define S_RSSCONTROL 16
33814 #define M_RSSCONTROL 0xffU
33815 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
33816 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
33818 #define S_QUEUENUMBER 0
33819 #define M_QUEUENUMBER 0xffffU
33820 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
33821 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
33823 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
33824 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
33826 #define S_TFINVERTMATCH 24
33827 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
33828 #define F_TFINVERTMATCH V_TFINVERTMATCH(1U)
33830 #define S_TFPKTTOOLARGE 23
33831 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
33832 #define F_TFPKTTOOLARGE V_TFPKTTOOLARGE(1U)
33835 #define V_TFEN(x) ((x) << S_TFEN)
33836 #define F_TFEN V_TFEN(1U)
33838 #define S_TFPORT 18
33839 #define M_TFPORT 0xfU
33840 #define V_TFPORT(x) ((x) << S_TFPORT)
33841 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
33843 #define S_TFDROP 17
33844 #define V_TFDROP(x) ((x) << S_TFDROP)
33845 #define F_TFDROP V_TFDROP(1U)
33847 #define S_TFSOPEOPERR 16
33848 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
33849 #define F_TFSOPEOPERR V_TFSOPEOPERR(1U)
33851 #define S_TFLENGTH 8
33852 #define M_TFLENGTH 0x1fU
33853 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
33854 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
33856 #define S_TFOFFSET 0
33857 #define M_TFOFFSET 0x1fU
33858 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
33859 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
33861 #define S_TFINSERTACTLEN 27
33862 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
33863 #define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U)
33865 #define S_TFINSERTTIMER 26
33866 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
33867 #define F_TFINSERTTIMER V_TFINSERTTIMER(1U)
33869 #define S_T5_TFINVERTMATCH 25
33870 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
33871 #define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U)
33873 #define S_T5_TFPKTTOOLARGE 24
33874 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
33875 #define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U)
33877 #define S_T5_TFEN 23
33878 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
33879 #define F_T5_TFEN V_T5_TFEN(1U)
33881 #define S_T5_TFPORT 18
33882 #define M_T5_TFPORT 0x1fU
33883 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
33884 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
33886 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
33888 #define S_TFMINPKTSIZE 16
33889 #define M_TFMINPKTSIZE 0x1ffU
33890 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
33891 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
33893 #define S_TFCAPTUREMAX 0
33894 #define M_TFCAPTUREMAX 0x3fffU
33895 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
33896 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
33898 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
33900 #define S_TFRUNTSIZE 0
33901 #define M_TFRUNTSIZE 0x3fU
33902 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
33903 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
33905 #define A_MPS_TRC_FILTER_DROP 0x9840
33907 #define S_TFDROPINPCOUNT 16
33908 #define M_TFDROPINPCOUNT 0xffffU
33909 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
33910 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
33912 #define S_TFDROPBUFFERCOUNT 0
33913 #define M_TFDROPBUFFERCOUNT 0xffffU
33914 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
33915 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
33917 #define A_MPS_TRC_PERR_INJECT 0x9850
33919 #define S_TRCMEMSEL 1
33920 #define M_TRCMEMSEL 0xfU
33921 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
33922 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
33924 #define A_MPS_TRC_PERR_ENABLE 0x9854
33926 #define S_MISCPERR 8
33927 #define V_MISCPERR(x) ((x) << S_MISCPERR)
33928 #define F_MISCPERR V_MISCPERR(1U)
33930 #define S_PKTFIFO 4
33931 #define M_PKTFIFO 0xfU
33932 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
33933 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
33935 #define S_FILTMEM 0
33936 #define M_FILTMEM 0xfU
33937 #define V_FILTMEM(x) ((x) << S_FILTMEM)
33938 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
33940 #define A_MPS_TRC_INT_ENABLE 0x9858
33942 #define S_TRCPLERRENB 9
33943 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
33944 #define F_TRCPLERRENB V_TRCPLERRENB(1U)
33946 #define A_MPS_TRC_INT_CAUSE 0x985c
33947 #define A_MPS_TRC_TIMESTAMP_L 0x9860
33948 #define A_MPS_TRC_TIMESTAMP_H 0x9864
33949 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
33950 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
33951 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
33952 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
33953 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
33954 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
33955 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
33956 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
33957 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
33958 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
33959 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
33960 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
33961 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
33962 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
33963 #define A_MPS_T5_TRC_RSS_HASH 0xa008
33964 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
33965 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
33967 #define S_TRCMPS2TP_MACONLY 20
33968 #define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
33969 #define F_TRCMPS2TP_MACONLY V_TRCMPS2TP_MACONLY(1U)
33971 #define S_TRCALLMPS2TP 19
33972 #define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
33973 #define F_TRCALLMPS2TP V_TRCALLMPS2TP(1U)
33975 #define S_TRCALLTP2MPS 18
33976 #define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
33977 #define F_TRCALLTP2MPS V_TRCALLTP2MPS(1U)
33979 #define S_TRCALLVF 17
33980 #define V_TRCALLVF(x) ((x) << S_TRCALLVF)
33981 #define F_TRCALLVF V_TRCALLVF(1U)
33983 #define S_TRC_OFLD_EN 16
33984 #define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
33985 #define F_TRC_OFLD_EN V_TRC_OFLD_EN(1U)
33987 #define S_VFFILTEN 15
33988 #define V_VFFILTEN(x) ((x) << S_VFFILTEN)
33989 #define F_VFFILTEN V_VFFILTEN(1U)
33991 #define S_VFFILTMASK 8
33992 #define M_VFFILTMASK 0x7fU
33993 #define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
33994 #define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
33996 #define S_VFFILTVALID 7
33997 #define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
33998 #define F_VFFILTVALID V_VFFILTVALID(1U)
34000 #define S_VFFILTDATA 0
34001 #define M_VFFILTDATA 0x7fU
34002 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
34003 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
34005 #define S_T6_TRCMPS2TP_MACONLY 22
34006 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34007 #define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U)
34009 #define S_T6_TRCALLMPS2TP 21
34010 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34011 #define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U)
34013 #define S_T6_TRCALLTP2MPS 20
34014 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34015 #define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U)
34017 #define S_T6_TRCALLVF 19
34018 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34019 #define F_T6_TRCALLVF V_T6_TRCALLVF(1U)
34021 #define S_T6_TRC_OFLD_EN 18
34022 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34023 #define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U)
34025 #define S_T6_VFFILTEN 17
34026 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34027 #define F_T6_VFFILTEN V_T6_VFFILTEN(1U)
34029 #define S_T6_VFFILTMASK 9
34030 #define M_T6_VFFILTMASK 0xffU
34031 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34032 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34034 #define S_T6_VFFILTVALID 8
34035 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34036 #define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U)
34038 #define S_T6_VFFILTDATA 0
34039 #define M_T6_VFFILTDATA 0xffU
34040 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34041 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34043 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
34045 #define S_T6_TRCMPS2TP_MACONLY 22
34046 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34047 #define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U)
34049 #define S_T6_TRCALLMPS2TP 21
34050 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34051 #define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U)
34053 #define S_T6_TRCALLTP2MPS 20
34054 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34055 #define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U)
34057 #define S_T6_TRCALLVF 19
34058 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34059 #define F_T6_TRCALLVF V_T6_TRCALLVF(1U)
34061 #define S_T6_TRC_OFLD_EN 18
34062 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34063 #define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U)
34065 #define S_T6_VFFILTEN 17
34066 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34067 #define F_T6_VFFILTEN V_T6_VFFILTEN(1U)
34069 #define S_T6_VFFILTMASK 9
34070 #define M_T6_VFFILTMASK 0xffU
34071 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34072 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34074 #define S_T6_VFFILTVALID 8
34075 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34076 #define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U)
34078 #define S_T6_VFFILTDATA 0
34079 #define M_T6_VFFILTDATA 0xffU
34080 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34081 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34083 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
34085 #define S_T6_TRCMPS2TP_MACONLY 22
34086 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34087 #define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U)
34089 #define S_T6_TRCALLMPS2TP 21
34090 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34091 #define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U)
34093 #define S_T6_TRCALLTP2MPS 20
34094 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34095 #define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U)
34097 #define S_T6_TRCALLVF 19
34098 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34099 #define F_T6_TRCALLVF V_T6_TRCALLVF(1U)
34101 #define S_T6_TRC_OFLD_EN 18
34102 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34103 #define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U)
34105 #define S_T6_VFFILTEN 17
34106 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34107 #define F_T6_VFFILTEN V_T6_VFFILTEN(1U)
34109 #define S_T6_VFFILTMASK 9
34110 #define M_T6_VFFILTMASK 0xffU
34111 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34112 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34114 #define S_T6_VFFILTVALID 8
34115 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34116 #define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U)
34118 #define S_T6_VFFILTDATA 0
34119 #define M_T6_VFFILTDATA 0xffU
34120 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34121 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34123 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
34125 #define S_T6_TRCMPS2TP_MACONLY 22
34126 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34127 #define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U)
34129 #define S_T6_TRCALLMPS2TP 21
34130 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34131 #define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U)
34133 #define S_T6_TRCALLTP2MPS 20
34134 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34135 #define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U)
34137 #define S_T6_TRCALLVF 19
34138 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34139 #define F_T6_TRCALLVF V_T6_TRCALLVF(1U)
34141 #define S_T6_TRC_OFLD_EN 18
34142 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34143 #define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U)
34145 #define S_T6_VFFILTEN 17
34146 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34147 #define F_T6_VFFILTEN V_T6_VFFILTEN(1U)
34149 #define S_T6_VFFILTMASK 9
34150 #define M_T6_VFFILTMASK 0xffU
34151 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34152 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34154 #define S_T6_VFFILTVALID 8
34155 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34156 #define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U)
34158 #define S_T6_VFFILTDATA 0
34159 #define M_T6_VFFILTDATA 0xffU
34160 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34161 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34163 #define A_MPS_TRC_CGEN 0xa020
34165 #define S_MPSTRCCGEN 0
34166 #define M_MPSTRCCGEN 0xfU
34167 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
34168 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
34170 #define A_MPS_CLS_CTL 0xd000
34172 #define S_MEMWRITEFAULT 4
34173 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
34174 #define F_MEMWRITEFAULT V_MEMWRITEFAULT(1U)
34176 #define S_MEMWRITEWAITING 3
34177 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
34178 #define F_MEMWRITEWAITING V_MEMWRITEWAITING(1U)
34180 #define S_CIMNOPROMISCUOUS 2
34181 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
34182 #define F_CIMNOPROMISCUOUS V_CIMNOPROMISCUOUS(1U)
34184 #define S_HYPERVISORONLY 1
34185 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
34186 #define F_HYPERVISORONLY V_HYPERVISORONLY(1U)
34188 #define S_VLANCLSEN 0
34189 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
34190 #define F_VLANCLSEN V_VLANCLSEN(1U)
34192 #define S_VLANCLSEN_IN 7
34193 #define V_VLANCLSEN_IN(x) ((x) << S_VLANCLSEN_IN)
34194 #define F_VLANCLSEN_IN V_VLANCLSEN_IN(1U)
34196 #define S_DISTCAMPARCHK 6
34197 #define V_DISTCAMPARCHK(x) ((x) << S_DISTCAMPARCHK)
34198 #define F_DISTCAMPARCHK V_DISTCAMPARCHK(1U)
34200 #define S_VLANLKPEN 5
34201 #define V_VLANLKPEN(x) ((x) << S_VLANLKPEN)
34202 #define F_VLANLKPEN V_VLANLKPEN(1U)
34204 #define A_MPS_CLS_ARB_WEIGHT 0xd004
34206 #define S_PLWEIGHT 16
34207 #define M_PLWEIGHT 0x1fU
34208 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
34209 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
34211 #define S_CIMWEIGHT 8
34212 #define M_CIMWEIGHT 0x1fU
34213 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
34214 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
34216 #define S_LPBKWEIGHT 0
34217 #define M_LPBKWEIGHT 0x1fU
34218 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
34219 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
34221 #define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
34222 #define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
34223 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
34224 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
34225 #define A_MPS_CLS_BMC_VLAN 0xd018
34226 #define A_MPS_CLS_PERR_INJECT 0xd01c
34228 #define S_CLS_MEMSEL 1
34229 #define M_CLS_MEMSEL 0x3U
34230 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
34231 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
34233 #define A_MPS_CLS_PERR_ENABLE 0xd020
34235 #define S_HASHSRAM 2
34236 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
34237 #define F_HASHSRAM V_HASHSRAM(1U)
34239 #define S_MATCHTCAM 1
34240 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
34241 #define F_MATCHTCAM V_MATCHTCAM(1U)
34243 #define S_MATCHSRAM 0
34244 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
34245 #define F_MATCHSRAM V_MATCHSRAM(1U)
34247 #define A_MPS_CLS_INT_ENABLE 0xd024
34249 #define S_PLERRENB 3
34250 #define V_PLERRENB(x) ((x) << S_PLERRENB)
34251 #define F_PLERRENB V_PLERRENB(1U)
34253 #define A_MPS_CLS_INT_CAUSE 0xd028
34254 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
34255 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
34256 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
34258 #define S_CLS_PRIORITY 24
34259 #define M_CLS_PRIORITY 0x7U
34260 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
34261 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
34263 #define S_CLS_REPLICATE 23
34264 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
34265 #define F_CLS_REPLICATE V_CLS_REPLICATE(1U)
34267 #define S_CLS_INDEX 14
34268 #define M_CLS_INDEX 0x1ffU
34269 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
34270 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
34273 #define M_CLS_VF 0x7fU
34274 #define V_CLS_VF(x) ((x) << S_CLS_VF)
34275 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
34277 #define S_CLS_VF_VLD 6
34278 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
34279 #define F_CLS_VF_VLD V_CLS_VF_VLD(1U)
34282 #define M_CLS_PF 0x7U
34283 #define V_CLS_PF(x) ((x) << S_CLS_PF)
34284 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
34286 #define S_CLS_MATCH 0
34287 #define M_CLS_MATCH 0x7U
34288 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
34289 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
34291 #define S_CLS_SPARE 28
34292 #define M_CLS_SPARE 0xfU
34293 #define V_CLS_SPARE(x) ((x) << S_CLS_SPARE)
34294 #define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE)
34296 #define S_T6_CLS_PRIORITY 25
34297 #define M_T6_CLS_PRIORITY 0x7U
34298 #define V_T6_CLS_PRIORITY(x) ((x) << S_T6_CLS_PRIORITY)
34299 #define G_T6_CLS_PRIORITY(x) (((x) >> S_T6_CLS_PRIORITY) & M_T6_CLS_PRIORITY)
34301 #define S_T6_CLS_REPLICATE 24
34302 #define V_T6_CLS_REPLICATE(x) ((x) << S_T6_CLS_REPLICATE)
34303 #define F_T6_CLS_REPLICATE V_T6_CLS_REPLICATE(1U)
34305 #define S_T6_CLS_INDEX 15
34306 #define M_T6_CLS_INDEX 0x1ffU
34307 #define V_T6_CLS_INDEX(x) ((x) << S_T6_CLS_INDEX)
34308 #define G_T6_CLS_INDEX(x) (((x) >> S_T6_CLS_INDEX) & M_T6_CLS_INDEX)
34310 #define S_T6_CLS_VF 7
34311 #define M_T6_CLS_VF 0xffU
34312 #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
34313 #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
34315 #define A_MPS_CLS_PL_TEST_CTL 0xd038
34317 #define S_PLTESTCTL 0
34318 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
34319 #define F_PLTESTCTL V_PLTESTCTL(1U)
34321 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
34323 #define S_PRTBMCCTL 0
34324 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
34325 #define F_PRTBMCCTL V_PRTBMCCTL(1U)
34327 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
34328 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
34329 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
34330 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
34331 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
34332 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
34333 #define A_MPS_CLS_MISS_CNT 0xd118
34334 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
34335 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
34337 #define S_CLSTRCMACDAHI 0
34338 #define M_CLSTRCMACDAHI 0xffffU
34339 #define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI)
34340 #define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI)
34342 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
34343 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
34345 #define S_CLSTRCMACSAHI 0
34346 #define M_CLSTRCMACSAHI 0xffffU
34347 #define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI)
34348 #define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI)
34350 #define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
34352 #define S_CLSTRCVLANVLD 31
34353 #define V_CLSTRCVLANVLD(x) ((x) << S_CLSTRCVLANVLD)
34354 #define F_CLSTRCVLANVLD V_CLSTRCVLANVLD(1U)
34356 #define S_CLSTRCVLANID 16
34357 #define M_CLSTRCVLANID 0xfffU
34358 #define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID)
34359 #define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID)
34361 #define S_CLSTRCREQPORT 0
34362 #define M_CLSTRCREQPORT 0xfU
34363 #define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT)
34364 #define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT)
34366 #define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
34368 #define S_CLSTRCLKPTYPE 31
34369 #define V_CLSTRCLKPTYPE(x) ((x) << S_CLSTRCLKPTYPE)
34370 #define F_CLSTRCLKPTYPE V_CLSTRCLKPTYPE(1U)
34372 #define S_CLSTRCDIPHIT 30
34373 #define V_CLSTRCDIPHIT(x) ((x) << S_CLSTRCDIPHIT)
34374 #define F_CLSTRCDIPHIT V_CLSTRCDIPHIT(1U)
34376 #define S_CLSTRCVNI 0
34377 #define M_CLSTRCVNI 0xffffffU
34378 #define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI)
34379 #define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI)
34381 #define A_MPS_CLS_RESULT_TRACE 0xd300
34383 #define S_CLSTRCPORTNUM 31
34384 #define V_CLSTRCPORTNUM(x) ((x) << S_CLSTRCPORTNUM)
34385 #define F_CLSTRCPORTNUM V_CLSTRCPORTNUM(1U)
34387 #define S_CLSTRCPRIORITY 28
34388 #define M_CLSTRCPRIORITY 0x7U
34389 #define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY)
34390 #define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY)
34392 #define S_CLSTRCMULTILISTEN 27
34393 #define V_CLSTRCMULTILISTEN(x) ((x) << S_CLSTRCMULTILISTEN)
34394 #define F_CLSTRCMULTILISTEN V_CLSTRCMULTILISTEN(1U)
34396 #define S_CLSTRCREPLICATE 26
34397 #define V_CLSTRCREPLICATE(x) ((x) << S_CLSTRCREPLICATE)
34398 #define F_CLSTRCREPLICATE V_CLSTRCREPLICATE(1U)
34400 #define S_CLSTRCPORTMAP 24
34401 #define M_CLSTRCPORTMAP 0x3U
34402 #define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP)
34403 #define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP)
34405 #define S_CLSTRCMATCH 21
34406 #define M_CLSTRCMATCH 0x7U
34407 #define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH)
34408 #define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH)
34410 #define S_CLSTRCINDEX 12
34411 #define M_CLSTRCINDEX 0x1ffU
34412 #define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX)
34413 #define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX)
34415 #define S_CLSTRCVF_VLD 11
34416 #define V_CLSTRCVF_VLD(x) ((x) << S_CLSTRCVF_VLD)
34417 #define F_CLSTRCVF_VLD V_CLSTRCVF_VLD(1U)
34419 #define S_CLSTRCPF 3
34420 #define M_CLSTRCPF 0xffU
34421 #define V_CLSTRCPF(x) ((x) << S_CLSTRCPF)
34422 #define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF)
34424 #define S_CLSTRCVF 0
34425 #define M_CLSTRCVF 0x7U
34426 #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
34427 #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
34429 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
34431 #define S_VLAN_MASK 16
34432 #define M_VLAN_MASK 0xfffU
34433 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
34434 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
34436 #define S_VLANPF 13
34437 #define M_VLANPF 0x7U
34438 #define V_VLANPF(x) ((x) << S_VLANPF)
34439 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
34441 #define S_VLAN_VALID 12
34442 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
34443 #define F_VLAN_VALID V_VLAN_VALID(1U)
34445 #define A_MPS_CLS_SRAM_L 0xe000
34447 #define S_MULTILISTEN3 28
34448 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
34449 #define F_MULTILISTEN3 V_MULTILISTEN3(1U)
34451 #define S_MULTILISTEN2 27
34452 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
34453 #define F_MULTILISTEN2 V_MULTILISTEN2(1U)
34455 #define S_MULTILISTEN1 26
34456 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
34457 #define F_MULTILISTEN1 V_MULTILISTEN1(1U)
34459 #define S_MULTILISTEN0 25
34460 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
34461 #define F_MULTILISTEN0 V_MULTILISTEN0(1U)
34463 #define S_SRAM_PRIO3 22
34464 #define M_SRAM_PRIO3 0x7U
34465 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
34466 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
34468 #define S_SRAM_PRIO2 19
34469 #define M_SRAM_PRIO2 0x7U
34470 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
34471 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
34473 #define S_SRAM_PRIO1 16
34474 #define M_SRAM_PRIO1 0x7U
34475 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
34476 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
34478 #define S_SRAM_PRIO0 13
34479 #define M_SRAM_PRIO0 0x7U
34480 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
34481 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
34483 #define S_SRAM_VLD 12
34484 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
34485 #define F_SRAM_VLD V_SRAM_VLD(1U)
34487 #define A_MPS_T5_CLS_SRAM_L 0xe000
34489 #define S_T6_DISENCAPOUTERRPLCT 31
34490 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
34491 #define F_T6_DISENCAPOUTERRPLCT V_T6_DISENCAPOUTERRPLCT(1U)
34493 #define S_T6_DISENCAP 30
34494 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
34495 #define F_T6_DISENCAP V_T6_DISENCAP(1U)
34497 #define S_T6_MULTILISTEN3 29
34498 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
34499 #define F_T6_MULTILISTEN3 V_T6_MULTILISTEN3(1U)
34501 #define S_T6_MULTILISTEN2 28
34502 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
34503 #define F_T6_MULTILISTEN2 V_T6_MULTILISTEN2(1U)
34505 #define S_T6_MULTILISTEN1 27
34506 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
34507 #define F_T6_MULTILISTEN1 V_T6_MULTILISTEN1(1U)
34509 #define S_T6_MULTILISTEN0 26
34510 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
34511 #define F_T6_MULTILISTEN0 V_T6_MULTILISTEN0(1U)
34513 #define S_T6_SRAM_PRIO3 23
34514 #define M_T6_SRAM_PRIO3 0x7U
34515 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
34516 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
34518 #define S_T6_SRAM_PRIO2 20
34519 #define M_T6_SRAM_PRIO2 0x7U
34520 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
34521 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
34523 #define S_T6_SRAM_PRIO1 17
34524 #define M_T6_SRAM_PRIO1 0x7U
34525 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
34526 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
34528 #define S_T6_SRAM_PRIO0 14
34529 #define M_T6_SRAM_PRIO0 0x7U
34530 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
34531 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
34533 #define S_T6_SRAM_VLD 13
34534 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
34535 #define F_T6_SRAM_VLD V_T6_SRAM_VLD(1U)
34537 #define S_T6_REPLICATE 12
34538 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
34539 #define F_T6_REPLICATE V_T6_REPLICATE(1U)
34542 #define M_T6_PF 0x7U
34543 #define V_T6_PF(x) ((x) << S_T6_PF)
34544 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
34546 #define S_T6_VF_VALID 8
34547 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
34548 #define F_T6_VF_VALID V_T6_VF_VALID(1U)
34551 #define M_T6_VF 0xffU
34552 #define V_T6_VF(x) ((x) << S_T6_VF)
34553 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
34555 #define A_MPS_CLS_SRAM_H 0xe004
34557 #define S_MACPARITY1 9
34558 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
34559 #define F_MACPARITY1 V_MACPARITY1(1U)
34561 #define S_MACPARITY0 8
34562 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
34563 #define F_MACPARITY0 V_MACPARITY0(1U)
34565 #define S_MACPARITYMASKSIZE 4
34566 #define M_MACPARITYMASKSIZE 0xfU
34567 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
34568 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
34570 #define S_PORTMAP 0
34571 #define M_PORTMAP 0xfU
34572 #define V_PORTMAP(x) ((x) << S_PORTMAP)
34573 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
34575 #define A_MPS_T5_CLS_SRAM_H 0xe004
34577 #define S_MACPARITY2 10
34578 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
34579 #define F_MACPARITY2 V_MACPARITY2(1U)
34581 #define A_MPS_CLS_TCAM_Y_L 0xf000
34582 #define A_MPS_CLS_TCAM_DATA0 0xf000
34583 #define A_MPS_CLS_TCAM_Y_H 0xf004
34586 #define M_TCAMYH 0xffffU
34587 #define V_TCAMYH(x) ((x) << S_TCAMYH)
34588 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
34590 #define A_MPS_CLS_TCAM_DATA1 0xf004
34593 #define M_VIDL 0xffffU
34594 #define V_VIDL(x) ((x) << S_VIDL)
34595 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
34598 #define M_DMACH 0xffffU
34599 #define V_DMACH(x) ((x) << S_DMACH)
34600 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
34602 #define A_MPS_CLS_TCAM_X_L 0xf008
34603 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
34605 #define S_CTLCMDTYPE 31
34606 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
34607 #define F_CTLCMDTYPE V_CTLCMDTYPE(1U)
34609 #define S_CTLREQID 30
34610 #define V_CTLREQID(x) ((x) << S_CTLREQID)
34611 #define F_CTLREQID V_CTLREQID(1U)
34613 #define S_CTLTCAMSEL 25
34614 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
34615 #define F_CTLTCAMSEL V_CTLTCAMSEL(1U)
34617 #define S_CTLTCAMINDEX 17
34618 #define M_CTLTCAMINDEX 0xffU
34619 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
34620 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
34622 #define S_CTLXYBITSEL 16
34623 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
34624 #define F_CTLXYBITSEL V_CTLXYBITSEL(1U)
34626 #define S_DATAPORTNUM 12
34627 #define M_DATAPORTNUM 0xfU
34628 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
34629 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
34631 #define S_DATALKPTYPE 10
34632 #define M_DATALKPTYPE 0x3U
34633 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
34634 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
34636 #define S_DATADIPHIT 8
34637 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
34638 #define F_DATADIPHIT V_DATADIPHIT(1U)
34640 #define S_DATAVIDH2 7
34641 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
34642 #define F_DATAVIDH2 V_DATAVIDH2(1U)
34644 #define S_DATAVIDH1 0
34645 #define M_DATAVIDH1 0x7fU
34646 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
34647 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
34649 #define A_MPS_CLS_TCAM_X_H 0xf00c
34652 #define M_TCAMXH 0xffffU
34653 #define V_TCAMXH(x) ((x) << S_TCAMXH)
34654 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
34656 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
34657 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
34658 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
34659 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
34660 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
34661 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
34662 #define A_MPS_RX_CTL 0x11000
34664 #define S_FILT_VLAN_SEL 17
34665 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
34666 #define F_FILT_VLAN_SEL V_FILT_VLAN_SEL(1U)
34668 #define S_CBA_EN 16
34669 #define V_CBA_EN(x) ((x) << S_CBA_EN)
34670 #define F_CBA_EN V_CBA_EN(1U)
34672 #define S_BLK_SNDR 12
34673 #define M_BLK_SNDR 0xfU
34674 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
34675 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
34678 #define M_CMPRS 0xfU
34679 #define V_CMPRS(x) ((x) << S_CMPRS)
34680 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
34683 #define M_SNF 0xffU
34684 #define V_SNF(x) ((x) << S_SNF)
34685 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
34687 #define A_MPS_RX_PORT_MUX_CTL 0x11004
34689 #define S_CTL_P3 12
34690 #define M_CTL_P3 0xfU
34691 #define V_CTL_P3(x) ((x) << S_CTL_P3)
34692 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
34695 #define M_CTL_P2 0xfU
34696 #define V_CTL_P2(x) ((x) << S_CTL_P2)
34697 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
34700 #define M_CTL_P1 0xfU
34701 #define V_CTL_P1(x) ((x) << S_CTL_P1)
34702 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
34705 #define M_CTL_P0 0xfU
34706 #define V_CTL_P0(x) ((x) << S_CTL_P0)
34707 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
34709 #define A_MPS_RX_PG_FL 0x11008
34712 #define V_RST(x) ((x) << S_RST)
34713 #define F_RST V_RST(1U)
34716 #define M_CNT 0xffffU
34717 #define V_CNT(x) ((x) << S_CNT)
34718 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
34720 #define A_MPS_RX_FIFO_0_CTL 0x11008
34722 #define S_DEST_SELECT 0
34723 #define M_DEST_SELECT 0xfU
34724 #define V_DEST_SELECT(x) ((x) << S_DEST_SELECT)
34725 #define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT)
34727 #define A_MPS_RX_PKT_FL 0x1100c
34728 #define A_MPS_RX_FIFO_1_CTL 0x1100c
34729 #define A_MPS_RX_PG_RSV0 0x11010
34731 #define S_CLR_INTR 31
34732 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
34733 #define F_CLR_INTR V_CLR_INTR(1U)
34735 #define S_SET_INTR 30
34736 #define V_SET_INTR(x) ((x) << S_SET_INTR)
34737 #define F_SET_INTR V_SET_INTR(1U)
34740 #define M_USED 0x7ffU
34741 #define V_USED(x) ((x) << S_USED)
34742 #define G_USED(x) (((x) >> S_USED) & M_USED)
34745 #define M_ALLOC 0x7ffU
34746 #define V_ALLOC(x) ((x) << S_ALLOC)
34747 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
34749 #define S_T5_USED 16
34750 #define M_T5_USED 0xfffU
34751 #define V_T5_USED(x) ((x) << S_T5_USED)
34752 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
34754 #define S_T5_ALLOC 0
34755 #define M_T5_ALLOC 0xfffU
34756 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
34757 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
34759 #define A_MPS_RX_FIFO_2_CTL 0x11010
34760 #define A_MPS_RX_PG_RSV1 0x11014
34761 #define A_MPS_RX_FIFO_3_CTL 0x11014
34762 #define A_MPS_RX_PG_RSV2 0x11018
34763 #define A_MPS_RX_PG_RSV3 0x1101c
34764 #define A_MPS_RX_PG_RSV4 0x11020
34765 #define A_MPS_RX_PG_RSV5 0x11024
34766 #define A_MPS_RX_PG_RSV6 0x11028
34767 #define A_MPS_RX_PG_RSV7 0x1102c
34768 #define A_MPS_RX_PG_SHR_BG0 0x11030
34771 #define V_EN(x) ((x) << S_EN)
34772 #define F_EN V_EN(1U)
34775 #define V_SEL(x) ((x) << S_SEL)
34776 #define F_SEL V_SEL(1U)
34779 #define M_MAX 0x7ffU
34780 #define V_MAX(x) ((x) << S_MAX)
34781 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
34784 #define M_BORW 0x7ffU
34785 #define V_BORW(x) ((x) << S_BORW)
34786 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
34788 #define S_T5_MAX 16
34789 #define M_T5_MAX 0xfffU
34790 #define V_T5_MAX(x) ((x) << S_T5_MAX)
34791 #define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
34793 #define S_T5_BORW 0
34794 #define M_T5_BORW 0xfffU
34795 #define V_T5_BORW(x) ((x) << S_T5_BORW)
34796 #define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
34798 #define A_MPS_RX_PG_SHR_BG1 0x11034
34799 #define A_MPS_RX_PG_SHR_BG2 0x11038
34800 #define A_MPS_RX_PG_SHR_BG3 0x1103c
34801 #define A_MPS_RX_PG_SHR0 0x11040
34804 #define M_QUOTA 0x7ffU
34805 #define V_QUOTA(x) ((x) << S_QUOTA)
34806 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
34808 #define S_SHR_USED 0
34809 #define M_SHR_USED 0x7ffU
34810 #define V_SHR_USED(x) ((x) << S_SHR_USED)
34811 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
34813 #define S_T5_QUOTA 16
34814 #define M_T5_QUOTA 0xfffU
34815 #define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
34816 #define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
34818 #define S_T5_SHR_USED 0
34819 #define M_T5_SHR_USED 0xfffU
34820 #define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
34821 #define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
34823 #define A_MPS_RX_PG_SHR1 0x11044
34824 #define A_MPS_RX_PG_HYST_BG0 0x11048
34827 #define M_TH 0x7ffU
34828 #define V_TH(x) ((x) << S_TH)
34829 #define G_TH(x) (((x) >> S_TH) & M_TH)
34832 #define M_T5_TH 0xfffU
34833 #define V_T5_TH(x) ((x) << S_T5_TH)
34834 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
34837 #define M_T6_TH 0x7ffU
34838 #define V_T6_TH(x) ((x) << S_T6_TH)
34839 #define G_T6_TH(x) (((x) >> S_T6_TH) & M_T6_TH)
34841 #define A_MPS_RX_PG_HYST_BG1 0x1104c
34842 #define A_MPS_RX_PG_HYST_BG2 0x11050
34843 #define A_MPS_RX_PG_HYST_BG3 0x11054
34844 #define A_MPS_RX_OCH_CTL 0x11058
34846 #define S_DROP_WT 27
34847 #define M_DROP_WT 0x1fU
34848 #define V_DROP_WT(x) ((x) << S_DROP_WT)
34849 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
34851 #define S_TRUNC_WT 22
34852 #define M_TRUNC_WT 0x1fU
34853 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
34854 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
34856 #define S_OCH_DRAIN 13
34857 #define M_OCH_DRAIN 0x1fU
34858 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
34859 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
34861 #define S_OCH_DROP 8
34862 #define M_OCH_DROP 0x1fU
34863 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
34864 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
34867 #define M_STOP 0x1fU
34868 #define V_STOP(x) ((x) << S_STOP)
34869 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
34871 #define A_MPS_RX_LPBK_BP0 0x1105c
34874 #define M_THRESH 0x7ffU
34875 #define V_THRESH(x) ((x) << S_THRESH)
34876 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
34878 #define A_MPS_RX_LPBK_BP1 0x11060
34879 #define A_MPS_RX_LPBK_BP2 0x11064
34880 #define A_MPS_RX_LPBK_BP3 0x11068
34881 #define A_MPS_RX_PORT_GAP 0x1106c
34884 #define M_GAP 0xfffffU
34885 #define V_GAP(x) ((x) << S_GAP)
34886 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
34888 #define A_MPS_RX_CHMN_CNT 0x11070
34889 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
34892 #define V_FF(x) ((x) << S_FF)
34893 #define F_FF V_FF(1U)
34896 #define V_PGMO(x) ((x) << S_PGMO)
34897 #define F_PGMO V_PGMO(1U)
34900 #define V_PGME(x) ((x) << S_PGME)
34901 #define F_PGME V_PGME(1U)
34904 #define V_CHMN(x) ((x) << S_CHMN)
34905 #define F_CHMN V_CHMN(1U)
34908 #define V_RPLC(x) ((x) << S_RPLC)
34909 #define F_RPLC V_RPLC(1U)
34912 #define V_ATRB(x) ((x) << S_ATRB)
34913 #define F_ATRB V_ATRB(1U)
34916 #define V_PSMX(x) ((x) << S_PSMX)
34917 #define F_PSMX V_PSMX(1U)
34920 #define V_PGLL(x) ((x) << S_PGLL)
34921 #define F_PGLL V_PGLL(1U)
34924 #define V_PGFL(x) ((x) << S_PGFL)
34925 #define F_PGFL V_PGFL(1U)
34928 #define V_PKTQ(x) ((x) << S_PKTQ)
34929 #define F_PKTQ V_PKTQ(1U)
34932 #define V_PKFL(x) ((x) << S_PKFL)
34933 #define F_PKFL V_PKFL(1U)
34936 #define V_PPM3(x) ((x) << S_PPM3)
34937 #define F_PPM3 V_PPM3(1U)
34940 #define V_PPM2(x) ((x) << S_PPM2)
34941 #define F_PPM2 V_PPM2(1U)
34944 #define V_PPM1(x) ((x) << S_PPM1)
34945 #define F_PPM1 V_PPM1(1U)
34948 #define V_PPM0(x) ((x) << S_PPM0)
34949 #define F_PPM0 V_PPM0(1U)
34952 #define V_SPMX(x) ((x) << S_SPMX)
34953 #define F_SPMX V_SPMX(1U)
34956 #define V_CDL3(x) ((x) << S_CDL3)
34957 #define F_CDL3 V_CDL3(1U)
34960 #define V_CDL2(x) ((x) << S_CDL2)
34961 #define F_CDL2 V_CDL2(1U)
34964 #define V_CDL1(x) ((x) << S_CDL1)
34965 #define F_CDL1 V_CDL1(1U)
34968 #define V_CDL0(x) ((x) << S_CDL0)
34969 #define F_CDL0 V_CDL0(1U)
34972 #define V_CDM3(x) ((x) << S_CDM3)
34973 #define F_CDM3 V_CDM3(1U)
34976 #define V_CDM2(x) ((x) << S_CDM2)
34977 #define F_CDM2 V_CDM2(1U)
34980 #define V_CDM1(x) ((x) << S_CDM1)
34981 #define F_CDM1 V_CDM1(1U)
34984 #define V_CDM0(x) ((x) << S_CDM0)
34985 #define F_CDM0 V_CDM0(1U)
34987 #define S_T6_INT_ERR_INT 24
34988 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
34989 #define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U)
34991 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
34993 #define S_T6_INT_ERR_INT 24
34994 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
34995 #define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U)
34997 #define A_MPS_RX_PERR_ENABLE 0x1107c
34999 #define S_T6_INT_ERR_INT 24
35000 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
35001 #define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U)
35003 #define A_MPS_RX_PERR_INJECT 0x11080
35004 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
35006 #define S_INT_ERR_INT 8
35007 #define M_INT_ERR_INT 0x1fU
35008 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
35009 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
35011 #define S_PG_TH_INT7 7
35012 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
35013 #define F_PG_TH_INT7 V_PG_TH_INT7(1U)
35015 #define S_PG_TH_INT6 6
35016 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
35017 #define F_PG_TH_INT6 V_PG_TH_INT6(1U)
35019 #define S_PG_TH_INT5 5
35020 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
35021 #define F_PG_TH_INT5 V_PG_TH_INT5(1U)
35023 #define S_PG_TH_INT4 4
35024 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
35025 #define F_PG_TH_INT4 V_PG_TH_INT4(1U)
35027 #define S_PG_TH_INT3 3
35028 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
35029 #define F_PG_TH_INT3 V_PG_TH_INT3(1U)
35031 #define S_PG_TH_INT2 2
35032 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
35033 #define F_PG_TH_INT2 V_PG_TH_INT2(1U)
35035 #define S_PG_TH_INT1 1
35036 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
35037 #define F_PG_TH_INT1 V_PG_TH_INT1(1U)
35039 #define S_PG_TH_INT0 0
35040 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
35041 #define F_PG_TH_INT0 V_PG_TH_INT0(1U)
35043 #define S_MTU_ERR_INT3 19
35044 #define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
35045 #define F_MTU_ERR_INT3 V_MTU_ERR_INT3(1U)
35047 #define S_MTU_ERR_INT2 18
35048 #define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
35049 #define F_MTU_ERR_INT2 V_MTU_ERR_INT2(1U)
35051 #define S_MTU_ERR_INT1 17
35052 #define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
35053 #define F_MTU_ERR_INT1 V_MTU_ERR_INT1(1U)
35055 #define S_MTU_ERR_INT0 16
35056 #define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
35057 #define F_MTU_ERR_INT0 V_MTU_ERR_INT0(1U)
35059 #define S_SE_CNT_ERR_INT 15
35060 #define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
35061 #define F_SE_CNT_ERR_INT V_SE_CNT_ERR_INT(1U)
35063 #define S_FRM_ERR_INT 14
35064 #define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
35065 #define F_FRM_ERR_INT V_FRM_ERR_INT(1U)
35067 #define S_LEN_ERR_INT 13
35068 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
35069 #define F_LEN_ERR_INT V_LEN_ERR_INT(1U)
35071 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
35072 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
35074 #define S_TH_HIGH 16
35075 #define M_TH_HIGH 0xffffU
35076 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
35077 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
35080 #define M_TH_LOW 0xffffU
35081 #define V_TH_LOW(x) ((x) << S_TH_LOW)
35082 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
35084 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
35085 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
35086 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
35087 #define A_MPS_RX_REPL_CTL 0x11098
35089 #define S_INDEX_SEL 0
35090 #define V_INDEX_SEL(x) ((x) << S_INDEX_SEL)
35091 #define F_INDEX_SEL V_INDEX_SEL(1U)
35093 #define A_MPS_RX_PPP_ATRB 0x1109c
35096 #define M_ETYPE 0xffffU
35097 #define V_ETYPE(x) ((x) << S_ETYPE)
35098 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
35101 #define M_OPCODE 0xffffU
35102 #define V_OPCODE(x) ((x) << S_OPCODE)
35103 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
35105 #define A_MPS_RX_QFC0_ATRB 0x110a0
35108 #define M_DA 0xffffU
35109 #define V_DA(x) ((x) << S_DA)
35110 #define G_DA(x) (((x) >> S_DA) & M_DA)
35112 #define A_MPS_RX_QFC1_ATRB 0x110a4
35113 #define A_MPS_RX_PT_ARB0 0x110a8
35115 #define S_LPBK_WT 16
35116 #define M_LPBK_WT 0x3fffU
35117 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
35118 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
35121 #define M_MAC_WT 0x3fffU
35122 #define V_MAC_WT(x) ((x) << S_MAC_WT)
35123 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
35125 #define A_MPS_RX_PT_ARB1 0x110ac
35126 #define A_MPS_RX_PT_ARB2 0x110b0
35127 #define A_MPS_RX_PT_ARB3 0x110b4
35128 #define A_T6_MPS_PF_OUT_EN 0x110b4
35129 #define A_MPS_RX_PT_ARB4 0x110b8
35130 #define A_T6_MPS_BMC_MTU 0x110b8
35131 #define A_MPS_PF_OUT_EN 0x110bc
35134 #define M_OUTEN 0xffU
35135 #define V_OUTEN(x) ((x) << S_OUTEN)
35136 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
35138 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
35139 #define A_MPS_BMC_MTU 0x110c0
35142 #define M_MTU 0x3fffU
35143 #define V_MTU(x) ((x) << S_MTU)
35144 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
35146 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
35147 #define A_MPS_BMC_PKT_CNT 0x110c4
35148 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
35150 #define S_T6_PFVF 0
35151 #define M_T6_PFVF 0x1ffU
35152 #define V_T6_PFVF(x) ((x) << S_T6_PFVF)
35153 #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
35155 #define A_MPS_BMC_BYTE_CNT 0x110c8
35156 #define A_T6_MPS_PFVF_ATRB 0x110c8
35158 #define S_FULL_FRAME_MODE 14
35159 #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
35160 #define F_FULL_FRAME_MODE V_FULL_FRAME_MODE(1U)
35162 #define A_MPS_PFVF_ATRB_CTL 0x110cc
35164 #define S_RD_WRN 31
35165 #define V_RD_WRN(x) ((x) << S_RD_WRN)
35166 #define F_RD_WRN V_RD_WRN(1U)
35169 #define M_PFVF 0xffU
35170 #define V_PFVF(x) ((x) << S_PFVF)
35171 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
35173 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
35174 #define A_MPS_PFVF_ATRB 0x110d0
35176 #define S_ATTR_PF 28
35177 #define M_ATTR_PF 0x7U
35178 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
35179 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
35182 #define V_OFF(x) ((x) << S_OFF)
35183 #define F_OFF V_OFF(1U)
35185 #define S_NV_DROP 17
35186 #define V_NV_DROP(x) ((x) << S_NV_DROP)
35187 #define F_NV_DROP V_NV_DROP(1U)
35189 #define S_ATTR_MODE 16
35190 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
35191 #define F_ATTR_MODE V_ATTR_MODE(1U)
35193 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
35194 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
35196 #define S_VLAN_EN 16
35197 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
35198 #define F_VLAN_EN V_VLAN_EN(1U)
35200 #define S_VLAN_ID 0
35201 #define M_VLAN_ID 0xfffU
35202 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
35203 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
35205 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
35206 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
35207 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
35208 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
35209 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
35210 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
35211 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
35212 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
35213 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
35214 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
35215 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
35216 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
35217 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
35218 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
35219 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
35220 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
35221 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
35222 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
35223 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
35224 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
35225 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
35226 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
35227 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
35228 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
35229 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
35230 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
35231 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
35232 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
35233 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
35234 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
35235 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
35236 #define A_MPS_RPLC_MAP_CTL 0x11114
35238 #define S_RPLC_MAP_ADDR 0
35239 #define M_RPLC_MAP_ADDR 0x3ffU
35240 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
35241 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
35243 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
35244 #define A_MPS_PF_RPLCT_MAP 0x11118
35247 #define M_PF_EN 0xffU
35248 #define V_PF_EN(x) ((x) << S_PF_EN)
35249 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
35251 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
35252 #define A_MPS_VF_RPLCT_MAP0 0x1111c
35253 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
35254 #define A_MPS_VF_RPLCT_MAP1 0x11120
35255 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
35256 #define A_MPS_VF_RPLCT_MAP2 0x11124
35257 #define A_MPS_VF_RPLCT_MAP3 0x11128
35258 #define A_MPS_MEM_DBG_CTL 0x1112c
35261 #define V_PKD(x) ((x) << S_PKD)
35262 #define F_PKD V_PKD(1U)
35265 #define V_PGD(x) ((x) << S_PGD)
35266 #define F_PGD V_PGD(1U)
35268 #define A_MPS_PKD_MEM_DATA0 0x11130
35269 #define A_MPS_PKD_MEM_DATA1 0x11134
35270 #define A_MPS_PKD_MEM_DATA2 0x11138
35271 #define A_MPS_PGD_MEM_DATA 0x1113c
35272 #define A_MPS_RX_SE_CNT_ERR 0x11140
35274 #define S_RX_SE_ERRMAP 0
35275 #define M_RX_SE_ERRMAP 0xfffffU
35276 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
35277 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
35279 #define A_MPS_RX_SE_CNT_CLR 0x11144
35280 #define A_MPS_RX_SE_CNT_IN0 0x11148
35282 #define S_SOP_CNT_PM 24
35283 #define M_SOP_CNT_PM 0xffU
35284 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
35285 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
35287 #define S_EOP_CNT_PM 16
35288 #define M_EOP_CNT_PM 0xffU
35289 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
35290 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
35292 #define S_SOP_CNT_IN 8
35293 #define M_SOP_CNT_IN 0xffU
35294 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
35295 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
35297 #define S_EOP_CNT_IN 0
35298 #define M_EOP_CNT_IN 0xffU
35299 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
35300 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
35302 #define A_MPS_RX_SE_CNT_IN1 0x1114c
35303 #define A_MPS_RX_SE_CNT_IN2 0x11150
35304 #define A_MPS_RX_SE_CNT_IN3 0x11154
35305 #define A_MPS_RX_SE_CNT_IN4 0x11158
35306 #define A_MPS_RX_SE_CNT_IN5 0x1115c
35307 #define A_MPS_RX_SE_CNT_IN6 0x11160
35308 #define A_MPS_RX_SE_CNT_IN7 0x11164
35309 #define A_MPS_RX_SE_CNT_OUT01 0x11168
35311 #define S_SOP_CNT_1 24
35312 #define M_SOP_CNT_1 0xffU
35313 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
35314 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
35316 #define S_EOP_CNT_1 16
35317 #define M_EOP_CNT_1 0xffU
35318 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
35319 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
35321 #define S_SOP_CNT_0 8
35322 #define M_SOP_CNT_0 0xffU
35323 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
35324 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
35326 #define S_EOP_CNT_0 0
35327 #define M_EOP_CNT_0 0xffU
35328 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
35329 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
35331 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
35333 #define S_SOP_CNT_3 24
35334 #define M_SOP_CNT_3 0xffU
35335 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
35336 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
35338 #define S_EOP_CNT_3 16
35339 #define M_EOP_CNT_3 0xffU
35340 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
35341 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
35343 #define S_SOP_CNT_2 8
35344 #define M_SOP_CNT_2 0xffU
35345 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
35346 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
35348 #define S_EOP_CNT_2 0
35349 #define M_EOP_CNT_2 0xffU
35350 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
35351 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
35353 #define A_MPS_RX_SPI_ERR 0x11170
35355 #define S_LENERR 21
35356 #define M_LENERR 0xfU
35357 #define V_LENERR(x) ((x) << S_LENERR)
35358 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
35361 #define M_SPIERR 0x1fffffU
35362 #define V_SPIERR(x) ((x) << S_SPIERR)
35363 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
35365 #define A_MPS_RX_IN_BUS_STATE 0x11174
35368 #define M_ST3 0xffU
35369 #define V_ST3(x) ((x) << S_ST3)
35370 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
35373 #define M_ST2 0xffU
35374 #define V_ST2(x) ((x) << S_ST2)
35375 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
35378 #define M_ST1 0xffU
35379 #define V_ST1(x) ((x) << S_ST1)
35380 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
35383 #define M_ST0 0xffU
35384 #define V_ST0(x) ((x) << S_ST0)
35385 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
35387 #define A_MPS_RX_OUT_BUS_STATE 0x11178
35389 #define S_ST_NCSI 23
35390 #define M_ST_NCSI 0x1ffU
35391 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
35392 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
35395 #define M_ST_TP 0x7fffffU
35396 #define V_ST_TP(x) ((x) << S_ST_TP)
35397 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
35399 #define A_MPS_RX_DBG_CTL 0x1117c
35401 #define S_OUT_DBG_CHNL 8
35402 #define M_OUT_DBG_CHNL 0x7U
35403 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
35404 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
35406 #define S_DBG_PKD_QSEL 7
35407 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
35408 #define F_DBG_PKD_QSEL V_DBG_PKD_QSEL(1U)
35410 #define S_DBG_CDS_INV 6
35411 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
35412 #define F_DBG_CDS_INV V_DBG_CDS_INV(1U)
35414 #define S_IN_DBG_PORT 3
35415 #define M_IN_DBG_PORT 0x7U
35416 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
35417 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
35419 #define S_IN_DBG_CHNL 0
35420 #define M_IN_DBG_CHNL 0x7U
35421 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
35422 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
35424 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
35426 #define S_LPBK_CNT0 16
35427 #define M_LPBK_CNT0 0xffffU
35428 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
35429 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
35431 #define S_MAC_CNT0 0
35432 #define M_MAC_CNT0 0xffffU
35433 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
35434 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
35436 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
35438 #define S_LPBK_CNT1 16
35439 #define M_LPBK_CNT1 0xffffU
35440 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
35441 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
35443 #define S_MAC_CNT1 0
35444 #define M_MAC_CNT1 0xffffU
35445 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
35446 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
35448 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
35450 #define S_LPBK_CNT2 16
35451 #define M_LPBK_CNT2 0xffffU
35452 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
35453 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
35455 #define S_MAC_CNT2 0
35456 #define M_MAC_CNT2 0xffffU
35457 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
35458 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
35460 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
35462 #define S_LPBK_CNT3 16
35463 #define M_LPBK_CNT3 0xffffU
35464 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
35465 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
35467 #define S_MAC_CNT3 0
35468 #define M_MAC_CNT3 0xffffU
35469 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
35470 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
35472 #define A_MPS_RX_SPARE 0x11190
35473 #define A_MPS_RX_PTP_ETYPE 0x11194
35475 #define S_PETYPE2 16
35476 #define M_PETYPE2 0xffffU
35477 #define V_PETYPE2(x) ((x) << S_PETYPE2)
35478 #define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
35480 #define S_PETYPE1 0
35481 #define M_PETYPE1 0xffffU
35482 #define V_PETYPE1(x) ((x) << S_PETYPE1)
35483 #define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
35485 #define A_MPS_RX_PTP_TCP 0x11198
35487 #define S_PTCPORT2 16
35488 #define M_PTCPORT2 0xffffU
35489 #define V_PTCPORT2(x) ((x) << S_PTCPORT2)
35490 #define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
35492 #define S_PTCPORT1 0
35493 #define M_PTCPORT1 0xffffU
35494 #define V_PTCPORT1(x) ((x) << S_PTCPORT1)
35495 #define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
35497 #define A_MPS_RX_PTP_UDP 0x1119c
35499 #define S_PUDPORT2 16
35500 #define M_PUDPORT2 0xffffU
35501 #define V_PUDPORT2(x) ((x) << S_PUDPORT2)
35502 #define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
35504 #define S_PUDPORT1 0
35505 #define M_PUDPORT1 0xffffU
35506 #define V_PUDPORT1(x) ((x) << S_PUDPORT1)
35507 #define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
35509 #define A_MPS_RX_PTP_CTL 0x111a0
35511 #define S_MIN_PTP_SPACE 24
35512 #define M_MIN_PTP_SPACE 0x7fU
35513 #define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
35514 #define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
35516 #define S_PUDP2EN 20
35517 #define M_PUDP2EN 0xfU
35518 #define V_PUDP2EN(x) ((x) << S_PUDP2EN)
35519 #define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
35521 #define S_PUDP1EN 16
35522 #define M_PUDP1EN 0xfU
35523 #define V_PUDP1EN(x) ((x) << S_PUDP1EN)
35524 #define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
35526 #define S_PTCP2EN 12
35527 #define M_PTCP2EN 0xfU
35528 #define V_PTCP2EN(x) ((x) << S_PTCP2EN)
35529 #define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
35531 #define S_PTCP1EN 8
35532 #define M_PTCP1EN 0xfU
35533 #define V_PTCP1EN(x) ((x) << S_PTCP1EN)
35534 #define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
35536 #define S_PETYPE2EN 4
35537 #define M_PETYPE2EN 0xfU
35538 #define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
35539 #define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
35541 #define S_PETYPE1EN 0
35542 #define M_PETYPE1EN 0xfU
35543 #define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
35544 #define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
35546 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
35547 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
35548 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
35549 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
35550 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
35551 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
35552 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
35553 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
35554 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
35555 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
35556 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
35557 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
35558 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
35559 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
35560 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
35561 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
35562 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
35563 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
35564 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
35565 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
35566 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
35567 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
35568 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
35569 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
35570 #define A_MPS_RX_CGEN 0x11204
35572 #define S_MPS_RX_CGEN_NCSI 12
35573 #define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
35574 #define F_MPS_RX_CGEN_NCSI V_MPS_RX_CGEN_NCSI(1U)
35576 #define S_MPS_RX_CGEN_OUT 8
35577 #define M_MPS_RX_CGEN_OUT 0xfU
35578 #define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
35579 #define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
35581 #define S_MPS_RX_CGEN_LPBK_IN 4
35582 #define M_MPS_RX_CGEN_LPBK_IN 0xfU
35583 #define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
35584 #define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
35586 #define S_MPS_RX_CGEN_MAC_IN 0
35587 #define M_MPS_RX_CGEN_MAC_IN 0xfU
35588 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
35589 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
35591 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
35593 #define S_MAC_USED 16
35594 #define M_MAC_USED 0x7ffU
35595 #define V_MAC_USED(x) ((x) << S_MAC_USED)
35596 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
35598 #define S_MAC_ALLOC 0
35599 #define M_MAC_ALLOC 0x7ffU
35600 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
35601 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
35603 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
35604 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
35605 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
35606 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
35608 #define S_LPBK_USED 16
35609 #define M_LPBK_USED 0x7ffU
35610 #define V_LPBK_USED(x) ((x) << S_LPBK_USED)
35611 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
35613 #define S_LPBK_ALLOC 0
35614 #define M_LPBK_ALLOC 0x7ffU
35615 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
35616 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
35618 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
35619 #define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
35621 #define S_CONG_EN 31
35622 #define V_CONG_EN(x) ((x) << S_CONG_EN)
35623 #define F_CONG_EN V_CONG_EN(1U)
35625 #define S_CONG_TH 0
35626 #define M_CONG_TH 0xfffffU
35627 #define V_CONG_TH(x) ((x) << S_CONG_TH)
35628 #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
35630 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
35631 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
35632 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
35633 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
35635 #define S_NVGRE_EN 9
35636 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
35637 #define F_NVGRE_EN V_NVGRE_EN(1U)
35640 #define V_GRE_EN(x) ((x) << S_GRE_EN)
35641 #define F_GRE_EN V_GRE_EN(1U)
35644 #define M_GRE 0xffU
35645 #define V_GRE(x) ((x) << S_GRE)
35646 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
35648 #define A_MPS_RX_VXLAN_TYPE 0x11234
35650 #define S_VXLAN_EN 16
35651 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
35652 #define F_VXLAN_EN V_VXLAN_EN(1U)
35655 #define M_VXLAN 0xffffU
35656 #define V_VXLAN(x) ((x) << S_VXLAN)
35657 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
35659 #define A_MPS_RX_GENEVE_TYPE 0x11238
35661 #define S_GENEVE_EN 16
35662 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
35663 #define F_GENEVE_EN V_GENEVE_EN(1U)
35666 #define M_GENEVE 0xffffU
35667 #define V_GENEVE(x) ((x) << S_GENEVE)
35668 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
35670 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
35672 #define S_T6_IVLAN_EN 16
35673 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
35674 #define F_T6_IVLAN_EN V_T6_IVLAN_EN(1U)
35676 #define A_MPS_RX_ENCAP_NVGRE 0x11240
35678 #define S_ETYPE_EN 16
35679 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
35680 #define F_ETYPE_EN V_ETYPE_EN(1U)
35682 #define S_T6_ETYPE 0
35683 #define M_T6_ETYPE 0xffffU
35684 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
35685 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
35687 #define A_MPS_RX_ENCAP_GENEVE 0x11244
35689 #define S_T6_ETYPE 0
35690 #define M_T6_ETYPE 0xffffU
35691 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
35692 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
35694 #define A_MPS_RX_TCP 0x11248
35696 #define S_PROT_TYPE_EN 8
35697 #define V_PROT_TYPE_EN(x) ((x) << S_PROT_TYPE_EN)
35698 #define F_PROT_TYPE_EN V_PROT_TYPE_EN(1U)
35700 #define S_PROT_TYPE 0
35701 #define M_PROT_TYPE 0xffU
35702 #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
35703 #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
35705 #define A_MPS_RX_UDP 0x1124c
35706 #define A_MPS_RX_PAUSE 0x11250
35707 #define A_MPS_RX_LENGTH 0x11254
35709 #define S_SAP_VALUE 16
35710 #define M_SAP_VALUE 0xffffU
35711 #define V_SAP_VALUE(x) ((x) << S_SAP_VALUE)
35712 #define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE)
35714 #define S_LENGTH_ETYPE 0
35715 #define M_LENGTH_ETYPE 0xffffU
35716 #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
35717 #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
35719 #define A_MPS_RX_CTL_ORG 0x11258
35721 #define S_CTL_VALUE 24
35722 #define M_CTL_VALUE 0xffU
35723 #define V_CTL_VALUE(x) ((x) << S_CTL_VALUE)
35724 #define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE)
35726 #define S_ORG_VALUE 0
35727 #define M_ORG_VALUE 0xffffffU
35728 #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
35729 #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
35731 #define A_MPS_RX_IPV4 0x1125c
35733 #define S_ETYPE_IPV4 0
35734 #define M_ETYPE_IPV4 0xffffU
35735 #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
35736 #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
35738 #define A_MPS_RX_IPV6 0x11260
35740 #define S_ETYPE_IPV6 0
35741 #define M_ETYPE_IPV6 0xffffU
35742 #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
35743 #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
35745 #define A_MPS_RX_TTL 0x11264
35747 #define S_TTL_IPV4 10
35748 #define M_TTL_IPV4 0xffU
35749 #define V_TTL_IPV4(x) ((x) << S_TTL_IPV4)
35750 #define G_TTL_IPV4(x) (((x) >> S_TTL_IPV4) & M_TTL_IPV4)
35752 #define S_TTL_IPV6 2
35753 #define M_TTL_IPV6 0xffU
35754 #define V_TTL_IPV6(x) ((x) << S_TTL_IPV6)
35755 #define G_TTL_IPV6(x) (((x) >> S_TTL_IPV6) & M_TTL_IPV6)
35757 #define S_TTL_CHK_EN_IPV4 1
35758 #define V_TTL_CHK_EN_IPV4(x) ((x) << S_TTL_CHK_EN_IPV4)
35759 #define F_TTL_CHK_EN_IPV4 V_TTL_CHK_EN_IPV4(1U)
35761 #define S_TTL_CHK_EN_IPV6 0
35762 #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
35763 #define F_TTL_CHK_EN_IPV6 V_TTL_CHK_EN_IPV6(1U)
35765 #define A_MPS_RX_DEFAULT_VNI 0x11268
35768 #define M_VNI 0xffffffU
35769 #define V_VNI(x) ((x) << S_VNI)
35770 #define G_VNI(x) (((x) >> S_VNI) & M_VNI)
35772 #define A_MPS_RX_PRS_CTL 0x1126c
35774 #define S_CTL_CHK_EN 28
35775 #define V_CTL_CHK_EN(x) ((x) << S_CTL_CHK_EN)
35776 #define F_CTL_CHK_EN V_CTL_CHK_EN(1U)
35778 #define S_ORG_CHK_EN 27
35779 #define V_ORG_CHK_EN(x) ((x) << S_ORG_CHK_EN)
35780 #define F_ORG_CHK_EN V_ORG_CHK_EN(1U)
35782 #define S_SAP_CHK_EN 26
35783 #define V_SAP_CHK_EN(x) ((x) << S_SAP_CHK_EN)
35784 #define F_SAP_CHK_EN V_SAP_CHK_EN(1U)
35786 #define S_VXLAN_FLAG_CHK_EN 25
35787 #define V_VXLAN_FLAG_CHK_EN(x) ((x) << S_VXLAN_FLAG_CHK_EN)
35788 #define F_VXLAN_FLAG_CHK_EN V_VXLAN_FLAG_CHK_EN(1U)
35790 #define S_VXLAN_FLAG_MASK 17
35791 #define M_VXLAN_FLAG_MASK 0xffU
35792 #define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK)
35793 #define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK)
35795 #define S_VXLAN_FLAG 9
35796 #define M_VXLAN_FLAG 0xffU
35797 #define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG)
35798 #define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG)
35800 #define S_GRE_VER_CHK_EN 8
35801 #define V_GRE_VER_CHK_EN(x) ((x) << S_GRE_VER_CHK_EN)
35802 #define F_GRE_VER_CHK_EN V_GRE_VER_CHK_EN(1U)
35804 #define S_GRE_VER 5
35805 #define M_GRE_VER 0x7U
35806 #define V_GRE_VER(x) ((x) << S_GRE_VER)
35807 #define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER)
35809 #define S_GENEVE_VER_CHK_EN 4
35810 #define V_GENEVE_VER_CHK_EN(x) ((x) << S_GENEVE_VER_CHK_EN)
35811 #define F_GENEVE_VER_CHK_EN V_GENEVE_VER_CHK_EN(1U)
35813 #define S_GENEVE_VER 2
35814 #define M_GENEVE_VER 0x3U
35815 #define V_GENEVE_VER(x) ((x) << S_GENEVE_VER)
35816 #define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER)
35819 #define V_DIP_EN(x) ((x) << S_DIP_EN)
35820 #define F_DIP_EN V_DIP_EN(1U)
35822 #define A_MPS_RX_PRS_CTL_2 0x11270
35824 #define S_EN_UDP_CSUM_CHK 4
35825 #define V_EN_UDP_CSUM_CHK(x) ((x) << S_EN_UDP_CSUM_CHK)
35826 #define F_EN_UDP_CSUM_CHK V_EN_UDP_CSUM_CHK(1U)
35828 #define S_EN_UDP_LEN_CHK 3
35829 #define V_EN_UDP_LEN_CHK(x) ((x) << S_EN_UDP_LEN_CHK)
35830 #define F_EN_UDP_LEN_CHK V_EN_UDP_LEN_CHK(1U)
35832 #define S_EN_IP_CSUM_CHK 2
35833 #define V_EN_IP_CSUM_CHK(x) ((x) << S_EN_IP_CSUM_CHK)
35834 #define F_EN_IP_CSUM_CHK V_EN_IP_CSUM_CHK(1U)
35836 #define S_EN_IP_PAYLOAD_LEN_CHK 1
35837 #define V_EN_IP_PAYLOAD_LEN_CHK(x) ((x) << S_EN_IP_PAYLOAD_LEN_CHK)
35838 #define F_EN_IP_PAYLOAD_LEN_CHK V_EN_IP_PAYLOAD_LEN_CHK(1U)
35840 #define S_T6_IPV6_UDP_CSUM_COMPAT 0
35841 #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
35842 #define F_T6_IPV6_UDP_CSUM_COMPAT V_T6_IPV6_UDP_CSUM_COMPAT(1U)
35844 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
35845 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
35848 #define M_T6_LEN 0x1ffU
35849 #define V_T6_LEN(x) ((x) << S_T6_LEN)
35850 #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
35852 #define A_MPS_RX_PAUSE_DA_H 0x1127c
35853 #define A_MPS_RX_PAUSE_DA_L 0x11280
35854 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
35855 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
35856 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
35857 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
35858 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
35859 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
35860 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
35861 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
35862 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
35863 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
35864 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
35865 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
35866 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
35867 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
35868 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
35869 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
35870 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
35871 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
35872 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
35873 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
35874 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
35875 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
35876 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
35877 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
35878 #define A_MPS_VF_RPLCT_MAP4 0x11300
35879 #define A_MPS_VF_RPLCT_MAP5 0x11304
35880 #define A_MPS_VF_RPLCT_MAP6 0x11308
35881 #define A_MPS_VF_RPLCT_MAP7 0x1130c
35882 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
35883 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
35884 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
35885 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
35886 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
35887 #define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
35888 #define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
35889 #define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
35890 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
35891 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
35892 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
35894 /* registers for module CPL_SWITCH */
35895 #define CPL_SWITCH_BASE_ADDR 0x19040
35897 #define A_CPL_SWITCH_CNTRL 0x19040
35899 #define S_CPL_PKT_TID 8
35900 #define M_CPL_PKT_TID 0xffffffU
35901 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
35902 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
35904 #define S_CIM_TRUNCATE_ENABLE 5
35905 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
35906 #define F_CIM_TRUNCATE_ENABLE V_CIM_TRUNCATE_ENABLE(1U)
35908 #define S_CIM_TO_UP_FULL_SIZE 4
35909 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
35910 #define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U)
35912 #define S_CPU_NO_ENABLE 3
35913 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
35914 #define F_CPU_NO_ENABLE V_CPU_NO_ENABLE(1U)
35916 #define S_SWITCH_TABLE_ENABLE 2
35917 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
35918 #define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U)
35920 #define S_SGE_ENABLE 1
35921 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
35922 #define F_SGE_ENABLE V_SGE_ENABLE(1U)
35924 #define S_CIM_ENABLE 0
35925 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
35926 #define F_CIM_ENABLE V_CIM_ENABLE(1U)
35928 #define S_CIM_SPLIT_ENABLE 6
35929 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
35930 #define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U)
35932 #define A_CPL_SWITCH_TBL_IDX 0x19044
35934 #define S_SWITCH_TBL_IDX 0
35935 #define M_SWITCH_TBL_IDX 0xfU
35936 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
35937 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
35939 #define A_CPL_SWITCH_TBL_DATA 0x19048
35940 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
35942 #define S_ZERO_CMD_CH1 8
35943 #define M_ZERO_CMD_CH1 0xffU
35944 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
35945 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
35947 #define S_ZERO_CMD_CH0 0
35948 #define M_ZERO_CMD_CH0 0xffU
35949 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
35950 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
35952 #define A_CPL_INTR_ENABLE 0x19050
35954 #define S_CIM_OP_MAP_PERR 5
35955 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
35956 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U)
35958 #define S_CIM_OVFL_ERROR 4
35959 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
35960 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
35962 #define S_TP_FRAMING_ERROR 3
35963 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
35964 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
35966 #define S_SGE_FRAMING_ERROR 2
35967 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
35968 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
35970 #define S_CIM_FRAMING_ERROR 1
35971 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
35972 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
35974 #define S_ZERO_SWITCH_ERROR 0
35975 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
35976 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
35978 #define S_PERR_CPL_128TO128_1 7
35979 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
35980 #define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U)
35982 #define S_PERR_CPL_128TO128_0 6
35983 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
35984 #define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U)
35986 #define A_CPL_INTR_CAUSE 0x19054
35987 #define A_CPL_MAP_TBL_IDX 0x19058
35989 #define S_MAP_TBL_IDX 0
35990 #define M_MAP_TBL_IDX 0xffU
35991 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
35992 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
35994 #define S_CIM_SPLIT_OPCODE_PROGRAM 8
35995 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
35996 #define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U)
35998 #define A_CPL_MAP_TBL_DATA 0x1905c
36000 #define S_MAP_TBL_DATA 0
36001 #define M_MAP_TBL_DATA 0xffU
36002 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
36003 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
36005 /* registers for module SMB */
36006 #define SMB_BASE_ADDR 0x19060
36008 #define A_SMB_GLOBAL_TIME_CFG 0x19060
36010 #define S_MACROCNTCFG 8
36011 #define M_MACROCNTCFG 0x1fU
36012 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
36013 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
36015 #define S_MICROCNTCFG 0
36016 #define M_MICROCNTCFG 0xffU
36017 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
36018 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
36020 #define A_SMB_MST_TIMEOUT_CFG 0x19064
36022 #define S_MSTTIMEOUTCFG 0
36023 #define M_MSTTIMEOUTCFG 0xffffffU
36024 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
36025 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
36027 #define A_SMB_MST_CTL_CFG 0x19068
36029 #define S_MSTFIFODBG 31
36030 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
36031 #define F_MSTFIFODBG V_MSTFIFODBG(1U)
36033 #define S_MSTFIFODBGCLR 30
36034 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
36035 #define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U)
36037 #define S_MSTRXBYTECFG 12
36038 #define M_MSTRXBYTECFG 0x3fU
36039 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
36040 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
36042 #define S_MSTTXBYTECFG 6
36043 #define M_MSTTXBYTECFG 0x3fU
36044 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
36045 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
36047 #define S_MSTRESET 1
36048 #define V_MSTRESET(x) ((x) << S_MSTRESET)
36049 #define F_MSTRESET V_MSTRESET(1U)
36051 #define S_MSTCTLEN 0
36052 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
36053 #define F_MSTCTLEN V_MSTCTLEN(1U)
36055 #define A_SMB_MST_CTL_STS 0x1906c
36057 #define S_MSTRXBYTECNT 12
36058 #define M_MSTRXBYTECNT 0x3fU
36059 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
36060 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
36062 #define S_MSTTXBYTECNT 6
36063 #define M_MSTTXBYTECNT 0x3fU
36064 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
36065 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
36067 #define S_MSTBUSYSTS 0
36068 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
36069 #define F_MSTBUSYSTS V_MSTBUSYSTS(1U)
36071 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
36072 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
36073 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
36075 #define S_SLVTIMEOUTCFG 0
36076 #define M_SLVTIMEOUTCFG 0xffffffU
36077 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
36078 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
36080 #define A_SMB_SLV_CTL_CFG 0x1907c
36082 #define S_SLVFIFODBG 31
36083 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
36084 #define F_SLVFIFODBG V_SLVFIFODBG(1U)
36086 #define S_SLVFIFODBGCLR 30
36087 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
36088 #define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U)
36090 #define S_SLVCRCOUTBITINV 21
36091 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
36092 #define F_SLVCRCOUTBITINV V_SLVCRCOUTBITINV(1U)
36094 #define S_SLVCRCOUTBITREV 20
36095 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
36096 #define F_SLVCRCOUTBITREV V_SLVCRCOUTBITREV(1U)
36098 #define S_SLVCRCINBITREV 19
36099 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
36100 #define F_SLVCRCINBITREV V_SLVCRCINBITREV(1U)
36102 #define S_SLVCRCPRESET 11
36103 #define M_SLVCRCPRESET 0xffU
36104 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
36105 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
36107 #define S_SLVADDRCFG 4
36108 #define M_SLVADDRCFG 0x7fU
36109 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
36110 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
36112 #define S_SLVALRTSET 2
36113 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
36114 #define F_SLVALRTSET V_SLVALRTSET(1U)
36116 #define S_SLVRESET 1
36117 #define V_SLVRESET(x) ((x) << S_SLVRESET)
36118 #define F_SLVRESET V_SLVRESET(1U)
36120 #define S_SLVCTLEN 0
36121 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
36122 #define F_SLVCTLEN V_SLVCTLEN(1U)
36124 #define A_SMB_SLV_CTL_STS 0x19080
36126 #define S_SLVFIFOTXCNT 12
36127 #define M_SLVFIFOTXCNT 0x3fU
36128 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
36129 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
36131 #define S_SLVFIFOCNT 6
36132 #define M_SLVFIFOCNT 0x3fU
36133 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
36134 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
36136 #define S_SLVALRTSTS 2
36137 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
36138 #define F_SLVALRTSTS V_SLVALRTSTS(1U)
36140 #define S_SLVBUSYSTS 0
36141 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
36142 #define F_SLVBUSYSTS V_SLVBUSYSTS(1U)
36144 #define A_SMB_SLV_FIFO_RDWR 0x19084
36145 #define A_SMB_INT_ENABLE 0x1908c
36147 #define S_MSTTXFIFOPAREN 21
36148 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
36149 #define F_MSTTXFIFOPAREN V_MSTTXFIFOPAREN(1U)
36151 #define S_MSTRXFIFOPAREN 20
36152 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
36153 #define F_MSTRXFIFOPAREN V_MSTRXFIFOPAREN(1U)
36155 #define S_SLVFIFOPAREN 19
36156 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
36157 #define F_SLVFIFOPAREN V_SLVFIFOPAREN(1U)
36159 #define S_SLVUNEXPBUSSTOPEN 18
36160 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
36161 #define F_SLVUNEXPBUSSTOPEN V_SLVUNEXPBUSSTOPEN(1U)
36163 #define S_SLVUNEXPBUSSTARTEN 17
36164 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
36165 #define F_SLVUNEXPBUSSTARTEN V_SLVUNEXPBUSSTARTEN(1U)
36167 #define S_SLVCOMMANDCODEINVEN 16
36168 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
36169 #define F_SLVCOMMANDCODEINVEN V_SLVCOMMANDCODEINVEN(1U)
36171 #define S_SLVBYTECNTERREN 15
36172 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
36173 #define F_SLVBYTECNTERREN V_SLVBYTECNTERREN(1U)
36175 #define S_SLVUNEXPACKMSTEN 14
36176 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
36177 #define F_SLVUNEXPACKMSTEN V_SLVUNEXPACKMSTEN(1U)
36179 #define S_SLVUNEXPNACKMSTEN 13
36180 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
36181 #define F_SLVUNEXPNACKMSTEN V_SLVUNEXPNACKMSTEN(1U)
36183 #define S_SLVNOBUSSTOPEN 12
36184 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
36185 #define F_SLVNOBUSSTOPEN V_SLVNOBUSSTOPEN(1U)
36187 #define S_SLVNOREPSTARTEN 11
36188 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
36189 #define F_SLVNOREPSTARTEN V_SLVNOREPSTARTEN(1U)
36191 #define S_SLVRXADDRINTEN 10
36192 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
36193 #define F_SLVRXADDRINTEN V_SLVRXADDRINTEN(1U)
36195 #define S_SLVRXPECERRINTEN 9
36196 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
36197 #define F_SLVRXPECERRINTEN V_SLVRXPECERRINTEN(1U)
36199 #define S_SLVPREPTOARPINTEN 8
36200 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
36201 #define F_SLVPREPTOARPINTEN V_SLVPREPTOARPINTEN(1U)
36203 #define S_SLVTIMEOUTINTEN 7
36204 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
36205 #define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U)
36207 #define S_SLVERRINTEN 6
36208 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
36209 #define F_SLVERRINTEN V_SLVERRINTEN(1U)
36211 #define S_SLVDONEINTEN 5
36212 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
36213 #define F_SLVDONEINTEN V_SLVDONEINTEN(1U)
36215 #define S_SLVRXRDYINTEN 4
36216 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
36217 #define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U)
36219 #define S_MSTTIMEOUTINTEN 3
36220 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
36221 #define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U)
36223 #define S_MSTNACKINTEN 2
36224 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
36225 #define F_MSTNACKINTEN V_MSTNACKINTEN(1U)
36227 #define S_MSTLOSTARBINTEN 1
36228 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
36229 #define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U)
36231 #define S_MSTDONEINTEN 0
36232 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
36233 #define F_MSTDONEINTEN V_MSTDONEINTEN(1U)
36235 #define A_SMB_INT_CAUSE 0x19090
36237 #define S_MSTTXFIFOPARINT 21
36238 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
36239 #define F_MSTTXFIFOPARINT V_MSTTXFIFOPARINT(1U)
36241 #define S_MSTRXFIFOPARINT 20
36242 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
36243 #define F_MSTRXFIFOPARINT V_MSTRXFIFOPARINT(1U)
36245 #define S_SLVFIFOPARINT 19
36246 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
36247 #define F_SLVFIFOPARINT V_SLVFIFOPARINT(1U)
36249 #define S_SLVUNEXPBUSSTOPINT 18
36250 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
36251 #define F_SLVUNEXPBUSSTOPINT V_SLVUNEXPBUSSTOPINT(1U)
36253 #define S_SLVUNEXPBUSSTARTINT 17
36254 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
36255 #define F_SLVUNEXPBUSSTARTINT V_SLVUNEXPBUSSTARTINT(1U)
36257 #define S_SLVCOMMANDCODEINVINT 16
36258 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
36259 #define F_SLVCOMMANDCODEINVINT V_SLVCOMMANDCODEINVINT(1U)
36261 #define S_SLVBYTECNTERRINT 15
36262 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
36263 #define F_SLVBYTECNTERRINT V_SLVBYTECNTERRINT(1U)
36265 #define S_SLVUNEXPACKMSTINT 14
36266 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
36267 #define F_SLVUNEXPACKMSTINT V_SLVUNEXPACKMSTINT(1U)
36269 #define S_SLVUNEXPNACKMSTINT 13
36270 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
36271 #define F_SLVUNEXPNACKMSTINT V_SLVUNEXPNACKMSTINT(1U)
36273 #define S_SLVNOBUSSTOPINT 12
36274 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
36275 #define F_SLVNOBUSSTOPINT V_SLVNOBUSSTOPINT(1U)
36277 #define S_SLVNOREPSTARTINT 11
36278 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
36279 #define F_SLVNOREPSTARTINT V_SLVNOREPSTARTINT(1U)
36281 #define S_SLVRXADDRINT 10
36282 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
36283 #define F_SLVRXADDRINT V_SLVRXADDRINT(1U)
36285 #define S_SLVRXPECERRINT 9
36286 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
36287 #define F_SLVRXPECERRINT V_SLVRXPECERRINT(1U)
36289 #define S_SLVPREPTOARPINT 8
36290 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
36291 #define F_SLVPREPTOARPINT V_SLVPREPTOARPINT(1U)
36293 #define S_SLVTIMEOUTINT 7
36294 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
36295 #define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U)
36297 #define S_SLVERRINT 6
36298 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
36299 #define F_SLVERRINT V_SLVERRINT(1U)
36301 #define S_SLVDONEINT 5
36302 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
36303 #define F_SLVDONEINT V_SLVDONEINT(1U)
36305 #define S_SLVRXRDYINT 4
36306 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
36307 #define F_SLVRXRDYINT V_SLVRXRDYINT(1U)
36309 #define S_MSTTIMEOUTINT 3
36310 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
36311 #define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U)
36313 #define S_MSTNACKINT 2
36314 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
36315 #define F_MSTNACKINT V_MSTNACKINT(1U)
36317 #define S_MSTLOSTARBINT 1
36318 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
36319 #define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U)
36321 #define S_MSTDONEINT 0
36322 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
36323 #define F_MSTDONEINT V_MSTDONEINT(1U)
36325 #define A_SMB_DEBUG_DATA 0x19094
36327 #define S_DEBUGDATAH 16
36328 #define M_DEBUGDATAH 0xffffU
36329 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
36330 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
36332 #define S_DEBUGDATAL 0
36333 #define M_DEBUGDATAL 0xffffU
36334 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
36335 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
36337 #define A_SMB_PERR_EN 0x19098
36339 #define S_MSTTXFIFOPERREN 2
36340 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
36341 #define F_MSTTXFIFOPERREN V_MSTTXFIFOPERREN(1U)
36343 #define S_MSTRXFIFOPERREN 1
36344 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
36345 #define F_MSTRXFIFOPERREN V_MSTRXFIFOPERREN(1U)
36347 #define S_SLVFIFOPERREN 0
36348 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
36349 #define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U)
36351 #define S_MSTTXFIFO 21
36352 #define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
36353 #define F_MSTTXFIFO V_MSTTXFIFO(1U)
36355 #define S_MSTRXFIFO 19
36356 #define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
36357 #define F_MSTRXFIFO V_MSTRXFIFO(1U)
36359 #define S_SLVFIFO 18
36360 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
36361 #define F_SLVFIFO V_SLVFIFO(1U)
36363 #define A_SMB_PERR_INJ 0x1909c
36365 #define S_MSTTXINJDATAERR 3
36366 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
36367 #define F_MSTTXINJDATAERR V_MSTTXINJDATAERR(1U)
36369 #define S_MSTRXINJDATAERR 2
36370 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
36371 #define F_MSTRXINJDATAERR V_MSTRXINJDATAERR(1U)
36373 #define S_SLVINJDATAERR 1
36374 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
36375 #define F_SLVINJDATAERR V_SLVINJDATAERR(1U)
36377 #define S_FIFOINJDATAERREN 0
36378 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
36379 #define F_FIFOINJDATAERREN V_FIFOINJDATAERREN(1U)
36381 #define A_SMB_SLV_ARP_CTL 0x190a0
36383 #define S_ARPCOMMANDCODE 2
36384 #define M_ARPCOMMANDCODE 0xffU
36385 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
36386 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
36388 #define S_ARPADDRRES 1
36389 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
36390 #define F_ARPADDRRES V_ARPADDRRES(1U)
36392 #define S_ARPADDRVAL 0
36393 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
36394 #define F_ARPADDRVAL V_ARPADDRVAL(1U)
36396 #define A_SMB_ARP_UDID0 0x190a4
36397 #define A_SMB_ARP_UDID1 0x190a8
36399 #define S_SUBSYSTEMVENDORID 16
36400 #define M_SUBSYSTEMVENDORID 0xffffU
36401 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
36402 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
36404 #define S_SUBSYSTEMDEVICEID 0
36405 #define M_SUBSYSTEMDEVICEID 0xffffU
36406 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
36407 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
36409 #define A_SMB_ARP_UDID2 0x190ac
36411 #define S_DEVICEID 16
36412 #define M_DEVICEID 0xffffU
36413 #define V_DEVICEID(x) ((x) << S_DEVICEID)
36414 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
36416 #define S_INTERFACE 0
36417 #define M_INTERFACE 0xffffU
36418 #define V_INTERFACE(x) ((x) << S_INTERFACE)
36419 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
36421 #define A_SMB_ARP_UDID3 0x190b0
36423 #define S_DEVICECAP 24
36424 #define M_DEVICECAP 0xffU
36425 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
36426 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
36428 #define S_VERSIONID 16
36429 #define M_VERSIONID 0xffU
36430 #define V_VERSIONID(x) ((x) << S_VERSIONID)
36431 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
36433 #define S_VENDORID 0
36434 #define M_VENDORID 0xffffU
36435 #define V_VENDORID(x) ((x) << S_VENDORID)
36436 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
36438 #define A_SMB_SLV_AUX_ADDR0 0x190b4
36440 #define S_AUXADDR0VAL 6
36441 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
36442 #define F_AUXADDR0VAL V_AUXADDR0VAL(1U)
36444 #define S_AUXADDR0 0
36445 #define M_AUXADDR0 0x3fU
36446 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
36447 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
36449 #define A_SMB_SLV_AUX_ADDR1 0x190b8
36451 #define S_AUXADDR1VAL 6
36452 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
36453 #define F_AUXADDR1VAL V_AUXADDR1VAL(1U)
36455 #define S_AUXADDR1 0
36456 #define M_AUXADDR1 0x3fU
36457 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
36458 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
36460 #define A_SMB_SLV_AUX_ADDR2 0x190bc
36462 #define S_AUXADDR2VAL 6
36463 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
36464 #define F_AUXADDR2VAL V_AUXADDR2VAL(1U)
36466 #define S_AUXADDR2 0
36467 #define M_AUXADDR2 0x3fU
36468 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
36469 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
36471 #define A_SMB_SLV_AUX_ADDR3 0x190c0
36473 #define S_AUXADDR3VAL 6
36474 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
36475 #define F_AUXADDR3VAL V_AUXADDR3VAL(1U)
36477 #define S_AUXADDR3 0
36478 #define M_AUXADDR3 0x3fU
36479 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
36480 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
36482 #define A_SMB_COMMAND_CODE0 0x190c4
36484 #define S_SMBUSCOMMANDCODE0 0
36485 #define M_SMBUSCOMMANDCODE0 0xffU
36486 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
36487 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
36489 #define A_SMB_COMMAND_CODE1 0x190c8
36491 #define S_SMBUSCOMMANDCODE1 0
36492 #define M_SMBUSCOMMANDCODE1 0xffU
36493 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
36494 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
36496 #define A_SMB_COMMAND_CODE2 0x190cc
36498 #define S_SMBUSCOMMANDCODE2 0
36499 #define M_SMBUSCOMMANDCODE2 0xffU
36500 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
36501 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
36503 #define A_SMB_COMMAND_CODE3 0x190d0
36505 #define S_SMBUSCOMMANDCODE3 0
36506 #define M_SMBUSCOMMANDCODE3 0xffU
36507 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
36508 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
36510 #define A_SMB_COMMAND_CODE4 0x190d4
36512 #define S_SMBUSCOMMANDCODE4 0
36513 #define M_SMBUSCOMMANDCODE4 0xffU
36514 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
36515 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
36517 #define A_SMB_COMMAND_CODE5 0x190d8
36519 #define S_SMBUSCOMMANDCODE5 0
36520 #define M_SMBUSCOMMANDCODE5 0xffU
36521 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
36522 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
36524 #define A_SMB_COMMAND_CODE6 0x190dc
36526 #define S_SMBUSCOMMANDCODE6 0
36527 #define M_SMBUSCOMMANDCODE6 0xffU
36528 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
36529 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
36531 #define A_SMB_COMMAND_CODE7 0x190e0
36533 #define S_SMBUSCOMMANDCODE7 0
36534 #define M_SMBUSCOMMANDCODE7 0xffU
36535 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
36536 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
36538 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
36540 #define S_MACROCNTCLKCFG 8
36541 #define M_MACROCNTCLKCFG 0x1fU
36542 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
36543 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
36545 #define S_MICROCNTCLKCFG 0
36546 #define M_MICROCNTCLKCFG 0xffU
36547 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
36548 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
36550 #define A_SMB_CTL_STATUS 0x190e8
36552 #define S_MSTBUSBUSY 2
36553 #define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
36554 #define F_MSTBUSBUSY V_MSTBUSBUSY(1U)
36556 #define S_SLVBUSBUSY 1
36557 #define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
36558 #define F_SLVBUSBUSY V_SLVBUSBUSY(1U)
36560 #define S_BUSBUSY 0
36561 #define V_BUSBUSY(x) ((x) << S_BUSBUSY)
36562 #define F_BUSBUSY V_BUSBUSY(1U)
36564 /* registers for module I2CM */
36565 #define I2CM_BASE_ADDR 0x190f0
36567 #define A_I2CM_CFG 0x190f0
36569 #define S_I2C_CLKDIV 0
36570 #define M_I2C_CLKDIV 0xfffU
36571 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
36572 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
36574 #define S_I2C_CLKDIV16B 0
36575 #define M_I2C_CLKDIV16B 0xffffU
36576 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
36577 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
36579 #define A_I2CM_DATA 0x190f4
36581 #define S_I2C_DATA 0
36582 #define M_I2C_DATA 0xffU
36583 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
36584 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
36586 #define A_I2CM_OP 0x190f8
36588 #define S_I2C_ACK 30
36589 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
36590 #define F_I2C_ACK V_I2C_ACK(1U)
36592 #define S_I2C_CONT 1
36593 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
36594 #define F_I2C_CONT V_I2C_CONT(1U)
36597 #define V_OP(x) ((x) << S_OP)
36598 #define F_OP V_OP(1U)
36600 /* registers for module MI */
36601 #define MI_BASE_ADDR 0x19100
36603 #define A_MI_CFG 0x19100
36606 #define V_T4_ST(x) ((x) << S_T4_ST)
36607 #define F_T4_ST V_T4_ST(1U)
36610 #define M_CLKDIV 0xffU
36611 #define V_CLKDIV(x) ((x) << S_CLKDIV)
36612 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
36616 #define V_ST(x) ((x) << S_ST)
36617 #define G_ST(x) (((x) >> S_ST) & M_ST)
36620 #define V_PREEN(x) ((x) << S_PREEN)
36621 #define F_PREEN V_PREEN(1U)
36624 #define V_MDIINV(x) ((x) << S_MDIINV)
36625 #define F_MDIINV V_MDIINV(1U)
36627 #define S_MDIO_1P2V_SEL 0
36628 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
36629 #define F_MDIO_1P2V_SEL V_MDIO_1P2V_SEL(1U)
36631 #define A_MI_ADDR 0x19104
36633 #define S_PHYADDR 5
36634 #define M_PHYADDR 0x1fU
36635 #define V_PHYADDR(x) ((x) << S_PHYADDR)
36636 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
36638 #define S_REGADDR 0
36639 #define M_REGADDR 0x1fU
36640 #define V_REGADDR(x) ((x) << S_REGADDR)
36641 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
36643 #define A_MI_DATA 0x19108
36645 #define S_MDIDATA 0
36646 #define M_MDIDATA 0xffffU
36647 #define V_MDIDATA(x) ((x) << S_MDIDATA)
36648 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
36650 #define A_MI_OP 0x1910c
36653 #define V_INC(x) ((x) << S_INC)
36654 #define F_INC V_INC(1U)
36657 #define M_MDIOP 0x3U
36658 #define V_MDIOP(x) ((x) << S_MDIOP)
36659 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
36661 /* registers for module UART */
36662 #define UART_BASE_ADDR 0x19110
36664 #define A_UART_CONFIG 0x19110
36666 #define S_STOPBITS 22
36667 #define M_STOPBITS 0x3U
36668 #define V_STOPBITS(x) ((x) << S_STOPBITS)
36669 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
36671 #define S_PARITY 20
36672 #define M_PARITY 0x3U
36673 #define V_PARITY(x) ((x) << S_PARITY)
36674 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
36676 #define S_DATABITS 16
36677 #define M_DATABITS 0xfU
36678 #define V_DATABITS(x) ((x) << S_DATABITS)
36679 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
36681 #define S_UART_CLKDIV 0
36682 #define M_UART_CLKDIV 0xfffU
36683 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
36684 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
36686 /* registers for module PMU */
36687 #define PMU_BASE_ADDR 0x19120
36689 #define A_PMU_PART_CG_PWRMODE 0x19120
36691 #define S_TPPARTCGEN 14
36692 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
36693 #define F_TPPARTCGEN V_TPPARTCGEN(1U)
36695 #define S_PDPPARTCGEN 13
36696 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
36697 #define F_PDPPARTCGEN V_PDPPARTCGEN(1U)
36699 #define S_PCIEPARTCGEN 12
36700 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
36701 #define F_PCIEPARTCGEN V_PCIEPARTCGEN(1U)
36703 #define S_EDC1PARTCGEN 11
36704 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
36705 #define F_EDC1PARTCGEN V_EDC1PARTCGEN(1U)
36707 #define S_MCPARTCGEN 10
36708 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
36709 #define F_MCPARTCGEN V_MCPARTCGEN(1U)
36711 #define S_EDC0PARTCGEN 9
36712 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
36713 #define F_EDC0PARTCGEN V_EDC0PARTCGEN(1U)
36715 #define S_LEPARTCGEN 8
36716 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
36717 #define F_LEPARTCGEN V_LEPARTCGEN(1U)
36719 #define S_INITPOWERMODE 0
36720 #define M_INITPOWERMODE 0x3U
36721 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
36722 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
36724 #define S_SGE_PART_CGEN 19
36725 #define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
36726 #define F_SGE_PART_CGEN V_SGE_PART_CGEN(1U)
36728 #define S_PDP_PART_CGEN 18
36729 #define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
36730 #define F_PDP_PART_CGEN V_PDP_PART_CGEN(1U)
36732 #define S_TP_PART_CGEN 17
36733 #define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
36734 #define F_TP_PART_CGEN V_TP_PART_CGEN(1U)
36736 #define S_EDC0_PART_CGEN 16
36737 #define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
36738 #define F_EDC0_PART_CGEN V_EDC0_PART_CGEN(1U)
36740 #define S_EDC1_PART_CGEN 15
36741 #define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
36742 #define F_EDC1_PART_CGEN V_EDC1_PART_CGEN(1U)
36744 #define S_LE_PART_CGEN 14
36745 #define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
36746 #define F_LE_PART_CGEN V_LE_PART_CGEN(1U)
36748 #define S_MA_PART_CGEN 13
36749 #define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
36750 #define F_MA_PART_CGEN V_MA_PART_CGEN(1U)
36752 #define S_MC0_PART_CGEN 12
36753 #define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
36754 #define F_MC0_PART_CGEN V_MC0_PART_CGEN(1U)
36756 #define S_MC1_PART_CGEN 11
36757 #define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
36758 #define F_MC1_PART_CGEN V_MC1_PART_CGEN(1U)
36760 #define S_PCIE_PART_CGEN 10
36761 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
36762 #define F_PCIE_PART_CGEN V_PCIE_PART_CGEN(1U)
36764 #define S_PL_DIS_PRTY_CHK 20
36765 #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
36766 #define F_PL_DIS_PRTY_CHK V_PL_DIS_PRTY_CHK(1U)
36768 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
36770 #define S_HWWAKEUPEN 5
36771 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
36772 #define F_HWWAKEUPEN V_HWWAKEUPEN(1U)
36774 #define S_PORT3SLEEPMODE 4
36775 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
36776 #define F_PORT3SLEEPMODE V_PORT3SLEEPMODE(1U)
36778 #define S_PORT2SLEEPMODE 3
36779 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
36780 #define F_PORT2SLEEPMODE V_PORT2SLEEPMODE(1U)
36782 #define S_PORT1SLEEPMODE 2
36783 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
36784 #define F_PORT1SLEEPMODE V_PORT1SLEEPMODE(1U)
36786 #define S_PORT0SLEEPMODE 1
36787 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
36788 #define F_PORT0SLEEPMODE V_PORT0SLEEPMODE(1U)
36791 #define V_WAKEUP(x) ((x) << S_WAKEUP)
36792 #define F_WAKEUP V_WAKEUP(1U)
36794 #define S_GLOBALDEEPSLEEPEN 6
36795 #define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
36796 #define F_GLOBALDEEPSLEEPEN V_GLOBALDEEPSLEEPEN(1U)
36798 /* registers for module ULP_RX */
36799 #define ULP_RX_BASE_ADDR 0x19150
36801 #define A_ULP_RX_CTL 0x19150
36803 #define S_PCMD1THRESHOLD 24
36804 #define M_PCMD1THRESHOLD 0xffU
36805 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
36806 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
36808 #define S_PCMD0THRESHOLD 16
36809 #define M_PCMD0THRESHOLD 0xffU
36810 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
36811 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
36813 #define S_DISABLE_0B_STAG_ERR 14
36814 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
36815 #define F_DISABLE_0B_STAG_ERR V_DISABLE_0B_STAG_ERR(1U)
36817 #define S_RDMA_0B_WR_OPCODE 10
36818 #define M_RDMA_0B_WR_OPCODE 0xfU
36819 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
36820 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
36822 #define S_RDMA_0B_WR_PASS 9
36823 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
36824 #define F_RDMA_0B_WR_PASS V_RDMA_0B_WR_PASS(1U)
36826 #define S_STAG_RQE 8
36827 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
36828 #define F_STAG_RQE V_STAG_RQE(1U)
36830 #define S_RDMA_STATE_EN 7
36831 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
36832 #define F_RDMA_STATE_EN V_RDMA_STATE_EN(1U)
36834 #define S_CRC1_EN 6
36835 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
36836 #define F_CRC1_EN V_CRC1_EN(1U)
36838 #define S_RDMA_0B_WR_CQE 5
36839 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
36840 #define F_RDMA_0B_WR_CQE V_RDMA_0B_WR_CQE(1U)
36842 #define S_PCIE_ATRB_EN 4
36843 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
36844 #define F_PCIE_ATRB_EN V_PCIE_ATRB_EN(1U)
36846 #define S_RDMA_PERMISSIVE_MODE 3
36847 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
36848 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U)
36850 #define S_PAGEPODME 2
36851 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
36852 #define F_PAGEPODME V_PAGEPODME(1U)
36854 #define S_ISCSITAGTCB 1
36855 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
36856 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U)
36858 #define S_TDDPTAGTCB 0
36859 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
36860 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U)
36862 #define A_ULP_RX_INT_ENABLE 0x19154
36864 #define S_ENABLE_CTX_1 24
36865 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
36866 #define F_ENABLE_CTX_1 V_ENABLE_CTX_1(1U)
36868 #define S_ENABLE_CTX_0 23
36869 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
36870 #define F_ENABLE_CTX_0 V_ENABLE_CTX_0(1U)
36872 #define S_ENABLE_FF 22
36873 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
36874 #define F_ENABLE_FF V_ENABLE_FF(1U)
36876 #define S_ENABLE_APF_1 21
36877 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
36878 #define F_ENABLE_APF_1 V_ENABLE_APF_1(1U)
36880 #define S_ENABLE_APF_0 20
36881 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
36882 #define F_ENABLE_APF_0 V_ENABLE_APF_0(1U)
36884 #define S_ENABLE_AF_1 19
36885 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
36886 #define F_ENABLE_AF_1 V_ENABLE_AF_1(1U)
36888 #define S_ENABLE_AF_0 18
36889 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
36890 #define F_ENABLE_AF_0 V_ENABLE_AF_0(1U)
36892 #define S_ENABLE_DDPDF_1 17
36893 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
36894 #define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U)
36896 #define S_ENABLE_DDPMF_1 16
36897 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
36898 #define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U)
36900 #define S_ENABLE_MEMRF_1 15
36901 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
36902 #define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U)
36904 #define S_ENABLE_PRSDF_1 14
36905 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
36906 #define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U)
36908 #define S_ENABLE_DDPDF_0 13
36909 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
36910 #define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U)
36912 #define S_ENABLE_DDPMF_0 12
36913 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
36914 #define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U)
36916 #define S_ENABLE_MEMRF_0 11
36917 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
36918 #define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U)
36920 #define S_ENABLE_PRSDF_0 10
36921 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
36922 #define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U)
36924 #define S_ENABLE_PCMDF_1 9
36925 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
36926 #define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U)
36928 #define S_ENABLE_TPTCF_1 8
36929 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
36930 #define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U)
36932 #define S_ENABLE_DDPCF_1 7
36933 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
36934 #define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U)
36936 #define S_ENABLE_MPARF_1 6
36937 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
36938 #define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U)
36940 #define S_ENABLE_MPARC_1 5
36941 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
36942 #define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U)
36944 #define S_ENABLE_PCMDF_0 4
36945 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
36946 #define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U)
36948 #define S_ENABLE_TPTCF_0 3
36949 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
36950 #define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U)
36952 #define S_ENABLE_DDPCF_0 2
36953 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
36954 #define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U)
36956 #define S_ENABLE_MPARF_0 1
36957 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
36958 #define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U)
36960 #define S_ENABLE_MPARC_0 0
36961 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
36962 #define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U)
36964 #define S_SE_CNT_MISMATCH_1 26
36965 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
36966 #define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U)
36968 #define S_SE_CNT_MISMATCH_0 25
36969 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
36970 #define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U)
36972 #define A_ULP_RX_INT_CAUSE 0x19158
36974 #define S_CAUSE_CTX_1 24
36975 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
36976 #define F_CAUSE_CTX_1 V_CAUSE_CTX_1(1U)
36978 #define S_CAUSE_CTX_0 23
36979 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
36980 #define F_CAUSE_CTX_0 V_CAUSE_CTX_0(1U)
36982 #define S_CAUSE_FF 22
36983 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
36984 #define F_CAUSE_FF V_CAUSE_FF(1U)
36986 #define S_CAUSE_APF_1 21
36987 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
36988 #define F_CAUSE_APF_1 V_CAUSE_APF_1(1U)
36990 #define S_CAUSE_APF_0 20
36991 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
36992 #define F_CAUSE_APF_0 V_CAUSE_APF_0(1U)
36994 #define S_CAUSE_AF_1 19
36995 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
36996 #define F_CAUSE_AF_1 V_CAUSE_AF_1(1U)
36998 #define S_CAUSE_AF_0 18
36999 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
37000 #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U)
37002 #define S_CAUSE_DDPDF_1 17
37003 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
37004 #define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U)
37006 #define S_CAUSE_DDPMF_1 16
37007 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
37008 #define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U)
37010 #define S_CAUSE_MEMRF_1 15
37011 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
37012 #define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U)
37014 #define S_CAUSE_PRSDF_1 14
37015 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
37016 #define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U)
37018 #define S_CAUSE_DDPDF_0 13
37019 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
37020 #define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U)
37022 #define S_CAUSE_DDPMF_0 12
37023 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
37024 #define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U)
37026 #define S_CAUSE_MEMRF_0 11
37027 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
37028 #define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U)
37030 #define S_CAUSE_PRSDF_0 10
37031 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
37032 #define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U)
37034 #define S_CAUSE_PCMDF_1 9
37035 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
37036 #define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U)
37038 #define S_CAUSE_TPTCF_1 8
37039 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
37040 #define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U)
37042 #define S_CAUSE_DDPCF_1 7
37043 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
37044 #define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U)
37046 #define S_CAUSE_MPARF_1 6
37047 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
37048 #define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U)
37050 #define S_CAUSE_MPARC_1 5
37051 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
37052 #define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U)
37054 #define S_CAUSE_PCMDF_0 4
37055 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
37056 #define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U)
37058 #define S_CAUSE_TPTCF_0 3
37059 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
37060 #define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U)
37062 #define S_CAUSE_DDPCF_0 2
37063 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
37064 #define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U)
37066 #define S_CAUSE_MPARF_0 1
37067 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
37068 #define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U)
37070 #define S_CAUSE_MPARC_0 0
37071 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
37072 #define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U)
37074 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
37076 #define S_ISCSILLIMIT 6
37077 #define M_ISCSILLIMIT 0x3ffffffU
37078 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
37079 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
37081 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
37083 #define S_ISCSIULIMIT 6
37084 #define M_ISCSIULIMIT 0x3ffffffU
37085 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
37086 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
37088 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
37090 #define S_ISCSITAGMASK 6
37091 #define M_ISCSITAGMASK 0x3ffffffU
37092 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
37093 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
37095 #define A_ULP_RX_ISCSI_PSZ 0x19168
37098 #define M_HPZ3 0xfU
37099 #define V_HPZ3(x) ((x) << S_HPZ3)
37100 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
37103 #define M_HPZ2 0xfU
37104 #define V_HPZ2(x) ((x) << S_HPZ2)
37105 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
37108 #define M_HPZ1 0xfU
37109 #define V_HPZ1(x) ((x) << S_HPZ1)
37110 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
37113 #define M_HPZ0 0xfU
37114 #define V_HPZ0(x) ((x) << S_HPZ0)
37115 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
37117 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
37119 #define S_TDDPLLIMIT 6
37120 #define M_TDDPLLIMIT 0x3ffffffU
37121 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
37122 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
37124 #define A_ULP_RX_TDDP_ULIMIT 0x19170
37126 #define S_TDDPULIMIT 6
37127 #define M_TDDPULIMIT 0x3ffffffU
37128 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
37129 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
37131 #define A_ULP_RX_TDDP_TAGMASK 0x19174
37133 #define S_TDDPTAGMASK 6
37134 #define M_TDDPTAGMASK 0x3ffffffU
37135 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
37136 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
37138 #define A_ULP_RX_TDDP_PSZ 0x19178
37139 #define A_ULP_RX_STAG_LLIMIT 0x1917c
37140 #define A_ULP_RX_STAG_ULIMIT 0x19180
37141 #define A_ULP_RX_RQ_LLIMIT 0x19184
37142 #define A_ULP_RX_RQ_ULIMIT 0x19188
37143 #define A_ULP_RX_PBL_LLIMIT 0x1918c
37144 #define A_ULP_RX_PBL_ULIMIT 0x19190
37145 #define A_ULP_RX_CTX_BASE 0x19194
37146 #define A_ULP_RX_PERR_ENABLE 0x1919c
37148 #define S_PERR_ENABLE_FF 22
37149 #define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
37150 #define F_PERR_ENABLE_FF V_PERR_ENABLE_FF(1U)
37152 #define S_PERR_ENABLE_APF_1 21
37153 #define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
37154 #define F_PERR_ENABLE_APF_1 V_PERR_ENABLE_APF_1(1U)
37156 #define S_PERR_ENABLE_APF_0 20
37157 #define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
37158 #define F_PERR_ENABLE_APF_0 V_PERR_ENABLE_APF_0(1U)
37160 #define S_PERR_ENABLE_AF_1 19
37161 #define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
37162 #define F_PERR_ENABLE_AF_1 V_PERR_ENABLE_AF_1(1U)
37164 #define S_PERR_ENABLE_AF_0 18
37165 #define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
37166 #define F_PERR_ENABLE_AF_0 V_PERR_ENABLE_AF_0(1U)
37168 #define S_PERR_ENABLE_DDPDF_1 17
37169 #define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
37170 #define F_PERR_ENABLE_DDPDF_1 V_PERR_ENABLE_DDPDF_1(1U)
37172 #define S_PERR_ENABLE_DDPMF_1 16
37173 #define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
37174 #define F_PERR_ENABLE_DDPMF_1 V_PERR_ENABLE_DDPMF_1(1U)
37176 #define S_PERR_ENABLE_MEMRF_1 15
37177 #define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
37178 #define F_PERR_ENABLE_MEMRF_1 V_PERR_ENABLE_MEMRF_1(1U)
37180 #define S_PERR_ENABLE_PRSDF_1 14
37181 #define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
37182 #define F_PERR_ENABLE_PRSDF_1 V_PERR_ENABLE_PRSDF_1(1U)
37184 #define S_PERR_ENABLE_DDPDF_0 13
37185 #define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
37186 #define F_PERR_ENABLE_DDPDF_0 V_PERR_ENABLE_DDPDF_0(1U)
37188 #define S_PERR_ENABLE_DDPMF_0 12
37189 #define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
37190 #define F_PERR_ENABLE_DDPMF_0 V_PERR_ENABLE_DDPMF_0(1U)
37192 #define S_PERR_ENABLE_MEMRF_0 11
37193 #define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
37194 #define F_PERR_ENABLE_MEMRF_0 V_PERR_ENABLE_MEMRF_0(1U)
37196 #define S_PERR_ENABLE_PRSDF_0 10
37197 #define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
37198 #define F_PERR_ENABLE_PRSDF_0 V_PERR_ENABLE_PRSDF_0(1U)
37200 #define S_PERR_ENABLE_PCMDF_1 9
37201 #define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
37202 #define F_PERR_ENABLE_PCMDF_1 V_PERR_ENABLE_PCMDF_1(1U)
37204 #define S_PERR_ENABLE_TPTCF_1 8
37205 #define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
37206 #define F_PERR_ENABLE_TPTCF_1 V_PERR_ENABLE_TPTCF_1(1U)
37208 #define S_PERR_ENABLE_DDPCF_1 7
37209 #define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
37210 #define F_PERR_ENABLE_DDPCF_1 V_PERR_ENABLE_DDPCF_1(1U)
37212 #define S_PERR_ENABLE_MPARF_1 6
37213 #define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
37214 #define F_PERR_ENABLE_MPARF_1 V_PERR_ENABLE_MPARF_1(1U)
37216 #define S_PERR_ENABLE_MPARC_1 5
37217 #define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
37218 #define F_PERR_ENABLE_MPARC_1 V_PERR_ENABLE_MPARC_1(1U)
37220 #define S_PERR_ENABLE_PCMDF_0 4
37221 #define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
37222 #define F_PERR_ENABLE_PCMDF_0 V_PERR_ENABLE_PCMDF_0(1U)
37224 #define S_PERR_ENABLE_TPTCF_0 3
37225 #define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
37226 #define F_PERR_ENABLE_TPTCF_0 V_PERR_ENABLE_TPTCF_0(1U)
37228 #define S_PERR_ENABLE_DDPCF_0 2
37229 #define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
37230 #define F_PERR_ENABLE_DDPCF_0 V_PERR_ENABLE_DDPCF_0(1U)
37232 #define S_PERR_ENABLE_MPARF_0 1
37233 #define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
37234 #define F_PERR_ENABLE_MPARF_0 V_PERR_ENABLE_MPARF_0(1U)
37236 #define S_PERR_ENABLE_MPARC_0 0
37237 #define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
37238 #define F_PERR_ENABLE_MPARC_0 V_PERR_ENABLE_MPARC_0(1U)
37240 #define S_PERR_SE_CNT_MISMATCH_1 26
37241 #define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
37242 #define F_PERR_SE_CNT_MISMATCH_1 V_PERR_SE_CNT_MISMATCH_1(1U)
37244 #define S_PERR_SE_CNT_MISMATCH_0 25
37245 #define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
37246 #define F_PERR_SE_CNT_MISMATCH_0 V_PERR_SE_CNT_MISMATCH_0(1U)
37248 #define S_PERR_RSVD0 24
37249 #define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
37250 #define F_PERR_RSVD0 V_PERR_RSVD0(1U)
37252 #define S_PERR_RSVD1 23
37253 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
37254 #define F_PERR_RSVD1 V_PERR_RSVD1(1U)
37256 #define S_PERR_ENABLE_CTX_1 24
37257 #define V_PERR_ENABLE_CTX_1(x) ((x) << S_PERR_ENABLE_CTX_1)
37258 #define F_PERR_ENABLE_CTX_1 V_PERR_ENABLE_CTX_1(1U)
37260 #define S_PERR_ENABLE_CTX_0 23
37261 #define V_PERR_ENABLE_CTX_0(x) ((x) << S_PERR_ENABLE_CTX_0)
37262 #define F_PERR_ENABLE_CTX_0 V_PERR_ENABLE_CTX_0(1U)
37264 #define A_ULP_RX_PERR_INJECT 0x191a0
37265 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
37266 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
37267 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
37270 #define V_REQ(x) ((x) << S_REQ)
37271 #define F_REQ V_REQ(1U)
37274 #define V_WB(x) ((x) << S_WB)
37275 #define F_WB V_WB(1U)
37277 #define S_ULPRX_TID 0
37278 #define M_ULPRX_TID 0xfffffU
37279 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
37280 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
37282 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
37283 #define A_ULP_RX_SE_CNT_ERR 0x191d0
37284 #define A_ULP_RX_SE_CNT_CLR 0x191d4
37286 #define S_CLRCHAN0 4
37287 #define M_CLRCHAN0 0xfU
37288 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
37289 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
37291 #define S_CLRCHAN1 0
37292 #define M_CLRCHAN1 0xfU
37293 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
37294 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
37296 #define A_ULP_RX_SE_CNT_CH0 0x191d8
37298 #define S_SOP_CNT_OUT0 28
37299 #define M_SOP_CNT_OUT0 0xfU
37300 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
37301 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
37303 #define S_EOP_CNT_OUT0 24
37304 #define M_EOP_CNT_OUT0 0xfU
37305 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
37306 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
37308 #define S_SOP_CNT_AL0 20
37309 #define M_SOP_CNT_AL0 0xfU
37310 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
37311 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
37313 #define S_EOP_CNT_AL0 16
37314 #define M_EOP_CNT_AL0 0xfU
37315 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
37316 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
37318 #define S_SOP_CNT_MR0 12
37319 #define M_SOP_CNT_MR0 0xfU
37320 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
37321 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
37323 #define S_EOP_CNT_MR0 8
37324 #define M_EOP_CNT_MR0 0xfU
37325 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
37326 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
37328 #define S_SOP_CNT_IN0 4
37329 #define M_SOP_CNT_IN0 0xfU
37330 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
37331 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
37333 #define S_EOP_CNT_IN0 0
37334 #define M_EOP_CNT_IN0 0xfU
37335 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
37336 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
37338 #define A_ULP_RX_SE_CNT_CH1 0x191dc
37340 #define S_SOP_CNT_OUT1 28
37341 #define M_SOP_CNT_OUT1 0xfU
37342 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
37343 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
37345 #define S_EOP_CNT_OUT1 24
37346 #define M_EOP_CNT_OUT1 0xfU
37347 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
37348 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
37350 #define S_SOP_CNT_AL1 20
37351 #define M_SOP_CNT_AL1 0xfU
37352 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
37353 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
37355 #define S_EOP_CNT_AL1 16
37356 #define M_EOP_CNT_AL1 0xfU
37357 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
37358 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
37360 #define S_SOP_CNT_MR1 12
37361 #define M_SOP_CNT_MR1 0xfU
37362 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
37363 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
37365 #define S_EOP_CNT_MR1 8
37366 #define M_EOP_CNT_MR1 0xfU
37367 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
37368 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
37370 #define S_SOP_CNT_IN1 4
37371 #define M_SOP_CNT_IN1 0xfU
37372 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
37373 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
37375 #define S_EOP_CNT_IN1 0
37376 #define M_EOP_CNT_IN1 0xfU
37377 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
37378 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
37380 #define A_ULP_RX_DBG_CTL 0x191e0
37382 #define S_EN_DBG_H 17
37383 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
37384 #define F_EN_DBG_H V_EN_DBG_H(1U)
37386 #define S_EN_DBG_L 16
37387 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
37388 #define F_EN_DBG_L V_EN_DBG_L(1U)
37391 #define M_SEL_H 0xffU
37392 #define V_SEL_H(x) ((x) << S_SEL_H)
37393 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
37396 #define M_SEL_L 0xffU
37397 #define V_SEL_L(x) ((x) << S_SEL_L)
37398 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
37400 #define A_ULP_RX_DBG_DATAH 0x191e4
37401 #define A_ULP_RX_DBG_DATAL 0x191e8
37402 #define A_ULP_RX_LA_CHNL 0x19238
37404 #define S_CHNL_SEL 0
37405 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
37406 #define F_CHNL_SEL V_CHNL_SEL(1U)
37408 #define A_ULP_RX_LA_CTL 0x1923c
37410 #define S_TRC_SEL 0
37411 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
37412 #define F_TRC_SEL V_TRC_SEL(1U)
37414 #define A_ULP_RX_LA_RDPTR 0x19240
37417 #define M_RD_PTR 0x1ffU
37418 #define V_RD_PTR(x) ((x) << S_RD_PTR)
37419 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
37421 #define A_ULP_RX_LA_RDDATA 0x19244
37422 #define A_ULP_RX_LA_WRPTR 0x19248
37425 #define M_WR_PTR 0x1ffU
37426 #define V_WR_PTR(x) ((x) << S_WR_PTR)
37427 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
37429 #define A_ULP_RX_LA_RESERVED 0x1924c
37430 #define A_ULP_RX_CQE_GEN_EN 0x19250
37432 #define S_TERMIMATE_MSG 1
37433 #define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
37434 #define F_TERMIMATE_MSG V_TERMIMATE_MSG(1U)
37436 #define S_TERMINATE_WITH_ERR 0
37437 #define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
37438 #define F_TERMINATE_WITH_ERR V_TERMINATE_WITH_ERR(1U)
37440 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
37442 #define S_ATOMIC_REQ_QNO 22
37443 #define M_ATOMIC_REQ_QNO 0x3U
37444 #define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
37445 #define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
37447 #define S_ATOMIC_RSP_QNO 20
37448 #define M_ATOMIC_RSP_QNO 0x3U
37449 #define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
37450 #define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
37452 #define S_IMMEDIATE_QNO 18
37453 #define M_IMMEDIATE_QNO 0x3U
37454 #define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
37455 #define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
37457 #define S_IMMEDIATE_WITH_SE_QNO 16
37458 #define M_IMMEDIATE_WITH_SE_QNO 0x3U
37459 #define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
37460 #define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
37462 #define S_ATOMIC_WR_OPCODE 12
37463 #define M_ATOMIC_WR_OPCODE 0xfU
37464 #define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
37465 #define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
37467 #define S_ATOMIC_RD_OPCODE 8
37468 #define M_ATOMIC_RD_OPCODE 0xfU
37469 #define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
37470 #define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
37472 #define S_IMMEDIATE_OPCODE 4
37473 #define M_IMMEDIATE_OPCODE 0xfU
37474 #define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
37475 #define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
37477 #define S_IMMEDIATE_WITH_SE_OPCODE 0
37478 #define M_IMMEDIATE_WITH_SE_OPCODE 0xfU
37479 #define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
37480 #define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
37482 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
37484 #define S_EN_ORIG_DATA 0
37485 #define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
37486 #define F_EN_ORIG_DATA V_EN_ORIG_DATA(1U)
37488 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
37490 #define S_TERMINATE_STATUS_EN 4
37491 #define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
37492 #define F_TERMINATE_STATUS_EN V_TERMINATE_STATUS_EN(1U)
37494 #define S_MULTIPLE_PREF_ENABLE 3
37495 #define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
37496 #define F_MULTIPLE_PREF_ENABLE V_MULTIPLE_PREF_ENABLE(1U)
37498 #define S_UMUDP_PBL_PREF_ENABLE 2
37499 #define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
37500 #define F_UMUDP_PBL_PREF_ENABLE V_UMUDP_PBL_PREF_ENABLE(1U)
37502 #define S_RDMA_PBL_PREF_EN 1
37503 #define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
37504 #define F_RDMA_PBL_PREF_EN V_RDMA_PBL_PREF_EN(1U)
37506 #define S_SDC_CRC_PROT_EN 0
37507 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
37508 #define F_SDC_CRC_PROT_EN V_SDC_CRC_PROT_EN(1U)
37510 #define S_ISCSI_DCRC_ERROR_CMP_EN 25
37511 #define V_ISCSI_DCRC_ERROR_CMP_EN(x) ((x) << S_ISCSI_DCRC_ERROR_CMP_EN)
37512 #define F_ISCSI_DCRC_ERROR_CMP_EN V_ISCSI_DCRC_ERROR_CMP_EN(1U)
37514 #define S_ISCSITAGPI 24
37515 #define V_ISCSITAGPI(x) ((x) << S_ISCSITAGPI)
37516 #define F_ISCSITAGPI V_ISCSITAGPI(1U)
37518 #define S_DDP_VERSION_1 22
37519 #define M_DDP_VERSION_1 0x3U
37520 #define V_DDP_VERSION_1(x) ((x) << S_DDP_VERSION_1)
37521 #define G_DDP_VERSION_1(x) (((x) >> S_DDP_VERSION_1) & M_DDP_VERSION_1)
37523 #define S_DDP_VERSION_0 20
37524 #define M_DDP_VERSION_0 0x3U
37525 #define V_DDP_VERSION_0(x) ((x) << S_DDP_VERSION_0)
37526 #define G_DDP_VERSION_0(x) (((x) >> S_DDP_VERSION_0) & M_DDP_VERSION_0)
37528 #define S_RDMA_VERSION_1 18
37529 #define M_RDMA_VERSION_1 0x3U
37530 #define V_RDMA_VERSION_1(x) ((x) << S_RDMA_VERSION_1)
37531 #define G_RDMA_VERSION_1(x) (((x) >> S_RDMA_VERSION_1) & M_RDMA_VERSION_1)
37533 #define S_RDMA_VERSION_0 16
37534 #define M_RDMA_VERSION_0 0x3U
37535 #define V_RDMA_VERSION_0(x) ((x) << S_RDMA_VERSION_0)
37536 #define G_RDMA_VERSION_0(x) (((x) >> S_RDMA_VERSION_0) & M_RDMA_VERSION_0)
37538 #define S_PBL_BOUND_CHECK_W_PGLEN 15
37539 #define V_PBL_BOUND_CHECK_W_PGLEN(x) ((x) << S_PBL_BOUND_CHECK_W_PGLEN)
37540 #define F_PBL_BOUND_CHECK_W_PGLEN V_PBL_BOUND_CHECK_W_PGLEN(1U)
37542 #define S_ZBYTE_FIX_DISABLE 14
37543 #define V_ZBYTE_FIX_DISABLE(x) ((x) << S_ZBYTE_FIX_DISABLE)
37544 #define F_ZBYTE_FIX_DISABLE V_ZBYTE_FIX_DISABLE(1U)
37546 #define S_T10_OFFSET_UPDATE_EN 13
37547 #define V_T10_OFFSET_UPDATE_EN(x) ((x) << S_T10_OFFSET_UPDATE_EN)
37548 #define F_T10_OFFSET_UPDATE_EN V_T10_OFFSET_UPDATE_EN(1U)
37550 #define S_ULP_INSERT_PI 12
37551 #define V_ULP_INSERT_PI(x) ((x) << S_ULP_INSERT_PI)
37552 #define F_ULP_INSERT_PI V_ULP_INSERT_PI(1U)
37554 #define S_PDU_DPI 11
37555 #define V_PDU_DPI(x) ((x) << S_PDU_DPI)
37556 #define F_PDU_DPI V_PDU_DPI(1U)
37558 #define S_ISCSI_EFF_OFFSET_EN 10
37559 #define V_ISCSI_EFF_OFFSET_EN(x) ((x) << S_ISCSI_EFF_OFFSET_EN)
37560 #define F_ISCSI_EFF_OFFSET_EN V_ISCSI_EFF_OFFSET_EN(1U)
37562 #define S_ISCSI_ALL_CMP_MODE 9
37563 #define V_ISCSI_ALL_CMP_MODE(x) ((x) << S_ISCSI_ALL_CMP_MODE)
37564 #define F_ISCSI_ALL_CMP_MODE V_ISCSI_ALL_CMP_MODE(1U)
37566 #define S_ISCSI_ENABLE_HDR_CMD 8
37567 #define V_ISCSI_ENABLE_HDR_CMD(x) ((x) << S_ISCSI_ENABLE_HDR_CMD)
37568 #define F_ISCSI_ENABLE_HDR_CMD V_ISCSI_ENABLE_HDR_CMD(1U)
37570 #define S_ISCSI_FORCE_CMP_MODE 7
37571 #define V_ISCSI_FORCE_CMP_MODE(x) ((x) << S_ISCSI_FORCE_CMP_MODE)
37572 #define F_ISCSI_FORCE_CMP_MODE V_ISCSI_FORCE_CMP_MODE(1U)
37574 #define S_ISCSI_ENABLE_CMP_MODE 6
37575 #define V_ISCSI_ENABLE_CMP_MODE(x) ((x) << S_ISCSI_ENABLE_CMP_MODE)
37576 #define F_ISCSI_ENABLE_CMP_MODE V_ISCSI_ENABLE_CMP_MODE(1U)
37578 #define S_PIO_RDMA_SEND_RQE 5
37579 #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
37580 #define F_PIO_RDMA_SEND_RQE V_PIO_RDMA_SEND_RQE(1U)
37582 #define A_ULP_RX_CH0_CGEN 0x19260
37584 #define S_BYPASS_CGEN 7
37585 #define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
37586 #define F_BYPASS_CGEN V_BYPASS_CGEN(1U)
37588 #define S_TDDP_CGEN 6
37589 #define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
37590 #define F_TDDP_CGEN V_TDDP_CGEN(1U)
37592 #define S_ISCSI_CGEN 5
37593 #define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
37594 #define F_ISCSI_CGEN V_ISCSI_CGEN(1U)
37596 #define S_RDMA_CGEN 4
37597 #define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
37598 #define F_RDMA_CGEN V_RDMA_CGEN(1U)
37600 #define S_CHANNEL_CGEN 3
37601 #define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
37602 #define F_CHANNEL_CGEN V_CHANNEL_CGEN(1U)
37604 #define S_ALL_DATAPATH_CGEN 2
37605 #define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
37606 #define F_ALL_DATAPATH_CGEN V_ALL_DATAPATH_CGEN(1U)
37608 #define S_T10DIFF_DATAPATH_CGEN 1
37609 #define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
37610 #define F_T10DIFF_DATAPATH_CGEN V_T10DIFF_DATAPATH_CGEN(1U)
37612 #define S_RDMA_DATAPATH_CGEN 0
37613 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
37614 #define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U)
37616 #define A_ULP_RX_CH1_CGEN 0x19264
37617 #define A_ULP_RX_RFE_DISABLE 0x19268
37619 #define S_RQE_LIM_CHECK_RFE_DISABLE 0
37620 #define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
37621 #define F_RQE_LIM_CHECK_RFE_DISABLE V_RQE_LIM_CHECK_RFE_DISABLE(1U)
37623 #define A_ULP_RX_INT_ENABLE_2 0x1926c
37625 #define S_ULPRX2MA_INTFPERR 8
37626 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
37627 #define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U)
37629 #define S_ALN_SDC_ERR_1 7
37630 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
37631 #define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U)
37633 #define S_ALN_SDC_ERR_0 6
37634 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
37635 #define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U)
37637 #define S_PF_UNTAGGED_TPT_1 5
37638 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
37639 #define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U)
37641 #define S_PF_UNTAGGED_TPT_0 4
37642 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
37643 #define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U)
37645 #define S_PF_PBL_1 3
37646 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
37647 #define F_PF_PBL_1 V_PF_PBL_1(1U)
37649 #define S_PF_PBL_0 2
37650 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
37651 #define F_PF_PBL_0 V_PF_PBL_0(1U)
37653 #define S_DDP_HINT_1 1
37654 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
37655 #define F_DDP_HINT_1 V_DDP_HINT_1(1U)
37657 #define S_DDP_HINT_0 0
37658 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
37659 #define F_DDP_HINT_0 V_DDP_HINT_0(1U)
37661 #define A_ULP_RX_INT_CAUSE_2 0x19270
37662 #define A_ULP_RX_PERR_ENABLE_2 0x19274
37664 #define S_ENABLE_ULPRX2MA_INTFPERR 8
37665 #define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
37666 #define F_ENABLE_ULPRX2MA_INTFPERR V_ENABLE_ULPRX2MA_INTFPERR(1U)
37668 #define S_ENABLE_ALN_SDC_ERR_1 7
37669 #define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
37670 #define F_ENABLE_ALN_SDC_ERR_1 V_ENABLE_ALN_SDC_ERR_1(1U)
37672 #define S_ENABLE_ALN_SDC_ERR_0 6
37673 #define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
37674 #define F_ENABLE_ALN_SDC_ERR_0 V_ENABLE_ALN_SDC_ERR_0(1U)
37676 #define S_ENABLE_PF_UNTAGGED_TPT_1 5
37677 #define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
37678 #define F_ENABLE_PF_UNTAGGED_TPT_1 V_ENABLE_PF_UNTAGGED_TPT_1(1U)
37680 #define S_ENABLE_PF_UNTAGGED_TPT_0 4
37681 #define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
37682 #define F_ENABLE_PF_UNTAGGED_TPT_0 V_ENABLE_PF_UNTAGGED_TPT_0(1U)
37684 #define S_ENABLE_PF_PBL_1 3
37685 #define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
37686 #define F_ENABLE_PF_PBL_1 V_ENABLE_PF_PBL_1(1U)
37688 #define S_ENABLE_PF_PBL_0 2
37689 #define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
37690 #define F_ENABLE_PF_PBL_0 V_ENABLE_PF_PBL_0(1U)
37692 #define S_ENABLE_DDP_HINT_1 1
37693 #define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
37694 #define F_ENABLE_DDP_HINT_1 V_ENABLE_DDP_HINT_1(1U)
37696 #define S_ENABLE_DDP_HINT_0 0
37697 #define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
37698 #define F_ENABLE_DDP_HINT_0 V_ENABLE_DDP_HINT_0(1U)
37700 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
37702 #define S_PIO_RQE_PBL_MULTIPLE_CNT 0
37703 #define M_PIO_RQE_PBL_MULTIPLE_CNT 0xfU
37704 #define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
37705 #define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
37707 #define A_ULP_RX_ATOMIC_LEN 0x1927c
37709 #define S_ATOMIC_RPL_LEN 16
37710 #define M_ATOMIC_RPL_LEN 0xffU
37711 #define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
37712 #define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
37714 #define S_ATOMIC_REQ_LEN 8
37715 #define M_ATOMIC_REQ_LEN 0xffU
37716 #define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
37717 #define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
37719 #define S_ATOMIC_IMMEDIATE_LEN 0
37720 #define M_ATOMIC_IMMEDIATE_LEN 0xffU
37721 #define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
37722 #define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
37724 #define A_ULP_RX_CGEN_GLOBAL 0x19280
37725 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
37727 #define S_CLEAR_CTX_ERR_CNT1 3
37728 #define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
37729 #define F_CLEAR_CTX_ERR_CNT1 V_CLEAR_CTX_ERR_CNT1(1U)
37731 #define S_CLEAR_CTX_ERR_CNT0 2
37732 #define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
37733 #define F_CLEAR_CTX_ERR_CNT0 V_CLEAR_CTX_ERR_CNT0(1U)
37735 #define S_SKIP_MA_REQ_EN1 1
37736 #define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
37737 #define F_SKIP_MA_REQ_EN1 V_SKIP_MA_REQ_EN1(1U)
37739 #define S_SKIP_MA_REQ_EN0 0
37740 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
37741 #define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U)
37743 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
37744 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
37745 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
37747 #define S_RD_OR_TERM_MSN_CHECK_ENABLE 2
37748 #define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
37749 #define F_RD_OR_TERM_MSN_CHECK_ENABLE V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
37751 #define S_ATOMIC_OP_MSN_CHECK_ENABLE 1
37752 #define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
37753 #define F_ATOMIC_OP_MSN_CHECK_ENABLE V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
37755 #define S_SEND_MSN_CHECK_ENABLE 0
37756 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
37757 #define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U)
37759 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
37761 #define S_TLSPPLLIMIT 6
37762 #define M_TLSPPLLIMIT 0x3ffffffU
37763 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
37764 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
37766 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
37768 #define S_TLSPPULIMIT 6
37769 #define M_TLSPPULIMIT 0x3ffffffU
37770 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
37771 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
37773 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
37775 #define S_TLSKEYLLIMIT 8
37776 #define M_TLSKEYLLIMIT 0xffffffU
37777 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
37778 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
37780 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
37782 #define S_TLSKEYULIMIT 8
37783 #define M_TLSKEYULIMIT 0xffffffU
37784 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
37785 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
37787 #define A_ULP_RX_TLS_CTL 0x192bc
37788 #define A_ULP_RX_TLS_IND_CMD 0x19348
37790 #define S_TLS_RX_REG_OFF_ADDR 0
37791 #define M_TLS_RX_REG_OFF_ADDR 0x3ffU
37792 #define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR)
37793 #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
37795 #define A_ULP_RX_TLS_IND_DATA 0x1934c
37797 /* registers for module SF */
37798 #define SF_BASE_ADDR 0x193f8
37800 #define A_SF_DATA 0x193f8
37801 #define A_SF_OP 0x193fc
37803 #define S_SF_LOCK 4
37804 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
37805 #define F_SF_LOCK V_SF_LOCK(1U)
37808 #define V_CONT(x) ((x) << S_CONT)
37809 #define F_CONT V_CONT(1U)
37811 #define S_BYTECNT 1
37812 #define M_BYTECNT 0x3U
37813 #define V_BYTECNT(x) ((x) << S_BYTECNT)
37814 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
37816 /* registers for module PL */
37817 #define PL_BASE_ADDR 0x19400
37819 #define A_PL_VF_WHOAMI 0x0
37821 #define S_PORTXMAP 24
37822 #define M_PORTXMAP 0x7U
37823 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
37824 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
37826 #define S_SOURCEBUS 16
37827 #define M_SOURCEBUS 0x3U
37828 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
37829 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
37831 #define S_SOURCEPF 8
37832 #define M_SOURCEPF 0x7U
37833 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
37834 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
37837 #define V_ISVF(x) ((x) << S_ISVF)
37838 #define F_ISVF V_ISVF(1U)
37841 #define M_VFID 0x7fU
37842 #define V_VFID(x) ((x) << S_VFID)
37843 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
37845 #define S_T6_SOURCEPF 9
37846 #define M_T6_SOURCEPF 0x7U
37847 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
37848 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
37850 #define S_T6_ISVF 8
37851 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
37852 #define F_T6_ISVF V_T6_ISVF(1U)
37854 #define S_T6_VFID 0
37855 #define M_T6_VFID 0xffU
37856 #define V_T6_VFID(x) ((x) << S_T6_VFID)
37857 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
37859 #define A_PL_VF_REV 0x4
37862 #define M_CHIPID 0xfU
37863 #define V_CHIPID(x) ((x) << S_CHIPID)
37864 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
37866 #define A_PL_VF_REVISION 0x8
37867 #define A_PL_PF_INT_CAUSE 0x3c0
37870 #define V_PFSW(x) ((x) << S_PFSW)
37871 #define F_PFSW V_PFSW(1U)
37874 #define V_PFSGE(x) ((x) << S_PFSGE)
37875 #define F_PFSGE V_PFSGE(1U)
37878 #define V_PFCIM(x) ((x) << S_PFCIM)
37879 #define F_PFCIM V_PFCIM(1U)
37882 #define V_PFMPS(x) ((x) << S_PFMPS)
37883 #define F_PFMPS V_PFMPS(1U)
37885 #define A_PL_PF_INT_ENABLE 0x3c4
37886 #define A_PL_PF_CTL 0x3c8
37889 #define V_SWINT(x) ((x) << S_SWINT)
37890 #define F_SWINT V_SWINT(1U)
37892 #define A_PL_WHOAMI 0x19400
37894 #define S_T6_SOURCEPF 9
37895 #define M_T6_SOURCEPF 0x7U
37896 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
37897 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
37899 #define S_T6_ISVF 8
37900 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
37901 #define F_T6_ISVF V_T6_ISVF(1U)
37903 #define S_T6_VFID 0
37904 #define M_T6_VFID 0xffU
37905 #define V_T6_VFID(x) ((x) << S_T6_VFID)
37906 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
37908 #define A_PL_PERR_CAUSE 0x19404
37911 #define V_UART(x) ((x) << S_UART)
37912 #define F_UART V_UART(1U)
37914 #define S_ULP_TX 27
37915 #define V_ULP_TX(x) ((x) << S_ULP_TX)
37916 #define F_ULP_TX V_ULP_TX(1U)
37919 #define V_SGE(x) ((x) << S_SGE)
37920 #define F_SGE V_SGE(1U)
37923 #define V_HMA(x) ((x) << S_HMA)
37924 #define F_HMA V_HMA(1U)
37926 #define S_CPL_SWITCH 24
37927 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
37928 #define F_CPL_SWITCH V_CPL_SWITCH(1U)
37930 #define S_ULP_RX 23
37931 #define V_ULP_RX(x) ((x) << S_ULP_RX)
37932 #define F_ULP_RX V_ULP_RX(1U)
37935 #define V_PM_RX(x) ((x) << S_PM_RX)
37936 #define F_PM_RX V_PM_RX(1U)
37939 #define V_PM_TX(x) ((x) << S_PM_TX)
37940 #define F_PM_TX V_PM_TX(1U)
37943 #define V_MA(x) ((x) << S_MA)
37944 #define F_MA V_MA(1U)
37947 #define V_TP(x) ((x) << S_TP)
37948 #define F_TP V_TP(1U)
37951 #define V_LE(x) ((x) << S_LE)
37952 #define F_LE V_LE(1U)
37955 #define V_EDC1(x) ((x) << S_EDC1)
37956 #define F_EDC1 V_EDC1(1U)
37959 #define V_EDC0(x) ((x) << S_EDC0)
37960 #define F_EDC0 V_EDC0(1U)
37963 #define V_MC(x) ((x) << S_MC)
37964 #define F_MC V_MC(1U)
37967 #define V_PCIE(x) ((x) << S_PCIE)
37968 #define F_PCIE V_PCIE(1U)
37971 #define V_PMU(x) ((x) << S_PMU)
37972 #define F_PMU V_PMU(1U)
37974 #define S_XGMAC_KR1 12
37975 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
37976 #define F_XGMAC_KR1 V_XGMAC_KR1(1U)
37978 #define S_XGMAC_KR0 11
37979 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
37980 #define F_XGMAC_KR0 V_XGMAC_KR0(1U)
37982 #define S_XGMAC1 10
37983 #define V_XGMAC1(x) ((x) << S_XGMAC1)
37984 #define F_XGMAC1 V_XGMAC1(1U)
37987 #define V_XGMAC0(x) ((x) << S_XGMAC0)
37988 #define F_XGMAC0 V_XGMAC0(1U)
37991 #define V_SMB(x) ((x) << S_SMB)
37992 #define F_SMB V_SMB(1U)
37995 #define V_SF(x) ((x) << S_SF)
37996 #define F_SF V_SF(1U)
37999 #define V_PL(x) ((x) << S_PL)
38000 #define F_PL V_PL(1U)
38003 #define V_NCSI(x) ((x) << S_NCSI)
38004 #define F_NCSI V_NCSI(1U)
38007 #define V_MPS(x) ((x) << S_MPS)
38008 #define F_MPS V_MPS(1U)
38011 #define V_MI(x) ((x) << S_MI)
38012 #define F_MI V_MI(1U)
38015 #define V_DBG(x) ((x) << S_DBG)
38016 #define F_DBG V_DBG(1U)
38019 #define V_I2CM(x) ((x) << S_I2CM)
38020 #define F_I2CM V_I2CM(1U)
38023 #define V_CIM(x) ((x) << S_CIM)
38024 #define F_CIM V_CIM(1U)
38027 #define V_MC1(x) ((x) << S_MC1)
38028 #define F_MC1 V_MC1(1U)
38031 #define V_MC0(x) ((x) << S_MC0)
38032 #define F_MC0 V_MC0(1U)
38035 #define V_ANYMAC(x) ((x) << S_ANYMAC)
38036 #define F_ANYMAC V_ANYMAC(1U)
38038 #define A_PL_PERR_ENABLE 0x19408
38039 #define A_PL_INT_CAUSE 0x1940c
38042 #define V_FLR(x) ((x) << S_FLR)
38043 #define F_FLR V_FLR(1U)
38045 #define S_SW_CIM 29
38046 #define V_SW_CIM(x) ((x) << S_SW_CIM)
38047 #define F_SW_CIM V_SW_CIM(1U)
38050 #define V_MAC3(x) ((x) << S_MAC3)
38051 #define F_MAC3 V_MAC3(1U)
38054 #define V_MAC2(x) ((x) << S_MAC2)
38055 #define F_MAC2 V_MAC2(1U)
38058 #define V_MAC1(x) ((x) << S_MAC1)
38059 #define F_MAC1 V_MAC1(1U)
38062 #define V_MAC0(x) ((x) << S_MAC0)
38063 #define F_MAC0 V_MAC0(1U)
38065 #define A_PL_INT_ENABLE 0x19410
38066 #define A_PL_INT_MAP0 0x19414
38068 #define S_MAPNCSI 16
38069 #define M_MAPNCSI 0x1ffU
38070 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
38071 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
38073 #define S_MAPDEFAULT 0
38074 #define M_MAPDEFAULT 0x1ffU
38075 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
38076 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
38078 #define A_PL_INT_MAP1 0x19418
38080 #define S_MAPXGMAC1 16
38081 #define M_MAPXGMAC1 0x1ffU
38082 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
38083 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
38085 #define S_MAPXGMAC0 0
38086 #define M_MAPXGMAC0 0x1ffU
38087 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
38088 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
38090 #define S_MAPMAC1 16
38091 #define M_MAPMAC1 0x1ffU
38092 #define V_MAPMAC1(x) ((x) << S_MAPMAC1)
38093 #define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
38095 #define S_MAPMAC0 0
38096 #define M_MAPMAC0 0x1ffU
38097 #define V_MAPMAC0(x) ((x) << S_MAPMAC0)
38098 #define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
38100 #define A_PL_INT_MAP2 0x1941c
38102 #define S_MAPXGMAC_KR1 16
38103 #define M_MAPXGMAC_KR1 0x1ffU
38104 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
38105 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
38107 #define S_MAPXGMAC_KR0 0
38108 #define M_MAPXGMAC_KR0 0x1ffU
38109 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
38110 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
38112 #define S_MAPMAC3 16
38113 #define M_MAPMAC3 0x1ffU
38114 #define V_MAPMAC3(x) ((x) << S_MAPMAC3)
38115 #define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
38117 #define S_MAPMAC2 0
38118 #define M_MAPMAC2 0x1ffU
38119 #define V_MAPMAC2(x) ((x) << S_MAPMAC2)
38120 #define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
38122 #define A_PL_INT_MAP3 0x19420
38125 #define M_MAPMI 0x1ffU
38126 #define V_MAPMI(x) ((x) << S_MAPMI)
38127 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
38130 #define M_MAPSMB 0x1ffU
38131 #define V_MAPSMB(x) ((x) << S_MAPSMB)
38132 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
38134 #define A_PL_INT_MAP4 0x19424
38136 #define S_MAPDBG 16
38137 #define M_MAPDBG 0x1ffU
38138 #define V_MAPDBG(x) ((x) << S_MAPDBG)
38139 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
38141 #define S_MAPI2CM 0
38142 #define M_MAPI2CM 0x1ffU
38143 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
38144 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
38146 #define A_PL_RST 0x19428
38148 #define S_FATALPERREN 3
38149 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
38150 #define F_FATALPERREN V_FATALPERREN(1U)
38152 #define S_SWINTCIM 2
38153 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
38154 #define F_SWINTCIM V_SWINTCIM(1U)
38157 #define V_PIORST(x) ((x) << S_PIORST)
38158 #define F_PIORST V_PIORST(1U)
38160 #define S_PIORSTMODE 0
38161 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
38162 #define F_PIORSTMODE V_PIORSTMODE(1U)
38164 #define S_AUTOPCIEPAUSE 4
38165 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
38166 #define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U)
38168 #define A_PL_PL_PERR_INJECT 0x1942c
38170 #define S_PL_MEMSEL 1
38171 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
38172 #define F_PL_MEMSEL V_PL_MEMSEL(1U)
38174 #define A_PL_PL_INT_CAUSE 0x19430
38176 #define S_PF_ENABLEERR 5
38177 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
38178 #define F_PF_ENABLEERR V_PF_ENABLEERR(1U)
38180 #define S_FATALPERR 4
38181 #define V_FATALPERR(x) ((x) << S_FATALPERR)
38182 #define F_FATALPERR V_FATALPERR(1U)
38184 #define S_INVALIDACCESS 3
38185 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
38186 #define F_INVALIDACCESS V_INVALIDACCESS(1U)
38188 #define S_TIMEOUT 2
38189 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
38190 #define F_TIMEOUT V_TIMEOUT(1U)
38193 #define V_PLERR(x) ((x) << S_PLERR)
38194 #define F_PLERR V_PLERR(1U)
38196 #define S_PERRVFID 0
38197 #define V_PERRVFID(x) ((x) << S_PERRVFID)
38198 #define F_PERRVFID V_PERRVFID(1U)
38200 #define S_PL_BUSPERR 6
38201 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
38202 #define F_PL_BUSPERR V_PL_BUSPERR(1U)
38204 #define A_PL_PL_INT_ENABLE 0x19434
38205 #define A_PL_PL_PERR_ENABLE 0x19438
38206 #define A_PL_REV 0x1943c
38210 #define V_REV(x) ((x) << S_REV)
38211 #define G_REV(x) (((x) >> S_REV) & M_REV)
38213 #define A_PL_PCIE_LINK 0x19440
38215 #define S_LN0_AESTAT 26
38216 #define M_LN0_AESTAT 0x7U
38217 #define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
38218 #define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
38220 #define S_LN0_AECMD 23
38221 #define M_LN0_AECMD 0x7U
38222 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
38223 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
38225 #define S_T5_STATECFGINITF 16
38226 #define M_T5_STATECFGINITF 0x7fU
38227 #define V_T5_STATECFGINITF(x) ((x) << S_T5_STATECFGINITF)
38228 #define G_T5_STATECFGINITF(x) (((x) >> S_T5_STATECFGINITF) & M_T5_STATECFGINITF)
38230 #define S_T5_STATECFGINIT 12
38231 #define M_T5_STATECFGINIT 0xfU
38232 #define V_T5_STATECFGINIT(x) ((x) << S_T5_STATECFGINIT)
38233 #define G_T5_STATECFGINIT(x) (((x) >> S_T5_STATECFGINIT) & M_T5_STATECFGINIT)
38235 #define S_PCIE_SPEED 8
38236 #define M_PCIE_SPEED 0x3U
38237 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
38238 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
38240 #define S_T5_PERSTTIMEOUT 7
38241 #define V_T5_PERSTTIMEOUT(x) ((x) << S_T5_PERSTTIMEOUT)
38242 #define F_T5_PERSTTIMEOUT V_T5_PERSTTIMEOUT(1U)
38244 #define S_T5_LTSSMENABLE 6
38245 #define V_T5_LTSSMENABLE(x) ((x) << S_T5_LTSSMENABLE)
38246 #define F_T5_LTSSMENABLE V_T5_LTSSMENABLE(1U)
38249 #define M_LTSSM 0x3fU
38250 #define V_LTSSM(x) ((x) << S_LTSSM)
38251 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
38253 #define S_T6_LN0_AESTAT 27
38254 #define M_T6_LN0_AESTAT 0x7U
38255 #define V_T6_LN0_AESTAT(x) ((x) << S_T6_LN0_AESTAT)
38256 #define G_T6_LN0_AESTAT(x) (((x) >> S_T6_LN0_AESTAT) & M_T6_LN0_AESTAT)
38258 #define S_T6_LN0_AECMD 24
38259 #define M_T6_LN0_AECMD 0x7U
38260 #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
38261 #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
38263 #define S_T6_STATECFGINITF 16
38264 #define M_T6_STATECFGINITF 0xffU
38265 #define V_T6_STATECFGINITF(x) ((x) << S_T6_STATECFGINITF)
38266 #define G_T6_STATECFGINITF(x) (((x) >> S_T6_STATECFGINITF) & M_T6_STATECFGINITF)
38268 #define S_T6_STATECFGINIT 12
38269 #define M_T6_STATECFGINIT 0xfU
38270 #define V_T6_STATECFGINIT(x) ((x) << S_T6_STATECFGINIT)
38271 #define G_T6_STATECFGINIT(x) (((x) >> S_T6_STATECFGINIT) & M_T6_STATECFGINIT)
38273 #define S_PHY_STATUS 10
38274 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
38275 #define F_PHY_STATUS V_PHY_STATUS(1U)
38277 #define S_SPEED_PL 8
38278 #define M_SPEED_PL 0x3U
38279 #define V_SPEED_PL(x) ((x) << S_SPEED_PL)
38280 #define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL)
38282 #define S_PERSTTIMEOUT_PL 7
38283 #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
38284 #define F_PERSTTIMEOUT_PL V_PERSTTIMEOUT_PL(1U)
38286 #define S_T6_LTSSMENABLE 6
38287 #define V_T6_LTSSMENABLE(x) ((x) << S_T6_LTSSMENABLE)
38288 #define F_T6_LTSSMENABLE V_T6_LTSSMENABLE(1U)
38290 #define A_PL_PCIE_CTL_STAT 0x19444
38292 #define S_PCIE_STATUS 16
38293 #define M_PCIE_STATUS 0xffffU
38294 #define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
38295 #define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
38297 #define S_PCIE_CONTROL 0
38298 #define M_PCIE_CONTROL 0xffffU
38299 #define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
38300 #define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
38302 #define A_PL_SEMAPHORE_CTL 0x1944c
38304 #define S_LOCKSTATUS 16
38305 #define M_LOCKSTATUS 0xffU
38306 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
38307 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
38309 #define S_OWNEROVERRIDE 8
38310 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
38311 #define F_OWNEROVERRIDE V_OWNEROVERRIDE(1U)
38313 #define S_ENABLEPF 0
38314 #define M_ENABLEPF 0xffU
38315 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
38316 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
38318 #define A_PL_SEMAPHORE_LOCK 0x19450
38320 #define S_SEMLOCK 31
38321 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
38322 #define F_SEMLOCK V_SEMLOCK(1U)
38324 #define S_SEMSRCBUS 3
38325 #define M_SEMSRCBUS 0x3U
38326 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
38327 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
38329 #define S_SEMSRCPF 0
38330 #define M_SEMSRCPF 0x7U
38331 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
38332 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
38334 #define A_PL_PF_ENABLE 0x19470
38336 #define S_PF_ENABLE 0
38337 #define M_PF_ENABLE 0xffU
38338 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
38339 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
38341 #define A_PL_PORTX_MAP 0x19474
38344 #define M_MAP7 0x7U
38345 #define V_MAP7(x) ((x) << S_MAP7)
38346 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
38349 #define M_MAP6 0x7U
38350 #define V_MAP6(x) ((x) << S_MAP6)
38351 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
38354 #define M_MAP5 0x7U
38355 #define V_MAP5(x) ((x) << S_MAP5)
38356 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
38359 #define M_MAP4 0x7U
38360 #define V_MAP4(x) ((x) << S_MAP4)
38361 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
38364 #define M_MAP3 0x7U
38365 #define V_MAP3(x) ((x) << S_MAP3)
38366 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
38369 #define M_MAP2 0x7U
38370 #define V_MAP2(x) ((x) << S_MAP2)
38371 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
38374 #define M_MAP1 0x7U
38375 #define V_MAP1(x) ((x) << S_MAP1)
38376 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
38379 #define M_MAP0 0x7U
38380 #define V_MAP0(x) ((x) << S_MAP0)
38381 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
38383 #define A_PL_VF_SLICE_L 0x19490
38385 #define S_LIMITADDR 16
38386 #define M_LIMITADDR 0x3ffU
38387 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
38388 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
38390 #define S_SLICEBASEADDR 0
38391 #define M_SLICEBASEADDR 0x3ffU
38392 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
38393 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
38395 #define A_PL_VF_SLICE_H 0x19494
38397 #define S_MODINDX 16
38398 #define M_MODINDX 0x7U
38399 #define V_MODINDX(x) ((x) << S_MODINDX)
38400 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
38402 #define S_MODOFFSET 0
38403 #define M_MODOFFSET 0x3ffU
38404 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
38405 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
38407 #define A_PL_FLR_VF_STATUS 0x194d0
38408 #define A_PL_FLR_PF_STATUS 0x194e0
38411 #define M_FLR_PF 0xffU
38412 #define V_FLR_PF(x) ((x) << S_FLR_PF)
38413 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
38415 #define A_PL_TIMEOUT_CTL 0x194f0
38417 #define S_PL_TIMEOUT 0
38418 #define M_PL_TIMEOUT 0xffffU
38419 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
38420 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
38422 #define S_PERRCAPTURE 16
38423 #define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
38424 #define F_PERRCAPTURE V_PERRCAPTURE(1U)
38426 #define A_PL_TIMEOUT_STATUS0 0x194f4
38428 #define S_PL_TOADDR 2
38429 #define M_PL_TOADDR 0xfffffffU
38430 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
38431 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
38433 #define A_PL_TIMEOUT_STATUS1 0x194f8
38435 #define S_PL_TOVALID 31
38436 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
38437 #define F_PL_TOVALID V_PL_TOVALID(1U)
38440 #define V_WRITE(x) ((x) << S_WRITE)
38441 #define F_WRITE V_WRITE(1U)
38443 #define S_PL_TOBUS 20
38444 #define M_PL_TOBUS 0x3U
38445 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
38446 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
38449 #define V_RGN(x) ((x) << S_RGN)
38450 #define F_RGN V_RGN(1U)
38452 #define S_PL_TOPF 16
38453 #define M_PL_TOPF 0x7U
38454 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
38455 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
38457 #define S_PL_TORID 0
38458 #define M_PL_TORID 0xffffU
38459 #define V_PL_TORID(x) ((x) << S_PL_TORID)
38460 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
38462 #define S_VALIDPERR 30
38463 #define V_VALIDPERR(x) ((x) << S_VALIDPERR)
38464 #define F_VALIDPERR V_VALIDPERR(1U)
38466 #define S_PL_TOVFID 0
38467 #define M_PL_TOVFID 0xffU
38468 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
38469 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
38471 #define S_T6_PL_TOVFID 0
38472 #define M_T6_PL_TOVFID 0x1ffU
38473 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
38474 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
38476 #define A_PL_VFID_MAP 0x19800
38478 #define S_VFID_VLD 7
38479 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
38480 #define F_VFID_VLD V_VFID_VLD(1U)
38482 /* registers for module LE */
38483 #define LE_BASE_ADDR 0x19c00
38485 #define A_LE_BUF_CONFIG 0x19c00
38486 #define A_LE_DB_ID 0x19c00
38487 #define A_LE_DB_CONFIG 0x19c04
38489 #define S_TCAMCMDOVLAPEN 21
38490 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
38491 #define F_TCAMCMDOVLAPEN V_TCAMCMDOVLAPEN(1U)
38493 #define S_HASHEN 20
38494 #define V_HASHEN(x) ((x) << S_HASHEN)
38495 #define F_HASHEN V_HASHEN(1U)
38497 #define S_ASBOTHSRCHEN 18
38498 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
38499 #define F_ASBOTHSRCHEN V_ASBOTHSRCHEN(1U)
38501 #define S_ASLIPCOMPEN 17
38502 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
38503 #define F_ASLIPCOMPEN V_ASLIPCOMPEN(1U)
38506 #define V_BUILD(x) ((x) << S_BUILD)
38507 #define F_BUILD V_BUILD(1U)
38509 #define S_FILTEREN 11
38510 #define V_FILTEREN(x) ((x) << S_FILTEREN)
38511 #define F_FILTEREN V_FILTEREN(1U)
38513 #define S_SYNMODE 7
38514 #define M_SYNMODE 0x3U
38515 #define V_SYNMODE(x) ((x) << S_SYNMODE)
38516 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
38518 #define S_LEBUSEN 5
38519 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
38520 #define F_LEBUSEN V_LEBUSEN(1U)
38522 #define S_ELOOKDUMEN 4
38523 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
38524 #define F_ELOOKDUMEN V_ELOOKDUMEN(1U)
38526 #define S_IPV4ONLYEN 3
38527 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
38528 #define F_IPV4ONLYEN V_IPV4ONLYEN(1U)
38530 #define S_MOSTCMDOEN 2
38531 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
38532 #define F_MOSTCMDOEN V_MOSTCMDOEN(1U)
38534 #define S_DELACTSYNOEN 1
38535 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
38536 #define F_DELACTSYNOEN V_DELACTSYNOEN(1U)
38538 #define S_CMDOVERLAPDIS 0
38539 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
38540 #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U)
38542 #define S_MASKCMDOLAPDIS 26
38543 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
38544 #define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U)
38546 #define S_IPV4HASHSIZEEN 25
38547 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
38548 #define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U)
38550 #define S_PROTOCOLMASKEN 24
38551 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
38552 #define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U)
38554 #define S_TUPLESIZEEN 23
38555 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
38556 #define F_TUPLESIZEEN V_TUPLESIZEEN(1U)
38558 #define S_SRVRSRAMEN 22
38559 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
38560 #define F_SRVRSRAMEN V_SRVRSRAMEN(1U)
38562 #define S_ASBOTHSRCHENPR 19
38563 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
38564 #define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U)
38566 #define S_POCLIPTID0 15
38567 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
38568 #define F_POCLIPTID0 V_POCLIPTID0(1U)
38570 #define S_TCAMARBOFF 14
38571 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
38572 #define F_TCAMARBOFF V_TCAMARBOFF(1U)
38574 #define S_ACCNTFULLEN 13
38575 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
38576 #define F_ACCNTFULLEN V_ACCNTFULLEN(1U)
38578 #define S_FILTERRWNOCLIP 12
38579 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
38580 #define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U)
38582 #define S_CRCHASH 10
38583 #define V_CRCHASH(x) ((x) << S_CRCHASH)
38584 #define F_CRCHASH V_CRCHASH(1U)
38586 #define S_COMPTID 9
38587 #define V_COMPTID(x) ((x) << S_COMPTID)
38588 #define F_COMPTID V_COMPTID(1U)
38590 #define S_SINGLETHREAD 6
38591 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
38592 #define F_SINGLETHREAD V_SINGLETHREAD(1U)
38594 #define S_CHK_FUL_TUP_ZERO 27
38595 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
38596 #define F_CHK_FUL_TUP_ZERO V_CHK_FUL_TUP_ZERO(1U)
38598 #define S_PRI_HASH 26
38599 #define V_PRI_HASH(x) ((x) << S_PRI_HASH)
38600 #define F_PRI_HASH V_PRI_HASH(1U)
38602 #define S_EXTN_HASH_IPV4 25
38603 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
38604 #define F_EXTN_HASH_IPV4 V_EXTN_HASH_IPV4(1U)
38606 #define S_ASLIPCOMPEN_IPV4 18
38607 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
38608 #define F_ASLIPCOMPEN_IPV4 V_ASLIPCOMPEN_IPV4(1U)
38610 #define S_IGNR_TUP_ZERO 9
38611 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
38612 #define F_IGNR_TUP_ZERO V_IGNR_TUP_ZERO(1U)
38614 #define S_IGNR_LIP_ZERO 8
38615 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
38616 #define F_IGNR_LIP_ZERO V_IGNR_LIP_ZERO(1U)
38618 #define S_CLCAM_INIT_BUSY 7
38619 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
38620 #define F_CLCAM_INIT_BUSY V_CLCAM_INIT_BUSY(1U)
38622 #define S_CLCAM_INIT 6
38623 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
38624 #define F_CLCAM_INIT V_CLCAM_INIT(1U)
38626 #define S_MTCAM_INIT_BUSY 5
38627 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
38628 #define F_MTCAM_INIT_BUSY V_MTCAM_INIT_BUSY(1U)
38630 #define S_MTCAM_INIT 4
38631 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
38632 #define F_MTCAM_INIT V_MTCAM_INIT(1U)
38634 #define S_REGION_EN 0
38635 #define M_REGION_EN 0xfU
38636 #define V_REGION_EN(x) ((x) << S_REGION_EN)
38637 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
38639 #define A_LE_MISC 0x19c08
38641 #define S_CMPUNVAIL 0
38642 #define M_CMPUNVAIL 0xfU
38643 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
38644 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
38646 #define S_SRAMDEEPSLEEP_STAT 11
38647 #define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
38648 #define F_SRAMDEEPSLEEP_STAT V_SRAMDEEPSLEEP_STAT(1U)
38650 #define S_TCAMDEEPSLEEP1_STAT 10
38651 #define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
38652 #define F_TCAMDEEPSLEEP1_STAT V_TCAMDEEPSLEEP1_STAT(1U)
38654 #define S_TCAMDEEPSLEEP0_STAT 9
38655 #define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
38656 #define F_TCAMDEEPSLEEP0_STAT V_TCAMDEEPSLEEP0_STAT(1U)
38658 #define S_SRAMDEEPSLEEP 8
38659 #define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
38660 #define F_SRAMDEEPSLEEP V_SRAMDEEPSLEEP(1U)
38662 #define S_TCAMDEEPSLEEP1 7
38663 #define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
38664 #define F_TCAMDEEPSLEEP1 V_TCAMDEEPSLEEP1(1U)
38666 #define S_TCAMDEEPSLEEP0 6
38667 #define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
38668 #define F_TCAMDEEPSLEEP0 V_TCAMDEEPSLEEP0(1U)
38670 #define S_SRVRAMCLKOFF 5
38671 #define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
38672 #define F_SRVRAMCLKOFF V_SRVRAMCLKOFF(1U)
38674 #define S_HASHCLKOFF 4
38675 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
38676 #define F_HASHCLKOFF V_HASHCLKOFF(1U)
38678 #define A_LE_DB_EXEC_CTRL 0x19c08
38680 #define S_TPDB_IF_PAUSE_ACK 10
38681 #define V_TPDB_IF_PAUSE_ACK(x) ((x) << S_TPDB_IF_PAUSE_ACK)
38682 #define F_TPDB_IF_PAUSE_ACK V_TPDB_IF_PAUSE_ACK(1U)
38684 #define S_TPDB_IF_PAUSE_REQ 9
38685 #define V_TPDB_IF_PAUSE_REQ(x) ((x) << S_TPDB_IF_PAUSE_REQ)
38686 #define F_TPDB_IF_PAUSE_REQ V_TPDB_IF_PAUSE_REQ(1U)
38688 #define S_ERRSTOP_EN 8
38689 #define V_ERRSTOP_EN(x) ((x) << S_ERRSTOP_EN)
38690 #define F_ERRSTOP_EN V_ERRSTOP_EN(1U)
38692 #define S_CMDLIMIT 0
38693 #define M_CMDLIMIT 0xffU
38694 #define V_CMDLIMIT(x) ((x) << S_CMDLIMIT)
38695 #define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT)
38697 #define A_LE_DB_PS_CTRL 0x19c0c
38699 #define S_CLTCAMDEEPSLEEP_STAT 10
38700 #define V_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_CLTCAMDEEPSLEEP_STAT)
38701 #define F_CLTCAMDEEPSLEEP_STAT V_CLTCAMDEEPSLEEP_STAT(1U)
38703 #define S_TCAMDEEPSLEEP_STAT 9
38704 #define V_TCAMDEEPSLEEP_STAT(x) ((x) << S_TCAMDEEPSLEEP_STAT)
38705 #define F_TCAMDEEPSLEEP_STAT V_TCAMDEEPSLEEP_STAT(1U)
38707 #define S_CLTCAMDEEPSLEEP 7
38708 #define V_CLTCAMDEEPSLEEP(x) ((x) << S_CLTCAMDEEPSLEEP)
38709 #define F_CLTCAMDEEPSLEEP V_CLTCAMDEEPSLEEP(1U)
38711 #define S_TCAMDEEPSLEEP 6
38712 #define V_TCAMDEEPSLEEP(x) ((x) << S_TCAMDEEPSLEEP)
38713 #define F_TCAMDEEPSLEEP V_TCAMDEEPSLEEP(1U)
38715 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
38718 #define M_RTINDX 0x3fU
38719 #define V_RTINDX(x) ((x) << S_RTINDX)
38720 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
38722 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
38725 #define M_ATINDX 0xfffffU
38726 #define V_ATINDX(x) ((x) << S_ATINDX)
38727 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
38729 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
38732 #define M_FTINDX 0x3fU
38733 #define V_FTINDX(x) ((x) << S_FTINDX)
38734 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
38736 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
38738 #define S_NFTINDX 0
38739 #define M_NFTINDX 0xfffffU
38740 #define V_NFTINDX(x) ((x) << S_NFTINDX)
38741 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
38743 #define A_LE_DB_SERVER_INDEX 0x19c18
38746 #define M_SRINDX 0x3fU
38747 #define V_SRINDX(x) ((x) << S_SRINDX)
38748 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
38750 #define A_LE_DB_SRVR_START_INDEX 0x19c18
38752 #define S_T6_SRINDX 0
38753 #define M_T6_SRINDX 0xfffffU
38754 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
38755 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
38757 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
38759 #define S_CLIPTINDX 7
38760 #define M_CLIPTINDX 0x3fU
38761 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
38762 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
38764 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
38766 #define S_HFTINDX 0
38767 #define M_HFTINDX 0xfffffU
38768 #define V_HFTINDX(x) ((x) << S_HFTINDX)
38769 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
38771 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
38773 #define S_ACTCNTIPV4 0
38774 #define M_ACTCNTIPV4 0xfffffU
38775 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
38776 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
38778 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
38780 #define S_ACTCNTIPV6 0
38781 #define M_ACTCNTIPV6 0xfffffU
38782 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
38783 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
38785 #define A_LE_DB_HASH_CONFIG 0x19c28
38787 #define S_HASHTIDSIZE 16
38788 #define M_HASHTIDSIZE 0x3fU
38789 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
38790 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
38792 #define S_HASHSIZE 0
38793 #define M_HASHSIZE 0x3fU
38794 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
38795 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
38797 #define S_NUMHASHBKT 20
38798 #define M_NUMHASHBKT 0x1fU
38799 #define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT)
38800 #define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT)
38802 #define S_HASHTBLSIZE 3
38803 #define M_HASHTBLSIZE 0x1ffffU
38804 #define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE)
38805 #define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE)
38807 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
38808 #define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
38810 #define S_MIN_ATCAM_ENTS 0
38811 #define M_MIN_ATCAM_ENTS 0xfffffU
38812 #define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS)
38813 #define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS)
38815 #define A_LE_DB_HASH_TID_BASE 0x19c30
38816 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
38818 #define S_HASHTBLADDR 4
38819 #define M_HASHTBLADDR 0xfffffffU
38820 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
38821 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
38823 #define A_LE_DB_SIZE 0x19c34
38824 #define A_LE_TCAM_SIZE 0x19c34
38826 #define S_TCAM_SIZE 0
38827 #define M_TCAM_SIZE 0x3U
38828 #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
38829 #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
38831 #define A_LE_DB_INT_ENABLE 0x19c38
38833 #define S_MSGSEL 27
38834 #define M_MSGSEL 0x1fU
38835 #define V_MSGSEL(x) ((x) << S_MSGSEL)
38836 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
38838 #define S_REQQPARERR 16
38839 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
38840 #define F_REQQPARERR V_REQQPARERR(1U)
38842 #define S_UNKNOWNCMD 15
38843 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
38844 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
38846 #define S_DROPFILTERHIT 13
38847 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
38848 #define F_DROPFILTERHIT V_DROPFILTERHIT(1U)
38850 #define S_FILTERHIT 12
38851 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
38852 #define F_FILTERHIT V_FILTERHIT(1U)
38854 #define S_SYNCOOKIEOFF 11
38855 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
38856 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U)
38858 #define S_SYNCOOKIEBAD 10
38859 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
38860 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U)
38862 #define S_SYNCOOKIE 9
38863 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
38864 #define F_SYNCOOKIE V_SYNCOOKIE(1U)
38866 #define S_NFASRCHFAIL 8
38867 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
38868 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
38870 #define S_ACTRGNFULL 7
38871 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
38872 #define F_ACTRGNFULL V_ACTRGNFULL(1U)
38874 #define S_PARITYERR 6
38875 #define V_PARITYERR(x) ((x) << S_PARITYERR)
38876 #define F_PARITYERR V_PARITYERR(1U)
38878 #define S_LIPMISS 5
38879 #define V_LIPMISS(x) ((x) << S_LIPMISS)
38880 #define F_LIPMISS V_LIPMISS(1U)
38883 #define V_LIP0(x) ((x) << S_LIP0)
38884 #define F_LIP0 V_LIP0(1U)
38887 #define V_MISS(x) ((x) << S_MISS)
38888 #define F_MISS V_MISS(1U)
38890 #define S_ROUTINGHIT 2
38891 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
38892 #define F_ROUTINGHIT V_ROUTINGHIT(1U)
38894 #define S_ACTIVEHIT 1
38895 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
38896 #define F_ACTIVEHIT V_ACTIVEHIT(1U)
38898 #define S_SERVERHIT 0
38899 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
38900 #define F_SERVERHIT V_SERVERHIT(1U)
38902 #define S_ACTCNTIPV6TZERO 21
38903 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
38904 #define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U)
38906 #define S_ACTCNTIPV4TZERO 20
38907 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
38908 #define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U)
38910 #define S_ACTCNTIPV6ZERO 19
38911 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
38912 #define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U)
38914 #define S_ACTCNTIPV4ZERO 18
38915 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
38916 #define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U)
38918 #define S_MARSPPARERR 17
38919 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
38920 #define F_MARSPPARERR V_MARSPPARERR(1U)
38922 #define S_VFPARERR 14
38923 #define V_VFPARERR(x) ((x) << S_VFPARERR)
38924 #define F_VFPARERR V_VFPARERR(1U)
38926 #define S_CLIPSUBERR 29
38927 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
38928 #define F_CLIPSUBERR V_CLIPSUBERR(1U)
38930 #define S_CLCAMFIFOERR 28
38931 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
38932 #define F_CLCAMFIFOERR V_CLCAMFIFOERR(1U)
38934 #define S_HASHTBLMEMCRCERR 27
38935 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
38936 #define F_HASHTBLMEMCRCERR V_HASHTBLMEMCRCERR(1U)
38938 #define S_CTCAMINVLDENT 26
38939 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
38940 #define F_CTCAMINVLDENT V_CTCAMINVLDENT(1U)
38942 #define S_TCAMINVLDENT 25
38943 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
38944 #define F_TCAMINVLDENT V_TCAMINVLDENT(1U)
38946 #define S_TOTCNTERR 24
38947 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
38948 #define F_TOTCNTERR V_TOTCNTERR(1U)
38950 #define S_CMDPRSRINTERR 23
38951 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
38952 #define F_CMDPRSRINTERR V_CMDPRSRINTERR(1U)
38954 #define S_CMDTIDERR 22
38955 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
38956 #define F_CMDTIDERR V_CMDTIDERR(1U)
38958 #define S_T6_ACTRGNFULL 21
38959 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
38960 #define F_T6_ACTRGNFULL V_T6_ACTRGNFULL(1U)
38962 #define S_T6_ACTCNTIPV6TZERO 20
38963 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
38964 #define F_T6_ACTCNTIPV6TZERO V_T6_ACTCNTIPV6TZERO(1U)
38966 #define S_T6_ACTCNTIPV4TZERO 19
38967 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
38968 #define F_T6_ACTCNTIPV4TZERO V_T6_ACTCNTIPV4TZERO(1U)
38970 #define S_T6_ACTCNTIPV6ZERO 18
38971 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
38972 #define F_T6_ACTCNTIPV6ZERO V_T6_ACTCNTIPV6ZERO(1U)
38974 #define S_T6_ACTCNTIPV4ZERO 17
38975 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
38976 #define F_T6_ACTCNTIPV4ZERO V_T6_ACTCNTIPV4ZERO(1U)
38978 #define S_MAIFWRINTPERR 16
38979 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
38980 #define F_MAIFWRINTPERR V_MAIFWRINTPERR(1U)
38982 #define S_HASHTBLMEMACCERR 15
38983 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
38984 #define F_HASHTBLMEMACCERR V_HASHTBLMEMACCERR(1U)
38986 #define S_TCAMCRCERR 14
38987 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
38988 #define F_TCAMCRCERR V_TCAMCRCERR(1U)
38990 #define S_TCAMINTPERR 13
38991 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
38992 #define F_TCAMINTPERR V_TCAMINTPERR(1U)
38994 #define S_VFSRAMPERR 12
38995 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
38996 #define F_VFSRAMPERR V_VFSRAMPERR(1U)
38998 #define S_SRVSRAMPERR 11
38999 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
39000 #define F_SRVSRAMPERR V_SRVSRAMPERR(1U)
39002 #define S_SSRAMINTPERR 10
39003 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
39004 #define F_SSRAMINTPERR V_SSRAMINTPERR(1U)
39006 #define S_CLCAMINTPERR 9
39007 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
39008 #define F_CLCAMINTPERR V_CLCAMINTPERR(1U)
39010 #define S_CLCAMCRCPARERR 8
39011 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
39012 #define F_CLCAMCRCPARERR V_CLCAMCRCPARERR(1U)
39014 #define S_HASHTBLACCFAIL 7
39015 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
39016 #define F_HASHTBLACCFAIL V_HASHTBLACCFAIL(1U)
39018 #define S_TCAMACCFAIL 6
39019 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
39020 #define F_TCAMACCFAIL V_TCAMACCFAIL(1U)
39022 #define S_SRVSRAMACCFAIL 5
39023 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
39024 #define F_SRVSRAMACCFAIL V_SRVSRAMACCFAIL(1U)
39026 #define S_CLIPTCAMACCFAIL 4
39027 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
39028 #define F_CLIPTCAMACCFAIL V_CLIPTCAMACCFAIL(1U)
39030 #define S_T6_UNKNOWNCMD 3
39031 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
39032 #define F_T6_UNKNOWNCMD V_T6_UNKNOWNCMD(1U)
39034 #define S_T6_LIP0 2
39035 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
39036 #define F_T6_LIP0 V_T6_LIP0(1U)
39038 #define S_T6_LIPMISS 1
39039 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
39040 #define F_T6_LIPMISS V_T6_LIPMISS(1U)
39042 #define S_PIPELINEERR 0
39043 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
39044 #define F_PIPELINEERR V_PIPELINEERR(1U)
39046 #define A_LE_DB_INT_CAUSE 0x19c3c
39048 #define S_T6_ACTRGNFULL 21
39049 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
39050 #define F_T6_ACTRGNFULL V_T6_ACTRGNFULL(1U)
39052 #define S_T6_ACTCNTIPV6TZERO 20
39053 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
39054 #define F_T6_ACTCNTIPV6TZERO V_T6_ACTCNTIPV6TZERO(1U)
39056 #define S_T6_ACTCNTIPV4TZERO 19
39057 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
39058 #define F_T6_ACTCNTIPV4TZERO V_T6_ACTCNTIPV4TZERO(1U)
39060 #define S_T6_ACTCNTIPV6ZERO 18
39061 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
39062 #define F_T6_ACTCNTIPV6ZERO V_T6_ACTCNTIPV6ZERO(1U)
39064 #define S_T6_ACTCNTIPV4ZERO 17
39065 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
39066 #define F_T6_ACTCNTIPV4ZERO V_T6_ACTCNTIPV4ZERO(1U)
39068 #define S_T6_UNKNOWNCMD 3
39069 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
39070 #define F_T6_UNKNOWNCMD V_T6_UNKNOWNCMD(1U)
39072 #define S_T6_LIP0 2
39073 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
39074 #define F_T6_LIP0 V_T6_LIP0(1U)
39076 #define S_T6_LIPMISS 1
39077 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
39078 #define F_T6_LIPMISS V_T6_LIPMISS(1U)
39080 #define A_LE_DB_INT_TID 0x19c40
39083 #define M_INTTID 0xfffffU
39084 #define V_INTTID(x) ((x) << S_INTTID)
39085 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
39087 #define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
39089 #define S_CMD_CMP_MASK 20
39090 #define M_CMD_CMP_MASK 0x1fU
39091 #define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK)
39092 #define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK)
39094 #define S_TID_CMP_MASK 0
39095 #define M_TID_CMP_MASK 0xfffffU
39096 #define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK)
39097 #define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK)
39099 #define A_LE_DB_INT_PTID 0x19c44
39101 #define S_INTPTID 0
39102 #define M_INTPTID 0xfffffU
39103 #define V_INTPTID(x) ((x) << S_INTPTID)
39104 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
39106 #define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
39108 #define S_CMD_CMP 20
39109 #define M_CMD_CMP 0x1fU
39110 #define V_CMD_CMP(x) ((x) << S_CMD_CMP)
39111 #define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP)
39113 #define S_TID_CMP 0
39114 #define M_TID_CMP 0xfffffU
39115 #define V_TID_CMP(x) ((x) << S_TID_CMP)
39116 #define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP)
39118 #define A_LE_DB_INT_INDEX 0x19c48
39120 #define S_INTINDEX 0
39121 #define M_INTINDEX 0xfffffU
39122 #define V_INTINDEX(x) ((x) << S_INTINDEX)
39123 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
39125 #define A_LE_DB_ERR_CMD_TID 0x19c48
39127 #define S_ERR_CID 22
39128 #define M_ERR_CID 0xffU
39129 #define V_ERR_CID(x) ((x) << S_ERR_CID)
39130 #define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID)
39132 #define S_ERR_PROT 20
39133 #define M_ERR_PROT 0x3U
39134 #define V_ERR_PROT(x) ((x) << S_ERR_PROT)
39135 #define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT)
39137 #define S_ERR_TID 0
39138 #define M_ERR_TID 0xfffffU
39139 #define V_ERR_TID(x) ((x) << S_ERR_TID)
39140 #define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID)
39142 #define A_LE_DB_INT_CMD 0x19c4c
39145 #define M_INTCMD 0xfU
39146 #define V_INTCMD(x) ((x) << S_INTCMD)
39147 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
39149 #define A_LE_DB_MASK_IPV4 0x19c50
39150 #define A_LE_T5_DB_MASK_IPV4 0x19c50
39151 #define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
39152 #define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
39154 #define S_MAX_HASH_ENTS 0
39155 #define M_MAX_HASH_ENTS 0xfffffU
39156 #define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS)
39157 #define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS)
39159 #define A_LE_DB_RSP_CODE_0 0x19c74
39161 #define S_SUCCESS 25
39162 #define M_SUCCESS 0x1fU
39163 #define V_SUCCESS(x) ((x) << S_SUCCESS)
39164 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
39166 #define S_TCAM_ACTV_SUCC 20
39167 #define M_TCAM_ACTV_SUCC 0x1fU
39168 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
39169 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
39171 #define S_HASH_ACTV_SUCC 15
39172 #define M_HASH_ACTV_SUCC 0x1fU
39173 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
39174 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
39176 #define S_TCAM_SRVR_HIT 10
39177 #define M_TCAM_SRVR_HIT 0x1fU
39178 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
39179 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
39181 #define S_SRAM_SRVR_HIT 5
39182 #define M_SRAM_SRVR_HIT 0x1fU
39183 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
39184 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
39186 #define S_TCAM_ACTV_HIT 0
39187 #define M_TCAM_ACTV_HIT 0x1fU
39188 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
39189 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
39191 #define A_LE_DB_RSP_CODE_1 0x19c78
39193 #define S_HASH_ACTV_HIT 25
39194 #define M_HASH_ACTV_HIT 0x1fU
39195 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
39196 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
39198 #define S_T6_MISS 20
39199 #define M_T6_MISS 0x1fU
39200 #define V_T6_MISS(x) ((x) << S_T6_MISS)
39201 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
39203 #define S_NORM_FILT_HIT 15
39204 #define M_NORM_FILT_HIT 0x1fU
39205 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
39206 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
39208 #define S_HPRI_FILT_HIT 10
39209 #define M_HPRI_FILT_HIT 0x1fU
39210 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
39211 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
39213 #define S_ACTV_OPEN_ERR 5
39214 #define M_ACTV_OPEN_ERR 0x1fU
39215 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
39216 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
39218 #define S_ACTV_FULL_ERR 0
39219 #define M_ACTV_FULL_ERR 0x1fU
39220 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
39221 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
39223 #define A_LE_DB_RSP_CODE_2 0x19c7c
39225 #define S_SRCH_RGN_HIT 25
39226 #define M_SRCH_RGN_HIT 0x1fU
39227 #define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT)
39228 #define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT)
39230 #define S_CLIP_FAIL 20
39231 #define M_CLIP_FAIL 0x1fU
39232 #define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL)
39233 #define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL)
39235 #define S_LIP_ZERO_ERR 15
39236 #define M_LIP_ZERO_ERR 0x1fU
39237 #define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR)
39238 #define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR)
39240 #define S_UNKNOWN_CMD 10
39241 #define M_UNKNOWN_CMD 0x1fU
39242 #define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD)
39243 #define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD)
39245 #define S_CMD_TID_ERR 5
39246 #define M_CMD_TID_ERR 0x1fU
39247 #define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR)
39248 #define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR)
39250 #define S_INTERNAL_ERR 0
39251 #define M_INTERNAL_ERR 0x1fU
39252 #define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR)
39253 #define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR)
39255 #define A_LE_DB_RSP_CODE_3 0x19c80
39257 #define S_SRAM_SRVR_HIT_ACTF 25
39258 #define M_SRAM_SRVR_HIT_ACTF 0x1fU
39259 #define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF)
39260 #define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF)
39262 #define S_TCAM_SRVR_HIT_ACTF 20
39263 #define M_TCAM_SRVR_HIT_ACTF 0x1fU
39264 #define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF)
39265 #define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF)
39267 #define S_INVLDRD 15
39268 #define M_INVLDRD 0x1fU
39269 #define V_INVLDRD(x) ((x) << S_INVLDRD)
39270 #define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD)
39272 #define S_TUPLZERO 10
39273 #define M_TUPLZERO 0x1fU
39274 #define V_TUPLZERO(x) ((x) << S_TUPLZERO)
39275 #define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO)
39277 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
39278 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
39279 #define A_LE_ACT_CNT_THRSH 0x19c9c
39281 #define S_ACT_CNT_THRSH 0
39282 #define M_ACT_CNT_THRSH 0x1fffffU
39283 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
39284 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
39286 #define A_LE_DB_MASK_IPV6 0x19ca0
39287 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
39288 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
39290 #define S_T4_RSPCNT 16
39291 #define M_T4_RSPCNT 0xffffU
39292 #define V_T4_RSPCNT(x) ((x) << S_T4_RSPCNT)
39293 #define G_T4_RSPCNT(x) (((x) >> S_T4_RSPCNT) & M_T4_RSPCNT)
39295 #define S_T4_REQCNT 0
39296 #define M_T4_REQCNT 0xffffU
39297 #define V_T4_REQCNT(x) ((x) << S_T4_REQCNT)
39298 #define G_T4_REQCNT(x) (((x) >> S_T4_REQCNT) & M_T4_REQCNT)
39300 #define S_RSPCNTLE 16
39301 #define M_RSPCNTLE 0xffffU
39302 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
39303 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
39305 #define S_REQCNTLE 0
39306 #define M_REQCNTLE 0xffffU
39307 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
39308 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
39310 #define A_LE_DB_DBGI_CONFIG 0x19cf0
39312 #define S_DBGICMDPERR 31
39313 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
39314 #define F_DBGICMDPERR V_DBGICMDPERR(1U)
39316 #define S_DBGICMDRANGE 22
39317 #define M_DBGICMDRANGE 0x7U
39318 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
39319 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
39321 #define S_DBGICMDMSKTYPE 21
39322 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
39323 #define F_DBGICMDMSKTYPE V_DBGICMDMSKTYPE(1U)
39325 #define S_DBGICMDSEARCH 20
39326 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
39327 #define F_DBGICMDSEARCH V_DBGICMDSEARCH(1U)
39329 #define S_DBGICMDREAD 19
39330 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
39331 #define F_DBGICMDREAD V_DBGICMDREAD(1U)
39333 #define S_DBGICMDLEARN 18
39334 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
39335 #define F_DBGICMDLEARN V_DBGICMDLEARN(1U)
39337 #define S_DBGICMDERASE 17
39338 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
39339 #define F_DBGICMDERASE V_DBGICMDERASE(1U)
39341 #define S_DBGICMDIPV6 16
39342 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
39343 #define F_DBGICMDIPV6 V_DBGICMDIPV6(1U)
39345 #define S_DBGICMDTYPE 13
39346 #define M_DBGICMDTYPE 0x7U
39347 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
39348 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
39350 #define S_DBGICMDACKERR 12
39351 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
39352 #define F_DBGICMDACKERR V_DBGICMDACKERR(1U)
39354 #define S_DBGICMDBUSY 3
39355 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
39356 #define F_DBGICMDBUSY V_DBGICMDBUSY(1U)
39358 #define S_DBGICMDSTRT 2
39359 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
39360 #define F_DBGICMDSTRT V_DBGICMDSTRT(1U)
39362 #define S_DBGICMDMODE 0
39363 #define M_DBGICMDMODE 0x3U
39364 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
39365 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
39367 #define S_DBGICMDMSKREAD 21
39368 #define V_DBGICMDMSKREAD(x) ((x) << S_DBGICMDMSKREAD)
39369 #define F_DBGICMDMSKREAD V_DBGICMDMSKREAD(1U)
39371 #define S_DBGICMDWRITE 17
39372 #define V_DBGICMDWRITE(x) ((x) << S_DBGICMDWRITE)
39373 #define F_DBGICMDWRITE V_DBGICMDWRITE(1U)
39375 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
39377 #define S_DBGICMD 20
39378 #define M_DBGICMD 0xfU
39379 #define V_DBGICMD(x) ((x) << S_DBGICMD)
39380 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
39382 #define S_DBGITINDEX 0
39383 #define M_DBGITINDEX 0xfffffU
39384 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
39385 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
39387 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
39389 #define S_DBGITID 0
39390 #define M_DBGITID 0xfffffU
39391 #define V_DBGITID(x) ((x) << S_DBGITID)
39392 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
39394 #define A_LE_PERR_ENABLE 0x19cf8
39396 #define S_REQQUEUE 1
39397 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
39398 #define F_REQQUEUE V_REQQUEUE(1U)
39401 #define V_TCAM(x) ((x) << S_TCAM)
39402 #define F_TCAM V_TCAM(1U)
39404 #define S_MARSPPARERRLE 17
39405 #define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
39406 #define F_MARSPPARERRLE V_MARSPPARERRLE(1U)
39408 #define S_REQQUEUELE 16
39409 #define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
39410 #define F_REQQUEUELE V_REQQUEUELE(1U)
39412 #define S_VFPARERRLE 14
39413 #define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
39414 #define F_VFPARERRLE V_VFPARERRLE(1U)
39417 #define V_TCAMLE(x) ((x) << S_TCAMLE)
39418 #define F_TCAMLE V_TCAMLE(1U)
39420 #define S_BKCHKPERIOD 22
39421 #define M_BKCHKPERIOD 0x3ffU
39422 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
39423 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
39425 #define S_TCAMBKCHKEN 21
39426 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
39427 #define F_TCAMBKCHKEN V_TCAMBKCHKEN(1U)
39429 #define S_T6_CLCAMFIFOERR 2
39430 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
39431 #define F_T6_CLCAMFIFOERR V_T6_CLCAMFIFOERR(1U)
39433 #define S_T6_HASHTBLMEMCRCERR 1
39434 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
39435 #define F_T6_HASHTBLMEMCRCERR V_T6_HASHTBLMEMCRCERR(1U)
39437 #define A_LE_SPARE 0x19cfc
39438 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
39439 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
39440 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
39442 #define S_DBGIRSPINDEX 12
39443 #define M_DBGIRSPINDEX 0xfffffU
39444 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
39445 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
39447 #define S_DBGIRSPMSG 8
39448 #define M_DBGIRSPMSG 0xfU
39449 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
39450 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
39452 #define S_DBGIRSPMSGVLD 7
39453 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
39454 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U)
39456 #define S_DBGIRSPMHIT 2
39457 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
39458 #define F_DBGIRSPMHIT V_DBGIRSPMHIT(1U)
39460 #define S_DBGIRSPHIT 1
39461 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
39462 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U)
39464 #define S_DBGIRSPVALID 0
39465 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
39466 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
39468 #define S_DBGIRSPTID 12
39469 #define M_DBGIRSPTID 0xfffffU
39470 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
39471 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
39473 #define S_DBGIRSPLEARN 2
39474 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
39475 #define F_DBGIRSPLEARN V_DBGIRSPLEARN(1U)
39477 #define A_LE_DBG_SEL 0x19d98
39478 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
39479 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
39481 #define S_LASTCMDB 16
39482 #define M_LASTCMDB 0x7ffU
39483 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
39484 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
39486 #define S_LASTCMDA 0
39487 #define M_LASTCMDA 0x7ffU
39488 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
39489 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
39491 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
39493 #define S_DROPFILTEREN 31
39494 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
39495 #define F_DROPFILTEREN V_DROPFILTEREN(1U)
39497 #define S_DROPFILTERCLEAR 17
39498 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
39499 #define F_DROPFILTERCLEAR V_DROPFILTERCLEAR(1U)
39501 #define S_DROPFILTERSET 16
39502 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
39503 #define F_DROPFILTERSET V_DROPFILTERSET(1U)
39505 #define S_DROPFILTERFIDX 0
39506 #define M_DROPFILTERFIDX 0x1fffU
39507 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
39508 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
39510 #define A_LE_DB_PTID_SVRBASE 0x19df0
39512 #define S_SVRBASE_ADDR 2
39513 #define M_SVRBASE_ADDR 0x3ffffU
39514 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
39515 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
39517 #define A_LE_DB_TCAM_TID_BASE 0x19df0
39519 #define S_TCAM_TID_BASE 0
39520 #define M_TCAM_TID_BASE 0xfffffU
39521 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
39522 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
39524 #define A_LE_DB_FTID_FLTRBASE 0x19df4
39526 #define S_FLTRBASE_ADDR 2
39527 #define M_FLTRBASE_ADDR 0x3ffffU
39528 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
39529 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
39531 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
39533 #define S_CLCAM_TID_BASE 0
39534 #define M_CLCAM_TID_BASE 0xfffffU
39535 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
39536 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
39538 #define A_LE_DB_TID_HASHBASE 0x19df8
39540 #define S_HASHBASE_ADDR 2
39541 #define M_HASHBASE_ADDR 0xfffffU
39542 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
39543 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
39545 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
39547 #define S_HASH_TID_BASE 0
39548 #define M_HASH_TID_BASE 0xfffffU
39549 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
39550 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
39552 #define A_LE_PERR_INJECT 0x19dfc
39554 #define S_LEMEMSEL 1
39555 #define M_LEMEMSEL 0x7U
39556 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
39557 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
39559 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
39561 #define S_SSRAM_TID_BASE 0
39562 #define M_SSRAM_TID_BASE 0xfffffU
39563 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
39564 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
39566 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
39567 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
39568 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
39569 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
39570 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
39571 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
39572 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
39573 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
39574 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
39575 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
39576 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
39577 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
39578 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
39579 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
39580 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
39581 #define A_LE_DEBUG_LA_CONFIG 0x19f20
39582 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
39583 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
39584 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
39585 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
39586 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
39587 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
39588 #define A_LE_SRVR_SRAM_INIT 0x19f34
39590 #define S_SRVRSRAMBASE 2
39591 #define M_SRVRSRAMBASE 0xfffffU
39592 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
39593 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
39595 #define S_SRVRINITBUSY 1
39596 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
39597 #define F_SRVRINITBUSY V_SRVRINITBUSY(1U)
39599 #define S_SRVRINIT 0
39600 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
39601 #define F_SRVRINIT V_SRVRINIT(1U)
39603 #define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
39605 #define S_PRI_HFILT 4
39606 #define V_PRI_HFILT(x) ((x) << S_PRI_HFILT)
39607 #define F_PRI_HFILT V_PRI_HFILT(1U)
39609 #define S_PRI_SRVR 3
39610 #define V_PRI_SRVR(x) ((x) << S_PRI_SRVR)
39611 #define F_PRI_SRVR V_PRI_SRVR(1U)
39613 #define S_PRI_FILT 2
39614 #define V_PRI_FILT(x) ((x) << S_PRI_FILT)
39615 #define F_PRI_FILT V_PRI_FILT(1U)
39617 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
39618 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
39621 #define V_RDWR(x) ((x) << S_RDWR)
39622 #define F_RDWR V_RDWR(1U)
39624 #define S_VFINDEX 14
39625 #define M_VFINDEX 0x7fU
39626 #define V_VFINDEX(x) ((x) << S_VFINDEX)
39627 #define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
39629 #define S_SRCHHADDR 7
39630 #define M_SRCHHADDR 0x7fU
39631 #define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
39632 #define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
39634 #define S_SRCHLADDR 0
39635 #define M_SRCHLADDR 0x7fU
39636 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
39637 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
39639 #define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
39641 #define S_VFLUTBUSY 10
39642 #define V_VFLUTBUSY(x) ((x) << S_VFLUTBUSY)
39643 #define F_VFLUTBUSY V_VFLUTBUSY(1U)
39645 #define S_VFLUTSTART 9
39646 #define V_VFLUTSTART(x) ((x) << S_VFLUTSTART)
39647 #define F_VFLUTSTART V_VFLUTSTART(1U)
39649 #define S_T6_RDWR 8
39650 #define V_T6_RDWR(x) ((x) << S_T6_RDWR)
39651 #define F_T6_RDWR V_T6_RDWR(1U)
39653 #define S_T6_VFINDEX 0
39654 #define M_T6_VFINDEX 0xffU
39655 #define V_T6_VFINDEX(x) ((x) << S_T6_VFINDEX)
39656 #define G_T6_VFINDEX(x) (((x) >> S_T6_VFINDEX) & M_T6_VFINDEX)
39658 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
39659 #define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
39661 #define S_T6_SRCHHADDR 12
39662 #define M_T6_SRCHHADDR 0xfffU
39663 #define V_T6_SRCHHADDR(x) ((x) << S_T6_SRCHHADDR)
39664 #define G_T6_SRCHHADDR(x) (((x) >> S_T6_SRCHHADDR) & M_T6_SRCHHADDR)
39666 #define S_T6_SRCHLADDR 0
39667 #define M_T6_SRCHLADDR 0xfffU
39668 #define V_T6_SRCHLADDR(x) ((x) << S_T6_SRCHLADDR)
39669 #define G_T6_SRCHLADDR(x) (((x) >> S_T6_SRCHLADDR) & M_T6_SRCHLADDR)
39671 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
39672 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
39673 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
39674 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
39675 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
39676 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
39677 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
39678 #define A_LE_HASH_COLLISION 0x19fc4
39679 #define A_LE_GLOBAL_COLLISION 0x19fc8
39680 #define A_LE_FULL_CNT_COLLISION 0x19fcc
39681 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
39682 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
39683 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
39684 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
39685 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
39686 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
39688 /* registers for module NCSI */
39689 #define NCSI_BASE_ADDR 0x1a000
39691 #define A_NCSI_PORT_CFGREG 0x1a000
39693 #define S_WIREEN 28
39694 #define M_WIREEN 0xfU
39695 #define V_WIREEN(x) ((x) << S_WIREEN)
39696 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
39698 #define S_STRP_CRC 24
39699 #define M_STRP_CRC 0xfU
39700 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
39701 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
39703 #define S_RX_HALT 22
39704 #define V_RX_HALT(x) ((x) << S_RX_HALT)
39705 #define F_RX_HALT V_RX_HALT(1U)
39707 #define S_FLUSH_RX_FIFO 21
39708 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
39709 #define F_FLUSH_RX_FIFO V_FLUSH_RX_FIFO(1U)
39711 #define S_HW_ARB_EN 20
39712 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
39713 #define F_HW_ARB_EN V_HW_ARB_EN(1U)
39715 #define S_SOFT_PKG_SEL 19
39716 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
39717 #define F_SOFT_PKG_SEL V_SOFT_PKG_SEL(1U)
39719 #define S_ERR_DISCARD_EN 18
39720 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
39721 #define F_ERR_DISCARD_EN V_ERR_DISCARD_EN(1U)
39723 #define S_MAX_PKT_SIZE 4
39724 #define M_MAX_PKT_SIZE 0x3fffU
39725 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
39726 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
39728 #define S_RX_BYTE_SWAP 3
39729 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
39730 #define F_RX_BYTE_SWAP V_RX_BYTE_SWAP(1U)
39732 #define S_TX_BYTE_SWAP 2
39733 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
39734 #define F_TX_BYTE_SWAP V_TX_BYTE_SWAP(1U)
39736 #define A_NCSI_RST_CTRL 0x1a004
39738 #define S_MAC_REF_RST 2
39739 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
39740 #define F_MAC_REF_RST V_MAC_REF_RST(1U)
39742 #define S_MAC_RX_RST 1
39743 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
39744 #define F_MAC_RX_RST V_MAC_RX_RST(1U)
39746 #define S_MAC_TX_RST 0
39747 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
39748 #define F_MAC_TX_RST V_MAC_TX_RST(1U)
39750 #define A_NCSI_CH0_SADDR_LOW 0x1a010
39751 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
39753 #define S_CHO_SADDR_EN 31
39754 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
39755 #define F_CHO_SADDR_EN V_CHO_SADDR_EN(1U)
39757 #define S_CH0_SADDR_HIGH 0
39758 #define M_CH0_SADDR_HIGH 0xffffU
39759 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
39760 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
39762 #define A_NCSI_CH1_SADDR_LOW 0x1a018
39763 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
39765 #define S_CH1_SADDR_EN 31
39766 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
39767 #define F_CH1_SADDR_EN V_CH1_SADDR_EN(1U)
39769 #define S_CH1_SADDR_HIGH 0
39770 #define M_CH1_SADDR_HIGH 0xffffU
39771 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
39772 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
39774 #define A_NCSI_CH2_SADDR_LOW 0x1a020
39775 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
39777 #define S_CH2_SADDR_EN 31
39778 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
39779 #define F_CH2_SADDR_EN V_CH2_SADDR_EN(1U)
39781 #define S_CH2_SADDR_HIGH 0
39782 #define M_CH2_SADDR_HIGH 0xffffU
39783 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
39784 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
39786 #define A_NCSI_CH3_SADDR_LOW 0x1a028
39787 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
39789 #define S_CH3_SADDR_EN 31
39790 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
39791 #define F_CH3_SADDR_EN V_CH3_SADDR_EN(1U)
39793 #define S_CH3_SADDR_HIGH 0
39794 #define M_CH3_SADDR_HIGH 0xffffU
39795 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
39796 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
39798 #define A_NCSI_WORK_REQHDR_0 0x1a030
39799 #define A_NCSI_WORK_REQHDR_1 0x1a034
39800 #define A_NCSI_WORK_REQHDR_2 0x1a038
39801 #define A_NCSI_WORK_REQHDR_3 0x1a03c
39802 #define A_NCSI_MPS_HDR_LO 0x1a040
39803 #define A_NCSI_MPS_HDR_HI 0x1a044
39804 #define A_NCSI_CTL 0x1a048
39806 #define S_STRIP_OVLAN 3
39807 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
39808 #define F_STRIP_OVLAN V_STRIP_OVLAN(1U)
39810 #define S_BMC_DROP_NON_BC 2
39811 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
39812 #define F_BMC_DROP_NON_BC V_BMC_DROP_NON_BC(1U)
39814 #define S_BMC_RX_FWD_ALL 1
39815 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
39816 #define F_BMC_RX_FWD_ALL V_BMC_RX_FWD_ALL(1U)
39818 #define S_FWD_BMC 0
39819 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
39820 #define F_FWD_BMC V_FWD_BMC(1U)
39822 #define A_NCSI_NCSI_ETYPE 0x1a04c
39824 #define S_NCSI_ETHERTYPE 0
39825 #define M_NCSI_ETHERTYPE 0xffffU
39826 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
39827 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
39829 #define A_NCSI_RX_FIFO_CNT 0x1a050
39831 #define S_NCSI_RXFIFO_CNT 0
39832 #define M_NCSI_RXFIFO_CNT 0x7ffU
39833 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
39834 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
39836 #define A_NCSI_RX_ERR_CNT 0x1a054
39837 #define A_NCSI_RX_OF_CNT 0x1a058
39838 #define A_NCSI_RX_MS_CNT 0x1a05c
39839 #define A_NCSI_RX_IE_CNT 0x1a060
39840 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
39842 #define S_MPS2CIM_CNT 16
39843 #define M_MPS2CIM_CNT 0x1ffU
39844 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
39845 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
39847 #define S_MPS2BMC_CNT 0
39848 #define M_MPS2BMC_CNT 0x1ffU
39849 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
39850 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
39852 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
39854 #define S_CIM2MPS_CNT 16
39855 #define M_CIM2MPS_CNT 0x1ffU
39856 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
39857 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
39859 #define S_CIM2BMC_CNT 0
39860 #define M_CIM2BMC_CNT 0x1ffU
39861 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
39862 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
39864 #define A_NCSI_TX_FIFO_CNT 0x1a06c
39866 #define S_TX_FIFO_CNT 0
39867 #define M_TX_FIFO_CNT 0x3ffU
39868 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
39869 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
39871 #define A_NCSI_SE_CNT_CTL 0x1a0b0
39873 #define S_SE_CNT_CLR 0
39874 #define M_SE_CNT_CLR 0xfU
39875 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
39876 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
39878 #define A_NCSI_SE_CNT_MPS 0x1a0b4
39880 #define S_NC2MPS_SOP_CNT 24
39881 #define M_NC2MPS_SOP_CNT 0xffU
39882 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
39883 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
39885 #define S_NC2MPS_EOP_CNT 16
39886 #define M_NC2MPS_EOP_CNT 0x3fU
39887 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
39888 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
39890 #define S_MPS2NC_SOP_CNT 8
39891 #define M_MPS2NC_SOP_CNT 0xffU
39892 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
39893 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
39895 #define S_MPS2NC_EOP_CNT 0
39896 #define M_MPS2NC_EOP_CNT 0xffU
39897 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
39898 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
39900 #define A_NCSI_SE_CNT_CIM 0x1a0b8
39902 #define S_NC2CIM_SOP_CNT 24
39903 #define M_NC2CIM_SOP_CNT 0xffU
39904 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
39905 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
39907 #define S_NC2CIM_EOP_CNT 16
39908 #define M_NC2CIM_EOP_CNT 0x3fU
39909 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
39910 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
39912 #define S_CIM2NC_SOP_CNT 8
39913 #define M_CIM2NC_SOP_CNT 0xffU
39914 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
39915 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
39917 #define S_CIM2NC_EOP_CNT 0
39918 #define M_CIM2NC_EOP_CNT 0xffU
39919 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
39920 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
39922 #define A_NCSI_BUS_DEBUG 0x1a0bc
39924 #define S_SOP_CNT_ERR 12
39925 #define M_SOP_CNT_ERR 0xfU
39926 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
39927 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
39929 #define S_BUS_STATE_MPS_OUT 6
39930 #define M_BUS_STATE_MPS_OUT 0x3U
39931 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
39932 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
39934 #define S_BUS_STATE_MPS_IN 4
39935 #define M_BUS_STATE_MPS_IN 0x3U
39936 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
39937 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
39939 #define S_BUS_STATE_CIM_OUT 2
39940 #define M_BUS_STATE_CIM_OUT 0x3U
39941 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
39942 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
39944 #define S_BUS_STATE_CIM_IN 0
39945 #define M_BUS_STATE_CIM_IN 0x3U
39946 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
39947 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
39949 #define A_NCSI_LA_RDPTR 0x1a0c0
39950 #define A_NCSI_LA_RDDATA 0x1a0c4
39951 #define A_NCSI_LA_WRPTR 0x1a0c8
39952 #define A_NCSI_LA_RESERVED 0x1a0cc
39953 #define A_NCSI_LA_CTL 0x1a0d0
39954 #define A_NCSI_INT_ENABLE 0x1a0d4
39956 #define S_CIM_DM_PRTY_ERR 8
39957 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
39958 #define F_CIM_DM_PRTY_ERR V_CIM_DM_PRTY_ERR(1U)
39960 #define S_MPS_DM_PRTY_ERR 7
39961 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
39962 #define F_MPS_DM_PRTY_ERR V_MPS_DM_PRTY_ERR(1U)
39965 #define V_TOKEN(x) ((x) << S_TOKEN)
39966 #define F_TOKEN V_TOKEN(1U)
39968 #define S_ARB_DONE 5
39969 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
39970 #define F_ARB_DONE V_ARB_DONE(1U)
39972 #define S_ARB_STARTED 4
39973 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
39974 #define F_ARB_STARTED V_ARB_STARTED(1U)
39977 #define V_WOL(x) ((x) << S_WOL)
39978 #define F_WOL V_WOL(1U)
39981 #define V_MACINT(x) ((x) << S_MACINT)
39982 #define F_MACINT V_MACINT(1U)
39984 #define S_TXFIFO_PRTY_ERR 1
39985 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
39986 #define F_TXFIFO_PRTY_ERR V_TXFIFO_PRTY_ERR(1U)
39988 #define S_RXFIFO_PRTY_ERR 0
39989 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
39990 #define F_RXFIFO_PRTY_ERR V_RXFIFO_PRTY_ERR(1U)
39992 #define A_NCSI_INT_CAUSE 0x1a0d8
39993 #define A_NCSI_STATUS 0x1a0dc
39996 #define V_MASTER(x) ((x) << S_MASTER)
39997 #define F_MASTER V_MASTER(1U)
39999 #define S_ARB_STATUS 0
40000 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
40001 #define F_ARB_STATUS V_ARB_STATUS(1U)
40003 #define A_NCSI_PAUSE_CTRL 0x1a0e0
40005 #define S_FORCEPAUSE 0
40006 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
40007 #define F_FORCEPAUSE V_FORCEPAUSE(1U)
40009 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
40010 #define A_NCSI_PAUSE_WM 0x1a0ec
40012 #define S_PAUSEHWM 16
40013 #define M_PAUSEHWM 0x7ffU
40014 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
40015 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
40017 #define S_PAUSELWM 0
40018 #define M_PAUSELWM 0x7ffU
40019 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
40020 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
40022 #define A_NCSI_DEBUG 0x1a0f0
40024 #define S_DEBUGSEL 0
40025 #define M_DEBUGSEL 0x3fU
40026 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
40027 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
40029 #define S_TXFIFO_EMPTY 4
40030 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
40031 #define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U)
40033 #define S_TXFIFO_FULL 3
40034 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
40035 #define F_TXFIFO_FULL V_TXFIFO_FULL(1U)
40038 #define M_PKG_ID 0x7U
40039 #define V_PKG_ID(x) ((x) << S_PKG_ID)
40040 #define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
40042 #define A_NCSI_PERR_INJECT 0x1a0f4
40044 #define S_MCSIMELSEL 1
40045 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
40046 #define F_MCSIMELSEL V_MCSIMELSEL(1U)
40048 #define A_NCSI_PERR_ENABLE 0x1a0f8
40049 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
40051 #define S_TXSNDZEROPAUSE 12
40052 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
40053 #define F_TXSNDZEROPAUSE V_TXSNDZEROPAUSE(1U)
40055 #define S_TXSNDPAUSE 11
40056 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
40057 #define F_TXSNDPAUSE V_TXSNDPAUSE(1U)
40059 #define S_TXSTOP 10
40060 #define V_TXSTOP(x) ((x) << S_TXSTOP)
40061 #define F_TXSTOP V_TXSTOP(1U)
40063 #define S_TXSTART 9
40064 #define V_TXSTART(x) ((x) << S_TXSTART)
40065 #define F_TXSTART V_TXSTART(1U)
40067 #define S_BACKPRESS 8
40068 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
40069 #define F_BACKPRESS V_BACKPRESS(1U)
40071 #define S_STATWREN 7
40072 #define V_STATWREN(x) ((x) << S_STATWREN)
40073 #define F_STATWREN V_STATWREN(1U)
40075 #define S_INCRSTAT 6
40076 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
40077 #define F_INCRSTAT V_INCRSTAT(1U)
40079 #define S_CLEARSTAT 5
40080 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
40081 #define F_CLEARSTAT V_CLEARSTAT(1U)
40083 #define S_ENMGMTPORT 4
40084 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
40085 #define F_ENMGMTPORT V_ENMGMTPORT(1U)
40087 #define S_NCSITXEN 3
40088 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
40089 #define F_NCSITXEN V_NCSITXEN(1U)
40091 #define S_NCSIRXEN 2
40092 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
40093 #define F_NCSIRXEN V_NCSIRXEN(1U)
40095 #define S_LOOPLOCAL 1
40096 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
40097 #define F_LOOPLOCAL V_LOOPLOCAL(1U)
40099 #define S_LOOPPHY 0
40100 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
40101 #define F_LOOPPHY V_LOOPPHY(1U)
40103 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
40105 #define S_PCLKDIV128 22
40106 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
40107 #define F_PCLKDIV128 V_PCLKDIV128(1U)
40109 #define S_COPYPAUSE 21
40110 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
40111 #define F_COPYPAUSE V_COPYPAUSE(1U)
40113 #define S_NONSTDPREOK 20
40114 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
40115 #define F_NONSTDPREOK V_NONSTDPREOK(1U)
40118 #define V_NOFCS(x) ((x) << S_NOFCS)
40119 #define F_NOFCS V_NOFCS(1U)
40121 #define S_RXENHALFDUP 18
40122 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
40123 #define F_RXENHALFDUP V_RXENHALFDUP(1U)
40125 #define S_NOCOPYFCS 17
40126 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
40127 #define F_NOCOPYFCS V_NOCOPYFCS(1U)
40129 #define S_LENCHKEN 16
40130 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
40131 #define F_LENCHKEN V_LENCHKEN(1U)
40133 #define S_RXBUFOFFSET 14
40134 #define M_RXBUFOFFSET 0x3U
40135 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
40136 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
40138 #define S_PAUSEEN 13
40139 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
40140 #define F_PAUSEEN V_PAUSEEN(1U)
40142 #define S_RETRYTEST 12
40143 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
40144 #define F_RETRYTEST V_RETRYTEST(1U)
40146 #define S_PCLKDIV 10
40147 #define M_PCLKDIV 0x3U
40148 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
40149 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
40151 #define S_EXTCLASS 9
40152 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
40153 #define F_EXTCLASS V_EXTCLASS(1U)
40155 #define S_EN1536FRAME 8
40156 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
40157 #define F_EN1536FRAME V_EN1536FRAME(1U)
40159 #define S_UCASTHASHEN 7
40160 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
40161 #define F_UCASTHASHEN V_UCASTHASHEN(1U)
40163 #define S_MCASTHASHEN 6
40164 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
40165 #define F_MCASTHASHEN V_MCASTHASHEN(1U)
40167 #define S_RXBCASTDIS 5
40168 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
40169 #define F_RXBCASTDIS V_RXBCASTDIS(1U)
40171 #define S_NCSICOPYALLFRAMES 4
40172 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
40173 #define F_NCSICOPYALLFRAMES V_NCSICOPYALLFRAMES(1U)
40175 #define S_JUMBOEN 3
40176 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
40177 #define F_JUMBOEN V_JUMBOEN(1U)
40180 #define V_SEREN(x) ((x) << S_SEREN)
40181 #define F_SEREN V_SEREN(1U)
40183 #define S_FULLDUPLEX 1
40184 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
40185 #define F_FULLDUPLEX V_FULLDUPLEX(1U)
40188 #define V_SPEED(x) ((x) << S_SPEED)
40189 #define F_SPEED V_SPEED(1U)
40191 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
40193 #define S_PHYMGMTSTATUS 2
40194 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
40195 #define F_PHYMGMTSTATUS V_PHYMGMTSTATUS(1U)
40197 #define S_MDISTATUS 1
40198 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
40199 #define F_MDISTATUS V_MDISTATUS(1U)
40201 #define S_LINKSTATUS 0
40202 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
40203 #define F_LINKSTATUS V_LINKSTATUS(1U)
40205 #define A_NCSI_MACB_TX_STATUS 0x1a114
40207 #define S_UNDERRUNERR 6
40208 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
40209 #define F_UNDERRUNERR V_UNDERRUNERR(1U)
40211 #define S_TXCOMPLETE 5
40212 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
40213 #define F_TXCOMPLETE V_TXCOMPLETE(1U)
40215 #define S_BUFFEREXHAUSTED 4
40216 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
40217 #define F_BUFFEREXHAUSTED V_BUFFEREXHAUSTED(1U)
40219 #define S_TXPROGRESS 3
40220 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
40221 #define F_TXPROGRESS V_TXPROGRESS(1U)
40223 #define S_RETRYLIMIT 2
40224 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
40225 #define F_RETRYLIMIT V_RETRYLIMIT(1U)
40227 #define S_COLEVENT 1
40228 #define V_COLEVENT(x) ((x) << S_COLEVENT)
40229 #define F_COLEVENT V_COLEVENT(1U)
40231 #define S_USEDBITREAD 0
40232 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
40233 #define F_USEDBITREAD V_USEDBITREAD(1U)
40235 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
40237 #define S_RXBUFQPTR 2
40238 #define M_RXBUFQPTR 0x3fffffffU
40239 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
40240 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
40242 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
40244 #define S_TXBUFQPTR 2
40245 #define M_TXBUFQPTR 0x3fffffffU
40246 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
40247 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
40249 #define A_NCSI_MACB_RX_STATUS 0x1a120
40251 #define S_RXOVERRUNERR 2
40252 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
40253 #define F_RXOVERRUNERR V_RXOVERRUNERR(1U)
40255 #define S_MACB_FRAMERCVD 1
40256 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
40257 #define F_MACB_FRAMERCVD V_MACB_FRAMERCVD(1U)
40259 #define S_NORXBUF 0
40260 #define V_NORXBUF(x) ((x) << S_NORXBUF)
40261 #define F_NORXBUF V_NORXBUF(1U)
40263 #define A_NCSI_MACB_INT_STATUS 0x1a124
40265 #define S_PAUSETIMEZERO 13
40266 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
40267 #define F_PAUSETIMEZERO V_PAUSETIMEZERO(1U)
40269 #define S_PAUSERCVD 12
40270 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
40271 #define F_PAUSERCVD V_PAUSERCVD(1U)
40273 #define S_HRESPNOTOK 11
40274 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
40275 #define F_HRESPNOTOK V_HRESPNOTOK(1U)
40277 #define S_RXOVERRUN 10
40278 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
40279 #define F_RXOVERRUN V_RXOVERRUN(1U)
40281 #define S_LINKCHANGE 9
40282 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
40283 #define F_LINKCHANGE V_LINKCHANGE(1U)
40285 #define S_INT_TXCOMPLETE 7
40286 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
40287 #define F_INT_TXCOMPLETE V_INT_TXCOMPLETE(1U)
40289 #define S_TXBUFERR 6
40290 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
40291 #define F_TXBUFERR V_TXBUFERR(1U)
40293 #define S_RETRYLIMITERR 5
40294 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
40295 #define F_RETRYLIMITERR V_RETRYLIMITERR(1U)
40297 #define S_TXBUFUNDERRUN 4
40298 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
40299 #define F_TXBUFUNDERRUN V_TXBUFUNDERRUN(1U)
40301 #define S_TXUSEDBITREAD 3
40302 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
40303 #define F_TXUSEDBITREAD V_TXUSEDBITREAD(1U)
40305 #define S_RXUSEDBITREAD 2
40306 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
40307 #define F_RXUSEDBITREAD V_RXUSEDBITREAD(1U)
40309 #define S_RXCOMPLETE 1
40310 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
40311 #define F_RXCOMPLETE V_RXCOMPLETE(1U)
40313 #define S_MGMTFRAMESENT 0
40314 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
40315 #define F_MGMTFRAMESENT V_MGMTFRAMESENT(1U)
40317 #define A_NCSI_MACB_INT_EN 0x1a128
40318 #define A_NCSI_MACB_INT_DIS 0x1a12c
40319 #define A_NCSI_MACB_INT_MASK 0x1a130
40320 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
40322 #define S_PAUSETIME 0
40323 #define M_PAUSETIME 0xffffU
40324 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
40325 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
40327 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
40329 #define S_PAUSEFRRCVD 0
40330 #define M_PAUSEFRRCVD 0xffffU
40331 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
40332 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
40334 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
40336 #define S_TXFRAMESOK 0
40337 #define M_TXFRAMESOK 0xffffffU
40338 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
40339 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
40341 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
40343 #define S_SINGLECOLTXFRAMES 0
40344 #define M_SINGLECOLTXFRAMES 0xffffU
40345 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
40346 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
40348 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
40350 #define S_MULCOLTXFRAMES 0
40351 #define M_MULCOLTXFRAMES 0xffffU
40352 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
40353 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
40355 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
40357 #define S_RXFRAMESOK 0
40358 #define M_RXFRAMESOK 0xffffffU
40359 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
40360 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
40362 #define A_NCSI_MACB_FCS_ERR 0x1a150
40364 #define S_RXFCSERR 0
40365 #define M_RXFCSERR 0xffU
40366 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
40367 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
40369 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
40371 #define S_RXALIGNERR 0
40372 #define M_RXALIGNERR 0xffU
40373 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
40374 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
40376 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
40378 #define S_TXDEFERREDFRAMES 0
40379 #define M_TXDEFERREDFRAMES 0xffffU
40380 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
40381 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
40383 #define A_NCSI_MACB_LATE_COL 0x1a15c
40385 #define S_LATECOLLISIONS 0
40386 #define M_LATECOLLISIONS 0xffffU
40387 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
40388 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
40390 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
40392 #define S_EXCESSIVECOLLISIONS 0
40393 #define M_EXCESSIVECOLLISIONS 0xffU
40394 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
40395 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
40397 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
40399 #define S_TXUNDERRUNERR 0
40400 #define M_TXUNDERRUNERR 0xffU
40401 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
40402 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
40404 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
40406 #define S_CARRIERSENSEERRS 0
40407 #define M_CARRIERSENSEERRS 0xffU
40408 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
40409 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
40411 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
40413 #define S_RXRESOURCEERR 0
40414 #define M_RXRESOURCEERR 0xffffU
40415 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
40416 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
40418 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
40420 #define S_RXOVERRUNERRCNT 0
40421 #define M_RXOVERRUNERRCNT 0xffU
40422 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
40423 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
40425 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
40427 #define S_RXSYMBOLERR 0
40428 #define M_RXSYMBOLERR 0xffU
40429 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
40430 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
40432 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
40434 #define S_RXOVERSIZEERR 0
40435 #define M_RXOVERSIZEERR 0xffU
40436 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
40437 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
40439 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
40441 #define S_RXJABBERERR 0
40442 #define M_RXJABBERERR 0xffU
40443 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
40444 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
40446 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
40448 #define S_RXUNDERSIZEFR 0
40449 #define M_RXUNDERSIZEFR 0xffU
40450 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
40451 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
40453 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
40455 #define S_SQETESTERR 0
40456 #define M_SQETESTERR 0xffU
40457 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
40458 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
40460 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
40462 #define S_LENGTHERR 0
40463 #define M_LENGTHERR 0xffU
40464 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
40465 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
40467 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
40469 #define S_TXPAUSEFRAMES 0
40470 #define M_TXPAUSEFRAMES 0xffffU
40471 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
40472 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
40474 #define A_NCSI_MACB_HASH_LOW 0x1a190
40475 #define A_NCSI_MACB_HASH_HIGH 0x1a194
40476 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
40477 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
40479 #define S_MATCHHIGH 0
40480 #define M_MATCHHIGH 0xffffU
40481 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
40482 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
40484 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
40485 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
40486 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
40487 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
40488 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
40489 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
40490 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
40493 #define M_TYPEID 0xffffU
40494 #define V_TYPEID(x) ((x) << S_TYPEID)
40495 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
40497 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
40499 #define S_TXPAUSEQUANTUM 0
40500 #define M_TXPAUSEQUANTUM 0xffffU
40501 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
40502 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
40504 #define A_NCSI_MACB_USER_IO 0x1a1c0
40506 #define S_USERPROGINPUT 16
40507 #define M_USERPROGINPUT 0xffffU
40508 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
40509 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
40511 #define S_USERPROGOUTPUT 0
40512 #define M_USERPROGOUTPUT 0xffffU
40513 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
40514 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
40516 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
40518 #define S_MCHASHEN 19
40519 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
40520 #define F_MCHASHEN V_MCHASHEN(1U)
40522 #define S_SPECIFIC1EN 18
40523 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
40524 #define F_SPECIFIC1EN V_SPECIFIC1EN(1U)
40527 #define V_ARPEN(x) ((x) << S_ARPEN)
40528 #define F_ARPEN V_ARPEN(1U)
40530 #define S_MAGICPKTEN 16
40531 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
40532 #define F_MAGICPKTEN V_MAGICPKTEN(1U)
40534 #define S_ARPIPADDR 0
40535 #define M_ARPIPADDR 0xffffU
40536 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
40537 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
40539 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
40541 #define S_PARTREF 16
40542 #define M_PARTREF 0xffffU
40543 #define V_PARTREF(x) ((x) << S_PARTREF)
40544 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
40547 #define M_DESREV 0xffffU
40548 #define V_DESREV(x) ((x) << S_DESREV)
40549 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
40551 /* registers for module XGMAC */
40552 #define XGMAC_BASE_ADDR 0x0
40554 #define A_XGMAC_PORT_CFG 0x1000
40556 #define S_XGMII_CLK_SEL 29
40557 #define M_XGMII_CLK_SEL 0x7U
40558 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
40559 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
40561 #define S_SINKTX 27
40562 #define V_SINKTX(x) ((x) << S_SINKTX)
40563 #define F_SINKTX V_SINKTX(1U)
40565 #define S_SINKTXONLINKDOWN 26
40566 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
40567 #define F_SINKTXONLINKDOWN V_SINKTXONLINKDOWN(1U)
40569 #define S_XG2G_SPEED_MODE 25
40570 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
40571 #define F_XG2G_SPEED_MODE V_XG2G_SPEED_MODE(1U)
40573 #define S_LOOPNOFWD 24
40574 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
40575 #define F_LOOPNOFWD V_LOOPNOFWD(1U)
40577 #define S_XGM_TX_PAUSE_SIZE 23
40578 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
40579 #define F_XGM_TX_PAUSE_SIZE V_XGM_TX_PAUSE_SIZE(1U)
40581 #define S_XGM_TX_PAUSE_FRAME 22
40582 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
40583 #define F_XGM_TX_PAUSE_FRAME V_XGM_TX_PAUSE_FRAME(1U)
40585 #define S_XGM_TX_DISABLE_PRE 21
40586 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
40587 #define F_XGM_TX_DISABLE_PRE V_XGM_TX_DISABLE_PRE(1U)
40589 #define S_XGM_TX_DISABLE_CRC 20
40590 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
40591 #define F_XGM_TX_DISABLE_CRC V_XGM_TX_DISABLE_CRC(1U)
40593 #define S_SMUX_RX_LOOP 19
40594 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
40595 #define F_SMUX_RX_LOOP V_SMUX_RX_LOOP(1U)
40597 #define S_RX_LANE_SWAP 18
40598 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
40599 #define F_RX_LANE_SWAP V_RX_LANE_SWAP(1U)
40601 #define S_TX_LANE_SWAP 17
40602 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
40603 #define F_TX_LANE_SWAP V_TX_LANE_SWAP(1U)
40605 #define S_SIGNAL_DET 14
40606 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
40607 #define F_SIGNAL_DET V_SIGNAL_DET(1U)
40609 #define S_PMUX_RX_LOOP 13
40610 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
40611 #define F_PMUX_RX_LOOP V_PMUX_RX_LOOP(1U)
40613 #define S_PMUX_TX_LOOP 12
40614 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
40615 #define F_PMUX_TX_LOOP V_PMUX_TX_LOOP(1U)
40617 #define S_XGM_RX_SEL 10
40618 #define M_XGM_RX_SEL 0x3U
40619 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
40620 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
40622 #define S_PCS_TX_SEL 8
40623 #define M_PCS_TX_SEL 0x3U
40624 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
40625 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
40627 #define S_XAUI20_REM_PRE 5
40628 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
40629 #define F_XAUI20_REM_PRE V_XAUI20_REM_PRE(1U)
40631 #define S_XAUI20_XGMII_SEL 4
40632 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
40633 #define F_XAUI20_XGMII_SEL V_XAUI20_XGMII_SEL(1U)
40635 #define S_PORT_SEL 0
40636 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
40637 #define F_PORT_SEL V_PORT_SEL(1U)
40639 #define A_XGMAC_PORT_RESET_CTRL 0x1004
40641 #define S_AUXEXT_RESET 10
40642 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
40643 #define F_AUXEXT_RESET V_AUXEXT_RESET(1U)
40645 #define S_TXFIFO_RESET 9
40646 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
40647 #define F_TXFIFO_RESET V_TXFIFO_RESET(1U)
40649 #define S_RXFIFO_RESET 8
40650 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
40651 #define F_RXFIFO_RESET V_RXFIFO_RESET(1U)
40653 #define S_BEAN_RESET 7
40654 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
40655 #define F_BEAN_RESET V_BEAN_RESET(1U)
40657 #define S_XAUI_RESET 6
40658 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
40659 #define F_XAUI_RESET V_XAUI_RESET(1U)
40661 #define S_AE_RESET 5
40662 #define V_AE_RESET(x) ((x) << S_AE_RESET)
40663 #define F_AE_RESET V_AE_RESET(1U)
40665 #define S_XGM_RESET 4
40666 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
40667 #define F_XGM_RESET V_XGM_RESET(1U)
40669 #define S_XG2G_RESET 3
40670 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
40671 #define F_XG2G_RESET V_XG2G_RESET(1U)
40673 #define S_WOL_RESET 2
40674 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
40675 #define F_WOL_RESET V_WOL_RESET(1U)
40677 #define S_XFI_PCS_RESET 1
40678 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
40679 #define F_XFI_PCS_RESET V_XFI_PCS_RESET(1U)
40681 #define S_HSS_RESET 0
40682 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
40683 #define F_HSS_RESET V_HSS_RESET(1U)
40685 #define A_XGMAC_PORT_LED_CFG 0x1008
40687 #define S_LED1_CFG 5
40688 #define M_LED1_CFG 0x7U
40689 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
40690 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
40692 #define S_LED1_POLARITY_INV 4
40693 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
40694 #define F_LED1_POLARITY_INV V_LED1_POLARITY_INV(1U)
40696 #define S_LED0_CFG 1
40697 #define M_LED0_CFG 0x7U
40698 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
40699 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
40701 #define S_LED0_POLARITY_INV 0
40702 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
40703 #define F_LED0_POLARITY_INV V_LED0_POLARITY_INV(1U)
40705 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
40707 #define S_LED_COUNT_HI 0
40708 #define M_LED_COUNT_HI 0x1ffffffU
40709 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
40710 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
40712 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
40714 #define S_LED_COUNT_LO 0
40715 #define M_LED_COUNT_LO 0x1ffffffU
40716 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
40717 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
40719 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
40721 #define S_TESTCLK_SEL 0
40722 #define M_TESTCLK_SEL 0xfU
40723 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
40724 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
40726 #define A_XGMAC_PORT_CFG2 0x1018
40728 #define S_RX_POLARITY_INV 28
40729 #define M_RX_POLARITY_INV 0xfU
40730 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
40731 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
40733 #define S_TX_POLARITY_INV 24
40734 #define M_TX_POLARITY_INV 0xfU
40735 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
40736 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
40738 #define S_INSTANCENUM 22
40739 #define M_INSTANCENUM 0x3U
40740 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
40741 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
40743 #define S_STOPONPERR 21
40744 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
40745 #define F_STOPONPERR V_STOPONPERR(1U)
40747 #define S_MACTXEN 20
40748 #define V_MACTXEN(x) ((x) << S_MACTXEN)
40749 #define F_MACTXEN V_MACTXEN(1U)
40751 #define S_MACRXEN 19
40752 #define V_MACRXEN(x) ((x) << S_MACRXEN)
40753 #define F_MACRXEN V_MACRXEN(1U)
40756 #define V_PATEN(x) ((x) << S_PATEN)
40757 #define F_PATEN V_PATEN(1U)
40759 #define S_MAGICEN 17
40760 #define V_MAGICEN(x) ((x) << S_MAGICEN)
40761 #define F_MAGICEN V_MAGICEN(1U)
40764 #define M_TX_IPG 0x1fffU
40765 #define V_TX_IPG(x) ((x) << S_TX_IPG)
40766 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
40768 #define S_AEC_PMA_TX_READY 1
40769 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
40770 #define F_AEC_PMA_TX_READY V_AEC_PMA_TX_READY(1U)
40772 #define S_AEC_PMA_RX_READY 0
40773 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
40774 #define F_AEC_PMA_RX_READY V_AEC_PMA_RX_READY(1U)
40776 #define A_XGMAC_PORT_PKT_COUNT 0x101c
40778 #define S_TX_SOP_COUNT 24
40779 #define M_TX_SOP_COUNT 0xffU
40780 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
40781 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
40783 #define S_TX_EOP_COUNT 16
40784 #define M_TX_EOP_COUNT 0xffU
40785 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
40786 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
40788 #define S_RX_SOP_COUNT 8
40789 #define M_RX_SOP_COUNT 0xffU
40790 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
40791 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
40793 #define S_RX_EOP_COUNT 0
40794 #define M_RX_EOP_COUNT 0xffU
40795 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
40796 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
40798 #define A_XGMAC_PORT_PERR_INJECT 0x1020
40800 #define S_XGMMEMSEL 1
40801 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
40802 #define F_XGMMEMSEL V_XGMMEMSEL(1U)
40804 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
40805 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
40807 #define S_MAC_WOL_DA 0
40808 #define M_MAC_WOL_DA 0xffffU
40809 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
40810 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
40812 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
40813 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
40816 #define M_TXSOP 0xffU
40817 #define V_TXSOP(x) ((x) << S_TXSOP)
40818 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
40821 #define M_TXEOP 0xffU
40822 #define V_TXEOP(x) ((x) << S_TXEOP)
40823 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
40826 #define M_RXSOP 0xffU
40827 #define V_RXSOP(x) ((x) << S_RXSOP)
40828 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
40830 #define S_T4_RXEOP 0
40831 #define M_T4_RXEOP 0xffU
40832 #define V_T4_RXEOP(x) ((x) << S_T4_RXEOP)
40833 #define G_T4_RXEOP(x) (((x) >> S_T4_RXEOP) & M_T4_RXEOP)
40835 #define A_XGMAC_PORT_LINK_STATUS 0x1034
40838 #define V_REMFLT(x) ((x) << S_REMFLT)
40839 #define F_REMFLT V_REMFLT(1U)
40842 #define V_LOCFLT(x) ((x) << S_LOCFLT)
40843 #define F_LOCFLT V_LOCFLT(1U)
40846 #define V_LINKUP(x) ((x) << S_LINKUP)
40847 #define F_LINKUP V_LINKUP(1U)
40850 #define V_LINKDN(x) ((x) << S_LINKDN)
40851 #define F_LINKDN V_LINKDN(1U)
40853 #define A_XGMAC_PORT_CHECKIN 0x1038
40855 #define S_PREAMBLE 1
40856 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
40857 #define F_PREAMBLE V_PREAMBLE(1U)
40859 #define S_CHECKIN 0
40860 #define V_CHECKIN(x) ((x) << S_CHECKIN)
40861 #define F_CHECKIN V_CHECKIN(1U)
40863 #define A_XGMAC_PORT_FAULT_TEST 0x103c
40865 #define S_FLTTYPE 1
40866 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
40867 #define F_FLTTYPE V_FLTTYPE(1U)
40869 #define S_FLTCTRL 0
40870 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
40871 #define F_FLTCTRL V_FLTCTRL(1U)
40873 #define A_XGMAC_PORT_SPARE 0x1040
40874 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
40876 #define S_SIGNALDETECT 0
40877 #define M_SIGNALDETECT 0xfU
40878 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
40879 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
40881 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
40882 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
40885 #define M_CTRL 0xfU
40886 #define V_CTRL(x) ((x) << S_CTRL)
40887 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
40889 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
40892 #define V_CTL(x) ((x) << S_CTL)
40893 #define F_CTL V_CTL(1U)
40896 #define M_HWM 0x1fffU
40897 #define V_HWM(x) ((x) << S_HWM)
40898 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
40901 #define M_LWM 0x1fffU
40902 #define V_LWM(x) ((x) << S_LWM)
40903 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
40905 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
40906 #define A_XGMAC_PORT_LA_TX_0 0x1058
40907 #define A_XGMAC_PORT_LA_RX_0 0x105c
40908 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
40911 #define V_RXRST(x) ((x) << S_RXRST)
40912 #define F_RXRST V_RXRST(1U)
40915 #define V_TXRST(x) ((x) << S_TXRST)
40916 #define F_TXRST V_TXRST(1U)
40919 #define V_XGMII(x) ((x) << S_XGMII)
40920 #define F_XGMII V_XGMII(1U)
40922 #define S_LAPAUSE 2
40923 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
40924 #define F_LAPAUSE V_LAPAUSE(1U)
40926 #define S_STOPERR 1
40927 #define V_STOPERR(x) ((x) << S_STOPERR)
40928 #define F_STOPERR V_STOPERR(1U)
40931 #define V_LASTOP(x) ((x) << S_LASTOP)
40932 #define F_LASTOP V_LASTOP(1U)
40934 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
40935 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
40936 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
40937 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
40938 #define A_XGMAC_PORT_EPIO_OP 0x10d0
40941 #define V_EPIOWR(x) ((x) << S_EPIOWR)
40942 #define F_EPIOWR V_EPIOWR(1U)
40944 #define S_ADDRESS 0
40945 #define M_ADDRESS 0xffU
40946 #define V_ADDRESS(x) ((x) << S_ADDRESS)
40947 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
40949 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
40951 #define S_MAGICDETECTED 31
40952 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
40953 #define F_MAGICDETECTED V_MAGICDETECTED(1U)
40955 #define S_PATDETECTED 30
40956 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
40957 #define F_PATDETECTED V_PATDETECTED(1U)
40959 #define S_CLEARMAGIC 4
40960 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
40961 #define F_CLEARMAGIC V_CLEARMAGIC(1U)
40963 #define S_CLEARMATCH 3
40964 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
40965 #define F_CLEARMATCH V_CLEARMATCH(1U)
40967 #define S_MATCHEDFILTER 0
40968 #define M_MATCHEDFILTER 0x7U
40969 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
40970 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
40972 #define A_XGMAC_PORT_INT_EN 0x10d8
40974 #define S_EXT_LOS 28
40975 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
40976 #define F_EXT_LOS V_EXT_LOS(1U)
40978 #define S_INCMPTBL_LINK 27
40979 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
40980 #define F_INCMPTBL_LINK V_INCMPTBL_LINK(1U)
40982 #define S_PATDETWAKE 26
40983 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
40984 #define F_PATDETWAKE V_PATDETWAKE(1U)
40986 #define S_MAGICWAKE 25
40987 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
40988 #define F_MAGICWAKE V_MAGICWAKE(1U)
40990 #define S_SIGDETCHG 24
40991 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
40992 #define F_SIGDETCHG V_SIGDETCHG(1U)
40994 #define S_PCSR_FEC_CORR 23
40995 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
40996 #define F_PCSR_FEC_CORR V_PCSR_FEC_CORR(1U)
40998 #define S_AE_TRAIN_LOCAL 22
40999 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
41000 #define F_AE_TRAIN_LOCAL V_AE_TRAIN_LOCAL(1U)
41002 #define S_HSSPLL_LOCK 21
41003 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
41004 #define F_HSSPLL_LOCK V_HSSPLL_LOCK(1U)
41006 #define S_HSSPRT_READY 20
41007 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
41008 #define F_HSSPRT_READY V_HSSPRT_READY(1U)
41010 #define S_AUTONEG_DONE 19
41011 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
41012 #define F_AUTONEG_DONE V_AUTONEG_DONE(1U)
41014 #define S_PCSR_HI_BER 18
41015 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
41016 #define F_PCSR_HI_BER V_PCSR_HI_BER(1U)
41018 #define S_PCSR_FEC_ERROR 17
41019 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
41020 #define F_PCSR_FEC_ERROR V_PCSR_FEC_ERROR(1U)
41022 #define S_PCSR_LINK_FAIL 16
41023 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
41024 #define F_PCSR_LINK_FAIL V_PCSR_LINK_FAIL(1U)
41026 #define S_XAUI_DEC_ERROR 15
41027 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
41028 #define F_XAUI_DEC_ERROR V_XAUI_DEC_ERROR(1U)
41030 #define S_XAUI_LINK_FAIL 14
41031 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
41032 #define F_XAUI_LINK_FAIL V_XAUI_LINK_FAIL(1U)
41034 #define S_PCS_CTC_ERROR 13
41035 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
41036 #define F_PCS_CTC_ERROR V_PCS_CTC_ERROR(1U)
41038 #define S_PCS_LINK_GOOD 12
41039 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
41040 #define F_PCS_LINK_GOOD V_PCS_LINK_GOOD(1U)
41042 #define S_PCS_LINK_FAIL 11
41043 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
41044 #define F_PCS_LINK_FAIL V_PCS_LINK_FAIL(1U)
41046 #define S_RXFIFOOVERFLOW 10
41047 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
41048 #define F_RXFIFOOVERFLOW V_RXFIFOOVERFLOW(1U)
41050 #define S_HSSPRBSERR 9
41051 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
41052 #define F_HSSPRBSERR V_HSSPRBSERR(1U)
41054 #define S_HSSEYEQUAL 8
41055 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
41056 #define F_HSSEYEQUAL V_HSSEYEQUAL(1U)
41058 #define S_REMOTEFAULT 7
41059 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
41060 #define F_REMOTEFAULT V_REMOTEFAULT(1U)
41062 #define S_LOCALFAULT 6
41063 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
41064 #define F_LOCALFAULT V_LOCALFAULT(1U)
41066 #define S_MAC_LINK_DOWN 5
41067 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
41068 #define F_MAC_LINK_DOWN V_MAC_LINK_DOWN(1U)
41070 #define S_MAC_LINK_UP 4
41071 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
41072 #define F_MAC_LINK_UP V_MAC_LINK_UP(1U)
41074 #define S_BEAN_INT 3
41075 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
41076 #define F_BEAN_INT V_BEAN_INT(1U)
41078 #define S_XGM_INT 2
41079 #define V_XGM_INT(x) ((x) << S_XGM_INT)
41080 #define F_XGM_INT V_XGM_INT(1U)
41082 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
41083 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
41086 #define V_TXDTS(x) ((x) << S_TXDTS)
41087 #define F_TXDTS V_TXDTS(1U)
41090 #define V_TXCTS(x) ((x) << S_TXCTS)
41091 #define F_TXCTS V_TXCTS(1U)
41094 #define V_TXBTS(x) ((x) << S_TXBTS)
41095 #define F_TXBTS V_TXBTS(1U)
41098 #define V_TXATS(x) ((x) << S_TXATS)
41099 #define F_TXATS V_TXATS(1U)
41101 #define S_TXDOBS 27
41102 #define V_TXDOBS(x) ((x) << S_TXDOBS)
41103 #define F_TXDOBS V_TXDOBS(1U)
41105 #define S_TXCOBS 26
41106 #define V_TXCOBS(x) ((x) << S_TXCOBS)
41107 #define F_TXCOBS V_TXCOBS(1U)
41109 #define S_TXBOBS 25
41110 #define V_TXBOBS(x) ((x) << S_TXBOBS)
41111 #define F_TXBOBS V_TXBOBS(1U)
41113 #define S_TXAOBS 24
41114 #define V_TXAOBS(x) ((x) << S_TXAOBS)
41115 #define F_TXAOBS V_TXAOBS(1U)
41117 #define S_HSSREFCLKSEL 20
41118 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
41119 #define F_HSSREFCLKSEL V_HSSREFCLKSEL(1U)
41121 #define S_HSSAVDHI 17
41122 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
41123 #define F_HSSAVDHI V_HSSAVDHI(1U)
41125 #define S_HSSRXTS 16
41126 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
41127 #define F_HSSRXTS V_HSSRXTS(1U)
41129 #define S_HSSTXACMODE 15
41130 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
41131 #define F_HSSTXACMODE V_HSSTXACMODE(1U)
41133 #define S_HSSRXACMODE 14
41134 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
41135 #define F_HSSRXACMODE V_HSSRXACMODE(1U)
41137 #define S_HSSRESYNC 13
41138 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
41139 #define F_HSSRESYNC V_HSSRESYNC(1U)
41141 #define S_HSSRECCAL 12
41142 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
41143 #define F_HSSRECCAL V_HSSRECCAL(1U)
41145 #define S_HSSPDWNPLL 11
41146 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
41147 #define F_HSSPDWNPLL V_HSSPDWNPLL(1U)
41149 #define S_HSSDIVSEL 9
41150 #define M_HSSDIVSEL 0x3U
41151 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
41152 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
41154 #define S_HSSREFDIV 8
41155 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
41156 #define F_HSSREFDIV V_HSSREFDIV(1U)
41158 #define S_HSSPLLBYP 7
41159 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
41160 #define F_HSSPLLBYP V_HSSPLLBYP(1U)
41162 #define S_HSSLOFREQPLL 6
41163 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
41164 #define F_HSSLOFREQPLL V_HSSLOFREQPLL(1U)
41166 #define S_HSSLOFREQ2PLL 5
41167 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
41168 #define F_HSSLOFREQ2PLL V_HSSLOFREQ2PLL(1U)
41170 #define S_HSSEXTC16SEL 4
41171 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
41172 #define F_HSSEXTC16SEL V_HSSEXTC16SEL(1U)
41174 #define S_HSSRSTCONFIG 1
41175 #define M_HSSRSTCONFIG 0x7U
41176 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
41177 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
41179 #define S_HSSPRBSEN 0
41180 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
41181 #define F_HSSPRBSEN V_HSSPRBSEN(1U)
41183 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
41185 #define S_RXDPRBSRST 28
41186 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
41187 #define F_RXDPRBSRST V_RXDPRBSRST(1U)
41189 #define S_RXDPRBSEN 27
41190 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
41191 #define F_RXDPRBSEN V_RXDPRBSEN(1U)
41193 #define S_RXDPRBSFRCERR 26
41194 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
41195 #define F_RXDPRBSFRCERR V_RXDPRBSFRCERR(1U)
41197 #define S_TXDPRBSRST 25
41198 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
41199 #define F_TXDPRBSRST V_TXDPRBSRST(1U)
41201 #define S_TXDPRBSEN 24
41202 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
41203 #define F_TXDPRBSEN V_TXDPRBSEN(1U)
41205 #define S_RXCPRBSRST 20
41206 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
41207 #define F_RXCPRBSRST V_RXCPRBSRST(1U)
41209 #define S_RXCPRBSEN 19
41210 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
41211 #define F_RXCPRBSEN V_RXCPRBSEN(1U)
41213 #define S_RXCPRBSFRCERR 18
41214 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
41215 #define F_RXCPRBSFRCERR V_RXCPRBSFRCERR(1U)
41217 #define S_TXCPRBSRST 17
41218 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
41219 #define F_TXCPRBSRST V_TXCPRBSRST(1U)
41221 #define S_TXCPRBSEN 16
41222 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
41223 #define F_TXCPRBSEN V_TXCPRBSEN(1U)
41225 #define S_RXBPRBSRST 12
41226 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
41227 #define F_RXBPRBSRST V_RXBPRBSRST(1U)
41229 #define S_RXBPRBSEN 11
41230 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
41231 #define F_RXBPRBSEN V_RXBPRBSEN(1U)
41233 #define S_RXBPRBSFRCERR 10
41234 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
41235 #define F_RXBPRBSFRCERR V_RXBPRBSFRCERR(1U)
41237 #define S_TXBPRBSRST 9
41238 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
41239 #define F_TXBPRBSRST V_TXBPRBSRST(1U)
41241 #define S_TXBPRBSEN 8
41242 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
41243 #define F_TXBPRBSEN V_TXBPRBSEN(1U)
41245 #define S_RXAPRBSRST 4
41246 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
41247 #define F_RXAPRBSRST V_RXAPRBSRST(1U)
41249 #define S_RXAPRBSEN 3
41250 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
41251 #define F_RXAPRBSEN V_RXAPRBSEN(1U)
41253 #define S_RXAPRBSFRCERR 2
41254 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
41255 #define F_RXAPRBSFRCERR V_RXAPRBSFRCERR(1U)
41257 #define S_TXAPRBSRST 1
41258 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
41259 #define F_TXAPRBSRST V_TXAPRBSRST(1U)
41261 #define S_TXAPRBSEN 0
41262 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
41263 #define F_TXAPRBSEN V_TXAPRBSEN(1U)
41265 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
41267 #define S_RXDDATASYNC 23
41268 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
41269 #define F_RXDDATASYNC V_RXDDATASYNC(1U)
41271 #define S_RXCDATASYNC 22
41272 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
41273 #define F_RXCDATASYNC V_RXCDATASYNC(1U)
41275 #define S_RXBDATASYNC 21
41276 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
41277 #define F_RXBDATASYNC V_RXBDATASYNC(1U)
41279 #define S_RXADATASYNC 20
41280 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
41281 #define F_RXADATASYNC V_RXADATASYNC(1U)
41283 #define S_RXDEARLYIN 19
41284 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
41285 #define F_RXDEARLYIN V_RXDEARLYIN(1U)
41287 #define S_RXDLATEIN 18
41288 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
41289 #define F_RXDLATEIN V_RXDLATEIN(1U)
41291 #define S_RXDPHSLOCK 17
41292 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
41293 #define F_RXDPHSLOCK V_RXDPHSLOCK(1U)
41295 #define S_RXDPHSDNIN 16
41296 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
41297 #define F_RXDPHSDNIN V_RXDPHSDNIN(1U)
41299 #define S_RXDPHSUPIN 15
41300 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
41301 #define F_RXDPHSUPIN V_RXDPHSUPIN(1U)
41303 #define S_RXCEARLYIN 14
41304 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
41305 #define F_RXCEARLYIN V_RXCEARLYIN(1U)
41307 #define S_RXCLATEIN 13
41308 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
41309 #define F_RXCLATEIN V_RXCLATEIN(1U)
41311 #define S_RXCPHSLOCK 12
41312 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
41313 #define F_RXCPHSLOCK V_RXCPHSLOCK(1U)
41315 #define S_RXCPHSDNIN 11
41316 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
41317 #define F_RXCPHSDNIN V_RXCPHSDNIN(1U)
41319 #define S_RXCPHSUPIN 10
41320 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
41321 #define F_RXCPHSUPIN V_RXCPHSUPIN(1U)
41323 #define S_RXBEARLYIN 9
41324 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
41325 #define F_RXBEARLYIN V_RXBEARLYIN(1U)
41327 #define S_RXBLATEIN 8
41328 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
41329 #define F_RXBLATEIN V_RXBLATEIN(1U)
41331 #define S_RXBPHSLOCK 7
41332 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
41333 #define F_RXBPHSLOCK V_RXBPHSLOCK(1U)
41335 #define S_RXBPHSDNIN 6
41336 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
41337 #define F_RXBPHSDNIN V_RXBPHSDNIN(1U)
41339 #define S_RXBPHSUPIN 5
41340 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
41341 #define F_RXBPHSUPIN V_RXBPHSUPIN(1U)
41343 #define S_RXAEARLYIN 4
41344 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
41345 #define F_RXAEARLYIN V_RXAEARLYIN(1U)
41347 #define S_RXALATEIN 3
41348 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
41349 #define F_RXALATEIN V_RXALATEIN(1U)
41351 #define S_RXAPHSLOCK 2
41352 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
41353 #define F_RXAPHSLOCK V_RXAPHSLOCK(1U)
41355 #define S_RXAPHSDNIN 1
41356 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
41357 #define F_RXAPHSDNIN V_RXAPHSDNIN(1U)
41359 #define S_RXAPHSUPIN 0
41360 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
41361 #define F_RXAPHSUPIN V_RXAPHSUPIN(1U)
41363 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
41365 #define S_RXDPRBSSYNC 15
41366 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
41367 #define F_RXDPRBSSYNC V_RXDPRBSSYNC(1U)
41369 #define S_RXCPRBSSYNC 14
41370 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
41371 #define F_RXCPRBSSYNC V_RXCPRBSSYNC(1U)
41373 #define S_RXBPRBSSYNC 13
41374 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
41375 #define F_RXBPRBSSYNC V_RXBPRBSSYNC(1U)
41377 #define S_RXAPRBSSYNC 12
41378 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
41379 #define F_RXAPRBSSYNC V_RXAPRBSSYNC(1U)
41381 #define S_RXDPRBSERR 11
41382 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
41383 #define F_RXDPRBSERR V_RXDPRBSERR(1U)
41385 #define S_RXCPRBSERR 10
41386 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
41387 #define F_RXCPRBSERR V_RXCPRBSERR(1U)
41389 #define S_RXBPRBSERR 9
41390 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
41391 #define F_RXBPRBSERR V_RXBPRBSERR(1U)
41393 #define S_RXAPRBSERR 8
41394 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
41395 #define F_RXAPRBSERR V_RXAPRBSERR(1U)
41397 #define S_RXDSIGDET 7
41398 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
41399 #define F_RXDSIGDET V_RXDSIGDET(1U)
41401 #define S_RXCSIGDET 6
41402 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
41403 #define F_RXCSIGDET V_RXCSIGDET(1U)
41405 #define S_RXBSIGDET 5
41406 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
41407 #define F_RXBSIGDET V_RXBSIGDET(1U)
41409 #define S_RXASIGDET 4
41410 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
41411 #define F_RXASIGDET V_RXASIGDET(1U)
41413 #define S_HSSPLLLOCK 1
41414 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
41415 #define F_HSSPLLLOCK V_HSSPLLLOCK(1U)
41417 #define S_HSSPRTREADY 0
41418 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
41419 #define F_HSSPRTREADY V_HSSPRTREADY(1U)
41421 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
41423 #define S_SENDPAUSE 2
41424 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
41425 #define F_SENDPAUSE V_SENDPAUSE(1U)
41427 #define S_SENDZEROPAUSE 1
41428 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
41429 #define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U)
41431 #define S_XGM_TXEN 0
41432 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
41433 #define F_XGM_TXEN V_XGM_TXEN(1U)
41435 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
41438 #define M_CRCCAL 0x3U
41439 #define V_CRCCAL(x) ((x) << S_CRCCAL)
41440 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
41442 #define S_DISDEFIDLECNT 7
41443 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
41444 #define F_DISDEFIDLECNT V_DISDEFIDLECNT(1U)
41446 #define S_DECAVGTXIPG 6
41447 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
41448 #define F_DECAVGTXIPG V_DECAVGTXIPG(1U)
41450 #define S_UNIDIRTXEN 5
41451 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
41452 #define F_UNIDIRTXEN V_UNIDIRTXEN(1U)
41454 #define S_CFGCLKSPEED 2
41455 #define M_CFGCLKSPEED 0x7U
41456 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
41457 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
41459 #define S_STRETCHMODE 1
41460 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
41461 #define F_STRETCHMODE V_STRETCHMODE(1U)
41463 #define S_TXPAUSEEN 0
41464 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
41465 #define F_TXPAUSEEN V_TXPAUSEEN(1U)
41467 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
41469 #define S_TXPAUSEQUANTA 0
41470 #define M_TXPAUSEQUANTA 0xffffU
41471 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
41472 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
41474 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
41475 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
41477 #define S_RXCRCCAL 16
41478 #define M_RXCRCCAL 0x3U
41479 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
41480 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
41482 #define S_STATLOCALFAULT 15
41483 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
41484 #define F_STATLOCALFAULT V_STATLOCALFAULT(1U)
41486 #define S_STATREMOTEFAULT 14
41487 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
41488 #define F_STATREMOTEFAULT V_STATREMOTEFAULT(1U)
41490 #define S_LENERRFRAMEDIS 13
41491 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
41492 #define F_LENERRFRAMEDIS V_LENERRFRAMEDIS(1U)
41494 #define S_CON802_3PREAMBLE 12
41495 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
41496 #define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U)
41498 #define S_ENNON802_3PREAMBLE 11
41499 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
41500 #define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U)
41502 #define S_COPYPREAMBLE 10
41503 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
41504 #define F_COPYPREAMBLE V_COPYPREAMBLE(1U)
41506 #define S_DISPAUSEFRAMES 9
41507 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
41508 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
41510 #define S_EN1536BFRAMES 8
41511 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
41512 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
41514 #define S_ENJUMBO 7
41515 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
41516 #define F_ENJUMBO V_ENJUMBO(1U)
41519 #define V_RMFCS(x) ((x) << S_RMFCS)
41520 #define F_RMFCS V_RMFCS(1U)
41522 #define S_DISNONVLAN 5
41523 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
41524 #define F_DISNONVLAN V_DISNONVLAN(1U)
41526 #define S_ENEXTMATCH 4
41527 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
41528 #define F_ENEXTMATCH V_ENEXTMATCH(1U)
41530 #define S_ENHASHUCAST 3
41531 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
41532 #define F_ENHASHUCAST V_ENHASHUCAST(1U)
41534 #define S_ENHASHMCAST 2
41535 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
41536 #define F_ENHASHMCAST V_ENHASHMCAST(1U)
41538 #define S_DISBCAST 1
41539 #define V_DISBCAST(x) ((x) << S_DISBCAST)
41540 #define F_DISBCAST V_DISBCAST(1U)
41542 #define S_COPYALLFRAMES 0
41543 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
41544 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
41546 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
41547 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
41548 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
41549 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
41551 #define S_ADDRESS_HIGH 0
41552 #define M_ADDRESS_HIGH 0xffffU
41553 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
41554 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
41556 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
41557 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
41558 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
41559 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
41560 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
41561 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
41562 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
41563 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
41564 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
41565 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
41566 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
41567 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
41568 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
41569 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
41570 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
41572 #define S_ENTYPEMATCH 31
41573 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
41574 #define F_ENTYPEMATCH V_ENTYPEMATCH(1U)
41577 #define M_TYPE 0xffffU
41578 #define V_TYPE(x) ((x) << S_TYPE)
41579 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
41581 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
41582 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
41583 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
41584 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
41586 #define S_XGMIIEXTINT 10
41587 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
41588 #define F_XGMIIEXTINT V_XGMIIEXTINT(1U)
41590 #define S_LINKFAULTCHANGE 9
41591 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
41592 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U)
41594 #define S_PHYFRAMECOMPLETE 8
41595 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
41596 #define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U)
41598 #define S_PAUSEFRAMETXMT 7
41599 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
41600 #define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U)
41602 #define S_PAUSECNTRTIMEOUT 6
41603 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
41604 #define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U)
41606 #define S_NON0PAUSERCVD 5
41607 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
41608 #define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U)
41610 #define S_STATOFLOW 4
41611 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
41612 #define F_STATOFLOW V_STATOFLOW(1U)
41614 #define S_TXERRFIFO 3
41615 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
41616 #define F_TXERRFIFO V_TXERRFIFO(1U)
41618 #define S_TXUFLOW 2
41619 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
41620 #define F_TXUFLOW V_TXUFLOW(1U)
41622 #define S_FRAMETXMT 1
41623 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
41624 #define F_FRAMETXMT V_FRAMETXMT(1U)
41626 #define S_FRAMERCVD 0
41627 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
41628 #define F_FRAMERCVD V_FRAMERCVD(1U)
41630 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
41631 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
41632 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
41633 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
41635 #define S_CURPAUSETIMER 0
41636 #define M_CURPAUSETIMER 0xffffU
41637 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
41638 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
41640 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
41642 #define S_READSNPSHOT 4
41643 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
41644 #define F_READSNPSHOT V_READSNPSHOT(1U)
41646 #define S_TAKESNPSHOT 3
41647 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
41648 #define F_TAKESNPSHOT V_TAKESNPSHOT(1U)
41650 #define S_CLRSTATS 2
41651 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
41652 #define F_CLRSTATS V_CLRSTATS(1U)
41654 #define S_INCRSTATS 1
41655 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
41656 #define F_INCRSTATS V_INCRSTATS(1U)
41658 #define S_ENTESTMODEWR 0
41659 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
41660 #define F_ENTESTMODEWR V_ENTESTMODEWR(1U)
41662 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
41664 #define S_FRAMETYPE 30
41665 #define M_FRAMETYPE 0x3U
41666 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
41667 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
41669 #define S_OPERATION 28
41670 #define M_OPERATION 0x3U
41671 #define V_OPERATION(x) ((x) << S_OPERATION)
41672 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
41674 #define S_PORTADDR 23
41675 #define M_PORTADDR 0x1fU
41676 #define V_PORTADDR(x) ((x) << S_PORTADDR)
41677 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
41679 #define S_DEVADDR 18
41680 #define M_DEVADDR 0x1fU
41681 #define V_DEVADDR(x) ((x) << S_DEVADDR)
41682 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
41685 #define M_RESRV 0x3U
41686 #define V_RESRV(x) ((x) << S_RESRV)
41687 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
41690 #define M_DATA 0xffffU
41691 #define V_DATA(x) ((x) << S_DATA)
41692 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
41694 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
41696 #define S_MODULEID 16
41697 #define M_MODULEID 0xffffU
41698 #define V_MODULEID(x) ((x) << S_MODULEID)
41699 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
41701 #define S_MODULEREV 0
41702 #define M_MODULEREV 0xffffU
41703 #define V_MODULEREV(x) ((x) << S_MODULEREV)
41704 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
41706 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
41707 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
41709 #define S_TXBYTES_HIGH 0
41710 #define M_TXBYTES_HIGH 0x1fffU
41711 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
41712 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
41714 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
41715 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
41717 #define S_TXFRAMES_HIGH 0
41718 #define M_TXFRAMES_HIGH 0xfU
41719 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
41720 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
41722 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
41723 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
41724 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
41725 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
41726 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
41727 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
41728 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
41729 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
41730 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
41731 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
41732 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
41733 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
41734 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
41736 #define S_RXBYTES_HIGH 0
41737 #define M_RXBYTES_HIGH 0x1fffU
41738 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
41739 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
41741 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
41742 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
41744 #define S_RXFRAMES_HIGH 0
41745 #define M_RXFRAMES_HIGH 0xfU
41746 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
41747 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
41749 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
41750 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
41751 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
41753 #define S_RXPAUSEFRAMES 0
41754 #define M_RXPAUSEFRAMES 0xffffU
41755 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
41756 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
41758 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
41759 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
41760 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
41761 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
41762 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
41763 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
41764 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
41765 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
41767 #define S_RXSHORTFRAMES 0
41768 #define M_RXSHORTFRAMES 0xffffU
41769 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
41770 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
41772 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
41774 #define S_RXOVERSIZEFRAMES 0
41775 #define M_RXOVERSIZEFRAMES 0xffffU
41776 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
41777 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
41779 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
41781 #define S_RXJABBERFRAMES 0
41782 #define M_RXJABBERFRAMES 0xffffU
41783 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
41784 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
41786 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
41788 #define S_RXCRCERRFRAMES 0
41789 #define M_RXCRCERRFRAMES 0xffffU
41790 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
41791 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
41793 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
41795 #define S_RXLENGTHERRFRAMES 0
41796 #define M_RXLENGTHERRFRAMES 0xffffU
41797 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
41798 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
41800 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
41802 #define S_RXSYMCODEERRFRAMES 0
41803 #define M_RXSYMCODEERRFRAMES 0xffffU
41804 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
41805 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
41807 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
41809 #define S_POLARITY_INV_RX 8
41810 #define M_POLARITY_INV_RX 0xfU
41811 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
41812 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
41814 #define S_POLARITY_INV_TX 4
41815 #define M_POLARITY_INV_TX 0xfU
41816 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
41817 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
41819 #define S_TEST_SEL 2
41820 #define M_TEST_SEL 0x3U
41821 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
41822 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
41824 #define S_TEST_EN 0
41825 #define V_TEST_EN(x) ((x) << S_TEST_EN)
41826 #define F_TEST_EN V_TEST_EN(1U)
41828 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
41830 #define S_DECODE_ERROR 12
41831 #define M_DECODE_ERROR 0xffU
41832 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
41833 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
41835 #define S_LANE3_CTC_STATUS 11
41836 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
41837 #define F_LANE3_CTC_STATUS V_LANE3_CTC_STATUS(1U)
41839 #define S_LANE2_CTC_STATUS 10
41840 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
41841 #define F_LANE2_CTC_STATUS V_LANE2_CTC_STATUS(1U)
41843 #define S_LANE1_CTC_STATUS 9
41844 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
41845 #define F_LANE1_CTC_STATUS V_LANE1_CTC_STATUS(1U)
41847 #define S_LANE0_CTC_STATUS 8
41848 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
41849 #define F_LANE0_CTC_STATUS V_LANE0_CTC_STATUS(1U)
41851 #define S_ALIGN_STATUS 4
41852 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
41853 #define F_ALIGN_STATUS V_ALIGN_STATUS(1U)
41855 #define S_LANE3_SYNC_STATUS 3
41856 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
41857 #define F_LANE3_SYNC_STATUS V_LANE3_SYNC_STATUS(1U)
41859 #define S_LANE2_SYNC_STATUS 2
41860 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
41861 #define F_LANE2_SYNC_STATUS V_LANE2_SYNC_STATUS(1U)
41863 #define S_LANE1_SYNC_STATUS 1
41864 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
41865 #define F_LANE1_SYNC_STATUS V_LANE1_SYNC_STATUS(1U)
41867 #define S_LANE0_SYNC_STATUS 0
41868 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
41869 #define F_LANE0_SYNC_STATUS V_LANE0_SYNC_STATUS(1U)
41871 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
41873 #define S_RX_CLK_SPEED 7
41874 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
41875 #define F_RX_CLK_SPEED V_RX_CLK_SPEED(1U)
41877 #define S_SCRBYPASS 6
41878 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
41879 #define F_SCRBYPASS V_SCRBYPASS(1U)
41881 #define S_FECERRINDEN 5
41882 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
41883 #define F_FECERRINDEN V_FECERRINDEN(1U)
41886 #define V_FECEN(x) ((x) << S_FECEN)
41887 #define F_FECEN V_FECEN(1U)
41889 #define S_TESTSEL 2
41890 #define M_TESTSEL 0x3U
41891 #define V_TESTSEL(x) ((x) << S_TESTSEL)
41892 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
41894 #define S_SCRLOOPEN 1
41895 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
41896 #define F_SCRLOOPEN V_SCRLOOPEN(1U)
41898 #define S_XGMIILOOPEN 0
41899 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
41900 #define F_XGMIILOOPEN V_XGMIILOOPEN(1U)
41902 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
41904 #define S_TX_PRBS9_EN 4
41905 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
41906 #define F_TX_PRBS9_EN V_TX_PRBS9_EN(1U)
41908 #define S_TX_PRBS31_EN 3
41909 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
41910 #define F_TX_PRBS31_EN V_TX_PRBS31_EN(1U)
41912 #define S_TX_TST_DAT_SEL 2
41913 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
41914 #define F_TX_TST_DAT_SEL V_TX_TST_DAT_SEL(1U)
41916 #define S_TX_TST_SEL 1
41917 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
41918 #define F_TX_TST_SEL V_TX_TST_SEL(1U)
41920 #define S_TX_TST_EN 0
41921 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
41922 #define F_TX_TST_EN V_TX_TST_EN(1U)
41924 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
41925 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
41927 #define S_SEEDA_UPPER 0
41928 #define M_SEEDA_UPPER 0x3ffffffU
41929 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
41930 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
41932 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
41933 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
41935 #define S_SEEDB_UPPER 0
41936 #define M_SEEDB_UPPER 0x3ffffffU
41937 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
41938 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
41940 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
41942 #define S_TPTER_CNT_RST 7
41943 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
41944 #define F_TPTER_CNT_RST V_TPTER_CNT_RST(1U)
41946 #define S_TEST_CNT_125US 6
41947 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
41948 #define F_TEST_CNT_125US V_TEST_CNT_125US(1U)
41950 #define S_TEST_CNT_PRE 5
41951 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
41952 #define F_TEST_CNT_PRE V_TEST_CNT_PRE(1U)
41954 #define S_BER_CNT_RST 4
41955 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
41956 #define F_BER_CNT_RST V_BER_CNT_RST(1U)
41958 #define S_ERR_BLK_CNT_RST 3
41959 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
41960 #define F_ERR_BLK_CNT_RST V_ERR_BLK_CNT_RST(1U)
41962 #define S_RX_PRBS31_EN 2
41963 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
41964 #define F_RX_PRBS31_EN V_RX_PRBS31_EN(1U)
41966 #define S_RX_TST_DAT_SEL 1
41967 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
41968 #define F_RX_TST_DAT_SEL V_RX_TST_DAT_SEL(1U)
41970 #define S_RX_TST_EN 0
41971 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
41972 #define F_RX_TST_EN V_RX_TST_EN(1U)
41974 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
41976 #define S_ERR_BLK_CNT 16
41977 #define M_ERR_BLK_CNT 0xffU
41978 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
41979 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
41981 #define S_BER_COUNT 8
41982 #define M_BER_COUNT 0x3fU
41983 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
41984 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
41987 #define V_HI_BER(x) ((x) << S_HI_BER)
41988 #define F_HI_BER V_HI_BER(1U)
41990 #define S_RX_FAULT 1
41991 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
41992 #define F_RX_FAULT V_RX_FAULT(1U)
41994 #define S_TX_FAULT 0
41995 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
41996 #define F_TX_FAULT V_TX_FAULT(1U)
41998 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
42000 #define S_TPT_ERR_CNT 0
42001 #define M_TPT_ERR_CNT 0xffffU
42002 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
42003 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
42005 #define A_XGMAC_PORT_AN_CONTROL 0x1600
42007 #define S_SOFT_RESET 15
42008 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
42009 #define F_SOFT_RESET V_SOFT_RESET(1U)
42011 #define S_AN_ENABLE 12
42012 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
42013 #define F_AN_ENABLE V_AN_ENABLE(1U)
42015 #define S_RESTART_AN 9
42016 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
42017 #define F_RESTART_AN V_RESTART_AN(1U)
42019 #define A_XGMAC_PORT_AN_STATUS 0x1604
42021 #define S_NONCER_MATCH 31
42022 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
42023 #define F_NONCER_MATCH V_NONCER_MATCH(1U)
42025 #define S_PARALLEL_DET_FAULT 9
42026 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
42027 #define F_PARALLEL_DET_FAULT V_PARALLEL_DET_FAULT(1U)
42029 #define S_PAGE_RECEIVED 6
42030 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
42031 #define F_PAGE_RECEIVED V_PAGE_RECEIVED(1U)
42033 #define S_AN_COMPLETE 5
42034 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
42035 #define F_AN_COMPLETE V_AN_COMPLETE(1U)
42037 #define S_STAT_REMFAULT 4
42038 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
42039 #define F_STAT_REMFAULT V_STAT_REMFAULT(1U)
42041 #define S_AN_ABILITY 3
42042 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
42043 #define F_AN_ABILITY V_AN_ABILITY(1U)
42045 #define S_LINK_STATUS 2
42046 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
42047 #define F_LINK_STATUS V_LINK_STATUS(1U)
42049 #define S_PARTNER_AN_ABILITY 0
42050 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
42051 #define F_PARTNER_AN_ABILITY V_PARTNER_AN_ABILITY(1U)
42053 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
42055 #define S_FEC_ENABLE 31
42056 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
42057 #define F_FEC_ENABLE V_FEC_ENABLE(1U)
42059 #define S_FEC_ABILITY 30
42060 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
42061 #define F_FEC_ABILITY V_FEC_ABILITY(1U)
42063 #define S_10GBASE_KR_CAPABLE 23
42064 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
42065 #define F_10GBASE_KR_CAPABLE V_10GBASE_KR_CAPABLE(1U)
42067 #define S_10GBASE_KX4_CAPABLE 22
42068 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
42069 #define F_10GBASE_KX4_CAPABLE V_10GBASE_KX4_CAPABLE(1U)
42071 #define S_1000BASE_KX_CAPABLE 21
42072 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
42073 #define F_1000BASE_KX_CAPABLE V_1000BASE_KX_CAPABLE(1U)
42075 #define S_TRANSMITTED_NONCE 16
42076 #define M_TRANSMITTED_NONCE 0x1fU
42077 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
42078 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
42081 #define V_NP(x) ((x) << S_NP)
42082 #define F_NP V_NP(1U)
42085 #define V_ACK(x) ((x) << S_ACK)
42086 #define F_ACK V_ACK(1U)
42088 #define S_REMOTE_FAULT 13
42089 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
42090 #define F_REMOTE_FAULT V_REMOTE_FAULT(1U)
42092 #define S_ASM_DIR 11
42093 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
42094 #define F_ASM_DIR V_ASM_DIR(1U)
42097 #define V_PAUSE(x) ((x) << S_PAUSE)
42098 #define F_PAUSE V_PAUSE(1U)
42100 #define S_ECHOED_NONCE 5
42101 #define M_ECHOED_NONCE 0x1fU
42102 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
42103 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
42105 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
42107 #define S_SELECTOR_FIELD 0
42108 #define M_SELECTOR_FIELD 0x1fU
42109 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
42110 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
42112 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
42114 #define S_NP_INFO 16
42115 #define M_NP_INFO 0xffffU
42116 #define V_NP_INFO(x) ((x) << S_NP_INFO)
42117 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
42119 #define S_NP_INDICATION 15
42120 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
42121 #define F_NP_INDICATION V_NP_INDICATION(1U)
42123 #define S_MESSAGE_PAGE 13
42124 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
42125 #define F_MESSAGE_PAGE V_MESSAGE_PAGE(1U)
42128 #define V_ACK_2(x) ((x) << S_ACK_2)
42129 #define F_ACK_2 V_ACK_2(1U)
42131 #define S_TOGGLE 11
42132 #define V_TOGGLE(x) ((x) << S_TOGGLE)
42133 #define F_TOGGLE V_TOGGLE(1U)
42135 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
42137 #define S_NP_INFO_HI 0
42138 #define M_NP_INFO_HI 0xffffU
42139 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
42140 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
42142 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
42143 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
42144 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
42146 #define S_TX_PAUSE_OKAY 6
42147 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
42148 #define F_TX_PAUSE_OKAY V_TX_PAUSE_OKAY(1U)
42150 #define S_RX_PAUSE_OKAY 5
42151 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
42152 #define F_RX_PAUSE_OKAY V_RX_PAUSE_OKAY(1U)
42154 #define S_10GBASE_KR_FEC_NEG 4
42155 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
42156 #define F_10GBASE_KR_FEC_NEG V_10GBASE_KR_FEC_NEG(1U)
42158 #define S_10GBASE_KR_NEG 3
42159 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
42160 #define F_10GBASE_KR_NEG V_10GBASE_KR_NEG(1U)
42162 #define S_10GBASE_KX4_NEG 2
42163 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
42164 #define F_10GBASE_KX4_NEG V_10GBASE_KX4_NEG(1U)
42166 #define S_1000BASE_KX_NEG 1
42167 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
42168 #define F_1000BASE_KX_NEG V_1000BASE_KX_NEG(1U)
42170 #define S_BP_AN_ABILITY 0
42171 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
42172 #define F_BP_AN_ABILITY V_BP_AN_ABILITY(1U)
42174 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
42176 #define S_BYPASS_LFSR 15
42177 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
42178 #define F_BYPASS_LFSR V_BYPASS_LFSR(1U)
42180 #define S_LFSR_INIT 0
42181 #define M_LFSR_INIT 0x7fffU
42182 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
42183 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
42185 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
42187 #define S_NP_FROM_LP 3
42188 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
42189 #define F_NP_FROM_LP V_NP_FROM_LP(1U)
42191 #define S_PARALLELDETFAULTINT 2
42192 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
42193 #define F_PARALLELDETFAULTINT V_PARALLELDETFAULTINT(1U)
42195 #define S_BP_FROM_LP 1
42196 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
42197 #define F_BP_FROM_LP V_BP_FROM_LP(1U)
42199 #define S_PCS_AN_COMPLETE 0
42200 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
42201 #define F_PCS_AN_COMPLETE V_PCS_AN_COMPLETE(1U)
42203 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
42205 #define S_GENERIC_TIMEOUT 0
42206 #define M_GENERIC_TIMEOUT 0x7fffffU
42207 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
42208 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
42210 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
42212 #define S_BREAK_LINK_TIMEOUT 0
42213 #define M_BREAK_LINK_TIMEOUT 0xffffffU
42214 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
42215 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
42217 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
42219 #define S_MODULE_ID 16
42220 #define M_MODULE_ID 0xffffU
42221 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
42222 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
42224 #define S_MODULE_REVISION 0
42225 #define M_MODULE_REVISION 0xffffU
42226 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
42227 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
42229 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
42231 #define S_RXREQ_CPRE 13
42232 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
42233 #define F_RXREQ_CPRE V_RXREQ_CPRE(1U)
42235 #define S_RXREQ_CINIT 12
42236 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
42237 #define F_RXREQ_CINIT V_RXREQ_CINIT(1U)
42239 #define S_RXREQ_C0 4
42240 #define M_RXREQ_C0 0x3U
42241 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
42242 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
42244 #define S_RXREQ_C1 2
42245 #define M_RXREQ_C1 0x3U
42246 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
42247 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
42249 #define S_RXREQ_C2 0
42250 #define M_RXREQ_C2 0x3U
42251 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
42252 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
42254 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
42256 #define S_RXSTAT_RDY 15
42257 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
42258 #define F_RXSTAT_RDY V_RXSTAT_RDY(1U)
42260 #define S_RXSTAT_C0 4
42261 #define M_RXSTAT_C0 0x3U
42262 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
42263 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
42265 #define S_RXSTAT_C1 2
42266 #define M_RXSTAT_C1 0x3U
42267 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
42268 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
42270 #define S_RXSTAT_C2 0
42271 #define M_RXSTAT_C2 0x3U
42272 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
42273 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
42275 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
42277 #define S_TXREQ_CPRE 13
42278 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
42279 #define F_TXREQ_CPRE V_TXREQ_CPRE(1U)
42281 #define S_TXREQ_CINIT 12
42282 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
42283 #define F_TXREQ_CINIT V_TXREQ_CINIT(1U)
42285 #define S_TXREQ_C0 4
42286 #define M_TXREQ_C0 0x3U
42287 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
42288 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
42290 #define S_TXREQ_C1 2
42291 #define M_TXREQ_C1 0x3U
42292 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
42293 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
42295 #define S_TXREQ_C2 0
42296 #define M_TXREQ_C2 0x3U
42297 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
42298 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
42300 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
42302 #define S_TXSTAT_RDY 15
42303 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
42304 #define F_TXSTAT_RDY V_TXSTAT_RDY(1U)
42306 #define S_TXSTAT_C0 4
42307 #define M_TXSTAT_C0 0x3U
42308 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
42309 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
42311 #define S_TXSTAT_C1 2
42312 #define M_TXSTAT_C1 0x3U
42313 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
42314 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
42316 #define S_TXSTAT_C2 0
42317 #define M_TXSTAT_C2 0x3U
42318 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
42319 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
42321 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
42323 #define S_MAN_DEC 4
42324 #define M_MAN_DEC 0x3U
42325 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
42326 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
42328 #define S_MANUAL_RDY 3
42329 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
42330 #define F_MANUAL_RDY V_MANUAL_RDY(1U)
42332 #define S_MWT_DISABLE 2
42333 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
42334 #define F_MWT_DISABLE V_MWT_DISABLE(1U)
42336 #define S_MDIO_OVR 1
42337 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
42338 #define F_MDIO_OVR V_MDIO_OVR(1U)
42340 #define S_STICKY_MODE 0
42341 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
42342 #define F_STICKY_MODE V_STICKY_MODE(1U)
42344 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
42346 #define S_PRBS_CHK_ERRCNT 8
42347 #define M_PRBS_CHK_ERRCNT 0xffU
42348 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
42349 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
42351 #define S_PRBS_SYNCCNT 5
42352 #define M_PRBS_SYNCCNT 0x7U
42353 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
42354 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
42356 #define S_PRBS_CHK_SYNC 4
42357 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
42358 #define F_PRBS_CHK_SYNC V_PRBS_CHK_SYNC(1U)
42360 #define S_PRBS_CHK_RST 3
42361 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
42362 #define F_PRBS_CHK_RST V_PRBS_CHK_RST(1U)
42364 #define S_PRBS_CHK_OFF 2
42365 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
42366 #define F_PRBS_CHK_OFF V_PRBS_CHK_OFF(1U)
42368 #define S_PRBS_GEN_FRCERR 1
42369 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
42370 #define F_PRBS_GEN_FRCERR V_PRBS_GEN_FRCERR(1U)
42372 #define S_PRBS_GEN_OFF 0
42373 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
42374 #define F_PRBS_GEN_OFF V_PRBS_GEN_OFF(1U)
42376 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
42378 #define S_FSM_TR_LCL 14
42379 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
42380 #define F_FSM_TR_LCL V_FSM_TR_LCL(1U)
42382 #define S_FSM_GDMRK 11
42383 #define M_FSM_GDMRK 0x7U
42384 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
42385 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
42387 #define S_FSM_BADMRK 8
42388 #define M_FSM_BADMRK 0x7U
42389 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
42390 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
42392 #define S_FSM_TR_FAIL 7
42393 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
42394 #define F_FSM_TR_FAIL V_FSM_TR_FAIL(1U)
42396 #define S_FSM_TR_ACT 6
42397 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
42398 #define F_FSM_TR_ACT V_FSM_TR_ACT(1U)
42400 #define S_FSM_FRM_LCK 5
42401 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
42402 #define F_FSM_FRM_LCK V_FSM_FRM_LCK(1U)
42404 #define S_FSM_TR_COMP 4
42405 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
42406 #define F_FSM_TR_COMP V_FSM_TR_COMP(1U)
42408 #define S_MC_RX_RDY 3
42409 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
42410 #define F_MC_RX_RDY V_MC_RX_RDY(1U)
42412 #define S_FSM_CU_DIS 2
42413 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
42414 #define F_FSM_CU_DIS V_FSM_CU_DIS(1U)
42416 #define S_FSM_TR_RST 1
42417 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
42418 #define F_FSM_TR_RST V_FSM_TR_RST(1U)
42420 #define S_FSM_TR_EN 0
42421 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
42422 #define F_FSM_TR_EN V_FSM_TR_EN(1U)
42424 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
42426 #define S_CC2FSM_STATE 13
42427 #define M_CC2FSM_STATE 0x7U
42428 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
42429 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
42431 #define S_CC1FSM_STATE 10
42432 #define M_CC1FSM_STATE 0x7U
42433 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
42434 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
42436 #define S_CC0FSM_STATE 7
42437 #define M_CC0FSM_STATE 0x7U
42438 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
42439 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
42441 #define S_FLFSM_STATE 4
42442 #define M_FLFSM_STATE 0x7U
42443 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
42444 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
42446 #define S_TFSM_STATE 0
42447 #define M_TFSM_STATE 0x7U
42448 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
42449 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
42451 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
42453 #define S_PMD_TX_DIS 0
42454 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
42455 #define F_PMD_TX_DIS V_PMD_TX_DIS(1U)
42457 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
42459 #define S_TRAINING_ENABLE 1
42460 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
42461 #define F_TRAINING_ENABLE V_TRAINING_ENABLE(1U)
42463 #define S_RESTART_TRAINING 0
42464 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
42465 #define F_RESTART_TRAINING V_RESTART_TRAINING(1U)
42467 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
42469 #define S_PMD_SIGDET 0
42470 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
42471 #define F_PMD_SIGDET V_PMD_SIGDET(1U)
42473 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
42475 #define S_TRAINING_FAILURE 3
42476 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
42477 #define F_TRAINING_FAILURE V_TRAINING_FAILURE(1U)
42479 #define S_TRAINING 2
42480 #define V_TRAINING(x) ((x) << S_TRAINING)
42481 #define F_TRAINING V_TRAINING(1U)
42483 #define S_FRAME_LOCK 1
42484 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
42485 #define F_FRAME_LOCK V_FRAME_LOCK(1U)
42487 #define S_RX_TRAINED 0
42488 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
42489 #define F_RX_TRAINED V_RX_TRAINED(1U)
42491 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
42494 #define M_BWSEL 0x3U
42495 #define V_BWSEL(x) ((x) << S_BWSEL)
42496 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
42499 #define M_RTSEL 0x3U
42500 #define V_RTSEL(x) ((x) << S_RTSEL)
42501 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
42503 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
42506 #define V_TWDP(x) ((x) << S_TWDP)
42507 #define F_TWDP V_TWDP(1U)
42510 #define V_TPGRST(x) ((x) << S_TPGRST)
42511 #define F_TPGRST V_TPGRST(1U)
42514 #define V_TPGEN(x) ((x) << S_TPGEN)
42515 #define F_TPGEN V_TPGEN(1U)
42518 #define M_TPSEL 0x7U
42519 #define V_TPSEL(x) ((x) << S_TPSEL)
42520 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
42522 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
42524 #define S_AEINVPOL 6
42525 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
42526 #define F_AEINVPOL V_AEINVPOL(1U)
42528 #define S_AESOURCE 5
42529 #define V_AESOURCE(x) ((x) << S_AESOURCE)
42530 #define F_AESOURCE V_AESOURCE(1U)
42533 #define V_EQMODE(x) ((x) << S_EQMODE)
42534 #define F_EQMODE V_EQMODE(1U)
42537 #define V_OCOEF(x) ((x) << S_OCOEF)
42538 #define F_OCOEF V_OCOEF(1U)
42540 #define S_COEFRST 2
42541 #define V_COEFRST(x) ((x) << S_COEFRST)
42542 #define F_COEFRST V_COEFRST(1U)
42545 #define V_SPEN(x) ((x) << S_SPEN)
42546 #define F_SPEN V_SPEN(1U)
42549 #define V_ALOAD(x) ((x) << S_ALOAD)
42550 #define F_ALOAD V_ALOAD(1U)
42552 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
42554 #define S_DRVOFFT 5
42555 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
42556 #define F_DRVOFFT V_DRVOFFT(1U)
42559 #define M_SLEW 0x7U
42560 #define V_SLEW(x) ((x) << S_SLEW)
42561 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
42565 #define V_FFE(x) ((x) << S_FFE)
42566 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
42568 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
42571 #define V_VLINC(x) ((x) << S_VLINC)
42572 #define F_VLINC V_VLINC(1U)
42575 #define V_VLDEC(x) ((x) << S_VLDEC)
42576 #define F_VLDEC V_VLDEC(1U)
42579 #define V_LOPWR(x) ((x) << S_LOPWR)
42580 #define F_LOPWR V_LOPWR(1U)
42583 #define V_TDMEN(x) ((x) << S_TDMEN)
42584 #define F_TDMEN V_TDMEN(1U)
42587 #define V_DCCEN(x) ((x) << S_DCCEN)
42588 #define F_DCCEN V_DCCEN(1U)
42591 #define V_VHSEL(x) ((x) << S_VHSEL)
42592 #define F_VHSEL V_VHSEL(1U)
42595 #define M_IDAC 0x3U
42596 #define V_IDAC(x) ((x) << S_IDAC)
42597 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
42599 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
42602 #define M_STBY 0xffffU
42603 #define V_STBY(x) ((x) << S_STBY)
42604 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
42606 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
42609 #define M_PON 0xffffU
42610 #define V_PON(x) ((x) << S_PON)
42611 #define G_PON(x) (((x) >> S_PON) & M_PON)
42613 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
42616 #define M_NXTT0 0xfU
42617 #define V_NXTT0(x) ((x) << S_NXTT0)
42618 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
42620 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
42623 #define M_NXTT1 0x3fU
42624 #define V_NXTT1(x) ((x) << S_NXTT1)
42625 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
42627 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
42630 #define M_NXTT2 0x1fU
42631 #define V_NXTT2(x) ((x) << S_NXTT2)
42632 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
42634 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
42637 #define M_TXPWR 0x7fU
42638 #define V_TXPWR(x) ((x) << S_TXPWR)
42639 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
42641 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
42644 #define M_TXPOL 0x7U
42645 #define V_TXPOL(x) ((x) << S_TXPOL)
42646 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
42649 #define M_NTXPOL 0x7U
42650 #define V_NTXPOL(x) ((x) << S_NTXPOL)
42651 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
42653 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
42655 #define S_CXPRESET 13
42656 #define V_CXPRESET(x) ((x) << S_CXPRESET)
42657 #define F_CXPRESET V_CXPRESET(1U)
42659 #define S_CXINIT 12
42660 #define V_CXINIT(x) ((x) << S_CXINIT)
42661 #define F_CXINIT V_CXINIT(1U)
42664 #define M_C2UPDT 0x3U
42665 #define V_C2UPDT(x) ((x) << S_C2UPDT)
42666 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
42669 #define M_C1UPDT 0x3U
42670 #define V_C1UPDT(x) ((x) << S_C1UPDT)
42671 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
42674 #define M_C0UPDT 0x3U
42675 #define V_C0UPDT(x) ((x) << S_C0UPDT)
42676 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
42678 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
42681 #define M_C2STAT 0x3U
42682 #define V_C2STAT(x) ((x) << S_C2STAT)
42683 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
42686 #define M_C1STAT 0x3U
42687 #define V_C1STAT(x) ((x) << S_C1STAT)
42688 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
42691 #define M_C0STAT 0x3U
42692 #define V_C0STAT(x) ((x) << S_C0STAT)
42693 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
42695 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
42698 #define M_NIDAC0 0x1fU
42699 #define V_NIDAC0(x) ((x) << S_NIDAC0)
42700 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
42702 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
42705 #define M_NIDAC1 0x7fU
42706 #define V_NIDAC1(x) ((x) << S_NIDAC1)
42707 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
42709 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
42712 #define M_NIDAC2 0x3fU
42713 #define V_NIDAC2(x) ((x) << S_NIDAC2)
42714 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
42716 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
42719 #define V_OPEN(x) ((x) << S_OPEN)
42720 #define F_OPEN V_OPEN(1U)
42723 #define M_OPVAL 0x1fU
42724 #define V_OPVAL(x) ((x) << S_OPVAL)
42725 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
42727 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
42730 #define M_PDAC 0x1fU
42731 #define V_PDAC(x) ((x) << S_PDAC)
42732 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
42734 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
42737 #define M_AIDAC0 0x1fU
42738 #define V_AIDAC0(x) ((x) << S_AIDAC0)
42739 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
42741 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
42744 #define M_AIDAC1 0x1fU
42745 #define V_AIDAC1(x) ((x) << S_AIDAC1)
42746 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
42748 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
42750 #define S_TXA_AIDAC2 0
42751 #define M_TXA_AIDAC2 0x1fU
42752 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
42753 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
42755 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
42758 #define M_CURSD 0x7fU
42759 #define V_CURSD(x) ((x) << S_CURSD)
42760 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
42762 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
42765 #define M_XDATA 0xffffU
42766 #define V_XDATA(x) ((x) << S_XDATA)
42767 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
42769 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
42771 #define S_EXTADDR 1
42772 #define M_EXTADDR 0x1fU
42773 #define V_EXTADDR(x) ((x) << S_EXTADDR)
42774 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
42777 #define V_XWR(x) ((x) << S_XWR)
42778 #define F_XWR V_XWR(1U)
42780 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
42781 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
42782 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
42783 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
42784 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
42785 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
42786 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
42787 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
42788 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
42789 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
42790 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
42791 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
42792 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
42793 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
42794 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
42795 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
42796 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
42797 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
42798 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
42799 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
42800 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
42801 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
42804 #define M_AIDAC2 0x3fU
42805 #define V_AIDAC2(x) ((x) << S_AIDAC2)
42806 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
42808 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
42809 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
42810 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
42813 #define M_XADDR 0xfU
42814 #define V_XADDR(x) ((x) << S_XADDR)
42815 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
42817 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
42820 #define V_BW810(x) ((x) << S_BW810)
42821 #define F_BW810 V_BW810(1U)
42824 #define V_AUXCLK(x) ((x) << S_AUXCLK)
42825 #define F_AUXCLK V_AUXCLK(1U)
42828 #define M_DMSEL 0x7U
42829 #define V_DMSEL(x) ((x) << S_DMSEL)
42830 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
42832 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
42834 #define S_RCLKEN 15
42835 #define V_RCLKEN(x) ((x) << S_RCLKEN)
42836 #define F_RCLKEN V_RCLKEN(1U)
42839 #define M_RRATE 0x3U
42840 #define V_RRATE(x) ((x) << S_RRATE)
42841 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
42843 #define S_LBFRCERROR 10
42844 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
42845 #define F_LBFRCERROR V_LBFRCERROR(1U)
42847 #define S_LBERROR 9
42848 #define V_LBERROR(x) ((x) << S_LBERROR)
42849 #define F_LBERROR V_LBERROR(1U)
42852 #define V_LBSYNC(x) ((x) << S_LBSYNC)
42853 #define F_LBSYNC V_LBSYNC(1U)
42855 #define S_FDWRAPCLK 7
42856 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
42857 #define F_FDWRAPCLK V_FDWRAPCLK(1U)
42860 #define V_FDWRAP(x) ((x) << S_FDWRAP)
42861 #define F_FDWRAP V_FDWRAP(1U)
42864 #define V_PRST(x) ((x) << S_PRST)
42865 #define F_PRST V_PRST(1U)
42868 #define V_PCHKEN(x) ((x) << S_PCHKEN)
42869 #define F_PCHKEN V_PCHKEN(1U)
42871 #define S_PRBSSEL 0
42872 #define M_PRBSSEL 0x7U
42873 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
42874 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
42876 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
42878 #define S_FTHROT 12
42879 #define M_FTHROT 0xfU
42880 #define V_FTHROT(x) ((x) << S_FTHROT)
42881 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
42883 #define S_RTHROT 11
42884 #define V_RTHROT(x) ((x) << S_RTHROT)
42885 #define F_RTHROT V_RTHROT(1U)
42887 #define S_FILTCTL 7
42888 #define M_FILTCTL 0xfU
42889 #define V_FILTCTL(x) ((x) << S_FILTCTL)
42890 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
42893 #define M_RSRVO 0x3U
42894 #define V_RSRVO(x) ((x) << S_RSRVO)
42895 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
42898 #define V_EXTEL(x) ((x) << S_EXTEL)
42899 #define F_EXTEL V_EXTEL(1U)
42901 #define S_RSTONSTUCK 3
42902 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
42903 #define F_RSTONSTUCK V_RSTONSTUCK(1U)
42905 #define S_FREEZEFW 2
42906 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
42907 #define F_FREEZEFW V_FREEZEFW(1U)
42909 #define S_RESETFW 1
42910 #define V_RESETFW(x) ((x) << S_RESETFW)
42911 #define F_RESETFW V_RESETFW(1U)
42913 #define S_SSCENABLE 0
42914 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
42915 #define F_SSCENABLE V_SSCENABLE(1U)
42917 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
42920 #define V_RSNP(x) ((x) << S_RSNP)
42921 #define F_RSNP V_RSNP(1U)
42924 #define V_TSOEN(x) ((x) << S_TSOEN)
42925 #define F_TSOEN V_TSOEN(1U)
42928 #define V_OFFEN(x) ((x) << S_OFFEN)
42929 #define F_OFFEN V_OFFEN(1U)
42932 #define M_TMSCAL 0x3U
42933 #define V_TMSCAL(x) ((x) << S_TMSCAL)
42934 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
42937 #define V_APADJ(x) ((x) << S_APADJ)
42938 #define F_APADJ V_APADJ(1U)
42941 #define V_RSEL(x) ((x) << S_RSEL)
42942 #define F_RSEL V_RSEL(1U)
42945 #define M_PHOFFS 0x1fU
42946 #define V_PHOFFS(x) ((x) << S_PHOFFS)
42947 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
42949 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
42952 #define M_ROT0A 0x3fU
42953 #define V_ROT0A(x) ((x) << S_ROT0A)
42954 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
42956 #define S_RTSEL_SNAPSHOT 0
42957 #define M_RTSEL_SNAPSHOT 0x3fU
42958 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
42959 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
42961 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
42964 #define M_ROT90 0x3fU
42965 #define V_ROT90(x) ((x) << S_ROT90)
42966 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
42968 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
42970 #define S_RCALER 15
42971 #define V_RCALER(x) ((x) << S_RCALER)
42972 #define F_RCALER V_RCALER(1U)
42974 #define S_RAOOFF 10
42975 #define M_RAOOFF 0x1fU
42976 #define V_RAOOFF(x) ((x) << S_RAOOFF)
42977 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
42980 #define M_RAEOFF 0x1fU
42981 #define V_RAEOFF(x) ((x) << S_RAEOFF)
42982 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
42985 #define M_RDOFF 0x1fU
42986 #define V_RDOFF(x) ((x) << S_RDOFF)
42987 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
42989 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
42991 #define S_SIGNSD 13
42992 #define M_SIGNSD 0x3U
42993 #define V_SIGNSD(x) ((x) << S_SIGNSD)
42994 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
42997 #define M_DACSD 0x1fU
42998 #define V_DACSD(x) ((x) << S_DACSD)
42999 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
43002 #define V_SDPDN(x) ((x) << S_SDPDN)
43003 #define F_SDPDN V_SDPDN(1U)
43006 #define V_SIGDET(x) ((x) << S_SIGDET)
43007 #define F_SIGDET V_SIGDET(1U)
43010 #define M_SDLVL 0x1fU
43011 #define V_SDLVL(x) ((x) << S_SDLVL)
43012 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
43014 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
43016 #define S_REQCMP 15
43017 #define V_REQCMP(x) ((x) << S_REQCMP)
43018 #define F_REQCMP V_REQCMP(1U)
43020 #define S_DFEREQ 14
43021 #define V_DFEREQ(x) ((x) << S_DFEREQ)
43022 #define F_DFEREQ V_DFEREQ(1U)
43025 #define V_SPCEN(x) ((x) << S_SPCEN)
43026 #define F_SPCEN V_SPCEN(1U)
43028 #define S_GATEEN 12
43029 #define V_GATEEN(x) ((x) << S_GATEEN)
43030 #define F_GATEEN V_GATEEN(1U)
43033 #define M_SPIFMT 0x7U
43034 #define V_SPIFMT(x) ((x) << S_SPIFMT)
43035 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
43038 #define M_DFEPWR 0x7U
43039 #define V_DFEPWR(x) ((x) << S_DFEPWR)
43040 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
43043 #define V_STNDBY(x) ((x) << S_STNDBY)
43044 #define F_STNDBY V_STNDBY(1U)
43047 #define V_FRCH(x) ((x) << S_FRCH)
43048 #define F_FRCH V_FRCH(1U)
43051 #define V_NONRND(x) ((x) << S_NONRND)
43052 #define F_NONRND V_NONRND(1U)
43055 #define V_NONRNF(x) ((x) << S_NONRNF)
43056 #define F_NONRNF V_NONRNF(1U)
43059 #define V_FSTLCK(x) ((x) << S_FSTLCK)
43060 #define F_FSTLCK V_FSTLCK(1U)
43063 #define V_DFERST(x) ((x) << S_DFERST)
43064 #define F_DFERST V_DFERST(1U)
43066 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
43069 #define M_ESAMP 0xffU
43070 #define V_ESAMP(x) ((x) << S_ESAMP)
43071 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
43074 #define M_DSAMP 0xffU
43075 #define V_DSAMP(x) ((x) << S_DSAMP)
43076 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
43078 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
43081 #define M_SMODE 0xfU
43082 #define V_SMODE(x) ((x) << S_SMODE)
43083 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
43086 #define V_ADCORR(x) ((x) << S_ADCORR)
43087 #define F_ADCORR V_ADCORR(1U)
43089 #define S_TRAINEN 6
43090 #define V_TRAINEN(x) ((x) << S_TRAINEN)
43091 #define F_TRAINEN V_TRAINEN(1U)
43094 #define M_ASAMPQ 0x7U
43095 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
43096 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
43099 #define M_ASAMP 0x7U
43100 #define V_ASAMP(x) ((x) << S_ASAMP)
43101 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
43103 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
43106 #define M_POLE 0x3U
43107 #define V_POLE(x) ((x) << S_POLE)
43108 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
43111 #define M_PEAK 0x7U
43112 #define V_PEAK(x) ((x) << S_PEAK)
43113 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
43116 #define M_VOFFSN 0x3U
43117 #define V_VOFFSN(x) ((x) << S_VOFFSN)
43118 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
43121 #define M_VOFFA 0x3fU
43122 #define V_VOFFA(x) ((x) << S_VOFFA)
43123 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
43125 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
43127 #define S_SHORTV 10
43128 #define V_SHORTV(x) ((x) << S_SHORTV)
43129 #define F_SHORTV V_SHORTV(1U)
43132 #define M_VGAIN 0xfU
43133 #define V_VGAIN(x) ((x) << S_VGAIN)
43134 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
43136 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
43139 #define V_HBND1(x) ((x) << S_HBND1)
43140 #define F_HBND1 V_HBND1(1U)
43143 #define V_HBND0(x) ((x) << S_HBND0)
43144 #define F_HBND0 V_HBND0(1U)
43147 #define V_VLCKD(x) ((x) << S_VLCKD)
43148 #define F_VLCKD V_VLCKD(1U)
43151 #define V_VLCKDF(x) ((x) << S_VLCKDF)
43152 #define F_VLCKDF V_VLCKDF(1U)
43155 #define M_AMAXT 0x7fU
43156 #define V_AMAXT(x) ((x) << S_AMAXT)
43157 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
43159 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
43162 #define M_D01SN 0x3U
43163 #define V_D01SN(x) ((x) << S_D01SN)
43164 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
43167 #define M_D01AMP 0x1fU
43168 #define V_D01AMP(x) ((x) << S_D01AMP)
43169 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
43172 #define M_D00SN 0x3U
43173 #define V_D00SN(x) ((x) << S_D00SN)
43174 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
43177 #define M_D00AMP 0x1fU
43178 #define V_D00AMP(x) ((x) << S_D00AMP)
43179 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
43181 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
43184 #define M_D11SN 0x3U
43185 #define V_D11SN(x) ((x) << S_D11SN)
43186 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
43189 #define M_D11AMP 0x1fU
43190 #define V_D11AMP(x) ((x) << S_D11AMP)
43191 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
43194 #define M_D10SN 0x3U
43195 #define V_D10SN(x) ((x) << S_D10SN)
43196 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
43199 #define M_D10AMP 0x1fU
43200 #define V_D10AMP(x) ((x) << S_D10AMP)
43201 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
43203 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
43206 #define M_E1SN 0x3U
43207 #define V_E1SN(x) ((x) << S_E1SN)
43208 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
43211 #define M_E1AMP 0x1fU
43212 #define V_E1AMP(x) ((x) << S_E1AMP)
43213 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
43216 #define M_E0SN 0x3U
43217 #define V_E0SN(x) ((x) << S_E0SN)
43218 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
43221 #define M_E0AMP 0x1fU
43222 #define V_E0AMP(x) ((x) << S_E0AMP)
43223 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
43225 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
43228 #define M_AOFFO 0x3fU
43229 #define V_AOFFO(x) ((x) << S_AOFFO)
43230 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
43233 #define M_AOFFE 0x3fU
43234 #define V_AOFFE(x) ((x) << S_AOFFE)
43235 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
43237 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
43240 #define M_DACAN 0xffU
43241 #define V_DACAN(x) ((x) << S_DACAN)
43242 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
43245 #define M_DACAP 0xffU
43246 #define V_DACAP(x) ((x) << S_DACAP)
43247 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
43249 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
43252 #define M_DACAZ 0xffU
43253 #define V_DACAZ(x) ((x) << S_DACAZ)
43254 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
43257 #define M_DACAM 0xffU
43258 #define V_DACAM(x) ((x) << S_DACAM)
43259 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
43261 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
43264 #define M_ADSN 0x3U
43265 #define V_ADSN(x) ((x) << S_ADSN)
43266 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
43269 #define M_ADMAG 0x7fU
43270 #define V_ADMAG(x) ((x) << S_ADMAG)
43271 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
43273 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
43276 #define V_BLKAZ(x) ((x) << S_BLKAZ)
43277 #define F_BLKAZ V_BLKAZ(1U)
43280 #define M_WIDTH 0x1fU
43281 #define V_WIDTH(x) ((x) << S_WIDTH)
43282 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
43284 #define S_MINWIDTH 5
43285 #define M_MINWIDTH 0x1fU
43286 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
43287 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
43290 #define M_MINAMP 0x1fU
43291 #define V_MINAMP(x) ((x) << S_MINAMP)
43292 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
43294 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
43296 #define S_EMBRDY 10
43297 #define V_EMBRDY(x) ((x) << S_EMBRDY)
43298 #define F_EMBRDY V_EMBRDY(1U)
43301 #define V_EMBUMP(x) ((x) << S_EMBUMP)
43302 #define F_EMBUMP V_EMBUMP(1U)
43305 #define M_EMMD 0x3U
43306 #define V_EMMD(x) ((x) << S_EMMD)
43307 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
43310 #define V_EMPAT(x) ((x) << S_EMPAT)
43311 #define F_EMPAT V_EMPAT(1U)
43314 #define V_EMEN(x) ((x) << S_EMEN)
43315 #define F_EMEN V_EMEN(1U)
43317 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
43320 #define M_H1OSN 0x3U
43321 #define V_H1OSN(x) ((x) << S_H1OSN)
43322 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
43325 #define M_H1OMAG 0x3fU
43326 #define V_H1OMAG(x) ((x) << S_H1OMAG)
43327 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
43330 #define M_H1ESN 0x3U
43331 #define V_H1ESN(x) ((x) << S_H1ESN)
43332 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
43335 #define M_H1EMAG 0x3fU
43336 #define V_H1EMAG(x) ((x) << S_H1EMAG)
43337 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
43339 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
43342 #define M_H2OSN 0x3U
43343 #define V_H2OSN(x) ((x) << S_H2OSN)
43344 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
43347 #define M_H2OMAG 0x1fU
43348 #define V_H2OMAG(x) ((x) << S_H2OMAG)
43349 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
43352 #define M_H2ESN 0x3U
43353 #define V_H2ESN(x) ((x) << S_H2ESN)
43354 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
43357 #define M_H2EMAG 0x1fU
43358 #define V_H2EMAG(x) ((x) << S_H2EMAG)
43359 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
43361 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
43364 #define M_H3OSN 0x3U
43365 #define V_H3OSN(x) ((x) << S_H3OSN)
43366 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
43369 #define M_H3OMAG 0xfU
43370 #define V_H3OMAG(x) ((x) << S_H3OMAG)
43371 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
43374 #define M_H3ESN 0x3U
43375 #define V_H3ESN(x) ((x) << S_H3ESN)
43376 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
43379 #define M_H3EMAG 0xfU
43380 #define V_H3EMAG(x) ((x) << S_H3EMAG)
43381 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
43383 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
43386 #define M_H4OSN 0x3U
43387 #define V_H4OSN(x) ((x) << S_H4OSN)
43388 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
43391 #define M_H4OMAG 0xfU
43392 #define V_H4OMAG(x) ((x) << S_H4OMAG)
43393 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
43396 #define M_H4ESN 0x3U
43397 #define V_H4ESN(x) ((x) << S_H4ESN)
43398 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
43401 #define M_H4EMAG 0xfU
43402 #define V_H4EMAG(x) ((x) << S_H4EMAG)
43403 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
43405 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
43408 #define M_H5OSN 0x3U
43409 #define V_H5OSN(x) ((x) << S_H5OSN)
43410 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
43413 #define M_H5OMAG 0xfU
43414 #define V_H5OMAG(x) ((x) << S_H5OMAG)
43415 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
43418 #define M_H5ESN 0x3U
43419 #define V_H5ESN(x) ((x) << S_H5ESN)
43420 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
43423 #define M_H5EMAG 0xfU
43424 #define V_H5EMAG(x) ((x) << S_H5EMAG)
43425 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
43427 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
43429 #define S_DPCCVG 13
43430 #define V_DPCCVG(x) ((x) << S_DPCCVG)
43431 #define F_DPCCVG V_DPCCVG(1U)
43433 #define S_DACCVG 12
43434 #define V_DACCVG(x) ((x) << S_DACCVG)
43435 #define F_DACCVG V_DACCVG(1U)
43438 #define M_DPCTGT 0x7U
43439 #define V_DPCTGT(x) ((x) << S_DPCTGT)
43440 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
43443 #define V_BLKH1T(x) ((x) << S_BLKH1T)
43444 #define F_BLKH1T V_BLKH1T(1U)
43447 #define V_BLKOAE(x) ((x) << S_BLKOAE)
43448 #define F_BLKOAE V_BLKOAE(1U)
43451 #define M_H1TGT 0x7U
43452 #define V_H1TGT(x) ((x) << S_H1TGT)
43453 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
43457 #define V_OAE(x) ((x) << S_OAE)
43458 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
43460 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
43463 #define M_OLS 0x1fU
43464 #define V_OLS(x) ((x) << S_OLS)
43465 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
43468 #define M_OES 0x1fU
43469 #define V_OES(x) ((x) << S_OES)
43470 #define G_OES(x) (((x) >> S_OES) & M_OES)
43472 #define S_BLKODEC 5
43473 #define V_BLKODEC(x) ((x) << S_BLKODEC)
43474 #define F_BLKODEC V_BLKODEC(1U)
43477 #define M_ODEC 0x1fU
43478 #define V_ODEC(x) ((x) << S_ODEC)
43479 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
43481 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
43484 #define V_BER6(x) ((x) << S_BER6)
43485 #define F_BER6 V_BER6(1U)
43487 #define S_BER6VAL 14
43488 #define V_BER6VAL(x) ((x) << S_BER6VAL)
43489 #define F_BER6VAL V_BER6VAL(1U)
43491 #define S_BER3VAL 13
43492 #define V_BER3VAL(x) ((x) << S_BER3VAL)
43493 #define F_BER3VAL V_BER3VAL(1U)
43496 #define V_DPCCMP(x) ((x) << S_DPCCMP)
43497 #define F_DPCCMP V_DPCCMP(1U)
43500 #define V_DACCMP(x) ((x) << S_DACCMP)
43501 #define F_DACCMP V_DACCMP(1U)
43504 #define V_DDCCMP(x) ((x) << S_DDCCMP)
43505 #define F_DDCCMP V_DDCCMP(1U)
43507 #define S_AERRFLG 6
43508 #define V_AERRFLG(x) ((x) << S_AERRFLG)
43509 #define F_AERRFLG V_AERRFLG(1U)
43511 #define S_WERRFLG 5
43512 #define V_WERRFLG(x) ((x) << S_WERRFLG)
43513 #define F_WERRFLG V_WERRFLG(1U)
43516 #define V_TRCMP(x) ((x) << S_TRCMP)
43517 #define F_TRCMP V_TRCMP(1U)
43520 #define V_VLCKF(x) ((x) << S_VLCKF)
43521 #define F_VLCKF V_VLCKF(1U)
43524 #define V_ROCADJ(x) ((x) << S_ROCADJ)
43525 #define F_ROCADJ V_ROCADJ(1U)
43528 #define V_ROCCMP(x) ((x) << S_ROCCMP)
43529 #define F_ROCCMP V_ROCCMP(1U)
43532 #define V_OCCMP(x) ((x) << S_OCCMP)
43533 #define F_OCCMP V_OCCMP(1U)
43535 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
43538 #define V_FDPC(x) ((x) << S_FDPC)
43539 #define F_FDPC V_FDPC(1U)
43542 #define V_FDAC(x) ((x) << S_FDAC)
43543 #define F_FDAC V_FDAC(1U)
43546 #define V_FDDC(x) ((x) << S_FDDC)
43547 #define F_FDDC V_FDDC(1U)
43550 #define V_FNRND(x) ((x) << S_FNRND)
43551 #define F_FNRND V_FNRND(1U)
43553 #define S_FVGAIN 11
43554 #define V_FVGAIN(x) ((x) << S_FVGAIN)
43555 #define F_FVGAIN V_FVGAIN(1U)
43558 #define V_FVOFF(x) ((x) << S_FVOFF)
43559 #define F_FVOFF V_FVOFF(1U)
43562 #define V_FSDET(x) ((x) << S_FSDET)
43563 #define F_FSDET V_FSDET(1U)
43566 #define V_FBER6(x) ((x) << S_FBER6)
43567 #define F_FBER6 V_FBER6(1U)
43570 #define V_FROTO(x) ((x) << S_FROTO)
43571 #define F_FROTO V_FROTO(1U)
43574 #define V_FH4H5(x) ((x) << S_FH4H5)
43575 #define F_FH4H5 V_FH4H5(1U)
43578 #define V_FH2H3(x) ((x) << S_FH2H3)
43579 #define F_FH2H3 V_FH2H3(1U)
43582 #define V_FH1(x) ((x) << S_FH1)
43583 #define F_FH1 V_FH1(1U)
43586 #define V_FH1SN(x) ((x) << S_FH1SN)
43587 #define F_FH1SN V_FH1SN(1U)
43590 #define V_FNRDF(x) ((x) << S_FNRDF)
43591 #define F_FNRDF V_FNRDF(1U)
43594 #define V_FADAC(x) ((x) << S_FADAC)
43595 #define F_FADAC V_FADAC(1U)
43597 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
43598 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
43599 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
43600 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
43601 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
43602 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
43603 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
43604 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
43605 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
43606 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
43607 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
43608 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
43609 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
43610 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
43611 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
43612 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
43613 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
43614 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
43615 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
43616 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
43617 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
43618 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
43619 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
43620 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
43621 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
43622 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
43623 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
43624 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
43625 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
43626 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
43627 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
43628 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
43629 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
43630 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
43631 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
43632 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
43633 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
43634 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
43635 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
43636 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
43637 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
43638 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
43639 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
43640 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
43641 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
43642 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
43643 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
43644 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
43645 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
43646 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
43647 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
43648 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
43649 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
43650 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
43651 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
43652 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
43653 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
43654 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
43655 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
43656 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
43657 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
43658 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
43659 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
43660 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
43661 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
43662 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
43663 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
43664 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
43665 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
43666 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
43667 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
43668 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
43669 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
43670 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
43671 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
43672 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
43673 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
43674 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
43675 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
43676 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
43677 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
43678 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
43679 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
43680 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
43681 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
43682 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
43683 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
43684 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
43685 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
43686 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
43687 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
43688 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
43689 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
43690 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
43691 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
43692 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
43693 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
43694 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
43695 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
43696 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
43697 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
43698 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
43699 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
43700 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
43701 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
43702 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
43703 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
43704 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
43705 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
43706 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
43707 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
43708 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
43709 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
43710 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
43711 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
43712 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
43713 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
43714 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
43715 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
43716 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
43717 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
43718 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
43719 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
43720 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
43721 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
43722 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
43723 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
43724 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
43725 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
43726 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
43727 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
43728 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
43729 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
43730 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
43731 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
43732 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
43733 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
43734 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
43735 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
43736 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
43737 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
43738 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
43739 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
43740 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
43741 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
43742 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
43743 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
43746 #define M_BSELO 0xfU
43747 #define V_BSELO(x) ((x) << S_BSELO)
43748 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
43750 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
43753 #define V_LDET(x) ((x) << S_LDET)
43754 #define F_LDET V_LDET(1U)
43757 #define V_CCERR(x) ((x) << S_CCERR)
43758 #define F_CCERR V_CCERR(1U)
43761 #define V_CCCMP(x) ((x) << S_CCCMP)
43762 #define F_CCCMP V_CCCMP(1U)
43764 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
43767 #define M_BSELI 0xfU
43768 #define V_BSELI(x) ((x) << S_BSELI)
43769 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
43771 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
43774 #define V_VISEL(x) ((x) << S_VISEL)
43775 #define F_VISEL V_VISEL(1U)
43778 #define V_FMIN(x) ((x) << S_FMIN)
43779 #define F_FMIN V_FMIN(1U)
43782 #define V_FMAX(x) ((x) << S_FMAX)
43783 #define F_FMAX V_FMAX(1U)
43786 #define V_CVHOLD(x) ((x) << S_CVHOLD)
43787 #define F_CVHOLD V_CVHOLD(1U)
43790 #define V_TCDIS(x) ((x) << S_TCDIS)
43791 #define F_TCDIS V_TCDIS(1U)
43793 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
43796 #define V_CMETH(x) ((x) << S_CMETH)
43797 #define F_CMETH V_CMETH(1U)
43800 #define V_RECAL(x) ((x) << S_RECAL)
43801 #define F_RECAL V_RECAL(1U)
43804 #define V_CCLD(x) ((x) << S_CCLD)
43805 #define F_CCLD V_CCLD(1U)
43807 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
43810 #define M_ATST 0x1fU
43811 #define V_ATST(x) ((x) << S_ATST)
43812 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
43814 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
43817 #define V_RXDEN(x) ((x) << S_RXDEN)
43818 #define F_RXDEN V_RXDEN(1U)
43821 #define V_RXCEN(x) ((x) << S_RXCEN)
43822 #define F_RXCEN V_RXCEN(1U)
43825 #define V_TXDEN(x) ((x) << S_TXDEN)
43826 #define F_TXDEN V_TXDEN(1U)
43829 #define V_TXCEN(x) ((x) << S_TXCEN)
43830 #define F_TXCEN V_TXCEN(1U)
43833 #define V_RXBEN(x) ((x) << S_RXBEN)
43834 #define F_RXBEN V_RXBEN(1U)
43837 #define V_RXAEN(x) ((x) << S_RXAEN)
43838 #define F_RXAEN V_RXAEN(1U)
43841 #define V_TXBEN(x) ((x) << S_TXBEN)
43842 #define F_TXBEN V_TXBEN(1U)
43845 #define V_TXAEN(x) ((x) << S_TXAEN)
43846 #define F_TXAEN V_TXAEN(1U)
43848 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
43851 #define V_RXDRST(x) ((x) << S_RXDRST)
43852 #define F_RXDRST V_RXDRST(1U)
43855 #define V_RXCRST(x) ((x) << S_RXCRST)
43856 #define F_RXCRST V_RXCRST(1U)
43859 #define V_TXDRST(x) ((x) << S_TXDRST)
43860 #define F_TXDRST V_TXDRST(1U)
43863 #define V_TXCRST(x) ((x) << S_TXCRST)
43864 #define F_TXCRST V_TXCRST(1U)
43867 #define V_RXBRST(x) ((x) << S_RXBRST)
43868 #define F_RXBRST V_RXBRST(1U)
43871 #define V_RXARST(x) ((x) << S_RXARST)
43872 #define F_RXARST V_RXARST(1U)
43875 #define V_TXBRST(x) ((x) << S_TXBRST)
43876 #define F_TXBRST V_TXBRST(1U)
43879 #define V_TXARST(x) ((x) << S_TXARST)
43880 #define F_TXARST V_TXARST(1U)
43882 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
43885 #define V_ENCPIS(x) ((x) << S_ENCPIS)
43886 #define F_ENCPIS V_ENCPIS(1U)
43889 #define M_CPISEL 0x3U
43890 #define V_CPISEL(x) ((x) << S_CPISEL)
43891 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
43893 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
43896 #define M_BGCTL 0x1fU
43897 #define V_BGCTL(x) ((x) << S_BGCTL)
43898 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
43900 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
43903 #define V_LFREQ2(x) ((x) << S_LFREQ2)
43904 #define F_LFREQ2 V_LFREQ2(1U)
43907 #define V_LFREQ1(x) ((x) << S_LFREQ1)
43908 #define F_LFREQ1 V_LFREQ1(1U)
43911 #define V_LFREQO(x) ((x) << S_LFREQO)
43912 #define F_LFREQO V_LFREQO(1U)
43915 #define V_LFSEL(x) ((x) << S_LFSEL)
43916 #define F_LFSEL V_LFSEL(1U)
43918 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
43921 #define V_PFVAL(x) ((x) << S_PFVAL)
43922 #define F_PFVAL V_PFVAL(1U)
43925 #define V_PFEN(x) ((x) << S_PFEN)
43926 #define F_PFEN V_PFEN(1U)
43929 #define V_VBADJ(x) ((x) << S_VBADJ)
43930 #define F_VBADJ V_VBADJ(1U)
43932 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
43933 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
43934 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
43935 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
43936 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
43937 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
43938 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
43939 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
43940 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
43941 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
43942 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
43943 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
43944 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
43945 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
43946 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
43947 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
43948 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
43949 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
43950 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
43951 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
43952 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
43953 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
43954 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
43955 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
43956 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
43957 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
43958 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
43959 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
43960 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
43961 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
43962 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
43963 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
43964 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
43965 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
43966 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
43967 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
43968 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
43969 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
43970 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
43971 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
43972 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
43973 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
43974 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
43975 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
43976 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
43977 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
43978 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
43979 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
43980 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
43981 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
43982 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
43983 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
43984 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
43985 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
43986 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
43987 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
43988 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
43989 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
43990 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
43992 /* registers for module UP */
43993 #define UP_BASE_ADDR 0x0
43995 #define A_UP_IBQ_CONFIG 0x0
43997 #define S_IBQGEN2 2
43998 #define M_IBQGEN2 0x3fffffffU
43999 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
44000 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
44002 #define S_IBQBUSY 1
44003 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
44004 #define F_IBQBUSY V_IBQBUSY(1U)
44007 #define V_IBQEN(x) ((x) << S_IBQEN)
44008 #define F_IBQEN V_IBQEN(1U)
44010 #define A_UP_OBQ_CONFIG 0x4
44012 #define S_OBQGEN2 2
44013 #define M_OBQGEN2 0x3fffffffU
44014 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
44015 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
44017 #define S_OBQBUSY 1
44018 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
44019 #define F_OBQBUSY V_OBQBUSY(1U)
44022 #define V_OBQEN(x) ((x) << S_OBQEN)
44023 #define F_OBQEN V_OBQEN(1U)
44025 #define A_UP_IBQ_GEN 0x8
44027 #define S_IBQGEN0 22
44028 #define M_IBQGEN0 0x3ffU
44029 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
44030 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
44032 #define S_IBQTSCHCHNLRDY 18
44033 #define M_IBQTSCHCHNLRDY 0xfU
44034 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
44035 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
44037 #define S_IBQMBVFSTATUS 17
44038 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
44039 #define F_IBQMBVFSTATUS V_IBQMBVFSTATUS(1U)
44041 #define S_IBQMBSTATUS 16
44042 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
44043 #define F_IBQMBSTATUS V_IBQMBSTATUS(1U)
44045 #define S_IBQGEN1 6
44046 #define M_IBQGEN1 0x3ffU
44047 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
44048 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
44050 #define S_IBQEMPTY 0
44051 #define M_IBQEMPTY 0x3fU
44052 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
44053 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
44055 #define A_UP_OBQ_GEN 0xc
44058 #define M_OBQGEN 0x3ffffffU
44059 #define V_OBQGEN(x) ((x) << S_OBQGEN)
44060 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
44062 #define S_OBQFULL 0
44063 #define M_OBQFULL 0x3fU
44064 #define V_OBQFULL(x) ((x) << S_OBQFULL)
44065 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
44067 #define S_T5_OBQGEN 8
44068 #define M_T5_OBQGEN 0xffffffU
44069 #define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
44070 #define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
44072 #define S_T5_OBQFULL 0
44073 #define M_T5_OBQFULL 0xffU
44074 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
44075 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
44077 #define A_UP_IBQ_0_RDADDR 0x10
44080 #define M_QUEID 0x7ffffU
44081 #define V_QUEID(x) ((x) << S_QUEID)
44082 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
44084 #define S_IBQRDADDR 0
44085 #define M_IBQRDADDR 0x1fffU
44086 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
44087 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
44089 #define A_UP_IBQ_0_WRADDR 0x14
44091 #define S_IBQWRADDR 0
44092 #define M_IBQWRADDR 0x1fffU
44093 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
44094 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
44096 #define A_UP_IBQ_0_STATUS 0x18
44098 #define S_QUEERRFRAME 31
44099 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
44100 #define F_QUEERRFRAME V_QUEERRFRAME(1U)
44102 #define S_QUEREMFLITS 0
44103 #define M_QUEREMFLITS 0x7ffU
44104 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
44105 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
44107 #define A_UP_IBQ_0_PKTCNT 0x1c
44109 #define S_QUEEOPCNT 16
44110 #define M_QUEEOPCNT 0xfffU
44111 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
44112 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
44114 #define S_QUESOPCNT 0
44115 #define M_QUESOPCNT 0xfffU
44116 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
44117 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
44119 #define A_UP_IBQ_1_RDADDR 0x20
44120 #define A_UP_IBQ_1_WRADDR 0x24
44121 #define A_UP_IBQ_1_STATUS 0x28
44122 #define A_UP_IBQ_1_PKTCNT 0x2c
44123 #define A_UP_IBQ_2_RDADDR 0x30
44124 #define A_UP_IBQ_2_WRADDR 0x34
44125 #define A_UP_IBQ_2_STATUS 0x38
44126 #define A_UP_IBQ_2_PKTCNT 0x3c
44127 #define A_UP_IBQ_3_RDADDR 0x40
44128 #define A_UP_IBQ_3_WRADDR 0x44
44129 #define A_UP_IBQ_3_STATUS 0x48
44130 #define A_UP_IBQ_3_PKTCNT 0x4c
44131 #define A_UP_IBQ_4_RDADDR 0x50
44132 #define A_UP_IBQ_4_WRADDR 0x54
44133 #define A_UP_IBQ_4_STATUS 0x58
44134 #define A_UP_IBQ_4_PKTCNT 0x5c
44135 #define A_UP_IBQ_5_RDADDR 0x60
44136 #define A_UP_IBQ_5_WRADDR 0x64
44137 #define A_UP_IBQ_5_STATUS 0x68
44138 #define A_UP_IBQ_5_PKTCNT 0x6c
44139 #define A_UP_OBQ_0_RDADDR 0x70
44142 #define M_OBQID 0x1ffffU
44143 #define V_OBQID(x) ((x) << S_OBQID)
44144 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
44146 #define S_QUERDADDR 0
44147 #define M_QUERDADDR 0x7fffU
44148 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
44149 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
44151 #define A_UP_OBQ_0_WRADDR 0x74
44153 #define S_QUEWRADDR 0
44154 #define M_QUEWRADDR 0x7fffU
44155 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
44156 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
44158 #define A_UP_OBQ_0_STATUS 0x78
44159 #define A_UP_OBQ_0_PKTCNT 0x7c
44160 #define A_UP_OBQ_1_RDADDR 0x80
44161 #define A_UP_OBQ_1_WRADDR 0x84
44162 #define A_UP_OBQ_1_STATUS 0x88
44163 #define A_UP_OBQ_1_PKTCNT 0x8c
44164 #define A_UP_OBQ_2_RDADDR 0x90
44165 #define A_UP_OBQ_2_WRADDR 0x94
44166 #define A_UP_OBQ_2_STATUS 0x98
44167 #define A_UP_OBQ_2_PKTCNT 0x9c
44168 #define A_UP_OBQ_3_RDADDR 0xa0
44169 #define A_UP_OBQ_3_WRADDR 0xa4
44170 #define A_UP_OBQ_3_STATUS 0xa8
44171 #define A_UP_OBQ_3_PKTCNT 0xac
44172 #define A_UP_OBQ_4_RDADDR 0xb0
44173 #define A_UP_OBQ_4_WRADDR 0xb4
44174 #define A_UP_OBQ_4_STATUS 0xb8
44175 #define A_UP_OBQ_4_PKTCNT 0xbc
44176 #define A_UP_OBQ_5_RDADDR 0xc0
44177 #define A_UP_OBQ_5_WRADDR 0xc4
44178 #define A_UP_OBQ_5_STATUS 0xc8
44179 #define A_UP_OBQ_5_PKTCNT 0xcc
44180 #define A_UP_IBQ_0_CONFIG 0xd0
44182 #define S_QUESIZE 26
44183 #define M_QUESIZE 0x3fU
44184 #define V_QUESIZE(x) ((x) << S_QUESIZE)
44185 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
44187 #define S_QUEBASE 8
44188 #define M_QUEBASE 0x3fU
44189 #define V_QUEBASE(x) ((x) << S_QUEBASE)
44190 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
44192 #define S_QUEDBG8BEN 7
44193 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
44194 #define F_QUEDBG8BEN V_QUEDBG8BEN(1U)
44196 #define S_QUEBAREADDR 0
44197 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
44198 #define F_QUEBAREADDR V_QUEBAREADDR(1U)
44200 #define S_QUE1KEN 6
44201 #define V_QUE1KEN(x) ((x) << S_QUE1KEN)
44202 #define F_QUE1KEN V_QUE1KEN(1U)
44204 #define A_UP_IBQ_0_REALADDR 0xd4
44206 #define S_QUERDADDRWRAP 31
44207 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
44208 #define F_QUERDADDRWRAP V_QUERDADDRWRAP(1U)
44210 #define S_QUEWRADDRWRAP 30
44211 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
44212 #define F_QUEWRADDRWRAP V_QUEWRADDRWRAP(1U)
44214 #define S_QUEMEMADDR 3
44215 #define M_QUEMEMADDR 0x7ffU
44216 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
44217 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
44219 #define A_UP_IBQ_1_CONFIG 0xd8
44220 #define A_UP_IBQ_1_REALADDR 0xdc
44221 #define A_UP_IBQ_2_CONFIG 0xe0
44222 #define A_UP_IBQ_2_REALADDR 0xe4
44223 #define A_UP_IBQ_3_CONFIG 0xe8
44224 #define A_UP_IBQ_3_REALADDR 0xec
44225 #define A_UP_IBQ_4_CONFIG 0xf0
44226 #define A_UP_IBQ_4_REALADDR 0xf4
44227 #define A_UP_IBQ_5_CONFIG 0xf8
44228 #define A_UP_IBQ_5_REALADDR 0xfc
44229 #define A_UP_OBQ_0_CONFIG 0x100
44230 #define A_UP_OBQ_0_REALADDR 0x104
44231 #define A_UP_OBQ_1_CONFIG 0x108
44232 #define A_UP_OBQ_1_REALADDR 0x10c
44233 #define A_UP_OBQ_2_CONFIG 0x110
44234 #define A_UP_OBQ_2_REALADDR 0x114
44235 #define A_UP_OBQ_3_CONFIG 0x118
44236 #define A_UP_OBQ_3_REALADDR 0x11c
44237 #define A_UP_OBQ_4_CONFIG 0x120
44238 #define A_UP_OBQ_4_REALADDR 0x124
44239 #define A_UP_OBQ_5_CONFIG 0x128
44240 #define A_UP_OBQ_5_REALADDR 0x12c
44241 #define A_UP_MAILBOX_STATUS 0x130
44243 #define S_MBGEN0 20
44244 #define M_MBGEN0 0xfffU
44245 #define V_MBGEN0(x) ((x) << S_MBGEN0)
44246 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
44248 #define S_GENTIMERTRIGGER 16
44249 #define M_GENTIMERTRIGGER 0xfU
44250 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
44251 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
44254 #define M_MBGEN1 0xffU
44255 #define V_MBGEN1(x) ((x) << S_MBGEN1)
44256 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
44258 #define S_MBPFINT 0
44259 #define M_MBPFINT 0xffU
44260 #define V_MBPFINT(x) ((x) << S_MBPFINT)
44261 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
44263 #define A_UP_UP_DBG_LA_CFG 0x140
44265 #define S_UPDBGLACAPTBUB 31
44266 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
44267 #define F_UPDBGLACAPTBUB V_UPDBGLACAPTBUB(1U)
44269 #define S_UPDBGLACAPTPCONLY 30
44270 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
44271 #define F_UPDBGLACAPTPCONLY V_UPDBGLACAPTPCONLY(1U)
44273 #define S_UPDBGLAMASKSTOP 29
44274 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
44275 #define F_UPDBGLAMASKSTOP V_UPDBGLAMASKSTOP(1U)
44277 #define S_UPDBGLAMASKTRIG 28
44278 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
44279 #define F_UPDBGLAMASKTRIG V_UPDBGLAMASKTRIG(1U)
44281 #define S_UPDBGLAWRPTR 16
44282 #define M_UPDBGLAWRPTR 0xfffU
44283 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
44284 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
44286 #define S_UPDBGLARDPTR 2
44287 #define M_UPDBGLARDPTR 0xfffU
44288 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
44289 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
44291 #define S_UPDBGLARDEN 1
44292 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
44293 #define F_UPDBGLARDEN V_UPDBGLARDEN(1U)
44295 #define S_UPDBGLAEN 0
44296 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
44297 #define F_UPDBGLAEN V_UPDBGLAEN(1U)
44299 #define S_UPDBGLABUSY 14
44300 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
44301 #define F_UPDBGLABUSY V_UPDBGLABUSY(1U)
44303 #define A_UP_UP_DBG_LA_DATA 0x144
44304 #define A_UP_PIO_MST_CONFIG 0x148
44307 #define M_FLSRC 0x7U
44308 #define V_FLSRC(x) ((x) << S_FLSRC)
44309 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
44311 #define S_SEPROT 23
44312 #define V_SEPROT(x) ((x) << S_SEPROT)
44313 #define F_SEPROT V_SEPROT(1U)
44316 #define M_SESRC 0x7U
44317 #define V_SESRC(x) ((x) << S_SESRC)
44318 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
44321 #define V_UPRGN(x) ((x) << S_UPRGN)
44322 #define F_UPRGN V_UPRGN(1U)
44325 #define M_UPPF 0x7U
44326 #define V_UPPF(x) ((x) << S_UPPF)
44327 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
44330 #define M_UPRID 0xffffU
44331 #define V_UPRID(x) ((x) << S_UPRID)
44332 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
44334 #define S_REQVFVLD 27
44335 #define V_REQVFVLD(x) ((x) << S_REQVFVLD)
44336 #define F_REQVFVLD V_REQVFVLD(1U)
44338 #define S_T5_UPRID 0
44339 #define M_T5_UPRID 0xffU
44340 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
44341 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
44343 #define S_T6_UPRID 0
44344 #define M_T6_UPRID 0x1ffU
44345 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
44346 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
44348 #define A_UP_UP_SELF_CONTROL 0x14c
44350 #define S_UPSELFRESET 0
44351 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
44352 #define F_UPSELFRESET V_UPSELFRESET(1U)
44354 #define A_UP_MAILBOX_PF0_CTL 0x180
44355 #define A_UP_MAILBOX_PF1_CTL 0x190
44356 #define A_UP_MAILBOX_PF2_CTL 0x1a0
44357 #define A_UP_MAILBOX_PF3_CTL 0x1b0
44358 #define A_UP_MAILBOX_PF4_CTL 0x1c0
44359 #define A_UP_MAILBOX_PF5_CTL 0x1d0
44360 #define A_UP_MAILBOX_PF6_CTL 0x1e0
44361 #define A_UP_MAILBOX_PF7_CTL 0x1f0
44362 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
44364 #define S_ECO_15444_SGE_DB_BUSY 31
44365 #define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
44366 #define F_ECO_15444_SGE_DB_BUSY V_ECO_15444_SGE_DB_BUSY(1U)
44368 #define S_ECO_15444_PL_INTF_BUSY 30
44369 #define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
44370 #define F_ECO_15444_PL_INTF_BUSY V_ECO_15444_PL_INTF_BUSY(1U)
44372 #define S_TSCHCHNLCRDY 0
44373 #define M_TSCHCHNLCRDY 0x3fffffffU
44374 #define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
44375 #define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
44377 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
44379 #define S_TSCHWRRLIMIT 16
44380 #define M_TSCHWRRLIMIT 0xffffU
44381 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
44382 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
44384 #define S_TSCHCHNLCWRDY 0
44385 #define M_TSCHCHNLCWRDY 0xffffU
44386 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
44387 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
44389 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
44391 #define S_TSCHWRRRELOAD 16
44392 #define M_TSCHWRRRELOAD 0xffffU
44393 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
44394 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
44396 #define S_TSCHCHNLCWATCH 0
44397 #define M_TSCHCHNLCWATCH 0xffffU
44398 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
44399 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
44401 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
44403 #define S_TSCHCHNLCNUM 24
44404 #define M_TSCHCHNLCNUM 0x1fU
44405 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
44406 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
44408 #define S_TSCHCHNLCCNT 0
44409 #define M_TSCHCHNLCCNT 0xffffffU
44410 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
44411 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
44413 #define S_TSCHCHNLCHDIS 31
44414 #define V_TSCHCHNLCHDIS(x) ((x) << S_TSCHCHNLCHDIS)
44415 #define F_TSCHCHNLCHDIS V_TSCHCHNLCHDIS(1U)
44417 #define S_TSCHCHNLWDIS 30
44418 #define V_TSCHCHNLWDIS(x) ((x) << S_TSCHCHNLWDIS)
44419 #define F_TSCHCHNLWDIS V_TSCHCHNLWDIS(1U)
44421 #define S_TSCHCHNLCLDIS 29
44422 #define V_TSCHCHNLCLDIS(x) ((x) << S_TSCHCHNLCLDIS)
44423 #define F_TSCHCHNLCLDIS V_TSCHCHNLCLDIS(1U)
44425 #define A_UP_UPLADBGPCCHKDATA_0 0x240
44426 #define A_UP_UPLADBGPCCHKMASK_0 0x244
44427 #define A_UP_UPLADBGPCCHKDATA_1 0x250
44428 #define A_UP_UPLADBGPCCHKMASK_1 0x254
44429 #define A_UP_UPLADBGPCCHKDATA_2 0x260
44430 #define A_UP_UPLADBGPCCHKMASK_2 0x264
44431 #define A_UP_UPLADBGPCCHKDATA_3 0x270
44432 #define A_UP_UPLADBGPCCHKMASK_3 0x274
44433 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
44434 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
44435 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
44436 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
44437 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
44438 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
44439 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
44440 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
44441 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
44442 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
44443 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
44444 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
44445 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
44446 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
44447 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
44448 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
44449 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
44450 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
44451 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
44452 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
44453 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
44454 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
44455 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
44456 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
44457 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
44458 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
44459 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
44460 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
44461 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
44462 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
44463 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
44464 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
44465 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
44466 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
44467 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
44468 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
44469 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
44470 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
44471 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
44472 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
44473 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
44474 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
44475 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
44476 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
44477 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
44478 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
44479 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
44480 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
44481 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
44482 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
44483 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
44484 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
44485 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
44486 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
44487 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
44488 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
44489 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
44490 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
44491 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
44492 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
44493 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
44494 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
44495 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
44496 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
44497 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
44498 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
44499 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
44500 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
44501 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
44502 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
44503 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
44504 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
44505 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
44506 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
44507 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
44508 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
44509 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
44510 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
44511 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
44512 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
44513 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
44514 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
44515 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
44516 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
44518 /* registers for module CIM_CTL */
44519 #define CIM_CTL_BASE_ADDR 0x0
44521 #define A_CIM_CTL_CONFIG 0x0
44523 #define S_AUTOPREFLOC 17
44524 #define M_AUTOPREFLOC 0x1fU
44525 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
44526 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
44528 #define S_AUTOPREFEN 16
44529 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
44530 #define F_AUTOPREFEN V_AUTOPREFEN(1U)
44532 #define S_DISMATIMEOUT 15
44533 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
44534 #define F_DISMATIMEOUT V_DISMATIMEOUT(1U)
44536 #define S_PIFMULTICMD 8
44537 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
44538 #define F_PIFMULTICMD V_PIFMULTICMD(1U)
44540 #define S_UPSELFRESETTOUT 7
44541 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
44542 #define F_UPSELFRESETTOUT V_UPSELFRESETTOUT(1U)
44544 #define S_PLSWAPDISWR 6
44545 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
44546 #define F_PLSWAPDISWR V_PLSWAPDISWR(1U)
44548 #define S_PLSWAPDISRD 5
44549 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
44550 #define F_PLSWAPDISRD V_PLSWAPDISRD(1U)
44553 #define V_PREFEN(x) ((x) << S_PREFEN)
44554 #define F_PREFEN V_PREFEN(1U)
44556 #define S_DISSLOWTIMEOUT 14
44557 #define V_DISSLOWTIMEOUT(x) ((x) << S_DISSLOWTIMEOUT)
44558 #define F_DISSLOWTIMEOUT V_DISSLOWTIMEOUT(1U)
44560 #define S_INTLRSPEN 9
44561 #define V_INTLRSPEN(x) ((x) << S_INTLRSPEN)
44562 #define F_INTLRSPEN V_INTLRSPEN(1U)
44564 #define A_CIM_CTL_PREFADDR 0x4
44565 #define A_CIM_CTL_ALLOCADDR 0x8
44566 #define A_CIM_CTL_INVLDTADDR 0xc
44567 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
44568 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
44569 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
44570 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
44571 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
44572 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
44573 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
44574 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
44575 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
44576 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
44577 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
44578 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
44579 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
44580 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
44581 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
44582 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
44583 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
44584 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
44585 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
44586 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
44587 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
44588 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
44589 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
44590 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
44591 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
44592 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
44593 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
44594 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
44595 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
44596 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
44597 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
44598 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
44599 #define A_CIM_CTL_FIFO_CNT 0x90
44601 #define S_CTLFIFOCNT 0
44602 #define M_CTLFIFOCNT 0xfU
44603 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
44604 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
44606 #define A_CIM_CTL_GLB_TIMER 0x94
44607 #define A_CIM_CTL_TIMER0 0x98
44608 #define A_CIM_CTL_TIMER1 0x9c
44609 #define A_CIM_CTL_GEN0 0xa0
44610 #define A_CIM_CTL_GEN1 0xa4
44611 #define A_CIM_CTL_GEN2 0xa8
44612 #define A_CIM_CTL_GEN3 0xac
44613 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
44614 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
44616 #define S_GENTIMERRUN 7
44617 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
44618 #define F_GENTIMERRUN V_GENTIMERRUN(1U)
44620 #define S_GENTIMERTRIG 6
44621 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
44622 #define F_GENTIMERTRIG V_GENTIMERTRIG(1U)
44624 #define S_GENTIMERACT 4
44625 #define M_GENTIMERACT 0x3U
44626 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
44627 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
44629 #define S_GENTIMERCFG 2
44630 #define M_GENTIMERCFG 0x3U
44631 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
44632 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
44634 #define S_GENTIMERSTOP 1
44635 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
44636 #define F_GENTIMERSTOP V_GENTIMERSTOP(1U)
44638 #define S_GENTIMERSTRT 0
44639 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
44640 #define F_GENTIMERSTRT V_GENTIMERSTRT(1U)
44642 #define A_CIM_CTL_GEN_TIMER0 0xb8
44643 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
44644 #define A_CIM_CTL_GEN_TIMER1 0xc0
44645 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
44646 #define A_CIM_CTL_GEN_TIMER2 0xc8
44647 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
44648 #define A_CIM_CTL_GEN_TIMER3 0xd0
44649 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
44650 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
44651 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
44653 #define S_TSCHNLEN 31
44654 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
44655 #define F_TSCHNLEN V_TSCHNLEN(1U)
44657 #define S_TSCHNRESET 30
44658 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
44659 #define F_TSCHNRESET V_TSCHNRESET(1U)
44661 #define S_T6_MIN_MAX_EN 29
44662 #define V_T6_MIN_MAX_EN(x) ((x) << S_T6_MIN_MAX_EN)
44663 #define F_T6_MIN_MAX_EN V_T6_MIN_MAX_EN(1U)
44665 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
44667 #define S_TSCHNLTICK 0
44668 #define M_TSCHNLTICK 0xffffU
44669 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
44670 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
44672 #define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
44674 #define S_TSC15RATECTL 15
44675 #define V_TSC15RATECTL(x) ((x) << S_TSC15RATECTL)
44676 #define F_TSC15RATECTL V_TSC15RATECTL(1U)
44678 #define S_TSC14RATECTL 14
44679 #define V_TSC14RATECTL(x) ((x) << S_TSC14RATECTL)
44680 #define F_TSC14RATECTL V_TSC14RATECTL(1U)
44682 #define S_TSC13RATECTL 13
44683 #define V_TSC13RATECTL(x) ((x) << S_TSC13RATECTL)
44684 #define F_TSC13RATECTL V_TSC13RATECTL(1U)
44686 #define S_TSC12RATECTL 12
44687 #define V_TSC12RATECTL(x) ((x) << S_TSC12RATECTL)
44688 #define F_TSC12RATECTL V_TSC12RATECTL(1U)
44690 #define S_TSC11RATECTL 11
44691 #define V_TSC11RATECTL(x) ((x) << S_TSC11RATECTL)
44692 #define F_TSC11RATECTL V_TSC11RATECTL(1U)
44694 #define S_TSC10RATECTL 10
44695 #define V_TSC10RATECTL(x) ((x) << S_TSC10RATECTL)
44696 #define F_TSC10RATECTL V_TSC10RATECTL(1U)
44698 #define S_TSC9RATECTL 9
44699 #define V_TSC9RATECTL(x) ((x) << S_TSC9RATECTL)
44700 #define F_TSC9RATECTL V_TSC9RATECTL(1U)
44702 #define S_TSC8RATECTL 8
44703 #define V_TSC8RATECTL(x) ((x) << S_TSC8RATECTL)
44704 #define F_TSC8RATECTL V_TSC8RATECTL(1U)
44706 #define S_TSC7RATECTL 7
44707 #define V_TSC7RATECTL(x) ((x) << S_TSC7RATECTL)
44708 #define F_TSC7RATECTL V_TSC7RATECTL(1U)
44710 #define S_TSC6RATECTL 6
44711 #define V_TSC6RATECTL(x) ((x) << S_TSC6RATECTL)
44712 #define F_TSC6RATECTL V_TSC6RATECTL(1U)
44714 #define S_TSC5RATECTL 5
44715 #define V_TSC5RATECTL(x) ((x) << S_TSC5RATECTL)
44716 #define F_TSC5RATECTL V_TSC5RATECTL(1U)
44718 #define S_TSC4RATECTL 4
44719 #define V_TSC4RATECTL(x) ((x) << S_TSC4RATECTL)
44720 #define F_TSC4RATECTL V_TSC4RATECTL(1U)
44722 #define S_TSC3RATECTL 3
44723 #define V_TSC3RATECTL(x) ((x) << S_TSC3RATECTL)
44724 #define F_TSC3RATECTL V_TSC3RATECTL(1U)
44726 #define S_TSC2RATECTL 2
44727 #define V_TSC2RATECTL(x) ((x) << S_TSC2RATECTL)
44728 #define F_TSC2RATECTL V_TSC2RATECTL(1U)
44730 #define S_TSC1RATECTL 1
44731 #define V_TSC1RATECTL(x) ((x) << S_TSC1RATECTL)
44732 #define F_TSC1RATECTL V_TSC1RATECTL(1U)
44734 #define S_TSC0RATECTL 0
44735 #define V_TSC0RATECTL(x) ((x) << S_TSC0RATECTL)
44736 #define F_TSC0RATECTL V_TSC0RATECTL(1U)
44738 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
44740 #define S_TSC15WRREN 31
44741 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
44742 #define F_TSC15WRREN V_TSC15WRREN(1U)
44744 #define S_TSC15RATEEN 30
44745 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
44746 #define F_TSC15RATEEN V_TSC15RATEEN(1U)
44748 #define S_TSC14WRREN 29
44749 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
44750 #define F_TSC14WRREN V_TSC14WRREN(1U)
44752 #define S_TSC14RATEEN 28
44753 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
44754 #define F_TSC14RATEEN V_TSC14RATEEN(1U)
44756 #define S_TSC13WRREN 27
44757 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
44758 #define F_TSC13WRREN V_TSC13WRREN(1U)
44760 #define S_TSC13RATEEN 26
44761 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
44762 #define F_TSC13RATEEN V_TSC13RATEEN(1U)
44764 #define S_TSC12WRREN 25
44765 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
44766 #define F_TSC12WRREN V_TSC12WRREN(1U)
44768 #define S_TSC12RATEEN 24
44769 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
44770 #define F_TSC12RATEEN V_TSC12RATEEN(1U)
44772 #define S_TSC11WRREN 23
44773 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
44774 #define F_TSC11WRREN V_TSC11WRREN(1U)
44776 #define S_TSC11RATEEN 22
44777 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
44778 #define F_TSC11RATEEN V_TSC11RATEEN(1U)
44780 #define S_TSC10WRREN 21
44781 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
44782 #define F_TSC10WRREN V_TSC10WRREN(1U)
44784 #define S_TSC10RATEEN 20
44785 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
44786 #define F_TSC10RATEEN V_TSC10RATEEN(1U)
44788 #define S_TSC9WRREN 19
44789 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
44790 #define F_TSC9WRREN V_TSC9WRREN(1U)
44792 #define S_TSC9RATEEN 18
44793 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
44794 #define F_TSC9RATEEN V_TSC9RATEEN(1U)
44796 #define S_TSC8WRREN 17
44797 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
44798 #define F_TSC8WRREN V_TSC8WRREN(1U)
44800 #define S_TSC8RATEEN 16
44801 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
44802 #define F_TSC8RATEEN V_TSC8RATEEN(1U)
44804 #define S_TSC7WRREN 15
44805 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
44806 #define F_TSC7WRREN V_TSC7WRREN(1U)
44808 #define S_TSC7RATEEN 14
44809 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
44810 #define F_TSC7RATEEN V_TSC7RATEEN(1U)
44812 #define S_TSC6WRREN 13
44813 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
44814 #define F_TSC6WRREN V_TSC6WRREN(1U)
44816 #define S_TSC6RATEEN 12
44817 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
44818 #define F_TSC6RATEEN V_TSC6RATEEN(1U)
44820 #define S_TSC5WRREN 11
44821 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
44822 #define F_TSC5WRREN V_TSC5WRREN(1U)
44824 #define S_TSC5RATEEN 10
44825 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
44826 #define F_TSC5RATEEN V_TSC5RATEEN(1U)
44828 #define S_TSC4WRREN 9
44829 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
44830 #define F_TSC4WRREN V_TSC4WRREN(1U)
44832 #define S_TSC4RATEEN 8
44833 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
44834 #define F_TSC4RATEEN V_TSC4RATEEN(1U)
44836 #define S_TSC3WRREN 7
44837 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
44838 #define F_TSC3WRREN V_TSC3WRREN(1U)
44840 #define S_TSC3RATEEN 6
44841 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
44842 #define F_TSC3RATEEN V_TSC3RATEEN(1U)
44844 #define S_TSC2WRREN 5
44845 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
44846 #define F_TSC2WRREN V_TSC2WRREN(1U)
44848 #define S_TSC2RATEEN 4
44849 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
44850 #define F_TSC2RATEEN V_TSC2RATEEN(1U)
44852 #define S_TSC1WRREN 3
44853 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
44854 #define F_TSC1WRREN V_TSC1WRREN(1U)
44856 #define S_TSC1RATEEN 2
44857 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
44858 #define F_TSC1RATEEN V_TSC1RATEEN(1U)
44860 #define S_TSC0WRREN 1
44861 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
44862 #define F_TSC0WRREN V_TSC0WRREN(1U)
44864 #define S_TSC0RATEEN 0
44865 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
44866 #define F_TSC0RATEEN V_TSC0RATEEN(1U)
44868 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
44870 #define S_MIN_MAX_EN 0
44871 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
44872 #define F_MIN_MAX_EN V_MIN_MAX_EN(1U)
44874 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
44876 #define S_TSCHNLRATENEG 31
44877 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
44878 #define F_TSCHNLRATENEG V_TSCHNLRATENEG(1U)
44880 #define S_TSCHNLRATEL 0
44881 #define M_TSCHNLRATEL 0x7fffffffU
44882 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
44883 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
44885 #define S_TSCHNLRATEPROT 30
44886 #define V_TSCHNLRATEPROT(x) ((x) << S_TSCHNLRATEPROT)
44887 #define F_TSCHNLRATEPROT V_TSCHNLRATEPROT(1U)
44889 #define S_T6_TSCHNLRATEL 0
44890 #define M_T6_TSCHNLRATEL 0x3fffffffU
44891 #define V_T6_TSCHNLRATEL(x) ((x) << S_T6_TSCHNLRATEL)
44892 #define G_T6_TSCHNLRATEL(x) (((x) >> S_T6_TSCHNLRATEL) & M_T6_TSCHNLRATEL)
44894 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
44896 #define S_TSCHNLRMAX 16
44897 #define M_TSCHNLRMAX 0xffffU
44898 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
44899 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
44901 #define S_TSCHNLRINCR 0
44902 #define M_TSCHNLRINCR 0xffffU
44903 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
44904 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
44906 #define S_TSCHNLRTSEL 14
44907 #define M_TSCHNLRTSEL 0x3U
44908 #define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL)
44909 #define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL)
44911 #define S_T6_TSCHNLRINCR 0
44912 #define M_T6_TSCHNLRINCR 0x3fffU
44913 #define V_T6_TSCHNLRINCR(x) ((x) << S_T6_TSCHNLRINCR)
44914 #define G_T6_TSCHNLRINCR(x) (((x) >> S_T6_TSCHNLRINCR) & M_T6_TSCHNLRINCR)
44916 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
44917 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
44919 #define S_TSCHNLWEIGHT 0
44920 #define M_TSCHNLWEIGHT 0x3fffffU
44921 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
44922 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
44924 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
44926 #define S_TSCCLRATENEG 31
44927 #define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
44928 #define F_TSCCLRATENEG V_TSCCLRATENEG(1U)
44930 #define S_TSCCLRATEL 0
44931 #define M_TSCCLRATEL 0xffffffU
44932 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
44933 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
44935 #define S_TSCCLRATEPROT 30
44936 #define V_TSCCLRATEPROT(x) ((x) << S_TSCCLRATEPROT)
44937 #define F_TSCCLRATEPROT V_TSCCLRATEPROT(1U)
44939 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
44941 #define S_TSCCLRMAX 16
44942 #define M_TSCCLRMAX 0xffffU
44943 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
44944 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
44946 #define S_TSCCLRINCR 0
44947 #define M_TSCCLRINCR 0xffffU
44948 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
44949 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
44951 #define S_TSCCLRTSEL 14
44952 #define M_TSCCLRTSEL 0x3U
44953 #define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL)
44954 #define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL)
44956 #define S_T6_TSCCLRINCR 0
44957 #define M_T6_TSCCLRINCR 0x3fffU
44958 #define V_T6_TSCCLRINCR(x) ((x) << S_T6_TSCCLRINCR)
44959 #define G_T6_TSCCLRINCR(x) (((x) >> S_T6_TSCCLRINCR) & M_T6_TSCCLRINCR)
44961 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
44963 #define S_TSCCLWRRNEG 31
44964 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
44965 #define F_TSCCLWRRNEG V_TSCCLWRRNEG(1U)
44967 #define S_TSCCLWRR 0
44968 #define M_TSCCLWRR 0x3ffffffU
44969 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
44970 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
44972 #define S_TSCCLWRRPROT 30
44973 #define V_TSCCLWRRPROT(x) ((x) << S_TSCCLWRRPROT)
44974 #define F_TSCCLWRRPROT V_TSCCLWRRPROT(1U)
44976 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
44978 #define S_TSCCLWEIGHT 0
44979 #define M_TSCCLWEIGHT 0xffffU
44980 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
44981 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
44983 #define S_PAUSEVECSEL 28
44984 #define M_PAUSEVECSEL 0x3U
44985 #define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL)
44986 #define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL)
44988 #define S_MPSPAUSEMASK 20
44989 #define M_MPSPAUSEMASK 0xffU
44990 #define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK)
44991 #define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK)
44993 #define A_CIM_CTL_TSCH_TICK0 0xd80
44994 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
44995 #define A_CIM_CTL_TSCH_TICK1 0xd84
44996 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
44997 #define A_CIM_CTL_TSCH_TICK2 0xd88
44998 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
44999 #define A_CIM_CTL_TSCH_TICK3 0xd8c
45000 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
45001 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
45002 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
45003 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
45004 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
45005 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
45006 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
45007 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
45008 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
45009 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
45010 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
45012 #define S_PF7_OWNER_PL 15
45013 #define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
45014 #define F_PF7_OWNER_PL V_PF7_OWNER_PL(1U)
45016 #define S_PF6_OWNER_PL 14
45017 #define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
45018 #define F_PF6_OWNER_PL V_PF6_OWNER_PL(1U)
45020 #define S_PF5_OWNER_PL 13
45021 #define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
45022 #define F_PF5_OWNER_PL V_PF5_OWNER_PL(1U)
45024 #define S_PF4_OWNER_PL 12
45025 #define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
45026 #define F_PF4_OWNER_PL V_PF4_OWNER_PL(1U)
45028 #define S_PF3_OWNER_PL 11
45029 #define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
45030 #define F_PF3_OWNER_PL V_PF3_OWNER_PL(1U)
45032 #define S_PF2_OWNER_PL 10
45033 #define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
45034 #define F_PF2_OWNER_PL V_PF2_OWNER_PL(1U)
45036 #define S_PF1_OWNER_PL 9
45037 #define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
45038 #define F_PF1_OWNER_PL V_PF1_OWNER_PL(1U)
45040 #define S_PF0_OWNER_PL 8
45041 #define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
45042 #define F_PF0_OWNER_PL V_PF0_OWNER_PL(1U)
45044 #define S_PF7_OWNER_UP 7
45045 #define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
45046 #define F_PF7_OWNER_UP V_PF7_OWNER_UP(1U)
45048 #define S_PF6_OWNER_UP 6
45049 #define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
45050 #define F_PF6_OWNER_UP V_PF6_OWNER_UP(1U)
45052 #define S_PF5_OWNER_UP 5
45053 #define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
45054 #define F_PF5_OWNER_UP V_PF5_OWNER_UP(1U)
45056 #define S_PF4_OWNER_UP 4
45057 #define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
45058 #define F_PF4_OWNER_UP V_PF4_OWNER_UP(1U)
45060 #define S_PF3_OWNER_UP 3
45061 #define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
45062 #define F_PF3_OWNER_UP V_PF3_OWNER_UP(1U)
45064 #define S_PF2_OWNER_UP 2
45065 #define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
45066 #define F_PF2_OWNER_UP V_PF2_OWNER_UP(1U)
45068 #define S_PF1_OWNER_UP 1
45069 #define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
45070 #define F_PF1_OWNER_UP V_PF1_OWNER_UP(1U)
45072 #define S_PF0_OWNER_UP 0
45073 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
45074 #define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U)
45076 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
45077 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
45079 #define S_T5_CTLRID 0
45080 #define M_T5_CTLRID 0xffU
45081 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
45082 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
45084 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
45085 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
45086 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
45087 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
45089 #define S_T6_UPRID 0
45090 #define M_T6_UPRID 0x1ffU
45091 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
45092 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
45094 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
45095 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
45096 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
45097 #define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
45098 #define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
45100 #define S_CH1_PRIO_EN 1
45101 #define V_CH1_PRIO_EN(x) ((x) << S_CH1_PRIO_EN)
45102 #define F_CH1_PRIO_EN V_CH1_PRIO_EN(1U)
45104 #define S_CH0_PRIO_EN 0
45105 #define V_CH0_PRIO_EN(x) ((x) << S_CH0_PRIO_EN)
45106 #define F_CH0_PRIO_EN V_CH0_PRIO_EN(1U)
45108 #define A_CIM_CTL_PIF_TIMEOUT 0xe40
45110 #define S_SLOW_TIMEOUT 16
45111 #define M_SLOW_TIMEOUT 0xffffU
45112 #define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT)
45113 #define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT)
45115 #define S_MA_TIMEOUT 0
45116 #define M_MA_TIMEOUT 0xffffU
45117 #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
45118 #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
45120 /* registers for module MAC */
45121 #define MAC_BASE_ADDR 0x0
45123 #define A_MAC_PORT_CFG 0x800
45125 #define S_MAC_CLK_SEL 29
45126 #define M_MAC_CLK_SEL 0x7U
45127 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
45128 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
45130 #define S_SMUXTXSEL 9
45131 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
45132 #define F_SMUXTXSEL V_SMUXTXSEL(1U)
45134 #define S_SMUXRXSEL 8
45135 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
45136 #define F_SMUXRXSEL V_SMUXRXSEL(1U)
45138 #define S_PORTSPEED 4
45139 #define M_PORTSPEED 0x3U
45140 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
45141 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
45143 #define S_ENA_ERR_RSP 28
45144 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
45145 #define F_ENA_ERR_RSP V_ENA_ERR_RSP(1U)
45147 #define S_DEBUG_CLR 25
45148 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
45149 #define F_DEBUG_CLR V_DEBUG_CLR(1U)
45151 #define S_PLL_SEL 23
45152 #define V_PLL_SEL(x) ((x) << S_PLL_SEL)
45153 #define F_PLL_SEL V_PLL_SEL(1U)
45155 #define S_PORT_MAP 20
45156 #define M_PORT_MAP 0x7U
45157 #define V_PORT_MAP(x) ((x) << S_PORT_MAP)
45158 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
45160 #define S_AEC_PAT_DATA 15
45161 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
45162 #define F_AEC_PAT_DATA V_AEC_PAT_DATA(1U)
45164 #define S_MACCLK_SEL 13
45165 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
45166 #define F_MACCLK_SEL V_MACCLK_SEL(1U)
45168 #define S_XGMII_SEL 12
45169 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
45170 #define F_XGMII_SEL V_XGMII_SEL(1U)
45172 #define S_DEBUG_PORT_SEL 10
45173 #define M_DEBUG_PORT_SEL 0x3U
45174 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
45175 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
45177 #define S_ENABLE_25G 7
45178 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
45179 #define F_ENABLE_25G V_ENABLE_25G(1U)
45181 #define S_ENABLE_50G 6
45182 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
45183 #define F_ENABLE_50G V_ENABLE_50G(1U)
45185 #define S_DEBUG_TX_RX_SEL 1
45186 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
45187 #define F_DEBUG_TX_RX_SEL V_DEBUG_TX_RX_SEL(1U)
45189 #define A_MAC_PORT_RESET_CTRL 0x804
45191 #define S_TWGDSK_HSSC16B 31
45192 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
45193 #define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U)
45195 #define S_EEE_RESET 30
45196 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
45197 #define F_EEE_RESET V_EEE_RESET(1U)
45199 #define S_PTP_TIMER 29
45200 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
45201 #define F_PTP_TIMER V_PTP_TIMER(1U)
45203 #define S_MTIPREFRESET 28
45204 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
45205 #define F_MTIPREFRESET V_MTIPREFRESET(1U)
45207 #define S_MTIPTXFFRESET 27
45208 #define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
45209 #define F_MTIPTXFFRESET V_MTIPTXFFRESET(1U)
45211 #define S_MTIPRXFFRESET 26
45212 #define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
45213 #define F_MTIPRXFFRESET V_MTIPRXFFRESET(1U)
45215 #define S_MTIPREGRESET 25
45216 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
45217 #define F_MTIPREGRESET V_MTIPREGRESET(1U)
45219 #define S_AEC3RESET 23
45220 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
45221 #define F_AEC3RESET V_AEC3RESET(1U)
45223 #define S_AEC2RESET 22
45224 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
45225 #define F_AEC2RESET V_AEC2RESET(1U)
45227 #define S_AEC1RESET 21
45228 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
45229 #define F_AEC1RESET V_AEC1RESET(1U)
45231 #define S_AEC0RESET 20
45232 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
45233 #define F_AEC0RESET V_AEC0RESET(1U)
45235 #define S_AET3RESET 19
45236 #define V_AET3RESET(x) ((x) << S_AET3RESET)
45237 #define F_AET3RESET V_AET3RESET(1U)
45239 #define S_AET2RESET 18
45240 #define V_AET2RESET(x) ((x) << S_AET2RESET)
45241 #define F_AET2RESET V_AET2RESET(1U)
45243 #define S_AET1RESET 17
45244 #define V_AET1RESET(x) ((x) << S_AET1RESET)
45245 #define F_AET1RESET V_AET1RESET(1U)
45247 #define S_AET0RESET 16
45248 #define V_AET0RESET(x) ((x) << S_AET0RESET)
45249 #define F_AET0RESET V_AET0RESET(1U)
45251 #define S_TXIF_RESET 12
45252 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
45253 #define F_TXIF_RESET V_TXIF_RESET(1U)
45255 #define S_RXIF_RESET 11
45256 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
45257 #define F_RXIF_RESET V_RXIF_RESET(1U)
45259 #define S_MTIPSD3TXRST 9
45260 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
45261 #define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U)
45263 #define S_MTIPSD2TXRST 8
45264 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
45265 #define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U)
45267 #define S_MTIPSD1TXRST 7
45268 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
45269 #define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U)
45271 #define S_MTIPSD0TXRST 6
45272 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
45273 #define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U)
45275 #define S_MTIPSD3RXRST 5
45276 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
45277 #define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U)
45279 #define S_MTIPSD2RXRST 4
45280 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
45281 #define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U)
45283 #define S_MTIPSD1RXRST 3
45284 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
45285 #define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U)
45287 #define S_MTIPSD0RXRST 1
45288 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
45289 #define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U)
45291 #define S_MAC100G40G_RESET 27
45292 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
45293 #define F_MAC100G40G_RESET V_MAC100G40G_RESET(1U)
45295 #define S_MAC10G1G_RESET 26
45296 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
45297 #define F_MAC10G1G_RESET V_MAC10G1G_RESET(1U)
45299 #define S_PCS1G_RESET 24
45300 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
45301 #define F_PCS1G_RESET V_PCS1G_RESET(1U)
45303 #define S_PCS10G_RESET 15
45304 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
45305 #define F_PCS10G_RESET V_PCS10G_RESET(1U)
45307 #define S_PCS40G_RESET 14
45308 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
45309 #define F_PCS40G_RESET V_PCS40G_RESET(1U)
45311 #define S_PCS100G_RESET 13
45312 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
45313 #define F_PCS100G_RESET V_PCS100G_RESET(1U)
45315 #define A_MAC_PORT_LED_CFG 0x808
45317 #define S_LED1_CFG1 14
45318 #define M_LED1_CFG1 0x3U
45319 #define V_LED1_CFG1(x) ((x) << S_LED1_CFG1)
45320 #define G_LED1_CFG1(x) (((x) >> S_LED1_CFG1) & M_LED1_CFG1)
45322 #define S_LED0_CFG1 12
45323 #define M_LED0_CFG1 0x3U
45324 #define V_LED0_CFG1(x) ((x) << S_LED0_CFG1)
45325 #define G_LED0_CFG1(x) (((x) >> S_LED0_CFG1) & M_LED0_CFG1)
45327 #define S_LED1_TLO 11
45328 #define V_LED1_TLO(x) ((x) << S_LED1_TLO)
45329 #define F_LED1_TLO V_LED1_TLO(1U)
45331 #define S_LED1_THI 10
45332 #define V_LED1_THI(x) ((x) << S_LED1_THI)
45333 #define F_LED1_THI V_LED1_THI(1U)
45335 #define S_LED0_TLO 9
45336 #define V_LED0_TLO(x) ((x) << S_LED0_TLO)
45337 #define F_LED0_TLO V_LED0_TLO(1U)
45339 #define S_LED0_THI 8
45340 #define V_LED0_THI(x) ((x) << S_LED0_THI)
45341 #define F_LED0_THI V_LED0_THI(1U)
45343 #define A_MAC_PORT_LED_COUNTHI 0x80c
45344 #define A_MAC_PORT_LED_COUNTLO 0x810
45345 #define A_MAC_PORT_CFG3 0x814
45347 #define S_T5_FPGA_PTP_PORT 26
45348 #define M_T5_FPGA_PTP_PORT 0x3U
45349 #define V_T5_FPGA_PTP_PORT(x) ((x) << S_T5_FPGA_PTP_PORT)
45350 #define G_T5_FPGA_PTP_PORT(x) (((x) >> S_T5_FPGA_PTP_PORT) & M_T5_FPGA_PTP_PORT)
45352 #define S_FCSDISCTRL 25
45353 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
45354 #define F_FCSDISCTRL V_FCSDISCTRL(1U)
45356 #define S_SIGDETCTRL 24
45357 #define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
45358 #define F_SIGDETCTRL V_SIGDETCTRL(1U)
45360 #define S_TX_LANE 23
45361 #define V_TX_LANE(x) ((x) << S_TX_LANE)
45362 #define F_TX_LANE V_TX_LANE(1U)
45364 #define S_RX_LANE 22
45365 #define V_RX_LANE(x) ((x) << S_RX_LANE)
45366 #define F_RX_LANE V_RX_LANE(1U)
45368 #define S_SE_CLR 21
45369 #define V_SE_CLR(x) ((x) << S_SE_CLR)
45370 #define F_SE_CLR V_SE_CLR(1U)
45372 #define S_AN_ENA 17
45373 #define M_AN_ENA 0xfU
45374 #define V_AN_ENA(x) ((x) << S_AN_ENA)
45375 #define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
45377 #define S_SD_RX_CLK_ENA 13
45378 #define M_SD_RX_CLK_ENA 0xfU
45379 #define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
45380 #define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
45382 #define S_SD_TX_CLK_ENA 9
45383 #define M_SD_TX_CLK_ENA 0xfU
45384 #define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
45385 #define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
45387 #define S_SGMIISEL 8
45388 #define V_SGMIISEL(x) ((x) << S_SGMIISEL)
45389 #define F_SGMIISEL V_SGMIISEL(1U)
45391 #define S_HSSPLLSEL 4
45392 #define M_HSSPLLSEL 0xfU
45393 #define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
45394 #define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
45396 #define S_HSSC16C20SEL 0
45397 #define M_HSSC16C20SEL 0xfU
45398 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
45399 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
45401 #define S_REF_CLK_SEL 30
45402 #define M_REF_CLK_SEL 0x3U
45403 #define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL)
45404 #define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL)
45406 #define S_SGMII_SD_SIG_DET 29
45407 #define V_SGMII_SD_SIG_DET(x) ((x) << S_SGMII_SD_SIG_DET)
45408 #define F_SGMII_SD_SIG_DET V_SGMII_SD_SIG_DET(1U)
45410 #define S_SGMII_SGPCS_ENA 28
45411 #define V_SGMII_SGPCS_ENA(x) ((x) << S_SGMII_SGPCS_ENA)
45412 #define F_SGMII_SGPCS_ENA V_SGMII_SGPCS_ENA(1U)
45414 #define S_MAC_FPGA_PTP_PORT 26
45415 #define M_MAC_FPGA_PTP_PORT 0x3U
45416 #define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT)
45417 #define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT)
45419 #define A_MAC_PORT_CFG2 0x818
45421 #define S_T5_AEC_PMA_TX_READY 4
45422 #define M_T5_AEC_PMA_TX_READY 0xfU
45423 #define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
45424 #define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
45426 #define S_T5_AEC_PMA_RX_READY 0
45427 #define M_T5_AEC_PMA_RX_READY 0xfU
45428 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
45429 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
45431 #define S_AN_DATA_CTL 19
45432 #define V_AN_DATA_CTL(x) ((x) << S_AN_DATA_CTL)
45433 #define F_AN_DATA_CTL V_AN_DATA_CTL(1U)
45435 #define A_MAC_PORT_PKT_COUNT 0x81c
45436 #define A_MAC_PORT_CFG4 0x820
45438 #define S_AEC3_RX_WIDTH 14
45439 #define M_AEC3_RX_WIDTH 0x3U
45440 #define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
45441 #define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
45443 #define S_AEC2_RX_WIDTH 12
45444 #define M_AEC2_RX_WIDTH 0x3U
45445 #define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
45446 #define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
45448 #define S_AEC1_RX_WIDTH 10
45449 #define M_AEC1_RX_WIDTH 0x3U
45450 #define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
45451 #define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
45453 #define S_AEC0_RX_WIDTH 8
45454 #define M_AEC0_RX_WIDTH 0x3U
45455 #define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
45456 #define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
45458 #define S_AEC3_TX_WIDTH 6
45459 #define M_AEC3_TX_WIDTH 0x3U
45460 #define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
45461 #define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
45463 #define S_AEC2_TX_WIDTH 4
45464 #define M_AEC2_TX_WIDTH 0x3U
45465 #define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
45466 #define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
45468 #define S_AEC1_TX_WIDTH 2
45469 #define M_AEC1_TX_WIDTH 0x3U
45470 #define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
45471 #define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
45473 #define S_AEC0_TX_WIDTH 0
45474 #define M_AEC0_TX_WIDTH 0x3U
45475 #define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
45476 #define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
45478 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
45479 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
45480 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
45482 #define S_AN_RESET_SD_TX_CLK 31
45483 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
45484 #define F_AN_RESET_SD_TX_CLK V_AN_RESET_SD_TX_CLK(1U)
45486 #define S_AN_RESET_SD_RX_CLK 30
45487 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
45488 #define F_AN_RESET_SD_RX_CLK V_AN_RESET_SD_RX_CLK(1U)
45490 #define S_SGMII_RESET_TX_CLK 29
45491 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
45492 #define F_SGMII_RESET_TX_CLK V_SGMII_RESET_TX_CLK(1U)
45494 #define S_SGMII_RESET_RX_CLK 28
45495 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
45496 #define F_SGMII_RESET_RX_CLK V_SGMII_RESET_RX_CLK(1U)
45498 #define S_SGMII_RESET_REF_CLK 27
45499 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
45500 #define F_SGMII_RESET_REF_CLK V_SGMII_RESET_REF_CLK(1U)
45502 #define S_PCS10G_RESET_XFI_RXCLK 26
45503 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
45504 #define F_PCS10G_RESET_XFI_RXCLK V_PCS10G_RESET_XFI_RXCLK(1U)
45506 #define S_PCS10G_RESET_XFI_TXCLK 25
45507 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
45508 #define F_PCS10G_RESET_XFI_TXCLK V_PCS10G_RESET_XFI_TXCLK(1U)
45510 #define S_PCS10G_RESET_SD_TX_CLK 24
45511 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
45512 #define F_PCS10G_RESET_SD_TX_CLK V_PCS10G_RESET_SD_TX_CLK(1U)
45514 #define S_PCS10G_RESET_SD_RX_CLK 23
45515 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
45516 #define F_PCS10G_RESET_SD_RX_CLK V_PCS10G_RESET_SD_RX_CLK(1U)
45518 #define S_PCS40G_RESET_RXCLK 22
45519 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
45520 #define F_PCS40G_RESET_RXCLK V_PCS40G_RESET_RXCLK(1U)
45522 #define S_PCS40G_RESET_SD_TX_CLK 21
45523 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
45524 #define F_PCS40G_RESET_SD_TX_CLK V_PCS40G_RESET_SD_TX_CLK(1U)
45526 #define S_PCS40G_RESET_SD0_RX_CLK 20
45527 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
45528 #define F_PCS40G_RESET_SD0_RX_CLK V_PCS40G_RESET_SD0_RX_CLK(1U)
45530 #define S_PCS40G_RESET_SD1_RX_CLK 19
45531 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
45532 #define F_PCS40G_RESET_SD1_RX_CLK V_PCS40G_RESET_SD1_RX_CLK(1U)
45534 #define S_PCS40G_RESET_SD2_RX_CLK 18
45535 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
45536 #define F_PCS40G_RESET_SD2_RX_CLK V_PCS40G_RESET_SD2_RX_CLK(1U)
45538 #define S_PCS40G_RESET_SD3_RX_CLK 17
45539 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
45540 #define F_PCS40G_RESET_SD3_RX_CLK V_PCS40G_RESET_SD3_RX_CLK(1U)
45542 #define S_PCS100G_RESET_CGMII_RXCLK 16
45543 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
45544 #define F_PCS100G_RESET_CGMII_RXCLK V_PCS100G_RESET_CGMII_RXCLK(1U)
45546 #define S_PCS100G_RESET_CGMII_TXCLK 15
45547 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
45548 #define F_PCS100G_RESET_CGMII_TXCLK V_PCS100G_RESET_CGMII_TXCLK(1U)
45550 #define S_PCS100G_RESET_TX_CLK 14
45551 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
45552 #define F_PCS100G_RESET_TX_CLK V_PCS100G_RESET_TX_CLK(1U)
45554 #define S_PCS100G_RESET_SD0_RX_CLK 13
45555 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
45556 #define F_PCS100G_RESET_SD0_RX_CLK V_PCS100G_RESET_SD0_RX_CLK(1U)
45558 #define S_PCS100G_RESET_SD1_RX_CLK 12
45559 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
45560 #define F_PCS100G_RESET_SD1_RX_CLK V_PCS100G_RESET_SD1_RX_CLK(1U)
45562 #define S_PCS100G_RESET_SD2_RX_CLK 11
45563 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
45564 #define F_PCS100G_RESET_SD2_RX_CLK V_PCS100G_RESET_SD2_RX_CLK(1U)
45566 #define S_PCS100G_RESET_SD3_RX_CLK 10
45567 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
45568 #define F_PCS100G_RESET_SD3_RX_CLK V_PCS100G_RESET_SD3_RX_CLK(1U)
45570 #define S_MAC40G100G_RESET_TXCLK 9
45571 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
45572 #define F_MAC40G100G_RESET_TXCLK V_MAC40G100G_RESET_TXCLK(1U)
45574 #define S_MAC40G100G_RESET_RXCLK 8
45575 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
45576 #define F_MAC40G100G_RESET_RXCLK V_MAC40G100G_RESET_RXCLK(1U)
45578 #define S_MAC40G100G_RESET_FF_TX_CLK 7
45579 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
45580 #define F_MAC40G100G_RESET_FF_TX_CLK V_MAC40G100G_RESET_FF_TX_CLK(1U)
45582 #define S_MAC40G100G_RESET_FF_RX_CLK 6
45583 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
45584 #define F_MAC40G100G_RESET_FF_RX_CLK V_MAC40G100G_RESET_FF_RX_CLK(1U)
45586 #define S_MAC40G100G_RESET_TS_CLK 5
45587 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
45588 #define F_MAC40G100G_RESET_TS_CLK V_MAC40G100G_RESET_TS_CLK(1U)
45590 #define S_MAC1G10G_RESET_RXCLK 4
45591 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
45592 #define F_MAC1G10G_RESET_RXCLK V_MAC1G10G_RESET_RXCLK(1U)
45594 #define S_MAC1G10G_RESET_TXCLK 3
45595 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
45596 #define F_MAC1G10G_RESET_TXCLK V_MAC1G10G_RESET_TXCLK(1U)
45598 #define S_MAC1G10G_RESET_FF_RX_CLK 2
45599 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
45600 #define F_MAC1G10G_RESET_FF_RX_CLK V_MAC1G10G_RESET_FF_RX_CLK(1U)
45602 #define S_MAC1G10G_RESET_FF_TX_CLK 1
45603 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
45604 #define F_MAC1G10G_RESET_FF_TX_CLK V_MAC1G10G_RESET_FF_TX_CLK(1U)
45606 #define S_XGMII_CLK_RESET 0
45607 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
45608 #define F_XGMII_CLK_RESET V_XGMII_CLK_RESET(1U)
45610 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
45612 #define S_AN_GATE_SD_TX_CLK 31
45613 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
45614 #define F_AN_GATE_SD_TX_CLK V_AN_GATE_SD_TX_CLK(1U)
45616 #define S_AN_GATE_SD_RX_CLK 30
45617 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
45618 #define F_AN_GATE_SD_RX_CLK V_AN_GATE_SD_RX_CLK(1U)
45620 #define S_SGMII_GATE_TX_CLK 29
45621 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
45622 #define F_SGMII_GATE_TX_CLK V_SGMII_GATE_TX_CLK(1U)
45624 #define S_SGMII_GATE_RX_CLK 28
45625 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
45626 #define F_SGMII_GATE_RX_CLK V_SGMII_GATE_RX_CLK(1U)
45628 #define S_SGMII_GATE_REF_CLK 27
45629 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
45630 #define F_SGMII_GATE_REF_CLK V_SGMII_GATE_REF_CLK(1U)
45632 #define S_PCS10G_GATE_XFI_RXCLK 26
45633 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
45634 #define F_PCS10G_GATE_XFI_RXCLK V_PCS10G_GATE_XFI_RXCLK(1U)
45636 #define S_PCS10G_GATE_XFI_TXCLK 25
45637 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
45638 #define F_PCS10G_GATE_XFI_TXCLK V_PCS10G_GATE_XFI_TXCLK(1U)
45640 #define S_PCS10G_GATE_SD_TX_CLK 24
45641 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
45642 #define F_PCS10G_GATE_SD_TX_CLK V_PCS10G_GATE_SD_TX_CLK(1U)
45644 #define S_PCS10G_GATE_SD_RX_CLK 23
45645 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
45646 #define F_PCS10G_GATE_SD_RX_CLK V_PCS10G_GATE_SD_RX_CLK(1U)
45648 #define S_PCS40G_GATE_RXCLK 22
45649 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
45650 #define F_PCS40G_GATE_RXCLK V_PCS40G_GATE_RXCLK(1U)
45652 #define S_PCS40G_GATE_SD_TX_CLK 21
45653 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
45654 #define F_PCS40G_GATE_SD_TX_CLK V_PCS40G_GATE_SD_TX_CLK(1U)
45656 #define S_PCS40G_GATE_SD_RX_CLK 20
45657 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
45658 #define F_PCS40G_GATE_SD_RX_CLK V_PCS40G_GATE_SD_RX_CLK(1U)
45660 #define S_PCS100G_GATE_CGMII_RXCLK 19
45661 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
45662 #define F_PCS100G_GATE_CGMII_RXCLK V_PCS100G_GATE_CGMII_RXCLK(1U)
45664 #define S_PCS100G_GATE_CGMII_TXCLK 18
45665 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
45666 #define F_PCS100G_GATE_CGMII_TXCLK V_PCS100G_GATE_CGMII_TXCLK(1U)
45668 #define S_PCS100G_GATE_TX_CLK 17
45669 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
45670 #define F_PCS100G_GATE_TX_CLK V_PCS100G_GATE_TX_CLK(1U)
45672 #define S_PCS100G_GATE_SD_RX_CLK 16
45673 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
45674 #define F_PCS100G_GATE_SD_RX_CLK V_PCS100G_GATE_SD_RX_CLK(1U)
45676 #define S_MAC40G100G_GATE_TXCLK 15
45677 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
45678 #define F_MAC40G100G_GATE_TXCLK V_MAC40G100G_GATE_TXCLK(1U)
45680 #define S_MAC40G100G_GATE_RXCLK 14
45681 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
45682 #define F_MAC40G100G_GATE_RXCLK V_MAC40G100G_GATE_RXCLK(1U)
45684 #define S_MAC40G100G_GATE_FF_TX_CLK 13
45685 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
45686 #define F_MAC40G100G_GATE_FF_TX_CLK V_MAC40G100G_GATE_FF_TX_CLK(1U)
45688 #define S_MAC40G100G_GATE_FF_RX_CLK 12
45689 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
45690 #define F_MAC40G100G_GATE_FF_RX_CLK V_MAC40G100G_GATE_FF_RX_CLK(1U)
45692 #define S_MAC40G100G_TS_CLK 11
45693 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
45694 #define F_MAC40G100G_TS_CLK V_MAC40G100G_TS_CLK(1U)
45696 #define S_MAC1G10G_GATE_RXCLK 10
45697 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
45698 #define F_MAC1G10G_GATE_RXCLK V_MAC1G10G_GATE_RXCLK(1U)
45700 #define S_MAC1G10G_GATE_TXCLK 9
45701 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
45702 #define F_MAC1G10G_GATE_TXCLK V_MAC1G10G_GATE_TXCLK(1U)
45704 #define S_MAC1G10G_GATE_FF_RX_CLK 8
45705 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
45706 #define F_MAC1G10G_GATE_FF_RX_CLK V_MAC1G10G_GATE_FF_RX_CLK(1U)
45708 #define S_MAC1G10G_GATE_FF_TX_CLK 7
45709 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
45710 #define F_MAC1G10G_GATE_FF_TX_CLK V_MAC1G10G_GATE_FF_TX_CLK(1U)
45713 #define V_AEC_RX(x) ((x) << S_AEC_RX)
45714 #define F_AEC_RX V_AEC_RX(1U)
45717 #define V_AEC_TX(x) ((x) << S_AEC_TX)
45718 #define F_AEC_TX V_AEC_TX(1U)
45720 #define S_PCS100G_CLK_ENABLE 4
45721 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
45722 #define F_PCS100G_CLK_ENABLE V_PCS100G_CLK_ENABLE(1U)
45724 #define S_PCS40G_CLK_ENABLE 3
45725 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
45726 #define F_PCS40G_CLK_ENABLE V_PCS40G_CLK_ENABLE(1U)
45728 #define S_PCS10G_CLK_ENABLE 2
45729 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
45730 #define F_PCS10G_CLK_ENABLE V_PCS10G_CLK_ENABLE(1U)
45732 #define S_PCS1G_CLK_ENABLE 1
45733 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
45734 #define F_PCS1G_CLK_ENABLE V_PCS1G_CLK_ENABLE(1U)
45736 #define S_AN_CLK_ENABLE 0
45737 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
45738 #define F_AN_CLK_ENABLE V_AN_CLK_ENABLE(1U)
45740 #define A_MAC_PORT_LINK_STATUS 0x834
45742 #define S_AN_DONE 6
45743 #define V_AN_DONE(x) ((x) << S_AN_DONE)
45744 #define F_AN_DONE V_AN_DONE(1U)
45746 #define S_ALIGN_DONE 5
45747 #define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
45748 #define F_ALIGN_DONE V_ALIGN_DONE(1U)
45750 #define S_BLOCK_LOCK 4
45751 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
45752 #define F_BLOCK_LOCK V_BLOCK_LOCK(1U)
45754 #define S_HI_BER_ST 7
45755 #define V_HI_BER_ST(x) ((x) << S_HI_BER_ST)
45756 #define F_HI_BER_ST V_HI_BER_ST(1U)
45758 #define S_AN_DONE_ST 6
45759 #define V_AN_DONE_ST(x) ((x) << S_AN_DONE_ST)
45760 #define F_AN_DONE_ST V_AN_DONE_ST(1U)
45762 #define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
45764 #define S_AEC_SYS_LANE_TYPE_3 11
45765 #define V_AEC_SYS_LANE_TYPE_3(x) ((x) << S_AEC_SYS_LANE_TYPE_3)
45766 #define F_AEC_SYS_LANE_TYPE_3 V_AEC_SYS_LANE_TYPE_3(1U)
45768 #define S_AEC_SYS_LANE_TYPE_2 10
45769 #define V_AEC_SYS_LANE_TYPE_2(x) ((x) << S_AEC_SYS_LANE_TYPE_2)
45770 #define F_AEC_SYS_LANE_TYPE_2 V_AEC_SYS_LANE_TYPE_2(1U)
45772 #define S_AEC_SYS_LANE_TYPE_1 9
45773 #define V_AEC_SYS_LANE_TYPE_1(x) ((x) << S_AEC_SYS_LANE_TYPE_1)
45774 #define F_AEC_SYS_LANE_TYPE_1 V_AEC_SYS_LANE_TYPE_1(1U)
45776 #define S_AEC_SYS_LANE_TYPE_0 8
45777 #define V_AEC_SYS_LANE_TYPE_0(x) ((x) << S_AEC_SYS_LANE_TYPE_0)
45778 #define F_AEC_SYS_LANE_TYPE_0 V_AEC_SYS_LANE_TYPE_0(1U)
45780 #define S_AEC_SYS_LANE_SELECT_3 6
45781 #define M_AEC_SYS_LANE_SELECT_3 0x3U
45782 #define V_AEC_SYS_LANE_SELECT_3(x) ((x) << S_AEC_SYS_LANE_SELECT_3)
45783 #define G_AEC_SYS_LANE_SELECT_3(x) (((x) >> S_AEC_SYS_LANE_SELECT_3) & M_AEC_SYS_LANE_SELECT_3)
45785 #define S_AEC_SYS_LANE_SELECT_2 4
45786 #define M_AEC_SYS_LANE_SELECT_2 0x3U
45787 #define V_AEC_SYS_LANE_SELECT_2(x) ((x) << S_AEC_SYS_LANE_SELECT_2)
45788 #define G_AEC_SYS_LANE_SELECT_2(x) (((x) >> S_AEC_SYS_LANE_SELECT_2) & M_AEC_SYS_LANE_SELECT_2)
45790 #define S_AEC_SYS_LANE_SELECT_1 2
45791 #define M_AEC_SYS_LANE_SELECT_1 0x3U
45792 #define V_AEC_SYS_LANE_SELECT_1(x) ((x) << S_AEC_SYS_LANE_SELECT_1)
45793 #define G_AEC_SYS_LANE_SELECT_1(x) (((x) >> S_AEC_SYS_LANE_SELECT_1) & M_AEC_SYS_LANE_SELECT_1)
45795 #define S_AEC_SYS_LANE_SELECT_O 0
45796 #define M_AEC_SYS_LANE_SELECT_O 0x3U
45797 #define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O)
45798 #define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O)
45800 #define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
45802 #define S_AEC_RX_UNKNOWN_LANE_3 11
45803 #define V_AEC_RX_UNKNOWN_LANE_3(x) ((x) << S_AEC_RX_UNKNOWN_LANE_3)
45804 #define F_AEC_RX_UNKNOWN_LANE_3 V_AEC_RX_UNKNOWN_LANE_3(1U)
45806 #define S_AEC_RX_UNKNOWN_LANE_2 10
45807 #define V_AEC_RX_UNKNOWN_LANE_2(x) ((x) << S_AEC_RX_UNKNOWN_LANE_2)
45808 #define F_AEC_RX_UNKNOWN_LANE_2 V_AEC_RX_UNKNOWN_LANE_2(1U)
45810 #define S_AEC_RX_UNKNOWN_LANE_1 9
45811 #define V_AEC_RX_UNKNOWN_LANE_1(x) ((x) << S_AEC_RX_UNKNOWN_LANE_1)
45812 #define F_AEC_RX_UNKNOWN_LANE_1 V_AEC_RX_UNKNOWN_LANE_1(1U)
45814 #define S_AEC_RX_UNKNOWN_LANE_0 8
45815 #define V_AEC_RX_UNKNOWN_LANE_0(x) ((x) << S_AEC_RX_UNKNOWN_LANE_0)
45816 #define F_AEC_RX_UNKNOWN_LANE_0 V_AEC_RX_UNKNOWN_LANE_0(1U)
45818 #define S_AEC_RX_LANE_ID_3 6
45819 #define M_AEC_RX_LANE_ID_3 0x3U
45820 #define V_AEC_RX_LANE_ID_3(x) ((x) << S_AEC_RX_LANE_ID_3)
45821 #define G_AEC_RX_LANE_ID_3(x) (((x) >> S_AEC_RX_LANE_ID_3) & M_AEC_RX_LANE_ID_3)
45823 #define S_AEC_RX_LANE_ID_2 4
45824 #define M_AEC_RX_LANE_ID_2 0x3U
45825 #define V_AEC_RX_LANE_ID_2(x) ((x) << S_AEC_RX_LANE_ID_2)
45826 #define G_AEC_RX_LANE_ID_2(x) (((x) >> S_AEC_RX_LANE_ID_2) & M_AEC_RX_LANE_ID_2)
45828 #define S_AEC_RX_LANE_ID_1 2
45829 #define M_AEC_RX_LANE_ID_1 0x3U
45830 #define V_AEC_RX_LANE_ID_1(x) ((x) << S_AEC_RX_LANE_ID_1)
45831 #define G_AEC_RX_LANE_ID_1(x) (((x) >> S_AEC_RX_LANE_ID_1) & M_AEC_RX_LANE_ID_1)
45833 #define S_AEC_RX_LANE_ID_O 0
45834 #define M_AEC_RX_LANE_ID_O 0x3U
45835 #define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O)
45836 #define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O)
45838 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
45840 #define S_XGMII_CLK_IN_1MS_LO_40G 0
45841 #define M_XGMII_CLK_IN_1MS_LO_40G 0xffffU
45842 #define V_XGMII_CLK_IN_1MS_LO_40G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_40G)
45843 #define G_XGMII_CLK_IN_1MS_LO_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_40G) & M_XGMII_CLK_IN_1MS_LO_40G)
45845 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
45847 #define S_XGMII_CLK_IN_1MS_HI_40G 0
45848 #define M_XGMII_CLK_IN_1MS_HI_40G 0xfU
45849 #define V_XGMII_CLK_IN_1MS_HI_40G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_40G)
45850 #define G_XGMII_CLK_IN_1MS_HI_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_40G) & M_XGMII_CLK_IN_1MS_HI_40G)
45852 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
45854 #define S_XGMII_CLK_IN_1MS_LO_100G 0
45855 #define M_XGMII_CLK_IN_1MS_LO_100G 0xffffU
45856 #define V_XGMII_CLK_IN_1MS_LO_100G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_100G)
45857 #define G_XGMII_CLK_IN_1MS_LO_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_100G) & M_XGMII_CLK_IN_1MS_LO_100G)
45859 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
45861 #define S_XGMII_CLK_IN_1MS_HI_100G 0
45862 #define M_XGMII_CLK_IN_1MS_HI_100G 0xfU
45863 #define V_XGMII_CLK_IN_1MS_HI_100G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_100G)
45864 #define G_XGMII_CLK_IN_1MS_HI_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_100G) & M_XGMII_CLK_IN_1MS_HI_100G)
45866 #define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
45868 #define S_CTL_FSM_CUR_STATE 28
45869 #define M_CTL_FSM_CUR_STATE 0x7U
45870 #define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE)
45871 #define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE)
45873 #define S_CIN_FSM_CUR_STATE 26
45874 #define M_CIN_FSM_CUR_STATE 0x3U
45875 #define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE)
45876 #define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE)
45878 #define S_CRI_FSM_CUR_STATE 23
45879 #define M_CRI_FSM_CUR_STATE 0x7U
45880 #define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE)
45881 #define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE)
45883 #define S_CU_C3_ACK_VALUE 21
45884 #define M_CU_C3_ACK_VALUE 0x3U
45885 #define V_CU_C3_ACK_VALUE(x) ((x) << S_CU_C3_ACK_VALUE)
45886 #define G_CU_C3_ACK_VALUE(x) (((x) >> S_CU_C3_ACK_VALUE) & M_CU_C3_ACK_VALUE)
45888 #define S_CU_C2_ACK_VALUE 19
45889 #define M_CU_C2_ACK_VALUE 0x3U
45890 #define V_CU_C2_ACK_VALUE(x) ((x) << S_CU_C2_ACK_VALUE)
45891 #define G_CU_C2_ACK_VALUE(x) (((x) >> S_CU_C2_ACK_VALUE) & M_CU_C2_ACK_VALUE)
45893 #define S_CU_C1_ACK_VALUE 17
45894 #define M_CU_C1_ACK_VALUE 0x3U
45895 #define V_CU_C1_ACK_VALUE(x) ((x) << S_CU_C1_ACK_VALUE)
45896 #define G_CU_C1_ACK_VALUE(x) (((x) >> S_CU_C1_ACK_VALUE) & M_CU_C1_ACK_VALUE)
45898 #define S_CU_C0_ACK_VALUE 15
45899 #define M_CU_C0_ACK_VALUE 0x3U
45900 #define V_CU_C0_ACK_VALUE(x) ((x) << S_CU_C0_ACK_VALUE)
45901 #define G_CU_C0_ACK_VALUE(x) (((x) >> S_CU_C0_ACK_VALUE) & M_CU_C0_ACK_VALUE)
45903 #define S_CX_INIT 13
45904 #define V_CX_INIT(x) ((x) << S_CX_INIT)
45905 #define F_CX_INIT V_CX_INIT(1U)
45907 #define S_CX_PRESET 12
45908 #define V_CX_PRESET(x) ((x) << S_CX_PRESET)
45909 #define F_CX_PRESET V_CX_PRESET(1U)
45911 #define S_CUF_C3_UPDATE 9
45912 #define M_CUF_C3_UPDATE 0x3U
45913 #define V_CUF_C3_UPDATE(x) ((x) << S_CUF_C3_UPDATE)
45914 #define G_CUF_C3_UPDATE(x) (((x) >> S_CUF_C3_UPDATE) & M_CUF_C3_UPDATE)
45916 #define S_CUF_C2_UPDATE 7
45917 #define M_CUF_C2_UPDATE 0x3U
45918 #define V_CUF_C2_UPDATE(x) ((x) << S_CUF_C2_UPDATE)
45919 #define G_CUF_C2_UPDATE(x) (((x) >> S_CUF_C2_UPDATE) & M_CUF_C2_UPDATE)
45921 #define S_CUF_C1_UPDATE 5
45922 #define M_CUF_C1_UPDATE 0x3U
45923 #define V_CUF_C1_UPDATE(x) ((x) << S_CUF_C1_UPDATE)
45924 #define G_CUF_C1_UPDATE(x) (((x) >> S_CUF_C1_UPDATE) & M_CUF_C1_UPDATE)
45926 #define S_CUF_C0_UPDATE 3
45927 #define M_CUF_C0_UPDATE 0x3U
45928 #define V_CUF_C0_UPDATE(x) ((x) << S_CUF_C0_UPDATE)
45929 #define G_CUF_C0_UPDATE(x) (((x) >> S_CUF_C0_UPDATE) & M_CUF_C0_UPDATE)
45931 #define S_REG_FPH_ATTR_TXUPDAT_VALID 2
45932 #define V_REG_FPH_ATTR_TXUPDAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXUPDAT_VALID)
45933 #define F_REG_FPH_ATTR_TXUPDAT_VALID V_REG_FPH_ATTR_TXUPDAT_VALID(1U)
45935 #define S_REG_FPH_ATTR_TXSTAT_VALID 1
45936 #define V_REG_FPH_ATTR_TXSTAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXSTAT_VALID)
45937 #define F_REG_FPH_ATTR_TXSTAT_VALID V_REG_FPH_ATTR_TXSTAT_VALID(1U)
45939 #define S_REG_MAN_DEC_REQ 0
45940 #define V_REG_MAN_DEC_REQ(x) ((x) << S_REG_MAN_DEC_REQ)
45941 #define F_REG_MAN_DEC_REQ V_REG_MAN_DEC_REQ(1U)
45943 #define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
45945 #define S_FC_LSNA_ 12
45946 #define V_FC_LSNA_(x) ((x) << S_FC_LSNA_)
45947 #define F_FC_LSNA_ V_FC_LSNA_(1U)
45949 #define S_CUF_C0_FSM_DEBUG 9
45950 #define M_CUF_C0_FSM_DEBUG 0x7U
45951 #define V_CUF_C0_FSM_DEBUG(x) ((x) << S_CUF_C0_FSM_DEBUG)
45952 #define G_CUF_C0_FSM_DEBUG(x) (((x) >> S_CUF_C0_FSM_DEBUG) & M_CUF_C0_FSM_DEBUG)
45954 #define S_CUF_C1_FSM_DEBUG 6
45955 #define M_CUF_C1_FSM_DEBUG 0x7U
45956 #define V_CUF_C1_FSM_DEBUG(x) ((x) << S_CUF_C1_FSM_DEBUG)
45957 #define G_CUF_C1_FSM_DEBUG(x) (((x) >> S_CUF_C1_FSM_DEBUG) & M_CUF_C1_FSM_DEBUG)
45959 #define S_CUF_C2_FSM_DEBUG 3
45960 #define M_CUF_C2_FSM_DEBUG 0x7U
45961 #define V_CUF_C2_FSM_DEBUG(x) ((x) << S_CUF_C2_FSM_DEBUG)
45962 #define G_CUF_C2_FSM_DEBUG(x) (((x) >> S_CUF_C2_FSM_DEBUG) & M_CUF_C2_FSM_DEBUG)
45964 #define S_LCK_FSM_CUR_STATE 0
45965 #define M_LCK_FSM_CUR_STATE 0x7U
45966 #define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE)
45967 #define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE)
45969 #define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
45970 #define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
45971 #define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
45972 #define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
45973 #define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
45974 #define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
45975 #define A_MAC_PORT_MAC_DEBUG_RO 0x870
45977 #define S_MAC40G100G_TX_UNDERFLOW 13
45978 #define V_MAC40G100G_TX_UNDERFLOW(x) ((x) << S_MAC40G100G_TX_UNDERFLOW)
45979 #define F_MAC40G100G_TX_UNDERFLOW V_MAC40G100G_TX_UNDERFLOW(1U)
45981 #define S_MAC1G10G_MAGIC_IND 12
45982 #define V_MAC1G10G_MAGIC_IND(x) ((x) << S_MAC1G10G_MAGIC_IND)
45983 #define F_MAC1G10G_MAGIC_IND V_MAC1G10G_MAGIC_IND(1U)
45985 #define S_MAC1G10G_FF_RX_EMPTY 11
45986 #define V_MAC1G10G_FF_RX_EMPTY(x) ((x) << S_MAC1G10G_FF_RX_EMPTY)
45987 #define F_MAC1G10G_FF_RX_EMPTY V_MAC1G10G_FF_RX_EMPTY(1U)
45989 #define S_MAC1G10G_FF_TX_OVR_ERR 10
45990 #define V_MAC1G10G_FF_TX_OVR_ERR(x) ((x) << S_MAC1G10G_FF_TX_OVR_ERR)
45991 #define F_MAC1G10G_FF_TX_OVR_ERR V_MAC1G10G_FF_TX_OVR_ERR(1U)
45993 #define S_MAC1G10G_IF_MODE_ENA 8
45994 #define M_MAC1G10G_IF_MODE_ENA 0x3U
45995 #define V_MAC1G10G_IF_MODE_ENA(x) ((x) << S_MAC1G10G_IF_MODE_ENA)
45996 #define G_MAC1G10G_IF_MODE_ENA(x) (((x) >> S_MAC1G10G_IF_MODE_ENA) & M_MAC1G10G_IF_MODE_ENA)
45998 #define S_MAC1G10G_MII_ENA_10 7
45999 #define V_MAC1G10G_MII_ENA_10(x) ((x) << S_MAC1G10G_MII_ENA_10)
46000 #define F_MAC1G10G_MII_ENA_10 V_MAC1G10G_MII_ENA_10(1U)
46002 #define S_MAC1G10G_PAUSE_ON 6
46003 #define V_MAC1G10G_PAUSE_ON(x) ((x) << S_MAC1G10G_PAUSE_ON)
46004 #define F_MAC1G10G_PAUSE_ON V_MAC1G10G_PAUSE_ON(1U)
46006 #define S_MAC1G10G_PFC_MODE 5
46007 #define V_MAC1G10G_PFC_MODE(x) ((x) << S_MAC1G10G_PFC_MODE)
46008 #define F_MAC1G10G_PFC_MODE V_MAC1G10G_PFC_MODE(1U)
46010 #define S_MAC1G10G_RX_SFD_O 4
46011 #define V_MAC1G10G_RX_SFD_O(x) ((x) << S_MAC1G10G_RX_SFD_O)
46012 #define F_MAC1G10G_RX_SFD_O V_MAC1G10G_RX_SFD_O(1U)
46014 #define S_MAC1G10G_TX_EMPTY 3
46015 #define V_MAC1G10G_TX_EMPTY(x) ((x) << S_MAC1G10G_TX_EMPTY)
46016 #define F_MAC1G10G_TX_EMPTY V_MAC1G10G_TX_EMPTY(1U)
46018 #define S_MAC1G10G_TX_SFD_O 2
46019 #define V_MAC1G10G_TX_SFD_O(x) ((x) << S_MAC1G10G_TX_SFD_O)
46020 #define F_MAC1G10G_TX_SFD_O V_MAC1G10G_TX_SFD_O(1U)
46022 #define S_MAC1G10G_TX_TS_FRM_OUT 1
46023 #define V_MAC1G10G_TX_TS_FRM_OUT(x) ((x) << S_MAC1G10G_TX_TS_FRM_OUT)
46024 #define F_MAC1G10G_TX_TS_FRM_OUT V_MAC1G10G_TX_TS_FRM_OUT(1U)
46026 #define S_MAC1G10G_TX_UNDERFLOW 0
46027 #define V_MAC1G10G_TX_UNDERFLOW(x) ((x) << S_MAC1G10G_TX_UNDERFLOW)
46028 #define F_MAC1G10G_TX_UNDERFLOW V_MAC1G10G_TX_UNDERFLOW(1U)
46030 #define A_MAC_PORT_MAC_CTRL_RW 0x874
46032 #define S_MAC40G100G_FF_TX_PFC_XOFF 17
46033 #define M_MAC40G100G_FF_TX_PFC_XOFF 0xffU
46034 #define V_MAC40G100G_FF_TX_PFC_XOFF(x) ((x) << S_MAC40G100G_FF_TX_PFC_XOFF)
46035 #define G_MAC40G100G_FF_TX_PFC_XOFF(x) (((x) >> S_MAC40G100G_FF_TX_PFC_XOFF) & M_MAC40G100G_FF_TX_PFC_XOFF)
46037 #define S_MAC40G100G_TX_LOC_FAULT 16
46038 #define V_MAC40G100G_TX_LOC_FAULT(x) ((x) << S_MAC40G100G_TX_LOC_FAULT)
46039 #define F_MAC40G100G_TX_LOC_FAULT V_MAC40G100G_TX_LOC_FAULT(1U)
46041 #define S_MAC40G100G_TX_REM_FAULT 15
46042 #define V_MAC40G100G_TX_REM_FAULT(x) ((x) << S_MAC40G100G_TX_REM_FAULT)
46043 #define F_MAC40G100G_TX_REM_FAULT V_MAC40G100G_TX_REM_FAULT(1U)
46045 #define S_MAC40G_LOOP_BCK 14
46046 #define V_MAC40G_LOOP_BCK(x) ((x) << S_MAC40G_LOOP_BCK)
46047 #define F_MAC40G_LOOP_BCK V_MAC40G_LOOP_BCK(1U)
46049 #define S_MAC1G10G_MAGIC_ENA 13
46050 #define V_MAC1G10G_MAGIC_ENA(x) ((x) << S_MAC1G10G_MAGIC_ENA)
46051 #define F_MAC1G10G_MAGIC_ENA V_MAC1G10G_MAGIC_ENA(1U)
46053 #define S_MAC1G10G_IF_MODE_SET 11
46054 #define M_MAC1G10G_IF_MODE_SET 0x3U
46055 #define V_MAC1G10G_IF_MODE_SET(x) ((x) << S_MAC1G10G_IF_MODE_SET)
46056 #define G_MAC1G10G_IF_MODE_SET(x) (((x) >> S_MAC1G10G_IF_MODE_SET) & M_MAC1G10G_IF_MODE_SET)
46058 #define S_MAC1G10G_TX_LOC_FAULT 10
46059 #define V_MAC1G10G_TX_LOC_FAULT(x) ((x) << S_MAC1G10G_TX_LOC_FAULT)
46060 #define F_MAC1G10G_TX_LOC_FAULT V_MAC1G10G_TX_LOC_FAULT(1U)
46062 #define S_MAC1G10G_TX_REM_FAULT 9
46063 #define V_MAC1G10G_TX_REM_FAULT(x) ((x) << S_MAC1G10G_TX_REM_FAULT)
46064 #define F_MAC1G10G_TX_REM_FAULT V_MAC1G10G_TX_REM_FAULT(1U)
46066 #define S_MAC1G10G_XOFF_GEN 1
46067 #define M_MAC1G10G_XOFF_GEN 0xffU
46068 #define V_MAC1G10G_XOFF_GEN(x) ((x) << S_MAC1G10G_XOFF_GEN)
46069 #define G_MAC1G10G_XOFF_GEN(x) (((x) >> S_MAC1G10G_XOFF_GEN) & M_MAC1G10G_XOFF_GEN)
46071 #define S_MAC1G_LOOP_BCK 0
46072 #define V_MAC1G_LOOP_BCK(x) ((x) << S_MAC1G_LOOP_BCK)
46073 #define F_MAC1G_LOOP_BCK V_MAC1G_LOOP_BCK(1U)
46075 #define A_MAC_PORT_PCS_DEBUG0_RO 0x878
46077 #define S_FPGA_LOCK 26
46078 #define M_FPGA_LOCK 0xfU
46079 #define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK)
46080 #define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK)
46082 #define S_T6_AN_DONE 25
46083 #define V_T6_AN_DONE(x) ((x) << S_T6_AN_DONE)
46084 #define F_T6_AN_DONE V_T6_AN_DONE(1U)
46086 #define S_AN_INT 24
46087 #define V_AN_INT(x) ((x) << S_AN_INT)
46088 #define F_AN_INT V_AN_INT(1U)
46090 #define S_AN_PCS_RX_CLK_ENA 23
46091 #define V_AN_PCS_RX_CLK_ENA(x) ((x) << S_AN_PCS_RX_CLK_ENA)
46092 #define F_AN_PCS_RX_CLK_ENA V_AN_PCS_RX_CLK_ENA(1U)
46094 #define S_AN_PCS_TX_CLK_ENA 22
46095 #define V_AN_PCS_TX_CLK_ENA(x) ((x) << S_AN_PCS_TX_CLK_ENA)
46096 #define F_AN_PCS_TX_CLK_ENA V_AN_PCS_TX_CLK_ENA(1U)
46098 #define S_AN_SELECT 17
46099 #define M_AN_SELECT 0x1fU
46100 #define V_AN_SELECT(x) ((x) << S_AN_SELECT)
46101 #define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT)
46103 #define S_AN_PROG 16
46104 #define V_AN_PROG(x) ((x) << S_AN_PROG)
46105 #define F_AN_PROG V_AN_PROG(1U)
46107 #define S_PCS40G_BLOCK_LOCK 12
46108 #define M_PCS40G_BLOCK_LOCK 0xfU
46109 #define V_PCS40G_BLOCK_LOCK(x) ((x) << S_PCS40G_BLOCK_LOCK)
46110 #define G_PCS40G_BLOCK_LOCK(x) (((x) >> S_PCS40G_BLOCK_LOCK) & M_PCS40G_BLOCK_LOCK)
46112 #define S_PCS40G_BER_TIMER_DONE 11
46113 #define V_PCS40G_BER_TIMER_DONE(x) ((x) << S_PCS40G_BER_TIMER_DONE)
46114 #define F_PCS40G_BER_TIMER_DONE V_PCS40G_BER_TIMER_DONE(1U)
46116 #define S_PCS10G_FEC_LOCKED 10
46117 #define V_PCS10G_FEC_LOCKED(x) ((x) << S_PCS10G_FEC_LOCKED)
46118 #define F_PCS10G_FEC_LOCKED V_PCS10G_FEC_LOCKED(1U)
46120 #define S_PCS10G_BLOCK_LOCK 9
46121 #define V_PCS10G_BLOCK_LOCK(x) ((x) << S_PCS10G_BLOCK_LOCK)
46122 #define F_PCS10G_BLOCK_LOCK V_PCS10G_BLOCK_LOCK(1U)
46124 #define S_SGMII_GMII_COL 8
46125 #define V_SGMII_GMII_COL(x) ((x) << S_SGMII_GMII_COL)
46126 #define F_SGMII_GMII_COL V_SGMII_GMII_COL(1U)
46128 #define S_SGMII_GMII_CRS 7
46129 #define V_SGMII_GMII_CRS(x) ((x) << S_SGMII_GMII_CRS)
46130 #define F_SGMII_GMII_CRS V_SGMII_GMII_CRS(1U)
46132 #define S_SGMII_SD_LOOPBACK 6
46133 #define V_SGMII_SD_LOOPBACK(x) ((x) << S_SGMII_SD_LOOPBACK)
46134 #define F_SGMII_SD_LOOPBACK V_SGMII_SD_LOOPBACK(1U)
46136 #define S_SGMII_SG_AN_DONE 5
46137 #define V_SGMII_SG_AN_DONE(x) ((x) << S_SGMII_SG_AN_DONE)
46138 #define F_SGMII_SG_AN_DONE V_SGMII_SG_AN_DONE(1U)
46140 #define S_SGMII_SG_HD 4
46141 #define V_SGMII_SG_HD(x) ((x) << S_SGMII_SG_HD)
46142 #define F_SGMII_SG_HD V_SGMII_SG_HD(1U)
46144 #define S_SGMII_SG_PAGE_RX 3
46145 #define V_SGMII_SG_PAGE_RX(x) ((x) << S_SGMII_SG_PAGE_RX)
46146 #define F_SGMII_SG_PAGE_RX V_SGMII_SG_PAGE_RX(1U)
46148 #define S_SGMII_SG_RX_SYNC 2
46149 #define V_SGMII_SG_RX_SYNC(x) ((x) << S_SGMII_SG_RX_SYNC)
46150 #define F_SGMII_SG_RX_SYNC V_SGMII_SG_RX_SYNC(1U)
46152 #define S_SGMII_SG_SPEED 0
46153 #define M_SGMII_SG_SPEED 0x3U
46154 #define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED)
46155 #define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED)
46157 #define A_MAC_PORT_PCS_CTRL_RW 0x87c
46159 #define S_TX_LI_FAULT 31
46160 #define V_TX_LI_FAULT(x) ((x) << S_TX_LI_FAULT)
46161 #define F_TX_LI_FAULT V_TX_LI_FAULT(1U)
46163 #define S_T6_PAD 30
46164 #define V_T6_PAD(x) ((x) << S_T6_PAD)
46165 #define F_T6_PAD V_T6_PAD(1U)
46167 #define S_BLK_STB_VAL 22
46168 #define M_BLK_STB_VAL 0xffU
46169 #define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL)
46170 #define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL)
46172 #define S_DEBUG_SEL 18
46173 #define M_DEBUG_SEL 0xfU
46174 #define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL)
46175 #define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL)
46177 #define S_SGMII_LOOP 15
46178 #define M_SGMII_LOOP 0x7U
46179 #define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP)
46180 #define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP)
46182 #define S_AN_DIS_TIMER 14
46183 #define V_AN_DIS_TIMER(x) ((x) << S_AN_DIS_TIMER)
46184 #define F_AN_DIS_TIMER V_AN_DIS_TIMER(1U)
46186 #define S_PCS100G_BER_TIMER_SHORT 13
46187 #define V_PCS100G_BER_TIMER_SHORT(x) ((x) << S_PCS100G_BER_TIMER_SHORT)
46188 #define F_PCS100G_BER_TIMER_SHORT V_PCS100G_BER_TIMER_SHORT(1U)
46190 #define S_PCS100G_TX_LANE_THRESH 9
46191 #define M_PCS100G_TX_LANE_THRESH 0xfU
46192 #define V_PCS100G_TX_LANE_THRESH(x) ((x) << S_PCS100G_TX_LANE_THRESH)
46193 #define G_PCS100G_TX_LANE_THRESH(x) (((x) >> S_PCS100G_TX_LANE_THRESH) & M_PCS100G_TX_LANE_THRESH)
46195 #define S_PCS100G_VL_INTVL 8
46196 #define V_PCS100G_VL_INTVL(x) ((x) << S_PCS100G_VL_INTVL)
46197 #define F_PCS100G_VL_INTVL V_PCS100G_VL_INTVL(1U)
46199 #define S_SGMII_TX_LANE_CKMULT 4
46200 #define M_SGMII_TX_LANE_CKMULT 0x7U
46201 #define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT)
46202 #define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT)
46204 #define S_SGMII_TX_LANE_THRESH 0
46205 #define M_SGMII_TX_LANE_THRESH 0xfU
46206 #define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH)
46207 #define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH)
46209 #define A_MAC_PORT_PCS_DEBUG1_RO 0x880
46211 #define S_PCS100G_ALIGN_LOCK 21
46212 #define V_PCS100G_ALIGN_LOCK(x) ((x) << S_PCS100G_ALIGN_LOCK)
46213 #define F_PCS100G_ALIGN_LOCK V_PCS100G_ALIGN_LOCK(1U)
46215 #define S_PCS100G_BER_TIMER_DONE 20
46216 #define V_PCS100G_BER_TIMER_DONE(x) ((x) << S_PCS100G_BER_TIMER_DONE)
46217 #define F_PCS100G_BER_TIMER_DONE V_PCS100G_BER_TIMER_DONE(1U)
46219 #define S_PCS100G_BLOCK_LOCK 0
46220 #define M_PCS100G_BLOCK_LOCK 0xfffffU
46221 #define V_PCS100G_BLOCK_LOCK(x) ((x) << S_PCS100G_BLOCK_LOCK)
46222 #define G_PCS100G_BLOCK_LOCK(x) (((x) >> S_PCS100G_BLOCK_LOCK) & M_PCS100G_BLOCK_LOCK)
46224 #define A_MAC_PORT_PERR_INT_EN_100G 0x884
46226 #define S_PERR_RX_FEC100G_DLY 29
46227 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
46228 #define F_PERR_RX_FEC100G_DLY V_PERR_RX_FEC100G_DLY(1U)
46230 #define S_PERR_RX_FEC100G 28
46231 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
46232 #define F_PERR_RX_FEC100G V_PERR_RX_FEC100G(1U)
46234 #define S_PERR_RX3_FEC100G_DK 27
46235 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
46236 #define F_PERR_RX3_FEC100G_DK V_PERR_RX3_FEC100G_DK(1U)
46238 #define S_PERR_RX2_FEC100G_DK 26
46239 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
46240 #define F_PERR_RX2_FEC100G_DK V_PERR_RX2_FEC100G_DK(1U)
46242 #define S_PERR_RX1_FEC100G_DK 25
46243 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
46244 #define F_PERR_RX1_FEC100G_DK V_PERR_RX1_FEC100G_DK(1U)
46246 #define S_PERR_RX0_FEC100G_DK 24
46247 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
46248 #define F_PERR_RX0_FEC100G_DK V_PERR_RX0_FEC100G_DK(1U)
46250 #define S_PERR_TX3_PCS100G 23
46251 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
46252 #define F_PERR_TX3_PCS100G V_PERR_TX3_PCS100G(1U)
46254 #define S_PERR_TX2_PCS100G 22
46255 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
46256 #define F_PERR_TX2_PCS100G V_PERR_TX2_PCS100G(1U)
46258 #define S_PERR_TX1_PCS100G 21
46259 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
46260 #define F_PERR_TX1_PCS100G V_PERR_TX1_PCS100G(1U)
46262 #define S_PERR_TX0_PCS100G 20
46263 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
46264 #define F_PERR_TX0_PCS100G V_PERR_TX0_PCS100G(1U)
46266 #define S_PERR_RX19_PCS100G 19
46267 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
46268 #define F_PERR_RX19_PCS100G V_PERR_RX19_PCS100G(1U)
46270 #define S_PERR_RX18_PCS100G 18
46271 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
46272 #define F_PERR_RX18_PCS100G V_PERR_RX18_PCS100G(1U)
46274 #define S_PERR_RX17_PCS100G 17
46275 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
46276 #define F_PERR_RX17_PCS100G V_PERR_RX17_PCS100G(1U)
46278 #define S_PERR_RX16_PCS100G 16
46279 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
46280 #define F_PERR_RX16_PCS100G V_PERR_RX16_PCS100G(1U)
46282 #define S_PERR_RX15_PCS100G 15
46283 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
46284 #define F_PERR_RX15_PCS100G V_PERR_RX15_PCS100G(1U)
46286 #define S_PERR_RX14_PCS100G 14
46287 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
46288 #define F_PERR_RX14_PCS100G V_PERR_RX14_PCS100G(1U)
46290 #define S_PERR_RX13_PCS100G 13
46291 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
46292 #define F_PERR_RX13_PCS100G V_PERR_RX13_PCS100G(1U)
46294 #define S_PERR_RX12_PCS100G 12
46295 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
46296 #define F_PERR_RX12_PCS100G V_PERR_RX12_PCS100G(1U)
46298 #define S_PERR_RX11_PCS100G 11
46299 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
46300 #define F_PERR_RX11_PCS100G V_PERR_RX11_PCS100G(1U)
46302 #define S_PERR_RX10_PCS100G 10
46303 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
46304 #define F_PERR_RX10_PCS100G V_PERR_RX10_PCS100G(1U)
46306 #define S_PERR_RX9_PCS100G 9
46307 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
46308 #define F_PERR_RX9_PCS100G V_PERR_RX9_PCS100G(1U)
46310 #define S_PERR_RX8_PCS100G 8
46311 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
46312 #define F_PERR_RX8_PCS100G V_PERR_RX8_PCS100G(1U)
46314 #define S_PERR_RX7_PCS100G 7
46315 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
46316 #define F_PERR_RX7_PCS100G V_PERR_RX7_PCS100G(1U)
46318 #define S_PERR_RX6_PCS100G 6
46319 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
46320 #define F_PERR_RX6_PCS100G V_PERR_RX6_PCS100G(1U)
46322 #define S_PERR_RX5_PCS100G 5
46323 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
46324 #define F_PERR_RX5_PCS100G V_PERR_RX5_PCS100G(1U)
46326 #define S_PERR_RX4_PCS100G 4
46327 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
46328 #define F_PERR_RX4_PCS100G V_PERR_RX4_PCS100G(1U)
46330 #define S_PERR_RX3_PCS100G 3
46331 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
46332 #define F_PERR_RX3_PCS100G V_PERR_RX3_PCS100G(1U)
46334 #define S_PERR_RX2_PCS100G 2
46335 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
46336 #define F_PERR_RX2_PCS100G V_PERR_RX2_PCS100G(1U)
46338 #define S_PERR_RX1_PCS100G 1
46339 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
46340 #define F_PERR_RX1_PCS100G V_PERR_RX1_PCS100G(1U)
46342 #define S_PERR_RX0_PCS100G 0
46343 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
46344 #define F_PERR_RX0_PCS100G V_PERR_RX0_PCS100G(1U)
46346 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
46347 #define A_MAC_PORT_PERR_ENABLE_100G 0x88c
46348 #define A_MAC_PORT_MAC_STAT_DEBUG 0x890
46349 #define A_MAC_PORT_MAC_25G_50G_AM0 0x894
46350 #define A_MAC_PORT_MAC_25G_50G_AM1 0x898
46351 #define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
46352 #define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
46353 #define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
46354 #define A_MAC_PORT_EPIO_DATA0 0x8c0
46355 #define A_MAC_PORT_EPIO_DATA1 0x8c4
46356 #define A_MAC_PORT_EPIO_DATA2 0x8c8
46357 #define A_MAC_PORT_EPIO_DATA3 0x8cc
46358 #define A_MAC_PORT_EPIO_OP 0x8d0
46359 #define A_MAC_PORT_WOL_STATUS 0x8d4
46360 #define A_MAC_PORT_INT_EN 0x8d8
46362 #define S_TX_TS_AVAIL 29
46363 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
46364 #define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U)
46366 #define S_AN_PAGE_RCVD 2
46367 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
46368 #define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U)
46371 #define V_PPS(x) ((x) << S_PPS)
46372 #define F_PPS V_PPS(1U)
46374 #define S_SINGLE_ALARM 28
46375 #define V_SINGLE_ALARM(x) ((x) << S_SINGLE_ALARM)
46376 #define F_SINGLE_ALARM V_SINGLE_ALARM(1U)
46378 #define S_PERIODIC_ALARM 27
46379 #define V_PERIODIC_ALARM(x) ((x) << S_PERIODIC_ALARM)
46380 #define F_PERIODIC_ALARM V_PERIODIC_ALARM(1U)
46382 #define A_MAC_PORT_INT_CAUSE 0x8dc
46383 #define A_MAC_PORT_PERR_INT_EN 0x8e0
46385 #define S_PERR_PKT_RAM 24
46386 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
46387 #define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U)
46389 #define S_PERR_MASK_RAM 23
46390 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
46391 #define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U)
46393 #define S_PERR_CRC_RAM 22
46394 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
46395 #define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U)
46397 #define S_RX_DFF_SEG0 21
46398 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
46399 #define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U)
46401 #define S_RX_SFF_SEG0 20
46402 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
46403 #define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U)
46405 #define S_RX_DFF_MAC10 19
46406 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
46407 #define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U)
46409 #define S_RX_SFF_MAC10 18
46410 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
46411 #define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U)
46413 #define S_TX_DFF_SEG0 17
46414 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
46415 #define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U)
46417 #define S_TX_SFF_SEG0 16
46418 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
46419 #define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U)
46421 #define S_TX_DFF_MAC10 15
46422 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
46423 #define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U)
46425 #define S_TX_SFF_MAC10 14
46426 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
46427 #define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U)
46429 #define S_RX_STATS 13
46430 #define V_RX_STATS(x) ((x) << S_RX_STATS)
46431 #define F_RX_STATS V_RX_STATS(1U)
46433 #define S_TX_STATS 12
46434 #define V_TX_STATS(x) ((x) << S_TX_STATS)
46435 #define F_TX_STATS V_TX_STATS(1U)
46437 #define S_PERR3_RX_MIX 11
46438 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
46439 #define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U)
46441 #define S_PERR3_RX_SD 10
46442 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
46443 #define F_PERR3_RX_SD V_PERR3_RX_SD(1U)
46445 #define S_PERR3_TX 9
46446 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
46447 #define F_PERR3_TX V_PERR3_TX(1U)
46449 #define S_PERR2_RX_MIX 8
46450 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
46451 #define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U)
46453 #define S_PERR2_RX_SD 7
46454 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
46455 #define F_PERR2_RX_SD V_PERR2_RX_SD(1U)
46457 #define S_PERR2_TX 6
46458 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
46459 #define F_PERR2_TX V_PERR2_TX(1U)
46461 #define S_PERR1_RX_MIX 5
46462 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
46463 #define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U)
46465 #define S_PERR1_RX_SD 4
46466 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
46467 #define F_PERR1_RX_SD V_PERR1_RX_SD(1U)
46469 #define S_PERR1_TX 3
46470 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
46471 #define F_PERR1_TX V_PERR1_TX(1U)
46473 #define S_PERR0_RX_MIX 2
46474 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
46475 #define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U)
46477 #define S_PERR0_RX_SD 1
46478 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
46479 #define F_PERR0_RX_SD V_PERR0_RX_SD(1U)
46481 #define S_PERR0_TX 0
46482 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
46483 #define F_PERR0_TX V_PERR0_TX(1U)
46485 #define S_T6_PERR_PKT_RAM 31
46486 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46487 #define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U)
46489 #define S_T6_PERR_MASK_RAM 30
46490 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46491 #define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U)
46493 #define S_T6_PERR_CRC_RAM 29
46494 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46495 #define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U)
46497 #define S_RX_MAC40G 28
46498 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
46499 #define F_RX_MAC40G V_RX_MAC40G(1U)
46501 #define S_TX_MAC40G 27
46502 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
46503 #define F_TX_MAC40G V_TX_MAC40G(1U)
46505 #define S_RX_ST_MAC40G 26
46506 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
46507 #define F_RX_ST_MAC40G V_RX_ST_MAC40G(1U)
46509 #define S_TX_ST_MAC40G 25
46510 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
46511 #define F_TX_ST_MAC40G V_TX_ST_MAC40G(1U)
46513 #define S_TX_MAC1G10G 24
46514 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
46515 #define F_TX_MAC1G10G V_TX_MAC1G10G(1U)
46517 #define S_RX_MAC1G10G 23
46518 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
46519 #define F_RX_MAC1G10G V_RX_MAC1G10G(1U)
46521 #define S_RX_STATUS_MAC1G10G 22
46522 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
46523 #define F_RX_STATUS_MAC1G10G V_RX_STATUS_MAC1G10G(1U)
46525 #define S_RX_ST_MAC1G10G 21
46526 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
46527 #define F_RX_ST_MAC1G10G V_RX_ST_MAC1G10G(1U)
46529 #define S_TX_ST_MAC1G10G 20
46530 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
46531 #define F_TX_ST_MAC1G10G V_TX_ST_MAC1G10G(1U)
46533 #define S_PERR_TX0_PCS40G 19
46534 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
46535 #define F_PERR_TX0_PCS40G V_PERR_TX0_PCS40G(1U)
46537 #define S_PERR_TX1_PCS40G 18
46538 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
46539 #define F_PERR_TX1_PCS40G V_PERR_TX1_PCS40G(1U)
46541 #define S_PERR_TX2_PCS40G 17
46542 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
46543 #define F_PERR_TX2_PCS40G V_PERR_TX2_PCS40G(1U)
46545 #define S_PERR_TX3_PCS40G 16
46546 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
46547 #define F_PERR_TX3_PCS40G V_PERR_TX3_PCS40G(1U)
46549 #define S_PERR_TX0_FEC40G 15
46550 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
46551 #define F_PERR_TX0_FEC40G V_PERR_TX0_FEC40G(1U)
46553 #define S_PERR_TX1_FEC40G 14
46554 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
46555 #define F_PERR_TX1_FEC40G V_PERR_TX1_FEC40G(1U)
46557 #define S_PERR_TX2_FEC40G 13
46558 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
46559 #define F_PERR_TX2_FEC40G V_PERR_TX2_FEC40G(1U)
46561 #define S_PERR_TX3_FEC40G 12
46562 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
46563 #define F_PERR_TX3_FEC40G V_PERR_TX3_FEC40G(1U)
46565 #define S_PERR_RX0_PCS40G 11
46566 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
46567 #define F_PERR_RX0_PCS40G V_PERR_RX0_PCS40G(1U)
46569 #define S_PERR_RX1_PCS40G 10
46570 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
46571 #define F_PERR_RX1_PCS40G V_PERR_RX1_PCS40G(1U)
46573 #define S_PERR_RX2_PCS40G 9
46574 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
46575 #define F_PERR_RX2_PCS40G V_PERR_RX2_PCS40G(1U)
46577 #define S_PERR_RX3_PCS40G 8
46578 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
46579 #define F_PERR_RX3_PCS40G V_PERR_RX3_PCS40G(1U)
46581 #define S_PERR_RX0_FEC40G 7
46582 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
46583 #define F_PERR_RX0_FEC40G V_PERR_RX0_FEC40G(1U)
46585 #define S_PERR_RX1_FEC40G 6
46586 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
46587 #define F_PERR_RX1_FEC40G V_PERR_RX1_FEC40G(1U)
46589 #define S_PERR_RX2_FEC40G 5
46590 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
46591 #define F_PERR_RX2_FEC40G V_PERR_RX2_FEC40G(1U)
46593 #define S_PERR_RX3_FEC40G 4
46594 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
46595 #define F_PERR_RX3_FEC40G V_PERR_RX3_FEC40G(1U)
46597 #define S_PERR_RX_PCS10G_LPBK 3
46598 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
46599 #define F_PERR_RX_PCS10G_LPBK V_PERR_RX_PCS10G_LPBK(1U)
46601 #define S_PERR_RX_PCS10G 2
46602 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
46603 #define F_PERR_RX_PCS10G V_PERR_RX_PCS10G(1U)
46605 #define S_PERR_RX_PCS1G 1
46606 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
46607 #define F_PERR_RX_PCS1G V_PERR_RX_PCS1G(1U)
46609 #define S_PERR_TX_PCS1G 0
46610 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
46611 #define F_PERR_TX_PCS1G V_PERR_TX_PCS1G(1U)
46613 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
46615 #define S_T6_PERR_PKT_RAM 31
46616 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46617 #define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U)
46619 #define S_T6_PERR_MASK_RAM 30
46620 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46621 #define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U)
46623 #define S_T6_PERR_CRC_RAM 29
46624 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46625 #define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U)
46627 #define A_MAC_PORT_PERR_ENABLE 0x8e8
46629 #define S_T6_PERR_PKT_RAM 31
46630 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46631 #define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U)
46633 #define S_T6_PERR_MASK_RAM 30
46634 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46635 #define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U)
46637 #define S_T6_PERR_CRC_RAM 29
46638 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46639 #define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U)
46641 #define A_MAC_PORT_PERR_INJECT 0x8ec
46643 #define S_MEMSEL_PERR 1
46644 #define M_MEMSEL_PERR 0x3fU
46645 #define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR)
46646 #define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR)
46648 #define A_MAC_PORT_HSS_CFG0 0x8f0
46650 #define S_HSSREFCLKVALIDA 20
46651 #define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
46652 #define F_HSSREFCLKVALIDA V_HSSREFCLKVALIDA(1U)
46654 #define S_HSSREFCLKVALIDB 19
46655 #define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
46656 #define F_HSSREFCLKVALIDB V_HSSREFCLKVALIDB(1U)
46658 #define S_HSSRESYNCA 18
46659 #define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
46660 #define F_HSSRESYNCA V_HSSRESYNCA(1U)
46662 #define S_HSSRESYNCB 16
46663 #define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
46664 #define F_HSSRESYNCB V_HSSRESYNCB(1U)
46666 #define S_HSSRECCALA 15
46667 #define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
46668 #define F_HSSRECCALA V_HSSRECCALA(1U)
46670 #define S_HSSRECCALB 13
46671 #define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
46672 #define F_HSSRECCALB V_HSSRECCALB(1U)
46674 #define S_HSSPLLBYPA 12
46675 #define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
46676 #define F_HSSPLLBYPA V_HSSPLLBYPA(1U)
46678 #define S_HSSPLLBYPB 11
46679 #define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
46680 #define F_HSSPLLBYPB V_HSSPLLBYPB(1U)
46682 #define S_HSSPDWNPLLA 10
46683 #define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
46684 #define F_HSSPDWNPLLA V_HSSPDWNPLLA(1U)
46686 #define S_HSSPDWNPLLB 9
46687 #define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
46688 #define F_HSSPDWNPLLB V_HSSPDWNPLLB(1U)
46690 #define S_HSSVCOSELA 8
46691 #define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
46692 #define F_HSSVCOSELA V_HSSVCOSELA(1U)
46694 #define S_HSSVCOSELB 7
46695 #define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
46696 #define F_HSSVCOSELB V_HSSVCOSELB(1U)
46698 #define S_HSSCALCOMP 6
46699 #define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
46700 #define F_HSSCALCOMP V_HSSCALCOMP(1U)
46702 #define S_HSSCALENAB 5
46703 #define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
46704 #define F_HSSCALENAB V_HSSCALENAB(1U)
46706 #define A_MAC_PORT_HSS_CFG1 0x8f4
46708 #define S_RXACONFIGSEL 30
46709 #define M_RXACONFIGSEL 0x3U
46710 #define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
46711 #define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
46713 #define S_RXAQUIET 29
46714 #define V_RXAQUIET(x) ((x) << S_RXAQUIET)
46715 #define F_RXAQUIET V_RXAQUIET(1U)
46717 #define S_RXAREFRESH 28
46718 #define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
46719 #define F_RXAREFRESH V_RXAREFRESH(1U)
46721 #define S_RXBCONFIGSEL 26
46722 #define M_RXBCONFIGSEL 0x3U
46723 #define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
46724 #define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
46726 #define S_RXBQUIET 25
46727 #define V_RXBQUIET(x) ((x) << S_RXBQUIET)
46728 #define F_RXBQUIET V_RXBQUIET(1U)
46730 #define S_RXBREFRESH 24
46731 #define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
46732 #define F_RXBREFRESH V_RXBREFRESH(1U)
46734 #define S_RXCCONFIGSEL 22
46735 #define M_RXCCONFIGSEL 0x3U
46736 #define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
46737 #define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
46739 #define S_RXCQUIET 21
46740 #define V_RXCQUIET(x) ((x) << S_RXCQUIET)
46741 #define F_RXCQUIET V_RXCQUIET(1U)
46743 #define S_RXCREFRESH 20
46744 #define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
46745 #define F_RXCREFRESH V_RXCREFRESH(1U)
46747 #define S_RXDCONFIGSEL 18
46748 #define M_RXDCONFIGSEL 0x3U
46749 #define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
46750 #define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
46752 #define S_RXDQUIET 17
46753 #define V_RXDQUIET(x) ((x) << S_RXDQUIET)
46754 #define F_RXDQUIET V_RXDQUIET(1U)
46756 #define S_RXDREFRESH 16
46757 #define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
46758 #define F_RXDREFRESH V_RXDREFRESH(1U)
46760 #define S_TXACONFIGSEL 14
46761 #define M_TXACONFIGSEL 0x3U
46762 #define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
46763 #define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
46765 #define S_TXAQUIET 13
46766 #define V_TXAQUIET(x) ((x) << S_TXAQUIET)
46767 #define F_TXAQUIET V_TXAQUIET(1U)
46769 #define S_TXAREFRESH 12
46770 #define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
46771 #define F_TXAREFRESH V_TXAREFRESH(1U)
46773 #define S_TXBCONFIGSEL 10
46774 #define M_TXBCONFIGSEL 0x3U
46775 #define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
46776 #define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
46778 #define S_TXBQUIET 9
46779 #define V_TXBQUIET(x) ((x) << S_TXBQUIET)
46780 #define F_TXBQUIET V_TXBQUIET(1U)
46782 #define S_TXBREFRESH 8
46783 #define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
46784 #define F_TXBREFRESH V_TXBREFRESH(1U)
46786 #define S_TXCCONFIGSEL 6
46787 #define M_TXCCONFIGSEL 0x3U
46788 #define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
46789 #define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
46791 #define S_TXCQUIET 5
46792 #define V_TXCQUIET(x) ((x) << S_TXCQUIET)
46793 #define F_TXCQUIET V_TXCQUIET(1U)
46795 #define S_TXCREFRESH 4
46796 #define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
46797 #define F_TXCREFRESH V_TXCREFRESH(1U)
46799 #define S_TXDCONFIGSEL 2
46800 #define M_TXDCONFIGSEL 0x3U
46801 #define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
46802 #define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
46804 #define S_TXDQUIET 1
46805 #define V_TXDQUIET(x) ((x) << S_TXDQUIET)
46806 #define F_TXDQUIET V_TXDQUIET(1U)
46808 #define S_TXDREFRESH 0
46809 #define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
46810 #define F_TXDREFRESH V_TXDREFRESH(1U)
46812 #define A_MAC_PORT_HSS_CFG2 0x8f8
46814 #define S_RXAASSTCLK 31
46815 #define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
46816 #define F_RXAASSTCLK V_RXAASSTCLK(1U)
46818 #define S_T5RXAPRBSRST 30
46819 #define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
46820 #define F_T5RXAPRBSRST V_T5RXAPRBSRST(1U)
46822 #define S_RXBASSTCLK 29
46823 #define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
46824 #define F_RXBASSTCLK V_RXBASSTCLK(1U)
46826 #define S_T5RXBPRBSRST 28
46827 #define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
46828 #define F_T5RXBPRBSRST V_T5RXBPRBSRST(1U)
46830 #define S_RXCASSTCLK 27
46831 #define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
46832 #define F_RXCASSTCLK V_RXCASSTCLK(1U)
46834 #define S_T5RXCPRBSRST 26
46835 #define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
46836 #define F_T5RXCPRBSRST V_T5RXCPRBSRST(1U)
46838 #define S_RXDASSTCLK 25
46839 #define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
46840 #define F_RXDASSTCLK V_RXDASSTCLK(1U)
46842 #define S_T5RXDPRBSRST 24
46843 #define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
46844 #define F_T5RXDPRBSRST V_T5RXDPRBSRST(1U)
46846 #define A_MAC_PORT_HSS_CFG3 0x8fc
46848 #define S_HSSCALSSTN 25
46849 #define M_HSSCALSSTN 0x7U
46850 #define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
46851 #define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
46853 #define S_HSSCALSSTP 22
46854 #define M_HSSCALSSTP 0x7U
46855 #define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
46856 #define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
46858 #define S_HSSVBOOSTDIVB 19
46859 #define M_HSSVBOOSTDIVB 0x7U
46860 #define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
46861 #define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
46863 #define S_HSSVBOOSTDIVA 16
46864 #define M_HSSVBOOSTDIVA 0x7U
46865 #define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
46866 #define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
46868 #define S_HSSPLLCONFIGB 8
46869 #define M_HSSPLLCONFIGB 0xffU
46870 #define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
46871 #define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
46873 #define S_HSSPLLCONFIGA 0
46874 #define M_HSSPLLCONFIGA 0xffU
46875 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
46876 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
46878 #define S_T6_HSSCALSSTN 22
46879 #define M_T6_HSSCALSSTN 0x3fU
46880 #define V_T6_HSSCALSSTN(x) ((x) << S_T6_HSSCALSSTN)
46881 #define G_T6_HSSCALSSTN(x) (((x) >> S_T6_HSSCALSSTN) & M_T6_HSSCALSSTN)
46883 #define S_T6_HSSCALSSTP 16
46884 #define M_T6_HSSCALSSTP 0x3fU
46885 #define V_T6_HSSCALSSTP(x) ((x) << S_T6_HSSCALSSTP)
46886 #define G_T6_HSSCALSSTP(x) (((x) >> S_T6_HSSCALSSTP) & M_T6_HSSCALSSTP)
46888 #define A_MAC_PORT_HSS_CFG4 0x900
46890 #define S_HSSDIVSELA 9
46891 #define M_HSSDIVSELA 0x1ffU
46892 #define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
46893 #define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
46895 #define S_HSSDIVSELB 0
46896 #define M_HSSDIVSELB 0x1ffU
46897 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
46898 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
46900 #define S_HSSREFDIVA 24
46901 #define M_HSSREFDIVA 0xfU
46902 #define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA)
46903 #define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA)
46905 #define S_HSSREFDIVB 20
46906 #define M_HSSREFDIVB 0xfU
46907 #define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB)
46908 #define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB)
46910 #define S_HSSPLLDIV2B 19
46911 #define V_HSSPLLDIV2B(x) ((x) << S_HSSPLLDIV2B)
46912 #define F_HSSPLLDIV2B V_HSSPLLDIV2B(1U)
46914 #define S_HSSPLLDIV2A 18
46915 #define V_HSSPLLDIV2A(x) ((x) << S_HSSPLLDIV2A)
46916 #define F_HSSPLLDIV2A V_HSSPLLDIV2A(1U)
46918 #define A_MAC_PORT_HSS_STATUS 0x904
46920 #define S_HSSPLLLOCKB 3
46921 #define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
46922 #define F_HSSPLLLOCKB V_HSSPLLLOCKB(1U)
46924 #define S_HSSPLLLOCKA 2
46925 #define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
46926 #define F_HSSPLLLOCKA V_HSSPLLLOCKA(1U)
46928 #define S_HSSPRTREADYB 1
46929 #define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
46930 #define F_HSSPRTREADYB V_HSSPRTREADYB(1U)
46932 #define S_HSSPRTREADYA 0
46933 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
46934 #define F_HSSPRTREADYA V_HSSPRTREADYA(1U)
46936 #define S_RXDERROFLOW 19
46937 #define V_RXDERROFLOW(x) ((x) << S_RXDERROFLOW)
46938 #define F_RXDERROFLOW V_RXDERROFLOW(1U)
46940 #define S_RXCERROFLOW 18
46941 #define V_RXCERROFLOW(x) ((x) << S_RXCERROFLOW)
46942 #define F_RXCERROFLOW V_RXCERROFLOW(1U)
46944 #define S_RXBERROFLOW 17
46945 #define V_RXBERROFLOW(x) ((x) << S_RXBERROFLOW)
46946 #define F_RXBERROFLOW V_RXBERROFLOW(1U)
46948 #define S_RXAERROFLOW 16
46949 #define V_RXAERROFLOW(x) ((x) << S_RXAERROFLOW)
46950 #define F_RXAERROFLOW V_RXAERROFLOW(1U)
46952 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
46954 #define S_RXAQUIET_STATUS 15
46955 #define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
46956 #define F_RXAQUIET_STATUS V_RXAQUIET_STATUS(1U)
46958 #define S_RXAREFRESH_STATUS 14
46959 #define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
46960 #define F_RXAREFRESH_STATUS V_RXAREFRESH_STATUS(1U)
46962 #define S_RXBQUIET_STATUS 13
46963 #define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
46964 #define F_RXBQUIET_STATUS V_RXBQUIET_STATUS(1U)
46966 #define S_RXBREFRESH_STATUS 12
46967 #define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
46968 #define F_RXBREFRESH_STATUS V_RXBREFRESH_STATUS(1U)
46970 #define S_RXCQUIET_STATUS 11
46971 #define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
46972 #define F_RXCQUIET_STATUS V_RXCQUIET_STATUS(1U)
46974 #define S_RXCREFRESH_STATUS 10
46975 #define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
46976 #define F_RXCREFRESH_STATUS V_RXCREFRESH_STATUS(1U)
46978 #define S_RXDQUIET_STATUS 9
46979 #define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
46980 #define F_RXDQUIET_STATUS V_RXDQUIET_STATUS(1U)
46982 #define S_RXDREFRESH_STATUS 8
46983 #define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
46984 #define F_RXDREFRESH_STATUS V_RXDREFRESH_STATUS(1U)
46986 #define S_TXAQUIET_STATUS 7
46987 #define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
46988 #define F_TXAQUIET_STATUS V_TXAQUIET_STATUS(1U)
46990 #define S_TXAREFRESH_STATUS 6
46991 #define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
46992 #define F_TXAREFRESH_STATUS V_TXAREFRESH_STATUS(1U)
46994 #define S_TXBQUIET_STATUS 5
46995 #define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
46996 #define F_TXBQUIET_STATUS V_TXBQUIET_STATUS(1U)
46998 #define S_TXBREFRESH_STATUS 4
46999 #define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
47000 #define F_TXBREFRESH_STATUS V_TXBREFRESH_STATUS(1U)
47002 #define S_TXCQUIET_STATUS 3
47003 #define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
47004 #define F_TXCQUIET_STATUS V_TXCQUIET_STATUS(1U)
47006 #define S_TXCREFRESH_STATUS 2
47007 #define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
47008 #define F_TXCREFRESH_STATUS V_TXCREFRESH_STATUS(1U)
47010 #define S_TXDQUIET_STATUS 1
47011 #define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
47012 #define F_TXDQUIET_STATUS V_TXDQUIET_STATUS(1U)
47014 #define S_TXDREFRESH_STATUS 0
47015 #define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
47016 #define F_TXDREFRESH_STATUS V_TXDREFRESH_STATUS(1U)
47018 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
47019 #define A_MAC_PORT_HSS_PL_CTL 0x910
47022 #define M_TOV 0xffU
47023 #define V_TOV(x) ((x) << S_TOV)
47024 #define G_TOV(x) (((x) >> S_TOV) & M_TOV)
47027 #define M_TSU 0xffU
47028 #define V_TSU(x) ((x) << S_TSU)
47029 #define G_TSU(x) (((x) >> S_TSU) & M_TSU)
47032 #define M_IPW 0xffU
47033 #define V_IPW(x) ((x) << S_IPW)
47034 #define G_IPW(x) (((x) >> S_IPW) & M_IPW)
47036 #define A_MAC_PORT_RUNT_FRAME 0x914
47038 #define S_RUNTCLEAR 16
47039 #define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
47040 #define F_RUNTCLEAR V_RUNTCLEAR(1U)
47043 #define M_RUNT 0xffffU
47044 #define V_RUNT(x) ((x) << S_RUNT)
47045 #define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
47047 #define A_MAC_PORT_EEE_STATUS 0x918
47049 #define S_EEE_TX_10G_STATE 10
47050 #define M_EEE_TX_10G_STATE 0x3U
47051 #define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
47052 #define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
47054 #define S_EEE_RX_10G_STATE 8
47055 #define M_EEE_RX_10G_STATE 0x3U
47056 #define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
47057 #define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
47059 #define S_EEE_TX_1G_STATE 6
47060 #define M_EEE_TX_1G_STATE 0x3U
47061 #define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
47062 #define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
47064 #define S_EEE_RX_1G_STATE 4
47065 #define M_EEE_RX_1G_STATE 0x3U
47066 #define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
47067 #define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
47069 #define S_PMA_RX_REFRESH 3
47070 #define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
47071 #define F_PMA_RX_REFRESH V_PMA_RX_REFRESH(1U)
47073 #define S_PMA_RX_QUIET 2
47074 #define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
47075 #define F_PMA_RX_QUIET V_PMA_RX_QUIET(1U)
47077 #define S_PMA_TX_REFRESH 1
47078 #define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
47079 #define F_PMA_TX_REFRESH V_PMA_TX_REFRESH(1U)
47081 #define S_PMA_TX_QUIET 0
47082 #define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
47083 #define F_PMA_TX_QUIET V_PMA_TX_QUIET(1U)
47085 #define A_MAC_PORT_CGEN 0x91c
47088 #define V_CGEN(x) ((x) << S_CGEN)
47089 #define F_CGEN V_CGEN(1U)
47091 #define S_SD7_CGEN 7
47092 #define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
47093 #define F_SD7_CGEN V_SD7_CGEN(1U)
47095 #define S_SD6_CGEN 6
47096 #define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
47097 #define F_SD6_CGEN V_SD6_CGEN(1U)
47099 #define S_SD5_CGEN 5
47100 #define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
47101 #define F_SD5_CGEN V_SD5_CGEN(1U)
47103 #define S_SD4_CGEN 4
47104 #define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
47105 #define F_SD4_CGEN V_SD4_CGEN(1U)
47107 #define S_SD3_CGEN 3
47108 #define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
47109 #define F_SD3_CGEN V_SD3_CGEN(1U)
47111 #define S_SD2_CGEN 2
47112 #define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
47113 #define F_SD2_CGEN V_SD2_CGEN(1U)
47115 #define S_SD1_CGEN 1
47116 #define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
47117 #define F_SD1_CGEN V_SD1_CGEN(1U)
47119 #define S_SD0_CGEN 0
47120 #define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
47121 #define F_SD0_CGEN V_SD0_CGEN(1U)
47123 #define A_MAC_PORT_CGEN_MTIP 0x920
47125 #define S_MACSEG5_CGEN 11
47126 #define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
47127 #define F_MACSEG5_CGEN V_MACSEG5_CGEN(1U)
47129 #define S_PCSSEG5_CGEN 10
47130 #define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
47131 #define F_PCSSEG5_CGEN V_PCSSEG5_CGEN(1U)
47133 #define S_MACSEG4_CGEN 9
47134 #define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
47135 #define F_MACSEG4_CGEN V_MACSEG4_CGEN(1U)
47137 #define S_PCSSEG4_CGEN 8
47138 #define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
47139 #define F_PCSSEG4_CGEN V_PCSSEG4_CGEN(1U)
47141 #define S_MACSEG3_CGEN 7
47142 #define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
47143 #define F_MACSEG3_CGEN V_MACSEG3_CGEN(1U)
47145 #define S_PCSSEG3_CGEN 6
47146 #define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
47147 #define F_PCSSEG3_CGEN V_PCSSEG3_CGEN(1U)
47149 #define S_MACSEG2_CGEN 5
47150 #define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
47151 #define F_MACSEG2_CGEN V_MACSEG2_CGEN(1U)
47153 #define S_PCSSEG2_CGEN 4
47154 #define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
47155 #define F_PCSSEG2_CGEN V_PCSSEG2_CGEN(1U)
47157 #define S_MACSEG1_CGEN 3
47158 #define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
47159 #define F_MACSEG1_CGEN V_MACSEG1_CGEN(1U)
47161 #define S_PCSSEG1_CGEN 2
47162 #define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
47163 #define F_PCSSEG1_CGEN V_PCSSEG1_CGEN(1U)
47165 #define S_MACSEG0_CGEN 1
47166 #define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
47167 #define F_MACSEG0_CGEN V_MACSEG0_CGEN(1U)
47169 #define S_PCSSEG0_CGEN 0
47170 #define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
47171 #define F_PCSSEG0_CGEN V_PCSSEG0_CGEN(1U)
47173 #define A_MAC_PORT_TX_TS_ID 0x924
47176 #define M_TS_ID 0x7U
47177 #define V_TS_ID(x) ((x) << S_TS_ID)
47178 #define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
47180 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
47181 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
47182 #define A_MAC_PORT_EEE_CTL 0x930
47184 #define S_EEE_CTRL 2
47185 #define M_EEE_CTRL 0x3fffffffU
47186 #define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
47187 #define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
47189 #define S_TICK_START 1
47190 #define V_TICK_START(x) ((x) << S_TICK_START)
47191 #define F_TICK_START V_TICK_START(1U)
47193 #define S_EEE_ENABLE 0
47194 #define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
47195 #define F_EEE_ENABLE V_EEE_ENABLE(1U)
47197 #define A_MAC_PORT_EEE_TX_CTL 0x934
47199 #define S_WAKE_TIMER 16
47200 #define M_WAKE_TIMER 0xffffU
47201 #define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
47202 #define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
47204 #define S_HSS_TIMER 5
47205 #define M_HSS_TIMER 0xfU
47206 #define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
47207 #define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
47209 #define S_HSS_CTL 4
47210 #define V_HSS_CTL(x) ((x) << S_HSS_CTL)
47211 #define F_HSS_CTL V_HSS_CTL(1U)
47213 #define S_LPI_ACTIVE 3
47214 #define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
47215 #define F_LPI_ACTIVE V_LPI_ACTIVE(1U)
47217 #define S_LPI_TXHOLD 2
47218 #define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
47219 #define F_LPI_TXHOLD V_LPI_TXHOLD(1U)
47221 #define S_LPI_REQ 1
47222 #define V_LPI_REQ(x) ((x) << S_LPI_REQ)
47223 #define F_LPI_REQ V_LPI_REQ(1U)
47225 #define S_EEE_TX_RESET 0
47226 #define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
47227 #define F_EEE_TX_RESET V_EEE_TX_RESET(1U)
47229 #define A_MAC_PORT_EEE_RX_CTL 0x938
47231 #define S_LPI_IND 1
47232 #define V_LPI_IND(x) ((x) << S_LPI_IND)
47233 #define F_LPI_IND V_LPI_IND(1U)
47235 #define S_EEE_RX_RESET 0
47236 #define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
47237 #define F_EEE_RX_RESET V_EEE_RX_RESET(1U)
47239 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
47240 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
47241 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
47242 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
47243 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
47244 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
47245 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
47246 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
47247 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
47248 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
47249 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
47250 #define A_MAC_PORT_EEE_WF_COUNT 0x968
47252 #define S_WAKE_CNT_CLR 16
47253 #define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
47254 #define F_WAKE_CNT_CLR V_WAKE_CNT_CLR(1U)
47256 #define S_WAKE_CNT 0
47257 #define M_WAKE_CNT 0xffffU
47258 #define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
47259 #define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
47261 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
47262 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
47263 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
47264 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
47265 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
47266 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
47267 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
47268 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
47269 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
47271 #define S_PTP_OFFSET 0
47272 #define M_PTP_OFFSET 0xffU
47273 #define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
47274 #define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
47276 #define A_MAC_PORT_PTP_SUM_LO 0x990
47277 #define A_MAC_PORT_PTP_SUM_HI 0x994
47278 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
47281 #define M_Y 0xffffU
47282 #define V_Y(x) ((x) << S_Y)
47283 #define G_Y(x) (((x) >> S_Y) & M_Y)
47286 #define M_X 0xffffU
47287 #define V_X(x) ((x) << S_X)
47288 #define G_X(x) (((x) >> S_X) & M_X)
47290 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
47292 #define S_Y_TICK 16
47293 #define M_Y_TICK 0xffffU
47294 #define V_Y_TICK(x) ((x) << S_Y_TICK)
47295 #define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
47298 #define M_X_TICK 0xffffU
47299 #define V_X_TICK(x) ((x) << S_X_TICK)
47300 #define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
47302 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
47303 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
47306 #define CXGBE_M_B 0xffffU
47307 #define V_B(x) ((x) << S_B)
47308 #define G_B(x) (((x) >> S_B) & CXGBE_M_B)
47311 #define M_A 0xffffU
47312 #define V_A(x) ((x) << S_A)
47313 #define G_A(x) (((x) >> S_A) & M_A)
47315 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
47316 #define A_MAC_PORT_PTP_CFG 0x9ac
47319 #define V_FRZ(x) ((x) << S_FRZ)
47320 #define F_FRZ V_FRZ(1U)
47322 #define S_OFFSER_ADJUST_SIGN 17
47323 #define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
47324 #define F_OFFSER_ADJUST_SIGN V_OFFSER_ADJUST_SIGN(1U)
47326 #define S_ADD_OFFSET 16
47327 #define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
47328 #define F_ADD_OFFSET V_ADD_OFFSET(1U)
47331 #define M_CYCLE1 0xffU
47332 #define V_CYCLE1(x) ((x) << S_CYCLE1)
47333 #define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
47337 #define V_Q(x) ((x) << S_Q)
47338 #define G_Q(x) (((x) >> S_Q) & M_Q)
47340 #define S_ALARM_EN 21
47341 #define V_ALARM_EN(x) ((x) << S_ALARM_EN)
47342 #define F_ALARM_EN V_ALARM_EN(1U)
47344 #define S_ALARM_START 20
47345 #define V_ALARM_START(x) ((x) << S_ALARM_START)
47346 #define F_ALARM_START V_ALARM_START(1U)
47348 #define S_PPS_EN 19
47349 #define V_PPS_EN(x) ((x) << S_PPS_EN)
47350 #define F_PPS_EN V_PPS_EN(1U)
47352 #define A_MAC_PORT_PTP_PPS 0x9b0
47353 #define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
47354 #define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
47355 #define A_MAC_PORT_PTP_STATUS 0x9bc
47357 #define S_ALARM_DONE 0
47358 #define V_ALARM_DONE(x) ((x) << S_ALARM_DONE)
47359 #define F_ALARM_DONE V_ALARM_DONE(1U)
47361 #define A_MAC_PORT_MTIP_REVISION 0xa00
47363 #define S_CUSTREV 16
47364 #define M_CUSTREV 0xffffU
47365 #define V_CUSTREV(x) ((x) << S_CUSTREV)
47366 #define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
47369 #define M_VER 0xffU
47370 #define V_VER(x) ((x) << S_VER)
47371 #define G_VER(x) (((x) >> S_VER) & M_VER)
47373 #define S_MTIP_REV 0
47374 #define M_MTIP_REV 0xffU
47375 #define V_MTIP_REV(x) ((x) << S_MTIP_REV)
47376 #define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
47378 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
47379 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
47381 #define S_TX_FLUSH_ENABLE 22
47382 #define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
47383 #define F_TX_FLUSH_ENABLE V_TX_FLUSH_ENABLE(1U)
47385 #define S_RX_SFD_ANY 21
47386 #define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
47387 #define F_RX_SFD_ANY V_RX_SFD_ANY(1U)
47389 #define S_PAUSE_PFC_COMP 20
47390 #define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
47391 #define F_PAUSE_PFC_COMP V_PAUSE_PFC_COMP(1U)
47393 #define S_PFC_MODE 19
47394 #define V_PFC_MODE(x) ((x) << S_PFC_MODE)
47395 #define F_PFC_MODE V_PFC_MODE(1U)
47397 #define S_RS_COL_CNT_EXT 18
47398 #define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
47399 #define F_RS_COL_CNT_EXT V_RS_COL_CNT_EXT(1U)
47401 #define S_NO_LGTH_CHECK 17
47402 #define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
47403 #define F_NO_LGTH_CHECK V_NO_LGTH_CHECK(1U)
47405 #define S_SEND_IDLE 16
47406 #define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
47407 #define F_SEND_IDLE V_SEND_IDLE(1U)
47409 #define S_PHY_TXENA 15
47410 #define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
47411 #define F_PHY_TXENA V_PHY_TXENA(1U)
47413 #define S_RX_ERR_DISC 14
47414 #define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
47415 #define F_RX_ERR_DISC V_RX_ERR_DISC(1U)
47417 #define S_CMD_FRAME_ENA 13
47418 #define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
47419 #define F_CMD_FRAME_ENA V_CMD_FRAME_ENA(1U)
47421 #define S_SW_RESET 12
47422 #define V_SW_RESET(x) ((x) << S_SW_RESET)
47423 #define F_SW_RESET V_SW_RESET(1U)
47425 #define S_TX_PAD_EN 11
47426 #define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
47427 #define F_TX_PAD_EN V_TX_PAD_EN(1U)
47429 #define S_PHY_LOOPBACK_EN 10
47430 #define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
47431 #define F_PHY_LOOPBACK_EN V_PHY_LOOPBACK_EN(1U)
47433 #define S_TX_ADDR_INS 9
47434 #define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
47435 #define F_TX_ADDR_INS V_TX_ADDR_INS(1U)
47437 #define S_PAUSE_IGNORE 8
47438 #define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
47439 #define F_PAUSE_IGNORE V_PAUSE_IGNORE(1U)
47441 #define S_PAUSE_FWD 7
47442 #define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
47443 #define F_PAUSE_FWD V_PAUSE_FWD(1U)
47445 #define S_CRC_FWD 6
47446 #define V_CRC_FWD(x) ((x) << S_CRC_FWD)
47447 #define F_CRC_FWD V_CRC_FWD(1U)
47450 #define V_PAD_EN(x) ((x) << S_PAD_EN)
47451 #define F_PAD_EN V_PAD_EN(1U)
47453 #define S_PROMIS_EN 4
47454 #define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
47455 #define F_PROMIS_EN V_PROMIS_EN(1U)
47457 #define S_WAN_MODE 3
47458 #define V_WAN_MODE(x) ((x) << S_WAN_MODE)
47459 #define F_WAN_MODE V_WAN_MODE(1U)
47462 #define V_RX_ENA(x) ((x) << S_RX_ENA)
47463 #define F_RX_ENA V_RX_ENA(1U)
47466 #define V_TX_ENA(x) ((x) << S_TX_ENA)
47467 #define F_TX_ENA V_TX_ENA(1U)
47469 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
47470 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
47472 #define S_MACADDRHI 0
47473 #define M_MACADDRHI 0xffffU
47474 #define V_MACADDRHI(x) ((x) << S_MACADDRHI)
47475 #define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
47477 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
47480 #define M_LEN 0xffffU
47481 #define V_LEN(x) ((x) << S_LEN)
47482 #define G_LEN(x) (((x) >> S_LEN) & M_LEN)
47484 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
47487 #define M_AVAIL 0xffffU
47488 #define V_AVAIL(x) ((x) << S_AVAIL)
47489 #define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
47492 #define M_EMPTY 0xffffU
47493 #define V_EMPTY(x) ((x) << S_EMPTY)
47494 #define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
47496 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
47497 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
47499 #define S_ALMSTFULL 16
47500 #define M_ALMSTFULL 0xffffU
47501 #define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
47502 #define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
47504 #define S_ALMSTEMPTY 0
47505 #define M_ALMSTEMPTY 0xffffU
47506 #define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
47507 #define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
47509 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
47510 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
47512 #define S_ENABLE_MCAST_RX 8
47513 #define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
47514 #define F_ENABLE_MCAST_RX V_ENABLE_MCAST_RX(1U)
47516 #define S_HASHTABLE_ADDR 0
47517 #define M_HASHTABLE_ADDR 0x3fU
47518 #define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
47519 #define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
47521 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
47523 #define S_TS_AVAIL 3
47524 #define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
47525 #define F_TS_AVAIL V_TS_AVAIL(1U)
47527 #define S_PHY_LOS 2
47528 #define V_PHY_LOS(x) ((x) << S_PHY_LOS)
47529 #define F_PHY_LOS V_PHY_LOS(1U)
47531 #define S_RX_REM_FAULT 1
47532 #define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
47533 #define F_RX_REM_FAULT V_RX_REM_FAULT(1U)
47535 #define S_RX_LOC_FAULT 0
47536 #define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
47537 #define F_RX_LOC_FAULT V_RX_LOC_FAULT(1U)
47539 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
47542 #define M_IPG 0x7fU
47543 #define V_IPG(x) ((x) << S_IPG)
47544 #define G_IPG(x) (((x) >> S_IPG) & M_IPG)
47546 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
47548 #define S_RXFIFORST 0
47549 #define V_RXFIFORST(x) ((x) << S_RXFIFORST)
47550 #define F_RXFIFORST V_RXFIFORST(1U)
47552 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
47554 #define S_MACCRDRST 0
47555 #define M_MACCRDRST 0xffU
47556 #define V_MACCRDRST(x) ((x) << S_MACCRDRST)
47557 #define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
47559 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
47561 #define S_INITCREDIT 0
47562 #define M_INITCREDIT 0xffU
47563 #define V_INITCREDIT(x) ((x) << S_INITCREDIT)
47564 #define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
47566 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
47569 #define M_STATUS 0xffU
47570 #define V_STATUS(x) ((x) << S_STATUS)
47571 #define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
47573 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
47574 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
47575 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
47576 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
47577 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
47578 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
47579 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
47580 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
47581 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
47582 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
47583 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
47584 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
47585 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
47586 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
47587 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
47588 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
47589 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
47590 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
47591 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
47592 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
47593 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
47594 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
47595 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
47596 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
47597 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
47598 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
47599 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
47600 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
47601 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
47602 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
47603 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
47604 #define A_MAC_PORT_IFOUTERRORS 0xaf8
47605 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
47606 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
47607 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
47608 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
47609 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
47610 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
47611 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
47612 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
47613 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
47614 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
47615 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
47616 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
47617 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
47618 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
47619 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
47620 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
47621 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
47622 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
47623 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
47624 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
47625 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
47626 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
47627 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
47628 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
47629 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
47630 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
47631 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
47632 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
47633 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
47634 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
47635 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
47636 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
47637 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
47638 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
47639 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
47640 #define A_MAC_PORT_IFINERRORS 0xb90
47641 #define A_MAC_PORT_IFINERRORSHI 0xb94
47642 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
47643 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
47644 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
47645 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
47646 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
47647 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
47648 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
47649 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
47650 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
47651 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
47652 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
47653 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
47654 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
47655 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
47656 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
47657 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
47658 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
47659 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
47660 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
47661 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
47662 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
47663 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
47664 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
47665 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
47666 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
47667 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
47668 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
47669 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
47670 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
47671 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
47672 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
47673 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
47674 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
47675 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
47676 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
47677 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
47678 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
47681 #define V_RESET(x) ((x) << S_RESET)
47682 #define F_RESET V_RESET(1U)
47684 #define S_LOOPBACK 14
47685 #define V_LOOPBACK(x) ((x) << S_LOOPBACK)
47686 #define F_LOOPBACK V_LOOPBACK(1U)
47688 #define S_SPPEDSEL1 13
47689 #define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
47690 #define F_SPPEDSEL1 V_SPPEDSEL1(1U)
47693 #define V_AN_EN(x) ((x) << S_AN_EN)
47694 #define F_AN_EN V_AN_EN(1U)
47696 #define S_PWRDWN 11
47697 #define V_PWRDWN(x) ((x) << S_PWRDWN)
47698 #define F_PWRDWN V_PWRDWN(1U)
47700 #define S_ISOLATE 10
47701 #define V_ISOLATE(x) ((x) << S_ISOLATE)
47702 #define F_ISOLATE V_ISOLATE(1U)
47704 #define S_AN_RESTART 9
47705 #define V_AN_RESTART(x) ((x) << S_AN_RESTART)
47706 #define F_AN_RESTART V_AN_RESTART(1U)
47709 #define V_DPLX(x) ((x) << S_DPLX)
47710 #define F_DPLX V_DPLX(1U)
47712 #define S_COLLISIONTEST 7
47713 #define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
47714 #define F_COLLISIONTEST V_COLLISIONTEST(1U)
47716 #define S_SPEEDSEL0 6
47717 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
47718 #define F_SPEEDSEL0 V_SPEEDSEL0(1U)
47720 #define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
47722 #define S_VER_1G10G 8
47723 #define M_VER_1G10G 0xffU
47724 #define V_VER_1G10G(x) ((x) << S_VER_1G10G)
47725 #define G_VER_1G10G(x) (((x) >> S_VER_1G10G) & M_VER_1G10G)
47727 #define S_REV_1G10G 0
47728 #define M_REV_1G10G 0xffU
47729 #define V_REV_1G10G(x) ((x) << S_REV_1G10G)
47730 #define G_REV_1G10G(x) (((x) >> S_REV_1G10G) & M_REV_1G10G)
47732 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
47734 #define S_100BASET4 15
47735 #define V_100BASET4(x) ((x) << S_100BASET4)
47736 #define F_100BASET4 V_100BASET4(1U)
47738 #define S_100BASEXFULLDPLX 14
47739 #define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
47740 #define F_100BASEXFULLDPLX V_100BASEXFULLDPLX(1U)
47742 #define S_100BASEXHALFDPLX 13
47743 #define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
47744 #define F_100BASEXHALFDPLX V_100BASEXHALFDPLX(1U)
47746 #define S_10MBPSFULLDPLX 12
47747 #define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
47748 #define F_10MBPSFULLDPLX V_10MBPSFULLDPLX(1U)
47750 #define S_10MBPSHALFDPLX 11
47751 #define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
47752 #define F_10MBPSHALFDPLX V_10MBPSHALFDPLX(1U)
47754 #define S_100BASET2FULLDPLX 10
47755 #define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
47756 #define F_100BASET2FULLDPLX V_100BASET2FULLDPLX(1U)
47758 #define S_100BASET2HALFDPLX 9
47759 #define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
47760 #define F_100BASET2HALFDPLX V_100BASET2HALFDPLX(1U)
47762 #define S_EXTDSTATUS 8
47763 #define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
47764 #define F_EXTDSTATUS V_EXTDSTATUS(1U)
47766 #define S_SGMII_REM_FAULT 4
47767 #define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
47768 #define F_SGMII_REM_FAULT V_SGMII_REM_FAULT(1U)
47770 #define S_JABBERDETECT 1
47771 #define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
47772 #define F_JABBERDETECT V_JABBERDETECT(1U)
47774 #define S_EXTDCAPABILITY 0
47775 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
47776 #define F_EXTDCAPABILITY V_EXTDCAPABILITY(1U)
47778 #define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
47779 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
47780 #define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
47782 #define S_SHORT_DISCARD 25
47783 #define V_SHORT_DISCARD(x) ((x) << S_SHORT_DISCARD)
47784 #define F_SHORT_DISCARD V_SHORT_DISCARD(1U)
47786 #define S_REG_LOWP_RXEMPTY 24
47787 #define V_REG_LOWP_RXEMPTY(x) ((x) << S_REG_LOWP_RXEMPTY)
47788 #define F_REG_LOWP_RXEMPTY V_REG_LOWP_RXEMPTY(1U)
47790 #define S_TX_LOWP_ENA 23
47791 #define V_TX_LOWP_ENA(x) ((x) << S_TX_LOWP_ENA)
47792 #define F_TX_LOWP_ENA V_TX_LOWP_ENA(1U)
47794 #define S_TX_FLUSH_EN 22
47795 #define V_TX_FLUSH_EN(x) ((x) << S_TX_FLUSH_EN)
47796 #define F_TX_FLUSH_EN V_TX_FLUSH_EN(1U)
47798 #define S_SFD_ANY 21
47799 #define V_SFD_ANY(x) ((x) << S_SFD_ANY)
47800 #define F_SFD_ANY V_SFD_ANY(1U)
47802 #define S_COL_CNT_EXT 18
47803 #define V_COL_CNT_EXT(x) ((x) << S_COL_CNT_EXT)
47804 #define F_COL_CNT_EXT V_COL_CNT_EXT(1U)
47806 #define S_FORCE_SEND_IDLE 16
47807 #define V_FORCE_SEND_IDLE(x) ((x) << S_FORCE_SEND_IDLE)
47808 #define F_FORCE_SEND_IDLE V_FORCE_SEND_IDLE(1U)
47810 #define S_CNTL_FRM_ENA 13
47811 #define V_CNTL_FRM_ENA(x) ((x) << S_CNTL_FRM_ENA)
47812 #define F_CNTL_FRM_ENA V_CNTL_FRM_ENA(1U)
47814 #define S_RX_ENAMAC 1
47815 #define V_RX_ENAMAC(x) ((x) << S_RX_ENAMAC)
47816 #define F_RX_ENAMAC V_RX_ENAMAC(1U)
47818 #define S_TX_ENAMAC 0
47819 #define V_TX_ENAMAC(x) ((x) << S_TX_ENAMAC)
47820 #define F_TX_ENAMAC V_TX_ENAMAC(1U)
47822 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
47823 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
47824 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
47827 #define V_RF2(x) ((x) << S_RF2)
47828 #define F_RF2 V_RF2(1U)
47831 #define V_RF1(x) ((x) << S_RF1)
47832 #define F_RF1 V_RF1(1U)
47835 #define V_PS2(x) ((x) << S_PS2)
47836 #define F_PS2 V_PS2(1U)
47839 #define V_PS1(x) ((x) << S_PS1)
47840 #define F_PS1 V_PS1(1U)
47843 #define V_HD(x) ((x) << S_HD)
47844 #define F_HD V_HD(1U)
47847 #define V_FD(x) ((x) << S_FD)
47848 #define F_FD V_FD(1U)
47850 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
47851 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
47853 #define S_CULINKSTATUS 15
47854 #define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
47855 #define F_CULINKSTATUS V_CULINKSTATUS(1U)
47857 #define S_CUDPLXSTATUS 12
47858 #define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
47859 #define F_CUDPLXSTATUS V_CUDPLXSTATUS(1U)
47861 #define S_CUSPEED 10
47862 #define M_CUSPEED 0x3U
47863 #define V_CUSPEED(x) ((x) << S_CUSPEED)
47864 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
47866 #define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
47868 #define S_SET_LEN 16
47869 #define M_SET_LEN 0xffffU
47870 #define V_SET_LEN(x) ((x) << S_SET_LEN)
47871 #define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN)
47873 #define S_FRM_LEN_SET 0
47874 #define M_FRM_LEN_SET 0xffffU
47875 #define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET)
47876 #define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET)
47878 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
47881 #define V_PGRCVD(x) ((x) << S_PGRCVD)
47882 #define F_PGRCVD V_PGRCVD(1U)
47884 #define S_REALTIMEPGRCVD 0
47885 #define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
47886 #define F_REALTIMEPGRCVD V_REALTIMEPGRCVD(1U)
47888 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
47889 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
47891 #define S_RX1G10G_EMPTY 16
47892 #define M_RX1G10G_EMPTY 0xffffU
47893 #define V_RX1G10G_EMPTY(x) ((x) << S_RX1G10G_EMPTY)
47894 #define G_RX1G10G_EMPTY(x) (((x) >> S_RX1G10G_EMPTY) & M_RX1G10G_EMPTY)
47896 #define S_RX1G10G_AVAIL 0
47897 #define M_RX1G10G_AVAIL 0xffffU
47898 #define V_RX1G10G_AVAIL(x) ((x) << S_RX1G10G_AVAIL)
47899 #define G_RX1G10G_AVAIL(x) (((x) >> S_RX1G10G_AVAIL) & M_RX1G10G_AVAIL)
47901 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
47902 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
47904 #define S_TX1G10G_EMPTY 16
47905 #define M_TX1G10G_EMPTY 0xffffU
47906 #define V_TX1G10G_EMPTY(x) ((x) << S_TX1G10G_EMPTY)
47907 #define G_TX1G10G_EMPTY(x) (((x) >> S_TX1G10G_EMPTY) & M_TX1G10G_EMPTY)
47909 #define S_TX1G10G_AVAIL 0
47910 #define M_TX1G10G_AVAIL 0xffffU
47911 #define V_TX1G10G_AVAIL(x) ((x) << S_TX1G10G_AVAIL)
47912 #define G_TX1G10G_AVAIL(x) (((x) >> S_TX1G10G_AVAIL) & M_TX1G10G_AVAIL)
47914 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
47916 #define S_ALMOSTFULL 16
47917 #define M_ALMOSTFULL 0xffffU
47918 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
47919 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
47921 #define S_ALMOSTEMPTY 0
47922 #define M_ALMOSTEMPTY 0xffffU
47923 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
47924 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
47926 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
47927 #define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
47928 #define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
47930 #define S_CLK_DIVISOR 7
47931 #define M_CLK_DIVISOR 0x1ffU
47932 #define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR)
47933 #define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR)
47935 #define S_ENA_CLAUSE 6
47936 #define V_ENA_CLAUSE(x) ((x) << S_ENA_CLAUSE)
47937 #define F_ENA_CLAUSE V_ENA_CLAUSE(1U)
47939 #define S_PREAMBLE_DISABLE 5
47940 #define V_PREAMBLE_DISABLE(x) ((x) << S_PREAMBLE_DISABLE)
47941 #define F_PREAMBLE_DISABLE V_PREAMBLE_DISABLE(1U)
47943 #define S_HOLD_TIME_SETTING 2
47944 #define M_HOLD_TIME_SETTING 0x7U
47945 #define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING)
47946 #define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING)
47948 #define S_MDIO_READ_ERROR 1
47949 #define V_MDIO_READ_ERROR(x) ((x) << S_MDIO_READ_ERROR)
47950 #define F_MDIO_READ_ERROR V_MDIO_READ_ERROR(1U)
47952 #define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
47954 #define S_READ_MODE 15
47955 #define V_READ_MODE(x) ((x) << S_READ_MODE)
47956 #define F_READ_MODE V_READ_MODE(1U)
47958 #define S_POST_INCR_READ 14
47959 #define V_POST_INCR_READ(x) ((x) << S_POST_INCR_READ)
47960 #define F_POST_INCR_READ V_POST_INCR_READ(1U)
47962 #define S_PORT_PHY_ADDR 5
47963 #define M_PORT_PHY_ADDR 0x1fU
47964 #define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR)
47965 #define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR)
47967 #define S_DEVICE_REG_ADDR 0
47968 #define M_DEVICE_REG_ADDR 0x1fU
47969 #define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR)
47970 #define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR)
47972 #define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
47974 #define S_MDIO_DATA 0
47975 #define M_MDIO_DATA 0xffffU
47976 #define V_MDIO_DATA(x) ((x) << S_MDIO_DATA)
47977 #define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA)
47979 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
47980 #define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
47981 #define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
47983 #define S_RX_LINT_FAULT 7
47984 #define V_RX_LINT_FAULT(x) ((x) << S_RX_LINT_FAULT)
47985 #define F_RX_LINT_FAULT V_RX_LINT_FAULT(1U)
47987 #define S_RX_EMPTY 6
47988 #define V_RX_EMPTY(x) ((x) << S_RX_EMPTY)
47989 #define F_RX_EMPTY V_RX_EMPTY(1U)
47991 #define S_TX_EMPTY 5
47992 #define V_TX_EMPTY(x) ((x) << S_TX_EMPTY)
47993 #define F_TX_EMPTY V_TX_EMPTY(1U)
47995 #define S_RX_LOWP 4
47996 #define V_RX_LOWP(x) ((x) << S_RX_LOWP)
47997 #define F_RX_LOWP V_RX_LOWP(1U)
47999 #define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
48000 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
48002 #define S_COUNT_LO 0
48003 #define M_COUNT_LO 0xffffU
48004 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
48005 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
48007 #define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
48008 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
48010 #define S_COUNT_HI 0
48011 #define M_COUNT_HI 0x1fU
48012 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
48013 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
48015 #define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
48016 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
48018 #define S_SGMII_PCS_ENABLE 5
48019 #define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
48020 #define F_SGMII_PCS_ENABLE V_SGMII_PCS_ENABLE(1U)
48022 #define S_SGMII_HDUPLEX 4
48023 #define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
48024 #define F_SGMII_HDUPLEX V_SGMII_HDUPLEX(1U)
48026 #define S_SGMII_SPEED 2
48027 #define M_SGMII_SPEED 0x3U
48028 #define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
48029 #define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
48031 #define S_USE_SGMII_AN 1
48032 #define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
48033 #define F_USE_SGMII_AN V_USE_SGMII_AN(1U)
48035 #define S_SGMII_ENA 0
48036 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
48037 #define F_SGMII_ENA V_SGMII_ENA(1U)
48039 #define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
48041 #define S_CL1_PAUSE_QUANTA 16
48042 #define M_CL1_PAUSE_QUANTA 0xffffU
48043 #define V_CL1_PAUSE_QUANTA(x) ((x) << S_CL1_PAUSE_QUANTA)
48044 #define G_CL1_PAUSE_QUANTA(x) (((x) >> S_CL1_PAUSE_QUANTA) & M_CL1_PAUSE_QUANTA)
48046 #define S_CL0_PAUSE_QUANTA 0
48047 #define M_CL0_PAUSE_QUANTA 0xffffU
48048 #define V_CL0_PAUSE_QUANTA(x) ((x) << S_CL0_PAUSE_QUANTA)
48049 #define G_CL0_PAUSE_QUANTA(x) (((x) >> S_CL0_PAUSE_QUANTA) & M_CL0_PAUSE_QUANTA)
48051 #define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
48053 #define S_CL3_PAUSE_QUANTA 16
48054 #define M_CL3_PAUSE_QUANTA 0xffffU
48055 #define V_CL3_PAUSE_QUANTA(x) ((x) << S_CL3_PAUSE_QUANTA)
48056 #define G_CL3_PAUSE_QUANTA(x) (((x) >> S_CL3_PAUSE_QUANTA) & M_CL3_PAUSE_QUANTA)
48058 #define S_CL2_PAUSE_QUANTA 0
48059 #define M_CL2_PAUSE_QUANTA 0xffffU
48060 #define V_CL2_PAUSE_QUANTA(x) ((x) << S_CL2_PAUSE_QUANTA)
48061 #define G_CL2_PAUSE_QUANTA(x) (((x) >> S_CL2_PAUSE_QUANTA) & M_CL2_PAUSE_QUANTA)
48063 #define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
48065 #define S_CL5_PAUSE_QUANTA 16
48066 #define M_CL5_PAUSE_QUANTA 0xffffU
48067 #define V_CL5_PAUSE_QUANTA(x) ((x) << S_CL5_PAUSE_QUANTA)
48068 #define G_CL5_PAUSE_QUANTA(x) (((x) >> S_CL5_PAUSE_QUANTA) & M_CL5_PAUSE_QUANTA)
48070 #define S_CL4_PAUSE_QUANTA 0
48071 #define M_CL4_PAUSE_QUANTA 0xffffU
48072 #define V_CL4_PAUSE_QUANTA(x) ((x) << S_CL4_PAUSE_QUANTA)
48073 #define G_CL4_PAUSE_QUANTA(x) (((x) >> S_CL4_PAUSE_QUANTA) & M_CL4_PAUSE_QUANTA)
48075 #define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
48077 #define S_CL7_PAUSE_QUANTA 16
48078 #define M_CL7_PAUSE_QUANTA 0xffffU
48079 #define V_CL7_PAUSE_QUANTA(x) ((x) << S_CL7_PAUSE_QUANTA)
48080 #define G_CL7_PAUSE_QUANTA(x) (((x) >> S_CL7_PAUSE_QUANTA) & M_CL7_PAUSE_QUANTA)
48082 #define S_CL6_PAUSE_QUANTA 0
48083 #define M_CL6_PAUSE_QUANTA 0xffffU
48084 #define V_CL6_PAUSE_QUANTA(x) ((x) << S_CL6_PAUSE_QUANTA)
48085 #define G_CL6_PAUSE_QUANTA(x) (((x) >> S_CL6_PAUSE_QUANTA) & M_CL6_PAUSE_QUANTA)
48087 #define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
48089 #define S_CL1_QUANTA_THRESH 16
48090 #define M_CL1_QUANTA_THRESH 0xffffU
48091 #define V_CL1_QUANTA_THRESH(x) ((x) << S_CL1_QUANTA_THRESH)
48092 #define G_CL1_QUANTA_THRESH(x) (((x) >> S_CL1_QUANTA_THRESH) & M_CL1_QUANTA_THRESH)
48094 #define S_CL0_QUANTA_THRESH 0
48095 #define M_CL0_QUANTA_THRESH 0xffffU
48096 #define V_CL0_QUANTA_THRESH(x) ((x) << S_CL0_QUANTA_THRESH)
48097 #define G_CL0_QUANTA_THRESH(x) (((x) >> S_CL0_QUANTA_THRESH) & M_CL0_QUANTA_THRESH)
48099 #define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
48101 #define S_CL3_QUANTA_THRESH 16
48102 #define M_CL3_QUANTA_THRESH 0xffffU
48103 #define V_CL3_QUANTA_THRESH(x) ((x) << S_CL3_QUANTA_THRESH)
48104 #define G_CL3_QUANTA_THRESH(x) (((x) >> S_CL3_QUANTA_THRESH) & M_CL3_QUANTA_THRESH)
48106 #define S_CL2_QUANTA_THRESH 0
48107 #define M_CL2_QUANTA_THRESH 0xffffU
48108 #define V_CL2_QUANTA_THRESH(x) ((x) << S_CL2_QUANTA_THRESH)
48109 #define G_CL2_QUANTA_THRESH(x) (((x) >> S_CL2_QUANTA_THRESH) & M_CL2_QUANTA_THRESH)
48111 #define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
48113 #define S_CL5_QUANTA_THRESH 16
48114 #define M_CL5_QUANTA_THRESH 0xffffU
48115 #define V_CL5_QUANTA_THRESH(x) ((x) << S_CL5_QUANTA_THRESH)
48116 #define G_CL5_QUANTA_THRESH(x) (((x) >> S_CL5_QUANTA_THRESH) & M_CL5_QUANTA_THRESH)
48118 #define S_CL4_QUANTA_THRESH 0
48119 #define M_CL4_QUANTA_THRESH 0xffffU
48120 #define V_CL4_QUANTA_THRESH(x) ((x) << S_CL4_QUANTA_THRESH)
48121 #define G_CL4_QUANTA_THRESH(x) (((x) >> S_CL4_QUANTA_THRESH) & M_CL4_QUANTA_THRESH)
48123 #define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
48125 #define S_CL7_QUANTA_THRESH 16
48126 #define M_CL7_QUANTA_THRESH 0xffffU
48127 #define V_CL7_QUANTA_THRESH(x) ((x) << S_CL7_QUANTA_THRESH)
48128 #define G_CL7_QUANTA_THRESH(x) (((x) >> S_CL7_QUANTA_THRESH) & M_CL7_QUANTA_THRESH)
48130 #define S_CL6_QUANTA_THRESH 0
48131 #define M_CL6_QUANTA_THRESH 0xffffU
48132 #define V_CL6_QUANTA_THRESH(x) ((x) << S_CL6_QUANTA_THRESH)
48133 #define G_CL6_QUANTA_THRESH(x) (((x) >> S_CL6_QUANTA_THRESH) & M_CL6_QUANTA_THRESH)
48135 #define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
48137 #define S_STATUS_BIT 0
48138 #define M_STATUS_BIT 0xffU
48139 #define V_STATUS_BIT(x) ((x) << S_STATUS_BIT)
48140 #define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT)
48142 #define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
48143 #define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
48146 #define V_CLEAR(x) ((x) << S_CLEAR)
48147 #define F_CLEAR V_CLEAR(1U)
48149 #define S_CLEAR_ON_READ 1
48150 #define V_CLEAR_ON_READ(x) ((x) << S_CLEAR_ON_READ)
48151 #define F_CLEAR_ON_READ V_CLEAR_ON_READ(1U)
48153 #define S_SATURATE 0
48154 #define V_SATURATE(x) ((x) << S_SATURATE)
48155 #define F_SATURATE V_SATURATE(1U)
48157 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
48158 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
48159 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
48160 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
48161 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
48162 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
48163 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
48164 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
48165 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
48166 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
48167 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
48168 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
48169 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
48170 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
48171 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
48172 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
48173 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
48174 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
48175 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
48176 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
48177 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
48178 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
48179 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
48180 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
48181 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
48182 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
48183 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
48184 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
48185 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
48186 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
48187 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
48188 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
48189 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
48190 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
48191 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
48192 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
48193 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
48194 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
48195 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
48196 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
48197 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
48198 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
48199 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
48200 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
48201 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
48202 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
48203 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
48204 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
48205 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
48206 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
48207 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
48208 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
48209 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
48210 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
48211 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
48212 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
48213 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
48214 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
48215 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
48216 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
48217 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
48218 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
48219 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
48220 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
48221 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
48222 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
48223 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
48224 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
48225 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
48226 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
48227 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
48228 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
48229 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
48230 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
48231 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
48232 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
48233 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
48234 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
48235 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
48236 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
48237 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
48238 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
48239 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
48240 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
48241 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
48242 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
48243 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
48244 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
48245 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
48246 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
48247 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
48248 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
48249 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
48250 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
48251 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
48252 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
48253 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
48254 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
48255 #define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
48257 #define S_MII_ENA_10 4
48258 #define V_MII_ENA_10(x) ((x) << S_MII_ENA_10)
48259 #define F_MII_ENA_10 V_MII_ENA_10(1U)
48261 #define S_IF_MODE 0
48262 #define M_IF_MODE 0x3U
48263 #define V_IF_MODE(x) ((x) << S_IF_MODE)
48264 #define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE)
48266 #define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
48268 #define S_IF_STATUS_MODE 0
48269 #define M_IF_STATUS_MODE 0x3U
48270 #define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE)
48271 #define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE)
48273 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
48274 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
48275 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
48276 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
48277 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
48278 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
48279 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
48280 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
48281 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
48282 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
48283 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
48284 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
48285 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
48286 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
48287 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
48288 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
48289 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
48290 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
48291 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
48292 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
48293 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
48294 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
48295 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
48296 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
48297 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
48298 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
48299 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
48300 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
48301 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
48302 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
48303 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
48304 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
48305 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
48308 #define M_ACTIVE 0x3fU
48309 #define V_ACTIVE(x) ((x) << S_ACTIVE)
48310 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
48312 #define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
48314 #define S_SPEED_SEL 13
48315 #define V_SPEED_SEL(x) ((x) << S_SPEED_SEL)
48316 #define F_SPEED_SEL V_SPEED_SEL(1U)
48318 #define S_PWR_DWN 11
48319 #define V_PWR_DWN(x) ((x) << S_PWR_DWN)
48320 #define F_PWR_DWN V_PWR_DWN(1U)
48322 #define S_DUPLEX_MODE 8
48323 #define V_DUPLEX_MODE(x) ((x) << S_DUPLEX_MODE)
48324 #define F_DUPLEX_MODE V_DUPLEX_MODE(1U)
48326 #define S_COLLISION_TEST 7
48327 #define V_COLLISION_TEST(x) ((x) << S_COLLISION_TEST)
48328 #define F_COLLISION_TEST V_COLLISION_TEST(1U)
48330 #define S_T6_SPEED_SEL1 6
48331 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
48332 #define F_T6_SPEED_SEL1 V_T6_SPEED_SEL1(1U)
48334 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
48336 #define S_MODE_CTL 0
48337 #define M_MODE_CTL 0x3U
48338 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
48339 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
48341 #define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
48343 #define S_T6_REM_FAULT 4
48344 #define V_T6_REM_FAULT(x) ((x) << S_T6_REM_FAULT)
48345 #define F_T6_REM_FAULT V_T6_REM_FAULT(1U)
48347 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
48349 #define S_TXCLK_CTL 0
48350 #define M_TXCLK_CTL 0xffffU
48351 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
48352 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
48354 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
48355 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
48356 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
48357 #define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
48358 #define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
48359 #define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
48361 #define S_NEXT_PAGE_ABLE 2
48362 #define V_NEXT_PAGE_ABLE(x) ((x) << S_NEXT_PAGE_ABLE)
48363 #define F_NEXT_PAGE_ABLE V_NEXT_PAGE_ABLE(1U)
48365 #define S_PAGE_RECEIVE 1
48366 #define V_PAGE_RECEIVE(x) ((x) << S_PAGE_RECEIVE)
48367 #define F_PAGE_RECEIVE V_PAGE_RECEIVE(1U)
48369 #define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
48372 #define M_NP_TX 0xffffU
48373 #define V_NP_TX(x) ((x) << S_NP_TX)
48374 #define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX)
48376 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
48378 #define S_COL_CNT 0
48379 #define M_COL_CNT 0xffffU
48380 #define V_COL_CNT(x) ((x) << S_COL_CNT)
48381 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
48383 #define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
48385 #define S_LP_NP_RX 0
48386 #define M_LP_NP_RX 0xffffU
48387 #define V_LP_NP_RX(x) ((x) << S_LP_NP_RX)
48388 #define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX)
48390 #define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
48392 #define S_EXTENDED_STATUS 0
48393 #define M_EXTENDED_STATUS 0xffffU
48394 #define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS)
48395 #define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS)
48397 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
48399 #define S_VL_INTVL 1
48400 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
48401 #define F_VL_INTVL V_VL_INTVL(1U)
48403 #define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
48405 #define S_SCRATCH 0
48406 #define M_SCRATCH 0xffffU
48407 #define V_SCRATCH(x) ((x) << S_SCRATCH)
48408 #define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH)
48410 #define A_MAC_PORT_MTIP_SGMII_REV 0x1244
48412 #define S_SGMII_VER 8
48413 #define M_SGMII_VER 0xffU
48414 #define V_SGMII_VER(x) ((x) << S_SGMII_VER)
48415 #define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER)
48417 #define S_SGMII_REV 0
48418 #define M_SGMII_REV 0xffU
48419 #define V_SGMII_REV(x) ((x) << S_SGMII_REV)
48420 #define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV)
48422 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
48424 #define S_LINK_TIMER_LO 0
48425 #define M_LINK_TIMER_LO 0xffffU
48426 #define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO)
48427 #define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO)
48429 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
48431 #define S_LINK_TIMER_HI 0
48432 #define M_LINK_TIMER_HI 0xffffU
48433 #define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI)
48434 #define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI)
48436 #define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
48438 #define S_SGMII_DUPLEX 4
48439 #define V_SGMII_DUPLEX(x) ((x) << S_SGMII_DUPLEX)
48440 #define F_SGMII_DUPLEX V_SGMII_DUPLEX(1U)
48442 #define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
48444 #define S_T6_DECODE_ERROR 0
48445 #define M_T6_DECODE_ERROR 0xffffU
48446 #define V_T6_DECODE_ERROR(x) ((x) << S_T6_DECODE_ERROR)
48447 #define G_T6_DECODE_ERROR(x) (((x) >> S_T6_DECODE_ERROR) & M_T6_DECODE_ERROR)
48449 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
48451 #define S_LOW_POWER 11
48452 #define V_LOW_POWER(x) ((x) << S_LOW_POWER)
48453 #define F_LOW_POWER V_LOW_POWER(1U)
48455 #define S_T6_SPEED_SEL1 6
48456 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
48457 #define F_T6_SPEED_SEL1 V_T6_SPEED_SEL1(1U)
48459 #define S_SPEED_SEL2 2
48460 #define M_SPEED_SEL2 0xfU
48461 #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
48462 #define G_SPEED_SEL2(x) (((x) >> S_SPEED_SEL2) & M_SPEED_SEL2)
48464 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
48466 #define S_TX_LPI 11
48467 #define V_TX_LPI(x) ((x) << S_TX_LPI)
48468 #define F_TX_LPI V_TX_LPI(1U)
48470 #define S_RX_LPI 10
48471 #define V_RX_LPI(x) ((x) << S_RX_LPI)
48472 #define F_RX_LPI V_RX_LPI(1U)
48474 #define S_TX_LPI_ACTIVE 9
48475 #define V_TX_LPI_ACTIVE(x) ((x) << S_TX_LPI_ACTIVE)
48476 #define F_TX_LPI_ACTIVE V_TX_LPI_ACTIVE(1U)
48478 #define S_RX_LPI_ACTIVE 8
48479 #define V_RX_LPI_ACTIVE(x) ((x) << S_RX_LPI_ACTIVE)
48480 #define F_RX_LPI_ACTIVE V_RX_LPI_ACTIVE(1U)
48483 #define V_FAULT(x) ((x) << S_FAULT)
48484 #define F_FAULT V_FAULT(1U)
48486 #define S_PCS_RX_LINK_STAT 2
48487 #define V_PCS_RX_LINK_STAT(x) ((x) << S_PCS_RX_LINK_STAT)
48488 #define F_PCS_RX_LINK_STAT V_PCS_RX_LINK_STAT(1U)
48490 #define S_LOW_POWER_ABILITY 1
48491 #define V_LOW_POWER_ABILITY(x) ((x) << S_LOW_POWER_ABILITY)
48492 #define F_LOW_POWER_ABILITY V_LOW_POWER_ABILITY(1U)
48494 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
48495 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
48496 #define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
48498 #define S_10G_CAPABLE 0
48499 #define V_10G_CAPABLE(x) ((x) << S_10G_CAPABLE)
48500 #define F_10G_CAPABLE V_10G_CAPABLE(1U)
48502 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
48504 #define S_AUTO_NEGOTIATION_PRESENT 7
48505 #define V_AUTO_NEGOTIATION_PRESENT(x) ((x) << S_AUTO_NEGOTIATION_PRESENT)
48506 #define F_AUTO_NEGOTIATION_PRESENT V_AUTO_NEGOTIATION_PRESENT(1U)
48508 #define S_DTE_XS_PRESENT 5
48509 #define V_DTE_XS_PRESENT(x) ((x) << S_DTE_XS_PRESENT)
48510 #define F_DTE_XS_PRESENT V_DTE_XS_PRESENT(1U)
48512 #define S_PHY_XS_PRESENT 4
48513 #define V_PHY_XS_PRESENT(x) ((x) << S_PHY_XS_PRESENT)
48514 #define F_PHY_XS_PRESENT V_PHY_XS_PRESENT(1U)
48516 #define S_PCS_PRESENT 3
48517 #define V_PCS_PRESENT(x) ((x) << S_PCS_PRESENT)
48518 #define F_PCS_PRESENT V_PCS_PRESENT(1U)
48520 #define S_WIS_PRESENT 2
48521 #define V_WIS_PRESENT(x) ((x) << S_WIS_PRESENT)
48522 #define F_WIS_PRESENT V_WIS_PRESENT(1U)
48524 #define S_PMD_PMA_PRESENT 1
48525 #define V_PMD_PMA_PRESENT(x) ((x) << S_PMD_PMA_PRESENT)
48526 #define F_PMD_PMA_PRESENT V_PMD_PMA_PRESENT(1U)
48528 #define S_CLAUSE_22_REG_PRESENT 0
48529 #define V_CLAUSE_22_REG_PRESENT(x) ((x) << S_CLAUSE_22_REG_PRESENT)
48530 #define F_CLAUSE_22_REG_PRESENT V_CLAUSE_22_REG_PRESENT(1U)
48532 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
48533 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
48535 #define S_PCS_TYPE_SELECTION 0
48536 #define M_PCS_TYPE_SELECTION 0x3U
48537 #define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION)
48538 #define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION)
48540 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
48542 #define S_DEVICE_PRESENT 14
48543 #define M_DEVICE_PRESENT 0x3U
48544 #define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT)
48545 #define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT)
48547 #define S_TRANSMIT_FAULT 11
48548 #define V_TRANSMIT_FAULT(x) ((x) << S_TRANSMIT_FAULT)
48549 #define F_TRANSMIT_FAULT V_TRANSMIT_FAULT(1U)
48551 #define S_RECEIVE_FAULT 10
48552 #define V_RECEIVE_FAULT(x) ((x) << S_RECEIVE_FAULT)
48553 #define F_RECEIVE_FAULT V_RECEIVE_FAULT(1U)
48555 #define S_10GBASE_W_CAPABLE 2
48556 #define V_10GBASE_W_CAPABLE(x) ((x) << S_10GBASE_W_CAPABLE)
48557 #define F_10GBASE_W_CAPABLE V_10GBASE_W_CAPABLE(1U)
48559 #define S_10GBASE_X_CAPABLE 1
48560 #define V_10GBASE_X_CAPABLE(x) ((x) << S_10GBASE_X_CAPABLE)
48561 #define F_10GBASE_X_CAPABLE V_10GBASE_X_CAPABLE(1U)
48563 #define S_10GBASE_R_CAPABLE 0
48564 #define V_10GBASE_R_CAPABLE(x) ((x) << S_10GBASE_R_CAPABLE)
48565 #define F_10GBASE_R_CAPABLE V_10GBASE_R_CAPABLE(1U)
48567 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
48569 #define S_PCS_PACKAGE_IDENTIFIER_LO 0
48570 #define M_PCS_PACKAGE_IDENTIFIER_LO 0xffffU
48571 #define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO)
48572 #define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO)
48574 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
48576 #define S_PCS_PACKAGE_IDENTIFIER_HI 0
48577 #define M_PCS_PACKAGE_IDENTIFIER_HI 0xffffU
48578 #define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI)
48579 #define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI)
48581 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
48583 #define S_10GBASE_R_RX_LINK_STATUS 12
48584 #define V_10GBASE_R_RX_LINK_STATUS(x) ((x) << S_10GBASE_R_RX_LINK_STATUS)
48585 #define F_10GBASE_R_RX_LINK_STATUS V_10GBASE_R_RX_LINK_STATUS(1U)
48587 #define S_PRBS9_PTTRN_TSTNG_ABILITY 3
48588 #define V_PRBS9_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS9_PTTRN_TSTNG_ABILITY)
48589 #define F_PRBS9_PTTRN_TSTNG_ABILITY V_PRBS9_PTTRN_TSTNG_ABILITY(1U)
48591 #define S_PRBS31_PTTRN_TSTNG_ABILITY 2
48592 #define V_PRBS31_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS31_PTTRN_TSTNG_ABILITY)
48593 #define F_PRBS31_PTTRN_TSTNG_ABILITY V_PRBS31_PTTRN_TSTNG_ABILITY(1U)
48595 #define S_10GBASE_R_PCS_HIGH_BER 1
48596 #define V_10GBASE_R_PCS_HIGH_BER(x) ((x) << S_10GBASE_R_PCS_HIGH_BER)
48597 #define F_10GBASE_R_PCS_HIGH_BER V_10GBASE_R_PCS_HIGH_BER(1U)
48599 #define S_10GBASE_R_PCS_BLOCK_LOCK 0
48600 #define V_10GBASE_R_PCS_BLOCK_LOCK(x) ((x) << S_10GBASE_R_PCS_BLOCK_LOCK)
48601 #define F_10GBASE_R_PCS_BLOCK_LOCK V_10GBASE_R_PCS_BLOCK_LOCK(1U)
48603 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
48605 #define S_LATCHED_BLOCK_LOCK 15
48606 #define V_LATCHED_BLOCK_LOCK(x) ((x) << S_LATCHED_BLOCK_LOCK)
48607 #define F_LATCHED_BLOCK_LOCK V_LATCHED_BLOCK_LOCK(1U)
48609 #define S_LATCHED_HIGH_BER 14
48610 #define V_LATCHED_HIGH_BER(x) ((x) << S_LATCHED_HIGH_BER)
48611 #define F_LATCHED_HIGH_BER V_LATCHED_HIGH_BER(1U)
48613 #define S_BERBER_COUNTER 8
48614 #define M_BERBER_COUNTER 0x3fU
48615 #define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER)
48616 #define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER)
48618 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
48620 #define S_TEST_PATTERN_SEED_A0 0
48621 #define M_TEST_PATTERN_SEED_A0 0xffffU
48622 #define V_TEST_PATTERN_SEED_A0(x) ((x) << S_TEST_PATTERN_SEED_A0)
48623 #define G_TEST_PATTERN_SEED_A0(x) (((x) >> S_TEST_PATTERN_SEED_A0) & M_TEST_PATTERN_SEED_A0)
48625 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
48627 #define S_TEST_PATTERN_SEED_A1 0
48628 #define M_TEST_PATTERN_SEED_A1 0xffffU
48629 #define V_TEST_PATTERN_SEED_A1(x) ((x) << S_TEST_PATTERN_SEED_A1)
48630 #define G_TEST_PATTERN_SEED_A1(x) (((x) >> S_TEST_PATTERN_SEED_A1) & M_TEST_PATTERN_SEED_A1)
48632 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
48634 #define S_TEST_PATTERN_SEED_A2 0
48635 #define M_TEST_PATTERN_SEED_A2 0xffffU
48636 #define V_TEST_PATTERN_SEED_A2(x) ((x) << S_TEST_PATTERN_SEED_A2)
48637 #define G_TEST_PATTERN_SEED_A2(x) (((x) >> S_TEST_PATTERN_SEED_A2) & M_TEST_PATTERN_SEED_A2)
48639 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
48641 #define S_TEST_PATTERN_SEED_A3 0
48642 #define M_TEST_PATTERN_SEED_A3 0x3ffU
48643 #define V_TEST_PATTERN_SEED_A3(x) ((x) << S_TEST_PATTERN_SEED_A3)
48644 #define G_TEST_PATTERN_SEED_A3(x) (((x) >> S_TEST_PATTERN_SEED_A3) & M_TEST_PATTERN_SEED_A3)
48646 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
48648 #define S_TEST_PATTERN_SEED_B0 0
48649 #define M_TEST_PATTERN_SEED_B0 0xffffU
48650 #define V_TEST_PATTERN_SEED_B0(x) ((x) << S_TEST_PATTERN_SEED_B0)
48651 #define G_TEST_PATTERN_SEED_B0(x) (((x) >> S_TEST_PATTERN_SEED_B0) & M_TEST_PATTERN_SEED_B0)
48653 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
48655 #define S_TEST_PATTERN_SEED_B1 0
48656 #define M_TEST_PATTERN_SEED_B1 0xffffU
48657 #define V_TEST_PATTERN_SEED_B1(x) ((x) << S_TEST_PATTERN_SEED_B1)
48658 #define G_TEST_PATTERN_SEED_B1(x) (((x) >> S_TEST_PATTERN_SEED_B1) & M_TEST_PATTERN_SEED_B1)
48660 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
48662 #define S_TEST_PATTERN_SEED_B2 0
48663 #define M_TEST_PATTERN_SEED_B2 0xffffU
48664 #define V_TEST_PATTERN_SEED_B2(x) ((x) << S_TEST_PATTERN_SEED_B2)
48665 #define G_TEST_PATTERN_SEED_B2(x) (((x) >> S_TEST_PATTERN_SEED_B2) & M_TEST_PATTERN_SEED_B2)
48667 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
48669 #define S_TEST_PATTERN_SEED_B3 0
48670 #define M_TEST_PATTERN_SEED_B3 0x3ffU
48671 #define V_TEST_PATTERN_SEED_B3(x) ((x) << S_TEST_PATTERN_SEED_B3)
48672 #define G_TEST_PATTERN_SEED_B3(x) (((x) >> S_TEST_PATTERN_SEED_B3) & M_TEST_PATTERN_SEED_B3)
48674 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
48676 #define S_PRBS9_TX_TST_PTTRN_EN 6
48677 #define V_PRBS9_TX_TST_PTTRN_EN(x) ((x) << S_PRBS9_TX_TST_PTTRN_EN)
48678 #define F_PRBS9_TX_TST_PTTRN_EN V_PRBS9_TX_TST_PTTRN_EN(1U)
48680 #define S_PRBS31_RX_TST_PTTRN_EN 5
48681 #define V_PRBS31_RX_TST_PTTRN_EN(x) ((x) << S_PRBS31_RX_TST_PTTRN_EN)
48682 #define F_PRBS31_RX_TST_PTTRN_EN V_PRBS31_RX_TST_PTTRN_EN(1U)
48684 #define S_PRBS31_TX_TST_PTTRN_EN 4
48685 #define V_PRBS31_TX_TST_PTTRN_EN(x) ((x) << S_PRBS31_TX_TST_PTTRN_EN)
48686 #define F_PRBS31_TX_TST_PTTRN_EN V_PRBS31_TX_TST_PTTRN_EN(1U)
48688 #define S_TX_TEST_PATTERN_EN 3
48689 #define V_TX_TEST_PATTERN_EN(x) ((x) << S_TX_TEST_PATTERN_EN)
48690 #define F_TX_TEST_PATTERN_EN V_TX_TEST_PATTERN_EN(1U)
48692 #define S_RX_TEST_PATTERN_EN 2
48693 #define V_RX_TEST_PATTERN_EN(x) ((x) << S_RX_TEST_PATTERN_EN)
48694 #define F_RX_TEST_PATTERN_EN V_RX_TEST_PATTERN_EN(1U)
48696 #define S_TEST_PATTERN_SELECT 1
48697 #define V_TEST_PATTERN_SELECT(x) ((x) << S_TEST_PATTERN_SELECT)
48698 #define F_TEST_PATTERN_SELECT V_TEST_PATTERN_SELECT(1U)
48700 #define S_DATA_PATTERN_SELECT 0
48701 #define V_DATA_PATTERN_SELECT(x) ((x) << S_DATA_PATTERN_SELECT)
48702 #define F_DATA_PATTERN_SELECT V_DATA_PATTERN_SELECT(1U)
48704 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
48706 #define S_TEST_PATTERN_ERR_CNTR 0
48707 #define M_TEST_PATTERN_ERR_CNTR 0xffffU
48708 #define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR)
48709 #define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR)
48711 #define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
48713 #define S_TRANSMIT_FIFO_FAULT 1
48714 #define V_TRANSMIT_FIFO_FAULT(x) ((x) << S_TRANSMIT_FIFO_FAULT)
48715 #define F_TRANSMIT_FIFO_FAULT V_TRANSMIT_FIFO_FAULT(1U)
48717 #define S_RECEIVE_FIFO_FAULT 0
48718 #define V_RECEIVE_FIFO_FAULT(x) ((x) << S_RECEIVE_FIFO_FAULT)
48719 #define F_RECEIVE_FIFO_FAULT V_RECEIVE_FIFO_FAULT(1U)
48721 #define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
48723 #define S_SPEED_SELECTION 13
48724 #define V_SPEED_SELECTION(x) ((x) << S_SPEED_SELECTION)
48725 #define F_SPEED_SELECTION V_SPEED_SELECTION(1U)
48727 #define S_SPEED_SELECTION1 6
48728 #define V_SPEED_SELECTION1(x) ((x) << S_SPEED_SELECTION1)
48729 #define F_SPEED_SELECTION1 V_SPEED_SELECTION1(1U)
48731 #define S_SPEED_SELECTION2 2
48732 #define M_SPEED_SELECTION2 0xfU
48733 #define V_SPEED_SELECTION2(x) ((x) << S_SPEED_SELECTION2)
48734 #define G_SPEED_SELECTION2(x) (((x) >> S_SPEED_SELECTION2) & M_SPEED_SELECTION2)
48736 #define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
48738 #define S_RECEIVE_LINK_STAT 2
48739 #define V_RECEIVE_LINK_STAT(x) ((x) << S_RECEIVE_LINK_STAT)
48740 #define F_RECEIVE_LINK_STAT V_RECEIVE_LINK_STAT(1U)
48742 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
48743 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
48745 #define S_T6_DEVICE_ID1 16
48746 #define M_T6_DEVICE_ID1 0xffffU
48747 #define V_T6_DEVICE_ID1(x) ((x) << S_T6_DEVICE_ID1)
48748 #define G_T6_DEVICE_ID1(x) (((x) >> S_T6_DEVICE_ID1) & M_T6_DEVICE_ID1)
48750 #define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
48752 #define S_100G_CAPABLE 3
48753 #define V_100G_CAPABLE(x) ((x) << S_100G_CAPABLE)
48754 #define F_100G_CAPABLE V_100G_CAPABLE(1U)
48756 #define S_40G_CAPABLE 2
48757 #define V_40G_CAPABLE(x) ((x) << S_40G_CAPABLE)
48758 #define F_40G_CAPABLE V_40G_CAPABLE(1U)
48760 #define S_10PASS_TS_2BASE_TL_CAPABLE 1
48761 #define V_10PASS_TS_2BASE_TL_CAPABLE(x) ((x) << S_10PASS_TS_2BASE_TL_CAPABLE)
48762 #define F_10PASS_TS_2BASE_TL_CAPABLE V_10PASS_TS_2BASE_TL_CAPABLE(1U)
48764 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
48766 #define S_CLAUSE_22_REG 0
48767 #define V_CLAUSE_22_REG(x) ((x) << S_CLAUSE_22_REG)
48768 #define F_CLAUSE_22_REG V_CLAUSE_22_REG(1U)
48770 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
48772 #define S_VENDOR_SPECIFIC_DEVICE 15
48773 #define V_VENDOR_SPECIFIC_DEVICE(x) ((x) << S_VENDOR_SPECIFIC_DEVICE)
48774 #define F_VENDOR_SPECIFIC_DEVICE V_VENDOR_SPECIFIC_DEVICE(1U)
48776 #define S_VENDOR_SPECIFIC_DEVICE1 14
48777 #define V_VENDOR_SPECIFIC_DEVICE1(x) ((x) << S_VENDOR_SPECIFIC_DEVICE1)
48778 #define F_VENDOR_SPECIFIC_DEVICE1 V_VENDOR_SPECIFIC_DEVICE1(1U)
48780 #define S_CLAUSE_22_EXT 13
48781 #define V_CLAUSE_22_EXT(x) ((x) << S_CLAUSE_22_EXT)
48782 #define F_CLAUSE_22_EXT V_CLAUSE_22_EXT(1U)
48784 #define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
48786 #define S_PCS_TYPE_SEL 0
48787 #define M_PCS_TYPE_SEL 0x7U
48788 #define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL)
48789 #define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL)
48791 #define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
48793 #define S_100GBASE_R_CAPABLE 5
48794 #define V_100GBASE_R_CAPABLE(x) ((x) << S_100GBASE_R_CAPABLE)
48795 #define F_100GBASE_R_CAPABLE V_100GBASE_R_CAPABLE(1U)
48797 #define S_40GBASE_R_CAPABLE 4
48798 #define V_40GBASE_R_CAPABLE(x) ((x) << S_40GBASE_R_CAPABLE)
48799 #define F_40GBASE_R_CAPABLE V_40GBASE_R_CAPABLE(1U)
48801 #define S_10GBASE_T_CAPABLE 3
48802 #define V_10GBASE_T_CAPABLE(x) ((x) << S_10GBASE_T_CAPABLE)
48803 #define F_10GBASE_T_CAPABLE V_10GBASE_T_CAPABLE(1U)
48805 #define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
48806 #define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
48807 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
48809 #define S_T6_RX_LINK_STATUS 12
48810 #define V_T6_RX_LINK_STATUS(x) ((x) << S_T6_RX_LINK_STATUS)
48811 #define F_T6_RX_LINK_STATUS V_T6_RX_LINK_STATUS(1U)
48813 #define S_HIGH_BER 1
48814 #define V_HIGH_BER(x) ((x) << S_HIGH_BER)
48815 #define F_HIGH_BER V_HIGH_BER(1U)
48817 #define S_KR4_BLOCK_LOCK 0
48818 #define V_KR4_BLOCK_LOCK(x) ((x) << S_KR4_BLOCK_LOCK)
48819 #define F_KR4_BLOCK_LOCK V_KR4_BLOCK_LOCK(1U)
48821 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
48823 #define S_LATCHED_BL_LK 15
48824 #define V_LATCHED_BL_LK(x) ((x) << S_LATCHED_BL_LK)
48825 #define F_LATCHED_BL_LK V_LATCHED_BL_LK(1U)
48827 #define S_LATCHED_HG_BR 14
48828 #define V_LATCHED_HG_BR(x) ((x) << S_LATCHED_HG_BR)
48829 #define F_LATCHED_HG_BR V_LATCHED_HG_BR(1U)
48831 #define S_BER_CNT 8
48832 #define M_BER_CNT 0x3fU
48833 #define V_BER_CNT(x) ((x) << S_BER_CNT)
48834 #define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT)
48836 #define S_ERR_BL_CNT 0
48837 #define M_ERR_BL_CNT 0xffU
48838 #define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT)
48839 #define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT)
48841 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
48843 #define S_TX_TP_EN 3
48844 #define V_TX_TP_EN(x) ((x) << S_TX_TP_EN)
48845 #define F_TX_TP_EN V_TX_TP_EN(1U)
48847 #define S_RX_TP_EN 2
48848 #define V_RX_TP_EN(x) ((x) << S_RX_TP_EN)
48849 #define F_RX_TP_EN V_RX_TP_EN(1U)
48851 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
48853 #define S_TP_ERR_CNTR 0
48854 #define M_TP_ERR_CNTR 0xffffU
48855 #define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR)
48856 #define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR)
48858 #define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
48860 #define S_BER_HI_ORDER_CNT 0
48861 #define M_BER_HI_ORDER_CNT 0xffffU
48862 #define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT)
48863 #define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT)
48865 #define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
48867 #define S_HI_ORDER_CNT_EN 15
48868 #define V_HI_ORDER_CNT_EN(x) ((x) << S_HI_ORDER_CNT_EN)
48869 #define F_HI_ORDER_CNT_EN V_HI_ORDER_CNT_EN(1U)
48871 #define S_ERR_BLK_CNTR 0
48872 #define M_ERR_BLK_CNTR 0x3fffU
48873 #define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR)
48874 #define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR)
48876 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
48878 #define S_LANE_ALIGN_STATUS 12
48879 #define V_LANE_ALIGN_STATUS(x) ((x) << S_LANE_ALIGN_STATUS)
48880 #define F_LANE_ALIGN_STATUS V_LANE_ALIGN_STATUS(1U)
48882 #define S_LANE_3_BLK_LCK 3
48883 #define V_LANE_3_BLK_LCK(x) ((x) << S_LANE_3_BLK_LCK)
48884 #define F_LANE_3_BLK_LCK V_LANE_3_BLK_LCK(1U)
48886 #define S_LANE_2_BLK_LC32_6431K 2
48887 #define V_LANE_2_BLK_LC32_6431K(x) ((x) << S_LANE_2_BLK_LC32_6431K)
48888 #define F_LANE_2_BLK_LC32_6431K V_LANE_2_BLK_LC32_6431K(1U)
48890 #define S_LANE_1_BLK_LCK 1
48891 #define V_LANE_1_BLK_LCK(x) ((x) << S_LANE_1_BLK_LCK)
48892 #define F_LANE_1_BLK_LCK V_LANE_1_BLK_LCK(1U)
48894 #define S_LANE_0_BLK_LCK 0
48895 #define V_LANE_0_BLK_LCK(x) ((x) << S_LANE_0_BLK_LCK)
48896 #define F_LANE_0_BLK_LCK V_LANE_0_BLK_LCK(1U)
48898 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
48899 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
48901 #define S_LANE_3_ALIGN_MRKR_LCK 3
48902 #define V_LANE_3_ALIGN_MRKR_LCK(x) ((x) << S_LANE_3_ALIGN_MRKR_LCK)
48903 #define F_LANE_3_ALIGN_MRKR_LCK V_LANE_3_ALIGN_MRKR_LCK(1U)
48905 #define S_LANE_2_ALIGN_MRKR_LCK 2
48906 #define V_LANE_2_ALIGN_MRKR_LCK(x) ((x) << S_LANE_2_ALIGN_MRKR_LCK)
48907 #define F_LANE_2_ALIGN_MRKR_LCK V_LANE_2_ALIGN_MRKR_LCK(1U)
48909 #define S_LANE_1_ALIGN_MRKR_LCK 1
48910 #define V_LANE_1_ALIGN_MRKR_LCK(x) ((x) << S_LANE_1_ALIGN_MRKR_LCK)
48911 #define F_LANE_1_ALIGN_MRKR_LCK V_LANE_1_ALIGN_MRKR_LCK(1U)
48913 #define S_LANE_0_ALIGN_MRKR_LCK 0
48914 #define V_LANE_0_ALIGN_MRKR_LCK(x) ((x) << S_LANE_0_ALIGN_MRKR_LCK)
48915 #define F_LANE_0_ALIGN_MRKR_LCK V_LANE_0_ALIGN_MRKR_LCK(1U)
48917 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
48918 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
48920 #define S_CLK_DIV 7
48921 #define M_CLK_DIV 0x1ffU
48922 #define V_CLK_DIV(x) ((x) << S_CLK_DIV)
48923 #define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
48925 #define S_CL45_EN 6
48926 #define V_CL45_EN(x) ((x) << S_CL45_EN)
48927 #define F_CL45_EN V_CL45_EN(1U)
48929 #define S_DISABLE_PREAMBLE 5
48930 #define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
48931 #define F_DISABLE_PREAMBLE V_DISABLE_PREAMBLE(1U)
48933 #define S_MDIO_HOLD_TIME 2
48934 #define M_MDIO_HOLD_TIME 0x7U
48935 #define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
48936 #define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
48938 #define S_MDIO_READ_ERR 1
48939 #define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
48940 #define F_MDIO_READ_ERR V_MDIO_READ_ERR(1U)
48942 #define S_MDIO_BUSY 0
48943 #define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
48944 #define F_MDIO_BUSY V_MDIO_BUSY(1U)
48946 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
48948 #define S_MDIO_CMD_READ 15
48949 #define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
48950 #define F_MDIO_CMD_READ V_MDIO_CMD_READ(1U)
48952 #define S_READ_INCR 14
48953 #define V_READ_INCR(x) ((x) << S_READ_INCR)
48954 #define F_READ_INCR V_READ_INCR(1U)
48956 #define S_PORT_ADDR 5
48957 #define M_PORT_ADDR 0x1fU
48958 #define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
48959 #define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
48961 #define S_DEV_ADDR 0
48962 #define M_DEV_ADDR 0x1fU
48963 #define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
48964 #define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
48966 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
48968 #define S_READBUSY 31
48969 #define V_READBUSY(x) ((x) << S_READBUSY)
48970 #define F_READBUSY V_READBUSY(1U)
48972 #define S_DATA_WORD 0
48973 #define M_DATA_WORD 0xffffU
48974 #define V_DATA_WORD(x) ((x) << S_DATA_WORD)
48975 #define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
48977 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
48979 #define S_MDIO_ADDR 0
48980 #define M_MDIO_ADDR 0xffffU
48981 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
48982 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
48984 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
48986 #define S_BIP_ERR_CNT_LANE_0 0
48987 #define M_BIP_ERR_CNT_LANE_0 0xffffU
48988 #define V_BIP_ERR_CNT_LANE_0(x) ((x) << S_BIP_ERR_CNT_LANE_0)
48989 #define G_BIP_ERR_CNT_LANE_0(x) (((x) >> S_BIP_ERR_CNT_LANE_0) & M_BIP_ERR_CNT_LANE_0)
48991 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
48993 #define S_BIP_ERR_CNT_LANE_1 0
48994 #define M_BIP_ERR_CNT_LANE_1 0xffffU
48995 #define V_BIP_ERR_CNT_LANE_1(x) ((x) << S_BIP_ERR_CNT_LANE_1)
48996 #define G_BIP_ERR_CNT_LANE_1(x) (((x) >> S_BIP_ERR_CNT_LANE_1) & M_BIP_ERR_CNT_LANE_1)
48998 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
49000 #define S_BIP_ERR_CNT_LANE_2 0
49001 #define M_BIP_ERR_CNT_LANE_2 0xffffU
49002 #define V_BIP_ERR_CNT_LANE_2(x) ((x) << S_BIP_ERR_CNT_LANE_2)
49003 #define G_BIP_ERR_CNT_LANE_2(x) (((x) >> S_BIP_ERR_CNT_LANE_2) & M_BIP_ERR_CNT_LANE_2)
49005 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
49007 #define S_BIP_ERR_CNT_LANE_3 0
49008 #define M_BIP_ERR_CNT_LANE_3 0xffffU
49009 #define V_BIP_ERR_CNT_LANE_3(x) ((x) << S_BIP_ERR_CNT_LANE_3)
49010 #define G_BIP_ERR_CNT_LANE_3(x) (((x) >> S_BIP_ERR_CNT_LANE_3) & M_BIP_ERR_CNT_LANE_3)
49012 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
49014 #define S_VLANTAG 0
49015 #define CXGBE_M_VLANTAG 0xffffU
49016 #define V_VLANTAG(x) ((x) << S_VLANTAG)
49017 #define G_VLANTAG(x) (((x) >> S_VLANTAG) & CXGBE_M_VLANTAG)
49019 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
49020 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
49021 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
49022 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
49023 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
49024 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
49025 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
49026 #define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
49028 #define S_KR4_LANE_0_MAPPING 0
49029 #define M_KR4_LANE_0_MAPPING 0x3U
49030 #define V_KR4_LANE_0_MAPPING(x) ((x) << S_KR4_LANE_0_MAPPING)
49031 #define G_KR4_LANE_0_MAPPING(x) (((x) >> S_KR4_LANE_0_MAPPING) & M_KR4_LANE_0_MAPPING)
49033 #define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
49035 #define S_KR4_LANE_1_MAPPING 0
49036 #define M_KR4_LANE_1_MAPPING 0x3U
49037 #define V_KR4_LANE_1_MAPPING(x) ((x) << S_KR4_LANE_1_MAPPING)
49038 #define G_KR4_LANE_1_MAPPING(x) (((x) >> S_KR4_LANE_1_MAPPING) & M_KR4_LANE_1_MAPPING)
49040 #define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
49042 #define S_KR4_LANE_2_MAPPING 0
49043 #define M_KR4_LANE_2_MAPPING 0x3U
49044 #define V_KR4_LANE_2_MAPPING(x) ((x) << S_KR4_LANE_2_MAPPING)
49045 #define G_KR4_LANE_2_MAPPING(x) (((x) >> S_KR4_LANE_2_MAPPING) & M_KR4_LANE_2_MAPPING)
49047 #define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
49049 #define S_KR4_LANE_3_MAPPING 0
49050 #define M_KR4_LANE_3_MAPPING 0x3U
49051 #define V_KR4_LANE_3_MAPPING(x) ((x) << S_KR4_LANE_3_MAPPING)
49052 #define G_KR4_LANE_3_MAPPING(x) (((x) >> S_KR4_LANE_3_MAPPING) & M_KR4_LANE_3_MAPPING)
49054 #define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
49055 #define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
49056 #define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
49058 #define S_SHRT_MRKR_CNFG 0
49059 #define V_SHRT_MRKR_CNFG(x) ((x) << S_SHRT_MRKR_CNFG)
49060 #define F_SHRT_MRKR_CNFG V_SHRT_MRKR_CNFG(1U)
49062 #define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
49063 #define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
49064 #define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
49066 #define S_CR4_RX_LINK_STATUS 2
49067 #define V_CR4_RX_LINK_STATUS(x) ((x) << S_CR4_RX_LINK_STATUS)
49068 #define F_CR4_RX_LINK_STATUS V_CR4_RX_LINK_STATUS(1U)
49070 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
49072 #define S_CR4_DEVICE_ID0 0
49073 #define M_CR4_DEVICE_ID0 0xffffU
49074 #define V_CR4_DEVICE_ID0(x) ((x) << S_CR4_DEVICE_ID0)
49075 #define G_CR4_DEVICE_ID0(x) (((x) >> S_CR4_DEVICE_ID0) & M_CR4_DEVICE_ID0)
49077 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
49079 #define S_CR4_DEVICE_ID1 0
49080 #define M_CR4_DEVICE_ID1 0xffffU
49081 #define V_CR4_DEVICE_ID1(x) ((x) << S_CR4_DEVICE_ID1)
49082 #define G_CR4_DEVICE_ID1(x) (((x) >> S_CR4_DEVICE_ID1) & M_CR4_DEVICE_ID1)
49084 #define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
49086 #define S_CR4_100G_CAPABLE 8
49087 #define V_CR4_100G_CAPABLE(x) ((x) << S_CR4_100G_CAPABLE)
49088 #define F_CR4_100G_CAPABLE V_CR4_100G_CAPABLE(1U)
49090 #define S_CR4_40G_CAPABLE 7
49091 #define V_CR4_40G_CAPABLE(x) ((x) << S_CR4_40G_CAPABLE)
49092 #define F_CR4_40G_CAPABLE V_CR4_40G_CAPABLE(1U)
49094 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
49096 #define S_CLAUSE22REG_PRESENT 0
49097 #define V_CLAUSE22REG_PRESENT(x) ((x) << S_CLAUSE22REG_PRESENT)
49098 #define F_CLAUSE22REG_PRESENT V_CLAUSE22REG_PRESENT(1U)
49100 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
49102 #define S_VSD_2_PRESENT 15
49103 #define V_VSD_2_PRESENT(x) ((x) << S_VSD_2_PRESENT)
49104 #define F_VSD_2_PRESENT V_VSD_2_PRESENT(1U)
49106 #define S_VSD_1_PRESENT 14
49107 #define V_VSD_1_PRESENT(x) ((x) << S_VSD_1_PRESENT)
49108 #define F_VSD_1_PRESENT V_VSD_1_PRESENT(1U)
49110 #define S_CLAUSE22_EXT_PRESENT 13
49111 #define V_CLAUSE22_EXT_PRESENT(x) ((x) << S_CLAUSE22_EXT_PRESENT)
49112 #define F_CLAUSE22_EXT_PRESENT V_CLAUSE22_EXT_PRESENT(1U)
49114 #define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
49116 #define S_CR4_PCS_TYPE_SELECTION 0
49117 #define M_CR4_PCS_TYPE_SELECTION 0x7U
49118 #define V_CR4_PCS_TYPE_SELECTION(x) ((x) << S_CR4_PCS_TYPE_SELECTION)
49119 #define G_CR4_PCS_TYPE_SELECTION(x) (((x) >> S_CR4_PCS_TYPE_SELECTION) & M_CR4_PCS_TYPE_SELECTION)
49121 #define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
49122 #define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
49123 #define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
49124 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
49126 #define S_RX_LINK_STAT 12
49127 #define V_RX_LINK_STAT(x) ((x) << S_RX_LINK_STAT)
49128 #define F_RX_LINK_STAT V_RX_LINK_STAT(1U)
49130 #define S_BR_BLOCK_LOCK 0
49131 #define V_BR_BLOCK_LOCK(x) ((x) << S_BR_BLOCK_LOCK)
49132 #define F_BR_BLOCK_LOCK V_BR_BLOCK_LOCK(1U)
49134 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
49136 #define S_BER_COUNTER 8
49137 #define M_BER_COUNTER 0x3fU
49138 #define V_BER_COUNTER(x) ((x) << S_BER_COUNTER)
49139 #define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER)
49141 #define S_ERRORED_BLOCKS_CNTR 0
49142 #define M_ERRORED_BLOCKS_CNTR 0xffU
49143 #define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR)
49144 #define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR)
49146 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
49148 #define S_SCRAMBLED_ID_TP_EN 7
49149 #define V_SCRAMBLED_ID_TP_EN(x) ((x) << S_SCRAMBLED_ID_TP_EN)
49150 #define F_SCRAMBLED_ID_TP_EN V_SCRAMBLED_ID_TP_EN(1U)
49152 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
49154 #define S_BASE_R_TEST_ERR_CNT 0
49155 #define M_BASE_R_TEST_ERR_CNT 0xffffU
49156 #define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT)
49157 #define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT)
49159 #define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
49161 #define S_BER_HIGH_ORDER_CNT 0
49162 #define M_BER_HIGH_ORDER_CNT 0xffffU
49163 #define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT)
49164 #define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT)
49166 #define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
49168 #define S_HI_ORDER_CNT_PRESENT 15
49169 #define V_HI_ORDER_CNT_PRESENT(x) ((x) << S_HI_ORDER_CNT_PRESENT)
49170 #define F_HI_ORDER_CNT_PRESENT V_HI_ORDER_CNT_PRESENT(1U)
49172 #define S_ERR_BLKS_CNTR 0
49173 #define M_ERR_BLKS_CNTR 0x3fffU
49174 #define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR)
49175 #define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR)
49177 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
49179 #define S_LANE_ALIGN_STAT 12
49180 #define V_LANE_ALIGN_STAT(x) ((x) << S_LANE_ALIGN_STAT)
49181 #define F_LANE_ALIGN_STAT V_LANE_ALIGN_STAT(1U)
49183 #define S_LANE_7_BLCK_LCK 7
49184 #define V_LANE_7_BLCK_LCK(x) ((x) << S_LANE_7_BLCK_LCK)
49185 #define F_LANE_7_BLCK_LCK V_LANE_7_BLCK_LCK(1U)
49187 #define S_LANE_6_BLCK_LCK 6
49188 #define V_LANE_6_BLCK_LCK(x) ((x) << S_LANE_6_BLCK_LCK)
49189 #define F_LANE_6_BLCK_LCK V_LANE_6_BLCK_LCK(1U)
49191 #define S_LANE_5_BLCK_LCK 5
49192 #define V_LANE_5_BLCK_LCK(x) ((x) << S_LANE_5_BLCK_LCK)
49193 #define F_LANE_5_BLCK_LCK V_LANE_5_BLCK_LCK(1U)
49195 #define S_LANE_4_BLCK_LCK 4
49196 #define V_LANE_4_BLCK_LCK(x) ((x) << S_LANE_4_BLCK_LCK)
49197 #define F_LANE_4_BLCK_LCK V_LANE_4_BLCK_LCK(1U)
49199 #define S_LANE_3_BLCK_LCK 3
49200 #define V_LANE_3_BLCK_LCK(x) ((x) << S_LANE_3_BLCK_LCK)
49201 #define F_LANE_3_BLCK_LCK V_LANE_3_BLCK_LCK(1U)
49203 #define S_LANE_2_BLCK_LCK 2
49204 #define V_LANE_2_BLCK_LCK(x) ((x) << S_LANE_2_BLCK_LCK)
49205 #define F_LANE_2_BLCK_LCK V_LANE_2_BLCK_LCK(1U)
49207 #define S_LANE_1_BLCK_LCK 1
49208 #define V_LANE_1_BLCK_LCK(x) ((x) << S_LANE_1_BLCK_LCK)
49209 #define F_LANE_1_BLCK_LCK V_LANE_1_BLCK_LCK(1U)
49211 #define S_LANE_0_BLCK_LCK 0
49212 #define V_LANE_0_BLCK_LCK(x) ((x) << S_LANE_0_BLCK_LCK)
49213 #define F_LANE_0_BLCK_LCK V_LANE_0_BLCK_LCK(1U)
49215 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
49217 #define S_LANE_19_BLCK_LCK 11
49218 #define V_LANE_19_BLCK_LCK(x) ((x) << S_LANE_19_BLCK_LCK)
49219 #define F_LANE_19_BLCK_LCK V_LANE_19_BLCK_LCK(1U)
49221 #define S_LANE_18_BLCK_LCK 10
49222 #define V_LANE_18_BLCK_LCK(x) ((x) << S_LANE_18_BLCK_LCK)
49223 #define F_LANE_18_BLCK_LCK V_LANE_18_BLCK_LCK(1U)
49225 #define S_LANE_17_BLCK_LCK 9
49226 #define V_LANE_17_BLCK_LCK(x) ((x) << S_LANE_17_BLCK_LCK)
49227 #define F_LANE_17_BLCK_LCK V_LANE_17_BLCK_LCK(1U)
49229 #define S_LANE_16_BLCK_LCK 8
49230 #define V_LANE_16_BLCK_LCK(x) ((x) << S_LANE_16_BLCK_LCK)
49231 #define F_LANE_16_BLCK_LCK V_LANE_16_BLCK_LCK(1U)
49233 #define S_LANE_15_BLCK_LCK 7
49234 #define V_LANE_15_BLCK_LCK(x) ((x) << S_LANE_15_BLCK_LCK)
49235 #define F_LANE_15_BLCK_LCK V_LANE_15_BLCK_LCK(1U)
49237 #define S_LANE_14_BLCK_LCK 6
49238 #define V_LANE_14_BLCK_LCK(x) ((x) << S_LANE_14_BLCK_LCK)
49239 #define F_LANE_14_BLCK_LCK V_LANE_14_BLCK_LCK(1U)
49241 #define S_LANE_13_BLCK_LCK 5
49242 #define V_LANE_13_BLCK_LCK(x) ((x) << S_LANE_13_BLCK_LCK)
49243 #define F_LANE_13_BLCK_LCK V_LANE_13_BLCK_LCK(1U)
49245 #define S_LANE_12_BLCK_LCK 4
49246 #define V_LANE_12_BLCK_LCK(x) ((x) << S_LANE_12_BLCK_LCK)
49247 #define F_LANE_12_BLCK_LCK V_LANE_12_BLCK_LCK(1U)
49249 #define S_LANE_11_BLCK_LCK 3
49250 #define V_LANE_11_BLCK_LCK(x) ((x) << S_LANE_11_BLCK_LCK)
49251 #define F_LANE_11_BLCK_LCK V_LANE_11_BLCK_LCK(1U)
49253 #define S_LANE_10_BLCK_LCK 2
49254 #define V_LANE_10_BLCK_LCK(x) ((x) << S_LANE_10_BLCK_LCK)
49255 #define F_LANE_10_BLCK_LCK V_LANE_10_BLCK_LCK(1U)
49257 #define S_LANE_9_BLCK_LCK 1
49258 #define V_LANE_9_BLCK_LCK(x) ((x) << S_LANE_9_BLCK_LCK)
49259 #define F_LANE_9_BLCK_LCK V_LANE_9_BLCK_LCK(1U)
49261 #define S_LANE_8_BLCK_LCK 0
49262 #define V_LANE_8_BLCK_LCK(x) ((x) << S_LANE_8_BLCK_LCK)
49263 #define F_LANE_8_BLCK_LCK V_LANE_8_BLCK_LCK(1U)
49265 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
49267 #define S_LANE7_ALGN_MRKR_LCK 7
49268 #define V_LANE7_ALGN_MRKR_LCK(x) ((x) << S_LANE7_ALGN_MRKR_LCK)
49269 #define F_LANE7_ALGN_MRKR_LCK V_LANE7_ALGN_MRKR_LCK(1U)
49271 #define S_LANE6_ALGN_MRKR_LCK 6
49272 #define V_LANE6_ALGN_MRKR_LCK(x) ((x) << S_LANE6_ALGN_MRKR_LCK)
49273 #define F_LANE6_ALGN_MRKR_LCK V_LANE6_ALGN_MRKR_LCK(1U)
49275 #define S_LANE5_ALGN_MRKR_LCK 5
49276 #define V_LANE5_ALGN_MRKR_LCK(x) ((x) << S_LANE5_ALGN_MRKR_LCK)
49277 #define F_LANE5_ALGN_MRKR_LCK V_LANE5_ALGN_MRKR_LCK(1U)
49279 #define S_LANE4_ALGN_MRKR_LCK 4
49280 #define V_LANE4_ALGN_MRKR_LCK(x) ((x) << S_LANE4_ALGN_MRKR_LCK)
49281 #define F_LANE4_ALGN_MRKR_LCK V_LANE4_ALGN_MRKR_LCK(1U)
49283 #define S_LANE3_ALGN_MRKR_LCK 3
49284 #define V_LANE3_ALGN_MRKR_LCK(x) ((x) << S_LANE3_ALGN_MRKR_LCK)
49285 #define F_LANE3_ALGN_MRKR_LCK V_LANE3_ALGN_MRKR_LCK(1U)
49287 #define S_LANE2_ALGN_MRKR_LCK 2
49288 #define V_LANE2_ALGN_MRKR_LCK(x) ((x) << S_LANE2_ALGN_MRKR_LCK)
49289 #define F_LANE2_ALGN_MRKR_LCK V_LANE2_ALGN_MRKR_LCK(1U)
49291 #define S_LANE1_ALGN_MRKR_LCK 1
49292 #define V_LANE1_ALGN_MRKR_LCK(x) ((x) << S_LANE1_ALGN_MRKR_LCK)
49293 #define F_LANE1_ALGN_MRKR_LCK V_LANE1_ALGN_MRKR_LCK(1U)
49295 #define S_LANE0_ALGN_MRKR_LCK 0
49296 #define V_LANE0_ALGN_MRKR_LCK(x) ((x) << S_LANE0_ALGN_MRKR_LCK)
49297 #define F_LANE0_ALGN_MRKR_LCK V_LANE0_ALGN_MRKR_LCK(1U)
49299 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
49301 #define S_LANE19_ALGN_MRKR_LCK 11
49302 #define V_LANE19_ALGN_MRKR_LCK(x) ((x) << S_LANE19_ALGN_MRKR_LCK)
49303 #define F_LANE19_ALGN_MRKR_LCK V_LANE19_ALGN_MRKR_LCK(1U)
49305 #define S_LANE18_ALGN_MRKR_LCK 10
49306 #define V_LANE18_ALGN_MRKR_LCK(x) ((x) << S_LANE18_ALGN_MRKR_LCK)
49307 #define F_LANE18_ALGN_MRKR_LCK V_LANE18_ALGN_MRKR_LCK(1U)
49309 #define S_LANE17_ALGN_MRKR_LCK 9
49310 #define V_LANE17_ALGN_MRKR_LCK(x) ((x) << S_LANE17_ALGN_MRKR_LCK)
49311 #define F_LANE17_ALGN_MRKR_LCK V_LANE17_ALGN_MRKR_LCK(1U)
49313 #define S_LANE16_ALGN_MRKR_LCK 8
49314 #define V_LANE16_ALGN_MRKR_LCK(x) ((x) << S_LANE16_ALGN_MRKR_LCK)
49315 #define F_LANE16_ALGN_MRKR_LCK V_LANE16_ALGN_MRKR_LCK(1U)
49317 #define S_LANE15_ALGN_MRKR_LCK 7
49318 #define V_LANE15_ALGN_MRKR_LCK(x) ((x) << S_LANE15_ALGN_MRKR_LCK)
49319 #define F_LANE15_ALGN_MRKR_LCK V_LANE15_ALGN_MRKR_LCK(1U)
49321 #define S_LANE14_ALGN_MRKR_LCK 6
49322 #define V_LANE14_ALGN_MRKR_LCK(x) ((x) << S_LANE14_ALGN_MRKR_LCK)
49323 #define F_LANE14_ALGN_MRKR_LCK V_LANE14_ALGN_MRKR_LCK(1U)
49325 #define S_LANE13_ALGN_MRKR_LCK 5
49326 #define V_LANE13_ALGN_MRKR_LCK(x) ((x) << S_LANE13_ALGN_MRKR_LCK)
49327 #define F_LANE13_ALGN_MRKR_LCK V_LANE13_ALGN_MRKR_LCK(1U)
49329 #define S_LANE12_ALGN_MRKR_LCK 4
49330 #define V_LANE12_ALGN_MRKR_LCK(x) ((x) << S_LANE12_ALGN_MRKR_LCK)
49331 #define F_LANE12_ALGN_MRKR_LCK V_LANE12_ALGN_MRKR_LCK(1U)
49333 #define S_LANE11_ALGN_MRKR_LCK 3
49334 #define V_LANE11_ALGN_MRKR_LCK(x) ((x) << S_LANE11_ALGN_MRKR_LCK)
49335 #define F_LANE11_ALGN_MRKR_LCK V_LANE11_ALGN_MRKR_LCK(1U)
49337 #define S_LANE10_ALGN_MRKR_LCK 2
49338 #define V_LANE10_ALGN_MRKR_LCK(x) ((x) << S_LANE10_ALGN_MRKR_LCK)
49339 #define F_LANE10_ALGN_MRKR_LCK V_LANE10_ALGN_MRKR_LCK(1U)
49341 #define S_LANE9_ALGN_MRKR_LCK 1
49342 #define V_LANE9_ALGN_MRKR_LCK(x) ((x) << S_LANE9_ALGN_MRKR_LCK)
49343 #define F_LANE9_ALGN_MRKR_LCK V_LANE9_ALGN_MRKR_LCK(1U)
49345 #define S_LANE8_ALGN_MRKR_LCK 0
49346 #define V_LANE8_ALGN_MRKR_LCK(x) ((x) << S_LANE8_ALGN_MRKR_LCK)
49347 #define F_LANE8_ALGN_MRKR_LCK V_LANE8_ALGN_MRKR_LCK(1U)
49349 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
49351 #define S_PCS_LPBK 14
49352 #define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
49353 #define F_PCS_LPBK V_PCS_LPBK(1U)
49355 #define S_SPEED_SEL1 13
49356 #define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
49357 #define F_SPEED_SEL1 V_SPEED_SEL1(1U)
49359 #define S_LP_MODE 11
49360 #define V_LP_MODE(x) ((x) << S_LP_MODE)
49361 #define F_LP_MODE V_LP_MODE(1U)
49363 #define S_SPEED_SEL0 6
49364 #define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
49365 #define F_SPEED_SEL0 V_SPEED_SEL0(1U)
49367 #define S_PCS_SPEED 2
49368 #define M_PCS_SPEED 0xfU
49369 #define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
49370 #define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
49372 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
49374 #define S_FAULTDET 7
49375 #define V_FAULTDET(x) ((x) << S_FAULTDET)
49376 #define F_FAULTDET V_FAULTDET(1U)
49378 #define S_RX_LINK_STATUS 2
49379 #define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
49380 #define F_RX_LINK_STATUS V_RX_LINK_STATUS(1U)
49382 #define S_LOPWRABL 1
49383 #define V_LOPWRABL(x) ((x) << S_LOPWRABL)
49384 #define F_LOPWRABL V_LOPWRABL(1U)
49386 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
49388 #define S_DEVICE_ID0 0
49389 #define M_DEVICE_ID0 0xffffU
49390 #define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
49391 #define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
49393 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
49395 #define S_DEVICE_ID1 0
49396 #define M_DEVICE_ID1 0xffffU
49397 #define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
49398 #define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
49400 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
49403 #define V_100G(x) ((x) << S_100G)
49404 #define F_100G V_100G(1U)
49407 #define V_40G(x) ((x) << S_40G)
49408 #define F_40G V_40G(1U)
49410 #define S_10BASE_TL 1
49411 #define V_10BASE_TL(x) ((x) << S_10BASE_TL)
49412 #define F_10BASE_TL V_10BASE_TL(1U)
49415 #define V_10G(x) ((x) << S_10G)
49416 #define F_10G V_10G(1U)
49418 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
49420 #define S_TC_PRESENT 6
49421 #define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
49422 #define F_TC_PRESENT V_TC_PRESENT(1U)
49425 #define V_DTEXS(x) ((x) << S_DTEXS)
49426 #define F_DTEXS V_DTEXS(1U)
49429 #define V_PHYXS(x) ((x) << S_PHYXS)
49430 #define F_PHYXS V_PHYXS(1U)
49433 #define V_PCS(x) ((x) << S_PCS)
49434 #define F_PCS V_PCS(1U)
49437 #define V_WIS(x) ((x) << S_WIS)
49438 #define F_WIS V_WIS(1U)
49440 #define S_PMD_PMA 1
49441 #define V_PMD_PMA(x) ((x) << S_PMD_PMA)
49442 #define F_PMD_PMA V_PMD_PMA(1U)
49445 #define V_CL22(x) ((x) << S_CL22)
49446 #define F_CL22 V_CL22(1U)
49448 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
49450 #define S_VENDDEV2 15
49451 #define V_VENDDEV2(x) ((x) << S_VENDDEV2)
49452 #define F_VENDDEV2 V_VENDDEV2(1U)
49454 #define S_VENDDEV1 14
49455 #define V_VENDDEV1(x) ((x) << S_VENDDEV1)
49456 #define F_VENDDEV1 V_VENDDEV1(1U)
49458 #define S_CL22EXT 13
49459 #define V_CL22EXT(x) ((x) << S_CL22EXT)
49460 #define F_CL22EXT V_CL22EXT(1U)
49462 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
49464 #define S_PCSTYPE 0
49465 #define M_PCSTYPE 0x7U
49466 #define V_PCSTYPE(x) ((x) << S_PCSTYPE)
49467 #define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
49469 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
49471 #define S_PCS_STAT2_DEVICE 15
49472 #define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
49473 #define F_PCS_STAT2_DEVICE V_PCS_STAT2_DEVICE(1U)
49475 #define S_TXFAULT 7
49476 #define V_TXFAULT(x) ((x) << S_TXFAULT)
49477 #define F_TXFAULT V_TXFAULT(1U)
49479 #define S_RXFAULT 6
49480 #define V_RXFAULT(x) ((x) << S_RXFAULT)
49481 #define F_RXFAULT V_RXFAULT(1U)
49483 #define S_100BASE_R 5
49484 #define V_100BASE_R(x) ((x) << S_100BASE_R)
49485 #define F_100BASE_R V_100BASE_R(1U)
49487 #define S_40GBASE_R 4
49488 #define V_40GBASE_R(x) ((x) << S_40GBASE_R)
49489 #define F_40GBASE_R V_40GBASE_R(1U)
49491 #define S_10GBASE_T 3
49492 #define V_10GBASE_T(x) ((x) << S_10GBASE_T)
49493 #define F_10GBASE_T V_10GBASE_T(1U)
49495 #define S_10GBASE_W 2
49496 #define V_10GBASE_W(x) ((x) << S_10GBASE_W)
49497 #define F_10GBASE_W V_10GBASE_W(1U)
49499 #define S_10GBASE_X 1
49500 #define V_10GBASE_X(x) ((x) << S_10GBASE_X)
49501 #define F_10GBASE_X V_10GBASE_X(1U)
49503 #define S_10GBASE_R 0
49504 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
49505 #define F_10GBASE_R V_10GBASE_R(1U)
49507 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
49509 #define S_BIP_ERR_CNTLANE_0 0
49510 #define M_BIP_ERR_CNTLANE_0 0xffffU
49511 #define V_BIP_ERR_CNTLANE_0(x) ((x) << S_BIP_ERR_CNTLANE_0)
49512 #define G_BIP_ERR_CNTLANE_0(x) (((x) >> S_BIP_ERR_CNTLANE_0) & M_BIP_ERR_CNTLANE_0)
49514 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
49516 #define S_BIP_ERR_CNTLANE_1 0
49517 #define M_BIP_ERR_CNTLANE_1 0xffffU
49518 #define V_BIP_ERR_CNTLANE_1(x) ((x) << S_BIP_ERR_CNTLANE_1)
49519 #define G_BIP_ERR_CNTLANE_1(x) (((x) >> S_BIP_ERR_CNTLANE_1) & M_BIP_ERR_CNTLANE_1)
49521 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
49523 #define S_BIP_ERR_CNTLANE_2 0
49524 #define M_BIP_ERR_CNTLANE_2 0xffffU
49525 #define V_BIP_ERR_CNTLANE_2(x) ((x) << S_BIP_ERR_CNTLANE_2)
49526 #define G_BIP_ERR_CNTLANE_2(x) (((x) >> S_BIP_ERR_CNTLANE_2) & M_BIP_ERR_CNTLANE_2)
49528 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
49530 #define S_BIP_ERR_CNTLANE_3 0
49531 #define M_BIP_ERR_CNTLANE_3 0xffffU
49532 #define V_BIP_ERR_CNTLANE_3(x) ((x) << S_BIP_ERR_CNTLANE_3)
49533 #define G_BIP_ERR_CNTLANE_3(x) (((x) >> S_BIP_ERR_CNTLANE_3) & M_BIP_ERR_CNTLANE_3)
49535 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
49537 #define S_BIP_ERR_CNTLANE_4 0
49538 #define M_BIP_ERR_CNTLANE_4 0xffffU
49539 #define V_BIP_ERR_CNTLANE_4(x) ((x) << S_BIP_ERR_CNTLANE_4)
49540 #define G_BIP_ERR_CNTLANE_4(x) (((x) >> S_BIP_ERR_CNTLANE_4) & M_BIP_ERR_CNTLANE_4)
49542 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
49544 #define S_BIP_ERR_CNTLANE_5 0
49545 #define M_BIP_ERR_CNTLANE_5 0xffffU
49546 #define V_BIP_ERR_CNTLANE_5(x) ((x) << S_BIP_ERR_CNTLANE_5)
49547 #define G_BIP_ERR_CNTLANE_5(x) (((x) >> S_BIP_ERR_CNTLANE_5) & M_BIP_ERR_CNTLANE_5)
49549 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
49551 #define S_PKG_ID0 0
49552 #define M_PKG_ID0 0xffffU
49553 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
49554 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
49556 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
49558 #define S_BIP_ERR_CNTLANE_6 0
49559 #define M_BIP_ERR_CNTLANE_6 0xffffU
49560 #define V_BIP_ERR_CNTLANE_6(x) ((x) << S_BIP_ERR_CNTLANE_6)
49561 #define G_BIP_ERR_CNTLANE_6(x) (((x) >> S_BIP_ERR_CNTLANE_6) & M_BIP_ERR_CNTLANE_6)
49563 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
49565 #define S_PKG_ID1 0
49566 #define M_PKG_ID1 0xffffU
49567 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
49568 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
49570 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
49572 #define S_BIP_ERR_CNTLANE_7 0
49573 #define M_BIP_ERR_CNTLANE_7 0xffffU
49574 #define V_BIP_ERR_CNTLANE_7(x) ((x) << S_BIP_ERR_CNTLANE_7)
49575 #define G_BIP_ERR_CNTLANE_7(x) (((x) >> S_BIP_ERR_CNTLANE_7) & M_BIP_ERR_CNTLANE_7)
49577 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
49579 #define S_BIP_ERR_CNTLANE_8 0
49580 #define M_BIP_ERR_CNTLANE_8 0xffffU
49581 #define V_BIP_ERR_CNTLANE_8(x) ((x) << S_BIP_ERR_CNTLANE_8)
49582 #define G_BIP_ERR_CNTLANE_8(x) (((x) >> S_BIP_ERR_CNTLANE_8) & M_BIP_ERR_CNTLANE_8)
49584 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
49586 #define S_BIP_ERR_CNTLANE_9 0
49587 #define M_BIP_ERR_CNTLANE_9 0xffffU
49588 #define V_BIP_ERR_CNTLANE_9(x) ((x) << S_BIP_ERR_CNTLANE_9)
49589 #define G_BIP_ERR_CNTLANE_9(x) (((x) >> S_BIP_ERR_CNTLANE_9) & M_BIP_ERR_CNTLANE_9)
49591 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
49593 #define S_BIP_ERR_CNTLANE_10 0
49594 #define M_BIP_ERR_CNTLANE_10 0xffffU
49595 #define V_BIP_ERR_CNTLANE_10(x) ((x) << S_BIP_ERR_CNTLANE_10)
49596 #define G_BIP_ERR_CNTLANE_10(x) (((x) >> S_BIP_ERR_CNTLANE_10) & M_BIP_ERR_CNTLANE_10)
49598 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
49600 #define S_BIP_ERR_CNTLANE_11 0
49601 #define M_BIP_ERR_CNTLANE_11 0xffffU
49602 #define V_BIP_ERR_CNTLANE_11(x) ((x) << S_BIP_ERR_CNTLANE_11)
49603 #define G_BIP_ERR_CNTLANE_11(x) (((x) >> S_BIP_ERR_CNTLANE_11) & M_BIP_ERR_CNTLANE_11)
49605 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
49607 #define S_BIP_ERR_CNTLANE_12 0
49608 #define M_BIP_ERR_CNTLANE_12 0xffffU
49609 #define V_BIP_ERR_CNTLANE_12(x) ((x) << S_BIP_ERR_CNTLANE_12)
49610 #define G_BIP_ERR_CNTLANE_12(x) (((x) >> S_BIP_ERR_CNTLANE_12) & M_BIP_ERR_CNTLANE_12)
49612 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
49614 #define S_BIP_ERR_CNTLANE_13 0
49615 #define M_BIP_ERR_CNTLANE_13 0xffffU
49616 #define V_BIP_ERR_CNTLANE_13(x) ((x) << S_BIP_ERR_CNTLANE_13)
49617 #define G_BIP_ERR_CNTLANE_13(x) (((x) >> S_BIP_ERR_CNTLANE_13) & M_BIP_ERR_CNTLANE_13)
49619 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
49621 #define S_BIP_ERR_CNTLANE_14 0
49622 #define M_BIP_ERR_CNTLANE_14 0xffffU
49623 #define V_BIP_ERR_CNTLANE_14(x) ((x) << S_BIP_ERR_CNTLANE_14)
49624 #define G_BIP_ERR_CNTLANE_14(x) (((x) >> S_BIP_ERR_CNTLANE_14) & M_BIP_ERR_CNTLANE_14)
49626 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
49628 #define S_BIP_ERR_CNTLANE_15 0
49629 #define M_BIP_ERR_CNTLANE_15 0xffffU
49630 #define V_BIP_ERR_CNTLANE_15(x) ((x) << S_BIP_ERR_CNTLANE_15)
49631 #define G_BIP_ERR_CNTLANE_15(x) (((x) >> S_BIP_ERR_CNTLANE_15) & M_BIP_ERR_CNTLANE_15)
49633 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
49635 #define S_BIP_ERR_CNTLANE_16 0
49636 #define M_BIP_ERR_CNTLANE_16 0xffffU
49637 #define V_BIP_ERR_CNTLANE_16(x) ((x) << S_BIP_ERR_CNTLANE_16)
49638 #define G_BIP_ERR_CNTLANE_16(x) (((x) >> S_BIP_ERR_CNTLANE_16) & M_BIP_ERR_CNTLANE_16)
49640 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
49642 #define S_BIP_ERR_CNTLANE_17 0
49643 #define M_BIP_ERR_CNTLANE_17 0xffffU
49644 #define V_BIP_ERR_CNTLANE_17(x) ((x) << S_BIP_ERR_CNTLANE_17)
49645 #define G_BIP_ERR_CNTLANE_17(x) (((x) >> S_BIP_ERR_CNTLANE_17) & M_BIP_ERR_CNTLANE_17)
49647 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
49649 #define S_BIP_ERR_CNTLANE_18 0
49650 #define M_BIP_ERR_CNTLANE_18 0xffffU
49651 #define V_BIP_ERR_CNTLANE_18(x) ((x) << S_BIP_ERR_CNTLANE_18)
49652 #define G_BIP_ERR_CNTLANE_18(x) (((x) >> S_BIP_ERR_CNTLANE_18) & M_BIP_ERR_CNTLANE_18)
49654 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
49656 #define S_BIP_ERR_CNTLANE_19 0
49657 #define M_BIP_ERR_CNTLANE_19 0xffffU
49658 #define V_BIP_ERR_CNTLANE_19(x) ((x) << S_BIP_ERR_CNTLANE_19)
49659 #define G_BIP_ERR_CNTLANE_19(x) (((x) >> S_BIP_ERR_CNTLANE_19) & M_BIP_ERR_CNTLANE_19)
49661 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
49663 #define S_RXLINKSTATUS 12
49664 #define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
49665 #define F_RXLINKSTATUS V_RXLINKSTATUS(1U)
49667 #define S_RESEREVED 4
49668 #define M_RESEREVED 0xffU
49669 #define V_RESEREVED(x) ((x) << S_RESEREVED)
49670 #define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
49672 #define S_10GPRBS9 3
49673 #define V_10GPRBS9(x) ((x) << S_10GPRBS9)
49674 #define F_10GPRBS9 V_10GPRBS9(1U)
49676 #define S_10GPRBS31 2
49677 #define V_10GPRBS31(x) ((x) << S_10GPRBS31)
49678 #define F_10GPRBS31 V_10GPRBS31(1U)
49681 #define V_HIBER(x) ((x) << S_HIBER)
49682 #define F_HIBER V_HIBER(1U)
49684 #define S_BLOCKLOCK 0
49685 #define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
49686 #define F_BLOCKLOCK V_BLOCKLOCK(1U)
49688 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
49690 #define S_BLOCKLOCKLL 15
49691 #define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
49692 #define F_BLOCKLOCKLL V_BLOCKLOCKLL(1U)
49694 #define S_HIBERLH 14
49695 #define V_HIBERLH(x) ((x) << S_HIBERLH)
49696 #define F_HIBERLH V_HIBERLH(1U)
49698 #define S_HIBERCOUNT 8
49699 #define M_HIBERCOUNT 0x3fU
49700 #define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
49701 #define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
49703 #define S_ERRBLKCNT 0
49704 #define M_ERRBLKCNT 0xffU
49705 #define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
49706 #define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
49708 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
49711 #define M_SEEDA 0xffffU
49712 #define V_SEEDA(x) ((x) << S_SEEDA)
49713 #define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
49715 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
49718 #define M_SEEDA1 0xffffU
49719 #define V_SEEDA1(x) ((x) << S_SEEDA1)
49720 #define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
49722 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
49725 #define M_SEEDA2 0xffffU
49726 #define V_SEEDA2(x) ((x) << S_SEEDA2)
49727 #define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
49729 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
49732 #define M_SEEDA3 0x3ffU
49733 #define V_SEEDA3(x) ((x) << S_SEEDA3)
49734 #define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
49736 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
49739 #define M_SEEDB 0xffffU
49740 #define V_SEEDB(x) ((x) << S_SEEDB)
49741 #define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
49743 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
49746 #define M_SEEDB1 0xffffU
49747 #define V_SEEDB1(x) ((x) << S_SEEDB1)
49748 #define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
49750 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
49753 #define M_SEEDB2 0xffffU
49754 #define V_SEEDB2(x) ((x) << S_SEEDB2)
49755 #define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
49757 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
49760 #define M_SEEDB3 0x3ffU
49761 #define V_SEEDB3(x) ((x) << S_SEEDB3)
49762 #define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
49764 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
49766 #define S_TXPRBS9 6
49767 #define V_TXPRBS9(x) ((x) << S_TXPRBS9)
49768 #define F_TXPRBS9 V_TXPRBS9(1U)
49770 #define S_RXPRBS31 5
49771 #define V_RXPRBS31(x) ((x) << S_RXPRBS31)
49772 #define F_RXPRBS31 V_RXPRBS31(1U)
49774 #define S_TXPRBS31 4
49775 #define V_TXPRBS31(x) ((x) << S_TXPRBS31)
49776 #define F_TXPRBS31 V_TXPRBS31(1U)
49778 #define S_TXTESTPATEN 3
49779 #define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
49780 #define F_TXTESTPATEN V_TXTESTPATEN(1U)
49782 #define S_RXTESTPATEN 2
49783 #define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
49784 #define F_RXTESTPATEN V_RXTESTPATEN(1U)
49786 #define S_TESTPATSEL 1
49787 #define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
49788 #define F_TESTPATSEL V_TESTPATSEL(1U)
49790 #define S_DATAPATSEL 0
49791 #define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
49792 #define F_DATAPATSEL V_DATAPATSEL(1U)
49794 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
49796 #define S_TEST_ERR_CNT 0
49797 #define M_TEST_ERR_CNT 0xffffU
49798 #define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
49799 #define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
49801 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
49803 #define S_BER_CNT_HI 0
49804 #define M_BER_CNT_HI 0xffffU
49805 #define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
49806 #define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
49808 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
49810 #define S_HICOUNTPRSNT 15
49811 #define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
49812 #define F_HICOUNTPRSNT V_HICOUNTPRSNT(1U)
49814 #define S_BLOCK_CNT_HI 0
49815 #define M_BLOCK_CNT_HI 0x3fffU
49816 #define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
49817 #define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
49819 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
49821 #define S_ALIGNSTATUS 12
49822 #define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
49823 #define F_ALIGNSTATUS V_ALIGNSTATUS(1U)
49826 #define V_LANE7(x) ((x) << S_LANE7)
49827 #define F_LANE7 V_LANE7(1U)
49830 #define V_LANE6(x) ((x) << S_LANE6)
49831 #define F_LANE6 V_LANE6(1U)
49834 #define V_LANE5(x) ((x) << S_LANE5)
49835 #define F_LANE5 V_LANE5(1U)
49838 #define V_LANE4(x) ((x) << S_LANE4)
49839 #define F_LANE4 V_LANE4(1U)
49842 #define V_LANE3(x) ((x) << S_LANE3)
49843 #define F_LANE3 V_LANE3(1U)
49846 #define V_LANE2(x) ((x) << S_LANE2)
49847 #define F_LANE2 V_LANE2(1U)
49850 #define V_LANE1(x) ((x) << S_LANE1)
49851 #define F_LANE1 V_LANE1(1U)
49854 #define V_LANE0(x) ((x) << S_LANE0)
49855 #define F_LANE0 V_LANE0(1U)
49857 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
49859 #define S_LANE19 11
49860 #define V_LANE19(x) ((x) << S_LANE19)
49861 #define F_LANE19 V_LANE19(1U)
49863 #define S_LANE18 10
49864 #define V_LANE18(x) ((x) << S_LANE18)
49865 #define F_LANE18 V_LANE18(1U)
49868 #define V_LANE17(x) ((x) << S_LANE17)
49869 #define F_LANE17 V_LANE17(1U)
49872 #define V_LANE16(x) ((x) << S_LANE16)
49873 #define F_LANE16 V_LANE16(1U)
49876 #define V_LANE15(x) ((x) << S_LANE15)
49877 #define F_LANE15 V_LANE15(1U)
49880 #define V_LANE14(x) ((x) << S_LANE14)
49881 #define F_LANE14 V_LANE14(1U)
49884 #define V_LANE13(x) ((x) << S_LANE13)
49885 #define F_LANE13 V_LANE13(1U)
49888 #define V_LANE12(x) ((x) << S_LANE12)
49889 #define F_LANE12 V_LANE12(1U)
49892 #define V_LANE11(x) ((x) << S_LANE11)
49893 #define F_LANE11 V_LANE11(1U)
49896 #define V_LANE10(x) ((x) << S_LANE10)
49897 #define F_LANE10 V_LANE10(1U)
49900 #define V_LANE9(x) ((x) << S_LANE9)
49901 #define F_LANE9 V_LANE9(1U)
49904 #define V_LANE8(x) ((x) << S_LANE8)
49905 #define F_LANE8 V_LANE8(1U)
49907 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
49909 #define S_AMLOCK7 7
49910 #define V_AMLOCK7(x) ((x) << S_AMLOCK7)
49911 #define F_AMLOCK7 V_AMLOCK7(1U)
49913 #define S_AMLOCK6 6
49914 #define V_AMLOCK6(x) ((x) << S_AMLOCK6)
49915 #define F_AMLOCK6 V_AMLOCK6(1U)
49917 #define S_AMLOCK5 5
49918 #define V_AMLOCK5(x) ((x) << S_AMLOCK5)
49919 #define F_AMLOCK5 V_AMLOCK5(1U)
49921 #define S_AMLOCK4 4
49922 #define V_AMLOCK4(x) ((x) << S_AMLOCK4)
49923 #define F_AMLOCK4 V_AMLOCK4(1U)
49925 #define S_AMLOCK3 3
49926 #define V_AMLOCK3(x) ((x) << S_AMLOCK3)
49927 #define F_AMLOCK3 V_AMLOCK3(1U)
49929 #define S_AMLOCK2 2
49930 #define V_AMLOCK2(x) ((x) << S_AMLOCK2)
49931 #define F_AMLOCK2 V_AMLOCK2(1U)
49933 #define S_AMLOCK1 1
49934 #define V_AMLOCK1(x) ((x) << S_AMLOCK1)
49935 #define F_AMLOCK1 V_AMLOCK1(1U)
49937 #define S_AMLOCK0 0
49938 #define V_AMLOCK0(x) ((x) << S_AMLOCK0)
49939 #define F_AMLOCK0 V_AMLOCK0(1U)
49941 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
49943 #define S_AMLOCK19 11
49944 #define V_AMLOCK19(x) ((x) << S_AMLOCK19)
49945 #define F_AMLOCK19 V_AMLOCK19(1U)
49947 #define S_AMLOCK18 10
49948 #define V_AMLOCK18(x) ((x) << S_AMLOCK18)
49949 #define F_AMLOCK18 V_AMLOCK18(1U)
49951 #define S_AMLOCK17 9
49952 #define V_AMLOCK17(x) ((x) << S_AMLOCK17)
49953 #define F_AMLOCK17 V_AMLOCK17(1U)
49955 #define S_AMLOCK16 8
49956 #define V_AMLOCK16(x) ((x) << S_AMLOCK16)
49957 #define F_AMLOCK16 V_AMLOCK16(1U)
49959 #define S_AMLOCK15 7
49960 #define V_AMLOCK15(x) ((x) << S_AMLOCK15)
49961 #define F_AMLOCK15 V_AMLOCK15(1U)
49963 #define S_AMLOCK14 6
49964 #define V_AMLOCK14(x) ((x) << S_AMLOCK14)
49965 #define F_AMLOCK14 V_AMLOCK14(1U)
49967 #define S_AMLOCK13 5
49968 #define V_AMLOCK13(x) ((x) << S_AMLOCK13)
49969 #define F_AMLOCK13 V_AMLOCK13(1U)
49971 #define S_AMLOCK12 4
49972 #define V_AMLOCK12(x) ((x) << S_AMLOCK12)
49973 #define F_AMLOCK12 V_AMLOCK12(1U)
49975 #define S_AMLOCK11 3
49976 #define V_AMLOCK11(x) ((x) << S_AMLOCK11)
49977 #define F_AMLOCK11 V_AMLOCK11(1U)
49979 #define S_AMLOCK10 2
49980 #define V_AMLOCK10(x) ((x) << S_AMLOCK10)
49981 #define F_AMLOCK10 V_AMLOCK10(1U)
49983 #define S_AMLOCK9 1
49984 #define V_AMLOCK9(x) ((x) << S_AMLOCK9)
49985 #define F_AMLOCK9 V_AMLOCK9(1U)
49987 #define S_AMLOCK8 0
49988 #define V_AMLOCK8(x) ((x) << S_AMLOCK8)
49989 #define F_AMLOCK8 V_AMLOCK8(1U)
49991 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
49993 #define S_BIPERR_CNT 0
49994 #define M_BIPERR_CNT 0xffffU
49995 #define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
49996 #define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
49998 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
49999 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
50000 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
50001 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
50002 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
50003 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
50004 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
50005 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
50006 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
50007 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
50008 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
50009 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
50010 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
50011 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
50012 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
50013 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
50014 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
50015 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
50016 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
50017 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
50020 #define M_MAP 0x1fU
50021 #define V_MAP(x) ((x) << S_MAP)
50022 #define G_MAP(x) (((x) >> S_MAP) & M_MAP)
50024 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
50025 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
50026 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
50027 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
50028 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
50029 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
50030 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
50031 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
50032 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
50033 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
50034 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
50035 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
50036 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
50037 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
50038 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
50039 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
50040 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
50041 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
50042 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
50043 #define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
50045 #define S_LANE_0_MAPPING 0
50046 #define M_LANE_0_MAPPING 0x3fU
50047 #define V_LANE_0_MAPPING(x) ((x) << S_LANE_0_MAPPING)
50048 #define G_LANE_0_MAPPING(x) (((x) >> S_LANE_0_MAPPING) & M_LANE_0_MAPPING)
50050 #define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
50052 #define S_LANE_1_MAPPING 0
50053 #define M_LANE_1_MAPPING 0x3fU
50054 #define V_LANE_1_MAPPING(x) ((x) << S_LANE_1_MAPPING)
50055 #define G_LANE_1_MAPPING(x) (((x) >> S_LANE_1_MAPPING) & M_LANE_1_MAPPING)
50057 #define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
50059 #define S_LANE_2_MAPPING 0
50060 #define M_LANE_2_MAPPING 0x3fU
50061 #define V_LANE_2_MAPPING(x) ((x) << S_LANE_2_MAPPING)
50062 #define G_LANE_2_MAPPING(x) (((x) >> S_LANE_2_MAPPING) & M_LANE_2_MAPPING)
50064 #define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
50066 #define S_LANE_3_MAPPING 0
50067 #define M_LANE_3_MAPPING 0x3fU
50068 #define V_LANE_3_MAPPING(x) ((x) << S_LANE_3_MAPPING)
50069 #define G_LANE_3_MAPPING(x) (((x) >> S_LANE_3_MAPPING) & M_LANE_3_MAPPING)
50071 #define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
50073 #define S_LANE_4_MAPPING 0
50074 #define M_LANE_4_MAPPING 0x3fU
50075 #define V_LANE_4_MAPPING(x) ((x) << S_LANE_4_MAPPING)
50076 #define G_LANE_4_MAPPING(x) (((x) >> S_LANE_4_MAPPING) & M_LANE_4_MAPPING)
50078 #define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
50080 #define S_LANE_5_MAPPING 0
50081 #define M_LANE_5_MAPPING 0x3fU
50082 #define V_LANE_5_MAPPING(x) ((x) << S_LANE_5_MAPPING)
50083 #define G_LANE_5_MAPPING(x) (((x) >> S_LANE_5_MAPPING) & M_LANE_5_MAPPING)
50085 #define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
50087 #define S_LANE_6_MAPPING 0
50088 #define M_LANE_6_MAPPING 0x3fU
50089 #define V_LANE_6_MAPPING(x) ((x) << S_LANE_6_MAPPING)
50090 #define G_LANE_6_MAPPING(x) (((x) >> S_LANE_6_MAPPING) & M_LANE_6_MAPPING)
50092 #define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
50094 #define S_LANE_7_MAPPING 0
50095 #define M_LANE_7_MAPPING 0x3fU
50096 #define V_LANE_7_MAPPING(x) ((x) << S_LANE_7_MAPPING)
50097 #define G_LANE_7_MAPPING(x) (((x) >> S_LANE_7_MAPPING) & M_LANE_7_MAPPING)
50099 #define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
50101 #define S_LANE_8_MAPPING 0
50102 #define M_LANE_8_MAPPING 0x3fU
50103 #define V_LANE_8_MAPPING(x) ((x) << S_LANE_8_MAPPING)
50104 #define G_LANE_8_MAPPING(x) (((x) >> S_LANE_8_MAPPING) & M_LANE_8_MAPPING)
50106 #define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
50108 #define S_LANE_9_MAPPING 0
50109 #define M_LANE_9_MAPPING 0x3fU
50110 #define V_LANE_9_MAPPING(x) ((x) << S_LANE_9_MAPPING)
50111 #define G_LANE_9_MAPPING(x) (((x) >> S_LANE_9_MAPPING) & M_LANE_9_MAPPING)
50113 #define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
50115 #define S_LANE_10_MAPPING 0
50116 #define M_LANE_10_MAPPING 0x3fU
50117 #define V_LANE_10_MAPPING(x) ((x) << S_LANE_10_MAPPING)
50118 #define G_LANE_10_MAPPING(x) (((x) >> S_LANE_10_MAPPING) & M_LANE_10_MAPPING)
50120 #define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
50122 #define S_LANE_11_MAPPING 0
50123 #define M_LANE_11_MAPPING 0x3fU
50124 #define V_LANE_11_MAPPING(x) ((x) << S_LANE_11_MAPPING)
50125 #define G_LANE_11_MAPPING(x) (((x) >> S_LANE_11_MAPPING) & M_LANE_11_MAPPING)
50127 #define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
50129 #define S_LANE_12_MAPPING 0
50130 #define M_LANE_12_MAPPING 0x3fU
50131 #define V_LANE_12_MAPPING(x) ((x) << S_LANE_12_MAPPING)
50132 #define G_LANE_12_MAPPING(x) (((x) >> S_LANE_12_MAPPING) & M_LANE_12_MAPPING)
50134 #define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
50136 #define S_LANE_13_MAPPING 0
50137 #define M_LANE_13_MAPPING 0x3fU
50138 #define V_LANE_13_MAPPING(x) ((x) << S_LANE_13_MAPPING)
50139 #define G_LANE_13_MAPPING(x) (((x) >> S_LANE_13_MAPPING) & M_LANE_13_MAPPING)
50141 #define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
50143 #define S_LANE_14_MAPPING 0
50144 #define M_LANE_14_MAPPING 0x3fU
50145 #define V_LANE_14_MAPPING(x) ((x) << S_LANE_14_MAPPING)
50146 #define G_LANE_14_MAPPING(x) (((x) >> S_LANE_14_MAPPING) & M_LANE_14_MAPPING)
50148 #define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
50150 #define S_LANE_15_MAPPING 0
50151 #define M_LANE_15_MAPPING 0x3fU
50152 #define V_LANE_15_MAPPING(x) ((x) << S_LANE_15_MAPPING)
50153 #define G_LANE_15_MAPPING(x) (((x) >> S_LANE_15_MAPPING) & M_LANE_15_MAPPING)
50155 #define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
50157 #define S_LANE_16_MAPPING 0
50158 #define M_LANE_16_MAPPING 0x3fU
50159 #define V_LANE_16_MAPPING(x) ((x) << S_LANE_16_MAPPING)
50160 #define G_LANE_16_MAPPING(x) (((x) >> S_LANE_16_MAPPING) & M_LANE_16_MAPPING)
50162 #define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
50164 #define S_LANE_17_MAPPING 0
50165 #define M_LANE_17_MAPPING 0x3fU
50166 #define V_LANE_17_MAPPING(x) ((x) << S_LANE_17_MAPPING)
50167 #define G_LANE_17_MAPPING(x) (((x) >> S_LANE_17_MAPPING) & M_LANE_17_MAPPING)
50169 #define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
50171 #define S_LANE_18_MAPPING 0
50172 #define M_LANE_18_MAPPING 0x3fU
50173 #define V_LANE_18_MAPPING(x) ((x) << S_LANE_18_MAPPING)
50174 #define G_LANE_18_MAPPING(x) (((x) >> S_LANE_18_MAPPING) & M_LANE_18_MAPPING)
50176 #define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
50178 #define S_LANE_19_MAPPING 0
50179 #define M_LANE_19_MAPPING 0x3fU
50180 #define V_LANE_19_MAPPING(x) ((x) << S_LANE_19_MAPPING)
50181 #define G_LANE_19_MAPPING(x) (((x) >> S_LANE_19_MAPPING) & M_LANE_19_MAPPING)
50183 #define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
50184 #define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
50186 #define S_CORE_REVISION 0
50187 #define M_CORE_REVISION 0xffffU
50188 #define V_CORE_REVISION(x) ((x) << S_CORE_REVISION)
50189 #define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION)
50191 #define A_MAC_PORT_BEAN_CTL 0x2200
50193 #define S_AN_RESET 15
50194 #define V_AN_RESET(x) ((x) << S_AN_RESET)
50195 #define F_AN_RESET V_AN_RESET(1U)
50197 #define S_EXT_NXP_CTRL 13
50198 #define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
50199 #define F_EXT_NXP_CTRL V_EXT_NXP_CTRL(1U)
50201 #define S_BEAN_EN 12
50202 #define V_BEAN_EN(x) ((x) << S_BEAN_EN)
50203 #define F_BEAN_EN V_BEAN_EN(1U)
50205 #define S_RESTART_BEAN 9
50206 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
50207 #define F_RESTART_BEAN V_RESTART_BEAN(1U)
50209 #define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
50211 #define S_RS_FEC_BYPASS_ERROR_INDICATION 1
50212 #define V_RS_FEC_BYPASS_ERROR_INDICATION(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION)
50213 #define F_RS_FEC_BYPASS_ERROR_INDICATION V_RS_FEC_BYPASS_ERROR_INDICATION(1U)
50215 #define S_RS_FEC_BYPASS_CORRECTION 0
50216 #define V_RS_FEC_BYPASS_CORRECTION(x) ((x) << S_RS_FEC_BYPASS_CORRECTION)
50217 #define F_RS_FEC_BYPASS_CORRECTION V_RS_FEC_BYPASS_CORRECTION(1U)
50219 #define A_MAC_PORT_BEAN_STATUS 0x2204
50222 #define V_PDF(x) ((x) << S_PDF)
50223 #define F_PDF V_PDF(1U)
50225 #define S_EXT_NXP_STATUS 7
50226 #define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
50227 #define F_EXT_NXP_STATUS V_EXT_NXP_STATUS(1U)
50229 #define S_PAGE_RCVD 6
50230 #define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
50231 #define F_PAGE_RCVD V_PAGE_RCVD(1U)
50233 #define S_BEAN_COMPLETE 5
50234 #define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
50235 #define F_BEAN_COMPLETE V_BEAN_COMPLETE(1U)
50237 #define S_REM_FAULT_STATUS 4
50238 #define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
50239 #define F_REM_FAULT_STATUS V_REM_FAULT_STATUS(1U)
50241 #define S_BEAN_ABILITY 3
50242 #define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
50243 #define F_BEAN_ABILITY V_BEAN_ABILITY(1U)
50245 #define S_LP_BEAN_ABILITY 0
50246 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
50247 #define F_LP_BEAN_ABILITY V_LP_BEAN_ABILITY(1U)
50249 #define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
50251 #define S_RS_FEC_PCS_ALIGN_STATUS 15
50252 #define V_RS_FEC_PCS_ALIGN_STATUS(x) ((x) << S_RS_FEC_PCS_ALIGN_STATUS)
50253 #define F_RS_FEC_PCS_ALIGN_STATUS V_RS_FEC_PCS_ALIGN_STATUS(1U)
50255 #define S_FEC_ALIGN_STATUS 14
50256 #define V_FEC_ALIGN_STATUS(x) ((x) << S_FEC_ALIGN_STATUS)
50257 #define F_FEC_ALIGN_STATUS V_FEC_ALIGN_STATUS(1U)
50259 #define S_RS_FEC_HIGH_SER 2
50260 #define V_RS_FEC_HIGH_SER(x) ((x) << S_RS_FEC_HIGH_SER)
50261 #define F_RS_FEC_HIGH_SER V_RS_FEC_HIGH_SER(1U)
50263 #define S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY 1
50264 #define V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY)
50265 #define F_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(1U)
50267 #define S_RS_FEC_BYPASS_CORRECTION_ABILITY 0
50268 #define V_RS_FEC_BYPASS_CORRECTION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_CORRECTION_ABILITY)
50269 #define F_RS_FEC_BYPASS_CORRECTION_ABILITY V_RS_FEC_BYPASS_CORRECTION_ABILITY(1U)
50271 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
50274 #define V_NXP(x) ((x) << S_NXP)
50275 #define F_NXP V_NXP(1U)
50277 #define S_REM_FAULT 13
50278 #define V_REM_FAULT(x) ((x) << S_REM_FAULT)
50279 #define F_REM_FAULT V_REM_FAULT(1U)
50281 #define S_PAUSE_ABILITY 10
50282 #define M_PAUSE_ABILITY 0x7U
50283 #define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
50284 #define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
50286 #define S_ECHO_NONCE 5
50287 #define M_ECHO_NONCE 0x1fU
50288 #define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
50289 #define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
50291 #define S_SELECTOR 0
50292 #define M_SELECTOR 0x1fU
50293 #define V_SELECTOR(x) ((x) << S_SELECTOR)
50294 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
50296 #define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
50298 #define S_RS_RS_FEC_CCW_LO 0
50299 #define M_RS_RS_FEC_CCW_LO 0xffffU
50300 #define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO)
50301 #define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO)
50303 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
50305 #define S_TECH_ABILITY_1 5
50306 #define M_TECH_ABILITY_1 0x7ffU
50307 #define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
50308 #define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
50310 #define S_TX_NONCE 0
50311 #define M_TX_NONCE 0x1fU
50312 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
50313 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
50315 #define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
50317 #define S_RS_RS_FEC_CCW_HI 0
50318 #define M_RS_RS_FEC_CCW_HI 0xffffU
50319 #define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI)
50320 #define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI)
50322 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
50324 #define S_T5_FEC_ABILITY 14
50325 #define M_T5_FEC_ABILITY 0x3U
50326 #define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
50327 #define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
50329 #define S_TECH_ABILITY_2 0
50330 #define M_TECH_ABILITY_2 0x3fffU
50331 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
50332 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
50334 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
50336 #define S_RS_RS_FEC_NCCW_LO 0
50337 #define M_RS_RS_FEC_NCCW_LO 0xffffU
50338 #define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO)
50339 #define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO)
50341 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
50342 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
50344 #define S_RS_RS_FEC_NCCW_HI 0
50345 #define M_RS_RS_FEC_NCCW_HI 0xffffU
50346 #define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI)
50347 #define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI)
50349 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
50350 #define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
50352 #define S_PMA_MAPPING 0
50353 #define M_PMA_MAPPING 0xffU
50354 #define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING)
50355 #define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING)
50357 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
50358 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
50360 #define S_MS_COUNT 0
50361 #define M_MS_COUNT 0xffffU
50362 #define V_MS_COUNT(x) ((x) << S_MS_COUNT)
50363 #define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
50365 #define A_MAC_PORT_BEAN_XNP_0 0x2224
50368 #define V_XNP(x) ((x) << S_XNP)
50369 #define F_XNP V_XNP(1U)
50371 #define S_ACKNOWLEDGE 14
50372 #define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
50373 #define F_ACKNOWLEDGE V_ACKNOWLEDGE(1U)
50376 #define V_MP(x) ((x) << S_MP)
50377 #define F_MP V_MP(1U)
50380 #define V_ACK2(x) ((x) << S_ACK2)
50381 #define F_ACK2 V_ACK2(1U)
50384 #define M_MU 0x7ffU
50385 #define V_MU(x) ((x) << S_MU)
50386 #define G_MU(x) (((x) >> S_MU) & M_MU)
50388 #define A_MAC_PORT_BEAN_XNP_1 0x2228
50390 #define S_UNFORMATED 0
50391 #define M_UNFORMATED 0xffffU
50392 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
50393 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
50395 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
50397 #define S_RS_FEC_SYMBLERR0_LO 0
50398 #define V_RS_FEC_SYMBLERR0_LO(x) ((x) << S_RS_FEC_SYMBLERR0_LO)
50399 #define F_RS_FEC_SYMBLERR0_LO V_RS_FEC_SYMBLERR0_LO(1U)
50401 #define A_MAC_PORT_BEAN_XNP_2 0x222c
50402 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
50404 #define S_RS_FEC_SYMBLERR0_HI 0
50405 #define V_RS_FEC_SYMBLERR0_HI(x) ((x) << S_RS_FEC_SYMBLERR0_HI)
50406 #define F_RS_FEC_SYMBLERR0_HI V_RS_FEC_SYMBLERR0_HI(1U)
50408 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
50409 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
50411 #define S_RS_FEC_SYMBLERR1_LO 0
50412 #define V_RS_FEC_SYMBLERR1_LO(x) ((x) << S_RS_FEC_SYMBLERR1_LO)
50413 #define F_RS_FEC_SYMBLERR1_LO V_RS_FEC_SYMBLERR1_LO(1U)
50415 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
50416 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
50418 #define S_RS_FEC_SYMBLERR1_HI 0
50419 #define V_RS_FEC_SYMBLERR1_HI(x) ((x) << S_RS_FEC_SYMBLERR1_HI)
50420 #define F_RS_FEC_SYMBLERR1_HI V_RS_FEC_SYMBLERR1_HI(1U)
50422 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
50423 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
50425 #define S_RS_FEC_SYMBLERR2_LO 0
50426 #define V_RS_FEC_SYMBLERR2_LO(x) ((x) << S_RS_FEC_SYMBLERR2_LO)
50427 #define F_RS_FEC_SYMBLERR2_LO V_RS_FEC_SYMBLERR2_LO(1U)
50429 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
50431 #define S_100GCR10 8
50432 #define V_100GCR10(x) ((x) << S_100GCR10)
50433 #define F_100GCR10 V_100GCR10(1U)
50436 #define V_40GCR4(x) ((x) << S_40GCR4)
50437 #define F_40GCR4 V_40GCR4(1U)
50440 #define V_40GKR4(x) ((x) << S_40GKR4)
50441 #define F_40GKR4 V_40GKR4(1U)
50444 #define V_FEC(x) ((x) << S_FEC)
50445 #define F_FEC V_FEC(1U)
50448 #define V_10GKR(x) ((x) << S_10GKR)
50449 #define F_10GKR V_10GKR(1U)
50452 #define V_10GKX4(x) ((x) << S_10GKX4)
50453 #define F_10GKX4 V_10GKX4(1U)
50456 #define V_1GKX(x) ((x) << S_1GKX)
50457 #define F_1GKX V_1GKX(1U)
50459 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
50461 #define S_RS_FEC_SYMBLERR2_HI 0
50462 #define V_RS_FEC_SYMBLERR2_HI(x) ((x) << S_RS_FEC_SYMBLERR2_HI)
50463 #define F_RS_FEC_SYMBLERR2_HI V_RS_FEC_SYMBLERR2_HI(1U)
50465 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
50466 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
50468 #define S_RS_FEC_SYMBLERR3_LO 0
50469 #define V_RS_FEC_SYMBLERR3_LO(x) ((x) << S_RS_FEC_SYMBLERR3_LO)
50470 #define F_RS_FEC_SYMBLERR3_LO V_RS_FEC_SYMBLERR3_LO(1U)
50472 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
50473 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
50475 #define S_RS_FEC_SYMBLERR3_HI 0
50476 #define V_RS_FEC_SYMBLERR3_HI(x) ((x) << S_RS_FEC_SYMBLERR3_HI)
50477 #define F_RS_FEC_SYMBLERR3_HI V_RS_FEC_SYMBLERR3_HI(1U)
50479 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
50480 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
50481 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
50482 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
50483 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
50484 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
50485 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
50486 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
50487 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
50488 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
50489 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
50490 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
50491 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
50492 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
50493 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
50494 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
50495 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
50496 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
50497 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
50498 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
50499 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
50500 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
50501 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
50502 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
50503 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
50504 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
50505 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
50506 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
50507 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
50508 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
50509 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
50510 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
50511 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
50512 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
50513 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
50514 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
50515 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
50516 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
50517 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
50518 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
50519 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
50520 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
50521 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
50522 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
50523 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
50524 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
50525 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
50527 #define S_RS_FEC_ENABLED_STATUS 15
50528 #define V_RS_FEC_ENABLED_STATUS(x) ((x) << S_RS_FEC_ENABLED_STATUS)
50529 #define F_RS_FEC_ENABLED_STATUS V_RS_FEC_ENABLED_STATUS(1U)
50531 #define S_RS_FEC_ENABLE 2
50532 #define V_RS_FEC_ENABLE(x) ((x) << S_RS_FEC_ENABLE)
50533 #define F_RS_FEC_ENABLE V_RS_FEC_ENABLE(1U)
50535 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
50537 #define S_DESKEW_EMPTY 12
50538 #define M_DESKEW_EMPTY 0xfU
50539 #define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY)
50540 #define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY)
50542 #define S_FEC_ALIGN_STATUS_LH 10
50543 #define V_FEC_ALIGN_STATUS_LH(x) ((x) << S_FEC_ALIGN_STATUS_LH)
50544 #define F_FEC_ALIGN_STATUS_LH V_FEC_ALIGN_STATUS_LH(1U)
50546 #define S_TX_DP_OVERFLOW 9
50547 #define V_TX_DP_OVERFLOW(x) ((x) << S_TX_DP_OVERFLOW)
50548 #define F_TX_DP_OVERFLOW V_TX_DP_OVERFLOW(1U)
50550 #define S_RX_DP_OVERFLOW 8
50551 #define V_RX_DP_OVERFLOW(x) ((x) << S_RX_DP_OVERFLOW)
50552 #define F_RX_DP_OVERFLOW V_RX_DP_OVERFLOW(1U)
50554 #define S_TX_DATAPATH_RESTART 7
50555 #define V_TX_DATAPATH_RESTART(x) ((x) << S_TX_DATAPATH_RESTART)
50556 #define F_TX_DATAPATH_RESTART V_TX_DATAPATH_RESTART(1U)
50558 #define S_RX_DATAPATH_RESTART 6
50559 #define V_RX_DATAPATH_RESTART(x) ((x) << S_RX_DATAPATH_RESTART)
50560 #define F_RX_DATAPATH_RESTART V_RX_DATAPATH_RESTART(1U)
50562 #define S_MARKER_CHECK_RESTART 5
50563 #define V_MARKER_CHECK_RESTART(x) ((x) << S_MARKER_CHECK_RESTART)
50564 #define F_MARKER_CHECK_RESTART V_MARKER_CHECK_RESTART(1U)
50566 #define S_FEC_ALIGN_STATUS_LL 4
50567 #define V_FEC_ALIGN_STATUS_LL(x) ((x) << S_FEC_ALIGN_STATUS_LL)
50568 #define F_FEC_ALIGN_STATUS_LL V_FEC_ALIGN_STATUS_LL(1U)
50570 #define S_AMPS_LOCK 0
50571 #define M_AMPS_LOCK 0xfU
50572 #define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK)
50573 #define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK)
50575 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
50576 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
50578 #define S_RS_FEC_VENDOR_REVISION 0
50579 #define M_RS_FEC_VENDOR_REVISION 0xffffU
50580 #define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION)
50581 #define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION)
50583 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
50585 #define S_RS_FEC_VENDOR_TX_TEST_KEY 0
50586 #define M_RS_FEC_VENDOR_TX_TEST_KEY 0xffffU
50587 #define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY)
50588 #define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY)
50590 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
50592 #define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0
50593 #define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0xffffU
50594 #define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
50595 #define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
50597 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
50599 #define S_RS_FEC_VENDOR_TX_TEST_PATTERN 0
50600 #define M_RS_FEC_VENDOR_TX_TEST_PATTERN 0xffffU
50601 #define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN)
50602 #define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN)
50604 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
50606 #define S_RS_FEC_VENDOR_TX_TEST_TRIGGER 0
50607 #define M_RS_FEC_VENDOR_TX_TEST_TRIGGER 0xffffU
50608 #define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER)
50609 #define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER)
50611 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
50613 #define S_ENABLE_TR 1
50614 #define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
50615 #define F_ENABLE_TR V_ENABLE_TR(1U)
50617 #define S_RESTART_TR 0
50618 #define V_RESTART_TR(x) ((x) << S_RESTART_TR)
50619 #define F_RESTART_TR V_RESTART_TR(1U)
50621 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
50623 #define S_FECKRSIGDET 15
50624 #define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
50625 #define F_FECKRSIGDET V_FECKRSIGDET(1U)
50627 #define S_TRAIN_FAIL 3
50628 #define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
50629 #define F_TRAIN_FAIL V_TRAIN_FAIL(1U)
50631 #define S_STARTUP_STATUS 2
50632 #define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
50633 #define F_STARTUP_STATUS V_STARTUP_STATUS(1U)
50635 #define S_RX_STATUS 0
50636 #define V_RX_STATUS(x) ((x) << S_RX_STATUS)
50637 #define F_RX_STATUS V_RX_STATUS(1U)
50639 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
50641 #define S_PRESET 13
50642 #define V_PRESET(x) ((x) << S_PRESET)
50643 #define F_PRESET V_PRESET(1U)
50645 #define S_INITIALIZE 12
50646 #define V_INITIALIZE(x) ((x) << S_INITIALIZE)
50647 #define F_INITIALIZE V_INITIALIZE(1U)
50649 #define S_CP1_UPD 4
50650 #define M_CP1_UPD 0x3U
50651 #define V_CP1_UPD(x) ((x) << S_CP1_UPD)
50652 #define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
50655 #define M_C0_UPD 0x3U
50656 #define V_C0_UPD(x) ((x) << S_C0_UPD)
50657 #define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
50659 #define S_CN1_UPD 0
50660 #define M_CN1_UPD 0x3U
50661 #define V_CN1_UPD(x) ((x) << S_CN1_UPD)
50662 #define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
50664 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
50666 #define S_RX_READY 15
50667 #define V_RX_READY(x) ((x) << S_RX_READY)
50668 #define F_RX_READY V_RX_READY(1U)
50670 #define S_CP1_STAT 4
50671 #define M_CP1_STAT 0x3U
50672 #define V_CP1_STAT(x) ((x) << S_CP1_STAT)
50673 #define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
50675 #define S_C0_STAT 2
50676 #define M_C0_STAT 0x3U
50677 #define V_C0_STAT(x) ((x) << S_C0_STAT)
50678 #define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
50680 #define S_CN1_STAT 0
50681 #define M_CN1_STAT 0x3U
50682 #define V_CN1_STAT(x) ((x) << S_CN1_STAT)
50683 #define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
50685 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
50686 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
50687 #define A_MAC_PORT_FEC_ABILITY 0x2618
50689 #define S_FEC_IND_ABILITY 1
50690 #define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
50691 #define F_FEC_IND_ABILITY V_FEC_IND_ABILITY(1U)
50693 #define S_ABILITY 0
50694 #define V_ABILITY(x) ((x) << S_ABILITY)
50695 #define F_ABILITY V_ABILITY(1U)
50697 #define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
50699 #define S_BASE_R_FEC_ERROR_INDICATION_ABILITY 1
50700 #define V_BASE_R_FEC_ERROR_INDICATION_ABILITY(x) ((x) << S_BASE_R_FEC_ERROR_INDICATION_ABILITY)
50701 #define F_BASE_R_FEC_ERROR_INDICATION_ABILITY V_BASE_R_FEC_ERROR_INDICATION_ABILITY(1U)
50703 #define S_BASE_R_FEC_ABILITY 0
50704 #define V_BASE_R_FEC_ABILITY(x) ((x) << S_BASE_R_FEC_ABILITY)
50705 #define F_BASE_R_FEC_ABILITY V_BASE_R_FEC_ABILITY(1U)
50707 #define A_MAC_PORT_FEC_CONTROL 0x261c
50709 #define S_FEC_EN_ERR_IND 1
50710 #define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
50711 #define F_FEC_EN_ERR_IND V_FEC_EN_ERR_IND(1U)
50714 #define V_FEC_EN(x) ((x) << S_FEC_EN)
50715 #define F_FEC_EN V_FEC_EN(1U)
50717 #define A_MAC_PORT_FEC_STATUS 0x2620
50719 #define S_FEC_LOCKED_100 1
50720 #define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
50721 #define F_FEC_LOCKED_100 V_FEC_LOCKED_100(1U)
50723 #define S_FEC_LOCKED 0
50724 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
50725 #define F_FEC_LOCKED V_FEC_LOCKED(1U)
50727 #define S_FEC_LOCKED0 1
50728 #define M_FEC_LOCKED0 0xfU
50729 #define V_FEC_LOCKED0(x) ((x) << S_FEC_LOCKED0)
50730 #define G_FEC_LOCKED0(x) (((x) >> S_FEC_LOCKED0) & M_FEC_LOCKED0)
50732 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
50734 #define S_FEC_CERR_CNT_0 0
50735 #define M_FEC_CERR_CNT_0 0xffffU
50736 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
50737 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
50739 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
50740 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
50742 #define S_FEC_CERR_CNT_1 0
50743 #define M_FEC_CERR_CNT_1 0xffffU
50744 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
50745 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
50747 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
50748 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
50750 #define S_FEC_NCERR_CNT_0 0
50751 #define M_FEC_NCERR_CNT_0 0xffffU
50752 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
50753 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
50755 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
50757 #define S_FEC0_NCERR_CNT_0 0
50758 #define M_FEC0_NCERR_CNT_0 0xffffU
50759 #define V_FEC0_NCERR_CNT_0(x) ((x) << S_FEC0_NCERR_CNT_0)
50760 #define G_FEC0_NCERR_CNT_0(x) (((x) >> S_FEC0_NCERR_CNT_0) & M_FEC0_NCERR_CNT_0)
50762 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
50764 #define S_FEC_NCERR_CNT_1 0
50765 #define M_FEC_NCERR_CNT_1 0xffffU
50766 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
50767 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
50769 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
50771 #define S_FEC0_NCERR_CNT_1 0
50772 #define M_FEC0_NCERR_CNT_1 0xffffU
50773 #define V_FEC0_NCERR_CNT_1(x) ((x) << S_FEC0_NCERR_CNT_1)
50774 #define G_FEC0_NCERR_CNT_1(x) (((x) >> S_FEC0_NCERR_CNT_1) & M_FEC0_NCERR_CNT_1)
50776 #define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
50777 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
50778 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
50779 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
50780 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
50781 #define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
50782 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
50783 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
50784 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
50785 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
50786 #define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
50787 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
50788 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
50789 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
50790 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
50791 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
50793 #define S_T5_RXREQ_C2 4
50794 #define M_T5_RXREQ_C2 0x3U
50795 #define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
50796 #define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
50798 #define S_T5_RXREQ_C1 2
50799 #define M_T5_RXREQ_C1 0x3U
50800 #define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
50801 #define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
50803 #define S_T5_RXREQ_C0 0
50804 #define M_T5_RXREQ_C0 0x3U
50805 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
50806 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
50808 #define S_T5_RXREQ_C3 6
50809 #define M_T5_RXREQ_C3 0x3U
50810 #define V_T5_RXREQ_C3(x) ((x) << S_T5_RXREQ_C3)
50811 #define G_T5_RXREQ_C3(x) (((x) >> S_T5_RXREQ_C3) & M_T5_RXREQ_C3)
50813 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
50815 #define S_T5_AE0_RXSTAT_RDY 15
50816 #define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
50817 #define F_T5_AE0_RXSTAT_RDY V_T5_AE0_RXSTAT_RDY(1U)
50819 #define S_T5_AE0_RXSTAT_C2 4
50820 #define M_T5_AE0_RXSTAT_C2 0x3U
50821 #define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
50822 #define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
50824 #define S_T5_AE0_RXSTAT_C1 2
50825 #define M_T5_AE0_RXSTAT_C1 0x3U
50826 #define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
50827 #define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
50829 #define S_T5_AE0_RXSTAT_C0 0
50830 #define M_T5_AE0_RXSTAT_C0 0x3U
50831 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
50832 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
50834 #define S_T5_AE0_RXSTAT_LSNA 14
50835 #define V_T5_AE0_RXSTAT_LSNA(x) ((x) << S_T5_AE0_RXSTAT_LSNA)
50836 #define F_T5_AE0_RXSTAT_LSNA V_T5_AE0_RXSTAT_LSNA(1U)
50838 #define S_T5_AE0_RXSTAT_FEC 13
50839 #define V_T5_AE0_RXSTAT_FEC(x) ((x) << S_T5_AE0_RXSTAT_FEC)
50840 #define F_T5_AE0_RXSTAT_FEC V_T5_AE0_RXSTAT_FEC(1U)
50842 #define S_T5_AE0_RXSTAT_TF 12
50843 #define V_T5_AE0_RXSTAT_TF(x) ((x) << S_T5_AE0_RXSTAT_TF)
50844 #define F_T5_AE0_RXSTAT_TF V_T5_AE0_RXSTAT_TF(1U)
50846 #define S_T5_AE0_RXSTAT_C3 6
50847 #define M_T5_AE0_RXSTAT_C3 0x3U
50848 #define V_T5_AE0_RXSTAT_C3(x) ((x) << S_T5_AE0_RXSTAT_C3)
50849 #define G_T5_AE0_RXSTAT_C3(x) (((x) >> S_T5_AE0_RXSTAT_C3) & M_T5_AE0_RXSTAT_C3)
50851 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
50853 #define S_T5_TXREQ_C2 4
50854 #define M_T5_TXREQ_C2 0x3U
50855 #define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
50856 #define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
50858 #define S_T5_TXREQ_C1 2
50859 #define M_T5_TXREQ_C1 0x3U
50860 #define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
50861 #define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
50863 #define S_T5_TXREQ_C0 0
50864 #define M_T5_TXREQ_C0 0x3U
50865 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
50866 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
50868 #define S_TXREQ_FEC 11
50869 #define V_TXREQ_FEC(x) ((x) << S_TXREQ_FEC)
50870 #define F_TXREQ_FEC V_TXREQ_FEC(1U)
50872 #define S_T5_TXREQ_C3 6
50873 #define M_T5_TXREQ_C3 0x3U
50874 #define V_T5_TXREQ_C3(x) ((x) << S_T5_TXREQ_C3)
50875 #define G_T5_TXREQ_C3(x) (((x) >> S_T5_TXREQ_C3) & M_T5_TXREQ_C3)
50877 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
50879 #define S_T5_TXSTAT_C2 4
50880 #define M_T5_TXSTAT_C2 0x3U
50881 #define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
50882 #define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
50884 #define S_T5_TXSTAT_C1 2
50885 #define M_T5_TXSTAT_C1 0x3U
50886 #define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
50887 #define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
50889 #define S_T5_TXSTAT_C0 0
50890 #define M_T5_TXSTAT_C0 0x3U
50891 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
50892 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
50894 #define S_T5_TXSTAT_C3 6
50895 #define M_T5_TXSTAT_C3 0x3U
50896 #define V_T5_TXSTAT_C3(x) ((x) << S_T5_TXSTAT_C3)
50897 #define G_T5_TXSTAT_C3(x) (((x) >> S_T5_TXSTAT_C3) & M_T5_TXSTAT_C3)
50899 #define A_MAC_PORT_AE_REG_MODE 0x2a10
50901 #define S_AET_RSVD 7
50902 #define V_AET_RSVD(x) ((x) << S_AET_RSVD)
50903 #define F_AET_RSVD V_AET_RSVD(1U)
50905 #define S_AET_ENABLE 6
50906 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
50907 #define F_AET_ENABLE V_AET_ENABLE(1U)
50909 #define S_SET_WAIT_TIMER 13
50910 #define M_SET_WAIT_TIMER 0x3U
50911 #define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER)
50912 #define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER)
50914 #define S_C2_C3_STATE_SEL 12
50915 #define V_C2_C3_STATE_SEL(x) ((x) << S_C2_C3_STATE_SEL)
50916 #define F_C2_C3_STATE_SEL V_C2_C3_STATE_SEL(1U)
50918 #define S_FFE4_EN 11
50919 #define V_FFE4_EN(x) ((x) << S_FFE4_EN)
50920 #define F_FFE4_EN V_FFE4_EN(1U)
50922 #define S_FEC_REQUEST 10
50923 #define V_FEC_REQUEST(x) ((x) << S_FEC_REQUEST)
50924 #define F_FEC_REQUEST V_FEC_REQUEST(1U)
50926 #define S_FEC_SUPPORTED 9
50927 #define V_FEC_SUPPORTED(x) ((x) << S_FEC_SUPPORTED)
50928 #define F_FEC_SUPPORTED V_FEC_SUPPORTED(1U)
50930 #define S_TX_FIXED 8
50931 #define V_TX_FIXED(x) ((x) << S_TX_FIXED)
50932 #define F_TX_FIXED V_TX_FIXED(1U)
50934 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
50935 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
50937 #define S_CIN_ENABLE 15
50938 #define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
50939 #define F_CIN_ENABLE V_CIN_ENABLE(1U)
50941 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
50942 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
50943 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
50945 #define S_T5_AE1_RXSTAT_RDY 15
50946 #define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
50947 #define F_T5_AE1_RXSTAT_RDY V_T5_AE1_RXSTAT_RDY(1U)
50949 #define S_T5_AE1_RXSTAT_C2 4
50950 #define M_T5_AE1_RXSTAT_C2 0x3U
50951 #define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
50952 #define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
50954 #define S_T5_AE1_RXSTAT_C1 2
50955 #define M_T5_AE1_RXSTAT_C1 0x3U
50956 #define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
50957 #define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
50959 #define S_T5_AE1_RXSTAT_C0 0
50960 #define M_T5_AE1_RXSTAT_C0 0x3U
50961 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
50962 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
50964 #define S_T5_AE1_RXSTAT_LSNA 14
50965 #define V_T5_AE1_RXSTAT_LSNA(x) ((x) << S_T5_AE1_RXSTAT_LSNA)
50966 #define F_T5_AE1_RXSTAT_LSNA V_T5_AE1_RXSTAT_LSNA(1U)
50968 #define S_T5_AE1_RXSTAT_FEC 13
50969 #define V_T5_AE1_RXSTAT_FEC(x) ((x) << S_T5_AE1_RXSTAT_FEC)
50970 #define F_T5_AE1_RXSTAT_FEC V_T5_AE1_RXSTAT_FEC(1U)
50972 #define S_T5_AE1_RXSTAT_TF 12
50973 #define V_T5_AE1_RXSTAT_TF(x) ((x) << S_T5_AE1_RXSTAT_TF)
50974 #define F_T5_AE1_RXSTAT_TF V_T5_AE1_RXSTAT_TF(1U)
50976 #define S_T5_AE1_RXSTAT_C3 6
50977 #define M_T5_AE1_RXSTAT_C3 0x3U
50978 #define V_T5_AE1_RXSTAT_C3(x) ((x) << S_T5_AE1_RXSTAT_C3)
50979 #define G_T5_AE1_RXSTAT_C3(x) (((x) >> S_T5_AE1_RXSTAT_C3) & M_T5_AE1_RXSTAT_C3)
50981 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
50982 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
50983 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
50984 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
50985 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
50986 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
50987 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
50988 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
50990 #define S_T5_AE2_RXSTAT_RDY 15
50991 #define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
50992 #define F_T5_AE2_RXSTAT_RDY V_T5_AE2_RXSTAT_RDY(1U)
50994 #define S_T5_AE2_RXSTAT_C2 4
50995 #define M_T5_AE2_RXSTAT_C2 0x3U
50996 #define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
50997 #define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
50999 #define S_T5_AE2_RXSTAT_C1 2
51000 #define M_T5_AE2_RXSTAT_C1 0x3U
51001 #define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
51002 #define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
51004 #define S_T5_AE2_RXSTAT_C0 0
51005 #define M_T5_AE2_RXSTAT_C0 0x3U
51006 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
51007 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
51009 #define S_T5_AE2_RXSTAT_LSNA 14
51010 #define V_T5_AE2_RXSTAT_LSNA(x) ((x) << S_T5_AE2_RXSTAT_LSNA)
51011 #define F_T5_AE2_RXSTAT_LSNA V_T5_AE2_RXSTAT_LSNA(1U)
51013 #define S_T5_AE2_RXSTAT_FEC 13
51014 #define V_T5_AE2_RXSTAT_FEC(x) ((x) << S_T5_AE2_RXSTAT_FEC)
51015 #define F_T5_AE2_RXSTAT_FEC V_T5_AE2_RXSTAT_FEC(1U)
51017 #define S_T5_AE2_RXSTAT_TF 12
51018 #define V_T5_AE2_RXSTAT_TF(x) ((x) << S_T5_AE2_RXSTAT_TF)
51019 #define F_T5_AE2_RXSTAT_TF V_T5_AE2_RXSTAT_TF(1U)
51021 #define S_T5_AE2_RXSTAT_C3 6
51022 #define M_T5_AE2_RXSTAT_C3 0x3U
51023 #define V_T5_AE2_RXSTAT_C3(x) ((x) << S_T5_AE2_RXSTAT_C3)
51024 #define G_T5_AE2_RXSTAT_C3(x) (((x) >> S_T5_AE2_RXSTAT_C3) & M_T5_AE2_RXSTAT_C3)
51026 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
51027 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
51028 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
51029 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
51030 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
51031 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
51032 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
51033 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
51035 #define S_T5_AE3_RXSTAT_RDY 15
51036 #define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
51037 #define F_T5_AE3_RXSTAT_RDY V_T5_AE3_RXSTAT_RDY(1U)
51039 #define S_T5_AE3_RXSTAT_C2 4
51040 #define M_T5_AE3_RXSTAT_C2 0x3U
51041 #define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
51042 #define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
51044 #define S_T5_AE3_RXSTAT_C1 2
51045 #define M_T5_AE3_RXSTAT_C1 0x3U
51046 #define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
51047 #define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
51049 #define S_T5_AE3_RXSTAT_C0 0
51050 #define M_T5_AE3_RXSTAT_C0 0x3U
51051 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
51052 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
51054 #define S_T5_AE3_RXSTAT_LSNA 14
51055 #define V_T5_AE3_RXSTAT_LSNA(x) ((x) << S_T5_AE3_RXSTAT_LSNA)
51056 #define F_T5_AE3_RXSTAT_LSNA V_T5_AE3_RXSTAT_LSNA(1U)
51058 #define S_T5_AE3_RXSTAT_FEC 13
51059 #define V_T5_AE3_RXSTAT_FEC(x) ((x) << S_T5_AE3_RXSTAT_FEC)
51060 #define F_T5_AE3_RXSTAT_FEC V_T5_AE3_RXSTAT_FEC(1U)
51062 #define S_T5_AE3_RXSTAT_TF 12
51063 #define V_T5_AE3_RXSTAT_TF(x) ((x) << S_T5_AE3_RXSTAT_TF)
51064 #define F_T5_AE3_RXSTAT_TF V_T5_AE3_RXSTAT_TF(1U)
51066 #define S_T5_AE3_RXSTAT_C3 6
51067 #define M_T5_AE3_RXSTAT_C3 0x3U
51068 #define V_T5_AE3_RXSTAT_C3(x) ((x) << S_T5_AE3_RXSTAT_C3)
51069 #define G_T5_AE3_RXSTAT_C3(x) (((x) >> S_T5_AE3_RXSTAT_C3) & M_T5_AE3_RXSTAT_C3)
51071 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
51072 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
51073 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
51074 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
51075 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
51076 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
51077 #define A_MAC_PORT_AE_TX_DIS 0x2a80
51078 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
51079 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
51080 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
51081 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
51082 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
51083 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
51084 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
51085 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
51086 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
51087 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
51088 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
51089 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
51090 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
51091 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
51092 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
51093 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
51095 #define S_EN_HOLD_FAIL 14
51096 #define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
51097 #define F_EN_HOLD_FAIL V_EN_HOLD_FAIL(1U)
51099 #define S_INIT_METH 12
51100 #define M_INIT_METH 0x3U
51101 #define V_INIT_METH(x) ((x) << S_INIT_METH)
51102 #define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
51104 #define S_CE_DECS 8
51105 #define M_CE_DECS 0xfU
51106 #define V_CE_DECS(x) ((x) << S_CE_DECS)
51107 #define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
51110 #define V_EN_ZFE(x) ((x) << S_EN_ZFE)
51111 #define F_EN_ZFE V_EN_ZFE(1U)
51113 #define S_EN_GAIN_TOG 6
51114 #define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
51115 #define F_EN_GAIN_TOG V_EN_GAIN_TOG(1U)
51117 #define S_EN_AI_C1 5
51118 #define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
51119 #define F_EN_AI_C1 V_EN_AI_C1(1U)
51121 #define S_EN_MAX_ST 4
51122 #define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
51123 #define F_EN_MAX_ST V_EN_MAX_ST(1U)
51125 #define S_EN_H1T_EQ 3
51126 #define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
51127 #define F_EN_H1T_EQ V_EN_H1T_EQ(1U)
51129 #define S_H1TEQ_GOAL 0
51130 #define M_H1TEQ_GOAL 0x7U
51131 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
51132 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
51134 #define S_T6_INIT_METH 12
51135 #define M_T6_INIT_METH 0xfU
51136 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51137 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51139 #define S_INIT_CNT 8
51140 #define M_INIT_CNT 0xfU
51141 #define V_INIT_CNT(x) ((x) << S_INIT_CNT)
51142 #define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT)
51144 #define S_EN_AI_N0 5
51145 #define V_EN_AI_N0(x) ((x) << S_EN_AI_N0)
51146 #define F_EN_AI_N0 V_EN_AI_N0(1U)
51148 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
51150 #define S_GAIN_TH 6
51151 #define M_GAIN_TH 0x1fU
51152 #define V_GAIN_TH(x) ((x) << S_GAIN_TH)
51153 #define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
51155 #define S_EN_SD_TH 5
51156 #define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
51157 #define F_EN_SD_TH V_EN_SD_TH(1U)
51159 #define S_EN_AMIN_TH 4
51160 #define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
51161 #define F_EN_AMIN_TH V_EN_AMIN_TH(1U)
51163 #define S_AMIN_TH 0
51164 #define M_AMIN_TH 0xfU
51165 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
51166 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
51168 #define S_FEC_CNV 15
51169 #define V_FEC_CNV(x) ((x) << S_FEC_CNV)
51170 #define F_FEC_CNV V_FEC_CNV(1U)
51172 #define S_EN_RETRY 14
51173 #define V_EN_RETRY(x) ((x) << S_EN_RETRY)
51174 #define F_EN_RETRY V_EN_RETRY(1U)
51176 #define S_DPC_METH 12
51177 #define M_DPC_METH 0x3U
51178 #define V_DPC_METH(x) ((x) << S_DPC_METH)
51179 #define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH)
51182 #define V_EN_P2(x) ((x) << S_EN_P2)
51183 #define F_EN_P2 V_EN_P2(1U)
51185 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
51187 #define S_ACC_LIM 8
51188 #define M_ACC_LIM 0xfU
51189 #define V_ACC_LIM(x) ((x) << S_ACC_LIM)
51190 #define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
51192 #define S_CNV_LIM 4
51193 #define M_CNV_LIM 0xfU
51194 #define V_CNV_LIM(x) ((x) << S_CNV_LIM)
51195 #define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
51197 #define S_TOG_LIM 0
51198 #define M_TOG_LIM 0xfU
51199 #define V_TOG_LIM(x) ((x) << S_TOG_LIM)
51200 #define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
51202 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
51204 #define S_BOOT_LUT7 12
51205 #define M_BOOT_LUT7 0xfU
51206 #define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
51207 #define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
51209 #define S_BOOT_LUT6 8
51210 #define M_BOOT_LUT6 0xfU
51211 #define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
51212 #define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
51214 #define S_BOOT_LUT45 4
51215 #define M_BOOT_LUT45 0xfU
51216 #define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
51217 #define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
51219 #define S_BOOT_LUT0123 2
51220 #define M_BOOT_LUT0123 0x3U
51221 #define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
51222 #define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
51224 #define S_BOOT_DEC_C0 1
51225 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
51226 #define F_BOOT_DEC_C0 V_BOOT_DEC_C0(1U)
51228 #define S_BOOT_LUT5 8
51229 #define M_BOOT_LUT5 0xfU
51230 #define V_BOOT_LUT5(x) ((x) << S_BOOT_LUT5)
51231 #define G_BOOT_LUT5(x) (((x) >> S_BOOT_LUT5) & M_BOOT_LUT5)
51233 #define A_MAC_PORT_AET_STATUS_0 0x2b10
51235 #define S_AET_STAT 9
51236 #define M_AET_STAT 0xfU
51237 #define V_AET_STAT(x) ((x) << S_AET_STAT)
51238 #define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
51240 #define S_NEU_STATE 5
51241 #define M_NEU_STATE 0xfU
51242 #define V_NEU_STATE(x) ((x) << S_NEU_STATE)
51243 #define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
51245 #define S_CTRL_STATE 0
51246 #define M_CTRL_STATE 0x1fU
51247 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
51248 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
51250 #define S_CTRL_STAT 8
51251 #define M_CTRL_STAT 0x1fU
51252 #define V_CTRL_STAT(x) ((x) << S_CTRL_STAT)
51253 #define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT)
51255 #define S_T6_NEU_STATE 4
51256 #define M_T6_NEU_STATE 0xfU
51257 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51258 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51260 #define S_T6_CTRL_STATE 0
51261 #define M_T6_CTRL_STATE 0xfU
51262 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51263 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51265 #define A_MAC_PORT_AET_STATUS_20 0x2b14
51267 #define S_FRAME_LOCK_CNT 0
51268 #define M_FRAME_LOCK_CNT 0x7U
51269 #define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT)
51270 #define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT)
51272 #define A_MAC_PORT_AET_LIMITS0 0x2b18
51274 #define S_DPC_TIME_LIM 0
51275 #define M_DPC_TIME_LIM 0x3U
51276 #define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM)
51277 #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
51279 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
51281 #define S_T6_INIT_METH 12
51282 #define M_T6_INIT_METH 0xfU
51283 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51284 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51286 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
51287 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
51288 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
51289 #define A_MAC_PORT_AET_STATUS_1 0x2b30
51291 #define S_T6_NEU_STATE 4
51292 #define M_T6_NEU_STATE 0xfU
51293 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51294 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51296 #define S_T6_CTRL_STATE 0
51297 #define M_T6_CTRL_STATE 0xfU
51298 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51299 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51301 #define A_MAC_PORT_AET_STATUS_21 0x2b34
51302 #define A_MAC_PORT_AET_LIMITS1 0x2b38
51303 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
51305 #define S_T6_INIT_METH 12
51306 #define M_T6_INIT_METH 0xfU
51307 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51308 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51310 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
51311 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
51312 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
51313 #define A_MAC_PORT_AET_STATUS_2 0x2b50
51315 #define S_T6_NEU_STATE 4
51316 #define M_T6_NEU_STATE 0xfU
51317 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51318 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51320 #define S_T6_CTRL_STATE 0
51321 #define M_T6_CTRL_STATE 0xfU
51322 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51323 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51325 #define A_MAC_PORT_AET_STATUS_22 0x2b54
51326 #define A_MAC_PORT_AET_LIMITS2 0x2b58
51327 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
51329 #define S_T6_INIT_METH 12
51330 #define M_T6_INIT_METH 0xfU
51331 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51332 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51334 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
51335 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
51336 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
51337 #define A_MAC_PORT_AET_STATUS_3 0x2b70
51339 #define S_T6_NEU_STATE 4
51340 #define M_T6_NEU_STATE 0xfU
51341 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51342 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51344 #define S_T6_CTRL_STATE 0
51345 #define M_T6_CTRL_STATE 0xfU
51346 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51347 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51349 #define A_MAC_PORT_AET_STATUS_23 0x2b74
51350 #define A_MAC_PORT_AET_LIMITS3 0x2b78
51351 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
51352 #define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
51353 #define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
51355 #define S_BEAN_REM_FAULT 13
51356 #define V_BEAN_REM_FAULT(x) ((x) << S_BEAN_REM_FAULT)
51357 #define F_BEAN_REM_FAULT V_BEAN_REM_FAULT(1U)
51359 #define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
51360 #define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
51361 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
51363 #define S_BEAN_ABL_REM_FAULT 13
51364 #define V_BEAN_ABL_REM_FAULT(x) ((x) << S_BEAN_ABL_REM_FAULT)
51365 #define F_BEAN_ABL_REM_FAULT V_BEAN_ABL_REM_FAULT(1U)
51367 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
51368 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
51369 #define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
51370 #define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
51371 #define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
51372 #define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
51373 #define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
51374 #define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
51375 #define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
51376 #define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
51378 #define S_100GCR4 11
51379 #define V_100GCR4(x) ((x) << S_100GCR4)
51380 #define F_100GCR4 V_100GCR4(1U)
51382 #define S_100GKR4 10
51383 #define V_100GKR4(x) ((x) << S_100GKR4)
51384 #define F_100GKR4 V_100GKR4(1U)
51386 #define S_100GKP4 9
51387 #define V_100GKP4(x) ((x) << S_100GKP4)
51388 #define F_100GKP4 V_100GKP4(1U)
51390 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
51392 #define S_T5_TX_LINKEN 15
51393 #define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
51394 #define F_T5_TX_LINKEN V_T5_TX_LINKEN(1U)
51396 #define S_T5_TX_LINKRST 14
51397 #define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
51398 #define F_T5_TX_LINKRST V_T5_TX_LINKRST(1U)
51400 #define S_T5_TX_CFGWRT 13
51401 #define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
51402 #define F_T5_TX_CFGWRT V_T5_TX_CFGWRT(1U)
51404 #define S_T5_TX_CFGPTR 11
51405 #define M_T5_TX_CFGPTR 0x3U
51406 #define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
51407 #define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
51409 #define S_T5_TX_CFGEXT 10
51410 #define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
51411 #define F_T5_TX_CFGEXT V_T5_TX_CFGEXT(1U)
51413 #define S_T5_TX_CFGACT 9
51414 #define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
51415 #define F_T5_TX_CFGACT V_T5_TX_CFGACT(1U)
51417 #define S_T5_TX_RSYNCC 8
51418 #define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
51419 #define F_T5_TX_RSYNCC V_T5_TX_RSYNCC(1U)
51421 #define S_T5_TX_PLLSEL 6
51422 #define M_T5_TX_PLLSEL 0x3U
51423 #define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
51424 #define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
51426 #define S_T5_TX_EXTC16 5
51427 #define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
51428 #define F_T5_TX_EXTC16 V_T5_TX_EXTC16(1U)
51430 #define S_T5_TX_DCKSEL 4
51431 #define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
51432 #define F_T5_TX_DCKSEL V_T5_TX_DCKSEL(1U)
51434 #define S_T5_TX_RXLOOP 3
51435 #define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
51436 #define F_T5_TX_RXLOOP V_T5_TX_RXLOOP(1U)
51438 #define S_T5_TX_BWSEL 2
51439 #define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
51440 #define F_T5_TX_BWSEL V_T5_TX_BWSEL(1U)
51442 #define S_T5_TX_RTSEL 0
51443 #define M_T5_TX_RTSEL 0x3U
51444 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
51445 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
51447 #define S_T6_T5_TX_RXLOOP 5
51448 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
51449 #define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U)
51451 #define S_T5_TX_ENFFE4 4
51452 #define V_T5_TX_ENFFE4(x) ((x) << S_T5_TX_ENFFE4)
51453 #define F_T5_TX_ENFFE4 V_T5_TX_ENFFE4(1U)
51455 #define S_T6_T5_TX_BWSEL 2
51456 #define M_T6_T5_TX_BWSEL 0x3U
51457 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
51458 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
51460 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
51463 #define M_SPSEL 0x7U
51464 #define V_SPSEL(x) ((x) << S_SPSEL)
51465 #define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
51468 #define V_AFDWEN(x) ((x) << S_AFDWEN)
51469 #define F_AFDWEN V_AFDWEN(1U)
51472 #define V_TPGMD(x) ((x) << S_TPGMD)
51473 #define F_TPGMD V_TPGMD(1U)
51475 #define S_TC_FRCERR 10
51476 #define V_TC_FRCERR(x) ((x) << S_TC_FRCERR)
51477 #define F_TC_FRCERR V_TC_FRCERR(1U)
51479 #define S_T6_ERROR 9
51480 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
51481 #define F_T6_ERROR V_T6_ERROR(1U)
51484 #define V_SYNC(x) ((x) << S_SYNC)
51485 #define F_SYNC V_SYNC(1U)
51488 #define V_P7CHK(x) ((x) << S_P7CHK)
51489 #define F_P7CHK V_P7CHK(1U)
51491 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
51493 #define S_ZCALOVRD 8
51494 #define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
51495 #define F_ZCALOVRD V_ZCALOVRD(1U)
51498 #define V_AMMODE(x) ((x) << S_AMMODE)
51499 #define F_AMMODE V_AMMODE(1U)
51502 #define V_AEPOL(x) ((x) << S_AEPOL)
51503 #define F_AEPOL V_AEPOL(1U)
51506 #define V_AESRC(x) ((x) << S_AESRC)
51507 #define F_AESRC V_AESRC(1U)
51509 #define S_SASMODE 7
51510 #define V_SASMODE(x) ((x) << S_SASMODE)
51511 #define F_SASMODE V_SASMODE(1U)
51513 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
51515 #define S_T5DRVHIZ 5
51516 #define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
51517 #define F_T5DRVHIZ V_T5DRVHIZ(1U)
51519 #define S_T5SASIMP 4
51520 #define V_T5SASIMP(x) ((x) << S_T5SASIMP)
51521 #define F_T5SASIMP V_T5SASIMP(1U)
51524 #define M_T5SLEW 0x3U
51525 #define V_T5SLEW(x) ((x) << S_T5SLEW)
51526 #define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
51528 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
51530 #define S_T5C2BUFDCEN 5
51531 #define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
51532 #define F_T5C2BUFDCEN V_T5C2BUFDCEN(1U)
51534 #define S_T5DCCEN 4
51535 #define V_T5DCCEN(x) ((x) << S_T5DCCEN)
51536 #define F_T5DCCEN V_T5DCCEN(1U)
51538 #define S_T5REGBYP 3
51539 #define V_T5REGBYP(x) ((x) << S_T5REGBYP)
51540 #define F_T5REGBYP V_T5REGBYP(1U)
51542 #define S_T5REGAEN 2
51543 #define V_T5REGAEN(x) ((x) << S_T5REGAEN)
51544 #define F_T5REGAEN V_T5REGAEN(1U)
51546 #define S_T5REGAMP 0
51547 #define M_T5REGAMP 0x3U
51548 #define V_T5REGAMP(x) ((x) << S_T5REGAMP)
51549 #define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
51551 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
51554 #define V_RSTEP(x) ((x) << S_RSTEP)
51555 #define F_RSTEP V_RSTEP(1U)
51558 #define V_RLOCK(x) ((x) << S_RLOCK)
51559 #define F_RLOCK V_RLOCK(1U)
51562 #define M_RPOS 0x3fU
51563 #define V_RPOS(x) ((x) << S_RPOS)
51564 #define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
51566 #define S_DCLKSAM 7
51567 #define V_DCLKSAM(x) ((x) << S_DCLKSAM)
51568 #define F_DCLKSAM V_DCLKSAM(1U)
51570 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
51572 #define S_CALSSTN 3
51573 #define M_CALSSTN 0x7U
51574 #define V_CALSSTN(x) ((x) << S_CALSSTN)
51575 #define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
51577 #define S_CALSSTP 0
51578 #define M_CALSSTP 0x7U
51579 #define V_CALSSTP(x) ((x) << S_CALSSTP)
51580 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
51582 #define S_T6_CALSSTN 8
51583 #define M_T6_CALSSTN 0x3fU
51584 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
51585 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
51587 #define S_T6_CALSSTP 0
51588 #define M_T6_CALSSTP 0x3fU
51589 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
51590 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
51592 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
51595 #define M_DRTOL 0x1fU
51596 #define V_DRTOL(x) ((x) << S_DRTOL)
51597 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
51599 #define S_T6_DRTOL 2
51600 #define M_T6_DRTOL 0x7U
51601 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
51602 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
51604 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
51606 #define S_T5NXTT0 0
51607 #define M_T5NXTT0 0x1fU
51608 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
51609 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
51611 #define S_T6_NXTT0 0
51612 #define M_T6_NXTT0 0x3fU
51613 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
51614 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
51616 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
51618 #define S_T5NXTT1 0
51619 #define M_T5NXTT1 0x3fU
51620 #define V_T5NXTT1(x) ((x) << S_T5NXTT1)
51621 #define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
51623 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
51625 #define S_T5NXTT2 0
51626 #define M_T5NXTT2 0x3fU
51627 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
51628 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
51630 #define S_T6_NXTT2 0
51631 #define M_T6_NXTT2 0x3fU
51632 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
51633 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
51635 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
51638 #define M_NXTT3 0x3fU
51639 #define V_NXTT3(x) ((x) << S_NXTT3)
51640 #define G_NXTT3(x) (((x) >> S_NXTT3) & M_NXTT3)
51642 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
51644 #define S_T5TXPWR 0
51645 #define M_T5TXPWR 0x3fU
51646 #define V_T5TXPWR(x) ((x) << S_T5TXPWR)
51647 #define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
51649 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
51652 #define M_NXTPOL 0x7U
51653 #define V_NXTPOL(x) ((x) << S_NXTPOL)
51654 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
51656 #define S_T6_NXTPOL 0
51657 #define M_T6_NXTPOL 0xfU
51658 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
51659 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
51661 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
51663 #define S_CPREST 13
51664 #define V_CPREST(x) ((x) << S_CPREST)
51665 #define F_CPREST V_CPREST(1U)
51668 #define V_CINIT(x) ((x) << S_CINIT)
51669 #define F_CINIT V_CINIT(1U)
51671 #define S_SASCMD 10
51672 #define M_SASCMD 0x3U
51673 #define V_SASCMD(x) ((x) << S_SASCMD)
51674 #define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD)
51676 #define S_T6_C0UPDT 6
51677 #define M_T6_C0UPDT 0x3U
51678 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
51679 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
51682 #define M_C3UPDT 0x3U
51683 #define V_C3UPDT(x) ((x) << S_C3UPDT)
51684 #define G_C3UPDT(x) (((x) >> S_C3UPDT) & M_C3UPDT)
51686 #define S_T6_C2UPDT 2
51687 #define M_T6_C2UPDT 0x3U
51688 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
51689 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
51691 #define S_T6_C1UPDT 0
51692 #define M_T6_C1UPDT 0x3U
51693 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
51694 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
51696 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
51698 #define S_T6_C0STAT 6
51699 #define M_T6_C0STAT 0x3U
51700 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
51701 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
51704 #define M_C3STAT 0x3U
51705 #define V_C3STAT(x) ((x) << S_C3STAT)
51706 #define G_C3STAT(x) (((x) >> S_C3STAT) & M_C3STAT)
51708 #define S_T6_C2STAT 2
51709 #define M_T6_C2STAT 0x3U
51710 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
51711 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
51713 #define S_T6_C1STAT 0
51714 #define M_T6_C1STAT 0x3U
51715 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
51716 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
51718 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51719 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51722 #define M_AETAP0 0x7fU
51723 #define V_AETAP0(x) ((x) << S_AETAP0)
51724 #define G_AETAP0(x) (((x) >> S_AETAP0) & M_AETAP0)
51726 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51728 #define S_T5NIDAC1 0
51729 #define M_T5NIDAC1 0x3fU
51730 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
51731 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
51733 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51736 #define M_AETAP1 0x7fU
51737 #define V_AETAP1(x) ((x) << S_AETAP1)
51738 #define G_AETAP1(x) (((x) >> S_AETAP1) & M_AETAP1)
51740 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51742 #define S_T5NIDAC2 0
51743 #define M_T5NIDAC2 0x3fU
51744 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
51745 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
51747 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51750 #define M_AETAP2 0x7fU
51751 #define V_AETAP2(x) ((x) << S_AETAP2)
51752 #define G_AETAP2(x) (((x) >> S_AETAP2) & M_AETAP2)
51754 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
51757 #define M_AETAP3 0x7fU
51758 #define V_AETAP3(x) ((x) << S_AETAP3)
51759 #define G_AETAP3(x) (((x) >> S_AETAP3) & M_AETAP3)
51761 #define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
51764 #define M_ATUNEN 0xffU
51765 #define V_ATUNEN(x) ((x) << S_ATUNEN)
51766 #define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN)
51769 #define M_ATUNEP 0xffU
51770 #define V_ATUNEP(x) ((x) << S_ATUNEP)
51771 #define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP)
51773 #define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
51775 #define S_DCCCOMPINV 8
51776 #define V_DCCCOMPINV(x) ((x) << S_DCCCOMPINV)
51777 #define F_DCCCOMPINV V_DCCCOMPINV(1U)
51779 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
51780 #define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
51783 #define M_AS4X7 0x3U
51784 #define V_AS4X7(x) ((x) << S_AS4X7)
51785 #define G_AS4X7(x) (((x) >> S_AS4X7) & M_AS4X7)
51788 #define M_AS4X6 0x3U
51789 #define V_AS4X6(x) ((x) << S_AS4X6)
51790 #define G_AS4X6(x) (((x) >> S_AS4X6) & M_AS4X6)
51793 #define M_AS4X5 0x3U
51794 #define V_AS4X5(x) ((x) << S_AS4X5)
51795 #define G_AS4X5(x) (((x) >> S_AS4X5) & M_AS4X5)
51798 #define M_AS4X4 0x3U
51799 #define V_AS4X4(x) ((x) << S_AS4X4)
51800 #define G_AS4X4(x) (((x) >> S_AS4X4) & M_AS4X4)
51803 #define M_AS4X3 0x3U
51804 #define V_AS4X3(x) ((x) << S_AS4X3)
51805 #define G_AS4X3(x) (((x) >> S_AS4X3) & M_AS4X3)
51808 #define M_AS4X2 0x3U
51809 #define V_AS4X2(x) ((x) << S_AS4X2)
51810 #define G_AS4X2(x) (((x) >> S_AS4X2) & M_AS4X2)
51813 #define M_AS4X1 0x3U
51814 #define V_AS4X1(x) ((x) << S_AS4X1)
51815 #define G_AS4X1(x) (((x) >> S_AS4X1) & M_AS4X1)
51818 #define M_AS4X0 0x3U
51819 #define V_AS4X0(x) ((x) << S_AS4X0)
51820 #define G_AS4X0(x) (((x) >> S_AS4X0) & M_AS4X0)
51822 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
51824 #define S_T5AIDAC1 0
51825 #define M_T5AIDAC1 0x3fU
51826 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
51827 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
51829 #define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
51832 #define M_AS2X3 0x3U
51833 #define V_AS2X3(x) ((x) << S_AS2X3)
51834 #define G_AS2X3(x) (((x) >> S_AS2X3) & M_AS2X3)
51837 #define M_AS2X2 0x3U
51838 #define V_AS2X2(x) ((x) << S_AS2X2)
51839 #define G_AS2X2(x) (((x) >> S_AS2X2) & M_AS2X2)
51842 #define M_AS2X1 0x3U
51843 #define V_AS2X1(x) ((x) << S_AS2X1)
51844 #define G_AS2X1(x) (((x) >> S_AS2X1) & M_AS2X1)
51847 #define M_AS2X0 0x3U
51848 #define V_AS2X0(x) ((x) << S_AS2X0)
51849 #define G_AS2X0(x) (((x) >> S_AS2X0) & M_AS2X0)
51851 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
51852 #define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
51855 #define M_AS1X7 0x3U
51856 #define V_AS1X7(x) ((x) << S_AS1X7)
51857 #define G_AS1X7(x) (((x) >> S_AS1X7) & M_AS1X7)
51860 #define M_AS1X6 0x3U
51861 #define V_AS1X6(x) ((x) << S_AS1X6)
51862 #define G_AS1X6(x) (((x) >> S_AS1X6) & M_AS1X6)
51865 #define M_AS1X5 0x3U
51866 #define V_AS1X5(x) ((x) << S_AS1X5)
51867 #define G_AS1X5(x) (((x) >> S_AS1X5) & M_AS1X5)
51870 #define M_AS1X4 0x3U
51871 #define V_AS1X4(x) ((x) << S_AS1X4)
51872 #define G_AS1X4(x) (((x) >> S_AS1X4) & M_AS1X4)
51875 #define M_AS1X3 0x3U
51876 #define V_AS1X3(x) ((x) << S_AS1X3)
51877 #define G_AS1X3(x) (((x) >> S_AS1X3) & M_AS1X3)
51880 #define M_AS1X2 0x3U
51881 #define V_AS1X2(x) ((x) << S_AS1X2)
51882 #define G_AS1X2(x) (((x) >> S_AS1X2) & M_AS1X2)
51885 #define M_AS1X1 0x3U
51886 #define V_AS1X1(x) ((x) << S_AS1X1)
51887 #define G_AS1X1(x) (((x) >> S_AS1X1) & M_AS1X1)
51890 #define M_AS1X0 0x3U
51891 #define V_AS1X0(x) ((x) << S_AS1X0)
51892 #define G_AS1X0(x) (((x) >> S_AS1X0) & M_AS1X0)
51894 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
51897 #define M_AT4X 0xffU
51898 #define V_AT4X(x) ((x) << S_AT4X)
51899 #define G_AT4X(x) (((x) >> S_AT4X) & M_AT4X)
51901 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
51904 #define M_MAINSC 0x3fU
51905 #define V_MAINSC(x) ((x) << S_MAINSC)
51906 #define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
51909 #define M_POSTSC 0x3fU
51910 #define V_POSTSC(x) ((x) << S_POSTSC)
51911 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
51913 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
51916 #define M_AT2X 0xfU
51917 #define V_AT2X(x) ((x) << S_AT2X)
51918 #define G_AT2X(x) (((x) >> S_AT2X) & M_AT2X)
51920 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
51923 #define M_PRESC 0x1fU
51924 #define V_PRESC(x) ((x) << S_PRESC)
51925 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
51927 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
51930 #define M_ATSIGN 0xfU
51931 #define V_ATSIGN(x) ((x) << S_ATSIGN)
51932 #define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN)
51934 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
51935 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
51937 #define S_T5XADDR 1
51938 #define M_T5XADDR 0x1fU
51939 #define V_T5XADDR(x) ((x) << S_T5XADDR)
51940 #define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
51943 #define V_T5XWR(x) ((x) << S_T5XWR)
51944 #define F_T5XWR V_T5XWR(1U)
51946 #define S_T6_XADDR 1
51947 #define M_T6_XADDR 0x1fU
51948 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
51949 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
51951 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
51954 #define M_XDAT10 0xffffU
51955 #define V_XDAT10(x) ((x) << S_XDAT10)
51956 #define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
51958 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
51961 #define M_XDAT32 0xffffU
51962 #define V_XDAT32(x) ((x) << S_XDAT32)
51963 #define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
51965 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
51968 #define M_XDAT4 0xffU
51969 #define V_XDAT4(x) ((x) << S_XDAT4)
51970 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
51972 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
51975 #define M_XDAT54 0xffffU
51976 #define V_XDAT54(x) ((x) << S_XDAT54)
51977 #define G_XDAT54(x) (((x) >> S_XDAT54) & M_XDAT54)
51979 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
51981 #define S_DCCTIMEDOUT 15
51982 #define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
51983 #define F_DCCTIMEDOUT V_DCCTIMEDOUT(1U)
51985 #define S_DCCTIMEEN 14
51986 #define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
51987 #define F_DCCTIMEEN V_DCCTIMEEN(1U)
51989 #define S_DCCLOCK 13
51990 #define V_DCCLOCK(x) ((x) << S_DCCLOCK)
51991 #define F_DCCLOCK V_DCCLOCK(1U)
51993 #define S_DCCOFFSET 8
51994 #define M_DCCOFFSET 0x1fU
51995 #define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
51996 #define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
51998 #define S_DCCSTEP 6
51999 #define M_DCCSTEP 0x3U
52000 #define V_DCCSTEP(x) ((x) << S_DCCSTEP)
52001 #define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
52003 #define S_DCCASTEP 1
52004 #define M_DCCASTEP 0x1fU
52005 #define V_DCCASTEP(x) ((x) << S_DCCASTEP)
52006 #define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
52009 #define V_DCCAEN(x) ((x) << S_DCCAEN)
52010 #define F_DCCAEN V_DCCAEN(1U)
52012 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
52015 #define M_XDAT76 0xffffU
52016 #define V_XDAT76(x) ((x) << S_XDAT76)
52017 #define G_XDAT76(x) (((x) >> S_XDAT76) & M_XDAT76)
52019 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
52021 #define S_DCCOUT 12
52022 #define V_DCCOUT(x) ((x) << S_DCCOUT)
52023 #define F_DCCOUT V_DCCOUT(1U)
52025 #define S_DCCCLK 11
52026 #define V_DCCCLK(x) ((x) << S_DCCCLK)
52027 #define F_DCCCLK V_DCCCLK(1U)
52029 #define S_DCCHOLD 10
52030 #define V_DCCHOLD(x) ((x) << S_DCCHOLD)
52031 #define F_DCCHOLD V_DCCHOLD(1U)
52033 #define S_DCCSIGN 8
52034 #define M_DCCSIGN 0x3U
52035 #define V_DCCSIGN(x) ((x) << S_DCCSIGN)
52036 #define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
52039 #define M_DCCAMP 0x7fU
52040 #define V_DCCAMP(x) ((x) << S_DCCAMP)
52041 #define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
52044 #define V_DCCOEN(x) ((x) << S_DCCOEN)
52045 #define F_DCCOEN V_DCCOEN(1U)
52047 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
52049 #define S_DCCASIGN 7
52050 #define M_DCCASIGN 0x3U
52051 #define V_DCCASIGN(x) ((x) << S_DCCASIGN)
52052 #define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
52054 #define S_DCCAAMP 0
52055 #define M_DCCAAMP 0x7fU
52056 #define V_DCCAAMP(x) ((x) << S_DCCAAMP)
52057 #define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
52059 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
52061 #define S_DCCTIMEOUTVAL 0
52062 #define M_DCCTIMEOUTVAL 0xffffU
52063 #define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
52064 #define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
52066 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
52068 #define S_LPIDCLK 4
52069 #define V_LPIDCLK(x) ((x) << S_LPIDCLK)
52070 #define F_LPIDCLK V_LPIDCLK(1U)
52072 #define S_LPITERM 2
52073 #define M_LPITERM 0x3U
52074 #define V_LPITERM(x) ((x) << S_LPITERM)
52075 #define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
52077 #define S_LPIPRCD 0
52078 #define M_LPIPRCD 0x3U
52079 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
52080 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
52082 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
52084 #define S_T6_DCCTIMEEN 13
52085 #define M_T6_DCCTIMEEN 0x3U
52086 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
52087 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
52089 #define S_T6_DCCLOCK 11
52090 #define M_T6_DCCLOCK 0x3U
52091 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
52092 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
52094 #define S_T6_DCCOFFSET 8
52095 #define M_T6_DCCOFFSET 0x7U
52096 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
52097 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
52099 #define S_TX_LINKA_DCCSTEP_CTL 6
52100 #define M_TX_LINKA_DCCSTEP_CTL 0x3U
52101 #define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL)
52102 #define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL)
52104 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
52105 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
52106 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
52107 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
52110 #define M_OSIGN 0xfU
52111 #define V_OSIGN(x) ((x) << S_OSIGN)
52112 #define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN)
52114 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
52117 #define M_OS4X7 0x3U
52118 #define V_OS4X7(x) ((x) << S_OS4X7)
52119 #define G_OS4X7(x) (((x) >> S_OS4X7) & M_OS4X7)
52122 #define M_OS4X6 0x3U
52123 #define V_OS4X6(x) ((x) << S_OS4X6)
52124 #define G_OS4X6(x) (((x) >> S_OS4X6) & M_OS4X6)
52127 #define M_OS4X5 0x3U
52128 #define V_OS4X5(x) ((x) << S_OS4X5)
52129 #define G_OS4X5(x) (((x) >> S_OS4X5) & M_OS4X5)
52132 #define M_OS4X4 0x3U
52133 #define V_OS4X4(x) ((x) << S_OS4X4)
52134 #define G_OS4X4(x) (((x) >> S_OS4X4) & M_OS4X4)
52137 #define M_OS4X3 0x3U
52138 #define V_OS4X3(x) ((x) << S_OS4X3)
52139 #define G_OS4X3(x) (((x) >> S_OS4X3) & M_OS4X3)
52142 #define M_OS4X2 0x3U
52143 #define V_OS4X2(x) ((x) << S_OS4X2)
52144 #define G_OS4X2(x) (((x) >> S_OS4X2) & M_OS4X2)
52147 #define M_OS4X1 0x3U
52148 #define V_OS4X1(x) ((x) << S_OS4X1)
52149 #define G_OS4X1(x) (((x) >> S_OS4X1) & M_OS4X1)
52152 #define M_OS4X0 0x3U
52153 #define V_OS4X0(x) ((x) << S_OS4X0)
52154 #define G_OS4X0(x) (((x) >> S_OS4X0) & M_OS4X0)
52156 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
52159 #define M_OS2X3 0x3U
52160 #define V_OS2X3(x) ((x) << S_OS2X3)
52161 #define G_OS2X3(x) (((x) >> S_OS2X3) & M_OS2X3)
52164 #define M_OS2X2 0x3U
52165 #define V_OS2X2(x) ((x) << S_OS2X2)
52166 #define G_OS2X2(x) (((x) >> S_OS2X2) & M_OS2X2)
52169 #define M_OS2X1 0x3U
52170 #define V_OS2X1(x) ((x) << S_OS2X1)
52171 #define G_OS2X1(x) (((x) >> S_OS2X1) & M_OS2X1)
52174 #define M_OS2X0 0x3U
52175 #define V_OS2X0(x) ((x) << S_OS2X0)
52176 #define G_OS2X0(x) (((x) >> S_OS2X0) & M_OS2X0)
52178 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
52181 #define M_OS1X7 0x3U
52182 #define V_OS1X7(x) ((x) << S_OS1X7)
52183 #define G_OS1X7(x) (((x) >> S_OS1X7) & M_OS1X7)
52186 #define M_OS1X6 0x3U
52187 #define V_OS1X6(x) ((x) << S_OS1X6)
52188 #define G_OS1X6(x) (((x) >> S_OS1X6) & M_OS1X6)
52191 #define M_OS1X5 0x3U
52192 #define V_OS1X5(x) ((x) << S_OS1X5)
52193 #define G_OS1X5(x) (((x) >> S_OS1X5) & M_OS1X5)
52196 #define M_OS1X4 0x3U
52197 #define V_OS1X4(x) ((x) << S_OS1X4)
52198 #define G_OS1X4(x) (((x) >> S_OS1X4) & M_OS1X4)
52201 #define M_OS1X3 0x3U
52202 #define V_OS1X3(x) ((x) << S_OS1X3)
52203 #define G_OS1X3(x) (((x) >> S_OS1X3) & M_OS1X3)
52206 #define M_OS1X2 0x3U
52207 #define V_OS1X2(x) ((x) << S_OS1X2)
52208 #define G_OS1X2(x) (((x) >> S_OS1X2) & M_OS1X2)
52211 #define M_OS1X1 0x3U
52212 #define V_OS1X1(x) ((x) << S_OS1X1)
52213 #define G_OS1X1(x) (((x) >> S_OS1X1) & M_OS1X1)
52216 #define M_OS1X0 0x3U
52217 #define V_OS1X0(x) ((x) << S_OS1X0)
52218 #define G_OS1X0(x) (((x) >> S_OS1X0) & M_OS1X0)
52220 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
52223 #define M_OT4X 0xffU
52224 #define V_OT4X(x) ((x) << S_OT4X)
52225 #define G_OT4X(x) (((x) >> S_OT4X) & M_OT4X)
52227 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
52230 #define M_OT2X 0xfU
52231 #define V_OT2X(x) ((x) << S_OT2X)
52232 #define G_OT2X(x) (((x) >> S_OT2X) & M_OT2X)
52234 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
52237 #define M_OT1X 0xffU
52238 #define V_OT1X(x) ((x) << S_OT1X)
52239 #define G_OT1X(x) (((x) >> S_OT1X) & M_OT1X)
52241 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
52243 #define S_ERRORP 15
52244 #define V_ERRORP(x) ((x) << S_ERRORP)
52245 #define F_ERRORP V_ERRORP(1U)
52247 #define S_ERRORN 14
52248 #define V_ERRORN(x) ((x) << S_ERRORN)
52249 #define F_ERRORN V_ERRORN(1U)
52251 #define S_TESTENA 13
52252 #define V_TESTENA(x) ((x) << S_TESTENA)
52253 #define F_TESTENA V_TESTENA(1U)
52255 #define S_TUNEBIT 10
52256 #define M_TUNEBIT 0x7U
52257 #define V_TUNEBIT(x) ((x) << S_TUNEBIT)
52258 #define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT)
52260 #define S_DATAPOS 8
52261 #define M_DATAPOS 0x3U
52262 #define V_DATAPOS(x) ((x) << S_DATAPOS)
52263 #define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS)
52266 #define M_SEGSEL 0x1fU
52267 #define V_SEGSEL(x) ((x) << S_SEGSEL)
52268 #define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL)
52271 #define M_TAPSEL 0x3U
52272 #define V_TAPSEL(x) ((x) << S_TAPSEL)
52273 #define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL)
52275 #define S_DATASIGN 0
52276 #define V_DATASIGN(x) ((x) << S_DATASIGN)
52277 #define F_DATASIGN V_DATASIGN(1U)
52279 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
52281 #define S_SDOVRDEN 8
52282 #define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
52283 #define F_SDOVRDEN V_SDOVRDEN(1U)
52286 #define M_SDOVRD 0xffU
52287 #define V_SDOVRD(x) ((x) << S_SDOVRD)
52288 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
52290 #define S_T6_SDOVRD 0
52291 #define M_T6_SDOVRD 0xffffU
52292 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
52293 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
52295 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
52297 #define S_SLEWCODE 1
52298 #define M_SLEWCODE 0x3U
52299 #define V_SLEWCODE(x) ((x) << S_SLEWCODE)
52300 #define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
52303 #define V_ASEGEN(x) ((x) << S_ASEGEN)
52304 #define F_ASEGEN V_ASEGEN(1U)
52307 #define M_WCNT 0x3ffU
52308 #define V_WCNT(x) ((x) << S_WCNT)
52309 #define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT)
52311 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
52313 #define S_AECMDVAL 14
52314 #define V_AECMDVAL(x) ((x) << S_AECMDVAL)
52315 #define F_AECMDVAL V_AECMDVAL(1U)
52317 #define S_AECMD1312 12
52318 #define M_AECMD1312 0x3U
52319 #define V_AECMD1312(x) ((x) << S_AECMD1312)
52320 #define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
52322 #define S_AECMD70 0
52323 #define M_AECMD70 0xffU
52324 #define V_AECMD70(x) ((x) << S_AECMD70)
52325 #define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
52327 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
52329 #define S_C48DIVCTL 12
52330 #define M_C48DIVCTL 0x7U
52331 #define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
52332 #define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
52334 #define S_RATEDIVCTL 9
52335 #define M_RATEDIVCTL 0x7U
52336 #define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
52337 #define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
52339 #define S_ANLGFLSH 8
52340 #define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
52341 #define F_ANLGFLSH V_ANLGFLSH(1U)
52343 #define S_DCCTSTOUT 7
52344 #define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
52345 #define F_DCCTSTOUT V_DCCTSTOUT(1U)
52348 #define V_BSOUT(x) ((x) << S_BSOUT)
52349 #define F_BSOUT V_BSOUT(1U)
52352 #define V_BSIN(x) ((x) << S_BSIN)
52353 #define F_BSIN V_BSIN(1U)
52355 #define S_JTAGAMPL 3
52356 #define M_JTAGAMPL 0x3U
52357 #define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
52358 #define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
52361 #define V_JTAGTS(x) ((x) << S_JTAGTS)
52362 #define F_JTAGTS V_JTAGTS(1U)
52365 #define V_TS(x) ((x) << S_TS)
52366 #define F_TS V_TS(1U)
52369 #define V_OBS(x) ((x) << S_OBS)
52370 #define F_OBS V_OBS(1U)
52372 #define S_T6_SDOVRDEN 15
52373 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
52374 #define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U)
52377 #define V_BSOUTN(x) ((x) << S_BSOUTN)
52378 #define F_BSOUTN V_BSOUTN(1U)
52381 #define V_BSOUTP(x) ((x) << S_BSOUTP)
52382 #define F_BSOUTP V_BSOUTP(1U)
52384 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
52386 #define S_T6_T5_TX_RXLOOP 5
52387 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
52388 #define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U)
52390 #define S_T6_T5_TX_BWSEL 2
52391 #define M_T6_T5_TX_BWSEL 0x3U
52392 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
52393 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
52395 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
52397 #define S_T6_ERROR 9
52398 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
52399 #define F_T6_ERROR V_T6_ERROR(1U)
52401 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
52402 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
52403 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
52404 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
52405 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
52407 #define S_T6_CALSSTN 8
52408 #define M_T6_CALSSTN 0x3fU
52409 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
52410 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
52412 #define S_T6_CALSSTP 0
52413 #define M_T6_CALSSTP 0x3fU
52414 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
52415 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
52417 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
52419 #define S_T6_DRTOL 2
52420 #define M_T6_DRTOL 0x7U
52421 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
52422 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
52424 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
52426 #define S_T6_NXTT0 0
52427 #define M_T6_NXTT0 0x3fU
52428 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
52429 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
52431 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
52432 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
52434 #define S_T6_NXTT2 0
52435 #define M_T6_NXTT2 0x3fU
52436 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
52437 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
52439 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
52440 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
52441 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
52443 #define S_T6_NXTPOL 0
52444 #define M_T6_NXTPOL 0xfU
52445 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
52446 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
52448 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
52450 #define S_T6_C0UPDT 6
52451 #define M_T6_C0UPDT 0x3U
52452 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
52453 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
52455 #define S_T6_C2UPDT 2
52456 #define M_T6_C2UPDT 0x3U
52457 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
52458 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
52460 #define S_T6_C1UPDT 0
52461 #define M_T6_C1UPDT 0x3U
52462 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
52463 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
52465 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
52467 #define S_T6_C0STAT 6
52468 #define M_T6_C0STAT 0x3U
52469 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
52470 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
52472 #define S_T6_C2STAT 2
52473 #define M_T6_C2STAT 0x3U
52474 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
52475 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
52477 #define S_T6_C1STAT 0
52478 #define M_T6_C1STAT 0x3U
52479 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
52480 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
52482 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52483 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52484 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52485 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52486 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52487 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52488 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
52489 #define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
52490 #define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
52491 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
52492 #define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
52493 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
52494 #define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
52495 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
52496 #define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
52497 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
52498 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
52499 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
52500 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
52501 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
52502 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
52503 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
52505 #define S_T6_XADDR 1
52506 #define M_T6_XADDR 0x1fU
52507 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
52508 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
52510 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
52511 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
52512 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
52513 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
52514 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
52515 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
52516 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
52517 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
52518 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
52519 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
52520 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
52522 #define S_T6_DCCTIMEEN 13
52523 #define M_T6_DCCTIMEEN 0x3U
52524 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
52525 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
52527 #define S_T6_DCCLOCK 11
52528 #define M_T6_DCCLOCK 0x3U
52529 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
52530 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
52532 #define S_T6_DCCOFFSET 8
52533 #define M_T6_DCCOFFSET 0x7U
52534 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
52535 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
52537 #define S_TX_LINKB_DCCSTEP_CTL 6
52538 #define M_TX_LINKB_DCCSTEP_CTL 0x3U
52539 #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
52540 #define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL)
52542 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
52543 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
52544 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
52545 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
52546 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
52547 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
52548 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
52549 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
52550 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
52551 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
52552 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
52553 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
52555 #define S_T6_SDOVRD 0
52556 #define M_T6_SDOVRD 0xffffU
52557 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
52558 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
52560 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
52561 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
52562 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
52564 #define S_T6_SDOVRDEN 15
52565 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
52566 #define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U)
52568 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
52570 #define S_T5_RX_LINKEN 15
52571 #define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
52572 #define F_T5_RX_LINKEN V_T5_RX_LINKEN(1U)
52574 #define S_T5_RX_LINKRST 14
52575 #define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
52576 #define F_T5_RX_LINKRST V_T5_RX_LINKRST(1U)
52578 #define S_T5_RX_CFGWRT 13
52579 #define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
52580 #define F_T5_RX_CFGWRT V_T5_RX_CFGWRT(1U)
52582 #define S_T5_RX_CFGPTR 11
52583 #define M_T5_RX_CFGPTR 0x3U
52584 #define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
52585 #define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
52587 #define S_T5_RX_CFGEXT 10
52588 #define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
52589 #define F_T5_RX_CFGEXT V_T5_RX_CFGEXT(1U)
52591 #define S_T5_RX_CFGACT 9
52592 #define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
52593 #define F_T5_RX_CFGACT V_T5_RX_CFGACT(1U)
52595 #define S_T5_RX_AUXCLK 8
52596 #define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
52597 #define F_T5_RX_AUXCLK V_T5_RX_AUXCLK(1U)
52599 #define S_T5_RX_PLLSEL 6
52600 #define M_T5_RX_PLLSEL 0x3U
52601 #define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
52602 #define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
52604 #define S_T5_RX_DMSEL 4
52605 #define M_T5_RX_DMSEL 0x3U
52606 #define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
52607 #define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
52609 #define S_T5_RX_BWSEL 2
52610 #define M_T5_RX_BWSEL 0x3U
52611 #define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
52612 #define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
52614 #define S_T5_RX_RTSEL 0
52615 #define M_T5_RX_RTSEL 0x3U
52616 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
52617 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
52619 #define S_T5_RX_MODE8023AZ 8
52620 #define V_T5_RX_MODE8023AZ(x) ((x) << S_T5_RX_MODE8023AZ)
52621 #define F_T5_RX_MODE8023AZ V_T5_RX_MODE8023AZ(1U)
52623 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
52625 #define S_FERRST 10
52626 #define V_FERRST(x) ((x) << S_FERRST)
52627 #define F_FERRST V_FERRST(1U)
52630 #define V_ERRST(x) ((x) << S_ERRST)
52631 #define F_ERRST V_ERRST(1U)
52634 #define V_SYNCST(x) ((x) << S_SYNCST)
52635 #define F_SYNCST V_SYNCST(1U)
52638 #define V_WRPSM(x) ((x) << S_WRPSM)
52639 #define F_WRPSM V_WRPSM(1U)
52642 #define V_WPLPEN(x) ((x) << S_WPLPEN)
52643 #define F_WPLPEN V_WPLPEN(1U)
52646 #define V_WRPMD(x) ((x) << S_WRPMD)
52647 #define F_WRPMD V_WRPMD(1U)
52650 #define M_PATSEL 0x7U
52651 #define V_PATSEL(x) ((x) << S_PATSEL)
52652 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
52654 #define S_APLYDCD 15
52655 #define V_APLYDCD(x) ((x) << S_APLYDCD)
52656 #define F_APLYDCD V_APLYDCD(1U)
52659 #define M_PPOL 0x3U
52660 #define V_PPOL(x) ((x) << S_PPOL)
52661 #define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL)
52663 #define S_PCLKSEL 11
52664 #define M_PCLKSEL 0x3U
52665 #define V_PCLKSEL(x) ((x) << S_PCLKSEL)
52666 #define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL)
52668 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
52671 #define V_RSTUCK(x) ((x) << S_RSTUCK)
52672 #define F_RSTUCK V_RSTUCK(1U)
52675 #define V_FRZFW(x) ((x) << S_FRZFW)
52676 #define F_FRZFW V_FRZFW(1U)
52679 #define V_RSTFW(x) ((x) << S_RSTFW)
52680 #define F_RSTFW V_RSTFW(1U)
52683 #define V_SSCEN(x) ((x) << S_SSCEN)
52684 #define F_SSCEN V_SSCEN(1U)
52686 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
52688 #define S_H1ANOFST 12
52689 #define M_H1ANOFST 0xfU
52690 #define V_H1ANOFST(x) ((x) << S_H1ANOFST)
52691 #define G_H1ANOFST(x) (((x) >> S_H1ANOFST) & M_H1ANOFST)
52693 #define S_T6_TMSCAL 8
52694 #define M_T6_TMSCAL 0x3U
52695 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
52696 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
52698 #define S_T6_APADJ 7
52699 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
52700 #define F_T6_APADJ V_T6_APADJ(1U)
52702 #define S_T6_RSEL 6
52703 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
52704 #define F_T6_RSEL V_T6_RSEL(1U)
52706 #define S_T6_PHOFFS 0
52707 #define M_T6_PHOFFS 0x3fU
52708 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
52709 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
52711 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
52714 #define M_ROT00 0x3fU
52715 #define V_ROT00(x) ((x) << S_ROT00)
52716 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
52719 #define M_ROTA 0x3fU
52720 #define V_ROTA(x) ((x) << S_ROTA)
52721 #define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA)
52724 #define M_ROTD 0x3fU
52725 #define V_ROTD(x) ((x) << S_ROTD)
52726 #define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD)
52728 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
52731 #define M_FREQFW 0xffU
52732 #define V_FREQFW(x) ((x) << S_FREQFW)
52733 #define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
52736 #define V_FWSNAP(x) ((x) << S_FWSNAP)
52737 #define F_FWSNAP V_FWSNAP(1U)
52740 #define M_ROTE 0x3fU
52741 #define V_ROTE(x) ((x) << S_ROTE)
52742 #define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE)
52744 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
52747 #define M_RAOFFF 0xfU
52748 #define V_RAOFFF(x) ((x) << S_RAOFFF)
52749 #define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF)
52752 #define M_RAOFF 0x1fU
52753 #define V_RAOFF(x) ((x) << S_RAOFF)
52754 #define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF)
52756 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
52758 #define S_RBOOFF 10
52759 #define M_RBOOFF 0x1fU
52760 #define V_RBOOFF(x) ((x) << S_RBOOFF)
52761 #define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
52764 #define M_RBEOFF 0x1fU
52765 #define V_RBEOFF(x) ((x) << S_RBEOFF)
52766 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
52768 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
52770 #define S_T6_SPIFMT 8
52771 #define M_T6_SPIFMT 0xfU
52772 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
52773 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
52775 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
52777 #define S_T5BYTE1 8
52778 #define M_T5BYTE1 0xffU
52779 #define V_T5BYTE1(x) ((x) << S_T5BYTE1)
52780 #define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
52782 #define S_T5BYTE0 0
52783 #define M_T5BYTE0 0xffU
52784 #define V_T5BYTE0(x) ((x) << S_T5BYTE0)
52785 #define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
52787 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
52789 #define S_T5_RX_SMODE 8
52790 #define M_T5_RX_SMODE 0x7U
52791 #define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
52792 #define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
52794 #define S_T5_RX_ADCORR 7
52795 #define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
52796 #define F_T5_RX_ADCORR V_T5_RX_ADCORR(1U)
52798 #define S_T5_RX_TRAINEN 6
52799 #define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
52800 #define F_T5_RX_TRAINEN V_T5_RX_TRAINEN(1U)
52802 #define S_T5_RX_ASAMPQ 3
52803 #define M_T5_RX_ASAMPQ 0x7U
52804 #define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
52805 #define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
52807 #define S_T5_RX_ASAMP 0
52808 #define M_T5_RX_ASAMP 0x7U
52809 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
52810 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
52812 #define S_REQWOV 15
52813 #define V_REQWOV(x) ((x) << S_REQWOV)
52814 #define F_REQWOV V_REQWOV(1U)
52817 #define M_RASEL 0x7U
52818 #define V_RASEL(x) ((x) << S_RASEL)
52819 #define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL)
52821 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
52823 #define S_T6_WRAPSEL 15
52824 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
52825 #define F_T6_WRAPSEL V_T6_WRAPSEL(1U)
52828 #define V_ACTL(x) ((x) << S_ACTL)
52829 #define F_ACTL V_ACTL(1U)
52831 #define S_T6_PEAK 9
52832 #define M_T6_PEAK 0x1fU
52833 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
52834 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
52836 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
52838 #define S_T5SHORTV 10
52839 #define V_T5SHORTV(x) ((x) << S_T5SHORTV)
52840 #define F_T5SHORTV V_T5SHORTV(1U)
52842 #define S_T5VGAIN 0
52843 #define M_T5VGAIN 0x1fU
52844 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
52845 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
52847 #define S_FVOFFSKP 15
52848 #define V_FVOFFSKP(x) ((x) << S_FVOFFSKP)
52849 #define F_FVOFFSKP V_FVOFFSKP(1U)
52851 #define S_FGAINCHK 14
52852 #define V_FGAINCHK(x) ((x) << S_FGAINCHK)
52853 #define F_FGAINCHK V_FGAINCHK(1U)
52855 #define S_FH1ACAL 13
52856 #define V_FH1ACAL(x) ((x) << S_FH1ACAL)
52857 #define F_FH1ACAL V_FH1ACAL(1U)
52859 #define S_FH1AFLTR 11
52860 #define M_FH1AFLTR 0x3U
52861 #define V_FH1AFLTR(x) ((x) << S_FH1AFLTR)
52862 #define G_FH1AFLTR(x) (((x) >> S_FH1AFLTR) & M_FH1AFLTR)
52865 #define M_WGAIN 0x3U
52866 #define V_WGAIN(x) ((x) << S_WGAIN)
52867 #define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN)
52869 #define S_GAIN_STAT 7
52870 #define V_GAIN_STAT(x) ((x) << S_GAIN_STAT)
52871 #define F_GAIN_STAT V_GAIN_STAT(1U)
52873 #define S_T6_T5VGAIN 0
52874 #define M_T6_T5VGAIN 0x7fU
52875 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
52876 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
52878 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
52879 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
52882 #define M_IQSEP 0x1fU
52883 #define V_IQSEP(x) ((x) << S_IQSEP)
52884 #define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
52887 #define M_DUTYQ 0x1fU
52888 #define V_DUTYQ(x) ((x) << S_DUTYQ)
52889 #define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
52892 #define M_DUTYI 0x1fU
52893 #define V_DUTYI(x) ((x) << S_DUTYI)
52894 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
52896 #define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
52899 #define M_PMCFG 0x3U
52900 #define V_PMCFG(x) ((x) << S_PMCFG)
52901 #define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG)
52903 #define S_PMOFFTIME 0
52904 #define M_PMOFFTIME 0x3fU
52905 #define V_PMOFFTIME(x) ((x) << S_PMOFFTIME)
52906 #define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME)
52908 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
52911 #define V_SELI(x) ((x) << S_SELI)
52912 #define F_SELI V_SELI(1U)
52914 #define S_SERVREF 5
52915 #define M_SERVREF 0x7U
52916 #define V_SERVREF(x) ((x) << S_SERVREF)
52917 #define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF)
52920 #define M_IQAMP 0x1fU
52921 #define V_IQAMP(x) ((x) << S_IQAMP)
52922 #define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP)
52924 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
52927 #define M_DTHR 0x3fU
52928 #define V_DTHR(x) ((x) << S_DTHR)
52929 #define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
52932 #define M_SNUL 0x1fU
52933 #define V_SNUL(x) ((x) << S_SNUL)
52934 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
52936 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
52937 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
52939 #define S_SAVEADAC 8
52940 #define V_SAVEADAC(x) ((x) << S_SAVEADAC)
52941 #define F_SAVEADAC V_SAVEADAC(1U)
52944 #define V_LOAD2(x) ((x) << S_LOAD2)
52945 #define F_LOAD2 V_LOAD2(1U)
52948 #define V_LOAD1(x) ((x) << S_LOAD1)
52949 #define F_LOAD1 V_LOAD1(1U)
52951 #define S_WRTACC2 5
52952 #define V_WRTACC2(x) ((x) << S_WRTACC2)
52953 #define F_WRTACC2 V_WRTACC2(1U)
52955 #define S_WRTACC1 4
52956 #define V_WRTACC1(x) ((x) << S_WRTACC1)
52957 #define F_WRTACC1 V_WRTACC1(1U)
52959 #define S_SELAPAN 3
52960 #define V_SELAPAN(x) ((x) << S_SELAPAN)
52961 #define F_SELAPAN V_SELAPAN(1U)
52964 #define M_DASEL 0x7U
52965 #define V_DASEL(x) ((x) << S_DASEL)
52966 #define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL)
52968 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
52969 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
52970 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
52971 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
52973 #define S_ADSN_READWRITE 8
52974 #define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
52975 #define F_ADSN_READWRITE V_ADSN_READWRITE(1U)
52977 #define S_ADSN_READONLY 7
52978 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
52979 #define F_ADSN_READONLY V_ADSN_READONLY(1U)
52982 #define M_ADAC2 0xffU
52983 #define V_ADAC2(x) ((x) << S_ADAC2)
52984 #define G_ADAC2(x) (((x) >> S_ADAC2) & M_ADAC2)
52987 #define M_ADAC1 0xffU
52988 #define V_ADAC1(x) ((x) << S_ADAC1)
52989 #define G_ADAC1(x) (((x) >> S_ADAC1) & M_ADAC1)
52991 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
52993 #define S_FACCPLDYN 13
52994 #define V_FACCPLDYN(x) ((x) << S_FACCPLDYN)
52995 #define F_FACCPLDYN V_FACCPLDYN(1U)
52997 #define S_ACCPLGAIN 10
52998 #define M_ACCPLGAIN 0x7U
52999 #define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN)
53000 #define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN)
53002 #define S_ACCPLREF 8
53003 #define M_ACCPLREF 0x3U
53004 #define V_ACCPLREF(x) ((x) << S_ACCPLREF)
53005 #define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF)
53007 #define S_ACCPLSTEP 6
53008 #define M_ACCPLSTEP 0x3U
53009 #define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP)
53010 #define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP)
53012 #define S_ACCPLASTEP 1
53013 #define M_ACCPLASTEP 0x1fU
53014 #define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP)
53015 #define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP)
53018 #define V_FACCPL(x) ((x) << S_FACCPL)
53019 #define F_FACCPL V_FACCPL(1U)
53021 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
53023 #define S_ACCPLMEANS 15
53024 #define V_ACCPLMEANS(x) ((x) << S_ACCPLMEANS)
53025 #define F_ACCPLMEANS V_ACCPLMEANS(1U)
53027 #define S_CDROVREN 8
53028 #define V_CDROVREN(x) ((x) << S_CDROVREN)
53029 #define F_CDROVREN V_CDROVREN(1U)
53031 #define S_ACCPLBIAS 0
53032 #define M_ACCPLBIAS 0xffU
53033 #define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS)
53034 #define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS)
53036 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
53039 #define M_H1O2 0x3fU
53040 #define V_H1O2(x) ((x) << S_H1O2)
53041 #define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
53044 #define M_H1E2 0x3fU
53045 #define V_H1E2(x) ((x) << S_H1E2)
53046 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
53048 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
53051 #define M_H123CH 0x3fU
53052 #define V_H123CH(x) ((x) << S_H123CH)
53053 #define G_H123CH(x) (((x) >> S_H123CH) & M_H123CH)
53055 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
53058 #define M_H1O3 0x3fU
53059 #define V_H1O3(x) ((x) << S_H1O3)
53060 #define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
53063 #define M_H1E3 0x3fU
53064 #define V_H1E3(x) ((x) << S_H1E3)
53065 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
53067 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
53070 #define M_H1OX 0x3fU
53071 #define V_H1OX(x) ((x) << S_H1OX)
53072 #define G_H1OX(x) (((x) >> S_H1OX) & M_H1OX)
53075 #define M_H1EX 0x3fU
53076 #define V_H1EX(x) ((x) << S_H1EX)
53077 #define G_H1EX(x) (((x) >> S_H1EX) & M_H1EX)
53079 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
53082 #define M_H1O4 0x3fU
53083 #define V_H1O4(x) ((x) << S_H1O4)
53084 #define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
53087 #define M_H1E4 0x3fU
53088 #define V_H1E4(x) ((x) << S_H1E4)
53089 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
53091 #define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
53093 #define S_PILOCK 10
53094 #define V_PILOCK(x) ((x) << S_PILOCK)
53095 #define F_PILOCK V_PILOCK(1U)
53097 #define S_UNPKPKA 2
53098 #define M_UNPKPKA 0x3fU
53099 #define V_UNPKPKA(x) ((x) << S_UNPKPKA)
53100 #define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA)
53102 #define S_UNPKVGA 0
53103 #define M_UNPKVGA 0x3U
53104 #define V_UNPKVGA(x) ((x) << S_UNPKVGA)
53105 #define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA)
53107 #define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
53110 #define V_OVRAC(x) ((x) << S_OVRAC)
53111 #define F_OVRAC V_OVRAC(1U)
53114 #define V_OVRPK(x) ((x) << S_OVRPK)
53115 #define F_OVRPK V_OVRPK(1U)
53117 #define S_OVRTAILS 12
53118 #define M_OVRTAILS 0x3U
53119 #define V_OVRTAILS(x) ((x) << S_OVRTAILS)
53120 #define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS)
53122 #define S_OVRTAILV 9
53123 #define M_OVRTAILV 0x7U
53124 #define V_OVRTAILV(x) ((x) << S_OVRTAILV)
53125 #define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV)
53128 #define V_OVRCAP(x) ((x) << S_OVRCAP)
53129 #define F_OVRCAP V_OVRCAP(1U)
53131 #define S_OVRDCDPRE 7
53132 #define V_OVRDCDPRE(x) ((x) << S_OVRDCDPRE)
53133 #define F_OVRDCDPRE V_OVRDCDPRE(1U)
53135 #define S_OVRDCDPST 6
53136 #define V_OVRDCDPST(x) ((x) << S_OVRDCDPST)
53137 #define F_OVRDCDPST V_OVRDCDPST(1U)
53139 #define S_DCVSCTMODE 2
53140 #define V_DCVSCTMODE(x) ((x) << S_DCVSCTMODE)
53141 #define F_DCVSCTMODE V_DCVSCTMODE(1U)
53143 #define S_CDRANLGSW 0
53144 #define M_CDRANLGSW 0x3U
53145 #define V_CDRANLGSW(x) ((x) << S_CDRANLGSW)
53146 #define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW)
53148 #define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
53151 #define M_PFLAG 0x3U
53152 #define V_PFLAG(x) ((x) << S_PFLAG)
53153 #define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG)
53155 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
53158 #define V_DPCMD(x) ((x) << S_DPCMD)
53159 #define F_DPCMD V_DPCMD(1U)
53161 #define S_DACCLIP 15
53162 #define V_DACCLIP(x) ((x) << S_DACCLIP)
53163 #define F_DACCLIP V_DACCLIP(1U)
53165 #define S_DPCFRZ 14
53166 #define V_DPCFRZ(x) ((x) << S_DPCFRZ)
53167 #define F_DPCFRZ V_DPCFRZ(1U)
53169 #define S_DPCLKNQ 11
53170 #define V_DPCLKNQ(x) ((x) << S_DPCLKNQ)
53171 #define F_DPCLKNQ V_DPCLKNQ(1U)
53173 #define S_DPCWDFE 10
53174 #define V_DPCWDFE(x) ((x) << S_DPCWDFE)
53175 #define F_DPCWDFE V_DPCWDFE(1U)
53178 #define V_DPCWPK(x) ((x) << S_DPCWPK)
53179 #define F_DPCWPK V_DPCWPK(1U)
53181 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
53183 #define S_VIEWSCAN 4
53184 #define V_VIEWSCAN(x) ((x) << S_VIEWSCAN)
53185 #define F_VIEWSCAN V_VIEWSCAN(1U)
53187 #define S_T6_ODEC 0
53188 #define M_T6_ODEC 0xfU
53189 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
53190 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
53192 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
53194 #define S_T5BER6VAL 15
53195 #define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
53196 #define F_T5BER6VAL V_T5BER6VAL(1U)
53198 #define S_T5BER6 14
53199 #define V_T5BER6(x) ((x) << S_T5BER6)
53200 #define F_T5BER6 V_T5BER6(1U)
53202 #define S_T5BER3VAL 13
53203 #define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
53204 #define F_T5BER3VAL V_T5BER3VAL(1U)
53206 #define S_T5TOOFAST 12
53207 #define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
53208 #define F_T5TOOFAST V_T5TOOFAST(1U)
53210 #define S_T5DPCCMP 9
53211 #define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
53212 #define F_T5DPCCMP V_T5DPCCMP(1U)
53214 #define S_T5DACCMP 8
53215 #define V_T5DACCMP(x) ((x) << S_T5DACCMP)
53216 #define F_T5DACCMP V_T5DACCMP(1U)
53218 #define S_T5DDCCMP 7
53219 #define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
53220 #define F_T5DDCCMP V_T5DDCCMP(1U)
53222 #define S_T5AERRFLG 6
53223 #define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
53224 #define F_T5AERRFLG V_T5AERRFLG(1U)
53226 #define S_T5WERRFLG 5
53227 #define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
53228 #define F_T5WERRFLG V_T5WERRFLG(1U)
53230 #define S_T5TRCMP 4
53231 #define V_T5TRCMP(x) ((x) << S_T5TRCMP)
53232 #define F_T5TRCMP V_T5TRCMP(1U)
53234 #define S_T5VLCKF 3
53235 #define V_T5VLCKF(x) ((x) << S_T5VLCKF)
53236 #define F_T5VLCKF V_T5VLCKF(1U)
53238 #define S_T5ROCCMP 2
53239 #define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
53240 #define F_T5ROCCMP V_T5ROCCMP(1U)
53242 #define S_T5DQCCCMP 1
53243 #define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
53244 #define F_T5DQCCCMP V_T5DQCCCMP(1U)
53246 #define S_T5OCCMP 0
53247 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
53248 #define F_T5OCCMP V_T5OCCMP(1U)
53250 #define S_RX_LINKA_ACCCMP_RIS 11
53251 #define V_RX_LINKA_ACCCMP_RIS(x) ((x) << S_RX_LINKA_ACCCMP_RIS)
53252 #define F_RX_LINKA_ACCCMP_RIS V_RX_LINKA_ACCCMP_RIS(1U)
53254 #define S_DCCCMP 10
53255 #define V_DCCCMP(x) ((x) << S_DCCCMP)
53256 #define F_DCCCMP V_DCCCMP(1U)
53258 #define S_T5IQCMP 1
53259 #define V_T5IQCMP(x) ((x) << S_T5IQCMP)
53260 #define F_T5IQCMP V_T5IQCMP(1U)
53262 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
53265 #define V_FLOFF(x) ((x) << S_FLOFF)
53266 #define F_FLOFF V_FLOFF(1U)
53268 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
53270 #define S_H25SPC 15
53271 #define V_H25SPC(x) ((x) << S_H25SPC)
53272 #define F_H25SPC V_H25SPC(1U)
53274 #define S_FTOOFAST 8
53275 #define V_FTOOFAST(x) ((x) << S_FTOOFAST)
53276 #define F_FTOOFAST V_FTOOFAST(1U)
53278 #define S_FINTTRIM 7
53279 #define V_FINTTRIM(x) ((x) << S_FINTTRIM)
53280 #define F_FINTTRIM V_FINTTRIM(1U)
53283 #define V_FDINV(x) ((x) << S_FDINV)
53284 #define F_FDINV V_FDINV(1U)
53287 #define V_FHGS(x) ((x) << S_FHGS)
53288 #define F_FHGS V_FHGS(1U)
53291 #define V_FH6H12(x) ((x) << S_FH6H12)
53292 #define F_FH6H12 V_FH6H12(1U)
53295 #define V_FH1CAL(x) ((x) << S_FH1CAL)
53296 #define F_FH1CAL V_FH1CAL(1U)
53298 #define S_FINTCAL 2
53299 #define V_FINTCAL(x) ((x) << S_FINTCAL)
53300 #define F_FINTCAL V_FINTCAL(1U)
53303 #define V_FDCA(x) ((x) << S_FDCA)
53304 #define F_FDCA V_FDCA(1U)
53307 #define V_FDQCC(x) ((x) << S_FDQCC)
53308 #define F_FDQCC V_FDQCC(1U)
53310 #define S_FDCCAL 14
53311 #define V_FDCCAL(x) ((x) << S_FDCCAL)
53312 #define F_FDCCAL V_FDCCAL(1U)
53314 #define S_FROTCAL 13
53315 #define V_FROTCAL(x) ((x) << S_FROTCAL)
53316 #define F_FROTCAL V_FROTCAL(1U)
53318 #define S_FIQAMP 12
53319 #define V_FIQAMP(x) ((x) << S_FIQAMP)
53320 #define F_FIQAMP V_FIQAMP(1U)
53322 #define S_FRPTCALF 11
53323 #define V_FRPTCALF(x) ((x) << S_FRPTCALF)
53324 #define F_FRPTCALF V_FRPTCALF(1U)
53326 #define S_FINTCALGS 10
53327 #define V_FINTCALGS(x) ((x) << S_FINTCALGS)
53328 #define F_FINTCALGS V_FINTCALGS(1U)
53331 #define V_FDCC(x) ((x) << S_FDCC)
53332 #define F_FDCC V_FDCC(1U)
53335 #define V_FDCD(x) ((x) << S_FDCD)
53336 #define F_FDCD V_FDCD(1U)
53338 #define S_FINTRCALDYN 1
53339 #define V_FINTRCALDYN(x) ((x) << S_FINTRCALDYN)
53340 #define F_FINTRCALDYN V_FINTRCALDYN(1U)
53343 #define V_FQCC(x) ((x) << S_FQCC)
53344 #define F_FQCC V_FQCC(1U)
53346 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
53348 #define S_LOFE2S_READWRITE 16
53349 #define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
53350 #define F_LOFE2S_READWRITE V_LOFE2S_READWRITE(1U)
53352 #define S_LOFE2S_READONLY 14
53353 #define M_LOFE2S_READONLY 0x3U
53354 #define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
53355 #define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
53358 #define M_LOFE2 0x3fU
53359 #define V_LOFE2(x) ((x) << S_LOFE2)
53360 #define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
53362 #define S_LOFE1S_READWRITE 7
53363 #define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
53364 #define F_LOFE1S_READWRITE V_LOFE1S_READWRITE(1U)
53366 #define S_LOFE1S_READONLY 6
53367 #define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
53368 #define F_LOFE1S_READONLY V_LOFE1S_READONLY(1U)
53371 #define M_LOFE1 0x3fU
53372 #define V_LOFE1(x) ((x) << S_LOFE1)
53373 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
53375 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
53377 #define S_QCCIND 13
53378 #define V_QCCIND(x) ((x) << S_QCCIND)
53379 #define F_QCCIND V_QCCIND(1U)
53381 #define S_DCDIND 10
53382 #define M_DCDIND 0x7U
53383 #define V_DCDIND(x) ((x) << S_DCDIND)
53384 #define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND)
53387 #define M_DCCIND 0x3U
53388 #define V_DCCIND(x) ((x) << S_DCCIND)
53389 #define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND)
53392 #define V_CFSEL(x) ((x) << S_CFSEL)
53393 #define F_CFSEL V_CFSEL(1U)
53396 #define M_LOFCH 0x1fU
53397 #define V_LOFCH(x) ((x) << S_LOFCH)
53398 #define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH)
53400 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
53402 #define S_LOFO2S_READWRITE 15
53403 #define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
53404 #define F_LOFO2S_READWRITE V_LOFO2S_READWRITE(1U)
53406 #define S_LOFO2S_READONLY 14
53407 #define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
53408 #define F_LOFO2S_READONLY V_LOFO2S_READONLY(1U)
53411 #define M_LOFO2 0x3fU
53412 #define V_LOFO2(x) ((x) << S_LOFO2)
53413 #define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
53415 #define S_LOFO1S_READWRITE 7
53416 #define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
53417 #define F_LOFO1S_READWRITE V_LOFO1S_READWRITE(1U)
53419 #define S_LOFO1S_READONLY 6
53420 #define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
53421 #define F_LOFO1S_READONLY V_LOFO1S_READONLY(1U)
53424 #define M_LOFO1 0x3fU
53425 #define V_LOFO1(x) ((x) << S_LOFO1)
53426 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
53428 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
53431 #define M_LOFU 0x7fU
53432 #define V_LOFU(x) ((x) << S_LOFU)
53433 #define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU)
53436 #define M_LOFL 0x7fU
53437 #define V_LOFL(x) ((x) << S_LOFL)
53438 #define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL)
53440 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
53442 #define S_LOFE4S_READWRITE 15
53443 #define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
53444 #define F_LOFE4S_READWRITE V_LOFE4S_READWRITE(1U)
53446 #define S_LOFE4S_READONLY 14
53447 #define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
53448 #define F_LOFE4S_READONLY V_LOFE4S_READONLY(1U)
53451 #define M_LOFE 0x3fU
53452 #define V_LOFE(x) ((x) << S_LOFE)
53453 #define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
53455 #define S_LOFE3S_READWRITE 7
53456 #define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
53457 #define F_LOFE3S_READWRITE V_LOFE3S_READWRITE(1U)
53459 #define S_LOFE3S_READONLY 6
53460 #define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
53461 #define F_LOFE3S_READONLY V_LOFE3S_READONLY(1U)
53464 #define M_LOFE3 0x3fU
53465 #define V_LOFE3(x) ((x) << S_LOFE3)
53466 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
53468 #define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
53470 #define S_HBISTMAN 12
53471 #define V_HBISTMAN(x) ((x) << S_HBISTMAN)
53472 #define F_HBISTMAN V_HBISTMAN(1U)
53474 #define S_HBISTRES 11
53475 #define V_HBISTRES(x) ((x) << S_HBISTRES)
53476 #define F_HBISTRES V_HBISTRES(1U)
53478 #define S_HBISTSP 8
53479 #define M_HBISTSP 0x7U
53480 #define V_HBISTSP(x) ((x) << S_HBISTSP)
53481 #define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP)
53483 #define S_HBISTEN 7
53484 #define V_HBISTEN(x) ((x) << S_HBISTEN)
53485 #define F_HBISTEN V_HBISTEN(1U)
53487 #define S_HBISTRST 6
53488 #define V_HBISTRST(x) ((x) << S_HBISTRST)
53489 #define F_HBISTRST V_HBISTRST(1U)
53492 #define V_HCOMP(x) ((x) << S_HCOMP)
53493 #define F_HCOMP V_HCOMP(1U)
53496 #define V_HPASS(x) ((x) << S_HPASS)
53497 #define F_HPASS V_HPASS(1U)
53500 #define M_HSEL 0xfU
53501 #define V_HSEL(x) ((x) << S_HSEL)
53502 #define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL)
53504 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
53506 #define S_LOFO4S_READWRITE 15
53507 #define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
53508 #define F_LOFO4S_READWRITE V_LOFO4S_READWRITE(1U)
53510 #define S_LOFO4S_READONLY 14
53511 #define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
53512 #define F_LOFO4S_READONLY V_LOFO4S_READONLY(1U)
53515 #define M_LOFO4 0x3fU
53516 #define V_LOFO4(x) ((x) << S_LOFO4)
53517 #define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
53519 #define S_LOFO3S_READWRITE 7
53520 #define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
53521 #define F_LOFO3S_READWRITE V_LOFO3S_READWRITE(1U)
53523 #define S_LOFO3S_READONLY 6
53524 #define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
53525 #define F_LOFO3S_READONLY V_LOFO3S_READONLY(1U)
53528 #define M_LOFO3 0x3fU
53529 #define V_LOFO3(x) ((x) << S_LOFO3)
53530 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
53532 #define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
53534 #define S_RX_LINKA_ACCCMP_BIST 13
53535 #define V_RX_LINKA_ACCCMP_BIST(x) ((x) << S_RX_LINKA_ACCCMP_BIST)
53536 #define F_RX_LINKA_ACCCMP_BIST V_RX_LINKA_ACCCMP_BIST(1U)
53539 #define V_ACCEN(x) ((x) << S_ACCEN)
53540 #define F_ACCEN V_ACCEN(1U)
53542 #define S_ACCRST 11
53543 #define V_ACCRST(x) ((x) << S_ACCRST)
53544 #define F_ACCRST V_ACCRST(1U)
53547 #define M_ACCIND 0x7U
53548 #define V_ACCIND(x) ((x) << S_ACCIND)
53549 #define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND)
53552 #define M_ACCRD 0xffU
53553 #define V_ACCRD(x) ((x) << S_ACCRD)
53554 #define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD)
53556 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
53558 #define S_T5E1SN_READWRITE 15
53559 #define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
53560 #define F_T5E1SN_READWRITE V_T5E1SN_READWRITE(1U)
53562 #define S_T5E1SN_READONLY 14
53563 #define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
53564 #define F_T5E1SN_READONLY V_T5E1SN_READONLY(1U)
53566 #define S_T5E1AMP 8
53567 #define M_T5E1AMP 0x3fU
53568 #define V_T5E1AMP(x) ((x) << S_T5E1AMP)
53569 #define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
53571 #define S_T5E0SN_READWRITE 7
53572 #define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
53573 #define F_T5E0SN_READWRITE V_T5E0SN_READWRITE(1U)
53575 #define S_T5E0SN_READONLY 6
53576 #define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
53577 #define F_T5E0SN_READONLY V_T5E0SN_READONLY(1U)
53579 #define S_T5E0AMP 0
53580 #define M_T5E0AMP 0x3fU
53581 #define V_T5E0AMP(x) ((x) << S_T5E0AMP)
53582 #define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
53584 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
53586 #define S_T5LFREG 12
53587 #define V_T5LFREG(x) ((x) << S_T5LFREG)
53588 #define F_T5LFREG V_T5LFREG(1U)
53590 #define S_T5LFRC 11
53591 #define V_T5LFRC(x) ((x) << S_T5LFRC)
53592 #define F_T5LFRC V_T5LFRC(1U)
53594 #define S_T5LFSEL 8
53595 #define M_T5LFSEL 0x7U
53596 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
53597 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
53599 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
53602 #define V_LFREG(x) ((x) << S_LFREG)
53603 #define F_LFREG V_LFREG(1U)
53606 #define V_LFRC(x) ((x) << S_LFRC)
53607 #define F_LFRC V_LFRC(1U)
53609 #define S_LGIDLE 13
53610 #define V_LGIDLE(x) ((x) << S_LGIDLE)
53611 #define F_LGIDLE V_LGIDLE(1U)
53614 #define M_LFTGT 0x1fU
53615 #define V_LFTGT(x) ((x) << S_LFTGT)
53616 #define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT)
53619 #define V_LGTGT(x) ((x) << S_LGTGT)
53620 #define F_LGTGT V_LGTGT(1U)
53623 #define V_LRDY(x) ((x) << S_LRDY)
53624 #define F_LRDY V_LRDY(1U)
53627 #define V_LIDLE(x) ((x) << S_LIDLE)
53628 #define F_LIDLE V_LIDLE(1U)
53631 #define M_LCURR 0x1fU
53632 #define V_LCURR(x) ((x) << S_LCURR)
53633 #define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR)
53635 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
53637 #define S_OFFSN_READWRITE 14
53638 #define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
53639 #define F_OFFSN_READWRITE V_OFFSN_READWRITE(1U)
53641 #define S_OFFSN_READONLY 13
53642 #define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
53643 #define F_OFFSN_READONLY V_OFFSN_READONLY(1U)
53646 #define M_OFFAMP 0x1fU
53647 #define V_OFFAMP(x) ((x) << S_OFFAMP)
53648 #define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
53651 #define V_SDACDC(x) ((x) << S_SDACDC)
53652 #define F_SDACDC V_SDACDC(1U)
53655 #define M_OFFSN 0x3U
53656 #define V_OFFSN(x) ((x) << S_OFFSN)
53657 #define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN)
53659 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
53661 #define S_T5_RX_SETHDIS 7
53662 #define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
53663 #define F_T5_RX_SETHDIS V_T5_RX_SETHDIS(1U)
53665 #define S_T5_RX_PDTERM 6
53666 #define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
53667 #define F_T5_RX_PDTERM V_T5_RX_PDTERM(1U)
53669 #define S_T5_RX_BYPASS 5
53670 #define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
53671 #define F_T5_RX_BYPASS V_T5_RX_BYPASS(1U)
53673 #define S_T5_RX_LPFEN 4
53674 #define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
53675 #define F_T5_RX_LPFEN V_T5_RX_LPFEN(1U)
53677 #define S_T5_RX_VGABOD 3
53678 #define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
53679 #define F_T5_RX_VGABOD V_T5_RX_VGABOD(1U)
53681 #define S_T5_RX_VTBYP 2
53682 #define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
53683 #define F_T5_RX_VTBYP V_T5_RX_VTBYP(1U)
53685 #define S_T5_RX_VTERM 0
53686 #define M_T5_RX_VTERM 0x3U
53687 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
53688 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
53690 #define S_RX_OVRSUMPD 15
53691 #define V_RX_OVRSUMPD(x) ((x) << S_RX_OVRSUMPD)
53692 #define F_RX_OVRSUMPD V_RX_OVRSUMPD(1U)
53694 #define S_RX_OVRKBPD 14
53695 #define V_RX_OVRKBPD(x) ((x) << S_RX_OVRKBPD)
53696 #define F_RX_OVRKBPD V_RX_OVRKBPD(1U)
53698 #define S_RX_OVRDIVPD 13
53699 #define V_RX_OVRDIVPD(x) ((x) << S_RX_OVRDIVPD)
53700 #define F_RX_OVRDIVPD V_RX_OVRDIVPD(1U)
53702 #define S_RX_OFFVGADIS 12
53703 #define V_RX_OFFVGADIS(x) ((x) << S_RX_OFFVGADIS)
53704 #define F_RX_OFFVGADIS V_RX_OFFVGADIS(1U)
53706 #define S_RX_OFFACDIS 11
53707 #define V_RX_OFFACDIS(x) ((x) << S_RX_OFFACDIS)
53708 #define F_RX_OFFACDIS V_RX_OFFACDIS(1U)
53710 #define S_RX_VTERM 10
53711 #define V_RX_VTERM(x) ((x) << S_RX_VTERM)
53712 #define F_RX_VTERM V_RX_VTERM(1U)
53714 #define S_RX_DISSPY2D 8
53715 #define V_RX_DISSPY2D(x) ((x) << S_RX_DISSPY2D)
53716 #define F_RX_DISSPY2D V_RX_DISSPY2D(1U)
53718 #define S_RX_OBSOVEN 7
53719 #define V_RX_OBSOVEN(x) ((x) << S_RX_OBSOVEN)
53720 #define F_RX_OBSOVEN V_RX_OBSOVEN(1U)
53722 #define S_RX_LINKANLGSW 0
53723 #define M_RX_LINKANLGSW 0x7fU
53724 #define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW)
53725 #define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW)
53727 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
53729 #define S_ISTRIMS 14
53730 #define M_ISTRIMS 0x3U
53731 #define V_ISTRIMS(x) ((x) << S_ISTRIMS)
53732 #define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
53735 #define M_ISTRIM 0x3fU
53736 #define V_ISTRIM(x) ((x) << S_ISTRIM)
53737 #define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
53740 #define V_HALF1(x) ((x) << S_HALF1)
53741 #define F_HALF1 V_HALF1(1U)
53744 #define V_HALF2(x) ((x) << S_HALF2)
53745 #define F_HALF2 V_HALF2(1U)
53748 #define M_INTDAC 0x3fU
53749 #define V_INTDAC(x) ((x) << S_INTDAC)
53750 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
53752 #define S_INTDACEGS 13
53753 #define M_INTDACEGS 0x7U
53754 #define V_INTDACEGS(x) ((x) << S_INTDACEGS)
53755 #define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS)
53757 #define S_INTDACE 8
53758 #define M_INTDACE 0x1fU
53759 #define V_INTDACE(x) ((x) << S_INTDACE)
53760 #define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE)
53762 #define S_INTDACGS 6
53763 #define M_INTDACGS 0x3U
53764 #define V_INTDACGS(x) ((x) << S_INTDACGS)
53765 #define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS)
53767 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
53769 #define S_MINWDTH 5
53770 #define M_MINWDTH 0x1fU
53771 #define V_MINWDTH(x) ((x) << S_MINWDTH)
53772 #define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
53774 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
53776 #define S_T5SMQM 13
53777 #define M_T5SMQM 0x7U
53778 #define V_T5SMQM(x) ((x) << S_T5SMQM)
53779 #define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
53782 #define M_T5SMQ 0xffU
53783 #define V_T5SMQ(x) ((x) << S_T5SMQ)
53784 #define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
53787 #define M_T5EMMD 0x3U
53788 #define V_T5EMMD(x) ((x) << S_T5EMMD)
53789 #define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
53791 #define S_T5EMBRDY 2
53792 #define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
53793 #define F_T5EMBRDY V_T5EMBRDY(1U)
53795 #define S_T5EMBUMP 1
53796 #define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
53797 #define F_T5EMBUMP V_T5EMBUMP(1U)
53800 #define V_T5EMEN(x) ((x) << S_T5EMEN)
53801 #define F_T5EMEN V_T5EMEN(1U)
53804 #define M_SMQM 0x7U
53805 #define V_SMQM(x) ((x) << S_SMQM)
53806 #define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM)
53809 #define M_SMQ 0xffU
53810 #define V_SMQ(x) ((x) << S_SMQ)
53811 #define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ)
53813 #define S_T6_EMMD 3
53814 #define M_T6_EMMD 0x3U
53815 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
53816 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
53818 #define S_T6_EMBRDY 2
53819 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
53820 #define F_T6_EMBRDY V_T6_EMBRDY(1U)
53822 #define S_T6_EMBUMP 1
53823 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
53824 #define F_T6_EMBUMP V_T6_EMBUMP(1U)
53826 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
53829 #define V_EMF8(x) ((x) << S_EMF8)
53830 #define F_EMF8 V_EMF8(1U)
53833 #define M_EMCNT 0xffU
53834 #define V_EMCNT(x) ((x) << S_EMCNT)
53835 #define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
53838 #define V_EMOFLO(x) ((x) << S_EMOFLO)
53839 #define F_EMOFLO V_EMOFLO(1U)
53842 #define V_EMCRST(x) ((x) << S_EMCRST)
53843 #define F_EMCRST V_EMCRST(1U)
53846 #define V_EMCEN(x) ((x) << S_EMCEN)
53847 #define F_EMCEN V_EMCEN(1U)
53850 #define V_EMSF(x) ((x) << S_EMSF)
53851 #define F_EMSF V_EMSF(1U)
53853 #define S_EMDATA59 12
53854 #define V_EMDATA59(x) ((x) << S_EMDATA59)
53855 #define F_EMDATA59 V_EMDATA59(1U)
53857 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
53859 #define S_SM2RDY 15
53860 #define V_SM2RDY(x) ((x) << S_SM2RDY)
53861 #define F_SM2RDY V_SM2RDY(1U)
53863 #define S_SM2RST 14
53864 #define V_SM2RST(x) ((x) << S_SM2RST)
53865 #define F_SM2RST V_SM2RST(1U)
53868 #define M_APDF 0xfffU
53869 #define V_APDF(x) ((x) << S_APDF)
53870 #define G_APDF(x) (((x) >> S_APDF) & M_APDF)
53872 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
53875 #define M_SM0LEN 0x7fffU
53876 #define V_SM0LEN(x) ((x) << S_SM0LEN)
53877 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
53879 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
53881 #define S_FTIMEOUT 15
53882 #define V_FTIMEOUT(x) ((x) << S_FTIMEOUT)
53883 #define F_FTIMEOUT V_FTIMEOUT(1U)
53885 #define S_FROTCAL4 14
53886 #define V_FROTCAL4(x) ((x) << S_FROTCAL4)
53887 #define F_FROTCAL4 V_FROTCAL4(1U)
53890 #define V_FDCD2(x) ((x) << S_FDCD2)
53891 #define F_FDCD2 V_FDCD2(1U)
53893 #define S_FPRBSPOLTOG 12
53894 #define V_FPRBSPOLTOG(x) ((x) << S_FPRBSPOLTOG)
53895 #define F_FPRBSPOLTOG V_FPRBSPOLTOG(1U)
53897 #define S_FPRBSOFF2 11
53898 #define V_FPRBSOFF2(x) ((x) << S_FPRBSOFF2)
53899 #define F_FPRBSOFF2 V_FPRBSOFF2(1U)
53901 #define S_FDDCAL2 10
53902 #define V_FDDCAL2(x) ((x) << S_FDDCAL2)
53903 #define F_FDDCAL2 V_FDDCAL2(1U)
53905 #define S_FDDCFLTR 9
53906 #define V_FDDCFLTR(x) ((x) << S_FDDCFLTR)
53907 #define F_FDDCFLTR V_FDDCFLTR(1U)
53910 #define V_FDAC6(x) ((x) << S_FDAC6)
53911 #define F_FDAC6 V_FDAC6(1U)
53914 #define V_FDDC5(x) ((x) << S_FDDC5)
53915 #define F_FDDC5 V_FDDC5(1U)
53917 #define S_FDDC3456 6
53918 #define V_FDDC3456(x) ((x) << S_FDDC3456)
53919 #define F_FDDC3456 V_FDDC3456(1U)
53921 #define S_FSPY2DATA 5
53922 #define V_FSPY2DATA(x) ((x) << S_FSPY2DATA)
53923 #define F_FSPY2DATA V_FSPY2DATA(1U)
53925 #define S_FPHSLOCK 4
53926 #define V_FPHSLOCK(x) ((x) << S_FPHSLOCK)
53927 #define F_FPHSLOCK V_FPHSLOCK(1U)
53929 #define S_FCLKALGN 3
53930 #define V_FCLKALGN(x) ((x) << S_FCLKALGN)
53931 #define F_FCLKALGN V_FCLKALGN(1U)
53933 #define S_FCLKALDYN 2
53934 #define V_FCLKALDYN(x) ((x) << S_FCLKALDYN)
53935 #define F_FCLKALDYN V_FCLKALDYN(1U)
53938 #define V_FDFE(x) ((x) << S_FDFE)
53939 #define F_FDFE V_FDFE(1U)
53941 #define S_FPRBSOFF 0
53942 #define V_FPRBSOFF(x) ((x) << S_FPRBSOFF)
53943 #define F_FPRBSOFF V_FPRBSOFF(1U)
53945 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
53948 #define M_H_EN 0xfffU
53949 #define V_H_EN(x) ((x) << S_H_EN)
53950 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
53952 #define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
53954 #define S_RX_LINKA_INDEX_DFE_TC 0
53955 #define M_RX_LINKA_INDEX_DFE_TC 0xfU
53956 #define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC)
53957 #define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC)
53959 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
53960 #define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
53962 #define S_RX_LINKA_INDEX_DFE_TAP 0
53963 #define M_RX_LINKA_INDEX_DFE_TAP 0xfU
53964 #define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP)
53965 #define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP)
53967 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
53969 #define S_H2OSN_READWRITE 14
53970 #define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
53971 #define F_H2OSN_READWRITE V_H2OSN_READWRITE(1U)
53973 #define S_H2OSN_READONLY 13
53974 #define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
53975 #define F_H2OSN_READONLY V_H2OSN_READONLY(1U)
53977 #define S_H2ESN_READWRITE 6
53978 #define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
53979 #define F_H2ESN_READWRITE V_H2ESN_READWRITE(1U)
53981 #define S_H2ESN_READONLY 5
53982 #define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
53983 #define F_H2ESN_READONLY V_H2ESN_READONLY(1U)
53985 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
53987 #define S_H3OSN_READWRITE 13
53988 #define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
53989 #define F_H3OSN_READWRITE V_H3OSN_READWRITE(1U)
53991 #define S_H3OSN_READONLY 12
53992 #define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
53993 #define F_H3OSN_READONLY V_H3OSN_READONLY(1U)
53995 #define S_H3ESN_READWRITE 5
53996 #define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
53997 #define F_H3ESN_READWRITE V_H3ESN_READWRITE(1U)
53999 #define S_H3ESN_READONLY 4
54000 #define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
54001 #define F_H3ESN_READONLY V_H3ESN_READONLY(1U)
54003 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
54006 #define M_H4OGS 0x3U
54007 #define V_H4OGS(x) ((x) << S_H4OGS)
54008 #define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
54010 #define S_H4OSN_READWRITE 13
54011 #define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
54012 #define F_H4OSN_READWRITE V_H4OSN_READWRITE(1U)
54014 #define S_H4OSN_READONLY 12
54015 #define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
54016 #define F_H4OSN_READONLY V_H4OSN_READONLY(1U)
54019 #define M_H4EGS 0x3U
54020 #define V_H4EGS(x) ((x) << S_H4EGS)
54021 #define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
54023 #define S_H4ESN_READWRITE 5
54024 #define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
54025 #define F_H4ESN_READWRITE V_H4ESN_READWRITE(1U)
54027 #define S_H4ESN_READONLY 4
54028 #define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
54029 #define F_H4ESN_READONLY V_H4ESN_READONLY(1U)
54031 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
54034 #define M_H5OGS 0x3U
54035 #define V_H5OGS(x) ((x) << S_H5OGS)
54036 #define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
54038 #define S_H5OSN_READWRITE 13
54039 #define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
54040 #define F_H5OSN_READWRITE V_H5OSN_READWRITE(1U)
54042 #define S_H5OSN_READONLY 12
54043 #define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
54044 #define F_H5OSN_READONLY V_H5OSN_READONLY(1U)
54047 #define M_H5EGS 0x3U
54048 #define V_H5EGS(x) ((x) << S_H5EGS)
54049 #define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
54051 #define S_H5ESN_READWRITE 5
54052 #define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
54053 #define F_H5ESN_READWRITE V_H5ESN_READWRITE(1U)
54055 #define S_H5ESN_READONLY 4
54056 #define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
54057 #define F_H5ESN_READONLY V_H5ESN_READONLY(1U)
54059 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
54062 #define M_H7GS 0x3U
54063 #define V_H7GS(x) ((x) << S_H7GS)
54064 #define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
54066 #define S_H7SN_READWRITE 13
54067 #define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
54068 #define F_H7SN_READWRITE V_H7SN_READWRITE(1U)
54070 #define S_H7SN_READONLY 12
54071 #define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
54072 #define F_H7SN_READONLY V_H7SN_READONLY(1U)
54075 #define M_H7MAG 0xfU
54076 #define V_H7MAG(x) ((x) << S_H7MAG)
54077 #define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
54080 #define M_H6GS 0x3U
54081 #define V_H6GS(x) ((x) << S_H6GS)
54082 #define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
54084 #define S_H6SN_READWRITE 5
54085 #define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
54086 #define F_H6SN_READWRITE V_H6SN_READWRITE(1U)
54088 #define S_H6SN_READONLY 4
54089 #define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
54090 #define F_H6SN_READONLY V_H6SN_READONLY(1U)
54093 #define M_H6MAG 0xfU
54094 #define V_H6MAG(x) ((x) << S_H6MAG)
54095 #define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
54097 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
54100 #define M_H9GS 0x3U
54101 #define V_H9GS(x) ((x) << S_H9GS)
54102 #define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
54104 #define S_H9SN_READWRITE 13
54105 #define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
54106 #define F_H9SN_READWRITE V_H9SN_READWRITE(1U)
54108 #define S_H9SN_READONLY 12
54109 #define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
54110 #define F_H9SN_READONLY V_H9SN_READONLY(1U)
54113 #define M_H9MAG 0xfU
54114 #define V_H9MAG(x) ((x) << S_H9MAG)
54115 #define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
54118 #define M_H8GS 0x3U
54119 #define V_H8GS(x) ((x) << S_H8GS)
54120 #define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
54122 #define S_H8SN_READWRITE 5
54123 #define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
54124 #define F_H8SN_READWRITE V_H8SN_READWRITE(1U)
54126 #define S_H8SN_READONLY 4
54127 #define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
54128 #define F_H8SN_READONLY V_H8SN_READONLY(1U)
54131 #define M_H8MAG 0xfU
54132 #define V_H8MAG(x) ((x) << S_H8MAG)
54133 #define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
54135 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
54138 #define M_H11GS 0x3U
54139 #define V_H11GS(x) ((x) << S_H11GS)
54140 #define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
54142 #define S_H11SN_READWRITE 13
54143 #define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
54144 #define F_H11SN_READWRITE V_H11SN_READWRITE(1U)
54146 #define S_H11SN_READONLY 12
54147 #define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
54148 #define F_H11SN_READONLY V_H11SN_READONLY(1U)
54151 #define M_H11MAG 0xfU
54152 #define V_H11MAG(x) ((x) << S_H11MAG)
54153 #define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
54156 #define M_H10GS 0x3U
54157 #define V_H10GS(x) ((x) << S_H10GS)
54158 #define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
54160 #define S_H10SN_READWRITE 5
54161 #define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
54162 #define F_H10SN_READWRITE V_H10SN_READWRITE(1U)
54164 #define S_H10SN_READONLY 4
54165 #define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
54166 #define F_H10SN_READONLY V_H10SN_READONLY(1U)
54169 #define M_H10MAG 0xfU
54170 #define V_H10MAG(x) ((x) << S_H10MAG)
54171 #define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
54173 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
54176 #define M_H12GS 0x3U
54177 #define V_H12GS(x) ((x) << S_H12GS)
54178 #define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
54180 #define S_H12SN_READWRITE 5
54181 #define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
54182 #define F_H12SN_READWRITE V_H12SN_READWRITE(1U)
54184 #define S_H12SN_READONLY 4
54185 #define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
54186 #define F_H12SN_READONLY V_H12SN_READONLY(1U)
54189 #define M_H12MAG 0xfU
54190 #define V_H12MAG(x) ((x) << S_H12MAG)
54191 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
54193 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
54195 #define S_STNDBYSTAT 15
54196 #define V_STNDBYSTAT(x) ((x) << S_STNDBYSTAT)
54197 #define F_STNDBYSTAT V_STNDBYSTAT(1U)
54199 #define S_CALSDONE 14
54200 #define V_CALSDONE(x) ((x) << S_CALSDONE)
54201 #define F_CALSDONE V_CALSDONE(1U)
54203 #define S_ACISRCCMP 5
54204 #define V_ACISRCCMP(x) ((x) << S_ACISRCCMP)
54205 #define F_ACISRCCMP V_ACISRCCMP(1U)
54207 #define S_PRBSOFFCMP 4
54208 #define V_PRBSOFFCMP(x) ((x) << S_PRBSOFFCMP)
54209 #define F_PRBSOFFCMP V_PRBSOFFCMP(1U)
54211 #define S_CLKALGNCMP 3
54212 #define V_CLKALGNCMP(x) ((x) << S_CLKALGNCMP)
54213 #define F_CLKALGNCMP V_CLKALGNCMP(1U)
54215 #define S_ROTFCMP 2
54216 #define V_ROTFCMP(x) ((x) << S_ROTFCMP)
54217 #define F_ROTFCMP V_ROTFCMP(1U)
54220 #define V_DCDCMP(x) ((x) << S_DCDCMP)
54221 #define F_DCDCMP V_DCDCMP(1U)
54224 #define V_QCCCMP(x) ((x) << S_QCCCMP)
54225 #define F_QCCCMP V_QCCCMP(1U)
54227 #define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
54230 #define V_FCSADJ(x) ((x) << S_FCSADJ)
54231 #define F_FCSADJ V_FCSADJ(1U)
54234 #define M_CSIND 0x3U
54235 #define V_CSIND(x) ((x) << S_CSIND)
54236 #define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND)
54239 #define M_CSVAL 0x7U
54240 #define V_CSVAL(x) ((x) << S_CSVAL)
54241 #define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL)
54243 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
54245 #define S_DCDTMDOUT 15
54246 #define V_DCDTMDOUT(x) ((x) << S_DCDTMDOUT)
54247 #define F_DCDTMDOUT V_DCDTMDOUT(1U)
54249 #define S_DCDTOEN 14
54250 #define V_DCDTOEN(x) ((x) << S_DCDTOEN)
54251 #define F_DCDTOEN V_DCDTOEN(1U)
54253 #define S_DCDLOCK 13
54254 #define V_DCDLOCK(x) ((x) << S_DCDLOCK)
54255 #define F_DCDLOCK V_DCDLOCK(1U)
54257 #define S_DCDSTEP 11
54258 #define M_DCDSTEP 0x3U
54259 #define V_DCDSTEP(x) ((x) << S_DCDSTEP)
54260 #define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP)
54262 #define S_DCDALTWPDIS 10
54263 #define V_DCDALTWPDIS(x) ((x) << S_DCDALTWPDIS)
54264 #define F_DCDALTWPDIS V_DCDALTWPDIS(1U)
54266 #define S_DCDOVRDEN 9
54267 #define V_DCDOVRDEN(x) ((x) << S_DCDOVRDEN)
54268 #define F_DCDOVRDEN V_DCDOVRDEN(1U)
54270 #define S_DCCAOVRDEN 8
54271 #define V_DCCAOVRDEN(x) ((x) << S_DCCAOVRDEN)
54272 #define F_DCCAOVRDEN V_DCCAOVRDEN(1U)
54274 #define S_DCDSIGN 6
54275 #define M_DCDSIGN 0x3U
54276 #define V_DCDSIGN(x) ((x) << S_DCDSIGN)
54277 #define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN)
54280 #define M_DCDAMP 0x3fU
54281 #define V_DCDAMP(x) ((x) << S_DCDAMP)
54282 #define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP)
54284 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
54286 #define S_PRBSMODE 14
54287 #define M_PRBSMODE 0x3U
54288 #define V_PRBSMODE(x) ((x) << S_PRBSMODE)
54289 #define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE)
54291 #define S_RX_LINKA_DCCSTEP_RXCTL 10
54292 #define M_RX_LINKA_DCCSTEP_RXCTL 0x3U
54293 #define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL)
54294 #define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL)
54296 #define S_DCCOVRDEN 9
54297 #define V_DCCOVRDEN(x) ((x) << S_DCCOVRDEN)
54298 #define F_DCCOVRDEN V_DCCOVRDEN(1U)
54300 #define S_RX_LINKA_DCCLOCK_RXCTL 8
54301 #define V_RX_LINKA_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKA_DCCLOCK_RXCTL)
54302 #define F_RX_LINKA_DCCLOCK_RXCTL V_RX_LINKA_DCCLOCK_RXCTL(1U)
54304 #define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
54306 #define S_DCCQCCMODE 15
54307 #define V_DCCQCCMODE(x) ((x) << S_DCCQCCMODE)
54308 #define F_DCCQCCMODE V_DCCQCCMODE(1U)
54310 #define S_DCCQCCDYN 14
54311 #define V_DCCQCCDYN(x) ((x) << S_DCCQCCDYN)
54312 #define F_DCCQCCDYN V_DCCQCCDYN(1U)
54314 #define S_DCCQCCHOLD 13
54315 #define V_DCCQCCHOLD(x) ((x) << S_DCCQCCHOLD)
54316 #define F_DCCQCCHOLD V_DCCQCCHOLD(1U)
54318 #define S_QCCSTEP 10
54319 #define M_QCCSTEP 0x3U
54320 #define V_QCCSTEP(x) ((x) << S_QCCSTEP)
54321 #define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP)
54323 #define S_QCCOVRDEN 9
54324 #define V_QCCOVRDEN(x) ((x) << S_QCCOVRDEN)
54325 #define F_QCCOVRDEN V_QCCOVRDEN(1U)
54327 #define S_QCCLOCK 8
54328 #define V_QCCLOCK(x) ((x) << S_QCCLOCK)
54329 #define F_QCCLOCK V_QCCLOCK(1U)
54331 #define S_QCCSIGN 6
54332 #define M_QCCSIGN 0x3U
54333 #define V_QCCSIGN(x) ((x) << S_QCCSIGN)
54334 #define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN)
54337 #define M_QCDAMP 0x3fU
54338 #define V_QCDAMP(x) ((x) << S_QCDAMP)
54339 #define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP)
54341 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
54343 #define S_DFEDACLSSD 6
54344 #define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
54345 #define F_DFEDACLSSD V_DFEDACLSSD(1U)
54348 #define V_SDLSSD(x) ((x) << S_SDLSSD)
54349 #define F_SDLSSD V_SDLSSD(1U)
54351 #define S_DFEOBSBIAS 4
54352 #define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
54353 #define F_DFEOBSBIAS V_DFEOBSBIAS(1U)
54355 #define S_GBOFSTLSSD 3
54356 #define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
54357 #define F_GBOFSTLSSD V_GBOFSTLSSD(1U)
54360 #define V_RXDOBS(x) ((x) << S_RXDOBS)
54361 #define F_RXDOBS V_RXDOBS(1U)
54364 #define V_ACJZPT(x) ((x) << S_ACJZPT)
54365 #define F_ACJZPT V_ACJZPT(1U)
54368 #define V_ACJZNT(x) ((x) << S_ACJZNT)
54369 #define F_ACJZNT V_ACJZNT(1U)
54371 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
54373 #define S_TSTCMP 15
54374 #define V_TSTCMP(x) ((x) << S_TSTCMP)
54375 #define F_TSTCMP V_TSTCMP(1U)
54377 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
54379 #define S_PHSLOCK 10
54380 #define V_PHSLOCK(x) ((x) << S_PHSLOCK)
54381 #define F_PHSLOCK V_PHSLOCK(1U)
54383 #define S_TESTMODE 9
54384 #define V_TESTMODE(x) ((x) << S_TESTMODE)
54385 #define F_TESTMODE V_TESTMODE(1U)
54387 #define S_CALMODE 8
54388 #define V_CALMODE(x) ((x) << S_CALMODE)
54389 #define F_CALMODE V_CALMODE(1U)
54392 #define V_AMPSEL(x) ((x) << S_AMPSEL)
54393 #define F_AMPSEL V_AMPSEL(1U)
54395 #define S_WHICHNRZ 6
54396 #define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
54397 #define F_WHICHNRZ V_WHICHNRZ(1U)
54400 #define V_BANKA(x) ((x) << S_BANKA)
54401 #define F_BANKA V_BANKA(1U)
54404 #define V_BANKB(x) ((x) << S_BANKB)
54405 #define F_BANKB V_BANKB(1U)
54408 #define V_ACJPDP(x) ((x) << S_ACJPDP)
54409 #define F_ACJPDP V_ACJPDP(1U)
54412 #define V_ACJPDN(x) ((x) << S_ACJPDN)
54413 #define F_ACJPDN V_ACJPDN(1U)
54416 #define V_LSSDT(x) ((x) << S_LSSDT)
54417 #define F_LSSDT V_LSSDT(1U)
54420 #define V_MTHOLD(x) ((x) << S_MTHOLD)
54421 #define F_MTHOLD V_MTHOLD(1U)
54423 #define S_CALMODEEDGE 14
54424 #define V_CALMODEEDGE(x) ((x) << S_CALMODEEDGE)
54425 #define F_CALMODEEDGE V_CALMODEEDGE(1U)
54427 #define S_TESTCAP 13
54428 #define V_TESTCAP(x) ((x) << S_TESTCAP)
54429 #define F_TESTCAP V_TESTCAP(1U)
54431 #define S_SNAPEN 12
54432 #define V_SNAPEN(x) ((x) << S_SNAPEN)
54433 #define F_SNAPEN V_SNAPEN(1U)
54435 #define S_ASYNCDIR 11
54436 #define V_ASYNCDIR(x) ((x) << S_ASYNCDIR)
54437 #define F_ASYNCDIR V_ASYNCDIR(1U)
54439 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
54440 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
54441 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
54442 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
54444 #define S_T6_TMSCAL 8
54445 #define M_T6_TMSCAL 0x3U
54446 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
54447 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
54449 #define S_T6_APADJ 7
54450 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
54451 #define F_T6_APADJ V_T6_APADJ(1U)
54453 #define S_T6_RSEL 6
54454 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
54455 #define F_T6_RSEL V_T6_RSEL(1U)
54457 #define S_T6_PHOFFS 0
54458 #define M_T6_PHOFFS 0x3fU
54459 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
54460 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
54462 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
54463 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
54464 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
54465 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
54466 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
54468 #define S_T6_SPIFMT 8
54469 #define M_T6_SPIFMT 0xfU
54470 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
54471 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
54473 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
54474 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
54475 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
54477 #define S_T6_WRAPSEL 15
54478 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
54479 #define F_T6_WRAPSEL V_T6_WRAPSEL(1U)
54481 #define S_T6_PEAK 9
54482 #define M_T6_PEAK 0x1fU
54483 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
54484 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
54486 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
54488 #define S_T6_T5VGAIN 0
54489 #define M_T6_T5VGAIN 0x7fU
54490 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
54491 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
54493 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
54494 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
54495 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
54496 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
54497 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
54498 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
54499 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
54500 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
54501 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
54502 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
54503 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
54504 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
54505 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
54506 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
54507 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
54508 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
54509 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
54510 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
54511 #define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
54512 #define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
54513 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
54514 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
54515 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
54517 #define S_T6_ODEC 0
54518 #define M_T6_ODEC 0xfU
54519 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
54520 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
54522 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
54524 #define S_RX_LINKB_ACCCMP_RIS 11
54525 #define V_RX_LINKB_ACCCMP_RIS(x) ((x) << S_RX_LINKB_ACCCMP_RIS)
54526 #define F_RX_LINKB_ACCCMP_RIS V_RX_LINKB_ACCCMP_RIS(1U)
54528 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
54529 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
54530 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
54531 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
54532 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
54533 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
54534 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
54535 #define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
54536 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
54537 #define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
54539 #define S_RX_LINKB_ACCCMP_BIST 13
54540 #define V_RX_LINKB_ACCCMP_BIST(x) ((x) << S_RX_LINKB_ACCCMP_BIST)
54541 #define F_RX_LINKB_ACCCMP_BIST V_RX_LINKB_ACCCMP_BIST(1U)
54543 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
54544 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
54545 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
54546 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
54547 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
54548 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
54549 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
54550 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
54552 #define S_T6_EMMD 3
54553 #define M_T6_EMMD 0x3U
54554 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
54555 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
54557 #define S_T6_EMBRDY 2
54558 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
54559 #define F_T6_EMBRDY V_T6_EMBRDY(1U)
54561 #define S_T6_EMBUMP 1
54562 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
54563 #define F_T6_EMBUMP V_T6_EMBUMP(1U)
54565 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
54566 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
54567 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
54568 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
54569 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
54570 #define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
54572 #define S_RX_LINKB_INDEX_DFE_TC 0
54573 #define M_RX_LINKB_INDEX_DFE_TC 0xfU
54574 #define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC)
54575 #define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC)
54577 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
54578 #define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
54580 #define S_RX_LINKB_INDEX_DFE_TAP 0
54581 #define M_RX_LINKB_INDEX_DFE_TAP 0xfU
54582 #define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP)
54583 #define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP)
54585 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
54586 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
54587 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
54588 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
54589 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
54590 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
54591 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
54592 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
54593 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
54594 #define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
54595 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
54596 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
54598 #define S_RX_LINKB_DCCSTEP_RXCTL 10
54599 #define M_RX_LINKB_DCCSTEP_RXCTL 0x3U
54600 #define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL)
54601 #define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL)
54603 #define S_RX_LINKB_DCCLOCK_RXCTL 8
54604 #define V_RX_LINKB_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKB_DCCLOCK_RXCTL)
54605 #define F_RX_LINKB_DCCLOCK_RXCTL V_RX_LINKB_DCCLOCK_RXCTL(1U)
54607 #define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
54608 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
54609 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
54610 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
54611 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
54613 #define S_T6_T5_TX_RXLOOP 5
54614 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
54615 #define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U)
54617 #define S_T6_T5_TX_BWSEL 2
54618 #define M_T6_T5_TX_BWSEL 0x3U
54619 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
54620 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
54622 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
54624 #define S_T6_ERROR 9
54625 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
54626 #define F_T6_ERROR V_T6_ERROR(1U)
54628 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
54629 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
54630 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
54631 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
54632 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
54634 #define S_T6_CALSSTN 8
54635 #define M_T6_CALSSTN 0x3fU
54636 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
54637 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
54639 #define S_T6_CALSSTP 0
54640 #define M_T6_CALSSTP 0x3fU
54641 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
54642 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
54644 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
54646 #define S_T6_DRTOL 2
54647 #define M_T6_DRTOL 0x7U
54648 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
54649 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
54651 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
54653 #define S_T6_NXTT0 0
54654 #define M_T6_NXTT0 0x3fU
54655 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
54656 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
54658 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
54659 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
54661 #define S_T6_NXTT2 0
54662 #define M_T6_NXTT2 0x3fU
54663 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
54664 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
54666 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
54667 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
54668 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
54670 #define S_T6_NXTPOL 0
54671 #define M_T6_NXTPOL 0xfU
54672 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
54673 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
54675 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
54677 #define S_T6_C0UPDT 6
54678 #define M_T6_C0UPDT 0x3U
54679 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
54680 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
54682 #define S_T6_C2UPDT 2
54683 #define M_T6_C2UPDT 0x3U
54684 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
54685 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
54687 #define S_T6_C1UPDT 0
54688 #define M_T6_C1UPDT 0x3U
54689 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
54690 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
54692 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
54694 #define S_T6_C0STAT 6
54695 #define M_T6_C0STAT 0x3U
54696 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
54697 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
54699 #define S_T6_C2STAT 2
54700 #define M_T6_C2STAT 0x3U
54701 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
54702 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
54704 #define S_T6_C1STAT 0
54705 #define M_T6_C1STAT 0x3U
54706 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
54707 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
54709 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54710 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54711 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54712 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54713 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54714 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54715 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
54716 #define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
54717 #define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
54718 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
54719 #define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
54720 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
54721 #define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
54722 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
54723 #define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
54724 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
54725 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
54726 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
54727 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
54728 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
54729 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
54730 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
54732 #define S_T6_XADDR 1
54733 #define M_T6_XADDR 0x1fU
54734 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
54735 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
54737 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
54738 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
54739 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
54740 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
54741 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
54742 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
54743 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
54744 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
54745 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
54746 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
54747 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
54749 #define S_T6_DCCTIMEEN 13
54750 #define M_T6_DCCTIMEEN 0x3U
54751 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
54752 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
54754 #define S_T6_DCCLOCK 11
54755 #define M_T6_DCCLOCK 0x3U
54756 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
54757 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
54759 #define S_T6_DCCOFFSET 8
54760 #define M_T6_DCCOFFSET 0x7U
54761 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
54762 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
54764 #define S_TX_LINKC_DCCSTEP_CTL 6
54765 #define M_TX_LINKC_DCCSTEP_CTL 0x3U
54766 #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
54767 #define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL)
54769 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
54770 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
54771 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
54772 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
54773 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
54774 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
54775 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
54776 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
54777 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
54778 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
54779 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
54780 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
54782 #define S_T6_SDOVRD 0
54783 #define M_T6_SDOVRD 0xffffU
54784 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
54785 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
54787 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
54788 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
54789 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
54791 #define S_T6_SDOVRDEN 15
54792 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
54793 #define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U)
54795 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
54797 #define S_T6_T5_TX_RXLOOP 5
54798 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
54799 #define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U)
54801 #define S_T6_T5_TX_BWSEL 2
54802 #define M_T6_T5_TX_BWSEL 0x3U
54803 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
54804 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
54806 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
54808 #define S_T6_ERROR 9
54809 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
54810 #define F_T6_ERROR V_T6_ERROR(1U)
54812 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
54813 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
54814 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
54815 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
54816 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
54818 #define S_T6_CALSSTN 8
54819 #define M_T6_CALSSTN 0x3fU
54820 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
54821 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
54823 #define S_T6_CALSSTP 0
54824 #define M_T6_CALSSTP 0x3fU
54825 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
54826 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
54828 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
54830 #define S_T6_DRTOL 2
54831 #define M_T6_DRTOL 0x7U
54832 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
54833 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
54835 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
54837 #define S_T6_NXTT0 0
54838 #define M_T6_NXTT0 0x3fU
54839 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
54840 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
54842 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
54843 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
54845 #define S_T6_NXTT2 0
54846 #define M_T6_NXTT2 0x3fU
54847 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
54848 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
54850 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
54851 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
54852 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
54854 #define S_T6_NXTPOL 0
54855 #define M_T6_NXTPOL 0xfU
54856 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
54857 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
54859 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
54861 #define S_T6_C0UPDT 6
54862 #define M_T6_C0UPDT 0x3U
54863 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
54864 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
54866 #define S_T6_C2UPDT 2
54867 #define M_T6_C2UPDT 0x3U
54868 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
54869 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
54871 #define S_T6_C1UPDT 0
54872 #define M_T6_C1UPDT 0x3U
54873 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
54874 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
54876 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
54878 #define S_T6_C0STAT 6
54879 #define M_T6_C0STAT 0x3U
54880 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
54881 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
54883 #define S_T6_C2STAT 2
54884 #define M_T6_C2STAT 0x3U
54885 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
54886 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
54888 #define S_T6_C1STAT 0
54889 #define M_T6_C1STAT 0x3U
54890 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
54891 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
54893 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54894 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54895 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54896 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54897 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54898 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54899 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
54900 #define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
54901 #define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
54902 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
54903 #define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
54904 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
54905 #define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
54906 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
54907 #define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
54908 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
54909 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
54910 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
54911 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
54912 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
54913 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
54914 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
54916 #define S_T6_XADDR 1
54917 #define M_T6_XADDR 0x1fU
54918 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
54919 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
54921 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
54922 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
54923 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
54924 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
54925 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
54926 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
54927 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
54928 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
54929 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
54930 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
54931 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
54933 #define S_T6_DCCTIMEEN 13
54934 #define M_T6_DCCTIMEEN 0x3U
54935 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
54936 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
54938 #define S_T6_DCCLOCK 11
54939 #define M_T6_DCCLOCK 0x3U
54940 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
54941 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
54943 #define S_T6_DCCOFFSET 8
54944 #define M_T6_DCCOFFSET 0x7U
54945 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
54946 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
54948 #define S_TX_LINKD_DCCSTEP_CTL 6
54949 #define M_TX_LINKD_DCCSTEP_CTL 0x3U
54950 #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
54951 #define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL)
54953 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
54954 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
54955 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
54956 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
54957 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
54958 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
54959 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
54960 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
54961 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
54962 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
54963 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
54964 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
54966 #define S_T6_SDOVRD 0
54967 #define M_T6_SDOVRD 0xffffU
54968 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
54969 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
54971 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
54972 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
54973 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
54975 #define S_T6_SDOVRDEN 15
54976 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
54977 #define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U)
54979 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
54980 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
54981 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
54982 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
54984 #define S_T6_TMSCAL 8
54985 #define M_T6_TMSCAL 0x3U
54986 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
54987 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
54989 #define S_T6_APADJ 7
54990 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
54991 #define F_T6_APADJ V_T6_APADJ(1U)
54993 #define S_T6_RSEL 6
54994 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
54995 #define F_T6_RSEL V_T6_RSEL(1U)
54997 #define S_T6_PHOFFS 0
54998 #define M_T6_PHOFFS 0x3fU
54999 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55000 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55002 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
55003 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
55004 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
55005 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
55006 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
55008 #define S_T6_SPIFMT 8
55009 #define M_T6_SPIFMT 0xfU
55010 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55011 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55013 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
55014 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
55015 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
55017 #define S_T6_WRAPSEL 15
55018 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55019 #define F_T6_WRAPSEL V_T6_WRAPSEL(1U)
55021 #define S_T6_PEAK 9
55022 #define M_T6_PEAK 0x1fU
55023 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55024 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55026 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
55028 #define S_T6_T5VGAIN 0
55029 #define M_T6_T5VGAIN 0x7fU
55030 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55031 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55033 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
55034 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
55035 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
55036 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
55037 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
55038 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
55039 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
55040 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
55041 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
55042 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
55043 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
55044 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
55045 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
55046 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
55047 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
55048 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
55049 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
55050 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
55051 #define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
55052 #define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
55053 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
55054 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
55055 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
55057 #define S_T6_ODEC 0
55058 #define M_T6_ODEC 0xfU
55059 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55060 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55062 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
55064 #define S_RX_LINKC_ACCCMP_RIS 11
55065 #define V_RX_LINKC_ACCCMP_RIS(x) ((x) << S_RX_LINKC_ACCCMP_RIS)
55066 #define F_RX_LINKC_ACCCMP_RIS V_RX_LINKC_ACCCMP_RIS(1U)
55068 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
55069 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
55070 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
55071 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
55072 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
55073 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
55074 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
55075 #define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
55076 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
55077 #define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
55079 #define S_RX_LINKC_ACCCMP_BIST 13
55080 #define V_RX_LINKC_ACCCMP_BIST(x) ((x) << S_RX_LINKC_ACCCMP_BIST)
55081 #define F_RX_LINKC_ACCCMP_BIST V_RX_LINKC_ACCCMP_BIST(1U)
55083 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
55084 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
55085 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
55086 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
55087 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
55088 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
55089 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
55090 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
55092 #define S_T6_EMMD 3
55093 #define M_T6_EMMD 0x3U
55094 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55095 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55097 #define S_T6_EMBRDY 2
55098 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55099 #define F_T6_EMBRDY V_T6_EMBRDY(1U)
55101 #define S_T6_EMBUMP 1
55102 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55103 #define F_T6_EMBUMP V_T6_EMBUMP(1U)
55105 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
55106 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
55107 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
55108 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
55109 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
55110 #define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
55112 #define S_RX_LINKC_INDEX_DFE_TC 0
55113 #define M_RX_LINKC_INDEX_DFE_TC 0xfU
55114 #define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC)
55115 #define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC)
55117 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
55118 #define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
55120 #define S_RX_LINKC_INDEX_DFE_TAP 0
55121 #define M_RX_LINKC_INDEX_DFE_TAP 0xfU
55122 #define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP)
55123 #define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP)
55125 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
55126 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
55127 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
55128 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
55129 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
55130 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
55131 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
55132 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
55133 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
55134 #define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
55135 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
55136 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
55138 #define S_RX_LINKC_DCCSTEP_RXCTL 10
55139 #define M_RX_LINKC_DCCSTEP_RXCTL 0x3U
55140 #define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL)
55141 #define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL)
55143 #define S_RX_LINKC_DCCLOCK_RXCTL 8
55144 #define V_RX_LINKC_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKC_DCCLOCK_RXCTL)
55145 #define F_RX_LINKC_DCCLOCK_RXCTL V_RX_LINKC_DCCLOCK_RXCTL(1U)
55147 #define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
55148 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
55149 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
55150 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
55151 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
55152 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
55153 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
55154 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
55156 #define S_T6_TMSCAL 8
55157 #define M_T6_TMSCAL 0x3U
55158 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
55159 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
55161 #define S_T6_APADJ 7
55162 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
55163 #define F_T6_APADJ V_T6_APADJ(1U)
55165 #define S_T6_RSEL 6
55166 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
55167 #define F_T6_RSEL V_T6_RSEL(1U)
55169 #define S_T6_PHOFFS 0
55170 #define M_T6_PHOFFS 0x3fU
55171 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55172 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55174 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
55175 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
55176 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
55177 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
55178 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
55180 #define S_T6_SPIFMT 8
55181 #define M_T6_SPIFMT 0xfU
55182 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55183 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55185 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
55186 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
55187 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
55189 #define S_T6_WRAPSEL 15
55190 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55191 #define F_T6_WRAPSEL V_T6_WRAPSEL(1U)
55193 #define S_T6_PEAK 9
55194 #define M_T6_PEAK 0x1fU
55195 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55196 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55198 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
55200 #define S_T6_T5VGAIN 0
55201 #define M_T6_T5VGAIN 0x7fU
55202 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55203 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55205 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
55206 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
55207 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
55208 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
55209 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
55210 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
55211 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
55212 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
55213 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
55214 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
55215 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
55216 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
55217 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
55218 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
55219 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
55220 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
55221 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
55222 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
55223 #define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
55224 #define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
55225 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
55226 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
55227 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
55229 #define S_T6_ODEC 0
55230 #define M_T6_ODEC 0xfU
55231 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55232 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55234 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
55236 #define S_RX_LINKD_ACCCMP_RIS 11
55237 #define V_RX_LINKD_ACCCMP_RIS(x) ((x) << S_RX_LINKD_ACCCMP_RIS)
55238 #define F_RX_LINKD_ACCCMP_RIS V_RX_LINKD_ACCCMP_RIS(1U)
55240 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
55241 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
55242 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
55243 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
55244 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
55245 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
55246 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
55247 #define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
55248 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
55249 #define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
55251 #define S_RX_LINKD_ACCCMP_BIST 13
55252 #define V_RX_LINKD_ACCCMP_BIST(x) ((x) << S_RX_LINKD_ACCCMP_BIST)
55253 #define F_RX_LINKD_ACCCMP_BIST V_RX_LINKD_ACCCMP_BIST(1U)
55255 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
55256 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
55257 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
55258 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
55259 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
55260 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
55261 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
55262 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
55264 #define S_T6_EMMD 3
55265 #define M_T6_EMMD 0x3U
55266 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55267 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55269 #define S_T6_EMBRDY 2
55270 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55271 #define F_T6_EMBRDY V_T6_EMBRDY(1U)
55273 #define S_T6_EMBUMP 1
55274 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55275 #define F_T6_EMBUMP V_T6_EMBUMP(1U)
55277 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
55278 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
55279 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
55280 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
55281 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
55282 #define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
55284 #define S_RX_LINKD_INDEX_DFE_TC 0
55285 #define M_RX_LINKD_INDEX_DFE_TC 0xfU
55286 #define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC)
55287 #define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC)
55289 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
55290 #define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
55292 #define S_RX_LINKD_INDEX_DFE_TAP 0
55293 #define M_RX_LINKD_INDEX_DFE_TAP 0xfU
55294 #define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP)
55295 #define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP)
55297 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
55298 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
55299 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
55300 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
55301 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
55302 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
55303 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
55304 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
55305 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
55306 #define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
55307 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
55308 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
55310 #define S_RX_LINKD_DCCSTEP_RXCTL 10
55311 #define M_RX_LINKD_DCCSTEP_RXCTL 0x3U
55312 #define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL)
55313 #define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL)
55315 #define S_RX_LINKD_DCCLOCK_RXCTL 8
55316 #define V_RX_LINKD_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKD_DCCLOCK_RXCTL)
55317 #define F_RX_LINKD_DCCLOCK_RXCTL V_RX_LINKD_DCCLOCK_RXCTL(1U)
55319 #define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
55320 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
55321 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
55322 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
55323 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
55324 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
55326 #define S_T5BGCTL 0
55327 #define M_T5BGCTL 0xfU
55328 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
55329 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
55331 #define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
55334 #define M_REFSEL 0x7U
55335 #define V_REFSEL(x) ((x) << S_REFSEL)
55336 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
55338 #define A_MAC_PORT_REFISINK_CONTROL 0x3858
55340 #define S_REFISINK 0
55341 #define M_REFISINK 0x3fU
55342 #define V_REFISINK(x) ((x) << S_REFISINK)
55343 #define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK)
55345 #define A_MAC_PORT_REFISRC_CONTROL 0x385c
55347 #define S_REFISRC 0
55348 #define M_REFISRC 0x3fU
55349 #define V_REFISRC(x) ((x) << S_REFISRC)
55350 #define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC)
55352 #define A_MAC_PORT_REFVREG_CONTROL 0x3860
55354 #define S_REFVREG 0
55355 #define M_REFVREG 0x3fU
55356 #define V_REFVREG(x) ((x) << S_REFVREG)
55357 #define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG)
55359 #define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
55361 #define S_BGCLKSEL 2
55362 #define V_BGCLKSEL(x) ((x) << S_BGCLKSEL)
55363 #define F_BGCLKSEL V_BGCLKSEL(1U)
55365 #define S_VBGENDOC 0
55366 #define M_VBGENDOC 0x3U
55367 #define V_VBGENDOC(x) ((x) << S_VBGENDOC)
55368 #define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC)
55370 #define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
55372 #define S_VREFTUNE 0
55373 #define M_VREFTUNE 0xfU
55374 #define V_VREFTUNE(x) ((x) << S_VREFTUNE)
55375 #define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE)
55377 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
55380 #define V_RCCTL1(x) ((x) << S_RCCTL1)
55381 #define F_RCCTL1 V_RCCTL1(1U)
55384 #define V_RCCTL0(x) ((x) << S_RCCTL0)
55385 #define F_RCCTL0 V_RCCTL0(1U)
55388 #define V_RCAMP1(x) ((x) << S_RCAMP1)
55389 #define F_RCAMP1 V_RCAMP1(1U)
55392 #define V_RCAMP0(x) ((x) << S_RCAMP0)
55393 #define F_RCAMP0 V_RCAMP0(1U)
55395 #define S_RCAMPEN 1
55396 #define V_RCAMPEN(x) ((x) << S_RCAMPEN)
55397 #define F_RCAMPEN V_RCAMPEN(1U)
55400 #define V_RCRST(x) ((x) << S_RCRST)
55401 #define F_RCRST V_RCRST(1U)
55403 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
55405 #define S_FRCCAL_COMP 6
55406 #define V_FRCCAL_COMP(x) ((x) << S_FRCCAL_COMP)
55407 #define F_FRCCAL_COMP V_FRCCAL_COMP(1U)
55409 #define S_IC_FRCERR 5
55410 #define V_IC_FRCERR(x) ((x) << S_IC_FRCERR)
55411 #define F_IC_FRCERR V_IC_FRCERR(1U)
55413 #define S_CAL_BISTENAB 4
55414 #define V_CAL_BISTENAB(x) ((x) << S_CAL_BISTENAB)
55415 #define F_CAL_BISTENAB V_CAL_BISTENAB(1U)
55417 #define S_RCAL_RESET 0
55418 #define V_RCAL_RESET(x) ((x) << S_RCAL_RESET)
55419 #define F_RCAL_RESET V_RCAL_RESET(1U)
55421 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
55424 #define V_RCERR(x) ((x) << S_RCERR)
55425 #define F_RCERR V_RCERR(1U)
55428 #define V_RCCOMP(x) ((x) << S_RCCOMP)
55429 #define F_RCCOMP V_RCCOMP(1U)
55431 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
55433 #define S_RCALBENAB 3
55434 #define V_RCALBENAB(x) ((x) << S_RCALBENAB)
55435 #define F_RCALBENAB V_RCALBENAB(1U)
55437 #define S_RCALBUSY 2
55438 #define V_RCALBUSY(x) ((x) << S_RCALBUSY)
55439 #define F_RCALBUSY V_RCALBUSY(1U)
55441 #define S_RCALERR 1
55442 #define V_RCALERR(x) ((x) << S_RCALERR)
55443 #define F_RCALERR V_RCALERR(1U)
55445 #define S_RCALCOMP 0
55446 #define V_RCALCOMP(x) ((x) << S_RCALCOMP)
55447 #define F_RCALCOMP V_RCALCOMP(1U)
55449 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
55451 #define S_RESREG2 0
55452 #define M_RESREG2 0xffU
55453 #define V_RESREG2(x) ((x) << S_RESREG2)
55454 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
55456 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
55458 #define S_T6_RESREG2 0
55459 #define M_T6_RESREG2 0x3fU
55460 #define V_T6_RESREG2(x) ((x) << S_T6_RESREG2)
55461 #define G_T6_RESREG2(x) (((x) >> S_T6_RESREG2) & M_T6_RESREG2)
55463 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
55465 #define S_RESREG3 0
55466 #define M_RESREG3 0xffU
55467 #define V_RESREG3(x) ((x) << S_RESREG3)
55468 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
55470 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
55472 #define S_T6_RESREG3 0
55473 #define M_T6_RESREG3 0x3fU
55474 #define V_T6_RESREG3(x) ((x) << S_T6_RESREG3)
55475 #define G_T6_RESREG3(x) (((x) >> S_T6_RESREG3) & M_T6_RESREG3)
55477 #define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
55480 #define V_ISGT(x) ((x) << S_ISGT)
55481 #define F_ISGT V_ISGT(1U)
55484 #define V_ISLT(x) ((x) << S_ISLT)
55485 #define F_ISLT V_ISLT(1U)
55488 #define V_ISEQ(x) ((x) << S_ISEQ)
55489 #define F_ISEQ V_ISEQ(1U)
55492 #define M_ISVAL 0x3U
55493 #define V_ISVAL(x) ((x) << S_ISVAL)
55494 #define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL)
55497 #define M_GTORLT 0x3U
55498 #define V_GTORLT(x) ((x) << S_GTORLT)
55499 #define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT)
55502 #define V_INEQ(x) ((x) << S_INEQ)
55503 #define F_INEQ V_INEQ(1U)
55505 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
55508 #define M_LLIM 0xffffU
55509 #define V_LLIM(x) ((x) << S_LLIM)
55510 #define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM)
55512 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
55515 #define M_LMSK 0xffffU
55516 #define V_LMSK(x) ((x) << S_LMSK)
55517 #define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK)
55519 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
55522 #define M_HLIM 0xffffU
55523 #define V_HLIM(x) ((x) << S_HLIM)
55524 #define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM)
55526 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
55529 #define M_HMSK 0xffffU
55530 #define V_HMSK(x) ((x) << S_HMSK)
55531 #define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK)
55533 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
55536 #define V_LBIST(x) ((x) << S_LBIST)
55537 #define F_LBIST V_LBIST(1U)
55539 #define S_LOGICTEST 6
55540 #define V_LOGICTEST(x) ((x) << S_LOGICTEST)
55541 #define F_LOGICTEST V_LOGICTEST(1U)
55544 #define V_MAVDHI(x) ((x) << S_MAVDHI)
55545 #define F_MAVDHI V_MAVDHI(1U)
55548 #define V_AUXEN(x) ((x) << S_AUXEN)
55549 #define F_AUXEN V_AUXEN(1U)
55552 #define V_JTAGMD(x) ((x) << S_JTAGMD)
55553 #define F_JTAGMD V_JTAGMD(1U)
55555 #define S_RXACMODE 2
55556 #define V_RXACMODE(x) ((x) << S_RXACMODE)
55557 #define F_RXACMODE V_RXACMODE(1U)
55559 #define S_HSSACJPC 1
55560 #define V_HSSACJPC(x) ((x) << S_HSSACJPC)
55561 #define F_HSSACJPC V_HSSACJPC(1U)
55563 #define S_HSSACJAC 0
55564 #define V_HSSACJAC(x) ((x) << S_HSSACJAC)
55565 #define F_HSSACJAC V_HSSACJAC(1U)
55567 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
55569 #define S_REFVALIDD 6
55570 #define V_REFVALIDD(x) ((x) << S_REFVALIDD)
55571 #define F_REFVALIDD V_REFVALIDD(1U)
55573 #define S_REFVALIDC 5
55574 #define V_REFVALIDC(x) ((x) << S_REFVALIDC)
55575 #define F_REFVALIDC V_REFVALIDC(1U)
55577 #define S_REFVALIDB 4
55578 #define V_REFVALIDB(x) ((x) << S_REFVALIDB)
55579 #define F_REFVALIDB V_REFVALIDB(1U)
55581 #define S_REFVALIDA 3
55582 #define V_REFVALIDA(x) ((x) << S_REFVALIDA)
55583 #define F_REFVALIDA V_REFVALIDA(1U)
55585 #define S_REFSELRESET 2
55586 #define V_REFSELRESET(x) ((x) << S_REFSELRESET)
55587 #define F_REFSELRESET V_REFSELRESET(1U)
55589 #define S_SOFTRESET 1
55590 #define V_SOFTRESET(x) ((x) << S_SOFTRESET)
55591 #define F_SOFTRESET V_SOFTRESET(1U)
55593 #define S_MACROTEST 0
55594 #define V_MACROTEST(x) ((x) << S_MACROTEST)
55595 #define F_MACROTEST V_MACROTEST(1U)
55597 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
55599 #define S_T6_T5_TX_RXLOOP 5
55600 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
55601 #define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U)
55603 #define S_T6_T5_TX_BWSEL 2
55604 #define M_T6_T5_TX_BWSEL 0x3U
55605 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
55606 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
55608 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
55610 #define S_T6_ERROR 9
55611 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
55612 #define F_T6_ERROR V_T6_ERROR(1U)
55614 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
55615 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
55616 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
55617 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
55618 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
55620 #define S_T6_CALSSTN 8
55621 #define M_T6_CALSSTN 0x3fU
55622 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
55623 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
55625 #define S_T6_CALSSTP 0
55626 #define M_T6_CALSSTP 0x3fU
55627 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
55628 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
55630 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
55632 #define S_T6_DRTOL 2
55633 #define M_T6_DRTOL 0x7U
55634 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
55635 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
55637 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
55639 #define S_T6_NXTT0 0
55640 #define M_T6_NXTT0 0x3fU
55641 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
55642 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
55644 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
55645 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
55647 #define S_T6_NXTT2 0
55648 #define M_T6_NXTT2 0x3fU
55649 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
55650 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
55652 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
55653 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
55654 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
55656 #define S_T6_NXTPOL 0
55657 #define M_T6_NXTPOL 0xfU
55658 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
55659 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
55661 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
55663 #define S_T6_C0UPDT 6
55664 #define M_T6_C0UPDT 0x3U
55665 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
55666 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
55668 #define S_T6_C2UPDT 2
55669 #define M_T6_C2UPDT 0x3U
55670 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
55671 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
55673 #define S_T6_C1UPDT 0
55674 #define M_T6_C1UPDT 0x3U
55675 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
55676 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
55678 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
55680 #define S_T6_C0STAT 6
55681 #define M_T6_C0STAT 0x3U
55682 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
55683 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
55685 #define S_T6_C2STAT 2
55686 #define M_T6_C2STAT 0x3U
55687 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
55688 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
55690 #define S_T6_C1STAT 0
55691 #define M_T6_C1STAT 0x3U
55692 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
55693 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
55695 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55696 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55697 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55698 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55699 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55700 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55701 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
55702 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
55703 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
55704 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
55705 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
55706 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
55707 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
55708 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
55709 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
55710 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
55711 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
55712 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
55713 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
55714 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
55715 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
55716 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
55718 #define S_T6_XADDR 1
55719 #define M_T6_XADDR 0x1fU
55720 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
55721 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
55723 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
55724 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
55725 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
55726 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
55727 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
55728 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
55729 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
55730 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
55731 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
55732 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
55733 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
55735 #define S_T6_DCCTIMEEN 13
55736 #define M_T6_DCCTIMEEN 0x3U
55737 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
55738 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
55740 #define S_T6_DCCLOCK 11
55741 #define M_T6_DCCLOCK 0x3U
55742 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
55743 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
55745 #define S_T6_DCCOFFSET 8
55746 #define M_T6_DCCOFFSET 0x7U
55747 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
55748 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
55750 #define S_TX_LINK_BCST_DCCSTEP_CTL 6
55751 #define M_TX_LINK_BCST_DCCSTEP_CTL 0x3U
55752 #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
55753 #define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL)
55755 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
55756 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
55757 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
55758 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
55759 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
55760 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
55761 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
55762 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
55763 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
55764 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
55765 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
55766 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
55768 #define S_T6_SDOVRD 0
55769 #define M_T6_SDOVRD 0xffffU
55770 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
55771 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
55773 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
55774 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
55775 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
55777 #define S_T6_SDOVRDEN 15
55778 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
55779 #define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U)
55781 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
55782 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
55783 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
55784 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
55786 #define S_T6_TMSCAL 8
55787 #define M_T6_TMSCAL 0x3U
55788 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
55789 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
55791 #define S_T6_APADJ 7
55792 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
55793 #define F_T6_APADJ V_T6_APADJ(1U)
55795 #define S_T6_RSEL 6
55796 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
55797 #define F_T6_RSEL V_T6_RSEL(1U)
55799 #define S_T6_PHOFFS 0
55800 #define M_T6_PHOFFS 0x3fU
55801 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55802 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55804 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
55805 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
55806 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
55807 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
55808 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
55810 #define S_T6_SPIFMT 8
55811 #define M_T6_SPIFMT 0xfU
55812 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55813 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55815 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
55816 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
55817 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
55819 #define S_T6_WRAPSEL 15
55820 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55821 #define F_T6_WRAPSEL V_T6_WRAPSEL(1U)
55823 #define S_T6_PEAK 9
55824 #define M_T6_PEAK 0x1fU
55825 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55826 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55828 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
55830 #define S_T6_T5VGAIN 0
55831 #define M_T6_T5VGAIN 0x7fU
55832 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55833 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55835 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
55836 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
55837 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
55838 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
55839 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
55840 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
55841 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
55842 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
55843 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
55844 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
55845 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
55846 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
55847 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
55848 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
55849 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
55850 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
55851 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
55852 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
55853 #define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
55854 #define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
55855 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
55856 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
55857 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
55859 #define S_T6_ODEC 0
55860 #define M_T6_ODEC 0xfU
55861 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55862 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55864 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
55866 #define S_RX_LINK_BCST_ACCCMP_RIS 11
55867 #define V_RX_LINK_BCST_ACCCMP_RIS(x) ((x) << S_RX_LINK_BCST_ACCCMP_RIS)
55868 #define F_RX_LINK_BCST_ACCCMP_RIS V_RX_LINK_BCST_ACCCMP_RIS(1U)
55870 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
55871 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
55872 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
55873 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
55874 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
55875 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
55876 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
55877 #define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
55878 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
55879 #define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
55881 #define S_RX_LINK_BCST_ACCCMP_BIST 13
55882 #define V_RX_LINK_BCST_ACCCMP_BIST(x) ((x) << S_RX_LINK_BCST_ACCCMP_BIST)
55883 #define F_RX_LINK_BCST_ACCCMP_BIST V_RX_LINK_BCST_ACCCMP_BIST(1U)
55885 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
55886 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
55887 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
55888 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
55889 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
55890 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
55891 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
55892 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
55894 #define S_T6_EMMD 3
55895 #define M_T6_EMMD 0x3U
55896 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55897 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55899 #define S_T6_EMBRDY 2
55900 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55901 #define F_T6_EMBRDY V_T6_EMBRDY(1U)
55903 #define S_T6_EMBUMP 1
55904 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55905 #define F_T6_EMBUMP V_T6_EMBUMP(1U)
55907 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
55908 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
55909 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
55910 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
55911 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
55912 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
55914 #define S_RX_LINK_BCST_INDEX_DFE_TC 0
55915 #define M_RX_LINK_BCST_INDEX_DFE_TC 0xfU
55916 #define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC)
55917 #define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC)
55919 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
55920 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
55922 #define S_RX_LINK_BCST_INDEX_DFE_TAP 0
55923 #define M_RX_LINK_BCST_INDEX_DFE_TAP 0xfU
55924 #define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP)
55925 #define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP)
55927 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
55928 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
55929 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
55930 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
55931 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
55932 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
55933 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
55934 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
55935 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
55936 #define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
55937 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
55938 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
55940 #define S_RX_LINK_BCST_DCCSTEP_RXCTL 10
55941 #define M_RX_LINK_BCST_DCCSTEP_RXCTL 0x3U
55942 #define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL)
55943 #define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL)
55945 #define S_RX_LINK_BCST_DCCLOCK_RXCTL 8
55946 #define V_RX_LINK_BCST_DCCLOCK_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCLOCK_RXCTL)
55947 #define F_RX_LINK_BCST_DCCLOCK_RXCTL V_RX_LINK_BCST_DCCLOCK_RXCTL(1U)
55949 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
55950 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
55951 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
55952 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
55953 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
55954 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
55955 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
55956 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
55957 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
55958 #define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
55960 #define S_SPWRENA 1
55961 #define V_SPWRENA(x) ((x) << S_SPWRENA)
55962 #define F_SPWRENA V_SPWRENA(1U)
55964 #define S_NPWRENA 0
55965 #define V_NPWRENA(x) ((x) << S_NPWRENA)
55966 #define F_NPWRENA V_NPWRENA(1U)
55968 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
55970 #define S_T5CPISEL 0
55971 #define M_T5CPISEL 0x7U
55972 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
55973 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
55975 #define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
55976 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
55979 #define M_SPEDIV 0x1fU
55980 #define V_SPEDIV(x) ((x) << S_SPEDIV)
55981 #define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
55984 #define M_PCKSEL 0x7U
55985 #define V_PCKSEL(x) ((x) << S_PCKSEL)
55986 #define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
55988 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
55991 #define V_EMIL(x) ((x) << S_EMIL)
55992 #define F_EMIL V_EMIL(1U)
55995 #define V_EMID(x) ((x) << S_EMID)
55996 #define F_EMID V_EMID(1U)
55999 #define V_EMIS(x) ((x) << S_EMIS)
56000 #define F_EMIS V_EMIS(1U)
56002 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
56005 #define M_EMIL1 0xffU
56006 #define V_EMIL1(x) ((x) << S_EMIL1)
56007 #define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
56009 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
56012 #define M_EMIL2 0xffU
56013 #define V_EMIL2(x) ((x) << S_EMIL2)
56014 #define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
56016 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
56019 #define M_EMIL3 0xffU
56020 #define V_EMIL3(x) ((x) << S_EMIL3)
56021 #define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
56023 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
56026 #define M_EMIL4 0xffU
56027 #define V_EMIL4(x) ((x) << S_EMIL4)
56028 #define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
56030 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
56033 #define M_VBST 0x7U
56034 #define V_VBST(x) ((x) << S_VBST)
56035 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
56037 #define S_PLLDIVA 4
56038 #define V_PLLDIVA(x) ((x) << S_PLLDIVA)
56039 #define F_PLLDIVA V_PLLDIVA(1U)
56042 #define M_REFDIV 0xfU
56043 #define V_REFDIV(x) ((x) << S_REFDIV)
56044 #define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV)
56046 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
56049 #define V_RESYNC(x) ((x) << S_RESYNC)
56050 #define F_RESYNC V_RESYNC(1U)
56052 #define S_RXCLKSEL 5
56053 #define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
56054 #define F_RXCLKSEL V_RXCLKSEL(1U)
56056 #define S_FRCBAND 4
56057 #define V_FRCBAND(x) ((x) << S_FRCBAND)
56058 #define F_FRCBAND V_FRCBAND(1U)
56061 #define V_PLLBYP(x) ((x) << S_PLLBYP)
56062 #define F_PLLBYP V_PLLBYP(1U)
56065 #define V_PDWNP(x) ((x) << S_PDWNP)
56066 #define F_PDWNP V_PDWNP(1U)
56069 #define V_VCOSEL(x) ((x) << S_VCOSEL)
56070 #define F_VCOSEL V_VCOSEL(1U)
56072 #define S_DIVSEL8 0
56073 #define V_DIVSEL8(x) ((x) << S_DIVSEL8)
56074 #define F_DIVSEL8 V_DIVSEL8(1U)
56076 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
56079 #define M_DIVSEL 0xffU
56080 #define V_DIVSEL(x) ((x) << S_DIVSEL)
56081 #define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
56083 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
56086 #define M_CONFIG 0xffU
56087 #define V_CONFIG(x) ((x) << S_CONFIG)
56088 #define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
56090 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
56091 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
56092 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
56093 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
56094 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
56095 #define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
56096 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
56097 #define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
56098 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
56099 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
56100 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
56101 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
56102 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
56103 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
56104 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
56105 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
56106 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
56107 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
56108 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56111 #define M_STEP 0x7U
56112 #define V_STEP(x) ((x) << S_STEP)
56113 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
56115 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56116 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56119 #define M_C0INIT 0x1fU
56120 #define V_C0INIT(x) ((x) << S_C0INIT)
56121 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
56123 #define S_C0PRESET 8
56124 #define M_C0PRESET 0x7fU
56125 #define V_C0PRESET(x) ((x) << S_C0PRESET)
56126 #define G_C0PRESET(x) (((x) >> S_C0PRESET) & M_C0PRESET)
56128 #define S_C0INIT1 0
56129 #define M_C0INIT1 0x7fU
56130 #define V_C0INIT1(x) ((x) << S_C0INIT1)
56131 #define G_C0INIT1(x) (((x) >> S_C0INIT1) & M_C0INIT1)
56133 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56136 #define M_C0MAX 0x1fU
56137 #define V_C0MAX(x) ((x) << S_C0MAX)
56138 #define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
56141 #define M_C0MIN 0x1fU
56142 #define V_C0MIN(x) ((x) << S_C0MIN)
56143 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
56145 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56147 #define S_T6_C0MAX 8
56148 #define M_T6_C0MAX 0x7fU
56149 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56150 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56152 #define S_T6_C0MIN 0
56153 #define M_T6_C0MIN 0x7fU
56154 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56155 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56157 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56160 #define M_C1INIT 0x7fU
56161 #define V_C1INIT(x) ((x) << S_C1INIT)
56162 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
56164 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56166 #define S_C1PRESET 8
56167 #define M_C1PRESET 0x7fU
56168 #define V_C1PRESET(x) ((x) << S_C1PRESET)
56169 #define G_C1PRESET(x) (((x) >> S_C1PRESET) & M_C1PRESET)
56171 #define S_C1INIT1 0
56172 #define M_C1INIT1 0x7fU
56173 #define V_C1INIT1(x) ((x) << S_C1INIT1)
56174 #define G_C1INIT1(x) (((x) >> S_C1INIT1) & M_C1INIT1)
56176 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56179 #define M_C1MAX 0x7fU
56180 #define V_C1MAX(x) ((x) << S_C1MAX)
56181 #define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
56184 #define M_C1MIN 0x7fU
56185 #define V_C1MIN(x) ((x) << S_C1MIN)
56186 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
56188 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56189 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56192 #define M_C2INIT 0x3fU
56193 #define V_C2INIT(x) ((x) << S_C2INIT)
56194 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
56196 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56198 #define S_C2PRESET 8
56199 #define M_C2PRESET 0x7fU
56200 #define V_C2PRESET(x) ((x) << S_C2PRESET)
56201 #define G_C2PRESET(x) (((x) >> S_C2PRESET) & M_C2PRESET)
56203 #define S_C2INIT1 0
56204 #define M_C2INIT1 0x7fU
56205 #define V_C2INIT1(x) ((x) << S_C2INIT1)
56206 #define G_C2INIT1(x) (((x) >> S_C2INIT1) & M_C2INIT1)
56208 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56211 #define M_C2MAX 0x3fU
56212 #define V_C2MAX(x) ((x) << S_C2MAX)
56213 #define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
56216 #define M_C2MIN 0x3fU
56217 #define V_C2MIN(x) ((x) << S_C2MIN)
56218 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
56220 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56222 #define S_T6_C2MAX 8
56223 #define M_T6_C2MAX 0x7fU
56224 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56225 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56227 #define S_T6_C2MIN 0
56228 #define M_T6_C2MIN 0x7fU
56229 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56230 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56232 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56235 #define M_VMMAX 0x7fU
56236 #define V_VMMAX(x) ((x) << S_VMMAX)
56237 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
56239 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56240 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56243 #define M_V2MIN 0x7fU
56244 #define V_V2MIN(x) ((x) << S_V2MIN)
56245 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
56247 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56248 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56250 #define S_C3PRESET 8
56251 #define M_C3PRESET 0x7fU
56252 #define V_C3PRESET(x) ((x) << S_C3PRESET)
56253 #define G_C3PRESET(x) (((x) >> S_C3PRESET) & M_C3PRESET)
56255 #define S_C3INIT1 0
56256 #define M_C3INIT1 0x7fU
56257 #define V_C3INIT1(x) ((x) << S_C3INIT1)
56258 #define G_C3INIT1(x) (((x) >> S_C3INIT1) & M_C3INIT1)
56260 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56263 #define M_C3MAX 0x7fU
56264 #define V_C3MAX(x) ((x) << S_C3MAX)
56265 #define G_C3MAX(x) (((x) >> S_C3MAX) & M_C3MAX)
56268 #define M_C3MIN 0x7fU
56269 #define V_C3MIN(x) ((x) << S_C3MIN)
56270 #define G_C3MIN(x) (((x) >> S_C3MIN) & M_C3MIN)
56272 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56274 #define S_C0INIT2 0
56275 #define M_C0INIT2 0x7fU
56276 #define V_C0INIT2(x) ((x) << S_C0INIT2)
56277 #define G_C0INIT2(x) (((x) >> S_C0INIT2) & M_C0INIT2)
56279 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56281 #define S_C1INIT2 0
56282 #define M_C1INIT2 0x7fU
56283 #define V_C1INIT2(x) ((x) << S_C1INIT2)
56284 #define G_C1INIT2(x) (((x) >> S_C1INIT2) & M_C1INIT2)
56286 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56288 #define S_C2INIT2 0
56289 #define M_C2INIT2 0x7fU
56290 #define V_C2INIT2(x) ((x) << S_C2INIT2)
56291 #define G_C2INIT2(x) (((x) >> S_C2INIT2) & M_C2INIT2)
56293 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56295 #define S_C3INIT2 0
56296 #define M_C3INIT2 0x7fU
56297 #define V_C3INIT2(x) ((x) << S_C3INIT2)
56298 #define G_C3INIT2(x) (((x) >> S_C3INIT2) & M_C3INIT2)
56300 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56301 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56302 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56303 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56304 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56306 #define S_T6_C0MAX 8
56307 #define M_T6_C0MAX 0x7fU
56308 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56309 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56311 #define S_T6_C0MIN 0
56312 #define M_T6_C0MIN 0x7fU
56313 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56314 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56316 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56317 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56318 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56319 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56320 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56321 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56322 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56323 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56325 #define S_T6_C2MAX 8
56326 #define M_T6_C2MAX 0x7fU
56327 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56328 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56330 #define S_T6_C2MIN 0
56331 #define M_T6_C2MIN 0x7fU
56332 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56333 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56335 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56336 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56337 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56338 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56339 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56340 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56341 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56342 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56343 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56344 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56345 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56346 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56347 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56348 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56349 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56351 #define S_T6_C0MAX 8
56352 #define M_T6_C0MAX 0x7fU
56353 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56354 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56356 #define S_T6_C0MIN 0
56357 #define M_T6_C0MIN 0x7fU
56358 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56359 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56361 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56362 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56363 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56364 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56365 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56366 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56367 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56368 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56370 #define S_T6_C2MAX 8
56371 #define M_T6_C2MAX 0x7fU
56372 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56373 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56375 #define S_T6_C2MIN 0
56376 #define M_T6_C2MIN 0x7fU
56377 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56378 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56380 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56381 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56382 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56383 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56384 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56385 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56386 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56387 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56388 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56389 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56390 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56391 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56392 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56393 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56394 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56396 #define S_T6_C0MAX 8
56397 #define M_T6_C0MAX 0x7fU
56398 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56399 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56401 #define S_T6_C0MIN 0
56402 #define M_T6_C0MIN 0x7fU
56403 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56404 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56406 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56407 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56408 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56409 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56410 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56411 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56412 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56413 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56415 #define S_T6_C2MAX 8
56416 #define M_T6_C2MAX 0x7fU
56417 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56418 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56420 #define S_T6_C2MIN 0
56421 #define M_T6_C2MIN 0x7fU
56422 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56423 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56425 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56426 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56427 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56428 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56429 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56430 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56431 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56432 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56433 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56434 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56435 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56436 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56437 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56438 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56439 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56441 #define S_T6_C0MAX 8
56442 #define M_T6_C0MAX 0x7fU
56443 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56444 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56446 #define S_T6_C0MIN 0
56447 #define M_T6_C0MIN 0x7fU
56448 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56449 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56451 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56452 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56453 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56454 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56455 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56456 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56457 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56458 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56460 #define S_T6_C2MAX 8
56461 #define M_T6_C2MAX 0x7fU
56462 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56463 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56465 #define S_T6_C2MIN 0
56466 #define M_T6_C2MIN 0x7fU
56467 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56468 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56470 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56471 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56472 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56473 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56474 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56475 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56476 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56477 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56478 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56479 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56480 #define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
56482 #define S_RX_LINKA_INDEX_DFE_EN 1
56483 #define M_RX_LINKA_INDEX_DFE_EN 0x7fffU
56484 #define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN)
56485 #define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN)
56487 #define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
56489 #define S_T6_H1OSN 13
56490 #define M_T6_H1OSN 0x7U
56491 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56492 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56494 #define S_T6_H1OMAG 8
56495 #define M_T6_H1OMAG 0x1fU
56496 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56497 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56499 #define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
56500 #define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
56501 #define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
56504 #define M_H4SN 0x3U
56505 #define V_H4SN(x) ((x) << S_H4SN)
56506 #define G_H4SN(x) (((x) >> S_H4SN) & M_H4SN)
56509 #define M_H4MAG 0xfU
56510 #define V_H4MAG(x) ((x) << S_H4MAG)
56511 #define G_H4MAG(x) (((x) >> S_H4MAG) & M_H4MAG)
56513 #define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
56516 #define M_H5GS 0x3U
56517 #define V_H5GS(x) ((x) << S_H5GS)
56518 #define G_H5GS(x) (((x) >> S_H5GS) & M_H5GS)
56521 #define M_H5SN 0x3U
56522 #define V_H5SN(x) ((x) << S_H5SN)
56523 #define G_H5SN(x) (((x) >> S_H5SN) & M_H5SN)
56526 #define M_H5MAG 0xfU
56527 #define V_H5MAG(x) ((x) << S_H5MAG)
56528 #define G_H5MAG(x) (((x) >> S_H5MAG) & M_H5MAG)
56530 #define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
56533 #define M_H7SN 0x3U
56534 #define V_H7SN(x) ((x) << S_H7SN)
56535 #define G_H7SN(x) (((x) >> S_H7SN) & M_H7SN)
56538 #define M_H6SN 0x3U
56539 #define V_H6SN(x) ((x) << S_H6SN)
56540 #define G_H6SN(x) (((x) >> S_H6SN) & M_H6SN)
56542 #define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
56545 #define M_H9SN 0x3U
56546 #define V_H9SN(x) ((x) << S_H9SN)
56547 #define G_H9SN(x) (((x) >> S_H9SN) & M_H9SN)
56550 #define M_H8SN 0x3U
56551 #define V_H8SN(x) ((x) << S_H8SN)
56552 #define G_H8SN(x) (((x) >> S_H8SN) & M_H8SN)
56554 #define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
56557 #define M_H11SN 0x3U
56558 #define V_H11SN(x) ((x) << S_H11SN)
56559 #define G_H11SN(x) (((x) >> S_H11SN) & M_H11SN)
56562 #define M_H10SN 0x3U
56563 #define V_H10SN(x) ((x) << S_H10SN)
56564 #define G_H10SN(x) (((x) >> S_H10SN) & M_H10SN)
56566 #define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
56569 #define M_H13GS 0x7U
56570 #define V_H13GS(x) ((x) << S_H13GS)
56571 #define G_H13GS(x) (((x) >> S_H13GS) & M_H13GS)
56574 #define M_H13SN 0x7U
56575 #define V_H13SN(x) ((x) << S_H13SN)
56576 #define G_H13SN(x) (((x) >> S_H13SN) & M_H13SN)
56579 #define M_H13MAG 0x3U
56580 #define V_H13MAG(x) ((x) << S_H13MAG)
56581 #define G_H13MAG(x) (((x) >> S_H13MAG) & M_H13MAG)
56584 #define M_H12SN 0x3U
56585 #define V_H12SN(x) ((x) << S_H12SN)
56586 #define G_H12SN(x) (((x) >> S_H12SN) & M_H12SN)
56588 #define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
56591 #define M_H15GS 0x7U
56592 #define V_H15GS(x) ((x) << S_H15GS)
56593 #define G_H15GS(x) (((x) >> S_H15GS) & M_H15GS)
56596 #define M_H15SN 0x7U
56597 #define V_H15SN(x) ((x) << S_H15SN)
56598 #define G_H15SN(x) (((x) >> S_H15SN) & M_H15SN)
56601 #define M_H15MAG 0x3U
56602 #define V_H15MAG(x) ((x) << S_H15MAG)
56603 #define G_H15MAG(x) (((x) >> S_H15MAG) & M_H15MAG)
56606 #define M_H14GS 0x3U
56607 #define V_H14GS(x) ((x) << S_H14GS)
56608 #define G_H14GS(x) (((x) >> S_H14GS) & M_H14GS)
56611 #define M_H14SN 0x3U
56612 #define V_H14SN(x) ((x) << S_H14SN)
56613 #define G_H14SN(x) (((x) >> S_H14SN) & M_H14SN)
56616 #define M_H14MAG 0xfU
56617 #define V_H14MAG(x) ((x) << S_H14MAG)
56618 #define G_H14MAG(x) (((x) >> S_H14MAG) & M_H14MAG)
56620 #define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
56622 #define S_H1ODELTA 8
56623 #define M_H1ODELTA 0x1fU
56624 #define V_H1ODELTA(x) ((x) << S_H1ODELTA)
56625 #define G_H1ODELTA(x) (((x) >> S_H1ODELTA) & M_H1ODELTA)
56627 #define S_H1EDELTA 0
56628 #define M_H1EDELTA 0x3fU
56629 #define V_H1EDELTA(x) ((x) << S_H1EDELTA)
56630 #define G_H1EDELTA(x) (((x) >> S_H1EDELTA) & M_H1EDELTA)
56632 #define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
56634 #define S_RX_LINKB_INDEX_DFE_EN 1
56635 #define M_RX_LINKB_INDEX_DFE_EN 0x7fffU
56636 #define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN)
56637 #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
56639 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
56641 #define S_T6_H1OSN 13
56642 #define M_T6_H1OSN 0x7U
56643 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56644 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56646 #define S_T6_H1OMAG 8
56647 #define M_T6_H1OMAG 0x1fU
56648 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56649 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56651 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
56652 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
56653 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
56654 #define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
56655 #define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
56656 #define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
56657 #define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
56658 #define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
56659 #define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
56660 #define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
56661 #define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
56663 #define S_RX_LINKC_INDEX_DFE_EN 1
56664 #define M_RX_LINKC_INDEX_DFE_EN 0x7fffU
56665 #define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN)
56666 #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
56668 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
56670 #define S_T6_H1OSN 13
56671 #define M_T6_H1OSN 0x7U
56672 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56673 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56675 #define S_T6_H1OMAG 8
56676 #define M_T6_H1OMAG 0x1fU
56677 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56678 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56680 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
56681 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
56682 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
56683 #define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
56684 #define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
56685 #define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
56686 #define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
56687 #define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
56688 #define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
56689 #define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
56690 #define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
56692 #define S_RX_LINKD_INDEX_DFE_EN 1
56693 #define M_RX_LINKD_INDEX_DFE_EN 0x7fffU
56694 #define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN)
56695 #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
56697 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
56699 #define S_T6_H1OSN 13
56700 #define M_T6_H1OSN 0x7U
56701 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56702 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56704 #define S_T6_H1OMAG 8
56705 #define M_T6_H1OMAG 0x1fU
56706 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56707 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56709 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
56710 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
56711 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
56712 #define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
56713 #define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
56714 #define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
56715 #define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
56716 #define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
56717 #define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
56718 #define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
56719 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
56721 #define S_RX_LINK_BCST_INDEX_DFE_EN 1
56722 #define M_RX_LINK_BCST_INDEX_DFE_EN 0x7fffU
56723 #define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN)
56724 #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
56726 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
56728 #define S_T6_H1OSN 13
56729 #define M_T6_H1OSN 0x7U
56730 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56731 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56733 #define S_T6_H1OMAG 8
56734 #define M_T6_H1OMAG 0x1fU
56735 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56736 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56738 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
56739 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
56740 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
56741 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
56742 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
56743 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
56744 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
56745 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
56746 #define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
56747 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
56749 /* registers for module MC_0 */
56750 #define MC_0_BASE_ADDR 0x40000
56752 #define A_MC_UPCTL_SCFG 0x40000
56754 #define S_BBFLAGS_TIMING 8
56755 #define M_BBFLAGS_TIMING 0xfU
56756 #define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
56757 #define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
56759 #define S_NFIFO_NIF1_DIS 6
56760 #define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
56761 #define F_NFIFO_NIF1_DIS V_NFIFO_NIF1_DIS(1U)
56763 #define A_MC_UPCTL_SCTL 0x40004
56764 #define A_MC_UPCTL_STAT 0x40008
56766 #define S_LP_TRIG 4
56767 #define M_LP_TRIG 0x7U
56768 #define V_LP_TRIG(x) ((x) << S_LP_TRIG)
56769 #define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
56771 #define A_MC_UPCTL_INTRSTAT 0x4000c
56773 #define S_PARITY_INTR 1
56774 #define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
56775 #define F_PARITY_INTR V_PARITY_INTR(1U)
56777 #define S_ECC_INTR 0
56778 #define V_ECC_INTR(x) ((x) << S_ECC_INTR)
56779 #define F_ECC_INTR V_ECC_INTR(1U)
56781 #define A_MC_UPCTL_MCMD 0x40040
56783 #define S_CMD_OPCODE0 0
56784 #define M_CMD_OPCODE0 0xfU
56785 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
56786 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
56788 #define A_MC_LMC_MCSTAT 0x40040
56790 #define S_INIT_COMPLETE 31
56791 #define V_INIT_COMPLETE(x) ((x) << S_INIT_COMPLETE)
56792 #define F_INIT_COMPLETE V_INIT_COMPLETE(1U)
56794 #define S_SELF_REF_MODE 30
56795 #define V_SELF_REF_MODE(x) ((x) << S_SELF_REF_MODE)
56796 #define F_SELF_REF_MODE V_SELF_REF_MODE(1U)
56799 #define V_IDLE(x) ((x) << S_IDLE)
56800 #define F_IDLE V_IDLE(1U)
56802 #define S_T6_DFI_INIT_COMPLETE 28
56803 #define V_T6_DFI_INIT_COMPLETE(x) ((x) << S_T6_DFI_INIT_COMPLETE)
56804 #define F_T6_DFI_INIT_COMPLETE V_T6_DFI_INIT_COMPLETE(1U)
56806 #define S_PREFILL_COMPLETE 27
56807 #define V_PREFILL_COMPLETE(x) ((x) << S_PREFILL_COMPLETE)
56808 #define F_PREFILL_COMPLETE V_PREFILL_COMPLETE(1U)
56810 #define A_MC_UPCTL_POWCTL 0x40044
56811 #define A_MC_UPCTL_POWSTAT 0x40048
56812 #define A_MC_UPCTL_CMDTSTAT 0x4004c
56814 #define S_CMD_TSTAT 0
56815 #define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
56816 #define F_CMD_TSTAT V_CMD_TSTAT(1U)
56818 #define A_MC_UPCTL_CMDTSTATEN 0x40050
56820 #define S_CMD_TSTAT_EN 0
56821 #define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
56822 #define F_CMD_TSTAT_EN V_CMD_TSTAT_EN(1U)
56824 #define A_MC_UPCTL_MRRCFG0 0x40060
56826 #define S_MRR_BYTE_SEL 0
56827 #define M_MRR_BYTE_SEL 0xfU
56828 #define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
56829 #define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
56831 #define A_MC_UPCTL_MRRSTAT0 0x40064
56833 #define S_MRRSTAT_BEAT3 24
56834 #define M_MRRSTAT_BEAT3 0xffU
56835 #define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
56836 #define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
56838 #define S_MRRSTAT_BEAT2 16
56839 #define M_MRRSTAT_BEAT2 0xffU
56840 #define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
56841 #define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
56843 #define S_MRRSTAT_BEAT1 8
56844 #define M_MRRSTAT_BEAT1 0xffU
56845 #define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
56846 #define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
56848 #define S_MRRSTAT_BEAT0 0
56849 #define M_MRRSTAT_BEAT0 0xffU
56850 #define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
56851 #define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
56853 #define A_MC_UPCTL_MRRSTAT1 0x40068
56855 #define S_MRRSTAT_BEAT7 24
56856 #define M_MRRSTAT_BEAT7 0xffU
56857 #define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
56858 #define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
56860 #define S_MRRSTAT_BEAT6 16
56861 #define M_MRRSTAT_BEAT6 0xffU
56862 #define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
56863 #define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
56865 #define S_MRRSTAT_BEAT5 8
56866 #define M_MRRSTAT_BEAT5 0xffU
56867 #define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
56868 #define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
56870 #define S_MRRSTAT_BEAT4 0
56871 #define M_MRRSTAT_BEAT4 0xffU
56872 #define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
56873 #define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
56875 #define A_MC_UPCTL_MCFG1 0x4007c
56877 #define S_HW_EXIT_IDLE_EN 31
56878 #define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
56879 #define F_HW_EXIT_IDLE_EN V_HW_EXIT_IDLE_EN(1U)
56881 #define S_HW_IDLE 16
56882 #define M_HW_IDLE 0xffU
56883 #define V_HW_IDLE(x) ((x) << S_HW_IDLE)
56884 #define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
56886 #define S_SR_IDLE 0
56887 #define M_SR_IDLE 0xffU
56888 #define V_SR_IDLE(x) ((x) << S_SR_IDLE)
56889 #define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
56891 #define A_MC_UPCTL_MCFG 0x40080
56893 #define S_MDDR_LPDDR2_CLK_STOP_IDLE 24
56894 #define M_MDDR_LPDDR2_CLK_STOP_IDLE 0xffU
56895 #define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
56896 #define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
56898 #define S_MDDR_LPDDR2_EN 22
56899 #define M_MDDR_LPDDR2_EN 0x3U
56900 #define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
56901 #define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
56903 #define S_MDDR_LPDDR2_BL 20
56904 #define M_MDDR_LPDDR2_BL 0x3U
56905 #define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
56906 #define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
56908 #define S_LPDDR2_S4 6
56909 #define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
56910 #define F_LPDDR2_S4 V_LPDDR2_S4(1U)
56912 #define S_STAGGER_CS 4
56913 #define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
56914 #define F_STAGGER_CS V_STAGGER_CS(1U)
56916 #define S_CKE_OR_EN 1
56917 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
56918 #define F_CKE_OR_EN V_CKE_OR_EN(1U)
56920 #define A_MC_LMC_MCOPT1 0x40080
56922 #define S_MC_PROTOCOL 31
56923 #define V_MC_PROTOCOL(x) ((x) << S_MC_PROTOCOL)
56924 #define F_MC_PROTOCOL V_MC_PROTOCOL(1U)
56926 #define S_DM_ENABLE 30
56927 #define V_DM_ENABLE(x) ((x) << S_DM_ENABLE)
56928 #define F_DM_ENABLE V_DM_ENABLE(1U)
56930 #define S_T6_ECC_EN 29
56931 #define V_T6_ECC_EN(x) ((x) << S_T6_ECC_EN)
56932 #define F_T6_ECC_EN V_T6_ECC_EN(1U)
56934 #define S_ECC_COR 28
56935 #define V_ECC_COR(x) ((x) << S_ECC_COR)
56936 #define F_ECC_COR V_ECC_COR(1U)
56939 #define V_RDIMM(x) ((x) << S_RDIMM)
56940 #define F_RDIMM V_RDIMM(1U)
56943 #define M_PMUM 0x3U
56944 #define V_PMUM(x) ((x) << S_PMUM)
56945 #define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM)
56947 #define S_WIDTH0 24
56948 #define V_WIDTH0(x) ((x) << S_WIDTH0)
56949 #define F_WIDTH0 V_WIDTH0(1U)
56951 #define S_PORT_ID_CHK_EN 23
56952 #define V_PORT_ID_CHK_EN(x) ((x) << S_PORT_ID_CHK_EN)
56953 #define F_PORT_ID_CHK_EN V_PORT_ID_CHK_EN(1U)
56956 #define V_UIOS(x) ((x) << S_UIOS)
56957 #define F_UIOS V_UIOS(1U)
56959 #define S_QUADCS_RDIMM 21
56960 #define V_QUADCS_RDIMM(x) ((x) << S_QUADCS_RDIMM)
56961 #define F_QUADCS_RDIMM V_QUADCS_RDIMM(1U)
56963 #define S_ZQCL_EN 20
56964 #define V_ZQCL_EN(x) ((x) << S_ZQCL_EN)
56965 #define F_ZQCL_EN V_ZQCL_EN(1U)
56967 #define S_WIDTH1 19
56968 #define V_WIDTH1(x) ((x) << S_WIDTH1)
56969 #define F_WIDTH1 V_WIDTH1(1U)
56971 #define S_WD_DLY 18
56972 #define V_WD_DLY(x) ((x) << S_WD_DLY)
56973 #define F_WD_DLY V_WD_DLY(1U)
56975 #define S_QDEPTH 16
56976 #define M_QDEPTH 0x3U
56977 #define V_QDEPTH(x) ((x) << S_QDEPTH)
56978 #define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH)
56981 #define V_RWOO(x) ((x) << S_RWOO)
56982 #define F_RWOO V_RWOO(1U)
56985 #define V_WOOO(x) ((x) << S_WOOO)
56986 #define F_WOOO V_WOOO(1U)
56989 #define V_DCOO(x) ((x) << S_DCOO)
56990 #define F_DCOO V_DCOO(1U)
56992 #define S_DEF_REF 12
56993 #define V_DEF_REF(x) ((x) << S_DEF_REF)
56994 #define F_DEF_REF V_DEF_REF(1U)
56996 #define S_DEV_TYPE 11
56997 #define V_DEV_TYPE(x) ((x) << S_DEV_TYPE)
56998 #define F_DEV_TYPE V_DEV_TYPE(1U)
57000 #define S_CA_PTY_DLY 10
57001 #define V_CA_PTY_DLY(x) ((x) << S_CA_PTY_DLY)
57002 #define F_CA_PTY_DLY V_CA_PTY_DLY(1U)
57004 #define S_ECC_MUX 8
57005 #define M_ECC_MUX 0x3U
57006 #define V_ECC_MUX(x) ((x) << S_ECC_MUX)
57007 #define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX)
57009 #define S_CE_THRESHOLD 0
57010 #define M_CE_THRESHOLD 0xffU
57011 #define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD)
57012 #define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD)
57014 #define A_MC_UPCTL_PPCFG 0x40084
57015 #define A_MC_LMC_MCOPT2 0x40084
57017 #define S_SELF_REF_EN 31
57018 #define V_SELF_REF_EN(x) ((x) << S_SELF_REF_EN)
57019 #define F_SELF_REF_EN V_SELF_REF_EN(1U)
57021 #define S_XSR_PREVENT 30
57022 #define V_XSR_PREVENT(x) ((x) << S_XSR_PREVENT)
57023 #define F_XSR_PREVENT V_XSR_PREVENT(1U)
57025 #define S_INIT_START 29
57026 #define V_INIT_START(x) ((x) << S_INIT_START)
57027 #define F_INIT_START V_INIT_START(1U)
57029 #define S_MC_ENABLE 28
57030 #define V_MC_ENABLE(x) ((x) << S_MC_ENABLE)
57031 #define F_MC_ENABLE V_MC_ENABLE(1U)
57033 #define S_CLK_DISABLE 24
57034 #define M_CLK_DISABLE 0xfU
57035 #define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE)
57036 #define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE)
57038 #define S_RESET_RANK 20
57039 #define M_RESET_RANK 0xfU
57040 #define V_RESET_RANK(x) ((x) << S_RESET_RANK)
57041 #define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK)
57043 #define S_MCIF_COMP_PTY_EN 19
57044 #define V_MCIF_COMP_PTY_EN(x) ((x) << S_MCIF_COMP_PTY_EN)
57045 #define F_MCIF_COMP_PTY_EN V_MCIF_COMP_PTY_EN(1U)
57047 #define S_CKE_OE 17
57048 #define V_CKE_OE(x) ((x) << S_CKE_OE)
57049 #define F_CKE_OE V_CKE_OE(1U)
57051 #define S_RESET_OE 16
57052 #define V_RESET_OE(x) ((x) << S_RESET_OE)
57053 #define F_RESET_OE V_RESET_OE(1U)
57055 #define S_DFI_PHYUD_CNTL 14
57056 #define V_DFI_PHYUD_CNTL(x) ((x) << S_DFI_PHYUD_CNTL)
57057 #define F_DFI_PHYUD_CNTL V_DFI_PHYUD_CNTL(1U)
57059 #define S_DFI_PHYUD_ACK 13
57060 #define V_DFI_PHYUD_ACK(x) ((x) << S_DFI_PHYUD_ACK)
57061 #define F_DFI_PHYUD_ACK V_DFI_PHYUD_ACK(1U)
57063 #define S_T6_DFI_INIT_START 12
57064 #define V_T6_DFI_INIT_START(x) ((x) << S_T6_DFI_INIT_START)
57065 #define F_T6_DFI_INIT_START V_T6_DFI_INIT_START(1U)
57067 #define S_PM_ENABLE 8
57068 #define M_PM_ENABLE 0xfU
57069 #define V_PM_ENABLE(x) ((x) << S_PM_ENABLE)
57070 #define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE)
57072 #define S_RD_DEFREF_CNT 4
57073 #define M_RD_DEFREF_CNT 0xfU
57074 #define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT)
57075 #define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT)
57077 #define A_MC_UPCTL_MSTAT 0x40088
57079 #define S_SELF_REFRESH 2
57080 #define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
57081 #define F_SELF_REFRESH V_SELF_REFRESH(1U)
57083 #define S_CLOCK_STOP 1
57084 #define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
57085 #define F_CLOCK_STOP V_CLOCK_STOP(1U)
57087 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
57089 #define S_ZQCL_OP 24
57090 #define M_ZQCL_OP 0xffU
57091 #define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
57092 #define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
57094 #define S_ZQCL_MA 16
57095 #define M_ZQCL_MA 0xffU
57096 #define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
57097 #define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
57099 #define S_ZQCS_OP 8
57100 #define M_ZQCS_OP 0xffU
57101 #define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
57102 #define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
57104 #define S_ZQCS_MA 0
57105 #define M_ZQCS_MA 0xffU
57106 #define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
57107 #define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
57109 #define A_MC_UPCTL_DTUPDES 0x40094
57111 #define S_DTU_ERR_B7 7
57112 #define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
57113 #define F_DTU_ERR_B7 V_DTU_ERR_B7(1U)
57115 #define A_MC_UPCTL_DTUNA 0x40098
57116 #define A_MC_UPCTL_DTUNE 0x4009c
57117 #define A_MC_UPCTL_DTUPRD0 0x400a0
57118 #define A_MC_UPCTL_DTUPRD1 0x400a4
57119 #define A_MC_UPCTL_DTUPRD2 0x400a8
57120 #define A_MC_UPCTL_DTUPRD3 0x400ac
57121 #define A_MC_UPCTL_DTUAWDT 0x400b0
57122 #define A_MC_UPCTL_TOGCNT1U 0x400c0
57123 #define A_MC_UPCTL_TINIT 0x400c4
57124 #define A_MC_UPCTL_TRSTH 0x400c8
57125 #define A_MC_UPCTL_TOGCNT100N 0x400cc
57126 #define A_MC_UPCTL_TREFI 0x400d0
57127 #define A_MC_UPCTL_TMRD 0x400d4
57128 #define A_MC_UPCTL_TRFC 0x400d8
57131 #define M_T_RFC0 0x1ffU
57132 #define V_T_RFC0(x) ((x) << S_T_RFC0)
57133 #define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
57135 #define A_MC_UPCTL_TRP 0x400dc
57137 #define S_PREA_EXTRA 16
57138 #define M_PREA_EXTRA 0x3U
57139 #define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
57140 #define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
57142 #define A_MC_UPCTL_TRTW 0x400e0
57145 #define M_T_RTW0 0xfU
57146 #define V_T_RTW0(x) ((x) << S_T_RTW0)
57147 #define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
57149 #define A_MC_UPCTL_TAL 0x400e4
57150 #define A_MC_UPCTL_TCL 0x400e8
57151 #define A_MC_UPCTL_TCWL 0x400ec
57152 #define A_MC_UPCTL_TRAS 0x400f0
57153 #define A_MC_UPCTL_TRC 0x400f4
57154 #define A_MC_UPCTL_TRCD 0x400f8
57155 #define A_MC_UPCTL_TRRD 0x400fc
57156 #define A_MC_UPCTL_TRTP 0x40100
57159 #define M_T_RTP0 0xfU
57160 #define V_T_RTP0(x) ((x) << S_T_RTP0)
57161 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
57163 #define A_MC_LMC_CFGR0 0x40100
57165 #define S_ROW_WIDTH 12
57166 #define M_ROW_WIDTH 0x7U
57167 #define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH)
57168 #define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH)
57170 #define S_ADDR_MODE 8
57171 #define M_ADDR_MODE 0xfU
57172 #define V_ADDR_MODE(x) ((x) << S_ADDR_MODE)
57173 #define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE)
57176 #define V_MIRROR(x) ((x) << S_MIRROR)
57177 #define F_MIRROR V_MIRROR(1U)
57179 #define S_RANK_ENABLE 0
57180 #define V_RANK_ENABLE(x) ((x) << S_RANK_ENABLE)
57181 #define F_RANK_ENABLE V_RANK_ENABLE(1U)
57183 #define A_MC_UPCTL_TWR 0x40104
57186 #define M_U_T_WR 0x1fU
57187 #define V_U_T_WR(x) ((x) << S_U_T_WR)
57188 #define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
57190 #define A_MC_UPCTL_TWTR 0x40108
57193 #define M_T_WTR0 0xfU
57194 #define V_T_WTR0(x) ((x) << S_T_WTR0)
57195 #define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
57197 #define A_MC_UPCTL_TEXSR 0x4010c
57198 #define A_MC_UPCTL_TXP 0x40110
57199 #define A_MC_UPCTL_TXPDLL 0x40114
57200 #define A_MC_UPCTL_TZQCS 0x40118
57201 #define A_MC_UPCTL_TZQCSI 0x4011c
57202 #define A_MC_UPCTL_TDQS 0x40120
57203 #define A_MC_UPCTL_TCKSRE 0x40124
57205 #define S_T_CKSRE0 0
57206 #define M_T_CKSRE0 0x1fU
57207 #define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
57208 #define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
57210 #define A_MC_UPCTL_TCKSRX 0x40128
57212 #define S_T_CKSRX0 0
57213 #define M_T_CKSRX0 0x1fU
57214 #define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
57215 #define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
57217 #define A_MC_UPCTL_TCKE 0x4012c
57218 #define A_MC_UPCTL_TMOD 0x40130
57221 #define M_T_MOD0 0x1fU
57222 #define V_T_MOD0(x) ((x) << S_T_MOD0)
57223 #define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
57225 #define A_MC_UPCTL_TRSTL 0x40134
57228 #define M_T_RSTL 0x7fU
57229 #define V_T_RSTL(x) ((x) << S_T_RSTL)
57230 #define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
57232 #define A_MC_UPCTL_TZQCL 0x40138
57233 #define A_MC_UPCTL_TMRR 0x4013c
57236 #define M_T_MRR 0xffU
57237 #define V_T_MRR(x) ((x) << S_T_MRR)
57238 #define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
57240 #define A_MC_UPCTL_TCKESR 0x40140
57242 #define S_T_CKESR 0
57243 #define M_T_CKESR 0xfU
57244 #define V_T_CKESR(x) ((x) << S_T_CKESR)
57245 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
57247 #define A_MC_LMC_INITSEQ0 0x40140
57249 #define S_INIT_ENABLE 31
57250 #define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
57251 #define F_INIT_ENABLE V_INIT_ENABLE(1U)
57254 #define M_WAIT 0xfffU
57255 #define CXGBE_V_WAIT(x) ((x) << S_WAIT)
57256 #define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
57258 #define S_EN_MULTI_RANK_SEL 4
57259 #define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
57260 #define F_EN_MULTI_RANK_SEL V_EN_MULTI_RANK_SEL(1U)
57262 #define S_T6_RANK 0
57263 #define M_T6_RANK 0xfU
57264 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57265 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57267 #define A_MC_UPCTL_TDPD 0x40144
57270 #define M_T_DPD 0x3ffU
57271 #define V_T_DPD(x) ((x) << S_T_DPD)
57272 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
57274 #define A_MC_LMC_CMD0 0x40144
57278 #define V_CMD(x) ((x) << S_CMD)
57279 #define G_CMD(x) (((x) >> S_CMD) & M_CMD)
57281 #define S_CMD_ACTN 28
57282 #define V_CMD_ACTN(x) ((x) << S_CMD_ACTN)
57283 #define F_CMD_ACTN V_CMD_ACTN(1U)
57286 #define V_BG1(x) ((x) << S_BG1)
57287 #define F_BG1 V_BG1(1U)
57290 #define M_BANK 0x7U
57291 #define V_BANK(x) ((x) << S_BANK)
57292 #define G_BANK(x) (((x) >> S_BANK) & M_BANK)
57294 #define A_MC_LMC_INITSEQ1 0x40148
57296 #define S_T6_RANK 0
57297 #define M_T6_RANK 0xfU
57298 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57299 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57301 #define A_MC_LMC_CMD1 0x4014c
57302 #define A_MC_LMC_INITSEQ2 0x40150
57304 #define S_T6_RANK 0
57305 #define M_T6_RANK 0xfU
57306 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57307 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57309 #define A_MC_LMC_CMD2 0x40154
57310 #define A_MC_LMC_INITSEQ3 0x40158
57312 #define S_T6_RANK 0
57313 #define M_T6_RANK 0xfU
57314 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57315 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57317 #define A_MC_LMC_CMD3 0x4015c
57318 #define A_MC_LMC_INITSEQ4 0x40160
57320 #define S_T6_RANK 0
57321 #define M_T6_RANK 0xfU
57322 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57323 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57325 #define A_MC_LMC_CMD4 0x40164
57326 #define A_MC_LMC_INITSEQ5 0x40168
57328 #define S_T6_RANK 0
57329 #define M_T6_RANK 0xfU
57330 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57331 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57333 #define A_MC_LMC_CMD5 0x4016c
57334 #define A_MC_LMC_INITSEQ6 0x40170
57336 #define S_T6_RANK 0
57337 #define M_T6_RANK 0xfU
57338 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57339 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57341 #define A_MC_LMC_CMD6 0x40174
57342 #define A_MC_LMC_INITSEQ7 0x40178
57344 #define S_T6_RANK 0
57345 #define M_T6_RANK 0xfU
57346 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57347 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57349 #define A_MC_LMC_CMD7 0x4017c
57350 #define A_MC_UPCTL_ECCCFG 0x40180
57351 #define A_MC_LMC_INITSEQ8 0x40180
57353 #define S_T6_RANK 0
57354 #define M_T6_RANK 0xfU
57355 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57356 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57358 #define A_MC_UPCTL_ECCTST 0x40184
57360 #define S_ECC_TEST_MASK0 0
57361 #define M_ECC_TEST_MASK0 0x7fU
57362 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
57363 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
57365 #define A_MC_LMC_CMD8 0x40184
57366 #define A_MC_UPCTL_ECCCLR 0x40188
57367 #define A_MC_LMC_INITSEQ9 0x40188
57369 #define S_T6_RANK 0
57370 #define M_T6_RANK 0xfU
57371 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57372 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57374 #define A_MC_UPCTL_ECCLOG 0x4018c
57375 #define A_MC_LMC_CMD9 0x4018c
57376 #define A_MC_LMC_INITSEQ10 0x40190
57378 #define S_T6_RANK 0
57379 #define M_T6_RANK 0xfU
57380 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57381 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57383 #define A_MC_LMC_CMD10 0x40194
57384 #define A_MC_LMC_INITSEQ11 0x40198
57386 #define S_T6_RANK 0
57387 #define M_T6_RANK 0xfU
57388 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57389 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57391 #define A_MC_LMC_CMD11 0x4019c
57392 #define A_MC_LMC_INITSEQ12 0x401a0
57394 #define S_T6_RANK 0
57395 #define M_T6_RANK 0xfU
57396 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57397 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57399 #define A_MC_LMC_CMD12 0x401a4
57400 #define A_MC_LMC_INITSEQ13 0x401a8
57402 #define S_T6_RANK 0
57403 #define M_T6_RANK 0xfU
57404 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57405 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57407 #define A_MC_LMC_CMD13 0x401ac
57408 #define A_MC_LMC_INITSEQ14 0x401b0
57410 #define S_T6_RANK 0
57411 #define M_T6_RANK 0xfU
57412 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57413 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57415 #define A_MC_LMC_CMD14 0x401b4
57416 #define A_MC_LMC_INITSEQ15 0x401b8
57418 #define S_T6_RANK 0
57419 #define M_T6_RANK 0xfU
57420 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57421 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57423 #define A_MC_LMC_CMD15 0x401bc
57424 #define A_MC_UPCTL_DTUWACTL 0x40200
57426 #define S_DTU_WR_ROW0 13
57427 #define M_DTU_WR_ROW0 0xffffU
57428 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
57429 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
57431 #define A_MC_LMC_SDTR0 0x40200
57434 #define M_REFI 0xffffU
57435 #define V_REFI(x) ((x) << S_REFI)
57436 #define G_REFI(x) (((x) >> S_REFI) & M_REFI)
57438 #define S_T_RFC_XPR 0
57439 #define M_T_RFC_XPR 0xfffU
57440 #define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR)
57441 #define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR)
57443 #define A_MC_UPCTL_DTURACTL 0x40204
57445 #define S_DTU_RD_ROW0 13
57446 #define M_DTU_RD_ROW0 0xffffU
57447 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
57448 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
57450 #define A_MC_LMC_SDTR1 0x40204
57452 #define S_T_LEADOFF 31
57453 #define V_T_LEADOFF(x) ((x) << S_T_LEADOFF)
57454 #define F_T_LEADOFF V_T_LEADOFF(1U)
57456 #define S_ODT_DELAY 30
57457 #define V_ODT_DELAY(x) ((x) << S_ODT_DELAY)
57458 #define F_ODT_DELAY V_ODT_DELAY(1U)
57460 #define S_ODT_WIDTH 29
57461 #define V_ODT_WIDTH(x) ((x) << S_ODT_WIDTH)
57462 #define F_ODT_WIDTH V_ODT_WIDTH(1U)
57464 #define S_T_WTRO 24
57465 #define M_T_WTRO 0xfU
57466 #define V_T_WTRO(x) ((x) << S_T_WTRO)
57467 #define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO)
57469 #define S_T_RTWO 16
57470 #define M_T_RTWO 0xfU
57471 #define V_T_RTWO(x) ((x) << S_T_RTWO)
57472 #define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO)
57474 #define S_T_RTW_ADJ 12
57475 #define M_T_RTW_ADJ 0xfU
57476 #define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ)
57477 #define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ)
57480 #define M_T_WTWO 0xfU
57481 #define V_T_WTWO(x) ((x) << S_T_WTWO)
57482 #define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO)
57485 #define M_T_RTRO 0xfU
57486 #define V_T_RTRO(x) ((x) << S_T_RTRO)
57487 #define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO)
57489 #define A_MC_UPCTL_DTUCFG 0x40208
57490 #define A_MC_LMC_SDTR2 0x40208
57492 #define S_T6_T_CWL 28
57493 #define M_T6_T_CWL 0xfU
57494 #define V_T6_T_CWL(x) ((x) << S_T6_T_CWL)
57495 #define G_T6_T_CWL(x) (((x) >> S_T6_T_CWL) & M_T6_T_CWL)
57497 #define S_T_RCD0 24
57498 #define M_T_RCD0 0xfU
57499 #define V_T_RCD0(x) ((x) << S_T_RCD0)
57500 #define G_T_RCD0(x) (((x) >> S_T_RCD0) & M_T_RCD0)
57503 #define M_T_PL 0xfU
57504 #define V_T_PL(x) ((x) << S_T_PL)
57505 #define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL)
57508 #define M_T_RP0 0xfU
57509 #define V_T_RP0(x) ((x) << S_T_RP0)
57510 #define G_T_RP0(x) (((x) >> S_T_RP0) & M_T_RP0)
57513 #define V_T_RP1(x) ((x) << S_T_RP1)
57514 #define F_T_RP1 V_T_RP1(1U)
57516 #define S_T_RCD1 14
57517 #define V_T_RCD1(x) ((x) << S_T_RCD1)
57518 #define F_T_RCD1 V_T_RCD1(1U)
57520 #define S_T6_T_RC 8
57521 #define M_T6_T_RC 0x3fU
57522 #define V_T6_T_RC(x) ((x) << S_T6_T_RC)
57523 #define G_T6_T_RC(x) (((x) >> S_T6_T_RC) & M_T6_T_RC)
57525 #define A_MC_UPCTL_DTUECTL 0x4020c
57526 #define A_MC_LMC_SDTR3 0x4020c
57528 #define S_T_WTR_S 28
57529 #define M_T_WTR_S 0xfU
57530 #define V_T_WTR_S(x) ((x) << S_T_WTR_S)
57531 #define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S)
57533 #define S_T6_T_WTR 24
57534 #define M_T6_T_WTR 0xfU
57535 #define V_T6_T_WTR(x) ((x) << S_T6_T_WTR)
57536 #define G_T6_T_WTR(x) (((x) >> S_T6_T_WTR) & M_T6_T_WTR)
57538 #define S_FAW_ADJ 20
57539 #define M_FAW_ADJ 0x3U
57540 #define V_FAW_ADJ(x) ((x) << S_FAW_ADJ)
57541 #define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ)
57543 #define S_T6_T_RTP 16
57544 #define M_T6_T_RTP 0xfU
57545 #define V_T6_T_RTP(x) ((x) << S_T6_T_RTP)
57546 #define G_T6_T_RTP(x) (((x) >> S_T6_T_RTP) & M_T6_T_RTP)
57548 #define S_T_RRD_L 12
57549 #define M_T_RRD_L 0xfU
57550 #define V_T_RRD_L(x) ((x) << S_T_RRD_L)
57551 #define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L)
57553 #define S_T6_T_RRD 8
57554 #define M_T6_T_RRD 0xfU
57555 #define V_T6_T_RRD(x) ((x) << S_T6_T_RRD)
57556 #define G_T6_T_RRD(x) (((x) >> S_T6_T_RRD) & M_T6_T_RRD)
57558 #define S_T_XSDLL 0
57559 #define M_T_XSDLL 0xffU
57560 #define V_T_XSDLL(x) ((x) << S_T_XSDLL)
57561 #define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL)
57563 #define A_MC_UPCTL_DTUWD0 0x40210
57564 #define A_MC_LMC_SDTR4 0x40210
57566 #define S_T_RDDATA_EN 24
57567 #define M_T_RDDATA_EN 0x7fU
57568 #define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN)
57569 #define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN)
57571 #define S_T_SYS_RDLAT 16
57572 #define M_T_SYS_RDLAT 0x3fU
57573 #define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT)
57574 #define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT)
57576 #define S_T_CCD_L 12
57577 #define M_T_CCD_L 0xfU
57578 #define V_T_CCD_L(x) ((x) << S_T_CCD_L)
57579 #define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L)
57582 #define M_T_CCD 0x7U
57583 #define V_T_CCD(x) ((x) << S_T_CCD)
57584 #define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD)
57586 #define S_T_CPDED 5
57587 #define M_T_CPDED 0x7U
57588 #define V_T_CPDED(x) ((x) << S_T_CPDED)
57589 #define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED)
57591 #define S_T6_T_MOD 0
57592 #define M_T6_T_MOD 0x1fU
57593 #define V_T6_T_MOD(x) ((x) << S_T6_T_MOD)
57594 #define G_T6_T_MOD(x) (((x) >> S_T6_T_MOD) & M_T6_T_MOD)
57596 #define A_MC_UPCTL_DTUWD1 0x40214
57597 #define A_MC_LMC_SDTR5 0x40214
57599 #define S_T_PHY_WRDATA 24
57600 #define M_T_PHY_WRDATA 0x7U
57601 #define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA)
57602 #define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA)
57604 #define S_T_PHY_WRLAT 16
57605 #define M_T_PHY_WRLAT 0x1fU
57606 #define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT)
57607 #define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT)
57609 #define A_MC_UPCTL_DTUWD2 0x40218
57610 #define A_MC_UPCTL_DTUWD3 0x4021c
57611 #define A_MC_UPCTL_DTUWDM 0x40220
57612 #define A_MC_UPCTL_DTURD0 0x40224
57613 #define A_MC_UPCTL_DTURD1 0x40228
57614 #define A_MC_LMC_DBG0 0x40228
57616 #define S_T_SYS_RDLAT_DBG 16
57617 #define M_T_SYS_RDLAT_DBG 0x1fU
57618 #define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG)
57619 #define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG)
57621 #define A_MC_UPCTL_DTURD2 0x4022c
57622 #define A_MC_UPCTL_DTURD3 0x40230
57623 #define A_MC_UPCTL_DTULFSRWD 0x40234
57624 #define A_MC_UPCTL_DTULFSRRD 0x40238
57625 #define A_MC_UPCTL_DTUEAF 0x4023c
57627 #define S_EA_ROW0 13
57628 #define M_EA_ROW0 0xffffU
57629 #define V_EA_ROW0(x) ((x) << S_EA_ROW0)
57630 #define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
57632 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
57634 #define S_TCTRL_DELAY 0
57635 #define M_TCTRL_DELAY 0xfU
57636 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
57637 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
57639 #define A_MC_LMC_SMR0 0x40240
57641 #define S_SMR0_RFU0 13
57642 #define M_SMR0_RFU0 0x7U
57643 #define V_SMR0_RFU0(x) ((x) << S_SMR0_RFU0)
57644 #define G_SMR0_RFU0(x) (((x) >> S_SMR0_RFU0) & M_SMR0_RFU0)
57647 #define V_PPD(x) ((x) << S_PPD)
57648 #define F_PPD V_PPD(1U)
57651 #define M_WR_RTP 0x7U
57652 #define V_WR_RTP(x) ((x) << S_WR_RTP)
57653 #define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP)
57655 #define S_SMR0_DLL 8
57656 #define V_SMR0_DLL(x) ((x) << S_SMR0_DLL)
57657 #define F_SMR0_DLL V_SMR0_DLL(1U)
57660 #define V_TM(x) ((x) << S_TM)
57661 #define F_TM V_TM(1U)
57664 #define M_CL31 0x7U
57665 #define V_CL31(x) ((x) << S_CL31)
57666 #define G_CL31(x) (((x) >> S_CL31) & M_CL31)
57669 #define V_RBT(x) ((x) << S_RBT)
57670 #define F_RBT V_RBT(1U)
57673 #define V_CL0(x) ((x) << S_CL0)
57674 #define F_CL0 V_CL0(1U)
57678 #define V_BL(x) ((x) << S_BL)
57679 #define G_BL(x) (((x) >> S_BL) & M_BL)
57681 #define A_MC_UPCTL_DFIODTCFG 0x40244
57683 #define S_RANK3_ODT_WRITE_NSEL 26
57684 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
57685 #define F_RANK3_ODT_WRITE_NSEL V_RANK3_ODT_WRITE_NSEL(1U)
57687 #define A_MC_LMC_SMR1 0x40244
57690 #define V_QOFF(x) ((x) << S_QOFF)
57691 #define F_QOFF V_QOFF(1U)
57694 #define V_TDQS(x) ((x) << S_TDQS)
57695 #define F_TDQS V_TDQS(1U)
57697 #define S_SMR1_RFU0 10
57698 #define V_SMR1_RFU0(x) ((x) << S_SMR1_RFU0)
57699 #define F_SMR1_RFU0 V_SMR1_RFU0(1U)
57701 #define S_RTT_NOM0 9
57702 #define V_RTT_NOM0(x) ((x) << S_RTT_NOM0)
57703 #define F_RTT_NOM0 V_RTT_NOM0(1U)
57705 #define S_SMR1_RFU1 8
57706 #define V_SMR1_RFU1(x) ((x) << S_SMR1_RFU1)
57707 #define F_SMR1_RFU1 V_SMR1_RFU1(1U)
57709 #define S_WR_LEVEL 7
57710 #define V_WR_LEVEL(x) ((x) << S_WR_LEVEL)
57711 #define F_WR_LEVEL V_WR_LEVEL(1U)
57713 #define S_RTT_NOM1 6
57714 #define V_RTT_NOM1(x) ((x) << S_RTT_NOM1)
57715 #define F_RTT_NOM1 V_RTT_NOM1(1U)
57718 #define V_DIC0(x) ((x) << S_DIC0)
57719 #define F_DIC0 V_DIC0(1U)
57723 #define V_AL(x) ((x) << S_AL)
57724 #define G_AL(x) (((x) >> S_AL) & M_AL)
57726 #define S_RTT_NOM2 2
57727 #define V_RTT_NOM2(x) ((x) << S_RTT_NOM2)
57728 #define F_RTT_NOM2 V_RTT_NOM2(1U)
57731 #define V_DIC1(x) ((x) << S_DIC1)
57732 #define F_DIC1 V_DIC1(1U)
57734 #define S_SMR1_DLL 0
57735 #define V_SMR1_DLL(x) ((x) << S_SMR1_DLL)
57736 #define F_SMR1_DLL V_SMR1_DLL(1U)
57738 #define A_MC_UPCTL_DFIODTCFG1 0x40248
57740 #define S_ODT_LEN_B8_R 24
57741 #define M_ODT_LEN_B8_R 0x7U
57742 #define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
57743 #define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
57745 #define S_ODT_LEN_BL8_W 16
57746 #define M_ODT_LEN_BL8_W 0x7U
57747 #define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
57748 #define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
57750 #define S_ODT_LAT_R 8
57751 #define M_ODT_LAT_R 0x1fU
57752 #define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
57753 #define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
57755 #define S_ODT_LAT_W 0
57756 #define M_ODT_LAT_W 0x1fU
57757 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
57758 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
57760 #define A_MC_LMC_SMR2 0x40248
57762 #define S_WR_CRC 12
57763 #define V_WR_CRC(x) ((x) << S_WR_CRC)
57764 #define F_WR_CRC V_WR_CRC(1U)
57766 #define S_RD_CRC 11
57767 #define V_RD_CRC(x) ((x) << S_RD_CRC)
57768 #define F_RD_CRC V_RD_CRC(1U)
57771 #define M_RTT_WR 0x3U
57772 #define V_RTT_WR(x) ((x) << S_RTT_WR)
57773 #define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR)
57775 #define S_SMR2_RFU0 8
57776 #define V_SMR2_RFU0(x) ((x) << S_SMR2_RFU0)
57777 #define F_SMR2_RFU0 V_SMR2_RFU0(1U)
57779 #define S_SRT_ASR1 7
57780 #define V_SRT_ASR1(x) ((x) << S_SRT_ASR1)
57781 #define F_SRT_ASR1 V_SRT_ASR1(1U)
57784 #define V_ASR0(x) ((x) << S_ASR0)
57785 #define F_ASR0 V_ASR0(1U)
57789 #define V_CWL(x) ((x) << S_CWL)
57790 #define G_CWL(x) (((x) >> S_CWL) & M_CWL)
57793 #define M_PASR 0x7U
57794 #define V_PASR(x) ((x) << S_PASR)
57795 #define G_PASR(x) (((x) >> S_PASR) & M_PASR)
57797 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
57799 #define S_ODT_RANK_MAP3 12
57800 #define M_ODT_RANK_MAP3 0xfU
57801 #define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
57802 #define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
57804 #define S_ODT_RANK_MAP2 8
57805 #define M_ODT_RANK_MAP2 0xfU
57806 #define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
57807 #define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
57809 #define S_ODT_RANK_MAP1 4
57810 #define M_ODT_RANK_MAP1 0xfU
57811 #define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
57812 #define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
57814 #define S_ODT_RANK_MAP0 0
57815 #define M_ODT_RANK_MAP0 0xfU
57816 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
57817 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
57819 #define A_MC_LMC_SMR3 0x4024c
57821 #define S_MPR_RD_FMT 11
57822 #define M_MPR_RD_FMT 0x3U
57823 #define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT)
57824 #define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT)
57826 #define S_SMR3_RFU0 9
57827 #define M_SMR3_RFU0 0x3U
57828 #define V_SMR3_RFU0(x) ((x) << S_SMR3_RFU0)
57829 #define G_SMR3_RFU0(x) (((x) >> S_SMR3_RFU0) & M_SMR3_RFU0)
57831 #define S_FGR_MODE 6
57832 #define M_FGR_MODE 0x7U
57833 #define V_FGR_MODE(x) ((x) << S_FGR_MODE)
57834 #define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE)
57836 #define S_MRS_RDO 5
57837 #define V_MRS_RDO(x) ((x) << S_MRS_RDO)
57838 #define F_MRS_RDO V_MRS_RDO(1U)
57840 #define S_DRAM_ADR 4
57841 #define V_DRAM_ADR(x) ((x) << S_DRAM_ADR)
57842 #define F_DRAM_ADR V_DRAM_ADR(1U)
57844 #define S_GD_MODE 3
57845 #define V_GD_MODE(x) ((x) << S_GD_MODE)
57846 #define F_GD_MODE V_GD_MODE(1U)
57849 #define V_MPR(x) ((x) << S_MPR)
57850 #define F_MPR V_MPR(1U)
57852 #define S_MPR_SEL 0
57853 #define M_MPR_SEL 0x3U
57854 #define V_MPR_SEL(x) ((x) << S_MPR_SEL)
57855 #define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL)
57857 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
57859 #define S_TPHY_WRDATA 0
57860 #define M_TPHY_WRDATA 0x1fU
57861 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
57862 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
57864 #define A_MC_LMC_SMR4 0x40250
57866 #define S_WR_PRE 12
57867 #define V_WR_PRE(x) ((x) << S_WR_PRE)
57868 #define F_WR_PRE V_WR_PRE(1U)
57870 #define S_RD_PRE 11
57871 #define V_RD_PRE(x) ((x) << S_RD_PRE)
57872 #define F_RD_PRE V_RD_PRE(1U)
57874 #define S_RPT_MODE 10
57875 #define V_RPT_MODE(x) ((x) << S_RPT_MODE)
57876 #define F_RPT_MODE V_RPT_MODE(1U)
57878 #define S_FESR_MODE 9
57879 #define V_FESR_MODE(x) ((x) << S_FESR_MODE)
57880 #define F_FESR_MODE V_FESR_MODE(1U)
57882 #define S_CS_LAT_MODE 6
57883 #define M_CS_LAT_MODE 0x7U
57884 #define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE)
57885 #define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE)
57887 #define S_ALERT_STAT 5
57888 #define V_ALERT_STAT(x) ((x) << S_ALERT_STAT)
57889 #define F_ALERT_STAT V_ALERT_STAT(1U)
57891 #define S_IVM_MODE 4
57892 #define V_IVM_MODE(x) ((x) << S_IVM_MODE)
57893 #define F_IVM_MODE V_IVM_MODE(1U)
57895 #define S_TCR_MODE 3
57896 #define V_TCR_MODE(x) ((x) << S_TCR_MODE)
57897 #define F_TCR_MODE V_TCR_MODE(1U)
57899 #define S_TCR_RANGE 2
57900 #define V_TCR_RANGE(x) ((x) << S_TCR_RANGE)
57901 #define F_TCR_RANGE V_TCR_RANGE(1U)
57903 #define S_MPD_MODE 1
57904 #define V_MPD_MODE(x) ((x) << S_MPD_MODE)
57905 #define F_MPD_MODE V_MPD_MODE(1U)
57907 #define S_SMR4_RFU 0
57908 #define V_SMR4_RFU(x) ((x) << S_SMR4_RFU)
57909 #define F_SMR4_RFU V_SMR4_RFU(1U)
57911 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
57913 #define S_TPHY_WRLAT 0
57914 #define M_TPHY_WRLAT 0x1fU
57915 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
57916 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
57918 #define A_MC_LMC_SMR5 0x40254
57920 #define S_RD_DBI 11
57921 #define V_RD_DBI(x) ((x) << S_RD_DBI)
57922 #define F_RD_DBI V_RD_DBI(1U)
57924 #define S_WR_DBI 10
57925 #define V_WR_DBI(x) ((x) << S_WR_DBI)
57926 #define F_WR_DBI V_WR_DBI(1U)
57928 #define S_DM_MODE 9
57929 #define V_DM_MODE(x) ((x) << S_DM_MODE)
57930 #define F_DM_MODE V_DM_MODE(1U)
57932 #define S_RTT_PARK 6
57933 #define M_RTT_PARK 0x7U
57934 #define V_RTT_PARK(x) ((x) << S_RTT_PARK)
57935 #define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK)
57937 #define S_SMR5_RFU 5
57938 #define V_SMR5_RFU(x) ((x) << S_SMR5_RFU)
57939 #define F_SMR5_RFU V_SMR5_RFU(1U)
57941 #define S_PAR_ERR_STAT 4
57942 #define V_PAR_ERR_STAT(x) ((x) << S_PAR_ERR_STAT)
57943 #define F_PAR_ERR_STAT V_PAR_ERR_STAT(1U)
57945 #define S_CRC_CLEAR 3
57946 #define V_CRC_CLEAR(x) ((x) << S_CRC_CLEAR)
57947 #define F_CRC_CLEAR V_CRC_CLEAR(1U)
57949 #define S_PAR_LAT_MODE 0
57950 #define M_PAR_LAT_MODE 0x7U
57951 #define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE)
57952 #define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE)
57954 #define A_MC_LMC_SMR6 0x40258
57956 #define S_TCCD_L 10
57957 #define M_TCCD_L 0x7U
57958 #define V_TCCD_L(x) ((x) << S_TCCD_L)
57959 #define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L)
57961 #define S_SRM6_RFU 7
57962 #define M_SRM6_RFU 0x7U
57963 #define V_SRM6_RFU(x) ((x) << S_SRM6_RFU)
57964 #define G_SRM6_RFU(x) (((x) >> S_SRM6_RFU) & M_SRM6_RFU)
57966 #define S_VREF_DQ_RANGE 6
57967 #define V_VREF_DQ_RANGE(x) ((x) << S_VREF_DQ_RANGE)
57968 #define F_VREF_DQ_RANGE V_VREF_DQ_RANGE(1U)
57970 #define S_VREF_DQ_VALUE 0
57971 #define M_VREF_DQ_VALUE 0x3fU
57972 #define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE)
57973 #define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE)
57975 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
57977 #define S_TRDDATA_EN 0
57978 #define M_TRDDATA_EN 0x1fU
57979 #define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
57980 #define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
57982 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
57984 #define S_TPHY_RDLAT 0
57985 #define M_TPHY_RDLAT 0x3fU
57986 #define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
57987 #define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
57989 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
57991 #define S_TPHYUPD_TYPE0 0
57992 #define M_TPHYUPD_TYPE0 0xfffU
57993 #define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
57994 #define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
57996 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
57998 #define S_TPHYUPD_TYPE1 0
57999 #define M_TPHYUPD_TYPE1 0xfffU
58000 #define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
58001 #define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
58003 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
58005 #define S_TPHYUPD_TYPE2 0
58006 #define M_TPHYUPD_TYPE2 0xfffU
58007 #define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
58008 #define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
58010 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
58012 #define S_TPHYUPD_TYPE3 0
58013 #define M_TPHYUPD_TYPE3 0xfffU
58014 #define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
58015 #define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
58017 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
58019 #define S_TCTRLUPD_MIN 0
58020 #define M_TCTRLUPD_MIN 0xffffU
58021 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
58022 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
58024 #define A_MC_LMC_ODTR0 0x40280
58027 #define V_RK0W(x) ((x) << S_RK0W)
58028 #define F_RK0W V_RK0W(1U)
58031 #define V_RK0R(x) ((x) << S_RK0R)
58032 #define F_RK0R V_RK0R(1U)
58034 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
58036 #define S_TCTRLUPD_MAX 0
58037 #define M_TCTRLUPD_MAX 0xffffU
58038 #define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
58039 #define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
58041 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
58043 #define S_TCTRLUPD_DLY 0
58044 #define M_TCTRLUPD_DLY 0xfU
58045 #define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
58046 #define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
58048 #define A_MC_UPCTL_DFIUPDCFG 0x40290
58050 #define S_DFI_PHYUPD_EN 1
58051 #define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
58052 #define F_DFI_PHYUPD_EN V_DFI_PHYUPD_EN(1U)
58054 #define S_DFI_CTRLUPD_EN 0
58055 #define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
58056 #define F_DFI_CTRLUPD_EN V_DFI_CTRLUPD_EN(1U)
58058 #define A_MC_UPCTL_DFITREFMSKI 0x40294
58060 #define S_TREFMSKI 0
58061 #define M_TREFMSKI 0xffU
58062 #define V_TREFMSKI(x) ((x) << S_TREFMSKI)
58063 #define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
58065 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
58066 #define A_MC_UPCTL_DFITRCFG0 0x402ac
58068 #define S_DFI_WRLVL_RANK_SEL 16
58069 #define M_DFI_WRLVL_RANK_SEL 0xfU
58070 #define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
58071 #define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
58073 #define S_DFI_RDLVL_EDGE 4
58074 #define M_DFI_RDLVL_EDGE 0x1ffU
58075 #define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
58076 #define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
58078 #define S_DFI_RDLVL_RANK_SEL 0
58079 #define M_DFI_RDLVL_RANK_SEL 0xfU
58080 #define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
58081 #define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
58083 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
58085 #define S_DFI_WRLVL_MODE 16
58086 #define M_DFI_WRLVL_MODE 0x3U
58087 #define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
58088 #define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
58090 #define S_DFI_RDLVL_GATE_MODE 8
58091 #define M_DFI_RDLVL_GATE_MODE 0x3U
58092 #define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
58093 #define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
58095 #define S_DFI_RDLVL_MODE 0
58096 #define M_DFI_RDLVL_MODE 0x3U
58097 #define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
58098 #define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
58100 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
58102 #define S_DFI_WRLVL_EN 0
58103 #define M_DFI_WRLVL_EN 0x1ffU
58104 #define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
58105 #define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
58107 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
58109 #define S_DFI_RDLVL_EN 0
58110 #define M_DFI_RDLVL_EN 0x1ffU
58111 #define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
58112 #define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
58114 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
58116 #define S_DFI_RDLVL_GATE_EN 0
58117 #define M_DFI_RDLVL_GATE_EN 0x1ffU
58118 #define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
58119 #define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
58121 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
58123 #define S_DFI_DATA_BYTE_DISABLE 16
58124 #define M_DFI_DATA_BYTE_DISABLE 0x1ffU
58125 #define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
58126 #define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
58128 #define S_DFI_FREQ_RATIO 4
58129 #define M_DFI_FREQ_RATIO 0x3U
58130 #define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
58131 #define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
58133 #define S_DFI_INIT_START0 1
58134 #define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
58135 #define F_DFI_INIT_START0 V_DFI_INIT_START0(1U)
58137 #define S_DFI_INIT_COMPLETE 0
58138 #define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
58139 #define F_DFI_INIT_COMPLETE V_DFI_INIT_COMPLETE(1U)
58141 #define A_MC_UPCTL_DFISTCFG0 0x402c4
58143 #define S_DFI_DATA_BYTE_DISABLE_EN 2
58144 #define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
58145 #define F_DFI_DATA_BYTE_DISABLE_EN V_DFI_DATA_BYTE_DISABLE_EN(1U)
58147 #define S_DFI_FREQ_RATIO_EN 1
58148 #define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
58149 #define F_DFI_FREQ_RATIO_EN V_DFI_FREQ_RATIO_EN(1U)
58151 #define S_DFI_INIT_START 0
58152 #define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
58153 #define F_DFI_INIT_START V_DFI_INIT_START(1U)
58155 #define A_MC_UPCTL_DFISTCFG1 0x402c8
58157 #define S_DFI_DRAM_CLK_DISABLE_EN_DPD 1
58158 #define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
58159 #define F_DFI_DRAM_CLK_DISABLE_EN_DPD V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
58161 #define S_DFI_DRAM_CLK_DISABLE_EN 0
58162 #define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
58163 #define F_DFI_DRAM_CLK_DISABLE_EN V_DFI_DRAM_CLK_DISABLE_EN(1U)
58165 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
58167 #define S_TDRAM_CLK_ENABLE 0
58168 #define M_TDRAM_CLK_ENABLE 0xfU
58169 #define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
58170 #define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
58172 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
58174 #define S_TDRAM_CLK_DISABLE 0
58175 #define M_TDRAM_CLK_DISABLE 0xfU
58176 #define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
58177 #define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
58179 #define A_MC_UPCTL_DFISTCFG2 0x402d8
58181 #define S_PARITY_EN 1
58182 #define V_PARITY_EN(x) ((x) << S_PARITY_EN)
58183 #define F_PARITY_EN V_PARITY_EN(1U)
58185 #define S_PARITY_INTR_EN 0
58186 #define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
58187 #define F_PARITY_INTR_EN V_PARITY_INTR_EN(1U)
58189 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
58191 #define S_PARITY_LOG_CLR 1
58192 #define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
58193 #define F_PARITY_LOG_CLR V_PARITY_LOG_CLR(1U)
58195 #define S_PARITY_INTR_CLR 0
58196 #define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
58197 #define F_PARITY_INTR_CLR V_PARITY_INTR_CLR(1U)
58199 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
58200 #define A_MC_UPCTL_DFILPCFG0 0x402f0
58202 #define S_DFI_LP_WAKEUP_DPD 28
58203 #define M_DFI_LP_WAKEUP_DPD 0xfU
58204 #define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
58205 #define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
58207 #define S_DFI_LP_EN_DPD 24
58208 #define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
58209 #define F_DFI_LP_EN_DPD V_DFI_LP_EN_DPD(1U)
58211 #define S_DFI_TLP_RESP 16
58212 #define M_DFI_TLP_RESP 0xfU
58213 #define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
58214 #define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
58216 #define S_DFI_LP_EN_SR 8
58217 #define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
58218 #define F_DFI_LP_EN_SR V_DFI_LP_EN_SR(1U)
58220 #define S_DFI_LP_WAKEUP_PD 4
58221 #define M_DFI_LP_WAKEUP_PD 0xfU
58222 #define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
58223 #define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
58225 #define S_DFI_LP_EN_PD 0
58226 #define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
58227 #define F_DFI_LP_EN_PD V_DFI_LP_EN_PD(1U)
58229 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
58230 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
58231 #define A_MC_LMC_CALSTAT 0x40304
58233 #define S_PHYUPD_ERR 28
58234 #define M_PHYUPD_ERR 0xfU
58235 #define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR)
58236 #define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR)
58238 #define S_PHYUPD_BUSY 27
58239 #define V_PHYUPD_BUSY(x) ((x) << S_PHYUPD_BUSY)
58240 #define F_PHYUPD_BUSY V_PHYUPD_BUSY(1U)
58242 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
58244 #define S_DFI_WRLVL_RESP2 0
58245 #define M_DFI_WRLVL_RESP2 0xffU
58246 #define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
58247 #define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
58249 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
58250 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
58251 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
58253 #define S_DFI_RDLVL_RESP2 0
58254 #define M_DFI_RDLVL_RESP2 0xffU
58255 #define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
58256 #define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
58258 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
58259 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
58260 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
58262 #define S_DFI_WRLVL_DELAY2 0
58263 #define M_DFI_WRLVL_DELAY2 0xffU
58264 #define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
58265 #define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
58267 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
58268 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
58269 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
58271 #define S_DFI_RDLVL_DELAY2 0
58272 #define M_DFI_RDLVL_DELAY2 0xffU
58273 #define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
58274 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
58276 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
58277 #define A_MC_LMC_T_PHYUPD0 0x40330
58278 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
58279 #define A_MC_LMC_T_PHYUPD1 0x40334
58280 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
58282 #define S_DFI_RDLVL_GATE_DELAY2 0
58283 #define M_DFI_RDLVL_GATE_DELAY2 0xffU
58284 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
58285 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
58287 #define A_MC_LMC_T_PHYUPD2 0x40338
58288 #define A_MC_UPCTL_DFITRCMD 0x4033c
58290 #define S_DFITRCMD_START 31
58291 #define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
58292 #define F_DFITRCMD_START V_DFITRCMD_START(1U)
58294 #define S_DFITRCMD_EN 4
58295 #define M_DFITRCMD_EN 0x1ffU
58296 #define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
58297 #define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
58299 #define S_DFITRCMD_OPCODE 0
58300 #define M_DFITRCMD_OPCODE 0x3U
58301 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
58302 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
58304 #define A_MC_LMC_T_PHYUPD3 0x4033c
58305 #define A_MC_UPCTL_IPVR 0x403f8
58306 #define A_MC_UPCTL_IPTR 0x403fc
58307 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
58309 #define S_PHY_DRAM_WL 17
58310 #define M_PHY_DRAM_WL 0x1fU
58311 #define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
58312 #define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
58314 #define S_PHY_CALIB_DONE 5
58315 #define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
58316 #define F_PHY_CALIB_DONE V_PHY_CALIB_DONE(1U)
58318 #define S_CTL_CAL_REQ 4
58319 #define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
58320 #define F_CTL_CAL_REQ V_CTL_CAL_REQ(1U)
58322 #define S_CTL_CKE 3
58323 #define V_CTL_CKE(x) ((x) << S_CTL_CKE)
58324 #define F_CTL_CKE V_CTL_CKE(1U)
58326 #define S_CTL_RST_N 2
58327 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
58328 #define F_CTL_RST_N V_CTL_RST_N(1U)
58330 #define S_PHY_CAL_REQ 21
58331 #define V_PHY_CAL_REQ(x) ((x) << S_PHY_CAL_REQ)
58332 #define F_PHY_CAL_REQ V_PHY_CAL_REQ(1U)
58334 #define S_T6_PHY_DRAM_WL 17
58335 #define M_T6_PHY_DRAM_WL 0xfU
58336 #define V_T6_PHY_DRAM_WL(x) ((x) << S_T6_PHY_DRAM_WL)
58337 #define G_T6_PHY_DRAM_WL(x) (((x) >> S_T6_PHY_DRAM_WL) & M_T6_PHY_DRAM_WL)
58339 #define A_MC_P_PERFORMANCE_CTRL 0x41304
58341 #define S_BUF_USE_TH 12
58342 #define M_BUF_USE_TH 0x7U
58343 #define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH)
58344 #define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH)
58346 #define S_MC_IDLE_TH 8
58347 #define M_MC_IDLE_TH 0xfU
58348 #define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH)
58349 #define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH)
58351 #define S_RMW_DEFER_EN 7
58352 #define V_RMW_DEFER_EN(x) ((x) << S_RMW_DEFER_EN)
58353 #define F_RMW_DEFER_EN V_RMW_DEFER_EN(1U)
58355 #define S_DDR3_BRBC_MODE 6
58356 #define V_DDR3_BRBC_MODE(x) ((x) << S_DDR3_BRBC_MODE)
58357 #define F_DDR3_BRBC_MODE V_DDR3_BRBC_MODE(1U)
58359 #define S_RMW_DWRITE_EN 5
58360 #define V_RMW_DWRITE_EN(x) ((x) << S_RMW_DWRITE_EN)
58361 #define F_RMW_DWRITE_EN V_RMW_DWRITE_EN(1U)
58363 #define S_RMW_MERGE_EN 4
58364 #define V_RMW_MERGE_EN(x) ((x) << S_RMW_MERGE_EN)
58365 #define F_RMW_MERGE_EN V_RMW_MERGE_EN(1U)
58367 #define S_SYNC_PAB_EN 3
58368 #define V_SYNC_PAB_EN(x) ((x) << S_SYNC_PAB_EN)
58369 #define F_SYNC_PAB_EN V_SYNC_PAB_EN(1U)
58371 #define A_MC_P_ECC_CTRL 0x41308
58372 #define A_MC_P_PAR_ENABLE 0x4130c
58373 #define A_MC_P_PAR_CAUSE 0x41310
58374 #define A_MC_P_INT_ENABLE 0x41314
58375 #define A_MC_P_INT_CAUSE 0x41318
58376 #define A_MC_P_ECC_STATUS 0x4131c
58377 #define A_MC_P_PHY_CTRL 0x41320
58378 #define A_MC_P_STATIC_CFG_STATUS 0x41324
58380 #define S_STATIC_AWEN 23
58381 #define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
58382 #define F_STATIC_AWEN V_STATIC_AWEN(1U)
58384 #define S_STATIC_SWLAT 18
58385 #define M_STATIC_SWLAT 0x1fU
58386 #define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
58387 #define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
58389 #define S_STATIC_WLAT 17
58390 #define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
58391 #define F_STATIC_WLAT V_STATIC_WLAT(1U)
58393 #define S_STATIC_ALIGN 16
58394 #define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
58395 #define F_STATIC_ALIGN V_STATIC_ALIGN(1U)
58397 #define S_STATIC_SLAT 11
58398 #define M_STATIC_SLAT 0x1fU
58399 #define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
58400 #define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
58402 #define S_STATIC_LAT 10
58403 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
58404 #define F_STATIC_LAT V_STATIC_LAT(1U)
58406 #define S_STATIC_PP64 26
58407 #define V_STATIC_PP64(x) ((x) << S_STATIC_PP64)
58408 #define F_STATIC_PP64 V_STATIC_PP64(1U)
58410 #define S_STATIC_PPEN 25
58411 #define V_STATIC_PPEN(x) ((x) << S_STATIC_PPEN)
58412 #define F_STATIC_PPEN V_STATIC_PPEN(1U)
58414 #define S_STATIC_OOOEN 24
58415 #define V_STATIC_OOOEN(x) ((x) << S_STATIC_OOOEN)
58416 #define F_STATIC_OOOEN V_STATIC_OOOEN(1U)
58418 #define A_MC_P_CORE_PCTL_STAT 0x41328
58419 #define A_MC_P_DEBUG_CNT 0x4132c
58420 #define A_MC_CE_ERR_DATA_RDATA 0x41330
58421 #define A_MC_CE_COR_DATA_RDATA 0x41350
58422 #define A_MC_UE_ERR_DATA_RDATA 0x41370
58423 #define A_MC_UE_COR_DATA_RDATA 0x41390
58424 #define A_MC_CE_ADDR 0x413b0
58425 #define A_MC_UE_ADDR 0x413b4
58426 #define A_MC_P_DEEP_SLEEP 0x413b8
58428 #define S_SLEEPSTATUS 1
58429 #define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
58430 #define F_SLEEPSTATUS V_SLEEPSTATUS(1U)
58432 #define S_SLEEPREQ 0
58433 #define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
58434 #define F_SLEEPREQ V_SLEEPREQ(1U)
58436 #define A_MC_P_FPGA_BONUS 0x413bc
58437 #define A_MC_P_DEBUG_CFG 0x413c0
58438 #define A_MC_P_DEBUG_RPT 0x413c4
58439 #define A_MC_P_PHY_ADR_CK_EN 0x413c8
58441 #define S_ADR_CK_EN 0
58442 #define V_ADR_CK_EN(x) ((x) << S_ADR_CK_EN)
58443 #define F_ADR_CK_EN V_ADR_CK_EN(1U)
58445 #define A_MC_CE_ERR_ECC_DATA0 0x413d0
58446 #define A_MC_CE_ERR_ECC_DATA1 0x413d4
58447 #define A_MC_UE_ERR_ECC_DATA0 0x413d8
58448 #define A_MC_UE_ERR_ECC_DATA1 0x413dc
58449 #define A_MC_P_RMW_PRIO 0x413f0
58451 #define S_WR_HI_TH 24
58452 #define M_WR_HI_TH 0xffU
58453 #define V_WR_HI_TH(x) ((x) << S_WR_HI_TH)
58454 #define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH)
58456 #define S_WR_MID_TH 16
58457 #define M_WR_MID_TH 0xffU
58458 #define V_WR_MID_TH(x) ((x) << S_WR_MID_TH)
58459 #define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH)
58461 #define S_RD_HI_TH 8
58462 #define M_RD_HI_TH 0xffU
58463 #define V_RD_HI_TH(x) ((x) << S_RD_HI_TH)
58464 #define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH)
58466 #define S_RD_MID_TH 0
58467 #define M_RD_MID_TH 0xffU
58468 #define V_RD_MID_TH(x) ((x) << S_RD_MID_TH)
58469 #define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH)
58471 #define A_MC_P_BIST_CMD 0x41400
58473 #define S_BURST_LEN 16
58474 #define M_BURST_LEN 0x3U
58475 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
58476 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
58478 #define A_MC_P_BIST_CMD_ADDR 0x41404
58479 #define A_MC_P_BIST_CMD_LEN 0x41408
58480 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
58481 #define A_MC_P_BIST_USER_WDATA0 0x41414
58482 #define A_MC_P_BIST_USER_WMASK0 0x41414
58483 #define A_MC_P_BIST_USER_WDATA1 0x41418
58484 #define A_MC_P_BIST_USER_WMASK1 0x41418
58485 #define A_MC_P_BIST_USER_WDATA2 0x4141c
58487 #define S_USER_DATA_MASK 8
58488 #define M_USER_DATA_MASK 0x1ffU
58489 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
58490 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
58492 #define A_MC_P_BIST_USER_WMASK2 0x4141c
58494 #define S_MASK_128_1 9
58495 #define V_MASK_128_1(x) ((x) << S_MASK_128_1)
58496 #define F_MASK_128_1 V_MASK_128_1(1U)
58498 #define S_MASK_128_0 8
58499 #define V_MASK_128_0(x) ((x) << S_MASK_128_0)
58500 #define F_MASK_128_0 V_MASK_128_0(1U)
58502 #define S_USER_MASK_ECC 0
58503 #define M_USER_MASK_ECC 0xffU
58504 #define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC)
58505 #define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC)
58507 #define A_MC_P_BIST_NUM_ERR 0x41480
58508 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
58509 #define A_MC_P_BIST_STATUS_RDATA 0x41488
58510 #define A_MC_P_BIST_CRC_SEED 0x414d0
58511 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
58513 #define S_DATA_BIT_ENABLE_0_15 0
58514 #define M_DATA_BIT_ENABLE_0_15 0xffffU
58515 #define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
58516 #define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
58518 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
58520 #define S_DATA_BIT_ENABLE_16_23 8
58521 #define M_DATA_BIT_ENABLE_16_23 0xffU
58522 #define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
58523 #define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
58525 #define S_DFT_FORCE_OUTPUTS 7
58526 #define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
58527 #define F_DFT_FORCE_OUTPUTS V_DFT_FORCE_OUTPUTS(1U)
58529 #define S_DFT_PRBS7_GEN_EN 6
58530 #define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
58531 #define F_DFT_PRBS7_GEN_EN V_DFT_PRBS7_GEN_EN(1U)
58533 #define S_WRAPSEL 5
58534 #define V_WRAPSEL(x) ((x) << S_WRAPSEL)
58535 #define F_WRAPSEL V_WRAPSEL(1U)
58537 #define S_MRS_CMD_DATA_N0 3
58538 #define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
58539 #define F_MRS_CMD_DATA_N0 V_MRS_CMD_DATA_N0(1U)
58541 #define S_MRS_CMD_DATA_N1 2
58542 #define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
58543 #define F_MRS_CMD_DATA_N1 V_MRS_CMD_DATA_N1(1U)
58545 #define S_MRS_CMD_DATA_N2 1
58546 #define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
58547 #define F_MRS_CMD_DATA_N2 V_MRS_CMD_DATA_N2(1U)
58549 #define S_MRS_CMD_DATA_N3 0
58550 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
58551 #define F_MRS_CMD_DATA_N3 V_MRS_CMD_DATA_N3(1U)
58553 #define S_DP18_WRAPSEL 5
58554 #define V_DP18_WRAPSEL(x) ((x) << S_DP18_WRAPSEL)
58555 #define F_DP18_WRAPSEL V_DP18_WRAPSEL(1U)
58557 #define S_HW_VALUE 4
58558 #define V_HW_VALUE(x) ((x) << S_HW_VALUE)
58559 #define F_HW_VALUE V_HW_VALUE(1U)
58561 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
58563 #define S_DATA_BIT_DIR_0_15 0
58564 #define M_DATA_BIT_DIR_0_15 0xffffU
58565 #define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
58566 #define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
58568 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
58570 #define S_DATA_BIT_DIR_16_23 8
58571 #define M_DATA_BIT_DIR_16_23 0xffU
58572 #define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
58573 #define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
58575 #define S_WL_ADVANCE_DISABLE 7
58576 #define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
58577 #define F_WL_ADVANCE_DISABLE V_WL_ADVANCE_DISABLE(1U)
58579 #define S_DISABLE_PING_PONG 6
58580 #define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
58581 #define F_DISABLE_PING_PONG V_DISABLE_PING_PONG(1U)
58583 #define S_DELAY_PING_PONG_HALF 5
58584 #define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
58585 #define F_DELAY_PING_PONG_HALF V_DELAY_PING_PONG_HALF(1U)
58587 #define S_ADVANCE_PING_PONG 4
58588 #define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
58589 #define F_ADVANCE_PING_PONG V_ADVANCE_PING_PONG(1U)
58591 #define S_ATEST_MUX_CTL0 3
58592 #define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
58593 #define F_ATEST_MUX_CTL0 V_ATEST_MUX_CTL0(1U)
58595 #define S_ATEST_MUX_CTL1 2
58596 #define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
58597 #define F_ATEST_MUX_CTL1 V_ATEST_MUX_CTL1(1U)
58599 #define S_ATEST_MUX_CTL2 1
58600 #define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
58601 #define F_ATEST_MUX_CTL2 V_ATEST_MUX_CTL2(1U)
58603 #define S_ATEST_MUX_CTL3 0
58604 #define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
58605 #define F_ATEST_MUX_CTL3 V_ATEST_MUX_CTL3(1U)
58607 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
58609 #define S_QUAD0_CLK16_BIT0 15
58610 #define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
58611 #define F_QUAD0_CLK16_BIT0 V_QUAD0_CLK16_BIT0(1U)
58613 #define S_QUAD1_CLK16_BIT1 14
58614 #define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
58615 #define F_QUAD1_CLK16_BIT1 V_QUAD1_CLK16_BIT1(1U)
58617 #define S_QUAD2_CLK16_BIT2 13
58618 #define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
58619 #define F_QUAD2_CLK16_BIT2 V_QUAD2_CLK16_BIT2(1U)
58621 #define S_QUAD3_CLK16_BIT3 12
58622 #define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
58623 #define F_QUAD3_CLK16_BIT3 V_QUAD3_CLK16_BIT3(1U)
58625 #define S_QUAD0_CLK18_BIT4 11
58626 #define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
58627 #define F_QUAD0_CLK18_BIT4 V_QUAD0_CLK18_BIT4(1U)
58629 #define S_QUAD1_CLK18_BIT5 10
58630 #define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
58631 #define F_QUAD1_CLK18_BIT5 V_QUAD1_CLK18_BIT5(1U)
58633 #define S_QUAD2_CLK20_BIT6 9
58634 #define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
58635 #define F_QUAD2_CLK20_BIT6 V_QUAD2_CLK20_BIT6(1U)
58637 #define S_QUAD3_CLK20_BIT7 8
58638 #define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
58639 #define F_QUAD3_CLK20_BIT7 V_QUAD3_CLK20_BIT7(1U)
58641 #define S_QUAD2_CLK22_BIT8 7
58642 #define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
58643 #define F_QUAD2_CLK22_BIT8 V_QUAD2_CLK22_BIT8(1U)
58645 #define S_QUAD3_CLK22_BIT9 6
58646 #define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
58647 #define F_QUAD3_CLK22_BIT9 V_QUAD3_CLK22_BIT9(1U)
58649 #define S_CLK16_SINGLE_ENDED_BIT10 5
58650 #define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
58651 #define F_CLK16_SINGLE_ENDED_BIT10 V_CLK16_SINGLE_ENDED_BIT10(1U)
58653 #define S_CLK18_SINGLE_ENDED_BIT11 4
58654 #define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
58655 #define F_CLK18_SINGLE_ENDED_BIT11 V_CLK18_SINGLE_ENDED_BIT11(1U)
58657 #define S_CLK20_SINGLE_ENDED_BIT12 3
58658 #define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
58659 #define F_CLK20_SINGLE_ENDED_BIT12 V_CLK20_SINGLE_ENDED_BIT12(1U)
58661 #define S_CLK22_SINGLE_ENDED_BIT13 2
58662 #define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
58663 #define F_CLK22_SINGLE_ENDED_BIT13 V_CLK22_SINGLE_ENDED_BIT13(1U)
58665 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
58667 #define S_QUAD2_CLK18_BIT14 1
58668 #define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
58669 #define F_QUAD2_CLK18_BIT14 V_QUAD2_CLK18_BIT14(1U)
58671 #define S_QUAD3_CLK18_BIT15 0
58672 #define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
58673 #define F_QUAD3_CLK18_BIT15 V_QUAD3_CLK18_BIT15(1U)
58675 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
58677 #define S_PEAK_AMP_CTL_SIDE0 13
58678 #define M_PEAK_AMP_CTL_SIDE0 0x7U
58679 #define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
58680 #define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
58682 #define S_PEAK_AMP_CTL_SIDE1 9
58683 #define M_PEAK_AMP_CTL_SIDE1 0x7U
58684 #define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
58685 #define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
58687 #define S_SXMCVREF_0_3 4
58688 #define M_SXMCVREF_0_3 0xfU
58689 #define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
58690 #define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
58692 #define S_SXPODVREF 3
58693 #define V_SXPODVREF(x) ((x) << S_SXPODVREF)
58694 #define F_SXPODVREF V_SXPODVREF(1U)
58696 #define S_DISABLE_TERMINATION 2
58697 #define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
58698 #define F_DISABLE_TERMINATION V_DISABLE_TERMINATION(1U)
58700 #define S_READ_CENTERING_MODE 0
58701 #define M_READ_CENTERING_MODE 0x3U
58702 #define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
58703 #define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
58705 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
58707 #define S_SYSCLK_PHASE_ALIGN_RESET 6
58708 #define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
58709 #define F_SYSCLK_PHASE_ALIGN_RESET V_SYSCLK_PHASE_ALIGN_RESET(1U)
58711 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
58713 #define S_DIGITAL_EYE_EN 15
58714 #define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
58715 #define F_DIGITAL_EYE_EN V_DIGITAL_EYE_EN(1U)
58718 #define V_BUMP(x) ((x) << S_BUMP)
58719 #define F_BUMP V_BUMP(1U)
58721 #define S_TRIG_PERIOD 13
58722 #define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
58723 #define F_TRIG_PERIOD V_TRIG_PERIOD(1U)
58725 #define S_CNTL_POL 12
58726 #define V_CNTL_POL(x) ((x) << S_CNTL_POL)
58727 #define F_CNTL_POL V_CNTL_POL(1U)
58729 #define S_CNTL_SRC 8
58730 #define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
58731 #define F_CNTL_SRC V_CNTL_SRC(1U)
58733 #define S_DIGITAL_EYE_VALUE 0
58734 #define M_DIGITAL_EYE_VALUE 0xffU
58735 #define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
58736 #define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
58738 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
58740 #define S_DQSCLK_SELECT0 14
58741 #define M_DQSCLK_SELECT0 0x3U
58742 #define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
58743 #define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
58745 #define S_RDCLK_SELECT0 12
58746 #define M_RDCLK_SELECT0 0x3U
58747 #define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
58748 #define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
58750 #define S_DQSCLK_SELECT1 10
58751 #define M_DQSCLK_SELECT1 0x3U
58752 #define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
58753 #define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
58755 #define S_RDCLK_SELECT1 8
58756 #define M_RDCLK_SELECT1 0x3U
58757 #define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
58758 #define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
58760 #define S_DQSCLK_SELECT2 6
58761 #define M_DQSCLK_SELECT2 0x3U
58762 #define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
58763 #define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
58765 #define S_RDCLK_SELECT2 4
58766 #define M_RDCLK_SELECT2 0x3U
58767 #define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
58768 #define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
58770 #define S_DQSCLK_SELECT3 2
58771 #define M_DQSCLK_SELECT3 0x3U
58772 #define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
58773 #define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
58775 #define S_RDCLK_SELECT3 0
58776 #define M_RDCLK_SELECT3 0x3U
58777 #define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
58778 #define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
58780 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
58782 #define S_MIN_RD_EYE_SIZE 8
58783 #define M_MIN_RD_EYE_SIZE 0x3fU
58784 #define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
58785 #define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
58787 #define S_MAX_DQS_DRIFT 0
58788 #define M_MAX_DQS_DRIFT 0x3fU
58789 #define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
58790 #define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
58792 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
58794 #define S_HS_PROBE_A_SEL 11
58795 #define M_HS_PROBE_A_SEL 0x1fU
58796 #define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
58797 #define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
58799 #define S_HS_PROBE_B_SEL 6
58800 #define M_HS_PROBE_B_SEL 0x1fU
58801 #define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
58802 #define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
58804 #define S_RD_DEBUG_SEL 3
58805 #define M_RD_DEBUG_SEL 0x7U
58806 #define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
58807 #define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
58809 #define S_WR_DEBUG_SEL 0
58810 #define M_WR_DEBUG_SEL 0x7U
58811 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
58812 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
58814 #define S_DP18_HS_PROBE_A_SEL 11
58815 #define M_DP18_HS_PROBE_A_SEL 0x1fU
58816 #define V_DP18_HS_PROBE_A_SEL(x) ((x) << S_DP18_HS_PROBE_A_SEL)
58817 #define G_DP18_HS_PROBE_A_SEL(x) (((x) >> S_DP18_HS_PROBE_A_SEL) & M_DP18_HS_PROBE_A_SEL)
58819 #define S_DP18_HS_PROBE_B_SEL 6
58820 #define M_DP18_HS_PROBE_B_SEL 0x1fU
58821 #define V_DP18_HS_PROBE_B_SEL(x) ((x) << S_DP18_HS_PROBE_B_SEL)
58822 #define G_DP18_HS_PROBE_B_SEL(x) (((x) >> S_DP18_HS_PROBE_B_SEL) & M_DP18_HS_PROBE_B_SEL)
58824 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
58826 #define S_OFFSET_BITS1_7 8
58827 #define M_OFFSET_BITS1_7 0x7fU
58828 #define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
58829 #define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
58831 #define S_OFFSET_BITS9_15 0
58832 #define M_OFFSET_BITS9_15 0x7fU
58833 #define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
58834 #define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
58836 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
58837 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
58839 #define S_LEADING_EDGE_NOT_FOUND_0 0
58840 #define M_LEADING_EDGE_NOT_FOUND_0 0xffffU
58841 #define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
58842 #define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
58844 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
58846 #define S_LEADING_EDGE_NOT_FOUND_1 8
58847 #define M_LEADING_EDGE_NOT_FOUND_1 0xffU
58848 #define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
58849 #define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
58851 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
58853 #define S_TRAILING_EDGE_NOT_FOUND 0
58854 #define M_TRAILING_EDGE_NOT_FOUND 0xffffU
58855 #define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
58856 #define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
58858 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
58860 #define S_TRAILING_EDGE_NOT_FOUND_16_23 8
58861 #define M_TRAILING_EDGE_NOT_FOUND_16_23 0xffU
58862 #define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
58863 #define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
58865 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
58867 #define S_DYN_POWER_CNTL_EN 15
58868 #define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
58869 #define F_DYN_POWER_CNTL_EN V_DYN_POWER_CNTL_EN(1U)
58871 #define S_DYN_MCTERM_CNTL_EN 14
58872 #define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
58873 #define F_DYN_MCTERM_CNTL_EN V_DYN_MCTERM_CNTL_EN(1U)
58875 #define S_DYN_RX_GATE_CNTL_EN 13
58876 #define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
58877 #define F_DYN_RX_GATE_CNTL_EN V_DYN_RX_GATE_CNTL_EN(1U)
58879 #define S_CALGATE_ON 12
58880 #define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
58881 #define F_CALGATE_ON V_CALGATE_ON(1U)
58883 #define S_PER_RDCLK_UPDATE_DIS 11
58884 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
58885 #define F_PER_RDCLK_UPDATE_DIS V_PER_RDCLK_UPDATE_DIS(1U)
58887 #define S_DQS_ALIGN_BY_QUAD 4
58888 #define V_DQS_ALIGN_BY_QUAD(x) ((x) << S_DQS_ALIGN_BY_QUAD)
58889 #define F_DQS_ALIGN_BY_QUAD V_DQS_ALIGN_BY_QUAD(1U)
58891 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
58893 #define S_DQS_GATE_DELAY_N0 12
58894 #define M_DQS_GATE_DELAY_N0 0x7U
58895 #define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
58896 #define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
58898 #define S_DQS_GATE_DELAY_N1 8
58899 #define M_DQS_GATE_DELAY_N1 0x7U
58900 #define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
58901 #define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
58903 #define S_DQS_GATE_DELAY_N2 4
58904 #define M_DQS_GATE_DELAY_N2 0x7U
58905 #define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
58906 #define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
58908 #define S_DQS_GATE_DELAY_N3 0
58909 #define M_DQS_GATE_DELAY_N3 0x7U
58910 #define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
58911 #define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
58913 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
58915 #define S_NO_EYE_DETECTED 15
58916 #define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
58917 #define F_NO_EYE_DETECTED V_NO_EYE_DETECTED(1U)
58919 #define S_LEADING_EDGE_FOUND 14
58920 #define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
58921 #define F_LEADING_EDGE_FOUND V_LEADING_EDGE_FOUND(1U)
58923 #define S_TRAILING_EDGE_FOUND 13
58924 #define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
58925 #define F_TRAILING_EDGE_FOUND V_TRAILING_EDGE_FOUND(1U)
58927 #define S_INCOMPLETE_RD_CAL_N0 12
58928 #define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
58929 #define F_INCOMPLETE_RD_CAL_N0 V_INCOMPLETE_RD_CAL_N0(1U)
58931 #define S_INCOMPLETE_RD_CAL_N1 11
58932 #define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
58933 #define F_INCOMPLETE_RD_CAL_N1 V_INCOMPLETE_RD_CAL_N1(1U)
58935 #define S_INCOMPLETE_RD_CAL_N2 10
58936 #define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
58937 #define F_INCOMPLETE_RD_CAL_N2 V_INCOMPLETE_RD_CAL_N2(1U)
58939 #define S_INCOMPLETE_RD_CAL_N3 9
58940 #define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
58941 #define F_INCOMPLETE_RD_CAL_N3 V_INCOMPLETE_RD_CAL_N3(1U)
58943 #define S_COARSE_PATTERN_ERR_N0 8
58944 #define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
58945 #define F_COARSE_PATTERN_ERR_N0 V_COARSE_PATTERN_ERR_N0(1U)
58947 #define S_COARSE_PATTERN_ERR_N1 7
58948 #define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
58949 #define F_COARSE_PATTERN_ERR_N1 V_COARSE_PATTERN_ERR_N1(1U)
58951 #define S_COARSE_PATTERN_ERR_N2 6
58952 #define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
58953 #define F_COARSE_PATTERN_ERR_N2 V_COARSE_PATTERN_ERR_N2(1U)
58955 #define S_COARSE_PATTERN_ERR_N3 5
58956 #define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
58957 #define F_COARSE_PATTERN_ERR_N3 V_COARSE_PATTERN_ERR_N3(1U)
58959 #define S_EYE_CLIPPING 4
58960 #define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
58961 #define F_EYE_CLIPPING V_EYE_CLIPPING(1U)
58964 #define V_NO_DQS(x) ((x) << S_NO_DQS)
58965 #define F_NO_DQS V_NO_DQS(1U)
58967 #define S_NO_LOCK 2
58968 #define V_NO_LOCK(x) ((x) << S_NO_LOCK)
58969 #define F_NO_LOCK V_NO_LOCK(1U)
58971 #define S_DRIFT_ERROR 1
58972 #define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
58973 #define F_DRIFT_ERROR V_DRIFT_ERROR(1U)
58975 #define S_MIN_EYE 0
58976 #define V_MIN_EYE(x) ((x) << S_MIN_EYE)
58977 #define F_MIN_EYE V_MIN_EYE(1U)
58979 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
58981 #define S_NO_EYE_DETECTED_MASK 15
58982 #define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
58983 #define F_NO_EYE_DETECTED_MASK V_NO_EYE_DETECTED_MASK(1U)
58985 #define S_LEADING_EDGE_FOUND_MASK 14
58986 #define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
58987 #define F_LEADING_EDGE_FOUND_MASK V_LEADING_EDGE_FOUND_MASK(1U)
58989 #define S_TRAILING_EDGE_FOUND_MASK 13
58990 #define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
58991 #define F_TRAILING_EDGE_FOUND_MASK V_TRAILING_EDGE_FOUND_MASK(1U)
58993 #define S_INCOMPLETE_RD_CAL_N0_MASK 12
58994 #define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
58995 #define F_INCOMPLETE_RD_CAL_N0_MASK V_INCOMPLETE_RD_CAL_N0_MASK(1U)
58997 #define S_INCOMPLETE_RD_CAL_N1_MASK 11
58998 #define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
58999 #define F_INCOMPLETE_RD_CAL_N1_MASK V_INCOMPLETE_RD_CAL_N1_MASK(1U)
59001 #define S_INCOMPLETE_RD_CAL_N2_MASK 10
59002 #define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
59003 #define F_INCOMPLETE_RD_CAL_N2_MASK V_INCOMPLETE_RD_CAL_N2_MASK(1U)
59005 #define S_INCOMPLETE_RD_CAL_N3_MASK 9
59006 #define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
59007 #define F_INCOMPLETE_RD_CAL_N3_MASK V_INCOMPLETE_RD_CAL_N3_MASK(1U)
59009 #define S_COARSE_PATTERN_ERR_N0_MASK 8
59010 #define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
59011 #define F_COARSE_PATTERN_ERR_N0_MASK V_COARSE_PATTERN_ERR_N0_MASK(1U)
59013 #define S_COARSE_PATTERN_ERR_N1_MASK 7
59014 #define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
59015 #define F_COARSE_PATTERN_ERR_N1_MASK V_COARSE_PATTERN_ERR_N1_MASK(1U)
59017 #define S_COARSE_PATTERN_ERR_N2_MASK 6
59018 #define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
59019 #define F_COARSE_PATTERN_ERR_N2_MASK V_COARSE_PATTERN_ERR_N2_MASK(1U)
59021 #define S_COARSE_PATTERN_ERR_N3_MASK 5
59022 #define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
59023 #define F_COARSE_PATTERN_ERR_N3_MASK V_COARSE_PATTERN_ERR_N3_MASK(1U)
59025 #define S_EYE_CLIPPING_MASK 4
59026 #define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
59027 #define F_EYE_CLIPPING_MASK V_EYE_CLIPPING_MASK(1U)
59029 #define S_NO_DQS_MASK 3
59030 #define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
59031 #define F_NO_DQS_MASK V_NO_DQS_MASK(1U)
59033 #define S_NO_LOCK_MASK 2
59034 #define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
59035 #define F_NO_LOCK_MASK V_NO_LOCK_MASK(1U)
59037 #define S_DRIFT_ERROR_MASK 1
59038 #define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
59039 #define F_DRIFT_ERROR_MASK V_DRIFT_ERROR_MASK(1U)
59041 #define S_MIN_EYE_MASK 0
59042 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
59043 #define F_MIN_EYE_MASK V_MIN_EYE_MASK(1U)
59045 #define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
59047 #define S_PRBS_WAIT 14
59048 #define M_PRBS_WAIT 0x3U
59049 #define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT)
59050 #define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT)
59052 #define S_PRBS_SYNC_EARLY 13
59053 #define V_PRBS_SYNC_EARLY(x) ((x) << S_PRBS_SYNC_EARLY)
59054 #define F_PRBS_SYNC_EARLY V_PRBS_SYNC_EARLY(1U)
59056 #define S_RD_DELAY_EARLY 12
59057 #define V_RD_DELAY_EARLY(x) ((x) << S_RD_DELAY_EARLY)
59058 #define F_RD_DELAY_EARLY V_RD_DELAY_EARLY(1U)
59060 #define S_SS_QUAD_CAL 10
59061 #define V_SS_QUAD_CAL(x) ((x) << S_SS_QUAD_CAL)
59062 #define F_SS_QUAD_CAL V_SS_QUAD_CAL(1U)
59064 #define S_SS_QUAD 8
59065 #define M_SS_QUAD 0x3U
59066 #define V_SS_QUAD(x) ((x) << S_SS_QUAD)
59067 #define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD)
59069 #define S_SS_RD_DELAY 7
59070 #define V_SS_RD_DELAY(x) ((x) << S_SS_RD_DELAY)
59071 #define F_SS_RD_DELAY V_SS_RD_DELAY(1U)
59073 #define S_FORCE_HI_Z 6
59074 #define V_FORCE_HI_Z(x) ((x) << S_FORCE_HI_Z)
59075 #define F_FORCE_HI_Z V_FORCE_HI_Z(1U)
59077 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
59079 #define S_CLK_LEVEL 14
59080 #define M_CLK_LEVEL 0x3U
59081 #define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
59082 #define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
59084 #define S_FINE_STEPPING 13
59085 #define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
59086 #define F_FINE_STEPPING V_FINE_STEPPING(1U)
59089 #define V_DONE(x) ((x) << S_DONE)
59090 #define F_DONE V_DONE(1U)
59092 #define S_WL_ERR_CLK16_ST 11
59093 #define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
59094 #define F_WL_ERR_CLK16_ST V_WL_ERR_CLK16_ST(1U)
59096 #define S_WL_ERR_CLK18_ST 10
59097 #define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
59098 #define F_WL_ERR_CLK18_ST V_WL_ERR_CLK18_ST(1U)
59100 #define S_WL_ERR_CLK20_ST 9
59101 #define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
59102 #define F_WL_ERR_CLK20_ST V_WL_ERR_CLK20_ST(1U)
59104 #define S_WL_ERR_CLK22_ST 8
59105 #define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
59106 #define F_WL_ERR_CLK22_ST V_WL_ERR_CLK22_ST(1U)
59108 #define S_ZERO_DETECTED 7
59109 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
59110 #define F_ZERO_DETECTED V_ZERO_DETECTED(1U)
59112 #define S_WR_LVL_DONE 12
59113 #define V_WR_LVL_DONE(x) ((x) << S_WR_LVL_DONE)
59114 #define F_WR_LVL_DONE V_WR_LVL_DONE(1U)
59116 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
59118 #define S_BIT_CENTERED 11
59119 #define M_BIT_CENTERED 0x1fU
59120 #define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
59121 #define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
59123 #define S_SMALL_STEP_LEFT 10
59124 #define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
59125 #define F_SMALL_STEP_LEFT V_SMALL_STEP_LEFT(1U)
59127 #define S_BIG_STEP_RIGHT 9
59128 #define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
59129 #define F_BIG_STEP_RIGHT V_BIG_STEP_RIGHT(1U)
59131 #define S_MATCH_STEP_RIGHT 8
59132 #define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
59133 #define F_MATCH_STEP_RIGHT V_MATCH_STEP_RIGHT(1U)
59135 #define S_JUMP_BACK_RIGHT 7
59136 #define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
59137 #define F_JUMP_BACK_RIGHT V_JUMP_BACK_RIGHT(1U)
59139 #define S_SMALL_STEP_RIGHT 6
59140 #define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
59141 #define F_SMALL_STEP_RIGHT V_SMALL_STEP_RIGHT(1U)
59144 #define V_DDONE(x) ((x) << S_DDONE)
59145 #define F_DDONE V_DDONE(1U)
59147 #define S_WR_CNTR_DONE 5
59148 #define V_WR_CNTR_DONE(x) ((x) << S_WR_CNTR_DONE)
59149 #define F_WR_CNTR_DONE V_WR_CNTR_DONE(1U)
59151 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
59153 #define S_FW_LEFT_SIDE 5
59154 #define M_FW_LEFT_SIDE 0x7ffU
59155 #define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
59156 #define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
59158 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
59160 #define S_FW_RIGHT_SIDE 5
59161 #define M_FW_RIGHT_SIDE 0x7ffU
59162 #define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
59163 #define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
59165 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
59167 #define S_WL_ERR_CLK16 15
59168 #define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
59169 #define F_WL_ERR_CLK16 V_WL_ERR_CLK16(1U)
59171 #define S_WL_ERR_CLK18 14
59172 #define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
59173 #define F_WL_ERR_CLK18 V_WL_ERR_CLK18(1U)
59175 #define S_WL_ERR_CLK20 13
59176 #define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
59177 #define F_WL_ERR_CLK20 V_WL_ERR_CLK20(1U)
59179 #define S_WL_ERR_CLK22 12
59180 #define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
59181 #define F_WL_ERR_CLK22 V_WL_ERR_CLK22(1U)
59183 #define S_VALID_NS_BIG_L 7
59184 #define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
59185 #define F_VALID_NS_BIG_L V_VALID_NS_BIG_L(1U)
59187 #define S_INVALID_NS_SMALL_L 6
59188 #define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
59189 #define F_INVALID_NS_SMALL_L V_INVALID_NS_SMALL_L(1U)
59191 #define S_VALID_NS_BIG_R 5
59192 #define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
59193 #define F_VALID_NS_BIG_R V_VALID_NS_BIG_R(1U)
59195 #define S_INVALID_NS_BIG_R 4
59196 #define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
59197 #define F_INVALID_NS_BIG_R V_INVALID_NS_BIG_R(1U)
59199 #define S_VALID_NS_JUMP_BACK 3
59200 #define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
59201 #define F_VALID_NS_JUMP_BACK V_VALID_NS_JUMP_BACK(1U)
59203 #define S_INVALID_NS_SMALL_R 2
59204 #define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
59205 #define F_INVALID_NS_SMALL_R V_INVALID_NS_SMALL_R(1U)
59207 #define S_OFFSET_ERR 1
59208 #define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
59209 #define F_OFFSET_ERR V_OFFSET_ERR(1U)
59211 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
59213 #define S_WL_ERR_CLK16_MASK 15
59214 #define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
59215 #define F_WL_ERR_CLK16_MASK V_WL_ERR_CLK16_MASK(1U)
59217 #define S_WL_ERR_CLK18_MASK 14
59218 #define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
59219 #define F_WL_ERR_CLK18_MASK V_WL_ERR_CLK18_MASK(1U)
59221 #define S_WL_ERR_CLK20_MASK 13
59222 #define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
59223 #define F_WL_ERR_CLK20_MASK V_WL_ERR_CLK20_MASK(1U)
59225 #define S_WR_ERR_CLK22_MASK 12
59226 #define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
59227 #define F_WR_ERR_CLK22_MASK V_WR_ERR_CLK22_MASK(1U)
59229 #define S_VALID_NS_BIG_L_MASK 7
59230 #define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
59231 #define F_VALID_NS_BIG_L_MASK V_VALID_NS_BIG_L_MASK(1U)
59233 #define S_INVALID_NS_SMALL_L_MASK 6
59234 #define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
59235 #define F_INVALID_NS_SMALL_L_MASK V_INVALID_NS_SMALL_L_MASK(1U)
59237 #define S_VALID_NS_BIG_R_MASK 5
59238 #define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
59239 #define F_VALID_NS_BIG_R_MASK V_VALID_NS_BIG_R_MASK(1U)
59241 #define S_INVALID_NS_BIG_R_MASK 4
59242 #define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
59243 #define F_INVALID_NS_BIG_R_MASK V_INVALID_NS_BIG_R_MASK(1U)
59245 #define S_VALID_NS_JUMP_BACK_MASK 3
59246 #define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
59247 #define F_VALID_NS_JUMP_BACK_MASK V_VALID_NS_JUMP_BACK_MASK(1U)
59249 #define S_INVALID_NS_SMALL_R_MASK 2
59250 #define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
59251 #define F_INVALID_NS_SMALL_R_MASK V_INVALID_NS_SMALL_R_MASK(1U)
59253 #define S_OFFSET_ERR_MASK 1
59254 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
59255 #define F_OFFSET_ERR_MASK V_OFFSET_ERR_MASK(1U)
59257 #define S_DQS_REC_LOW_POWER 11
59258 #define V_DQS_REC_LOW_POWER(x) ((x) << S_DQS_REC_LOW_POWER)
59259 #define F_DQS_REC_LOW_POWER V_DQS_REC_LOW_POWER(1U)
59261 #define S_DQ_REC_LOW_POWER 10
59262 #define V_DQ_REC_LOW_POWER(x) ((x) << S_DQ_REC_LOW_POWER)
59263 #define F_DQ_REC_LOW_POWER V_DQ_REC_LOW_POWER(1U)
59265 #define S_ADVANCE_PR_VALUE 0
59266 #define V_ADVANCE_PR_VALUE(x) ((x) << S_ADVANCE_PR_VALUE)
59267 #define F_ADVANCE_PR_VALUE V_ADVANCE_PR_VALUE(1U)
59269 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
59271 #define S_CHECKER_RESET 14
59272 #define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
59273 #define F_CHECKER_RESET V_CHECKER_RESET(1U)
59275 #define S_DP18_DFT_SYNC 6
59276 #define M_DP18_DFT_SYNC 0x3fU
59277 #define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
59278 #define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
59281 #define M_ERROR 0x3fU
59282 #define V_ERROR(x) ((x) << S_ERROR)
59283 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
59285 #define S_CHECKER_ENABLE 15
59286 #define V_CHECKER_ENABLE(x) ((x) << S_CHECKER_ENABLE)
59287 #define F_CHECKER_ENABLE V_CHECKER_ENABLE(1U)
59289 #define S_DP18_DFT_ERROR 0
59290 #define M_DP18_DFT_ERROR 0x3fU
59291 #define V_DP18_DFT_ERROR(x) ((x) << S_DP18_DFT_ERROR)
59292 #define G_DP18_DFT_ERROR(x) (((x) >> S_DP18_DFT_ERROR) & M_DP18_DFT_ERROR)
59294 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
59296 #define S_SYSCLK_RDCLK_OFFSET 8
59297 #define M_SYSCLK_RDCLK_OFFSET 0x7fU
59298 #define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET)
59299 #define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET)
59301 #define S_SYSCLK_DQSCLK_OFFSET 0
59302 #define M_SYSCLK_DQSCLK_OFFSET 0x7fU
59303 #define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET)
59304 #define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET)
59306 #define S_T6_SYSCLK_DQSCLK_OFFSET 8
59307 #define M_T6_SYSCLK_DQSCLK_OFFSET 0x7fU
59308 #define V_T6_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_T6_SYSCLK_DQSCLK_OFFSET)
59309 #define G_T6_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_DQSCLK_OFFSET) & M_T6_SYSCLK_DQSCLK_OFFSET)
59311 #define S_T6_SYSCLK_RDCLK_OFFSET 0
59312 #define M_T6_SYSCLK_RDCLK_OFFSET 0x7fU
59313 #define V_T6_SYSCLK_RDCLK_OFFSET(x) ((x) << S_T6_SYSCLK_RDCLK_OFFSET)
59314 #define G_T6_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_RDCLK_OFFSET) & M_T6_SYSCLK_RDCLK_OFFSET)
59316 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
59317 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
59319 #define S_DQSCLK_ROT_CLK_N0_N2 8
59320 #define M_DQSCLK_ROT_CLK_N0_N2 0x7fU
59321 #define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
59322 #define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
59324 #define S_DQSCLK_ROT_CLK_N1_N3 0
59325 #define M_DQSCLK_ROT_CLK_N1_N3 0x7fU
59326 #define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
59327 #define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
59329 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
59330 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
59332 #define S_MEMINTD00_POS 14
59333 #define M_MEMINTD00_POS 0x3U
59334 #define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
59335 #define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
59337 #define S_MEMINTD01_PO 12
59338 #define M_MEMINTD01_PO 0x3U
59339 #define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
59340 #define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
59342 #define S_MEMINTD02_POS 10
59343 #define M_MEMINTD02_POS 0x3U
59344 #define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
59345 #define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
59347 #define S_MEMINTD03_POS 8
59348 #define M_MEMINTD03_POS 0x3U
59349 #define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
59350 #define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
59352 #define S_MEMINTD04_POS 6
59353 #define M_MEMINTD04_POS 0x3U
59354 #define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
59355 #define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
59357 #define S_MEMINTD05_POS 4
59358 #define M_MEMINTD05_POS 0x3U
59359 #define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
59360 #define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
59362 #define S_MEMINTD06_POS 2
59363 #define M_MEMINTD06_POS 0x3U
59364 #define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
59365 #define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
59367 #define S_MEMINTD07_POS 0
59368 #define M_MEMINTD07_POS 0x3U
59369 #define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
59370 #define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
59372 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
59374 #define S_MEMINTD08_POS 14
59375 #define M_MEMINTD08_POS 0x3U
59376 #define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
59377 #define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
59379 #define S_MEMINTD09_POS 12
59380 #define M_MEMINTD09_POS 0x3U
59381 #define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
59382 #define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
59384 #define S_MEMINTD10_POS 10
59385 #define M_MEMINTD10_POS 0x3U
59386 #define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
59387 #define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
59389 #define S_MEMINTD11_POS 8
59390 #define M_MEMINTD11_POS 0x3U
59391 #define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
59392 #define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
59394 #define S_MEMINTD12_POS 6
59395 #define M_MEMINTD12_POS 0x3U
59396 #define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
59397 #define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
59399 #define S_MEMINTD13_POS 4
59400 #define M_MEMINTD13_POS 0x3U
59401 #define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
59402 #define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
59404 #define S_MEMINTD14_POS 2
59405 #define M_MEMINTD14_POS 0x3U
59406 #define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
59407 #define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
59409 #define S_MEMINTD15_POS 0
59410 #define M_MEMINTD15_POS 0x3U
59411 #define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
59412 #define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
59414 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
59416 #define S_MEMINTD16_POS 14
59417 #define M_MEMINTD16_POS 0x3U
59418 #define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
59419 #define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
59421 #define S_MEMINTD17_POS 12
59422 #define M_MEMINTD17_POS 0x3U
59423 #define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
59424 #define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
59426 #define S_MEMINTD18_POS 10
59427 #define M_MEMINTD18_POS 0x3U
59428 #define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
59429 #define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
59431 #define S_MEMINTD19_POS 8
59432 #define M_MEMINTD19_POS 0x3U
59433 #define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
59434 #define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
59436 #define S_MEMINTD20_POS 6
59437 #define M_MEMINTD20_POS 0x3U
59438 #define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
59439 #define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
59441 #define S_MEMINTD21_POS 4
59442 #define M_MEMINTD21_POS 0x3U
59443 #define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
59444 #define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
59446 #define S_MEMINTD22_POS 2
59447 #define M_MEMINTD22_POS 0x3U
59448 #define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
59449 #define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
59451 #define S_MEMINTD23_POS 0
59452 #define M_MEMINTD23_POS 0x3U
59453 #define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
59454 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
59456 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
59458 #define S_DQS_ALIGN_SM 11
59459 #define M_DQS_ALIGN_SM 0x1fU
59460 #define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM)
59461 #define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM)
59463 #define S_DQS_ALIGN_CNTR 7
59464 #define M_DQS_ALIGN_CNTR 0xfU
59465 #define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR)
59466 #define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR)
59468 #define S_ITERATION_CNTR 6
59469 #define V_ITERATION_CNTR(x) ((x) << S_ITERATION_CNTR)
59470 #define F_ITERATION_CNTR V_ITERATION_CNTR(1U)
59472 #define S_DQS_ALIGN_ITER_CNTR 0
59473 #define M_DQS_ALIGN_ITER_CNTR 0x3fU
59474 #define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR)
59475 #define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR)
59477 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
59479 #define S_CALIBRATE_BIT 13
59480 #define M_CALIBRATE_BIT 0x7U
59481 #define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT)
59482 #define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT)
59484 #define S_DQS_ALIGN_QUAD 11
59485 #define M_DQS_ALIGN_QUAD 0x3U
59486 #define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD)
59487 #define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD)
59489 #define S_DQS_QUAD_CONFIG 8
59490 #define M_DQS_QUAD_CONFIG 0x7U
59491 #define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG)
59492 #define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG)
59494 #define S_OPERATE_MODE 4
59495 #define M_OPERATE_MODE 0xfU
59496 #define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE)
59497 #define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE)
59499 #define S_EN_DQS_OFFSET 3
59500 #define V_EN_DQS_OFFSET(x) ((x) << S_EN_DQS_OFFSET)
59501 #define F_EN_DQS_OFFSET V_EN_DQS_OFFSET(1U)
59503 #define S_DQS_ALIGN_JITTER 2
59504 #define V_DQS_ALIGN_JITTER(x) ((x) << S_DQS_ALIGN_JITTER)
59505 #define F_DQS_ALIGN_JITTER V_DQS_ALIGN_JITTER(1U)
59507 #define S_DIS_CLK_GATE 1
59508 #define V_DIS_CLK_GATE(x) ((x) << S_DIS_CLK_GATE)
59509 #define F_DIS_CLK_GATE V_DIS_CLK_GATE(1U)
59511 #define S_MAX_DQS_ITER 0
59512 #define V_MAX_DQS_ITER(x) ((x) << S_MAX_DQS_ITER)
59513 #define F_MAX_DQS_ITER V_MAX_DQS_ITER(1U)
59515 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
59517 #define S_DQS_OFFSET 8
59518 #define M_DQS_OFFSET 0x7fU
59519 #define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
59520 #define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
59522 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
59524 #define S_WR_DELAY 6
59525 #define M_WR_DELAY 0x3ffU
59526 #define V_WR_DELAY(x) ((x) << S_WR_DELAY)
59527 #define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
59529 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
59530 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
59531 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
59532 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
59533 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
59534 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
59535 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
59536 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
59537 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
59538 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
59539 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
59540 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
59541 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
59542 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
59543 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
59544 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
59545 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
59546 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
59547 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
59548 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
59549 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
59550 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
59551 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
59552 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
59554 #define S_RD_DELAY_BITS0_6 9
59555 #define M_RD_DELAY_BITS0_6 0x7fU
59556 #define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
59557 #define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
59559 #define S_RD_DELAY_BITS8_14 1
59560 #define M_RD_DELAY_BITS8_14 0x7fU
59561 #define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
59562 #define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
59564 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
59565 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
59566 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
59567 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
59568 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
59569 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
59570 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
59571 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
59572 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
59573 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
59574 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
59575 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
59577 #define S_INITIAL_DQS_ROT_N0_N2 8
59578 #define M_INITIAL_DQS_ROT_N0_N2 0x7fU
59579 #define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
59580 #define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
59582 #define S_INITIAL_DQS_ROT_N1_N3 0
59583 #define M_INITIAL_DQS_ROT_N1_N3 0x7fU
59584 #define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
59585 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
59587 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
59588 #define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
59590 #define S_WRCLK_CALIB_DONE 15
59591 #define V_WRCLK_CALIB_DONE(x) ((x) << S_WRCLK_CALIB_DONE)
59592 #define F_WRCLK_CALIB_DONE V_WRCLK_CALIB_DONE(1U)
59594 #define S_VALUE_UPDATED 14
59595 #define V_VALUE_UPDATED(x) ((x) << S_VALUE_UPDATED)
59596 #define F_VALUE_UPDATED V_VALUE_UPDATED(1U)
59598 #define S_FAIL_PASS_V 13
59599 #define V_FAIL_PASS_V(x) ((x) << S_FAIL_PASS_V)
59600 #define F_FAIL_PASS_V V_FAIL_PASS_V(1U)
59602 #define S_PASS_FAIL_V 12
59603 #define V_PASS_FAIL_V(x) ((x) << S_PASS_FAIL_V)
59604 #define F_PASS_FAIL_V V_PASS_FAIL_V(1U)
59606 #define S_FP_PF_EDGE_NF 11
59607 #define V_FP_PF_EDGE_NF(x) ((x) << S_FP_PF_EDGE_NF)
59608 #define F_FP_PF_EDGE_NF V_FP_PF_EDGE_NF(1U)
59610 #define S_NON_SYMETRIC 10
59611 #define V_NON_SYMETRIC(x) ((x) << S_NON_SYMETRIC)
59612 #define F_NON_SYMETRIC V_NON_SYMETRIC(1U)
59614 #define S_FULL_RANGE 8
59615 #define V_FULL_RANGE(x) ((x) << S_FULL_RANGE)
59616 #define F_FULL_RANGE V_FULL_RANGE(1U)
59618 #define S_QUAD3_EDGES 7
59619 #define V_QUAD3_EDGES(x) ((x) << S_QUAD3_EDGES)
59620 #define F_QUAD3_EDGES V_QUAD3_EDGES(1U)
59622 #define S_QUAD2_EDGES 6
59623 #define V_QUAD2_EDGES(x) ((x) << S_QUAD2_EDGES)
59624 #define F_QUAD2_EDGES V_QUAD2_EDGES(1U)
59626 #define S_QUAD1_EDGES 5
59627 #define V_QUAD1_EDGES(x) ((x) << S_QUAD1_EDGES)
59628 #define F_QUAD1_EDGES V_QUAD1_EDGES(1U)
59630 #define S_QUAD0_EDGES 4
59631 #define V_QUAD0_EDGES(x) ((x) << S_QUAD0_EDGES)
59632 #define F_QUAD0_EDGES V_QUAD0_EDGES(1U)
59634 #define S_QUAD3_CAVEAT 3
59635 #define V_QUAD3_CAVEAT(x) ((x) << S_QUAD3_CAVEAT)
59636 #define F_QUAD3_CAVEAT V_QUAD3_CAVEAT(1U)
59638 #define S_QUAD2_CAVEAT 2
59639 #define V_QUAD2_CAVEAT(x) ((x) << S_QUAD2_CAVEAT)
59640 #define F_QUAD2_CAVEAT V_QUAD2_CAVEAT(1U)
59642 #define S_QUAD1_CAVEAT 1
59643 #define V_QUAD1_CAVEAT(x) ((x) << S_QUAD1_CAVEAT)
59644 #define F_QUAD1_CAVEAT V_QUAD1_CAVEAT(1U)
59646 #define S_QUAD0_CAVEAT 0
59647 #define V_QUAD0_CAVEAT(x) ((x) << S_QUAD0_CAVEAT)
59648 #define F_QUAD0_CAVEAT V_QUAD0_CAVEAT(1U)
59650 #define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
59652 #define S_FAIL_PASS_VALUE 8
59653 #define M_FAIL_PASS_VALUE 0x7fU
59654 #define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE)
59655 #define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE)
59657 #define S_PASS_FAIL_VALUE 0
59658 #define M_PASS_FAIL_VALUE 0xffU
59659 #define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE)
59660 #define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE)
59662 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
59664 #define S_RD_EYE_SIZE_BITS2_7 8
59665 #define M_RD_EYE_SIZE_BITS2_7 0x3fU
59666 #define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
59667 #define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
59669 #define S_RD_EYE_SIZE_BITS10_15 0
59670 #define M_RD_EYE_SIZE_BITS10_15 0x3fU
59671 #define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
59672 #define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
59674 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
59675 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
59676 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
59677 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
59678 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
59679 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
59680 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
59681 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
59682 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
59683 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
59684 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
59685 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
59687 #define S_DESIRED_EDGE_CNTR_TARGET_HIGH 8
59688 #define M_DESIRED_EDGE_CNTR_TARGET_HIGH 0xffU
59689 #define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH)
59690 #define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH)
59692 #define S_DESIRED_EDGE_CNTR_TARGET_LOW 0
59693 #define M_DESIRED_EDGE_CNTR_TARGET_LOW 0xffU
59694 #define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW)
59695 #define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW)
59697 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
59699 #define S_APPROACH_ALIGNMENT 15
59700 #define V_APPROACH_ALIGNMENT(x) ((x) << S_APPROACH_ALIGNMENT)
59701 #define F_APPROACH_ALIGNMENT V_APPROACH_ALIGNMENT(1U)
59703 #define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
59705 #define S_QUAD0_PWR_CTL 12
59706 #define M_QUAD0_PWR_CTL 0xfU
59707 #define V_QUAD0_PWR_CTL(x) ((x) << S_QUAD0_PWR_CTL)
59708 #define G_QUAD0_PWR_CTL(x) (((x) >> S_QUAD0_PWR_CTL) & M_QUAD0_PWR_CTL)
59710 #define S_QUAD1_PWR_CTL 8
59711 #define M_QUAD1_PWR_CTL 0xfU
59712 #define V_QUAD1_PWR_CTL(x) ((x) << S_QUAD1_PWR_CTL)
59713 #define G_QUAD1_PWR_CTL(x) (((x) >> S_QUAD1_PWR_CTL) & M_QUAD1_PWR_CTL)
59715 #define S_QUAD2_PWR_CTL 4
59716 #define M_QUAD2_PWR_CTL 0xfU
59717 #define V_QUAD2_PWR_CTL(x) ((x) << S_QUAD2_PWR_CTL)
59718 #define G_QUAD2_PWR_CTL(x) (((x) >> S_QUAD2_PWR_CTL) & M_QUAD2_PWR_CTL)
59720 #define S_QUAD3_PWR_CTL 0
59721 #define M_QUAD3_PWR_CTL 0xfU
59722 #define V_QUAD3_PWR_CTL(x) ((x) << S_QUAD3_PWR_CTL)
59723 #define G_QUAD3_PWR_CTL(x) (((x) >> S_QUAD3_PWR_CTL) & M_QUAD3_PWR_CTL)
59725 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
59727 #define S_REFERENCE_BITS1_7 8
59728 #define M_REFERENCE_BITS1_7 0x7fU
59729 #define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
59730 #define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
59732 #define S_REFERENCE_BITS9_15 0
59733 #define M_REFERENCE_BITS9_15 0x7fU
59734 #define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
59735 #define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
59737 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
59738 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
59740 #define S_REFERENCE 8
59741 #define M_REFERENCE 0x7fU
59742 #define V_REFERENCE(x) ((x) << S_REFERENCE)
59743 #define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
59745 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
59746 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
59747 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
59749 #define S_INTERP_SIG_SLEW 12
59750 #define M_INTERP_SIG_SLEW 0xfU
59751 #define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
59752 #define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
59754 #define S_POST_CURSOR 8
59755 #define M_POST_CURSOR 0xfU
59756 #define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
59757 #define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
59759 #define S_SLEW_CTL 4
59760 #define M_SLEW_CTL 0xfU
59761 #define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
59762 #define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
59764 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
59765 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
59767 #define S_CE0DLTVCCA 7
59768 #define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
59769 #define F_CE0DLTVCCA V_CE0DLTVCCA(1U)
59771 #define S_CE0DLTVCCD1 4
59772 #define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
59773 #define F_CE0DLTVCCD1 V_CE0DLTVCCD1(1U)
59775 #define S_CE0DLTVCCD2 3
59776 #define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
59777 #define F_CE0DLTVCCD2 V_CE0DLTVCCD2(1U)
59779 #define S_S0INSDLYTAP 2
59780 #define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
59781 #define F_S0INSDLYTAP V_S0INSDLYTAP(1U)
59783 #define S_S1INSDLYTAP 1
59784 #define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
59785 #define F_S1INSDLYTAP V_S1INSDLYTAP(1U)
59787 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
59789 #define S_EN_SLICE_N_WR 8
59790 #define M_EN_SLICE_N_WR 0xffU
59791 #define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
59792 #define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
59794 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
59795 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
59797 #define S_EN_TERM_N_WR 8
59798 #define M_EN_TERM_N_WR 0xffU
59799 #define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
59800 #define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
59802 #define S_EN_TERM_N_WR_FFE 4
59803 #define M_EN_TERM_N_WR_FFE 0xfU
59804 #define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
59805 #define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
59807 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
59809 #define S_EN_TERM_P_WR 8
59810 #define M_EN_TERM_P_WR 0xffU
59811 #define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
59812 #define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
59814 #define S_EN_TERM_P_WR_FFE 4
59815 #define M_EN_TERM_P_WR_FFE 0xfU
59816 #define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
59817 #define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
59819 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
59821 #define S_DATA_BIT_DISABLE_0_15 0
59822 #define M_DATA_BIT_DISABLE_0_15 0xffffU
59823 #define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
59824 #define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
59826 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
59828 #define S_DATA_BIT_DISABLE_16_23 8
59829 #define M_DATA_BIT_DISABLE_16_23 0xffU
59830 #define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
59831 #define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
59833 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
59835 #define S_DQ_WR_OFFSET_N0 12
59836 #define M_DQ_WR_OFFSET_N0 0xfU
59837 #define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
59838 #define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
59840 #define S_DQ_WR_OFFSET_N1 8
59841 #define M_DQ_WR_OFFSET_N1 0xfU
59842 #define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
59843 #define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
59845 #define S_DQ_WR_OFFSET_N2 4
59846 #define M_DQ_WR_OFFSET_N2 0xfU
59847 #define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
59848 #define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
59850 #define S_DQ_WR_OFFSET_N3 0
59851 #define M_DQ_WR_OFFSET_N3 0xfU
59852 #define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
59853 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
59855 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
59857 #define S_EYEDAC_PD 13
59858 #define V_EYEDAC_PD(x) ((x) << S_EYEDAC_PD)
59859 #define F_EYEDAC_PD V_EYEDAC_PD(1U)
59861 #define S_ANALOG_OUTPUT_STAB 9
59862 #define V_ANALOG_OUTPUT_STAB(x) ((x) << S_ANALOG_OUTPUT_STAB)
59863 #define F_ANALOG_OUTPUT_STAB V_ANALOG_OUTPUT_STAB(1U)
59865 #define S_DP18_RX_PD 2
59866 #define M_DP18_RX_PD 0x3U
59867 #define V_DP18_RX_PD(x) ((x) << S_DP18_RX_PD)
59868 #define G_DP18_RX_PD(x) (((x) >> S_DP18_RX_PD) & M_DP18_RX_PD)
59870 #define S_DELAY_LINE_CTL_OVERRIDE 4
59871 #define V_DELAY_LINE_CTL_OVERRIDE(x) ((x) << S_DELAY_LINE_CTL_OVERRIDE)
59872 #define F_DELAY_LINE_CTL_OVERRIDE V_DELAY_LINE_CTL_OVERRIDE(1U)
59874 #define S_VCC_REG_PD 0
59875 #define V_VCC_REG_PD(x) ((x) << S_VCC_REG_PD)
59876 #define F_VCC_REG_PD V_VCC_REG_PD(1U)
59878 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
59880 #define S_BIT_ENABLE_0_11 4
59881 #define M_BIT_ENABLE_0_11 0xfffU
59882 #define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
59883 #define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
59885 #define S_BIT_ENABLE_12_15 0
59886 #define M_BIT_ENABLE_12_15 0xfU
59887 #define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
59888 #define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
59890 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
59892 #define S_DI_ADR0_ADR1 15
59893 #define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
59894 #define F_DI_ADR0_ADR1 V_DI_ADR0_ADR1(1U)
59896 #define S_DI_ADR2_ADR3 14
59897 #define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
59898 #define F_DI_ADR2_ADR3 V_DI_ADR2_ADR3(1U)
59900 #define S_DI_ADR4_ADR5 13
59901 #define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
59902 #define F_DI_ADR4_ADR5 V_DI_ADR4_ADR5(1U)
59904 #define S_DI_ADR6_ADR7 12
59905 #define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
59906 #define F_DI_ADR6_ADR7 V_DI_ADR6_ADR7(1U)
59908 #define S_DI_ADR8_ADR9 11
59909 #define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
59910 #define F_DI_ADR8_ADR9 V_DI_ADR8_ADR9(1U)
59912 #define S_DI_ADR10_ADR11 10
59913 #define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
59914 #define F_DI_ADR10_ADR11 V_DI_ADR10_ADR11(1U)
59916 #define S_DI_ADR12_ADR13 9
59917 #define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
59918 #define F_DI_ADR12_ADR13 V_DI_ADR12_ADR13(1U)
59920 #define S_DI_ADR14_ADR15 8
59921 #define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
59922 #define F_DI_ADR14_ADR15 V_DI_ADR14_ADR15(1U)
59924 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
59926 #define S_ADR_DELAY_BITS1_7 8
59927 #define M_ADR_DELAY_BITS1_7 0x7fU
59928 #define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
59929 #define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
59931 #define S_ADR_DELAY_BITS9_15 0
59932 #define M_ADR_DELAY_BITS9_15 0x7fU
59933 #define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
59934 #define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
59936 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
59937 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
59938 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
59939 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
59940 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
59941 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
59942 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
59943 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
59945 #define S_ADR_TEST_LANE_PAIR_FAIL 8
59946 #define M_ADR_TEST_LANE_PAIR_FAIL 0xffU
59947 #define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
59948 #define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
59950 #define S_ADR_TEST_DATA_EN 7
59951 #define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
59952 #define F_ADR_TEST_DATA_EN V_ADR_TEST_DATA_EN(1U)
59954 #define S_DADR_TEST_MODE 5
59955 #define M_DADR_TEST_MODE 0x3U
59956 #define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
59957 #define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
59959 #define S_ADR_TEST_4TO1_MODE 4
59960 #define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
59961 #define F_ADR_TEST_4TO1_MODE V_ADR_TEST_4TO1_MODE(1U)
59963 #define S_ADR_TEST_RESET 3
59964 #define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
59965 #define F_ADR_TEST_RESET V_ADR_TEST_RESET(1U)
59967 #define S_ADR_TEST_GEN_EN 2
59968 #define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
59969 #define F_ADR_TEST_GEN_EN V_ADR_TEST_GEN_EN(1U)
59971 #define S_ADR_TEST_CLEAR_ERROR 1
59972 #define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
59973 #define F_ADR_TEST_CLEAR_ERROR V_ADR_TEST_CLEAR_ERROR(1U)
59975 #define S_ADR_TEST_CHECK_EN 0
59976 #define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
59977 #define F_ADR_TEST_CHECK_EN V_ADR_TEST_CHECK_EN(1U)
59979 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
59981 #define S_EN_SLICE_N_WR_0 8
59982 #define M_EN_SLICE_N_WR_0 0xffU
59983 #define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
59984 #define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
59986 #define S_EN_SLICE_N_WR_FFE 4
59987 #define M_EN_SLICE_N_WR_FFE 0xfU
59988 #define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
59989 #define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
59991 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
59993 #define S_EN_SLICE_N_WR_1 8
59994 #define M_EN_SLICE_N_WR_1 0xffU
59995 #define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
59996 #define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
59998 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
60000 #define S_EN_SLICE_N_WR_2 8
60001 #define M_EN_SLICE_N_WR_2 0xffU
60002 #define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
60003 #define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
60005 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
60007 #define S_EN_SLICE_N_WR_3 8
60008 #define M_EN_SLICE_N_WR_3 0xffU
60009 #define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
60010 #define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
60012 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
60014 #define S_EN_SLICE_P_WR 8
60015 #define M_EN_SLICE_P_WR 0xffU
60016 #define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
60017 #define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
60019 #define S_EN_SLICE_P_WR_FFE 4
60020 #define M_EN_SLICE_P_WR_FFE 0xfU
60021 #define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
60022 #define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
60024 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
60025 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
60026 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
60027 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
60029 #define S_POST_CURSOR0 12
60030 #define M_POST_CURSOR0 0xfU
60031 #define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
60032 #define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
60034 #define S_POST_CURSOR1 8
60035 #define M_POST_CURSOR1 0xfU
60036 #define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
60037 #define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
60039 #define S_POST_CURSOR2 4
60040 #define M_POST_CURSOR2 0xfU
60041 #define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
60042 #define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
60044 #define S_POST_CURSOR3 0
60045 #define M_POST_CURSOR3 0xfU
60046 #define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
60047 #define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
60049 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
60051 #define S_SLEW_CTL0 12
60052 #define M_SLEW_CTL0 0xfU
60053 #define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
60054 #define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
60056 #define S_SLEW_CTL1 8
60057 #define M_SLEW_CTL1 0xfU
60058 #define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
60059 #define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
60061 #define S_SLEW_CTL2 4
60062 #define M_SLEW_CTL2 0xfU
60063 #define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
60064 #define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
60066 #define S_SLEW_CTL3 0
60067 #define M_SLEW_CTL3 0xfU
60068 #define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
60069 #define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
60071 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
60073 #define S_SLICE_SEL_REG_BITS0_1 14
60074 #define M_SLICE_SEL_REG_BITS0_1 0x3U
60075 #define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
60076 #define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
60078 #define S_SLICE_SEL_REG_BITS2_3 12
60079 #define M_SLICE_SEL_REG_BITS2_3 0x3U
60080 #define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
60081 #define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
60083 #define S_SLICE_SEL_REG_BITS4_5 10
60084 #define M_SLICE_SEL_REG_BITS4_5 0x3U
60085 #define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
60086 #define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
60088 #define S_SLICE_SEL_REG_BITS6_7 8
60089 #define M_SLICE_SEL_REG_BITS6_7 0x3U
60090 #define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
60091 #define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
60093 #define S_SLICE_SEL_REG_BITS8_9 6
60094 #define M_SLICE_SEL_REG_BITS8_9 0x3U
60095 #define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
60096 #define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
60098 #define S_SLICE_SEL_REG_BITS10_11 4
60099 #define M_SLICE_SEL_REG_BITS10_11 0x3U
60100 #define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
60101 #define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
60103 #define S_SLICE_SEL_REG_BITS12_13 2
60104 #define M_SLICE_SEL_REG_BITS12_13 0x3U
60105 #define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
60106 #define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
60108 #define S_SLICE_SEL_REG_BITS14_15 0
60109 #define M_SLICE_SEL_REG_BITS14_15 0x3U
60110 #define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
60111 #define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
60113 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
60114 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
60116 #define S_POST_CUR_SEL_BITS0_1 14
60117 #define M_POST_CUR_SEL_BITS0_1 0x3U
60118 #define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
60119 #define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
60121 #define S_POST_CUR_SEL_BITS2_3 12
60122 #define M_POST_CUR_SEL_BITS2_3 0x3U
60123 #define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
60124 #define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
60126 #define S_POST_CUR_SEL_BITS4_5 10
60127 #define M_POST_CUR_SEL_BITS4_5 0x3U
60128 #define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
60129 #define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
60131 #define S_POST_CUR_SEL_BITS6_7 8
60132 #define M_POST_CUR_SEL_BITS6_7 0x3U
60133 #define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
60134 #define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
60136 #define S_POST_CUR_SEL_BITS8_9 6
60137 #define M_POST_CUR_SEL_BITS8_9 0x3U
60138 #define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
60139 #define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
60141 #define S_POST_CUR_SEL_BITS10_11 4
60142 #define M_POST_CUR_SEL_BITS10_11 0x3U
60143 #define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
60144 #define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
60146 #define S_POST_CUR_SEL_BITS12_13 2
60147 #define M_POST_CUR_SEL_BITS12_13 0x3U
60148 #define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
60149 #define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
60151 #define S_POST_CUR_SEL_BITS14_15 0
60152 #define M_POST_CUR_SEL_BITS14_15 0x3U
60153 #define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
60154 #define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
60156 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
60157 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
60159 #define S_SLEW_CTL_SEL_BITS0_1 14
60160 #define M_SLEW_CTL_SEL_BITS0_1 0x3U
60161 #define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
60162 #define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
60164 #define S_SLEW_CTL_SEL_BITS2_3 12
60165 #define M_SLEW_CTL_SEL_BITS2_3 0x3U
60166 #define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
60167 #define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
60169 #define S_SLEW_CTL_SEL_BITS4_5 10
60170 #define M_SLEW_CTL_SEL_BITS4_5 0x3U
60171 #define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
60172 #define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
60174 #define S_SLEW_CTL_SEL_BITS6_7 8
60175 #define M_SLEW_CTL_SEL_BITS6_7 0x3U
60176 #define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
60177 #define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
60179 #define S_SLEW_CTL_SEL_BITS8_9 6
60180 #define M_SLEW_CTL_SEL_BITS8_9 0x3U
60181 #define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
60182 #define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
60184 #define S_SLEW_CTL_SEL_BITS10_11 4
60185 #define M_SLEW_CTL_SEL_BITS10_11 0x3U
60186 #define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
60187 #define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
60189 #define S_SLEW_CTL_SEL_BITS12_13 2
60190 #define M_SLEW_CTL_SEL_BITS12_13 0x3U
60191 #define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
60192 #define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
60194 #define S_SLEW_CTL_SEL_BITS14_15 0
60195 #define M_SLEW_CTL_SEL_BITS14_15 0x3U
60196 #define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
60197 #define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
60199 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
60200 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
60202 #define S_ADR_LANE_0_11_PD 4
60203 #define M_ADR_LANE_0_11_PD 0xfffU
60204 #define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
60205 #define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
60207 #define S_ADR_LANE_12_15_PD 0
60208 #define M_ADR_LANE_12_15_PD 0xfU
60209 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
60210 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
60212 #define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
60213 #define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
60214 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
60215 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
60216 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
60217 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
60218 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
60219 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
60220 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
60221 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
60222 #define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
60224 #define S_ADR_TEST_MODE 5
60225 #define M_ADR_TEST_MODE 0x3U
60226 #define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE)
60227 #define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE)
60229 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
60230 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
60231 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
60232 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
60233 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
60234 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
60235 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
60236 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
60237 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
60238 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
60239 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
60240 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
60241 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
60242 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
60243 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
60244 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
60245 #define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
60246 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
60248 #define S_PLL_TUNE_0_2 13
60249 #define M_PLL_TUNE_0_2 0x7U
60250 #define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
60251 #define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
60253 #define S_PLL_TUNECP_0_2 10
60254 #define M_PLL_TUNECP_0_2 0x7U
60255 #define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
60256 #define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
60258 #define S_PLL_TUNEF_0_5 4
60259 #define M_PLL_TUNEF_0_5 0x3fU
60260 #define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
60261 #define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
60263 #define S_PLL_TUNEVCO_0_1 2
60264 #define M_PLL_TUNEVCO_0_1 0x3U
60265 #define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
60266 #define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
60268 #define S_PLL_PLLXTR_0_1 0
60269 #define M_PLL_PLLXTR_0_1 0x3U
60270 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
60271 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
60273 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
60274 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
60276 #define S_PLL_TUNETDIV_0_2 13
60277 #define M_PLL_TUNETDIV_0_2 0x7U
60278 #define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
60279 #define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
60281 #define S_PLL_TUNEMDIV_0_1 11
60282 #define M_PLL_TUNEMDIV_0_1 0x3U
60283 #define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
60284 #define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
60286 #define S_PLL_TUNEATST 10
60287 #define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
60288 #define F_PLL_TUNEATST V_PLL_TUNEATST(1U)
60290 #define S_VREG_RANGE_0_1 8
60291 #define M_VREG_RANGE_0_1 0x3U
60292 #define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
60293 #define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
60295 #define S_VREG_VREGSPARE 7
60296 #define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
60297 #define F_VREG_VREGSPARE V_VREG_VREGSPARE(1U)
60299 #define S_VREG_VCCTUNE_0_1 5
60300 #define M_VREG_VCCTUNE_0_1 0x3U
60301 #define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
60302 #define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
60304 #define S_INTERP_SIG_SLEW_0_3 1
60305 #define M_INTERP_SIG_SLEW_0_3 0xfU
60306 #define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
60307 #define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
60309 #define S_ANALOG_WRAPON 0
60310 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
60311 #define F_ANALOG_WRAPON V_ANALOG_WRAPON(1U)
60313 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
60314 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
60316 #define S_SYSCLK_ENABLE 15
60317 #define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
60318 #define F_SYSCLK_ENABLE V_SYSCLK_ENABLE(1U)
60320 #define S_SYSCLK_ROT_OVERRIDE 8
60321 #define M_SYSCLK_ROT_OVERRIDE 0x7fU
60322 #define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
60323 #define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
60325 #define S_SYSCLK_ROT_OVERRIDE_EN 7
60326 #define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
60327 #define F_SYSCLK_ROT_OVERRIDE_EN V_SYSCLK_ROT_OVERRIDE_EN(1U)
60329 #define S_SYSCLK_PHASE_ALIGN_RESE 6
60330 #define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
60331 #define F_SYSCLK_PHASE_ALIGN_RESE V_SYSCLK_PHASE_ALIGN_RESE(1U)
60333 #define S_SYSCLK_PHASE_CNTL_EN 5
60334 #define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
60335 #define F_SYSCLK_PHASE_CNTL_EN V_SYSCLK_PHASE_CNTL_EN(1U)
60337 #define S_SYSCLK_PHASE_DEFAULT_EN 4
60338 #define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
60339 #define F_SYSCLK_PHASE_DEFAULT_EN V_SYSCLK_PHASE_DEFAULT_EN(1U)
60341 #define S_SYSCLK_POS_EDGE_ALIGN 3
60342 #define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
60343 #define F_SYSCLK_POS_EDGE_ALIGN V_SYSCLK_POS_EDGE_ALIGN(1U)
60345 #define S_CONTINUOUS_UPDATE 2
60346 #define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
60347 #define F_CONTINUOUS_UPDATE V_CONTINUOUS_UPDATE(1U)
60349 #define S_CE0DLTVCC 0
60350 #define M_CE0DLTVCC 0x3U
60351 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
60352 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
60354 #define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
60355 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60357 #define S_TSYS_WRCLK 8
60358 #define M_TSYS_WRCLK 0x7fU
60359 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
60360 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
60362 #define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60363 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
60365 #define S_SLEW_LATE_SAMPLE 15
60366 #define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
60367 #define F_SLEW_LATE_SAMPLE V_SLEW_LATE_SAMPLE(1U)
60369 #define S_SYSCLK_ROT 8
60370 #define M_SYSCLK_ROT 0x7fU
60371 #define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
60372 #define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
60374 #define S_BB_LOCK 7
60375 #define V_BB_LOCK(x) ((x) << S_BB_LOCK)
60376 #define F_BB_LOCK V_BB_LOCK(1U)
60378 #define S_SLEW_EARLY_SAMPLE 6
60379 #define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
60380 #define F_SLEW_EARLY_SAMPLE V_SLEW_EARLY_SAMPLE(1U)
60382 #define S_SLEW_DONE_STATUS 4
60383 #define M_SLEW_DONE_STATUS 0x3U
60384 #define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
60385 #define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
60387 #define S_SLEW_CNTL 0
60388 #define M_SLEW_CNTL 0xfU
60389 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
60390 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
60392 #define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
60393 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
60396 #define V_FLUSH(x) ((x) << S_FLUSH)
60397 #define F_FLUSH V_FLUSH(1U)
60399 #define S_GIANT_MUX_TEST_EN 14
60400 #define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
60401 #define F_GIANT_MUX_TEST_EN V_GIANT_MUX_TEST_EN(1U)
60403 #define S_GIANT_MUX_TEST_VAL 13
60404 #define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
60405 #define F_GIANT_MUX_TEST_VAL V_GIANT_MUX_TEST_VAL(1U)
60407 #define S_HS_PROBE_A_SEL_ 8
60408 #define M_HS_PROBE_A_SEL_ 0xfU
60409 #define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
60410 #define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
60412 #define S_HS_PROBE_B_SEL_ 4
60413 #define M_HS_PROBE_B_SEL_ 0xfU
60414 #define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
60415 #define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
60417 #define S_ATEST1CTL0 3
60418 #define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
60419 #define F_ATEST1CTL0 V_ATEST1CTL0(1U)
60421 #define S_ATEST1CTL1 2
60422 #define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
60423 #define F_ATEST1CTL1 V_ATEST1CTL1(1U)
60425 #define S_ATEST1CTL2 1
60426 #define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
60427 #define F_ATEST1CTL2 V_ATEST1CTL2(1U)
60429 #define S_ATEST1CTL3 0
60430 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
60431 #define F_ATEST1CTL3 V_ATEST1CTL3(1U)
60433 #define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
60435 #define S_FORCE_EN 14
60436 #define V_FORCE_EN(x) ((x) << S_FORCE_EN)
60437 #define F_FORCE_EN V_FORCE_EN(1U)
60439 #define S_AD32S_HS_PROBE_A_SEL 8
60440 #define M_AD32S_HS_PROBE_A_SEL 0xfU
60441 #define V_AD32S_HS_PROBE_A_SEL(x) ((x) << S_AD32S_HS_PROBE_A_SEL)
60442 #define G_AD32S_HS_PROBE_A_SEL(x) (((x) >> S_AD32S_HS_PROBE_A_SEL) & M_AD32S_HS_PROBE_A_SEL)
60444 #define S_AD32S_HS_PROBE_B_SEL 4
60445 #define M_AD32S_HS_PROBE_B_SEL 0xfU
60446 #define V_AD32S_HS_PROBE_B_SEL(x) ((x) << S_AD32S_HS_PROBE_B_SEL)
60447 #define G_AD32S_HS_PROBE_B_SEL(x) (((x) >> S_AD32S_HS_PROBE_B_SEL) & M_AD32S_HS_PROBE_B_SEL)
60449 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
60451 #define S_GIANT_MUX_TEST_RESULTS 0
60452 #define M_GIANT_MUX_TEST_RESULTS 0xffffU
60453 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
60454 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
60456 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
60458 #define S_OUTPUT_DRIVER_FORCE_VALUE 0
60459 #define M_OUTPUT_DRIVER_FORCE_VALUE 0xffffU
60460 #define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE)
60461 #define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE)
60463 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
60464 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
60465 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
60467 #define S_MASTER_PD_CNTL 15
60468 #define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
60469 #define F_MASTER_PD_CNTL V_MASTER_PD_CNTL(1U)
60471 #define S_ANALOG_INPUT_STAB2 14
60472 #define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
60473 #define F_ANALOG_INPUT_STAB2 V_ANALOG_INPUT_STAB2(1U)
60475 #define S_ANALOG_INPUT_STAB1 8
60476 #define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
60477 #define F_ANALOG_INPUT_STAB1 V_ANALOG_INPUT_STAB1(1U)
60479 #define S_SYSCLK_CLK_GATE 6
60480 #define M_SYSCLK_CLK_GATE 0x3U
60481 #define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
60482 #define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
60484 #define S_WR_FIFO_STAB 5
60485 #define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
60486 #define F_WR_FIFO_STAB V_WR_FIFO_STAB(1U)
60488 #define S_ADR_RX_PD 4
60489 #define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
60490 #define F_ADR_RX_PD V_ADR_RX_PD(1U)
60492 #define S_TX_TRISTATE_CNTL 1
60493 #define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
60494 #define F_TX_TRISTATE_CNTL V_TX_TRISTATE_CNTL(1U)
60496 #define S_DVCC_REG_PD 0
60497 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
60498 #define F_DVCC_REG_PD V_DVCC_REG_PD(1U)
60500 #define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
60501 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
60503 #define S_SLEW_CAL_ENABLE 15
60504 #define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
60505 #define F_SLEW_CAL_ENABLE V_SLEW_CAL_ENABLE(1U)
60507 #define S_SLEW_CAL_START 14
60508 #define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
60509 #define F_SLEW_CAL_START V_SLEW_CAL_START(1U)
60511 #define S_SLEW_CAL_OVERRIDE_EN 12
60512 #define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
60513 #define F_SLEW_CAL_OVERRIDE_EN V_SLEW_CAL_OVERRIDE_EN(1U)
60515 #define S_SLEW_CAL_OVERRIDE 8
60516 #define M_SLEW_CAL_OVERRIDE 0xfU
60517 #define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
60518 #define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
60520 #define S_SLEW_TARGET_PR_OFFSET 0
60521 #define M_SLEW_TARGET_PR_OFFSET 0x1fU
60522 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
60523 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
60525 #define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
60526 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
60528 #define S_DP18_PLL_LOCK 1
60529 #define M_DP18_PLL_LOCK 0x7fffU
60530 #define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
60531 #define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
60533 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
60535 #define S_AD32S_PLL_LOCK 14
60536 #define M_AD32S_PLL_LOCK 0x3U
60537 #define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
60538 #define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
60540 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
60542 #define S_RANK_PAIR0_PRI 13
60543 #define M_RANK_PAIR0_PRI 0x7U
60544 #define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
60545 #define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
60547 #define S_RANK_PAIR0_PRI_V 12
60548 #define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
60549 #define F_RANK_PAIR0_PRI_V V_RANK_PAIR0_PRI_V(1U)
60551 #define S_RANK_PAIR0_SEC 9
60552 #define M_RANK_PAIR0_SEC 0x7U
60553 #define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
60554 #define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
60556 #define S_RANK_PAIR0_SEC_V 8
60557 #define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
60558 #define F_RANK_PAIR0_SEC_V V_RANK_PAIR0_SEC_V(1U)
60560 #define S_RANK_PAIR1_PRI 5
60561 #define M_RANK_PAIR1_PRI 0x7U
60562 #define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
60563 #define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
60565 #define S_RANK_PAIR1_PRI_V 4
60566 #define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
60567 #define F_RANK_PAIR1_PRI_V V_RANK_PAIR1_PRI_V(1U)
60569 #define S_RANK_PAIR1_SEC 1
60570 #define M_RANK_PAIR1_SEC 0x7U
60571 #define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
60572 #define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
60574 #define S_RANK_PAIR1_SEC_V 0
60575 #define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
60576 #define F_RANK_PAIR1_SEC_V V_RANK_PAIR1_SEC_V(1U)
60578 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
60580 #define S_RANK_PAIR2_PRI 13
60581 #define M_RANK_PAIR2_PRI 0x7U
60582 #define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
60583 #define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
60585 #define S_RANK_PAIR2_PRI_V 12
60586 #define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
60587 #define F_RANK_PAIR2_PRI_V V_RANK_PAIR2_PRI_V(1U)
60589 #define S_RANK_PAIR2_SEC 9
60590 #define M_RANK_PAIR2_SEC 0x7U
60591 #define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
60592 #define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
60594 #define S_RANK_PAIR2_SEC_V 8
60595 #define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
60596 #define F_RANK_PAIR2_SEC_V V_RANK_PAIR2_SEC_V(1U)
60598 #define S_RANK_PAIR3_PRI 5
60599 #define M_RANK_PAIR3_PRI 0x7U
60600 #define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
60601 #define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
60603 #define S_RANK_PAIR3_PRI_V 4
60604 #define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
60605 #define F_RANK_PAIR3_PRI_V V_RANK_PAIR3_PRI_V(1U)
60607 #define S_RANK_PAIR3_SEC 1
60608 #define M_RANK_PAIR3_SEC 0x7U
60609 #define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
60610 #define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
60612 #define S_RANK_PAIR3_SEC_V 0
60613 #define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
60614 #define F_RANK_PAIR3_SEC_V V_RANK_PAIR3_SEC_V(1U)
60616 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
60618 #define S_PERIODIC_BASE_CNTR0 0
60619 #define M_PERIODIC_BASE_CNTR0 0xffffU
60620 #define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
60621 #define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
60623 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
60625 #define S_PERIODIC_CAL_REQ_EN 15
60626 #define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
60627 #define F_PERIODIC_CAL_REQ_EN V_PERIODIC_CAL_REQ_EN(1U)
60629 #define S_PERIODIC_RELOAD_VALUE0 0
60630 #define M_PERIODIC_RELOAD_VALUE0 0x7fffU
60631 #define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
60632 #define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
60634 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
60636 #define S_PERIODIC_BASE_CNTR1 0
60637 #define M_PERIODIC_BASE_CNTR1 0xffffU
60638 #define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
60639 #define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
60641 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
60643 #define S_PERIODIC_CAL_TIMER 0
60644 #define M_PERIODIC_CAL_TIMER 0xffffU
60645 #define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
60646 #define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
60648 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
60650 #define S_PERIODIC_TIMER_RELOAD_VALUE 0
60651 #define M_PERIODIC_TIMER_RELOAD_VALUE 0xffffU
60652 #define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
60653 #define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
60655 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
60657 #define S_PERIODIC_ZCAL_TIMER 0
60658 #define M_PERIODIC_ZCAL_TIMER 0xffffU
60659 #define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
60660 #define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
60662 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
60663 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
60665 #define S_PER_ENA_RANK_PAIR 12
60666 #define M_PER_ENA_RANK_PAIR 0xfU
60667 #define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
60668 #define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
60670 #define S_PER_ENA_ZCAL 11
60671 #define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
60672 #define F_PER_ENA_ZCAL V_PER_ENA_ZCAL(1U)
60674 #define S_PER_ENA_SYSCLK_ALIGN 10
60675 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
60676 #define F_PER_ENA_SYSCLK_ALIGN V_PER_ENA_SYSCLK_ALIGN(1U)
60678 #define S_ENA_PER_READ_CTR 9
60679 #define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
60680 #define F_ENA_PER_READ_CTR V_ENA_PER_READ_CTR(1U)
60682 #define S_ENA_PER_RDCLK_ALIGN 8
60683 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
60684 #define F_ENA_PER_RDCLK_ALIGN V_ENA_PER_RDCLK_ALIGN(1U)
60686 #define S_ENA_PER_DQS_ALIGN 7
60687 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
60688 #define F_ENA_PER_DQS_ALIGN V_ENA_PER_DQS_ALIGN(1U)
60690 #define S_PER_NEXT_RANK_PAIR 5
60691 #define M_PER_NEXT_RANK_PAIR 0x3U
60692 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
60693 #define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
60695 #define S_FAST_SIM_PER_CNTR 4
60696 #define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
60697 #define F_FAST_SIM_PER_CNTR V_FAST_SIM_PER_CNTR(1U)
60699 #define S_START_INIT_CAL 3
60700 #define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
60701 #define F_START_INIT_CAL V_START_INIT_CAL(1U)
60703 #define S_START_PER_CAL 2
60704 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
60705 #define F_START_PER_CAL V_START_PER_CAL(1U)
60707 #define S_ABORT_ON_ERR_EN 1
60708 #define V_ABORT_ON_ERR_EN(x) ((x) << S_ABORT_ON_ERR_EN)
60709 #define F_ABORT_ON_ERR_EN V_ABORT_ON_ERR_EN(1U)
60711 #define S_ENA_PER_RD_CTR 9
60712 #define V_ENA_PER_RD_CTR(x) ((x) << S_ENA_PER_RD_CTR)
60713 #define F_ENA_PER_RD_CTR V_ENA_PER_RD_CTR(1U)
60715 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
60717 #define S_PROTOCOL_DDR 12
60718 #define M_PROTOCOL_DDR 0xfU
60719 #define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
60720 #define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
60722 #define S_DATA_MUX4_1MODE 11
60723 #define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
60724 #define F_DATA_MUX4_1MODE V_DATA_MUX4_1MODE(1U)
60726 #define S_DDR4_CMD_SIG_REDUCTION 9
60727 #define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
60728 #define F_DDR4_CMD_SIG_REDUCTION V_DDR4_CMD_SIG_REDUCTION(1U)
60730 #define S_SYSCLK_2X_MEMINTCLKO 8
60731 #define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
60732 #define F_SYSCLK_2X_MEMINTCLKO V_SYSCLK_2X_MEMINTCLKO(1U)
60734 #define S_RANK_OVERRIDE 7
60735 #define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
60736 #define F_RANK_OVERRIDE V_RANK_OVERRIDE(1U)
60738 #define S_RANK_OVERRIDE_VALUE 4
60739 #define M_RANK_OVERRIDE_VALUE 0x7U
60740 #define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
60741 #define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
60743 #define S_LOW_LATENCY 3
60744 #define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
60745 #define F_LOW_LATENCY V_LOW_LATENCY(1U)
60747 #define S_DDR4_BANK_REFRESH 2
60748 #define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
60749 #define F_DDR4_BANK_REFRESH V_DDR4_BANK_REFRESH(1U)
60751 #define S_DDR4_VLEVEL_BANK_GROUP 1
60752 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
60753 #define F_DDR4_VLEVEL_BANK_GROUP V_DDR4_VLEVEL_BANK_GROUP(1U)
60755 #define S_DDRPHY_PROTOCOL 12
60756 #define M_DDRPHY_PROTOCOL 0xfU
60757 #define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL)
60758 #define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL)
60760 #define S_SPAM_EN 10
60761 #define V_SPAM_EN(x) ((x) << S_SPAM_EN)
60762 #define F_SPAM_EN V_SPAM_EN(1U)
60764 #define S_DDR4_IPW_LOOP_DIS 2
60765 #define V_DDR4_IPW_LOOP_DIS(x) ((x) << S_DDR4_IPW_LOOP_DIS)
60766 #define F_DDR4_IPW_LOOP_DIS V_DDR4_IPW_LOOP_DIS(1U)
60768 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
60770 #define S_WRITE_LATENCY_OFFSET 12
60771 #define M_WRITE_LATENCY_OFFSET 0xfU
60772 #define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
60773 #define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
60775 #define S_READ_LATENCY_OFFSET 8
60776 #define M_READ_LATENCY_OFFSET 0xfU
60777 #define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
60778 #define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
60780 #define S_MEMCTL_CIC_FAST 7
60781 #define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
60782 #define F_MEMCTL_CIC_FAST V_MEMCTL_CIC_FAST(1U)
60784 #define S_MEMCTL_CTRN_IGNORE 6
60785 #define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
60786 #define F_MEMCTL_CTRN_IGNORE V_MEMCTL_CTRN_IGNORE(1U)
60788 #define S_DISABLE_MEMCTL_CAL 5
60789 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
60790 #define F_DISABLE_MEMCTL_CAL V_DISABLE_MEMCTL_CAL(1U)
60792 #define S_MEMCTL_CIS_IGNORE 6
60793 #define V_MEMCTL_CIS_IGNORE(x) ((x) << S_MEMCTL_CIS_IGNORE)
60794 #define F_MEMCTL_CIS_IGNORE V_MEMCTL_CIS_IGNORE(1U)
60796 #define S_MEMORY_TYPE 2
60797 #define M_MEMORY_TYPE 0x7U
60798 #define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE)
60799 #define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE)
60801 #define S_DDR4_PDA_MODE 1
60802 #define V_DDR4_PDA_MODE(x) ((x) << S_DDR4_PDA_MODE)
60803 #define F_DDR4_PDA_MODE V_DDR4_PDA_MODE(1U)
60805 #define A_MC_DDRPHY_PC_RESETS 0x47038
60807 #define S_PLL_RESET 15
60808 #define V_PLL_RESET(x) ((x) << S_PLL_RESET)
60809 #define F_PLL_RESET V_PLL_RESET(1U)
60811 #define S_SYSCLK_RESET 14
60812 #define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
60813 #define F_SYSCLK_RESET V_SYSCLK_RESET(1U)
60815 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
60817 #define S_PER_ZCAL_ENA_RANK 8
60818 #define M_PER_ZCAL_ENA_RANK 0xffU
60819 #define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
60820 #define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
60822 #define S_PER_ZCAL_NEXT_RANK 5
60823 #define M_PER_ZCAL_NEXT_RANK 0x7U
60824 #define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
60825 #define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
60827 #define S_START_PER_ZCAL 4
60828 #define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
60829 #define F_START_PER_ZCAL V_START_PER_ZCAL(1U)
60831 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
60833 #define S_ADDR_MIRROR_RP0_PRI 15
60834 #define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
60835 #define F_ADDR_MIRROR_RP0_PRI V_ADDR_MIRROR_RP0_PRI(1U)
60837 #define S_ADDR_MIRROR_RP0_SEC 14
60838 #define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
60839 #define F_ADDR_MIRROR_RP0_SEC V_ADDR_MIRROR_RP0_SEC(1U)
60841 #define S_ADDR_MIRROR_RP1_PRI 13
60842 #define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
60843 #define F_ADDR_MIRROR_RP1_PRI V_ADDR_MIRROR_RP1_PRI(1U)
60845 #define S_ADDR_MIRROR_RP1_SEC 12
60846 #define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
60847 #define F_ADDR_MIRROR_RP1_SEC V_ADDR_MIRROR_RP1_SEC(1U)
60849 #define S_ADDR_MIRROR_RP2_PRI 11
60850 #define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
60851 #define F_ADDR_MIRROR_RP2_PRI V_ADDR_MIRROR_RP2_PRI(1U)
60853 #define S_ADDR_MIRROR_RP2_SEC 10
60854 #define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
60855 #define F_ADDR_MIRROR_RP2_SEC V_ADDR_MIRROR_RP2_SEC(1U)
60857 #define S_ADDR_MIRROR_RP3_PRI 9
60858 #define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
60859 #define F_ADDR_MIRROR_RP3_PRI V_ADDR_MIRROR_RP3_PRI(1U)
60861 #define S_ADDR_MIRROR_RP3_SEC 8
60862 #define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
60863 #define F_ADDR_MIRROR_RP3_SEC V_ADDR_MIRROR_RP3_SEC(1U)
60865 #define S_RANK_GROUPING 6
60866 #define M_RANK_GROUPING 0x3U
60867 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
60868 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
60870 #define S_ADDR_MIRROR_A3_A4 5
60871 #define V_ADDR_MIRROR_A3_A4(x) ((x) << S_ADDR_MIRROR_A3_A4)
60872 #define F_ADDR_MIRROR_A3_A4 V_ADDR_MIRROR_A3_A4(1U)
60874 #define S_ADDR_MIRROR_A5_A6 4
60875 #define V_ADDR_MIRROR_A5_A6(x) ((x) << S_ADDR_MIRROR_A5_A6)
60876 #define F_ADDR_MIRROR_A5_A6 V_ADDR_MIRROR_A5_A6(1U)
60878 #define S_ADDR_MIRROR_A7_A8 3
60879 #define V_ADDR_MIRROR_A7_A8(x) ((x) << S_ADDR_MIRROR_A7_A8)
60880 #define F_ADDR_MIRROR_A7_A8 V_ADDR_MIRROR_A7_A8(1U)
60882 #define S_ADDR_MIRROR_A11_A13 2
60883 #define V_ADDR_MIRROR_A11_A13(x) ((x) << S_ADDR_MIRROR_A11_A13)
60884 #define F_ADDR_MIRROR_A11_A13 V_ADDR_MIRROR_A11_A13(1U)
60886 #define S_ADDR_MIRROR_BA0_BA1 1
60887 #define V_ADDR_MIRROR_BA0_BA1(x) ((x) << S_ADDR_MIRROR_BA0_BA1)
60888 #define F_ADDR_MIRROR_BA0_BA1 V_ADDR_MIRROR_BA0_BA1(1U)
60890 #define S_ADDR_MIRROR_BG0_BG1 0
60891 #define V_ADDR_MIRROR_BG0_BG1(x) ((x) << S_ADDR_MIRROR_BG0_BG1)
60892 #define F_ADDR_MIRROR_BG0_BG1 V_ADDR_MIRROR_BG0_BG1(1U)
60894 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
60896 #define S_RC_ERROR 15
60897 #define V_RC_ERROR(x) ((x) << S_RC_ERROR)
60898 #define F_RC_ERROR V_RC_ERROR(1U)
60900 #define S_WC_ERROR 14
60901 #define V_WC_ERROR(x) ((x) << S_WC_ERROR)
60902 #define F_WC_ERROR V_WC_ERROR(1U)
60904 #define S_SEQ_ERROR 13
60905 #define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
60906 #define F_SEQ_ERROR V_SEQ_ERROR(1U)
60908 #define S_CC_ERROR 12
60909 #define V_CC_ERROR(x) ((x) << S_CC_ERROR)
60910 #define F_CC_ERROR V_CC_ERROR(1U)
60912 #define S_APB_ERROR 11
60913 #define V_APB_ERROR(x) ((x) << S_APB_ERROR)
60914 #define F_APB_ERROR V_APB_ERROR(1U)
60916 #define S_PC_ERROR 10
60917 #define V_PC_ERROR(x) ((x) << S_PC_ERROR)
60918 #define F_PC_ERROR V_PC_ERROR(1U)
60920 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
60922 #define S_RC_ERROR_MASK 15
60923 #define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
60924 #define F_RC_ERROR_MASK V_RC_ERROR_MASK(1U)
60926 #define S_WC_ERROR_MASK 14
60927 #define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
60928 #define F_WC_ERROR_MASK V_WC_ERROR_MASK(1U)
60930 #define S_SEQ_ERROR_MASK 13
60931 #define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
60932 #define F_SEQ_ERROR_MASK V_SEQ_ERROR_MASK(1U)
60934 #define S_CC_ERROR_MASK 12
60935 #define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
60936 #define F_CC_ERROR_MASK V_CC_ERROR_MASK(1U)
60938 #define S_APB_ERROR_MASK 11
60939 #define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
60940 #define F_APB_ERROR_MASK V_APB_ERROR_MASK(1U)
60942 #define S_PC_ERROR_MASK 10
60943 #define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
60944 #define F_PC_ERROR_MASK V_PC_ERROR_MASK(1U)
60946 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
60949 #define M_PVTP 0x1fU
60950 #define V_PVTP(x) ((x) << S_PVTP)
60951 #define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
60954 #define M_PVTN 0x1fU
60955 #define V_PVTN(x) ((x) << S_PVTN)
60956 #define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
60958 #define S_PVT_OVERRIDE 5
60959 #define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
60960 #define F_PVT_OVERRIDE V_PVT_OVERRIDE(1U)
60962 #define S_ENABLE_ZCAL 4
60963 #define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
60964 #define F_ENABLE_ZCAL V_ENABLE_ZCAL(1U)
60966 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
60968 #define S_VREFDQ0DSGN 15
60969 #define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
60970 #define F_VREFDQ0DSGN V_VREFDQ0DSGN(1U)
60972 #define S_VREFDQ0D 11
60973 #define M_VREFDQ0D 0xfU
60974 #define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
60975 #define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
60977 #define S_VREFDQ1DSGN 10
60978 #define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
60979 #define F_VREFDQ1DSGN V_VREFDQ1DSGN(1U)
60981 #define S_VREFDQ1D 6
60982 #define M_VREFDQ1D 0xfU
60983 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
60984 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
60986 #define S_EN_ANALOG_PD 3
60987 #define V_EN_ANALOG_PD(x) ((x) << S_EN_ANALOG_PD)
60988 #define F_EN_ANALOG_PD V_EN_ANALOG_PD(1U)
60990 #define S_ANALOG_PD_DLY 2
60991 #define V_ANALOG_PD_DLY(x) ((x) << S_ANALOG_PD_DLY)
60992 #define F_ANALOG_PD_DLY V_ANALOG_PD_DLY(1U)
60994 #define S_ANALOG_PD_DIV 0
60995 #define M_ANALOG_PD_DIV 0x3U
60996 #define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV)
60997 #define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV)
60999 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
61001 #define S_ENA_WR_LEVEL 15
61002 #define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
61003 #define F_ENA_WR_LEVEL V_ENA_WR_LEVEL(1U)
61005 #define S_ENA_INITIAL_PAT_WR 14
61006 #define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
61007 #define F_ENA_INITIAL_PAT_WR V_ENA_INITIAL_PAT_WR(1U)
61009 #define S_ENA_DQS_ALIGN 13
61010 #define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
61011 #define F_ENA_DQS_ALIGN V_ENA_DQS_ALIGN(1U)
61013 #define S_ENA_RDCLK_ALIGN 12
61014 #define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
61015 #define F_ENA_RDCLK_ALIGN V_ENA_RDCLK_ALIGN(1U)
61017 #define S_ENA_READ_CTR 11
61018 #define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
61019 #define F_ENA_READ_CTR V_ENA_READ_CTR(1U)
61021 #define S_ENA_WRITE_CTR 10
61022 #define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
61023 #define F_ENA_WRITE_CTR V_ENA_WRITE_CTR(1U)
61025 #define S_ENA_INITIAL_COARSE_WR 9
61026 #define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
61027 #define F_ENA_INITIAL_COARSE_WR V_ENA_INITIAL_COARSE_WR(1U)
61029 #define S_ENA_COARSE_RD 8
61030 #define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
61031 #define F_ENA_COARSE_RD V_ENA_COARSE_RD(1U)
61033 #define S_ENA_CUSTOM_RD 7
61034 #define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
61035 #define F_ENA_CUSTOM_RD V_ENA_CUSTOM_RD(1U)
61037 #define S_ENA_CUSTOM_WR 6
61038 #define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
61039 #define F_ENA_CUSTOM_WR V_ENA_CUSTOM_WR(1U)
61041 #define S_ABORT_ON_CAL_ERROR 5
61042 #define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
61043 #define F_ABORT_ON_CAL_ERROR V_ABORT_ON_CAL_ERROR(1U)
61045 #define S_ENA_DIGITAL_EYE 4
61046 #define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
61047 #define F_ENA_DIGITAL_EYE V_ENA_DIGITAL_EYE(1U)
61049 #define S_ENA_RANK_PAIR 0
61050 #define M_ENA_RANK_PAIR 0xfU
61051 #define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
61052 #define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
61054 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
61056 #define S_REFRESH_COUNT 12
61057 #define M_REFRESH_COUNT 0xfU
61058 #define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
61059 #define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
61061 #define S_REFRESH_CONTROL 10
61062 #define M_REFRESH_CONTROL 0x3U
61063 #define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
61064 #define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
61066 #define S_REFRESH_ALL_RANKS 9
61067 #define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
61068 #define F_REFRESH_ALL_RANKS V_REFRESH_ALL_RANKS(1U)
61070 #define S_REFRESH_INTERVAL 0
61071 #define M_REFRESH_INTERVAL 0x7fU
61072 #define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
61073 #define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
61075 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
61077 #define S_ERROR_WR_LEVEL 15
61078 #define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
61079 #define F_ERROR_WR_LEVEL V_ERROR_WR_LEVEL(1U)
61081 #define S_ERROR_INITIAL_PAT_WRITE 14
61082 #define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
61083 #define F_ERROR_INITIAL_PAT_WRITE V_ERROR_INITIAL_PAT_WRITE(1U)
61085 #define S_ERROR_DQS_ALIGN 13
61086 #define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
61087 #define F_ERROR_DQS_ALIGN V_ERROR_DQS_ALIGN(1U)
61089 #define S_ERROR_RDCLK_ALIGN 12
61090 #define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
61091 #define F_ERROR_RDCLK_ALIGN V_ERROR_RDCLK_ALIGN(1U)
61093 #define S_ERROR_READ_CTR 11
61094 #define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
61095 #define F_ERROR_READ_CTR V_ERROR_READ_CTR(1U)
61097 #define S_ERROR_WRITE_CTR 10
61098 #define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
61099 #define F_ERROR_WRITE_CTR V_ERROR_WRITE_CTR(1U)
61101 #define S_ERROR_INITIAL_COARSE_WR 9
61102 #define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
61103 #define F_ERROR_INITIAL_COARSE_WR V_ERROR_INITIAL_COARSE_WR(1U)
61105 #define S_ERROR_COARSE_RD 8
61106 #define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
61107 #define F_ERROR_COARSE_RD V_ERROR_COARSE_RD(1U)
61109 #define S_ERROR_CUSTOM_RD 7
61110 #define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
61111 #define F_ERROR_CUSTOM_RD V_ERROR_CUSTOM_RD(1U)
61113 #define S_ERROR_CUSTOM_WR 6
61114 #define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
61115 #define F_ERROR_CUSTOM_WR V_ERROR_CUSTOM_WR(1U)
61117 #define S_ERROR_DIGITAL_EYE 5
61118 #define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
61119 #define F_ERROR_DIGITAL_EYE V_ERROR_DIGITAL_EYE(1U)
61121 #define S_ERROR_RANK_PAIR 0
61122 #define M_ERROR_RANK_PAIR 0xfU
61123 #define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
61124 #define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
61126 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
61128 #define S_INIT_CAL_COMPLETE 12
61129 #define M_INIT_CAL_COMPLETE 0xfU
61130 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
61131 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
61133 #define S_PER_CAL_ABORT 6
61134 #define V_PER_CAL_ABORT(x) ((x) << S_PER_CAL_ABORT)
61135 #define F_PER_CAL_ABORT V_PER_CAL_ABORT(1U)
61137 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
61139 #define S_ERROR_WR_LEVEL_MASK 15
61140 #define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
61141 #define F_ERROR_WR_LEVEL_MASK V_ERROR_WR_LEVEL_MASK(1U)
61143 #define S_ERROR_INITIAL_PAT_WRITE_MASK 14
61144 #define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
61145 #define F_ERROR_INITIAL_PAT_WRITE_MASK V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
61147 #define S_ERROR_DQS_ALIGN_MASK 13
61148 #define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
61149 #define F_ERROR_DQS_ALIGN_MASK V_ERROR_DQS_ALIGN_MASK(1U)
61151 #define S_ERROR_RDCLK_ALIGN_MASK 12
61152 #define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
61153 #define F_ERROR_RDCLK_ALIGN_MASK V_ERROR_RDCLK_ALIGN_MASK(1U)
61155 #define S_ERROR_READ_CTR_MASK 11
61156 #define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
61157 #define F_ERROR_READ_CTR_MASK V_ERROR_READ_CTR_MASK(1U)
61159 #define S_ERROR_WRITE_CTR_MASK 10
61160 #define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
61161 #define F_ERROR_WRITE_CTR_MASK V_ERROR_WRITE_CTR_MASK(1U)
61163 #define S_ERROR_INITIAL_COARSE_WR_MASK 9
61164 #define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
61165 #define F_ERROR_INITIAL_COARSE_WR_MASK V_ERROR_INITIAL_COARSE_WR_MASK(1U)
61167 #define S_ERROR_COARSE_RD_MASK 8
61168 #define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
61169 #define F_ERROR_COARSE_RD_MASK V_ERROR_COARSE_RD_MASK(1U)
61171 #define S_ERROR_CUSTOM_RD_MASK 7
61172 #define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
61173 #define F_ERROR_CUSTOM_RD_MASK V_ERROR_CUSTOM_RD_MASK(1U)
61175 #define S_ERROR_CUSTOM_WR_MASK 6
61176 #define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
61177 #define F_ERROR_CUSTOM_WR_MASK V_ERROR_CUSTOM_WR_MASK(1U)
61179 #define S_ERROR_DIGITAL_EYE_MASK 5
61180 #define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
61181 #define F_ERROR_DIGITAL_EYE_MASK V_ERROR_DIGITAL_EYE_MASK(1U)
61183 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
61184 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
61186 #define S_MODEREGISTER0VALUE 0
61187 #define M_MODEREGISTER0VALUE 0xffffU
61188 #define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
61189 #define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
61191 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
61193 #define S_MODEREGISTER1VALUE 0
61194 #define M_MODEREGISTER1VALUE 0xffffU
61195 #define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
61196 #define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
61198 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
61200 #define S_MODEREGISTER2VALUE 0
61201 #define M_MODEREGISTER2VALUE 0xffffU
61202 #define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
61203 #define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
61205 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
61207 #define S_MODEREGISTER3VALUE 0
61208 #define M_MODEREGISTER3VALUE 0xffffU
61209 #define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
61210 #define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
61212 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
61213 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
61214 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
61215 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
61217 #define S_MODE_REGISTER_3_VALUE 0
61218 #define M_MODE_REGISTER_3_VALUE 0xffffU
61219 #define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
61220 #define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
61222 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
61224 #define S_DRD_WR_DATA_REG 0
61225 #define M_DRD_WR_DATA_REG 0xffffU
61226 #define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
61227 #define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
61229 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
61230 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
61232 #define S_MPR_PATTERN_BIT 15
61233 #define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
61234 #define F_MPR_PATTERN_BIT V_MPR_PATTERN_BIT(1U)
61236 #define S_TWO_CYCLE_ADDR_EN 14
61237 #define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
61238 #define F_TWO_CYCLE_ADDR_EN V_TWO_CYCLE_ADDR_EN(1U)
61240 #define S_MR_MASK_EN 10
61241 #define M_MR_MASK_EN 0xfU
61242 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
61243 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
61245 #define S_PARITY_DLY 9
61246 #define V_PARITY_DLY(x) ((x) << S_PARITY_DLY)
61247 #define F_PARITY_DLY V_PARITY_DLY(1U)
61249 #define S_FORCE_RESERVED 7
61250 #define V_FORCE_RESERVED(x) ((x) << S_FORCE_RESERVED)
61251 #define F_FORCE_RESERVED V_FORCE_RESERVED(1U)
61253 #define S_HALT_ROTATION 6
61254 #define V_HALT_ROTATION(x) ((x) << S_HALT_ROTATION)
61255 #define F_HALT_ROTATION V_HALT_ROTATION(1U)
61257 #define S_FORCE_MPR 5
61258 #define V_FORCE_MPR(x) ((x) << S_FORCE_MPR)
61259 #define F_FORCE_MPR V_FORCE_MPR(1U)
61261 #define S_IPW_SIDEAB_SEL 2
61262 #define V_IPW_SIDEAB_SEL(x) ((x) << S_IPW_SIDEAB_SEL)
61263 #define F_IPW_SIDEAB_SEL V_IPW_SIDEAB_SEL(1U)
61265 #define S_PARITY_A17_MASK 1
61266 #define V_PARITY_A17_MASK(x) ((x) << S_PARITY_A17_MASK)
61267 #define F_PARITY_A17_MASK V_PARITY_A17_MASK(1U)
61269 #define S_X16_DEVICE 0
61270 #define V_X16_DEVICE(x) ((x) << S_X16_DEVICE)
61271 #define F_X16_DEVICE V_X16_DEVICE(1U)
61273 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
61274 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
61275 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
61276 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
61277 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
61278 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
61280 #define S_MULTIPLE_REQ_ERROR 15
61281 #define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
61282 #define F_MULTIPLE_REQ_ERROR V_MULTIPLE_REQ_ERROR(1U)
61284 #define S_INVALID_REQTYPE_ERRO 14
61285 #define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
61286 #define F_INVALID_REQTYPE_ERRO V_INVALID_REQTYPE_ERRO(1U)
61288 #define S_EARLY_REQ_ERROR 13
61289 #define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
61290 #define F_EARLY_REQ_ERROR V_EARLY_REQ_ERROR(1U)
61292 #define S_MULTIPLE_REQ_SOURCE 10
61293 #define M_MULTIPLE_REQ_SOURCE 0x7U
61294 #define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
61295 #define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
61297 #define S_INVALID_REQTYPE 6
61298 #define M_INVALID_REQTYPE 0xfU
61299 #define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
61300 #define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
61302 #define S_INVALID_REQ_SOURCE 3
61303 #define M_INVALID_REQ_SOURCE 0x7U
61304 #define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
61305 #define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
61307 #define S_EARLY_REQ_SOURCE 0
61308 #define M_EARLY_REQ_SOURCE 0x7U
61309 #define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
61310 #define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
61312 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
61314 #define S_MULT_REQ_ERR_MASK 15
61315 #define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
61316 #define F_MULT_REQ_ERR_MASK V_MULT_REQ_ERR_MASK(1U)
61318 #define S_INVALID_REQTYPE_ERR_MASK 14
61319 #define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
61320 #define F_INVALID_REQTYPE_ERR_MASK V_INVALID_REQTYPE_ERR_MASK(1U)
61322 #define S_EARLY_REQ_ERR_MASK 13
61323 #define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
61324 #define F_EARLY_REQ_ERR_MASK V_EARLY_REQ_ERR_MASK(1U)
61326 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
61328 #define S_ODT_WR_VALUES_BITS0_7 8
61329 #define M_ODT_WR_VALUES_BITS0_7 0xffU
61330 #define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
61331 #define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
61333 #define S_ODT_WR_VALUES_BITS8_15 0
61334 #define M_ODT_WR_VALUES_BITS8_15 0xffU
61335 #define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
61336 #define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
61338 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
61339 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
61340 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
61341 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
61343 #define S_ODT_RD_VALUES_X2 8
61344 #define M_ODT_RD_VALUES_X2 0xffU
61345 #define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
61346 #define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
61348 #define S_ODT_RD_VALUES_X2PLUS1 0
61349 #define M_ODT_RD_VALUES_X2PLUS1 0xffU
61350 #define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
61351 #define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
61353 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
61354 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
61355 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
61356 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
61358 #define S_TMOD_CYCLES 12
61359 #define M_TMOD_CYCLES 0xfU
61360 #define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
61361 #define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
61363 #define S_TRCD_CYCLES 8
61364 #define M_TRCD_CYCLES 0xfU
61365 #define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
61366 #define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
61368 #define S_TRP_CYCLES 4
61369 #define M_TRP_CYCLES 0xfU
61370 #define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
61371 #define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
61373 #define S_TRFC_CYCLES 0
61374 #define M_TRFC_CYCLES 0xfU
61375 #define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
61376 #define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
61378 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
61380 #define S_TZQINIT_CYCLES 12
61381 #define M_TZQINIT_CYCLES 0xfU
61382 #define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
61383 #define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
61385 #define S_TZQCS_CYCLES 8
61386 #define M_TZQCS_CYCLES 0xfU
61387 #define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
61388 #define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
61390 #define S_TWLDQSEN_CYCLES 4
61391 #define M_TWLDQSEN_CYCLES 0xfU
61392 #define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
61393 #define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
61395 #define S_TWRMRD_CYCLES 0
61396 #define M_TWRMRD_CYCLES 0xfU
61397 #define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
61398 #define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
61400 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
61402 #define S_TODTLON_OFF_CYCLES 12
61403 #define M_TODTLON_OFF_CYCLES 0xfU
61404 #define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
61405 #define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
61407 #define S_TRC_CYCLES 8
61408 #define M_TRC_CYCLES 0xfU
61409 #define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
61410 #define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
61412 #define S_TMRSC_CYCLES 4
61413 #define M_TMRSC_CYCLES 0xfU
61414 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
61415 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
61417 #define S_MRS_CMD_SPACE 0
61418 #define M_MRS_CMD_SPACE 0xfU
61419 #define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE)
61420 #define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE)
61422 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
61424 #define S_GLOBAL_PHY_OFFSET 12
61425 #define M_GLOBAL_PHY_OFFSET 0xfU
61426 #define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
61427 #define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
61429 #define S_ADVANCE_RD_VALID 11
61430 #define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
61431 #define F_ADVANCE_RD_VALID V_ADVANCE_RD_VALID(1U)
61433 #define S_SINGLE_BIT_MPR_RP0 6
61434 #define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
61435 #define F_SINGLE_BIT_MPR_RP0 V_SINGLE_BIT_MPR_RP0(1U)
61437 #define S_SINGLE_BIT_MPR_RP1 5
61438 #define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
61439 #define F_SINGLE_BIT_MPR_RP1 V_SINGLE_BIT_MPR_RP1(1U)
61441 #define S_SINGLE_BIT_MPR_RP2 4
61442 #define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
61443 #define F_SINGLE_BIT_MPR_RP2 V_SINGLE_BIT_MPR_RP2(1U)
61445 #define S_SINGLE_BIT_MPR_RP3 3
61446 #define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
61447 #define F_SINGLE_BIT_MPR_RP3 V_SINGLE_BIT_MPR_RP3(1U)
61449 #define S_ALIGN_ON_EVEN_CYCLES 2
61450 #define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
61451 #define F_ALIGN_ON_EVEN_CYCLES V_ALIGN_ON_EVEN_CYCLES(1U)
61453 #define S_PERFORM_RDCLK_ALIGN 1
61454 #define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
61455 #define F_PERFORM_RDCLK_ALIGN V_PERFORM_RDCLK_ALIGN(1U)
61457 #define S_STAGGERED_PATTERN 0
61458 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
61459 #define F_STAGGERED_PATTERN V_STAGGERED_PATTERN(1U)
61461 #define S_ERS_MODE 10
61462 #define V_ERS_MODE(x) ((x) << S_ERS_MODE)
61463 #define F_ERS_MODE V_ERS_MODE(1U)
61465 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
61467 #define S_OUTER_LOOP_CNT 2
61468 #define M_OUTER_LOOP_CNT 0x3fffU
61469 #define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
61470 #define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
61472 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
61474 #define S_CONSEQ_PASS 11
61475 #define M_CONSEQ_PASS 0x1fU
61476 #define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
61477 #define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
61479 #define S_BURST_WINDOW 5
61480 #define M_BURST_WINDOW 0x3U
61481 #define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
61482 #define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
61484 #define S_ALLOW_RD_FIFO_AUTO_R_ESET 4
61485 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
61486 #define F_ALLOW_RD_FIFO_AUTO_R_ESET V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
61488 #define S_DIS_LOW_PWR_PER_CAL 3
61489 #define V_DIS_LOW_PWR_PER_CAL(x) ((x) << S_DIS_LOW_PWR_PER_CAL)
61490 #define F_DIS_LOW_PWR_PER_CAL V_DIS_LOW_PWR_PER_CAL(1U)
61492 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
61494 #define S_RD_CNTL_ERROR 15
61495 #define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
61496 #define F_RD_CNTL_ERROR V_RD_CNTL_ERROR(1U)
61498 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
61500 #define S_RD_CNTL_ERROR_MASK 15
61501 #define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
61502 #define F_RD_CNTL_ERROR_MASK V_RD_CNTL_ERROR_MASK(1U)
61504 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
61506 #define S_FINE_CAL_STEP_SIZE 13
61507 #define M_FINE_CAL_STEP_SIZE 0x7U
61508 #define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
61509 #define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
61511 #define S_COARSE_CAL_STEP_SIZE 9
61512 #define M_COARSE_CAL_STEP_SIZE 0xfU
61513 #define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
61514 #define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
61516 #define S_DQ_SEL_QUAD 7
61517 #define M_DQ_SEL_QUAD 0x3U
61518 #define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
61519 #define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
61521 #define S_DQ_SEL_LANE 4
61522 #define M_DQ_SEL_LANE 0x7U
61523 #define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
61524 #define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
61526 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
61527 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
61529 #define S_TWLO_TWLOE 8
61530 #define M_TWLO_TWLOE 0xffU
61531 #define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
61532 #define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
61534 #define S_WL_ONE_DQS_PULSE 7
61535 #define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
61536 #define F_WL_ONE_DQS_PULSE V_WL_ONE_DQS_PULSE(1U)
61538 #define S_FW_WR_RD 1
61539 #define M_FW_WR_RD 0x3fU
61540 #define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
61541 #define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
61543 #define S_CUSTOM_INIT_WRITE 0
61544 #define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
61545 #define F_CUSTOM_INIT_WRITE V_CUSTOM_INIT_WRITE(1U)
61547 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
61549 #define S_BIG_STEP 12
61550 #define M_BIG_STEP 0xfU
61551 #define V_BIG_STEP(x) ((x) << S_BIG_STEP)
61552 #define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
61554 #define S_SMALL_STEP 9
61555 #define M_SMALL_STEP 0x7U
61556 #define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
61557 #define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
61559 #define S_WR_PRE_DLY 3
61560 #define M_WR_PRE_DLY 0x3fU
61561 #define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
61562 #define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
61564 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
61566 #define S_NUM_VALID_SAMPLES 12
61567 #define M_NUM_VALID_SAMPLES 0xfU
61568 #define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
61569 #define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
61571 #define S_FW_RD_WR 6
61572 #define M_FW_RD_WR 0x3fU
61573 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
61574 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
61576 #define S_EN_RESET_WR_DELAY_WL 0
61577 #define V_EN_RESET_WR_DELAY_WL(x) ((x) << S_EN_RESET_WR_DELAY_WL)
61578 #define F_EN_RESET_WR_DELAY_WL V_EN_RESET_WR_DELAY_WL(1U)
61580 #define S_TWR_MPR 2
61581 #define M_TWR_MPR 0xfU
61582 #define V_TWR_MPR(x) ((x) << S_TWR_MPR)
61583 #define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR)
61585 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
61587 #define S_WR_CNTL_ERROR 15
61588 #define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
61589 #define F_WR_CNTL_ERROR V_WR_CNTL_ERROR(1U)
61591 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
61593 #define S_WR_CNTL_ERROR_MASK 15
61594 #define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
61595 #define F_WR_CNTL_ERROR_MASK V_WR_CNTL_ERROR_MASK(1U)
61597 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
61599 #define S_DDR4_MRS_CMD_DQ_EN 15
61600 #define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
61601 #define F_DDR4_MRS_CMD_DQ_EN V_DDR4_MRS_CMD_DQ_EN(1U)
61603 #define S_MRS_CMD_DQ_ON 9
61604 #define M_MRS_CMD_DQ_ON 0x3fU
61605 #define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
61606 #define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
61608 #define S_MRS_CMD_DQ_OFF 3
61609 #define M_MRS_CMD_DQ_OFF 0x3fU
61610 #define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
61611 #define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
61613 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
61615 #define S_WRCLK_CAL_START 15
61616 #define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
61617 #define F_WRCLK_CAL_START V_WRCLK_CAL_START(1U)
61619 #define S_WRCLK_CAL_DONE 14
61620 #define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
61621 #define F_WRCLK_CAL_DONE V_WRCLK_CAL_DONE(1U)
61623 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
61625 #define S_DISABLE_PARITY_CHECKER 15
61626 #define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
61627 #define F_DISABLE_PARITY_CHECKER V_DISABLE_PARITY_CHECKER(1U)
61629 #define S_GENERATE_EVEN_PARITY 14
61630 #define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
61631 #define F_GENERATE_EVEN_PARITY V_GENERATE_EVEN_PARITY(1U)
61633 #define S_FORCE_ON_CLK_GATE 13
61634 #define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
61635 #define F_FORCE_ON_CLK_GATE V_FORCE_ON_CLK_GATE(1U)
61637 #define S_DEBUG_BUS_SEL_LO 12
61638 #define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
61639 #define F_DEBUG_BUS_SEL_LO V_DEBUG_BUS_SEL_LO(1U)
61641 #define S_DEBUG_BUS_SEL_HI 8
61642 #define M_DEBUG_BUS_SEL_HI 0xfU
61643 #define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
61644 #define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
61646 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
61648 #define S_INVALID_ADDRESS 15
61649 #define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
61650 #define F_INVALID_ADDRESS V_INVALID_ADDRESS(1U)
61652 #define S_WR_PAR_ERR 14
61653 #define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
61654 #define F_WR_PAR_ERR V_WR_PAR_ERR(1U)
61656 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
61658 #define S_INVALID_ADDRESS_MASK 15
61659 #define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
61660 #define F_INVALID_ADDRESS_MASK V_INVALID_ADDRESS_MASK(1U)
61662 #define S_WR_PAR_ERR_MASK 14
61663 #define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
61664 #define F_WR_PAR_ERR_MASK V_WR_PAR_ERR_MASK(1U)
61666 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
61668 #define S_DP18_0_POPULATED 15
61669 #define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
61670 #define F_DP18_0_POPULATED V_DP18_0_POPULATED(1U)
61672 #define S_DP18_1_POPULATED 14
61673 #define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
61674 #define F_DP18_1_POPULATED V_DP18_1_POPULATED(1U)
61676 #define S_DP18_2_POPULATED 13
61677 #define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
61678 #define F_DP18_2_POPULATED V_DP18_2_POPULATED(1U)
61680 #define S_DP18_3_POPULATED 12
61681 #define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
61682 #define F_DP18_3_POPULATED V_DP18_3_POPULATED(1U)
61684 #define S_DP18_4_POPULATED 11
61685 #define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
61686 #define F_DP18_4_POPULATED V_DP18_4_POPULATED(1U)
61688 #define S_DP18_5_POPULATED 10
61689 #define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
61690 #define F_DP18_5_POPULATED V_DP18_5_POPULATED(1U)
61692 #define S_DP18_6_POPULATED 9
61693 #define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
61694 #define F_DP18_6_POPULATED V_DP18_6_POPULATED(1U)
61696 #define S_DP18_7_POPULATED 8
61697 #define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
61698 #define F_DP18_7_POPULATED V_DP18_7_POPULATED(1U)
61700 #define S_DP18_8_POPULATED 7
61701 #define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
61702 #define F_DP18_8_POPULATED V_DP18_8_POPULATED(1U)
61704 #define S_DP18_9_POPULATED 6
61705 #define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
61706 #define F_DP18_9_POPULATED V_DP18_9_POPULATED(1U)
61708 #define S_DP18_10_POPULATED 5
61709 #define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
61710 #define F_DP18_10_POPULATED V_DP18_10_POPULATED(1U)
61712 #define S_DP18_11_POPULATED 4
61713 #define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
61714 #define F_DP18_11_POPULATED V_DP18_11_POPULATED(1U)
61716 #define S_DP18_12_POPULATED 3
61717 #define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
61718 #define F_DP18_12_POPULATED V_DP18_12_POPULATED(1U)
61720 #define S_DP18_13_POPULATED 2
61721 #define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
61722 #define F_DP18_13_POPULATED V_DP18_13_POPULATED(1U)
61724 #define S_DP18_14_POPULATED 1
61725 #define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
61726 #define F_DP18_14_POPULATED V_DP18_14_POPULATED(1U)
61728 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
61730 #define S_ADR16_0_POPULATED 15
61731 #define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
61732 #define F_ADR16_0_POPULATED V_ADR16_0_POPULATED(1U)
61734 #define S_ADR16_1_POPULATED 14
61735 #define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
61736 #define F_ADR16_1_POPULATED V_ADR16_1_POPULATED(1U)
61738 #define S_ADR16_2_POPULATED 13
61739 #define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
61740 #define F_ADR16_2_POPULATED V_ADR16_2_POPULATED(1U)
61742 #define S_ADR16_3_POPULATED 12
61743 #define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
61744 #define F_ADR16_3_POPULATED V_ADR16_3_POPULATED(1U)
61746 #define S_ADR12_0_POPULATED 7
61747 #define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
61748 #define F_ADR12_0_POPULATED V_ADR12_0_POPULATED(1U)
61750 #define S_ADR12_1_POPULATED 6
61751 #define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
61752 #define F_ADR12_1_POPULATED V_ADR12_1_POPULATED(1U)
61754 #define S_ADR12_2_POPULATED 5
61755 #define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
61756 #define F_ADR12_2_POPULATED V_ADR12_2_POPULATED(1U)
61758 #define S_ADR12_3_POPULATED 4
61759 #define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
61760 #define F_ADR12_3_POPULATED V_ADR12_3_POPULATED(1U)
61762 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
61764 #define S_ATEST_CNTL 10
61765 #define M_ATEST_CNTL 0x3fU
61766 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
61767 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
61769 #define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
61771 #define S_MT_DATA_MUX4_1MODE 15
61772 #define V_MT_DATA_MUX4_1MODE(x) ((x) << S_MT_DATA_MUX4_1MODE)
61773 #define F_MT_DATA_MUX4_1MODE V_MT_DATA_MUX4_1MODE(1U)
61775 #define S_MT_PLL_RESET 14
61776 #define V_MT_PLL_RESET(x) ((x) << S_MT_PLL_RESET)
61777 #define F_MT_PLL_RESET V_MT_PLL_RESET(1U)
61779 #define S_MT_SYSCLK_RESET 13
61780 #define V_MT_SYSCLK_RESET(x) ((x) << S_MT_SYSCLK_RESET)
61781 #define F_MT_SYSCLK_RESET V_MT_SYSCLK_RESET(1U)
61783 #define S_MT_GLOBAL_PHY_OFFSET 9
61784 #define M_MT_GLOBAL_PHY_OFFSET 0xfU
61785 #define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET)
61786 #define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET)
61788 #define S_MT_DQ_SEL_QUAD 7
61789 #define M_MT_DQ_SEL_QUAD 0x3U
61790 #define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD)
61791 #define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD)
61793 #define S_MT_PERFORM_RDCLK_ALIGN 6
61794 #define V_MT_PERFORM_RDCLK_ALIGN(x) ((x) << S_MT_PERFORM_RDCLK_ALIGN)
61795 #define F_MT_PERFORM_RDCLK_ALIGN V_MT_PERFORM_RDCLK_ALIGN(1U)
61797 #define S_MT_ALIGN_ON_EVEN_CYCLES 5
61798 #define V_MT_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_MT_ALIGN_ON_EVEN_CYCLES)
61799 #define F_MT_ALIGN_ON_EVEN_CYCLES V_MT_ALIGN_ON_EVEN_CYCLES(1U)
61801 #define S_MT_WRCLK_CAL_START 4
61802 #define V_MT_WRCLK_CAL_START(x) ((x) << S_MT_WRCLK_CAL_START)
61803 #define F_MT_WRCLK_CAL_START V_MT_WRCLK_CAL_START(1U)
61805 #define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
61807 #define S_MT_WPRD_ENABLE 15
61808 #define V_MT_WPRD_ENABLE(x) ((x) << S_MT_WPRD_ENABLE)
61809 #define F_MT_WPRD_ENABLE V_MT_WPRD_ENABLE(1U)
61811 #define S_MT_PVTP 10
61812 #define M_MT_PVTP 0x1fU
61813 #define V_MT_PVTP(x) ((x) << S_MT_PVTP)
61814 #define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP)
61816 #define S_MT_PVTN 5
61817 #define M_MT_PVTN 0x1fU
61818 #define V_MT_PVTN(x) ((x) << S_MT_PVTN)
61819 #define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN)
61821 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
61822 #define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
61824 #define S_MT_ADR32_PLL_LOCK_SUM 1
61825 #define V_MT_ADR32_PLL_LOCK_SUM(x) ((x) << S_MT_ADR32_PLL_LOCK_SUM)
61826 #define F_MT_ADR32_PLL_LOCK_SUM V_MT_ADR32_PLL_LOCK_SUM(1U)
61828 #define S_MT_DP18_PLL_LOCK_SUM 0
61829 #define V_MT_DP18_PLL_LOCK_SUM(x) ((x) << S_MT_DP18_PLL_LOCK_SUM)
61830 #define F_MT_DP18_PLL_LOCK_SUM V_MT_DP18_PLL_LOCK_SUM(1U)
61832 /* registers for module MC_1 */
61833 #define MC_1_BASE_ADDR 0x48000
61835 /* registers for module EDC_T50 */
61836 #define EDC_T50_BASE_ADDR 0x50000
61838 #define A_EDC_H_REF 0x50000
61840 #define S_EDC_SLEEPSTATUS 31
61841 #define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
61842 #define F_EDC_SLEEPSTATUS V_EDC_SLEEPSTATUS(1U)
61844 #define S_EDC_SLEEPREQ 30
61845 #define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
61846 #define F_EDC_SLEEPREQ V_EDC_SLEEPREQ(1U)
61848 #define S_PING_PONG 29
61849 #define V_PING_PONG(x) ((x) << S_PING_PONG)
61850 #define F_PING_PONG V_PING_PONG(1U)
61852 #define A_EDC_H_BIST_CMD 0x50004
61853 #define A_EDC_H_BIST_CMD_ADDR 0x50008
61854 #define A_EDC_H_BIST_CMD_LEN 0x5000c
61855 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
61856 #define A_EDC_H_BIST_USER_WDATA0 0x50014
61857 #define A_EDC_H_BIST_USER_WDATA1 0x50018
61858 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
61859 #define A_EDC_H_BIST_NUM_ERR 0x50020
61860 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
61861 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
61862 #define A_EDC_H_PAR_ENABLE 0x50070
61864 #define S_PERR_PAR_ENABLE 0
61865 #define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
61866 #define F_PERR_PAR_ENABLE V_PERR_PAR_ENABLE(1U)
61868 #define A_EDC_H_INT_ENABLE 0x50074
61869 #define A_EDC_H_INT_CAUSE 0x50078
61871 #define S_ECC_UE_INT0_CAUSE 5
61872 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
61873 #define F_ECC_UE_INT0_CAUSE V_ECC_UE_INT0_CAUSE(1U)
61875 #define S_ECC_CE_INT0_CAUSE 4
61876 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
61877 #define F_ECC_CE_INT0_CAUSE V_ECC_CE_INT0_CAUSE(1U)
61879 #define S_PERR_INT0_CAUSE 3
61880 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
61881 #define F_PERR_INT0_CAUSE V_PERR_INT0_CAUSE(1U)
61883 #define A_EDC_H_ECC_STATUS 0x5007c
61884 #define A_EDC_H_ECC_ERR_SEL 0x50080
61888 #define V_CFG(x) ((x) << S_CFG)
61889 #define G_CFG(x) (((x) >> S_CFG) & M_CFG)
61891 #define A_EDC_H_ECC_ERR_ADDR 0x50084
61893 #define S_ECC_ADDR 0
61894 #define M_ECC_ADDR 0x7fffffU
61895 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
61896 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
61898 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
61899 #define A_EDC_H_BIST_CRC_SEED 0x50400
61901 /* registers for module EDC_T51 */
61902 #define EDC_T51_BASE_ADDR 0x50800
61904 /* registers for module HMA_T5 */
61905 #define HMA_T5_BASE_ADDR 0x51000
61907 #define A_HMA_TABLE_ACCESS 0x51000
61910 #define V_TRIG(x) ((x) << S_TRIG)
61911 #define F_TRIG V_TRIG(1U)
61914 #define V_RW(x) ((x) << S_RW)
61915 #define F_RW V_RW(1U)
61918 #define M_L_SEL 0xfU
61919 #define V_L_SEL(x) ((x) << S_L_SEL)
61920 #define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
61922 #define A_HMA_TABLE_LINE0 0x51004
61924 #define S_CLIENT_EN 0
61925 #define M_CLIENT_EN 0x1fffU
61926 #define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
61927 #define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
61929 #define A_HMA_TABLE_LINE1 0x51008
61930 #define A_HMA_TABLE_LINE2 0x5100c
61931 #define A_HMA_TABLE_LINE3 0x51010
61932 #define A_HMA_TABLE_LINE4 0x51014
61933 #define A_HMA_TABLE_LINE5 0x51018
61936 #define M_FID 0x7ffU
61937 #define V_FID(x) ((x) << S_FID)
61938 #define G_FID(x) (((x) >> S_FID) & M_FID)
61941 #define V_NOS(x) ((x) << S_NOS)
61942 #define F_NOS V_NOS(1U)
61945 #define V_RO(x) ((x) << S_RO)
61946 #define F_RO V_RO(1U)
61948 #define A_HMA_COOKIE 0x5101c
61951 #define V_C_REQ(x) ((x) << S_C_REQ)
61952 #define F_C_REQ V_C_REQ(1U)
61955 #define M_C_FID 0x7ffU
61956 #define V_C_FID(x) ((x) << S_C_FID)
61957 #define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
61960 #define M_C_VAL 0x3ffU
61961 #define V_C_VAL(x) ((x) << S_C_VAL)
61962 #define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
61965 #define M_C_SEL 0xfU
61966 #define V_C_SEL(x) ((x) << S_C_SEL)
61967 #define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
61969 #define A_HMA_PAR_ENABLE 0x51300
61970 #define A_HMA_INT_ENABLE 0x51304
61971 #define A_HMA_INT_CAUSE 0x51308
61973 /* registers for module EDC_T60 */
61974 #define EDC_T60_BASE_ADDR 0x50000
61976 #define S_QDR_CLKPHASE 24
61977 #define M_QDR_CLKPHASE 0x7U
61978 #define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE)
61979 #define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE)
61981 #define S_MAXOPSPERTRC 21
61982 #define M_MAXOPSPERTRC 0x7U
61983 #define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC)
61984 #define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC)
61986 #define S_NUMPIPESTAGES 19
61987 #define M_NUMPIPESTAGES 0x3U
61988 #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
61989 #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
61991 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
61993 #define S_MCMDADDR 12
61994 #define M_MCMDADDR 0xfffffU
61995 #define V_MCMDADDR(x) ((x) << S_MCMDADDR)
61996 #define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR)
61998 #define S_MCMDLEN 5
61999 #define M_MCMDLEN 0x7fU
62000 #define V_MCMDLEN(x) ((x) << S_MCMDLEN)
62001 #define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN)
62003 #define S_MCMDNRE 4
62004 #define V_MCMDNRE(x) ((x) << S_MCMDNRE)
62005 #define F_MCMDNRE V_MCMDNRE(1U)
62007 #define S_MCMDNRB 3
62008 #define V_MCMDNRB(x) ((x) << S_MCMDNRB)
62009 #define F_MCMDNRB V_MCMDNRB(1U)
62012 #define V_MCMDWR(x) ((x) << S_MCMDWR)
62013 #define F_MCMDWR V_MCMDWR(1U)
62015 #define S_MCMDRDY 1
62016 #define V_MCMDRDY(x) ((x) << S_MCMDRDY)
62017 #define F_MCMDRDY V_MCMDRDY(1U)
62019 #define S_MCMDVLD 0
62020 #define V_MCMDVLD(x) ((x) << S_MCMDVLD)
62021 #define F_MCMDVLD V_MCMDVLD(1U)
62023 #define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
62025 #define S_MWDATAVLD 31
62026 #define V_MWDATAVLD(x) ((x) << S_MWDATAVLD)
62027 #define F_MWDATAVLD V_MWDATAVLD(1U)
62029 #define S_MWDATARDY 30
62030 #define V_MWDATARDY(x) ((x) << S_MWDATARDY)
62031 #define F_MWDATARDY V_MWDATARDY(1U)
62034 #define M_MWDATA 0x3fffffffU
62035 #define V_MWDATA(x) ((x) << S_MWDATA)
62036 #define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA)
62038 #define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
62040 #define S_MRSPVLD 31
62041 #define V_MRSPVLD(x) ((x) << S_MRSPVLD)
62042 #define F_MRSPVLD V_MRSPVLD(1U)
62044 #define S_MRSPRDY 30
62045 #define V_MRSPRDY(x) ((x) << S_MRSPRDY)
62046 #define F_MRSPRDY V_MRSPRDY(1U)
62048 #define S_MRSPDATA 0
62049 #define M_MRSPDATA 0x3fffffffU
62050 #define V_MRSPDATA(x) ((x) << S_MRSPDATA)
62051 #define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA)
62053 #define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
62055 #define S_BCMDADDR 9
62056 #define M_BCMDADDR 0x7fffffU
62057 #define V_BCMDADDR(x) ((x) << S_BCMDADDR)
62058 #define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR)
62060 #define S_BCMDLEN 3
62061 #define M_BCMDLEN 0x3fU
62062 #define V_BCMDLEN(x) ((x) << S_BCMDLEN)
62063 #define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN)
62066 #define V_BCMDWR(x) ((x) << S_BCMDWR)
62067 #define F_BCMDWR V_BCMDWR(1U)
62069 #define S_BCMDRDY 1
62070 #define V_BCMDRDY(x) ((x) << S_BCMDRDY)
62071 #define F_BCMDRDY V_BCMDRDY(1U)
62073 #define S_BCMDVLD 0
62074 #define V_BCMDVLD(x) ((x) << S_BCMDVLD)
62075 #define F_BCMDVLD V_BCMDVLD(1U)
62077 #define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
62079 #define S_BWDATAVLD 31
62080 #define V_BWDATAVLD(x) ((x) << S_BWDATAVLD)
62081 #define F_BWDATAVLD V_BWDATAVLD(1U)
62083 #define S_BWDATARDY 30
62084 #define V_BWDATARDY(x) ((x) << S_BWDATARDY)
62085 #define F_BWDATARDY V_BWDATARDY(1U)
62088 #define M_BWDATA 0x3fffffffU
62089 #define V_BWDATA(x) ((x) << S_BWDATA)
62090 #define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA)
62092 #define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
62094 #define S_BRSPVLD 31
62095 #define V_BRSPVLD(x) ((x) << S_BRSPVLD)
62096 #define F_BRSPVLD V_BRSPVLD(1U)
62098 #define S_BRSPRDY 30
62099 #define V_BRSPRDY(x) ((x) << S_BRSPRDY)
62100 #define F_BRSPRDY V_BRSPRDY(1U)
62102 #define S_BRSPDATA 0
62103 #define M_BRSPDATA 0x3fffffffU
62104 #define V_BRSPDATA(x) ((x) << S_BRSPDATA)
62105 #define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA)
62107 #define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
62109 #define S_EDRAMADDR 16
62110 #define M_EDRAMADDR 0xffffU
62111 #define V_EDRAMADDR(x) ((x) << S_EDRAMADDR)
62112 #define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR)
62114 #define S_EDRAMDWSN 8
62115 #define M_EDRAMDWSN 0xffU
62116 #define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN)
62117 #define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN)
62119 #define S_EDRAMCRA 5
62120 #define M_EDRAMCRA 0x7U
62121 #define V_EDRAMCRA(x) ((x) << S_EDRAMCRA)
62122 #define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA)
62124 #define S_EDRAMREFENLO 4
62125 #define V_EDRAMREFENLO(x) ((x) << S_EDRAMREFENLO)
62126 #define F_EDRAMREFENLO V_EDRAMREFENLO(1U)
62128 #define S_EDRAM1WRENLO 3
62129 #define V_EDRAM1WRENLO(x) ((x) << S_EDRAM1WRENLO)
62130 #define F_EDRAM1WRENLO V_EDRAM1WRENLO(1U)
62132 #define S_EDRAM1RDENLO 2
62133 #define V_EDRAM1RDENLO(x) ((x) << S_EDRAM1RDENLO)
62134 #define F_EDRAM1RDENLO V_EDRAM1RDENLO(1U)
62136 #define S_EDRAM0WRENLO 1
62137 #define V_EDRAM0WRENLO(x) ((x) << S_EDRAM0WRENLO)
62138 #define F_EDRAM0WRENLO V_EDRAM0WRENLO(1U)
62140 #define S_EDRAM0RDENLO 0
62141 #define V_EDRAM0RDENLO(x) ((x) << S_EDRAM0RDENLO)
62142 #define F_EDRAM0RDENLO V_EDRAM0RDENLO(1U)
62144 #define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
62146 #define S_EDRAMWDATA 9
62147 #define M_EDRAMWDATA 0x7fffffU
62148 #define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA)
62149 #define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA)
62151 #define S_EDRAMWBYTEEN 0
62152 #define M_EDRAMWBYTEEN 0x1ffU
62153 #define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN)
62154 #define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN)
62156 #define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
62157 #define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
62158 #define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
62159 #define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
62160 #define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
62161 #define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
62162 #define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
62163 #define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
62164 #define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
62165 #define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
62166 #define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
62167 #define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
62168 #define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
62169 #define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
62170 #define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
62171 #define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
62172 #define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
62173 #define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
62174 #define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
62175 #define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
62176 #define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
62177 #define A_EDC_H_DBG_FIFO_STATUS 0x50374
62179 #define S_RDTAG_NOTFULL 17
62180 #define V_RDTAG_NOTFULL(x) ((x) << S_RDTAG_NOTFULL)
62181 #define F_RDTAG_NOTFULL V_RDTAG_NOTFULL(1U)
62183 #define S_RDTAG_NOTEMPTY 16
62184 #define V_RDTAG_NOTEMPTY(x) ((x) << S_RDTAG_NOTEMPTY)
62185 #define F_RDTAG_NOTEMPTY V_RDTAG_NOTEMPTY(1U)
62187 #define S_INP_CMDQ_NOTFULL_ARB 15
62188 #define V_INP_CMDQ_NOTFULL_ARB(x) ((x) << S_INP_CMDQ_NOTFULL_ARB)
62189 #define F_INP_CMDQ_NOTFULL_ARB V_INP_CMDQ_NOTFULL_ARB(1U)
62191 #define S_INP_CMDQ_NOTEMPTY 14
62192 #define V_INP_CMDQ_NOTEMPTY(x) ((x) << S_INP_CMDQ_NOTEMPTY)
62193 #define F_INP_CMDQ_NOTEMPTY V_INP_CMDQ_NOTEMPTY(1U)
62195 #define S_INP_WRDQ_WRRDY 13
62196 #define V_INP_WRDQ_WRRDY(x) ((x) << S_INP_WRDQ_WRRDY)
62197 #define F_INP_WRDQ_WRRDY V_INP_WRDQ_WRRDY(1U)
62199 #define S_INP_WRDQ_NOTEMPTY 12
62200 #define V_INP_WRDQ_NOTEMPTY(x) ((x) << S_INP_WRDQ_NOTEMPTY)
62201 #define F_INP_WRDQ_NOTEMPTY V_INP_WRDQ_NOTEMPTY(1U)
62203 #define S_INP_BEQ_WRRDY_OPEN 11
62204 #define V_INP_BEQ_WRRDY_OPEN(x) ((x) << S_INP_BEQ_WRRDY_OPEN)
62205 #define F_INP_BEQ_WRRDY_OPEN V_INP_BEQ_WRRDY_OPEN(1U)
62207 #define S_INP_BEQ_NOTEMPTY 10
62208 #define V_INP_BEQ_NOTEMPTY(x) ((x) << S_INP_BEQ_NOTEMPTY)
62209 #define F_INP_BEQ_NOTEMPTY V_INP_BEQ_NOTEMPTY(1U)
62211 #define S_RDDQ_NOTFULL_OPEN 9
62212 #define V_RDDQ_NOTFULL_OPEN(x) ((x) << S_RDDQ_NOTFULL_OPEN)
62213 #define F_RDDQ_NOTFULL_OPEN V_RDDQ_NOTFULL_OPEN(1U)
62215 #define S_RDDQ_RDCNT 4
62216 #define M_RDDQ_RDCNT 0x1fU
62217 #define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT)
62218 #define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT)
62220 #define S_RDSIDEQ_NOTFULL 3
62221 #define V_RDSIDEQ_NOTFULL(x) ((x) << S_RDSIDEQ_NOTFULL)
62222 #define F_RDSIDEQ_NOTFULL V_RDSIDEQ_NOTFULL(1U)
62224 #define S_RDSIDEQ_NOTEMPTY 2
62225 #define V_RDSIDEQ_NOTEMPTY(x) ((x) << S_RDSIDEQ_NOTEMPTY)
62226 #define F_RDSIDEQ_NOTEMPTY V_RDSIDEQ_NOTEMPTY(1U)
62228 #define S_STG_CMDQ_NOTEMPTY 1
62229 #define V_STG_CMDQ_NOTEMPTY(x) ((x) << S_STG_CMDQ_NOTEMPTY)
62230 #define F_STG_CMDQ_NOTEMPTY V_STG_CMDQ_NOTEMPTY(1U)
62232 #define S_STG_WRDQ_NOTEMPTY 0
62233 #define V_STG_WRDQ_NOTEMPTY(x) ((x) << S_STG_WRDQ_NOTEMPTY)
62234 #define F_STG_WRDQ_NOTEMPTY V_STG_WRDQ_NOTEMPTY(1U)
62236 #define A_EDC_H_DBG_FSM_STATE 0x50378
62238 #define S_CMDSPLITFSM 3
62239 #define V_CMDSPLITFSM(x) ((x) << S_CMDSPLITFSM)
62240 #define F_CMDSPLITFSM V_CMDSPLITFSM(1U)
62243 #define M_CMDFSM 0x7U
62244 #define V_CMDFSM(x) ((x) << S_CMDFSM)
62245 #define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM)
62247 #define A_EDC_H_DBG_STALL_CYCLES 0x5037c
62249 #define S_STALL_RMW 19
62250 #define V_STALL_RMW(x) ((x) << S_STALL_RMW)
62251 #define F_STALL_RMW V_STALL_RMW(1U)
62253 #define S_STALL_EDC_CMD 18
62254 #define V_STALL_EDC_CMD(x) ((x) << S_STALL_EDC_CMD)
62255 #define F_STALL_EDC_CMD V_STALL_EDC_CMD(1U)
62257 #define S_DEAD_CYCLE0 17
62258 #define V_DEAD_CYCLE0(x) ((x) << S_DEAD_CYCLE0)
62259 #define F_DEAD_CYCLE0 V_DEAD_CYCLE0(1U)
62261 #define S_DEAD_CYCLE1 16
62262 #define V_DEAD_CYCLE1(x) ((x) << S_DEAD_CYCLE1)
62263 #define F_DEAD_CYCLE1 V_DEAD_CYCLE1(1U)
62265 #define S_DEAD_CYCLE0_BBI 15
62266 #define V_DEAD_CYCLE0_BBI(x) ((x) << S_DEAD_CYCLE0_BBI)
62267 #define F_DEAD_CYCLE0_BBI V_DEAD_CYCLE0_BBI(1U)
62269 #define S_DEAD_CYCLE1_BBI 14
62270 #define V_DEAD_CYCLE1_BBI(x) ((x) << S_DEAD_CYCLE1_BBI)
62271 #define F_DEAD_CYCLE1_BBI V_DEAD_CYCLE1_BBI(1U)
62273 #define S_DEAD_CYCLE0_MAX_OP 13
62274 #define V_DEAD_CYCLE0_MAX_OP(x) ((x) << S_DEAD_CYCLE0_MAX_OP)
62275 #define F_DEAD_CYCLE0_MAX_OP V_DEAD_CYCLE0_MAX_OP(1U)
62277 #define S_DEAD_CYCLE1_MAX_OP 12
62278 #define V_DEAD_CYCLE1_MAX_OP(x) ((x) << S_DEAD_CYCLE1_MAX_OP)
62279 #define F_DEAD_CYCLE1_MAX_OP V_DEAD_CYCLE1_MAX_OP(1U)
62281 #define S_DEAD_CYCLE0_PRE_REF 11
62282 #define V_DEAD_CYCLE0_PRE_REF(x) ((x) << S_DEAD_CYCLE0_PRE_REF)
62283 #define F_DEAD_CYCLE0_PRE_REF V_DEAD_CYCLE0_PRE_REF(1U)
62285 #define S_DEAD_CYCLE1_PRE_REF 10
62286 #define V_DEAD_CYCLE1_PRE_REF(x) ((x) << S_DEAD_CYCLE1_PRE_REF)
62287 #define F_DEAD_CYCLE1_PRE_REF V_DEAD_CYCLE1_PRE_REF(1U)
62289 #define S_DEAD_CYCLE0_POST_REF 9
62290 #define V_DEAD_CYCLE0_POST_REF(x) ((x) << S_DEAD_CYCLE0_POST_REF)
62291 #define F_DEAD_CYCLE0_POST_REF V_DEAD_CYCLE0_POST_REF(1U)
62293 #define S_DEAD_CYCLE1_POST_REF 8
62294 #define V_DEAD_CYCLE1_POST_REF(x) ((x) << S_DEAD_CYCLE1_POST_REF)
62295 #define F_DEAD_CYCLE1_POST_REF V_DEAD_CYCLE1_POST_REF(1U)
62297 #define S_DEAD_CYCLE0_RMW 7
62298 #define V_DEAD_CYCLE0_RMW(x) ((x) << S_DEAD_CYCLE0_RMW)
62299 #define F_DEAD_CYCLE0_RMW V_DEAD_CYCLE0_RMW(1U)
62301 #define S_DEAD_CYCLE1_RMW 6
62302 #define V_DEAD_CYCLE1_RMW(x) ((x) << S_DEAD_CYCLE1_RMW)
62303 #define F_DEAD_CYCLE1_RMW V_DEAD_CYCLE1_RMW(1U)
62305 #define S_DEAD_CYCLE0_BBI_RMW 5
62306 #define V_DEAD_CYCLE0_BBI_RMW(x) ((x) << S_DEAD_CYCLE0_BBI_RMW)
62307 #define F_DEAD_CYCLE0_BBI_RMW V_DEAD_CYCLE0_BBI_RMW(1U)
62309 #define S_DEAD_CYCLE1_BBI_RMW 4
62310 #define V_DEAD_CYCLE1_BBI_RMW(x) ((x) << S_DEAD_CYCLE1_BBI_RMW)
62311 #define F_DEAD_CYCLE1_BBI_RMW V_DEAD_CYCLE1_BBI_RMW(1U)
62313 #define S_DEAD_CYCLE0_PRE_REF_RMW 3
62314 #define V_DEAD_CYCLE0_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE0_PRE_REF_RMW)
62315 #define F_DEAD_CYCLE0_PRE_REF_RMW V_DEAD_CYCLE0_PRE_REF_RMW(1U)
62317 #define S_DEAD_CYCLE1_PRE_REF_RMW 2
62318 #define V_DEAD_CYCLE1_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE1_PRE_REF_RMW)
62319 #define F_DEAD_CYCLE1_PRE_REF_RMW V_DEAD_CYCLE1_PRE_REF_RMW(1U)
62321 #define S_DEAD_CYCLE0_POST_REF_RMW 1
62322 #define V_DEAD_CYCLE0_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE0_POST_REF_RMW)
62323 #define F_DEAD_CYCLE0_POST_REF_RMW V_DEAD_CYCLE0_POST_REF_RMW(1U)
62325 #define S_DEAD_CYCLE1_POST_REF_RMW 0
62326 #define V_DEAD_CYCLE1_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE1_POST_REF_RMW)
62327 #define F_DEAD_CYCLE1_POST_REF_RMW V_DEAD_CYCLE1_POST_REF_RMW(1U)
62329 #define A_EDC_H_DBG_CMD_QUEUE 0x50380
62331 #define S_ECMDNRE 31
62332 #define V_ECMDNRE(x) ((x) << S_ECMDNRE)
62333 #define F_ECMDNRE V_ECMDNRE(1U)
62335 #define S_ECMDNRB 30
62336 #define V_ECMDNRB(x) ((x) << S_ECMDNRB)
62337 #define F_ECMDNRB V_ECMDNRB(1U)
62339 #define S_ECMDWR 29
62340 #define V_ECMDWR(x) ((x) << S_ECMDWR)
62341 #define F_ECMDWR V_ECMDWR(1U)
62343 #define S_ECMDLEN 22
62344 #define M_ECMDLEN 0x7fU
62345 #define V_ECMDLEN(x) ((x) << S_ECMDLEN)
62346 #define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN)
62348 #define S_ECMDADDR 0
62349 #define M_ECMDADDR 0x3fffffU
62350 #define V_ECMDADDR(x) ((x) << S_ECMDADDR)
62351 #define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR)
62353 #define A_EDC_H_DBG_REFRESH 0x50384
62355 #define S_REFDONE 12
62356 #define V_REFDONE(x) ((x) << S_REFDONE)
62357 #define F_REFDONE V_REFDONE(1U)
62359 #define S_REFCNTEXPR 11
62360 #define V_REFCNTEXPR(x) ((x) << S_REFCNTEXPR)
62361 #define F_REFCNTEXPR V_REFCNTEXPR(1U)
62364 #define M_REFPTR 0x7U
62365 #define V_REFPTR(x) ((x) << S_REFPTR)
62366 #define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR)
62369 #define M_REFCNT 0xffU
62370 #define V_REFCNT(x) ((x) << S_REFCNT)
62371 #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
62373 /* registers for module EDC_T61 */
62374 #define EDC_T61_BASE_ADDR 0x50800
62376 /* registers for module HMA_T6 */
62377 #define HMA_T6_BASE_ADDR 0x51000
62381 #define V_TPH(x) ((x) << S_TPH)
62382 #define G_TPH(x) (((x) >> S_TPH) & M_TPH)
62385 #define V_TPH_V(x) ((x) << S_TPH_V)
62386 #define F_TPH_V V_TPH_V(1U)
62389 #define M_DCA 0x7ffU
62390 #define V_DCA(x) ((x) << S_DCA)
62391 #define G_DCA(x) (((x) >> S_DCA) & M_DCA)
62393 #define A_HMA_CFG 0x51020
62395 #define S_OP_MODE 31
62396 #define V_OP_MODE(x) ((x) << S_OP_MODE)
62397 #define F_OP_MODE V_OP_MODE(1U)
62399 #define A_HMA_TLB_ACCESS 0x51028
62401 #define S_INV_ALL 29
62402 #define V_INV_ALL(x) ((x) << S_INV_ALL)
62403 #define F_INV_ALL V_INV_ALL(1U)
62405 #define S_LOCK_ENTRY 28
62406 #define V_LOCK_ENTRY(x) ((x) << S_LOCK_ENTRY)
62407 #define F_LOCK_ENTRY V_LOCK_ENTRY(1U)
62410 #define M_E_SEL 0x1fU
62411 #define V_E_SEL(x) ((x) << S_E_SEL)
62412 #define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL)
62414 #define A_HMA_TLB_BITS 0x5102c
62417 #define M_VA 0xfffffU
62418 #define V_VA(x) ((x) << S_VA)
62419 #define G_VA(x) (((x) >> S_VA) & M_VA)
62421 #define S_VALID_E 4
62422 #define V_VALID_E(x) ((x) << S_VALID_E)
62423 #define F_VALID_E V_VALID_E(1U)
62425 #define S_LOCK_HMA 3
62426 #define V_LOCK_HMA(x) ((x) << S_LOCK_HMA)
62427 #define F_LOCK_HMA V_LOCK_HMA(1U)
62429 #define S_T6_USED 2
62430 #define V_T6_USED(x) ((x) << S_T6_USED)
62431 #define F_T6_USED V_T6_USED(1U)
62434 #define M_REGION 0x3U
62435 #define V_REGION(x) ((x) << S_REGION)
62436 #define G_REGION(x) (((x) >> S_REGION) & M_REGION)
62438 #define A_HMA_TLB_DESC_0_H 0x51030
62439 #define A_HMA_TLB_DESC_0_L 0x51034
62440 #define A_HMA_TLB_DESC_1_H 0x51038
62441 #define A_HMA_TLB_DESC_1_L 0x5103c
62442 #define A_HMA_TLB_DESC_2_H 0x51040
62443 #define A_HMA_TLB_DESC_2_L 0x51044
62444 #define A_HMA_TLB_DESC_3_H 0x51048
62445 #define A_HMA_TLB_DESC_3_L 0x5104c
62446 #define A_HMA_TLB_DESC_4_H 0x51050
62447 #define A_HMA_TLB_DESC_4_L 0x51054
62448 #define A_HMA_TLB_DESC_5_H 0x51058
62449 #define A_HMA_TLB_DESC_5_L 0x5105c
62450 #define A_HMA_TLB_DESC_6_H 0x51060
62451 #define A_HMA_TLB_DESC_6_L 0x51064
62452 #define A_HMA_TLB_DESC_7_H 0x51068
62453 #define A_HMA_TLB_DESC_7_L 0x5106c
62454 #define A_HMA_REG0_MIN 0x51070
62456 #define S_ADDR0_MIN 12
62457 #define M_ADDR0_MIN 0xfffffU
62458 #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
62459 #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
62461 #define A_HMA_REG0_MAX 0x51074
62463 #define S_ADDR0_MAX 12
62464 #define M_ADDR0_MAX 0xfffffU
62465 #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
62466 #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
62468 #define A_HMA_REG0_MASK 0x51078
62470 #define S_PAGE_SIZE0 12
62471 #define M_PAGE_SIZE0 0xfffffU
62472 #define V_PAGE_SIZE0(x) ((x) << S_PAGE_SIZE0)
62473 #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
62475 #define A_HMA_REG0_BASE 0x5107c
62476 #define A_HMA_REG1_MIN 0x51080
62478 #define S_ADDR1_MIN 12
62479 #define M_ADDR1_MIN 0xfffffU
62480 #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
62481 #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
62483 #define A_HMA_REG1_MAX 0x51084
62485 #define S_ADDR1_MAX 12
62486 #define M_ADDR1_MAX 0xfffffU
62487 #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
62488 #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
62490 #define A_HMA_REG1_MASK 0x51088
62492 #define S_PAGE_SIZE1 12
62493 #define M_PAGE_SIZE1 0xfffffU
62494 #define V_PAGE_SIZE1(x) ((x) << S_PAGE_SIZE1)
62495 #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
62497 #define A_HMA_REG1_BASE 0x5108c
62498 #define A_HMA_REG2_MIN 0x51090
62500 #define S_ADDR2_MIN 12
62501 #define M_ADDR2_MIN 0xfffffU
62502 #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
62503 #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
62505 #define A_HMA_REG2_MAX 0x51094
62507 #define S_ADDR2_MAX 12
62508 #define M_ADDR2_MAX 0xfffffU
62509 #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
62510 #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
62512 #define A_HMA_REG2_MASK 0x51098
62514 #define S_PAGE_SIZE2 12
62515 #define M_PAGE_SIZE2 0xfffffU
62516 #define V_PAGE_SIZE2(x) ((x) << S_PAGE_SIZE2)
62517 #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
62519 #define A_HMA_REG2_BASE 0x5109c
62520 #define A_HMA_REG3_MIN 0x510a0
62522 #define S_ADDR3_MIN 12
62523 #define M_ADDR3_MIN 0xfffffU
62524 #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
62525 #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
62527 #define A_HMA_REG3_MAX 0x510a4
62529 #define S_ADDR3_MAX 12
62530 #define M_ADDR3_MAX 0xfffffU
62531 #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
62532 #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
62534 #define A_HMA_REG3_MASK 0x510a8
62536 #define S_PAGE_SIZE3 12
62537 #define M_PAGE_SIZE3 0xfffffU
62538 #define V_PAGE_SIZE3(x) ((x) << S_PAGE_SIZE3)
62539 #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
62541 #define A_HMA_REG3_BASE 0x510ac
62542 #define A_HMA_SW_SYNC 0x510b0
62544 #define S_ENTER_SYNC 31
62545 #define V_ENTER_SYNC(x) ((x) << S_ENTER_SYNC)
62546 #define F_ENTER_SYNC V_ENTER_SYNC(1U)
62548 #define S_EXIT_SYNC 30
62549 #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
62550 #define F_EXIT_SYNC V_EXIT_SYNC(1U)
62552 #define S_IDTF_INT_ENABLE 5
62553 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
62554 #define F_IDTF_INT_ENABLE V_IDTF_INT_ENABLE(1U)
62556 #define S_OTF_INT_ENABLE 4
62557 #define V_OTF_INT_ENABLE(x) ((x) << S_OTF_INT_ENABLE)
62558 #define F_OTF_INT_ENABLE V_OTF_INT_ENABLE(1U)
62560 #define S_RTF_INT_ENABLE 3
62561 #define V_RTF_INT_ENABLE(x) ((x) << S_RTF_INT_ENABLE)
62562 #define F_RTF_INT_ENABLE V_RTF_INT_ENABLE(1U)
62564 #define S_PCIEMST_INT_ENABLE 2
62565 #define V_PCIEMST_INT_ENABLE(x) ((x) << S_PCIEMST_INT_ENABLE)
62566 #define F_PCIEMST_INT_ENABLE V_PCIEMST_INT_ENABLE(1U)
62568 #define S_MAMST_INT_ENABLE 1
62569 #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
62570 #define F_MAMST_INT_ENABLE V_MAMST_INT_ENABLE(1U)
62572 #define S_IDTF_INT_CAUSE 5
62573 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
62574 #define F_IDTF_INT_CAUSE V_IDTF_INT_CAUSE(1U)
62576 #define S_OTF_INT_CAUSE 4
62577 #define V_OTF_INT_CAUSE(x) ((x) << S_OTF_INT_CAUSE)
62578 #define F_OTF_INT_CAUSE V_OTF_INT_CAUSE(1U)
62580 #define S_RTF_INT_CAUSE 3
62581 #define V_RTF_INT_CAUSE(x) ((x) << S_RTF_INT_CAUSE)
62582 #define F_RTF_INT_CAUSE V_RTF_INT_CAUSE(1U)
62584 #define S_PCIEMST_INT_CAUSE 2
62585 #define V_PCIEMST_INT_CAUSE(x) ((x) << S_PCIEMST_INT_CAUSE)
62586 #define F_PCIEMST_INT_CAUSE V_PCIEMST_INT_CAUSE(1U)
62588 #define S_MAMST_INT_CAUSE 1
62589 #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
62590 #define F_MAMST_INT_CAUSE V_MAMST_INT_CAUSE(1U)
62592 #define A_HMA_MA_MST_ERR 0x5130c
62593 #define A_HMA_RTF_ERR 0x51310
62594 #define A_HMA_OTF_ERR 0x51314
62595 #define A_HMA_IDTF_ERR 0x51318
62596 #define A_HMA_EXIT_TF 0x5131c
62599 #define V_RTF(x) ((x) << S_RTF)
62600 #define F_RTF V_RTF(1U)
62603 #define V_OTF(x) ((x) << S_OTF)
62604 #define F_OTF V_OTF(1U)
62607 #define V_IDTF(x) ((x) << S_IDTF)
62608 #define F_IDTF V_IDTF(1U)
62610 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
62611 #define A_HMA_LOCAL_DEBUG_RPT 0x51324
62612 #define A_HMA_DEBUG_FSM_0 0xa000
62614 #define S_EDC_FSM 18
62615 #define M_EDC_FSM 0x1fU
62616 #define V_EDC_FSM(x) ((x) << S_EDC_FSM)
62617 #define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM)
62619 #define S_RAS_FSM_SLV 15
62620 #define M_RAS_FSM_SLV 0x7U
62621 #define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV)
62622 #define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV)
62624 #define S_FC_FSM 10
62625 #define M_FC_FSM 0x1fU
62626 #define V_FC_FSM(x) ((x) << S_FC_FSM)
62627 #define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM)
62629 #define S_COOKIE_ARB_FSM 8
62630 #define M_COOKIE_ARB_FSM 0x3U
62631 #define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM)
62632 #define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM)
62634 #define S_PCIE_CHUNK_FSM 6
62635 #define M_PCIE_CHUNK_FSM 0x3U
62636 #define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM)
62637 #define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM)
62639 #define S_WTRANSFER_FSM 4
62640 #define M_WTRANSFER_FSM 0x3U
62641 #define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM)
62642 #define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM)
62645 #define M_WD_FSM 0x3U
62646 #define V_WD_FSM(x) ((x) << S_WD_FSM)
62647 #define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM)
62650 #define M_RD_FSM 0x3U
62651 #define V_RD_FSM(x) ((x) << S_RD_FSM)
62652 #define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM)
62654 #define A_HMA_DEBUG_FSM_1 0xa001
62656 #define S_SYNC_FSM 11
62657 #define M_SYNC_FSM 0x3ffU
62658 #define V_SYNC_FSM(x) ((x) << S_SYNC_FSM)
62659 #define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM)
62661 #define S_OCHK_FSM 9
62662 #define M_OCHK_FSM 0x3U
62663 #define V_OCHK_FSM(x) ((x) << S_OCHK_FSM)
62664 #define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM)
62666 #define S_TLB_FSM 5
62667 #define M_TLB_FSM 0xfU
62668 #define V_TLB_FSM(x) ((x) << S_TLB_FSM)
62669 #define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM)
62671 #define S_PIO_FSM 0
62672 #define M_PIO_FSM 0x1fU
62673 #define V_PIO_FSM(x) ((x) << S_PIO_FSM)
62674 #define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM)
62676 #define A_HMA_DEBUG_PCIE_INTF 0xa002
62678 #define S_T6_H_REQVLD 28
62679 #define V_T6_H_REQVLD(x) ((x) << S_T6_H_REQVLD)
62680 #define F_T6_H_REQVLD V_T6_H_REQVLD(1U)
62682 #define S_H_REQFULL 27
62683 #define V_H_REQFULL(x) ((x) << S_H_REQFULL)
62684 #define F_H_REQFULL V_H_REQFULL(1U)
62686 #define S_H_REQSOP 26
62687 #define V_H_REQSOP(x) ((x) << S_H_REQSOP)
62688 #define F_H_REQSOP V_H_REQSOP(1U)
62690 #define S_H_REQEOP 25
62691 #define V_H_REQEOP(x) ((x) << S_H_REQEOP)
62692 #define F_H_REQEOP V_H_REQEOP(1U)
62694 #define S_T6_H_RSPVLD 24
62695 #define V_T6_H_RSPVLD(x) ((x) << S_T6_H_RSPVLD)
62696 #define F_T6_H_RSPVLD V_T6_H_RSPVLD(1U)
62698 #define S_H_RSPFULL 23
62699 #define V_H_RSPFULL(x) ((x) << S_H_RSPFULL)
62700 #define F_H_RSPFULL V_H_RSPFULL(1U)
62702 #define S_H_RSPSOP 22
62703 #define V_H_RSPSOP(x) ((x) << S_H_RSPSOP)
62704 #define F_H_RSPSOP V_H_RSPSOP(1U)
62706 #define S_H_RSPEOP 21
62707 #define V_H_RSPEOP(x) ((x) << S_H_RSPEOP)
62708 #define F_H_RSPEOP V_H_RSPEOP(1U)
62710 #define S_H_RSPERR 20
62711 #define V_H_RSPERR(x) ((x) << S_H_RSPERR)
62712 #define F_H_RSPERR V_H_RSPERR(1U)
62714 #define S_PCIE_CMD_AVAIL 19
62715 #define V_PCIE_CMD_AVAIL(x) ((x) << S_PCIE_CMD_AVAIL)
62716 #define F_PCIE_CMD_AVAIL V_PCIE_CMD_AVAIL(1U)
62718 #define S_PCIE_CMD_RDY 18
62719 #define V_PCIE_CMD_RDY(x) ((x) << S_PCIE_CMD_RDY)
62720 #define F_PCIE_CMD_RDY V_PCIE_CMD_RDY(1U)
62722 #define S_PCIE_WNR 17
62723 #define V_PCIE_WNR(x) ((x) << S_PCIE_WNR)
62724 #define F_PCIE_WNR V_PCIE_WNR(1U)
62726 #define S_PCIE_LEN 9
62727 #define M_PCIE_LEN 0xffU
62728 #define V_PCIE_LEN(x) ((x) << S_PCIE_LEN)
62729 #define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN)
62731 #define S_PCIE_TRWDAT_RDY 8
62732 #define V_PCIE_TRWDAT_RDY(x) ((x) << S_PCIE_TRWDAT_RDY)
62733 #define F_PCIE_TRWDAT_RDY V_PCIE_TRWDAT_RDY(1U)
62735 #define S_PCIE_TRWDAT_AVAIL 7
62736 #define V_PCIE_TRWDAT_AVAIL(x) ((x) << S_PCIE_TRWDAT_AVAIL)
62737 #define F_PCIE_TRWDAT_AVAIL V_PCIE_TRWDAT_AVAIL(1U)
62739 #define S_PCIE_TRWSOP 6
62740 #define V_PCIE_TRWSOP(x) ((x) << S_PCIE_TRWSOP)
62741 #define F_PCIE_TRWSOP V_PCIE_TRWSOP(1U)
62743 #define S_PCIE_TRWEOP 5
62744 #define V_PCIE_TRWEOP(x) ((x) << S_PCIE_TRWEOP)
62745 #define F_PCIE_TRWEOP V_PCIE_TRWEOP(1U)
62747 #define S_PCIE_TRRDAT_RDY 4
62748 #define V_PCIE_TRRDAT_RDY(x) ((x) << S_PCIE_TRRDAT_RDY)
62749 #define F_PCIE_TRRDAT_RDY V_PCIE_TRRDAT_RDY(1U)
62751 #define S_PCIE_TRRDAT_AVAIL 3
62752 #define V_PCIE_TRRDAT_AVAIL(x) ((x) << S_PCIE_TRRDAT_AVAIL)
62753 #define F_PCIE_TRRDAT_AVAIL V_PCIE_TRRDAT_AVAIL(1U)
62755 #define S_PCIE_TRRSOP 2
62756 #define V_PCIE_TRRSOP(x) ((x) << S_PCIE_TRRSOP)
62757 #define F_PCIE_TRRSOP V_PCIE_TRRSOP(1U)
62759 #define S_PCIE_TRREOP 1
62760 #define V_PCIE_TRREOP(x) ((x) << S_PCIE_TRREOP)
62761 #define F_PCIE_TRREOP V_PCIE_TRREOP(1U)
62763 #define S_PCIE_TRRERR 0
62764 #define V_PCIE_TRRERR(x) ((x) << S_PCIE_TRRERR)
62765 #define F_PCIE_TRRERR V_PCIE_TRRERR(1U)
62767 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
62768 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
62769 #define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
62771 #define S_REQDATA2 24
62772 #define M_REQDATA2 0xffU
62773 #define V_REQDATA2(x) ((x) << S_REQDATA2)
62774 #define G_REQDATA2(x) (((x) >> S_REQDATA2) & M_REQDATA2)
62776 #define S_REQDATA1 21
62777 #define M_REQDATA1 0x7U
62778 #define V_REQDATA1(x) ((x) << S_REQDATA1)
62779 #define G_REQDATA1(x) (((x) >> S_REQDATA1) & M_REQDATA1)
62781 #define S_REQDATA0 0
62782 #define M_REQDATA0 0x1fffffU
62783 #define V_REQDATA0(x) ((x) << S_REQDATA0)
62784 #define G_REQDATA0(x) (((x) >> S_REQDATA0) & M_REQDATA0)
62786 #define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
62788 #define S_RSPDATA3 24
62789 #define M_RSPDATA3 0xffU
62790 #define V_RSPDATA3(x) ((x) << S_RSPDATA3)
62791 #define G_RSPDATA3(x) (((x) >> S_RSPDATA3) & M_RSPDATA3)
62793 #define S_RSPDATA2 16
62794 #define M_RSPDATA2 0xffU
62795 #define V_RSPDATA2(x) ((x) << S_RSPDATA2)
62796 #define G_RSPDATA2(x) (((x) >> S_RSPDATA2) & M_RSPDATA2)
62798 #define S_RSPDATA1 8
62799 #define M_RSPDATA1 0xffU
62800 #define V_RSPDATA1(x) ((x) << S_RSPDATA1)
62801 #define G_RSPDATA1(x) (((x) >> S_RSPDATA1) & M_RSPDATA1)
62803 #define S_RSPDATA0 0
62804 #define M_RSPDATA0 0xffU
62805 #define V_RSPDATA0(x) ((x) << S_RSPDATA0)
62806 #define G_RSPDATA0(x) (((x) >> S_RSPDATA0) & M_RSPDATA0)
62808 #define A_HMA_DEBUG_MA_SLV_CTL 0xa007
62810 #define S_MA_CMD_AVAIL 19
62811 #define V_MA_CMD_AVAIL(x) ((x) << S_MA_CMD_AVAIL)
62812 #define F_MA_CMD_AVAIL V_MA_CMD_AVAIL(1U)
62814 #define S_MA_CLNT 15
62815 #define M_MA_CLNT 0xfU
62816 #define V_MA_CLNT(x) ((x) << S_MA_CLNT)
62817 #define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT)
62819 #define S_MA_WNR 14
62820 #define V_MA_WNR(x) ((x) << S_MA_WNR)
62821 #define F_MA_WNR V_MA_WNR(1U)
62824 #define M_MA_LEN 0xffU
62825 #define V_MA_LEN(x) ((x) << S_MA_LEN)
62826 #define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN)
62828 #define S_MA_MST_RD 5
62829 #define V_MA_MST_RD(x) ((x) << S_MA_MST_RD)
62830 #define F_MA_MST_RD V_MA_MST_RD(1U)
62832 #define S_MA_MST_VLD 4
62833 #define V_MA_MST_VLD(x) ((x) << S_MA_MST_VLD)
62834 #define F_MA_MST_VLD V_MA_MST_VLD(1U)
62836 #define S_MA_MST_ERR 3
62837 #define V_MA_MST_ERR(x) ((x) << S_MA_MST_ERR)
62838 #define F_MA_MST_ERR V_MA_MST_ERR(1U)
62840 #define S_MAS_TLB_REQ 2
62841 #define V_MAS_TLB_REQ(x) ((x) << S_MAS_TLB_REQ)
62842 #define F_MAS_TLB_REQ V_MAS_TLB_REQ(1U)
62844 #define S_MAS_TLB_ACK 1
62845 #define V_MAS_TLB_ACK(x) ((x) << S_MAS_TLB_ACK)
62846 #define F_MAS_TLB_ACK V_MAS_TLB_ACK(1U)
62848 #define S_MAS_TLB_ERR 0
62849 #define V_MAS_TLB_ERR(x) ((x) << S_MAS_TLB_ERR)
62850 #define F_MAS_TLB_ERR V_MAS_TLB_ERR(1U)
62852 #define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
62853 #define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
62854 #define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
62855 #define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
62856 #define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
62858 #define S_LKP_REQ_VLD 4
62859 #define V_LKP_REQ_VLD(x) ((x) << S_LKP_REQ_VLD)
62860 #define F_LKP_REQ_VLD V_LKP_REQ_VLD(1U)
62862 #define S_LKP_DESC_SEL 1
62863 #define M_LKP_DESC_SEL 0x7U
62864 #define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL)
62865 #define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL)
62867 #define S_LKP_RSP_VLD 0
62868 #define V_LKP_RSP_VLD(x) ((x) << S_LKP_RSP_VLD)
62869 #define F_LKP_RSP_VLD V_LKP_RSP_VLD(1U)
62871 #define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
62872 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
62873 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
62874 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
62875 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
62876 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
62877 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
62878 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
62879 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
62880 #define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
62881 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
62882 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
62883 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
62884 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
62885 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
62886 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
62887 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
62888 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
62889 #define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
62891 #define S_WR_EOP_CNT 16
62892 #define M_WR_EOP_CNT 0xffU
62893 #define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT)
62894 #define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT)
62896 #define S_RD_SOP_CNT 8
62897 #define M_RD_SOP_CNT 0xffU
62898 #define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT)
62899 #define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT)
62901 #define S_RD_EOP_CNT 0
62902 #define M_RD_EOP_CNT 0xffU
62903 #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
62904 #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)