2 * Copyright (c) 2017 Chelsio Communications, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/types.h>
34 #include <sys/malloc.h>
35 #include <sys/mutex.h>
36 #include <sys/module.h>
37 #include <sys/sglist.h>
39 #include <opencrypto/cryptodev.h>
40 #include <opencrypto/xform.h>
42 #include "cryptodev_if.h"
44 #include "common/common.h"
45 #include "crypto/t4_crypto.h"
48 * Requests consist of:
50 * +-------------------------------+
51 * | struct fw_crypto_lookaside_wr |
52 * +-------------------------------+
53 * | struct ulp_txpkt |
54 * +-------------------------------+
55 * | struct ulptx_idata |
56 * +-------------------------------+
57 * | struct cpl_tx_sec_pdu |
58 * +-------------------------------+
59 * | struct cpl_tls_tx_scmd_fmt |
60 * +-------------------------------+
61 * | key context header |
62 * +-------------------------------+
63 * | AES key | ----- For requests with AES
64 * +-------------------------------+ -
65 * | IPAD (16-byte aligned) | \
66 * +-------------------------------+ +---- For requests with HMAC
67 * | OPAD (16-byte aligned) | /
68 * +-------------------------------+ -
69 * | GMAC H | ----- For AES-GCM
70 * +-------------------------------+ -
71 * | struct cpl_rx_phys_dsgl | \
72 * +-------------------------------+ +---- Destination buffer for
73 * | PHYS_DSGL entries | / non-hash-only requests
74 * +-------------------------------+ -
75 * | 16 dummy bytes | ----- Only for hash-only requests
76 * +-------------------------------+
77 * | IV | ----- If immediate IV
78 * +-------------------------------+
79 * | Payload | ----- If immediate Payload
80 * +-------------------------------+ -
81 * | struct ulptx_sgl | \
82 * +-------------------------------+ +---- If payload via SGL
84 * +-------------------------------+ -
86 * Note that the key context must be padded to ensure 16-byte alignment.
87 * For HMAC requests, the key consists of the partial hash of the IPAD
88 * followed by the partial hash of the OPAD.
92 * +-------------------------------+
93 * | struct cpl_fw6_pld |
94 * +-------------------------------+
95 * | hash digest | ----- For HMAC request with
96 * +-------------------------------+ 'hash_size' set in work request
98 * A 32-bit big-endian error status word is supplied in the last 4
99 * bytes of data[0] in the CPL_FW6_PLD message. bit 0 indicates a
100 * "MAC" error and bit 1 indicates a "PAD" error.
102 * The 64-bit 'cookie' field from the fw_crypto_lookaside_wr message
103 * in the request is returned in data[1] of the CPL_FW6_PLD message.
105 * For block cipher replies, the updated IV is supplied in data[2] and
106 * data[3] of the CPL_FW6_PLD message.
108 * For hash replies where the work request set 'hash_size' to request
109 * a copy of the hash in the reply, the hash digest is supplied
110 * immediately following the CPL_FW6_PLD message.
114 * The documentation for CPL_RX_PHYS_DSGL claims a maximum of 32
117 #define MAX_RX_PHYS_DSGL_SGE 32
118 #define DSGL_SGE_MAXLEN 65535
121 * The adapter only supports requests with a total input or output
122 * length of 64k-1 or smaller. Longer requests either result in hung
123 * requests or incorrect results.
125 #define MAX_REQUEST_SIZE 65535
127 static MALLOC_DEFINE(M_CCR, "ccr", "Chelsio T6 crypto");
129 struct ccr_session_hmac {
130 struct auth_hash *auth_hash;
132 unsigned int partial_digest_len;
133 unsigned int auth_mode;
134 unsigned int mk_size;
135 char ipad[CHCR_HASH_MAX_BLOCK_SIZE_128];
136 char opad[CHCR_HASH_MAX_BLOCK_SIZE_128];
139 struct ccr_session_gmac {
141 char ghash_h[GMAC_BLOCK_LEN];
144 struct ccr_session_blkcipher {
145 unsigned int cipher_mode;
146 unsigned int key_len;
149 char enckey[CHCR_AES_MAX_KEY_LEN];
150 char deckey[CHCR_AES_MAX_KEY_LEN];
156 enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode;
158 struct ccr_session_hmac hmac;
159 struct ccr_session_gmac gmac;
161 struct ccr_session_blkcipher blkcipher;
165 struct adapter *adapter;
169 struct ccr_session *sessions;
177 * Pre-allocate S/G lists used when preparing a work request.
178 * 'sg_crp' contains an sglist describing the entire buffer
179 * for a 'struct cryptop'. 'sg_ulptx' is used to describe
180 * the data the engine should DMA as input via ULPTX_SGL.
181 * 'sg_dsgl' is used to describe the destination that cipher
182 * text and a tag should be written to.
184 struct sglist *sg_crp;
185 struct sglist *sg_ulptx;
186 struct sglist *sg_dsgl;
189 uint64_t stats_blkcipher_encrypt;
190 uint64_t stats_blkcipher_decrypt;
192 uint64_t stats_authenc_encrypt;
193 uint64_t stats_authenc_decrypt;
194 uint64_t stats_gcm_encrypt;
195 uint64_t stats_gcm_decrypt;
196 uint64_t stats_wr_nomem;
197 uint64_t stats_inflight;
198 uint64_t stats_mac_error;
199 uint64_t stats_pad_error;
200 uint64_t stats_bad_session;
201 uint64_t stats_sglist_error;
202 uint64_t stats_process_error;
206 * Crypto requests involve two kind of scatter/gather lists.
208 * Non-hash-only requests require a PHYS_DSGL that describes the
209 * location to store the results of the encryption or decryption
210 * operation. This SGL uses a different format (PHYS_DSGL) and should
211 * exclude the crd_skip bytes at the start of the data as well as
212 * any AAD or IV. For authenticated encryption requests it should
213 * cover include the destination of the hash or tag.
215 * The input payload may either be supplied inline as immediate data,
216 * or via a standard ULP_TX SGL. This SGL should include AAD,
217 * ciphertext, and the hash or tag for authenticated decryption
220 * These scatter/gather lists can describe different subsets of the
221 * buffer described by the crypto operation. ccr_populate_sglist()
222 * generates a scatter/gather list that covers the entire crypto
223 * operation buffer that is then used to construct the other
224 * scatter/gather lists.
227 ccr_populate_sglist(struct sglist *sg, struct cryptop *crp)
232 if (crp->crp_flags & CRYPTO_F_IMBUF)
233 error = sglist_append_mbuf(sg, (struct mbuf *)crp->crp_buf);
234 else if (crp->crp_flags & CRYPTO_F_IOV)
235 error = sglist_append_uio(sg, (struct uio *)crp->crp_buf);
237 error = sglist_append(sg, crp->crp_buf, crp->crp_ilen);
242 * Segments in 'sg' larger than 'maxsegsize' are counted as multiple
246 ccr_count_sgl(struct sglist *sg, int maxsegsize)
251 for (i = 0; i < sg->sg_nseg; i++)
252 nsegs += howmany(sg->sg_segs[i].ss_len, maxsegsize);
256 /* These functions deal with PHYS_DSGL for the reply buffer. */
258 ccr_phys_dsgl_len(int nsegs)
262 len = (nsegs / 8) * sizeof(struct phys_sge_pairs);
263 if ((nsegs % 8) != 0) {
264 len += sizeof(uint16_t) * 8;
265 len += roundup2(nsegs % 8, 2) * sizeof(uint64_t);
271 ccr_write_phys_dsgl(struct ccr_softc *sc, void *dst, int nsegs)
274 struct cpl_rx_phys_dsgl *cpl;
275 struct phys_sge_pairs *sgl;
282 cpl->op_to_tid = htobe32(V_CPL_RX_PHYS_DSGL_OPCODE(CPL_RX_PHYS_DSGL) |
283 V_CPL_RX_PHYS_DSGL_ISRDMA(0));
284 cpl->pcirlxorder_to_noofsgentr = htobe32(
285 V_CPL_RX_PHYS_DSGL_PCIRLXORDER(0) |
286 V_CPL_RX_PHYS_DSGL_PCINOSNOOP(0) |
287 V_CPL_RX_PHYS_DSGL_PCITPHNTENB(0) | V_CPL_RX_PHYS_DSGL_DCAID(0) |
288 V_CPL_RX_PHYS_DSGL_NOOFSGENTR(nsegs));
289 cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR;
290 cpl->rss_hdr_int.qid = htobe16(sc->rxq->iq.abs_id);
291 cpl->rss_hdr_int.hash_val = 0;
292 sgl = (struct phys_sge_pairs *)(cpl + 1);
294 for (i = 0; i < sg->sg_nseg; i++) {
295 seglen = sg->sg_segs[i].ss_len;
296 paddr = sg->sg_segs[i].ss_paddr;
298 sgl->addr[j] = htobe64(paddr);
299 if (seglen > DSGL_SGE_MAXLEN) {
300 sgl->len[j] = htobe16(DSGL_SGE_MAXLEN);
301 paddr += DSGL_SGE_MAXLEN;
302 seglen -= DSGL_SGE_MAXLEN;
304 sgl->len[j] = htobe16(seglen);
312 } while (seglen != 0);
314 MPASS(j + 8 * (sgl - (struct phys_sge_pairs *)(cpl + 1)) == nsegs);
317 /* These functions deal with the ULPTX_SGL for input payload. */
319 ccr_ulptx_sgl_len(int nsegs)
323 nsegs--; /* first segment is part of ulptx_sgl */
324 n = sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
325 return (roundup2(n, 16));
329 ccr_write_ulptx_sgl(struct ccr_softc *sc, void *dst, int nsegs)
331 struct ulptx_sgl *usgl;
333 struct sglist_seg *ss;
337 MPASS(nsegs == sg->sg_nseg);
338 ss = &sg->sg_segs[0];
340 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
341 V_ULPTX_NSGE(nsegs));
342 usgl->len0 = htobe32(ss->ss_len);
343 usgl->addr0 = htobe64(ss->ss_paddr);
345 for (i = 0; i < sg->sg_nseg - 1; i++) {
346 usgl->sge[i / 2].len[i & 1] = htobe32(ss->ss_len);
347 usgl->sge[i / 2].addr[i & 1] = htobe64(ss->ss_paddr);
354 ccr_use_imm_data(u_int transhdr_len, u_int input_len)
357 if (input_len > CRYPTO_MAX_IMM_TX_PKT_LEN)
359 if (roundup2(transhdr_len, 16) + roundup2(input_len, 16) >
366 ccr_populate_wreq(struct ccr_softc *sc, struct chcr_wr *crwr, u_int kctx_len,
367 u_int wr_len, uint32_t sid, u_int imm_len, u_int sgl_len, u_int hash_size,
368 u_int iv_loc, struct cryptop *crp)
372 cctx_size = sizeof(struct _key_ctx) + kctx_len;
373 crwr->wreq.op_to_cctx_size = htobe32(
374 V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(FW_CRYPTO_LOOKASIDE_WR) |
375 V_FW_CRYPTO_LOOKASIDE_WR_COMPL(0) |
376 V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(imm_len) |
377 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(1) |
378 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(cctx_size >> 4));
379 crwr->wreq.len16_pkd = htobe32(
380 V_FW_CRYPTO_LOOKASIDE_WR_LEN16(wr_len / 16));
381 crwr->wreq.session_id = htobe32(sid);
382 crwr->wreq.rx_chid_to_rx_q_id = htobe32(
383 V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(sc->tx_channel_id) |
384 V_FW_CRYPTO_LOOKASIDE_WR_LCB(0) |
385 V_FW_CRYPTO_LOOKASIDE_WR_PHASH(0) |
386 V_FW_CRYPTO_LOOKASIDE_WR_IV(iv_loc) |
387 V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(0) |
388 V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(0) |
389 V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(sc->rxq->iq.abs_id));
390 crwr->wreq.key_addr = 0;
391 crwr->wreq.pld_size_hash_size = htobe32(
392 V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(sgl_len) |
393 V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(hash_size));
394 crwr->wreq.cookie = htobe64((uintptr_t)crp);
396 crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
397 V_ULP_TXPKT_DATAMODIFY(0) |
398 V_ULP_TXPKT_CHANNELID(sc->tx_channel_id) | V_ULP_TXPKT_DEST(0) |
399 V_ULP_TXPKT_FID(0) | V_ULP_TXPKT_RO(1));
400 crwr->ulptx.len = htobe32(
401 ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16));
403 crwr->sc_imm.cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
404 V_ULP_TX_SC_MORE(imm_len != 0 ? 0 : 1));
405 crwr->sc_imm.len = htobe32(wr_len - offsetof(struct chcr_wr, sec_cpl) -
410 ccr_hmac(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s,
413 struct chcr_wr *crwr;
415 struct auth_hash *axf;
416 struct cryptodesc *crd;
418 u_int hash_size_in_response, kctx_flits, kctx_len, transhdr_len, wr_len;
419 u_int imm_len, iopad_size;
420 int error, sgl_nsegs, sgl_len;
424 /* Reject requests with too large of an input buffer. */
425 if (crd->crd_len > MAX_REQUEST_SIZE)
428 axf = s->hmac.auth_hash;
430 /* PADs must be 128-bit aligned. */
431 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
434 * The 'key' part of the context includes the aligned IPAD and
437 kctx_len = iopad_size * 2;
438 hash_size_in_response = axf->hashsize;
439 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len);
441 if (ccr_use_imm_data(transhdr_len, crd->crd_len)) {
442 imm_len = crd->crd_len;
447 sglist_reset(sc->sg_ulptx);
448 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
449 crd->crd_skip, crd->crd_len);
452 sgl_nsegs = sc->sg_ulptx->sg_nseg;
453 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
456 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len;
457 wr = alloc_wrqe(wr_len, sc->txq);
459 sc->stats_wr_nomem++;
463 memset(crwr, 0, wr_len);
465 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len,
466 hash_size_in_response, IV_NOP, crp);
468 /* XXX: Hardcodes SGE loopback channel of 0. */
469 crwr->sec_cpl.op_ivinsrtofst = htobe32(
470 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
471 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) |
472 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
473 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
474 V_CPL_TX_SEC_PDU_IVINSRTOFST(0));
476 crwr->sec_cpl.pldlen = htobe32(crd->crd_len);
478 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
479 V_CPL_TX_SEC_PDU_AUTHSTART(1) | V_CPL_TX_SEC_PDU_AUTHSTOP(0));
481 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
482 crwr->sec_cpl.seqno_numivs = htobe32(
483 V_SCMD_SEQ_NO_CTRL(0) |
484 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) |
485 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_NOP) |
486 V_SCMD_AUTH_MODE(s->hmac.auth_mode) |
487 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NO_TRUNC));
488 crwr->sec_cpl.ivgen_hdrlen = htobe32(
489 V_SCMD_LAST_FRAG(0) | V_SCMD_MORE_FRAGS(0) | V_SCMD_MAC_ONLY(1));
491 memcpy(crwr->key_ctx.key, s->hmac.ipad, s->hmac.partial_digest_len);
492 memcpy(crwr->key_ctx.key + iopad_size, s->hmac.opad,
493 s->hmac.partial_digest_len);
495 /* XXX: F_KEY_CONTEXT_SALT_PRESENT set, but 'salt' not set. */
496 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16;
497 crwr->key_ctx.ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) |
498 V_KEY_CONTEXT_OPAD_PRESENT(1) | V_KEY_CONTEXT_SALT_PRESENT(1) |
499 V_KEY_CONTEXT_CK_SIZE(CHCR_KEYCTX_NO_KEY) |
500 V_KEY_CONTEXT_MK_SIZE(s->hmac.mk_size) | V_KEY_CONTEXT_VALID(1));
502 dst = (char *)(crwr + 1) + kctx_len + DUMMY_BYTES;
504 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip,
507 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs);
509 /* XXX: TODO backpressure */
510 t4_wrq_tx(sc->adapter, wr);
516 ccr_hmac_done(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp,
517 const struct cpl_fw6_pld *cpl, int error)
519 struct cryptodesc *crd;
523 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
524 s->hmac.hash_len, (c_caddr_t)(cpl + 1));
531 ccr_blkcipher(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s,
534 char iv[CHCR_MAX_CRYPTO_IV_LEN];
535 struct chcr_wr *crwr;
537 struct cryptodesc *crd;
539 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len;
541 int dsgl_nsegs, dsgl_len;
542 int sgl_nsegs, sgl_len;
547 if (s->blkcipher.key_len == 0)
549 if (crd->crd_alg == CRYPTO_AES_CBC &&
550 (crd->crd_len % AES_BLOCK_LEN) != 0)
553 /* Reject requests with too large of an input buffer. */
554 if (crd->crd_len > MAX_REQUEST_SIZE)
558 if (crd->crd_flags & CRD_F_ENCRYPT) {
559 op_type = CHCR_ENCRYPT_OP;
560 if (crd->crd_flags & CRD_F_IV_EXPLICIT)
561 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len);
563 arc4rand(iv, s->blkcipher.iv_len, 0);
564 iv_loc = IV_IMMEDIATE;
565 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0)
566 crypto_copyback(crp->crp_flags, crp->crp_buf,
567 crd->crd_inject, s->blkcipher.iv_len, iv);
569 op_type = CHCR_DECRYPT_OP;
570 if (crd->crd_flags & CRD_F_IV_EXPLICIT) {
571 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len);
572 iv_loc = IV_IMMEDIATE;
577 sglist_reset(sc->sg_dsgl);
578 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crd->crd_skip,
582 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN);
583 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
585 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
587 /* The 'key' must be 128-bit aligned. */
588 kctx_len = roundup2(s->blkcipher.key_len, 16);
589 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
591 if (ccr_use_imm_data(transhdr_len, crd->crd_len +
592 s->blkcipher.iv_len)) {
593 imm_len = crd->crd_len;
594 if (iv_loc == IV_DSGL) {
595 crypto_copydata(crp->crp_flags, crp->crp_buf,
596 crd->crd_inject, s->blkcipher.iv_len, iv);
597 iv_loc = IV_IMMEDIATE;
603 sglist_reset(sc->sg_ulptx);
604 if (iv_loc == IV_DSGL) {
605 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
606 crd->crd_inject, s->blkcipher.iv_len);
610 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
611 crd->crd_skip, crd->crd_len);
614 sgl_nsegs = sc->sg_ulptx->sg_nseg;
615 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
618 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len;
619 if (iv_loc == IV_IMMEDIATE)
620 wr_len += s->blkcipher.iv_len;
621 wr = alloc_wrqe(wr_len, sc->txq);
623 sc->stats_wr_nomem++;
627 memset(crwr, 0, wr_len);
629 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 0,
632 /* XXX: Hardcodes SGE loopback channel of 0. */
633 crwr->sec_cpl.op_ivinsrtofst = htobe32(
634 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
635 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) |
636 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
637 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
638 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
640 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + crd->crd_len);
642 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
643 V_CPL_TX_SEC_PDU_CIPHERSTART(s->blkcipher.iv_len + 1) |
644 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0));
645 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
646 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0));
648 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
649 crwr->sec_cpl.seqno_numivs = htobe32(
650 V_SCMD_SEQ_NO_CTRL(0) |
651 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) |
652 V_SCMD_ENC_DEC_CTRL(op_type) |
653 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) |
654 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_NOP) |
655 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NOP) |
656 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) |
658 crwr->sec_cpl.ivgen_hdrlen = htobe32(
659 V_SCMD_IV_GEN_CTRL(0) |
660 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
661 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len));
663 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
664 switch (crd->crd_alg) {
666 if (crd->crd_flags & CRD_F_ENCRYPT)
667 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
668 s->blkcipher.key_len);
670 memcpy(crwr->key_ctx.key, s->blkcipher.deckey,
671 s->blkcipher.key_len);
674 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
675 s->blkcipher.key_len);
678 key_half = s->blkcipher.key_len / 2;
679 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half,
681 if (crd->crd_flags & CRD_F_ENCRYPT)
682 memcpy(crwr->key_ctx.key + key_half,
683 s->blkcipher.enckey, key_half);
685 memcpy(crwr->key_ctx.key + key_half,
686 s->blkcipher.deckey, key_half);
690 dst = (char *)(crwr + 1) + kctx_len;
691 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs);
692 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
693 if (iv_loc == IV_IMMEDIATE) {
694 memcpy(dst, iv, s->blkcipher.iv_len);
695 dst += s->blkcipher.iv_len;
698 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip,
701 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs);
703 /* XXX: TODO backpressure */
704 t4_wrq_tx(sc->adapter, wr);
710 ccr_blkcipher_done(struct ccr_softc *sc, struct ccr_session *s,
711 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
715 * The updated IV to permit chained requests is at
716 * cpl->data[2], but OCF doesn't permit chained requests.
722 * 'hashsize' is the length of a full digest. 'authsize' is the
723 * requested digest length for this operation which may be less
727 ccr_hmac_ctrl(unsigned int hashsize, unsigned int authsize)
731 return (CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366);
733 return (CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT);
734 if (authsize == hashsize / 2)
735 return (CHCR_SCMD_HMAC_CTRL_DIV2);
736 return (CHCR_SCMD_HMAC_CTRL_NO_TRUNC);
740 ccr_authenc(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s,
741 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde)
743 char iv[CHCR_MAX_CRYPTO_IV_LEN];
744 struct chcr_wr *crwr;
746 struct auth_hash *axf;
748 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len;
749 u_int hash_size_in_response, imm_len, iopad_size;
750 u_int aad_start, aad_len, aad_stop;
751 u_int auth_start, auth_stop, auth_insert;
752 u_int cipher_start, cipher_stop;
753 u_int hmac_ctrl, input_len;
754 int dsgl_nsegs, dsgl_len;
755 int sgl_nsegs, sgl_len;
758 if (s->blkcipher.key_len == 0)
760 if (crde->crd_alg == CRYPTO_AES_CBC &&
761 (crde->crd_len % AES_BLOCK_LEN) != 0)
765 * AAD is only permitted before the cipher/plain text, not
768 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip)
771 axf = s->hmac.auth_hash;
772 hash_size_in_response = s->hmac.hash_len;
775 * The IV is always stored at the start of the buffer even
776 * though it may be duplicated in the payload. The crypto
777 * engine doesn't work properly if the IV offset points inside
778 * of the AAD region, so a second copy is always required.
780 iv_loc = IV_IMMEDIATE;
781 if (crde->crd_flags & CRD_F_ENCRYPT) {
782 op_type = CHCR_ENCRYPT_OP;
783 if (crde->crd_flags & CRD_F_IV_EXPLICIT)
784 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len);
786 arc4rand(iv, s->blkcipher.iv_len, 0);
787 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0)
788 crypto_copyback(crp->crp_flags, crp->crp_buf,
789 crde->crd_inject, s->blkcipher.iv_len, iv);
791 op_type = CHCR_DECRYPT_OP;
792 if (crde->crd_flags & CRD_F_IV_EXPLICIT)
793 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len);
795 crypto_copydata(crp->crp_flags, crp->crp_buf,
796 crde->crd_inject, s->blkcipher.iv_len, iv);
800 * The output buffer consists of the cipher text followed by
801 * the hash when encrypting. For decryption it only contains
804 if (op_type == CHCR_ENCRYPT_OP) {
805 if (crde->crd_len + hash_size_in_response > MAX_REQUEST_SIZE)
808 if (crde->crd_len > MAX_REQUEST_SIZE)
811 sglist_reset(sc->sg_dsgl);
812 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip,
816 if (op_type == CHCR_ENCRYPT_OP) {
817 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp,
818 crda->crd_inject, hash_size_in_response);
822 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN);
823 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
825 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
827 /* PADs must be 128-bit aligned. */
828 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
831 * The 'key' part of the key context consists of the key followed
832 * by the IPAD and OPAD.
834 kctx_len = roundup2(s->blkcipher.key_len, 16) + iopad_size * 2;
835 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
838 * The input buffer consists of the IV, any AAD, and then the
839 * cipher/plain text. For decryption requests the hash is
840 * appended after the cipher text.
842 if (crda->crd_skip < crde->crd_skip) {
843 if (crda->crd_skip + crda->crd_len > crde->crd_skip)
844 aad_len = (crde->crd_skip - crda->crd_skip);
846 aad_len = crda->crd_len;
849 input_len = aad_len + crde->crd_len;
852 * The firmware hangs if sent a request which is a
853 * bit smaller than MAX_REQUEST_SIZE. In particular, the
854 * firmware appears to require 512 - 16 bytes of spare room
855 * along with the size of the hash even if the hash isn't
856 * included in the input buffer.
858 if (input_len + roundup2(axf->hashsize, 16) + (512 - 16) >
861 if (op_type == CHCR_DECRYPT_OP)
862 input_len += hash_size_in_response;
863 if (ccr_use_imm_data(transhdr_len, s->blkcipher.iv_len + input_len)) {
869 sglist_reset(sc->sg_ulptx);
871 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
872 crda->crd_skip, aad_len);
876 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
877 crde->crd_skip, crde->crd_len);
880 if (op_type == CHCR_DECRYPT_OP) {
881 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
882 crda->crd_inject, hash_size_in_response);
886 sgl_nsegs = sc->sg_ulptx->sg_nseg;
887 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
891 * Any auth-only data before the cipher region is marked as AAD.
892 * Auth-data that overlaps with the cipher region is placed in
896 aad_start = s->blkcipher.iv_len + 1;
897 aad_stop = aad_start + aad_len - 1;
902 cipher_start = s->blkcipher.iv_len + aad_len + 1;
903 if (op_type == CHCR_DECRYPT_OP)
904 cipher_stop = hash_size_in_response;
907 if (aad_len == crda->crd_len) {
912 auth_start = cipher_start;
914 auth_start = s->blkcipher.iv_len + crda->crd_skip -
916 auth_stop = (crde->crd_skip + crde->crd_len) -
917 (crda->crd_skip + crda->crd_len) + cipher_stop;
919 if (op_type == CHCR_DECRYPT_OP)
920 auth_insert = hash_size_in_response;
924 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len;
925 if (iv_loc == IV_IMMEDIATE)
926 wr_len += s->blkcipher.iv_len;
927 wr = alloc_wrqe(wr_len, sc->txq);
929 sc->stats_wr_nomem++;
933 memset(crwr, 0, wr_len);
935 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len,
936 op_type == CHCR_DECRYPT_OP ? hash_size_in_response : 0, iv_loc,
939 /* XXX: Hardcodes SGE loopback channel of 0. */
940 crwr->sec_cpl.op_ivinsrtofst = htobe32(
941 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
942 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) |
943 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
944 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
945 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
947 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + input_len);
949 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
950 V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
951 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
952 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
953 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4));
954 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
955 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) |
956 V_CPL_TX_SEC_PDU_AUTHSTART(auth_start) |
957 V_CPL_TX_SEC_PDU_AUTHSTOP(auth_stop) |
958 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
960 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
961 hmac_ctrl = ccr_hmac_ctrl(axf->hashsize, hash_size_in_response);
962 crwr->sec_cpl.seqno_numivs = htobe32(
963 V_SCMD_SEQ_NO_CTRL(0) |
964 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) |
965 V_SCMD_ENC_DEC_CTRL(op_type) |
966 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) |
967 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) |
968 V_SCMD_AUTH_MODE(s->hmac.auth_mode) |
969 V_SCMD_HMAC_CTRL(hmac_ctrl) |
970 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) |
972 crwr->sec_cpl.ivgen_hdrlen = htobe32(
973 V_SCMD_IV_GEN_CTRL(0) |
974 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
975 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len));
977 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
978 switch (crde->crd_alg) {
980 if (crde->crd_flags & CRD_F_ENCRYPT)
981 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
982 s->blkcipher.key_len);
984 memcpy(crwr->key_ctx.key, s->blkcipher.deckey,
985 s->blkcipher.key_len);
988 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
989 s->blkcipher.key_len);
992 key_half = s->blkcipher.key_len / 2;
993 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half,
995 if (crde->crd_flags & CRD_F_ENCRYPT)
996 memcpy(crwr->key_ctx.key + key_half,
997 s->blkcipher.enckey, key_half);
999 memcpy(crwr->key_ctx.key + key_half,
1000 s->blkcipher.deckey, key_half);
1004 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16);
1005 memcpy(dst, s->hmac.ipad, s->hmac.partial_digest_len);
1006 memcpy(dst + iopad_size, s->hmac.opad, s->hmac.partial_digest_len);
1008 dst = (char *)(crwr + 1) + kctx_len;
1009 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs);
1010 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
1011 if (iv_loc == IV_IMMEDIATE) {
1012 memcpy(dst, iv, s->blkcipher.iv_len);
1013 dst += s->blkcipher.iv_len;
1017 crypto_copydata(crp->crp_flags, crp->crp_buf,
1018 crda->crd_skip, aad_len, dst);
1021 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip,
1022 crde->crd_len, dst);
1023 dst += crde->crd_len;
1024 if (op_type == CHCR_DECRYPT_OP)
1025 crypto_copydata(crp->crp_flags, crp->crp_buf,
1026 crda->crd_inject, hash_size_in_response, dst);
1028 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs);
1030 /* XXX: TODO backpressure */
1031 t4_wrq_tx(sc->adapter, wr);
1037 ccr_authenc_done(struct ccr_softc *sc, struct ccr_session *s,
1038 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
1040 struct cryptodesc *crd;
1043 * The updated IV to permit chained requests is at
1044 * cpl->data[2], but OCF doesn't permit chained requests.
1046 * For a decryption request, the hardware may do a verification
1047 * of the HMAC which will fail if the existing HMAC isn't in the
1048 * buffer. If that happens, clear the error and copy the HMAC
1049 * from the CPL reply into the buffer.
1051 * For encryption requests, crd should be the cipher request
1052 * which will have CRD_F_ENCRYPT set. For decryption
1053 * requests, crp_desc will be the HMAC request which should
1054 * not have this flag set.
1056 crd = crp->crp_desc;
1057 if (error == EBADMSG && !CHK_PAD_ERR_BIT(be64toh(cpl->data[0])) &&
1058 !(crd->crd_flags & CRD_F_ENCRYPT)) {
1059 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1060 s->hmac.hash_len, (c_caddr_t)(cpl + 1));
1067 ccr_gcm(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s,
1068 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde)
1070 char iv[CHCR_MAX_CRYPTO_IV_LEN];
1071 struct chcr_wr *crwr;
1074 u_int iv_len, iv_loc, kctx_len, op_type, transhdr_len, wr_len;
1075 u_int hash_size_in_response, imm_len;
1076 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert;
1077 u_int hmac_ctrl, input_len;
1078 int dsgl_nsegs, dsgl_len;
1079 int sgl_nsegs, sgl_len;
1082 if (s->blkcipher.key_len == 0)
1086 * AAD is only permitted before the cipher/plain text, not
1089 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip)
1092 hash_size_in_response = s->gmac.hash_len;
1095 * The IV is always stored at the start of the buffer even
1096 * though it may be duplicated in the payload. The crypto
1097 * engine doesn't work properly if the IV offset points inside
1098 * of the AAD region, so a second copy is always required.
1100 * The IV for GCM is further complicated in that IPSec
1101 * provides a full 16-byte IV (including the counter), whereas
1102 * the /dev/crypto interface sometimes provides a full 16-byte
1103 * IV (if no IV is provided in the ioctl) and sometimes a
1104 * 12-byte IV (if the IV was explicit). For now the driver
1105 * always assumes a 12-byte IV and initializes the low 4 byte
1108 iv_loc = IV_IMMEDIATE;
1109 if (crde->crd_flags & CRD_F_ENCRYPT) {
1110 op_type = CHCR_ENCRYPT_OP;
1111 if (crde->crd_flags & CRD_F_IV_EXPLICIT)
1112 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len);
1114 arc4rand(iv, s->blkcipher.iv_len, 0);
1115 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0)
1116 crypto_copyback(crp->crp_flags, crp->crp_buf,
1117 crde->crd_inject, s->blkcipher.iv_len, iv);
1119 op_type = CHCR_DECRYPT_OP;
1120 if (crde->crd_flags & CRD_F_IV_EXPLICIT)
1121 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len);
1123 crypto_copydata(crp->crp_flags, crp->crp_buf,
1124 crde->crd_inject, s->blkcipher.iv_len, iv);
1128 * If the input IV is 12 bytes, append an explicit counter of
1131 if (s->blkcipher.iv_len == 12) {
1132 *(uint32_t *)&iv[12] = htobe32(1);
1133 iv_len = AES_BLOCK_LEN;
1135 iv_len = s->blkcipher.iv_len;
1138 * The output buffer consists of the cipher text followed by
1139 * the tag when encrypting. For decryption it only contains
1142 if (op_type == CHCR_ENCRYPT_OP) {
1143 if (crde->crd_len + hash_size_in_response > MAX_REQUEST_SIZE)
1146 if (crde->crd_len > MAX_REQUEST_SIZE)
1149 sglist_reset(sc->sg_dsgl);
1150 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip,
1154 if (op_type == CHCR_ENCRYPT_OP) {
1155 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp,
1156 crda->crd_inject, hash_size_in_response);
1160 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN);
1161 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
1163 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
1166 * The 'key' part of the key context consists of the key followed
1167 * by the Galois hash key.
1169 kctx_len = roundup2(s->blkcipher.key_len, 16) + GMAC_BLOCK_LEN;
1170 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
1173 * The input buffer consists of the IV, any AAD, and then the
1174 * cipher/plain text. For decryption requests the hash is
1175 * appended after the cipher text.
1177 input_len = crda->crd_len + crde->crd_len;
1178 if (op_type == CHCR_DECRYPT_OP)
1179 input_len += hash_size_in_response;
1180 if (input_len > MAX_REQUEST_SIZE)
1182 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) {
1183 imm_len = input_len;
1188 sglist_reset(sc->sg_ulptx);
1189 if (crda->crd_len != 0) {
1190 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
1191 crda->crd_skip, crda->crd_len);
1195 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
1196 crde->crd_skip, crde->crd_len);
1199 if (op_type == CHCR_DECRYPT_OP) {
1200 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp,
1201 crda->crd_inject, hash_size_in_response);
1205 sgl_nsegs = sc->sg_ulptx->sg_nseg;
1206 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
1209 if (crda->crd_len != 0) {
1210 aad_start = iv_len + 1;
1211 aad_stop = aad_start + crda->crd_len - 1;
1216 cipher_start = iv_len + crda->crd_len + 1;
1217 if (op_type == CHCR_DECRYPT_OP)
1218 cipher_stop = hash_size_in_response;
1221 if (op_type == CHCR_DECRYPT_OP)
1222 auth_insert = hash_size_in_response;
1226 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len;
1227 if (iv_loc == IV_IMMEDIATE)
1229 wr = alloc_wrqe(wr_len, sc->txq);
1231 sc->stats_wr_nomem++;
1235 memset(crwr, 0, wr_len);
1237 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len,
1240 /* XXX: Hardcodes SGE loopback channel of 0. */
1241 crwr->sec_cpl.op_ivinsrtofst = htobe32(
1242 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
1243 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) |
1244 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
1245 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
1246 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
1248 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len);
1251 * NB: cipherstop is explicitly set to 0. On encrypt it
1252 * should normally be set to 0 anyway (as the encrypt crd ends
1253 * at the end of the input). However, for decrypt the cipher
1254 * ends before the tag in the AUTHENC case (and authstop is
1255 * set to stop before the tag), but for GCM the cipher still
1256 * runs to the end of the buffer. Not sure if this is
1257 * intentional or a firmware quirk, but it is required for
1258 * working tag validation with GCM decryption.
1260 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
1261 V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
1262 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
1263 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
1264 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0));
1265 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
1266 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) |
1267 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) |
1268 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) |
1269 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
1271 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
1272 hmac_ctrl = ccr_hmac_ctrl(AES_GMAC_HASH_LEN, hash_size_in_response);
1273 crwr->sec_cpl.seqno_numivs = htobe32(
1274 V_SCMD_SEQ_NO_CTRL(0) |
1275 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) |
1276 V_SCMD_ENC_DEC_CTRL(op_type) |
1277 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) |
1278 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_AES_GCM) |
1279 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_GHASH) |
1280 V_SCMD_HMAC_CTRL(hmac_ctrl) |
1281 V_SCMD_IV_SIZE(iv_len / 2) |
1283 crwr->sec_cpl.ivgen_hdrlen = htobe32(
1284 V_SCMD_IV_GEN_CTRL(0) |
1285 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
1286 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len));
1288 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
1289 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len);
1290 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16);
1291 memcpy(dst, s->gmac.ghash_h, GMAC_BLOCK_LEN);
1293 dst = (char *)(crwr + 1) + kctx_len;
1294 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs);
1295 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
1296 if (iv_loc == IV_IMMEDIATE) {
1297 memcpy(dst, iv, iv_len);
1301 if (crda->crd_len != 0) {
1302 crypto_copydata(crp->crp_flags, crp->crp_buf,
1303 crda->crd_skip, crda->crd_len, dst);
1304 dst += crda->crd_len;
1306 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip,
1307 crde->crd_len, dst);
1308 dst += crde->crd_len;
1309 if (op_type == CHCR_DECRYPT_OP)
1310 crypto_copydata(crp->crp_flags, crp->crp_buf,
1311 crda->crd_inject, hash_size_in_response, dst);
1313 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs);
1315 /* XXX: TODO backpressure */
1316 t4_wrq_tx(sc->adapter, wr);
1322 ccr_gcm_done(struct ccr_softc *sc, struct ccr_session *s,
1323 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
1327 * The updated IV to permit chained requests is at
1328 * cpl->data[2], but OCF doesn't permit chained requests.
1330 * Note that the hardware should always verify the GMAC hash.
1336 ccr_identify(driver_t *driver, device_t parent)
1340 sc = device_get_softc(parent);
1341 if (sc->cryptocaps & FW_CAPS_CONFIG_CRYPTO_LOOKASIDE &&
1342 device_find_child(parent, "ccr", -1) == NULL)
1343 device_add_child(parent, "ccr", -1);
1347 ccr_probe(device_t dev)
1350 device_set_desc(dev, "Chelsio Crypto Accelerator");
1351 return (BUS_PROBE_DEFAULT);
1355 ccr_sysctls(struct ccr_softc *sc)
1357 struct sysctl_ctx_list *ctx;
1358 struct sysctl_oid *oid;
1359 struct sysctl_oid_list *children;
1361 ctx = device_get_sysctl_ctx(sc->dev);
1366 oid = device_get_sysctl_tree(sc->dev);
1367 children = SYSCTL_CHILDREN(oid);
1372 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
1373 NULL, "statistics");
1374 children = SYSCTL_CHILDREN(oid);
1376 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "hmac", CTLFLAG_RD,
1377 &sc->stats_hmac, 0, "HMAC requests submitted");
1378 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_encrypt", CTLFLAG_RD,
1379 &sc->stats_blkcipher_encrypt, 0,
1380 "Cipher encryption requests submitted");
1381 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_decrypt", CTLFLAG_RD,
1382 &sc->stats_blkcipher_decrypt, 0,
1383 "Cipher decryption requests submitted");
1384 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_encrypt", CTLFLAG_RD,
1385 &sc->stats_authenc_encrypt, 0,
1386 "Combined AES+HMAC encryption requests submitted");
1387 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_decrypt", CTLFLAG_RD,
1388 &sc->stats_authenc_decrypt, 0,
1389 "Combined AES+HMAC decryption requests submitted");
1390 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_encrypt", CTLFLAG_RD,
1391 &sc->stats_gcm_encrypt, 0, "AES-GCM encryption requests submitted");
1392 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_decrypt", CTLFLAG_RD,
1393 &sc->stats_gcm_decrypt, 0, "AES-GCM decryption requests submitted");
1394 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "wr_nomem", CTLFLAG_RD,
1395 &sc->stats_wr_nomem, 0, "Work request memory allocation failures");
1396 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "inflight", CTLFLAG_RD,
1397 &sc->stats_inflight, 0, "Requests currently pending");
1398 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "mac_error", CTLFLAG_RD,
1399 &sc->stats_mac_error, 0, "MAC errors");
1400 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "pad_error", CTLFLAG_RD,
1401 &sc->stats_pad_error, 0, "Padding errors");
1402 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "bad_session", CTLFLAG_RD,
1403 &sc->stats_pad_error, 0, "Requests with invalid session ID");
1404 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "sglist_error", CTLFLAG_RD,
1405 &sc->stats_pad_error, 0, "Requests for which DMA mapping failed");
1406 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "process_error", CTLFLAG_RD,
1407 &sc->stats_pad_error, 0, "Requests failed during queueing");
1411 ccr_attach(device_t dev)
1413 struct ccr_softc *sc;
1417 * TODO: Crypto requests will panic if the parent device isn't
1418 * initialized so that the queues are up and running. Need to
1419 * figure out how to handle that correctly, maybe just reject
1420 * requests if the adapter isn't fully initialized?
1422 sc = device_get_softc(dev);
1424 sc->adapter = device_get_softc(device_get_parent(dev));
1425 sc->txq = &sc->adapter->sge.ctrlq[0];
1426 sc->rxq = &sc->adapter->sge.rxq[0];
1427 cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
1429 device_printf(dev, "could not get crypto driver id\n");
1433 sc->adapter->ccr_softc = sc;
1436 sc->tx_channel_id = 0;
1438 mtx_init(&sc->lock, "ccr", NULL, MTX_DEF);
1439 sc->sg_crp = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
1440 sc->sg_ulptx = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
1441 sc->sg_dsgl = sglist_alloc(MAX_RX_PHYS_DSGL_SGE, M_WAITOK);
1444 crypto_register(cid, CRYPTO_SHA1_HMAC, 0, 0);
1445 crypto_register(cid, CRYPTO_SHA2_256_HMAC, 0, 0);
1446 crypto_register(cid, CRYPTO_SHA2_384_HMAC, 0, 0);
1447 crypto_register(cid, CRYPTO_SHA2_512_HMAC, 0, 0);
1448 crypto_register(cid, CRYPTO_AES_CBC, 0, 0);
1449 crypto_register(cid, CRYPTO_AES_ICM, 0, 0);
1450 crypto_register(cid, CRYPTO_AES_NIST_GCM_16, 0, 0);
1451 crypto_register(cid, CRYPTO_AES_128_NIST_GMAC, 0, 0);
1452 crypto_register(cid, CRYPTO_AES_192_NIST_GMAC, 0, 0);
1453 crypto_register(cid, CRYPTO_AES_256_NIST_GMAC, 0, 0);
1454 crypto_register(cid, CRYPTO_AES_XTS, 0, 0);
1459 ccr_detach(device_t dev)
1461 struct ccr_softc *sc;
1464 sc = device_get_softc(dev);
1466 mtx_lock(&sc->lock);
1467 for (i = 0; i < sc->nsessions; i++) {
1468 if (sc->sessions[i].active || sc->sessions[i].pending != 0) {
1469 mtx_unlock(&sc->lock);
1473 sc->detaching = true;
1474 mtx_unlock(&sc->lock);
1476 crypto_unregister_all(sc->cid);
1477 free(sc->sessions, M_CCR);
1478 mtx_destroy(&sc->lock);
1479 sglist_free(sc->sg_dsgl);
1480 sglist_free(sc->sg_ulptx);
1481 sglist_free(sc->sg_crp);
1482 sc->adapter->ccr_softc = NULL;
1487 ccr_copy_partial_hash(void *dst, int cri_alg, union authctx *auth_ctx)
1493 u32 = (uint32_t *)dst;
1494 u64 = (uint64_t *)dst;
1496 case CRYPTO_SHA1_HMAC:
1497 for (i = 0; i < SHA1_HASH_LEN / 4; i++)
1498 u32[i] = htobe32(auth_ctx->sha1ctx.h.b32[i]);
1500 case CRYPTO_SHA2_256_HMAC:
1501 for (i = 0; i < SHA2_256_HASH_LEN / 4; i++)
1502 u32[i] = htobe32(auth_ctx->sha256ctx.state[i]);
1504 case CRYPTO_SHA2_384_HMAC:
1505 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++)
1506 u64[i] = htobe64(auth_ctx->sha384ctx.state[i]);
1508 case CRYPTO_SHA2_512_HMAC:
1509 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++)
1510 u64[i] = htobe64(auth_ctx->sha512ctx.state[i]);
1516 ccr_init_hmac_digest(struct ccr_session *s, int cri_alg, char *key,
1519 union authctx auth_ctx;
1520 struct auth_hash *axf;
1524 * If the key is larger than the block size, use the digest of
1525 * the key as the key instead.
1527 axf = s->hmac.auth_hash;
1529 if (klen > axf->blocksize) {
1530 axf->Init(&auth_ctx);
1531 axf->Update(&auth_ctx, key, klen);
1532 axf->Final(s->hmac.ipad, &auth_ctx);
1533 klen = axf->hashsize;
1535 memcpy(s->hmac.ipad, key, klen);
1537 memset(s->hmac.ipad + klen, 0, axf->blocksize);
1538 memcpy(s->hmac.opad, s->hmac.ipad, axf->blocksize);
1540 for (i = 0; i < axf->blocksize; i++) {
1541 s->hmac.ipad[i] ^= HMAC_IPAD_VAL;
1542 s->hmac.opad[i] ^= HMAC_OPAD_VAL;
1546 * Hash the raw ipad and opad and store the partial result in
1549 axf->Init(&auth_ctx);
1550 axf->Update(&auth_ctx, s->hmac.ipad, axf->blocksize);
1551 ccr_copy_partial_hash(s->hmac.ipad, cri_alg, &auth_ctx);
1553 axf->Init(&auth_ctx);
1554 axf->Update(&auth_ctx, s->hmac.opad, axf->blocksize);
1555 ccr_copy_partial_hash(s->hmac.opad, cri_alg, &auth_ctx);
1559 * Borrowed from AES_GMAC_Setkey().
1562 ccr_init_gmac_hash(struct ccr_session *s, char *key, int klen)
1564 static char zeroes[GMAC_BLOCK_LEN];
1565 uint32_t keysched[4 * (RIJNDAEL_MAXNR + 1)];
1568 rounds = rijndaelKeySetupEnc(keysched, key, klen);
1569 rijndaelEncrypt(keysched, rounds, zeroes, s->gmac.ghash_h);
1573 ccr_aes_check_keylen(int alg, int klen)
1579 if (alg == CRYPTO_AES_XTS)
1585 if (alg != CRYPTO_AES_XTS)
1595 * Borrowed from cesa_prep_aes_key(). We should perhaps have a public
1596 * function to generate this instead.
1598 * NB: The crypto engine wants the words in the decryption key in reverse
1602 ccr_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
1604 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
1608 rijndaelKeySetupEnc(ek, enc_key, kbits);
1610 dkey += (kbits / 8) / 4;
1614 for (i = 0; i < 4; i++)
1615 *--dkey = htobe32(ek[4 * 10 + i]);
1618 for (i = 0; i < 2; i++)
1619 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
1620 for (i = 0; i < 4; i++)
1621 *--dkey = htobe32(ek[4 * 12 + i]);
1624 for (i = 0; i < 4; i++)
1625 *--dkey = htobe32(ek[4 * 13 + i]);
1626 for (i = 0; i < 4; i++)
1627 *--dkey = htobe32(ek[4 * 14 + i]);
1630 MPASS(dkey == dec_key);
1634 ccr_aes_setkey(struct ccr_session *s, int alg, const void *key, int klen)
1636 unsigned int ck_size, iopad_size, kctx_flits, kctx_len, kbits, mk_size;
1637 unsigned int opad_present;
1639 if (alg == CRYPTO_AES_XTS)
1645 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
1648 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
1651 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
1654 panic("should not get here");
1657 s->blkcipher.key_len = klen / 8;
1658 memcpy(s->blkcipher.enckey, key, s->blkcipher.key_len);
1660 case CRYPTO_AES_CBC:
1661 case CRYPTO_AES_XTS:
1662 ccr_aes_getdeckey(s->blkcipher.deckey, key, kbits);
1666 kctx_len = roundup2(s->blkcipher.key_len, 16);
1669 mk_size = s->hmac.mk_size;
1671 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
1672 kctx_len += iopad_size * 2;
1675 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128;
1677 kctx_len += GMAC_BLOCK_LEN;
1680 mk_size = CHCR_KEYCTX_NO_KEY;
1684 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16;
1685 s->blkcipher.key_ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) |
1686 V_KEY_CONTEXT_DUAL_CK(alg == CRYPTO_AES_XTS) |
1687 V_KEY_CONTEXT_OPAD_PRESENT(opad_present) |
1688 V_KEY_CONTEXT_SALT_PRESENT(1) | V_KEY_CONTEXT_CK_SIZE(ck_size) |
1689 V_KEY_CONTEXT_MK_SIZE(mk_size) | V_KEY_CONTEXT_VALID(1));
1693 ccr_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri)
1695 struct ccr_softc *sc;
1696 struct ccr_session *s;
1697 struct auth_hash *auth_hash;
1698 struct cryptoini *c, *hash, *cipher;
1699 unsigned int auth_mode, cipher_mode, iv_len, mk_size;
1700 unsigned int partial_digest_len;
1704 if (sidp == NULL || cri == NULL)
1711 auth_mode = CHCR_SCMD_AUTH_MODE_NOP;
1712 cipher_mode = CHCR_SCMD_CIPHER_MODE_NOP;
1715 partial_digest_len = 0;
1716 for (c = cri; c != NULL; c = c->cri_next) {
1717 switch (c->cri_alg) {
1718 case CRYPTO_SHA1_HMAC:
1719 case CRYPTO_SHA2_256_HMAC:
1720 case CRYPTO_SHA2_384_HMAC:
1721 case CRYPTO_SHA2_512_HMAC:
1722 case CRYPTO_AES_128_NIST_GMAC:
1723 case CRYPTO_AES_192_NIST_GMAC:
1724 case CRYPTO_AES_256_NIST_GMAC:
1728 switch (c->cri_alg) {
1729 case CRYPTO_SHA1_HMAC:
1730 auth_hash = &auth_hash_hmac_sha1;
1731 auth_mode = CHCR_SCMD_AUTH_MODE_SHA1;
1732 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160;
1733 partial_digest_len = SHA1_HASH_LEN;
1735 case CRYPTO_SHA2_256_HMAC:
1736 auth_hash = &auth_hash_hmac_sha2_256;
1737 auth_mode = CHCR_SCMD_AUTH_MODE_SHA256;
1738 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
1739 partial_digest_len = SHA2_256_HASH_LEN;
1741 case CRYPTO_SHA2_384_HMAC:
1742 auth_hash = &auth_hash_hmac_sha2_384;
1743 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384;
1744 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
1745 partial_digest_len = SHA2_512_HASH_LEN;
1747 case CRYPTO_SHA2_512_HMAC:
1748 auth_hash = &auth_hash_hmac_sha2_512;
1749 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512;
1750 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
1751 partial_digest_len = SHA2_512_HASH_LEN;
1753 case CRYPTO_AES_128_NIST_GMAC:
1754 case CRYPTO_AES_192_NIST_GMAC:
1755 case CRYPTO_AES_256_NIST_GMAC:
1757 auth_mode = CHCR_SCMD_AUTH_MODE_GHASH;
1758 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128;
1762 case CRYPTO_AES_CBC:
1763 case CRYPTO_AES_ICM:
1764 case CRYPTO_AES_NIST_GCM_16:
1765 case CRYPTO_AES_XTS:
1769 switch (c->cri_alg) {
1770 case CRYPTO_AES_CBC:
1771 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC;
1772 iv_len = AES_BLOCK_LEN;
1774 case CRYPTO_AES_ICM:
1775 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR;
1776 iv_len = AES_BLOCK_LEN;
1778 case CRYPTO_AES_NIST_GCM_16:
1779 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_GCM;
1780 iv_len = AES_GCM_IV_LEN;
1782 case CRYPTO_AES_XTS:
1783 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS;
1784 iv_len = AES_BLOCK_LEN;
1787 if (c->cri_key != NULL) {
1788 error = ccr_aes_check_keylen(c->cri_alg,
1798 if (gcm_hash != (cipher_mode == CHCR_SCMD_CIPHER_MODE_AES_GCM))
1800 if (hash == NULL && cipher == NULL)
1802 if (hash != NULL && hash->cri_key == NULL)
1805 sc = device_get_softc(dev);
1806 mtx_lock(&sc->lock);
1807 if (sc->detaching) {
1808 mtx_unlock(&sc->lock);
1812 for (i = 0; i < sc->nsessions; i++) {
1813 if (!sc->sessions[i].active && sc->sessions[i].pending == 0) {
1819 s = malloc(sizeof(*s) * (sc->nsessions + 1), M_CCR,
1822 mtx_unlock(&sc->lock);
1825 if (sc->sessions != NULL)
1826 memcpy(s, sc->sessions, sizeof(*s) * sc->nsessions);
1827 sess = sc->nsessions;
1828 free(sc->sessions, M_CCR);
1833 s = &sc->sessions[sess];
1837 else if (hash != NULL && cipher != NULL)
1839 else if (hash != NULL)
1842 MPASS(cipher != NULL);
1843 s->mode = BLKCIPHER;
1846 if (hash->cri_mlen == 0)
1847 s->gmac.hash_len = AES_GMAC_HASH_LEN;
1849 s->gmac.hash_len = hash->cri_mlen;
1850 ccr_init_gmac_hash(s, hash->cri_key, hash->cri_klen);
1851 } else if (hash != NULL) {
1852 s->hmac.auth_hash = auth_hash;
1853 s->hmac.auth_mode = auth_mode;
1854 s->hmac.mk_size = mk_size;
1855 s->hmac.partial_digest_len = partial_digest_len;
1856 if (hash->cri_mlen == 0)
1857 s->hmac.hash_len = auth_hash->hashsize;
1859 s->hmac.hash_len = hash->cri_mlen;
1860 ccr_init_hmac_digest(s, hash->cri_alg, hash->cri_key,
1863 if (cipher != NULL) {
1864 s->blkcipher.cipher_mode = cipher_mode;
1865 s->blkcipher.iv_len = iv_len;
1866 if (cipher->cri_key != NULL)
1867 ccr_aes_setkey(s, cipher->cri_alg, cipher->cri_key,
1872 mtx_unlock(&sc->lock);
1879 ccr_freesession(device_t dev, uint64_t tid)
1881 struct ccr_softc *sc;
1885 sc = device_get_softc(dev);
1886 sid = CRYPTO_SESID2LID(tid);
1887 mtx_lock(&sc->lock);
1888 if (sid >= sc->nsessions || !sc->sessions[sid].active)
1891 if (sc->sessions[sid].pending != 0)
1893 "session %d freed with %d pending requests\n", sid,
1894 sc->sessions[sid].pending);
1895 sc->sessions[sid].active = false;
1898 mtx_unlock(&sc->lock);
1903 ccr_process(device_t dev, struct cryptop *crp, int hint)
1905 struct ccr_softc *sc;
1906 struct ccr_session *s;
1907 struct cryptodesc *crd, *crda, *crde;
1914 crd = crp->crp_desc;
1915 sid = CRYPTO_SESID2LID(crp->crp_sid);
1916 sc = device_get_softc(dev);
1917 mtx_lock(&sc->lock);
1918 if (sid >= sc->nsessions || !sc->sessions[sid].active) {
1919 sc->stats_bad_session++;
1924 error = ccr_populate_sglist(sc->sg_crp, crp);
1926 sc->stats_sglist_error++;
1930 s = &sc->sessions[sid];
1933 if (crd->crd_flags & CRD_F_KEY_EXPLICIT)
1934 ccr_init_hmac_digest(s, crd->crd_alg, crd->crd_key,
1936 error = ccr_hmac(sc, sid, s, crp);
1941 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) {
1942 error = ccr_aes_check_keylen(crd->crd_alg,
1946 ccr_aes_setkey(s, crd->crd_alg, crd->crd_key,
1949 error = ccr_blkcipher(sc, sid, s, crp);
1951 if (crd->crd_flags & CRD_F_ENCRYPT)
1952 sc->stats_blkcipher_encrypt++;
1954 sc->stats_blkcipher_decrypt++;
1959 switch (crd->crd_alg) {
1960 case CRYPTO_AES_CBC:
1961 case CRYPTO_AES_ICM:
1962 case CRYPTO_AES_XTS:
1963 /* Only encrypt-then-authenticate supported. */
1965 crda = crd->crd_next;
1966 if (!(crde->crd_flags & CRD_F_ENCRYPT)) {
1973 crde = crd->crd_next;
1974 if (crde->crd_flags & CRD_F_ENCRYPT) {
1982 if (crda->crd_flags & CRD_F_KEY_EXPLICIT)
1983 ccr_init_hmac_digest(s, crda->crd_alg, crda->crd_key,
1985 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) {
1986 error = ccr_aes_check_keylen(crde->crd_alg,
1990 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key,
1993 error = ccr_authenc(sc, sid, s, crp, crda, crde);
1995 if (crde->crd_flags & CRD_F_ENCRYPT)
1996 sc->stats_authenc_encrypt++;
1998 sc->stats_authenc_decrypt++;
2003 if (crd->crd_alg == CRYPTO_AES_NIST_GCM_16) {
2005 crda = crd->crd_next;
2008 crde = crd->crd_next;
2010 if (crda->crd_flags & CRD_F_KEY_EXPLICIT)
2011 ccr_init_gmac_hash(s, crda->crd_key, crda->crd_klen);
2012 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) {
2013 error = ccr_aes_check_keylen(crde->crd_alg,
2017 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key,
2020 error = ccr_gcm(sc, sid, s, crp, crda, crde);
2022 if (crde->crd_flags & CRD_F_ENCRYPT)
2023 sc->stats_gcm_encrypt++;
2025 sc->stats_gcm_decrypt++;
2032 sc->stats_inflight++;
2034 sc->stats_process_error++;
2037 mtx_unlock(&sc->lock);
2040 crp->crp_etype = error;
2048 do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss,
2051 struct ccr_softc *sc = iq->adapter->ccr_softc;
2052 struct ccr_session *s;
2053 const struct cpl_fw6_pld *cpl;
2054 struct cryptop *crp;
2055 uint32_t sid, status;
2059 cpl = mtod(m, const void *);
2061 cpl = (const void *)(rss + 1);
2063 crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]);
2064 sid = CRYPTO_SESID2LID(crp->crp_sid);
2065 status = be64toh(cpl->data[0]);
2066 if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status))
2071 mtx_lock(&sc->lock);
2072 MPASS(sid < sc->nsessions);
2073 s = &sc->sessions[sid];
2075 sc->stats_inflight--;
2079 error = ccr_hmac_done(sc, s, crp, cpl, error);
2082 error = ccr_blkcipher_done(sc, s, crp, cpl, error);
2085 error = ccr_authenc_done(sc, s, crp, cpl, error);
2088 error = ccr_gcm_done(sc, s, crp, cpl, error);
2092 if (error == EBADMSG) {
2093 if (CHK_MAC_ERR_BIT(status))
2094 sc->stats_mac_error++;
2095 if (CHK_PAD_ERR_BIT(status))
2096 sc->stats_pad_error++;
2098 mtx_unlock(&sc->lock);
2099 crp->crp_etype = error;
2106 ccr_modevent(module_t mod, int cmd, void *arg)
2111 t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld);
2114 t4_register_cpl_handler(CPL_FW6_PLD, NULL);
2117 return (EOPNOTSUPP);
2121 static device_method_t ccr_methods[] = {
2122 DEVMETHOD(device_identify, ccr_identify),
2123 DEVMETHOD(device_probe, ccr_probe),
2124 DEVMETHOD(device_attach, ccr_attach),
2125 DEVMETHOD(device_detach, ccr_detach),
2127 DEVMETHOD(cryptodev_newsession, ccr_newsession),
2128 DEVMETHOD(cryptodev_freesession, ccr_freesession),
2129 DEVMETHOD(cryptodev_process, ccr_process),
2134 static driver_t ccr_driver = {
2137 sizeof(struct ccr_softc)
2140 static devclass_t ccr_devclass;
2142 DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_devclass, ccr_modevent, NULL);
2143 MODULE_VERSION(ccr, 1);
2144 MODULE_DEPEND(ccr, crypto, 1, 1, 1);
2145 MODULE_DEPEND(ccr, t6nex, 1, 1, 1);