2 * Copyright (c) 2017 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __CUDBG_ENTITY_H__
31 #define __CUDBG_ENTITY_H__
34 #define ATTRIBUTE_UNUSED __attribute__ ((unused))
36 #define ATTRIBUTE_UNUSED
44 #define NUM_PCIE_CONFIG_REGS 0x61
45 #define CUDBG_CTXT_SIZE_BYTES 24
46 #define CUDBG_MAX_INGRESS_QIDS 65536
47 #define CUDBG_MAX_FL_QIDS 2048
48 #define CUDBG_MAX_CNM_QIDS 1024
49 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
51 #define CUDBG_MAX_RPLC_SIZE 128
52 #define CUDBG_NUM_REQ_REGS 17
53 #define CUDBG_MAX_TCAM_TID 0x800
54 #define CUDBG_NUM_ULPTX 11
55 #define CUDBG_NUM_ULPTX_READ 512
57 #define SN_REG_ADDR 0x183f
58 #define BN_REG_ADDR 0x1819
59 #define NA_REG_ADDR 0x185a
60 #define MN_REG_ADDR 0x1803
62 #define A_MPS_VF_RPLCT_MAP0 0x1111c
63 #define A_MPS_VF_RPLCT_MAP1 0x11120
64 #define A_MPS_VF_RPLCT_MAP2 0x11124
65 #define A_MPS_VF_RPLCT_MAP3 0x11128
66 #define A_MPS_VF_RPLCT_MAP4 0x11300
67 #define A_MPS_VF_RPLCT_MAP5 0x11304
68 #define A_MPS_VF_RPLCT_MAP6 0x11308
69 #define A_MPS_VF_RPLCT_MAP7 0x1130c
71 #define PORT_TYPE_ADDR 0x1869
72 #define PORT_TYPE_LEN 8
75 #define SN_T6_ADDR 0x83f
76 #define BN_T6_ADDR 0x819
77 #define NA_T6_ADDR 0x85a
78 #define MN_T6_ADDR 0x803
84 #define MAX_VPD_DATA_LEN 32
86 #define VPD_VER_ADDR 0x18c7
88 #define SCFG_VER_ADDR 0x06
89 #define SCFG_VER_LEN 4
91 #define CUDBG_CIM_BUSY_BIT (1 << 17)
93 #define CUDBG_CHAC_PBT_ADDR 0x2800
94 #define CUDBG_CHAC_PBT_LRF 0x3000
95 #define CUDBG_CHAC_PBT_DATA 0x3800
96 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
97 #define CUDBG_PBT_STATIC_ENTRIES 16
98 #define CUDBG_LRF_ENTRIES 8
99 #define CUDBG_PBT_DATA_ENTRIES 512
101 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
102 #define CUDBG_TID_INFO_REV 1
103 #define CUDBG_MAC_STATS_REV 1
106 #define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0]))
109 struct cudbg_pbt_tables {
110 u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
111 u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
112 u32 lrf_table[CUDBG_LRF_ENTRIES];
113 u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
131 struct cudbg_ch_cntxt {
134 uint32_t data[SGE_CTXT_SIZE / 4];
147 struct cudbg_mbox_log {
148 struct mbox_cmd entry;
149 u32 hi[MBOX_LEN / 8];
150 u32 lo[MBOX_LEN / 8];
154 struct cudbg_tid_data {
159 u32 data[CUDBG_NUM_REQ_REGS];
162 struct cudbg_cntxt_field {
170 struct cudbg_mps_tcam {
195 u32 tp_rssconf; /* A_TP_RSS_CONFIG */
196 u32 tp_rssconf_tnl; /* A_TP_RSS_CONFIG_TNL */
197 u32 tp_rssconf_ofd; /* A_TP_RSS_CONFIG_OFD */
198 u32 tp_rssconf_syn; /* A_TP_RSS_CONFIG_SYN */
199 u32 tp_rssconf_vrt; /* A_TP_RSS_CONFIG_VRT */
200 u32 tp_rssconf_cng; /* A_TP_RSS_CONFIG_CNG */
204 struct struct_pm_stats {
205 u32 tx_cnt[T6_PM_NSTATS];
206 u32 rx_cnt[T6_PM_NSTATS];
207 u64 tx_cyc[T6_PM_NSTATS];
208 u64 rx_cyc[T6_PM_NSTATS];
211 struct struct_hw_sched {
214 u32 pace_tab[NTX_SCHED];
219 struct struct_tcp_stats {
220 struct tp_tcp_stats v4, v6;
223 struct struct_tp_err_stats {
224 struct tp_err_stats stats;
228 struct struct_tp_fcoe_stats {
229 struct tp_fcoe_stats stats[4];
233 struct struct_mac_stats {
235 struct port_stats stats[4];
238 struct struct_mac_stats_rev1 {
239 struct cudbg_ver_hdr ver_hdr;
242 struct port_stats stats[4];
245 struct struct_tp_cpl_stats {
246 struct tp_cpl_stats stats;
250 struct struct_wc_stats {
255 struct struct_ulptx_la {
256 u32 rdptr[CUDBG_NUM_ULPTX];
257 u32 wrptr[CUDBG_NUM_ULPTX];
258 u32 rddata[CUDBG_NUM_ULPTX];
259 u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
262 struct struct_ulprx_la {
263 u32 data[ULPRX_LA_SIZE * 8];
267 struct struct_cim_qcfg {
269 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
270 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
271 u16 thres[CIM_NUM_IBQ];
272 u32 obq_wr[2 * CIM_NUM_OBQ_T5];
273 u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
277 REGN_DBQ_CONTEXS_IDX,
278 REGN_IMSG_CONTEXTS_IDX,
298 REGN_ULPRX_STATE_IDX,
299 REGN_ULPTX_STATE_IDX,
300 #ifndef __NO_DRIVER_OCQ_SUPPORT__
305 static const char * const region[] = {
306 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
307 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
308 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
309 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
310 "RQUDP region:", "PBL region:", "TXPBL region:",
311 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
312 #ifndef __NO_DRIVER_OCQ_SUPPORT__
317 /* Info relative to memory region (i.e. wrt 0). */
318 struct struct_region_info {
319 bool exist; /* Does region exists in current memory region? */
320 u32 start; /* Start wrt 0 */
321 u32 end; /* End wrt 0 */
324 struct struct_port_usage {
330 struct struct_lpbk_usage {
336 struct struct_mem_desc {
342 enum string_size_units {
343 STRING_UNITS_10, /* use powers of 10^3 (standard SI) */
344 STRING_UNITS_2, /* use binary powers of 2^10 */
347 struct struct_meminfo {
348 struct struct_mem_desc avail[4];
349 struct struct_mem_desc mem[ARRAY_SIZE(region) + 3];
356 u32 rx_pages_data[3];
357 u32 tx_pages_data[4];
359 struct struct_port_usage port_data[4];
362 u32 loopback_used[NCHAN];
363 u32 loopback_alloc[NCHAN];
367 #pragma warning(disable : 4200)
370 struct struct_lb_stats {
372 struct lb_port_stats s[0];
375 struct struct_clk_info {
378 u64 persist_timer_min;
379 u64 persist_timer_max;
380 u64 keepalive_idle_timer;
381 u64 keepalive_interval;
389 char core_clk_period[32];
390 char tp_timer_tick[32];
391 char tcp_tstamp_tick[32];
400 struct struct_tp_la {
440 /*TX path, Request Work request sub-path:*/
442 struct wtp_type_1 sge_pcie_cmd_req; /*SGE_DEBUG PC_Req_xOPn*/
443 struct wtp_type_1 pcie_core_cmd_req; /*PCIE_CMDR_REQ_CNT*/
446 /*TX path, Work request to uP sub-path*/
447 struct wtp_type_1 core_pcie_cmd_rsp; /*PCIE_CMDR_RSP_CNT*/
448 struct wtp_type_1 pcie_sge_cmd_rsp; /*SGE_DEBUG PC_Rsp_xOPn*/
449 struct wtp_type_1 sge_cim; /*SGE_DEBUG CIM_xOPn*/
451 /*TX path, Data request path from ULP_TX to core*/
452 struct wtp_type_2 utx_sge_dma_req; /*SGE UD_Rx_xOPn*/
453 struct wtp_type_2 sge_pcie_dma_req; /*SGE PD_Req_Rdn (no eops)*/
454 struct wtp_type_2 pcie_core_dma_req; /*PCIE_DMAR_REQ_CNT (no eops)*/
456 /*Main TX path, from core to wire*/
457 struct wtp_type_2 core_pcie_dma_rsp; /*PCIE_DMAR_RSP_SOP_CNT/
459 struct wtp_type_2 pcie_sge_dma_rsp; /*SGE_DEBUG PD_Rsp_xOPn*/
460 struct wtp_type_2 sge_utx; /*SGE_DEBUG U_Tx_xOPn*/
461 struct wtp_type_2 utx_tp; /*ULP_TX_SE_CNT_CHn[xOP_CNT_ULP2TP]*/
462 struct wtp_type_2 utx_tpcside; /*TP_DBG_CSIDE_RXn[RxXoPCnt]*/
464 struct wtp_type_2 tpcside_rxpld;
465 struct wtp_type_2 tpcside_rxarb; /*TP_DBG_CSIDE_RXn[RxArbXopCnt]*/
466 struct wtp_type_2 tpcside_rxcpl;
468 struct wtp_type_2 tpeside_mps; /*TP_DBG_ESDIE_PKT0[TxXoPCnt]*/
469 struct wtp_type_2 tpeside_pm;
470 struct wtp_type_2 tpeside_pld;
472 /*Tx path, PCIE t5 DMA stat*/
473 struct wtp_type_2 pcie_t5_dma_stat3;
475 /*Tx path, SGE debug data high index 6*/
476 struct wtp_type_2 sge_debug_data_high_index_6;
478 /*Tx path, SGE debug data high index 3*/
479 struct wtp_type_2 sge_debug_data_high_index_3;
481 /*Tx path, ULP SE CNT CHx*/
482 struct wtp_type_2 ulp_se_cnt_chx;
485 struct wtp_type_2 pcie_cmd_stat2;
488 struct wtp_type_2 pcie_cmd_stat3;
490 struct wtp_type_2 pcie_dma1_stat2_core;
492 struct wtp_type_1 sge_work_req_pkt;
494 struct wtp_type_2 sge_debug_data_high_indx5;
496 /*Tx path, mac portx pkt count*/
497 struct wtp_type_2 mac_portx_pkt_count;
499 /*Rx path, mac porrx pkt count*/
500 struct wtp_type_2 mac_porrx_pkt_count;
502 /*Rx path, PCIE T5 dma1 stat 2*/
503 struct wtp_type_2 pcie_dma1_stat2;
505 /*Rx path, sge debug data high index 7*/
506 struct wtp_type_2 sge_debug_data_high_indx7;
508 /*Rx path, sge debug data high index 1*/
509 struct wtp_type_1 sge_debug_data_high_indx1;
511 /*Rx path, TP debug CSIDE Tx register*/
512 struct wtp_type_1 utx_tpcside_tx;
514 /*Rx path, LE DB response count*/
515 struct wtp_type_0 le_db_rsp_cnt;
517 /*Rx path, TP debug Eside PKTx*/
518 struct wtp_type_2 tp_dbg_eside_pktx;
520 /*Rx path, sge debug data high index 9*/
521 struct wtp_type_1 sge_debug_data_high_indx9;
523 /*Tx path, mac portx aFramesTransmittesok*/
524 struct wtp_type_2 mac_portx_aframestra_ok;
526 /*Rx path, mac portx aFramesTransmittesok*/
527 struct wtp_type_2 mac_porrx_aframestra_ok;
529 /*Tx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
530 struct wtp_type_1 mac_portx_etherstatspkts;
532 /*Rx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
533 struct wtp_type_1 mac_porrx_etherstatspkts;
535 struct wtp_type_3 tp_mps; /*MPS_TX_SE_CNT_TP01 and
537 struct wtp_type_3 mps_xgm; /*MPS_TX_SE_CNT_MAC01 and
538 MPS_TX_SE_CNT_MAC34*/
539 struct wtp_type_2 tx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/
540 struct wtp_type_2 xgm_wire; /*XGMAC_PORT_XGM_STAT_TX_FRAME_LOW_PORT_N
543 /*RX path, from wire to core.*/
544 struct wtp_type_2 wire_xgm; /*XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW_PORT_N
546 struct wtp_type_2 rx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/
547 struct _xgm_mps { /*MPS_RX_SE_CNT_INn*/
548 u32 sop[8]; /* => undef,*/
549 u32 eop[8]; /* => undef,*/
550 u32 drop; /* => undef,*/
551 u32 cls_drop; /* => undef,*/
552 u32 err; /* => undef,*/
553 u32 bp; /* => undef,*/
556 struct wtp_type_3 mps_tp; /*MPS_RX_SE_CNT_OUT01 and
557 MPS_RX_SE_CNT_OUT23*/
558 struct wtp_type_2 mps_tpeside; /*TP_DBG_ESIDE_PKTn*/
559 struct wtp_type_1 tpeside_pmrx; /*???*/
560 struct wtp_type_2 pmrx_ulprx; /*ULP_RX_SE_CNT_CHn[xOP_CNT_INn]*/
561 struct wtp_type_2 ulprx_tpcside; /*ULP_RX_SE_CNT_CHn[xOP_CNT_OUTn]*/
562 struct wtp_type_2 tpcside_csw; /*TP_DBG_CSIDE_TXn[TxSopCnt]*/
563 struct wtp_type_2 tpcside_pm;
564 struct wtp_type_2 tpcside_uturn;
565 struct wtp_type_2 tpcside_txcpl;
566 struct wtp_type_1 tp_csw; /*SGE_DEBUG CPLSW_TP_Rx_xOPn*/
567 struct wtp_type_1 csw_sge; /*SGE_DEBUG T_Rx_xOPn*/
568 struct wtp_type_2 sge_pcie; /*SGE_DEBUG PD_Req_SopN -
569 PD_Req_RdN - PD_ReqIntN*/
570 struct wtp_type_2 sge_pcie_ints; /*SGE_DEBUG PD_Req_IntN*/
571 struct wtp_type_2 pcie_core_dmaw; /*PCIE_DMAW_SOP_CNT and
573 struct wtp_type_2 pcie_core_dmai; /*PCIE_DMAI_CNT*/
578 struct tp_mib_type TP_MIB_MAC_IN_ERR_0;
579 struct tp_mib_type TP_MIB_MAC_IN_ERR_1;
580 struct tp_mib_type TP_MIB_MAC_IN_ERR_2;
581 struct tp_mib_type TP_MIB_MAC_IN_ERR_3;
582 struct tp_mib_type TP_MIB_HDR_IN_ERR_0;
583 struct tp_mib_type TP_MIB_HDR_IN_ERR_1;
584 struct tp_mib_type TP_MIB_HDR_IN_ERR_2;
585 struct tp_mib_type TP_MIB_HDR_IN_ERR_3;
586 struct tp_mib_type TP_MIB_TCP_IN_ERR_0;
587 struct tp_mib_type TP_MIB_TCP_IN_ERR_1;
588 struct tp_mib_type TP_MIB_TCP_IN_ERR_2;
589 struct tp_mib_type TP_MIB_TCP_IN_ERR_3;
590 struct tp_mib_type TP_MIB_TCP_OUT_RST;
591 struct tp_mib_type TP_MIB_TCP_IN_SEG_HI;
592 struct tp_mib_type TP_MIB_TCP_IN_SEG_LO;
593 struct tp_mib_type TP_MIB_TCP_OUT_SEG_HI;
594 struct tp_mib_type TP_MIB_TCP_OUT_SEG_LO;
595 struct tp_mib_type TP_MIB_TCP_RXT_SEG_HI;
596 struct tp_mib_type TP_MIB_TCP_RXT_SEG_LO;
597 struct tp_mib_type TP_MIB_TNL_CNG_DROP_0;
598 struct tp_mib_type TP_MIB_TNL_CNG_DROP_1;
599 struct tp_mib_type TP_MIB_TNL_CNG_DROP_2;
600 struct tp_mib_type TP_MIB_TNL_CNG_DROP_3;
601 struct tp_mib_type TP_MIB_OFD_CHN_DROP_0;
602 struct tp_mib_type TP_MIB_OFD_CHN_DROP_1;
603 struct tp_mib_type TP_MIB_OFD_CHN_DROP_2;
604 struct tp_mib_type TP_MIB_OFD_CHN_DROP_3;
605 struct tp_mib_type TP_MIB_TNL_OUT_PKT_0;
606 struct tp_mib_type TP_MIB_TNL_OUT_PKT_1;
607 struct tp_mib_type TP_MIB_TNL_OUT_PKT_2;
608 struct tp_mib_type TP_MIB_TNL_OUT_PKT_3;
609 struct tp_mib_type TP_MIB_TNL_IN_PKT_0;
610 struct tp_mib_type TP_MIB_TNL_IN_PKT_1;
611 struct tp_mib_type TP_MIB_TNL_IN_PKT_2;
612 struct tp_mib_type TP_MIB_TNL_IN_PKT_3;
613 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_0;
614 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_1;
615 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_2;
616 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_3;
617 struct tp_mib_type TP_MIB_TCP_V6OUT_RST;
618 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_HI;
619 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_LO;
620 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_HI;
621 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_LO;
622 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_HI;
623 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_LO;
624 struct tp_mib_type TP_MIB_OFD_ARP_DROP;
625 struct tp_mib_type TP_MIB_OFD_DFR_DROP;
626 struct tp_mib_type TP_MIB_CPL_IN_REQ_0;
627 struct tp_mib_type TP_MIB_CPL_IN_REQ_1;
628 struct tp_mib_type TP_MIB_CPL_IN_REQ_2;
629 struct tp_mib_type TP_MIB_CPL_IN_REQ_3;
630 struct tp_mib_type TP_MIB_CPL_OUT_RSP_0;
631 struct tp_mib_type TP_MIB_CPL_OUT_RSP_1;
632 struct tp_mib_type TP_MIB_CPL_OUT_RSP_2;
633 struct tp_mib_type TP_MIB_CPL_OUT_RSP_3;
634 struct tp_mib_type TP_MIB_TNL_LPBK_0;
635 struct tp_mib_type TP_MIB_TNL_LPBK_1;
636 struct tp_mib_type TP_MIB_TNL_LPBK_2;
637 struct tp_mib_type TP_MIB_TNL_LPBK_3;
638 struct tp_mib_type TP_MIB_TNL_DROP_0;
639 struct tp_mib_type TP_MIB_TNL_DROP_1;
640 struct tp_mib_type TP_MIB_TNL_DROP_2;
641 struct tp_mib_type TP_MIB_TNL_DROP_3;
642 struct tp_mib_type TP_MIB_FCOE_DDP_0;
643 struct tp_mib_type TP_MIB_FCOE_DDP_1;
644 struct tp_mib_type TP_MIB_FCOE_DDP_2;
645 struct tp_mib_type TP_MIB_FCOE_DDP_3;
646 struct tp_mib_type TP_MIB_FCOE_DROP_0;
647 struct tp_mib_type TP_MIB_FCOE_DROP_1;
648 struct tp_mib_type TP_MIB_FCOE_DROP_2;
649 struct tp_mib_type TP_MIB_FCOE_DROP_3;
650 struct tp_mib_type TP_MIB_FCOE_BYTE_0_HI;
651 struct tp_mib_type TP_MIB_FCOE_BYTE_0_LO;
652 struct tp_mib_type TP_MIB_FCOE_BYTE_1_HI;
653 struct tp_mib_type TP_MIB_FCOE_BYTE_1_LO;
654 struct tp_mib_type TP_MIB_FCOE_BYTE_2_HI;
655 struct tp_mib_type TP_MIB_FCOE_BYTE_2_LO;
656 struct tp_mib_type TP_MIB_FCOE_BYTE_3_HI;
657 struct tp_mib_type TP_MIB_FCOE_BYTE_3_LO;
658 struct tp_mib_type TP_MIB_OFD_VLN_DROP_0;
659 struct tp_mib_type TP_MIB_OFD_VLN_DROP_1;
660 struct tp_mib_type TP_MIB_OFD_VLN_DROP_2;
661 struct tp_mib_type TP_MIB_OFD_VLN_DROP_3;
662 struct tp_mib_type TP_MIB_USM_PKTS;
663 struct tp_mib_type TP_MIB_USM_DROP;
664 struct tp_mib_type TP_MIB_USM_BYTES_HI;
665 struct tp_mib_type TP_MIB_USM_BYTES_LO;
666 struct tp_mib_type TP_MIB_TID_DEL;
667 struct tp_mib_type TP_MIB_TID_INV;
668 struct tp_mib_type TP_MIB_TID_ACT;
669 struct tp_mib_type TP_MIB_TID_PAS;
670 struct tp_mib_type TP_MIB_RQE_DFR_MOD;
671 struct tp_mib_type TP_MIB_RQE_DFR_PKT;
674 struct cudbg_reg_info {
680 struct tp1_reg_info {
688 u32 ireg_local_offset;
689 u32 ireg_offset_range;
693 struct ireg_field tp_pio;
703 struct tid_info_region {
715 /* Server filter region */
719 /* UO context range */
733 struct tid_info_region_rev1 {
734 struct cudbg_ver_hdr ver_hdr;
735 struct tid_info_region tid;
740 struct struct_vpd_data {
741 u8 sn[SN_MAX_LEN + 1];
742 u8 bn[BN_MAX_LEN + 1];
743 u8 na[NA_MAX_LEN + 1];
744 u8 mn[MN_MAX_LEN + 1];
755 u8 caller_string[100];
761 static u32 ATTRIBUTE_UNUSED t6_tp_pio_array[][4] = {
762 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
763 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
764 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
765 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
766 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
767 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
768 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
769 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
770 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
771 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
772 {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
773 {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
776 static u32 ATTRIBUTE_UNUSED t5_tp_pio_array[][4] = {
777 {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
778 {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
779 {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
780 {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
781 {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
782 {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
783 {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
784 {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
785 {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
786 {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
787 {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
790 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array[][4] = {
791 {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
792 {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
793 {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
796 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array2[][4] = {
797 {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
798 {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
801 static u32 ATTRIBUTE_UNUSED t6_hma_ireg_array[][4] = {
802 {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
804 static u32 ATTRIBUTE_UNUSED t5_pcie_pdbg_array[][4] = {
805 {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
806 {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
807 {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
810 static u32 ATTRIBUTE_UNUSED t5_pcie_config_array[][2] = {
827 static u32 ATTRIBUTE_UNUSED t5_pcie_cdbg_array[][4] = {
828 {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
829 {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
832 static u32 ATTRIBUTE_UNUSED t6_tp_tm_pio_array[1][4] = {
833 {0x7e18, 0x7e1c, 0x0, 12}
836 static u32 ATTRIBUTE_UNUSED t5_tp_tm_pio_array[1][4] = {
837 {0x7e18, 0x7e1c, 0x0, 12}
840 static u32 ATTRIBUTE_UNUSED t5_pm_rx_array[][4] = {
841 {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
842 {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
845 static u32 ATTRIBUTE_UNUSED t5_pm_tx_array[][4] = {
846 {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
847 {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
850 static u32 ATTRIBUTE_UNUSED t6_tp_mib_index_array[6][4] = {
851 {0x7e50, 0x7e54, 0x0, 13},
852 {0x7e50, 0x7e54, 0x10, 6},
853 {0x7e50, 0x7e54, 0x18, 21},
854 {0x7e50, 0x7e54, 0x30, 32},
855 {0x7e50, 0x7e54, 0x50, 22},
856 {0x7e50, 0x7e54, 0x68, 12}
859 static u32 ATTRIBUTE_UNUSED t5_tp_mib_index_array[9][4] = {
860 {0x7e50, 0x7e54, 0x0, 13},
861 {0x7e50, 0x7e54, 0x10, 6},
862 {0x7e50, 0x7e54, 0x18, 8},
863 {0x7e50, 0x7e54, 0x20, 13},
864 {0x7e50, 0x7e54, 0x30, 16},
865 {0x7e50, 0x7e54, 0x40, 16},
866 {0x7e50, 0x7e54, 0x50, 16},
867 {0x7e50, 0x7e54, 0x60, 6},
868 {0x7e50, 0x7e54, 0x68, 4}
871 static u32 ATTRIBUTE_UNUSED t5_sge_dbg_index_array[9][4] = {
872 {0x10cc, 0x10d0, 0x0, 16},
873 {0x10cc, 0x10d4, 0x0, 16},
876 static u32 ATTRIBUTE_UNUSED t6_up_cim_reg_array[][4] = {
877 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
878 {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
879 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
880 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
881 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
882 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
883 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
884 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
885 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
886 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
887 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
888 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
889 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
893 static u32 ATTRIBUTE_UNUSED t5_up_cim_reg_array[][4] = {
894 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
895 {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
896 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
897 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
898 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
899 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
900 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
901 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
902 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
903 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
904 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
905 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
906 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */