2 * Copyright (c) 2012 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _T4FW_INTERFACE_H_
31 #define _T4FW_INTERFACE_H_
33 /******************************************************************************
34 * R E T U R N V A L U E S
35 ********************************/
38 FW_SUCCESS = 0, /* completed sucessfully */
39 FW_EPERM = 1, /* operation not permitted */
40 FW_ENOENT = 2, /* no such file or directory */
41 FW_EIO = 5, /* input/output error; hw bad */
42 FW_ENOEXEC = 8, /* exec format error; inv microcode */
43 FW_EAGAIN = 11, /* try again */
44 FW_ENOMEM = 12, /* out of memory */
45 FW_EFAULT = 14, /* bad address; fw bad */
46 FW_EBUSY = 16, /* resource busy */
47 FW_EEXIST = 17, /* file exists */
48 FW_ENODEV = 19, /* no such device */
49 FW_EINVAL = 22, /* invalid argument */
50 FW_ENOSPC = 28, /* no space left on device */
51 FW_ENOSYS = 38, /* functionality not implemented */
52 FW_ENODATA = 61, /* no data available */
53 FW_EPROTO = 71, /* protocol error */
54 FW_EADDRINUSE = 98, /* address already in use */
55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
56 FW_ENETDOWN = 100, /* network is down */
57 FW_ENETUNREACH = 101, /* network is unreachable */
58 FW_ENOBUFS = 105, /* no buffer space available */
59 FW_ETIMEDOUT = 110, /* timeout */
60 FW_EINPROGRESS = 115, /* fw internal */
61 FW_SCSI_ABORT_REQUESTED = 128, /* */
62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
63 FW_SCSI_ABORTED = 130, /* */
64 FW_SCSI_CLOSE_REQUESTED = 131, /* */
65 FW_ERR_LINK_DOWN = 132, /* */
66 FW_RDEV_NOT_READY = 133, /* */
67 FW_ERR_RDEV_LOST = 134, /* */
68 FW_ERR_RDEV_LOGO = 135, /* */
69 FW_FCOE_NO_XCHG = 136, /* */
70 FW_SCSI_RSP_ERR = 137, /* */
71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
73 FW_SCSI_OVER_FLOW_ERR = 140, /* */
74 FW_SCSI_DDP_ERR = 141, /* DDP error*/
75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
78 /******************************************************************************
79 * M E M O R Y T Y P E s
80 ******************************/
83 FW_MEMTYPE_EDC0 = 0x0,
84 FW_MEMTYPE_EDC1 = 0x1,
85 FW_MEMTYPE_EXTMEM = 0x2,
86 FW_MEMTYPE_FLASH = 0x4,
87 FW_MEMTYPE_INTERNAL = 0x5,
88 FW_MEMTYPE_EXTMEM1 = 0x6,
91 /******************************************************************************
92 * W O R K R E Q U E S T s
93 ********************************/
100 FW_ETH_TX_PKT_WR = 0x08,
101 FW_ETH_TX_PKT2_WR = 0x44,
102 FW_ETH_TX_PKTS_WR = 0x09,
103 FW_ETH_TX_UO_WR = 0x1c,
104 FW_EQ_FLUSH_WR = 0x1b,
105 FW_OFLD_CONNECTION_WR = 0x2f,
107 FW_OFLD_TX_DATA_WR = 0x0b,
109 FW_ETH_TX_PKT_VM_WR = 0x11,
111 FW_RI_RDMA_WRITE_WR = 0x14,
112 FW_RI_SEND_WR = 0x15,
113 FW_RI_RDMA_READ_WR = 0x16,
114 FW_RI_RECV_WR = 0x17,
115 FW_RI_BIND_MW_WR = 0x18,
116 FW_RI_FR_NSMR_WR = 0x19,
117 FW_RI_INV_LSTAG_WR = 0x1a,
118 FW_RI_SEND_IMMEDIATE_WR = 0x15,
119 FW_RI_ATOMIC_WR = 0x16,
121 FW_CHNET_IFCONF_WR = 0x6b,
123 FW_FOISCSI_NODE_WR = 0x60,
124 FW_FOISCSI_CTRL_WR = 0x6a,
125 FW_FOISCSI_CHAP_WR = 0x6c,
126 FW_FCOE_ELS_CT_WR = 0x30,
127 FW_SCSI_WRITE_WR = 0x31,
128 FW_SCSI_READ_WR = 0x32,
129 FW_SCSI_CMD_WR = 0x33,
130 FW_SCSI_ABRT_CLS_WR = 0x34,
131 FW_SCSI_TGT_ACC_WR = 0x35,
132 FW_SCSI_TGT_XMIT_WR = 0x36,
133 FW_SCSI_TGT_RSP_WR = 0x37,
134 FW_POFCOE_TCB_WR = 0x42,
135 FW_POFCOE_ULPTX_WR = 0x43,
140 * Generic work request header flit0
147 /* work request opcode (hi)
149 #define S_FW_WR_OP 24
150 #define M_FW_WR_OP 0xff
151 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
152 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
154 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
156 #define S_FW_WR_ATOMIC 23
157 #define M_FW_WR_ATOMIC 0x1
158 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
159 #define G_FW_WR_ATOMIC(x) \
160 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
161 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U)
163 /* flush flag (hi) - firmware flushes flushable work request buffered
164 * in the flow context.
166 #define S_FW_WR_FLUSH 22
167 #define M_FW_WR_FLUSH 0x1
168 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH)
169 #define G_FW_WR_FLUSH(x) \
170 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
171 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U)
173 /* completion flag (hi) - firmware generates a cpl_fw6_ack
175 #define S_FW_WR_COMPL 21
176 #define M_FW_WR_COMPL 0x1
177 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL)
178 #define G_FW_WR_COMPL(x) \
179 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
180 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U)
183 /* work request immediate data lengh (hi)
185 #define S_FW_WR_IMMDLEN 0
186 #define M_FW_WR_IMMDLEN 0xff
187 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
188 #define G_FW_WR_IMMDLEN(x) \
189 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
191 /* egress queue status update to associated ingress queue entry (lo)
193 #define S_FW_WR_EQUIQ 31
194 #define M_FW_WR_EQUIQ 0x1
195 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ)
196 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
197 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U)
199 /* egress queue status update to egress queue status entry (lo)
201 #define S_FW_WR_EQUEQ 30
202 #define M_FW_WR_EQUEQ 0x1
203 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
204 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
205 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
207 /* flow context identifier (lo)
209 #define S_FW_WR_FLOWID 8
210 #define M_FW_WR_FLOWID 0xfffff
211 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
212 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
214 /* length in units of 16-bytes (lo)
216 #define S_FW_WR_LEN16 0
217 #define M_FW_WR_LEN16 0xff
218 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
219 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
222 __be32 op_to_fragoff16;
227 #define S_FW_FRAG_WR_EOF 15
228 #define M_FW_FRAG_WR_EOF 0x1
229 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF)
230 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
231 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U)
233 #define S_FW_FRAG_WR_FRAGOFF16 8
234 #define M_FW_FRAG_WR_FRAGOFF16 0x7f
235 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16)
236 #define G_FW_FRAG_WR_FRAGOFF16(x) \
237 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
239 /* valid filter configurations for compressed tuple
240 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
241 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
242 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
243 * OV - Outer VLAN/VNIC_ID,
245 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3
246 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3
247 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B
248 #define HW_TPL_FR_MT_M_OV_P_FC 0x387
249 #define HW_TPL_FR_MT_E_PR_T 0x370
250 #define HW_TPL_FR_MT_E_PR_P_FC 0X363
251 #define HW_TPL_FR_MT_E_T_P_FC 0X353
252 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
253 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
254 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B
255 #define HW_TPL_FR_MT_T_OV_P_FC 0X317
256 #define HW_TPL_FR_M_E_PR_FC 0X2E1
257 #define HW_TPL_FR_M_E_T_FC 0X2D1
258 #define HW_TPL_FR_M_PR_IV_FC 0X2A9
259 #define HW_TPL_FR_M_PR_OV_FC 0X2A5
260 #define HW_TPL_FR_M_T_IV_FC 0X299
261 #define HW_TPL_FR_M_T_OV_FC 0X295
262 #define HW_TPL_FR_E_PR_T_P 0X272
263 #define HW_TPL_FR_E_PR_T_FC 0X271
264 #define HW_TPL_FR_E_IV_FC 0X249
265 #define HW_TPL_FR_E_OV_FC 0X245
266 #define HW_TPL_FR_PR_T_IV_FC 0X239
267 #define HW_TPL_FR_PR_T_OV_FC 0X235
268 #define HW_TPL_FR_IV_OV_FC 0X20D
269 #define HW_TPL_MT_M_E_PR 0X1E0
270 #define HW_TPL_MT_M_E_T 0X1D0
271 #define HW_TPL_MT_E_PR_T_FC 0X171
272 #define HW_TPL_MT_E_IV 0X148
273 #define HW_TPL_MT_E_OV 0X144
274 #define HW_TPL_MT_PR_T_IV 0X138
275 #define HW_TPL_MT_PR_T_OV 0X134
276 #define HW_TPL_M_E_PR_P 0X0E2
277 #define HW_TPL_M_E_T_P 0X0D2
278 #define HW_TPL_E_PR_T_P_FC 0X073
279 #define HW_TPL_E_IV_P 0X04A
280 #define HW_TPL_E_OV_P 0X046
281 #define HW_TPL_PR_T_IV_P 0X03A
282 #define HW_TPL_PR_T_OV_P 0X036
284 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
285 enum fw_filter_wr_cookie {
286 FW_FILTER_WR_SUCCESS,
287 FW_FILTER_WR_FLT_ADDED,
288 FW_FILTER_WR_FLT_DELETED,
289 FW_FILTER_WR_SMT_TBL_FULL,
293 struct fw_filter_wr {
298 __be32 del_filter_to_l2tix;
301 __u8 frag_to_ovlan_vldm;
303 __be16 rx_chan_rx_rpl_iq;
304 __be32 maci_to_matchtypem;
325 #define S_FW_FILTER_WR_TID 12
326 #define M_FW_FILTER_WR_TID 0xfffff
327 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
328 #define G_FW_FILTER_WR_TID(x) \
329 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
331 #define S_FW_FILTER_WR_RQTYPE 11
332 #define M_FW_FILTER_WR_RQTYPE 0x1
333 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
334 #define G_FW_FILTER_WR_RQTYPE(x) \
335 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
336 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
338 #define S_FW_FILTER_WR_NOREPLY 10
339 #define M_FW_FILTER_WR_NOREPLY 0x1
340 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
341 #define G_FW_FILTER_WR_NOREPLY(x) \
342 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
343 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
345 #define S_FW_FILTER_WR_IQ 0
346 #define M_FW_FILTER_WR_IQ 0x3ff
347 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
348 #define G_FW_FILTER_WR_IQ(x) \
349 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
351 #define S_FW_FILTER_WR_DEL_FILTER 31
352 #define M_FW_FILTER_WR_DEL_FILTER 0x1
353 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
354 #define G_FW_FILTER_WR_DEL_FILTER(x) \
355 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
356 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
358 #define S_FW_FILTER_WR_RPTTID 25
359 #define M_FW_FILTER_WR_RPTTID 0x1
360 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
361 #define G_FW_FILTER_WR_RPTTID(x) \
362 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
363 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
365 #define S_FW_FILTER_WR_DROP 24
366 #define M_FW_FILTER_WR_DROP 0x1
367 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
368 #define G_FW_FILTER_WR_DROP(x) \
369 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
370 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
372 #define S_FW_FILTER_WR_DIRSTEER 23
373 #define M_FW_FILTER_WR_DIRSTEER 0x1
374 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
375 #define G_FW_FILTER_WR_DIRSTEER(x) \
376 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
377 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
379 #define S_FW_FILTER_WR_MASKHASH 22
380 #define M_FW_FILTER_WR_MASKHASH 0x1
381 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
382 #define G_FW_FILTER_WR_MASKHASH(x) \
383 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
384 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
386 #define S_FW_FILTER_WR_DIRSTEERHASH 21
387 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
388 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
389 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
390 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
391 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
393 #define S_FW_FILTER_WR_LPBK 20
394 #define M_FW_FILTER_WR_LPBK 0x1
395 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
396 #define G_FW_FILTER_WR_LPBK(x) \
397 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
398 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
400 #define S_FW_FILTER_WR_DMAC 19
401 #define M_FW_FILTER_WR_DMAC 0x1
402 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
403 #define G_FW_FILTER_WR_DMAC(x) \
404 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
405 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
407 #define S_FW_FILTER_WR_SMAC 18
408 #define M_FW_FILTER_WR_SMAC 0x1
409 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
410 #define G_FW_FILTER_WR_SMAC(x) \
411 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
412 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
414 #define S_FW_FILTER_WR_INSVLAN 17
415 #define M_FW_FILTER_WR_INSVLAN 0x1
416 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
417 #define G_FW_FILTER_WR_INSVLAN(x) \
418 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
419 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
421 #define S_FW_FILTER_WR_RMVLAN 16
422 #define M_FW_FILTER_WR_RMVLAN 0x1
423 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
424 #define G_FW_FILTER_WR_RMVLAN(x) \
425 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
426 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
428 #define S_FW_FILTER_WR_HITCNTS 15
429 #define M_FW_FILTER_WR_HITCNTS 0x1
430 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
431 #define G_FW_FILTER_WR_HITCNTS(x) \
432 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
433 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
435 #define S_FW_FILTER_WR_TXCHAN 13
436 #define M_FW_FILTER_WR_TXCHAN 0x3
437 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
438 #define G_FW_FILTER_WR_TXCHAN(x) \
439 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
441 #define S_FW_FILTER_WR_PRIO 12
442 #define M_FW_FILTER_WR_PRIO 0x1
443 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
444 #define G_FW_FILTER_WR_PRIO(x) \
445 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
446 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
448 #define S_FW_FILTER_WR_L2TIX 0
449 #define M_FW_FILTER_WR_L2TIX 0xfff
450 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
451 #define G_FW_FILTER_WR_L2TIX(x) \
452 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
454 #define S_FW_FILTER_WR_FRAG 7
455 #define M_FW_FILTER_WR_FRAG 0x1
456 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
457 #define G_FW_FILTER_WR_FRAG(x) \
458 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
459 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
461 #define S_FW_FILTER_WR_FRAGM 6
462 #define M_FW_FILTER_WR_FRAGM 0x1
463 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
464 #define G_FW_FILTER_WR_FRAGM(x) \
465 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
466 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
468 #define S_FW_FILTER_WR_IVLAN_VLD 5
469 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
470 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
471 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
472 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
473 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
475 #define S_FW_FILTER_WR_OVLAN_VLD 4
476 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
477 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
478 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
479 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
480 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
482 #define S_FW_FILTER_WR_IVLAN_VLDM 3
483 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
484 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
485 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
486 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
487 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
489 #define S_FW_FILTER_WR_OVLAN_VLDM 2
490 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
491 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
492 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
493 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
494 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
496 #define S_FW_FILTER_WR_RX_CHAN 15
497 #define M_FW_FILTER_WR_RX_CHAN 0x1
498 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
499 #define G_FW_FILTER_WR_RX_CHAN(x) \
500 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
501 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
503 #define S_FW_FILTER_WR_RX_RPL_IQ 0
504 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
505 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
506 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
507 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
509 #define S_FW_FILTER_WR_MACI 23
510 #define M_FW_FILTER_WR_MACI 0x1ff
511 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
512 #define G_FW_FILTER_WR_MACI(x) \
513 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
515 #define S_FW_FILTER_WR_MACIM 14
516 #define M_FW_FILTER_WR_MACIM 0x1ff
517 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
518 #define G_FW_FILTER_WR_MACIM(x) \
519 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
521 #define S_FW_FILTER_WR_FCOE 13
522 #define M_FW_FILTER_WR_FCOE 0x1
523 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
524 #define G_FW_FILTER_WR_FCOE(x) \
525 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
526 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
528 #define S_FW_FILTER_WR_FCOEM 12
529 #define M_FW_FILTER_WR_FCOEM 0x1
530 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
531 #define G_FW_FILTER_WR_FCOEM(x) \
532 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
533 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
535 #define S_FW_FILTER_WR_PORT 9
536 #define M_FW_FILTER_WR_PORT 0x7
537 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
538 #define G_FW_FILTER_WR_PORT(x) \
539 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
541 #define S_FW_FILTER_WR_PORTM 6
542 #define M_FW_FILTER_WR_PORTM 0x7
543 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
544 #define G_FW_FILTER_WR_PORTM(x) \
545 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
547 #define S_FW_FILTER_WR_MATCHTYPE 3
548 #define M_FW_FILTER_WR_MATCHTYPE 0x7
549 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
550 #define G_FW_FILTER_WR_MATCHTYPE(x) \
551 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
553 #define S_FW_FILTER_WR_MATCHTYPEM 0
554 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
555 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
556 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
557 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
566 __be32 op_to_immdlen;
571 struct fw_eth_tx_pkt_wr {
573 __be32 equiq_to_len16;
577 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
578 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
579 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
580 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
581 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
583 struct fw_eth_tx_pkt2_wr {
585 __be32 equiq_to_len16;
587 __be32 L4ChkDisable_to_IpHdrLen;
590 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
591 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
592 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
593 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
594 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
596 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
597 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
598 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
599 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
600 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
601 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
602 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
603 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
604 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
606 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
607 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
608 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
609 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
610 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
611 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
612 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
613 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
614 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
616 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28
617 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
618 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
619 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
620 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
621 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
623 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
624 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
625 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
626 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
627 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
629 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
630 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
631 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
632 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
633 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
635 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
636 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
637 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
638 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
639 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
641 struct fw_eth_tx_pkts_wr {
643 __be32 equiq_to_len16;
650 struct fw_eth_tx_uo_wr {
652 __be32 equiq_to_len16;
665 struct fw_eq_flush_wr {
668 __be32 equiq_to_len16;
672 struct fw_ofld_connection_wr {
678 struct fw_ofld_connection_le {
684 union fw_ofld_connection_leip {
685 struct fw_ofld_connection_le_ipv4 {
692 struct fw_ofld_connection_le_ipv6 {
700 struct fw_ofld_connection_tcb {
701 __be32 t_state_to_astid;
702 __be16 cplrxdataack_cplpassacceptrpl;
714 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
715 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
716 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
717 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
718 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
719 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
720 M_FW_OFLD_CONNECTION_WR_VERSION)
721 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)
723 #define S_FW_OFLD_CONNECTION_WR_CPL 30
724 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
725 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
726 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
727 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
728 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
730 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
731 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
732 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
733 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
734 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
735 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
736 M_FW_OFLD_CONNECTION_WR_T_STATE)
738 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
739 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
740 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
741 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
742 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
743 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
744 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
746 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
747 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
748 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
749 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
750 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
751 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
753 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
754 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
755 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
756 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
757 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
758 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
759 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
760 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
761 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
763 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
764 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
765 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
766 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
767 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
768 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
769 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
770 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
771 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
773 enum fw_flowc_mnem_tcpstate {
774 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
775 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
776 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
777 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
778 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
779 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
780 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
781 * will resend FIN - equiv ESTAB
783 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
784 * will resend FIN but have
787 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
788 * will resend FIN but have
791 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
794 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
797 enum fw_flowc_mnem_uostate {
798 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */
799 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */
800 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending
801 * outstanding payload
803 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after
804 * discarding outstanding payload
809 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
810 FW_FLOWC_MNEM_CH = 1,
811 FW_FLOWC_MNEM_PORT = 2,
812 FW_FLOWC_MNEM_IQID = 3,
813 FW_FLOWC_MNEM_SNDNXT = 4,
814 FW_FLOWC_MNEM_RCVNXT = 5,
815 FW_FLOWC_MNEM_SNDBUF = 6,
816 FW_FLOWC_MNEM_MSS = 7,
817 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
818 FW_FLOWC_MNEM_TCPSTATE = 9,
819 FW_FLOWC_MNEM_UOSTATE = 10,
820 FW_FLOWC_MNEM_SCHEDCLASS = 11,
821 FW_FLOWC_MNEM_DCBPRIO = 12,
824 struct fw_flowc_mnemval {
831 __be32 op_to_nparams;
833 #ifndef C99_NOT_SUPPORTED
834 struct fw_flowc_mnemval mnemval[0];
838 #define S_FW_FLOWC_WR_NPARAMS 0
839 #define M_FW_FLOWC_WR_NPARAMS 0xff
840 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS)
841 #define G_FW_FLOWC_WR_NPARAMS(x) \
842 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
844 struct fw_ofld_tx_data_wr {
845 __be32 op_to_immdlen;
848 __be32 lsodisable_to_proxy;
851 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
852 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
853 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
854 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
855 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
856 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
857 M_FW_OFLD_TX_DATA_WR_LSODISABLE)
858 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
860 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
861 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
862 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
863 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
864 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
865 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
866 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
868 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
869 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
870 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
871 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
872 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
873 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
874 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
875 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
876 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
878 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19
879 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1
880 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
881 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \
882 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
883 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U)
885 #define S_FW_OFLD_TX_DATA_WR_SAVE 18
886 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1
887 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE)
888 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \
889 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
890 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U)
892 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17
893 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1
894 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH)
895 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \
896 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
897 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U)
899 #define S_FW_OFLD_TX_DATA_WR_URGENT 16
900 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1
901 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT)
902 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \
903 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
904 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U)
906 #define S_FW_OFLD_TX_DATA_WR_MORE 15
907 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1
908 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE)
909 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \
910 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
911 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U)
913 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14
914 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1
915 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE)
916 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \
917 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
918 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U)
920 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10
921 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf
922 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE)
923 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \
924 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)
926 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6
927 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf
928 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \
929 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
930 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \
931 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
932 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
934 #define S_FW_OFLD_TX_DATA_WR_PROXY 5
935 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1
936 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY)
937 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \
938 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
939 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U)
947 #define S_FW_CMD_WR_DMA 17
948 #define M_FW_CMD_WR_DMA 0x1
949 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA)
950 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
951 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)
953 struct fw_eth_tx_pkt_vm_wr {
955 __be32 equiq_to_len16;
963 /******************************************************************************
964 * R I W O R K R E Q U E S T s
965 **************************************/
967 enum fw_ri_wr_opcode {
968 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
969 FW_RI_READ_REQ = 0x1,
970 FW_RI_READ_RESP = 0x2,
972 FW_RI_SEND_WITH_INV = 0x4,
973 FW_RI_SEND_WITH_SE = 0x5,
974 FW_RI_SEND_WITH_SE_INV = 0x6,
975 FW_RI_TERMINATE = 0x7,
976 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
978 FW_RI_FAST_REGISTER = 0xa,
979 FW_RI_LOCAL_INV = 0xb,
980 FW_RI_QP_MODIFY = 0xc,
984 FW_RI_SEND_IMMEDIATE = 0x8,
985 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9,
986 FW_RI_ATOMIC_REQUEST = 0xa,
987 FW_RI_ATOMIC_RESPONSE = 0xb,
989 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */
990 FW_RI_FAST_REGISTER = 0xd,
991 FW_RI_LOCAL_INV = 0xe,
993 FW_RI_SGE_EC_CR_RETURN = 0xf
996 enum fw_ri_wr_flags {
997 FW_RI_COMPLETION_FLAG = 0x01,
998 FW_RI_NOTIFICATION_FLAG = 0x02,
999 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
1000 FW_RI_READ_FENCE_FLAG = 0x08,
1001 FW_RI_LOCAL_FENCE_FLAG = 0x10,
1002 FW_RI_RDMA_READ_INVALIDATE = 0x20
1005 enum fw_ri_mpa_attrs {
1006 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
1007 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
1008 FW_RI_MPA_CRC_ENABLE = 0x04,
1009 FW_RI_MPA_IETF_ENABLE = 0x08
1012 enum fw_ri_qp_caps {
1013 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
1014 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
1015 FW_RI_QP_BIND_ENABLE = 0x04,
1016 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
1017 FW_RI_QP_STAG0_ENABLE = 0x10,
1018 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1021 enum fw_ri_addr_type {
1022 FW_RI_ZERO_BASED_TO = 0x00,
1023 FW_RI_VA_BASED_TO = 0x01
1026 enum fw_ri_mem_perms {
1027 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
1028 FW_RI_MEM_ACCESS_REM_READ = 0x02,
1029 FW_RI_MEM_ACCESS_REM = 0x03,
1030 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
1031 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
1032 FW_RI_MEM_ACCESS_LOCAL = 0x0C
1035 enum fw_ri_stag_type {
1036 FW_RI_STAG_NSMR = 0x00,
1037 FW_RI_STAG_SMR = 0x01,
1038 FW_RI_STAG_MW = 0x02,
1039 FW_RI_STAG_MW_RELAXED = 0x03
1042 enum fw_ri_data_op {
1043 FW_RI_DATA_IMMD = 0x81,
1044 FW_RI_DATA_DSGL = 0x82,
1045 FW_RI_DATA_ISGL = 0x83
1048 enum fw_ri_sgl_depth {
1049 FW_RI_SGL_DEPTH_MAX_SQ = 16,
1050 FW_RI_SGL_DEPTH_MAX_RQ = 4
1053 enum fw_ri_cqe_err {
1054 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */
1055 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */
1056 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */
1057 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */
1058 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */
1059 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */
1060 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */
1061 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1062 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1063 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */
1064 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1065 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */
1066 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */
1067 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */
1068 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */
1069 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */
1070 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */
1071 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */
1072 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */
1073 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */
1074 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */
1075 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */
1076 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1077 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */
1078 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */
1079 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */
1080 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */
1081 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */
1085 struct fw_ri_dsge_pair {
1096 #ifndef C99_NOT_SUPPORTED
1097 struct fw_ri_dsge_pair sge[0];
1112 #ifndef C99_NOT_SUPPORTED
1113 struct fw_ri_sge sge[0];
1122 #ifndef C99_NOT_SUPPORTED
1128 __be32 valid_to_pdid;
1129 __be32 locread_to_qpid;
1130 __be32 nosnoop_pbladdr;
1134 __be32 dca_mwbcnt_pstag;
1138 #define S_FW_RI_TPTE_VALID 31
1139 #define M_FW_RI_TPTE_VALID 0x1
1140 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
1141 #define G_FW_RI_TPTE_VALID(x) \
1142 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1143 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
1145 #define S_FW_RI_TPTE_STAGKEY 23
1146 #define M_FW_RI_TPTE_STAGKEY 0xff
1147 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
1148 #define G_FW_RI_TPTE_STAGKEY(x) \
1149 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1151 #define S_FW_RI_TPTE_STAGSTATE 22
1152 #define M_FW_RI_TPTE_STAGSTATE 0x1
1153 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
1154 #define G_FW_RI_TPTE_STAGSTATE(x) \
1155 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1156 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
1158 #define S_FW_RI_TPTE_STAGTYPE 20
1159 #define M_FW_RI_TPTE_STAGTYPE 0x3
1160 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
1161 #define G_FW_RI_TPTE_STAGTYPE(x) \
1162 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1164 #define S_FW_RI_TPTE_PDID 0
1165 #define M_FW_RI_TPTE_PDID 0xfffff
1166 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
1167 #define G_FW_RI_TPTE_PDID(x) \
1168 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1170 #define S_FW_RI_TPTE_PERM 28
1171 #define M_FW_RI_TPTE_PERM 0xf
1172 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
1173 #define G_FW_RI_TPTE_PERM(x) \
1174 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1176 #define S_FW_RI_TPTE_REMINVDIS 27
1177 #define M_FW_RI_TPTE_REMINVDIS 0x1
1178 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
1179 #define G_FW_RI_TPTE_REMINVDIS(x) \
1180 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1181 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
1183 #define S_FW_RI_TPTE_ADDRTYPE 26
1184 #define M_FW_RI_TPTE_ADDRTYPE 1
1185 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
1186 #define G_FW_RI_TPTE_ADDRTYPE(x) \
1187 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1188 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
1190 #define S_FW_RI_TPTE_MWBINDEN 25
1191 #define M_FW_RI_TPTE_MWBINDEN 0x1
1192 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
1193 #define G_FW_RI_TPTE_MWBINDEN(x) \
1194 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1195 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
1197 #define S_FW_RI_TPTE_PS 20
1198 #define M_FW_RI_TPTE_PS 0x1f
1199 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
1200 #define G_FW_RI_TPTE_PS(x) \
1201 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1203 #define S_FW_RI_TPTE_QPID 0
1204 #define M_FW_RI_TPTE_QPID 0xfffff
1205 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
1206 #define G_FW_RI_TPTE_QPID(x) \
1207 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1209 #define S_FW_RI_TPTE_NOSNOOP 31
1210 #define M_FW_RI_TPTE_NOSNOOP 0x1
1211 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
1212 #define G_FW_RI_TPTE_NOSNOOP(x) \
1213 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1214 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
1216 #define S_FW_RI_TPTE_PBLADDR 0
1217 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff
1218 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
1219 #define G_FW_RI_TPTE_PBLADDR(x) \
1220 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1222 #define S_FW_RI_TPTE_DCA 24
1223 #define M_FW_RI_TPTE_DCA 0x1f
1224 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
1225 #define G_FW_RI_TPTE_DCA(x) \
1226 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1228 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0
1229 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
1230 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
1231 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1232 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
1233 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1235 enum fw_ri_cqe_rxtx {
1236 FW_RI_CQE_RXTX_RX = 0x0,
1237 FW_RI_CQE_RXTX_TX = 0x1,
1243 __be32 qpid_n_stat_rxtx_type;
1249 __be32 qpid_n_stat_rxtx_type;
1257 #define S_FW_RI_CQE_QPID 12
1258 #define M_FW_RI_CQE_QPID 0xfffff
1259 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID)
1260 #define G_FW_RI_CQE_QPID(x) \
1261 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
1263 #define S_FW_RI_CQE_NOTIFY 10
1264 #define M_FW_RI_CQE_NOTIFY 0x1
1265 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1266 #define G_FW_RI_CQE_NOTIFY(x) \
1267 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
1269 #define S_FW_RI_CQE_STATUS 5
1270 #define M_FW_RI_CQE_STATUS 0x1f
1271 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1272 #define G_FW_RI_CQE_STATUS(x) \
1273 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
1276 #define S_FW_RI_CQE_RXTX 4
1277 #define M_FW_RI_CQE_RXTX 0x1
1278 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX)
1279 #define G_FW_RI_CQE_RXTX(x) \
1280 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
1282 #define S_FW_RI_CQE_TYPE 0
1283 #define M_FW_RI_CQE_TYPE 0xf
1284 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE)
1285 #define G_FW_RI_CQE_TYPE(x) \
1286 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
1288 enum fw_ri_res_type {
1300 union fw_ri_restype {
1301 struct fw_ri_res_sqrq {
1307 __be32 fetchszm_to_iqid;
1308 __be32 dcaen_to_eqsize;
1311 struct fw_ri_res_cq {
1317 __be32 iqandst_to_iqandstindex;
1318 __be16 iqdroprss_to_iqesize;
1328 struct fw_ri_res_wr {
1332 #ifndef C99_NOT_SUPPORTED
1333 struct fw_ri_res res[0];
1337 #define S_FW_RI_RES_WR_NRES 0
1338 #define M_FW_RI_RES_WR_NRES 0xff
1339 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
1340 #define G_FW_RI_RES_WR_NRES(x) \
1341 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1343 #define S_FW_RI_RES_WR_FETCHSZM 26
1344 #define M_FW_RI_RES_WR_FETCHSZM 0x1
1345 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
1346 #define G_FW_RI_RES_WR_FETCHSZM(x) \
1347 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1348 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
1350 #define S_FW_RI_RES_WR_STATUSPGNS 25
1351 #define M_FW_RI_RES_WR_STATUSPGNS 0x1
1352 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
1353 #define G_FW_RI_RES_WR_STATUSPGNS(x) \
1354 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1355 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
1357 #define S_FW_RI_RES_WR_STATUSPGRO 24
1358 #define M_FW_RI_RES_WR_STATUSPGRO 0x1
1359 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
1360 #define G_FW_RI_RES_WR_STATUSPGRO(x) \
1361 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1362 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
1364 #define S_FW_RI_RES_WR_FETCHNS 23
1365 #define M_FW_RI_RES_WR_FETCHNS 0x1
1366 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
1367 #define G_FW_RI_RES_WR_FETCHNS(x) \
1368 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1369 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
1371 #define S_FW_RI_RES_WR_FETCHRO 22
1372 #define M_FW_RI_RES_WR_FETCHRO 0x1
1373 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
1374 #define G_FW_RI_RES_WR_FETCHRO(x) \
1375 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1376 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
1378 #define S_FW_RI_RES_WR_HOSTFCMODE 20
1379 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3
1380 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1381 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \
1382 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1384 #define S_FW_RI_RES_WR_CPRIO 19
1385 #define M_FW_RI_RES_WR_CPRIO 0x1
1386 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
1387 #define G_FW_RI_RES_WR_CPRIO(x) \
1388 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1389 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
1391 #define S_FW_RI_RES_WR_ONCHIP 18
1392 #define M_FW_RI_RES_WR_ONCHIP 0x1
1393 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
1394 #define G_FW_RI_RES_WR_ONCHIP(x) \
1395 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1396 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
1398 #define S_FW_RI_RES_WR_PCIECHN 16
1399 #define M_FW_RI_RES_WR_PCIECHN 0x3
1400 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
1401 #define G_FW_RI_RES_WR_PCIECHN(x) \
1402 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1404 #define S_FW_RI_RES_WR_IQID 0
1405 #define M_FW_RI_RES_WR_IQID 0xffff
1406 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
1407 #define G_FW_RI_RES_WR_IQID(x) \
1408 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1410 #define S_FW_RI_RES_WR_DCAEN 31
1411 #define M_FW_RI_RES_WR_DCAEN 0x1
1412 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
1413 #define G_FW_RI_RES_WR_DCAEN(x) \
1414 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1415 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
1417 #define S_FW_RI_RES_WR_DCACPU 26
1418 #define M_FW_RI_RES_WR_DCACPU 0x1f
1419 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
1420 #define G_FW_RI_RES_WR_DCACPU(x) \
1421 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1423 #define S_FW_RI_RES_WR_FBMIN 23
1424 #define M_FW_RI_RES_WR_FBMIN 0x7
1425 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
1426 #define G_FW_RI_RES_WR_FBMIN(x) \
1427 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1429 #define S_FW_RI_RES_WR_FBMAX 20
1430 #define M_FW_RI_RES_WR_FBMAX 0x7
1431 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
1432 #define G_FW_RI_RES_WR_FBMAX(x) \
1433 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1435 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19
1436 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
1437 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1438 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
1439 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1440 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1442 #define S_FW_RI_RES_WR_CIDXFTHRESH 16
1443 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
1444 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1445 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
1446 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1448 #define S_FW_RI_RES_WR_EQSIZE 0
1449 #define M_FW_RI_RES_WR_EQSIZE 0xffff
1450 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
1451 #define G_FW_RI_RES_WR_EQSIZE(x) \
1452 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1454 #define S_FW_RI_RES_WR_IQANDST 15
1455 #define M_FW_RI_RES_WR_IQANDST 0x1
1456 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
1457 #define G_FW_RI_RES_WR_IQANDST(x) \
1458 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1459 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
1461 #define S_FW_RI_RES_WR_IQANUS 14
1462 #define M_FW_RI_RES_WR_IQANUS 0x1
1463 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
1464 #define G_FW_RI_RES_WR_IQANUS(x) \
1465 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1466 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
1468 #define S_FW_RI_RES_WR_IQANUD 12
1469 #define M_FW_RI_RES_WR_IQANUD 0x3
1470 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
1471 #define G_FW_RI_RES_WR_IQANUD(x) \
1472 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1474 #define S_FW_RI_RES_WR_IQANDSTINDEX 0
1475 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
1476 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1477 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
1478 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1480 #define S_FW_RI_RES_WR_IQDROPRSS 15
1481 #define M_FW_RI_RES_WR_IQDROPRSS 0x1
1482 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
1483 #define G_FW_RI_RES_WR_IQDROPRSS(x) \
1484 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1485 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
1487 #define S_FW_RI_RES_WR_IQGTSMODE 14
1488 #define M_FW_RI_RES_WR_IQGTSMODE 0x1
1489 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
1490 #define G_FW_RI_RES_WR_IQGTSMODE(x) \
1491 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1492 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
1494 #define S_FW_RI_RES_WR_IQPCIECH 12
1495 #define M_FW_RI_RES_WR_IQPCIECH 0x3
1496 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
1497 #define G_FW_RI_RES_WR_IQPCIECH(x) \
1498 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1500 #define S_FW_RI_RES_WR_IQDCAEN 11
1501 #define M_FW_RI_RES_WR_IQDCAEN 0x1
1502 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
1503 #define G_FW_RI_RES_WR_IQDCAEN(x) \
1504 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1505 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
1507 #define S_FW_RI_RES_WR_IQDCACPU 6
1508 #define M_FW_RI_RES_WR_IQDCACPU 0x1f
1509 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
1510 #define G_FW_RI_RES_WR_IQDCACPU(x) \
1511 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1513 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
1514 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
1515 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1516 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1517 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1518 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1520 #define S_FW_RI_RES_WR_IQO 3
1521 #define M_FW_RI_RES_WR_IQO 0x1
1522 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
1523 #define G_FW_RI_RES_WR_IQO(x) \
1524 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1525 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
1527 #define S_FW_RI_RES_WR_IQCPRIO 2
1528 #define M_FW_RI_RES_WR_IQCPRIO 0x1
1529 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
1530 #define G_FW_RI_RES_WR_IQCPRIO(x) \
1531 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1532 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
1534 #define S_FW_RI_RES_WR_IQESIZE 0
1535 #define M_FW_RI_RES_WR_IQESIZE 0x3
1536 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
1537 #define G_FW_RI_RES_WR_IQESIZE(x) \
1538 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1540 #define S_FW_RI_RES_WR_IQNS 31
1541 #define M_FW_RI_RES_WR_IQNS 0x1
1542 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
1543 #define G_FW_RI_RES_WR_IQNS(x) \
1544 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1545 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
1547 #define S_FW_RI_RES_WR_IQRO 30
1548 #define M_FW_RI_RES_WR_IQRO 0x1
1549 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
1550 #define G_FW_RI_RES_WR_IQRO(x) \
1551 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1552 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
1554 struct fw_ri_rdma_write_wr {
1564 #ifndef C99_NOT_SUPPORTED
1566 struct fw_ri_immd immd_src[0];
1567 struct fw_ri_isgl isgl_src[0];
1572 struct fw_ri_send_wr {
1583 #ifndef C99_NOT_SUPPORTED
1585 struct fw_ri_immd immd_src[0];
1586 struct fw_ri_isgl isgl_src[0];
1591 #define S_FW_RI_SEND_WR_SENDOP 0
1592 #define M_FW_RI_SEND_WR_SENDOP 0xf
1593 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
1594 #define G_FW_RI_SEND_WR_SENDOP(x) \
1595 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1597 struct fw_ri_rdma_read_wr {
1614 struct fw_ri_recv_wr {
1620 struct fw_ri_isgl isgl;
1623 struct fw_ri_bind_mw_wr {
1629 __u8 qpbinde_to_dcacpu;
1641 #define S_FW_RI_BIND_MW_WR_QPBINDE 6
1642 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
1643 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1644 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
1645 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1646 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1648 #define S_FW_RI_BIND_MW_WR_NS 5
1649 #define M_FW_RI_BIND_MW_WR_NS 0x1
1650 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
1651 #define G_FW_RI_BIND_MW_WR_NS(x) \
1652 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1653 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
1655 #define S_FW_RI_BIND_MW_WR_DCACPU 0
1656 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
1657 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1658 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \
1659 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1661 struct fw_ri_fr_nsmr_wr {
1667 __u8 qpbinde_to_dcacpu;
1678 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6
1679 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
1680 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1681 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
1682 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1683 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1685 #define S_FW_RI_FR_NSMR_WR_NS 5
1686 #define M_FW_RI_FR_NSMR_WR_NS 0x1
1687 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
1688 #define G_FW_RI_FR_NSMR_WR_NS(x) \
1689 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1690 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
1692 #define S_FW_RI_FR_NSMR_WR_DCACPU 0
1693 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
1694 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1695 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
1696 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1698 struct fw_ri_inv_lstag_wr {
1708 struct fw_ri_send_immediate_wr {
1714 __be32 sendimmop_pkd;
1719 #ifndef C99_NOT_SUPPORTED
1720 struct fw_ri_immd immd_src[0];
1724 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
1725 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf
1726 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1727 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1728 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1729 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1730 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1732 enum fw_ri_atomic_op {
1733 FW_RI_ATOMIC_OP_FETCHADD,
1734 FW_RI_ATOMIC_OP_SWAP,
1735 FW_RI_ATOMIC_OP_CMDSWAP,
1738 struct fw_ri_atomic_wr {
1744 __be32 atomicop_pkd;
1751 __be32 addswap_data_hi;
1752 __be32 addswap_data_lo;
1753 __be32 addswap_mask_hi;
1754 __be32 addswap_mask_lo;
1755 __be32 compare_data_hi;
1756 __be32 compare_data_lo;
1757 __be32 compare_mask_hi;
1758 __be32 compare_mask_lo;
1762 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0
1763 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf
1764 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1765 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
1766 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1768 #define S_FW_RI_ATOMIC_WR_AOPCODE 0
1769 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf
1770 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1771 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
1772 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1777 FW_RI_TYPE_TERMINATE
1780 enum fw_ri_init_p2ptype {
1781 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
1782 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
1783 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
1784 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
1785 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
1786 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
1787 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
1792 __be32 flowid_len16;
1797 __u8 mpareqbit_p2ptype;
1815 union fw_ri_init_p2p {
1816 struct fw_ri_rdma_write_wr write;
1817 struct fw_ri_rdma_read_wr read;
1818 struct fw_ri_send_wr send;
1826 struct fw_ri_terminate {
1835 #define S_FW_RI_WR_MPAREQBIT 7
1836 #define M_FW_RI_WR_MPAREQBIT 0x1
1837 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
1838 #define G_FW_RI_WR_MPAREQBIT(x) \
1839 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
1840 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
1842 #define S_FW_RI_WR_0BRRBIT 6
1843 #define M_FW_RI_WR_0BRRBIT 0x1
1844 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT)
1845 #define G_FW_RI_WR_0BRRBIT(x) \
1846 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
1847 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U)
1849 #define S_FW_RI_WR_P2PTYPE 0
1850 #define M_FW_RI_WR_P2PTYPE 0xf
1851 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
1852 #define G_FW_RI_WR_P2PTYPE(x) \
1853 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
1855 /******************************************************************************
1856 * F O i S C S I W O R K R E Q U E S T s
1857 *********************************************/
1859 #define FW_FOISCSI_NAME_MAX_LEN 224
1860 #define FW_FOISCSI_ALIAS_MAX_LEN 224
1861 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128
1862 #define FW_FOISCSI_INIT_NODE_MAX 8
1864 enum fw_chnet_ifconf_wr_subop {
1865 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
1867 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
1868 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
1870 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
1871 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
1873 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
1874 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
1876 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
1877 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
1879 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
1880 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
1882 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
1883 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
1885 FW_CHNET_IFCONF_WR_SUBOP_MAX,
1888 struct fw_chnet_ifconf_wr {
1890 __be32 flowid_len16;
1898 struct fw_chnet_ifconf_params {
1902 union fw_chnet_ifconf_addr_type {
1903 struct fw_chnet_ifconf_ipv4 {
1910 struct fw_chnet_ifconf_ipv6 {
1911 __be64 linklocal_lo;
1912 __be64 linklocal_hi;
1917 __be64 linklocal_aconf_hi;
1918 __be64 linklocal_aconf_lo;
1919 __be64 router_aconf_hi;
1920 __be64 router_aconf_lo;
1927 enum fw_foiscsi_node_type {
1928 FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
1929 FW_FOISCSI_NODE_TYPE_TARGET,
1932 enum fw_foiscsi_session_type {
1933 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
1934 FW_FOISCSI_SESSION_TYPE_NORMAL,
1937 enum fw_foiscsi_auth_policy {
1938 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
1939 FW_FOISCSI_AUTH_POLICY_MUTUAL,
1942 enum fw_foiscsi_auth_method {
1943 FW_FOISCSI_AUTH_METHOD_NONE = 0,
1944 FW_FOISCSI_AUTH_METHOD_CHAP,
1945 FW_FOISCSI_AUTH_METHOD_CHAP_FST,
1946 FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
1949 enum fw_foiscsi_digest_type {
1950 FW_FOISCSI_DIGEST_TYPE_NONE = 0,
1951 FW_FOISCSI_DIGEST_TYPE_CRC32,
1952 FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
1953 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
1956 enum fw_foiscsi_wr_subop {
1957 FW_FOISCSI_WR_SUBOP_ADD = 1,
1958 FW_FOISCSI_WR_SUBOP_DEL = 2,
1959 FW_FOISCSI_WR_SUBOP_MOD = 4,
1962 enum fw_foiscsi_ctrl_state {
1963 FW_FOISCSI_CTRL_STATE_FREE = 0,
1964 FW_FOISCSI_CTRL_STATE_ONLINE = 1,
1965 FW_FOISCSI_CTRL_STATE_FAILED,
1966 FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
1967 FW_FOISCSI_CTRL_STATE_REDIRECT,
1971 __be32 op_to_immdlen;
1972 __be32 alloc_to_len16;
1978 __be32 flags_to_assoc_flowid;
1980 struct fcoe_rdev_entry {
1989 __u8 rd_xfer_rdy_to_rport_type;
1991 __u8 org_proc_assoc_to_acc_rsp_code;
1992 __u8 enh_disc_to_tgt;
1999 struct iscsi_rdev_entry {
2010 __be16 first_brst_len;
2011 __be16 max_brst_len;
2013 __be16 def_time2wait;
2014 __be16 def_time2ret;
2015 __be16 nop_out_intrvl;
2027 #define S_FW_RDEV_WR_IMMDLEN 0
2028 #define M_FW_RDEV_WR_IMMDLEN 0xff
2029 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)
2030 #define G_FW_RDEV_WR_IMMDLEN(x) \
2031 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2033 #define S_FW_RDEV_WR_ALLOC 31
2034 #define M_FW_RDEV_WR_ALLOC 0x1
2035 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC)
2036 #define G_FW_RDEV_WR_ALLOC(x) \
2037 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2038 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U)
2040 #define S_FW_RDEV_WR_FREE 30
2041 #define M_FW_RDEV_WR_FREE 0x1
2042 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE)
2043 #define G_FW_RDEV_WR_FREE(x) \
2044 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2045 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U)
2047 #define S_FW_RDEV_WR_MODIFY 29
2048 #define M_FW_RDEV_WR_MODIFY 0x1
2049 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY)
2050 #define G_FW_RDEV_WR_MODIFY(x) \
2051 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2052 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U)
2054 #define S_FW_RDEV_WR_FLOWID 8
2055 #define M_FW_RDEV_WR_FLOWID 0xfffff
2056 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID)
2057 #define G_FW_RDEV_WR_FLOWID(x) \
2058 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2060 #define S_FW_RDEV_WR_LEN16 0
2061 #define M_FW_RDEV_WR_LEN16 0xff
2062 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16)
2063 #define G_FW_RDEV_WR_LEN16(x) \
2064 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2066 #define S_FW_RDEV_WR_FLAGS 24
2067 #define M_FW_RDEV_WR_FLAGS 0xff
2068 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS)
2069 #define G_FW_RDEV_WR_FLAGS(x) \
2070 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2072 #define S_FW_RDEV_WR_GET_NEXT 20
2073 #define M_FW_RDEV_WR_GET_NEXT 0xf
2074 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT)
2075 #define G_FW_RDEV_WR_GET_NEXT(x) \
2076 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2078 #define S_FW_RDEV_WR_ASSOC_FLOWID 0
2079 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff
2080 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2081 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
2082 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2084 #define S_FW_RDEV_WR_RJT 7
2085 #define M_FW_RDEV_WR_RJT 0x1
2086 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT)
2087 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2088 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U)
2090 #define S_FW_RDEV_WR_REASON 0
2091 #define M_FW_RDEV_WR_REASON 0x7f
2092 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON)
2093 #define G_FW_RDEV_WR_REASON(x) \
2094 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2096 #define S_FW_RDEV_WR_RD_XFER_RDY 7
2097 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1
2098 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2099 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \
2100 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2101 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U)
2103 #define S_FW_RDEV_WR_WR_XFER_RDY 6
2104 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1
2105 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2106 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \
2107 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2108 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U)
2110 #define S_FW_RDEV_WR_FC_SP 5
2111 #define M_FW_RDEV_WR_FC_SP 0x1
2112 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP)
2113 #define G_FW_RDEV_WR_FC_SP(x) \
2114 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2115 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U)
2117 #define S_FW_RDEV_WR_RPORT_TYPE 0
2118 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f
2119 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE)
2120 #define G_FW_RDEV_WR_RPORT_TYPE(x) \
2121 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2123 #define S_FW_RDEV_WR_VFT 7
2124 #define M_FW_RDEV_WR_VFT 0x1
2125 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT)
2126 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2127 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U)
2129 #define S_FW_RDEV_WR_NPIV 6
2130 #define M_FW_RDEV_WR_NPIV 0x1
2131 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV)
2132 #define G_FW_RDEV_WR_NPIV(x) \
2133 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2134 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U)
2136 #define S_FW_RDEV_WR_CLASS 4
2137 #define M_FW_RDEV_WR_CLASS 0x3
2138 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS)
2139 #define G_FW_RDEV_WR_CLASS(x) \
2140 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2142 #define S_FW_RDEV_WR_SEQ_DEL 3
2143 #define M_FW_RDEV_WR_SEQ_DEL 0x1
2144 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)
2145 #define G_FW_RDEV_WR_SEQ_DEL(x) \
2146 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2147 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U)
2149 #define S_FW_RDEV_WR_PRIO_PREEMP 2
2150 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1
2151 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2152 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \
2153 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2154 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U)
2156 #define S_FW_RDEV_WR_PREF 1
2157 #define M_FW_RDEV_WR_PREF 0x1
2158 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF)
2159 #define G_FW_RDEV_WR_PREF(x) \
2160 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2161 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U)
2163 #define S_FW_RDEV_WR_QOS 0
2164 #define M_FW_RDEV_WR_QOS 0x1
2165 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS)
2166 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2167 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U)
2169 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7
2170 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1
2171 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2172 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
2173 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2174 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2176 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6
2177 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1
2178 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2179 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
2180 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2181 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2183 #define S_FW_RDEV_WR_IMAGE_PAIR 5
2184 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1
2185 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2186 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \
2187 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2188 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)
2190 #define S_FW_RDEV_WR_ACC_RSP_CODE 0
2191 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f
2192 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2193 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
2194 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2196 #define S_FW_RDEV_WR_ENH_DISC 7
2197 #define M_FW_RDEV_WR_ENH_DISC 0x1
2198 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC)
2199 #define G_FW_RDEV_WR_ENH_DISC(x) \
2200 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2201 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U)
2203 #define S_FW_RDEV_WR_REC 6
2204 #define M_FW_RDEV_WR_REC 0x1
2205 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC)
2206 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2207 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U)
2209 #define S_FW_RDEV_WR_TASK_RETRY_ID 5
2210 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1
2211 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2212 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
2213 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2214 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2216 #define S_FW_RDEV_WR_RETRY 4
2217 #define M_FW_RDEV_WR_RETRY 0x1
2218 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY)
2219 #define G_FW_RDEV_WR_RETRY(x) \
2220 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2221 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U)
2223 #define S_FW_RDEV_WR_CONF_CMPL 3
2224 #define M_FW_RDEV_WR_CONF_CMPL 0x1
2225 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL)
2226 #define G_FW_RDEV_WR_CONF_CMPL(x) \
2227 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2228 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U)
2230 #define S_FW_RDEV_WR_DATA_OVLY 2
2231 #define M_FW_RDEV_WR_DATA_OVLY 0x1
2232 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY)
2233 #define G_FW_RDEV_WR_DATA_OVLY(x) \
2234 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2235 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U)
2237 #define S_FW_RDEV_WR_INI 1
2238 #define M_FW_RDEV_WR_INI 0x1
2239 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI)
2240 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2241 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U)
2243 #define S_FW_RDEV_WR_TGT 0
2244 #define M_FW_RDEV_WR_TGT 0x1
2245 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT)
2246 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2247 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U)
2249 struct fw_foiscsi_node_wr {
2250 __be32 op_to_immdlen;
2251 __be32 flowid_len16;
2260 __be16 retry_timeout;
2266 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
2267 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff
2268 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2269 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
2270 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2272 struct fw_foiscsi_ctrl_wr {
2274 __be32 flowid_len16;
2283 struct fw_foiscsi_sess_attr {
2284 __be32 sess_type_to_erl;
2293 struct fw_foiscsi_conn_attr {
2294 __be32 hdigest_to_ddp_pgsz;
2299 union fw_foiscsi_conn_attr_addr {
2300 struct fw_foiscsi_conn_attr_ipv6 {
2304 struct fw_foiscsi_conn_attr_ipv4 {
2312 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2315 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30
2316 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3
2317 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2318 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2319 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2320 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2322 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29
2323 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1
2324 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2325 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2326 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2327 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2328 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2329 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
2330 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2332 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28
2333 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1
2334 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2335 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2336 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2337 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2338 M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2339 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
2340 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2342 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27
2343 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1
2344 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2345 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2346 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2347 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2348 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2349 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
2350 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2352 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26
2353 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1
2354 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2355 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2356 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2357 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2358 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2359 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
2360 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2362 #define S_FW_FOISCSI_CTRL_WR_ERL 24
2363 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3
2364 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2365 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \
2366 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2368 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30
2369 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3
2370 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2371 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
2372 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2374 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28
2375 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3
2376 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2377 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
2378 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2380 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25
2381 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7
2382 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2383 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2384 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2385 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2386 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2388 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23
2389 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3
2390 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2391 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2392 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2393 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2394 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2396 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21
2397 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3
2398 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2399 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2400 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2401 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2403 struct fw_foiscsi_chap_wr {
2405 __be32 flowid_len16;
2413 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN];
2414 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2417 /******************************************************************************
2418 * F O F C O E W O R K R E Q U E S T s
2419 *******************************************/
2421 struct fw_fcoe_els_ct_wr {
2423 __be32 flowid_len16;
2440 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24
2441 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff
2442 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2443 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
2444 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2446 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
2447 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff
2448 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2449 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
2450 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2452 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8
2453 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff
2454 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2455 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
2456 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2458 #define S_FW_FCOE_ELS_CT_WR_LEN16 0
2459 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff
2460 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2461 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
2462 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2464 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6
2465 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3
2466 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2467 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
2468 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2470 #define S_FW_FCOE_ELS_CT_WR_CLASS 4
2471 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3
2472 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2473 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
2474 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2476 #define S_FW_FCOE_ELS_CT_WR_FL 2
2477 #define M_FW_FCOE_ELS_CT_WR_FL 0x1
2478 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL)
2479 #define G_FW_FCOE_ELS_CT_WR_FL(x) \
2480 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2481 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U)
2483 #define S_FW_FCOE_ELS_CT_WR_NPIV 1
2484 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1
2485 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2486 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
2487 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2488 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2490 #define S_FW_FCOE_ELS_CT_WR_SP 0
2491 #define M_FW_FCOE_ELS_CT_WR_SP 0x1
2492 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP)
2493 #define G_FW_FCOE_ELS_CT_WR_SP(x) \
2494 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2495 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U)
2497 /******************************************************************************
2498 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path)
2499 *****************************************************************************/
2501 struct fw_scsi_write_wr {
2503 __be32 flowid_len16;
2508 union fw_scsi_write_priv {
2509 struct fcoe_write_priv {
2514 struct iscsi_write_priv {
2519 __be32 ini_xfer_cnt;
2525 #define S_FW_SCSI_WRITE_WR_OPCODE 24
2526 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff
2527 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2528 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \
2529 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2531 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0
2532 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff
2533 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2534 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
2535 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2537 #define S_FW_SCSI_WRITE_WR_FLOWID 8
2538 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff
2539 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2540 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \
2541 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2543 #define S_FW_SCSI_WRITE_WR_LEN16 0
2544 #define M_FW_SCSI_WRITE_WR_LEN16 0xff
2545 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16)
2546 #define G_FW_SCSI_WRITE_WR_LEN16(x) \
2547 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2549 #define S_FW_SCSI_WRITE_WR_CP_EN 6
2550 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3
2551 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2552 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \
2553 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2555 #define S_FW_SCSI_WRITE_WR_CLASS 4
2556 #define M_FW_SCSI_WRITE_WR_CLASS 0x3
2557 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS)
2558 #define G_FW_SCSI_WRITE_WR_CLASS(x) \
2559 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2561 struct fw_scsi_read_wr {
2563 __be32 flowid_len16;
2568 union fw_scsi_read_priv {
2569 struct fcoe_read_priv {
2574 struct iscsi_read_priv {
2579 __be32 ini_xfer_cnt;
2585 #define S_FW_SCSI_READ_WR_OPCODE 24
2586 #define M_FW_SCSI_READ_WR_OPCODE 0xff
2587 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE)
2588 #define G_FW_SCSI_READ_WR_OPCODE(x) \
2589 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2591 #define S_FW_SCSI_READ_WR_IMMDLEN 0
2592 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff
2593 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2594 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \
2595 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2597 #define S_FW_SCSI_READ_WR_FLOWID 8
2598 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff
2599 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID)
2600 #define G_FW_SCSI_READ_WR_FLOWID(x) \
2601 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2603 #define S_FW_SCSI_READ_WR_LEN16 0
2604 #define M_FW_SCSI_READ_WR_LEN16 0xff
2605 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16)
2606 #define G_FW_SCSI_READ_WR_LEN16(x) \
2607 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2609 #define S_FW_SCSI_READ_WR_CP_EN 6
2610 #define M_FW_SCSI_READ_WR_CP_EN 0x3
2611 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN)
2612 #define G_FW_SCSI_READ_WR_CP_EN(x) \
2613 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
2615 #define S_FW_SCSI_READ_WR_CLASS 4
2616 #define M_FW_SCSI_READ_WR_CLASS 0x3
2617 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS)
2618 #define G_FW_SCSI_READ_WR_CLASS(x) \
2619 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
2621 struct fw_scsi_cmd_wr {
2623 __be32 flowid_len16;
2628 union fw_scsi_cmd_priv {
2629 struct fcoe_cmd_priv {
2634 struct iscsi_cmd_priv {
2644 #define S_FW_SCSI_CMD_WR_OPCODE 24
2645 #define M_FW_SCSI_CMD_WR_OPCODE 0xff
2646 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE)
2647 #define G_FW_SCSI_CMD_WR_OPCODE(x) \
2648 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
2650 #define S_FW_SCSI_CMD_WR_IMMDLEN 0
2651 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff
2652 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
2653 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
2654 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
2656 #define S_FW_SCSI_CMD_WR_FLOWID 8
2657 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff
2658 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID)
2659 #define G_FW_SCSI_CMD_WR_FLOWID(x) \
2660 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
2662 #define S_FW_SCSI_CMD_WR_LEN16 0
2663 #define M_FW_SCSI_CMD_WR_LEN16 0xff
2664 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16)
2665 #define G_FW_SCSI_CMD_WR_LEN16(x) \
2666 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
2668 #define S_FW_SCSI_CMD_WR_CP_EN 6
2669 #define M_FW_SCSI_CMD_WR_CP_EN 0x3
2670 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN)
2671 #define G_FW_SCSI_CMD_WR_CP_EN(x) \
2672 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
2674 #define S_FW_SCSI_CMD_WR_CLASS 4
2675 #define M_FW_SCSI_CMD_WR_CLASS 0x3
2676 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS)
2677 #define G_FW_SCSI_CMD_WR_CLASS(x) \
2678 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
2680 struct fw_scsi_abrt_cls_wr {
2682 __be32 flowid_len16;
2686 __u8 sub_opcode_to_chk_all_io;
2691 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24
2692 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff
2693 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
2694 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
2695 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
2697 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
2698 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff
2699 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
2700 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2701 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
2702 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2704 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8
2705 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff
2706 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
2707 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
2708 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
2710 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
2711 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff
2712 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
2713 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
2714 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
2716 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2
2717 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f
2718 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
2719 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2720 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
2721 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
2722 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2724 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1
2725 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1
2726 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
2727 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
2728 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
2729 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
2731 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
2732 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1
2733 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
2734 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2735 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
2736 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
2737 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2738 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
2739 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
2741 struct fw_scsi_tgt_acc_wr {
2743 __be32 flowid_len16;
2748 union fw_scsi_tgt_acc_priv {
2749 struct fcoe_tgt_acc_priv {
2754 struct iscsi_tgt_acc_priv {
2762 __be32 tot_xfer_len;
2765 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24
2766 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff
2767 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
2768 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
2769 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
2771 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
2772 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff
2773 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2774 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
2775 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2777 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8
2778 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff
2779 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
2780 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
2781 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
2783 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0
2784 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff
2785 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
2786 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
2787 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
2789 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6
2790 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3
2791 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
2792 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
2793 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
2795 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4
2796 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3
2797 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
2798 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
2799 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
2801 struct fw_scsi_tgt_xmit_wr {
2803 __be32 flowid_len16;
2808 union fw_scsi_tgt_xmit_priv {
2809 struct fcoe_tgt_xmit_priv {
2814 struct iscsi_tgt_xmit_priv {
2822 __be32 tot_xfer_len;
2825 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24
2826 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff
2827 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
2828 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
2829 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
2831 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
2832 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff
2833 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
2834 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2835 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
2836 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2838 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8
2839 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff
2840 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
2841 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
2842 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
2844 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
2845 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff
2846 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
2847 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
2848 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
2850 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6
2851 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3
2852 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
2853 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
2854 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
2856 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4
2857 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3
2858 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
2859 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
2860 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
2862 struct fw_scsi_tgt_rsp_wr {
2864 __be32 flowid_len16;
2868 union fw_scsi_tgt_rsp_priv {
2869 struct fcoe_tgt_rsp_priv {
2874 struct iscsi_tgt_rsp_priv {
2881 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24
2882 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff
2883 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
2884 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
2885 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
2887 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
2888 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff
2889 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2890 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
2891 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2893 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8
2894 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff
2895 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
2896 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
2897 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
2899 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0
2900 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff
2901 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
2902 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
2903 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
2905 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6
2906 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3
2907 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
2908 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
2909 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
2911 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4
2912 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3
2913 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
2914 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
2915 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
2917 struct fw_pofcoe_tcb_wr {
2919 __be32 equiq_to_len16;
2933 #define S_FW_POFCOE_TCB_WR_TID 12
2934 #define M_FW_POFCOE_TCB_WR_TID 0xfffff
2935 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID)
2936 #define G_FW_POFCOE_TCB_WR_TID(x) \
2937 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
2939 #define S_FW_POFCOE_TCB_WR_ALLOC 4
2940 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1
2941 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC)
2942 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \
2943 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
2944 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U)
2946 #define S_FW_POFCOE_TCB_WR_FREE 3
2947 #define M_FW_POFCOE_TCB_WR_FREE 0x1
2948 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE)
2949 #define G_FW_POFCOE_TCB_WR_FREE(x) \
2950 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
2951 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)
2953 #define S_FW_POFCOE_TCB_WR_PORT 0
2954 #define M_FW_POFCOE_TCB_WR_PORT 0x7
2955 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT)
2956 #define G_FW_POFCOE_TCB_WR_PORT(x) \
2957 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
2959 struct fw_pofcoe_ulptx_wr {
2961 __be32 equiq_to_len16;
2966 /******************************************************************************
2968 *********************/
2971 * The maximum length of time, in miliseconds, that we expect any firmware
2972 * command to take to execute and return a reply to the host. The RESET
2973 * and INITIALIZE commands can take a fair amount of time to execute but
2974 * most execute in far less time than this maximum. This constant is used
2975 * by host software to determine how long to wait for a firmware command
2976 * reply before declaring the firmware as dead/unreachable ...
2978 #define FW_CMD_MAX_TIMEOUT 10000
2981 * If a host driver does a HELLO and discovers that there's already a MASTER
2982 * selected, we may have to wait for that MASTER to finish issuing RESET,
2983 * configuration and INITIALIZE commands. Also, there's a possibility that
2984 * our own HELLO may get lost if it happens right as the MASTER is issuign a
2985 * RESET command, so we need to be willing to make a few retries of our HELLO.
2987 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
2988 #define FW_CMD_HELLO_RETRIES 3
2990 enum fw_cmd_opcodes {
2992 FW_RESET_CMD = 0x03,
2993 FW_HELLO_CMD = 0x04,
2995 FW_INITIALIZE_CMD = 0x06,
2996 FW_CAPS_CONFIG_CMD = 0x07,
2997 FW_PARAMS_CMD = 0x08,
3000 FW_EQ_MNGT_CMD = 0x11,
3001 FW_EQ_ETH_CMD = 0x12,
3002 FW_EQ_CTRL_CMD = 0x13,
3003 FW_EQ_OFLD_CMD = 0x21,
3005 FW_VI_MAC_CMD = 0x15,
3006 FW_VI_RXMODE_CMD = 0x16,
3007 FW_VI_ENABLE_CMD = 0x17,
3008 FW_VI_STATS_CMD = 0x1a,
3009 FW_ACL_MAC_CMD = 0x18,
3010 FW_ACL_VLAN_CMD = 0x19,
3012 FW_PORT_STATS_CMD = 0x1c,
3013 FW_PORT_LB_STATS_CMD = 0x1d,
3014 FW_PORT_TRACE_CMD = 0x1e,
3015 FW_PORT_TRACE_MMAP_CMD = 0x1f,
3016 FW_RSS_IND_TBL_CMD = 0x20,
3017 FW_RSS_GLB_CONFIG_CMD = 0x22,
3018 FW_RSS_VI_CONFIG_CMD = 0x23,
3019 FW_SCHED_CMD = 0x24,
3020 FW_DEVLOG_CMD = 0x25,
3021 FW_WATCHDOG_CMD = 0x27,
3023 FW_CHNET_IFACE_CMD = 0x26,
3024 FW_FCOE_RES_INFO_CMD = 0x31,
3025 FW_FCOE_LINK_CMD = 0x32,
3026 FW_FCOE_VNP_CMD = 0x33,
3027 FW_FCOE_SPARAMS_CMD = 0x35,
3028 FW_FCOE_STATS_CMD = 0x37,
3029 FW_FCOE_FCF_CMD = 0x38,
3030 FW_LASTC2E_CMD = 0x40,
3031 FW_ERROR_CMD = 0x80,
3032 FW_DEBUG_CMD = 0x81,
3036 FW_CMD_CAP_PF = 0x01,
3037 FW_CMD_CAP_DMAQ = 0x02,
3038 FW_CMD_CAP_PORT = 0x04,
3039 FW_CMD_CAP_PORTPROMISC = 0x08,
3040 FW_CMD_CAP_PORTSTATS = 0x10,
3041 FW_CMD_CAP_VF = 0x80,
3045 * Generic command header flit0
3052 #define S_FW_CMD_OP 24
3053 #define M_FW_CMD_OP 0xff
3054 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
3055 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
3057 #define S_FW_CMD_REQUEST 23
3058 #define M_FW_CMD_REQUEST 0x1
3059 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
3060 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
3061 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
3063 #define S_FW_CMD_READ 22
3064 #define M_FW_CMD_READ 0x1
3065 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
3066 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
3067 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
3069 #define S_FW_CMD_WRITE 21
3070 #define M_FW_CMD_WRITE 0x1
3071 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
3072 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
3073 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
3075 #define S_FW_CMD_EXEC 20
3076 #define M_FW_CMD_EXEC 0x1
3077 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
3078 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
3079 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
3081 #define S_FW_CMD_RAMASK 20
3082 #define M_FW_CMD_RAMASK 0xf
3083 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK)
3084 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
3086 #define S_FW_CMD_RETVAL 8
3087 #define M_FW_CMD_RETVAL 0xff
3088 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
3089 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
3091 #define S_FW_CMD_LEN16 0
3092 #define M_FW_CMD_LEN16 0xff
3093 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
3094 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
3096 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
3101 enum fw_ldst_addrspc {
3102 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
3103 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
3104 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
3105 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
3106 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
3107 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
3108 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
3109 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
3110 FW_LDST_ADDRSPC_MDIO = 0x0018,
3111 FW_LDST_ADDRSPC_MPS = 0x0020,
3112 FW_LDST_ADDRSPC_FUNC = 0x0028,
3113 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
3114 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */
3115 FW_LDST_ADDRSPC_LE = 0x0030,
3116 FW_LDST_ADDRSPC_I2C = 0x0038,
3117 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
3118 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041,
3119 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042,
3123 * MDIO VSC8634 register access control field
3125 enum fw_ldst_mdio_vsc8634_aid {
3126 FW_LDST_MDIO_VS_STANDARD,
3127 FW_LDST_MDIO_VS_EXTENDED,
3128 FW_LDST_MDIO_VS_GPIO
3131 enum fw_ldst_mps_fid {
3136 enum fw_ldst_func_access_ctl {
3137 FW_LDST_FUNC_ACC_CTL_VIID,
3138 FW_LDST_FUNC_ACC_CTL_FID
3141 enum fw_ldst_func_mod_index {
3145 struct fw_ldst_cmd {
3146 __be32 op_to_addrspace;
3147 __be32 cycles_to_len16;
3149 struct fw_ldst_addrval {
3153 struct fw_ldst_idctxt {
3155 __be32 msg_ctxtflush;
3165 struct fw_ldst_mdio {
3171 struct fw_ldst_mps {
3181 struct fw_ldst_func {
3189 struct fw_ldst_pcie {
3194 __u8 select_naccess;
3199 struct fw_ldst_i2c_deprecated {
3206 struct fw_ldst_i2c {
3223 #define S_FW_LDST_CMD_ADDRSPACE 0
3224 #define M_FW_LDST_CMD_ADDRSPACE 0xff
3225 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
3226 #define G_FW_LDST_CMD_ADDRSPACE(x) \
3227 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
3229 #define S_FW_LDST_CMD_CYCLES 16
3230 #define M_FW_LDST_CMD_CYCLES 0xffff
3231 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES)
3232 #define G_FW_LDST_CMD_CYCLES(x) \
3233 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
3235 #define S_FW_LDST_CMD_MSG 31
3236 #define M_FW_LDST_CMD_MSG 0x1
3237 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG)
3238 #define G_FW_LDST_CMD_MSG(x) \
3239 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
3240 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U)
3242 #define S_FW_LDST_CMD_CTXTFLUSH 30
3243 #define M_FW_LDST_CMD_CTXTFLUSH 0x1
3244 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH)
3245 #define G_FW_LDST_CMD_CTXTFLUSH(x) \
3246 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
3247 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U)
3249 #define S_FW_LDST_CMD_PADDR 8
3250 #define M_FW_LDST_CMD_PADDR 0x1f
3251 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR)
3252 #define G_FW_LDST_CMD_PADDR(x) \
3253 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
3255 #define S_FW_LDST_CMD_MMD 0
3256 #define M_FW_LDST_CMD_MMD 0x1f
3257 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD)
3258 #define G_FW_LDST_CMD_MMD(x) \
3259 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
3261 #define S_FW_LDST_CMD_FID 15
3262 #define M_FW_LDST_CMD_FID 0x1
3263 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID)
3264 #define G_FW_LDST_CMD_FID(x) \
3265 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
3266 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U)
3268 #define S_FW_LDST_CMD_CTL 0
3269 #define M_FW_LDST_CMD_CTL 0x7fff
3270 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL)
3271 #define G_FW_LDST_CMD_CTL(x) \
3272 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL)
3274 #define S_FW_LDST_CMD_RPLCPF 0
3275 #define M_FW_LDST_CMD_RPLCPF 0xff
3276 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF)
3277 #define G_FW_LDST_CMD_RPLCPF(x) \
3278 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
3280 #define S_FW_LDST_CMD_CTRL 7
3281 #define M_FW_LDST_CMD_CTRL 0x1
3282 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL)
3283 #define G_FW_LDST_CMD_CTRL(x) \
3284 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
3285 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U)
3287 #define S_FW_LDST_CMD_LC 4
3288 #define M_FW_LDST_CMD_LC 0x1
3289 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC)
3290 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
3291 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U)
3293 #define S_FW_LDST_CMD_AI 3
3294 #define M_FW_LDST_CMD_AI 0x1
3295 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI)
3296 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
3297 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U)
3299 #define S_FW_LDST_CMD_FN 0
3300 #define M_FW_LDST_CMD_FN 0x7
3301 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN)
3302 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
3304 #define S_FW_LDST_CMD_SELECT 4
3305 #define M_FW_LDST_CMD_SELECT 0xf
3306 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT)
3307 #define G_FW_LDST_CMD_SELECT(x) \
3308 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
3310 #define S_FW_LDST_CMD_NACCESS 0
3311 #define M_FW_LDST_CMD_NACCESS 0xf
3312 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS)
3313 #define G_FW_LDST_CMD_NACCESS(x) \
3314 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
3316 #define S_FW_LDST_CMD_NSET 14
3317 #define M_FW_LDST_CMD_NSET 0x3
3318 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET)
3319 #define G_FW_LDST_CMD_NSET(x) \
3320 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
3322 #define S_FW_LDST_CMD_PID 6
3323 #define M_FW_LDST_CMD_PID 0x3
3324 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID)
3325 #define G_FW_LDST_CMD_PID(x) \
3326 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
3328 struct fw_reset_cmd {
3330 __be32 retval_len16;
3335 #define S_FW_RESET_CMD_HALT 31
3336 #define M_FW_RESET_CMD_HALT 0x1
3337 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
3338 #define G_FW_RESET_CMD_HALT(x) \
3339 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
3340 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
3343 FW_HELLO_CMD_STAGE_OS = 0,
3344 FW_HELLO_CMD_STAGE_PREOS0 = 1,
3345 FW_HELLO_CMD_STAGE_PREOS1 = 2,
3346 FW_HELLO_CMD_STAGE_POSTOS = 3,
3349 struct fw_hello_cmd {
3351 __be32 retval_len16;
3352 __be32 err_to_clearinit;
3356 #define S_FW_HELLO_CMD_ERR 31
3357 #define M_FW_HELLO_CMD_ERR 0x1
3358 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
3359 #define G_FW_HELLO_CMD_ERR(x) \
3360 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
3361 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
3363 #define S_FW_HELLO_CMD_INIT 30
3364 #define M_FW_HELLO_CMD_INIT 0x1
3365 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
3366 #define G_FW_HELLO_CMD_INIT(x) \
3367 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
3368 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
3370 #define S_FW_HELLO_CMD_MASTERDIS 29
3371 #define M_FW_HELLO_CMD_MASTERDIS 0x1
3372 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
3373 #define G_FW_HELLO_CMD_MASTERDIS(x) \
3374 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
3375 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
3377 #define S_FW_HELLO_CMD_MASTERFORCE 28
3378 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
3379 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
3380 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
3381 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
3382 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
3384 #define S_FW_HELLO_CMD_MBMASTER 24
3385 #define M_FW_HELLO_CMD_MBMASTER 0xf
3386 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
3387 #define G_FW_HELLO_CMD_MBMASTER(x) \
3388 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
3390 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23
3391 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1
3392 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
3393 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
3394 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
3395 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
3397 #define S_FW_HELLO_CMD_MBASYNCNOT 20
3398 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
3399 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
3400 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
3401 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
3403 #define S_FW_HELLO_CMD_STAGE 17
3404 #define M_FW_HELLO_CMD_STAGE 0x7
3405 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
3406 #define G_FW_HELLO_CMD_STAGE(x) \
3407 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
3409 #define S_FW_HELLO_CMD_CLEARINIT 16
3410 #define M_FW_HELLO_CMD_CLEARINIT 0x1
3411 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
3412 #define G_FW_HELLO_CMD_CLEARINIT(x) \
3413 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
3414 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
3418 __be32 retval_len16;
3422 struct fw_initialize_cmd {
3424 __be32 retval_len16;
3428 enum fw_caps_config_hm {
3429 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
3430 FW_CAPS_CONFIG_HM_PL = 0x00000002,
3431 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
3432 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
3433 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
3434 FW_CAPS_CONFIG_HM_TP = 0x00000020,
3435 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
3436 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
3437 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
3438 FW_CAPS_CONFIG_HM_MC = 0x00000200,
3439 FW_CAPS_CONFIG_HM_LE = 0x00000400,
3440 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
3441 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
3442 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
3443 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
3444 FW_CAPS_CONFIG_HM_MI = 0x00008000,
3445 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
3446 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
3447 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
3448 FW_CAPS_CONFIG_HM_MA = 0x00080000,
3449 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
3450 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
3451 FW_CAPS_CONFIG_HM_UART = 0x00400000,
3452 FW_CAPS_CONFIG_HM_SF = 0x00800000,
3456 * The VF Register Map.
3458 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
3459 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
3460 * the Slice to Module Map Table (see below) in the Physical Function Register
3461 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
3462 * and Offset registers in the PF Register Map. The MBDATA base address is
3463 * quite constrained as it determines the Mailbox Data addresses for both PFs
3464 * and VFs, and therefore must fit in both the VF and PF Register Maps without
3465 * overlapping other registers.
3467 #define FW_T4VF_SGE_BASE_ADDR 0x0000
3468 #define FW_T4VF_MPS_BASE_ADDR 0x0100
3469 #define FW_T4VF_PL_BASE_ADDR 0x0200
3470 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
3471 #define FW_T4VF_CIM_BASE_ADDR 0x0300
3473 #define FW_T4VF_REGMAP_START 0x0000
3474 #define FW_T4VF_REGMAP_SIZE 0x0400
3476 enum fw_caps_config_nbm {
3477 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
3478 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
3481 enum fw_caps_config_link {
3482 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
3483 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
3484 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
3487 enum fw_caps_config_switch {
3488 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
3489 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
3492 enum fw_caps_config_nic {
3493 FW_CAPS_CONFIG_NIC = 0x00000001,
3494 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
3495 FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
3496 FW_CAPS_CONFIG_NIC_UM = 0x00000008,
3497 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
3498 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
3499 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
3502 enum fw_caps_config_toe {
3503 FW_CAPS_CONFIG_TOE = 0x00000001,
3506 enum fw_caps_config_rdma {
3507 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
3508 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
3511 enum fw_caps_config_iscsi {
3512 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
3513 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
3514 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
3515 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
3516 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
3517 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
3520 enum fw_caps_config_fcoe {
3521 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
3522 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
3523 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
3524 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
3525 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
3528 struct fw_caps_config_cmd {
3530 __be32 cfvalid_to_len16;
3548 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
3549 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
3550 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
3551 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
3552 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
3553 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
3555 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
3556 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
3557 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
3558 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
3559 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
3560 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
3561 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
3563 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
3564 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
3565 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
3566 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
3567 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
3568 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
3569 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
3572 * params command mnemonics
3574 enum fw_params_mnem {
3575 FW_PARAMS_MNEM_DEV = 1, /* device params */
3576 FW_PARAMS_MNEM_PFVF = 2, /* function params */
3577 FW_PARAMS_MNEM_REG = 3, /* limited register access */
3578 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
3585 enum fw_params_param_dev {
3586 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
3587 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
3588 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
3589 * allocated by the device's
3592 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
3593 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,
3594 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
3595 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
3596 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07,
3597 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
3598 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
3599 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
3600 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
3601 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
3602 FW_PARAMS_PARAM_DEV_CF = 0x0D,
3603 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
3604 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
3605 FW_PARAMS_PARAM_DEV_LOAD = 0x10,
3606 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
3607 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
3608 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
3610 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
3612 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
3613 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
3614 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
3618 * physical and virtual function parameters
3620 enum fw_params_param_pfvf {
3621 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
3622 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
3623 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
3624 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
3625 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
3626 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
3627 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
3628 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
3629 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
3630 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
3631 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
3632 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
3633 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
3634 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
3635 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
3636 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
3637 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
3638 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
3639 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
3640 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
3641 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
3642 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
3643 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
3644 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
3645 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
3646 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
3647 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
3648 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
3649 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
3650 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
3651 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
3652 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
3653 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
3654 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
3655 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
3656 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
3657 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
3658 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
3659 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
3660 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
3664 * dma queue parameters
3666 enum fw_params_param_dmaq {
3667 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
3668 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
3669 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
3670 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
3671 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
3672 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
3673 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
3674 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
3678 * dev bypass parameters; actions and modes
3680 enum fw_params_param_dev_bypass {
3684 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
3685 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
3689 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
3690 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
3691 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
3694 enum fw_params_phyfw_actions {
3695 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00,
3696 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01,
3699 enum fw_params_param_dev_diag {
3700 FW_PARAM_DEV_DIAG_TMP = 0x00,
3701 FW_PARAM_DEV_DIAG_VDD = 0x01,
3704 #define S_FW_PARAMS_MNEM 24
3705 #define M_FW_PARAMS_MNEM 0xff
3706 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
3707 #define G_FW_PARAMS_MNEM(x) \
3708 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
3710 #define S_FW_PARAMS_PARAM_X 16
3711 #define M_FW_PARAMS_PARAM_X 0xff
3712 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
3713 #define G_FW_PARAMS_PARAM_X(x) \
3714 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
3716 #define S_FW_PARAMS_PARAM_Y 8
3717 #define M_FW_PARAMS_PARAM_Y 0xff
3718 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
3719 #define G_FW_PARAMS_PARAM_Y(x) \
3720 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
3722 #define S_FW_PARAMS_PARAM_Z 0
3723 #define M_FW_PARAMS_PARAM_Z 0xff
3724 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
3725 #define G_FW_PARAMS_PARAM_Z(x) \
3726 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
3728 #define S_FW_PARAMS_PARAM_XYZ 0
3729 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
3730 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
3731 #define G_FW_PARAMS_PARAM_XYZ(x) \
3732 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
3734 #define S_FW_PARAMS_PARAM_YZ 0
3735 #define M_FW_PARAMS_PARAM_YZ 0xffff
3736 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
3737 #define G_FW_PARAMS_PARAM_YZ(x) \
3738 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
3740 struct fw_params_cmd {
3742 __be32 retval_len16;
3743 struct fw_params_param {
3749 #define S_FW_PARAMS_CMD_PFN 8
3750 #define M_FW_PARAMS_CMD_PFN 0x7
3751 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
3752 #define G_FW_PARAMS_CMD_PFN(x) \
3753 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
3755 #define S_FW_PARAMS_CMD_VFN 0
3756 #define M_FW_PARAMS_CMD_VFN 0xff
3757 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
3758 #define G_FW_PARAMS_CMD_VFN(x) \
3759 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
3761 struct fw_pfvf_cmd {
3763 __be32 retval_len16;
3764 __be32 niqflint_niq;
3766 __be32 tc_to_nexactf;
3767 __be32 r_caps_to_nethctrl;
3773 #define S_FW_PFVF_CMD_PFN 8
3774 #define M_FW_PFVF_CMD_PFN 0x7
3775 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
3776 #define G_FW_PFVF_CMD_PFN(x) \
3777 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
3779 #define S_FW_PFVF_CMD_VFN 0
3780 #define M_FW_PFVF_CMD_VFN 0xff
3781 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
3782 #define G_FW_PFVF_CMD_VFN(x) \
3783 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
3785 #define S_FW_PFVF_CMD_NIQFLINT 20
3786 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
3787 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT)
3788 #define G_FW_PFVF_CMD_NIQFLINT(x) \
3789 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
3791 #define S_FW_PFVF_CMD_NIQ 0
3792 #define M_FW_PFVF_CMD_NIQ 0xfffff
3793 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ)
3794 #define G_FW_PFVF_CMD_NIQ(x) \
3795 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
3797 #define S_FW_PFVF_CMD_TYPE 31
3798 #define M_FW_PFVF_CMD_TYPE 0x1
3799 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE)
3800 #define G_FW_PFVF_CMD_TYPE(x) \
3801 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
3802 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U)
3804 #define S_FW_PFVF_CMD_CMASK 24
3805 #define M_FW_PFVF_CMD_CMASK 0xf
3806 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK)
3807 #define G_FW_PFVF_CMD_CMASK(x) \
3808 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
3810 #define S_FW_PFVF_CMD_PMASK 20
3811 #define M_FW_PFVF_CMD_PMASK 0xf
3812 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK)
3813 #define G_FW_PFVF_CMD_PMASK(x) \
3814 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
3816 #define S_FW_PFVF_CMD_NEQ 0
3817 #define M_FW_PFVF_CMD_NEQ 0xfffff
3818 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ)
3819 #define G_FW_PFVF_CMD_NEQ(x) \
3820 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
3822 #define S_FW_PFVF_CMD_TC 24
3823 #define M_FW_PFVF_CMD_TC 0xff
3824 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC)
3825 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
3827 #define S_FW_PFVF_CMD_NVI 16
3828 #define M_FW_PFVF_CMD_NVI 0xff
3829 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI)
3830 #define G_FW_PFVF_CMD_NVI(x) \
3831 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
3833 #define S_FW_PFVF_CMD_NEXACTF 0
3834 #define M_FW_PFVF_CMD_NEXACTF 0xffff
3835 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF)
3836 #define G_FW_PFVF_CMD_NEXACTF(x) \
3837 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
3839 #define S_FW_PFVF_CMD_R_CAPS 24
3840 #define M_FW_PFVF_CMD_R_CAPS 0xff
3841 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS)
3842 #define G_FW_PFVF_CMD_R_CAPS(x) \
3843 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
3845 #define S_FW_PFVF_CMD_WX_CAPS 16
3846 #define M_FW_PFVF_CMD_WX_CAPS 0xff
3847 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS)
3848 #define G_FW_PFVF_CMD_WX_CAPS(x) \
3849 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
3851 #define S_FW_PFVF_CMD_NETHCTRL 0
3852 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
3853 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL)
3854 #define G_FW_PFVF_CMD_NETHCTRL(x) \
3855 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
3858 * ingress queue type; the first 1K ingress queues can have associated 0,
3859 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
3863 FW_IQ_TYPE_FL_INT_CAP,
3864 FW_IQ_TYPE_NO_FL_INT_CAP
3869 __be32 alloc_to_len16;
3874 __be32 type_to_iqandstindex;
3875 __be16 iqdroprss_to_iqesize;
3878 __be32 iqns_to_fl0congen;
3879 __be16 fl0dcaen_to_fl0cidxfthresh;
3882 __be32 fl1cngchmap_to_fl1congen;
3883 __be16 fl1dcaen_to_fl1cidxfthresh;
3888 #define S_FW_IQ_CMD_PFN 8
3889 #define M_FW_IQ_CMD_PFN 0x7
3890 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
3891 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
3893 #define S_FW_IQ_CMD_VFN 0
3894 #define M_FW_IQ_CMD_VFN 0xff
3895 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
3896 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
3898 #define S_FW_IQ_CMD_ALLOC 31
3899 #define M_FW_IQ_CMD_ALLOC 0x1
3900 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
3901 #define G_FW_IQ_CMD_ALLOC(x) \
3902 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
3903 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
3905 #define S_FW_IQ_CMD_FREE 30
3906 #define M_FW_IQ_CMD_FREE 0x1
3907 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
3908 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
3909 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
3911 #define S_FW_IQ_CMD_MODIFY 29
3912 #define M_FW_IQ_CMD_MODIFY 0x1
3913 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY)
3914 #define G_FW_IQ_CMD_MODIFY(x) \
3915 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
3916 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U)
3918 #define S_FW_IQ_CMD_IQSTART 28
3919 #define M_FW_IQ_CMD_IQSTART 0x1
3920 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
3921 #define G_FW_IQ_CMD_IQSTART(x) \
3922 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
3923 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
3925 #define S_FW_IQ_CMD_IQSTOP 27
3926 #define M_FW_IQ_CMD_IQSTOP 0x1
3927 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
3928 #define G_FW_IQ_CMD_IQSTOP(x) \
3929 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
3930 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
3932 #define S_FW_IQ_CMD_TYPE 29
3933 #define M_FW_IQ_CMD_TYPE 0x7
3934 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
3935 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
3937 #define S_FW_IQ_CMD_IQASYNCH 28
3938 #define M_FW_IQ_CMD_IQASYNCH 0x1
3939 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
3940 #define G_FW_IQ_CMD_IQASYNCH(x) \
3941 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
3942 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
3944 #define S_FW_IQ_CMD_VIID 16
3945 #define M_FW_IQ_CMD_VIID 0xfff
3946 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
3947 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
3949 #define S_FW_IQ_CMD_IQANDST 15
3950 #define M_FW_IQ_CMD_IQANDST 0x1
3951 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
3952 #define G_FW_IQ_CMD_IQANDST(x) \
3953 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
3954 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
3956 #define S_FW_IQ_CMD_IQANUS 14
3957 #define M_FW_IQ_CMD_IQANUS 0x1
3958 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS)
3959 #define G_FW_IQ_CMD_IQANUS(x) \
3960 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
3961 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U)
3963 #define S_FW_IQ_CMD_IQANUD 12
3964 #define M_FW_IQ_CMD_IQANUD 0x3
3965 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
3966 #define G_FW_IQ_CMD_IQANUD(x) \
3967 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
3969 #define S_FW_IQ_CMD_IQANDSTINDEX 0
3970 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
3971 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
3972 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
3973 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
3975 #define S_FW_IQ_CMD_IQDROPRSS 15
3976 #define M_FW_IQ_CMD_IQDROPRSS 0x1
3977 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS)
3978 #define G_FW_IQ_CMD_IQDROPRSS(x) \
3979 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
3980 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U)
3982 #define S_FW_IQ_CMD_IQGTSMODE 14
3983 #define M_FW_IQ_CMD_IQGTSMODE 0x1
3984 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
3985 #define G_FW_IQ_CMD_IQGTSMODE(x) \
3986 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
3987 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
3989 #define S_FW_IQ_CMD_IQPCIECH 12
3990 #define M_FW_IQ_CMD_IQPCIECH 0x3
3991 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
3992 #define G_FW_IQ_CMD_IQPCIECH(x) \
3993 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
3995 #define S_FW_IQ_CMD_IQDCAEN 11
3996 #define M_FW_IQ_CMD_IQDCAEN 0x1
3997 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN)
3998 #define G_FW_IQ_CMD_IQDCAEN(x) \
3999 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
4000 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U)
4002 #define S_FW_IQ_CMD_IQDCACPU 6
4003 #define M_FW_IQ_CMD_IQDCACPU 0x1f
4004 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU)
4005 #define G_FW_IQ_CMD_IQDCACPU(x) \
4006 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
4008 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
4009 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
4010 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
4011 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
4012 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
4014 #define S_FW_IQ_CMD_IQO 3
4015 #define M_FW_IQ_CMD_IQO 0x1
4016 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO)
4017 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
4018 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U)
4020 #define S_FW_IQ_CMD_IQCPRIO 2
4021 #define M_FW_IQ_CMD_IQCPRIO 0x1
4022 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO)
4023 #define G_FW_IQ_CMD_IQCPRIO(x) \
4024 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
4025 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U)
4027 #define S_FW_IQ_CMD_IQESIZE 0
4028 #define M_FW_IQ_CMD_IQESIZE 0x3
4029 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
4030 #define G_FW_IQ_CMD_IQESIZE(x) \
4031 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
4033 #define S_FW_IQ_CMD_IQNS 31
4034 #define M_FW_IQ_CMD_IQNS 0x1
4035 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS)
4036 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
4037 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U)
4039 #define S_FW_IQ_CMD_IQRO 30
4040 #define M_FW_IQ_CMD_IQRO 0x1
4041 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
4042 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
4043 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
4045 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28
4046 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3
4047 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
4048 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
4049 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
4051 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
4052 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
4053 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
4054 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
4055 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
4056 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
4058 #define S_FW_IQ_CMD_IQFLINTISCSIC 26
4059 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1
4060 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
4061 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
4062 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
4063 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
4065 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
4066 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
4067 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
4068 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
4069 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
4071 #define S_FW_IQ_CMD_FL0CACHELOCK 15
4072 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1
4073 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK)
4074 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \
4075 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
4076 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U)
4078 #define S_FW_IQ_CMD_FL0DBP 14
4079 #define M_FW_IQ_CMD_FL0DBP 0x1
4080 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP)
4081 #define G_FW_IQ_CMD_FL0DBP(x) \
4082 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
4083 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U)
4085 #define S_FW_IQ_CMD_FL0DATANS 13
4086 #define M_FW_IQ_CMD_FL0DATANS 0x1
4087 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS)
4088 #define G_FW_IQ_CMD_FL0DATANS(x) \
4089 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
4090 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U)
4092 #define S_FW_IQ_CMD_FL0DATARO 12
4093 #define M_FW_IQ_CMD_FL0DATARO 0x1
4094 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
4095 #define G_FW_IQ_CMD_FL0DATARO(x) \
4096 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
4097 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
4099 #define S_FW_IQ_CMD_FL0CONGCIF 11
4100 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
4101 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
4102 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
4103 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
4104 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
4106 #define S_FW_IQ_CMD_FL0ONCHIP 10
4107 #define M_FW_IQ_CMD_FL0ONCHIP 0x1
4108 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP)
4109 #define G_FW_IQ_CMD_FL0ONCHIP(x) \
4110 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
4111 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U)
4113 #define S_FW_IQ_CMD_FL0STATUSPGNS 9
4114 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1
4115 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
4116 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
4117 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
4118 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U)
4120 #define S_FW_IQ_CMD_FL0STATUSPGRO 8
4121 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1
4122 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
4123 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
4124 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
4125 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U)
4127 #define S_FW_IQ_CMD_FL0FETCHNS 7
4128 #define M_FW_IQ_CMD_FL0FETCHNS 0x1
4129 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS)
4130 #define G_FW_IQ_CMD_FL0FETCHNS(x) \
4131 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
4132 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U)
4134 #define S_FW_IQ_CMD_FL0FETCHRO 6
4135 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
4136 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
4137 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
4138 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
4139 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
4141 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
4142 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
4143 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
4144 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
4145 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
4147 #define S_FW_IQ_CMD_FL0CPRIO 3
4148 #define M_FW_IQ_CMD_FL0CPRIO 0x1
4149 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO)
4150 #define G_FW_IQ_CMD_FL0CPRIO(x) \
4151 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
4152 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U)
4154 #define S_FW_IQ_CMD_FL0PADEN 2
4155 #define M_FW_IQ_CMD_FL0PADEN 0x1
4156 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
4157 #define G_FW_IQ_CMD_FL0PADEN(x) \
4158 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
4159 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
4161 #define S_FW_IQ_CMD_FL0PACKEN 1
4162 #define M_FW_IQ_CMD_FL0PACKEN 0x1
4163 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
4164 #define G_FW_IQ_CMD_FL0PACKEN(x) \
4165 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
4166 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
4168 #define S_FW_IQ_CMD_FL0CONGEN 0
4169 #define M_FW_IQ_CMD_FL0CONGEN 0x1
4170 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
4171 #define G_FW_IQ_CMD_FL0CONGEN(x) \
4172 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
4173 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
4175 #define S_FW_IQ_CMD_FL0DCAEN 15
4176 #define M_FW_IQ_CMD_FL0DCAEN 0x1
4177 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN)
4178 #define G_FW_IQ_CMD_FL0DCAEN(x) \
4179 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
4180 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U)
4182 #define S_FW_IQ_CMD_FL0DCACPU 10
4183 #define M_FW_IQ_CMD_FL0DCACPU 0x1f
4184 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU)
4185 #define G_FW_IQ_CMD_FL0DCACPU(x) \
4186 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
4188 #define S_FW_IQ_CMD_FL0FBMIN 7
4189 #define M_FW_IQ_CMD_FL0FBMIN 0x7
4190 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
4191 #define G_FW_IQ_CMD_FL0FBMIN(x) \
4192 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
4194 #define S_FW_IQ_CMD_FL0FBMAX 4
4195 #define M_FW_IQ_CMD_FL0FBMAX 0x7
4196 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
4197 #define G_FW_IQ_CMD_FL0FBMAX(x) \
4198 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
4200 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3
4201 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1
4202 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
4203 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
4204 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
4205 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
4207 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
4208 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7
4209 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
4210 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
4211 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
4213 #define S_FW_IQ_CMD_FL1CNGCHMAP 20
4214 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf
4215 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
4216 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
4217 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
4219 #define S_FW_IQ_CMD_FL1CACHELOCK 15
4220 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1
4221 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK)
4222 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \
4223 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
4224 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U)
4226 #define S_FW_IQ_CMD_FL1DBP 14
4227 #define M_FW_IQ_CMD_FL1DBP 0x1
4228 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP)
4229 #define G_FW_IQ_CMD_FL1DBP(x) \
4230 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
4231 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U)
4233 #define S_FW_IQ_CMD_FL1DATANS 13
4234 #define M_FW_IQ_CMD_FL1DATANS 0x1
4235 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS)
4236 #define G_FW_IQ_CMD_FL1DATANS(x) \
4237 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
4238 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U)
4240 #define S_FW_IQ_CMD_FL1DATARO 12
4241 #define M_FW_IQ_CMD_FL1DATARO 0x1
4242 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO)
4243 #define G_FW_IQ_CMD_FL1DATARO(x) \
4244 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
4245 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U)
4247 #define S_FW_IQ_CMD_FL1CONGCIF 11
4248 #define M_FW_IQ_CMD_FL1CONGCIF 0x1
4249 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF)
4250 #define G_FW_IQ_CMD_FL1CONGCIF(x) \
4251 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
4252 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U)
4254 #define S_FW_IQ_CMD_FL1ONCHIP 10
4255 #define M_FW_IQ_CMD_FL1ONCHIP 0x1
4256 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP)
4257 #define G_FW_IQ_CMD_FL1ONCHIP(x) \
4258 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
4259 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U)
4261 #define S_FW_IQ_CMD_FL1STATUSPGNS 9
4262 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1
4263 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
4264 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
4265 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
4266 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U)
4268 #define S_FW_IQ_CMD_FL1STATUSPGRO 8
4269 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1
4270 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
4271 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
4272 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
4273 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U)
4275 #define S_FW_IQ_CMD_FL1FETCHNS 7
4276 #define M_FW_IQ_CMD_FL1FETCHNS 0x1
4277 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS)
4278 #define G_FW_IQ_CMD_FL1FETCHNS(x) \
4279 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
4280 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U)
4282 #define S_FW_IQ_CMD_FL1FETCHRO 6
4283 #define M_FW_IQ_CMD_FL1FETCHRO 0x1
4284 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO)
4285 #define G_FW_IQ_CMD_FL1FETCHRO(x) \
4286 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
4287 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U)
4289 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4
4290 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3
4291 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
4292 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
4293 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
4295 #define S_FW_IQ_CMD_FL1CPRIO 3
4296 #define M_FW_IQ_CMD_FL1CPRIO 0x1
4297 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO)
4298 #define G_FW_IQ_CMD_FL1CPRIO(x) \
4299 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
4300 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U)
4302 #define S_FW_IQ_CMD_FL1PADEN 2
4303 #define M_FW_IQ_CMD_FL1PADEN 0x1
4304 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN)
4305 #define G_FW_IQ_CMD_FL1PADEN(x) \
4306 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
4307 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U)
4309 #define S_FW_IQ_CMD_FL1PACKEN 1
4310 #define M_FW_IQ_CMD_FL1PACKEN 0x1
4311 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN)
4312 #define G_FW_IQ_CMD_FL1PACKEN(x) \
4313 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
4314 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U)
4316 #define S_FW_IQ_CMD_FL1CONGEN 0
4317 #define M_FW_IQ_CMD_FL1CONGEN 0x1
4318 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN)
4319 #define G_FW_IQ_CMD_FL1CONGEN(x) \
4320 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
4321 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U)
4323 #define S_FW_IQ_CMD_FL1DCAEN 15
4324 #define M_FW_IQ_CMD_FL1DCAEN 0x1
4325 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN)
4326 #define G_FW_IQ_CMD_FL1DCAEN(x) \
4327 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
4328 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U)
4330 #define S_FW_IQ_CMD_FL1DCACPU 10
4331 #define M_FW_IQ_CMD_FL1DCACPU 0x1f
4332 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU)
4333 #define G_FW_IQ_CMD_FL1DCACPU(x) \
4334 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
4336 #define S_FW_IQ_CMD_FL1FBMIN 7
4337 #define M_FW_IQ_CMD_FL1FBMIN 0x7
4338 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN)
4339 #define G_FW_IQ_CMD_FL1FBMIN(x) \
4340 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
4342 #define S_FW_IQ_CMD_FL1FBMAX 4
4343 #define M_FW_IQ_CMD_FL1FBMAX 0x7
4344 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX)
4345 #define G_FW_IQ_CMD_FL1FBMAX(x) \
4346 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
4348 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3
4349 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1
4350 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
4351 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
4352 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
4353 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
4355 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
4356 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7
4357 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
4358 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
4359 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
4361 struct fw_eq_mngt_cmd {
4363 __be32 alloc_to_len16;
4364 __be32 cmpliqid_eqid;
4365 __be32 physeqid_pkd;
4366 __be32 fetchszm_to_iqid;
4367 __be32 dcaen_to_eqsize;
4371 #define S_FW_EQ_MNGT_CMD_PFN 8
4372 #define M_FW_EQ_MNGT_CMD_PFN 0x7
4373 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN)
4374 #define G_FW_EQ_MNGT_CMD_PFN(x) \
4375 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
4377 #define S_FW_EQ_MNGT_CMD_VFN 0
4378 #define M_FW_EQ_MNGT_CMD_VFN 0xff
4379 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN)
4380 #define G_FW_EQ_MNGT_CMD_VFN(x) \
4381 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
4383 #define S_FW_EQ_MNGT_CMD_ALLOC 31
4384 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1
4385 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC)
4386 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \
4387 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
4388 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U)
4390 #define S_FW_EQ_MNGT_CMD_FREE 30
4391 #define M_FW_EQ_MNGT_CMD_FREE 0x1
4392 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE)
4393 #define G_FW_EQ_MNGT_CMD_FREE(x) \
4394 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
4395 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U)
4397 #define S_FW_EQ_MNGT_CMD_MODIFY 29
4398 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1
4399 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY)
4400 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \
4401 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
4402 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U)
4404 #define S_FW_EQ_MNGT_CMD_EQSTART 28
4405 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1
4406 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART)
4407 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \
4408 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
4409 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U)
4411 #define S_FW_EQ_MNGT_CMD_EQSTOP 27
4412 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1
4413 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
4414 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
4415 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
4416 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U)
4418 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20
4419 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff
4420 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
4421 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
4422 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
4424 #define S_FW_EQ_MNGT_CMD_EQID 0
4425 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff
4426 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID)
4427 #define G_FW_EQ_MNGT_CMD_EQID(x) \
4428 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
4430 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0
4431 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff
4432 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
4433 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
4434 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
4436 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26
4437 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1
4438 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
4439 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
4440 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
4441 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
4443 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25
4444 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1
4445 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
4446 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
4447 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
4448 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
4450 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24
4451 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1
4452 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
4453 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
4454 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
4455 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
4457 #define S_FW_EQ_MNGT_CMD_FETCHNS 23
4458 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1
4459 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
4460 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
4461 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
4462 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U)
4464 #define S_FW_EQ_MNGT_CMD_FETCHRO 22
4465 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1
4466 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
4467 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
4468 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
4469 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U)
4471 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20
4472 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3
4473 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
4474 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
4475 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
4477 #define S_FW_EQ_MNGT_CMD_CPRIO 19
4478 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1
4479 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO)
4480 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \
4481 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
4482 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U)
4484 #define S_FW_EQ_MNGT_CMD_ONCHIP 18
4485 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1
4486 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
4487 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
4488 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
4489 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U)
4491 #define S_FW_EQ_MNGT_CMD_PCIECHN 16
4492 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3
4493 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
4494 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
4495 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
4497 #define S_FW_EQ_MNGT_CMD_IQID 0
4498 #define M_FW_EQ_MNGT_CMD_IQID 0xffff
4499 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID)
4500 #define G_FW_EQ_MNGT_CMD_IQID(x) \
4501 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
4503 #define S_FW_EQ_MNGT_CMD_DCAEN 31
4504 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1
4505 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN)
4506 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \
4507 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
4508 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U)
4510 #define S_FW_EQ_MNGT_CMD_DCACPU 26
4511 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f
4512 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU)
4513 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \
4514 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
4516 #define S_FW_EQ_MNGT_CMD_FBMIN 23
4517 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7
4518 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN)
4519 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \
4520 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
4522 #define S_FW_EQ_MNGT_CMD_FBMAX 20
4523 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7
4524 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX)
4525 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \
4526 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
4528 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19
4529 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1
4530 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
4531 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
4532 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
4533 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
4534 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
4536 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16
4537 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7
4538 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
4539 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
4540 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
4542 #define S_FW_EQ_MNGT_CMD_EQSIZE 0
4543 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff
4544 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
4545 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
4546 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
4548 struct fw_eq_eth_cmd {
4550 __be32 alloc_to_len16;
4552 __be32 physeqid_pkd;
4553 __be32 fetchszm_to_iqid;
4554 __be32 dcaen_to_eqsize;
4561 #define S_FW_EQ_ETH_CMD_PFN 8
4562 #define M_FW_EQ_ETH_CMD_PFN 0x7
4563 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
4564 #define G_FW_EQ_ETH_CMD_PFN(x) \
4565 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
4567 #define S_FW_EQ_ETH_CMD_VFN 0
4568 #define M_FW_EQ_ETH_CMD_VFN 0xff
4569 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
4570 #define G_FW_EQ_ETH_CMD_VFN(x) \
4571 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
4573 #define S_FW_EQ_ETH_CMD_ALLOC 31
4574 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
4575 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
4576 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
4577 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
4578 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
4580 #define S_FW_EQ_ETH_CMD_FREE 30
4581 #define M_FW_EQ_ETH_CMD_FREE 0x1
4582 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
4583 #define G_FW_EQ_ETH_CMD_FREE(x) \
4584 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
4585 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
4587 #define S_FW_EQ_ETH_CMD_MODIFY 29
4588 #define M_FW_EQ_ETH_CMD_MODIFY 0x1
4589 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY)
4590 #define G_FW_EQ_ETH_CMD_MODIFY(x) \
4591 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
4592 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U)
4594 #define S_FW_EQ_ETH_CMD_EQSTART 28
4595 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
4596 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
4597 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
4598 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
4599 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
4601 #define S_FW_EQ_ETH_CMD_EQSTOP 27
4602 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1
4603 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP)
4604 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \
4605 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
4606 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U)
4608 #define S_FW_EQ_ETH_CMD_EQID 0
4609 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
4610 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
4611 #define G_FW_EQ_ETH_CMD_EQID(x) \
4612 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
4614 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
4615 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
4616 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
4617 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
4618 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
4620 #define S_FW_EQ_ETH_CMD_FETCHSZM 26
4621 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1
4622 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
4623 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
4624 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
4625 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U)
4627 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25
4628 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1
4629 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
4630 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
4631 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
4632 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
4634 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24
4635 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1
4636 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
4637 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
4638 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
4639 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
4641 #define S_FW_EQ_ETH_CMD_FETCHNS 23
4642 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1
4643 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS)
4644 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \
4645 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
4646 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U)
4648 #define S_FW_EQ_ETH_CMD_FETCHRO 22
4649 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
4650 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
4651 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
4652 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
4653 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
4655 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
4656 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
4657 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
4658 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
4659 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
4661 #define S_FW_EQ_ETH_CMD_CPRIO 19
4662 #define M_FW_EQ_ETH_CMD_CPRIO 0x1
4663 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO)
4664 #define G_FW_EQ_ETH_CMD_CPRIO(x) \
4665 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
4666 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U)
4668 #define S_FW_EQ_ETH_CMD_ONCHIP 18
4669 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1
4670 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP)
4671 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \
4672 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
4673 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U)
4675 #define S_FW_EQ_ETH_CMD_PCIECHN 16
4676 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
4677 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
4678 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
4679 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
4681 #define S_FW_EQ_ETH_CMD_IQID 0
4682 #define M_FW_EQ_ETH_CMD_IQID 0xffff
4683 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
4684 #define G_FW_EQ_ETH_CMD_IQID(x) \
4685 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
4687 #define S_FW_EQ_ETH_CMD_DCAEN 31
4688 #define M_FW_EQ_ETH_CMD_DCAEN 0x1
4689 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN)
4690 #define G_FW_EQ_ETH_CMD_DCAEN(x) \
4691 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
4692 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U)
4694 #define S_FW_EQ_ETH_CMD_DCACPU 26
4695 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f
4696 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU)
4697 #define G_FW_EQ_ETH_CMD_DCACPU(x) \
4698 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
4700 #define S_FW_EQ_ETH_CMD_FBMIN 23
4701 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
4702 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
4703 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
4704 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
4706 #define S_FW_EQ_ETH_CMD_FBMAX 20
4707 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
4708 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
4709 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
4710 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
4712 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19
4713 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1
4714 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
4715 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
4716 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
4717 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
4719 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
4720 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
4721 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
4722 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
4723 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
4725 #define S_FW_EQ_ETH_CMD_EQSIZE 0
4726 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
4727 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
4728 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
4729 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
4731 #define S_FW_EQ_ETH_CMD_VIID 16
4732 #define M_FW_EQ_ETH_CMD_VIID 0xfff
4733 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
4734 #define G_FW_EQ_ETH_CMD_VIID(x) \
4735 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
4737 struct fw_eq_ctrl_cmd {
4739 __be32 alloc_to_len16;
4740 __be32 cmpliqid_eqid;
4741 __be32 physeqid_pkd;
4742 __be32 fetchszm_to_iqid;
4743 __be32 dcaen_to_eqsize;
4747 #define S_FW_EQ_CTRL_CMD_PFN 8
4748 #define M_FW_EQ_CTRL_CMD_PFN 0x7
4749 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
4750 #define G_FW_EQ_CTRL_CMD_PFN(x) \
4751 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
4753 #define S_FW_EQ_CTRL_CMD_VFN 0
4754 #define M_FW_EQ_CTRL_CMD_VFN 0xff
4755 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
4756 #define G_FW_EQ_CTRL_CMD_VFN(x) \
4757 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
4759 #define S_FW_EQ_CTRL_CMD_ALLOC 31
4760 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1
4761 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
4762 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \
4763 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
4764 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
4766 #define S_FW_EQ_CTRL_CMD_FREE 30
4767 #define M_FW_EQ_CTRL_CMD_FREE 0x1
4768 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
4769 #define G_FW_EQ_CTRL_CMD_FREE(x) \
4770 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
4771 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
4773 #define S_FW_EQ_CTRL_CMD_MODIFY 29
4774 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1
4775 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY)
4776 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \
4777 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
4778 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U)
4780 #define S_FW_EQ_CTRL_CMD_EQSTART 28
4781 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1
4782 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
4783 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \
4784 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
4785 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
4787 #define S_FW_EQ_CTRL_CMD_EQSTOP 27
4788 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1
4789 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
4790 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
4791 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
4792 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U)
4794 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
4795 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff
4796 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
4797 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
4798 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
4800 #define S_FW_EQ_CTRL_CMD_EQID 0
4801 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
4802 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
4803 #define G_FW_EQ_CTRL_CMD_EQID(x) \
4804 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
4806 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
4807 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
4808 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
4809 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
4810 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
4812 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26
4813 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1
4814 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
4815 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
4816 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
4817 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
4819 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25
4820 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1
4821 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
4822 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
4823 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
4824 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
4826 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24
4827 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1
4828 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
4829 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
4830 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
4831 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
4833 #define S_FW_EQ_CTRL_CMD_FETCHNS 23
4834 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1
4835 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
4836 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
4837 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
4838 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U)
4840 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
4841 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1
4842 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
4843 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
4844 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
4845 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
4847 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
4848 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
4849 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
4850 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
4851 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
4853 #define S_FW_EQ_CTRL_CMD_CPRIO 19
4854 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1
4855 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO)
4856 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \
4857 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
4858 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U)
4860 #define S_FW_EQ_CTRL_CMD_ONCHIP 18
4861 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1
4862 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
4863 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
4864 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
4865 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U)
4867 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
4868 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3
4869 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
4870 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
4871 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
4873 #define S_FW_EQ_CTRL_CMD_IQID 0
4874 #define M_FW_EQ_CTRL_CMD_IQID 0xffff
4875 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
4876 #define G_FW_EQ_CTRL_CMD_IQID(x) \
4877 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
4879 #define S_FW_EQ_CTRL_CMD_DCAEN 31
4880 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1
4881 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN)
4882 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \
4883 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
4884 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U)
4886 #define S_FW_EQ_CTRL_CMD_DCACPU 26
4887 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f
4888 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU)
4889 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \
4890 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
4892 #define S_FW_EQ_CTRL_CMD_FBMIN 23
4893 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7
4894 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
4895 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \
4896 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
4898 #define S_FW_EQ_CTRL_CMD_FBMAX 20
4899 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7
4900 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
4901 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \
4902 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
4904 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19
4905 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1
4906 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
4907 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
4908 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
4909 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
4910 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
4912 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
4913 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7
4914 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
4915 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
4916 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
4918 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
4919 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff
4920 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
4921 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
4922 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
4924 struct fw_eq_ofld_cmd {
4926 __be32 alloc_to_len16;
4928 __be32 physeqid_pkd;
4929 __be32 fetchszm_to_iqid;
4930 __be32 dcaen_to_eqsize;
4934 #define S_FW_EQ_OFLD_CMD_PFN 8
4935 #define M_FW_EQ_OFLD_CMD_PFN 0x7
4936 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN)
4937 #define G_FW_EQ_OFLD_CMD_PFN(x) \
4938 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
4940 #define S_FW_EQ_OFLD_CMD_VFN 0
4941 #define M_FW_EQ_OFLD_CMD_VFN 0xff
4942 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN)
4943 #define G_FW_EQ_OFLD_CMD_VFN(x) \
4944 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
4946 #define S_FW_EQ_OFLD_CMD_ALLOC 31
4947 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1
4948 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC)
4949 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \
4950 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
4951 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U)
4953 #define S_FW_EQ_OFLD_CMD_FREE 30
4954 #define M_FW_EQ_OFLD_CMD_FREE 0x1
4955 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE)
4956 #define G_FW_EQ_OFLD_CMD_FREE(x) \
4957 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
4958 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U)
4960 #define S_FW_EQ_OFLD_CMD_MODIFY 29
4961 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1
4962 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY)
4963 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \
4964 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
4965 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U)
4967 #define S_FW_EQ_OFLD_CMD_EQSTART 28
4968 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1
4969 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART)
4970 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \
4971 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
4972 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U)
4974 #define S_FW_EQ_OFLD_CMD_EQSTOP 27
4975 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1
4976 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
4977 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
4978 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
4979 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U)
4981 #define S_FW_EQ_OFLD_CMD_EQID 0
4982 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff
4983 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID)
4984 #define G_FW_EQ_OFLD_CMD_EQID(x) \
4985 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
4987 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0
4988 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff
4989 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
4990 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
4991 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
4993 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26
4994 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1
4995 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
4996 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
4997 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
4998 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
5000 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25
5001 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1
5002 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
5003 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
5004 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
5005 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
5007 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24
5008 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1
5009 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
5010 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
5011 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
5012 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
5014 #define S_FW_EQ_OFLD_CMD_FETCHNS 23
5015 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1
5016 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
5017 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
5018 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
5019 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U)
5021 #define S_FW_EQ_OFLD_CMD_FETCHRO 22
5022 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1
5023 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
5024 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
5025 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
5026 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U)
5028 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20
5029 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3
5030 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
5031 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
5032 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
5034 #define S_FW_EQ_OFLD_CMD_CPRIO 19
5035 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1
5036 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO)
5037 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \
5038 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
5039 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U)
5041 #define S_FW_EQ_OFLD_CMD_ONCHIP 18
5042 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1
5043 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
5044 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
5045 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
5046 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U)
5048 #define S_FW_EQ_OFLD_CMD_PCIECHN 16
5049 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3
5050 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
5051 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
5052 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
5054 #define S_FW_EQ_OFLD_CMD_IQID 0
5055 #define M_FW_EQ_OFLD_CMD_IQID 0xffff
5056 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID)
5057 #define G_FW_EQ_OFLD_CMD_IQID(x) \
5058 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
5060 #define S_FW_EQ_OFLD_CMD_DCAEN 31
5061 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1
5062 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN)
5063 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \
5064 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
5065 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U)
5067 #define S_FW_EQ_OFLD_CMD_DCACPU 26
5068 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f
5069 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU)
5070 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \
5071 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
5073 #define S_FW_EQ_OFLD_CMD_FBMIN 23
5074 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7
5075 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN)
5076 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \
5077 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
5079 #define S_FW_EQ_OFLD_CMD_FBMAX 20
5080 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7
5081 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX)
5082 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \
5083 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
5085 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19
5086 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1
5087 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
5088 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
5089 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
5090 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
5091 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
5093 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16
5094 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7
5095 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
5096 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
5097 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
5099 #define S_FW_EQ_OFLD_CMD_EQSIZE 0
5100 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff
5101 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
5102 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
5103 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
5105 /* Macros for VIID parsing:
5106 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
5107 #define S_FW_VIID_PFN 8
5108 #define M_FW_VIID_PFN 0x7
5109 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN)
5110 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
5112 #define S_FW_VIID_VIVLD 7
5113 #define M_FW_VIID_VIVLD 0x1
5114 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD)
5115 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
5117 #define S_FW_VIID_VIN 0
5118 #define M_FW_VIID_VIN 0x7F
5119 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
5120 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
5126 FW_VI_FUNC_OPENISCSI,
5127 FW_VI_FUNC_OPENFCOE,
5135 __be32 alloc_to_len16;
5136 __be16 type_to_viid;
5141 __be16 norss_rsssize;
5151 #define S_FW_VI_CMD_PFN 8
5152 #define M_FW_VI_CMD_PFN 0x7
5153 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
5154 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
5156 #define S_FW_VI_CMD_VFN 0
5157 #define M_FW_VI_CMD_VFN 0xff
5158 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
5159 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
5161 #define S_FW_VI_CMD_ALLOC 31
5162 #define M_FW_VI_CMD_ALLOC 0x1
5163 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
5164 #define G_FW_VI_CMD_ALLOC(x) \
5165 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
5166 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
5168 #define S_FW_VI_CMD_FREE 30
5169 #define M_FW_VI_CMD_FREE 0x1
5170 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
5171 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
5172 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
5174 #define S_FW_VI_CMD_TYPE 15
5175 #define M_FW_VI_CMD_TYPE 0x1
5176 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
5177 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
5178 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
5180 #define S_FW_VI_CMD_FUNC 12
5181 #define M_FW_VI_CMD_FUNC 0x7
5182 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
5183 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
5185 #define S_FW_VI_CMD_VIID 0
5186 #define M_FW_VI_CMD_VIID 0xfff
5187 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
5188 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
5190 #define S_FW_VI_CMD_PORTID 4
5191 #define M_FW_VI_CMD_PORTID 0xf
5192 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
5193 #define G_FW_VI_CMD_PORTID(x) \
5194 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
5196 #define S_FW_VI_CMD_NORSS 11
5197 #define M_FW_VI_CMD_NORSS 0x1
5198 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS)
5199 #define G_FW_VI_CMD_NORSS(x) \
5200 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
5201 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U)
5203 #define S_FW_VI_CMD_RSSSIZE 0
5204 #define M_FW_VI_CMD_RSSSIZE 0x7ff
5205 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
5206 #define G_FW_VI_CMD_RSSSIZE(x) \
5207 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
5209 #define S_FW_VI_CMD_IDSIIQ 0
5210 #define M_FW_VI_CMD_IDSIIQ 0x3ff
5211 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ)
5212 #define G_FW_VI_CMD_IDSIIQ(x) \
5213 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
5215 #define S_FW_VI_CMD_IDSEIQ 0
5216 #define M_FW_VI_CMD_IDSEIQ 0x3ff
5217 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ)
5218 #define G_FW_VI_CMD_IDSEIQ(x) \
5219 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
5221 /* Special VI_MAC command index ids */
5222 #define FW_VI_MAC_ADD_MAC 0x3FF
5223 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
5224 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
5226 enum fw_vi_mac_smac {
5227 FW_VI_MAC_MPS_TCAM_ENTRY,
5228 FW_VI_MAC_MPS_TCAM_ONLY,
5230 FW_VI_MAC_SMT_AND_MPSTCAM
5233 enum fw_vi_mac_result {
5234 FW_VI_MAC_R_SUCCESS,
5235 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
5236 FW_VI_MAC_R_SMAC_FAIL,
5237 FW_VI_MAC_R_F_ACL_CHECK
5240 struct fw_vi_mac_cmd {
5242 __be32 freemacs_to_len16;
5244 struct fw_vi_mac_exact {
5245 __be16 valid_to_idx;
5248 struct fw_vi_mac_hash {
5254 #define S_FW_VI_MAC_CMD_VIID 0
5255 #define M_FW_VI_MAC_CMD_VIID 0xfff
5256 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
5257 #define G_FW_VI_MAC_CMD_VIID(x) \
5258 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
5260 #define S_FW_VI_MAC_CMD_FREEMACS 31
5261 #define M_FW_VI_MAC_CMD_FREEMACS 0x1
5262 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
5263 #define G_FW_VI_MAC_CMD_FREEMACS(x) \
5264 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
5265 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
5267 #define S_FW_VI_MAC_CMD_HASHVECEN 23
5268 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1
5269 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN)
5270 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \
5271 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN)
5272 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U)
5274 #define S_FW_VI_MAC_CMD_HASHUNIEN 22
5275 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
5276 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
5277 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
5278 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
5279 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U)
5281 #define S_FW_VI_MAC_CMD_VALID 15
5282 #define M_FW_VI_MAC_CMD_VALID 0x1
5283 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
5284 #define G_FW_VI_MAC_CMD_VALID(x) \
5285 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
5286 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
5288 #define S_FW_VI_MAC_CMD_PRIO 12
5289 #define M_FW_VI_MAC_CMD_PRIO 0x7
5290 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO)
5291 #define G_FW_VI_MAC_CMD_PRIO(x) \
5292 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
5294 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
5295 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
5296 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
5297 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
5298 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
5300 #define S_FW_VI_MAC_CMD_IDX 0
5301 #define M_FW_VI_MAC_CMD_IDX 0x3ff
5302 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
5303 #define G_FW_VI_MAC_CMD_IDX(x) \
5304 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
5306 /* T4 max MTU supported */
5307 #define T4_MAX_MTU_SUPPORTED 9600
5308 #define FW_RXMODE_MTU_NO_CHG 65535
5310 struct fw_vi_rxmode_cmd {
5312 __be32 retval_len16;
5313 __be32 mtu_to_vlanexen;
5317 #define S_FW_VI_RXMODE_CMD_VIID 0
5318 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
5319 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
5320 #define G_FW_VI_RXMODE_CMD_VIID(x) \
5321 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
5323 #define S_FW_VI_RXMODE_CMD_MTU 16
5324 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
5325 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
5326 #define G_FW_VI_RXMODE_CMD_MTU(x) \
5327 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
5329 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
5330 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
5331 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
5332 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
5333 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
5335 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
5336 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
5337 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
5338 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
5339 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
5340 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
5342 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
5343 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
5344 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
5345 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
5346 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
5347 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
5349 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
5350 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
5351 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
5352 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
5353 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
5355 struct fw_vi_enable_cmd {
5357 __be32 ien_to_len16;
5363 #define S_FW_VI_ENABLE_CMD_VIID 0
5364 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
5365 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
5366 #define G_FW_VI_ENABLE_CMD_VIID(x) \
5367 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
5369 #define S_FW_VI_ENABLE_CMD_IEN 31
5370 #define M_FW_VI_ENABLE_CMD_IEN 0x1
5371 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
5372 #define G_FW_VI_ENABLE_CMD_IEN(x) \
5373 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
5374 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
5376 #define S_FW_VI_ENABLE_CMD_EEN 30
5377 #define M_FW_VI_ENABLE_CMD_EEN 0x1
5378 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
5379 #define G_FW_VI_ENABLE_CMD_EEN(x) \
5380 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
5381 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
5383 #define S_FW_VI_ENABLE_CMD_LED 29
5384 #define M_FW_VI_ENABLE_CMD_LED 0x1
5385 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED)
5386 #define G_FW_VI_ENABLE_CMD_LED(x) \
5387 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
5388 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U)
5390 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
5391 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
5392 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
5393 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
5394 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
5395 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
5397 /* VI VF stats offset definitions */
5398 #define VI_VF_NUM_STATS 16
5399 enum fw_vi_stats_vf_index {
5400 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
5401 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
5402 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
5403 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
5404 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
5405 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
5406 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
5407 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
5408 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
5409 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
5410 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
5411 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
5412 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
5413 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
5414 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
5415 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
5418 /* VI PF stats offset definitions */
5419 #define VI_PF_NUM_STATS 17
5420 enum fw_vi_stats_pf_index {
5421 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
5422 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
5423 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
5424 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
5425 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
5426 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
5427 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
5428 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
5429 FW_VI_PF_STAT_RX_BYTES_IX,
5430 FW_VI_PF_STAT_RX_FRAMES_IX,
5431 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
5432 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
5433 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
5434 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
5435 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
5436 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
5437 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
5440 struct fw_vi_stats_cmd {
5442 __be32 retval_len16;
5444 struct fw_vi_stats_ctl {
5455 struct fw_vi_stats_pf {
5456 __be64 tx_bcast_bytes;
5457 __be64 tx_bcast_frames;
5458 __be64 tx_mcast_bytes;
5459 __be64 tx_mcast_frames;
5460 __be64 tx_ucast_bytes;
5461 __be64 tx_ucast_frames;
5462 __be64 tx_offload_bytes;
5463 __be64 tx_offload_frames;
5465 __be64 rx_pf_frames;
5466 __be64 rx_bcast_bytes;
5467 __be64 rx_bcast_frames;
5468 __be64 rx_mcast_bytes;
5469 __be64 rx_mcast_frames;
5470 __be64 rx_ucast_bytes;
5471 __be64 rx_ucast_frames;
5472 __be64 rx_err_frames;
5474 struct fw_vi_stats_vf {
5475 __be64 tx_bcast_bytes;
5476 __be64 tx_bcast_frames;
5477 __be64 tx_mcast_bytes;
5478 __be64 tx_mcast_frames;
5479 __be64 tx_ucast_bytes;
5480 __be64 tx_ucast_frames;
5481 __be64 tx_drop_frames;
5482 __be64 tx_offload_bytes;
5483 __be64 tx_offload_frames;
5484 __be64 rx_bcast_bytes;
5485 __be64 rx_bcast_frames;
5486 __be64 rx_mcast_bytes;
5487 __be64 rx_mcast_frames;
5488 __be64 rx_ucast_bytes;
5489 __be64 rx_ucast_frames;
5490 __be64 rx_err_frames;
5495 #define S_FW_VI_STATS_CMD_VIID 0
5496 #define M_FW_VI_STATS_CMD_VIID 0xfff
5497 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
5498 #define G_FW_VI_STATS_CMD_VIID(x) \
5499 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
5501 #define S_FW_VI_STATS_CMD_NSTATS 12
5502 #define M_FW_VI_STATS_CMD_NSTATS 0x7
5503 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
5504 #define G_FW_VI_STATS_CMD_NSTATS(x) \
5505 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
5507 #define S_FW_VI_STATS_CMD_IX 0
5508 #define M_FW_VI_STATS_CMD_IX 0x1f
5509 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
5510 #define G_FW_VI_STATS_CMD_IX(x) \
5511 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
5513 struct fw_acl_mac_cmd {
5528 #define S_FW_ACL_MAC_CMD_PFN 8
5529 #define M_FW_ACL_MAC_CMD_PFN 0x7
5530 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN)
5531 #define G_FW_ACL_MAC_CMD_PFN(x) \
5532 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
5534 #define S_FW_ACL_MAC_CMD_VFN 0
5535 #define M_FW_ACL_MAC_CMD_VFN 0xff
5536 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN)
5537 #define G_FW_ACL_MAC_CMD_VFN(x) \
5538 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
5540 #define S_FW_ACL_MAC_CMD_EN 31
5541 #define M_FW_ACL_MAC_CMD_EN 0x1
5542 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN)
5543 #define G_FW_ACL_MAC_CMD_EN(x) \
5544 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
5545 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U)
5547 struct fw_acl_vlan_cmd {
5556 #define S_FW_ACL_VLAN_CMD_PFN 8
5557 #define M_FW_ACL_VLAN_CMD_PFN 0x7
5558 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN)
5559 #define G_FW_ACL_VLAN_CMD_PFN(x) \
5560 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
5562 #define S_FW_ACL_VLAN_CMD_VFN 0
5563 #define M_FW_ACL_VLAN_CMD_VFN 0xff
5564 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN)
5565 #define G_FW_ACL_VLAN_CMD_VFN(x) \
5566 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
5568 #define S_FW_ACL_VLAN_CMD_EN 31
5569 #define M_FW_ACL_VLAN_CMD_EN 0x1
5570 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN)
5571 #define G_FW_ACL_VLAN_CMD_EN(x) \
5572 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
5573 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
5575 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
5576 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
5577 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
5578 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
5579 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
5580 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
5582 #define S_FW_ACL_VLAN_CMD_FM 6
5583 #define M_FW_ACL_VLAN_CMD_FM 0x1
5584 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM)
5585 #define G_FW_ACL_VLAN_CMD_FM(x) \
5586 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
5587 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
5589 /* port capabilities bitmap */
5591 FW_PORT_CAP_SPEED_100M = 0x0001,
5592 FW_PORT_CAP_SPEED_1G = 0x0002,
5593 FW_PORT_CAP_SPEED_2_5G = 0x0004,
5594 FW_PORT_CAP_SPEED_10G = 0x0008,
5595 FW_PORT_CAP_SPEED_40G = 0x0010,
5596 FW_PORT_CAP_SPEED_100G = 0x0020,
5597 FW_PORT_CAP_FC_RX = 0x0040,
5598 FW_PORT_CAP_FC_TX = 0x0080,
5599 FW_PORT_CAP_ANEG = 0x0100,
5600 FW_PORT_CAP_MDIX = 0x0200,
5601 FW_PORT_CAP_MDIAUTO = 0x0400,
5602 FW_PORT_CAP_FEC = 0x0800,
5603 FW_PORT_CAP_TECHKR = 0x1000,
5604 FW_PORT_CAP_TECHKX4 = 0x2000,
5607 #define S_FW_PORT_AUXLINFO_MDI 3
5608 #define M_FW_PORT_AUXLINFO_MDI 0x3
5609 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI)
5610 #define G_FW_PORT_AUXLINFO_MDI(x) \
5611 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI)
5613 #define S_FW_PORT_AUXLINFO_KX4 2
5614 #define M_FW_PORT_AUXLINFO_KX4 0x1
5615 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4)
5616 #define G_FW_PORT_AUXLINFO_KX4(x) \
5617 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
5618 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
5620 #define S_FW_PORT_AUXLINFO_KR 1
5621 #define M_FW_PORT_AUXLINFO_KR 0x1
5622 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR)
5623 #define G_FW_PORT_AUXLINFO_KR(x) \
5624 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
5625 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
5627 #define S_FW_PORT_AUXLINFO_FEC 0
5628 #define M_FW_PORT_AUXLINFO_FEC 0x1
5629 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC)
5630 #define G_FW_PORT_AUXLINFO_FEC(x) \
5631 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC)
5632 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U)
5634 #define S_FW_PORT_RCAP_AUX 11
5635 #define M_FW_PORT_RCAP_AUX 0x7
5636 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX)
5637 #define G_FW_PORT_RCAP_AUX(x) \
5638 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX)
5640 #define S_FW_PORT_CAP_SPEED 0
5641 #define M_FW_PORT_CAP_SPEED 0x3f
5642 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
5643 #define G_FW_PORT_CAP_SPEED(x) \
5644 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
5646 #define S_FW_PORT_CAP_FC 6
5647 #define M_FW_PORT_CAP_FC 0x3
5648 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC)
5649 #define G_FW_PORT_CAP_FC(x) \
5650 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
5652 #define S_FW_PORT_CAP_ANEG 8
5653 #define M_FW_PORT_CAP_ANEG 0x1
5654 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG)
5655 #define G_FW_PORT_CAP_ANEG(x) \
5656 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
5659 FW_PORT_CAP_MDI_UNCHANGED,
5660 FW_PORT_CAP_MDI_AUTO,
5661 FW_PORT_CAP_MDI_F_STRAIGHT,
5662 FW_PORT_CAP_MDI_F_CROSSOVER
5665 #define S_FW_PORT_CAP_MDI 9
5666 #define M_FW_PORT_CAP_MDI 3
5667 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
5668 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
5670 enum fw_port_action {
5671 FW_PORT_ACTION_L1_CFG = 0x0001,
5672 FW_PORT_ACTION_L2_CFG = 0x0002,
5673 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
5674 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
5675 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
5676 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
5677 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
5678 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
5679 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
5680 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
5681 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
5682 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
5683 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021,
5684 FW_PORT_ACTION_MAC_LPBK = 0x0022,
5685 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023,
5686 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026,
5687 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
5688 FW_PORT_ACTION_PCS_LPBK = 0x0028,
5689 FW_PORT_ACTION_PHY_RESET = 0x0040,
5690 FW_PORT_ACTION_PMA_RESET = 0x0041,
5691 FW_PORT_ACTION_PCS_RESET = 0x0042,
5692 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
5693 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
5694 FW_PORT_ACTION_AN_RESET = 0x0045,
5697 enum fw_port_l2cfg_ctlbf {
5698 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
5699 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
5700 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
5701 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
5702 FW_PORT_L2_CTLBF_IVLAN = 0x10,
5703 FW_PORT_L2_CTLBF_TXIPG = 0x20,
5704 FW_PORT_L2_CTLBF_MTU = 0x40
5707 enum fw_port_dcb_cfg {
5708 FW_PORT_DCB_CFG_PG = 0x01,
5709 FW_PORT_DCB_CFG_PFC = 0x02,
5710 FW_PORT_DCB_CFG_APPL = 0x04
5713 enum fw_port_dcb_cfg_rc {
5714 FW_PORT_DCB_CFG_SUCCESS = 0x0,
5715 FW_PORT_DCB_CFG_ERROR = 0x1
5718 enum fw_port_dcb_type {
5719 FW_PORT_DCB_TYPE_PGID = 0x00,
5720 FW_PORT_DCB_TYPE_PGRATE = 0x01,
5721 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
5722 FW_PORT_DCB_TYPE_PFC = 0x03,
5723 FW_PORT_DCB_TYPE_APP_ID = 0x04,
5724 FW_PORT_DCB_TYPE_CONTROL = 0x05,
5727 enum fw_port_diag_ops {
5728 FW_PORT_DIAGS_TEMP = 0x00,
5729 FW_PORT_DIAGS_TX_POWER = 0x01,
5730 FW_PORT_DIAGS_RX_POWER = 0x02,
5733 struct fw_port_cmd {
5734 __be32 op_to_portid;
5735 __be32 action_to_len16;
5737 struct fw_port_l1cfg {
5741 struct fw_port_l2cfg {
5743 __u8 ovlan3_to_ivlan0;
5745 __be16 txipg_force_pinfo;
5756 struct fw_port_info {
5757 __be32 lstatus_to_modtype;
5766 struct fw_port_diags {
5772 struct fw_port_dcb_pgid {
5779 struct fw_port_dcb_pgrate {
5783 __u8 num_tcs_supported;
5786 struct fw_port_dcb_priorate {
5790 __u8 strict_priorate[8];
5792 struct fw_port_dcb_pfc {
5798 struct fw_port_app_priority {
5807 struct fw_port_dcb_control {
5817 #define S_FW_PORT_CMD_READ 22
5818 #define M_FW_PORT_CMD_READ 0x1
5819 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)
5820 #define G_FW_PORT_CMD_READ(x) \
5821 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
5822 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U)
5824 #define S_FW_PORT_CMD_PORTID 0
5825 #define M_FW_PORT_CMD_PORTID 0xf
5826 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
5827 #define G_FW_PORT_CMD_PORTID(x) \
5828 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
5830 #define S_FW_PORT_CMD_ACTION 16
5831 #define M_FW_PORT_CMD_ACTION 0xffff
5832 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
5833 #define G_FW_PORT_CMD_ACTION(x) \
5834 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
5836 #define S_FW_PORT_CMD_OVLAN3 7
5837 #define M_FW_PORT_CMD_OVLAN3 0x1
5838 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3)
5839 #define G_FW_PORT_CMD_OVLAN3(x) \
5840 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
5841 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U)
5843 #define S_FW_PORT_CMD_OVLAN2 6
5844 #define M_FW_PORT_CMD_OVLAN2 0x1
5845 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2)
5846 #define G_FW_PORT_CMD_OVLAN2(x) \
5847 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
5848 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U)
5850 #define S_FW_PORT_CMD_OVLAN1 5
5851 #define M_FW_PORT_CMD_OVLAN1 0x1
5852 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1)
5853 #define G_FW_PORT_CMD_OVLAN1(x) \
5854 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
5855 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U)
5857 #define S_FW_PORT_CMD_OVLAN0 4
5858 #define M_FW_PORT_CMD_OVLAN0 0x1
5859 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0)
5860 #define G_FW_PORT_CMD_OVLAN0(x) \
5861 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
5862 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U)
5864 #define S_FW_PORT_CMD_IVLAN0 3
5865 #define M_FW_PORT_CMD_IVLAN0 0x1
5866 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0)
5867 #define G_FW_PORT_CMD_IVLAN0(x) \
5868 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
5869 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
5871 #define S_FW_PORT_CMD_TXIPG 3
5872 #define M_FW_PORT_CMD_TXIPG 0x1fff
5873 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
5874 #define G_FW_PORT_CMD_TXIPG(x) \
5875 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
5877 #define S_FW_PORT_CMD_FORCE_PINFO 0
5878 #define M_FW_PORT_CMD_FORCE_PINFO 0x1
5879 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO)
5880 #define G_FW_PORT_CMD_FORCE_PINFO(x) \
5881 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
5882 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U)
5884 #define S_FW_PORT_CMD_LSTATUS 31
5885 #define M_FW_PORT_CMD_LSTATUS 0x1
5886 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
5887 #define G_FW_PORT_CMD_LSTATUS(x) \
5888 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
5889 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
5891 #define S_FW_PORT_CMD_LSPEED 24
5892 #define M_FW_PORT_CMD_LSPEED 0x3f
5893 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
5894 #define G_FW_PORT_CMD_LSPEED(x) \
5895 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
5897 #define S_FW_PORT_CMD_TXPAUSE 23
5898 #define M_FW_PORT_CMD_TXPAUSE 0x1
5899 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
5900 #define G_FW_PORT_CMD_TXPAUSE(x) \
5901 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
5902 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
5904 #define S_FW_PORT_CMD_RXPAUSE 22
5905 #define M_FW_PORT_CMD_RXPAUSE 0x1
5906 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
5907 #define G_FW_PORT_CMD_RXPAUSE(x) \
5908 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
5909 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
5911 #define S_FW_PORT_CMD_MDIOCAP 21
5912 #define M_FW_PORT_CMD_MDIOCAP 0x1
5913 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
5914 #define G_FW_PORT_CMD_MDIOCAP(x) \
5915 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
5916 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
5918 #define S_FW_PORT_CMD_MDIOADDR 16
5919 #define M_FW_PORT_CMD_MDIOADDR 0x1f
5920 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
5921 #define G_FW_PORT_CMD_MDIOADDR(x) \
5922 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
5924 #define S_FW_PORT_CMD_LPTXPAUSE 15
5925 #define M_FW_PORT_CMD_LPTXPAUSE 0x1
5926 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE)
5927 #define G_FW_PORT_CMD_LPTXPAUSE(x) \
5928 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
5929 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U)
5931 #define S_FW_PORT_CMD_LPRXPAUSE 14
5932 #define M_FW_PORT_CMD_LPRXPAUSE 0x1
5933 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE)
5934 #define G_FW_PORT_CMD_LPRXPAUSE(x) \
5935 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
5936 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U)
5938 #define S_FW_PORT_CMD_PTYPE 8
5939 #define M_FW_PORT_CMD_PTYPE 0x1f
5940 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
5941 #define G_FW_PORT_CMD_PTYPE(x) \
5942 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
5944 #define S_FW_PORT_CMD_LINKDNRC 5
5945 #define M_FW_PORT_CMD_LINKDNRC 0x7
5946 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
5947 #define G_FW_PORT_CMD_LINKDNRC(x) \
5948 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
5950 #define S_FW_PORT_CMD_MODTYPE 0
5951 #define M_FW_PORT_CMD_MODTYPE 0x1f
5952 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
5953 #define G_FW_PORT_CMD_MODTYPE(x) \
5954 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
5956 #define S_FW_PORT_CMD_APPLY 7
5957 #define M_FW_PORT_CMD_APPLY 0x1
5958 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
5959 #define G_FW_PORT_CMD_APPLY(x) \
5960 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
5961 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
5963 #define S_FW_PORT_CMD_ALL_SYNCD 7
5964 #define M_FW_PORT_CMD_ALL_SYNCD 0x1
5965 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
5966 #define G_FW_PORT_CMD_ALL_SYNCD(x) \
5967 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
5968 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
5971 * These are configured into the VPD and hence tools that generate
5972 * VPD may use this enumeration.
5973 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
5976 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
5977 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
5978 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
5979 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */
5980 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */
5981 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
5982 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
5983 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
5984 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
5985 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
5986 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
5987 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
5988 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
5989 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
5990 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
5992 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
5995 /* These are read from module's EEPROM and determined once the
5996 module is inserted. */
5997 enum fw_port_module_type {
5998 FW_PORT_MOD_TYPE_NA = 0x0,
5999 FW_PORT_MOD_TYPE_LR = 0x1,
6000 FW_PORT_MOD_TYPE_SR = 0x2,
6001 FW_PORT_MOD_TYPE_ER = 0x3,
6002 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
6003 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
6004 FW_PORT_MOD_TYPE_LRM = 0x6,
6005 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
6006 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
6007 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
6008 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
6011 /* used by FW and tools may use this to generate VPD */
6012 enum fw_port_mod_sub_type {
6013 FW_PORT_MOD_SUB_TYPE_NA,
6014 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
6015 FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
6016 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
6017 FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
6018 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
6019 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
6020 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
6023 * The following will never been in the VPD. They are TWINAX cable
6024 * lengths decoded from SFP+ module i2c PROMs. These should almost
6025 * certainly go somewhere else ...
6027 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
6028 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
6029 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
6030 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
6033 /* link down reason codes (3b) */
6034 enum fw_port_link_dn_rc {
6035 FW_PORT_LINK_DN_RC_NONE,
6036 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
6037 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
6038 FW_PORT_LINK_DN_RESERVED3,
6039 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
6040 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
6041 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
6042 FW_PORT_LINK_DN_RESERVED7
6046 #define FW_NUM_PORT_STATS 50
6047 #define FW_NUM_PORT_TX_STATS 23
6048 #define FW_NUM_PORT_RX_STATS 27
6050 enum fw_port_stats_tx_index {
6051 FW_STAT_TX_PORT_BYTES_IX,
6052 FW_STAT_TX_PORT_FRAMES_IX,
6053 FW_STAT_TX_PORT_BCAST_IX,
6054 FW_STAT_TX_PORT_MCAST_IX,
6055 FW_STAT_TX_PORT_UCAST_IX,
6056 FW_STAT_TX_PORT_ERROR_IX,
6057 FW_STAT_TX_PORT_64B_IX,
6058 FW_STAT_TX_PORT_65B_127B_IX,
6059 FW_STAT_TX_PORT_128B_255B_IX,
6060 FW_STAT_TX_PORT_256B_511B_IX,
6061 FW_STAT_TX_PORT_512B_1023B_IX,
6062 FW_STAT_TX_PORT_1024B_1518B_IX,
6063 FW_STAT_TX_PORT_1519B_MAX_IX,
6064 FW_STAT_TX_PORT_DROP_IX,
6065 FW_STAT_TX_PORT_PAUSE_IX,
6066 FW_STAT_TX_PORT_PPP0_IX,
6067 FW_STAT_TX_PORT_PPP1_IX,
6068 FW_STAT_TX_PORT_PPP2_IX,
6069 FW_STAT_TX_PORT_PPP3_IX,
6070 FW_STAT_TX_PORT_PPP4_IX,
6071 FW_STAT_TX_PORT_PPP5_IX,
6072 FW_STAT_TX_PORT_PPP6_IX,
6073 FW_STAT_TX_PORT_PPP7_IX
6076 enum fw_port_stat_rx_index {
6077 FW_STAT_RX_PORT_BYTES_IX,
6078 FW_STAT_RX_PORT_FRAMES_IX,
6079 FW_STAT_RX_PORT_BCAST_IX,
6080 FW_STAT_RX_PORT_MCAST_IX,
6081 FW_STAT_RX_PORT_UCAST_IX,
6082 FW_STAT_RX_PORT_MTU_ERROR_IX,
6083 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
6084 FW_STAT_RX_PORT_CRC_ERROR_IX,
6085 FW_STAT_RX_PORT_LEN_ERROR_IX,
6086 FW_STAT_RX_PORT_SYM_ERROR_IX,
6087 FW_STAT_RX_PORT_64B_IX,
6088 FW_STAT_RX_PORT_65B_127B_IX,
6089 FW_STAT_RX_PORT_128B_255B_IX,
6090 FW_STAT_RX_PORT_256B_511B_IX,
6091 FW_STAT_RX_PORT_512B_1023B_IX,
6092 FW_STAT_RX_PORT_1024B_1518B_IX,
6093 FW_STAT_RX_PORT_1519B_MAX_IX,
6094 FW_STAT_RX_PORT_PAUSE_IX,
6095 FW_STAT_RX_PORT_PPP0_IX,
6096 FW_STAT_RX_PORT_PPP1_IX,
6097 FW_STAT_RX_PORT_PPP2_IX,
6098 FW_STAT_RX_PORT_PPP3_IX,
6099 FW_STAT_RX_PORT_PPP4_IX,
6100 FW_STAT_RX_PORT_PPP5_IX,
6101 FW_STAT_RX_PORT_PPP6_IX,
6102 FW_STAT_RX_PORT_PPP7_IX,
6103 FW_STAT_RX_PORT_LESS_64B_IX
6106 struct fw_port_stats_cmd {
6107 __be32 op_to_portid;
6108 __be32 retval_len16;
6109 union fw_port_stats {
6110 struct fw_port_stats_ctl {
6122 struct fw_port_stats_all {
6131 __be64 tx_128b_255b;
6132 __be64 tx_256b_511b;
6133 __be64 tx_512b_1023b;
6134 __be64 tx_1024b_1518b;
6135 __be64 tx_1519b_max;
6151 __be64 rx_mtu_error;
6152 __be64 rx_mtu_crc_error;
6153 __be64 rx_crc_error;
6154 __be64 rx_len_error;
6155 __be64 rx_sym_error;
6158 __be64 rx_128b_255b;
6159 __be64 rx_256b_511b;
6160 __be64 rx_512b_1023b;
6161 __be64 rx_1024b_1518b;
6162 __be64 rx_1519b_max;
6179 #define S_FW_PORT_STATS_CMD_NSTATS 4
6180 #define M_FW_PORT_STATS_CMD_NSTATS 0x7
6181 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS)
6182 #define G_FW_PORT_STATS_CMD_NSTATS(x) \
6183 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
6185 #define S_FW_PORT_STATS_CMD_BG_BM 0
6186 #define M_FW_PORT_STATS_CMD_BG_BM 0x3
6187 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM)
6188 #define G_FW_PORT_STATS_CMD_BG_BM(x) \
6189 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
6191 #define S_FW_PORT_STATS_CMD_TX 7
6192 #define M_FW_PORT_STATS_CMD_TX 0x1
6193 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX)
6194 #define G_FW_PORT_STATS_CMD_TX(x) \
6195 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
6196 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U)
6198 #define S_FW_PORT_STATS_CMD_IX 0
6199 #define M_FW_PORT_STATS_CMD_IX 0x3f
6200 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX)
6201 #define G_FW_PORT_STATS_CMD_IX(x) \
6202 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
6204 /* port loopback stats */
6205 #define FW_NUM_LB_STATS 14
6206 enum fw_port_lb_stats_index {
6207 FW_STAT_LB_PORT_BYTES_IX,
6208 FW_STAT_LB_PORT_FRAMES_IX,
6209 FW_STAT_LB_PORT_BCAST_IX,
6210 FW_STAT_LB_PORT_MCAST_IX,
6211 FW_STAT_LB_PORT_UCAST_IX,
6212 FW_STAT_LB_PORT_ERROR_IX,
6213 FW_STAT_LB_PORT_64B_IX,
6214 FW_STAT_LB_PORT_65B_127B_IX,
6215 FW_STAT_LB_PORT_128B_255B_IX,
6216 FW_STAT_LB_PORT_256B_511B_IX,
6217 FW_STAT_LB_PORT_512B_1023B_IX,
6218 FW_STAT_LB_PORT_1024B_1518B_IX,
6219 FW_STAT_LB_PORT_1519B_MAX_IX,
6220 FW_STAT_LB_PORT_DROP_FRAMES_IX
6223 struct fw_port_lb_stats_cmd {
6224 __be32 op_to_lbport;
6225 __be32 retval_len16;
6226 union fw_port_lb_stats {
6227 struct fw_port_lb_stats_ctl {
6239 struct fw_port_lb_stats_all {
6248 __be64 tx_128b_255b;
6249 __be64 tx_256b_511b;
6250 __be64 tx_512b_1023b;
6251 __be64 tx_1024b_1518b;
6252 __be64 tx_1519b_max;
6259 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0
6260 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf
6261 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
6262 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
6263 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
6264 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
6266 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4
6267 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7
6268 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
6269 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
6270 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
6271 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
6273 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0
6274 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3
6275 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
6276 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
6277 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
6279 #define S_FW_PORT_LB_STATS_CMD_IX 0
6280 #define M_FW_PORT_LB_STATS_CMD_IX 0xf
6281 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX)
6282 #define G_FW_PORT_LB_STATS_CMD_IX(x) \
6283 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
6285 /* Trace related defines */
6286 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
6287 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560
6289 struct fw_port_trace_cmd {
6290 __be32 op_to_portid;
6291 __be32 retval_len16;
6292 __be16 traceen_to_pciech;
6297 #define S_FW_PORT_TRACE_CMD_PORTID 0
6298 #define M_FW_PORT_TRACE_CMD_PORTID 0xf
6299 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID)
6300 #define G_FW_PORT_TRACE_CMD_PORTID(x) \
6301 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
6303 #define S_FW_PORT_TRACE_CMD_TRACEEN 15
6304 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1
6305 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
6306 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
6307 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
6308 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U)
6310 #define S_FW_PORT_TRACE_CMD_FLTMODE 14
6311 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1
6312 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
6313 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
6314 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
6315 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U)
6317 #define S_FW_PORT_TRACE_CMD_DUPLEN 13
6318 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1
6319 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
6320 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
6321 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
6322 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U)
6324 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8
6325 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f
6326 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
6327 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
6328 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
6329 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
6330 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
6332 #define S_FW_PORT_TRACE_CMD_PCIECH 6
6333 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3
6334 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH)
6335 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \
6336 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
6338 struct fw_port_trace_mmap_cmd {
6339 __be32 op_to_portid;
6340 __be32 retval_len16;
6341 __be32 fid_to_skipoffset;
6342 __be32 minpktsize_capturemax;
6346 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
6347 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf
6348 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
6349 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
6350 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
6351 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
6352 M_FW_PORT_TRACE_MMAP_CMD_PORTID)
6354 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30
6355 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3
6356 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
6357 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
6358 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
6360 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29
6361 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1
6362 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
6363 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
6364 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
6365 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
6366 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
6367 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
6369 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
6370 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
6371 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
6372 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
6373 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
6374 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
6375 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
6376 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \
6377 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
6379 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
6380 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
6381 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
6382 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
6383 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
6384 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
6385 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
6387 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
6388 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
6389 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
6390 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
6391 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
6392 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
6393 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
6395 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
6396 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
6397 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
6398 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
6399 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
6400 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
6401 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
6403 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
6404 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
6405 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
6406 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
6407 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
6408 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
6409 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
6411 struct fw_rss_ind_tbl_cmd {
6413 __be32 retval_len16;
6421 __be32 iq12_to_iq14;
6422 __be32 iq15_to_iq17;
6423 __be32 iq18_to_iq20;
6424 __be32 iq21_to_iq23;
6425 __be32 iq24_to_iq26;
6426 __be32 iq27_to_iq29;
6431 #define S_FW_RSS_IND_TBL_CMD_VIID 0
6432 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
6433 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
6434 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
6435 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
6437 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
6438 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
6439 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
6440 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
6441 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
6443 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
6444 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
6445 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
6446 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
6447 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
6449 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
6450 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
6451 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
6452 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
6453 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
6455 #define S_FW_RSS_IND_TBL_CMD_IQ3 20
6456 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff
6457 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
6458 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
6459 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
6461 #define S_FW_RSS_IND_TBL_CMD_IQ4 10
6462 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff
6463 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
6464 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
6465 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
6467 #define S_FW_RSS_IND_TBL_CMD_IQ5 0
6468 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff
6469 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
6470 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
6471 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
6473 #define S_FW_RSS_IND_TBL_CMD_IQ6 20
6474 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff
6475 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
6476 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
6477 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
6479 #define S_FW_RSS_IND_TBL_CMD_IQ7 10
6480 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff
6481 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
6482 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
6483 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
6485 #define S_FW_RSS_IND_TBL_CMD_IQ8 0
6486 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff
6487 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
6488 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
6489 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
6491 #define S_FW_RSS_IND_TBL_CMD_IQ9 20
6492 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff
6493 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
6494 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
6495 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
6497 #define S_FW_RSS_IND_TBL_CMD_IQ10 10
6498 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff
6499 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
6500 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
6501 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
6503 #define S_FW_RSS_IND_TBL_CMD_IQ11 0
6504 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff
6505 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
6506 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
6507 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
6509 #define S_FW_RSS_IND_TBL_CMD_IQ12 20
6510 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff
6511 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
6512 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
6513 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
6515 #define S_FW_RSS_IND_TBL_CMD_IQ13 10
6516 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff
6517 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
6518 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
6519 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
6521 #define S_FW_RSS_IND_TBL_CMD_IQ14 0
6522 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff
6523 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
6524 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
6525 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
6527 #define S_FW_RSS_IND_TBL_CMD_IQ15 20
6528 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff
6529 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
6530 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
6531 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
6533 #define S_FW_RSS_IND_TBL_CMD_IQ16 10
6534 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff
6535 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
6536 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
6537 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
6539 #define S_FW_RSS_IND_TBL_CMD_IQ17 0
6540 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff
6541 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
6542 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
6543 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
6545 #define S_FW_RSS_IND_TBL_CMD_IQ18 20
6546 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff
6547 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
6548 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
6549 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
6551 #define S_FW_RSS_IND_TBL_CMD_IQ19 10
6552 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff
6553 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
6554 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
6555 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
6557 #define S_FW_RSS_IND_TBL_CMD_IQ20 0
6558 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff
6559 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
6560 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
6561 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
6563 #define S_FW_RSS_IND_TBL_CMD_IQ21 20
6564 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff
6565 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
6566 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
6567 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
6569 #define S_FW_RSS_IND_TBL_CMD_IQ22 10
6570 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff
6571 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
6572 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
6573 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
6575 #define S_FW_RSS_IND_TBL_CMD_IQ23 0
6576 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff
6577 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
6578 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
6579 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
6581 #define S_FW_RSS_IND_TBL_CMD_IQ24 20
6582 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff
6583 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
6584 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
6585 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
6587 #define S_FW_RSS_IND_TBL_CMD_IQ25 10
6588 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff
6589 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
6590 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
6591 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
6593 #define S_FW_RSS_IND_TBL_CMD_IQ26 0
6594 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff
6595 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
6596 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
6597 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
6599 #define S_FW_RSS_IND_TBL_CMD_IQ27 20
6600 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff
6601 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
6602 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
6603 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
6605 #define S_FW_RSS_IND_TBL_CMD_IQ28 10
6606 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff
6607 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
6608 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
6609 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
6611 #define S_FW_RSS_IND_TBL_CMD_IQ29 0
6612 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff
6613 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
6614 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
6615 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
6617 #define S_FW_RSS_IND_TBL_CMD_IQ30 20
6618 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff
6619 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
6620 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
6621 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
6623 #define S_FW_RSS_IND_TBL_CMD_IQ31 10
6624 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff
6625 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
6626 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
6627 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
6629 struct fw_rss_glb_config_cmd {
6631 __be32 retval_len16;
6632 union fw_rss_glb_config {
6633 struct fw_rss_glb_config_manual {
6639 struct fw_rss_glb_config_basicvirtual {
6641 __be32 synmapen_to_hashtoeplitz;
6648 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
6649 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
6650 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
6651 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
6652 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
6654 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
6655 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
6656 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
6658 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
6659 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
6660 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
6661 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
6662 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
6663 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
6664 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
6665 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \
6666 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
6668 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
6669 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
6670 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
6671 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
6672 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
6673 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
6674 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
6675 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
6676 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
6678 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
6679 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
6680 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
6681 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
6682 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
6683 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
6684 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
6685 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
6686 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
6688 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
6689 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
6690 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
6691 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
6692 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
6693 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
6694 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
6695 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
6696 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
6698 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
6699 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
6700 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
6701 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
6702 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
6703 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
6704 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
6705 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
6706 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
6708 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
6709 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
6710 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
6711 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
6712 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
6713 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
6714 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
6715 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \
6716 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
6718 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
6719 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
6720 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
6721 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
6722 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
6723 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
6724 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
6725 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \
6726 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
6728 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
6729 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
6730 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
6731 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
6732 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
6733 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
6734 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
6735 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
6736 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
6738 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
6739 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
6740 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
6741 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
6742 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
6743 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
6744 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
6745 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
6746 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
6748 struct fw_rss_vi_config_cmd {
6750 __be32 retval_len16;
6751 union fw_rss_vi_config {
6752 struct fw_rss_vi_config_manual {
6757 struct fw_rss_vi_config_basicvirtual {
6759 __be32 defaultq_to_udpen;
6766 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
6767 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
6768 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
6769 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
6770 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
6772 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
6773 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
6774 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
6775 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
6776 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
6777 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
6778 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
6780 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
6781 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
6782 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
6783 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6784 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
6785 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
6786 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6787 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
6788 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
6790 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
6791 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
6792 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
6793 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6794 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
6795 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
6796 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6797 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
6798 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
6800 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
6801 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
6802 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
6803 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6804 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
6805 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
6806 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6807 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
6808 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
6810 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
6811 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
6812 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
6813 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6814 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
6815 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
6816 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6817 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
6818 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
6820 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
6821 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
6822 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
6823 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
6824 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
6825 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
6828 FW_SCHED_SC_CONFIG = 0,
6829 FW_SCHED_SC_PARAMS = 1,
6832 enum fw_sched_type {
6833 FW_SCHED_TYPE_PKTSCHED = 0,
6834 FW_SCHED_TYPE_STREAMSCHED = 1,
6837 enum fw_sched_params_level {
6838 FW_SCHED_PARAMS_LEVEL_CL_RL = 0,
6839 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1,
6840 FW_SCHED_PARAMS_LEVEL_CH_RL = 2,
6843 enum fw_sched_params_mode {
6844 FW_SCHED_PARAMS_MODE_CLASS = 0,
6845 FW_SCHED_PARAMS_MODE_FLOW = 1,
6848 enum fw_sched_params_unit {
6849 FW_SCHED_PARAMS_UNIT_BITRATE = 0,
6850 FW_SCHED_PARAMS_UNIT_PKTRATE = 1,
6853 enum fw_sched_params_rate {
6854 FW_SCHED_PARAMS_RATE_REL = 0,
6855 FW_SCHED_PARAMS_RATE_ABS = 1,
6858 struct fw_sched_cmd {
6860 __be32 retval_len16;
6862 struct fw_sched_config {
6870 struct fw_sched_params {
6890 * length of the formatting string
6892 #define FW_DEVLOG_FMT_LEN 192
6895 * maximum number of the formatting string parameters
6897 #define FW_DEVLOG_FMT_PARAMS_NUM 8
6902 enum fw_devlog_level {
6903 FW_DEVLOG_LEVEL_EMERG = 0x0,
6904 FW_DEVLOG_LEVEL_CRIT = 0x1,
6905 FW_DEVLOG_LEVEL_ERR = 0x2,
6906 FW_DEVLOG_LEVEL_NOTICE = 0x3,
6907 FW_DEVLOG_LEVEL_INFO = 0x4,
6908 FW_DEVLOG_LEVEL_DEBUG = 0x5,
6909 FW_DEVLOG_LEVEL_MAX = 0x5,
6913 * facilities that may send a log message
6915 enum fw_devlog_facility {
6916 FW_DEVLOG_FACILITY_CORE = 0x00,
6917 FW_DEVLOG_FACILITY_CF = 0x01,
6918 FW_DEVLOG_FACILITY_SCHED = 0x02,
6919 FW_DEVLOG_FACILITY_TIMER = 0x04,
6920 FW_DEVLOG_FACILITY_RES = 0x06,
6921 FW_DEVLOG_FACILITY_HW = 0x08,
6922 FW_DEVLOG_FACILITY_FLR = 0x10,
6923 FW_DEVLOG_FACILITY_DMAQ = 0x12,
6924 FW_DEVLOG_FACILITY_PHY = 0x14,
6925 FW_DEVLOG_FACILITY_MAC = 0x16,
6926 FW_DEVLOG_FACILITY_PORT = 0x18,
6927 FW_DEVLOG_FACILITY_VI = 0x1A,
6928 FW_DEVLOG_FACILITY_FILTER = 0x1C,
6929 FW_DEVLOG_FACILITY_ACL = 0x1E,
6930 FW_DEVLOG_FACILITY_TM = 0x20,
6931 FW_DEVLOG_FACILITY_QFC = 0x22,
6932 FW_DEVLOG_FACILITY_DCB = 0x24,
6933 FW_DEVLOG_FACILITY_ETH = 0x26,
6934 FW_DEVLOG_FACILITY_OFLD = 0x28,
6935 FW_DEVLOG_FACILITY_RI = 0x2A,
6936 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
6937 FW_DEVLOG_FACILITY_FCOE = 0x2E,
6938 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
6939 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
6940 FW_DEVLOG_FACILITY_MAX = 0x32,
6944 * log message format
6946 struct fw_devlog_e {
6952 __u8 fmt[FW_DEVLOG_FMT_LEN];
6953 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
6954 __be32 reserved3[4];
6957 struct fw_devlog_cmd {
6959 __be32 retval_len16;
6962 __be32 memtype_devlog_memaddr16_devlog;
6963 __be32 memsize_devlog;
6967 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28
6968 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf
6969 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
6970 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
6971 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
6972 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
6974 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
6975 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
6976 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
6977 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
6978 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
6979 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
6980 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
6982 enum fw_watchdog_actions {
6983 FW_WATCHDOG_ACTION_SHUTDOWN = 0,
6984 FW_WATCHDOG_ACTION_FLR = 1,
6985 FW_WATCHDOG_ACTION_BYPASS = 2,
6986 FW_WATCHDOG_ACTION_TMPCHK = 3,
6988 FW_WATCHDOG_ACTION_MAX = 4,
6991 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60
6993 struct fw_watchdog_cmd {
6995 __be32 retval_len16;
7000 #define S_FW_WATCHDOG_CMD_PFN 8
7001 #define M_FW_WATCHDOG_CMD_PFN 0x7
7002 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN)
7003 #define G_FW_WATCHDOG_CMD_PFN(x) \
7004 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
7006 #define S_FW_WATCHDOG_CMD_VFN 0
7007 #define M_FW_WATCHDOG_CMD_VFN 0xff
7008 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN)
7009 #define G_FW_WATCHDOG_CMD_VFN(x) \
7010 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
7012 struct fw_clip_cmd {
7014 __be32 alloc_to_len16;
7020 #define S_FW_CLIP_CMD_ALLOC 31
7021 #define M_FW_CLIP_CMD_ALLOC 0x1
7022 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
7023 #define G_FW_CLIP_CMD_ALLOC(x) \
7024 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
7025 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
7027 #define S_FW_CLIP_CMD_FREE 30
7028 #define M_FW_CLIP_CMD_FREE 0x1
7029 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
7030 #define G_FW_CLIP_CMD_FREE(x) \
7031 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
7032 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
7034 /******************************************************************************
7035 * F O i S C S I C O M M A N D s
7036 **************************************/
7038 #define FW_CHNET_IFACE_ADDR_MAX 3
7040 enum fw_chnet_iface_cmd_subop {
7041 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
7043 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
7044 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
7046 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
7047 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
7049 FW_CHNET_IFACE_CMD_SUBOP_MAX,
7052 struct fw_chnet_iface_cmd {
7053 __be32 op_to_portid;
7054 __be32 retval_len16;
7057 __be32 ifid_ifstate;
7065 #define S_FW_CHNET_IFACE_CMD_PORTID 0
7066 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf
7067 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID)
7068 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \
7069 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
7071 #define S_FW_CHNET_IFACE_CMD_IFID 8
7072 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
7073 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
7074 #define G_FW_CHNET_IFACE_CMD_IFID(x) \
7075 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
7077 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0
7078 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff
7079 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
7080 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
7081 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
7083 /******************************************************************************
7084 * F O F C O E C O M M A N D s
7085 ************************************/
7087 struct fw_fcoe_res_info_cmd {
7089 __be32 retval_len16;
7104 struct fw_fcoe_link_cmd {
7105 __be32 op_to_portid;
7106 __be32 retval_len16;
7107 __be32 sub_opcode_fcfi;
7117 __u8 vnport_wwnn[8];
7118 __u8 vnport_wwpn[8];
7121 #define S_FW_FCOE_LINK_CMD_PORTID 0
7122 #define M_FW_FCOE_LINK_CMD_PORTID 0xf
7123 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID)
7124 #define G_FW_FCOE_LINK_CMD_PORTID(x) \
7125 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
7127 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24
7128 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff
7129 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
7130 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
7131 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
7132 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
7134 #define S_FW_FCOE_LINK_CMD_FCFI 0
7135 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff
7136 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI)
7137 #define G_FW_FCOE_LINK_CMD_FCFI(x) \
7138 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
7140 #define S_FW_FCOE_LINK_CMD_VNPI 0
7141 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff
7142 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI)
7143 #define G_FW_FCOE_LINK_CMD_VNPI(x) \
7144 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
7146 struct fw_fcoe_vnp_cmd {
7148 __be32 alloc_to_len16;
7149 __be32 gen_wwn_to_vnpi;
7153 __u8 vnport_wwnn[8];
7154 __u8 vnport_wwpn[8];
7155 __u8 cmn_srv_parms[16];
7156 __u8 clsp_word_0_1[8];
7159 #define S_FW_FCOE_VNP_CMD_FCFI 0
7160 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff
7161 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI)
7162 #define G_FW_FCOE_VNP_CMD_FCFI(x) \
7163 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
7165 #define S_FW_FCOE_VNP_CMD_ALLOC 31
7166 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1
7167 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC)
7168 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \
7169 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
7170 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U)
7172 #define S_FW_FCOE_VNP_CMD_FREE 30
7173 #define M_FW_FCOE_VNP_CMD_FREE 0x1
7174 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE)
7175 #define G_FW_FCOE_VNP_CMD_FREE(x) \
7176 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
7177 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U)
7179 #define S_FW_FCOE_VNP_CMD_MODIFY 29
7180 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1
7181 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY)
7182 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \
7183 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
7184 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U)
7186 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22
7187 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1
7188 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
7189 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
7190 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
7191 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
7193 #define S_FW_FCOE_VNP_CMD_PERSIST 21
7194 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1
7195 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST)
7196 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \
7197 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
7198 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U)
7200 #define S_FW_FCOE_VNP_CMD_VFID_EN 20
7201 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1
7202 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
7203 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
7204 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
7205 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U)
7207 #define S_FW_FCOE_VNP_CMD_VNPI 0
7208 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff
7209 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI)
7210 #define G_FW_FCOE_VNP_CMD_VNPI(x) \
7211 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
7213 struct fw_fcoe_sparams_cmd {
7214 __be32 op_to_portid;
7215 __be32 retval_len16;
7220 __u8 cmn_srv_parms[16];
7221 __u8 cls_srv_parms[16];
7224 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0
7225 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf
7226 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
7227 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
7228 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
7230 struct fw_fcoe_stats_cmd {
7231 __be32 op_to_flowid;
7232 __be32 free_to_len16;
7233 union fw_fcoe_stats {
7234 struct fw_fcoe_stats_ctl {
7246 struct fw_fcoe_port_stats {
7247 __be64 tx_bcast_bytes;
7248 __be64 tx_bcast_frames;
7249 __be64 tx_mcast_bytes;
7250 __be64 tx_mcast_frames;
7251 __be64 tx_ucast_bytes;
7252 __be64 tx_ucast_frames;
7253 __be64 tx_drop_frames;
7254 __be64 tx_offload_bytes;
7255 __be64 tx_offload_frames;
7256 __be64 rx_bcast_bytes;
7257 __be64 rx_bcast_frames;
7258 __be64 rx_mcast_bytes;
7259 __be64 rx_mcast_frames;
7260 __be64 rx_ucast_bytes;
7261 __be64 rx_ucast_frames;
7262 __be64 rx_err_frames;
7264 struct fw_fcoe_fcf_stats {
7265 __be32 fip_tx_bytes;
7268 __be64 mcast_adv_rcvd;
7269 __be16 ucast_adv_rcvd;
7287 struct fw_fcoe_pcb_stats {
7293 __be32 unsol_els_rcvd;
7294 __be64 unsol_cmd_rcvd;
7295 __be16 implicit_logo;
7296 __be16 flogi_inv_sparm;
7297 __be16 fdisc_inv_sparm;
7301 __be16 mac_flt_fail;
7304 struct fw_fcoe_scb_stats {
7309 __be32 host_abrt_req;
7310 __be32 adap_auto_abrt;
7311 __be32 adap_abrt_rsp;
7312 __be32 host_ios_req;
7313 __be16 ssn_offl_ios;
7314 __be16 ssn_not_rdy_ios;
7315 __u8 rx_data_ddp_err;
7316 __u8 ddp_flt_set_err;
7317 __be16 rx_data_fr_err;
7318 __u8 bad_st_abrt_req;
7319 __u8 no_io_abrt_req;
7323 __u8 no_ppod_res_tmo;
7327 __be32 host_cls_req;
7328 __be64 unsol_cmd_rcvd;
7329 __be32 plogi_req_rcvd;
7330 __be32 prli_req_rcvd;
7331 __be16 logo_req_rcvd;
7332 __be16 prlo_req_rcvd;
7333 __be16 plogi_rjt_rcvd;
7334 __be16 prli_rjt_rcvd;
7335 __be32 adisc_req_rcvd;
7337 __be32 rrq_req_rcvd;
7338 __be32 unsol_els_rcvd;
7339 __u8 adisc_rjt_rcvd;
7342 __u8 inval_bls_rcvd;
7348 #define S_FW_FCOE_STATS_CMD_FLOWID 0
7349 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff
7350 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID)
7351 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \
7352 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
7354 #define S_FW_FCOE_STATS_CMD_FREE 30
7355 #define M_FW_FCOE_STATS_CMD_FREE 0x1
7356 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE)
7357 #define G_FW_FCOE_STATS_CMD_FREE(x) \
7358 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
7359 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U)
7361 #define S_FW_FCOE_STATS_CMD_NSTATS 4
7362 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7
7363 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS)
7364 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \
7365 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
7367 #define S_FW_FCOE_STATS_CMD_PORT 0
7368 #define M_FW_FCOE_STATS_CMD_PORT 0x3
7369 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT)
7370 #define G_FW_FCOE_STATS_CMD_PORT(x) \
7371 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
7373 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7
7374 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1
7375 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
7376 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
7377 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
7378 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
7379 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
7381 #define S_FW_FCOE_STATS_CMD_IX 0
7382 #define M_FW_FCOE_STATS_CMD_IX 0x3f
7383 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX)
7384 #define G_FW_FCOE_STATS_CMD_IX(x) \
7385 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
7387 struct fw_fcoe_fcf_cmd {
7389 __be32 retval_len16;
7390 __be16 priority_pkd;
7395 __be16 max_fcoe_size;
7401 __u8 fpma_to_portid;
7406 #define S_FW_FCOE_FCF_CMD_FCFI 0
7407 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff
7408 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI)
7409 #define G_FW_FCOE_FCF_CMD_FCFI(x) \
7410 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
7412 #define S_FW_FCOE_FCF_CMD_PRIORITY 0
7413 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff
7414 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
7415 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
7416 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
7418 #define S_FW_FCOE_FCF_CMD_FPMA 6
7419 #define M_FW_FCOE_FCF_CMD_FPMA 0x1
7420 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA)
7421 #define G_FW_FCOE_FCF_CMD_FPMA(x) \
7422 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
7423 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U)
7425 #define S_FW_FCOE_FCF_CMD_SPMA 5
7426 #define M_FW_FCOE_FCF_CMD_SPMA 0x1
7427 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA)
7428 #define G_FW_FCOE_FCF_CMD_SPMA(x) \
7429 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
7430 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U)
7432 #define S_FW_FCOE_FCF_CMD_LOGIN 4
7433 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1
7434 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN)
7435 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \
7436 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
7437 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U)
7439 #define S_FW_FCOE_FCF_CMD_PORTID 0
7440 #define M_FW_FCOE_FCF_CMD_PORTID 0xf
7441 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID)
7442 #define G_FW_FCOE_FCF_CMD_PORTID(x) \
7443 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
7445 /******************************************************************************
7446 * E R R O R a n d D E B U G C O M M A N D s
7447 ******************************************************/
7449 enum fw_error_type {
7450 FW_ERROR_TYPE_EXCEPTION = 0x0,
7451 FW_ERROR_TYPE_HWMODULE = 0x1,
7452 FW_ERROR_TYPE_WR = 0x2,
7453 FW_ERROR_TYPE_ACL = 0x3,
7456 struct fw_error_cmd {
7460 struct fw_error_exception {
7463 struct fw_error_hwmodule {
7467 struct fw_error_wr {
7473 struct fw_error_acl {
7484 #define S_FW_ERROR_CMD_FATAL 4
7485 #define M_FW_ERROR_CMD_FATAL 0x1
7486 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL)
7487 #define G_FW_ERROR_CMD_FATAL(x) \
7488 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
7489 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U)
7491 #define S_FW_ERROR_CMD_TYPE 0
7492 #define M_FW_ERROR_CMD_TYPE 0xf
7493 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE)
7494 #define G_FW_ERROR_CMD_TYPE(x) \
7495 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
7497 #define S_FW_ERROR_CMD_PFN 8
7498 #define M_FW_ERROR_CMD_PFN 0x7
7499 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
7500 #define G_FW_ERROR_CMD_PFN(x) \
7501 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
7503 #define S_FW_ERROR_CMD_VFN 0
7504 #define M_FW_ERROR_CMD_VFN 0xff
7505 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
7506 #define G_FW_ERROR_CMD_VFN(x) \
7507 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
7509 #define S_FW_ERROR_CMD_PFN 8
7510 #define M_FW_ERROR_CMD_PFN 0x7
7511 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
7512 #define G_FW_ERROR_CMD_PFN(x) \
7513 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
7515 #define S_FW_ERROR_CMD_VFN 0
7516 #define M_FW_ERROR_CMD_VFN 0xff
7517 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
7518 #define G_FW_ERROR_CMD_VFN(x) \
7519 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
7521 #define S_FW_ERROR_CMD_MV 15
7522 #define M_FW_ERROR_CMD_MV 0x1
7523 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV)
7524 #define G_FW_ERROR_CMD_MV(x) \
7525 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
7526 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U)
7528 struct fw_debug_cmd {
7532 struct fw_debug_assert {
7537 __u8 filename_0_7[8];
7538 __u8 filename_8_15[8];
7541 struct fw_debug_prt {
7544 __be32 dprtstrparam0;
7545 __be32 dprtstrparam1;
7546 __be32 dprtstrparam2;
7547 __be32 dprtstrparam3;
7552 #define S_FW_DEBUG_CMD_TYPE 0
7553 #define M_FW_DEBUG_CMD_TYPE 0xff
7554 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
7555 #define G_FW_DEBUG_CMD_TYPE(x) \
7556 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
7558 /******************************************************************************
7559 * P C I E F W R E G I S T E R
7560 **************************************/
7563 PCIE_FW_EVAL_CRASH = 0,
7564 PCIE_FW_EVAL_PREP = 1,
7565 PCIE_FW_EVAL_CONF = 2,
7566 PCIE_FW_EVAL_INIT = 3,
7567 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4,
7568 PCIE_FW_EVAL_OVERHEAT = 5,
7569 PCIE_FW_EVAL_DEVICESHUTDOWN = 6,
7573 * Register definitions for the PCIE_FW register which the firmware uses
7574 * to retain status across RESETs. This register should be considered
7575 * as a READ-ONLY register for Host Software and only to be used to
7576 * track firmware initialization/error state, etc.
7578 #define S_PCIE_FW_ERR 31
7579 #define M_PCIE_FW_ERR 0x1
7580 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
7581 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
7582 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
7584 #define S_PCIE_FW_INIT 30
7585 #define M_PCIE_FW_INIT 0x1
7586 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
7587 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
7588 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
7590 #define S_PCIE_FW_HALT 29
7591 #define M_PCIE_FW_HALT 0x1
7592 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
7593 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
7594 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
7596 #define S_PCIE_FW_EVAL 24
7597 #define M_PCIE_FW_EVAL 0x7
7598 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
7599 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
7601 #define S_PCIE_FW_STAGE 21
7602 #define M_PCIE_FW_STAGE 0x7
7603 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE)
7604 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
7606 #define S_PCIE_FW_ASYNCNOT_VLD 20
7607 #define M_PCIE_FW_ASYNCNOT_VLD 0x1
7608 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
7609 ((x) << S_PCIE_FW_ASYNCNOT_VLD)
7610 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
7611 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
7612 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U)
7614 #define S_PCIE_FW_ASYNCNOTINT 19
7615 #define M_PCIE_FW_ASYNCNOTINT 0x1
7616 #define V_PCIE_FW_ASYNCNOTINT(x) \
7617 ((x) << S_PCIE_FW_ASYNCNOTINT)
7618 #define G_PCIE_FW_ASYNCNOTINT(x) \
7619 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
7620 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U)
7622 #define S_PCIE_FW_ASYNCNOT 16
7623 #define M_PCIE_FW_ASYNCNOT 0x7
7624 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT)
7625 #define G_PCIE_FW_ASYNCNOT(x) \
7626 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
7628 #define S_PCIE_FW_MASTER_VLD 15
7629 #define M_PCIE_FW_MASTER_VLD 0x1
7630 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
7631 #define G_PCIE_FW_MASTER_VLD(x) \
7632 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
7633 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
7635 #define S_PCIE_FW_MASTER 12
7636 #define M_PCIE_FW_MASTER 0x7
7637 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
7638 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
7640 #define S_PCIE_FW_RESET_VLD 11
7641 #define M_PCIE_FW_RESET_VLD 0x1
7642 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD)
7643 #define G_PCIE_FW_RESET_VLD(x) \
7644 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
7645 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U)
7647 #define S_PCIE_FW_RESET 8
7648 #define M_PCIE_FW_RESET 0x7
7649 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET)
7650 #define G_PCIE_FW_RESET(x) \
7651 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
7653 #define S_PCIE_FW_REGISTERED 0
7654 #define M_PCIE_FW_REGISTERED 0xff
7655 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
7656 #define G_PCIE_FW_REGISTERED(x) \
7657 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
7660 /******************************************************************************
7661 * B I N A R Y H E A D E R F O R M A T
7662 **********************************************/
7665 * firmware binary header format
7669 __u8 chip; /* terminator chip family */
7670 __be16 len512; /* bin length in units of 512-bytes */
7671 __be32 fw_ver; /* firmware version */
7672 __be32 tp_microcode_ver; /* tcp processor microcode version */
7677 __u8 intfver_iscsipdu;
7679 __u8 intfver_fcoepdu;
7683 __u32 magic; /* runtime or bootstrap fw */
7685 __be32 reserved6[23];
7693 #define S_FW_HDR_FW_VER_MAJOR 24
7694 #define M_FW_HDR_FW_VER_MAJOR 0xff
7695 #define V_FW_HDR_FW_VER_MAJOR(x) \
7696 ((x) << S_FW_HDR_FW_VER_MAJOR)
7697 #define G_FW_HDR_FW_VER_MAJOR(x) \
7698 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
7700 #define S_FW_HDR_FW_VER_MINOR 16
7701 #define M_FW_HDR_FW_VER_MINOR 0xff
7702 #define V_FW_HDR_FW_VER_MINOR(x) \
7703 ((x) << S_FW_HDR_FW_VER_MINOR)
7704 #define G_FW_HDR_FW_VER_MINOR(x) \
7705 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
7707 #define S_FW_HDR_FW_VER_MICRO 8
7708 #define M_FW_HDR_FW_VER_MICRO 0xff
7709 #define V_FW_HDR_FW_VER_MICRO(x) \
7710 ((x) << S_FW_HDR_FW_VER_MICRO)
7711 #define G_FW_HDR_FW_VER_MICRO(x) \
7712 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
7714 #define S_FW_HDR_FW_VER_BUILD 0
7715 #define M_FW_HDR_FW_VER_BUILD 0xff
7716 #define V_FW_HDR_FW_VER_BUILD(x) \
7717 ((x) << S_FW_HDR_FW_VER_BUILD)
7718 #define G_FW_HDR_FW_VER_BUILD(x) \
7719 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
7722 T4FW_VERSION_MAJOR = 0x01,
7723 T4FW_VERSION_MINOR = 0x09,
7724 T4FW_VERSION_MICRO = 0x0c,
7725 T4FW_VERSION_BUILD = 0x00,
7727 T5FW_VERSION_MAJOR = 0x01,
7728 T5FW_VERSION_MINOR = 0x09,
7729 T5FW_VERSION_MICRO = 0x0c,
7730 T5FW_VERSION_BUILD = 0x00,
7734 T4FW_HDR_INTFVER_NIC = 0x00,
7735 T4FW_HDR_INTFVER_VNIC = 0x00,
7736 T4FW_HDR_INTFVER_OFLD = 0x00,
7737 T4FW_HDR_INTFVER_RI = 0x00,
7738 T4FW_HDR_INTFVER_ISCSIPDU = 0x00,
7739 T4FW_HDR_INTFVER_ISCSI = 0x00,
7740 T4FW_HDR_INTFVER_FCOEPDU = 0x00,
7741 T4FW_HDR_INTFVER_FCOE = 0x00,
7743 T5FW_HDR_INTFVER_NIC = 0x00,
7744 T5FW_HDR_INTFVER_VNIC = 0x00,
7745 T5FW_HDR_INTFVER_OFLD = 0x00,
7746 T5FW_HDR_INTFVER_RI = 0x00,
7747 T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
7748 T5FW_HDR_INTFVER_ISCSI = 0x00,
7749 T5FW_HDR_INTFVER_FCOEPDU= 0x00,
7750 T5FW_HDR_INTFVER_FCOE = 0x00,
7754 FW_HDR_MAGIC_RUNTIME = 0x00000000,
7755 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
7759 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
7762 #endif /* _T4FW_INTERFACE_H_ */