2 * Copyright (c) 2012-2017 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _T4FW_INTERFACE_H_
31 #define _T4FW_INTERFACE_H_
33 /******************************************************************************
34 * R E T U R N V A L U E S
35 ********************************/
38 FW_SUCCESS = 0, /* completed successfully */
39 FW_EPERM = 1, /* operation not permitted */
40 FW_ENOENT = 2, /* no such file or directory */
41 FW_EIO = 5, /* input/output error; hw bad */
42 FW_ENOEXEC = 8, /* exec format error; inv microcode */
43 FW_EAGAIN = 11, /* try again */
44 FW_ENOMEM = 12, /* out of memory */
45 FW_EFAULT = 14, /* bad address; fw bad */
46 FW_EBUSY = 16, /* resource busy */
47 FW_EEXIST = 17, /* file exists */
48 FW_ENODEV = 19, /* no such device */
49 FW_EINVAL = 22, /* invalid argument */
50 FW_ENOSPC = 28, /* no space left on device */
51 FW_ENOSYS = 38, /* functionality not implemented */
52 FW_ENODATA = 61, /* no data available */
53 FW_EPROTO = 71, /* protocol error */
54 FW_EADDRINUSE = 98, /* address already in use */
55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
56 FW_ENETDOWN = 100, /* network is down */
57 FW_ENETUNREACH = 101, /* network is unreachable */
58 FW_ENOBUFS = 105, /* no buffer space available */
59 FW_ETIMEDOUT = 110, /* timeout */
60 FW_EINPROGRESS = 115, /* fw internal */
61 FW_SCSI_ABORT_REQUESTED = 128, /* */
62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
63 FW_SCSI_ABORTED = 130, /* */
64 FW_SCSI_CLOSE_REQUESTED = 131, /* */
65 FW_ERR_LINK_DOWN = 132, /* */
66 FW_RDEV_NOT_READY = 133, /* */
67 FW_ERR_RDEV_LOST = 134, /* */
68 FW_ERR_RDEV_LOGO = 135, /* */
69 FW_FCOE_NO_XCHG = 136, /* */
70 FW_SCSI_RSP_ERR = 137, /* */
71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
73 FW_SCSI_OVER_FLOW_ERR = 140, /* */
74 FW_SCSI_DDP_ERR = 141, /* DDP error*/
75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
78 /******************************************************************************
79 * M E M O R Y T Y P E s
80 ******************************/
83 FW_MEMTYPE_EDC0 = 0x0,
84 FW_MEMTYPE_EDC1 = 0x1,
85 FW_MEMTYPE_EXTMEM = 0x2,
86 FW_MEMTYPE_FLASH = 0x4,
87 FW_MEMTYPE_INTERNAL = 0x5,
88 FW_MEMTYPE_EXTMEM1 = 0x6,
92 /******************************************************************************
93 * W O R K R E Q U E S T s
94 ********************************/
101 FW_ETH_TX_PKT_WR = 0x08,
102 FW_ETH_TX_PKT2_WR = 0x44,
103 FW_ETH_TX_PKTS_WR = 0x09,
104 FW_ETH_TX_PKTS2_WR = 0x78,
105 FW_ETH_TX_EO_WR = 0x1c,
106 FW_EQ_FLUSH_WR = 0x1b,
107 FW_OFLD_CONNECTION_WR = 0x2f,
109 FW_OFLD_TX_DATA_WR = 0x0b,
111 FW_ETH_TX_PKT_VM_WR = 0x11,
113 FW_RI_RDMA_WRITE_WR = 0x14,
114 FW_RI_SEND_WR = 0x15,
115 FW_RI_RDMA_READ_WR = 0x16,
116 FW_RI_RECV_WR = 0x17,
117 FW_RI_BIND_MW_WR = 0x18,
118 FW_RI_FR_NSMR_WR = 0x19,
119 FW_RI_FR_NSMR_TPTE_WR = 0x20,
120 FW_RI_INV_LSTAG_WR = 0x1a,
121 FW_RI_SEND_IMMEDIATE_WR = 0x15,
122 FW_RI_ATOMIC_WR = 0x16,
124 FW_CHNET_IFCONF_WR = 0x6b,
126 FW_FOISCSI_NODE_WR = 0x60,
127 FW_FOISCSI_CTRL_WR = 0x6a,
128 FW_FOISCSI_CHAP_WR = 0x6c,
129 FW_FCOE_ELS_CT_WR = 0x30,
130 FW_SCSI_WRITE_WR = 0x31,
131 FW_SCSI_READ_WR = 0x32,
132 FW_SCSI_CMD_WR = 0x33,
133 FW_SCSI_ABRT_CLS_WR = 0x34,
134 FW_SCSI_TGT_ACC_WR = 0x35,
135 FW_SCSI_TGT_XMIT_WR = 0x36,
136 FW_SCSI_TGT_RSP_WR = 0x37,
137 FW_POFCOE_TCB_WR = 0x42,
138 FW_POFCOE_ULPTX_WR = 0x43,
139 FW_ISCSI_TX_DATA_WR = 0x45,
140 FW_PTP_TX_PKT_WR = 0x46,
141 FW_TLSTX_DATA_WR = 0x68,
142 FW_CRYPTO_LOOKASIDE_WR = 0x6d,
143 FW_COiSCSI_TGT_WR = 0x70,
144 FW_COiSCSI_TGT_CONN_WR = 0x71,
145 FW_COiSCSI_TGT_XMIT_WR = 0x72,
147 FW_ISNS_XMIT_WR = 0x76,
148 FW_FILTER2_WR = 0x77,
153 * Generic work request header flit0
160 /* work request opcode (hi)
162 #define S_FW_WR_OP 24
163 #define M_FW_WR_OP 0xff
164 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
165 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
167 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
169 #define S_FW_WR_ATOMIC 23
170 #define M_FW_WR_ATOMIC 0x1
171 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
172 #define G_FW_WR_ATOMIC(x) \
173 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
174 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U)
176 /* flush flag (hi) - firmware flushes flushable work request buffered
177 * in the flow context.
179 #define S_FW_WR_FLUSH 22
180 #define M_FW_WR_FLUSH 0x1
181 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH)
182 #define G_FW_WR_FLUSH(x) \
183 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
184 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U)
186 /* completion flag (hi) - firmware generates a cpl_fw6_ack
188 #define S_FW_WR_COMPL 21
189 #define M_FW_WR_COMPL 0x1
190 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL)
191 #define G_FW_WR_COMPL(x) \
192 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
193 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U)
196 /* work request immediate data lengh (hi)
198 #define S_FW_WR_IMMDLEN 0
199 #define M_FW_WR_IMMDLEN 0xff
200 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
201 #define G_FW_WR_IMMDLEN(x) \
202 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
204 /* egress queue status update to associated ingress queue entry (lo)
206 #define S_FW_WR_EQUIQ 31
207 #define M_FW_WR_EQUIQ 0x1
208 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ)
209 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
210 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U)
212 /* egress queue status update to egress queue status entry (lo)
214 #define S_FW_WR_EQUEQ 30
215 #define M_FW_WR_EQUEQ 0x1
216 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
217 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
218 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
220 /* flow context identifier (lo)
222 #define S_FW_WR_FLOWID 8
223 #define M_FW_WR_FLOWID 0xfffff
224 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
225 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
227 /* length in units of 16-bytes (lo)
229 #define S_FW_WR_LEN16 0
230 #define M_FW_WR_LEN16 0xff
231 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
232 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
235 __be32 op_to_fragoff16;
240 #define S_FW_FRAG_WR_EOF 15
241 #define M_FW_FRAG_WR_EOF 0x1
242 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF)
243 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
244 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U)
246 #define S_FW_FRAG_WR_FRAGOFF16 8
247 #define M_FW_FRAG_WR_FRAGOFF16 0x7f
248 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16)
249 #define G_FW_FRAG_WR_FRAGOFF16(x) \
250 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
252 /* valid filter configurations for compressed tuple
253 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
254 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
255 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
256 * OV - Outer VLAN/VNIC_ID,
258 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3
259 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3
260 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B
261 #define HW_TPL_FR_MT_M_OV_P_FC 0x387
262 #define HW_TPL_FR_MT_E_PR_T 0x370
263 #define HW_TPL_FR_MT_E_PR_P_FC 0X363
264 #define HW_TPL_FR_MT_E_T_P_FC 0X353
265 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
266 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
267 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B
268 #define HW_TPL_FR_MT_T_OV_P_FC 0X317
269 #define HW_TPL_FR_M_E_PR_FC 0X2E1
270 #define HW_TPL_FR_M_E_T_FC 0X2D1
271 #define HW_TPL_FR_M_PR_IV_FC 0X2A9
272 #define HW_TPL_FR_M_PR_OV_FC 0X2A5
273 #define HW_TPL_FR_M_T_IV_FC 0X299
274 #define HW_TPL_FR_M_T_OV_FC 0X295
275 #define HW_TPL_FR_E_PR_T_P 0X272
276 #define HW_TPL_FR_E_PR_T_FC 0X271
277 #define HW_TPL_FR_E_IV_FC 0X249
278 #define HW_TPL_FR_E_OV_FC 0X245
279 #define HW_TPL_FR_PR_T_IV_FC 0X239
280 #define HW_TPL_FR_PR_T_OV_FC 0X235
281 #define HW_TPL_FR_IV_OV_FC 0X20D
282 #define HW_TPL_MT_M_E_PR 0X1E0
283 #define HW_TPL_MT_M_E_T 0X1D0
284 #define HW_TPL_MT_E_PR_T_FC 0X171
285 #define HW_TPL_MT_E_IV 0X148
286 #define HW_TPL_MT_E_OV 0X144
287 #define HW_TPL_MT_PR_T_IV 0X138
288 #define HW_TPL_MT_PR_T_OV 0X134
289 #define HW_TPL_M_E_PR_P 0X0E2
290 #define HW_TPL_M_E_T_P 0X0D2
291 #define HW_TPL_E_PR_T_P_FC 0X073
292 #define HW_TPL_E_IV_P 0X04A
293 #define HW_TPL_E_OV_P 0X046
294 #define HW_TPL_PR_T_IV_P 0X03A
295 #define HW_TPL_PR_T_OV_P 0X036
297 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
298 enum fw_filter_wr_cookie {
299 FW_FILTER_WR_SUCCESS,
300 FW_FILTER_WR_FLT_ADDED,
301 FW_FILTER_WR_FLT_DELETED,
302 FW_FILTER_WR_SMT_TBL_FULL,
306 enum fw_filter_wr_nat_mode {
307 FW_FILTER_WR_NATMODE_NONE = 0,
308 FW_FILTER_WR_NATMODE_DIP ,
309 FW_FILTER_WR_NATMODE_DIPDP,
310 FW_FILTER_WR_NATMODE_DIPDPSIP,
311 FW_FILTER_WR_NATMODE_DIPDPSP,
312 FW_FILTER_WR_NATMODE_SIPSP,
313 FW_FILTER_WR_NATMODE_DIPSIPSP,
314 FW_FILTER_WR_NATMODE_FOURTUPLE,
317 struct fw_filter_wr {
322 __be32 del_filter_to_l2tix;
325 __u8 frag_to_ovlan_vldm;
327 __be16 rx_chan_rx_rpl_iq;
328 __be32 maci_to_matchtypem;
349 struct fw_filter2_wr {
354 __be32 del_filter_to_l2tix;
357 __u8 frag_to_ovlan_vldm;
359 __be16 rx_chan_rx_rpl_iq;
360 __be32 maci_to_matchtypem;
380 __u8 filter_type_swapmac;
381 __u8 natmode_to_ulp_type;
394 #define S_FW_FILTER_WR_TID 12
395 #define M_FW_FILTER_WR_TID 0xfffff
396 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
397 #define G_FW_FILTER_WR_TID(x) \
398 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
400 #define S_FW_FILTER_WR_RQTYPE 11
401 #define M_FW_FILTER_WR_RQTYPE 0x1
402 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
403 #define G_FW_FILTER_WR_RQTYPE(x) \
404 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
405 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
407 #define S_FW_FILTER_WR_NOREPLY 10
408 #define M_FW_FILTER_WR_NOREPLY 0x1
409 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
410 #define G_FW_FILTER_WR_NOREPLY(x) \
411 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
412 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
414 #define S_FW_FILTER_WR_IQ 0
415 #define M_FW_FILTER_WR_IQ 0x3ff
416 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
417 #define G_FW_FILTER_WR_IQ(x) \
418 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
420 #define S_FW_FILTER_WR_DEL_FILTER 31
421 #define M_FW_FILTER_WR_DEL_FILTER 0x1
422 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
423 #define G_FW_FILTER_WR_DEL_FILTER(x) \
424 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
425 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
427 #define S_FW_FILTER_WR_RPTTID 25
428 #define M_FW_FILTER_WR_RPTTID 0x1
429 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
430 #define G_FW_FILTER_WR_RPTTID(x) \
431 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
432 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
434 #define S_FW_FILTER_WR_DROP 24
435 #define M_FW_FILTER_WR_DROP 0x1
436 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
437 #define G_FW_FILTER_WR_DROP(x) \
438 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
439 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
441 #define S_FW_FILTER_WR_DIRSTEER 23
442 #define M_FW_FILTER_WR_DIRSTEER 0x1
443 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
444 #define G_FW_FILTER_WR_DIRSTEER(x) \
445 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
446 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
448 #define S_FW_FILTER_WR_MASKHASH 22
449 #define M_FW_FILTER_WR_MASKHASH 0x1
450 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
451 #define G_FW_FILTER_WR_MASKHASH(x) \
452 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
453 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
455 #define S_FW_FILTER_WR_DIRSTEERHASH 21
456 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
457 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
458 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
459 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
460 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
462 #define S_FW_FILTER_WR_LPBK 20
463 #define M_FW_FILTER_WR_LPBK 0x1
464 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
465 #define G_FW_FILTER_WR_LPBK(x) \
466 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
467 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
469 #define S_FW_FILTER_WR_DMAC 19
470 #define M_FW_FILTER_WR_DMAC 0x1
471 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
472 #define G_FW_FILTER_WR_DMAC(x) \
473 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
474 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
476 #define S_FW_FILTER_WR_SMAC 18
477 #define M_FW_FILTER_WR_SMAC 0x1
478 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
479 #define G_FW_FILTER_WR_SMAC(x) \
480 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
481 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
483 #define S_FW_FILTER_WR_INSVLAN 17
484 #define M_FW_FILTER_WR_INSVLAN 0x1
485 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
486 #define G_FW_FILTER_WR_INSVLAN(x) \
487 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
488 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
490 #define S_FW_FILTER_WR_RMVLAN 16
491 #define M_FW_FILTER_WR_RMVLAN 0x1
492 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
493 #define G_FW_FILTER_WR_RMVLAN(x) \
494 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
495 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
497 #define S_FW_FILTER_WR_HITCNTS 15
498 #define M_FW_FILTER_WR_HITCNTS 0x1
499 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
500 #define G_FW_FILTER_WR_HITCNTS(x) \
501 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
502 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
504 #define S_FW_FILTER_WR_TXCHAN 13
505 #define M_FW_FILTER_WR_TXCHAN 0x3
506 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
507 #define G_FW_FILTER_WR_TXCHAN(x) \
508 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
510 #define S_FW_FILTER_WR_PRIO 12
511 #define M_FW_FILTER_WR_PRIO 0x1
512 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
513 #define G_FW_FILTER_WR_PRIO(x) \
514 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
515 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
517 #define S_FW_FILTER_WR_L2TIX 0
518 #define M_FW_FILTER_WR_L2TIX 0xfff
519 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
520 #define G_FW_FILTER_WR_L2TIX(x) \
521 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
523 #define S_FW_FILTER_WR_FRAG 7
524 #define M_FW_FILTER_WR_FRAG 0x1
525 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
526 #define G_FW_FILTER_WR_FRAG(x) \
527 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
528 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
530 #define S_FW_FILTER_WR_FRAGM 6
531 #define M_FW_FILTER_WR_FRAGM 0x1
532 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
533 #define G_FW_FILTER_WR_FRAGM(x) \
534 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
535 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
537 #define S_FW_FILTER_WR_IVLAN_VLD 5
538 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
539 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
540 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
541 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
542 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
544 #define S_FW_FILTER_WR_OVLAN_VLD 4
545 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
546 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
547 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
548 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
549 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
551 #define S_FW_FILTER_WR_IVLAN_VLDM 3
552 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
553 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
554 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
555 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
556 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
558 #define S_FW_FILTER_WR_OVLAN_VLDM 2
559 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
560 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
561 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
562 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
563 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
565 #define S_FW_FILTER_WR_RX_CHAN 15
566 #define M_FW_FILTER_WR_RX_CHAN 0x1
567 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
568 #define G_FW_FILTER_WR_RX_CHAN(x) \
569 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
570 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
572 #define S_FW_FILTER_WR_RX_RPL_IQ 0
573 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
574 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
575 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
576 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
578 #define S_FW_FILTER2_WR_FILTER_TYPE 1
579 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1
580 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE)
581 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \
582 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
583 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U)
585 #define S_FW_FILTER2_WR_SWAPMAC 0
586 #define M_FW_FILTER2_WR_SWAPMAC 0x1
587 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
588 #define G_FW_FILTER2_WR_SWAPMAC(x) \
589 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
590 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U)
592 #define S_FW_FILTER2_WR_NATMODE 5
593 #define M_FW_FILTER2_WR_NATMODE 0x7
594 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
595 #define G_FW_FILTER2_WR_NATMODE(x) \
596 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
598 #define S_FW_FILTER2_WR_NATFLAGCHECK 4
599 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1
600 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
601 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \
602 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
603 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U)
605 #define S_FW_FILTER2_WR_ULP_TYPE 0
606 #define M_FW_FILTER2_WR_ULP_TYPE 0xf
607 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
608 #define G_FW_FILTER2_WR_ULP_TYPE(x) \
609 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
611 #define S_FW_FILTER_WR_MACI 23
612 #define M_FW_FILTER_WR_MACI 0x1ff
613 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
614 #define G_FW_FILTER_WR_MACI(x) \
615 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
617 #define S_FW_FILTER_WR_MACIM 14
618 #define M_FW_FILTER_WR_MACIM 0x1ff
619 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
620 #define G_FW_FILTER_WR_MACIM(x) \
621 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
623 #define S_FW_FILTER_WR_FCOE 13
624 #define M_FW_FILTER_WR_FCOE 0x1
625 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
626 #define G_FW_FILTER_WR_FCOE(x) \
627 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
628 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
630 #define S_FW_FILTER_WR_FCOEM 12
631 #define M_FW_FILTER_WR_FCOEM 0x1
632 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
633 #define G_FW_FILTER_WR_FCOEM(x) \
634 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
635 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
637 #define S_FW_FILTER_WR_PORT 9
638 #define M_FW_FILTER_WR_PORT 0x7
639 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
640 #define G_FW_FILTER_WR_PORT(x) \
641 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
643 #define S_FW_FILTER_WR_PORTM 6
644 #define M_FW_FILTER_WR_PORTM 0x7
645 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
646 #define G_FW_FILTER_WR_PORTM(x) \
647 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
649 #define S_FW_FILTER_WR_MATCHTYPE 3
650 #define M_FW_FILTER_WR_MATCHTYPE 0x7
651 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
652 #define G_FW_FILTER_WR_MATCHTYPE(x) \
653 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
655 #define S_FW_FILTER_WR_MATCHTYPEM 0
656 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
657 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
658 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
659 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
668 __be32 op_to_immdlen;
673 struct fw_eth_tx_pkt_wr {
675 __be32 equiq_to_len16;
679 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
680 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
681 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
682 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
683 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
685 struct fw_eth_tx_pkt2_wr {
687 __be32 equiq_to_len16;
689 __be32 L4ChkDisable_to_IpHdrLen;
692 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
693 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
694 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
695 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
696 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
698 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
699 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
700 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
701 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
702 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
703 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
704 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
705 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
706 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
708 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
709 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
710 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
711 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
712 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
713 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
714 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
715 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
716 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
718 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28
719 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
720 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
721 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
722 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
723 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
725 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
726 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
727 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
728 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
729 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
731 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
732 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
733 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
734 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
735 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
737 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
738 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
739 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
740 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
741 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
743 struct fw_eth_tx_pkts_wr {
745 __be32 equiq_to_len16;
752 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0
753 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff
754 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
755 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \
756 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
758 struct fw_eth_tx_pkt_ptp_wr {
760 __be32 equiq_to_len16;
764 enum fw_eth_tx_eo_type {
765 FW_ETH_TX_EO_TYPE_UDPSEG,
766 FW_ETH_TX_EO_TYPE_TCPSEG,
767 FW_ETH_TX_EO_TYPE_NVGRESEG,
768 FW_ETH_TX_EO_TYPE_VXLANSEG,
769 FW_ETH_TX_EO_TYPE_GENEVESEG,
772 struct fw_eth_tx_eo_wr {
774 __be32 equiq_to_len16;
777 struct fw_eth_tx_eo_udpseg {
788 struct fw_eth_tx_eo_tcpseg {
799 struct fw_eth_tx_eo_nvgreseg {
809 struct fw_eth_tx_eo_vxlanseg {
820 struct fw_eth_tx_eo_geneveseg {
833 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0
834 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
835 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
836 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
837 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
839 #define S_FW_ETH_TX_EO_WR_TSCLK 6
840 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3
841 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
842 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \
843 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
845 #define S_FW_ETH_TX_EO_WR_TSOFF 0
846 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
847 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
848 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \
849 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
851 struct fw_eq_flush_wr {
854 __be32 equiq_to_len16;
858 struct fw_ofld_connection_wr {
864 struct fw_ofld_connection_le {
870 union fw_ofld_connection_leip {
871 struct fw_ofld_connection_le_ipv4 {
878 struct fw_ofld_connection_le_ipv6 {
886 struct fw_ofld_connection_tcb {
887 __be32 t_state_to_astid;
888 __be16 cplrxdataack_cplpassacceptrpl;
900 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
901 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
902 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
903 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
904 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
905 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
906 M_FW_OFLD_CONNECTION_WR_VERSION)
907 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)
909 #define S_FW_OFLD_CONNECTION_WR_CPL 30
910 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
911 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
912 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
913 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
914 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
916 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
917 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
918 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
919 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
920 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
921 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
922 M_FW_OFLD_CONNECTION_WR_T_STATE)
924 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
925 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
926 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
927 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
928 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
929 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
930 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
932 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
933 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
934 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
935 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
936 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
937 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
939 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
940 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
941 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
942 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
943 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
944 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
945 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
946 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
947 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
949 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
950 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
951 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
952 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
953 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
954 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
955 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
956 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
957 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
959 enum fw_flowc_mnem_tcpstate {
960 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
961 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
962 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
963 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
964 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
965 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
966 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
967 * will resend FIN - equiv ESTAB
969 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
970 * will resend FIN but have
973 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
974 * will resend FIN but have
977 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
980 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
983 enum fw_flowc_mnem_eostate {
984 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
985 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
986 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
987 * outstanding payload
989 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
990 * discarding outstanding payload
995 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
996 FW_FLOWC_MNEM_CH = 1,
997 FW_FLOWC_MNEM_PORT = 2,
998 FW_FLOWC_MNEM_IQID = 3,
999 FW_FLOWC_MNEM_SNDNXT = 4,
1000 FW_FLOWC_MNEM_RCVNXT = 5,
1001 FW_FLOWC_MNEM_SNDBUF = 6,
1002 FW_FLOWC_MNEM_MSS = 7,
1003 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
1004 FW_FLOWC_MNEM_TCPSTATE = 9,
1005 FW_FLOWC_MNEM_EOSTATE = 10,
1006 FW_FLOWC_MNEM_SCHEDCLASS = 11,
1007 FW_FLOWC_MNEM_DCBPRIO = 12,
1008 FW_FLOWC_MNEM_SND_SCALE = 13,
1009 FW_FLOWC_MNEM_RCV_SCALE = 14,
1010 FW_FLOWC_MNEM_ULP_MODE = 15,
1011 FW_FLOWC_MNEM_MAX = 16,
1014 struct fw_flowc_mnemval {
1020 struct fw_flowc_wr {
1021 __be32 op_to_nparams;
1022 __be32 flowid_len16;
1023 #ifndef C99_NOT_SUPPORTED
1024 struct fw_flowc_mnemval mnemval[0];
1028 #define S_FW_FLOWC_WR_NPARAMS 0
1029 #define M_FW_FLOWC_WR_NPARAMS 0xff
1030 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS)
1031 #define G_FW_FLOWC_WR_NPARAMS(x) \
1032 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1034 struct fw_ofld_tx_data_wr {
1035 __be32 op_to_immdlen;
1036 __be32 flowid_len16;
1038 __be32 lsodisable_to_flags;
1041 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
1042 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
1043 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1044 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1045 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1046 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1047 M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1048 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1050 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
1051 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
1052 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1053 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1054 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1055 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1056 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1058 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
1059 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
1060 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1061 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1062 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1063 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1064 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1065 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
1066 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1068 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0
1069 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff
1070 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1071 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \
1072 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1075 /* Use fw_ofld_tx_data_wr structure */
1076 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10
1077 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff
1078 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1079 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1080 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1081 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1083 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9
1084 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1
1085 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1086 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1087 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1088 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1089 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1090 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \
1091 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1093 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8
1094 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1
1095 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1096 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1097 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1098 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1099 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1100 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \
1101 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1103 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7
1104 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1
1105 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1106 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1107 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1108 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1109 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1110 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \
1111 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1113 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6
1114 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1
1115 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1116 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1117 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1118 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1119 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1120 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \
1121 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1123 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0
1124 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f
1125 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1126 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1127 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1128 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1133 __be64 cookie_daddr;
1136 #define S_FW_CMD_WR_DMA 17
1137 #define M_FW_CMD_WR_DMA 0x1
1138 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA)
1139 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1140 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)
1142 struct fw_eth_tx_pkt_vm_wr {
1144 __be32 equiq_to_len16;
1152 /******************************************************************************
1153 * R I W O R K R E Q U E S T s
1154 **************************************/
1156 enum fw_ri_wr_opcode {
1157 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
1158 FW_RI_READ_REQ = 0x1,
1159 FW_RI_READ_RESP = 0x2,
1161 FW_RI_SEND_WITH_INV = 0x4,
1162 FW_RI_SEND_WITH_SE = 0x5,
1163 FW_RI_SEND_WITH_SE_INV = 0x6,
1164 FW_RI_TERMINATE = 0x7,
1165 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
1166 FW_RI_BIND_MW = 0x9,
1167 FW_RI_FAST_REGISTER = 0xa,
1168 FW_RI_LOCAL_INV = 0xb,
1169 FW_RI_QP_MODIFY = 0xc,
1171 FW_RI_RECEIVE = 0xe,
1173 FW_RI_SEND_IMMEDIATE = 0x8,
1174 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9,
1175 FW_RI_ATOMIC_REQUEST = 0xa,
1176 FW_RI_ATOMIC_RESPONSE = 0xb,
1178 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */
1179 FW_RI_FAST_REGISTER = 0xd,
1180 FW_RI_LOCAL_INV = 0xe,
1182 FW_RI_SGE_EC_CR_RETURN = 0xf,
1183 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT,
1186 enum fw_ri_wr_flags {
1187 FW_RI_COMPLETION_FLAG = 0x01,
1188 FW_RI_NOTIFICATION_FLAG = 0x02,
1189 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
1190 FW_RI_READ_FENCE_FLAG = 0x08,
1191 FW_RI_LOCAL_FENCE_FLAG = 0x10,
1192 FW_RI_RDMA_READ_INVALIDATE = 0x20,
1193 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
1196 enum fw_ri_mpa_attrs {
1197 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
1198 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
1199 FW_RI_MPA_CRC_ENABLE = 0x04,
1200 FW_RI_MPA_IETF_ENABLE = 0x08
1203 enum fw_ri_qp_caps {
1204 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
1205 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
1206 FW_RI_QP_BIND_ENABLE = 0x04,
1207 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
1208 FW_RI_QP_STAG0_ENABLE = 0x10,
1209 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1212 enum fw_ri_addr_type {
1213 FW_RI_ZERO_BASED_TO = 0x00,
1214 FW_RI_VA_BASED_TO = 0x01
1217 enum fw_ri_mem_perms {
1218 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
1219 FW_RI_MEM_ACCESS_REM_READ = 0x02,
1220 FW_RI_MEM_ACCESS_REM = 0x03,
1221 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
1222 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
1223 FW_RI_MEM_ACCESS_LOCAL = 0x0C
1226 enum fw_ri_stag_type {
1227 FW_RI_STAG_NSMR = 0x00,
1228 FW_RI_STAG_SMR = 0x01,
1229 FW_RI_STAG_MW = 0x02,
1230 FW_RI_STAG_MW_RELAXED = 0x03
1233 enum fw_ri_data_op {
1234 FW_RI_DATA_IMMD = 0x81,
1235 FW_RI_DATA_DSGL = 0x82,
1236 FW_RI_DATA_ISGL = 0x83
1239 enum fw_ri_sgl_depth {
1240 FW_RI_SGL_DEPTH_MAX_SQ = 16,
1241 FW_RI_SGL_DEPTH_MAX_RQ = 4
1244 enum fw_ri_cqe_err {
1245 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */
1246 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */
1247 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */
1248 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */
1249 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */
1250 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */
1251 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */
1252 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1253 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1254 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */
1255 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1256 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */
1257 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */
1258 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */
1259 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */
1260 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */
1261 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */
1262 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */
1263 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */
1264 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */
1265 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */
1266 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */
1267 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1268 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */
1269 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */
1270 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */
1271 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */
1272 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */
1276 struct fw_ri_dsge_pair {
1287 #ifndef C99_NOT_SUPPORTED
1288 struct fw_ri_dsge_pair sge[0];
1303 #ifndef C99_NOT_SUPPORTED
1304 struct fw_ri_sge sge[0];
1313 #ifndef C99_NOT_SUPPORTED
1319 __be32 valid_to_pdid;
1320 __be32 locread_to_qpid;
1321 __be32 nosnoop_pbladdr;
1325 __be32 dca_mwbcnt_pstag;
1329 #define S_FW_RI_TPTE_VALID 31
1330 #define M_FW_RI_TPTE_VALID 0x1
1331 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
1332 #define G_FW_RI_TPTE_VALID(x) \
1333 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1334 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
1336 #define S_FW_RI_TPTE_STAGKEY 23
1337 #define M_FW_RI_TPTE_STAGKEY 0xff
1338 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
1339 #define G_FW_RI_TPTE_STAGKEY(x) \
1340 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1342 #define S_FW_RI_TPTE_STAGSTATE 22
1343 #define M_FW_RI_TPTE_STAGSTATE 0x1
1344 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
1345 #define G_FW_RI_TPTE_STAGSTATE(x) \
1346 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1347 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
1349 #define S_FW_RI_TPTE_STAGTYPE 20
1350 #define M_FW_RI_TPTE_STAGTYPE 0x3
1351 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
1352 #define G_FW_RI_TPTE_STAGTYPE(x) \
1353 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1355 #define S_FW_RI_TPTE_PDID 0
1356 #define M_FW_RI_TPTE_PDID 0xfffff
1357 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
1358 #define G_FW_RI_TPTE_PDID(x) \
1359 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1361 #define S_FW_RI_TPTE_PERM 28
1362 #define M_FW_RI_TPTE_PERM 0xf
1363 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
1364 #define G_FW_RI_TPTE_PERM(x) \
1365 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1367 #define S_FW_RI_TPTE_REMINVDIS 27
1368 #define M_FW_RI_TPTE_REMINVDIS 0x1
1369 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
1370 #define G_FW_RI_TPTE_REMINVDIS(x) \
1371 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1372 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
1374 #define S_FW_RI_TPTE_ADDRTYPE 26
1375 #define M_FW_RI_TPTE_ADDRTYPE 1
1376 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
1377 #define G_FW_RI_TPTE_ADDRTYPE(x) \
1378 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1379 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
1381 #define S_FW_RI_TPTE_MWBINDEN 25
1382 #define M_FW_RI_TPTE_MWBINDEN 0x1
1383 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
1384 #define G_FW_RI_TPTE_MWBINDEN(x) \
1385 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1386 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
1388 #define S_FW_RI_TPTE_PS 20
1389 #define M_FW_RI_TPTE_PS 0x1f
1390 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
1391 #define G_FW_RI_TPTE_PS(x) \
1392 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1394 #define S_FW_RI_TPTE_QPID 0
1395 #define M_FW_RI_TPTE_QPID 0xfffff
1396 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
1397 #define G_FW_RI_TPTE_QPID(x) \
1398 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1400 #define S_FW_RI_TPTE_NOSNOOP 31
1401 #define M_FW_RI_TPTE_NOSNOOP 0x1
1402 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
1403 #define G_FW_RI_TPTE_NOSNOOP(x) \
1404 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1405 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
1407 #define S_FW_RI_TPTE_PBLADDR 0
1408 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff
1409 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
1410 #define G_FW_RI_TPTE_PBLADDR(x) \
1411 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1413 #define S_FW_RI_TPTE_DCA 24
1414 #define M_FW_RI_TPTE_DCA 0x1f
1415 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
1416 #define G_FW_RI_TPTE_DCA(x) \
1417 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1419 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0
1420 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
1421 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
1422 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1423 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
1424 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1426 enum fw_ri_cqe_rxtx {
1427 FW_RI_CQE_RXTX_RX = 0x0,
1428 FW_RI_CQE_RXTX_TX = 0x1,
1434 __be32 qpid_n_stat_rxtx_type;
1440 __be32 qpid_n_stat_rxtx_type;
1445 struct fw_ri_rcqe_imm {
1446 __be32 qpid_n_stat_rxtx_type;
1455 #define S_FW_RI_CQE_QPID 12
1456 #define M_FW_RI_CQE_QPID 0xfffff
1457 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID)
1458 #define G_FW_RI_CQE_QPID(x) \
1459 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
1461 #define S_FW_RI_CQE_NOTIFY 10
1462 #define M_FW_RI_CQE_NOTIFY 0x1
1463 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1464 #define G_FW_RI_CQE_NOTIFY(x) \
1465 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
1467 #define S_FW_RI_CQE_STATUS 5
1468 #define M_FW_RI_CQE_STATUS 0x1f
1469 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1470 #define G_FW_RI_CQE_STATUS(x) \
1471 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
1474 #define S_FW_RI_CQE_RXTX 4
1475 #define M_FW_RI_CQE_RXTX 0x1
1476 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX)
1477 #define G_FW_RI_CQE_RXTX(x) \
1478 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
1480 #define S_FW_RI_CQE_TYPE 0
1481 #define M_FW_RI_CQE_TYPE 0xf
1482 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE)
1483 #define G_FW_RI_CQE_TYPE(x) \
1484 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
1486 enum fw_ri_res_type {
1499 union fw_ri_restype {
1500 struct fw_ri_res_sqrq {
1506 __be32 fetchszm_to_iqid;
1507 __be32 dcaen_to_eqsize;
1510 struct fw_ri_res_cq {
1516 __be32 iqandst_to_iqandstindex;
1517 __be16 iqdroprss_to_iqesize;
1524 struct fw_ri_res_srq {
1530 __be32 fetchszm_to_iqid;
1531 __be32 dcaen_to_eqsize;
1541 struct fw_ri_res_wr {
1545 #ifndef C99_NOT_SUPPORTED
1546 struct fw_ri_res res[0];
1550 #define S_FW_RI_RES_WR_VFN 8
1551 #define M_FW_RI_RES_WR_VFN 0xff
1552 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN)
1553 #define G_FW_RI_RES_WR_VFN(x) \
1554 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1556 #define S_FW_RI_RES_WR_NRES 0
1557 #define M_FW_RI_RES_WR_NRES 0xff
1558 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
1559 #define G_FW_RI_RES_WR_NRES(x) \
1560 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1562 #define S_FW_RI_RES_WR_FETCHSZM 26
1563 #define M_FW_RI_RES_WR_FETCHSZM 0x1
1564 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
1565 #define G_FW_RI_RES_WR_FETCHSZM(x) \
1566 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1567 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
1569 #define S_FW_RI_RES_WR_STATUSPGNS 25
1570 #define M_FW_RI_RES_WR_STATUSPGNS 0x1
1571 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
1572 #define G_FW_RI_RES_WR_STATUSPGNS(x) \
1573 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1574 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
1576 #define S_FW_RI_RES_WR_STATUSPGRO 24
1577 #define M_FW_RI_RES_WR_STATUSPGRO 0x1
1578 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
1579 #define G_FW_RI_RES_WR_STATUSPGRO(x) \
1580 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1581 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
1583 #define S_FW_RI_RES_WR_FETCHNS 23
1584 #define M_FW_RI_RES_WR_FETCHNS 0x1
1585 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
1586 #define G_FW_RI_RES_WR_FETCHNS(x) \
1587 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1588 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
1590 #define S_FW_RI_RES_WR_FETCHRO 22
1591 #define M_FW_RI_RES_WR_FETCHRO 0x1
1592 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
1593 #define G_FW_RI_RES_WR_FETCHRO(x) \
1594 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1595 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
1597 #define S_FW_RI_RES_WR_HOSTFCMODE 20
1598 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3
1599 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1600 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \
1601 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1603 #define S_FW_RI_RES_WR_CPRIO 19
1604 #define M_FW_RI_RES_WR_CPRIO 0x1
1605 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
1606 #define G_FW_RI_RES_WR_CPRIO(x) \
1607 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1608 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
1610 #define S_FW_RI_RES_WR_ONCHIP 18
1611 #define M_FW_RI_RES_WR_ONCHIP 0x1
1612 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
1613 #define G_FW_RI_RES_WR_ONCHIP(x) \
1614 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1615 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
1617 #define S_FW_RI_RES_WR_PCIECHN 16
1618 #define M_FW_RI_RES_WR_PCIECHN 0x3
1619 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
1620 #define G_FW_RI_RES_WR_PCIECHN(x) \
1621 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1623 #define S_FW_RI_RES_WR_IQID 0
1624 #define M_FW_RI_RES_WR_IQID 0xffff
1625 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
1626 #define G_FW_RI_RES_WR_IQID(x) \
1627 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1629 #define S_FW_RI_RES_WR_DCAEN 31
1630 #define M_FW_RI_RES_WR_DCAEN 0x1
1631 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
1632 #define G_FW_RI_RES_WR_DCAEN(x) \
1633 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1634 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
1636 #define S_FW_RI_RES_WR_DCACPU 26
1637 #define M_FW_RI_RES_WR_DCACPU 0x1f
1638 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
1639 #define G_FW_RI_RES_WR_DCACPU(x) \
1640 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1642 #define S_FW_RI_RES_WR_FBMIN 23
1643 #define M_FW_RI_RES_WR_FBMIN 0x7
1644 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
1645 #define G_FW_RI_RES_WR_FBMIN(x) \
1646 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1648 #define S_FW_RI_RES_WR_FBMAX 20
1649 #define M_FW_RI_RES_WR_FBMAX 0x7
1650 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
1651 #define G_FW_RI_RES_WR_FBMAX(x) \
1652 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1654 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19
1655 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
1656 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1657 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
1658 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1659 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1661 #define S_FW_RI_RES_WR_CIDXFTHRESH 16
1662 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
1663 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1664 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
1665 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1667 #define S_FW_RI_RES_WR_EQSIZE 0
1668 #define M_FW_RI_RES_WR_EQSIZE 0xffff
1669 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
1670 #define G_FW_RI_RES_WR_EQSIZE(x) \
1671 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1673 #define S_FW_RI_RES_WR_IQANDST 15
1674 #define M_FW_RI_RES_WR_IQANDST 0x1
1675 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
1676 #define G_FW_RI_RES_WR_IQANDST(x) \
1677 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1678 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
1680 #define S_FW_RI_RES_WR_IQANUS 14
1681 #define M_FW_RI_RES_WR_IQANUS 0x1
1682 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
1683 #define G_FW_RI_RES_WR_IQANUS(x) \
1684 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1685 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
1687 #define S_FW_RI_RES_WR_IQANUD 12
1688 #define M_FW_RI_RES_WR_IQANUD 0x3
1689 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
1690 #define G_FW_RI_RES_WR_IQANUD(x) \
1691 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1693 #define S_FW_RI_RES_WR_IQANDSTINDEX 0
1694 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
1695 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1696 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
1697 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1699 #define S_FW_RI_RES_WR_IQDROPRSS 15
1700 #define M_FW_RI_RES_WR_IQDROPRSS 0x1
1701 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
1702 #define G_FW_RI_RES_WR_IQDROPRSS(x) \
1703 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1704 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
1706 #define S_FW_RI_RES_WR_IQGTSMODE 14
1707 #define M_FW_RI_RES_WR_IQGTSMODE 0x1
1708 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
1709 #define G_FW_RI_RES_WR_IQGTSMODE(x) \
1710 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1711 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
1713 #define S_FW_RI_RES_WR_IQPCIECH 12
1714 #define M_FW_RI_RES_WR_IQPCIECH 0x3
1715 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
1716 #define G_FW_RI_RES_WR_IQPCIECH(x) \
1717 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1719 #define S_FW_RI_RES_WR_IQDCAEN 11
1720 #define M_FW_RI_RES_WR_IQDCAEN 0x1
1721 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
1722 #define G_FW_RI_RES_WR_IQDCAEN(x) \
1723 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1724 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
1726 #define S_FW_RI_RES_WR_IQDCACPU 6
1727 #define M_FW_RI_RES_WR_IQDCACPU 0x1f
1728 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
1729 #define G_FW_RI_RES_WR_IQDCACPU(x) \
1730 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1732 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
1733 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
1734 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1735 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1736 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1737 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1739 #define S_FW_RI_RES_WR_IQO 3
1740 #define M_FW_RI_RES_WR_IQO 0x1
1741 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
1742 #define G_FW_RI_RES_WR_IQO(x) \
1743 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1744 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
1746 #define S_FW_RI_RES_WR_IQCPRIO 2
1747 #define M_FW_RI_RES_WR_IQCPRIO 0x1
1748 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
1749 #define G_FW_RI_RES_WR_IQCPRIO(x) \
1750 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1751 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
1753 #define S_FW_RI_RES_WR_IQESIZE 0
1754 #define M_FW_RI_RES_WR_IQESIZE 0x3
1755 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
1756 #define G_FW_RI_RES_WR_IQESIZE(x) \
1757 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1759 #define S_FW_RI_RES_WR_IQNS 31
1760 #define M_FW_RI_RES_WR_IQNS 0x1
1761 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
1762 #define G_FW_RI_RES_WR_IQNS(x) \
1763 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1764 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
1766 #define S_FW_RI_RES_WR_IQRO 30
1767 #define M_FW_RI_RES_WR_IQRO 0x1
1768 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
1769 #define G_FW_RI_RES_WR_IQRO(x) \
1770 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1771 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
1773 struct fw_ri_rdma_write_wr {
1783 #ifndef C99_NOT_SUPPORTED
1785 struct fw_ri_immd immd_src[0];
1786 struct fw_ri_isgl isgl_src[0];
1791 struct fw_ri_send_wr {
1802 #ifndef C99_NOT_SUPPORTED
1804 struct fw_ri_immd immd_src[0];
1805 struct fw_ri_isgl isgl_src[0];
1810 #define S_FW_RI_SEND_WR_SENDOP 0
1811 #define M_FW_RI_SEND_WR_SENDOP 0xf
1812 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
1813 #define G_FW_RI_SEND_WR_SENDOP(x) \
1814 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1816 struct fw_ri_rdma_read_wr {
1833 struct fw_ri_recv_wr {
1839 struct fw_ri_isgl isgl;
1842 struct fw_ri_bind_mw_wr {
1848 __u8 qpbinde_to_dcacpu;
1860 #define S_FW_RI_BIND_MW_WR_QPBINDE 6
1861 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
1862 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1863 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
1864 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1865 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1867 #define S_FW_RI_BIND_MW_WR_NS 5
1868 #define M_FW_RI_BIND_MW_WR_NS 0x1
1869 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
1870 #define G_FW_RI_BIND_MW_WR_NS(x) \
1871 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1872 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
1874 #define S_FW_RI_BIND_MW_WR_DCACPU 0
1875 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
1876 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1877 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \
1878 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1880 struct fw_ri_fr_nsmr_wr {
1886 __u8 qpbinde_to_dcacpu;
1897 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6
1898 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
1899 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1900 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
1901 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1902 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1904 #define S_FW_RI_FR_NSMR_WR_NS 5
1905 #define M_FW_RI_FR_NSMR_WR_NS 0x1
1906 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
1907 #define G_FW_RI_FR_NSMR_WR_NS(x) \
1908 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1909 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
1911 #define S_FW_RI_FR_NSMR_WR_DCACPU 0
1912 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
1913 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1914 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
1915 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1917 struct fw_ri_fr_nsmr_tpte_wr {
1925 struct fw_ri_tpte tpte;
1929 struct fw_ri_inv_lstag_wr {
1939 struct fw_ri_send_immediate_wr {
1945 __be32 sendimmop_pkd;
1950 #ifndef C99_NOT_SUPPORTED
1951 struct fw_ri_immd immd_src[0];
1955 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
1956 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf
1957 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1958 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1959 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1960 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1961 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1963 enum fw_ri_atomic_op {
1964 FW_RI_ATOMIC_OP_FETCHADD,
1965 FW_RI_ATOMIC_OP_SWAP,
1966 FW_RI_ATOMIC_OP_CMDSWAP,
1969 struct fw_ri_atomic_wr {
1975 __be32 atomicop_pkd;
1982 __be32 addswap_data_hi;
1983 __be32 addswap_data_lo;
1984 __be32 addswap_mask_hi;
1985 __be32 addswap_mask_lo;
1986 __be32 compare_data_hi;
1987 __be32 compare_data_lo;
1988 __be32 compare_mask_hi;
1989 __be32 compare_mask_lo;
1993 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0
1994 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf
1995 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1996 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
1997 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1999 #define S_FW_RI_ATOMIC_WR_AOPCODE 0
2000 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf
2001 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
2002 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
2003 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
2008 FW_RI_TYPE_TERMINATE
2011 enum fw_ri_init_p2ptype {
2012 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
2013 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
2014 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
2015 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
2016 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
2017 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
2018 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
2021 enum fw_ri_init_rqeqid_srq {
2022 FW_RI_INIT_RQEQID_SRQ = 1 << 31,
2027 __be32 flowid_len16;
2032 __u8 mpareqbit_p2ptype;
2050 union fw_ri_init_p2p {
2051 struct fw_ri_rdma_write_wr write;
2052 struct fw_ri_rdma_read_wr read;
2053 struct fw_ri_send_wr send;
2061 struct fw_ri_terminate {
2070 #define S_FW_RI_WR_MPAREQBIT 7
2071 #define M_FW_RI_WR_MPAREQBIT 0x1
2072 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
2073 #define G_FW_RI_WR_MPAREQBIT(x) \
2074 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2075 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
2077 #define S_FW_RI_WR_0BRRBIT 6
2078 #define M_FW_RI_WR_0BRRBIT 0x1
2079 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT)
2080 #define G_FW_RI_WR_0BRRBIT(x) \
2081 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2082 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U)
2084 #define S_FW_RI_WR_P2PTYPE 0
2085 #define M_FW_RI_WR_P2PTYPE 0xf
2086 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
2087 #define G_FW_RI_WR_P2PTYPE(x) \
2088 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2090 /******************************************************************************
2091 * F O i S C S I W O R K R E Q U E S T s
2092 *********************************************/
2094 #define FW_FOISCSI_NAME_MAX_LEN 224
2095 #define FW_FOISCSI_ALIAS_MAX_LEN 224
2096 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128
2097 #define FW_FOISCSI_INIT_NODE_MAX 8
2099 enum fw_chnet_ifconf_wr_subop {
2100 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2102 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2103 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2105 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2106 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2108 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2109 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2111 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2112 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2114 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2115 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2117 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2118 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2120 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2121 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2123 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2124 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2125 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2127 FW_CHNET_IFCONF_WR_SUBOP_MAX,
2130 struct fw_chnet_ifconf_wr {
2132 __be32 flowid_len16;
2140 struct fw_chnet_ifconf_params {
2144 union fw_chnet_ifconf_addr_type {
2145 struct fw_chnet_ifconf_ipv4 {
2152 struct fw_chnet_ifconf_ipv6 {
2166 enum fw_foiscsi_node_type {
2167 FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2168 FW_FOISCSI_NODE_TYPE_TARGET,
2171 enum fw_foiscsi_session_type {
2172 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2173 FW_FOISCSI_SESSION_TYPE_NORMAL,
2176 enum fw_foiscsi_auth_policy {
2177 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2178 FW_FOISCSI_AUTH_POLICY_MUTUAL,
2181 enum fw_foiscsi_auth_method {
2182 FW_FOISCSI_AUTH_METHOD_NONE = 0,
2183 FW_FOISCSI_AUTH_METHOD_CHAP,
2184 FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2185 FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2188 enum fw_foiscsi_digest_type {
2189 FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2190 FW_FOISCSI_DIGEST_TYPE_CRC32,
2191 FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2192 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2195 enum fw_foiscsi_wr_subop {
2196 FW_FOISCSI_WR_SUBOP_ADD = 1,
2197 FW_FOISCSI_WR_SUBOP_DEL = 2,
2198 FW_FOISCSI_WR_SUBOP_MOD = 4,
2201 enum fw_foiscsi_ctrl_state {
2202 FW_FOISCSI_CTRL_STATE_FREE = 0,
2203 FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2204 FW_FOISCSI_CTRL_STATE_FAILED,
2205 FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2206 FW_FOISCSI_CTRL_STATE_REDIRECT,
2210 __be32 op_to_immdlen;
2211 __be32 alloc_to_len16;
2217 __be32 flags_to_assoc_flowid;
2219 struct fcoe_rdev_entry {
2228 __u8 rd_xfer_rdy_to_rport_type;
2230 __u8 org_proc_assoc_to_acc_rsp_code;
2231 __u8 enh_disc_to_tgt;
2238 struct iscsi_rdev_entry {
2249 __be16 first_brst_len;
2250 __be16 max_brst_len;
2252 __be16 def_time2wait;
2253 __be16 def_time2ret;
2254 __be16 nop_out_intrvl;
2266 #define S_FW_RDEV_WR_IMMDLEN 0
2267 #define M_FW_RDEV_WR_IMMDLEN 0xff
2268 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)
2269 #define G_FW_RDEV_WR_IMMDLEN(x) \
2270 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2272 #define S_FW_RDEV_WR_ALLOC 31
2273 #define M_FW_RDEV_WR_ALLOC 0x1
2274 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC)
2275 #define G_FW_RDEV_WR_ALLOC(x) \
2276 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2277 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U)
2279 #define S_FW_RDEV_WR_FREE 30
2280 #define M_FW_RDEV_WR_FREE 0x1
2281 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE)
2282 #define G_FW_RDEV_WR_FREE(x) \
2283 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2284 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U)
2286 #define S_FW_RDEV_WR_MODIFY 29
2287 #define M_FW_RDEV_WR_MODIFY 0x1
2288 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY)
2289 #define G_FW_RDEV_WR_MODIFY(x) \
2290 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2291 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U)
2293 #define S_FW_RDEV_WR_FLOWID 8
2294 #define M_FW_RDEV_WR_FLOWID 0xfffff
2295 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID)
2296 #define G_FW_RDEV_WR_FLOWID(x) \
2297 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2299 #define S_FW_RDEV_WR_LEN16 0
2300 #define M_FW_RDEV_WR_LEN16 0xff
2301 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16)
2302 #define G_FW_RDEV_WR_LEN16(x) \
2303 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2305 #define S_FW_RDEV_WR_FLAGS 24
2306 #define M_FW_RDEV_WR_FLAGS 0xff
2307 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS)
2308 #define G_FW_RDEV_WR_FLAGS(x) \
2309 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2311 #define S_FW_RDEV_WR_GET_NEXT 20
2312 #define M_FW_RDEV_WR_GET_NEXT 0xf
2313 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT)
2314 #define G_FW_RDEV_WR_GET_NEXT(x) \
2315 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2317 #define S_FW_RDEV_WR_ASSOC_FLOWID 0
2318 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff
2319 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2320 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
2321 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2323 #define S_FW_RDEV_WR_RJT 7
2324 #define M_FW_RDEV_WR_RJT 0x1
2325 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT)
2326 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2327 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U)
2329 #define S_FW_RDEV_WR_REASON 0
2330 #define M_FW_RDEV_WR_REASON 0x7f
2331 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON)
2332 #define G_FW_RDEV_WR_REASON(x) \
2333 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2335 #define S_FW_RDEV_WR_RD_XFER_RDY 7
2336 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1
2337 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2338 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \
2339 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2340 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U)
2342 #define S_FW_RDEV_WR_WR_XFER_RDY 6
2343 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1
2344 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2345 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \
2346 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2347 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U)
2349 #define S_FW_RDEV_WR_FC_SP 5
2350 #define M_FW_RDEV_WR_FC_SP 0x1
2351 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP)
2352 #define G_FW_RDEV_WR_FC_SP(x) \
2353 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2354 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U)
2356 #define S_FW_RDEV_WR_RPORT_TYPE 0
2357 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f
2358 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE)
2359 #define G_FW_RDEV_WR_RPORT_TYPE(x) \
2360 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2362 #define S_FW_RDEV_WR_VFT 7
2363 #define M_FW_RDEV_WR_VFT 0x1
2364 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT)
2365 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2366 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U)
2368 #define S_FW_RDEV_WR_NPIV 6
2369 #define M_FW_RDEV_WR_NPIV 0x1
2370 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV)
2371 #define G_FW_RDEV_WR_NPIV(x) \
2372 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2373 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U)
2375 #define S_FW_RDEV_WR_CLASS 4
2376 #define M_FW_RDEV_WR_CLASS 0x3
2377 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS)
2378 #define G_FW_RDEV_WR_CLASS(x) \
2379 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2381 #define S_FW_RDEV_WR_SEQ_DEL 3
2382 #define M_FW_RDEV_WR_SEQ_DEL 0x1
2383 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)
2384 #define G_FW_RDEV_WR_SEQ_DEL(x) \
2385 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2386 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U)
2388 #define S_FW_RDEV_WR_PRIO_PREEMP 2
2389 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1
2390 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2391 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \
2392 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2393 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U)
2395 #define S_FW_RDEV_WR_PREF 1
2396 #define M_FW_RDEV_WR_PREF 0x1
2397 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF)
2398 #define G_FW_RDEV_WR_PREF(x) \
2399 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2400 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U)
2402 #define S_FW_RDEV_WR_QOS 0
2403 #define M_FW_RDEV_WR_QOS 0x1
2404 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS)
2405 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2406 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U)
2408 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7
2409 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1
2410 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2411 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
2412 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2413 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2415 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6
2416 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1
2417 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2418 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
2419 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2420 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2422 #define S_FW_RDEV_WR_IMAGE_PAIR 5
2423 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1
2424 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2425 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \
2426 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2427 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)
2429 #define S_FW_RDEV_WR_ACC_RSP_CODE 0
2430 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f
2431 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2432 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
2433 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2435 #define S_FW_RDEV_WR_ENH_DISC 7
2436 #define M_FW_RDEV_WR_ENH_DISC 0x1
2437 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC)
2438 #define G_FW_RDEV_WR_ENH_DISC(x) \
2439 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2440 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U)
2442 #define S_FW_RDEV_WR_REC 6
2443 #define M_FW_RDEV_WR_REC 0x1
2444 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC)
2445 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2446 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U)
2448 #define S_FW_RDEV_WR_TASK_RETRY_ID 5
2449 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1
2450 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2451 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
2452 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2453 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2455 #define S_FW_RDEV_WR_RETRY 4
2456 #define M_FW_RDEV_WR_RETRY 0x1
2457 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY)
2458 #define G_FW_RDEV_WR_RETRY(x) \
2459 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2460 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U)
2462 #define S_FW_RDEV_WR_CONF_CMPL 3
2463 #define M_FW_RDEV_WR_CONF_CMPL 0x1
2464 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL)
2465 #define G_FW_RDEV_WR_CONF_CMPL(x) \
2466 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2467 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U)
2469 #define S_FW_RDEV_WR_DATA_OVLY 2
2470 #define M_FW_RDEV_WR_DATA_OVLY 0x1
2471 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY)
2472 #define G_FW_RDEV_WR_DATA_OVLY(x) \
2473 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2474 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U)
2476 #define S_FW_RDEV_WR_INI 1
2477 #define M_FW_RDEV_WR_INI 0x1
2478 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI)
2479 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2480 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U)
2482 #define S_FW_RDEV_WR_TGT 0
2483 #define M_FW_RDEV_WR_TGT 0x1
2484 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT)
2485 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2486 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U)
2488 struct fw_foiscsi_node_wr {
2489 __be32 op_to_immdlen;
2490 __be32 flowid_len16;
2499 __be16 retry_timeout;
2505 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
2506 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff
2507 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2508 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
2509 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2511 struct fw_foiscsi_ctrl_wr {
2513 __be32 flowid_len16;
2522 struct fw_foiscsi_sess_attr {
2523 __be32 sess_type_to_erl;
2532 struct fw_foiscsi_conn_attr {
2533 __be32 hdigest_to_ddp_pgsz;
2538 union fw_foiscsi_conn_attr_addr {
2539 struct fw_foiscsi_conn_attr_ipv6 {
2543 struct fw_foiscsi_conn_attr_ipv4 {
2551 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2554 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30
2555 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3
2556 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2557 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2558 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2559 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2561 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29
2562 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1
2563 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2564 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2565 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2566 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2567 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2568 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
2569 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2571 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28
2572 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1
2573 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2574 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2575 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2576 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2577 M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2578 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
2579 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2581 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27
2582 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1
2583 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2584 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2585 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2586 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2587 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2588 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
2589 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2591 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26
2592 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1
2593 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2594 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2595 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2596 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2597 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2598 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
2599 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2601 #define S_FW_FOISCSI_CTRL_WR_ERL 24
2602 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3
2603 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2604 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \
2605 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2607 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30
2608 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3
2609 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2610 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
2611 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2613 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28
2614 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3
2615 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2616 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
2617 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2619 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25
2620 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7
2621 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2622 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2623 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2624 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2625 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2627 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23
2628 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3
2629 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2630 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2631 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2632 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2633 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2635 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21
2636 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3
2637 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2638 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2639 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2640 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2642 #define S_FW_FOISCSI_CTRL_WR_IPV6 20
2643 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1
2644 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2645 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \
2646 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2647 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2649 struct fw_foiscsi_chap_wr {
2651 __be32 flowid_len16;
2659 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN];
2660 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2663 /******************************************************************************
2664 * C O i S C S I W O R K R E Q U E S T S
2665 ********************************************/
2667 enum fw_chnet_addr_type {
2668 FW_CHNET_ADDD_TYPE_NONE = 0,
2669 FW_CHNET_ADDR_TYPE_IPV4,
2670 FW_CHNET_ADDR_TYPE_IPV6,
2673 enum fw_msg_wr_type {
2674 FW_MSG_WR_TYPE_RPL = 0,
2679 struct fw_coiscsi_tgt_wr {
2681 __be32 flowid_len16;
2687 struct fw_coiscsi_tgt_conn_attr {
2692 union fw_coiscsi_tgt_conn_attr_addr {
2693 struct fw_coiscsi_tgt_conn_attr_in_addr {
2698 struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2705 struct fw_coiscsi_tgt_conn_wr {
2707 __be32 flowid_len16;
2715 struct fw_coiscsi_tgt_conn_tcp {
2719 union fw_coiscsi_tgt_conn_tcp_addr {
2720 struct fw_coiscsi_tgt_conn_tcp_in_addr {
2724 struct fw_coiscsi_tgt_conn_tcp_in_addr6 {
2730 struct fw_coiscsi_tgt_conn_iscsi {
2731 __be32 hdigest_to_ddp_pgsz;
2743 struct fw_coiscsi_tgt_xmit_wr {
2744 __be32 op_to_immdlen;
2745 __be32 flowid_len16;
2757 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23
2758 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1
2759 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
2760 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2761 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
2762 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2763 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
2765 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22
2766 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1
2767 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
2768 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2769 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
2770 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2771 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
2773 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20
2774 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1
2775 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
2776 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \
2777 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
2778 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
2780 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19
2781 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1
2782 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \
2783 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2784 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \
2785 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2786 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U)
2788 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18
2789 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1
2790 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \
2791 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2792 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \
2793 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2794 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U)
2796 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16
2797 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3
2798 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \
2799 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2800 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \
2801 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \
2802 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2804 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0
2805 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff
2806 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
2807 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2808 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
2809 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
2810 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2814 __be32 flowid_len16;
2820 struct fw_tcp_conn_attr {
2825 union fw_tcp_conn_attr_addr {
2826 struct fw_tcp_conn_attr_in_addr {
2831 struct fw_tcp_conn_attr_in_addr6 {
2838 struct fw_isns_xmit_wr {
2839 __be32 op_to_immdlen;
2840 __be32 flowid_len16;
2848 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0
2849 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff
2850 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
2851 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \
2852 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
2854 /******************************************************************************
2855 * F O F C O E W O R K R E Q U E S T s
2856 *******************************************/
2858 struct fw_fcoe_els_ct_wr {
2860 __be32 flowid_len16;
2877 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24
2878 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff
2879 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2880 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
2881 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2883 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
2884 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff
2885 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2886 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
2887 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2889 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8
2890 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff
2891 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2892 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
2893 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2895 #define S_FW_FCOE_ELS_CT_WR_LEN16 0
2896 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff
2897 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2898 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
2899 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2901 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6
2902 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3
2903 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2904 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
2905 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2907 #define S_FW_FCOE_ELS_CT_WR_CLASS 4
2908 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3
2909 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2910 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
2911 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2913 #define S_FW_FCOE_ELS_CT_WR_FL 2
2914 #define M_FW_FCOE_ELS_CT_WR_FL 0x1
2915 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL)
2916 #define G_FW_FCOE_ELS_CT_WR_FL(x) \
2917 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2918 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U)
2920 #define S_FW_FCOE_ELS_CT_WR_NPIV 1
2921 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1
2922 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2923 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
2924 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2925 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2927 #define S_FW_FCOE_ELS_CT_WR_SP 0
2928 #define M_FW_FCOE_ELS_CT_WR_SP 0x1
2929 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP)
2930 #define G_FW_FCOE_ELS_CT_WR_SP(x) \
2931 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2932 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U)
2934 /******************************************************************************
2935 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path)
2936 *****************************************************************************/
2938 struct fw_scsi_write_wr {
2940 __be32 flowid_len16;
2945 union fw_scsi_write_priv {
2946 struct fcoe_write_priv {
2951 struct iscsi_write_priv {
2956 __be32 ini_xfer_cnt;
2962 #define S_FW_SCSI_WRITE_WR_OPCODE 24
2963 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff
2964 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2965 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \
2966 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2968 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0
2969 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff
2970 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2971 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
2972 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2974 #define S_FW_SCSI_WRITE_WR_FLOWID 8
2975 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff
2976 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2977 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \
2978 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2980 #define S_FW_SCSI_WRITE_WR_LEN16 0
2981 #define M_FW_SCSI_WRITE_WR_LEN16 0xff
2982 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16)
2983 #define G_FW_SCSI_WRITE_WR_LEN16(x) \
2984 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2986 #define S_FW_SCSI_WRITE_WR_CP_EN 6
2987 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3
2988 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2989 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \
2990 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2992 #define S_FW_SCSI_WRITE_WR_CLASS 4
2993 #define M_FW_SCSI_WRITE_WR_CLASS 0x3
2994 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS)
2995 #define G_FW_SCSI_WRITE_WR_CLASS(x) \
2996 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2998 struct fw_scsi_read_wr {
3000 __be32 flowid_len16;
3005 union fw_scsi_read_priv {
3006 struct fcoe_read_priv {
3011 struct iscsi_read_priv {
3016 __be32 ini_xfer_cnt;
3022 #define S_FW_SCSI_READ_WR_OPCODE 24
3023 #define M_FW_SCSI_READ_WR_OPCODE 0xff
3024 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE)
3025 #define G_FW_SCSI_READ_WR_OPCODE(x) \
3026 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
3028 #define S_FW_SCSI_READ_WR_IMMDLEN 0
3029 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff
3030 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN)
3031 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \
3032 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
3034 #define S_FW_SCSI_READ_WR_FLOWID 8
3035 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff
3036 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID)
3037 #define G_FW_SCSI_READ_WR_FLOWID(x) \
3038 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
3040 #define S_FW_SCSI_READ_WR_LEN16 0
3041 #define M_FW_SCSI_READ_WR_LEN16 0xff
3042 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16)
3043 #define G_FW_SCSI_READ_WR_LEN16(x) \
3044 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
3046 #define S_FW_SCSI_READ_WR_CP_EN 6
3047 #define M_FW_SCSI_READ_WR_CP_EN 0x3
3048 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN)
3049 #define G_FW_SCSI_READ_WR_CP_EN(x) \
3050 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3052 #define S_FW_SCSI_READ_WR_CLASS 4
3053 #define M_FW_SCSI_READ_WR_CLASS 0x3
3054 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS)
3055 #define G_FW_SCSI_READ_WR_CLASS(x) \
3056 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3058 struct fw_scsi_cmd_wr {
3060 __be32 flowid_len16;
3065 union fw_scsi_cmd_priv {
3066 struct fcoe_cmd_priv {
3071 struct iscsi_cmd_priv {
3081 #define S_FW_SCSI_CMD_WR_OPCODE 24
3082 #define M_FW_SCSI_CMD_WR_OPCODE 0xff
3083 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE)
3084 #define G_FW_SCSI_CMD_WR_OPCODE(x) \
3085 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3087 #define S_FW_SCSI_CMD_WR_IMMDLEN 0
3088 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff
3089 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3090 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
3091 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3093 #define S_FW_SCSI_CMD_WR_FLOWID 8
3094 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff
3095 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID)
3096 #define G_FW_SCSI_CMD_WR_FLOWID(x) \
3097 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3099 #define S_FW_SCSI_CMD_WR_LEN16 0
3100 #define M_FW_SCSI_CMD_WR_LEN16 0xff
3101 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16)
3102 #define G_FW_SCSI_CMD_WR_LEN16(x) \
3103 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3105 #define S_FW_SCSI_CMD_WR_CP_EN 6
3106 #define M_FW_SCSI_CMD_WR_CP_EN 0x3
3107 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN)
3108 #define G_FW_SCSI_CMD_WR_CP_EN(x) \
3109 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3111 #define S_FW_SCSI_CMD_WR_CLASS 4
3112 #define M_FW_SCSI_CMD_WR_CLASS 0x3
3113 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS)
3114 #define G_FW_SCSI_CMD_WR_CLASS(x) \
3115 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3117 struct fw_scsi_abrt_cls_wr {
3119 __be32 flowid_len16;
3123 __u8 sub_opcode_to_chk_all_io;
3128 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24
3129 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff
3130 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3131 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
3132 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3134 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
3135 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff
3136 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3137 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3138 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3139 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3141 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8
3142 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff
3143 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3144 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
3145 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3147 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
3148 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff
3149 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3150 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
3151 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3153 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2
3154 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f
3155 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3156 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3157 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3158 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3159 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3161 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1
3162 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1
3163 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3164 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
3165 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3166 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3168 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
3169 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1
3170 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3171 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3172 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3173 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3174 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3175 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
3176 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3178 struct fw_scsi_tgt_acc_wr {
3180 __be32 flowid_len16;
3185 union fw_scsi_tgt_acc_priv {
3186 struct fcoe_tgt_acc_priv {
3191 struct iscsi_tgt_acc_priv {
3199 __be32 tot_xfer_len;
3202 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24
3203 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff
3204 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3205 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
3206 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3208 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
3209 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff
3210 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3211 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
3212 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3214 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8
3215 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff
3216 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3217 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
3218 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3220 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0
3221 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff
3222 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3223 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
3224 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3226 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6
3227 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3
3228 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3229 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
3230 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3232 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4
3233 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3
3234 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3235 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
3236 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3238 struct fw_scsi_tgt_xmit_wr {
3240 __be32 flowid_len16;
3245 union fw_scsi_tgt_xmit_priv {
3246 struct fcoe_tgt_xmit_priv {
3251 struct iscsi_tgt_xmit_priv {
3259 __be32 tot_xfer_len;
3262 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24
3263 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff
3264 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3265 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
3266 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3268 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
3269 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff
3270 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3271 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3272 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3273 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3275 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8
3276 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff
3277 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3278 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
3279 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3281 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
3282 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff
3283 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3284 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
3285 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3287 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6
3288 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3
3289 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3290 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
3291 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3293 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4
3294 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3
3295 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3296 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
3297 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3299 struct fw_scsi_tgt_rsp_wr {
3301 __be32 flowid_len16;
3305 union fw_scsi_tgt_rsp_priv {
3306 struct fcoe_tgt_rsp_priv {
3311 struct iscsi_tgt_rsp_priv {
3318 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24
3319 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff
3320 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3321 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
3322 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3324 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
3325 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff
3326 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3327 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
3328 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3330 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8
3331 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff
3332 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3333 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
3334 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3336 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0
3337 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff
3338 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3339 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
3340 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3342 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6
3343 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3
3344 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3345 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
3346 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3348 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4
3349 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3
3350 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3351 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
3352 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3354 struct fw_pofcoe_tcb_wr {
3356 __be32 equiq_to_len16;
3370 #define S_FW_POFCOE_TCB_WR_TID 12
3371 #define M_FW_POFCOE_TCB_WR_TID 0xfffff
3372 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID)
3373 #define G_FW_POFCOE_TCB_WR_TID(x) \
3374 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3376 #define S_FW_POFCOE_TCB_WR_ALLOC 4
3377 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1
3378 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3379 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \
3380 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3381 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U)
3383 #define S_FW_POFCOE_TCB_WR_FREE 3
3384 #define M_FW_POFCOE_TCB_WR_FREE 0x1
3385 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE)
3386 #define G_FW_POFCOE_TCB_WR_FREE(x) \
3387 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3388 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)
3390 #define S_FW_POFCOE_TCB_WR_PORT 0
3391 #define M_FW_POFCOE_TCB_WR_PORT 0x7
3392 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT)
3393 #define G_FW_POFCOE_TCB_WR_PORT(x) \
3394 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3396 struct fw_pofcoe_ulptx_wr {
3398 __be32 equiq_to_len16;
3402 /*******************************************************************
3403 * T10 DIF related definition
3404 *******************************************************************/
3405 struct fw_tx_pi_header {
3406 __be16 op_to_inline;
3407 __u8 pi_interval_tag_type;
3409 __be32 pi_start4_pi_end4;
3410 __u8 tag_gen_enabled_pkd;
3416 #define S_FW_TX_PI_HEADER_OP 8
3417 #define M_FW_TX_PI_HEADER_OP 0xff
3418 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP)
3419 #define G_FW_TX_PI_HEADER_OP(x) \
3420 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3422 #define S_FW_TX_PI_HEADER_ULPTXMORE 7
3423 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1
3424 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3425 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \
3426 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3427 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3429 #define S_FW_TX_PI_HEADER_PI_CONTROL 4
3430 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7
3431 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3432 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \
3433 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3435 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2
3436 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1
3437 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3438 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \
3439 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3440 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3442 #define S_FW_TX_PI_HEADER_VALIDATE 1
3443 #define M_FW_TX_PI_HEADER_VALIDATE 0x1
3444 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE)
3445 #define G_FW_TX_PI_HEADER_VALIDATE(x) \
3446 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3447 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U)
3449 #define S_FW_TX_PI_HEADER_INLINE 0
3450 #define M_FW_TX_PI_HEADER_INLINE 0x1
3451 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE)
3452 #define G_FW_TX_PI_HEADER_INLINE(x) \
3453 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3454 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U)
3456 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7
3457 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1
3458 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3459 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3460 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3461 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3462 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3464 #define S_FW_TX_PI_HEADER_TAG_TYPE 5
3465 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3
3466 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3467 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \
3468 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3470 #define S_FW_TX_PI_HEADER_PI_START4 22
3471 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff
3472 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4)
3473 #define G_FW_TX_PI_HEADER_PI_START4(x) \
3474 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3476 #define S_FW_TX_PI_HEADER_PI_END4 0
3477 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff
3478 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4)
3479 #define G_FW_TX_PI_HEADER_PI_END4(x) \
3480 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3482 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6
3483 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3
3484 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3485 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3486 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3487 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3488 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3490 enum fw_pi_error_type {
3491 FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3494 struct fw_pi_error {
3495 __be32 err_type_pkd;
3496 __be32 flowid_len16;
3503 #define S_FW_PI_ERROR_ERR_TYPE 24
3504 #define M_FW_PI_ERROR_ERR_TYPE 0xff
3505 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE)
3506 #define G_FW_PI_ERROR_ERR_TYPE(x) \
3507 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3509 struct fw_tlstx_data_wr {
3510 __be32 op_to_immdlen;
3511 __be32 flowid_len16;
3513 __be32 lsodisable_to_flags;
3515 __be32 ctxloc_to_exp;
3517 __be16 adjustedplen_pkd;
3518 __be16 expinplenmax_pkd;
3519 __u8 pdusinplenmax_pkd;
3523 #define S_FW_TLSTX_DATA_WR_OPCODE 24
3524 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff
3525 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3526 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \
3527 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3529 #define S_FW_TLSTX_DATA_WR_COMPL 21
3530 #define M_FW_TLSTX_DATA_WR_COMPL 0x1
3531 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3532 #define G_FW_TLSTX_DATA_WR_COMPL(x) \
3533 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3534 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U)
3536 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0
3537 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff
3538 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3539 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \
3540 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3542 #define S_FW_TLSTX_DATA_WR_FLOWID 8
3543 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff
3544 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3545 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \
3546 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3548 #define S_FW_TLSTX_DATA_WR_LEN16 0
3549 #define M_FW_TLSTX_DATA_WR_LEN16 0xff
3550 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3551 #define G_FW_TLSTX_DATA_WR_LEN16(x) \
3552 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3554 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31
3555 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1
3556 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3557 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3558 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3559 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3560 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3562 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30
3563 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1
3564 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3565 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \
3566 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3567 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3569 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3570 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3571 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3572 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3573 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3574 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3575 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3576 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3578 #define S_FW_TLSTX_DATA_WR_FLAGS 0
3579 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff
3580 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3581 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \
3582 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3584 #define S_FW_TLSTX_DATA_WR_CTXLOC 30
3585 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3
3586 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3587 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \
3588 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3590 #define S_FW_TLSTX_DATA_WR_IVDSGL 29
3591 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1
3592 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3593 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \
3594 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3595 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3597 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24
3598 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f
3599 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3600 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \
3601 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3603 #define S_FW_TLSTX_DATA_WR_NUMIVS 14
3604 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff
3605 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3606 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \
3607 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3609 #define S_FW_TLSTX_DATA_WR_EXP 0
3610 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff
3611 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP)
3612 #define G_FW_TLSTX_DATA_WR_EXP(x) \
3613 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3615 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3616 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3617 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3618 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3619 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3620 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3621 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3623 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3624 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3625 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3626 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3627 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3628 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3629 M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3631 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3632 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3633 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3634 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3635 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3636 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3637 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3639 struct fw_crypto_lookaside_wr {
3640 __be32 op_to_cctx_size;
3643 __be32 rx_chid_to_rx_q_id;
3645 __be32 pld_size_hash_size;
3649 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3650 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3651 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3652 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3653 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3654 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3655 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3657 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3658 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
3659 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3660 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3661 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3662 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
3663 M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3664 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
3666 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
3667 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
3668 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3669 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3670 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3671 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
3672 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3674 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
3675 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
3676 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3677 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3678 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3679 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
3680 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3682 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
3683 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
3684 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3685 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3686 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3687 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
3688 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3690 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
3691 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
3692 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3693 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3694 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3695 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
3696 M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3698 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
3699 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
3700 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3701 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3702 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3703 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
3704 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3706 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27
3707 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3
3708 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3709 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
3710 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3711 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
3713 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
3714 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
3715 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3716 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3717 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3718 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
3719 M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3721 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23
3722 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3
3723 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
3724 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
3725 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
3726 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
3728 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
3729 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
3730 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
3731 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
3732 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
3733 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
3734 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
3736 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
3737 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
3738 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
3739 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
3740 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
3741 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
3742 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
3744 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
3745 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
3746 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
3747 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
3748 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
3749 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
3750 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
3752 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
3753 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
3754 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
3755 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
3756 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
3757 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
3758 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
3760 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
3761 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
3762 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
3763 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
3764 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
3765 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
3766 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
3768 /******************************************************************************
3770 *********************/
3773 * The maximum length of time, in miliseconds, that we expect any firmware
3774 * command to take to execute and return a reply to the host. The RESET
3775 * and INITIALIZE commands can take a fair amount of time to execute but
3776 * most execute in far less time than this maximum. This constant is used
3777 * by host software to determine how long to wait for a firmware command
3778 * reply before declaring the firmware as dead/unreachable ...
3780 #define FW_CMD_MAX_TIMEOUT 10000
3783 * If a host driver does a HELLO and discovers that there's already a MASTER
3784 * selected, we may have to wait for that MASTER to finish issuing RESET,
3785 * configuration and INITIALIZE commands. Also, there's a possibility that
3786 * our own HELLO may get lost if it happens right as the MASTER is issuign a
3787 * RESET command, so we need to be willing to make a few retries of our HELLO.
3789 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
3790 #define FW_CMD_HELLO_RETRIES 3
3792 enum fw_cmd_opcodes {
3794 FW_RESET_CMD = 0x03,
3795 FW_HELLO_CMD = 0x04,
3797 FW_INITIALIZE_CMD = 0x06,
3798 FW_CAPS_CONFIG_CMD = 0x07,
3799 FW_PARAMS_CMD = 0x08,
3802 FW_EQ_MNGT_CMD = 0x11,
3803 FW_EQ_ETH_CMD = 0x12,
3804 FW_EQ_CTRL_CMD = 0x13,
3805 FW_EQ_OFLD_CMD = 0x21,
3807 FW_VI_MAC_CMD = 0x15,
3808 FW_VI_RXMODE_CMD = 0x16,
3809 FW_VI_ENABLE_CMD = 0x17,
3810 FW_VI_STATS_CMD = 0x1a,
3811 FW_ACL_MAC_CMD = 0x18,
3812 FW_ACL_VLAN_CMD = 0x19,
3814 FW_PORT_STATS_CMD = 0x1c,
3815 FW_PORT_LB_STATS_CMD = 0x1d,
3816 FW_PORT_TRACE_CMD = 0x1e,
3817 FW_PORT_TRACE_MMAP_CMD = 0x1f,
3818 FW_RSS_IND_TBL_CMD = 0x20,
3819 FW_RSS_GLB_CONFIG_CMD = 0x22,
3820 FW_RSS_VI_CONFIG_CMD = 0x23,
3821 FW_SCHED_CMD = 0x24,
3822 FW_DEVLOG_CMD = 0x25,
3823 FW_WATCHDOG_CMD = 0x27,
3825 FW_CHNET_IFACE_CMD = 0x26,
3826 FW_FCOE_RES_INFO_CMD = 0x31,
3827 FW_FCOE_LINK_CMD = 0x32,
3828 FW_FCOE_VNP_CMD = 0x33,
3829 FW_FCOE_SPARAMS_CMD = 0x35,
3830 FW_FCOE_STATS_CMD = 0x37,
3831 FW_FCOE_FCF_CMD = 0x38,
3832 FW_DCB_IEEE_CMD = 0x3a,
3836 FW_LASTC2E_CMD = 0x40,
3837 FW_ERROR_CMD = 0x80,
3838 FW_DEBUG_CMD = 0x81,
3842 FW_CMD_CAP_PF = 0x01,
3843 FW_CMD_CAP_DMAQ = 0x02,
3844 FW_CMD_CAP_PORT = 0x04,
3845 FW_CMD_CAP_PORTPROMISC = 0x08,
3846 FW_CMD_CAP_PORTSTATS = 0x10,
3847 FW_CMD_CAP_VF = 0x80,
3851 * Generic command header flit0
3858 #define S_FW_CMD_OP 24
3859 #define M_FW_CMD_OP 0xff
3860 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
3861 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
3863 #define S_FW_CMD_REQUEST 23
3864 #define M_FW_CMD_REQUEST 0x1
3865 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
3866 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
3867 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
3869 #define S_FW_CMD_READ 22
3870 #define M_FW_CMD_READ 0x1
3871 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
3872 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
3873 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
3875 #define S_FW_CMD_WRITE 21
3876 #define M_FW_CMD_WRITE 0x1
3877 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
3878 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
3879 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
3881 #define S_FW_CMD_EXEC 20
3882 #define M_FW_CMD_EXEC 0x1
3883 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
3884 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
3885 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
3887 #define S_FW_CMD_RAMASK 20
3888 #define M_FW_CMD_RAMASK 0xf
3889 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK)
3890 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
3892 #define S_FW_CMD_RETVAL 8
3893 #define M_FW_CMD_RETVAL 0xff
3894 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
3895 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
3897 #define S_FW_CMD_LEN16 0
3898 #define M_FW_CMD_LEN16 0xff
3899 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
3900 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
3902 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
3907 enum fw_ldst_addrspc {
3908 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
3909 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
3910 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
3911 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
3912 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
3913 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
3914 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
3915 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
3916 FW_LDST_ADDRSPC_MDIO = 0x0018,
3917 FW_LDST_ADDRSPC_MPS = 0x0020,
3918 FW_LDST_ADDRSPC_FUNC = 0x0028,
3919 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
3920 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */
3921 FW_LDST_ADDRSPC_LE = 0x0030,
3922 FW_LDST_ADDRSPC_I2C = 0x0038,
3923 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
3924 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041,
3925 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042,
3926 FW_LDST_ADDRSPC_CIM_Q = 0x0048,
3930 * MDIO VSC8634 register access control field
3932 enum fw_ldst_mdio_vsc8634_aid {
3933 FW_LDST_MDIO_VS_STANDARD,
3934 FW_LDST_MDIO_VS_EXTENDED,
3935 FW_LDST_MDIO_VS_GPIO
3938 enum fw_ldst_mps_fid {
3943 enum fw_ldst_func_access_ctl {
3944 FW_LDST_FUNC_ACC_CTL_VIID,
3945 FW_LDST_FUNC_ACC_CTL_FID
3948 enum fw_ldst_func_mod_index {
3952 struct fw_ldst_cmd {
3953 __be32 op_to_addrspace;
3954 __be32 cycles_to_len16;
3956 struct fw_ldst_addrval {
3960 struct fw_ldst_idctxt {
3962 __be32 msg_ctxtflush;
3972 struct fw_ldst_mdio {
3978 struct fw_ldst_cim_rq {
3979 __u8 req_first64[8];
3980 __u8 req_second64[8];
3981 __u8 resp_first64[8];
3982 __u8 resp_second64[8];
3986 struct fw_ldst_mps_rplc {
3998 struct fw_ldst_mps_atrb {
4007 struct fw_ldst_func {
4015 struct fw_ldst_pcie {
4020 __u8 select_naccess;
4025 struct fw_ldst_i2c_deprecated {
4032 struct fw_ldst_i2c {
4049 #define S_FW_LDST_CMD_ADDRSPACE 0
4050 #define M_FW_LDST_CMD_ADDRSPACE 0xff
4051 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
4052 #define G_FW_LDST_CMD_ADDRSPACE(x) \
4053 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4055 #define S_FW_LDST_CMD_CYCLES 16
4056 #define M_FW_LDST_CMD_CYCLES 0xffff
4057 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES)
4058 #define G_FW_LDST_CMD_CYCLES(x) \
4059 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4061 #define S_FW_LDST_CMD_MSG 31
4062 #define M_FW_LDST_CMD_MSG 0x1
4063 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG)
4064 #define G_FW_LDST_CMD_MSG(x) \
4065 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4066 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U)
4068 #define S_FW_LDST_CMD_CTXTFLUSH 30
4069 #define M_FW_LDST_CMD_CTXTFLUSH 0x1
4070 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH)
4071 #define G_FW_LDST_CMD_CTXTFLUSH(x) \
4072 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4073 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U)
4075 #define S_FW_LDST_CMD_PADDR 8
4076 #define M_FW_LDST_CMD_PADDR 0x1f
4077 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR)
4078 #define G_FW_LDST_CMD_PADDR(x) \
4079 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4081 #define S_FW_LDST_CMD_MMD 0
4082 #define M_FW_LDST_CMD_MMD 0x1f
4083 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD)
4084 #define G_FW_LDST_CMD_MMD(x) \
4085 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4087 #define S_FW_LDST_CMD_FID 15
4088 #define M_FW_LDST_CMD_FID 0x1
4089 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID)
4090 #define G_FW_LDST_CMD_FID(x) \
4091 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4092 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U)
4094 #define S_FW_LDST_CMD_IDX 0
4095 #define M_FW_LDST_CMD_IDX 0x7fff
4096 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX)
4097 #define G_FW_LDST_CMD_IDX(x) \
4098 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4100 #define S_FW_LDST_CMD_RPLCPF 0
4101 #define M_FW_LDST_CMD_RPLCPF 0xff
4102 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF)
4103 #define G_FW_LDST_CMD_RPLCPF(x) \
4104 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4106 #define S_FW_LDST_CMD_MPSID 0
4107 #define M_FW_LDST_CMD_MPSID 0x7fff
4108 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID)
4109 #define G_FW_LDST_CMD_MPSID(x) \
4110 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4112 #define S_FW_LDST_CMD_CTRL 7
4113 #define M_FW_LDST_CMD_CTRL 0x1
4114 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL)
4115 #define G_FW_LDST_CMD_CTRL(x) \
4116 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4117 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U)
4119 #define S_FW_LDST_CMD_LC 4
4120 #define M_FW_LDST_CMD_LC 0x1
4121 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC)
4122 #define G_FW_LDST_CMD_LC(x) \
4123 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4124 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U)
4126 #define S_FW_LDST_CMD_AI 3
4127 #define M_FW_LDST_CMD_AI 0x1
4128 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI)
4129 #define G_FW_LDST_CMD_AI(x) \
4130 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4131 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U)
4133 #define S_FW_LDST_CMD_FN 0
4134 #define M_FW_LDST_CMD_FN 0x7
4135 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN)
4136 #define G_FW_LDST_CMD_FN(x) \
4137 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4139 #define S_FW_LDST_CMD_SELECT 4
4140 #define M_FW_LDST_CMD_SELECT 0xf
4141 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT)
4142 #define G_FW_LDST_CMD_SELECT(x) \
4143 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4145 #define S_FW_LDST_CMD_NACCESS 0
4146 #define M_FW_LDST_CMD_NACCESS 0xf
4147 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS)
4148 #define G_FW_LDST_CMD_NACCESS(x) \
4149 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4151 #define S_FW_LDST_CMD_NSET 14
4152 #define M_FW_LDST_CMD_NSET 0x3
4153 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET)
4154 #define G_FW_LDST_CMD_NSET(x) \
4155 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4157 #define S_FW_LDST_CMD_PID 6
4158 #define M_FW_LDST_CMD_PID 0x3
4159 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID)
4160 #define G_FW_LDST_CMD_PID(x) \
4161 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4163 struct fw_reset_cmd {
4165 __be32 retval_len16;
4170 #define S_FW_RESET_CMD_HALT 31
4171 #define M_FW_RESET_CMD_HALT 0x1
4172 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
4173 #define G_FW_RESET_CMD_HALT(x) \
4174 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4175 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
4178 FW_HELLO_CMD_STAGE_OS = 0,
4179 FW_HELLO_CMD_STAGE_PREOS0 = 1,
4180 FW_HELLO_CMD_STAGE_PREOS1 = 2,
4181 FW_HELLO_CMD_STAGE_POSTOS = 3,
4184 struct fw_hello_cmd {
4186 __be32 retval_len16;
4187 __be32 err_to_clearinit;
4191 #define S_FW_HELLO_CMD_ERR 31
4192 #define M_FW_HELLO_CMD_ERR 0x1
4193 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
4194 #define G_FW_HELLO_CMD_ERR(x) \
4195 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4196 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
4198 #define S_FW_HELLO_CMD_INIT 30
4199 #define M_FW_HELLO_CMD_INIT 0x1
4200 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
4201 #define G_FW_HELLO_CMD_INIT(x) \
4202 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4203 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
4205 #define S_FW_HELLO_CMD_MASTERDIS 29
4206 #define M_FW_HELLO_CMD_MASTERDIS 0x1
4207 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
4208 #define G_FW_HELLO_CMD_MASTERDIS(x) \
4209 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4210 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
4212 #define S_FW_HELLO_CMD_MASTERFORCE 28
4213 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
4214 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
4215 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
4216 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4217 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
4219 #define S_FW_HELLO_CMD_MBMASTER 24
4220 #define M_FW_HELLO_CMD_MBMASTER 0xf
4221 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
4222 #define G_FW_HELLO_CMD_MBMASTER(x) \
4223 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4225 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23
4226 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1
4227 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4228 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
4229 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4230 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4232 #define S_FW_HELLO_CMD_MBASYNCNOT 20
4233 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
4234 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4235 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
4236 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4238 #define S_FW_HELLO_CMD_STAGE 17
4239 #define M_FW_HELLO_CMD_STAGE 0x7
4240 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
4241 #define G_FW_HELLO_CMD_STAGE(x) \
4242 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4244 #define S_FW_HELLO_CMD_CLEARINIT 16
4245 #define M_FW_HELLO_CMD_CLEARINIT 0x1
4246 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
4247 #define G_FW_HELLO_CMD_CLEARINIT(x) \
4248 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4249 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
4253 __be32 retval_len16;
4257 struct fw_initialize_cmd {
4259 __be32 retval_len16;
4263 enum fw_caps_config_hm {
4264 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
4265 FW_CAPS_CONFIG_HM_PL = 0x00000002,
4266 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
4267 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
4268 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
4269 FW_CAPS_CONFIG_HM_TP = 0x00000020,
4270 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
4271 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
4272 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
4273 FW_CAPS_CONFIG_HM_MC = 0x00000200,
4274 FW_CAPS_CONFIG_HM_LE = 0x00000400,
4275 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
4276 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
4277 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
4278 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
4279 FW_CAPS_CONFIG_HM_MI = 0x00008000,
4280 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
4281 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
4282 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
4283 FW_CAPS_CONFIG_HM_MA = 0x00080000,
4284 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
4285 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
4286 FW_CAPS_CONFIG_HM_UART = 0x00400000,
4287 FW_CAPS_CONFIG_HM_SF = 0x00800000,
4291 * The VF Register Map.
4293 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4294 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4295 * the Slice to Module Map Table (see below) in the Physical Function Register
4296 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4297 * and Offset registers in the PF Register Map. The MBDATA base address is
4298 * quite constrained as it determines the Mailbox Data addresses for both PFs
4299 * and VFs, and therefore must fit in both the VF and PF Register Maps without
4300 * overlapping other registers.
4302 #define FW_T4VF_SGE_BASE_ADDR 0x0000
4303 #define FW_T4VF_MPS_BASE_ADDR 0x0100
4304 #define FW_T4VF_PL_BASE_ADDR 0x0200
4305 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
4306 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */
4307 #define FW_T4VF_CIM_BASE_ADDR 0x0300
4309 #define FW_T4VF_REGMAP_START 0x0000
4310 #define FW_T4VF_REGMAP_SIZE 0x0400
4312 enum fw_caps_config_nbm {
4313 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
4314 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
4317 enum fw_caps_config_link {
4318 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
4319 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
4320 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
4323 enum fw_caps_config_switch {
4324 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
4325 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
4328 enum fw_caps_config_nic {
4329 FW_CAPS_CONFIG_NIC = 0x00000001,
4330 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
4331 FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
4332 FW_CAPS_CONFIG_NIC_UM = 0x00000008,
4333 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
4334 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
4335 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
4338 enum fw_caps_config_toe {
4339 FW_CAPS_CONFIG_TOE = 0x00000001,
4342 enum fw_caps_config_rdma {
4343 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
4344 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
4347 enum fw_caps_config_iscsi {
4348 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4349 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4350 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4351 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4352 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4353 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4354 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4355 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4356 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4359 enum fw_caps_config_crypto {
4360 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4361 FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4364 enum fw_caps_config_fcoe {
4365 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
4366 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
4367 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
4368 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4369 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
4372 enum fw_memtype_cf {
4373 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
4374 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
4375 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
4376 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
4377 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
4378 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
4381 struct fw_caps_config_cmd {
4383 __be32 cfvalid_to_len16;
4401 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
4402 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
4403 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4404 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
4405 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4406 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4408 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
4409 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
4410 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4411 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4412 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4413 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4414 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4416 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4417 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4418 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4419 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4420 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4421 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4422 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4425 * params command mnemonics
4427 enum fw_params_mnem {
4428 FW_PARAMS_MNEM_DEV = 1, /* device params */
4429 FW_PARAMS_MNEM_PFVF = 2, /* function params */
4430 FW_PARAMS_MNEM_REG = 3, /* limited register access */
4431 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
4432 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
4439 enum fw_params_param_dev {
4440 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
4441 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
4442 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
4443 * allocated by the device's
4446 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4447 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,
4448 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4449 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4450 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07,
4451 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4452 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4453 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4454 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
4455 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
4456 FW_PARAMS_PARAM_DEV_CF = 0x0D,
4457 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
4458 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
4459 FW_PARAMS_PARAM_DEV_LOAD = 0x10,
4460 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
4461 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
4462 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4464 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4466 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4467 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
4468 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4469 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
4470 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
4471 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
4472 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
4473 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
4474 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
4476 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
4477 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
4478 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
4479 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
4480 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22,
4481 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
4485 * dev bypass parameters; actions and modes
4487 enum fw_params_param_dev_bypass {
4491 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4492 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4496 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4497 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
4498 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4501 enum fw_params_param_dev_phyfw {
4502 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4503 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4506 enum fw_params_param_dev_diag {
4507 FW_PARAM_DEV_DIAG_TMP = 0x00,
4508 FW_PARAM_DEV_DIAG_VDD = 0x01,
4511 enum fw_params_param_dev_fwcache {
4512 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
4513 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
4517 * physical and virtual function parameters
4519 enum fw_params_param_pfvf {
4520 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
4521 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4522 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4523 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4524 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4525 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4526 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4527 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4528 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4529 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4530 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4531 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4532 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4533 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4534 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4535 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4536 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
4537 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4538 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
4539 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4540 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4541 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4542 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
4543 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
4544 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
4545 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
4546 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
4547 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4548 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
4549 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
4550 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
4551 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
4552 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
4553 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4554 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4555 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
4556 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
4557 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4558 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4559 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4560 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4561 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4562 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4563 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4564 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4565 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4566 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
4567 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
4568 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
4569 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
4570 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
4571 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
4572 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
4576 * dma queue parameters
4578 enum fw_params_param_dmaq {
4579 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4580 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4581 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
4582 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03,
4583 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4584 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4585 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4586 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4587 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
4588 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
4589 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
4595 enum fw_params_param_chnet {
4596 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00,
4599 enum fw_params_param_chnet_flags {
4600 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,
4601 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2,
4602 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
4605 #define S_FW_PARAMS_MNEM 24
4606 #define M_FW_PARAMS_MNEM 0xff
4607 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
4608 #define G_FW_PARAMS_MNEM(x) \
4609 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
4611 #define S_FW_PARAMS_PARAM_X 16
4612 #define M_FW_PARAMS_PARAM_X 0xff
4613 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
4614 #define G_FW_PARAMS_PARAM_X(x) \
4615 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
4617 #define S_FW_PARAMS_PARAM_Y 8
4618 #define M_FW_PARAMS_PARAM_Y 0xff
4619 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
4620 #define G_FW_PARAMS_PARAM_Y(x) \
4621 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
4623 #define S_FW_PARAMS_PARAM_Z 0
4624 #define M_FW_PARAMS_PARAM_Z 0xff
4625 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
4626 #define G_FW_PARAMS_PARAM_Z(x) \
4627 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
4629 #define S_FW_PARAMS_PARAM_XYZ 0
4630 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
4631 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
4632 #define G_FW_PARAMS_PARAM_XYZ(x) \
4633 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
4635 #define S_FW_PARAMS_PARAM_YZ 0
4636 #define M_FW_PARAMS_PARAM_YZ 0xffff
4637 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
4638 #define G_FW_PARAMS_PARAM_YZ(x) \
4639 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
4641 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
4642 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
4643 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4644 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4645 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4646 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
4647 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4649 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
4650 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
4651 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4652 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4653 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4654 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
4655 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4657 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0
4658 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff
4659 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4660 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4661 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4662 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4664 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29
4665 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7
4666 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
4667 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
4668 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
4669 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
4670 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
4672 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0
4673 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff
4674 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
4675 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
4676 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
4677 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
4678 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
4680 struct fw_params_cmd {
4682 __be32 retval_len16;
4683 struct fw_params_param {
4689 #define S_FW_PARAMS_CMD_PFN 8
4690 #define M_FW_PARAMS_CMD_PFN 0x7
4691 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
4692 #define G_FW_PARAMS_CMD_PFN(x) \
4693 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
4695 #define S_FW_PARAMS_CMD_VFN 0
4696 #define M_FW_PARAMS_CMD_VFN 0xff
4697 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
4698 #define G_FW_PARAMS_CMD_VFN(x) \
4699 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
4701 struct fw_pfvf_cmd {
4703 __be32 retval_len16;
4704 __be32 niqflint_niq;
4706 __be32 tc_to_nexactf;
4707 __be32 r_caps_to_nethctrl;
4713 #define S_FW_PFVF_CMD_PFN 8
4714 #define M_FW_PFVF_CMD_PFN 0x7
4715 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
4716 #define G_FW_PFVF_CMD_PFN(x) \
4717 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
4719 #define S_FW_PFVF_CMD_VFN 0
4720 #define M_FW_PFVF_CMD_VFN 0xff
4721 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
4722 #define G_FW_PFVF_CMD_VFN(x) \
4723 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
4725 #define S_FW_PFVF_CMD_NIQFLINT 20
4726 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
4727 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT)
4728 #define G_FW_PFVF_CMD_NIQFLINT(x) \
4729 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
4731 #define S_FW_PFVF_CMD_NIQ 0
4732 #define M_FW_PFVF_CMD_NIQ 0xfffff
4733 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ)
4734 #define G_FW_PFVF_CMD_NIQ(x) \
4735 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
4737 #define S_FW_PFVF_CMD_TYPE 31
4738 #define M_FW_PFVF_CMD_TYPE 0x1
4739 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE)
4740 #define G_FW_PFVF_CMD_TYPE(x) \
4741 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
4742 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U)
4744 #define S_FW_PFVF_CMD_CMASK 24
4745 #define M_FW_PFVF_CMD_CMASK 0xf
4746 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK)
4747 #define G_FW_PFVF_CMD_CMASK(x) \
4748 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
4750 #define S_FW_PFVF_CMD_PMASK 20
4751 #define M_FW_PFVF_CMD_PMASK 0xf
4752 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK)
4753 #define G_FW_PFVF_CMD_PMASK(x) \
4754 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
4756 #define S_FW_PFVF_CMD_NEQ 0
4757 #define M_FW_PFVF_CMD_NEQ 0xfffff
4758 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ)
4759 #define G_FW_PFVF_CMD_NEQ(x) \
4760 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
4762 #define S_FW_PFVF_CMD_TC 24
4763 #define M_FW_PFVF_CMD_TC 0xff
4764 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC)
4765 #define G_FW_PFVF_CMD_TC(x) \
4766 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
4768 #define S_FW_PFVF_CMD_NVI 16
4769 #define M_FW_PFVF_CMD_NVI 0xff
4770 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI)
4771 #define G_FW_PFVF_CMD_NVI(x) \
4772 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
4774 #define S_FW_PFVF_CMD_NEXACTF 0
4775 #define M_FW_PFVF_CMD_NEXACTF 0xffff
4776 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF)
4777 #define G_FW_PFVF_CMD_NEXACTF(x) \
4778 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
4780 #define S_FW_PFVF_CMD_R_CAPS 24
4781 #define M_FW_PFVF_CMD_R_CAPS 0xff
4782 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS)
4783 #define G_FW_PFVF_CMD_R_CAPS(x) \
4784 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
4786 #define S_FW_PFVF_CMD_WX_CAPS 16
4787 #define M_FW_PFVF_CMD_WX_CAPS 0xff
4788 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS)
4789 #define G_FW_PFVF_CMD_WX_CAPS(x) \
4790 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
4792 #define S_FW_PFVF_CMD_NETHCTRL 0
4793 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
4794 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL)
4795 #define G_FW_PFVF_CMD_NETHCTRL(x) \
4796 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
4799 * ingress queue type; the first 1K ingress queues can have associated 0,
4800 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
4804 FW_IQ_TYPE_FL_INT_CAP,
4805 FW_IQ_TYPE_NO_FL_INT_CAP,
4811 __be32 alloc_to_len16;
4816 __be32 type_to_iqandstindex;
4817 __be16 iqdroprss_to_iqesize;
4820 __be32 iqns_to_fl0congen;
4821 __be16 fl0dcaen_to_fl0cidxfthresh;
4824 __be32 fl1cngchmap_to_fl1congen;
4825 __be16 fl1dcaen_to_fl1cidxfthresh;
4830 #define S_FW_IQ_CMD_PFN 8
4831 #define M_FW_IQ_CMD_PFN 0x7
4832 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
4833 #define G_FW_IQ_CMD_PFN(x) \
4834 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
4836 #define S_FW_IQ_CMD_VFN 0
4837 #define M_FW_IQ_CMD_VFN 0xff
4838 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
4839 #define G_FW_IQ_CMD_VFN(x) \
4840 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
4842 #define S_FW_IQ_CMD_ALLOC 31
4843 #define M_FW_IQ_CMD_ALLOC 0x1
4844 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
4845 #define G_FW_IQ_CMD_ALLOC(x) \
4846 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
4847 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
4849 #define S_FW_IQ_CMD_FREE 30
4850 #define M_FW_IQ_CMD_FREE 0x1
4851 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
4852 #define G_FW_IQ_CMD_FREE(x) \
4853 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
4854 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
4856 #define S_FW_IQ_CMD_MODIFY 29
4857 #define M_FW_IQ_CMD_MODIFY 0x1
4858 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY)
4859 #define G_FW_IQ_CMD_MODIFY(x) \
4860 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
4861 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U)
4863 #define S_FW_IQ_CMD_IQSTART 28
4864 #define M_FW_IQ_CMD_IQSTART 0x1
4865 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
4866 #define G_FW_IQ_CMD_IQSTART(x) \
4867 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
4868 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
4870 #define S_FW_IQ_CMD_IQSTOP 27
4871 #define M_FW_IQ_CMD_IQSTOP 0x1
4872 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
4873 #define G_FW_IQ_CMD_IQSTOP(x) \
4874 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
4875 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
4877 #define S_FW_IQ_CMD_TYPE 29
4878 #define M_FW_IQ_CMD_TYPE 0x7
4879 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
4880 #define G_FW_IQ_CMD_TYPE(x) \
4881 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
4883 #define S_FW_IQ_CMD_IQASYNCH 28
4884 #define M_FW_IQ_CMD_IQASYNCH 0x1
4885 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
4886 #define G_FW_IQ_CMD_IQASYNCH(x) \
4887 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
4888 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
4890 #define S_FW_IQ_CMD_VIID 16
4891 #define M_FW_IQ_CMD_VIID 0xfff
4892 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
4893 #define G_FW_IQ_CMD_VIID(x) \
4894 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
4896 #define S_FW_IQ_CMD_IQANDST 15
4897 #define M_FW_IQ_CMD_IQANDST 0x1
4898 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
4899 #define G_FW_IQ_CMD_IQANDST(x) \
4900 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
4901 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
4903 #define S_FW_IQ_CMD_IQANUS 14
4904 #define M_FW_IQ_CMD_IQANUS 0x1
4905 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS)
4906 #define G_FW_IQ_CMD_IQANUS(x) \
4907 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
4908 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U)
4910 #define S_FW_IQ_CMD_IQANUD 12
4911 #define M_FW_IQ_CMD_IQANUD 0x3
4912 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
4913 #define G_FW_IQ_CMD_IQANUD(x) \
4914 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
4916 #define S_FW_IQ_CMD_IQANDSTINDEX 0
4917 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
4918 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
4919 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
4920 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
4922 #define S_FW_IQ_CMD_IQDROPRSS 15
4923 #define M_FW_IQ_CMD_IQDROPRSS 0x1
4924 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS)
4925 #define G_FW_IQ_CMD_IQDROPRSS(x) \
4926 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
4927 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U)
4929 #define S_FW_IQ_CMD_IQGTSMODE 14
4930 #define M_FW_IQ_CMD_IQGTSMODE 0x1
4931 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
4932 #define G_FW_IQ_CMD_IQGTSMODE(x) \
4933 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
4934 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
4936 #define S_FW_IQ_CMD_IQPCIECH 12
4937 #define M_FW_IQ_CMD_IQPCIECH 0x3
4938 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
4939 #define G_FW_IQ_CMD_IQPCIECH(x) \
4940 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
4942 #define S_FW_IQ_CMD_IQDCAEN 11
4943 #define M_FW_IQ_CMD_IQDCAEN 0x1
4944 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN)
4945 #define G_FW_IQ_CMD_IQDCAEN(x) \
4946 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
4947 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U)
4949 #define S_FW_IQ_CMD_IQDCACPU 6
4950 #define M_FW_IQ_CMD_IQDCACPU 0x1f
4951 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU)
4952 #define G_FW_IQ_CMD_IQDCACPU(x) \
4953 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
4955 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
4956 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
4957 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
4958 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
4959 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
4961 #define S_FW_IQ_CMD_IQO 3
4962 #define M_FW_IQ_CMD_IQO 0x1
4963 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO)
4964 #define G_FW_IQ_CMD_IQO(x) \
4965 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
4966 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U)
4968 #define S_FW_IQ_CMD_IQCPRIO 2
4969 #define M_FW_IQ_CMD_IQCPRIO 0x1
4970 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO)
4971 #define G_FW_IQ_CMD_IQCPRIO(x) \
4972 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
4973 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U)
4975 #define S_FW_IQ_CMD_IQESIZE 0
4976 #define M_FW_IQ_CMD_IQESIZE 0x3
4977 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
4978 #define G_FW_IQ_CMD_IQESIZE(x) \
4979 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
4981 #define S_FW_IQ_CMD_IQNS 31
4982 #define M_FW_IQ_CMD_IQNS 0x1
4983 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS)
4984 #define G_FW_IQ_CMD_IQNS(x) \
4985 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
4986 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U)
4988 #define S_FW_IQ_CMD_IQRO 30
4989 #define M_FW_IQ_CMD_IQRO 0x1
4990 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
4991 #define G_FW_IQ_CMD_IQRO(x) \
4992 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
4993 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
4995 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28
4996 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3
4997 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
4998 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
4999 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5001 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
5002 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
5003 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5004 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
5005 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5006 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5008 #define S_FW_IQ_CMD_IQFLINTISCSIC 26
5009 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1
5010 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5011 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
5012 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5013 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5015 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
5016 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
5017 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5018 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
5019 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5021 #define S_FW_IQ_CMD_FL0CONGDROP 16
5022 #define M_FW_IQ_CMD_FL0CONGDROP 0x1
5023 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP)
5024 #define G_FW_IQ_CMD_FL0CONGDROP(x) \
5025 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5026 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U)
5028 #define S_FW_IQ_CMD_FL0CACHELOCK 15
5029 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1
5030 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5031 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \
5032 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5033 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U)
5035 #define S_FW_IQ_CMD_FL0DBP 14
5036 #define M_FW_IQ_CMD_FL0DBP 0x1
5037 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP)
5038 #define G_FW_IQ_CMD_FL0DBP(x) \
5039 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5040 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U)
5042 #define S_FW_IQ_CMD_FL0DATANS 13
5043 #define M_FW_IQ_CMD_FL0DATANS 0x1
5044 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS)
5045 #define G_FW_IQ_CMD_FL0DATANS(x) \
5046 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5047 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U)
5049 #define S_FW_IQ_CMD_FL0DATARO 12
5050 #define M_FW_IQ_CMD_FL0DATARO 0x1
5051 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
5052 #define G_FW_IQ_CMD_FL0DATARO(x) \
5053 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5054 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
5056 #define S_FW_IQ_CMD_FL0CONGCIF 11
5057 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
5058 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
5059 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
5060 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5061 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
5063 #define S_FW_IQ_CMD_FL0ONCHIP 10
5064 #define M_FW_IQ_CMD_FL0ONCHIP 0x1
5065 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP)
5066 #define G_FW_IQ_CMD_FL0ONCHIP(x) \
5067 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5068 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U)
5070 #define S_FW_IQ_CMD_FL0STATUSPGNS 9
5071 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1
5072 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5073 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
5074 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5075 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5077 #define S_FW_IQ_CMD_FL0STATUSPGRO 8
5078 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1
5079 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5080 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
5081 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5082 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5084 #define S_FW_IQ_CMD_FL0FETCHNS 7
5085 #define M_FW_IQ_CMD_FL0FETCHNS 0x1
5086 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS)
5087 #define G_FW_IQ_CMD_FL0FETCHNS(x) \
5088 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5089 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U)
5091 #define S_FW_IQ_CMD_FL0FETCHRO 6
5092 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
5093 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
5094 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
5095 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5096 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
5098 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
5099 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
5100 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5101 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
5102 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5104 #define S_FW_IQ_CMD_FL0CPRIO 3
5105 #define M_FW_IQ_CMD_FL0CPRIO 0x1
5106 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO)
5107 #define G_FW_IQ_CMD_FL0CPRIO(x) \
5108 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5109 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U)
5111 #define S_FW_IQ_CMD_FL0PADEN 2
5112 #define M_FW_IQ_CMD_FL0PADEN 0x1
5113 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
5114 #define G_FW_IQ_CMD_FL0PADEN(x) \
5115 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5116 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
5118 #define S_FW_IQ_CMD_FL0PACKEN 1
5119 #define M_FW_IQ_CMD_FL0PACKEN 0x1
5120 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
5121 #define G_FW_IQ_CMD_FL0PACKEN(x) \
5122 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5123 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
5125 #define S_FW_IQ_CMD_FL0CONGEN 0
5126 #define M_FW_IQ_CMD_FL0CONGEN 0x1
5127 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
5128 #define G_FW_IQ_CMD_FL0CONGEN(x) \
5129 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5130 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
5132 #define S_FW_IQ_CMD_FL0DCAEN 15
5133 #define M_FW_IQ_CMD_FL0DCAEN 0x1
5134 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN)
5135 #define G_FW_IQ_CMD_FL0DCAEN(x) \
5136 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5137 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U)
5139 #define S_FW_IQ_CMD_FL0DCACPU 10
5140 #define M_FW_IQ_CMD_FL0DCACPU 0x1f
5141 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU)
5142 #define G_FW_IQ_CMD_FL0DCACPU(x) \
5143 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5145 #define S_FW_IQ_CMD_FL0FBMIN 7
5146 #define M_FW_IQ_CMD_FL0FBMIN 0x7
5147 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
5148 #define G_FW_IQ_CMD_FL0FBMIN(x) \
5149 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5151 #define S_FW_IQ_CMD_FL0FBMAX 4
5152 #define M_FW_IQ_CMD_FL0FBMAX 0x7
5153 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
5154 #define G_FW_IQ_CMD_FL0FBMAX(x) \
5155 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5157 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3
5158 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1
5159 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5160 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
5161 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5162 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5164 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
5165 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7
5166 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5167 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
5168 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5170 #define S_FW_IQ_CMD_FL1CNGCHMAP 20
5171 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf
5172 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5173 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
5174 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5176 #define S_FW_IQ_CMD_FL1CONGDROP 16
5177 #define M_FW_IQ_CMD_FL1CONGDROP 0x1
5178 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP)
5179 #define G_FW_IQ_CMD_FL1CONGDROP(x) \
5180 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5181 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U)
5183 #define S_FW_IQ_CMD_FL1CACHELOCK 15
5184 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1
5185 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5186 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \
5187 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5188 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U)
5190 #define S_FW_IQ_CMD_FL1DBP 14
5191 #define M_FW_IQ_CMD_FL1DBP 0x1
5192 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP)
5193 #define G_FW_IQ_CMD_FL1DBP(x) \
5194 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5195 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U)
5197 #define S_FW_IQ_CMD_FL1DATANS 13
5198 #define M_FW_IQ_CMD_FL1DATANS 0x1
5199 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS)
5200 #define G_FW_IQ_CMD_FL1DATANS(x) \
5201 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5202 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U)
5204 #define S_FW_IQ_CMD_FL1DATARO 12
5205 #define M_FW_IQ_CMD_FL1DATARO 0x1
5206 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO)
5207 #define G_FW_IQ_CMD_FL1DATARO(x) \
5208 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5209 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U)
5211 #define S_FW_IQ_CMD_FL1CONGCIF 11
5212 #define M_FW_IQ_CMD_FL1CONGCIF 0x1
5213 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF)
5214 #define G_FW_IQ_CMD_FL1CONGCIF(x) \
5215 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5216 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U)
5218 #define S_FW_IQ_CMD_FL1ONCHIP 10
5219 #define M_FW_IQ_CMD_FL1ONCHIP 0x1
5220 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP)
5221 #define G_FW_IQ_CMD_FL1ONCHIP(x) \
5222 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5223 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U)
5225 #define S_FW_IQ_CMD_FL1STATUSPGNS 9
5226 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1
5227 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5228 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
5229 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5230 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5232 #define S_FW_IQ_CMD_FL1STATUSPGRO 8
5233 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1
5234 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5235 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
5236 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5237 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5239 #define S_FW_IQ_CMD_FL1FETCHNS 7
5240 #define M_FW_IQ_CMD_FL1FETCHNS 0x1
5241 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS)
5242 #define G_FW_IQ_CMD_FL1FETCHNS(x) \
5243 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5244 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U)
5246 #define S_FW_IQ_CMD_FL1FETCHRO 6
5247 #define M_FW_IQ_CMD_FL1FETCHRO 0x1
5248 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO)
5249 #define G_FW_IQ_CMD_FL1FETCHRO(x) \
5250 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5251 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U)
5253 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4
5254 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3
5255 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5256 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
5257 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5259 #define S_FW_IQ_CMD_FL1CPRIO 3
5260 #define M_FW_IQ_CMD_FL1CPRIO 0x1
5261 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO)
5262 #define G_FW_IQ_CMD_FL1CPRIO(x) \
5263 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5264 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U)
5266 #define S_FW_IQ_CMD_FL1PADEN 2
5267 #define M_FW_IQ_CMD_FL1PADEN 0x1
5268 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN)
5269 #define G_FW_IQ_CMD_FL1PADEN(x) \
5270 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5271 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U)
5273 #define S_FW_IQ_CMD_FL1PACKEN 1
5274 #define M_FW_IQ_CMD_FL1PACKEN 0x1
5275 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN)
5276 #define G_FW_IQ_CMD_FL1PACKEN(x) \
5277 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5278 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U)
5280 #define S_FW_IQ_CMD_FL1CONGEN 0
5281 #define M_FW_IQ_CMD_FL1CONGEN 0x1
5282 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN)
5283 #define G_FW_IQ_CMD_FL1CONGEN(x) \
5284 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5285 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U)
5287 #define S_FW_IQ_CMD_FL1DCAEN 15
5288 #define M_FW_IQ_CMD_FL1DCAEN 0x1
5289 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN)
5290 #define G_FW_IQ_CMD_FL1DCAEN(x) \
5291 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5292 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U)
5294 #define S_FW_IQ_CMD_FL1DCACPU 10
5295 #define M_FW_IQ_CMD_FL1DCACPU 0x1f
5296 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU)
5297 #define G_FW_IQ_CMD_FL1DCACPU(x) \
5298 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5300 #define S_FW_IQ_CMD_FL1FBMIN 7
5301 #define M_FW_IQ_CMD_FL1FBMIN 0x7
5302 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN)
5303 #define G_FW_IQ_CMD_FL1FBMIN(x) \
5304 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5306 #define S_FW_IQ_CMD_FL1FBMAX 4
5307 #define M_FW_IQ_CMD_FL1FBMAX 0x7
5308 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX)
5309 #define G_FW_IQ_CMD_FL1FBMAX(x) \
5310 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5312 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3
5313 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1
5314 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5315 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
5316 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5317 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5319 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
5320 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7
5321 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5322 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
5323 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5325 struct fw_eq_mngt_cmd {
5327 __be32 alloc_to_len16;
5328 __be32 cmpliqid_eqid;
5329 __be32 physeqid_pkd;
5330 __be32 fetchszm_to_iqid;
5331 __be32 dcaen_to_eqsize;
5335 #define S_FW_EQ_MNGT_CMD_PFN 8
5336 #define M_FW_EQ_MNGT_CMD_PFN 0x7
5337 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN)
5338 #define G_FW_EQ_MNGT_CMD_PFN(x) \
5339 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5341 #define S_FW_EQ_MNGT_CMD_VFN 0
5342 #define M_FW_EQ_MNGT_CMD_VFN 0xff
5343 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN)
5344 #define G_FW_EQ_MNGT_CMD_VFN(x) \
5345 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5347 #define S_FW_EQ_MNGT_CMD_ALLOC 31
5348 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1
5349 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5350 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \
5351 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5352 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U)
5354 #define S_FW_EQ_MNGT_CMD_FREE 30
5355 #define M_FW_EQ_MNGT_CMD_FREE 0x1
5356 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE)
5357 #define G_FW_EQ_MNGT_CMD_FREE(x) \
5358 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5359 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U)
5361 #define S_FW_EQ_MNGT_CMD_MODIFY 29
5362 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1
5363 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5364 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \
5365 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5366 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U)
5368 #define S_FW_EQ_MNGT_CMD_EQSTART 28
5369 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1
5370 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5371 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \
5372 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5373 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U)
5375 #define S_FW_EQ_MNGT_CMD_EQSTOP 27
5376 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1
5377 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5378 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
5379 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5380 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5382 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20
5383 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff
5384 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5385 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
5386 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5388 #define S_FW_EQ_MNGT_CMD_EQID 0
5389 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff
5390 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID)
5391 #define G_FW_EQ_MNGT_CMD_EQID(x) \
5392 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5394 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0
5395 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff
5396 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5397 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
5398 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5400 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26
5401 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1
5402 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5403 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
5404 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5405 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5407 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25
5408 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1
5409 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5410 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
5411 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5412 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5414 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24
5415 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1
5416 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5417 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
5418 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5419 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5421 #define S_FW_EQ_MNGT_CMD_FETCHNS 23
5422 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1
5423 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5424 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
5425 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5426 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5428 #define S_FW_EQ_MNGT_CMD_FETCHRO 22
5429 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1
5430 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5431 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
5432 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5433 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5435 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20
5436 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3
5437 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5438 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
5439 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5441 #define S_FW_EQ_MNGT_CMD_CPRIO 19
5442 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1
5443 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5444 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \
5445 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5446 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U)
5448 #define S_FW_EQ_MNGT_CMD_ONCHIP 18
5449 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1
5450 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5451 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
5452 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5453 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5455 #define S_FW_EQ_MNGT_CMD_PCIECHN 16
5456 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3
5457 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5458 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
5459 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5461 #define S_FW_EQ_MNGT_CMD_IQID 0
5462 #define M_FW_EQ_MNGT_CMD_IQID 0xffff
5463 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID)
5464 #define G_FW_EQ_MNGT_CMD_IQID(x) \
5465 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5467 #define S_FW_EQ_MNGT_CMD_DCAEN 31
5468 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1
5469 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5470 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \
5471 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5472 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U)
5474 #define S_FW_EQ_MNGT_CMD_DCACPU 26
5475 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f
5476 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5477 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \
5478 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5480 #define S_FW_EQ_MNGT_CMD_FBMIN 23
5481 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7
5482 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5483 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \
5484 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5486 #define S_FW_EQ_MNGT_CMD_FBMAX 20
5487 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7
5488 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5489 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \
5490 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5492 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19
5493 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1
5494 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5495 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5496 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5497 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5498 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5500 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16
5501 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7
5502 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5503 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
5504 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5506 #define S_FW_EQ_MNGT_CMD_EQSIZE 0
5507 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff
5508 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5509 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
5510 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5512 struct fw_eq_eth_cmd {
5514 __be32 alloc_to_len16;
5516 __be32 physeqid_pkd;
5517 __be32 fetchszm_to_iqid;
5518 __be32 dcaen_to_eqsize;
5520 __be32 autoequiqe_to_viid;
5525 #define S_FW_EQ_ETH_CMD_PFN 8
5526 #define M_FW_EQ_ETH_CMD_PFN 0x7
5527 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
5528 #define G_FW_EQ_ETH_CMD_PFN(x) \
5529 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5531 #define S_FW_EQ_ETH_CMD_VFN 0
5532 #define M_FW_EQ_ETH_CMD_VFN 0xff
5533 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
5534 #define G_FW_EQ_ETH_CMD_VFN(x) \
5535 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5537 #define S_FW_EQ_ETH_CMD_ALLOC 31
5538 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
5539 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
5540 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
5541 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5542 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
5544 #define S_FW_EQ_ETH_CMD_FREE 30
5545 #define M_FW_EQ_ETH_CMD_FREE 0x1
5546 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
5547 #define G_FW_EQ_ETH_CMD_FREE(x) \
5548 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5549 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
5551 #define S_FW_EQ_ETH_CMD_MODIFY 29
5552 #define M_FW_EQ_ETH_CMD_MODIFY 0x1
5553 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY)
5554 #define G_FW_EQ_ETH_CMD_MODIFY(x) \
5555 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5556 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U)
5558 #define S_FW_EQ_ETH_CMD_EQSTART 28
5559 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
5560 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
5561 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
5562 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5563 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
5565 #define S_FW_EQ_ETH_CMD_EQSTOP 27
5566 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1
5567 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5568 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \
5569 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5570 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U)
5572 #define S_FW_EQ_ETH_CMD_EQID 0
5573 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
5574 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
5575 #define G_FW_EQ_ETH_CMD_EQID(x) \
5576 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5578 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
5579 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
5580 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5581 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
5582 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5584 #define S_FW_EQ_ETH_CMD_FETCHSZM 26
5585 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1
5586 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5587 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
5588 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5589 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U)
5591 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25
5592 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1
5593 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
5594 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
5595 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
5596 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
5598 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24
5599 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1
5600 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
5601 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
5602 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
5603 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
5605 #define S_FW_EQ_ETH_CMD_FETCHNS 23
5606 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1
5607 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS)
5608 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \
5609 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
5610 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U)
5612 #define S_FW_EQ_ETH_CMD_FETCHRO 22
5613 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
5614 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
5615 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
5616 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
5617 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
5619 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
5620 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
5621 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
5622 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
5623 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
5625 #define S_FW_EQ_ETH_CMD_CPRIO 19
5626 #define M_FW_EQ_ETH_CMD_CPRIO 0x1
5627 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO)
5628 #define G_FW_EQ_ETH_CMD_CPRIO(x) \
5629 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
5630 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U)
5632 #define S_FW_EQ_ETH_CMD_ONCHIP 18
5633 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1
5634 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP)
5635 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \
5636 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
5637 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U)
5639 #define S_FW_EQ_ETH_CMD_PCIECHN 16
5640 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
5641 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
5642 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
5643 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
5645 #define S_FW_EQ_ETH_CMD_IQID 0
5646 #define M_FW_EQ_ETH_CMD_IQID 0xffff
5647 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
5648 #define G_FW_EQ_ETH_CMD_IQID(x) \
5649 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
5651 #define S_FW_EQ_ETH_CMD_DCAEN 31
5652 #define M_FW_EQ_ETH_CMD_DCAEN 0x1
5653 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN)
5654 #define G_FW_EQ_ETH_CMD_DCAEN(x) \
5655 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
5656 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U)
5658 #define S_FW_EQ_ETH_CMD_DCACPU 26
5659 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f
5660 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU)
5661 #define G_FW_EQ_ETH_CMD_DCACPU(x) \
5662 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
5664 #define S_FW_EQ_ETH_CMD_FBMIN 23
5665 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
5666 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
5667 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
5668 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
5670 #define S_FW_EQ_ETH_CMD_FBMAX 20
5671 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
5672 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
5673 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
5674 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
5676 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19
5677 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1
5678 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5679 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
5680 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5681 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
5683 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
5684 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
5685 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
5686 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
5687 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
5689 #define S_FW_EQ_ETH_CMD_EQSIZE 0
5690 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
5691 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
5692 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
5693 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
5695 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
5696 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
5697 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
5698 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
5699 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
5700 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
5702 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
5703 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
5704 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
5705 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
5706 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
5707 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
5709 #define S_FW_EQ_ETH_CMD_VIID 16
5710 #define M_FW_EQ_ETH_CMD_VIID 0xfff
5711 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
5712 #define G_FW_EQ_ETH_CMD_VIID(x) \
5713 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
5715 struct fw_eq_ctrl_cmd {
5717 __be32 alloc_to_len16;
5718 __be32 cmpliqid_eqid;
5719 __be32 physeqid_pkd;
5720 __be32 fetchszm_to_iqid;
5721 __be32 dcaen_to_eqsize;
5725 #define S_FW_EQ_CTRL_CMD_PFN 8
5726 #define M_FW_EQ_CTRL_CMD_PFN 0x7
5727 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
5728 #define G_FW_EQ_CTRL_CMD_PFN(x) \
5729 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
5731 #define S_FW_EQ_CTRL_CMD_VFN 0
5732 #define M_FW_EQ_CTRL_CMD_VFN 0xff
5733 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
5734 #define G_FW_EQ_CTRL_CMD_VFN(x) \
5735 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
5737 #define S_FW_EQ_CTRL_CMD_ALLOC 31
5738 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1
5739 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
5740 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \
5741 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
5742 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
5744 #define S_FW_EQ_CTRL_CMD_FREE 30
5745 #define M_FW_EQ_CTRL_CMD_FREE 0x1
5746 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
5747 #define G_FW_EQ_CTRL_CMD_FREE(x) \
5748 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
5749 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
5751 #define S_FW_EQ_CTRL_CMD_MODIFY 29
5752 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1
5753 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY)
5754 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \
5755 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
5756 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U)
5758 #define S_FW_EQ_CTRL_CMD_EQSTART 28
5759 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1
5760 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
5761 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \
5762 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
5763 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
5765 #define S_FW_EQ_CTRL_CMD_EQSTOP 27
5766 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1
5767 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
5768 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
5769 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
5770 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U)
5772 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
5773 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff
5774 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
5775 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
5776 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
5778 #define S_FW_EQ_CTRL_CMD_EQID 0
5779 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
5780 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
5781 #define G_FW_EQ_CTRL_CMD_EQID(x) \
5782 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
5784 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
5785 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
5786 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
5787 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
5788 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
5790 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26
5791 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1
5792 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
5793 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
5794 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
5795 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
5797 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25
5798 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1
5799 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
5800 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
5801 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
5802 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
5804 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24
5805 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1
5806 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
5807 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
5808 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
5809 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
5811 #define S_FW_EQ_CTRL_CMD_FETCHNS 23
5812 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1
5813 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
5814 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
5815 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
5816 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U)
5818 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
5819 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1
5820 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
5821 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
5822 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
5823 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
5825 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
5826 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
5827 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
5828 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
5829 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
5831 #define S_FW_EQ_CTRL_CMD_CPRIO 19
5832 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1
5833 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO)
5834 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \
5835 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
5836 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U)
5838 #define S_FW_EQ_CTRL_CMD_ONCHIP 18
5839 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1
5840 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
5841 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
5842 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
5843 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U)
5845 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
5846 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3
5847 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
5848 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
5849 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
5851 #define S_FW_EQ_CTRL_CMD_IQID 0
5852 #define M_FW_EQ_CTRL_CMD_IQID 0xffff
5853 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
5854 #define G_FW_EQ_CTRL_CMD_IQID(x) \
5855 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
5857 #define S_FW_EQ_CTRL_CMD_DCAEN 31
5858 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1
5859 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN)
5860 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \
5861 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
5862 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U)
5864 #define S_FW_EQ_CTRL_CMD_DCACPU 26
5865 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f
5866 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU)
5867 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \
5868 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
5870 #define S_FW_EQ_CTRL_CMD_FBMIN 23
5871 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7
5872 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
5873 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \
5874 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
5876 #define S_FW_EQ_CTRL_CMD_FBMAX 20
5877 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7
5878 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
5879 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \
5880 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
5882 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19
5883 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1
5884 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
5885 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
5886 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
5887 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
5888 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
5890 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
5891 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7
5892 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
5893 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
5894 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
5896 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
5897 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff
5898 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
5899 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
5900 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
5902 struct fw_eq_ofld_cmd {
5904 __be32 alloc_to_len16;
5906 __be32 physeqid_pkd;
5907 __be32 fetchszm_to_iqid;
5908 __be32 dcaen_to_eqsize;
5912 #define S_FW_EQ_OFLD_CMD_PFN 8
5913 #define M_FW_EQ_OFLD_CMD_PFN 0x7
5914 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN)
5915 #define G_FW_EQ_OFLD_CMD_PFN(x) \
5916 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
5918 #define S_FW_EQ_OFLD_CMD_VFN 0
5919 #define M_FW_EQ_OFLD_CMD_VFN 0xff
5920 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN)
5921 #define G_FW_EQ_OFLD_CMD_VFN(x) \
5922 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
5924 #define S_FW_EQ_OFLD_CMD_ALLOC 31
5925 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1
5926 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC)
5927 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \
5928 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
5929 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U)
5931 #define S_FW_EQ_OFLD_CMD_FREE 30
5932 #define M_FW_EQ_OFLD_CMD_FREE 0x1
5933 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE)
5934 #define G_FW_EQ_OFLD_CMD_FREE(x) \
5935 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
5936 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U)
5938 #define S_FW_EQ_OFLD_CMD_MODIFY 29
5939 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1
5940 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY)
5941 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \
5942 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
5943 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U)
5945 #define S_FW_EQ_OFLD_CMD_EQSTART 28
5946 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1
5947 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART)
5948 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \
5949 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
5950 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U)
5952 #define S_FW_EQ_OFLD_CMD_EQSTOP 27
5953 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1
5954 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
5955 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
5956 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
5957 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U)
5959 #define S_FW_EQ_OFLD_CMD_EQID 0
5960 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff
5961 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID)
5962 #define G_FW_EQ_OFLD_CMD_EQID(x) \
5963 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
5965 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0
5966 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff
5967 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
5968 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
5969 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
5971 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26
5972 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1
5973 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
5974 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
5975 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
5976 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
5978 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25
5979 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1
5980 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
5981 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
5982 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
5983 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
5985 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24
5986 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1
5987 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
5988 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
5989 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
5990 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
5992 #define S_FW_EQ_OFLD_CMD_FETCHNS 23
5993 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1
5994 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
5995 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
5996 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
5997 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U)
5999 #define S_FW_EQ_OFLD_CMD_FETCHRO 22
6000 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1
6001 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6002 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
6003 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6004 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6006 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20
6007 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3
6008 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6009 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
6010 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6012 #define S_FW_EQ_OFLD_CMD_CPRIO 19
6013 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1
6014 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6015 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \
6016 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6017 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U)
6019 #define S_FW_EQ_OFLD_CMD_ONCHIP 18
6020 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1
6021 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6022 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
6023 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6024 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6026 #define S_FW_EQ_OFLD_CMD_PCIECHN 16
6027 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3
6028 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6029 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
6030 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6032 #define S_FW_EQ_OFLD_CMD_IQID 0
6033 #define M_FW_EQ_OFLD_CMD_IQID 0xffff
6034 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID)
6035 #define G_FW_EQ_OFLD_CMD_IQID(x) \
6036 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6038 #define S_FW_EQ_OFLD_CMD_DCAEN 31
6039 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1
6040 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6041 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \
6042 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6043 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U)
6045 #define S_FW_EQ_OFLD_CMD_DCACPU 26
6046 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f
6047 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6048 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \
6049 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6051 #define S_FW_EQ_OFLD_CMD_FBMIN 23
6052 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7
6053 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6054 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \
6055 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6057 #define S_FW_EQ_OFLD_CMD_FBMAX 20
6058 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7
6059 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6060 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \
6061 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6063 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19
6064 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1
6065 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6066 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6067 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6068 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6069 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6071 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16
6072 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7
6073 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6074 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
6075 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6077 #define S_FW_EQ_OFLD_CMD_EQSIZE 0
6078 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff
6079 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6080 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
6081 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6083 /* Macros for VIID parsing:
6084 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6085 #define S_FW_VIID_PFN 8
6086 #define M_FW_VIID_PFN 0x7
6087 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN)
6088 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6090 #define S_FW_VIID_VIVLD 7
6091 #define M_FW_VIID_VIVLD 0x1
6092 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD)
6093 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6095 #define S_FW_VIID_VIN 0
6096 #define M_FW_VIID_VIN 0x7F
6097 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
6098 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6104 FW_VI_FUNC_OPENISCSI,
6105 FW_VI_FUNC_OPENFCOE,
6113 __be32 alloc_to_len16;
6114 __be16 type_to_viid;
6119 __be16 norss_rsssize;
6129 #define S_FW_VI_CMD_PFN 8
6130 #define M_FW_VI_CMD_PFN 0x7
6131 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
6132 #define G_FW_VI_CMD_PFN(x) \
6133 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6135 #define S_FW_VI_CMD_VFN 0
6136 #define M_FW_VI_CMD_VFN 0xff
6137 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
6138 #define G_FW_VI_CMD_VFN(x) \
6139 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6141 #define S_FW_VI_CMD_ALLOC 31
6142 #define M_FW_VI_CMD_ALLOC 0x1
6143 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
6144 #define G_FW_VI_CMD_ALLOC(x) \
6145 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6146 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
6148 #define S_FW_VI_CMD_FREE 30
6149 #define M_FW_VI_CMD_FREE 0x1
6150 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
6151 #define G_FW_VI_CMD_FREE(x) \
6152 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6153 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
6155 #define S_FW_VI_CMD_TYPE 15
6156 #define M_FW_VI_CMD_TYPE 0x1
6157 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
6158 #define G_FW_VI_CMD_TYPE(x) \
6159 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6160 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
6162 #define S_FW_VI_CMD_FUNC 12
6163 #define M_FW_VI_CMD_FUNC 0x7
6164 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
6165 #define G_FW_VI_CMD_FUNC(x) \
6166 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6168 #define S_FW_VI_CMD_VIID 0
6169 #define M_FW_VI_CMD_VIID 0xfff
6170 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
6171 #define G_FW_VI_CMD_VIID(x) \
6172 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6174 #define S_FW_VI_CMD_PORTID 4
6175 #define M_FW_VI_CMD_PORTID 0xf
6176 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
6177 #define G_FW_VI_CMD_PORTID(x) \
6178 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6180 #define S_FW_VI_CMD_NORSS 11
6181 #define M_FW_VI_CMD_NORSS 0x1
6182 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS)
6183 #define G_FW_VI_CMD_NORSS(x) \
6184 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6185 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U)
6187 #define S_FW_VI_CMD_RSSSIZE 0
6188 #define M_FW_VI_CMD_RSSSIZE 0x7ff
6189 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
6190 #define G_FW_VI_CMD_RSSSIZE(x) \
6191 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6193 #define S_FW_VI_CMD_IDSIIQ 0
6194 #define M_FW_VI_CMD_IDSIIQ 0x3ff
6195 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ)
6196 #define G_FW_VI_CMD_IDSIIQ(x) \
6197 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6199 #define S_FW_VI_CMD_IDSEIQ 0
6200 #define M_FW_VI_CMD_IDSEIQ 0x3ff
6201 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ)
6202 #define G_FW_VI_CMD_IDSEIQ(x) \
6203 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6205 /* Special VI_MAC command index ids */
6206 #define FW_VI_MAC_ADD_MAC 0x3FF
6207 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
6208 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
6210 enum fw_vi_mac_smac {
6211 FW_VI_MAC_MPS_TCAM_ENTRY,
6212 FW_VI_MAC_MPS_TCAM_ONLY,
6214 FW_VI_MAC_SMT_AND_MPSTCAM
6217 enum fw_vi_mac_result {
6218 FW_VI_MAC_R_SUCCESS,
6219 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6220 FW_VI_MAC_R_SMAC_FAIL,
6221 FW_VI_MAC_R_F_ACL_CHECK
6224 enum fw_vi_mac_entry_types {
6225 FW_VI_MAC_TYPE_EXACTMAC,
6226 FW_VI_MAC_TYPE_HASHVEC,
6228 FW_VI_MAC_TYPE_EXACTMAC_VNI,
6231 struct fw_vi_mac_cmd {
6233 __be32 freemacs_to_len16;
6235 struct fw_vi_mac_exact {
6236 __be16 valid_to_idx;
6239 struct fw_vi_mac_hash {
6242 struct fw_vi_mac_raw {
6249 struct fw_vi_mac_vni {
6250 __be16 valid_to_idx;
6253 __u8 macaddr_mask[6];
6254 __be32 lookup_type_to_vni;
6255 __be32 vni_mask_pkd;
6260 #define S_FW_VI_MAC_CMD_VIID 0
6261 #define M_FW_VI_MAC_CMD_VIID 0xfff
6262 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
6263 #define G_FW_VI_MAC_CMD_VIID(x) \
6264 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6266 #define S_FW_VI_MAC_CMD_FREEMACS 31
6267 #define M_FW_VI_MAC_CMD_FREEMACS 0x1
6268 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
6269 #define G_FW_VI_MAC_CMD_FREEMACS(x) \
6270 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6271 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
6273 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
6274 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
6275 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6276 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \
6277 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6279 #define S_FW_VI_MAC_CMD_HASHUNIEN 22
6280 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
6281 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6282 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
6283 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6284 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6286 #define S_FW_VI_MAC_CMD_VALID 15
6287 #define M_FW_VI_MAC_CMD_VALID 0x1
6288 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
6289 #define G_FW_VI_MAC_CMD_VALID(x) \
6290 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6291 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
6293 #define S_FW_VI_MAC_CMD_PRIO 12
6294 #define M_FW_VI_MAC_CMD_PRIO 0x7
6295 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO)
6296 #define G_FW_VI_MAC_CMD_PRIO(x) \
6297 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6299 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
6300 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
6301 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6302 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
6303 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6305 #define S_FW_VI_MAC_CMD_IDX 0
6306 #define M_FW_VI_MAC_CMD_IDX 0x3ff
6307 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
6308 #define G_FW_VI_MAC_CMD_IDX(x) \
6309 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6311 #define S_FW_VI_MAC_CMD_RAW_IDX 16
6312 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
6313 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6314 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
6315 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6317 #define S_FW_VI_MAC_CMD_DATA0 0
6318 #define M_FW_VI_MAC_CMD_DATA0 0xffff
6319 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0)
6320 #define G_FW_VI_MAC_CMD_DATA0(x) \
6321 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6323 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31
6324 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1
6325 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
6326 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \
6327 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
6328 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
6330 #define S_FW_VI_MAC_CMD_DIP_HIT 30
6331 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1
6332 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT)
6333 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \
6334 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
6335 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U)
6337 #define S_FW_VI_MAC_CMD_VNI 0
6338 #define M_FW_VI_MAC_CMD_VNI 0xffffff
6339 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI)
6340 #define G_FW_VI_MAC_CMD_VNI(x) \
6341 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
6343 #define S_FW_VI_MAC_CMD_VNI_MASK 0
6344 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff
6345 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK)
6346 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \
6347 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
6349 /* T4 max MTU supported */
6350 #define T4_MAX_MTU_SUPPORTED 9600
6351 #define FW_RXMODE_MTU_NO_CHG 65535
6353 struct fw_vi_rxmode_cmd {
6355 __be32 retval_len16;
6356 __be32 mtu_to_vlanexen;
6360 #define S_FW_VI_RXMODE_CMD_VIID 0
6361 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
6362 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
6363 #define G_FW_VI_RXMODE_CMD_VIID(x) \
6364 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6366 #define S_FW_VI_RXMODE_CMD_MTU 16
6367 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
6368 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
6369 #define G_FW_VI_RXMODE_CMD_MTU(x) \
6370 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6372 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
6373 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
6374 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6375 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
6376 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6378 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
6379 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
6380 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6381 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6382 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6383 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6385 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
6386 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
6387 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6388 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6389 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6390 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6392 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
6393 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
6394 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6395 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
6396 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6398 struct fw_vi_enable_cmd {
6400 __be32 ien_to_len16;
6406 #define S_FW_VI_ENABLE_CMD_VIID 0
6407 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
6408 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
6409 #define G_FW_VI_ENABLE_CMD_VIID(x) \
6410 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6412 #define S_FW_VI_ENABLE_CMD_IEN 31
6413 #define M_FW_VI_ENABLE_CMD_IEN 0x1
6414 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
6415 #define G_FW_VI_ENABLE_CMD_IEN(x) \
6416 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6417 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
6419 #define S_FW_VI_ENABLE_CMD_EEN 30
6420 #define M_FW_VI_ENABLE_CMD_EEN 0x1
6421 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
6422 #define G_FW_VI_ENABLE_CMD_EEN(x) \
6423 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6424 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
6426 #define S_FW_VI_ENABLE_CMD_LED 29
6427 #define M_FW_VI_ENABLE_CMD_LED 0x1
6428 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED)
6429 #define G_FW_VI_ENABLE_CMD_LED(x) \
6430 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6431 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U)
6433 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
6434 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
6435 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6436 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
6437 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6438 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6440 /* VI VF stats offset definitions */
6441 #define VI_VF_NUM_STATS 16
6442 enum fw_vi_stats_vf_index {
6443 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6444 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6445 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6446 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6447 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6448 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6449 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6450 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6451 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6452 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6453 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6454 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6455 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6456 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6457 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6458 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6461 /* VI PF stats offset definitions */
6462 #define VI_PF_NUM_STATS 17
6463 enum fw_vi_stats_pf_index {
6464 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6465 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6466 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6467 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6468 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6469 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6470 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6471 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6472 FW_VI_PF_STAT_RX_BYTES_IX,
6473 FW_VI_PF_STAT_RX_FRAMES_IX,
6474 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6475 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6476 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6477 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6478 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6479 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6480 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6483 struct fw_vi_stats_cmd {
6485 __be32 retval_len16;
6487 struct fw_vi_stats_ctl {
6498 struct fw_vi_stats_pf {
6499 __be64 tx_bcast_bytes;
6500 __be64 tx_bcast_frames;
6501 __be64 tx_mcast_bytes;
6502 __be64 tx_mcast_frames;
6503 __be64 tx_ucast_bytes;
6504 __be64 tx_ucast_frames;
6505 __be64 tx_offload_bytes;
6506 __be64 tx_offload_frames;
6508 __be64 rx_pf_frames;
6509 __be64 rx_bcast_bytes;
6510 __be64 rx_bcast_frames;
6511 __be64 rx_mcast_bytes;
6512 __be64 rx_mcast_frames;
6513 __be64 rx_ucast_bytes;
6514 __be64 rx_ucast_frames;
6515 __be64 rx_err_frames;
6517 struct fw_vi_stats_vf {
6518 __be64 tx_bcast_bytes;
6519 __be64 tx_bcast_frames;
6520 __be64 tx_mcast_bytes;
6521 __be64 tx_mcast_frames;
6522 __be64 tx_ucast_bytes;
6523 __be64 tx_ucast_frames;
6524 __be64 tx_drop_frames;
6525 __be64 tx_offload_bytes;
6526 __be64 tx_offload_frames;
6527 __be64 rx_bcast_bytes;
6528 __be64 rx_bcast_frames;
6529 __be64 rx_mcast_bytes;
6530 __be64 rx_mcast_frames;
6531 __be64 rx_ucast_bytes;
6532 __be64 rx_ucast_frames;
6533 __be64 rx_err_frames;
6538 #define S_FW_VI_STATS_CMD_VIID 0
6539 #define M_FW_VI_STATS_CMD_VIID 0xfff
6540 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
6541 #define G_FW_VI_STATS_CMD_VIID(x) \
6542 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
6544 #define S_FW_VI_STATS_CMD_NSTATS 12
6545 #define M_FW_VI_STATS_CMD_NSTATS 0x7
6546 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
6547 #define G_FW_VI_STATS_CMD_NSTATS(x) \
6548 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
6550 #define S_FW_VI_STATS_CMD_IX 0
6551 #define M_FW_VI_STATS_CMD_IX 0x1f
6552 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
6553 #define G_FW_VI_STATS_CMD_IX(x) \
6554 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
6556 struct fw_acl_mac_cmd {
6571 #define S_FW_ACL_MAC_CMD_PFN 8
6572 #define M_FW_ACL_MAC_CMD_PFN 0x7
6573 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN)
6574 #define G_FW_ACL_MAC_CMD_PFN(x) \
6575 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
6577 #define S_FW_ACL_MAC_CMD_VFN 0
6578 #define M_FW_ACL_MAC_CMD_VFN 0xff
6579 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN)
6580 #define G_FW_ACL_MAC_CMD_VFN(x) \
6581 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
6583 #define S_FW_ACL_MAC_CMD_EN 31
6584 #define M_FW_ACL_MAC_CMD_EN 0x1
6585 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN)
6586 #define G_FW_ACL_MAC_CMD_EN(x) \
6587 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
6588 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U)
6590 struct fw_acl_vlan_cmd {
6599 #define S_FW_ACL_VLAN_CMD_PFN 8
6600 #define M_FW_ACL_VLAN_CMD_PFN 0x7
6601 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN)
6602 #define G_FW_ACL_VLAN_CMD_PFN(x) \
6603 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
6605 #define S_FW_ACL_VLAN_CMD_VFN 0
6606 #define M_FW_ACL_VLAN_CMD_VFN 0xff
6607 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN)
6608 #define G_FW_ACL_VLAN_CMD_VFN(x) \
6609 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
6611 #define S_FW_ACL_VLAN_CMD_EN 31
6612 #define M_FW_ACL_VLAN_CMD_EN 0x1
6613 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN)
6614 #define G_FW_ACL_VLAN_CMD_EN(x) \
6615 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
6616 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
6618 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
6619 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
6620 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
6621 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
6622 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
6623 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
6625 #define S_FW_ACL_VLAN_CMD_FM 6
6626 #define M_FW_ACL_VLAN_CMD_FM 0x1
6627 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM)
6628 #define G_FW_ACL_VLAN_CMD_FM(x) \
6629 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
6630 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
6632 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
6634 FW_PORT_CAP_SPEED_100M = 0x0001,
6635 FW_PORT_CAP_SPEED_1G = 0x0002,
6636 FW_PORT_CAP_SPEED_25G = 0x0004,
6637 FW_PORT_CAP_SPEED_10G = 0x0008,
6638 FW_PORT_CAP_SPEED_40G = 0x0010,
6639 FW_PORT_CAP_SPEED_100G = 0x0020,
6640 FW_PORT_CAP_FC_RX = 0x0040,
6641 FW_PORT_CAP_FC_TX = 0x0080,
6642 FW_PORT_CAP_ANEG = 0x0100,
6643 FW_PORT_CAP_MDIX = 0x0200,
6644 FW_PORT_CAP_MDIAUTO = 0x0400,
6645 FW_PORT_CAP_FEC_RS = 0x0800,
6646 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
6647 FW_PORT_CAP_FEC_RESERVED = 0x2000,
6648 FW_PORT_CAP_802_3_PAUSE = 0x4000,
6649 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
6652 #define S_FW_PORT_CAP_SPEED 0
6653 #define M_FW_PORT_CAP_SPEED 0x3f
6654 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
6655 #define G_FW_PORT_CAP_SPEED(x) \
6656 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
6658 #define S_FW_PORT_CAP_FC 6
6659 #define M_FW_PORT_CAP_FC 0x3
6660 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC)
6661 #define G_FW_PORT_CAP_FC(x) \
6662 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
6664 #define S_FW_PORT_CAP_ANEG 8
6665 #define M_FW_PORT_CAP_ANEG 0x1
6666 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG)
6667 #define G_FW_PORT_CAP_ANEG(x) \
6668 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
6670 #define S_FW_PORT_CAP_FEC 11
6671 #define M_FW_PORT_CAP_FEC 0x7
6672 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
6673 #define G_FW_PORT_CAP_FEC(x) \
6674 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
6676 #define S_FW_PORT_CAP_802_3 14
6677 #define M_FW_PORT_CAP_802_3 0x3
6678 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
6679 #define G_FW_PORT_CAP_802_3(x) \
6680 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
6683 FW_PORT_CAP_MDI_UNCHANGED,
6684 FW_PORT_CAP_MDI_AUTO,
6685 FW_PORT_CAP_MDI_F_STRAIGHT,
6686 FW_PORT_CAP_MDI_F_CROSSOVER
6689 #define S_FW_PORT_CAP_MDI 9
6690 #define M_FW_PORT_CAP_MDI 3
6691 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
6692 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
6694 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
6695 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
6696 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
6697 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
6698 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
6699 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
6700 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
6701 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
6702 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
6703 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
6704 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
6705 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
6706 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
6707 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
6708 #define FW_PORT_CAP32_FC_RX 0x00010000UL
6709 #define FW_PORT_CAP32_FC_TX 0x00020000UL
6710 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
6711 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
6712 #define FW_PORT_CAP32_ANEG 0x00100000UL
6713 #define FW_PORT_CAP32_MDIX 0x00200000UL
6714 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
6715 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
6716 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
6717 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
6718 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
6719 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
6720 #define FW_PORT_CAP32_RESERVED2 0xf0000000UL
6722 #define S_FW_PORT_CAP32_SPEED 0
6723 #define M_FW_PORT_CAP32_SPEED 0xfff
6724 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
6725 #define G_FW_PORT_CAP32_SPEED(x) \
6726 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
6728 #define S_FW_PORT_CAP32_FC 16
6729 #define M_FW_PORT_CAP32_FC 0x3
6730 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC)
6731 #define G_FW_PORT_CAP32_FC(x) \
6732 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
6734 #define S_FW_PORT_CAP32_802_3 18
6735 #define M_FW_PORT_CAP32_802_3 0x3
6736 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3)
6737 #define G_FW_PORT_CAP32_802_3(x) \
6738 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
6740 #define S_FW_PORT_CAP32_ANEG 20
6741 #define M_FW_PORT_CAP32_ANEG 0x1
6742 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG)
6743 #define G_FW_PORT_CAP32_ANEG(x) \
6744 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
6746 enum fw_port_mdi32 {
6747 FW_PORT_CAP32_MDI_UNCHANGED,
6748 FW_PORT_CAP32_MDI_AUTO,
6749 FW_PORT_CAP32_MDI_F_STRAIGHT,
6750 FW_PORT_CAP32_MDI_F_CROSSOVER
6753 #define S_FW_PORT_CAP32_MDI 21
6754 #define M_FW_PORT_CAP32_MDI 3
6755 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
6756 #define G_FW_PORT_CAP32_MDI(x) \
6757 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
6759 #define S_FW_PORT_CAP32_FEC 23
6760 #define M_FW_PORT_CAP32_FEC 0x1f
6761 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)
6762 #define G_FW_PORT_CAP32_FEC(x) \
6763 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
6765 /* macros to isolate various 32-bit Port Capabilities sub-fields */
6766 #define CAP32_SPEED(__cap32) \
6767 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)
6769 #define CAP32_FEC(__cap32) \
6770 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
6772 enum fw_port_action {
6773 FW_PORT_ACTION_L1_CFG = 0x0001,
6774 FW_PORT_ACTION_L2_CFG = 0x0002,
6775 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
6776 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
6777 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
6778 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
6779 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
6780 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
6781 FW_PORT_ACTION_L1_CFG32 = 0x0009,
6782 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
6783 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
6784 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
6785 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
6786 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
6787 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
6788 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
6789 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
6790 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
6791 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
6792 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
6793 FW_PORT_ACTION_PHY_RESET = 0x0040,
6794 FW_PORT_ACTION_PMA_RESET = 0x0041,
6795 FW_PORT_ACTION_PCS_RESET = 0x0042,
6796 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
6797 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
6798 FW_PORT_ACTION_AN_RESET = 0x0045,
6801 enum fw_port_l2cfg_ctlbf {
6802 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
6803 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
6804 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
6805 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
6806 FW_PORT_L2_CTLBF_IVLAN = 0x10,
6807 FW_PORT_L2_CTLBF_TXIPG = 0x20,
6808 FW_PORT_L2_CTLBF_MTU = 0x40
6811 enum fw_dcb_app_tlv_sf {
6812 FW_DCB_APP_SF_ETHERTYPE,
6813 FW_DCB_APP_SF_SOCKET_TCP,
6814 FW_DCB_APP_SF_SOCKET_UDP,
6815 FW_DCB_APP_SF_SOCKET_ALL,
6818 enum fw_port_dcb_versions {
6819 FW_PORT_DCB_VER_UNKNOWN,
6820 FW_PORT_DCB_VER_CEE1D0,
6821 FW_PORT_DCB_VER_CEE1D01,
6822 FW_PORT_DCB_VER_IEEE,
6823 FW_PORT_DCB_VER_AUTO=7
6826 enum fw_port_dcb_cfg {
6827 FW_PORT_DCB_CFG_PG = 0x01,
6828 FW_PORT_DCB_CFG_PFC = 0x02,
6829 FW_PORT_DCB_CFG_APPL = 0x04
6832 enum fw_port_dcb_cfg_rc {
6833 FW_PORT_DCB_CFG_SUCCESS = 0x0,
6834 FW_PORT_DCB_CFG_ERROR = 0x1
6837 enum fw_port_dcb_type {
6838 FW_PORT_DCB_TYPE_PGID = 0x00,
6839 FW_PORT_DCB_TYPE_PGRATE = 0x01,
6840 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
6841 FW_PORT_DCB_TYPE_PFC = 0x03,
6842 FW_PORT_DCB_TYPE_APP_ID = 0x04,
6843 FW_PORT_DCB_TYPE_CONTROL = 0x05,
6846 enum fw_port_dcb_feature_state {
6847 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
6848 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
6849 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
6850 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
6853 enum fw_port_diag_ops {
6854 FW_PORT_DIAGS_TEMP = 0x00,
6855 FW_PORT_DIAGS_TX_POWER = 0x01,
6856 FW_PORT_DIAGS_RX_POWER = 0x02,
6857 FW_PORT_DIAGS_TX_DIS = 0x03,
6860 struct fw_port_cmd {
6861 __be32 op_to_portid;
6862 __be32 action_to_len16;
6864 struct fw_port_l1cfg {
6868 struct fw_port_l2cfg {
6870 __u8 ovlan3_to_ivlan0;
6872 __be16 txipg_force_pinfo;
6883 struct fw_port_info {
6884 __be32 lstatus_to_modtype;
6895 struct fw_port_diags {
6901 struct fw_port_dcb_pgid {
6908 struct fw_port_dcb_pgrate {
6912 __u8 num_tcs_supported;
6916 struct fw_port_dcb_priorate {
6920 __u8 strict_priorate[8];
6922 struct fw_port_dcb_pfc {
6929 struct fw_port_app_priority {
6938 struct fw_port_dcb_control {
6941 __be16 dcb_version_to_app_state;
6946 struct fw_port_l1cfg32 {
6950 struct fw_port_info32 {
6951 __be32 lstatus32_to_cbllen32;
6952 __be32 auxlinfo32_mtu32;
6961 #define S_FW_PORT_CMD_READ 22
6962 #define M_FW_PORT_CMD_READ 0x1
6963 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)
6964 #define G_FW_PORT_CMD_READ(x) \
6965 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
6966 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U)
6968 #define S_FW_PORT_CMD_PORTID 0
6969 #define M_FW_PORT_CMD_PORTID 0xf
6970 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
6971 #define G_FW_PORT_CMD_PORTID(x) \
6972 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
6974 #define S_FW_PORT_CMD_ACTION 16
6975 #define M_FW_PORT_CMD_ACTION 0xffff
6976 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
6977 #define G_FW_PORT_CMD_ACTION(x) \
6978 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
6980 #define S_FW_PORT_CMD_OVLAN3 7
6981 #define M_FW_PORT_CMD_OVLAN3 0x1
6982 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3)
6983 #define G_FW_PORT_CMD_OVLAN3(x) \
6984 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
6985 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U)
6987 #define S_FW_PORT_CMD_OVLAN2 6
6988 #define M_FW_PORT_CMD_OVLAN2 0x1
6989 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2)
6990 #define G_FW_PORT_CMD_OVLAN2(x) \
6991 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
6992 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U)
6994 #define S_FW_PORT_CMD_OVLAN1 5
6995 #define M_FW_PORT_CMD_OVLAN1 0x1
6996 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1)
6997 #define G_FW_PORT_CMD_OVLAN1(x) \
6998 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
6999 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U)
7001 #define S_FW_PORT_CMD_OVLAN0 4
7002 #define M_FW_PORT_CMD_OVLAN0 0x1
7003 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0)
7004 #define G_FW_PORT_CMD_OVLAN0(x) \
7005 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7006 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U)
7008 #define S_FW_PORT_CMD_IVLAN0 3
7009 #define M_FW_PORT_CMD_IVLAN0 0x1
7010 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0)
7011 #define G_FW_PORT_CMD_IVLAN0(x) \
7012 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7013 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
7015 #define S_FW_PORT_CMD_TXIPG 3
7016 #define M_FW_PORT_CMD_TXIPG 0x1fff
7017 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
7018 #define G_FW_PORT_CMD_TXIPG(x) \
7019 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7021 #define S_FW_PORT_CMD_FORCE_PINFO 0
7022 #define M_FW_PORT_CMD_FORCE_PINFO 0x1
7023 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO)
7024 #define G_FW_PORT_CMD_FORCE_PINFO(x) \
7025 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7026 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U)
7028 #define S_FW_PORT_CMD_LSTATUS 31
7029 #define M_FW_PORT_CMD_LSTATUS 0x1
7030 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
7031 #define G_FW_PORT_CMD_LSTATUS(x) \
7032 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7033 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
7035 #define S_FW_PORT_CMD_LSPEED 24
7036 #define M_FW_PORT_CMD_LSPEED 0x3f
7037 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
7038 #define G_FW_PORT_CMD_LSPEED(x) \
7039 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7041 #define S_FW_PORT_CMD_TXPAUSE 23
7042 #define M_FW_PORT_CMD_TXPAUSE 0x1
7043 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
7044 #define G_FW_PORT_CMD_TXPAUSE(x) \
7045 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7046 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
7048 #define S_FW_PORT_CMD_RXPAUSE 22
7049 #define M_FW_PORT_CMD_RXPAUSE 0x1
7050 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
7051 #define G_FW_PORT_CMD_RXPAUSE(x) \
7052 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7053 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
7055 #define S_FW_PORT_CMD_MDIOCAP 21
7056 #define M_FW_PORT_CMD_MDIOCAP 0x1
7057 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
7058 #define G_FW_PORT_CMD_MDIOCAP(x) \
7059 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7060 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
7062 #define S_FW_PORT_CMD_MDIOADDR 16
7063 #define M_FW_PORT_CMD_MDIOADDR 0x1f
7064 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
7065 #define G_FW_PORT_CMD_MDIOADDR(x) \
7066 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7068 #define S_FW_PORT_CMD_LPTXPAUSE 15
7069 #define M_FW_PORT_CMD_LPTXPAUSE 0x1
7070 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE)
7071 #define G_FW_PORT_CMD_LPTXPAUSE(x) \
7072 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7073 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U)
7075 #define S_FW_PORT_CMD_LPRXPAUSE 14
7076 #define M_FW_PORT_CMD_LPRXPAUSE 0x1
7077 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE)
7078 #define G_FW_PORT_CMD_LPRXPAUSE(x) \
7079 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7080 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U)
7082 #define S_FW_PORT_CMD_PTYPE 8
7083 #define M_FW_PORT_CMD_PTYPE 0x1f
7084 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
7085 #define G_FW_PORT_CMD_PTYPE(x) \
7086 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7088 #define S_FW_PORT_CMD_LINKDNRC 5
7089 #define M_FW_PORT_CMD_LINKDNRC 0x7
7090 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
7091 #define G_FW_PORT_CMD_LINKDNRC(x) \
7092 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7094 #define S_FW_PORT_CMD_MODTYPE 0
7095 #define M_FW_PORT_CMD_MODTYPE 0x1f
7096 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
7097 #define G_FW_PORT_CMD_MODTYPE(x) \
7098 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7100 #define S_FW_PORT_AUXLINFO_KX4 2
7101 #define M_FW_PORT_AUXLINFO_KX4 0x1
7102 #define V_FW_PORT_AUXLINFO_KX4(x) \
7103 ((x) << S_FW_PORT_AUXLINFO_KX4)
7104 #define G_FW_PORT_AUXLINFO_KX4(x) \
7105 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
7106 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
7108 #define S_FW_PORT_AUXLINFO_KR 1
7109 #define M_FW_PORT_AUXLINFO_KR 0x1
7110 #define V_FW_PORT_AUXLINFO_KR(x) \
7111 ((x) << S_FW_PORT_AUXLINFO_KR)
7112 #define G_FW_PORT_AUXLINFO_KR(x) \
7113 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
7114 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
7116 #define S_FW_PORT_CMD_DCBXDIS 7
7117 #define M_FW_PORT_CMD_DCBXDIS 0x1
7118 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
7119 #define G_FW_PORT_CMD_DCBXDIS(x) \
7120 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7121 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
7123 #define S_FW_PORT_CMD_APPLY 7
7124 #define M_FW_PORT_CMD_APPLY 0x1
7125 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
7126 #define G_FW_PORT_CMD_APPLY(x) \
7127 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7128 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
7130 #define S_FW_PORT_CMD_ALL_SYNCD 7
7131 #define M_FW_PORT_CMD_ALL_SYNCD 0x1
7132 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
7133 #define G_FW_PORT_CMD_ALL_SYNCD(x) \
7134 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7135 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
7137 #define S_FW_PORT_CMD_DCB_VERSION 12
7138 #define M_FW_PORT_CMD_DCB_VERSION 0x7
7139 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION)
7140 #define G_FW_PORT_CMD_DCB_VERSION(x) \
7141 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7143 #define S_FW_PORT_CMD_PFC_STATE 8
7144 #define M_FW_PORT_CMD_PFC_STATE 0xf
7145 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
7146 #define G_FW_PORT_CMD_PFC_STATE(x) \
7147 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7149 #define S_FW_PORT_CMD_ETS_STATE 4
7150 #define M_FW_PORT_CMD_ETS_STATE 0xf
7151 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
7152 #define G_FW_PORT_CMD_ETS_STATE(x) \
7153 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7155 #define S_FW_PORT_CMD_APP_STATE 0
7156 #define M_FW_PORT_CMD_APP_STATE 0xf
7157 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
7158 #define G_FW_PORT_CMD_APP_STATE(x) \
7159 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7161 #define S_FW_PORT_CMD_LSTATUS32 31
7162 #define M_FW_PORT_CMD_LSTATUS32 0x1
7163 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
7164 #define G_FW_PORT_CMD_LSTATUS32(x) \
7165 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
7166 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
7168 #define S_FW_PORT_CMD_LINKDNRC32 28
7169 #define M_FW_PORT_CMD_LINKDNRC32 0x7
7170 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32)
7171 #define G_FW_PORT_CMD_LINKDNRC32(x) \
7172 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
7174 #define S_FW_PORT_CMD_DCBXDIS32 27
7175 #define M_FW_PORT_CMD_DCBXDIS32 0x1
7176 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32)
7177 #define G_FW_PORT_CMD_DCBXDIS32(x) \
7178 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
7179 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U)
7181 #define S_FW_PORT_CMD_MDIOCAP32 26
7182 #define M_FW_PORT_CMD_MDIOCAP32 0x1
7183 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
7184 #define G_FW_PORT_CMD_MDIOCAP32(x) \
7185 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
7186 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
7188 #define S_FW_PORT_CMD_MDIOADDR32 21
7189 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
7190 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32)
7191 #define G_FW_PORT_CMD_MDIOADDR32(x) \
7192 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
7194 #define S_FW_PORT_CMD_PORTTYPE32 13
7195 #define M_FW_PORT_CMD_PORTTYPE32 0xff
7196 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32)
7197 #define G_FW_PORT_CMD_PORTTYPE32(x) \
7198 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
7200 #define S_FW_PORT_CMD_MODTYPE32 8
7201 #define M_FW_PORT_CMD_MODTYPE32 0x1f
7202 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32)
7203 #define G_FW_PORT_CMD_MODTYPE32(x) \
7204 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
7206 #define S_FW_PORT_CMD_CBLLEN32 0
7207 #define M_FW_PORT_CMD_CBLLEN32 0xff
7208 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32)
7209 #define G_FW_PORT_CMD_CBLLEN32(x) \
7210 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
7212 #define S_FW_PORT_CMD_AUXLINFO32 24
7213 #define M_FW_PORT_CMD_AUXLINFO32 0xff
7214 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32)
7215 #define G_FW_PORT_CMD_AUXLINFO32(x) \
7216 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
7218 #define S_FW_PORT_AUXLINFO32_KX4 2
7219 #define M_FW_PORT_AUXLINFO32_KX4 0x1
7220 #define V_FW_PORT_AUXLINFO32_KX4(x) \
7221 ((x) << S_FW_PORT_AUXLINFO32_KX4)
7222 #define G_FW_PORT_AUXLINFO32_KX4(x) \
7223 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
7224 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U)
7226 #define S_FW_PORT_AUXLINFO32_KR 1
7227 #define M_FW_PORT_AUXLINFO32_KR 0x1
7228 #define V_FW_PORT_AUXLINFO32_KR(x) \
7229 ((x) << S_FW_PORT_AUXLINFO32_KR)
7230 #define G_FW_PORT_AUXLINFO32_KR(x) \
7231 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
7232 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U)
7234 #define S_FW_PORT_CMD_MTU32 0
7235 #define M_FW_PORT_CMD_MTU32 0xffff
7236 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32)
7237 #define G_FW_PORT_CMD_MTU32(x) \
7238 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
7241 * These are configured into the VPD and hence tools that generate
7242 * VPD may use this enumeration.
7243 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
7246 * Update the Common Code t4_hw.c:t4_get_port_type_description()
7247 * with any new Firmware Port Technology Types!
7250 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
7251 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
7252 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
7253 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */
7254 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */
7255 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
7256 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
7257 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
7258 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
7259 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
7260 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7261 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7262 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
7263 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
7264 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
7265 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7266 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
7267 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
7268 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
7269 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
7270 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
7271 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
7272 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7275 /* These are read from module's EEPROM and determined once the
7276 module is inserted. */
7277 enum fw_port_module_type {
7278 FW_PORT_MOD_TYPE_NA = 0x0,
7279 FW_PORT_MOD_TYPE_LR = 0x1,
7280 FW_PORT_MOD_TYPE_SR = 0x2,
7281 FW_PORT_MOD_TYPE_ER = 0x3,
7282 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
7283 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
7284 FW_PORT_MOD_TYPE_LRM = 0x6,
7285 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
7286 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
7287 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
7288 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
7291 /* used by FW and tools may use this to generate VPD */
7292 enum fw_port_mod_sub_type {
7293 FW_PORT_MOD_SUB_TYPE_NA,
7294 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7295 FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7296 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7297 FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7298 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7299 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7300 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7301 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7304 * The following will never been in the VPD. They are TWINAX cable
7305 * lengths decoded from SFP+ module i2c PROMs. These should almost
7306 * certainly go somewhere else ...
7308 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7309 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7310 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7311 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7314 /* link down reason codes (3b) */
7315 enum fw_port_link_dn_rc {
7316 FW_PORT_LINK_DN_RC_NONE,
7317 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
7318 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
7319 FW_PORT_LINK_DN_RESERVED3,
7320 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
7321 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
7322 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
7323 FW_PORT_LINK_DN_RESERVED7
7325 enum fw_port_stats_tx_index {
7326 FW_STAT_TX_PORT_BYTES_IX = 0,
7327 FW_STAT_TX_PORT_FRAMES_IX,
7328 FW_STAT_TX_PORT_BCAST_IX,
7329 FW_STAT_TX_PORT_MCAST_IX,
7330 FW_STAT_TX_PORT_UCAST_IX,
7331 FW_STAT_TX_PORT_ERROR_IX,
7332 FW_STAT_TX_PORT_64B_IX,
7333 FW_STAT_TX_PORT_65B_127B_IX,
7334 FW_STAT_TX_PORT_128B_255B_IX,
7335 FW_STAT_TX_PORT_256B_511B_IX,
7336 FW_STAT_TX_PORT_512B_1023B_IX,
7337 FW_STAT_TX_PORT_1024B_1518B_IX,
7338 FW_STAT_TX_PORT_1519B_MAX_IX,
7339 FW_STAT_TX_PORT_DROP_IX,
7340 FW_STAT_TX_PORT_PAUSE_IX,
7341 FW_STAT_TX_PORT_PPP0_IX,
7342 FW_STAT_TX_PORT_PPP1_IX,
7343 FW_STAT_TX_PORT_PPP2_IX,
7344 FW_STAT_TX_PORT_PPP3_IX,
7345 FW_STAT_TX_PORT_PPP4_IX,
7346 FW_STAT_TX_PORT_PPP5_IX,
7347 FW_STAT_TX_PORT_PPP6_IX,
7348 FW_STAT_TX_PORT_PPP7_IX,
7349 FW_NUM_PORT_TX_STATS
7352 enum fw_port_stat_rx_index {
7353 FW_STAT_RX_PORT_BYTES_IX = 0,
7354 FW_STAT_RX_PORT_FRAMES_IX,
7355 FW_STAT_RX_PORT_BCAST_IX,
7356 FW_STAT_RX_PORT_MCAST_IX,
7357 FW_STAT_RX_PORT_UCAST_IX,
7358 FW_STAT_RX_PORT_MTU_ERROR_IX,
7359 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7360 FW_STAT_RX_PORT_CRC_ERROR_IX,
7361 FW_STAT_RX_PORT_LEN_ERROR_IX,
7362 FW_STAT_RX_PORT_SYM_ERROR_IX,
7363 FW_STAT_RX_PORT_64B_IX,
7364 FW_STAT_RX_PORT_65B_127B_IX,
7365 FW_STAT_RX_PORT_128B_255B_IX,
7366 FW_STAT_RX_PORT_256B_511B_IX,
7367 FW_STAT_RX_PORT_512B_1023B_IX,
7368 FW_STAT_RX_PORT_1024B_1518B_IX,
7369 FW_STAT_RX_PORT_1519B_MAX_IX,
7370 FW_STAT_RX_PORT_PAUSE_IX,
7371 FW_STAT_RX_PORT_PPP0_IX,
7372 FW_STAT_RX_PORT_PPP1_IX,
7373 FW_STAT_RX_PORT_PPP2_IX,
7374 FW_STAT_RX_PORT_PPP3_IX,
7375 FW_STAT_RX_PORT_PPP4_IX,
7376 FW_STAT_RX_PORT_PPP5_IX,
7377 FW_STAT_RX_PORT_PPP6_IX,
7378 FW_STAT_RX_PORT_PPP7_IX,
7379 FW_STAT_RX_PORT_LESS_64B_IX,
7380 FW_STAT_RX_PORT_MAC_ERROR_IX,
7381 FW_NUM_PORT_RX_STATS
7384 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7385 FW_NUM_PORT_RX_STATS)
7388 struct fw_port_stats_cmd {
7389 __be32 op_to_portid;
7390 __be32 retval_len16;
7391 union fw_port_stats {
7392 struct fw_port_stats_ctl {
7404 struct fw_port_stats_all {
7413 __be64 tx_128b_255b;
7414 __be64 tx_256b_511b;
7415 __be64 tx_512b_1023b;
7416 __be64 tx_1024b_1518b;
7417 __be64 tx_1519b_max;
7433 __be64 rx_mtu_error;
7434 __be64 rx_mtu_crc_error;
7435 __be64 rx_crc_error;
7436 __be64 rx_len_error;
7437 __be64 rx_sym_error;
7440 __be64 rx_128b_255b;
7441 __be64 rx_256b_511b;
7442 __be64 rx_512b_1023b;
7443 __be64 rx_1024b_1518b;
7444 __be64 rx_1519b_max;
7461 #define S_FW_PORT_STATS_CMD_NSTATS 4
7462 #define M_FW_PORT_STATS_CMD_NSTATS 0x7
7463 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS)
7464 #define G_FW_PORT_STATS_CMD_NSTATS(x) \
7465 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
7467 #define S_FW_PORT_STATS_CMD_BG_BM 0
7468 #define M_FW_PORT_STATS_CMD_BG_BM 0x3
7469 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM)
7470 #define G_FW_PORT_STATS_CMD_BG_BM(x) \
7471 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
7473 #define S_FW_PORT_STATS_CMD_TX 7
7474 #define M_FW_PORT_STATS_CMD_TX 0x1
7475 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX)
7476 #define G_FW_PORT_STATS_CMD_TX(x) \
7477 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
7478 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U)
7480 #define S_FW_PORT_STATS_CMD_IX 0
7481 #define M_FW_PORT_STATS_CMD_IX 0x3f
7482 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX)
7483 #define G_FW_PORT_STATS_CMD_IX(x) \
7484 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
7486 /* port loopback stats */
7487 #define FW_NUM_LB_STATS 14
7488 enum fw_port_lb_stats_index {
7489 FW_STAT_LB_PORT_BYTES_IX,
7490 FW_STAT_LB_PORT_FRAMES_IX,
7491 FW_STAT_LB_PORT_BCAST_IX,
7492 FW_STAT_LB_PORT_MCAST_IX,
7493 FW_STAT_LB_PORT_UCAST_IX,
7494 FW_STAT_LB_PORT_ERROR_IX,
7495 FW_STAT_LB_PORT_64B_IX,
7496 FW_STAT_LB_PORT_65B_127B_IX,
7497 FW_STAT_LB_PORT_128B_255B_IX,
7498 FW_STAT_LB_PORT_256B_511B_IX,
7499 FW_STAT_LB_PORT_512B_1023B_IX,
7500 FW_STAT_LB_PORT_1024B_1518B_IX,
7501 FW_STAT_LB_PORT_1519B_MAX_IX,
7502 FW_STAT_LB_PORT_DROP_FRAMES_IX
7505 struct fw_port_lb_stats_cmd {
7506 __be32 op_to_lbport;
7507 __be32 retval_len16;
7508 union fw_port_lb_stats {
7509 struct fw_port_lb_stats_ctl {
7521 struct fw_port_lb_stats_all {
7530 __be64 tx_128b_255b;
7531 __be64 tx_256b_511b;
7532 __be64 tx_512b_1023b;
7533 __be64 tx_1024b_1518b;
7534 __be64 tx_1519b_max;
7541 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0
7542 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf
7543 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7544 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
7545 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7546 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
7548 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4
7549 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7
7550 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7551 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
7552 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7553 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
7555 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0
7556 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3
7557 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
7558 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
7559 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
7561 #define S_FW_PORT_LB_STATS_CMD_IX 0
7562 #define M_FW_PORT_LB_STATS_CMD_IX 0xf
7563 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX)
7564 #define G_FW_PORT_LB_STATS_CMD_IX(x) \
7565 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
7567 /* Trace related defines */
7568 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
7569 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560
7571 struct fw_port_trace_cmd {
7572 __be32 op_to_portid;
7573 __be32 retval_len16;
7574 __be16 traceen_to_pciech;
7579 #define S_FW_PORT_TRACE_CMD_PORTID 0
7580 #define M_FW_PORT_TRACE_CMD_PORTID 0xf
7581 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID)
7582 #define G_FW_PORT_TRACE_CMD_PORTID(x) \
7583 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
7585 #define S_FW_PORT_TRACE_CMD_TRACEEN 15
7586 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1
7587 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
7588 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
7589 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
7590 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U)
7592 #define S_FW_PORT_TRACE_CMD_FLTMODE 14
7593 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1
7594 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
7595 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
7596 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
7597 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U)
7599 #define S_FW_PORT_TRACE_CMD_DUPLEN 13
7600 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1
7601 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
7602 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
7603 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
7604 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U)
7606 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8
7607 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f
7608 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7609 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7610 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7611 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
7612 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7614 #define S_FW_PORT_TRACE_CMD_PCIECH 6
7615 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3
7616 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH)
7617 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \
7618 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
7620 struct fw_port_trace_mmap_cmd {
7621 __be32 op_to_portid;
7622 __be32 retval_len16;
7623 __be32 fid_to_skipoffset;
7624 __be32 minpktsize_capturemax;
7628 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
7629 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf
7630 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7631 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
7632 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7633 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
7634 M_FW_PORT_TRACE_MMAP_CMD_PORTID)
7636 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30
7637 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3
7638 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
7639 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
7640 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
7642 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29
7643 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1
7644 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7645 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7646 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7647 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
7648 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7649 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
7651 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
7652 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
7653 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7654 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7655 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7656 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
7657 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7658 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
7660 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
7661 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
7662 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7663 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7664 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7665 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
7666 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7668 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
7669 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
7670 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7671 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7672 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7673 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
7674 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7676 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
7677 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
7678 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7679 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7680 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7681 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
7682 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7684 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
7685 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
7686 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7687 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7688 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7689 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
7690 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7695 FW_PTP_SC_INIT_TIMER = 0x00,
7696 FW_PTP_SC_TX_TYPE = 0x01,
7699 FW_PTP_SC_RXTIME_STAMP = 0x08,
7700 FW_PTP_SC_RDRX_TYPE = 0x09,
7703 FW_PTP_SC_ADJ_FREQ = 0x10,
7704 FW_PTP_SC_ADJ_TIME = 0x11,
7705 FW_PTP_SC_ADJ_FTIME = 0x12,
7706 FW_PTP_SC_WALL_CLOCK = 0x13,
7707 FW_PTP_SC_GET_TIME = 0x14,
7708 FW_PTP_SC_SET_TIME = 0x15,
7712 __be32 op_to_portid;
7713 __be32 retval_len16;
7719 struct fw_ptp_init {
7737 #define S_FW_PTP_CMD_PORTID 0
7738 #define M_FW_PTP_CMD_PORTID 0xf
7739 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID)
7740 #define G_FW_PTP_CMD_PORTID(x) \
7741 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
7743 struct fw_rss_ind_tbl_cmd {
7745 __be32 retval_len16;
7753 __be32 iq12_to_iq14;
7754 __be32 iq15_to_iq17;
7755 __be32 iq18_to_iq20;
7756 __be32 iq21_to_iq23;
7757 __be32 iq24_to_iq26;
7758 __be32 iq27_to_iq29;
7763 #define S_FW_RSS_IND_TBL_CMD_VIID 0
7764 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
7765 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
7766 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
7767 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
7769 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
7770 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
7771 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
7772 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
7773 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
7775 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
7776 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
7777 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
7778 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
7779 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
7781 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
7782 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
7783 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
7784 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
7785 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
7787 #define S_FW_RSS_IND_TBL_CMD_IQ3 20
7788 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff
7789 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
7790 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
7791 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
7793 #define S_FW_RSS_IND_TBL_CMD_IQ4 10
7794 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff
7795 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
7796 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
7797 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
7799 #define S_FW_RSS_IND_TBL_CMD_IQ5 0
7800 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff
7801 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
7802 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
7803 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
7805 #define S_FW_RSS_IND_TBL_CMD_IQ6 20
7806 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff
7807 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
7808 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
7809 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
7811 #define S_FW_RSS_IND_TBL_CMD_IQ7 10
7812 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff
7813 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
7814 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
7815 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
7817 #define S_FW_RSS_IND_TBL_CMD_IQ8 0
7818 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff
7819 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
7820 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
7821 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
7823 #define S_FW_RSS_IND_TBL_CMD_IQ9 20
7824 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff
7825 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
7826 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
7827 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
7829 #define S_FW_RSS_IND_TBL_CMD_IQ10 10
7830 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff
7831 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
7832 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
7833 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
7835 #define S_FW_RSS_IND_TBL_CMD_IQ11 0
7836 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff
7837 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
7838 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
7839 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
7841 #define S_FW_RSS_IND_TBL_CMD_IQ12 20
7842 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff
7843 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
7844 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
7845 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
7847 #define S_FW_RSS_IND_TBL_CMD_IQ13 10
7848 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff
7849 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
7850 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
7851 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
7853 #define S_FW_RSS_IND_TBL_CMD_IQ14 0
7854 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff
7855 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
7856 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
7857 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
7859 #define S_FW_RSS_IND_TBL_CMD_IQ15 20
7860 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff
7861 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
7862 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
7863 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
7865 #define S_FW_RSS_IND_TBL_CMD_IQ16 10
7866 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff
7867 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
7868 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
7869 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
7871 #define S_FW_RSS_IND_TBL_CMD_IQ17 0
7872 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff
7873 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
7874 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
7875 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
7877 #define S_FW_RSS_IND_TBL_CMD_IQ18 20
7878 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff
7879 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
7880 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
7881 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
7883 #define S_FW_RSS_IND_TBL_CMD_IQ19 10
7884 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff
7885 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
7886 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
7887 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
7889 #define S_FW_RSS_IND_TBL_CMD_IQ20 0
7890 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff
7891 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
7892 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
7893 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
7895 #define S_FW_RSS_IND_TBL_CMD_IQ21 20
7896 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff
7897 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
7898 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
7899 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
7901 #define S_FW_RSS_IND_TBL_CMD_IQ22 10
7902 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff
7903 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
7904 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
7905 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
7907 #define S_FW_RSS_IND_TBL_CMD_IQ23 0
7908 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff
7909 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
7910 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
7911 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
7913 #define S_FW_RSS_IND_TBL_CMD_IQ24 20
7914 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff
7915 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
7916 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
7917 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
7919 #define S_FW_RSS_IND_TBL_CMD_IQ25 10
7920 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff
7921 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
7922 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
7923 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
7925 #define S_FW_RSS_IND_TBL_CMD_IQ26 0
7926 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff
7927 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
7928 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
7929 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
7931 #define S_FW_RSS_IND_TBL_CMD_IQ27 20
7932 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff
7933 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
7934 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
7935 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
7937 #define S_FW_RSS_IND_TBL_CMD_IQ28 10
7938 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff
7939 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
7940 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
7941 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
7943 #define S_FW_RSS_IND_TBL_CMD_IQ29 0
7944 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff
7945 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
7946 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
7947 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
7949 #define S_FW_RSS_IND_TBL_CMD_IQ30 20
7950 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff
7951 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
7952 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
7953 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
7955 #define S_FW_RSS_IND_TBL_CMD_IQ31 10
7956 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff
7957 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
7958 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
7959 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
7961 struct fw_rss_glb_config_cmd {
7963 __be32 retval_len16;
7964 union fw_rss_glb_config {
7965 struct fw_rss_glb_config_manual {
7971 struct fw_rss_glb_config_basicvirtual {
7972 __be32 mode_keymode;
7973 __be32 synmapen_to_hashtoeplitz;
7980 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
7981 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
7982 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
7983 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
7984 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
7986 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
7987 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
7988 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
7990 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
7991 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
7992 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
7993 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
7994 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
7995 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
7996 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
7998 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
7999 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
8000 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
8001 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
8003 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
8004 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
8005 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8006 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8007 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8008 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
8009 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8010 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
8012 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
8013 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
8014 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8015 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8016 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8017 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8018 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8019 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8020 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8022 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8023 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8024 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8025 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8026 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8027 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8028 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8029 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8030 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8032 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8033 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8034 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8035 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8036 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8037 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8038 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8039 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8040 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8042 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8043 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8044 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8045 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8046 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8047 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8048 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8049 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8050 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8052 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8053 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8054 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8055 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8056 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8057 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8058 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8059 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8061 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8062 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8063 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8064 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8065 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8066 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8067 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8068 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8070 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8071 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8072 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8073 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8074 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8075 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8076 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8077 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8078 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8080 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8081 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8082 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8083 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8084 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8085 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8086 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8087 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8088 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8090 struct fw_rss_vi_config_cmd {
8092 __be32 retval_len16;
8093 union fw_rss_vi_config {
8094 struct fw_rss_vi_config_manual {
8099 struct fw_rss_vi_config_basicvirtual {
8101 __be32 defaultq_to_udpen;
8102 __be32 secretkeyidx_pkd;
8103 __be32 secretkeyxor;
8109 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
8110 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
8111 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8112 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
8113 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8115 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
8116 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
8117 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8118 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8119 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8120 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8121 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8123 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8124 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8125 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8126 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8127 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8128 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8129 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8130 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8131 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8133 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8134 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8135 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8136 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8137 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8138 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8139 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8140 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8141 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8143 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8144 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8145 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8146 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8147 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8148 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8149 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8150 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8151 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8153 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8154 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8155 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8156 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8157 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8158 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8159 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8160 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8161 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8163 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
8164 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
8165 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8166 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
8167 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8168 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8170 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8171 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8172 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8173 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8174 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8175 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8176 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8179 FW_SCHED_SC_CONFIG = 0,
8180 FW_SCHED_SC_PARAMS = 1,
8183 enum fw_sched_type {
8184 FW_SCHED_TYPE_PKTSCHED = 0,
8185 FW_SCHED_TYPE_STREAMSCHED = 1,
8188 enum fw_sched_params_level {
8189 FW_SCHED_PARAMS_LEVEL_CL_RL = 0,
8190 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1,
8191 FW_SCHED_PARAMS_LEVEL_CH_RL = 2,
8194 enum fw_sched_params_mode {
8195 FW_SCHED_PARAMS_MODE_CLASS = 0,
8196 FW_SCHED_PARAMS_MODE_FLOW = 1,
8199 enum fw_sched_params_unit {
8200 FW_SCHED_PARAMS_UNIT_BITRATE = 0,
8201 FW_SCHED_PARAMS_UNIT_PKTRATE = 1,
8204 enum fw_sched_params_rate {
8205 FW_SCHED_PARAMS_RATE_REL = 0,
8206 FW_SCHED_PARAMS_RATE_ABS = 1,
8209 struct fw_sched_cmd {
8211 __be32 retval_len16;
8213 struct fw_sched_config {
8221 struct fw_sched_params {
8241 * length of the formatting string
8243 #define FW_DEVLOG_FMT_LEN 192
8246 * maximum number of the formatting string parameters
8248 #define FW_DEVLOG_FMT_PARAMS_NUM 8
8253 enum fw_devlog_level {
8254 FW_DEVLOG_LEVEL_EMERG = 0x0,
8255 FW_DEVLOG_LEVEL_CRIT = 0x1,
8256 FW_DEVLOG_LEVEL_ERR = 0x2,
8257 FW_DEVLOG_LEVEL_NOTICE = 0x3,
8258 FW_DEVLOG_LEVEL_INFO = 0x4,
8259 FW_DEVLOG_LEVEL_DEBUG = 0x5,
8260 FW_DEVLOG_LEVEL_MAX = 0x5,
8264 * facilities that may send a log message
8266 enum fw_devlog_facility {
8267 FW_DEVLOG_FACILITY_CORE = 0x00,
8268 FW_DEVLOG_FACILITY_CF = 0x01,
8269 FW_DEVLOG_FACILITY_SCHED = 0x02,
8270 FW_DEVLOG_FACILITY_TIMER = 0x04,
8271 FW_DEVLOG_FACILITY_RES = 0x06,
8272 FW_DEVLOG_FACILITY_HW = 0x08,
8273 FW_DEVLOG_FACILITY_FLR = 0x10,
8274 FW_DEVLOG_FACILITY_DMAQ = 0x12,
8275 FW_DEVLOG_FACILITY_PHY = 0x14,
8276 FW_DEVLOG_FACILITY_MAC = 0x16,
8277 FW_DEVLOG_FACILITY_PORT = 0x18,
8278 FW_DEVLOG_FACILITY_VI = 0x1A,
8279 FW_DEVLOG_FACILITY_FILTER = 0x1C,
8280 FW_DEVLOG_FACILITY_ACL = 0x1E,
8281 FW_DEVLOG_FACILITY_TM = 0x20,
8282 FW_DEVLOG_FACILITY_QFC = 0x22,
8283 FW_DEVLOG_FACILITY_DCB = 0x24,
8284 FW_DEVLOG_FACILITY_ETH = 0x26,
8285 FW_DEVLOG_FACILITY_OFLD = 0x28,
8286 FW_DEVLOG_FACILITY_RI = 0x2A,
8287 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
8288 FW_DEVLOG_FACILITY_FCOE = 0x2E,
8289 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
8290 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
8291 FW_DEVLOG_FACILITY_CHNET = 0x34,
8292 FW_DEVLOG_FACILITY_COiSCSI = 0x36,
8293 FW_DEVLOG_FACILITY_MAX = 0x38,
8297 * log message format
8299 struct fw_devlog_e {
8305 __u8 fmt[FW_DEVLOG_FMT_LEN];
8306 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
8307 __be32 reserved3[4];
8310 struct fw_devlog_cmd {
8312 __be32 retval_len16;
8315 __be32 memtype_devlog_memaddr16_devlog;
8316 __be32 memsize_devlog;
8320 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28
8321 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf
8322 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8323 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8324 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8325 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8327 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8328 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8329 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8330 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8331 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8332 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8333 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8335 enum fw_watchdog_actions {
8336 FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8337 FW_WATCHDOG_ACTION_FLR = 1,
8338 FW_WATCHDOG_ACTION_BYPASS = 2,
8339 FW_WATCHDOG_ACTION_TMPCHK = 3,
8340 FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8342 FW_WATCHDOG_ACTION_MAX = 5,
8345 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60
8347 struct fw_watchdog_cmd {
8349 __be32 retval_len16;
8354 #define S_FW_WATCHDOG_CMD_PFN 8
8355 #define M_FW_WATCHDOG_CMD_PFN 0x7
8356 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN)
8357 #define G_FW_WATCHDOG_CMD_PFN(x) \
8358 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8360 #define S_FW_WATCHDOG_CMD_VFN 0
8361 #define M_FW_WATCHDOG_CMD_VFN 0xff
8362 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN)
8363 #define G_FW_WATCHDOG_CMD_VFN(x) \
8364 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8366 struct fw_clip_cmd {
8368 __be32 alloc_to_len16;
8374 #define S_FW_CLIP_CMD_ALLOC 31
8375 #define M_FW_CLIP_CMD_ALLOC 0x1
8376 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
8377 #define G_FW_CLIP_CMD_ALLOC(x) \
8378 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8379 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
8381 #define S_FW_CLIP_CMD_FREE 30
8382 #define M_FW_CLIP_CMD_FREE 0x1
8383 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
8384 #define G_FW_CLIP_CMD_FREE(x) \
8385 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8386 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
8388 /******************************************************************************
8389 * F O i S C S I C O M M A N D s
8390 **************************************/
8392 #define FW_CHNET_IFACE_ADDR_MAX 3
8394 enum fw_chnet_iface_cmd_subop {
8395 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8397 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8398 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8400 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8401 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8403 FW_CHNET_IFACE_CMD_SUBOP_MAX,
8406 struct fw_chnet_iface_cmd {
8407 __be32 op_to_portid;
8408 __be32 retval_len16;
8411 __be32 ifid_ifstate;
8419 #define S_FW_CHNET_IFACE_CMD_PORTID 0
8420 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf
8421 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8422 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \
8423 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8425 #define S_FW_CHNET_IFACE_CMD_IFID 8
8426 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
8427 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
8428 #define G_FW_CHNET_IFACE_CMD_IFID(x) \
8429 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
8431 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0
8432 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff
8433 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
8434 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
8435 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
8437 struct fw_fcoe_res_info_cmd {
8439 __be32 retval_len16;
8454 struct fw_fcoe_link_cmd {
8455 __be32 op_to_portid;
8456 __be32 retval_len16;
8457 __be32 sub_opcode_fcfi;
8467 __u8 vnport_wwnn[8];
8468 __u8 vnport_wwpn[8];
8471 #define S_FW_FCOE_LINK_CMD_PORTID 0
8472 #define M_FW_FCOE_LINK_CMD_PORTID 0xf
8473 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID)
8474 #define G_FW_FCOE_LINK_CMD_PORTID(x) \
8475 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
8477 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24
8478 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff
8479 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8480 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
8481 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8482 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
8484 #define S_FW_FCOE_LINK_CMD_FCFI 0
8485 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff
8486 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI)
8487 #define G_FW_FCOE_LINK_CMD_FCFI(x) \
8488 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
8490 #define S_FW_FCOE_LINK_CMD_VNPI 0
8491 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff
8492 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI)
8493 #define G_FW_FCOE_LINK_CMD_VNPI(x) \
8494 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
8496 struct fw_fcoe_vnp_cmd {
8498 __be32 alloc_to_len16;
8499 __be32 gen_wwn_to_vnpi;
8503 __u8 vnport_wwnn[8];
8504 __u8 vnport_wwpn[8];
8505 __u8 cmn_srv_parms[16];
8506 __u8 clsp_word_0_1[8];
8509 #define S_FW_FCOE_VNP_CMD_FCFI 0
8510 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff
8511 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI)
8512 #define G_FW_FCOE_VNP_CMD_FCFI(x) \
8513 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
8515 #define S_FW_FCOE_VNP_CMD_ALLOC 31
8516 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1
8517 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC)
8518 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \
8519 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
8520 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U)
8522 #define S_FW_FCOE_VNP_CMD_FREE 30
8523 #define M_FW_FCOE_VNP_CMD_FREE 0x1
8524 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE)
8525 #define G_FW_FCOE_VNP_CMD_FREE(x) \
8526 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
8527 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U)
8529 #define S_FW_FCOE_VNP_CMD_MODIFY 29
8530 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1
8531 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY)
8532 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \
8533 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
8534 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U)
8536 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22
8537 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1
8538 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
8539 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
8540 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
8541 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
8543 #define S_FW_FCOE_VNP_CMD_PERSIST 21
8544 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1
8545 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST)
8546 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \
8547 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
8548 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U)
8550 #define S_FW_FCOE_VNP_CMD_VFID_EN 20
8551 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1
8552 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
8553 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
8554 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
8555 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U)
8557 #define S_FW_FCOE_VNP_CMD_VNPI 0
8558 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff
8559 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI)
8560 #define G_FW_FCOE_VNP_CMD_VNPI(x) \
8561 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
8563 struct fw_fcoe_sparams_cmd {
8564 __be32 op_to_portid;
8565 __be32 retval_len16;
8570 __u8 cmn_srv_parms[16];
8571 __u8 cls_srv_parms[16];
8574 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0
8575 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf
8576 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
8577 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
8578 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
8580 struct fw_fcoe_stats_cmd {
8581 __be32 op_to_flowid;
8582 __be32 free_to_len16;
8583 union fw_fcoe_stats {
8584 struct fw_fcoe_stats_ctl {
8596 struct fw_fcoe_port_stats {
8597 __be64 tx_bcast_bytes;
8598 __be64 tx_bcast_frames;
8599 __be64 tx_mcast_bytes;
8600 __be64 tx_mcast_frames;
8601 __be64 tx_ucast_bytes;
8602 __be64 tx_ucast_frames;
8603 __be64 tx_drop_frames;
8604 __be64 tx_offload_bytes;
8605 __be64 tx_offload_frames;
8606 __be64 rx_bcast_bytes;
8607 __be64 rx_bcast_frames;
8608 __be64 rx_mcast_bytes;
8609 __be64 rx_mcast_frames;
8610 __be64 rx_ucast_bytes;
8611 __be64 rx_ucast_frames;
8612 __be64 rx_err_frames;
8614 struct fw_fcoe_fcf_stats {
8615 __be32 fip_tx_bytes;
8618 __be64 mcast_adv_rcvd;
8619 __be16 ucast_adv_rcvd;
8637 struct fw_fcoe_pcb_stats {
8643 __be32 unsol_els_rcvd;
8644 __be64 unsol_cmd_rcvd;
8645 __be16 implicit_logo;
8646 __be16 flogi_inv_sparm;
8647 __be16 fdisc_inv_sparm;
8651 __be16 mac_flt_fail;
8654 struct fw_fcoe_scb_stats {
8659 __be32 host_abrt_req;
8660 __be32 adap_auto_abrt;
8661 __be32 adap_abrt_rsp;
8662 __be32 host_ios_req;
8663 __be16 ssn_offl_ios;
8664 __be16 ssn_not_rdy_ios;
8665 __u8 rx_data_ddp_err;
8666 __u8 ddp_flt_set_err;
8667 __be16 rx_data_fr_err;
8668 __u8 bad_st_abrt_req;
8669 __u8 no_io_abrt_req;
8673 __u8 no_ppod_res_tmo;
8677 __be32 host_cls_req;
8678 __be64 unsol_cmd_rcvd;
8679 __be32 plogi_req_rcvd;
8680 __be32 prli_req_rcvd;
8681 __be16 logo_req_rcvd;
8682 __be16 prlo_req_rcvd;
8683 __be16 plogi_rjt_rcvd;
8684 __be16 prli_rjt_rcvd;
8685 __be32 adisc_req_rcvd;
8687 __be32 rrq_req_rcvd;
8688 __be32 unsol_els_rcvd;
8689 __u8 adisc_rjt_rcvd;
8692 __u8 inval_bls_rcvd;
8698 #define S_FW_FCOE_STATS_CMD_FLOWID 0
8699 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff
8700 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID)
8701 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \
8702 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
8704 #define S_FW_FCOE_STATS_CMD_FREE 30
8705 #define M_FW_FCOE_STATS_CMD_FREE 0x1
8706 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE)
8707 #define G_FW_FCOE_STATS_CMD_FREE(x) \
8708 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
8709 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U)
8711 #define S_FW_FCOE_STATS_CMD_NSTATS 4
8712 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7
8713 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS)
8714 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \
8715 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
8717 #define S_FW_FCOE_STATS_CMD_PORT 0
8718 #define M_FW_FCOE_STATS_CMD_PORT 0x3
8719 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT)
8720 #define G_FW_FCOE_STATS_CMD_PORT(x) \
8721 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
8723 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7
8724 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1
8725 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8726 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
8727 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8728 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
8729 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
8731 #define S_FW_FCOE_STATS_CMD_IX 0
8732 #define M_FW_FCOE_STATS_CMD_IX 0x3f
8733 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX)
8734 #define G_FW_FCOE_STATS_CMD_IX(x) \
8735 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
8737 struct fw_fcoe_fcf_cmd {
8739 __be32 retval_len16;
8740 __be16 priority_pkd;
8745 __be16 max_fcoe_size;
8751 __u8 fpma_to_portid;
8756 #define S_FW_FCOE_FCF_CMD_FCFI 0
8757 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff
8758 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI)
8759 #define G_FW_FCOE_FCF_CMD_FCFI(x) \
8760 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
8762 #define S_FW_FCOE_FCF_CMD_PRIORITY 0
8763 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff
8764 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
8765 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
8766 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
8768 #define S_FW_FCOE_FCF_CMD_FPMA 6
8769 #define M_FW_FCOE_FCF_CMD_FPMA 0x1
8770 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA)
8771 #define G_FW_FCOE_FCF_CMD_FPMA(x) \
8772 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
8773 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U)
8775 #define S_FW_FCOE_FCF_CMD_SPMA 5
8776 #define M_FW_FCOE_FCF_CMD_SPMA 0x1
8777 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA)
8778 #define G_FW_FCOE_FCF_CMD_SPMA(x) \
8779 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
8780 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U)
8782 #define S_FW_FCOE_FCF_CMD_LOGIN 4
8783 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1
8784 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN)
8785 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \
8786 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
8787 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U)
8789 #define S_FW_FCOE_FCF_CMD_PORTID 0
8790 #define M_FW_FCOE_FCF_CMD_PORTID 0xf
8791 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID)
8792 #define G_FW_FCOE_FCF_CMD_PORTID(x) \
8793 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
8795 /******************************************************************************
8796 * E R R O R a n d D E B U G C O M M A N D s
8797 ******************************************************/
8799 enum fw_error_type {
8800 FW_ERROR_TYPE_EXCEPTION = 0x0,
8801 FW_ERROR_TYPE_HWMODULE = 0x1,
8802 FW_ERROR_TYPE_WR = 0x2,
8803 FW_ERROR_TYPE_ACL = 0x3,
8806 enum fw_dcb_ieee_locations {
8809 FW_IEEE_LOC_OPERATIONAL,
8812 struct fw_dcb_ieee_cmd {
8813 __be32 op_to_location;
8814 __be32 changed_to_len16;
8815 union fw_dcbx_stats {
8816 struct fw_dcbx_pfc_stats_ieee {
8818 __be32 pfc_willing_to_pfc_en;
8820 struct fw_dcbx_ets_stats_ieee {
8821 __be32 cbs_to_ets_max_tc;
8826 struct fw_dcbx_app_stats_ieee {
8827 __be32 num_apps_pkd;
8831 struct fw_dcbx_control {
8832 __be32 multi_peer_invalidated;
8838 #define S_FW_DCB_IEEE_CMD_PORT 8
8839 #define M_FW_DCB_IEEE_CMD_PORT 0x7
8840 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT)
8841 #define G_FW_DCB_IEEE_CMD_PORT(x) \
8842 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
8844 #define S_FW_DCB_IEEE_CMD_FEATURE 2
8845 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7
8846 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE)
8847 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \
8848 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
8850 #define S_FW_DCB_IEEE_CMD_LOCATION 0
8851 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3
8852 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION)
8853 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \
8854 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
8856 #define S_FW_DCB_IEEE_CMD_CHANGED 20
8857 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1
8858 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED)
8859 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \
8860 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
8861 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U)
8863 #define S_FW_DCB_IEEE_CMD_RECEIVED 19
8864 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1
8865 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
8866 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \
8867 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
8868 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U)
8870 #define S_FW_DCB_IEEE_CMD_APPLY 18
8871 #define M_FW_DCB_IEEE_CMD_APPLY 0x1
8872 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY)
8873 #define G_FW_DCB_IEEE_CMD_APPLY(x) \
8874 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
8875 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)
8877 #define S_FW_DCB_IEEE_CMD_DISABLED 17
8878 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1
8879 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED)
8880 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \
8881 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
8882 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U)
8884 #define S_FW_DCB_IEEE_CMD_MORE 16
8885 #define M_FW_DCB_IEEE_CMD_MORE 0x1
8886 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE)
8887 #define G_FW_DCB_IEEE_CMD_MORE(x) \
8888 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
8889 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U)
8891 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0
8892 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1
8893 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
8894 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \
8895 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
8896 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
8898 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16
8899 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1
8900 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
8901 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
8902 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
8903 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
8904 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
8906 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8
8907 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff
8908 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8909 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \
8910 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8912 #define S_FW_DCB_IEEE_CMD_PFC_EN 0
8913 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff
8914 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
8915 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \
8916 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
8918 #define S_FW_DCB_IEEE_CMD_CBS 16
8919 #define M_FW_DCB_IEEE_CMD_CBS 0x1
8920 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS)
8921 #define G_FW_DCB_IEEE_CMD_CBS(x) \
8922 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
8923 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U)
8925 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8
8926 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1
8927 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
8928 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
8929 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
8930 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
8931 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
8933 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0
8934 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff
8935 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
8936 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \
8937 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
8939 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0
8940 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7
8941 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
8942 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \
8943 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
8945 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31
8946 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1
8947 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
8948 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \
8949 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
8950 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
8952 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30
8953 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1
8954 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \
8955 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
8956 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \
8957 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
8958 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
8961 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16
8962 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff
8963 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
8964 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \
8965 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
8967 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3
8968 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7
8969 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
8970 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \
8971 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
8973 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0
8974 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7
8975 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
8976 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \
8977 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
8980 struct fw_error_cmd {
8984 struct fw_error_exception {
8987 struct fw_error_hwmodule {
8991 struct fw_error_wr {
8997 struct fw_error_acl {
9008 #define S_FW_ERROR_CMD_FATAL 4
9009 #define M_FW_ERROR_CMD_FATAL 0x1
9010 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL)
9011 #define G_FW_ERROR_CMD_FATAL(x) \
9012 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
9013 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U)
9015 #define S_FW_ERROR_CMD_TYPE 0
9016 #define M_FW_ERROR_CMD_TYPE 0xf
9017 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE)
9018 #define G_FW_ERROR_CMD_TYPE(x) \
9019 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9021 #define S_FW_ERROR_CMD_PFN 8
9022 #define M_FW_ERROR_CMD_PFN 0x7
9023 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9024 #define G_FW_ERROR_CMD_PFN(x) \
9025 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9027 #define S_FW_ERROR_CMD_VFN 0
9028 #define M_FW_ERROR_CMD_VFN 0xff
9029 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9030 #define G_FW_ERROR_CMD_VFN(x) \
9031 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9033 #define S_FW_ERROR_CMD_PFN 8
9034 #define M_FW_ERROR_CMD_PFN 0x7
9035 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9036 #define G_FW_ERROR_CMD_PFN(x) \
9037 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9039 #define S_FW_ERROR_CMD_VFN 0
9040 #define M_FW_ERROR_CMD_VFN 0xff
9041 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9042 #define G_FW_ERROR_CMD_VFN(x) \
9043 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9045 #define S_FW_ERROR_CMD_MV 15
9046 #define M_FW_ERROR_CMD_MV 0x1
9047 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV)
9048 #define G_FW_ERROR_CMD_MV(x) \
9049 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9050 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U)
9052 struct fw_debug_cmd {
9056 struct fw_debug_assert {
9061 __u8 filename_0_7[8];
9062 __u8 filename_8_15[8];
9065 struct fw_debug_prt {
9068 __be32 dprtstrparam0;
9069 __be32 dprtstrparam1;
9070 __be32 dprtstrparam2;
9071 __be32 dprtstrparam3;
9076 #define S_FW_DEBUG_CMD_TYPE 0
9077 #define M_FW_DEBUG_CMD_TYPE 0xff
9078 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
9079 #define G_FW_DEBUG_CMD_TYPE(x) \
9080 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9082 enum fw_diag_cmd_type {
9083 FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9086 enum fw_diag_cmd_ofldiag_op {
9087 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9088 FW_DIAG_CMD_OFLDIAG_TEST_START,
9089 FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9090 FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9093 enum fw_diag_cmd_ofldiag_status {
9094 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9095 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9096 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9097 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9100 struct fw_diag_cmd {
9103 union fw_diag_test {
9104 struct fw_diag_test_ofldiag {
9113 #define S_FW_DIAG_CMD_TYPE 0
9114 #define M_FW_DIAG_CMD_TYPE 0xff
9115 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
9116 #define G_FW_DIAG_CMD_TYPE(x) \
9117 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9121 __be32 retval_len16;
9122 __be32 mode_to_pcie_params;
9124 __be32 addr_size_pkd;
9126 __be64 phy_address[5];
9129 #define S_FW_HMA_CMD_MODE 31
9130 #define M_FW_HMA_CMD_MODE 0x1
9131 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE)
9132 #define G_FW_HMA_CMD_MODE(x) \
9133 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
9134 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U)
9136 #define S_FW_HMA_CMD_SOC 30
9137 #define M_FW_HMA_CMD_SOC 0x1
9138 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC)
9139 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
9140 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U)
9142 #define S_FW_HMA_CMD_EOC 29
9143 #define M_FW_HMA_CMD_EOC 0x1
9144 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC)
9145 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
9146 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U)
9148 #define S_FW_HMA_CMD_PCIE_PARAMS 0
9149 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff
9150 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS)
9151 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \
9152 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
9154 #define S_FW_HMA_CMD_NADDR 12
9155 #define M_FW_HMA_CMD_NADDR 0x3f
9156 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR)
9157 #define G_FW_HMA_CMD_NADDR(x) \
9158 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
9160 #define S_FW_HMA_CMD_SIZE 0
9161 #define M_FW_HMA_CMD_SIZE 0xfff
9162 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE)
9163 #define G_FW_HMA_CMD_SIZE(x) \
9164 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
9166 #define S_FW_HMA_CMD_ADDR_SIZE 11
9167 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff
9168 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE)
9169 #define G_FW_HMA_CMD_ADDR_SIZE(x) \
9170 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
9172 /******************************************************************************
9173 * P C I E F W R E G I S T E R
9174 **************************************/
9177 PCIE_FW_EVAL_CRASH = 0,
9178 PCIE_FW_EVAL_PREP = 1,
9179 PCIE_FW_EVAL_CONF = 2,
9180 PCIE_FW_EVAL_INIT = 3,
9181 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4,
9182 PCIE_FW_EVAL_OVERHEAT = 5,
9183 PCIE_FW_EVAL_DEVICESHUTDOWN = 6,
9187 * Register definitions for the PCIE_FW register which the firmware uses
9188 * to retain status across RESETs. This register should be considered
9189 * as a READ-ONLY register for Host Software and only to be used to
9190 * track firmware initialization/error state, etc.
9192 #define S_PCIE_FW_ERR 31
9193 #define M_PCIE_FW_ERR 0x1
9194 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
9195 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9196 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
9198 #define S_PCIE_FW_INIT 30
9199 #define M_PCIE_FW_INIT 0x1
9200 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
9201 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9202 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
9204 #define S_PCIE_FW_HALT 29
9205 #define M_PCIE_FW_HALT 0x1
9206 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
9207 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9208 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
9210 #define S_PCIE_FW_EVAL 24
9211 #define M_PCIE_FW_EVAL 0x7
9212 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
9213 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9215 #define S_PCIE_FW_STAGE 21
9216 #define M_PCIE_FW_STAGE 0x7
9217 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE)
9218 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9220 #define S_PCIE_FW_ASYNCNOT_VLD 20
9221 #define M_PCIE_FW_ASYNCNOT_VLD 0x1
9222 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
9223 ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9224 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
9225 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9226 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U)
9228 #define S_PCIE_FW_ASYNCNOTINT 19
9229 #define M_PCIE_FW_ASYNCNOTINT 0x1
9230 #define V_PCIE_FW_ASYNCNOTINT(x) \
9231 ((x) << S_PCIE_FW_ASYNCNOTINT)
9232 #define G_PCIE_FW_ASYNCNOTINT(x) \
9233 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9234 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U)
9236 #define S_PCIE_FW_ASYNCNOT 16
9237 #define M_PCIE_FW_ASYNCNOT 0x7
9238 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT)
9239 #define G_PCIE_FW_ASYNCNOT(x) \
9240 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9242 #define S_PCIE_FW_MASTER_VLD 15
9243 #define M_PCIE_FW_MASTER_VLD 0x1
9244 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
9245 #define G_PCIE_FW_MASTER_VLD(x) \
9246 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9247 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
9249 #define S_PCIE_FW_MASTER 12
9250 #define M_PCIE_FW_MASTER 0x7
9251 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
9252 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9254 #define S_PCIE_FW_RESET_VLD 11
9255 #define M_PCIE_FW_RESET_VLD 0x1
9256 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD)
9257 #define G_PCIE_FW_RESET_VLD(x) \
9258 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9259 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U)
9261 #define S_PCIE_FW_RESET 8
9262 #define M_PCIE_FW_RESET 0x7
9263 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET)
9264 #define G_PCIE_FW_RESET(x) \
9265 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9267 #define S_PCIE_FW_REGISTERED 0
9268 #define M_PCIE_FW_REGISTERED 0xff
9269 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
9270 #define G_PCIE_FW_REGISTERED(x) \
9271 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9274 /******************************************************************************
9275 * P C I E F W P F 0 R E G I S T E R
9276 **********************************************/
9279 * this register is available as 32-bit of persistent storage (across
9280 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9281 * will not write it)
9285 /******************************************************************************
9286 * P C I E F W P F 7 R E G I S T E R
9287 **********************************************/
9290 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9291 * access the "devlog" which needing to contact firmware. The encoding is
9292 * mostly the same as that returned by the DEVLOG command except for the size
9293 * which is encoded as the number of entries in multiples-1 of 128 here rather
9294 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
9295 * and 15 means 2048. This of course in turn constrains the allowed values
9296 * for the devlog size ...
9298 #define PCIE_FW_PF_DEVLOG 7
9300 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28
9301 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf
9302 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9303 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9304 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9305 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9306 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9308 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4
9309 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff
9310 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9311 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9312 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9314 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0
9315 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf
9316 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9317 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9318 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9321 /******************************************************************************
9322 * B I N A R Y H E A D E R F O R M A T
9323 **********************************************/
9326 * firmware binary header format
9330 __u8 chip; /* terminator chip family */
9331 __be16 len512; /* bin length in units of 512-bytes */
9332 __be32 fw_ver; /* firmware version */
9333 __be32 tp_microcode_ver; /* tcp processor microcode version */
9338 __u8 intfver_iscsipdu;
9340 __u8 intfver_fcoepdu;
9344 __be32 magic; /* runtime or bootstrap fw */
9346 __be32 reserved6[23];
9355 #define S_FW_HDR_FW_VER_MAJOR 24
9356 #define M_FW_HDR_FW_VER_MAJOR 0xff
9357 #define V_FW_HDR_FW_VER_MAJOR(x) \
9358 ((x) << S_FW_HDR_FW_VER_MAJOR)
9359 #define G_FW_HDR_FW_VER_MAJOR(x) \
9360 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9362 #define S_FW_HDR_FW_VER_MINOR 16
9363 #define M_FW_HDR_FW_VER_MINOR 0xff
9364 #define V_FW_HDR_FW_VER_MINOR(x) \
9365 ((x) << S_FW_HDR_FW_VER_MINOR)
9366 #define G_FW_HDR_FW_VER_MINOR(x) \
9367 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9369 #define S_FW_HDR_FW_VER_MICRO 8
9370 #define M_FW_HDR_FW_VER_MICRO 0xff
9371 #define V_FW_HDR_FW_VER_MICRO(x) \
9372 ((x) << S_FW_HDR_FW_VER_MICRO)
9373 #define G_FW_HDR_FW_VER_MICRO(x) \
9374 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9376 #define S_FW_HDR_FW_VER_BUILD 0
9377 #define M_FW_HDR_FW_VER_BUILD 0xff
9378 #define V_FW_HDR_FW_VER_BUILD(x) \
9379 ((x) << S_FW_HDR_FW_VER_BUILD)
9380 #define G_FW_HDR_FW_VER_BUILD(x) \
9381 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
9384 T4FW_VERSION_MAJOR = 0x01,
9385 T4FW_VERSION_MINOR = 0x10,
9386 T4FW_VERSION_MICRO = 0x3b,
9387 T4FW_VERSION_BUILD = 0x00,
9389 T5FW_VERSION_MAJOR = 0x01,
9390 T5FW_VERSION_MINOR = 0x10,
9391 T5FW_VERSION_MICRO = 0x3b,
9392 T5FW_VERSION_BUILD = 0x00,
9394 T6FW_VERSION_MAJOR = 0x01,
9395 T6FW_VERSION_MINOR = 0x10,
9396 T6FW_VERSION_MICRO = 0x3b,
9397 T6FW_VERSION_BUILD = 0x00,
9403 T4FW_HDR_INTFVER_NIC = 0x00,
9404 T4FW_HDR_INTFVER_VNIC = 0x00,
9405 T4FW_HDR_INTFVER_OFLD = 0x00,
9406 T4FW_HDR_INTFVER_RI = 0x00,
9407 T4FW_HDR_INTFVER_ISCSIPDU= 0x00,
9408 T4FW_HDR_INTFVER_ISCSI = 0x00,
9409 T4FW_HDR_INTFVER_FCOEPDU = 0x00,
9410 T4FW_HDR_INTFVER_FCOE = 0x00,
9414 T5FW_HDR_INTFVER_NIC = 0x00,
9415 T5FW_HDR_INTFVER_VNIC = 0x00,
9416 T5FW_HDR_INTFVER_OFLD = 0x00,
9417 T5FW_HDR_INTFVER_RI = 0x00,
9418 T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
9419 T5FW_HDR_INTFVER_ISCSI = 0x00,
9420 T5FW_HDR_INTFVER_FCOEPDU= 0x00,
9421 T5FW_HDR_INTFVER_FCOE = 0x00,
9425 T6FW_HDR_INTFVER_NIC = 0x00,
9426 T6FW_HDR_INTFVER_VNIC = 0x00,
9427 T6FW_HDR_INTFVER_OFLD = 0x00,
9428 T6FW_HDR_INTFVER_RI = 0x00,
9429 T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
9430 T6FW_HDR_INTFVER_ISCSI = 0x00,
9431 T6FW_HDR_INTFVER_FCOEPDU= 0x00,
9432 T6FW_HDR_INTFVER_FCOE = 0x00,
9436 FW_HDR_MAGIC_RUNTIME = 0x00000000,
9437 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
9441 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
9445 * External PHY firmware binary header format
9447 struct fw_ephy_hdr {
9450 __be16 len512; /* bin length in units of 512-bytes */
9457 __be32 reserved1[4];
9461 FW_EPHY_HDR_MAGIC = 0x65706879,
9464 #endif /* _T4FW_INTERFACE_H_ */