1 # Chelsio T6 Factory Default configuration file.
3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
5 # DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
11 # adapters shipped from the factory. These defaults are designed to address
12 # the needs of the vast majority of Terminator customers. The basic idea is to
13 # have a default configuration which allows a customer to plug a Terminator
14 # adapter in and have it work regardless of OS, driver or application except in
15 # the most unusual and/or demanding customer applications.
17 # Many of the Terminator resources which are described by this configuration
18 # are finite. This requires balancing the configuration/operation needs of
19 # device drivers across OSes and a large number of customer application.
21 # Some of the more important resources to allocate and their constaints are:
22 # 1. Virtual Interfaces: 256.
23 # 2. Ingress Queues with Free Lists: 1024.
24 # 3. Egress Queues: 128K.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
27 # address matching on Ingress Packets.
29 # Some of the important OS/Driver resource needs are:
30 # 6. Some OS Drivers will manage all resources through a single Physical
31 # Function (currently PF4 but it could be any Physical Function).
32 # 7. Some OS Drivers will manage different ports and functions (NIC,
33 # storage, etc.) on different Physical Functions. For example, NIC
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
36 # Some of the customer application needs which need to be accommodated:
37 # 8. Some customers will want to support large CPU count systems with
38 # good scaling. Thus, we'll need to accommodate a number of
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
40 # to be involved per port and per application function. For example,
41 # in the case where all ports and application functions will be
42 # managed via a single Unified PF and we want to accommodate scaling up
43 # to 8 CPUs, we would want:
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
50 # (Plus a few for Firmware Event Queues, etc.)
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
53 # Machines to directly access T6 functionality via SR-IOV Virtual Functions
54 # and "PCI Device Passthrough" -- this is especially true for the NIC
55 # application functionality.
59 # Global configuration settings.
62 rss_glb_config_mode = basicvirtual
63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
66 pl_timeout_value = 200 # the timeout value in units of us
68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host
69 # Page Size and a 64B L1 Cache Line Size. It programs the
70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
71 # If a Master PF Driver finds itself on a machine with different
72 # parameters, then the Master PF Driver is responsible for initializing
73 # these parameters to appropriate values.
76 # 1. The Free List Buffer Sizes below are raw and the firmware will
77 # round them up to the Ingress Padding Boundary.
78 # 2. The SGE Timer Values below are expressed below in microseconds.
79 # The firmware will convert these values to Core Clock Ticks when
80 # it processes the configuration parameters.
82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
95 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
96 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
98 # enable TP_OUT_CONFIG.IPIDSPLITMODE
99 reg[0x7d04] = 0x00010000/0x00010000
101 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
103 #Tick granularities in kbps
104 tsch_ticks = 100000, 10000, 1000, 10
106 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
107 # filter control: compact, fcoemask
108 # server sram : srvrsram
109 # filter tuples : fragmentation, mpshittype, macmatch, ethertype,
110 # protocol, tos, vlan, vnic_id, port, fcoe
111 # valid filterModes are described the Terminator 5 Data Book
112 # vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation
113 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
115 # filter tuples enforced in LE active region (equal to or subset of filterMode)
116 filterMask = protocol, fcoe
118 # Percentage of dynamic memory (in either the EDRAM or external MEM)
119 # to use for TP RX payload
122 # TP RX payload page size
123 tp_pmrx_pagesize = 64K
125 # TP number of RX channels
126 tp_nrxch = 0 # 0 (auto) = 1
128 # Percentage of dynamic memory (in either the EDRAM or external MEM)
129 # to use for TP TX payload
132 # TP TX payload page size
133 tp_pmtx_pagesize = 64K
135 # TP number of TX channels
136 tp_ntxch = 0 # 0 (auto) = equal number of ports
139 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
141 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
142 reg[0x7d04] = 0x00010008/0x00010008
145 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
148 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
151 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
153 # ULPRX iSCSI Page Sizes
154 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
157 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
158 # LE IPv4 compression disabled
160 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
163 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
164 # Enable more error msg for ...
167 # ULP_RX_MISC_FEATURE_ENABLE
168 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
169 # Enable offset decrement after ...
170 # PI extraction and before DDP
171 # ulp insert pi source info in DIF
172 # iscsi_eff_offset_en
174 #Enable iscsi completion moderation feature
175 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
176 # PI extraction and before DDP.
177 # ulp insert pi source info in
179 # Enable iscsi hdr cmd mode.
180 # iscsi force cmd mode.
181 # Enable iscsi cmp mode.
183 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC
186 hma_size = 92 # Size (in MBs) of host memory expected
187 hma_regions = stag,pbl,rq # What all regions to place in host memory
189 # Some "definitions" to make the rest of this a bit more readable. We support
190 # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
191 # per function per port ...
193 # NMSIX = 1088 # available MSI-X Vectors
194 # NVI = 256 # available Virtual Interfaces
195 # NMPSTCAM = 336 # MPS TCAM entries
198 # NCPUS = 16 # CPUs we want to support scalably
199 # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
201 # Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
202 # PF" which many OS Drivers will use to manage most or all functions.
204 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
205 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
206 # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
207 # will be specified as the "Ingress Queue Asynchronous Destination Index."
208 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
209 # than or equal to the number of Ingress Queues ...
211 # NVI_NIC = 4 # NIC access to NPORTS
212 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
213 # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
214 # NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
215 # NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
216 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
218 # NVI_OFLD = 0 # Offload uses NIC function to access ports
219 # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
220 # NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
221 # NEQ_OFLD = 16 # Offload Egress Queues (FL)
222 # NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
223 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
225 # NVI_RDMA = 0 # RDMA uses NIC function to access ports
226 # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
227 # NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
228 # NEQ_RDMA = 4 # RDMA Egress Queues (FL)
229 # NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
230 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
232 # NEQ_WD = 128 # Wire Direct TX Queues and FLs
233 # NETHCTRL_WD = 64 # Wire Direct TX Queues
234 # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
236 # NVI_ISCSI = 4 # ISCSI access to NPORTS
237 # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
238 # NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
239 # NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
240 # NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
241 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
243 # NVI_FCOE = 4 # FCOE access to NPORTS
244 # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
245 # NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
246 # NEQ_FCOE = 66 # FCOE Egress Queues (FL)
247 # NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
248 # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
250 # Two extra Ingress Queues per function for Firmware Events and Forwarded
251 # Interrupts, and two extra interrupts per function for Firmware Events (or a
252 # Forwarded Interrupt Queue) and General Interrupts per function.
254 # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
255 # # Forwarded Interrupts
256 # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
257 # # General Interrupts
259 # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
260 # their interrupts forwarded to another set of Forwarded Interrupt Queues.
262 # NVI_HYPERV = 16 # VMs we want to support
263 # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
264 # NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
265 # NEQ_HYPERV = 32 # VIQs Free Lists
266 # NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
267 # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
269 # Adding all of the above Unified PF resource needs together: (NIC + OFLD +
270 # RDMA + ISCSI + FCOE + EXTRA + HYPERV)
273 # NFLIQ_UNIFIED = 106
274 # NETHCTRL_UNIFIED = 32
276 # NMPSTCAM_UNIFIED = 40
278 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
279 # that up to 128 to make sure the Unified PF doesn't run out of resources.
281 # NMSIX_UNIFIED = 128
283 # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
284 # which is 34 but they're probably safe with 32.
288 # Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
289 # associated with it. Thus, the MSI-X Vector allocations we give to the
290 # UnifiedPF aren't inherited by any Virtual Functions. As a result we can
291 # provision many more Virtual Functions than we can if the UnifiedPF were
295 # All of the below PCI-E parameters are actually stored in various *_init.txt
296 # files. We include them below essentially as comments.
298 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
301 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
303 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
304 # storage applications across all four possible ports.
306 # Additionally, since the UnifiedPF isn't one of the per-port Physical
307 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
308 # different PCI Device IDs which will allow Unified and Per-Port Drivers
309 # to directly select the type of Physical Function to which they wish to be
312 # Note that the actual values used for the PCI-E Intelectual Property will be
313 # 1 less than those below since that's the way it "counts" things. For
314 # readability, we use the number we actually mean ...
316 # PF0_INT = 8 # NCPUS
317 # PF1_INT = 8 # NCPUS
318 # PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
320 # PF4_INT = 128 # NMSIX_UNIFIED
321 # PF5_INT = 32 # NMSIX_STORAGE
322 # PF6_INT = 32 # NMSIX_STORAGE
323 # PF7_INT = 0 # Nothing Assigned
324 # PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
326 # PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
328 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
329 # but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
334 # For those OSes which manage different ports on different PFs, we need
335 # only enough resources to support a single port's NIC application functions
336 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
337 # Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
338 # managed on the "storage PFs" (see below).
341 nvf = 16 # NVF on this function
342 wx_caps = all # write/execute permissions for all commands
343 r_caps = all # read permissions for all commands
345 niqflint = 8 # NCPUS "Queue Sets"
346 nethctrl = 8 # NCPUS "Queue Sets"
347 neq = 16 # niqflint + nethctrl Egress Queues
348 nexactf = 8 # number of exact MPSTCAM MAC filters
349 cmask = all # access to all channels
350 pmask = 0x1 # access to only one port
354 nvf = 16 # NVF on this function
355 wx_caps = all # write/execute permissions for all commands
356 r_caps = all # read permissions for all commands
358 niqflint = 8 # NCPUS "Queue Sets"
359 nethctrl = 8 # NCPUS "Queue Sets"
360 neq = 16 # niqflint + nethctrl Egress Queues
361 nexactf = 8 # number of exact MPSTCAM MAC filters
362 cmask = all # access to all channels
363 pmask = 0x2 # access to only one port
366 nvf = 16 # NVF on this function
367 wx_caps = all # write/execute permissions for all commands
368 r_caps = all # read permissions for all commands
370 niqflint = 8 # NCPUS "Queue Sets"
371 nethctrl = 8 # NCPUS "Queue Sets"
372 neq = 16 # niqflint + nethctrl Egress Queues
373 nexactf = 8 # number of exact MPSTCAM MAC filters
374 cmask = all # access to all channels
375 pmask = 0x4 # access to only one port
378 nvf = 16 # NVF on this function
379 wx_caps = all # write/execute permissions for all commands
380 r_caps = all # read permissions for all commands
382 niqflint = 8 # NCPUS "Queue Sets"
383 nethctrl = 8 # NCPUS "Queue Sets"
384 neq = 16 # niqflint + nethctrl Egress Queues
385 nexactf = 8 # number of exact MPSTCAM MAC filters
386 cmask = all # access to all channels
387 pmask = 0x8 # access to only one port
390 # Some OS Drivers manage all application functions for all ports via PF4.
391 # Thus we need to provide a large number of resources here. For Egress
392 # Queues we need to account for both TX Queues as well as Free List Queues
393 # (because the host is responsible for producing Free List Buffers for the
394 # hardware to consume).
397 wx_caps = all # write/execute permissions for all commands
398 r_caps = all # read permissions for all commands
399 nvi = 28 # NVI_UNIFIED
400 niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
401 nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside
402 neq = 256 # NEQ_UNIFIED + NEQ_WD
404 nexactf = 40 # NMPSTCAM_UNIFIED
406 cmask = all # access to all channels
407 pmask = all # access to all four ports ...
408 nethofld = 1024 # number of user mode ethernet flow contexts
409 ncrypto_lookaside = 16 # Number of lookaside flow contexts
410 nclip = 320 # number of clip region entries
411 nfilter = 496 # number of filter region entries
412 nserver = 496 # number of server region entries
413 nhash = 12288 # number of hash region entries
414 nhpfilter = 64 # number of high priority filter region entries
415 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline
420 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes
426 # We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
427 # need to have Virtual Interfaces on each of the four ports with up to NCPUS
431 wx_caps = all # write/execute permissions for all commands
432 r_caps = all # read permissions for all commands
434 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
435 nethctrl = 32 # NPORTS*NCPUS
436 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
437 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
438 cmask = all # access to all channels
439 pmask = all # access to all four ports ...
444 protocol = iscsi_initiator_fofld
448 iscsi_nconn_per_session = 1
449 iscsi_ninitiator_instance = 64
453 wx_caps = all # write/execute permissions for all commands
454 r_caps = all # read permissions for all commands
456 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
457 nethctrl = 32 # NPORTS*NCPUS
458 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
459 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
460 # which is OK since < MIN(SUM PF0..3, PF4)
461 # and we never load PF0..3 and PF4 concurrently
462 cmask = all # access to all channels
463 pmask = all # access to all four ports ...
466 protocol = fcoe_initiator
473 # The following function, 1023, is not an actual PCIE function but is used to
474 # configure and reserve firmware internal resources that come from the global
478 wx_caps = all # write/execute permissions for all commands
479 r_caps = all # read permissions for all commands
480 nvi = 4 # NVI_UNIFIED
481 cmask = all # access to all channels
482 pmask = all # access to all four ports ...
483 nexactf = 8 # NPORTS + DCBX +
484 nfilter = 16 # number of filter region entries
487 # For Virtual functions, we only allow NIC functionality and we only allow
488 # access to one port (1 << PF). Note that because of limitations in the
489 # Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
490 # and GTS registers, the number of Ingress and Egress Queues must be a power
493 [function "0/*"] # NVF
494 wx_caps = 0x82 # DMAQ | VF
495 r_caps = 0x86 # DMAQ | VF | PORT
497 niqflint = 6 # 2 "Queue Sets" + NXIQ
498 nethctrl = 4 # 2 "Queue Sets"
499 neq = 8 # 2 "Queue Sets" * 2
501 cmask = all # access to all channels
502 pmask = 0x1 # access to only one port ...
505 [function "1/*"] # NVF
506 wx_caps = 0x82 # DMAQ | VF
507 r_caps = 0x86 # DMAQ | VF | PORT
509 niqflint = 6 # 2 "Queue Sets" + NXIQ
510 nethctrl = 4 # 2 "Queue Sets"
511 neq = 8 # 2 "Queue Sets" * 2
513 cmask = all # access to all channels
514 pmask = 0x2 # access to only one port ...
516 [function "2/*"] # NVF
517 wx_caps = 0x82 # DMAQ | VF
518 r_caps = 0x86 # DMAQ | VF | PORT
520 niqflint = 6 # 2 "Queue Sets" + NXIQ
521 nethctrl = 4 # 2 "Queue Sets"
522 neq = 8 # 2 "Queue Sets" * 2
524 cmask = all # access to all channels
525 pmask = 0x1 # access to only one port ...
528 [function "3/*"] # NVF
529 wx_caps = 0x82 # DMAQ | VF
530 r_caps = 0x86 # DMAQ | VF | PORT
532 niqflint = 6 # 2 "Queue Sets" + NXIQ
533 nethctrl = 4 # 2 "Queue Sets"
534 neq = 8 # 2 "Queue Sets" * 2
536 cmask = all # access to all channels
537 pmask = 0x2 # access to only one port ...
539 # MPS features a 196608 bytes ingress buffer that is used for ingress buffering
540 # for packets from the wire as well as the loopback path of the L2 switch. The
541 # folling params control how the buffer memory is distributed and the L2 flow
544 # bg_mem: %-age of mem to use for port/buffer group
545 # lpbk_mem: %-age of port/bg mem to use for loopback
546 # hwm: high watermark; bytes available when starting to send pause
547 # frames (in units of 0.1 MTU)
548 # lwm: low watermark; bytes remaining when sending 'unpause' frame
549 # (in inuits of 0.1 MTU)
550 # dwm: minimum delta between high and low watermark (in units of 100
554 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
560 dcb_app_tlv[0] = 0x8906, ethertype, 3
561 dcb_app_tlv[1] = 0x8914, ethertype, 3
562 dcb_app_tlv[2] = 3260, socketnum, 5
571 dcb_app_tlv[0] = 0x8906, ethertype, 3
572 dcb_app_tlv[1] = 0x8914, ethertype, 3
573 dcb_app_tlv[2] = 3260, socketnum, 5
577 checksum = 0x64f3def4
579 # Total resources used by above allocations:
580 # Virtual Interfaces: 104
581 # Ingress Queues/w Free Lists and Interrupts: 526
583 # MPS TCAM Entries: 336
585 # Virtual Functions: 64