2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef __IW_CXGB4_H__
36 #define __IW_CXGB4_H__
38 #include <linux/list.h>
39 #include <linux/spinlock.h>
40 #include <linux/idr.h>
41 #include <linux/completion.h>
42 #include <linux/netdevice.h>
43 #include <linux/sched.h>
44 #include <linux/pci.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/wait.h>
47 #include <linux/kref.h>
48 #include <linux/timer.h>
52 #include <asm/byteorder.h>
54 #include <netinet/in.h>
55 #include <netinet/toecore.h>
57 #include <rdma/ib_verbs.h>
58 #include <rdma/iw_cm.h>
62 #include "common/common.h"
63 #include "common/t4_msg.h"
64 #include "common/t4_regs.h"
65 #include "common/t4_tcb.h"
68 #define DRV_NAME "iw_cxgbe"
69 #define MOD DRV_NAME ":"
70 #define KTR_IW_CXGBE KTR_SPARE3
72 extern int c4iw_debug;
74 extern int inline_threshold;
76 #define PDBG(fmt, args...) \
79 printf(MOD fmt, ## args); \
84 static inline void *cplhdr(struct mbuf *m)
86 return mtod(m, void*);
89 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
90 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
92 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
93 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
95 struct c4iw_id_table {
97 u32 start; /* logical minimal id */
98 u32 last; /* hint for find */
101 unsigned long *table;
104 struct c4iw_resource {
105 struct c4iw_id_table tpt_table;
106 struct c4iw_id_table qid_table;
107 struct c4iw_id_table pdid_table;
110 struct c4iw_qid_list {
111 struct list_head entry;
115 struct c4iw_dev_ucontext {
116 struct list_head qpids;
117 struct list_head cqids;
121 enum c4iw_rdev_flags {
122 T4_FATAL_ERROR = (1<<0),
123 T4_STATUS_PAGE_DISABLED = (1<<1),
135 struct c4iw_stat qid;
137 struct c4iw_stat stag;
138 struct c4iw_stat pbl;
139 struct c4iw_stat rqt;
142 struct c4iw_hw_queue {
143 int t4_eq_status_entries;
154 struct adapter *adap;
155 struct c4iw_resource resource;
156 unsigned long qpshift;
158 unsigned long cqshift;
160 struct c4iw_dev_ucontext uctx;
164 struct c4iw_stats stats;
165 struct c4iw_hw_queue hw_queue;
166 struct t4_dev_status_page *status_page;
167 unsigned long bar2_pa;
168 void __iomem *bar2_kva;
169 unsigned int bar2_len;
170 struct workqueue_struct *free_workq;
173 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
175 return rdev->flags & T4_FATAL_ERROR;
178 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
180 return (int)(rdev->adap->vres.stag.size >> 5);
183 #define C4IW_WR_TO (60*HZ)
185 struct c4iw_wr_wait {
187 struct completion completion;
190 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
193 init_completion(&wr_waitp->completion);
196 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
199 complete(&wr_waitp->completion);
203 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
204 u32 hwtid, u32 qpid, struct socket *so, const char *func)
206 struct adapter *sc = rdev->adap;
207 unsigned to = C4IW_WR_TO;
210 struct timeval t1, t2;
212 if (c4iw_fatal_error(rdev)) {
213 wr_waitp->ret = -EIO;
219 /* If waiting for reply in rdma_init()/rdma_fini() threads, then
220 * check if there are any connection errors.
222 if (so && so->so_error) {
223 wr_waitp->ret = -ECONNRESET;
224 CTR5(KTR_IW_CXGBE, "%s - Connection ERROR %u for sock %p"
225 "tid %u qpid %u", func,
226 so->so_error, so, hwtid, qpid);
230 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
233 timevalsub(&t2, &t1);
234 printf("%s - Device %s not responding after %ld.%06ld "
235 "seconds - tid %u qpid %u\n", func,
236 device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
238 if (c4iw_fatal_error(rdev)) {
239 wr_waitp->ret = -EIO;
250 timevalsub(&t2, &t1);
251 printf("%s - Device %s reply after %ld.%06ld seconds - "
252 "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
253 t2.tv_sec, t2.tv_usec, hwtid, qpid);
256 CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
257 wr_waitp->ret, hwtid, qpid);
258 return (wr_waitp->ret);
262 struct ib_device ibdev;
263 struct c4iw_rdev rdev;
264 u32 device_cap_flags;
269 struct dentry *debugfs_root;
273 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
275 return container_of(ibdev, struct c4iw_dev, ibdev);
278 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
280 return container_of(rdev, struct c4iw_dev, rdev);
283 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
285 return idr_find(&rhp->cqidr, cqid);
288 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
290 return idr_find(&rhp->qpidr, qpid);
293 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
295 return idr_find(&rhp->mmidr, mmid);
298 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
299 void *handle, u32 id, int lock)
305 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
308 spin_lock_irq(&rhp->lock);
309 ret = idr_get_new_above(idr, handle, id, &newid);
310 BUG_ON(!ret && newid != id);
312 spin_unlock_irq(&rhp->lock);
313 } while (ret == -EAGAIN);
318 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
319 void *handle, u32 id)
321 return _insert_handle(rhp, idr, handle, id, 1);
324 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
325 void *handle, u32 id)
327 return _insert_handle(rhp, idr, handle, id, 0);
330 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
334 spin_lock_irq(&rhp->lock);
337 spin_unlock_irq(&rhp->lock);
340 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
342 _remove_handle(rhp, idr, id, 1);
345 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
346 struct idr *idr, u32 id)
348 _remove_handle(rhp, idr, id, 0);
351 extern int c4iw_max_read_depth;
353 static inline int cur_max_read_depth(struct c4iw_dev *dev)
355 return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth);
361 struct c4iw_dev *rhp;
364 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
366 return container_of(ibpd, struct c4iw_pd, ibpd);
369 struct tpt_attributes {
372 enum fw_ri_mem_perms perms;
381 u32 remote_invaliate_disable:1;
383 u32 mw_bind_enable:1;
389 struct ib_umem *umem;
390 struct c4iw_dev *rhp;
392 struct tpt_attributes attr;
399 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
401 return container_of(ibmr, struct c4iw_mr, ibmr);
406 struct c4iw_dev *rhp;
408 struct tpt_attributes attr;
411 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
413 return container_of(ibmw, struct c4iw_mw, ibmw);
418 struct c4iw_dev *rhp;
421 spinlock_t comp_handler_lock;
423 wait_queue_head_t wait;
426 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
428 return container_of(ibcq, struct c4iw_cq, ibcq);
431 struct c4iw_mpa_attributes {
433 u8 recv_marker_enabled;
434 u8 xmit_marker_enabled;
436 u8 enhanced_rdma_conn;
441 struct c4iw_qp_attributes {
447 u32 sq_max_sges_rdma_write;
451 u8 enable_rdma_write;
453 u8 enable_mmid0_fastreg;
458 char terminate_buffer[52];
459 u32 terminate_msg_len;
460 u8 is_terminate_local;
461 struct c4iw_mpa_attributes mpa_attr;
462 struct c4iw_ep *llp_stream_handle;
472 struct c4iw_dev *rhp;
474 struct c4iw_qp_attributes attr;
479 wait_queue_head_t wait;
480 struct timer_list timer;
482 struct work_struct free_work;
483 struct c4iw_ucontext *ucontext;
486 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
488 return container_of(ibqp, struct c4iw_qp, ibqp);
491 struct c4iw_ucontext {
492 struct ib_ucontext ibucontext;
493 struct c4iw_dev_ucontext uctx;
495 spinlock_t mmap_lock;
496 struct list_head mmaps;
500 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
502 return container_of(c, struct c4iw_ucontext, ibucontext);
505 void _c4iw_free_ucontext(struct kref *kref);
507 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
509 kref_put(&ucontext->kref, _c4iw_free_ucontext);
511 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
513 kref_get(&ucontext->kref);
516 struct c4iw_mm_entry {
517 struct list_head entry;
523 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
524 u32 key, unsigned len)
526 struct list_head *pos, *nxt;
527 struct c4iw_mm_entry *mm;
529 spin_lock(&ucontext->mmap_lock);
530 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
532 mm = list_entry(pos, struct c4iw_mm_entry, entry);
533 if (mm->key == key && mm->len == len) {
534 list_del_init(&mm->entry);
535 spin_unlock(&ucontext->mmap_lock);
536 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
537 __func__, key, (unsigned long long) mm->addr,
542 spin_unlock(&ucontext->mmap_lock);
546 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
547 struct c4iw_mm_entry *mm)
549 spin_lock(&ucontext->mmap_lock);
550 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
551 (unsigned long long) mm->addr, mm->len);
552 list_add_tail(&mm->entry, &ucontext->mmaps);
553 spin_unlock(&ucontext->mmap_lock);
556 enum c4iw_qp_attr_mask {
557 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
558 C4IW_QP_ATTR_SQ_DB = 1<<1,
559 C4IW_QP_ATTR_RQ_DB = 1<<2,
560 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
561 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
562 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
563 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
564 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
565 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
566 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
567 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
568 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
569 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
570 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
571 C4IW_QP_ATTR_MAX_ORD |
572 C4IW_QP_ATTR_MAX_IRD |
573 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
574 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
575 C4IW_QP_ATTR_MPA_ATTR |
576 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
579 int c4iw_modify_qp(struct c4iw_dev *rhp,
581 enum c4iw_qp_attr_mask mask,
582 struct c4iw_qp_attributes *attrs,
589 C4IW_QP_STATE_TERMINATE,
590 C4IW_QP_STATE_CLOSING,
595 * IW_CXGBE event bits.
596 * These bits are used for handling all events for a particular 'ep' serially.
598 #define C4IW_EVENT_SOCKET 0x0001
599 #define C4IW_EVENT_TIMEOUT 0x0002
600 #define C4IW_EVENT_TERM 0x0004
602 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
607 return C4IW_QP_STATE_IDLE;
609 return C4IW_QP_STATE_RTS;
611 return C4IW_QP_STATE_CLOSING;
613 return C4IW_QP_STATE_TERMINATE;
615 return C4IW_QP_STATE_ERROR;
621 static inline int to_ib_qp_state(int c4iw_qp_state)
623 switch (c4iw_qp_state) {
624 case C4IW_QP_STATE_IDLE:
626 case C4IW_QP_STATE_RTS:
628 case C4IW_QP_STATE_CLOSING:
630 case C4IW_QP_STATE_TERMINATE:
632 case C4IW_QP_STATE_ERROR:
638 #define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
640 static inline u32 c4iw_ib_to_tpt_access(int a)
642 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
643 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
644 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
645 FW_RI_MEM_ACCESS_LOCAL_READ;
648 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
650 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
651 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
654 enum c4iw_mmid_state {
655 C4IW_STAG_STATE_VALID,
656 C4IW_STAG_STATE_INVALID
659 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
661 #define MPA_KEY_REQ "MPA ID Req Frame"
662 #define MPA_KEY_REP "MPA ID Rep Frame"
664 #define MPA_MAX_PRIVATE_DATA 256
665 #define MPA_ENHANCED_RDMA_CONN 0x10
666 #define MPA_REJECT 0x20
668 #define MPA_MARKERS 0x80
669 #define MPA_FLAGS_MASK 0xE0
671 #define MPA_V2_PEER2PEER_MODEL 0x8000
672 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
673 #define MPA_V2_RDMA_WRITE_RTR 0x8000
674 #define MPA_V2_RDMA_READ_RTR 0x4000
675 #define MPA_V2_IRD_ORD_MASK 0x3FFF
677 #define c4iw_put_ep(ep) { \
678 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
679 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
680 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
681 kref_put(&((ep)->kref), _c4iw_free_ep); \
684 #define c4iw_get_ep(ep) { \
685 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
686 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
687 kref_get(&((ep)->kref)); \
690 void _c4iw_free_ep(struct kref *kref);
696 __be16 private_data_size;
700 struct mpa_v2_conn_params {
705 struct terminate_message {
712 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
714 enum c4iw_layers_types {
718 RDMAP_LOCAL_CATA = 0x00,
719 RDMAP_REMOTE_PROT = 0x01,
720 RDMAP_REMOTE_OP = 0x02,
721 DDP_LOCAL_CATA = 0x00,
722 DDP_TAGGED_ERR = 0x01,
723 DDP_UNTAGGED_ERR = 0x02,
727 enum c4iw_rdma_ecodes {
728 RDMAP_INV_STAG = 0x00,
729 RDMAP_BASE_BOUNDS = 0x01,
730 RDMAP_ACC_VIOL = 0x02,
731 RDMAP_STAG_NOT_ASSOC = 0x03,
732 RDMAP_TO_WRAP = 0x04,
733 RDMAP_INV_VERS = 0x05,
734 RDMAP_INV_OPCODE = 0x06,
735 RDMAP_STREAM_CATA = 0x07,
736 RDMAP_GLOBAL_CATA = 0x08,
737 RDMAP_CANT_INV_STAG = 0x09,
738 RDMAP_UNSPECIFIED = 0xff
741 enum c4iw_ddp_ecodes {
742 DDPT_INV_STAG = 0x00,
743 DDPT_BASE_BOUNDS = 0x01,
744 DDPT_STAG_NOT_ASSOC = 0x02,
746 DDPT_INV_VERS = 0x04,
748 DDPU_INV_MSN_NOBUF = 0x02,
749 DDPU_INV_MSN_RANGE = 0x03,
751 DDPU_MSG_TOOBIG = 0x05,
755 enum c4iw_mpa_ecodes {
757 MPA_MARKER_ERR = 0x03,
758 MPA_LOCAL_CATA = 0x05,
759 MPA_INSUFF_IRD = 0x06,
760 MPA_NOMATCH_RTR = 0x07,
779 PEER_ABORT_IN_PROGRESS = 0,
780 ABORT_REQ_IN_PROGRESS = 1,
781 RELEASE_RESOURCES = 2,
788 enum c4iw_ep_history {
808 CONN_RPL_UPCALL = 19,
809 ACT_RETRY_NOMEM = 20,
810 ACT_RETRY_INUSE = 21,
819 struct c4iw_ep_common {
820 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
821 struct iw_cm_id *cm_id;
823 struct c4iw_dev *dev;
824 enum c4iw_ep_state state;
827 struct sockaddr_storage local_addr;
828 struct sockaddr_storage remote_addr;
829 struct c4iw_wr_wait wr_wait;
831 unsigned long history;
834 struct thread *thread;
839 struct c4iw_listen_ep {
840 struct c4iw_ep_common com;
843 struct list_head listen_ep_list; /* list of all listener ep's bound
844 to one port address */
848 struct c4iw_ep_common com;
849 struct c4iw_listen_ep *parent_ep;
850 struct timer_list timer;
855 struct l2t_entry *l2t;
856 struct dst_entry *dst;
857 struct c4iw_mpa_attributes mpa_attr;
858 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
859 unsigned int mpa_pkt_len;
871 u8 retry_with_mpa_v1;
872 u8 tried_with_mpa_v1;
875 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
877 return cm_id->provider_data;
880 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
882 return cm_id->provider_data;
885 static inline int compute_wscale(int win)
889 while (wscale < 14 && (65535<<wscale) < win)
894 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
895 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
896 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
897 u32 reserved, u32 flags);
898 void c4iw_id_table_free(struct c4iw_id_table *alloc);
900 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
902 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
903 struct l2t_entry *l2t);
904 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
905 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
906 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
907 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
908 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
909 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
910 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
911 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
912 void c4iw_destroy_resource(struct c4iw_resource *rscp);
913 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
914 int c4iw_register_device(struct c4iw_dev *dev);
915 void c4iw_unregister_device(struct c4iw_dev *dev);
916 int __init c4iw_cm_init(void);
917 void __exit c4iw_cm_term(void);
918 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
919 struct c4iw_dev_ucontext *uctx);
920 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
921 struct c4iw_dev_ucontext *uctx);
922 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
923 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
924 struct ib_send_wr **bad_wr);
925 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
926 struct ib_recv_wr **bad_wr);
927 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
928 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
929 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
930 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
931 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
932 void c4iw_qp_add_ref(struct ib_qp *qp);
933 void c4iw_qp_rem_ref(struct ib_qp *qp);
934 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
936 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
937 int sg_nents, unsigned int *sg_offset);
938 int c4iw_dealloc_mw(struct ib_mw *mw);
939 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
940 struct ib_udata *udata);
941 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
942 virt, int acc, struct ib_udata *udata);
943 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
944 int c4iw_dereg_mr(struct ib_mr *ib_mr);
945 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
946 int c4iw_destroy_cq(struct ib_cq *ib_cq);
947 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
948 const struct ib_cq_init_attr *attr,
949 struct ib_ucontext *ib_context,
950 struct ib_udata *udata);
951 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
952 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
953 int c4iw_destroy_qp(struct ib_qp *ib_qp);
954 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
955 struct ib_qp_init_attr *attrs,
956 struct ib_udata *udata);
957 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
958 int attr_mask, struct ib_udata *udata);
959 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
960 int attr_mask, struct ib_qp_init_attr *init_attr);
961 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
962 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
963 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
964 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
965 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
966 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
967 void c4iw_flush_hw_cq(struct c4iw_cq *cq);
968 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
969 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
970 int __c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
971 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
972 int c4iw_flush_sq(struct c4iw_qp *qhp);
973 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
974 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
975 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
976 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
977 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
978 struct c4iw_dev_ucontext *uctx);
979 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
980 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
981 struct c4iw_dev_ucontext *uctx);
982 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);