2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef __IW_CXGB4_H__
36 #define __IW_CXGB4_H__
38 #include <linux/list.h>
39 #include <linux/spinlock.h>
40 #include <linux/idr.h>
41 #include <linux/completion.h>
42 #include <linux/netdevice.h>
43 #include <linux/sched.h>
44 #include <linux/pci.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/wait.h>
47 #include <linux/kref.h>
48 #include <linux/timer.h>
52 #include <asm/byteorder.h>
54 #include <netinet/in.h>
55 #include <netinet/toecore.h>
57 #include <rdma/ib_verbs.h>
58 #include <rdma/iw_cm.h>
62 #include "common/common.h"
63 #include "common/t4_msg.h"
64 #include "common/t4_regs.h"
65 #include "common/t4_tcb.h"
68 #define DRV_NAME "iw_cxgbe"
69 #define MOD DRV_NAME ":"
70 #define KTR_IW_CXGBE KTR_SPARE3
72 extern int c4iw_debug;
73 #define PDBG(fmt, args...) \
76 printf(MOD fmt, ## args); \
81 static inline void *cplhdr(struct mbuf *m)
83 return mtod(m, void*);
86 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
87 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
89 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
90 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
92 struct c4iw_id_table {
94 u32 start; /* logical minimal id */
95 u32 last; /* hint for find */
101 struct c4iw_resource {
102 struct c4iw_id_table tpt_table;
103 struct c4iw_id_table qid_table;
104 struct c4iw_id_table pdid_table;
107 struct c4iw_qid_list {
108 struct list_head entry;
112 struct c4iw_dev_ucontext {
113 struct list_head qpids;
114 struct list_head cqids;
118 enum c4iw_rdev_flags {
119 T4_FATAL_ERROR = (1<<0),
120 T4_STATUS_PAGE_DISABLED = (1<<1),
132 struct c4iw_stat qid;
134 struct c4iw_stat stag;
135 struct c4iw_stat pbl;
136 struct c4iw_stat rqt;
139 struct c4iw_hw_queue {
140 int t4_eq_status_entries;
151 struct adapter *adap;
152 struct c4iw_resource resource;
153 unsigned long qpshift;
155 unsigned long cqshift;
157 struct c4iw_dev_ucontext uctx;
161 struct c4iw_stats stats;
162 struct c4iw_hw_queue hw_queue;
163 struct t4_dev_status_page *status_page;
164 unsigned long bar2_pa;
165 void __iomem *bar2_kva;
166 unsigned int bar2_len;
167 struct workqueue_struct *free_workq;
170 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
172 return rdev->flags & T4_FATAL_ERROR;
175 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
177 return (int)(rdev->adap->vres.stag.size >> 5);
180 #define C4IW_WR_TO (60*HZ)
182 struct c4iw_wr_wait {
184 struct completion completion;
187 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
190 init_completion(&wr_waitp->completion);
193 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
196 complete(&wr_waitp->completion);
200 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
201 u32 hwtid, u32 qpid, struct socket *so, const char *func)
203 struct adapter *sc = rdev->adap;
204 unsigned to = C4IW_WR_TO;
207 struct timeval t1, t2;
209 if (c4iw_fatal_error(rdev)) {
210 wr_waitp->ret = -EIO;
216 /* If waiting for reply in rdma_init()/rdma_fini() threads, then
217 * check if there are any connection errors.
219 if (so && so->so_error) {
220 wr_waitp->ret = -ECONNRESET;
221 CTR5(KTR_IW_CXGBE, "%s - Connection ERROR %u for sock %p"
222 "tid %u qpid %u", func,
223 so->so_error, so, hwtid, qpid);
227 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
230 timevalsub(&t2, &t1);
231 printf("%s - Device %s not responding after %ld.%06ld "
232 "seconds - tid %u qpid %u\n", func,
233 device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
235 if (c4iw_fatal_error(rdev)) {
236 wr_waitp->ret = -EIO;
247 timevalsub(&t2, &t1);
248 printf("%s - Device %s reply after %ld.%06ld seconds - "
249 "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
250 t2.tv_sec, t2.tv_usec, hwtid, qpid);
253 CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
254 wr_waitp->ret, hwtid, qpid);
255 return (wr_waitp->ret);
259 struct ib_device ibdev;
260 struct c4iw_rdev rdev;
261 u32 device_cap_flags;
266 struct dentry *debugfs_root;
270 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
272 return container_of(ibdev, struct c4iw_dev, ibdev);
275 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
277 return container_of(rdev, struct c4iw_dev, rdev);
280 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
282 return idr_find(&rhp->cqidr, cqid);
285 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
287 return idr_find(&rhp->qpidr, qpid);
290 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
292 return idr_find(&rhp->mmidr, mmid);
295 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
296 void *handle, u32 id, int lock)
302 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
305 spin_lock_irq(&rhp->lock);
306 ret = idr_get_new_above(idr, handle, id, &newid);
307 BUG_ON(!ret && newid != id);
309 spin_unlock_irq(&rhp->lock);
310 } while (ret == -EAGAIN);
315 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
316 void *handle, u32 id)
318 return _insert_handle(rhp, idr, handle, id, 1);
321 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
322 void *handle, u32 id)
324 return _insert_handle(rhp, idr, handle, id, 0);
327 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
331 spin_lock_irq(&rhp->lock);
334 spin_unlock_irq(&rhp->lock);
337 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
339 _remove_handle(rhp, idr, id, 1);
342 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
343 struct idr *idr, u32 id)
345 _remove_handle(rhp, idr, id, 0);
348 extern int c4iw_max_read_depth;
350 static inline int cur_max_read_depth(struct c4iw_dev *dev)
352 return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth);
358 struct c4iw_dev *rhp;
361 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
363 return container_of(ibpd, struct c4iw_pd, ibpd);
366 struct tpt_attributes {
369 enum fw_ri_mem_perms perms;
378 u32 remote_invaliate_disable:1;
380 u32 mw_bind_enable:1;
386 struct ib_umem *umem;
387 struct c4iw_dev *rhp;
389 struct tpt_attributes attr;
396 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
398 return container_of(ibmr, struct c4iw_mr, ibmr);
403 struct c4iw_dev *rhp;
405 struct tpt_attributes attr;
408 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
410 return container_of(ibmw, struct c4iw_mw, ibmw);
415 struct c4iw_dev *rhp;
418 spinlock_t comp_handler_lock;
420 wait_queue_head_t wait;
423 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
425 return container_of(ibcq, struct c4iw_cq, ibcq);
428 struct c4iw_mpa_attributes {
430 u8 recv_marker_enabled;
431 u8 xmit_marker_enabled;
433 u8 enhanced_rdma_conn;
438 struct c4iw_qp_attributes {
444 u32 sq_max_sges_rdma_write;
448 u8 enable_rdma_write;
450 u8 enable_mmid0_fastreg;
455 char terminate_buffer[52];
456 u32 terminate_msg_len;
457 u8 is_terminate_local;
458 struct c4iw_mpa_attributes mpa_attr;
459 struct c4iw_ep *llp_stream_handle;
469 struct c4iw_dev *rhp;
471 struct c4iw_qp_attributes attr;
476 wait_queue_head_t wait;
477 struct timer_list timer;
479 struct work_struct free_work;
480 struct c4iw_ucontext *ucontext;
483 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
485 return container_of(ibqp, struct c4iw_qp, ibqp);
488 struct c4iw_ucontext {
489 struct ib_ucontext ibucontext;
490 struct c4iw_dev_ucontext uctx;
492 spinlock_t mmap_lock;
493 struct list_head mmaps;
497 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
499 return container_of(c, struct c4iw_ucontext, ibucontext);
502 void _c4iw_free_ucontext(struct kref *kref);
504 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
506 kref_put(&ucontext->kref, _c4iw_free_ucontext);
508 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
510 kref_get(&ucontext->kref);
513 struct c4iw_mm_entry {
514 struct list_head entry;
520 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
521 u32 key, unsigned len)
523 struct list_head *pos, *nxt;
524 struct c4iw_mm_entry *mm;
526 spin_lock(&ucontext->mmap_lock);
527 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
529 mm = list_entry(pos, struct c4iw_mm_entry, entry);
530 if (mm->key == key && mm->len == len) {
531 list_del_init(&mm->entry);
532 spin_unlock(&ucontext->mmap_lock);
533 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
534 __func__, key, (unsigned long long) mm->addr,
539 spin_unlock(&ucontext->mmap_lock);
543 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
544 struct c4iw_mm_entry *mm)
546 spin_lock(&ucontext->mmap_lock);
547 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
548 (unsigned long long) mm->addr, mm->len);
549 list_add_tail(&mm->entry, &ucontext->mmaps);
550 spin_unlock(&ucontext->mmap_lock);
553 enum c4iw_qp_attr_mask {
554 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
555 C4IW_QP_ATTR_SQ_DB = 1<<1,
556 C4IW_QP_ATTR_RQ_DB = 1<<2,
557 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
558 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
559 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
560 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
561 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
562 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
563 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
564 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
565 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
566 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
567 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
568 C4IW_QP_ATTR_MAX_ORD |
569 C4IW_QP_ATTR_MAX_IRD |
570 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
571 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
572 C4IW_QP_ATTR_MPA_ATTR |
573 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
576 int c4iw_modify_qp(struct c4iw_dev *rhp,
578 enum c4iw_qp_attr_mask mask,
579 struct c4iw_qp_attributes *attrs,
586 C4IW_QP_STATE_TERMINATE,
587 C4IW_QP_STATE_CLOSING,
592 * IW_CXGBE event bits.
593 * These bits are used for handling all events for a particular 'ep' serially.
595 #define C4IW_EVENT_SOCKET 0x0001
596 #define C4IW_EVENT_TIMEOUT 0x0002
597 #define C4IW_EVENT_TERM 0x0004
599 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
604 return C4IW_QP_STATE_IDLE;
606 return C4IW_QP_STATE_RTS;
608 return C4IW_QP_STATE_CLOSING;
610 return C4IW_QP_STATE_TERMINATE;
612 return C4IW_QP_STATE_ERROR;
618 static inline int to_ib_qp_state(int c4iw_qp_state)
620 switch (c4iw_qp_state) {
621 case C4IW_QP_STATE_IDLE:
623 case C4IW_QP_STATE_RTS:
625 case C4IW_QP_STATE_CLOSING:
627 case C4IW_QP_STATE_TERMINATE:
629 case C4IW_QP_STATE_ERROR:
635 #define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
637 static inline u32 c4iw_ib_to_tpt_access(int a)
639 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
640 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
641 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
642 FW_RI_MEM_ACCESS_LOCAL_READ;
645 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
647 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
648 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
651 enum c4iw_mmid_state {
652 C4IW_STAG_STATE_VALID,
653 C4IW_STAG_STATE_INVALID
656 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
658 #define MPA_KEY_REQ "MPA ID Req Frame"
659 #define MPA_KEY_REP "MPA ID Rep Frame"
661 #define MPA_MAX_PRIVATE_DATA 256
662 #define MPA_ENHANCED_RDMA_CONN 0x10
663 #define MPA_REJECT 0x20
665 #define MPA_MARKERS 0x80
666 #define MPA_FLAGS_MASK 0xE0
668 #define MPA_V2_PEER2PEER_MODEL 0x8000
669 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
670 #define MPA_V2_RDMA_WRITE_RTR 0x8000
671 #define MPA_V2_RDMA_READ_RTR 0x4000
672 #define MPA_V2_IRD_ORD_MASK 0x3FFF
674 #define c4iw_put_ep(ep) { \
675 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
676 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
677 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
678 kref_put(&((ep)->kref), _c4iw_free_ep); \
681 #define c4iw_get_ep(ep) { \
682 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
683 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
684 kref_get(&((ep)->kref)); \
687 void _c4iw_free_ep(struct kref *kref);
693 __be16 private_data_size;
697 struct mpa_v2_conn_params {
702 struct terminate_message {
709 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
711 enum c4iw_layers_types {
715 RDMAP_LOCAL_CATA = 0x00,
716 RDMAP_REMOTE_PROT = 0x01,
717 RDMAP_REMOTE_OP = 0x02,
718 DDP_LOCAL_CATA = 0x00,
719 DDP_TAGGED_ERR = 0x01,
720 DDP_UNTAGGED_ERR = 0x02,
724 enum c4iw_rdma_ecodes {
725 RDMAP_INV_STAG = 0x00,
726 RDMAP_BASE_BOUNDS = 0x01,
727 RDMAP_ACC_VIOL = 0x02,
728 RDMAP_STAG_NOT_ASSOC = 0x03,
729 RDMAP_TO_WRAP = 0x04,
730 RDMAP_INV_VERS = 0x05,
731 RDMAP_INV_OPCODE = 0x06,
732 RDMAP_STREAM_CATA = 0x07,
733 RDMAP_GLOBAL_CATA = 0x08,
734 RDMAP_CANT_INV_STAG = 0x09,
735 RDMAP_UNSPECIFIED = 0xff
738 enum c4iw_ddp_ecodes {
739 DDPT_INV_STAG = 0x00,
740 DDPT_BASE_BOUNDS = 0x01,
741 DDPT_STAG_NOT_ASSOC = 0x02,
743 DDPT_INV_VERS = 0x04,
745 DDPU_INV_MSN_NOBUF = 0x02,
746 DDPU_INV_MSN_RANGE = 0x03,
748 DDPU_MSG_TOOBIG = 0x05,
752 enum c4iw_mpa_ecodes {
754 MPA_MARKER_ERR = 0x03,
755 MPA_LOCAL_CATA = 0x05,
756 MPA_INSUFF_IRD = 0x06,
757 MPA_NOMATCH_RTR = 0x07,
776 PEER_ABORT_IN_PROGRESS = 0,
777 ABORT_REQ_IN_PROGRESS = 1,
778 RELEASE_RESOURCES = 2,
785 enum c4iw_ep_history {
805 CONN_RPL_UPCALL = 19,
806 ACT_RETRY_NOMEM = 20,
807 ACT_RETRY_INUSE = 21,
816 struct c4iw_ep_common {
817 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
818 struct iw_cm_id *cm_id;
820 struct c4iw_dev *dev;
821 enum c4iw_ep_state state;
824 struct sockaddr_storage local_addr;
825 struct sockaddr_storage remote_addr;
826 struct c4iw_wr_wait wr_wait;
828 unsigned long history;
831 struct thread *thread;
836 struct c4iw_listen_ep {
837 struct c4iw_ep_common com;
840 struct list_head listen_ep_list; /* list of all listener ep's bound
841 to one port address */
845 struct c4iw_ep_common com;
846 struct c4iw_listen_ep *parent_ep;
847 struct timer_list timer;
852 struct l2t_entry *l2t;
853 struct dst_entry *dst;
854 struct c4iw_mpa_attributes mpa_attr;
855 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
856 unsigned int mpa_pkt_len;
869 u8 retry_with_mpa_v1;
870 u8 tried_with_mpa_v1;
873 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
875 return cm_id->provider_data;
878 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
880 return cm_id->provider_data;
883 static inline int compute_wscale(int win)
887 while (wscale < 14 && (65535<<wscale) < win)
892 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
893 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
894 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
895 u32 reserved, u32 flags);
896 void c4iw_id_table_free(struct c4iw_id_table *alloc);
898 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
900 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
901 struct l2t_entry *l2t);
902 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
903 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
904 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
905 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
906 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
907 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
908 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
909 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
910 void c4iw_destroy_resource(struct c4iw_resource *rscp);
911 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
912 int c4iw_register_device(struct c4iw_dev *dev);
913 void c4iw_unregister_device(struct c4iw_dev *dev);
914 int __init c4iw_cm_init(void);
915 void __exit c4iw_cm_term(void);
916 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
917 struct c4iw_dev_ucontext *uctx);
918 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
919 struct c4iw_dev_ucontext *uctx);
920 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
921 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
922 struct ib_send_wr **bad_wr);
923 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
924 struct ib_recv_wr **bad_wr);
925 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
926 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
927 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
928 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
929 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
930 void c4iw_qp_add_ref(struct ib_qp *qp);
931 void c4iw_qp_rem_ref(struct ib_qp *qp);
932 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
934 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
935 int sg_nents, unsigned int *sg_offset);
936 int c4iw_dealloc_mw(struct ib_mw *mw);
937 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
938 struct ib_udata *udata);
939 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
940 virt, int acc, struct ib_udata *udata);
941 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
942 int c4iw_dereg_mr(struct ib_mr *ib_mr);
943 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
944 int c4iw_destroy_cq(struct ib_cq *ib_cq);
945 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
946 const struct ib_cq_init_attr *attr,
947 struct ib_ucontext *ib_context,
948 struct ib_udata *udata);
949 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
950 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
951 int c4iw_destroy_qp(struct ib_qp *ib_qp);
952 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
953 struct ib_qp_init_attr *attrs,
954 struct ib_udata *udata);
955 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
956 int attr_mask, struct ib_udata *udata);
957 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
958 int attr_mask, struct ib_qp_init_attr *init_attr);
959 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
960 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
961 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
962 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
963 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
964 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
965 void c4iw_flush_hw_cq(struct c4iw_cq *cq);
966 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
967 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
968 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
969 int __c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
970 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
971 int c4iw_flush_sq(struct c4iw_qp *qhp);
972 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
973 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
974 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
975 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
976 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
977 struct c4iw_dev_ucontext *uctx);
978 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
979 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
980 struct c4iw_dev_ucontext *uctx);
981 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
982 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
983 enum t4_bar2_qtype qtype,
984 unsigned int *pbar2_qid, u64 *pbar2_pa);
985 extern struct cxgb4_client t4c_client;
986 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
988 #if defined(__i386__) || defined(__amd64__)
989 #define L1_CACHE_BYTES 128
991 #define L1_CACHE_BYTES 32
994 void your_reg_device(struct c4iw_dev *dev);
996 #define SGE_CTRLQ_NUM 0