2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
38 #include <linux/types.h>
39 #include <linux/kref.h>
40 #include <rdma/ib_umem.h>
41 #include <asm/atomic.h>
43 #include <common/t4_msg.h>
46 #define T4_ULPTX_MIN_IO 32
47 #define C4IW_MAX_INLINE_SIZE 96
50 write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
52 struct adapter *sc = rdev->adap;
53 struct ulp_mem_io *ulpmc;
54 struct ulptx_idata *ulpsc;
55 u8 wr_len, *to_dp, *from_dp;
56 int copy_len, num_wqe, i, ret = 0;
57 struct c4iw_wr_wait wr_wait;
61 cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE));
63 cmd |= cpu_to_be32(F_ULP_MEMIO_ORDER);
65 cmd |= cpu_to_be32(F_T5_ULP_MEMIO_IMM);
68 CTR3(KTR_IW_CXGBE, "%s addr 0x%x len %u", __func__, addr, len);
69 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
70 c4iw_init_wr_wait(&wr_wait);
71 for (i = 0; i < num_wqe; i++) {
73 copy_len = min(len, C4IW_MAX_INLINE_SIZE);
74 wr_len = roundup(sizeof *ulpmc + sizeof *ulpsc +
75 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
77 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq);
82 memset(ulpmc, 0, wr_len);
83 INIT_ULPTX_WR(ulpmc, wr_len, 0, 0);
85 if (i == (num_wqe-1)) {
86 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) |
88 ulpmc->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait;
90 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR));
91 ulpmc->wr.wr_mid = cpu_to_be32(
92 V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16)));
95 ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN(
96 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
97 ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr),
99 ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr + i * 3));
101 ulpsc = (struct ulptx_idata *)(ulpmc + 1);
102 ulpsc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
103 ulpsc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
105 to_dp = (u8 *)(ulpsc + 1);
106 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
108 memcpy(to_dp, from_dp, copy_len);
110 memset(to_dp, 0, copy_len);
111 if (copy_len % T4_ULPTX_MIN_IO)
112 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
113 (copy_len % T4_ULPTX_MIN_IO));
115 len -= C4IW_MAX_INLINE_SIZE;
118 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
123 * Build and write a TPT entry.
124 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size,
125 * pbl_size and pbl_addr
128 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
129 u32 *stag, u8 stag_state, u32 pdid,
130 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
131 int bind_enabled, u32 zbva, u64 to,
132 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr)
135 struct fw_ri_tpte tpt;
139 if (c4iw_fatal_error(rdev))
142 stag_state = stag_state > 0;
143 stag_idx = (*stag) >> 8;
145 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
146 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
149 mutex_lock(&rdev->stats.lock);
150 rdev->stats.stag.cur += 32;
151 if (rdev->stats.stag.cur > rdev->stats.stag.max)
152 rdev->stats.stag.max = rdev->stats.stag.cur;
153 mutex_unlock(&rdev->stats.lock);
154 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
157 "%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x",
158 __func__, stag_state, type, pdid, stag_idx);
160 /* write TPT entry */
162 memset(&tpt, 0, sizeof(tpt));
164 tpt.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID |
165 V_FW_RI_TPTE_STAGKEY((*stag & M_FW_RI_TPTE_STAGKEY)) |
166 V_FW_RI_TPTE_STAGSTATE(stag_state) |
167 V_FW_RI_TPTE_STAGTYPE(type) | V_FW_RI_TPTE_PDID(pdid));
168 tpt.locread_to_qpid = cpu_to_be32(V_FW_RI_TPTE_PERM(perm) |
169 (bind_enabled ? F_FW_RI_TPTE_MWBINDEN : 0) |
170 V_FW_RI_TPTE_ADDRTYPE((zbva ? FW_RI_ZERO_BASED_TO :
172 V_FW_RI_TPTE_PS(page_size));
173 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
174 V_FW_RI_TPTE_PBLADDR(PBL_OFF(rdev, pbl_addr)>>3));
175 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
176 tpt.va_hi = cpu_to_be32((u32)(to >> 32));
177 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
178 tpt.dca_mwbcnt_pstag = cpu_to_be32(0);
179 tpt.len_hi = cpu_to_be32((u32)(len >> 32));
181 err = write_adapter_mem(rdev, stag_idx +
182 (rdev->adap->vres.stag.start >> 5),
185 if (reset_tpt_entry) {
186 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
187 mutex_lock(&rdev->stats.lock);
188 rdev->stats.stag.cur -= 32;
189 mutex_unlock(&rdev->stats.lock);
194 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
195 u32 pbl_addr, u32 pbl_size)
199 CTR4(KTR_IW_CXGBE, "%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d",
200 __func__, pbl_addr, rdev->adap->vres.pbl.start, pbl_size);
202 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl);
206 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
209 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
213 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
215 *stag = T4_STAG_UNSET;
216 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
220 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag)
222 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
226 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
227 u32 pbl_size, u32 pbl_addr)
229 *stag = T4_STAG_UNSET;
230 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
231 0UL, 0, 0, pbl_size, pbl_addr);
234 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
239 mhp->attr.stag = stag;
241 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
242 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p", __func__, mmid, mhp);
243 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
246 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
247 struct c4iw_mr *mhp, int shift)
249 u32 stag = T4_STAG_UNSET;
252 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
253 FW_RI_STAG_NSMR, mhp->attr.perms,
254 mhp->attr.mw_bind_enable, mhp->attr.zbva,
255 mhp->attr.va_fbo, mhp->attr.len, shift - 12,
256 mhp->attr.pbl_size, mhp->attr.pbl_addr);
260 ret = finish_mem_reg(mhp, stag);
262 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
267 static int reregister_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
268 struct c4iw_mr *mhp, int shift, int npages)
273 if (npages > mhp->attr.pbl_size)
276 stag = mhp->attr.stag;
277 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
278 FW_RI_STAG_NSMR, mhp->attr.perms,
279 mhp->attr.mw_bind_enable, mhp->attr.zbva,
280 mhp->attr.va_fbo, mhp->attr.len, shift - 12,
281 mhp->attr.pbl_size, mhp->attr.pbl_addr);
285 ret = finish_mem_reg(mhp, stag);
287 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
293 static int alloc_pbl(struct c4iw_mr *mhp, int npages)
295 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
298 if (!mhp->attr.pbl_addr)
301 mhp->attr.pbl_size = npages;
306 static int build_phys_page_list(struct ib_phys_buf *buffer_list,
307 int num_phys_buf, u64 *iova_start,
308 u64 *total_size, int *npages,
309 int *shift, __be64 **page_list)
316 for (i = 0; i < num_phys_buf; ++i) {
317 if (i != 0 && buffer_list[i].addr & ~PAGE_MASK)
319 if (i != 0 && i != num_phys_buf - 1 &&
320 (buffer_list[i].size & ~PAGE_MASK))
322 *total_size += buffer_list[i].size;
324 mask |= buffer_list[i].addr;
326 mask |= buffer_list[i].addr & PAGE_MASK;
327 if (i != num_phys_buf - 1)
328 mask |= buffer_list[i].addr + buffer_list[i].size;
330 mask |= (buffer_list[i].addr + buffer_list[i].size +
331 PAGE_SIZE - 1) & PAGE_MASK;
334 if (*total_size > 0xFFFFFFFFULL)
337 /* Find largest page shift we can use to cover buffers */
338 for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift))
339 if ((1ULL << *shift) & mask)
342 buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1);
343 buffer_list[0].addr &= ~0ull << *shift;
346 for (i = 0; i < num_phys_buf; ++i)
347 *npages += (buffer_list[i].size +
348 (1ULL << *shift) - 1) >> *shift;
353 *page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL);
358 for (i = 0; i < num_phys_buf; ++i)
360 j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift;
362 (*page_list)[n++] = cpu_to_be64(buffer_list[i].addr +
363 ((u64) j << *shift));
366 "%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d", __func__,
367 (unsigned long long)*iova_start, (unsigned long long)mask, *shift,
368 (unsigned long long)*total_size, *npages);
374 int c4iw_reregister_phys_mem(struct ib_mr *mr, int mr_rereg_mask,
375 struct ib_pd *pd, struct ib_phys_buf *buffer_list,
376 int num_phys_buf, int acc, u64 *iova_start)
379 struct c4iw_mr mh, *mhp;
381 struct c4iw_dev *rhp;
382 __be64 *page_list = NULL;
388 CTR3(KTR_IW_CXGBE, "%s ib_mr %p ib_pd %p", __func__, mr, pd);
390 /* There can be no memory windows */
391 if (atomic_read(&mr->usecnt))
394 mhp = to_c4iw_mr(mr);
396 php = to_c4iw_pd(mr->pd);
398 /* make sure we are on the same adapter */
402 memcpy(&mh, mhp, sizeof *mhp);
404 if (mr_rereg_mask & IB_MR_REREG_PD)
405 php = to_c4iw_pd(pd);
406 if (mr_rereg_mask & IB_MR_REREG_ACCESS) {
407 mh.attr.perms = c4iw_ib_to_tpt_access(acc);
408 mh.attr.mw_bind_enable = (acc & IB_ACCESS_MW_BIND) ==
411 if (mr_rereg_mask & IB_MR_REREG_TRANS) {
412 ret = build_phys_page_list(buffer_list, num_phys_buf,
414 &total_size, &npages,
420 ret = reregister_mem(rhp, php, &mh, shift, npages);
424 if (mr_rereg_mask & IB_MR_REREG_PD)
425 mhp->attr.pdid = php->pdid;
426 if (mr_rereg_mask & IB_MR_REREG_ACCESS)
427 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
428 if (mr_rereg_mask & IB_MR_REREG_TRANS) {
430 mhp->attr.va_fbo = *iova_start;
431 mhp->attr.page_size = shift - 12;
432 mhp->attr.len = (u32) total_size;
433 mhp->attr.pbl_size = npages;
439 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
440 struct ib_phys_buf *buffer_list,
441 int num_phys_buf, int acc, u64 *iova_start)
447 struct c4iw_dev *rhp;
452 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
453 php = to_c4iw_pd(pd);
456 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
458 return ERR_PTR(-ENOMEM);
462 /* First check that we have enough alignment */
463 if ((*iova_start & ~PAGE_MASK) != (buffer_list[0].addr & ~PAGE_MASK)) {
468 if (num_phys_buf > 1 &&
469 ((buffer_list[0].addr + buffer_list[0].size) & ~PAGE_MASK)) {
474 ret = build_phys_page_list(buffer_list, num_phys_buf, iova_start,
475 &total_size, &npages, &shift,
480 ret = alloc_pbl(mhp, npages);
486 ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr,
492 mhp->attr.pdid = php->pdid;
495 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
496 mhp->attr.va_fbo = *iova_start;
497 mhp->attr.page_size = shift - 12;
499 mhp->attr.len = (u32) total_size;
500 mhp->attr.pbl_size = npages;
501 ret = register_mem(rhp, php, mhp, shift);
508 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
509 mhp->attr.pbl_size << 3);
517 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
519 struct c4iw_dev *rhp;
523 u32 stag = T4_STAG_UNSET;
525 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
526 php = to_c4iw_pd(pd);
529 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
531 return ERR_PTR(-ENOMEM);
534 mhp->attr.pdid = php->pdid;
535 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
536 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
538 mhp->attr.va_fbo = 0;
539 mhp->attr.page_size = 0;
540 mhp->attr.len = ~0UL;
541 mhp->attr.pbl_size = 0;
543 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
544 FW_RI_STAG_NSMR, mhp->attr.perms,
545 mhp->attr.mw_bind_enable, 0, 0, ~0UL, 0, 0, 0);
549 ret = finish_mem_reg(mhp, stag);
554 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
561 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
562 u64 virt, int acc, struct ib_udata *udata, int mr_id)
568 struct ib_umem_chunk *chunk;
569 struct c4iw_dev *rhp;
573 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
576 return ERR_PTR(-EINVAL);
578 if ((length + start) < start)
579 return ERR_PTR(-EINVAL);
581 php = to_c4iw_pd(pd);
583 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
585 return ERR_PTR(-ENOMEM);
589 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
590 if (IS_ERR(mhp->umem)) {
591 err = PTR_ERR(mhp->umem);
596 shift = ffs(mhp->umem->page_size) - 1;
599 list_for_each_entry(chunk, &mhp->umem->chunk_list, list)
602 err = alloc_pbl(mhp, n);
606 pages = (__be64 *) __get_free_page(GFP_KERNEL);
614 list_for_each_entry(chunk, &mhp->umem->chunk_list, list)
615 for (j = 0; j < chunk->nmap; ++j) {
616 len = sg_dma_len(&chunk->page_list[j]) >> shift;
617 for (k = 0; k < len; ++k) {
618 pages[i++] = cpu_to_be64(sg_dma_address(
619 &chunk->page_list[j]) +
620 mhp->umem->page_size * k);
621 if (i == PAGE_SIZE / sizeof *pages) {
622 err = write_pbl(&mhp->rhp->rdev,
624 mhp->attr.pbl_addr + (n << 3), i);
634 err = write_pbl(&mhp->rhp->rdev, pages,
635 mhp->attr.pbl_addr + (n << 3), i);
638 free_page((unsigned long) pages);
642 mhp->attr.pdid = php->pdid;
644 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
645 mhp->attr.va_fbo = virt;
646 mhp->attr.page_size = shift - 12;
647 mhp->attr.len = length;
649 err = register_mem(rhp, php, mhp, shift);
656 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
657 mhp->attr.pbl_size << 3);
660 ib_umem_release(mhp->umem);
665 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd)
667 struct c4iw_dev *rhp;
674 php = to_c4iw_pd(pd);
676 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
678 return ERR_PTR(-ENOMEM);
679 ret = allocate_window(&rhp->rdev, &stag, php->pdid);
685 mhp->attr.pdid = php->pdid;
686 mhp->attr.type = FW_RI_STAG_MW;
687 mhp->attr.stag = stag;
689 mhp->ibmw.rkey = stag;
690 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
691 deallocate_window(&rhp->rdev, mhp->attr.stag);
693 return ERR_PTR(-ENOMEM);
695 CTR4(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p stag 0x%x", __func__, mmid, mhp,
700 int c4iw_dealloc_mw(struct ib_mw *mw)
702 struct c4iw_dev *rhp;
706 mhp = to_c4iw_mw(mw);
708 mmid = (mw->rkey) >> 8;
709 remove_handle(rhp, &rhp->mmidr, mmid);
710 deallocate_window(&rhp->rdev, mhp->attr.stag);
712 CTR4(KTR_IW_CXGBE, "%s ib_mw %p mmid 0x%x ptr %p", __func__, mw, mmid,
717 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth)
719 struct c4iw_dev *rhp;
726 php = to_c4iw_pd(pd);
728 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
735 ret = alloc_pbl(mhp, pbl_depth);
738 mhp->attr.pbl_size = pbl_depth;
739 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
740 mhp->attr.pbl_size, mhp->attr.pbl_addr);
743 mhp->attr.pdid = php->pdid;
744 mhp->attr.type = FW_RI_STAG_NSMR;
745 mhp->attr.stag = stag;
748 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
749 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
754 CTR4(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p stag 0x%x", __func__, mmid, mhp,
758 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
761 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
762 mhp->attr.pbl_size << 3);
769 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device,
772 struct c4iw_fr_page_list *c4pl;
773 struct c4iw_dev *dev = to_c4iw_dev(device);
775 int size = sizeof *c4pl + page_list_len * sizeof(u64);
777 c4pl = contigmalloc(size,
778 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0);
780 dma_addr = vtophys(c4pl);
782 return ERR_PTR(-ENOMEM);;
784 pci_unmap_addr_set(c4pl, mapping, dma_addr);
785 c4pl->dma_addr = dma_addr;
788 c4pl->ibpl.page_list = (u64 *)(c4pl + 1);
789 c4pl->ibpl.max_page_list_len = page_list_len;
794 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl)
796 struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl);
797 contigfree(c4pl, c4pl->size, M_DEVBUF);
800 int c4iw_dereg_mr(struct ib_mr *ib_mr)
802 struct c4iw_dev *rhp;
806 CTR2(KTR_IW_CXGBE, "%s ib_mr %p", __func__, ib_mr);
807 /* There can be no memory windows */
808 if (atomic_read(&ib_mr->usecnt))
811 mhp = to_c4iw_mr(ib_mr);
813 mmid = mhp->attr.stag >> 8;
814 remove_handle(rhp, &rhp->mmidr, mmid);
815 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
817 if (mhp->attr.pbl_size)
818 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
819 mhp->attr.pbl_size << 3);
821 kfree((void *) (unsigned long) mhp->kva);
823 ib_umem_release(mhp->umem);
824 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x ptr %p", __func__, mmid, mhp);