sys/dev/cxgbe/iw_cxgbe/qp.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 #include "opt_inet.h"
  38
  39 #ifdef TCP_OFFLOAD
  40 #include <sys/types.h>
  41 #include <sys/malloc.h>
  42 #include <sys/socket.h>
  43 #include <sys/socketvar.h>
  44 #include <sys/sockio.h>
  45 #include <sys/taskqueue.h>
  46 #include <netinet/in.h>
  47 #include <net/route.h>
  48
  49 #include <netinet/in_systm.h>
  50 #include <netinet/in_pcb.h>
  51 #include <netinet/ip.h>
  52 #include <netinet/ip_var.h>
  53 #include <netinet/tcp_var.h>
  54 #include <netinet/tcp.h>
  55 #include <netinet/tcpip.h>
  56
  57 #include <netinet/toecore.h>
  58
  59 struct sge_iq;
  60 struct rss_header;
  61 struct cpl_set_tcb_rpl;
  62 #include <linux/types.h>
  63 #include "offload.h"
  64 #include "tom/t4_tom.h"
  65
  66 #include "iw_cxgbe.h"
  67 #include "user.h"
  68
  69 static int creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize);
  70 static int max_fr_immd = T4_MAX_FR_IMMD;//SYSCTL parameter later...
  71
  72 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
  73 {
  74         int ret = 0;
  75
  76         spin_lock_irq(&dev->lock);
  77         if (ird <= dev->avail_ird)
  78                 dev->avail_ird -= ird;
  79         else
  80                 ret = -ENOMEM;
  81         spin_unlock_irq(&dev->lock);
  82
  83         if (ret)
  84                 log(LOG_WARNING, "%s: device IRD resources exhausted\n",
  85                         device_get_nameunit(dev->rdev.adap->dev));
  86
  87         return ret;
  88 }
  89
  90 static void free_ird(struct c4iw_dev *dev, int ird)
  91 {
  92         spin_lock_irq(&dev->lock);
  93         dev->avail_ird += ird;
  94         spin_unlock_irq(&dev->lock);
  95 }
  96
  97 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  98 {
  99         unsigned long flag;
 100         spin_lock_irqsave(&qhp->lock, flag);
 101         qhp->attr.state = state;
 102         spin_unlock_irqrestore(&qhp->lock, flag);
 103 }
 104
 105 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 106                       struct c4iw_dev_ucontext *uctx)
 107 {
 108         struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev);
 109         /*
 110          * uP clears EQ contexts when the connection exits rdma mode,
 111          * so no need to post a RESET WR for these EQs.
 112          */
 113         dma_free_coherent(rhp->ibdev.dma_device,
 114                         wq->rq.memsize, wq->rq.queue,
 115                         dma_unmap_addr(&wq->rq, mapping));
 116         dma_free_coherent(rhp->ibdev.dma_device,
 117                         wq->sq.memsize, wq->sq.queue,
 118                         dma_unmap_addr(&wq->sq, mapping));
 119         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 120         kfree(wq->rq.sw_rq);
 121         kfree(wq->sq.sw_sq);
 122         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 123         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 124         return 0;
 125 }
 126
 127 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 128                      struct t4_cq *rcq, struct t4_cq *scq,
 129                      struct c4iw_dev_ucontext *uctx)
 130 {
 131         struct adapter *sc = rdev->adap;
 132         struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev);
 133         int user = (uctx != &rdev->uctx);
 134         struct fw_ri_res_wr *res_wr;
 135         struct fw_ri_res *res;
 136         int wr_len;
 137         struct c4iw_wr_wait wr_wait;
 138         int ret = 0;
 139         int eqsize;
 140         struct wrqe *wr;
 141         u64 sq_bar2_qoffset = 0, rq_bar2_qoffset = 0;
 142
 143         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 144         if (!wq->sq.qid)
 145                 return -ENOMEM;
 146
 147         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 148         if (!wq->rq.qid) {
 149                 ret = -ENOMEM;
 150                 goto free_sq_qid;
 151         }
 152
 153         if (!user) {
 154                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 155                                  GFP_KERNEL);
 156                 if (!wq->sq.sw_sq) {
 157                         ret = -ENOMEM;
 158                         goto free_rq_qid;
 159                 }
 160
 161                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 162                                  GFP_KERNEL);
 163                 if (!wq->rq.sw_rq) {
 164                         ret = -ENOMEM;
 165                         goto free_sw_sq;
 166                 }
 167         }
 168
 169         /*
 170          * RQT must be a power of 2 and at least 16 deep.
 171          */
 172         wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
 173         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 174         if (!wq->rq.rqt_hwaddr) {
 175                 ret = -ENOMEM;
 176                 goto free_sw_rq;
 177         }
 178
 179         /*QP memory, allocate DMAable memory for Send & Receive Queues */
 180         wq->sq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, wq->sq.memsize,
 181                                        &(wq->sq.dma_addr), GFP_KERNEL);
 182         if (!wq->sq.queue) {
 183                 ret = -ENOMEM;
 184                 goto free_hwaddr;
 185         }
 186         wq->sq.phys_addr = vtophys(wq->sq.queue);
 187         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 188         memset(wq->sq.queue, 0, wq->sq.memsize);
 189
 190         wq->rq.queue = dma_alloc_coherent(rhp->ibdev.dma_device,
 191                         wq->rq.memsize, &(wq->rq.dma_addr), GFP_KERNEL);
 192         if (!wq->rq.queue) {
 193                 ret = -ENOMEM;
 194                 goto free_sq_dma;
 195         }
 196         wq->rq.phys_addr = vtophys(wq->rq.queue);
 197         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 198         memset(wq->rq.queue, 0, wq->rq.memsize);
 199
 200         CTR5(KTR_IW_CXGBE,
 201             "%s QP sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx",
 202             __func__,
 203             wq->sq.queue, (unsigned long long)wq->sq.phys_addr,
 204             wq->rq.queue, (unsigned long long)wq->rq.phys_addr);
 205
 206         /* Doorbell/WC regions, determine the BAR2 queue offset and qid. */
 207         t4_bar2_sge_qregs(rdev->adap, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, user,
 208                         &sq_bar2_qoffset, &wq->sq.bar2_qid);
 209         t4_bar2_sge_qregs(rdev->adap, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, user,
 210                         &rq_bar2_qoffset, &wq->rq.bar2_qid);
 211
 212         if (user) {
 213                 /* Compute BAR2 DB/WC physical address(page-aligned) for
 214                  * Userspace mapping.
 215                  */
 216                 wq->sq.bar2_pa = (rdev->bar2_pa + sq_bar2_qoffset) & PAGE_MASK;
 217                 wq->rq.bar2_pa = (rdev->bar2_pa + rq_bar2_qoffset) & PAGE_MASK;
 218                 CTR3(KTR_IW_CXGBE,
 219                         "%s BAR2 DB/WC sq base pa 0x%llx rq base pa 0x%llx",
 220                         __func__, (unsigned long long)wq->sq.bar2_pa,
 221                         (unsigned long long)wq->rq.bar2_pa);
 222         } else {
 223                 /* Compute BAR2 DB/WC virtual address to access in kernel. */
 224                 wq->sq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
 225                                 sq_bar2_qoffset);
 226                 wq->rq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
 227                                 rq_bar2_qoffset);
 228                 CTR3(KTR_IW_CXGBE, "%s BAR2 DB/WC sq base va %p rq base va %p",
 229                         __func__, (unsigned long long)wq->sq.bar2_va,
 230                         (unsigned long long)wq->rq.bar2_va);
 231         }
 232
 233         wq->rdev = rdev;
 234         wq->rq.msn = 1;
 235
 236         /* build fw_ri_res_wr */
 237         wr_len = sizeof *res_wr + 2 * sizeof *res;
 238
 239         wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]);
 240         if (wr == NULL) {
 241                 ret = -ENOMEM;
 242                 goto free_rq_dma;
 243         }
 244         res_wr = wrtod(wr);
 245
 246         memset(res_wr, 0, wr_len);
 247         res_wr->op_nres = cpu_to_be32(
 248                         V_FW_WR_OP(FW_RI_RES_WR) |
 249                         V_FW_RI_RES_WR_NRES(2) |
 250                         F_FW_WR_COMPL);
 251         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 252         res_wr->cookie = (unsigned long) &wr_wait;
 253         res = res_wr->res;
 254         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 255         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 256
 257         /* eqsize is the number of 64B entries plus the status page size. */
 258         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
 259                         rdev->hw_queue.t4_eq_status_entries;
 260
 261         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 262                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 263                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 264                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 265                 V_FW_RI_RES_WR_IQID(scq->cqid));
 266         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 267                 V_FW_RI_RES_WR_DCAEN(0) |
 268                 V_FW_RI_RES_WR_DCACPU(0) |
 269                 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
 270                     X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
 271                 V_FW_RI_RES_WR_FBMAX(3) |
 272                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 273                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 274                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 275         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 276         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 277         res++;
 278         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 279         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 280
 281         /* eqsize is the number of 64B entries plus the status page size. */
 282         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
 283                         rdev->hw_queue.t4_eq_status_entries;
 284         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 285                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 286                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 287                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 288                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 289         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 290                 V_FW_RI_RES_WR_DCAEN(0) |
 291                 V_FW_RI_RES_WR_DCACPU(0) |
 292                 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
 293                     X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
 294                 V_FW_RI_RES_WR_FBMAX(3) |
 295                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 296                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 297                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 298         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 299         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 300
 301         c4iw_init_wr_wait(&wr_wait);
 302
 303         t4_wrq_tx(sc, wr);
 304         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid,
 305                         NULL, __func__);
 306         if (ret)
 307                 goto free_rq_dma;
 308
 309         CTR5(KTR_IW_CXGBE,
 310             "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx",
 311             __func__, wq->sq.qid, wq->rq.qid,
 312             (unsigned long long)wq->sq.bar2_va,
 313             (unsigned long long)wq->rq.bar2_va);
 314
 315         return 0;
 316 free_rq_dma:
 317         dma_free_coherent(rhp->ibdev.dma_device,
 318                           wq->rq.memsize, wq->rq.queue,
 319                           dma_unmap_addr(&wq->rq, mapping));
 320 free_sq_dma:
 321         dma_free_coherent(rhp->ibdev.dma_device,
 322                           wq->sq.memsize, wq->sq.queue,
 323                           dma_unmap_addr(&wq->sq, mapping));
 324 free_hwaddr:
 325         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 326 free_sw_rq:
 327         kfree(wq->rq.sw_rq);
 328 free_sw_sq:
 329         kfree(wq->sq.sw_sq);
 330 free_rq_qid:
 331         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 332 free_sq_qid:
 333         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 334         return ret;
 335 }
 336
 337 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 338                       struct ib_send_wr *wr, int max, u32 *plenp)
 339 {
 340         u8 *dstp, *srcp;
 341         u32 plen = 0;
 342         int i;
 343         int rem, len;
 344
 345         dstp = (u8 *)immdp->data;
 346         for (i = 0; i < wr->num_sge; i++) {
 347                 if ((plen + wr->sg_list[i].length) > max)
 348                         return -EMSGSIZE;
 349                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 350                 plen += wr->sg_list[i].length;
 351                 rem = wr->sg_list[i].length;
 352                 while (rem) {
 353                         if (dstp == (u8 *)&sq->queue[sq->size])
 354                                 dstp = (u8 *)sq->queue;
 355                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 356                                 len = rem;
 357                         else
 358                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 359                         memcpy(dstp, srcp, len);
 360                         dstp += len;
 361                         srcp += len;
 362                         rem -= len;
 363                 }
 364         }
 365         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 366         if (len)
 367                 memset(dstp, 0, len);
 368         immdp->op = FW_RI_DATA_IMMD;
 369         immdp->r1 = 0;
 370         immdp->r2 = 0;
 371         immdp->immdlen = cpu_to_be32(plen);
 372         *plenp = plen;
 373         return 0;
 374 }
 375
 376 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 377                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 378                       int num_sge, u32 *plenp)
 379
 380 {
 381         int i;
 382         u32 plen = 0;
 383         __be64 *flitp = (__be64 *)isglp->sge;
 384
 385         for (i = 0; i < num_sge; i++) {
 386                 if ((plen + sg_list[i].length) < plen)
 387                         return -EMSGSIZE;
 388                 plen += sg_list[i].length;
 389                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 390                                      sg_list[i].length);
 391                 if (++flitp == queue_end)
 392                         flitp = queue_start;
 393                 *flitp = cpu_to_be64(sg_list[i].addr);
 394                 if (++flitp == queue_end)
 395                         flitp = queue_start;
 396         }
 397         *flitp = (__force __be64)0;
 398         isglp->op = FW_RI_DATA_ISGL;
 399         isglp->r1 = 0;
 400         isglp->nsge = cpu_to_be16(num_sge);
 401         isglp->r2 = 0;
 402         if (plenp)
 403                 *plenp = plen;
 404         return 0;
 405 }
 406
 407 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 408                            struct ib_send_wr *wr, u8 *len16)
 409 {
 410         u32 plen;
 411         int size;
 412         int ret;
 413
 414         if (wr->num_sge > T4_MAX_SEND_SGE)
 415                 return -EINVAL;
 416         switch (wr->opcode) {
 417         case IB_WR_SEND:
 418                 if (wr->send_flags & IB_SEND_SOLICITED)
 419                         wqe->send.sendop_pkd = cpu_to_be32(
 420                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 421                 else
 422                         wqe->send.sendop_pkd = cpu_to_be32(
 423                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 424                 wqe->send.stag_inv = 0;
 425                 break;
 426         case IB_WR_SEND_WITH_INV:
 427                 if (wr->send_flags & IB_SEND_SOLICITED)
 428                         wqe->send.sendop_pkd = cpu_to_be32(
 429                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 430                 else
 431                         wqe->send.sendop_pkd = cpu_to_be32(
 432                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 433                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 434                 break;
 435
 436         default:
 437                 return -EINVAL;
 438         }
 439         wqe->send.r3 = 0;
 440         wqe->send.r4 = 0;
 441
 442         plen = 0;
 443         if (wr->num_sge) {
 444                 if (wr->send_flags & IB_SEND_INLINE) {
 445                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 446                                          T4_MAX_SEND_INLINE, &plen);
 447                         if (ret)
 448                                 return ret;
 449                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 450                                plen;
 451                 } else {
 452                         ret = build_isgl((__be64 *)sq->queue,
 453                                          (__be64 *)&sq->queue[sq->size],
 454                                          wqe->send.u.isgl_src,
 455                                          wr->sg_list, wr->num_sge, &plen);
 456                         if (ret)
 457                                 return ret;
 458                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 459                                wr->num_sge * sizeof(struct fw_ri_sge);
 460                 }
 461         } else {
 462                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 463                 wqe->send.u.immd_src[0].r1 = 0;
 464                 wqe->send.u.immd_src[0].r2 = 0;
 465                 wqe->send.u.immd_src[0].immdlen = 0;
 466                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 467                 plen = 0;
 468         }
 469         *len16 = DIV_ROUND_UP(size, 16);
 470         wqe->send.plen = cpu_to_be32(plen);
 471         return 0;
 472 }
 473
 474 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 475                             struct ib_send_wr *wr, u8 *len16)
 476 {
 477         u32 plen;
 478         int size;
 479         int ret;
 480
 481         if (wr->num_sge > T4_MAX_SEND_SGE)
 482                 return -EINVAL;
 483         wqe->write.immd_data = 0;
 484         wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
 485         wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
 486         if (wr->num_sge) {
 487                 if (wr->send_flags & IB_SEND_INLINE) {
 488                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 489                                          T4_MAX_WRITE_INLINE, &plen);
 490                         if (ret)
 491                                 return ret;
 492                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 493                                plen;
 494                 } else {
 495                         ret = build_isgl((__be64 *)sq->queue,
 496                                          (__be64 *)&sq->queue[sq->size],
 497                                          wqe->write.u.isgl_src,
 498                                          wr->sg_list, wr->num_sge, &plen);
 499                         if (ret)
 500                                 return ret;
 501                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 502                                wr->num_sge * sizeof(struct fw_ri_sge);
 503                 }
 504         } else {
 505                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 506                 wqe->write.u.immd_src[0].r1 = 0;
 507                 wqe->write.u.immd_src[0].r2 = 0;
 508                 wqe->write.u.immd_src[0].immdlen = 0;
 509                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 510                 plen = 0;
 511         }
 512         *len16 = DIV_ROUND_UP(size, 16);
 513         wqe->write.plen = cpu_to_be32(plen);
 514         return 0;
 515 }
 516
 517 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 518 {
 519         if (wr->num_sge > 1)
 520                 return -EINVAL;
 521         if (wr->num_sge && wr->sg_list[0].length) {
 522                 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
 523                 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
 524                                                         >> 32));
 525                 wqe->read.to_src_lo =
 526                         cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
 527                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 528                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 529                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 530                                                          >> 32));
 531                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 532         } else {
 533                 wqe->read.stag_src = cpu_to_be32(2);
 534                 wqe->read.to_src_hi = 0;
 535                 wqe->read.to_src_lo = 0;
 536                 wqe->read.stag_sink = cpu_to_be32(2);
 537                 wqe->read.plen = 0;
 538                 wqe->read.to_sink_hi = 0;
 539                 wqe->read.to_sink_lo = 0;
 540         }
 541         wqe->read.r2 = 0;
 542         wqe->read.r5 = 0;
 543         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 544         return 0;
 545 }
 546
 547 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 548                            struct ib_recv_wr *wr, u8 *len16)
 549 {
 550         int ret;
 551
 552         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 553                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 554                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 555         if (ret)
 556                 return ret;
 557         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 558                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 559         return 0;
 560 }
 561
 562 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 563                           u8 *len16)
 564 {
 565         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 566         wqe->inv.r2 = 0;
 567         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 568         return 0;
 569 }
 570
 571 static void free_qp_work(struct work_struct *work)
 572 {
 573         struct c4iw_ucontext *ucontext;
 574         struct c4iw_qp *qhp;
 575         struct c4iw_dev *rhp;
 576
 577         qhp = container_of(work, struct c4iw_qp, free_work);
 578         ucontext = qhp->ucontext;
 579         rhp = qhp->rhp;
 580
 581         CTR3(KTR_IW_CXGBE, "%s qhp %p ucontext %p", __func__,
 582                         qhp, ucontext);
 583         destroy_qp(&rhp->rdev, &qhp->wq,
 584                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
 585
 586         if (ucontext)
 587                 c4iw_put_ucontext(ucontext);
 588         kfree(qhp);
 589 }
 590
 591 static void queue_qp_free(struct kref *kref)
 592 {
 593         struct c4iw_qp *qhp;
 594
 595         qhp = container_of(kref, struct c4iw_qp, kref);
 596         CTR2(KTR_IW_CXGBE, "%s qhp %p", __func__, qhp);
 597         queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
 598 }
 599
 600 void c4iw_qp_add_ref(struct ib_qp *qp)
 601 {
 602         CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
 603         kref_get(&to_c4iw_qp(qp)->kref);
 604 }
 605
 606 void c4iw_qp_rem_ref(struct ib_qp *qp)
 607 {
 608         CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
 609         kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
 610 }
 611
 612 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
 613 {
 614         struct t4_cqe cqe = {};
 615         struct c4iw_cq *schp;
 616         unsigned long flag;
 617         struct t4_cq *cq;
 618
 619         schp = to_c4iw_cq(qhp->ibqp.send_cq);
 620         cq = &schp->cq;
 621
 622         PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid);
 623         cqe.u.drain_cookie = wr->wr_id;
 624         cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
 625                                  V_CQE_OPCODE(C4IW_DRAIN_OPCODE) |
 626                                  V_CQE_TYPE(1) |
 627                                  V_CQE_SWCQE(1) |
 628                                  V_CQE_QPID(qhp->wq.sq.qid));
 629
 630         spin_lock_irqsave(&schp->lock, flag);
 631         cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
 632         cq->sw_queue[cq->sw_pidx] = cqe;
 633         t4_swcq_produce(cq);
 634         spin_unlock_irqrestore(&schp->lock, flag);
 635
 636         spin_lock_irqsave(&schp->comp_handler_lock, flag);
 637         (*schp->ibcq.comp_handler)(&schp->ibcq,
 638                                    schp->ibcq.cq_context);
 639         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
 640 }
 641
 642 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
 643 {
 644         struct t4_cqe cqe = {};
 645         struct c4iw_cq *rchp;
 646         unsigned long flag;
 647         struct t4_cq *cq;
 648
 649         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
 650         cq = &rchp->cq;
 651
 652         PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid);
 653         cqe.u.drain_cookie = wr->wr_id;
 654         cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
 655                                  V_CQE_OPCODE(C4IW_DRAIN_OPCODE) |
 656                                  V_CQE_TYPE(0) |
 657                                  V_CQE_SWCQE(1) |
 658                                  V_CQE_QPID(qhp->wq.sq.qid));
 659
 660         spin_lock_irqsave(&rchp->lock, flag);
 661         cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
 662         cq->sw_queue[cq->sw_pidx] = cqe;
 663         t4_swcq_produce(cq);
 664         spin_unlock_irqrestore(&rchp->lock, flag);
 665
 666         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 667         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
 668                                    rchp->ibcq.cq_context);
 669         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 670 }
 671
 672 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
 673                 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16)
 674 {
 675         __be64 *p = (__be64 *)fr->pbl;
 676
 677         fr->r2 = cpu_to_be32(0);
 678         fr->stag = cpu_to_be32(mhp->ibmr.rkey);
 679
 680         fr->tpte.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID |
 681                         V_FW_RI_TPTE_STAGKEY((mhp->ibmr.rkey & M_FW_RI_TPTE_STAGKEY)) |
 682                         V_FW_RI_TPTE_STAGSTATE(1) |
 683                         V_FW_RI_TPTE_STAGTYPE(FW_RI_STAG_NSMR) |
 684                         V_FW_RI_TPTE_PDID(mhp->attr.pdid));
 685         fr->tpte.locread_to_qpid = cpu_to_be32(
 686                         V_FW_RI_TPTE_PERM(c4iw_ib_to_tpt_access(wr->access)) |
 687                         V_FW_RI_TPTE_ADDRTYPE(FW_RI_VA_BASED_TO) |
 688                         V_FW_RI_TPTE_PS(ilog2(wr->mr->page_size) - 12));
 689         fr->tpte.nosnoop_pbladdr = cpu_to_be32(V_FW_RI_TPTE_PBLADDR(
 690                               PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
 691         fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
 692         fr->tpte.len_hi = cpu_to_be32(0);
 693         fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
 694         fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 695         fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
 696
 697         p[0] = cpu_to_be64((u64)mhp->mpl[0]);
 698         p[1] = cpu_to_be64((u64)mhp->mpl[1]);
 699
 700         *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
 701 }
 702
 703 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
 704                 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
 705                 bool dsgl_supported)
 706 {
 707         struct fw_ri_immd *imdp;
 708         __be64 *p;
 709         int i;
 710         int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
 711         int rem;
 712
 713         if (mhp->mpl_len > t4_max_fr_depth(use_dsgl && dsgl_supported))
 714                 return -EINVAL;
 715
 716         wqe->fr.qpbinde_to_dcacpu = 0;
 717         wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
 718         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 719         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
 720         wqe->fr.len_hi = 0;
 721         wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
 722         wqe->fr.stag = cpu_to_be32(wr->key);
 723         wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 724         wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
 725                         0xffffffff);
 726
 727         if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
 728                 struct fw_ri_dsgl *sglp;
 729
 730                 for (i = 0; i < mhp->mpl_len; i++)
 731                         mhp->mpl[i] =
 732                                      (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
 733
 734                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 735                 sglp->op = FW_RI_DATA_DSGL;
 736                 sglp->r1 = 0;
 737                 sglp->nsge = cpu_to_be16(1);
 738                 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
 739                 sglp->len0 = cpu_to_be32(pbllen);
 740
 741                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 742         } else {
 743                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 744                 imdp->op = FW_RI_DATA_IMMD;
 745                 imdp->r1 = 0;
 746                 imdp->r2 = 0;
 747                 imdp->immdlen = cpu_to_be32(pbllen);
 748                 p = (__be64 *)(imdp + 1);
 749                 rem = pbllen;
 750                 for (i = 0; i < mhp->mpl_len; i++) {
 751                         *p = cpu_to_be64((u64)mhp->mpl[i]);
 752                         rem -= sizeof(*p);
 753                         if (++p == (__be64 *)&sq->queue[sq->size])
 754                                 p = (__be64 *)sq->queue;
 755                 }
 756                 BUG_ON(rem < 0);
 757                 while (rem) {
 758                         *p = 0;
 759                         rem -= sizeof(*p);
 760                         if (++p == (__be64 *)&sq->queue[sq->size])
 761                                 p = (__be64 *)sq->queue;
 762                 }
 763                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 764                                 + pbllen, 16);
 765         }
 766
 767         return 0;
 768 }
 769
 770 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 771                    struct ib_send_wr **bad_wr)
 772 {
 773         int err = 0;
 774         u8 len16 = 0;
 775         enum fw_wr_opcodes fw_opcode = 0;
 776         enum fw_ri_wr_flags fw_flags;
 777         struct c4iw_qp *qhp;
 778         union t4_wr *wqe = NULL;
 779         u32 num_wrs;
 780         struct t4_swsqe *swsqe;
 781         unsigned long flag;
 782         u16 idx = 0;
 783         struct c4iw_rdev *rdev;
 784
 785         qhp = to_c4iw_qp(ibqp);
 786         rdev = &qhp->rhp->rdev;
 787         spin_lock_irqsave(&qhp->lock, flag);
 788         if (t4_wq_in_error(&qhp->wq)) {
 789                 spin_unlock_irqrestore(&qhp->lock, flag);
 790                 complete_sq_drain_wr(qhp, wr);
 791                 return err;
 792         }
 793         num_wrs = t4_sq_avail(&qhp->wq);
 794         if (num_wrs == 0) {
 795                 spin_unlock_irqrestore(&qhp->lock, flag);
 796                 *bad_wr = wr;
 797                 return -ENOMEM;
 798         }
 799         while (wr) {
 800                 if (num_wrs == 0) {
 801                         err = -ENOMEM;
 802                         *bad_wr = wr;
 803                         break;
 804                 }
 805                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 806                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 807
 808                 fw_flags = 0;
 809                 if (wr->send_flags & IB_SEND_SOLICITED)
 810                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 811                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
 812                         fw_flags |= FW_RI_COMPLETION_FLAG;
 813                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 814                 switch (wr->opcode) {
 815                 case IB_WR_SEND_WITH_INV:
 816                 case IB_WR_SEND:
 817                         if (wr->send_flags & IB_SEND_FENCE)
 818                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 819                         fw_opcode = FW_RI_SEND_WR;
 820                         if (wr->opcode == IB_WR_SEND)
 821                                 swsqe->opcode = FW_RI_SEND;
 822                         else
 823                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 824                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 825                         break;
 826                 case IB_WR_RDMA_WRITE:
 827                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 828                         swsqe->opcode = FW_RI_RDMA_WRITE;
 829                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 830                         break;
 831                 case IB_WR_RDMA_READ:
 832                 case IB_WR_RDMA_READ_WITH_INV:
 833                         fw_opcode = FW_RI_RDMA_READ_WR;
 834                         swsqe->opcode = FW_RI_READ_REQ;
 835                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
 836                                 c4iw_invalidate_mr(qhp->rhp,
 837                                                    wr->sg_list[0].lkey);
 838                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 839                         } else {
 840                                 fw_flags = 0;
 841                         }
 842                         err = build_rdma_read(wqe, wr, &len16);
 843                         if (err)
 844                                 break;
 845                         swsqe->read_len = wr->sg_list[0].length;
 846                         if (!qhp->wq.sq.oldest_read)
 847                                 qhp->wq.sq.oldest_read = swsqe;
 848                         break;
 849                 case IB_WR_REG_MR: {
 850                         struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
 851
 852                         swsqe->opcode = FW_RI_FAST_REGISTER;
 853                         if (rdev->adap->params.fr_nsmr_tpte_wr_support &&
 854                                         !mhp->attr.state && mhp->mpl_len <= 2) {
 855                                 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
 856                                 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
 857                                                 mhp, &len16);
 858                         } else {
 859                                 fw_opcode = FW_RI_FR_NSMR_WR;
 860                                 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
 861                                         mhp, &len16,
 862                                         rdev->adap->params.ulptx_memwrite_dsgl);
 863                                 if (err)
 864                                         break;
 865                         }
 866                         mhp->attr.state = 1;
 867                         break;
 868                 }
 869                 case IB_WR_LOCAL_INV:
 870                         if (wr->send_flags & IB_SEND_FENCE)
 871                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 872                         fw_opcode = FW_RI_INV_LSTAG_WR;
 873                         swsqe->opcode = FW_RI_LOCAL_INV;
 874                         err = build_inv_stag(wqe, wr, &len16);
 875                         c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
 876                         break;
 877                 default:
 878                         CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__,
 879                              wr->opcode);
 880                         err = -EINVAL;
 881                 }
 882                 if (err) {
 883                         *bad_wr = wr;
 884                         break;
 885                 }
 886                 swsqe->idx = qhp->wq.sq.pidx;
 887                 swsqe->complete = 0;
 888                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
 889                                         qhp->sq_sig_all;
 890                 swsqe->flushed = 0;
 891                 swsqe->wr_id = wr->wr_id;
 892
 893                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 894
 895                 CTR5(KTR_IW_CXGBE,
 896                     "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u",
 897                     __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 898                     swsqe->opcode, swsqe->read_len);
 899                 wr = wr->next;
 900                 num_wrs--;
 901                 t4_sq_produce(&qhp->wq, len16);
 902                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 903         }
 904
 905         t4_ring_sq_db(&qhp->wq, idx, wqe, rdev->adap->iwt.wc_en);
 906         spin_unlock_irqrestore(&qhp->lock, flag);
 907         return err;
 908 }
 909
 910 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 911                       struct ib_recv_wr **bad_wr)
 912 {
 913         int err = 0;
 914         struct c4iw_qp *qhp;
 915         union t4_recv_wr *wqe = NULL;
 916         u32 num_wrs;
 917         u8 len16 = 0;
 918         unsigned long flag;
 919         u16 idx = 0;
 920
 921         qhp = to_c4iw_qp(ibqp);
 922         spin_lock_irqsave(&qhp->lock, flag);
 923         if (t4_wq_in_error(&qhp->wq)) {
 924                 spin_unlock_irqrestore(&qhp->lock, flag);
 925                 complete_rq_drain_wr(qhp, wr);
 926                 return err;
 927         }
 928         num_wrs = t4_rq_avail(&qhp->wq);
 929         if (num_wrs == 0) {
 930                 spin_unlock_irqrestore(&qhp->lock, flag);
 931                 *bad_wr = wr;
 932                 return -ENOMEM;
 933         }
 934         while (wr) {
 935                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 936                         err = -EINVAL;
 937                         *bad_wr = wr;
 938                         break;
 939                 }
 940                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 941                                            qhp->wq.rq.wq_pidx *
 942                                            T4_EQ_ENTRY_SIZE);
 943                 if (num_wrs)
 944                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 945                 else
 946                         err = -ENOMEM;
 947                 if (err) {
 948                         *bad_wr = wr;
 949                         break;
 950                 }
 951
 952                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 953
 954                 wqe->recv.opcode = FW_RI_RECV_WR;
 955                 wqe->recv.r1 = 0;
 956                 wqe->recv.wrid = qhp->wq.rq.pidx;
 957                 wqe->recv.r2[0] = 0;
 958                 wqe->recv.r2[1] = 0;
 959                 wqe->recv.r2[2] = 0;
 960                 wqe->recv.len16 = len16;
 961                 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__,
 962                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 963                 t4_rq_produce(&qhp->wq, len16);
 964                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 965                 wr = wr->next;
 966                 num_wrs--;
 967         }
 968
 969         t4_ring_rq_db(&qhp->wq, idx, wqe, qhp->rhp->rdev.adap->iwt.wc_en);
 970         spin_unlock_irqrestore(&qhp->lock, flag);
 971         return err;
 972 }
 973
 974 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 975                                     u8 *ecode)
 976 {
 977         int status;
 978         int tagged;
 979         int opcode;
 980         int rqtype;
 981         int send_inv;
 982
 983         if (!err_cqe) {
 984                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 985                 *ecode = 0;
 986                 return;
 987         }
 988
 989         status = CQE_STATUS(err_cqe);
 990         opcode = CQE_OPCODE(err_cqe);
 991         rqtype = RQ_TYPE(err_cqe);
 992         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 993                    (opcode == FW_RI_SEND_WITH_SE_INV);
 994         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 995                  (rqtype && (opcode == FW_RI_READ_RESP));
 996
 997         switch (status) {
 998         case T4_ERR_STAG:
 999                 if (send_inv) {
1000                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1001                         *ecode = RDMAP_CANT_INV_STAG;
1002                 } else {
1003                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1004                         *ecode = RDMAP_INV_STAG;
1005                 }
1006                 break;
1007         case T4_ERR_PDID:
1008                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1009                 if ((opcode == FW_RI_SEND_WITH_INV) ||
1010                     (opcode == FW_RI_SEND_WITH_SE_INV))
1011                         *ecode = RDMAP_CANT_INV_STAG;
1012                 else
1013                         *ecode = RDMAP_STAG_NOT_ASSOC;
1014                 break;
1015         case T4_ERR_QPID:
1016                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1017                 *ecode = RDMAP_STAG_NOT_ASSOC;
1018                 break;
1019         case T4_ERR_ACCESS:
1020                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1021                 *ecode = RDMAP_ACC_VIOL;
1022                 break;
1023         case T4_ERR_WRAP:
1024                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1025                 *ecode = RDMAP_TO_WRAP;
1026                 break;
1027         case T4_ERR_BOUND:
1028                 if (tagged) {
1029                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1030                         *ecode = DDPT_BASE_BOUNDS;
1031                 } else {
1032                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1033                         *ecode = RDMAP_BASE_BOUNDS;
1034                 }
1035                 break;
1036         case T4_ERR_INVALIDATE_SHARED_MR:
1037         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1038                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1039                 *ecode = RDMAP_CANT_INV_STAG;
1040                 break;
1041         case T4_ERR_ECC:
1042         case T4_ERR_ECC_PSTAG:
1043         case T4_ERR_INTERNAL_ERR:
1044                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1045                 *ecode = 0;
1046                 break;
1047         case T4_ERR_OUT_OF_RQE:
1048                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1049                 *ecode = DDPU_INV_MSN_NOBUF;
1050                 break;
1051         case T4_ERR_PBL_ADDR_BOUND:
1052                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1053                 *ecode = DDPT_BASE_BOUNDS;
1054                 break;
1055         case T4_ERR_CRC:
1056                 *layer_type = LAYER_MPA|DDP_LLP;
1057                 *ecode = MPA_CRC_ERR;
1058                 break;
1059         case T4_ERR_MARKER:
1060                 *layer_type = LAYER_MPA|DDP_LLP;
1061                 *ecode = MPA_MARKER_ERR;
1062                 break;
1063         case T4_ERR_PDU_LEN_ERR:
1064                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1065                 *ecode = DDPU_MSG_TOOBIG;
1066                 break;
1067         case T4_ERR_DDP_VERSION:
1068                 if (tagged) {
1069                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1070                         *ecode = DDPT_INV_VERS;
1071                 } else {
1072                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1073                         *ecode = DDPU_INV_VERS;
1074                 }
1075                 break;
1076         case T4_ERR_RDMA_VERSION:
1077                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1078                 *ecode = RDMAP_INV_VERS;
1079                 break;
1080         case T4_ERR_OPCODE:
1081                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1082                 *ecode = RDMAP_INV_OPCODE;
1083                 break;
1084         case T4_ERR_DDP_QUEUE_NUM:
1085                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1086                 *ecode = DDPU_INV_QN;
1087                 break;
1088         case T4_ERR_MSN:
1089         case T4_ERR_MSN_GAP:
1090         case T4_ERR_MSN_RANGE:
1091         case T4_ERR_IRD_OVERFLOW:
1092                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1093                 *ecode = DDPU_INV_MSN_RANGE;
1094                 break;
1095         case T4_ERR_TBIT:
1096                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1097                 *ecode = 0;
1098                 break;
1099         case T4_ERR_MO:
1100                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1101                 *ecode = DDPU_INV_MO;
1102                 break;
1103         default:
1104                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1105                 *ecode = 0;
1106                 break;
1107         }
1108 }
1109
1110 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1111                            gfp_t gfp)
1112 {
1113         int ret;
1114         struct fw_ri_wr *wqe;
1115         struct terminate_message *term;
1116         struct wrqe *wr;
1117         struct socket *so = qhp->ep->com.so;
1118         struct inpcb *inp = sotoinpcb(so);
1119         struct tcpcb *tp = intotcpcb(inp);
1120         struct toepcb *toep = tp->t_toe;
1121
1122         CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp,
1123             qhp->wq.sq.qid, qhp->ep->hwtid);
1124
1125         wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
1126         if (wr == NULL)
1127                 return;
1128         wqe = wrtod(wr);
1129
1130         memset(wqe, 0, sizeof *wqe);
1131         wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR));
1132         wqe->flowid_len16 = cpu_to_be32(
1133                 V_FW_WR_FLOWID(qhp->ep->hwtid) |
1134                 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1135
1136         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1137         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1138         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1139         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1140                 term->layer_etype = qhp->attr.layer_etype;
1141                 term->ecode = qhp->attr.ecode;
1142         } else
1143                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1144         ret = creds(toep, inp, sizeof(*wqe));
1145         if (ret) {
1146                 free_wrqe(wr);
1147                 return;
1148         }
1149         t4_wrq_tx(qhp->rhp->rdev.adap, wr);
1150 }
1151
1152 /* Assumes qhp lock is held. */
1153 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1154                        struct c4iw_cq *schp)
1155 {
1156         int count;
1157         int rq_flushed, sq_flushed;
1158         unsigned long flag;
1159
1160         CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp,
1161             schp);
1162
1163         /* locking hierarchy: cq lock first, then qp lock. */
1164         spin_lock_irqsave(&rchp->lock, flag);
1165         spin_lock(&qhp->lock);
1166
1167         if (qhp->wq.flushed) {
1168                 spin_unlock(&qhp->lock);
1169                 spin_unlock_irqrestore(&rchp->lock, flag);
1170                 return;
1171         }
1172         qhp->wq.flushed = 1;
1173
1174         c4iw_flush_hw_cq(rchp);
1175         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1176         rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1177         spin_unlock(&qhp->lock);
1178         spin_unlock_irqrestore(&rchp->lock, flag);
1179
1180         /* locking hierarchy: cq lock first, then qp lock. */
1181         spin_lock_irqsave(&schp->lock, flag);
1182         spin_lock(&qhp->lock);
1183         if (schp != rchp)
1184                 c4iw_flush_hw_cq(schp);
1185         sq_flushed = c4iw_flush_sq(qhp);
1186         spin_unlock(&qhp->lock);
1187         spin_unlock_irqrestore(&schp->lock, flag);
1188
1189         if (schp == rchp) {
1190                 if (t4_clear_cq_armed(&rchp->cq) &&
1191                     (rq_flushed || sq_flushed)) {
1192                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1193                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1194                                                    rchp->ibcq.cq_context);
1195                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1196                 }
1197         } else {
1198                 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1199                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1200                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1201                                                    rchp->ibcq.cq_context);
1202                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1203                 }
1204                 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1205                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1206                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1207                                                    schp->ibcq.cq_context);
1208                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1209                 }
1210         }
1211 }
1212
1213 static void flush_qp(struct c4iw_qp *qhp)
1214 {
1215         struct c4iw_cq *rchp, *schp;
1216         unsigned long flag;
1217
1218         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1219         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1220
1221         t4_set_wq_in_error(&qhp->wq);
1222         if (qhp->ibqp.uobject) {
1223                 t4_set_cq_in_error(&rchp->cq);
1224                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1225                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1226                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1227                 if (schp != rchp) {
1228                         t4_set_cq_in_error(&schp->cq);
1229                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1230                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1231                                         schp->ibcq.cq_context);
1232                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1233                 }
1234                 return;
1235         }
1236         __flush_qp(qhp, rchp, schp);
1237 }
1238
1239 static int
1240 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep)
1241 {
1242         struct c4iw_rdev *rdev = &rhp->rdev;
1243         struct adapter *sc = rdev->adap;
1244         struct fw_ri_wr *wqe;
1245         int ret;
1246         struct wrqe *wr;
1247         struct socket *so = ep->com.so;
1248         struct inpcb *inp = sotoinpcb(so);
1249         struct tcpcb *tp = intotcpcb(inp);
1250         struct toepcb *toep = tp->t_toe;
1251
1252         KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__));
1253
1254         CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp,
1255             qhp->wq.sq.qid, ep, ep->hwtid);
1256
1257         wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
1258         if (wr == NULL)
1259                 return (0);
1260         wqe = wrtod(wr);
1261
1262         memset(wqe, 0, sizeof *wqe);
1263
1264         wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL);
1265         wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1266             V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1267         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1268         wqe->u.fini.type = FW_RI_TYPE_FINI;
1269
1270         c4iw_init_wr_wait(&ep->com.wr_wait);
1271
1272         ret = creds(toep, inp, sizeof(*wqe));
1273         if (ret) {
1274                 free_wrqe(wr);
1275                 return ret;
1276         }
1277         t4_wrq_tx(sc, wr);
1278
1279         ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid,
1280                         qhp->wq.sq.qid, ep->com.so, __func__);
1281         return ret;
1282 }
1283
1284 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1285 {
1286         CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type);
1287         memset(&init->u, 0, sizeof init->u);
1288         switch (p2p_type) {
1289         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1290                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1291                 init->u.write.stag_sink = cpu_to_be32(1);
1292                 init->u.write.to_sink = cpu_to_be64(1);
1293                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1294                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1295                                                    sizeof(struct fw_ri_immd),
1296                                                    16);
1297                 break;
1298         case FW_RI_INIT_P2PTYPE_READ_REQ:
1299                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1300                 init->u.read.stag_src = cpu_to_be32(1);
1301                 init->u.read.to_src_lo = cpu_to_be32(1);
1302                 init->u.read.stag_sink = cpu_to_be32(1);
1303                 init->u.read.to_sink_lo = cpu_to_be32(1);
1304                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1305                 break;
1306         }
1307 }
1308
1309 static int
1310 creds(struct toepcb *toep, struct inpcb *inp, size_t wrsize)
1311 {
1312         struct ofld_tx_sdesc *txsd;
1313
1314         CTR3(KTR_IW_CXGBE, "%s:creB  %p %u", __func__, toep , wrsize);
1315         INP_WLOCK(inp);
1316         if ((inp->inp_flags & (INP_DROPPED | INP_TIMEWAIT)) != 0) {
1317                 INP_WUNLOCK(inp);
1318                 return (EINVAL);
1319         }
1320         txsd = &toep->txsd[toep->txsd_pidx];
1321         txsd->tx_credits = howmany(wrsize, 16);
1322         txsd->plen = 0;
1323         KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0,
1324                         ("%s: not enough credits (%d)", __func__, toep->tx_credits));
1325         toep->tx_credits -= txsd->tx_credits;
1326         if (__predict_false(++toep->txsd_pidx == toep->txsd_total))
1327                 toep->txsd_pidx = 0;
1328         toep->txsd_avail--;
1329         INP_WUNLOCK(inp);
1330         CTR5(KTR_IW_CXGBE, "%s:creE  %p %u %u %u", __func__, toep ,
1331             txsd->tx_credits, toep->tx_credits, toep->txsd_pidx);
1332         return (0);
1333 }
1334
1335 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1336 {
1337         struct fw_ri_wr *wqe;
1338         int ret;
1339         struct wrqe *wr;
1340         struct c4iw_ep *ep = qhp->ep;
1341         struct c4iw_rdev *rdev = &qhp->rhp->rdev;
1342         struct adapter *sc = rdev->adap;
1343         struct socket *so = ep->com.so;
1344         struct inpcb *inp = sotoinpcb(so);
1345         struct tcpcb *tp = intotcpcb(inp);
1346         struct toepcb *toep = tp->t_toe;
1347
1348         CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp,
1349             qhp->wq.sq.qid, ep, ep->hwtid);
1350
1351         wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq);
1352         if (wr == NULL)
1353                 return (0);
1354         wqe = wrtod(wr);
1355         ret = alloc_ird(rhp, qhp->attr.max_ird);
1356         if (ret) {
1357                 qhp->attr.max_ird = 0;
1358                 free_wrqe(wr);
1359                 return ret;
1360         }
1361
1362         memset(wqe, 0, sizeof *wqe);
1363
1364         wqe->op_compl = cpu_to_be32(
1365                 V_FW_WR_OP(FW_RI_WR) |
1366                 F_FW_WR_COMPL);
1367         wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1368             V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1369
1370         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1371
1372         wqe->u.init.type = FW_RI_TYPE_INIT;
1373         wqe->u.init.mpareqbit_p2ptype =
1374                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1375                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1376         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1377         if (qhp->attr.mpa_attr.recv_marker_enabled)
1378                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1379         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1380                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1381         if (qhp->attr.mpa_attr.crc_enabled)
1382                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1383
1384         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1385                             FW_RI_QP_RDMA_WRITE_ENABLE |
1386                             FW_RI_QP_BIND_ENABLE;
1387         if (!qhp->ibqp.uobject)
1388                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1389                                      FW_RI_QP_STAG0_ENABLE;
1390         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1391         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1392         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1393         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1394         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1395         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1396         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1397         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1398         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1399         wqe->u.init.iss = cpu_to_be32(ep->snd_seq);
1400         wqe->u.init.irs = cpu_to_be32(ep->rcv_seq);
1401         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1402         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1403             sc->vres.rq.start);
1404         if (qhp->attr.mpa_attr.initiator)
1405                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1406
1407         c4iw_init_wr_wait(&ep->com.wr_wait);
1408
1409         ret = creds(toep, inp, sizeof(*wqe));
1410         if (ret) {
1411                 free_wrqe(wr);
1412                 free_ird(rhp, qhp->attr.max_ird);
1413                 return ret;
1414         }
1415         t4_wrq_tx(sc, wr);
1416
1417         ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid,
1418                         qhp->wq.sq.qid, ep->com.so, __func__);
1419
1420         toep->params.ulp_mode = ULP_MODE_RDMA;
1421         free_ird(rhp, qhp->attr.max_ird);
1422
1423         return ret;
1424 }
1425
1426 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1427                    enum c4iw_qp_attr_mask mask,
1428                    struct c4iw_qp_attributes *attrs,
1429                    int internal)
1430 {
1431         int ret = 0;
1432         struct c4iw_qp_attributes newattr = qhp->attr;
1433         int disconnect = 0;
1434         int terminate = 0;
1435         int abort = 0;
1436         int free = 0;
1437         struct c4iw_ep *ep = NULL;
1438
1439         CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp,
1440             qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep);
1441         CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state,
1442             (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1443
1444         mutex_lock(&qhp->mutex);
1445
1446         /* Process attr changes if in IDLE */
1447         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1448                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1449                         ret = -EIO;
1450                         goto out;
1451                 }
1452                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1453                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1454                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1455                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1456                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1457                         newattr.enable_bind = attrs->enable_bind;
1458                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1459                         if (attrs->max_ord > c4iw_max_read_depth) {
1460                                 ret = -EINVAL;
1461                                 goto out;
1462                         }
1463                         newattr.max_ord = attrs->max_ord;
1464                 }
1465                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1466                         if (attrs->max_ird > cur_max_read_depth(rhp)) {
1467                                 ret = -EINVAL;
1468                                 goto out;
1469                         }
1470                         newattr.max_ird = attrs->max_ird;
1471                 }
1472                 qhp->attr = newattr;
1473         }
1474
1475         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1476                 goto out;
1477         if (qhp->attr.state == attrs->next_state)
1478                 goto out;
1479
1480         /* Return EINPROGRESS if QP is already in transition state.
1481          * Eg: CLOSING->IDLE transition or *->ERROR transition.
1482          * This can happen while connection is switching(due to rdma_fini)
1483          * from iWARP/RDDP to TOE mode and any inflight RDMA RX data will
1484          * reach TOE driver -> TCP stack -> iWARP driver. In this way
1485          * iWARP driver keep receiving inflight RDMA RX data until socket
1486          * is closed or aborted. And if iWARP CM is in FPDU sate, then
1487          * it tries to put QP in TERM state and disconnects endpoint.
1488          * But as QP is already in transition state, this event is ignored.
1489          */
1490         if ((qhp->attr.state >= C4IW_QP_STATE_ERROR) &&
1491                 (attrs->next_state == C4IW_QP_STATE_TERMINATE)) {
1492                 ret = -EINPROGRESS;
1493                 goto out;
1494         }
1495
1496         switch (qhp->attr.state) {
1497         case C4IW_QP_STATE_IDLE:
1498                 switch (attrs->next_state) {
1499                 case C4IW_QP_STATE_RTS:
1500                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1501                                 ret = -EINVAL;
1502                                 goto out;
1503                         }
1504                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1505                                 ret = -EINVAL;
1506                                 goto out;
1507                         }
1508                         qhp->attr.mpa_attr = attrs->mpa_attr;
1509                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1510                         qhp->ep = qhp->attr.llp_stream_handle;
1511                         set_state(qhp, C4IW_QP_STATE_RTS);
1512
1513                         /*
1514                          * Ref the endpoint here and deref when we
1515                          * disassociate the endpoint from the QP.  This
1516                          * happens in CLOSING->IDLE transition or *->ERROR
1517                          * transition.
1518                          */
1519                         c4iw_get_ep(&qhp->ep->com);
1520                         ret = rdma_init(rhp, qhp);
1521                         if (ret)
1522                                 goto err;
1523                         break;
1524                 case C4IW_QP_STATE_ERROR:
1525                         set_state(qhp, C4IW_QP_STATE_ERROR);
1526                         flush_qp(qhp);
1527                         break;
1528                 default:
1529                         ret = -EINVAL;
1530                         goto out;
1531                 }
1532                 break;
1533         case C4IW_QP_STATE_RTS:
1534                 switch (attrs->next_state) {
1535                 case C4IW_QP_STATE_CLOSING:
1536                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1537                         t4_set_wq_in_error(&qhp->wq);
1538                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1539                         ep = qhp->ep;
1540                         if (!internal) {
1541                                 abort = 0;
1542                                 disconnect = 1;
1543                                 c4iw_get_ep(&qhp->ep->com);
1544                         }
1545                         ret = rdma_fini(rhp, qhp, ep);
1546                         if (ret)
1547                                 goto err;
1548                         break;
1549                 case C4IW_QP_STATE_TERMINATE:
1550                         t4_set_wq_in_error(&qhp->wq);
1551                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1552                         qhp->attr.layer_etype = attrs->layer_etype;
1553                         qhp->attr.ecode = attrs->ecode;
1554                         ep = qhp->ep;
1555                         if (!internal) {
1556                                 c4iw_get_ep(&qhp->ep->com);
1557                                 terminate = 1;
1558                                 disconnect = 1;
1559                         } else {
1560                                 terminate = qhp->attr.send_term;
1561                                 ret = rdma_fini(rhp, qhp, ep);
1562                                 if (ret)
1563                                         goto err;
1564                         }
1565                         break;
1566                 case C4IW_QP_STATE_ERROR:
1567                         t4_set_wq_in_error(&qhp->wq);
1568                         set_state(qhp, C4IW_QP_STATE_ERROR);
1569                         if (!internal) {
1570                                 abort = 1;
1571                                 disconnect = 1;
1572                                 ep = qhp->ep;
1573                                 c4iw_get_ep(&qhp->ep->com);
1574                         }
1575                         goto err;
1576                         break;
1577                 default:
1578                         ret = -EINVAL;
1579                         goto out;
1580                 }
1581                 break;
1582         case C4IW_QP_STATE_CLOSING:
1583
1584                 /*
1585                  * Allow kernel users to move to ERROR for qp draining.
1586                  */
1587                 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1588                                   C4IW_QP_STATE_ERROR)) {
1589                         ret = -EINVAL;
1590                         goto out;
1591                 }
1592                 switch (attrs->next_state) {
1593                 case C4IW_QP_STATE_IDLE:
1594                         flush_qp(qhp);
1595                         set_state(qhp, C4IW_QP_STATE_IDLE);
1596                         qhp->attr.llp_stream_handle = NULL;
1597                         c4iw_put_ep(&qhp->ep->com);
1598                         qhp->ep = NULL;
1599                         wake_up(&qhp->wait);
1600                         break;
1601                 case C4IW_QP_STATE_ERROR:
1602                         goto err;
1603                 default:
1604                         ret = -EINVAL;
1605                         goto err;
1606                 }
1607                 break;
1608         case C4IW_QP_STATE_ERROR:
1609                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1610                         ret = -EINVAL;
1611                         goto out;
1612                 }
1613                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1614                         ret = -EINVAL;
1615                         goto out;
1616                 }
1617                 set_state(qhp, C4IW_QP_STATE_IDLE);
1618                 break;
1619         case C4IW_QP_STATE_TERMINATE:
1620                 if (!internal) {
1621                         ret = -EINVAL;
1622                         goto out;
1623                 }
1624                 goto err;
1625                 break;
1626         default:
1627                 printf("%s in a bad state %d\n",
1628                        __func__, qhp->attr.state);
1629                 ret = -EINVAL;
1630                 goto err;
1631                 break;
1632         }
1633         goto out;
1634 err:
1635         CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__,
1636             qhp->ep, qhp->wq.sq.qid);
1637
1638         /* disassociate the LLP connection */
1639         qhp->attr.llp_stream_handle = NULL;
1640         if (!ep)
1641                 ep = qhp->ep;
1642         qhp->ep = NULL;
1643         set_state(qhp, C4IW_QP_STATE_ERROR);
1644         free = 1;
1645         abort = 1;
1646         BUG_ON(!ep);
1647         flush_qp(qhp);
1648         wake_up(&qhp->wait);
1649 out:
1650         mutex_unlock(&qhp->mutex);
1651
1652         if (terminate)
1653                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1654
1655         /*
1656          * If disconnect is 1, then we need to initiate a disconnect
1657          * on the EP.  This can be a normal close (RTS->CLOSING) or
1658          * an abnormal close (RTS/CLOSING->ERROR).
1659          */
1660         if (disconnect) {
1661                 __c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1662                                                          GFP_KERNEL);
1663                 c4iw_put_ep(&ep->com);
1664         }
1665
1666         /*
1667          * If free is 1, then we've disassociated the EP from the QP
1668          * and we need to dereference the EP.
1669          */
1670         if (free)
1671                 c4iw_put_ep(&ep->com);
1672         CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state);
1673         return ret;
1674 }
1675
1676 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1677 {
1678         struct c4iw_dev *rhp;
1679         struct c4iw_qp *qhp;
1680         struct c4iw_qp_attributes attrs;
1681
1682         CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp);
1683         qhp = to_c4iw_qp(ib_qp);
1684         rhp = qhp->rhp;
1685
1686         attrs.next_state = C4IW_QP_STATE_ERROR;
1687         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1688                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1689         else
1690                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1691         wait_event(qhp->wait, !qhp->ep);
1692
1693         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1694
1695         free_ird(rhp, qhp->attr.max_ird);
1696         c4iw_qp_rem_ref(ib_qp);
1697
1698         CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp,
1699             qhp->wq.sq.qid);
1700         return 0;
1701 }
1702
1703 struct ib_qp *
1704 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1705     struct ib_udata *udata)
1706 {
1707         struct c4iw_dev *rhp;
1708         struct c4iw_qp *qhp;
1709         struct c4iw_pd *php;
1710         struct c4iw_cq *schp;
1711         struct c4iw_cq *rchp;
1712         struct c4iw_create_qp_resp uresp;
1713         unsigned int sqsize, rqsize;
1714         struct c4iw_ucontext *ucontext;
1715         int ret;
1716         struct c4iw_mm_entry *sq_key_mm = NULL, *rq_key_mm = NULL;
1717         struct c4iw_mm_entry *sq_db_key_mm = NULL, *rq_db_key_mm = NULL;
1718
1719         CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
1720
1721         if (attrs->qp_type != IB_QPT_RC)
1722                 return ERR_PTR(-EINVAL);
1723
1724         php = to_c4iw_pd(pd);
1725         rhp = php->rhp;
1726         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1727         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1728         if (!schp || !rchp)
1729                 return ERR_PTR(-EINVAL);
1730
1731         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1732                 return ERR_PTR(-EINVAL);
1733
1734         if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1735                 return ERR_PTR(-E2BIG);
1736         rqsize = attrs->cap.max_recv_wr + 1;
1737         if (rqsize < 8)
1738                 rqsize = 8;
1739
1740         if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1741                 return ERR_PTR(-E2BIG);
1742         sqsize = attrs->cap.max_send_wr + 1;
1743         if (sqsize < 8)
1744                 sqsize = 8;
1745
1746         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1747
1748         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1749         if (!qhp)
1750                 return ERR_PTR(-ENOMEM);
1751         qhp->wq.sq.size = sqsize;
1752         qhp->wq.sq.memsize =
1753                 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1754                 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1755         qhp->wq.sq.flush_cidx = -1;
1756         qhp->wq.rq.size = rqsize;
1757         qhp->wq.rq.memsize =
1758                 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1759                 sizeof(*qhp->wq.rq.queue);
1760
1761         if (ucontext) {
1762                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1763                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1764         }
1765
1766         CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu",
1767             __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1768
1769         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1770                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1771         if (ret)
1772                 goto err1;
1773
1774         attrs->cap.max_recv_wr = rqsize - 1;
1775         attrs->cap.max_send_wr = sqsize - 1;
1776         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1777
1778         qhp->rhp = rhp;
1779         qhp->attr.pd = php->pdid;
1780         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1781         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1782         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1783         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1784         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1785         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1786         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1787         qhp->attr.state = C4IW_QP_STATE_IDLE;
1788         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1789         qhp->attr.enable_rdma_read = 1;
1790         qhp->attr.enable_rdma_write = 1;
1791         qhp->attr.enable_bind = 1;
1792         qhp->attr.max_ord = 0;
1793         qhp->attr.max_ird = 0;
1794         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1795         spin_lock_init(&qhp->lock);
1796         mutex_init(&qhp->mutex);
1797         init_waitqueue_head(&qhp->wait);
1798         kref_init(&qhp->kref);
1799         INIT_WORK(&qhp->free_work, free_qp_work);
1800
1801         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1802         if (ret)
1803                 goto err2;
1804
1805         if (udata) {
1806                 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1807                 if (!sq_key_mm) {
1808                         ret = -ENOMEM;
1809                         goto err3;
1810                 }
1811                 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1812                 if (!rq_key_mm) {
1813                         ret = -ENOMEM;
1814                         goto err4;
1815                 }
1816                 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1817                 if (!sq_db_key_mm) {
1818                         ret = -ENOMEM;
1819                         goto err5;
1820                 }
1821                 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1822                 if (!rq_db_key_mm) {
1823                         ret = -ENOMEM;
1824                         goto err6;
1825                 }
1826                 uresp.flags = 0;
1827                 uresp.qid_mask = rhp->rdev.qpmask;
1828                 uresp.sqid = qhp->wq.sq.qid;
1829                 uresp.sq_size = qhp->wq.sq.size;
1830                 uresp.sq_memsize = qhp->wq.sq.memsize;
1831                 uresp.rqid = qhp->wq.rq.qid;
1832                 uresp.rq_size = qhp->wq.rq.size;
1833                 uresp.rq_memsize = qhp->wq.rq.memsize;
1834                 spin_lock(&ucontext->mmap_lock);
1835                 uresp.ma_sync_key =  0;
1836                 uresp.sq_key = ucontext->key;
1837                 ucontext->key += PAGE_SIZE;
1838                 uresp.rq_key = ucontext->key;
1839                 ucontext->key += PAGE_SIZE;
1840                 uresp.sq_db_gts_key = ucontext->key;
1841                 ucontext->key += PAGE_SIZE;
1842                 uresp.rq_db_gts_key = ucontext->key;
1843                 ucontext->key += PAGE_SIZE;
1844                 spin_unlock(&ucontext->mmap_lock);
1845                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1846                 if (ret)
1847                         goto err7;
1848                 sq_key_mm->key = uresp.sq_key;
1849                 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1850                 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1851                 CTR4(KTR_IW_CXGBE, "%s sq_key_mm %x, %x, %d", __func__,
1852                                 sq_key_mm->key, sq_key_mm->addr,
1853                                 sq_key_mm->len);
1854                 insert_mmap(ucontext, sq_key_mm);
1855                 rq_key_mm->key = uresp.rq_key;
1856                 rq_key_mm->addr = qhp->wq.rq.phys_addr;
1857                 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1858                 CTR4(KTR_IW_CXGBE, "%s rq_key_mm %x, %x, %d", __func__,
1859                                 rq_key_mm->key, rq_key_mm->addr,
1860                                 rq_key_mm->len);
1861                 insert_mmap(ucontext, rq_key_mm);
1862                 sq_db_key_mm->key = uresp.sq_db_gts_key;
1863                 sq_db_key_mm->addr = (u64)qhp->wq.sq.bar2_pa;
1864                 sq_db_key_mm->len = PAGE_SIZE;
1865                 CTR4(KTR_IW_CXGBE, "%s sq_db_key_mm %x, %x, %d", __func__,
1866                                 sq_db_key_mm->key, sq_db_key_mm->addr,
1867                                 sq_db_key_mm->len);
1868                 insert_mmap(ucontext, sq_db_key_mm);
1869                 rq_db_key_mm->key = uresp.rq_db_gts_key;
1870                 rq_db_key_mm->addr = (u64)qhp->wq.rq.bar2_pa;
1871                 rq_db_key_mm->len = PAGE_SIZE;
1872                 CTR4(KTR_IW_CXGBE, "%s rq_db_key_mm %x, %x, %d", __func__,
1873                                 rq_db_key_mm->key, rq_db_key_mm->addr,
1874                                 rq_db_key_mm->len);
1875                 insert_mmap(ucontext, rq_db_key_mm);
1876
1877                 c4iw_get_ucontext(ucontext);
1878                 qhp->ucontext = ucontext;
1879         }
1880         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1881         init_timer(&(qhp->timer));
1882
1883         CTR5(KTR_IW_CXGBE, "%s sq id %u size %u memsize %zu num_entries %u",
1884                  __func__, qhp->wq.sq.qid,
1885                  qhp->wq.sq.size, qhp->wq.sq.memsize, attrs->cap.max_send_wr);
1886         CTR5(KTR_IW_CXGBE, "%s rq id %u size %u memsize %zu num_entries %u",
1887                  __func__, qhp->wq.rq.qid,
1888                  qhp->wq.rq.size, qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1889         return &qhp->ibqp;
1890 err7:
1891         kfree(rq_db_key_mm);
1892 err6:
1893         kfree(sq_db_key_mm);
1894 err5:
1895         kfree(rq_key_mm);
1896 err4:
1897         kfree(sq_key_mm);
1898 err3:
1899         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1900 err2:
1901         destroy_qp(&rhp->rdev, &qhp->wq,
1902                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1903 err1:
1904         kfree(qhp);
1905         return ERR_PTR(ret);
1906 }
1907
1908 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1909                       int attr_mask, struct ib_udata *udata)
1910 {
1911         struct c4iw_dev *rhp;
1912         struct c4iw_qp *qhp;
1913         enum c4iw_qp_attr_mask mask = 0;
1914         struct c4iw_qp_attributes attrs;
1915
1916         CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp);
1917
1918         /* iwarp does not support the RTR state */
1919         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1920                 attr_mask &= ~IB_QP_STATE;
1921
1922         /* Make sure we still have something left to do */
1923         if (!attr_mask)
1924                 return 0;
1925
1926         memset(&attrs, 0, sizeof attrs);
1927         qhp = to_c4iw_qp(ibqp);
1928         rhp = qhp->rhp;
1929
1930         attrs.next_state = c4iw_convert_state(attr->qp_state);
1931         attrs.enable_rdma_read = (attr->qp_access_flags &
1932                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1933         attrs.enable_rdma_write = (attr->qp_access_flags &
1934                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1935         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1936
1937
1938         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1939         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1940                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1941                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1942                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1943
1944         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1945 }
1946
1947 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1948 {
1949         CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn);
1950         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1951 }
1952
1953 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1954                      int attr_mask, struct ib_qp_init_attr *init_attr)
1955 {
1956         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1957
1958         memset(attr, 0, sizeof *attr);
1959         memset(init_attr, 0, sizeof *init_attr);
1960         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1961         init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1962         init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1963         init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1964         init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1965         init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1966         init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1967         return 0;
1968 }
1969 #endif