2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_IOCTL_H__
32 #define __T4_IOCTL_H__
34 #include <sys/types.h>
35 #include <net/ethernet.h>
38 * Ioctl commands specific to this driver.
41 T4_GETREG = 0x40, /* read register */
42 T4_SETREG, /* write register */
43 T4_REGDUMP, /* dump of all registers */
44 T4_GET_FILTER_MODE, /* get global filter mode */
45 T4_SET_FILTER_MODE, /* set global filter mode */
46 T4_GET_FILTER, /* get information about a filter */
47 T4_SET_FILTER, /* program a filter */
48 T4_DEL_FILTER, /* delete a filter */
49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */
50 T4_LOAD_FW, /* flash firmware */
51 T4_GET_MEM, /* read memory */
60 #define T4_REGDUMP_SIZE (160 * 1024)
63 uint32_t len; /* bytes */
73 * A hardware filter is some valid combination of these.
75 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */
76 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */
77 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */
78 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */
79 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */
80 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */
81 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */
82 #define T4_FILTER_PORT 0x80 /* Physical ingress port */
83 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */
84 #define T4_FILTER_VLAN 0x200 /* VLAN ID */
85 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */
86 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */
87 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */
88 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */
89 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */
90 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */
94 FILTER_PASS = 0, /* default */
99 /* 802.1q manipulation on FILTER_SWITCH */
101 VLAN_NOCHANGE = 0, /* default */
109 UCAST_EXACT = 0, /* exact unicast match */
110 UCAST_HASH = 1, /* inexact (hashed) unicast match */
111 MCAST_EXACT = 2, /* exact multicast match */
112 MCAST_HASH = 3, /* inexact (hashed) multicast match */
113 PROMISC = 4, /* no match but port is promiscuous */
114 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */
115 BCAST = 6, /* broadcast packet */
120 DST_MODE_QUEUE, /* queue is directly specified by filter */
121 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */
122 DST_MODE_RSS, /* queue selected by default RSS hash lookup */
123 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified
127 struct t4_filter_tuple {
129 * These are always available.
131 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */
132 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */
133 uint16_t sport; /* source port */
134 uint16_t dport; /* destination port */
137 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP
138 * is used to select the global mode and all filters are limited to the
139 * set of fields allowed by the global mode.
141 uint16_t vnic; /* VNIC id or outer VLAN tag */
142 uint16_t vlan; /* VLAN tag */
143 uint16_t ethtype; /* Ethernet type */
144 uint8_t tos; /* TOS/Traffic Type */
145 uint8_t proto; /* protocol type */
146 uint32_t fcoe:1; /* FCoE packet */
147 uint32_t iport:3; /* ingress port */
148 uint32_t matchtype:3; /* MPS match type */
149 uint32_t frag:1; /* fragmentation extension header */
150 uint32_t macidx:9; /* exact match MAC index */
151 uint32_t vlan_vld:1; /* VLAN valid */
152 uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */
155 struct t4_filter_specification {
156 uint32_t hitcnts:1; /* count filter hits in TCB */
157 uint32_t prio:1; /* filter has priority over active/server */
158 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
159 uint32_t action:2; /* drop, pass, switch */
160 uint32_t rpttid:1; /* report TID in RSS hash field */
161 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
162 uint32_t iq:10; /* ingress queue */
163 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
164 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
165 /* 1 => TCB contains IQ ID */
168 * Switch proxy/rewrite fields. An ingress packet which matches a
169 * filter with "switch" set will be looped back out as an egress
170 * packet -- potentially with some Ethernet header rewriting.
172 uint32_t eport:2; /* egress port to switch packet out */
173 uint32_t newdmac:1; /* rewrite destination MAC address */
174 uint32_t newsmac:1; /* rewrite source MAC address */
175 uint32_t newvlan:2; /* rewrite VLAN Tag */
176 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */
177 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */
178 uint16_t vlan; /* VLAN Tag to insert */
181 * Filter rule value/mask pairs.
183 struct t4_filter_tuple val;
184 struct t4_filter_tuple mask;
192 struct t4_filter_specification fs;
195 #define T4_SGE_CONTEXT_SIZE 24
203 struct t4_sge_context {
206 uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
209 struct t4_mem_range {
215 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg)
216 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg)
217 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump)
218 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t)
219 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t)
220 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter)
221 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter)
222 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter)
223 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \
224 struct t4_sge_context)
225 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data)
226 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range)