2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_IOCTL_H__
34 #define __T4_IOCTL_H__
36 #include <sys/types.h>
37 #include <net/ethernet.h>
41 * Ioctl commands specific to this driver.
44 T4_GETREG = 0x40, /* read register */
45 T4_SETREG, /* write register */
46 T4_REGDUMP, /* dump of all registers */
47 T4_GET_FILTER_MODE, /* get global filter mode */
48 T4_SET_FILTER_MODE, /* set global filter mode */
49 T4_GET_FILTER, /* get information about a filter */
50 T4_SET_FILTER, /* program a filter */
51 T4_DEL_FILTER, /* delete a filter */
52 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */
53 T4_LOAD_FW, /* flash firmware */
54 T4_GET_MEM, /* read memory */
55 T4_GET_I2C, /* read from i2c addressible device */
56 T4_CLEAR_STATS, /* clear a port's MAC statistics */
57 T4_SET_OFLD_POLICY, /* Set offload policy */
58 T4_SET_SCHED_CLASS, /* set sched class */
59 T4_SET_SCHED_QUEUE, /* set queue class */
60 T4_GET_TRACER, /* get information about a tracer */
61 T4_SET_TRACER, /* program a tracer */
62 T4_LOAD_CFG, /* copy a config file to card's flash */
63 T4_LOAD_BOOT, /* flash boot rom */
64 T4_LOAD_BOOTCFG, /* flash bootcfg */
65 T4_CUDBG_DUMP, /* debug dump of chip state */
66 T4_SET_FILTER_MASK, /* set filter mask (hashfilter mode) */
75 #define T4_REGDUMP_SIZE (160 * 1024)
76 #define T5_REGDUMP_SIZE (332 * 1024)
79 uint32_t len; /* bytes */
104 * A hardware filter is some valid combination of these.
106 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */
107 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */
108 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */
109 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */
110 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */
111 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */
112 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */
113 #define T4_FILTER_PORT 0x80 /* Physical ingress port */
114 #define T4_FILTER_VNIC 0x100 /* See the IC_* bits towards the end */
115 #define T4_FILTER_VLAN 0x200 /* VLAN ID */
116 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */
117 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */
118 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */
119 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */
120 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */
121 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */
123 * T4_FILTER_VNIC's real meaning depends on the ingress config.
125 #define T4_FILTER_IC_OVLAN 0 /* outer VLAN */
126 #define T4_FILTER_IC_VNIC 0x80000000 /* VNIC id (PF/VF) */
127 #define T4_FILTER_IC_ENCAP 0x40000000
131 FILTER_PASS = 0, /* default */
136 /* 802.1q manipulation on FILTER_SWITCH */
138 VLAN_NOCHANGE = 0, /* default */
146 UCAST_EXACT = 0, /* exact unicast match */
147 UCAST_HASH = 1, /* inexact (hashed) unicast match */
148 MCAST_EXACT = 2, /* exact multicast match */
149 MCAST_HASH = 3, /* inexact (hashed) multicast match */
150 PROMISC = 4, /* no match but port is promiscuous */
151 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */
152 BCAST = 6, /* broadcast packet */
157 DST_MODE_QUEUE, /* queue is directly specified by filter */
158 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */
159 DST_MODE_RSS, /* queue selected by default RSS hash lookup */
160 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified
165 NAT_MODE_NONE = 0, /* No NAT performed */
166 NAT_MODE_DIP, /* NAT on Dst IP */
167 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
168 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
169 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
170 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
171 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
172 NAT_MODE_ALL /* NAT on entire 4-tuple */
175 struct t4_filter_tuple {
177 * These are always available.
179 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */
180 uint8_t dip[16]; /* destination IP address (IPv4 in [3:0]) */
181 uint16_t sport; /* source port */
182 uint16_t dport; /* destination port */
185 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP
186 * is used to select the global mode and all filters are limited to the
187 * set of fields allowed by the global mode.
189 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */
190 uint16_t vlan; /* VLAN tag */
191 uint16_t ethtype; /* Ethernet type */
192 uint8_t tos; /* TOS/Traffic Type */
193 uint8_t proto; /* protocol type */
194 uint32_t fcoe:1; /* FCoE packet */
195 uint32_t iport:3; /* ingress port */
196 uint32_t matchtype:3; /* MPS match type */
197 uint32_t frag:1; /* fragmentation extension header */
198 uint32_t macidx:9; /* exact match MAC index */
199 uint32_t vlan_vld:1; /* VLAN valid */
200 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */
201 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */
204 struct t4_filter_specification {
205 uint32_t hitcnts:1; /* count filter hits in TCB */
206 uint32_t prio:1; /* filter has priority over active/server */
207 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
208 uint32_t hash:1; /* 0 => LE TCAM, 1 => Hash */
209 uint32_t action:2; /* drop, pass, switch */
210 uint32_t rpttid:1; /* report TID in RSS hash field */
211 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
212 uint32_t iq:10; /* ingress queue */
213 uint32_t maskhash:1; /* dirsteer=0: steer to an RSS sub-region */
214 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
215 /* 1 => TCB contains IQ ID */
218 * Switch proxy/rewrite fields. An ingress packet which matches a
219 * filter with "switch" set will be looped back out as an egress
220 * packet -- potentially with some Ethernet header rewriting.
222 uint32_t eport:2; /* egress port to switch packet out */
223 uint32_t newdmac:1; /* rewrite destination MAC address */
224 uint32_t newsmac:1; /* rewrite source MAC address */
225 uint32_t swapmac:1; /* swap SMAC/DMAC for loopback packet */
226 uint32_t newvlan:2; /* rewrite VLAN Tag */
227 uint32_t nat_mode:3; /* NAT operation mode */
228 uint32_t nat_flag_chk:1;/* check TCP flags before NAT'ing */
229 uint32_t nat_seq_chk; /* sequence value to use for NAT check*/
230 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */
231 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */
232 uint16_t vlan; /* VLAN Tag to insert */
234 uint8_t nat_dip[16]; /* destination IP to use after NAT'ing */
235 uint8_t nat_sip[16]; /* source IP to use after NAT'ing */
236 uint16_t nat_dport; /* destination port to use after NAT'ing */
237 uint16_t nat_sport; /* source port to use after NAT'ing */
240 * Filter rule value/mask pairs.
242 struct t4_filter_tuple val;
243 struct t4_filter_tuple mask;
251 struct t4_filter_specification fs;
254 /* Tx Scheduling Class parameters */
255 struct t4_sched_class_params {
256 int8_t level; /* scheduler hierarchy level */
257 int8_t mode; /* per-class or per-flow */
258 int8_t rateunit; /* bit or packet rate */
259 int8_t ratemode; /* %port relative or kbps absolute */
260 int8_t channel; /* scheduler channel [0..N] */
261 int8_t cl; /* scheduler class [0..N] */
262 int32_t minrate; /* minimum rate */
263 int32_t maxrate; /* maximum rate */
264 int16_t weight; /* percent weight */
265 int16_t pktsize; /* average packet size */
269 * Support for "sched-class" command to allow a TX Scheduling Class to be
270 * programmed with various parameters.
272 struct t4_sched_params {
273 int8_t subcmd; /* sub-command */
274 int8_t type; /* packet or flow */
276 struct { /* sub-command SCHED_CLASS_CONFIG */
277 int8_t minmax; /* minmax enable */
279 struct t4_sched_class_params params;
280 uint8_t reserved[6 + 8 * 8];
285 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */
286 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */
290 SCHED_CLASS_TYPE_PACKET,
294 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */
295 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */
296 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */
300 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */
301 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
305 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */
306 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */
310 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */
311 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */
315 * Support for "sched_queue" command to allow one or more NIC TX Queues to be
316 * bound to a TX Scheduling Class.
318 struct t4_sched_queue {
320 int8_t queue; /* queue index; -1 => all queues */
321 int8_t cl; /* class index; -1 => unbind */
324 #define T4_SGE_CONTEXT_SIZE 24
332 struct t4_sge_context {
335 uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
338 struct t4_mem_range {
344 #define T4_TRACE_LEN 112
345 struct t4_trace_params {
346 uint32_t data[T4_TRACE_LEN / 4];
347 uint32_t mask[T4_TRACE_LEN / 4];
360 struct t4_trace_params tp;
363 struct t4_cudbg_dump {
371 OPEN_TYPE_LISTEN = 'L',
372 OPEN_TYPE_ACTIVE = 'A',
373 OPEN_TYPE_PASSIVE = 'P',
374 OPEN_TYPE_DONTCARE = 'D',
377 struct offload_settings {
393 struct offload_rule {
395 struct offload_settings settings;
396 struct bpf_program bpf_prog; /* compiled program/filter */
400 * An offload policy consists of a set of rules matched in sequence. The
401 * settings of the first rule that matches are applied to that connection.
403 struct t4_offload_policy {
405 struct offload_rule *rule;
408 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg)
409 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg)
410 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump)
411 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t)
412 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t)
413 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter)
414 #define CHELSIO_T4_SET_FILTER _IOWR('f', T4_SET_FILTER, struct t4_filter)
415 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter)
416 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \
417 struct t4_sge_context)
418 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data)
419 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range)
420 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data)
421 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t)
422 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \
423 struct t4_sched_params)
424 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \
425 struct t4_sched_queue)
426 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer)
427 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer)
428 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data)
429 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom)
430 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data)
431 #define CHELSIO_T4_CUDBG_DUMP _IOWR('f', T4_CUDBG_DUMP, struct t4_cudbg_dump)
432 #define CHELSIO_T4_SET_OFLD_POLICY _IOW('f', T4_SET_OFLD_POLICY, struct t4_offload_policy)
433 #define CHELSIO_T4_SET_FILTER_MASK _IOW('f', T4_SET_FILTER_MASK, uint32_t)