sys/dev/cxgbe/t4_main.c

   1 /*-
   2  * Copyright (c) 2011 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  * Written by: Navdeep Parhar <np@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_ddb.h"
  32 #include "opt_inet.h"
  33 #include "opt_inet6.h"
  34 #include "opt_rss.h"
  35
  36 #include <sys/param.h>
  37 #include <sys/conf.h>
  38 #include <sys/priv.h>
  39 #include <sys/kernel.h>
  40 #include <sys/bus.h>
  41 #include <sys/module.h>
  42 #include <sys/malloc.h>
  43 #include <sys/queue.h>
  44 #include <sys/taskqueue.h>
  45 #include <sys/pciio.h>
  46 #include <dev/pci/pcireg.h>
  47 #include <dev/pci/pcivar.h>
  48 #include <dev/pci/pci_private.h>
  49 #include <sys/firmware.h>
  50 #include <sys/sbuf.h>
  51 #include <sys/smp.h>
  52 #include <sys/socket.h>
  53 #include <sys/sockio.h>
  54 #include <sys/sysctl.h>
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_types.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_vlan_var.h>
  60 #ifdef RSS
  61 #include <net/rss_config.h>
  62 #endif
  63 #if defined(__i386__) || defined(__amd64__)
  64 #include <machine/md_var.h>
  65 #include <machine/cputypes.h>
  66 #include <vm/vm.h>
  67 #include <vm/pmap.h>
  68 #endif
  69 #include <crypto/rijndael/rijndael.h>
  70 #ifdef DDB
  71 #include <ddb/ddb.h>
  72 #include <ddb/db_lex.h>
  73 #endif
  74
  75 #include "common/common.h"
  76 #include "common/t4_msg.h"
  77 #include "common/t4_regs.h"
  78 #include "common/t4_regs_values.h"
  79 #include "cudbg/cudbg.h"
  80 #include "t4_ioctl.h"
  81 #include "t4_l2t.h"
  82 #include "t4_mp_ring.h"
  83 #include "t4_if.h"
  84
  85 /* T4 bus driver interface */
  86 static int t4_probe(device_t);
  87 static int t4_attach(device_t);
  88 static int t4_detach(device_t);
  89 static int t4_child_location_str(device_t, device_t, char *, size_t);
  90 static int t4_ready(device_t);
  91 static int t4_read_port_device(device_t, int, device_t *);
  92 static device_method_t t4_methods[] = {
  93         DEVMETHOD(device_probe,         t4_probe),
  94         DEVMETHOD(device_attach,        t4_attach),
  95         DEVMETHOD(device_detach,        t4_detach),
  96
  97         DEVMETHOD(bus_child_location_str, t4_child_location_str),
  98
  99         DEVMETHOD(t4_is_main_ready,     t4_ready),
 100         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 101
 102         DEVMETHOD_END
 103 };
 104 static driver_t t4_driver = {
 105         "t4nex",
 106         t4_methods,
 107         sizeof(struct adapter)
 108 };
 109
 110
 111 /* T4 port (cxgbe) interface */
 112 static int cxgbe_probe(device_t);
 113 static int cxgbe_attach(device_t);
 114 static int cxgbe_detach(device_t);
 115 device_method_t cxgbe_methods[] = {
 116         DEVMETHOD(device_probe,         cxgbe_probe),
 117         DEVMETHOD(device_attach,        cxgbe_attach),
 118         DEVMETHOD(device_detach,        cxgbe_detach),
 119         { 0, 0 }
 120 };
 121 static driver_t cxgbe_driver = {
 122         "cxgbe",
 123         cxgbe_methods,
 124         sizeof(struct port_info)
 125 };
 126
 127 /* T4 VI (vcxgbe) interface */
 128 static int vcxgbe_probe(device_t);
 129 static int vcxgbe_attach(device_t);
 130 static int vcxgbe_detach(device_t);
 131 static device_method_t vcxgbe_methods[] = {
 132         DEVMETHOD(device_probe,         vcxgbe_probe),
 133         DEVMETHOD(device_attach,        vcxgbe_attach),
 134         DEVMETHOD(device_detach,        vcxgbe_detach),
 135         { 0, 0 }
 136 };
 137 static driver_t vcxgbe_driver = {
 138         "vcxgbe",
 139         vcxgbe_methods,
 140         sizeof(struct vi_info)
 141 };
 142
 143 static d_ioctl_t t4_ioctl;
 144
 145 static struct cdevsw t4_cdevsw = {
 146        .d_version = D_VERSION,
 147        .d_ioctl = t4_ioctl,
 148        .d_name = "t4nex",
 149 };
 150
 151 /* T5 bus driver interface */
 152 static int t5_probe(device_t);
 153 static device_method_t t5_methods[] = {
 154         DEVMETHOD(device_probe,         t5_probe),
 155         DEVMETHOD(device_attach,        t4_attach),
 156         DEVMETHOD(device_detach,        t4_detach),
 157
 158         DEVMETHOD(bus_child_location_str, t4_child_location_str),
 159
 160         DEVMETHOD(t4_is_main_ready,     t4_ready),
 161         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 162
 163         DEVMETHOD_END
 164 };
 165 static driver_t t5_driver = {
 166         "t5nex",
 167         t5_methods,
 168         sizeof(struct adapter)
 169 };
 170
 171
 172 /* T5 port (cxl) interface */
 173 static driver_t cxl_driver = {
 174         "cxl",
 175         cxgbe_methods,
 176         sizeof(struct port_info)
 177 };
 178
 179 /* T5 VI (vcxl) interface */
 180 static driver_t vcxl_driver = {
 181         "vcxl",
 182         vcxgbe_methods,
 183         sizeof(struct vi_info)
 184 };
 185
 186 /* T6 bus driver interface */
 187 static int t6_probe(device_t);
 188 static device_method_t t6_methods[] = {
 189         DEVMETHOD(device_probe,         t6_probe),
 190         DEVMETHOD(device_attach,        t4_attach),
 191         DEVMETHOD(device_detach,        t4_detach),
 192
 193         DEVMETHOD(bus_child_location_str, t4_child_location_str),
 194
 195         DEVMETHOD(t4_is_main_ready,     t4_ready),
 196         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 197
 198         DEVMETHOD_END
 199 };
 200 static driver_t t6_driver = {
 201         "t6nex",
 202         t6_methods,
 203         sizeof(struct adapter)
 204 };
 205
 206
 207 /* T6 port (cc) interface */
 208 static driver_t cc_driver = {
 209         "cc",
 210         cxgbe_methods,
 211         sizeof(struct port_info)
 212 };
 213
 214 /* T6 VI (vcc) interface */
 215 static driver_t vcc_driver = {
 216         "vcc",
 217         vcxgbe_methods,
 218         sizeof(struct vi_info)
 219 };
 220
 221 /* ifnet + media interface */
 222 static void cxgbe_init(void *);
 223 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
 224 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
 225 static void cxgbe_qflush(struct ifnet *);
 226 static int cxgbe_media_change(struct ifnet *);
 227 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
 228
 229 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
 230
 231 /*
 232  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
 233  * then ADAPTER_LOCK, then t4_uld_list_lock.
 234  */
 235 static struct sx t4_list_lock;
 236 SLIST_HEAD(, adapter) t4_list;
 237 #ifdef TCP_OFFLOAD
 238 static struct sx t4_uld_list_lock;
 239 SLIST_HEAD(, uld_info) t4_uld_list;
 240 #endif
 241
 242 /*
 243  * Tunables.  See tweak_tunables() too.
 244  *
 245  * Each tunable is set to a default value here if it's known at compile-time.
 246  * Otherwise it is set to -n as an indication to tweak_tunables() that it should
 247  * provide a reasonable default (upto n) when the driver is loaded.
 248  *
 249  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
 250  * T5 are under hw.cxl.
 251  */
 252 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
 253 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
 254 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
 255
 256 /*
 257  * Number of queues for tx and rx, NIC and offload.
 258  */
 259 #define NTXQ 16
 260 int t4_ntxq = -NTXQ;
 261 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
 262     "Number of TX queues per port");
 263 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq);      /* Old name, undocumented */
 264
 265 #define NRXQ 8
 266 int t4_nrxq = -NRXQ;
 267 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
 268     "Number of RX queues per port");
 269 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq);      /* Old name, undocumented */
 270
 271 #define NTXQ_VI 1
 272 static int t4_ntxq_vi = -NTXQ_VI;
 273 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
 274     "Number of TX queues per VI");
 275
 276 #define NRXQ_VI 1
 277 static int t4_nrxq_vi = -NRXQ_VI;
 278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
 279     "Number of RX queues per VI");
 280
 281 static int t4_rsrv_noflowq = 0;
 282 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
 283     0, "Reserve TX queue 0 of each VI for non-flowid packets");
 284
 285 #ifdef TCP_OFFLOAD
 286 #define NOFLDTXQ 8
 287 static int t4_nofldtxq = -NOFLDTXQ;
 288 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
 289     "Number of offload TX queues per port");
 290
 291 #define NOFLDRXQ 2
 292 static int t4_nofldrxq = -NOFLDRXQ;
 293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
 294     "Number of offload RX queues per port");
 295
 296 #define NOFLDTXQ_VI 1
 297 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
 298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
 299     "Number of offload TX queues per VI");
 300
 301 #define NOFLDRXQ_VI 1
 302 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
 303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
 304     "Number of offload RX queues per VI");
 305
 306 #define TMR_IDX_OFLD 1
 307 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
 308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
 309     &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
 310
 311 #define PKTC_IDX_OFLD (-1)
 312 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
 313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
 314     &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
 315
 316 /* 0 means chip/fw default, non-zero number is value in microseconds */
 317 static u_long t4_toe_keepalive_idle = 0;
 318 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
 319     &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
 320
 321 /* 0 means chip/fw default, non-zero number is value in microseconds */
 322 static u_long t4_toe_keepalive_interval = 0;
 323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
 324     &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
 325
 326 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
 327 static int t4_toe_keepalive_count = 0;
 328 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
 329     &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
 330
 331 /* 0 means chip/fw default, non-zero number is value in microseconds */
 332 static u_long t4_toe_rexmt_min = 0;
 333 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
 334     &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
 335
 336 /* 0 means chip/fw default, non-zero number is value in microseconds */
 337 static u_long t4_toe_rexmt_max = 0;
 338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
 339     &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
 340
 341 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
 342 static int t4_toe_rexmt_count = 0;
 343 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
 344     &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
 345
 346 /* -1 means chip/fw default, other values are raw backoff values to use */
 347 static int t4_toe_rexmt_backoff[16] = {
 348         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 349 };
 350 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
 351     "cxgbe(4) TOE retransmit backoff values");
 352 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
 353     &t4_toe_rexmt_backoff[0], 0, "");
 354 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
 355     &t4_toe_rexmt_backoff[1], 0, "");
 356 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
 357     &t4_toe_rexmt_backoff[2], 0, "");
 358 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
 359     &t4_toe_rexmt_backoff[3], 0, "");
 360 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
 361     &t4_toe_rexmt_backoff[4], 0, "");
 362 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
 363     &t4_toe_rexmt_backoff[5], 0, "");
 364 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
 365     &t4_toe_rexmt_backoff[6], 0, "");
 366 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
 367     &t4_toe_rexmt_backoff[7], 0, "");
 368 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
 369     &t4_toe_rexmt_backoff[8], 0, "");
 370 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
 371     &t4_toe_rexmt_backoff[9], 0, "");
 372 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
 373     &t4_toe_rexmt_backoff[10], 0, "");
 374 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
 375     &t4_toe_rexmt_backoff[11], 0, "");
 376 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
 377     &t4_toe_rexmt_backoff[12], 0, "");
 378 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
 379     &t4_toe_rexmt_backoff[13], 0, "");
 380 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
 381     &t4_toe_rexmt_backoff[14], 0, "");
 382 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
 383     &t4_toe_rexmt_backoff[15], 0, "");
 384 #endif
 385
 386 #ifdef DEV_NETMAP
 387 #define NNMTXQ_VI 2
 388 static int t4_nnmtxq_vi = -NNMTXQ_VI;
 389 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
 390     "Number of netmap TX queues per VI");
 391
 392 #define NNMRXQ_VI 2
 393 static int t4_nnmrxq_vi = -NNMRXQ_VI;
 394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
 395     "Number of netmap RX queues per VI");
 396 #endif
 397
 398 /*
 399  * Holdoff parameters for ports.
 400  */
 401 #define TMR_IDX 1
 402 int t4_tmr_idx = TMR_IDX;
 403 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
 404     0, "Holdoff timer index");
 405 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx);     /* Old name */
 406
 407 #define PKTC_IDX (-1)
 408 int t4_pktc_idx = PKTC_IDX;
 409 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
 410     0, "Holdoff packet counter index");
 411 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx);     /* Old name */
 412
 413 /*
 414  * Size (# of entries) of each tx and rx queue.
 415  */
 416 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
 417 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
 418     "Number of descriptors in each TX queue");
 419
 420 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
 421 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
 422     "Number of descriptors in each RX queue");
 423
 424 /*
 425  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
 426  */
 427 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
 428 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
 429     0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
 430
 431 /*
 432  * Configuration file.  All the _CF names here are special.
 433  */
 434 #define DEFAULT_CF      "default"
 435 #define BUILTIN_CF      "built-in"
 436 #define FLASH_CF        "flash"
 437 #define UWIRE_CF        "uwire"
 438 #define FPGA_CF         "fpga"
 439 static char t4_cfg_file[32] = DEFAULT_CF;
 440 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
 441     sizeof(t4_cfg_file), "Firmware configuration file");
 442
 443 /*
 444  * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
 445  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
 446  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
 447  *            mark or when signalled to do so, 0 to never emit PAUSE.
 448  * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
 449  *                 negotiated settings will override rx_pause/tx_pause.
 450  *                 Otherwise rx_pause/tx_pause are applied forcibly.
 451  */
 452 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
 453 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
 454     &t4_pause_settings, 0,
 455     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
 456
 457 /*
 458  * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
 459  * -1 to run with the firmware default.  Same as FEC_AUTO (bit 5)
 460  *  0 to disable FEC.
 461  */
 462 static int t4_fec = -1;
 463 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
 464     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
 465
 466 /*
 467  * Link autonegotiation.
 468  * -1 to run with the firmware default.
 469  *  0 to disable.
 470  *  1 to enable.
 471  */
 472 static int t4_autoneg = -1;
 473 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
 474     "Link autonegotiation");
 475
 476 /*
 477  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
 478  * encouraged respectively).
 479  */
 480 static unsigned int t4_fw_install = 1;
 481 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
 482     "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
 483
 484 /*
 485  * ASIC features that will be used.  Disable the ones you don't want so that the
 486  * chip resources aren't wasted on features that will not be used.
 487  */
 488 static int t4_nbmcaps_allowed = 0;
 489 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
 490     &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
 491
 492 static int t4_linkcaps_allowed = 0;     /* No DCBX, PPP, etc. by default */
 493 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
 494     &t4_linkcaps_allowed, 0, "Default link capabilities");
 495
 496 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
 497     FW_CAPS_CONFIG_SWITCH_EGRESS;
 498 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
 499     &t4_switchcaps_allowed, 0, "Default switch capabilities");
 500
 501 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
 502 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
 503     &t4_niccaps_allowed, 0, "Default NIC capabilities");
 504
 505 static int t4_toecaps_allowed = -1;
 506 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
 507     &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
 508
 509 static int t4_rdmacaps_allowed = -1;
 510 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
 511     &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
 512
 513 static int t4_cryptocaps_allowed = -1;
 514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
 515     &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
 516
 517 static int t4_iscsicaps_allowed = -1;
 518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
 519     &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
 520
 521 static int t4_fcoecaps_allowed = 0;
 522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
 523     &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
 524
 525 static int t5_write_combine = 0;
 526 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
 527     0, "Use WC instead of UC for BAR2");
 528
 529 static int t4_num_vis = 1;
 530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
 531     "Number of VIs per port");
 532
 533 /*
 534  * PCIe Relaxed Ordering.
 535  * -1: driver should figure out a good value.
 536  * 0: disable RO.
 537  * 1: enable RO.
 538  * 2: leave RO alone.
 539  */
 540 static int pcie_relaxed_ordering = -1;
 541 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
 542     &pcie_relaxed_ordering, 0,
 543     "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
 544
 545
 546 #ifdef TCP_OFFLOAD
 547 /*
 548  * TOE tunables.
 549  */
 550 static int t4_cop_managed_offloading = 0;
 551 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
 552 #endif
 553
 554 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
 555 static int vi_mac_funcs[] = {
 556         FW_VI_FUNC_ETH,
 557         FW_VI_FUNC_OFLD,
 558         FW_VI_FUNC_IWARP,
 559         FW_VI_FUNC_OPENISCSI,
 560         FW_VI_FUNC_OPENFCOE,
 561         FW_VI_FUNC_FOISCSI,
 562         FW_VI_FUNC_FOFCOE,
 563 };
 564
 565 struct intrs_and_queues {
 566         uint16_t intr_type;     /* INTx, MSI, or MSI-X */
 567         uint16_t num_vis;       /* number of VIs for each port */
 568         uint16_t nirq;          /* Total # of vectors */
 569         uint16_t ntxq;          /* # of NIC txq's for each port */
 570         uint16_t nrxq;          /* # of NIC rxq's for each port */
 571         uint16_t nofldtxq;      /* # of TOE txq's for each port */
 572         uint16_t nofldrxq;      /* # of TOE rxq's for each port */
 573
 574         /* The vcxgbe/vcxl interfaces use these and not the ones above. */
 575         uint16_t ntxq_vi;       /* # of NIC txq's */
 576         uint16_t nrxq_vi;       /* # of NIC rxq's */
 577         uint16_t nofldtxq_vi;   /* # of TOE txq's */
 578         uint16_t nofldrxq_vi;   /* # of TOE rxq's */
 579         uint16_t nnmtxq_vi;     /* # of netmap txq's */
 580         uint16_t nnmrxq_vi;     /* # of netmap rxq's */
 581 };
 582
 583 struct filter_entry {
 584         uint32_t valid:1;       /* filter allocated and valid */
 585         uint32_t locked:1;      /* filter is administratively locked */
 586         uint32_t pending:1;     /* filter action is pending firmware reply */
 587         uint32_t smtidx:8;      /* Source MAC Table index for smac */
 588         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 589
 590         struct t4_filter_specification fs;
 591 };
 592
 593 static void setup_memwin(struct adapter *);
 594 static void position_memwin(struct adapter *, int, uint32_t);
 595 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
 596 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
 597     int);
 598 static inline int write_via_memwin(struct adapter *, int, uint32_t,
 599     const uint32_t *, int);
 600 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
 601 static int fwmtype_to_hwmtype(int);
 602 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
 603     uint32_t *);
 604 static int fixup_devlog_params(struct adapter *);
 605 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
 606 static int prep_firmware(struct adapter *);
 607 static int partition_resources(struct adapter *, const struct firmware *,
 608     const char *);
 609 static int get_params__pre_init(struct adapter *);
 610 static int get_params__post_init(struct adapter *);
 611 static int set_params__post_init(struct adapter *);
 612 static void t4_set_desc(struct adapter *);
 613 static bool fixed_ifmedia(struct port_info *);
 614 static void build_medialist(struct port_info *);
 615 static void init_link_config(struct port_info *);
 616 static int fixup_link_config(struct port_info *);
 617 static int apply_link_config(struct port_info *);
 618 static int cxgbe_init_synchronized(struct vi_info *);
 619 static int cxgbe_uninit_synchronized(struct vi_info *);
 620 static void quiesce_txq(struct adapter *, struct sge_txq *);
 621 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
 622 static void quiesce_iq(struct adapter *, struct sge_iq *);
 623 static void quiesce_fl(struct adapter *, struct sge_fl *);
 624 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
 625     driver_intr_t *, void *, char *);
 626 static int t4_free_irq(struct adapter *, struct irq *);
 627 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
 628 static void vi_refresh_stats(struct adapter *, struct vi_info *);
 629 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
 630 static void cxgbe_tick(void *);
 631 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
 632 static void cxgbe_sysctls(struct port_info *);
 633 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
 634 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
 635 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
 636 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
 637 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
 638 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
 639 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
 640 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
 641 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
 642 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
 643 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
 644 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
 645 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
 646 #ifdef SBUF_DRAIN
 647 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
 648 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
 649 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
 650 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
 651 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
 652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
 653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
 654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
 655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
 656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
 657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
 658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
 659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
 660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
 661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
 662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
 663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
 664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
 665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
 666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
 667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
 668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
 669 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
 670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
 671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
 672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
 673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
 674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
 675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
 676 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
 677 #endif
 678 #ifdef TCP_OFFLOAD
 679 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
 680 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
 681 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
 682 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
 683 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
 684 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
 685 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
 686 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
 687 #endif
 688 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
 689 static uint32_t mode_to_fconf(uint32_t);
 690 static uint32_t mode_to_iconf(uint32_t);
 691 static int check_fspec_against_fconf_iconf(struct adapter *,
 692     struct t4_filter_specification *);
 693 static int get_filter_mode(struct adapter *, uint32_t *);
 694 static int set_filter_mode(struct adapter *, uint32_t);
 695 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
 696 static int get_filter(struct adapter *, struct t4_filter *);
 697 static int set_filter(struct adapter *, struct t4_filter *);
 698 static int del_filter(struct adapter *, struct t4_filter *);
 699 static void clear_filter(struct filter_entry *);
 700 static int set_filter_wr(struct adapter *, int);
 701 static int del_filter_wr(struct adapter *, int);
 702 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
 703     struct mbuf *);
 704 static int get_sge_context(struct adapter *, struct t4_sge_context *);
 705 static int load_fw(struct adapter *, struct t4_data *);
 706 static int load_cfg(struct adapter *, struct t4_data *);
 707 static int load_boot(struct adapter *, struct t4_bootrom *);
 708 static int load_bootcfg(struct adapter *, struct t4_data *);
 709 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
 710 static void free_offload_policy(struct t4_offload_policy *);
 711 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
 712 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
 713 static int read_i2c(struct adapter *, struct t4_i2c_data *);
 714 #ifdef TCP_OFFLOAD
 715 static int toe_capability(struct vi_info *, int);
 716 #endif
 717 static int mod_event(module_t, int, void *);
 718 static int notify_siblings(device_t, int);
 719
 720 struct {
 721         uint16_t device;
 722         char *desc;
 723 } t4_pciids[] = {
 724         {0xa000, "Chelsio Terminator 4 FPGA"},
 725         {0x4400, "Chelsio T440-dbg"},
 726         {0x4401, "Chelsio T420-CR"},
 727         {0x4402, "Chelsio T422-CR"},
 728         {0x4403, "Chelsio T440-CR"},
 729         {0x4404, "Chelsio T420-BCH"},
 730         {0x4405, "Chelsio T440-BCH"},
 731         {0x4406, "Chelsio T440-CH"},
 732         {0x4407, "Chelsio T420-SO"},
 733         {0x4408, "Chelsio T420-CX"},
 734         {0x4409, "Chelsio T420-BT"},
 735         {0x440a, "Chelsio T404-BT"},
 736         {0x440e, "Chelsio T440-LP-CR"},
 737 }, t5_pciids[] = {
 738         {0xb000, "Chelsio Terminator 5 FPGA"},
 739         {0x5400, "Chelsio T580-dbg"},
 740         {0x5401,  "Chelsio T520-CR"},           /* 2 x 10G */
 741         {0x5402,  "Chelsio T522-CR"},           /* 2 x 10G, 2 X 1G */
 742         {0x5403,  "Chelsio T540-CR"},           /* 4 x 10G */
 743         {0x5407,  "Chelsio T520-SO"},           /* 2 x 10G, nomem */
 744         {0x5409,  "Chelsio T520-BT"},           /* 2 x 10GBaseT */
 745         {0x540a,  "Chelsio T504-BT"},           /* 4 x 1G */
 746         {0x540d,  "Chelsio T580-CR"},           /* 2 x 40G */
 747         {0x540e,  "Chelsio T540-LP-CR"},        /* 4 x 10G */
 748         {0x5410,  "Chelsio T580-LP-CR"},        /* 2 x 40G */
 749         {0x5411,  "Chelsio T520-LL-CR"},        /* 2 x 10G */
 750         {0x5412,  "Chelsio T560-CR"},           /* 1 x 40G, 2 x 10G */
 751         {0x5414,  "Chelsio T580-LP-SO-CR"},     /* 2 x 40G, nomem */
 752         {0x5415,  "Chelsio T502-BT"},           /* 2 x 1G */
 753         {0x5418,  "Chelsio T540-BT"},           /* 4 x 10GBaseT */
 754         {0x5419,  "Chelsio T540-LP-BT"},        /* 4 x 10GBaseT */
 755         {0x541a,  "Chelsio T540-SO-BT"},        /* 4 x 10GBaseT, nomem */
 756         {0x541b,  "Chelsio T540-SO-CR"},        /* 4 x 10G, nomem */
 757
 758         /* Custom */
 759         {0x5483, "Custom T540-CR"},
 760         {0x5484, "Custom T540-BT"},
 761 }, t6_pciids[] = {
 762         {0xc006, "Chelsio Terminator 6 FPGA"},  /* T6 PE10K6 FPGA (PF0) */
 763         {0x6400, "Chelsio T6-DBG-25"},          /* 2 x 10/25G, debug */
 764         {0x6401, "Chelsio T6225-CR"},           /* 2 x 10/25G */
 765         {0x6402, "Chelsio T6225-SO-CR"},        /* 2 x 10/25G, nomem */
 766         {0x6403, "Chelsio T6425-CR"},           /* 4 x 10/25G */
 767         {0x6404, "Chelsio T6425-SO-CR"},        /* 4 x 10/25G, nomem */
 768         {0x6405, "Chelsio T6225-OCP-SO"},       /* 2 x 10/25G, nomem */
 769         {0x6406, "Chelsio T62100-OCP-SO"},      /* 2 x 40/50/100G, nomem */
 770         {0x6407, "Chelsio T62100-LP-CR"},       /* 2 x 40/50/100G */
 771         {0x6408, "Chelsio T62100-SO-CR"},       /* 2 x 40/50/100G, nomem */
 772         {0x6409, "Chelsio T6210-BT"},           /* 2 x 10GBASE-T */
 773         {0x640d, "Chelsio T62100-CR"},          /* 2 x 40/50/100G */
 774         {0x6410, "Chelsio T6-DBG-100"},         /* 2 x 40/50/100G, debug */
 775         {0x6411, "Chelsio T6225-LL-CR"},        /* 2 x 10/25G */
 776         {0x6414, "Chelsio T61100-OCP-SO"},      /* 1 x 40/50/100G, nomem */
 777         {0x6415, "Chelsio T6201-BT"},           /* 2 x 1000BASE-T */
 778
 779         /* Custom */
 780         {0x6480, "Custom T6225-CR"},
 781         {0x6481, "Custom T62100-CR"},
 782         {0x6482, "Custom T6225-CR"},
 783         {0x6483, "Custom T62100-CR"},
 784         {0x6484, "Custom T64100-CR"},
 785         {0x6485, "Custom T6240-SO"},
 786         {0x6486, "Custom T6225-SO-CR"},
 787         {0x6487, "Custom T6225-CR"},
 788 };
 789
 790 #ifdef TCP_OFFLOAD
 791 /*
 792  * service_iq() has an iq and needs the fl.  Offset of fl from the iq should be
 793  * exactly the same for both rxq and ofld_rxq.
 794  */
 795 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
 796 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
 797 #endif
 798 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
 799
 800 static int
 801 t4_probe(device_t dev)
 802 {
 803         int i;
 804         uint16_t v = pci_get_vendor(dev);
 805         uint16_t d = pci_get_device(dev);
 806         uint8_t f = pci_get_function(dev);
 807
 808         if (v != PCI_VENDOR_ID_CHELSIO)
 809                 return (ENXIO);
 810
 811         /* Attach only to PF0 of the FPGA */
 812         if (d == 0xa000 && f != 0)
 813                 return (ENXIO);
 814
 815         for (i = 0; i < nitems(t4_pciids); i++) {
 816                 if (d == t4_pciids[i].device) {
 817                         device_set_desc(dev, t4_pciids[i].desc);
 818                         return (BUS_PROBE_DEFAULT);
 819                 }
 820         }
 821
 822         return (ENXIO);
 823 }
 824
 825 static int
 826 t5_probe(device_t dev)
 827 {
 828         int i;
 829         uint16_t v = pci_get_vendor(dev);
 830         uint16_t d = pci_get_device(dev);
 831         uint8_t f = pci_get_function(dev);
 832
 833         if (v != PCI_VENDOR_ID_CHELSIO)
 834                 return (ENXIO);
 835
 836         /* Attach only to PF0 of the FPGA */
 837         if (d == 0xb000 && f != 0)
 838                 return (ENXIO);
 839
 840         for (i = 0; i < nitems(t5_pciids); i++) {
 841                 if (d == t5_pciids[i].device) {
 842                         device_set_desc(dev, t5_pciids[i].desc);
 843                         return (BUS_PROBE_DEFAULT);
 844                 }
 845         }
 846
 847         return (ENXIO);
 848 }
 849
 850 static int
 851 t6_probe(device_t dev)
 852 {
 853         int i;
 854         uint16_t v = pci_get_vendor(dev);
 855         uint16_t d = pci_get_device(dev);
 856
 857         if (v != PCI_VENDOR_ID_CHELSIO)
 858                 return (ENXIO);
 859
 860         for (i = 0; i < nitems(t6_pciids); i++) {
 861                 if (d == t6_pciids[i].device) {
 862                         device_set_desc(dev, t6_pciids[i].desc);
 863                         return (BUS_PROBE_DEFAULT);
 864                 }
 865         }
 866
 867         return (ENXIO);
 868 }
 869
 870 static void
 871 t5_attribute_workaround(device_t dev)
 872 {
 873         device_t root_port;
 874         uint32_t v;
 875
 876         /*
 877          * The T5 chips do not properly echo the No Snoop and Relaxed
 878          * Ordering attributes when replying to a TLP from a Root
 879          * Port.  As a workaround, find the parent Root Port and
 880          * disable No Snoop and Relaxed Ordering.  Note that this
 881          * affects all devices under this root port.
 882          */
 883         root_port = pci_find_pcie_root_port(dev);
 884         if (root_port == NULL) {
 885                 device_printf(dev, "Unable to find parent root port\n");
 886                 return;
 887         }
 888
 889         v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
 890             PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
 891         if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
 892             0)
 893                 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
 894                     device_get_nameunit(root_port));
 895 }
 896
 897 static const struct devnames devnames[] = {
 898         {
 899                 .nexus_name = "t4nex",
 900                 .ifnet_name = "cxgbe",
 901                 .vi_ifnet_name = "vcxgbe",
 902                 .pf03_drv_name = "t4iov",
 903                 .vf_nexus_name = "t4vf",
 904                 .vf_ifnet_name = "cxgbev"
 905         }, {
 906                 .nexus_name = "t5nex",
 907                 .ifnet_name = "cxl",
 908                 .vi_ifnet_name = "vcxl",
 909                 .pf03_drv_name = "t5iov",
 910                 .vf_nexus_name = "t5vf",
 911                 .vf_ifnet_name = "cxlv"
 912         }, {
 913                 .nexus_name = "t6nex",
 914                 .ifnet_name = "cc",
 915                 .vi_ifnet_name = "vcc",
 916                 .pf03_drv_name = "t6iov",
 917                 .vf_nexus_name = "t6vf",
 918                 .vf_ifnet_name = "ccv"
 919         }
 920 };
 921
 922 void
 923 t4_init_devnames(struct adapter *sc)
 924 {
 925         int id;
 926
 927         id = chip_id(sc);
 928         if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
 929                 sc->names = &devnames[id - CHELSIO_T4];
 930         else {
 931                 device_printf(sc->dev, "chip id %d is not supported.\n", id);
 932                 sc->names = NULL;
 933         }
 934 }
 935
 936 static int
 937 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
 938 {
 939         const char *parent, *name;
 940         long value;
 941         int line, unit;
 942
 943         line = 0;
 944         parent = device_get_nameunit(sc->dev);
 945         name = sc->names->ifnet_name;
 946         while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
 947                 if (resource_long_value(name, unit, "port", &value) == 0 &&
 948                     value == pi->port_id)
 949                         return (unit);
 950         }
 951         return (-1);
 952 }
 953
 954 static int
 955 t4_attach(device_t dev)
 956 {
 957         struct adapter *sc;
 958         int rc = 0, i, j, rqidx, tqidx, nports;
 959         struct make_dev_args mda;
 960         struct intrs_and_queues iaq;
 961         struct sge *s;
 962         uint32_t *buf;
 963 #ifdef TCP_OFFLOAD
 964         int ofld_rqidx, ofld_tqidx;
 965 #endif
 966 #ifdef DEV_NETMAP
 967         int nm_rqidx, nm_tqidx;
 968 #endif
 969         int num_vis;
 970
 971         sc = device_get_softc(dev);
 972         sc->dev = dev;
 973         TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
 974
 975         if ((pci_get_device(dev) & 0xff00) == 0x5400)
 976                 t5_attribute_workaround(dev);
 977         pci_enable_busmaster(dev);
 978         if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
 979                 uint32_t v;
 980
 981                 pci_set_max_read_req(dev, 4096);
 982                 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
 983                 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
 984                 if (pcie_relaxed_ordering == 0 &&
 985                     (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
 986                         v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
 987                         pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
 988                 } else if (pcie_relaxed_ordering == 1 &&
 989                     (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
 990                         v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
 991                         pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
 992                 }
 993         }
 994
 995         sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
 996         sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
 997         sc->traceq = -1;
 998         mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
 999         snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1000             device_get_nameunit(dev));
1001
1002         snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1003             device_get_nameunit(dev));
1004         mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1005         t4_add_adapter(sc);
1006
1007         mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1008         TAILQ_INIT(&sc->sfl);
1009         callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1010
1011         mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1012
1013         sc->policy = NULL;
1014         rw_init(&sc->policy_lock, "connection offload policy");
1015
1016         rc = t4_map_bars_0_and_4(sc);
1017         if (rc != 0)
1018                 goto done; /* error message displayed already */
1019
1020         memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1021
1022         /* Prepare the adapter for operation. */
1023         buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1024         rc = -t4_prep_adapter(sc, buf);
1025         free(buf, M_CXGBE);
1026         if (rc != 0) {
1027                 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1028                 goto done;
1029         }
1030
1031         /*
1032          * This is the real PF# to which we're attaching.  Works from within PCI
1033          * passthrough environments too, where pci_get_function() could return a
1034          * different PF# depending on the passthrough configuration.  We need to
1035          * use the real PF# in all our communication with the firmware.
1036          */
1037         j = t4_read_reg(sc, A_PL_WHOAMI);
1038         sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1039         sc->mbox = sc->pf;
1040
1041         t4_init_devnames(sc);
1042         if (sc->names == NULL) {
1043                 rc = ENOTSUP;
1044                 goto done; /* error message displayed already */
1045         }
1046
1047         /*
1048          * Do this really early, with the memory windows set up even before the
1049          * character device.  The userland tool's register i/o and mem read
1050          * will work even in "recovery mode".
1051          */
1052         setup_memwin(sc);
1053         if (t4_init_devlog_params(sc, 0) == 0)
1054                 fixup_devlog_params(sc);
1055         make_dev_args_init(&mda);
1056         mda.mda_devsw = &t4_cdevsw;
1057         mda.mda_uid = UID_ROOT;
1058         mda.mda_gid = GID_WHEEL;
1059         mda.mda_mode = 0600;
1060         mda.mda_si_drv1 = sc;
1061         rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1062         if (rc != 0)
1063                 device_printf(dev, "failed to create nexus char device: %d.\n",
1064                     rc);
1065
1066         /* Go no further if recovery mode has been requested. */
1067         if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1068                 device_printf(dev, "recovery mode.\n");
1069                 goto done;
1070         }
1071
1072 #if defined(__i386__)
1073         if ((cpu_feature & CPUID_CX8) == 0) {
1074                 device_printf(dev, "64 bit atomics not available.\n");
1075                 rc = ENOTSUP;
1076                 goto done;
1077         }
1078 #endif
1079
1080         /* Prepare the firmware for operation */
1081         rc = prep_firmware(sc);
1082         if (rc != 0)
1083                 goto done; /* error message displayed already */
1084
1085         rc = get_params__post_init(sc);
1086         if (rc != 0)
1087                 goto done; /* error message displayed already */
1088
1089         rc = set_params__post_init(sc);
1090         if (rc != 0)
1091                 goto done; /* error message displayed already */
1092
1093         rc = t4_map_bar_2(sc);
1094         if (rc != 0)
1095                 goto done; /* error message displayed already */
1096
1097         rc = t4_create_dma_tag(sc);
1098         if (rc != 0)
1099                 goto done; /* error message displayed already */
1100
1101         /*
1102          * First pass over all the ports - allocate VIs and initialize some
1103          * basic parameters like mac address, port type, etc.
1104          */
1105         for_each_port(sc, i) {
1106                 struct port_info *pi;
1107
1108                 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1109                 sc->port[i] = pi;
1110
1111                 /* These must be set before t4_port_init */
1112                 pi->adapter = sc;
1113                 pi->port_id = i;
1114                 /*
1115                  * XXX: vi[0] is special so we can't delay this allocation until
1116                  * pi->nvi's final value is known.
1117                  */
1118                 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1119                     M_ZERO | M_WAITOK);
1120
1121                 /*
1122                  * Allocate the "main" VI and initialize parameters
1123                  * like mac addr.
1124                  */
1125                 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1126                 if (rc != 0) {
1127                         device_printf(dev, "unable to initialize port %d: %d\n",
1128                             i, rc);
1129                         free(pi->vi, M_CXGBE);
1130                         free(pi, M_CXGBE);
1131                         sc->port[i] = NULL;
1132                         goto done;
1133                 }
1134
1135                 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1136                     device_get_nameunit(dev), i);
1137                 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1138                 sc->chan_map[pi->tx_chan] = i;
1139
1140                 /* All VIs on this port share this media. */
1141                 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1142                     cxgbe_media_status);
1143
1144                 PORT_LOCK(pi);
1145                 init_link_config(pi);
1146                 fixup_link_config(pi);
1147                 build_medialist(pi);
1148                 if (fixed_ifmedia(pi))
1149                         pi->flags |= FIXED_IFMEDIA;
1150                 PORT_UNLOCK(pi);
1151
1152                 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1153                     t4_ifnet_unit(sc, pi));
1154                 if (pi->dev == NULL) {
1155                         device_printf(dev,
1156                             "failed to add device for port %d.\n", i);
1157                         rc = ENXIO;
1158                         goto done;
1159                 }
1160                 pi->vi[0].dev = pi->dev;
1161                 device_set_softc(pi->dev, pi);
1162         }
1163
1164         /*
1165          * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1166          */
1167         nports = sc->params.nports;
1168         rc = cfg_itype_and_nqueues(sc, &iaq);
1169         if (rc != 0)
1170                 goto done; /* error message displayed already */
1171
1172         num_vis = iaq.num_vis;
1173         sc->intr_type = iaq.intr_type;
1174         sc->intr_count = iaq.nirq;
1175
1176         s = &sc->sge;
1177         s->nrxq = nports * iaq.nrxq;
1178         s->ntxq = nports * iaq.ntxq;
1179         if (num_vis > 1) {
1180                 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1181                 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1182         }
1183         s->neq = s->ntxq + s->nrxq;     /* the free list in an rxq is an eq */
1184         s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1185         s->niq = s->nrxq + 1;           /* 1 extra for firmware event queue */
1186 #ifdef TCP_OFFLOAD
1187         if (is_offload(sc)) {
1188                 s->nofldrxq = nports * iaq.nofldrxq;
1189                 s->nofldtxq = nports * iaq.nofldtxq;
1190                 if (num_vis > 1) {
1191                         s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1192                         s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1193                 }
1194                 s->neq += s->nofldtxq + s->nofldrxq;
1195                 s->niq += s->nofldrxq;
1196
1197                 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1198                     M_CXGBE, M_ZERO | M_WAITOK);
1199                 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1200                     M_CXGBE, M_ZERO | M_WAITOK);
1201         }
1202 #endif
1203 #ifdef DEV_NETMAP
1204         if (num_vis > 1) {
1205                 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1206                 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1207         }
1208         s->neq += s->nnmtxq + s->nnmrxq;
1209         s->niq += s->nnmrxq;
1210
1211         s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1212             M_CXGBE, M_ZERO | M_WAITOK);
1213         s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1214             M_CXGBE, M_ZERO | M_WAITOK);
1215 #endif
1216
1217         s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1218             M_ZERO | M_WAITOK);
1219         s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1220             M_ZERO | M_WAITOK);
1221         s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1222             M_ZERO | M_WAITOK);
1223         s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1224             M_ZERO | M_WAITOK);
1225         s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1226             M_ZERO | M_WAITOK);
1227
1228         sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1229             M_ZERO | M_WAITOK);
1230
1231         t4_init_l2t(sc, M_WAITOK);
1232         t4_init_tx_sched(sc);
1233         if (sc->vres.key.size != 0)
1234                 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1235                     sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1236
1237         /*
1238          * Second pass over the ports.  This time we know the number of rx and
1239          * tx queues that each port should get.
1240          */
1241         rqidx = tqidx = 0;
1242 #ifdef TCP_OFFLOAD
1243         ofld_rqidx = ofld_tqidx = 0;
1244 #endif
1245 #ifdef DEV_NETMAP
1246         nm_rqidx = nm_tqidx = 0;
1247 #endif
1248         for_each_port(sc, i) {
1249                 struct port_info *pi = sc->port[i];
1250                 struct vi_info *vi;
1251
1252                 if (pi == NULL)
1253                         continue;
1254
1255                 pi->nvi = num_vis;
1256                 for_each_vi(pi, j, vi) {
1257                         vi->pi = pi;
1258                         vi->qsize_rxq = t4_qsize_rxq;
1259                         vi->qsize_txq = t4_qsize_txq;
1260
1261                         vi->first_rxq = rqidx;
1262                         vi->first_txq = tqidx;
1263                         vi->tmr_idx = t4_tmr_idx;
1264                         vi->pktc_idx = t4_pktc_idx;
1265                         vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1266                         vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1267
1268                         rqidx += vi->nrxq;
1269                         tqidx += vi->ntxq;
1270
1271                         if (j == 0 && vi->ntxq > 1)
1272                                 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1273                         else
1274                                 vi->rsrv_noflowq = 0;
1275
1276 #ifdef TCP_OFFLOAD
1277                         vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1278                         vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1279                         vi->first_ofld_rxq = ofld_rqidx;
1280                         vi->first_ofld_txq = ofld_tqidx;
1281                         vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1282                         vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1283
1284                         ofld_rqidx += vi->nofldrxq;
1285                         ofld_tqidx += vi->nofldtxq;
1286 #endif
1287 #ifdef DEV_NETMAP
1288                         if (j > 0) {
1289                                 vi->first_nm_rxq = nm_rqidx;
1290                                 vi->first_nm_txq = nm_tqidx;
1291                                 vi->nnmrxq = iaq.nnmrxq_vi;
1292                                 vi->nnmtxq = iaq.nnmtxq_vi;
1293                                 nm_rqidx += vi->nnmrxq;
1294                                 nm_tqidx += vi->nnmtxq;
1295                         }
1296 #endif
1297                 }
1298         }
1299
1300         rc = t4_setup_intr_handlers(sc);
1301         if (rc != 0) {
1302                 device_printf(dev,
1303                     "failed to setup interrupt handlers: %d\n", rc);
1304                 goto done;
1305         }
1306
1307         rc = bus_generic_probe(dev);
1308         if (rc != 0) {
1309                 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1310                 goto done;
1311         }
1312
1313         /*
1314          * Ensure thread-safe mailbox access (in debug builds).
1315          *
1316          * So far this was the only thread accessing the mailbox but various
1317          * ifnets and sysctls are about to be created and their handlers/ioctls
1318          * will access the mailbox from different threads.
1319          */
1320         sc->flags |= CHK_MBOX_ACCESS;
1321
1322         rc = bus_generic_attach(dev);
1323         if (rc != 0) {
1324                 device_printf(dev,
1325                     "failed to attach all child ports: %d\n", rc);
1326                 goto done;
1327         }
1328
1329         device_printf(dev,
1330             "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1331             sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1332             sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1333             (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1334             sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1335
1336         t4_set_desc(sc);
1337
1338         notify_siblings(dev, 0);
1339
1340 done:
1341         if (rc != 0 && sc->cdev) {
1342                 /* cdev was created and so cxgbetool works; recover that way. */
1343                 device_printf(dev,
1344                     "error during attach, adapter is now in recovery mode.\n");
1345                 rc = 0;
1346         }
1347
1348         if (rc != 0)
1349                 t4_detach_common(dev);
1350         else
1351                 t4_sysctls(sc);
1352
1353         return (rc);
1354 }
1355
1356 static int
1357 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1358 {
1359         struct adapter *sc;
1360         struct port_info *pi;
1361         int i;
1362
1363         sc = device_get_softc(bus);
1364         buf[0] = '\0';
1365         for_each_port(sc, i) {
1366                 pi = sc->port[i];
1367                 if (pi != NULL && pi->dev == dev) {
1368                         snprintf(buf, buflen, "port=%d", pi->port_id);
1369                         break;
1370                 }
1371         }
1372         return (0);
1373 }
1374
1375 static int
1376 t4_ready(device_t dev)
1377 {
1378         struct adapter *sc;
1379
1380         sc = device_get_softc(dev);
1381         if (sc->flags & FW_OK)
1382                 return (0);
1383         return (ENXIO);
1384 }
1385
1386 static int
1387 t4_read_port_device(device_t dev, int port, device_t *child)
1388 {
1389         struct adapter *sc;
1390         struct port_info *pi;
1391
1392         sc = device_get_softc(dev);
1393         if (port < 0 || port >= MAX_NPORTS)
1394                 return (EINVAL);
1395         pi = sc->port[port];
1396         if (pi == NULL || pi->dev == NULL)
1397                 return (ENXIO);
1398         *child = pi->dev;
1399         return (0);
1400 }
1401
1402 static int
1403 notify_siblings(device_t dev, int detaching)
1404 {
1405         device_t sibling;
1406         int error, i;
1407
1408         error = 0;
1409         for (i = 0; i < PCI_FUNCMAX; i++) {
1410                 if (i == pci_get_function(dev))
1411                         continue;
1412                 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1413                     pci_get_slot(dev), i);
1414                 if (sibling == NULL || !device_is_attached(sibling))
1415                         continue;
1416                 if (detaching)
1417                         error = T4_DETACH_CHILD(sibling);
1418                 else
1419                         (void)T4_ATTACH_CHILD(sibling);
1420                 if (error)
1421                         break;
1422         }
1423         return (error);
1424 }
1425
1426 /*
1427  * Idempotent
1428  */
1429 static int
1430 t4_detach(device_t dev)
1431 {
1432         struct adapter *sc;
1433         int rc;
1434
1435         sc = device_get_softc(dev);
1436
1437         rc = notify_siblings(dev, 1);
1438         if (rc) {
1439                 device_printf(dev,
1440                     "failed to detach sibling devices: %d\n", rc);
1441                 return (rc);
1442         }
1443
1444         return (t4_detach_common(dev));
1445 }
1446
1447 int
1448 t4_detach_common(device_t dev)
1449 {
1450         struct adapter *sc;
1451         struct port_info *pi;
1452         int i, rc;
1453
1454         sc = device_get_softc(dev);
1455
1456         if (sc->cdev) {
1457                 destroy_dev(sc->cdev);
1458                 sc->cdev = NULL;
1459         }
1460
1461         sc->flags &= ~CHK_MBOX_ACCESS;
1462         if (sc->flags & FULL_INIT_DONE) {
1463                 if (!(sc->flags & IS_VF))
1464                         t4_intr_disable(sc);
1465         }
1466
1467         if (device_is_attached(dev)) {
1468                 rc = bus_generic_detach(dev);
1469                 if (rc) {
1470                         device_printf(dev,
1471                             "failed to detach child devices: %d\n", rc);
1472                         return (rc);
1473                 }
1474         }
1475
1476         for (i = 0; i < sc->intr_count; i++)
1477                 t4_free_irq(sc, &sc->irq[i]);
1478
1479         if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1480                 t4_free_tx_sched(sc);
1481
1482         for (i = 0; i < MAX_NPORTS; i++) {
1483                 pi = sc->port[i];
1484                 if (pi) {
1485                         t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1486                         if (pi->dev)
1487                                 device_delete_child(dev, pi->dev);
1488
1489                         mtx_destroy(&pi->pi_lock);
1490                         free(pi->vi, M_CXGBE);
1491                         free(pi, M_CXGBE);
1492                 }
1493         }
1494
1495         device_delete_children(dev);
1496
1497         if (sc->flags & FULL_INIT_DONE)
1498                 adapter_full_uninit(sc);
1499
1500         if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1501                 t4_fw_bye(sc, sc->mbox);
1502
1503         if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1504                 pci_release_msi(dev);
1505
1506         if (sc->regs_res)
1507                 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1508                     sc->regs_res);
1509
1510         if (sc->udbs_res)
1511                 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1512                     sc->udbs_res);
1513
1514         if (sc->msix_res)
1515                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1516                     sc->msix_res);
1517
1518         if (sc->l2t)
1519                 t4_free_l2t(sc->l2t);
1520         if (sc->key_map)
1521                 vmem_destroy(sc->key_map);
1522
1523 #ifdef TCP_OFFLOAD
1524         free(sc->sge.ofld_rxq, M_CXGBE);
1525         free(sc->sge.ofld_txq, M_CXGBE);
1526 #endif
1527 #ifdef DEV_NETMAP
1528         free(sc->sge.nm_rxq, M_CXGBE);
1529         free(sc->sge.nm_txq, M_CXGBE);
1530 #endif
1531         free(sc->irq, M_CXGBE);
1532         free(sc->sge.rxq, M_CXGBE);
1533         free(sc->sge.txq, M_CXGBE);
1534         free(sc->sge.ctrlq, M_CXGBE);
1535         free(sc->sge.iqmap, M_CXGBE);
1536         free(sc->sge.eqmap, M_CXGBE);
1537         free(sc->tids.ftid_tab, M_CXGBE);
1538         free(sc->tt.tls_rx_ports, M_CXGBE);
1539         t4_destroy_dma_tag(sc);
1540         if (mtx_initialized(&sc->sc_lock)) {
1541                 sx_xlock(&t4_list_lock);
1542                 SLIST_REMOVE(&t4_list, sc, adapter, link);
1543                 sx_xunlock(&t4_list_lock);
1544                 mtx_destroy(&sc->sc_lock);
1545         }
1546
1547         callout_drain(&sc->sfl_callout);
1548         if (mtx_initialized(&sc->tids.ftid_lock))
1549                 mtx_destroy(&sc->tids.ftid_lock);
1550         if (mtx_initialized(&sc->sfl_lock))
1551                 mtx_destroy(&sc->sfl_lock);
1552         if (mtx_initialized(&sc->ifp_lock))
1553                 mtx_destroy(&sc->ifp_lock);
1554         if (mtx_initialized(&sc->reg_lock))
1555                 mtx_destroy(&sc->reg_lock);
1556
1557         if (rw_initialized(&sc->policy_lock)) {
1558                 rw_destroy(&sc->policy_lock);
1559 #ifdef TCP_OFFLOAD
1560                 if (sc->policy != NULL)
1561                         free_offload_policy(sc->policy);
1562 #endif
1563         }
1564
1565         for (i = 0; i < NUM_MEMWIN; i++) {
1566                 struct memwin *mw = &sc->memwin[i];
1567
1568                 if (rw_initialized(&mw->mw_lock))
1569                         rw_destroy(&mw->mw_lock);
1570         }
1571
1572         bzero(sc, sizeof(*sc));
1573
1574         return (0);
1575 }
1576
1577 static int
1578 cxgbe_probe(device_t dev)
1579 {
1580         char buf[128];
1581         struct port_info *pi = device_get_softc(dev);
1582
1583         snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1584         device_set_desc_copy(dev, buf);
1585
1586         return (BUS_PROBE_DEFAULT);
1587 }
1588
1589 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1590     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1591     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1592 #define T4_CAP_ENABLE (T4_CAP)
1593
1594 static int
1595 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1596 {
1597         struct ifnet *ifp;
1598         struct sbuf *sb;
1599
1600         vi->xact_addr_filt = -1;
1601         callout_init(&vi->tick, 1);
1602
1603         /* Allocate an ifnet and set it up */
1604         ifp = if_alloc(IFT_ETHER);
1605         if (ifp == NULL) {
1606                 device_printf(dev, "Cannot allocate ifnet\n");
1607                 return (ENOMEM);
1608         }
1609         vi->ifp = ifp;
1610         ifp->if_softc = vi;
1611
1612         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1613         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1614
1615         ifp->if_init = cxgbe_init;
1616         ifp->if_ioctl = cxgbe_ioctl;
1617         ifp->if_transmit = cxgbe_transmit;
1618         ifp->if_qflush = cxgbe_qflush;
1619         ifp->if_get_counter = cxgbe_get_counter;
1620
1621         ifp->if_capabilities = T4_CAP;
1622 #ifdef TCP_OFFLOAD
1623         if (vi->nofldrxq != 0)
1624                 ifp->if_capabilities |= IFCAP_TOE;
1625 #endif
1626         ifp->if_capenable = T4_CAP_ENABLE;
1627         ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1628             CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1629
1630         ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1631         ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1632         ifp->if_hw_tsomaxsegsize = 65536;
1633
1634         vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1635             EVENTHANDLER_PRI_ANY);
1636
1637         ether_ifattach(ifp, vi->hw_addr);
1638 #ifdef DEV_NETMAP
1639         if (vi->nnmrxq != 0)
1640                 cxgbe_nm_attach(vi);
1641 #endif
1642         sb = sbuf_new_auto();
1643         sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1644 #ifdef TCP_OFFLOAD
1645         if (ifp->if_capabilities & IFCAP_TOE)
1646                 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1647                     vi->nofldtxq, vi->nofldrxq);
1648 #endif
1649 #ifdef DEV_NETMAP
1650         if (ifp->if_capabilities & IFCAP_NETMAP)
1651                 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1652                     vi->nnmtxq, vi->nnmrxq);
1653 #endif
1654         sbuf_finish(sb);
1655         device_printf(dev, "%s\n", sbuf_data(sb));
1656         sbuf_delete(sb);
1657
1658         vi_sysctls(vi);
1659
1660         return (0);
1661 }
1662
1663 static int
1664 cxgbe_attach(device_t dev)
1665 {
1666         struct port_info *pi = device_get_softc(dev);
1667         struct adapter *sc = pi->adapter;
1668         struct vi_info *vi;
1669         int i, rc;
1670
1671         callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1672
1673         rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1674         if (rc)
1675                 return (rc);
1676
1677         for_each_vi(pi, i, vi) {
1678                 if (i == 0)
1679                         continue;
1680                 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1681                 if (vi->dev == NULL) {
1682                         device_printf(dev, "failed to add VI %d\n", i);
1683                         continue;
1684                 }
1685                 device_set_softc(vi->dev, vi);
1686         }
1687
1688         cxgbe_sysctls(pi);
1689
1690         bus_generic_attach(dev);
1691
1692         return (0);
1693 }
1694
1695 static void
1696 cxgbe_vi_detach(struct vi_info *vi)
1697 {
1698         struct ifnet *ifp = vi->ifp;
1699
1700         ether_ifdetach(ifp);
1701
1702         if (vi->vlan_c)
1703                 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1704
1705         /* Let detach proceed even if these fail. */
1706 #ifdef DEV_NETMAP
1707         if (ifp->if_capabilities & IFCAP_NETMAP)
1708                 cxgbe_nm_detach(vi);
1709 #endif
1710         cxgbe_uninit_synchronized(vi);
1711         callout_drain(&vi->tick);
1712         vi_full_uninit(vi);
1713
1714         if_free(vi->ifp);
1715         vi->ifp = NULL;
1716 }
1717
1718 static int
1719 cxgbe_detach(device_t dev)
1720 {
1721         struct port_info *pi = device_get_softc(dev);
1722         struct adapter *sc = pi->adapter;
1723         int rc;
1724
1725         /* Detach the extra VIs first. */
1726         rc = bus_generic_detach(dev);
1727         if (rc)
1728                 return (rc);
1729         device_delete_children(dev);
1730
1731         doom_vi(sc, &pi->vi[0]);
1732
1733         if (pi->flags & HAS_TRACEQ) {
1734                 sc->traceq = -1;        /* cloner should not create ifnet */
1735                 t4_tracer_port_detach(sc);
1736         }
1737
1738         cxgbe_vi_detach(&pi->vi[0]);
1739         callout_drain(&pi->tick);
1740         ifmedia_removeall(&pi->media);
1741
1742         end_synchronized_op(sc, 0);
1743
1744         return (0);
1745 }
1746
1747 static void
1748 cxgbe_init(void *arg)
1749 {
1750         struct vi_info *vi = arg;
1751         struct adapter *sc = vi->pi->adapter;
1752
1753         if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1754                 return;
1755         cxgbe_init_synchronized(vi);
1756         end_synchronized_op(sc, 0);
1757 }
1758
1759 static int
1760 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1761 {
1762         int rc = 0, mtu, can_sleep, if_flags, if_drv_flags, vi_if_flags;
1763         struct vi_info *vi = ifp->if_softc;
1764         struct port_info *pi = vi->pi;
1765         struct adapter *sc = pi->adapter;
1766         struct ifreq *ifr = (struct ifreq *)data;
1767         uint32_t mask;
1768
1769         switch (cmd) {
1770         case SIOCSIFMTU:
1771                 mtu = ifr->ifr_mtu;
1772                 if (mtu < ETHERMIN || mtu > MAX_MTU)
1773                         return (EINVAL);
1774
1775                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1776                 if (rc)
1777                         return (rc);
1778                 ifp->if_mtu = mtu;
1779                 if (vi->flags & VI_INIT_DONE) {
1780                         t4_update_fl_bufsize(ifp);
1781                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1782                                 rc = update_mac_settings(ifp, XGMAC_MTU);
1783                 }
1784                 end_synchronized_op(sc, 0);
1785                 break;
1786
1787         case SIOCSIFFLAGS:
1788                 /*
1789                  * Decide what to do, with the port lock held.
1790                  */
1791                 PORT_LOCK(pi);
1792                 if_flags = ifp->if_flags;
1793                 if_drv_flags = ifp->if_drv_flags;
1794                 vi_if_flags = vi->if_flags;
1795                 if (if_flags & IFF_UP && if_drv_flags & IFF_DRV_RUNNING &&
1796                     (vi_if_flags ^ if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) {
1797                         can_sleep = 0;
1798                 } else {
1799                         can_sleep = 1;
1800                 }
1801                 PORT_UNLOCK(pi);
1802
1803                 /*
1804                  * ifp/vi flags may change here but we'll just do what our local
1805                  * copy of the flags indicates and then update the driver owned
1806                  * ifp/vi flags (in a synch-op and with the port lock held) to
1807                  * reflect what we did.
1808                  */
1809
1810                 rc = begin_synchronized_op(sc, vi,
1811                     can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1812                 if (rc) {
1813                         if_printf(ifp, "%ssleepable synch operation failed: %d."
1814                             "  if_flags 0x%08x, if_drv_flags 0x%08x\n",
1815                             can_sleep ? "" : "non-", rc, if_flags,
1816                             if_drv_flags);
1817                         return (rc);
1818                 }
1819
1820                 if (if_flags & IFF_UP) {
1821                         if (if_drv_flags & IFF_DRV_RUNNING) {
1822                                 if ((if_flags ^ vi_if_flags) &
1823                                     (IFF_PROMISC | IFF_ALLMULTI)) {
1824                                         MPASS(can_sleep == 0);
1825                                         rc = update_mac_settings(ifp,
1826                                             XGMAC_PROMISC | XGMAC_ALLMULTI);
1827                                 }
1828                         } else {
1829                                 MPASS(can_sleep == 1);
1830                                 rc = cxgbe_init_synchronized(vi);
1831                         }
1832                 } else if (if_drv_flags & IFF_DRV_RUNNING) {
1833                         MPASS(can_sleep == 1);
1834                         rc = cxgbe_uninit_synchronized(vi);
1835                 }
1836                 PORT_LOCK(pi);
1837                 vi->if_flags = if_flags;
1838                 PORT_UNLOCK(pi);
1839                 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1840                 break;
1841
1842         case SIOCADDMULTI:
1843         case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1844                 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1845                 if (rc)
1846                         return (rc);
1847                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1848                         rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1849                 end_synchronized_op(sc, LOCK_HELD);
1850                 break;
1851
1852         case SIOCSIFCAP:
1853                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1854                 if (rc)
1855                         return (rc);
1856
1857                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1858                 if (mask & IFCAP_TXCSUM) {
1859                         ifp->if_capenable ^= IFCAP_TXCSUM;
1860                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1861
1862                         if (IFCAP_TSO4 & ifp->if_capenable &&
1863                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1864                                 ifp->if_capenable &= ~IFCAP_TSO4;
1865                                 if_printf(ifp,
1866                                     "tso4 disabled due to -txcsum.\n");
1867                         }
1868                 }
1869                 if (mask & IFCAP_TXCSUM_IPV6) {
1870                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1871                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1872
1873                         if (IFCAP_TSO6 & ifp->if_capenable &&
1874                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1875                                 ifp->if_capenable &= ~IFCAP_TSO6;
1876                                 if_printf(ifp,
1877                                     "tso6 disabled due to -txcsum6.\n");
1878                         }
1879                 }
1880                 if (mask & IFCAP_RXCSUM)
1881                         ifp->if_capenable ^= IFCAP_RXCSUM;
1882                 if (mask & IFCAP_RXCSUM_IPV6)
1883                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1884
1885                 /*
1886                  * Note that we leave CSUM_TSO alone (it is always set).  The
1887                  * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1888                  * sending a TSO request our way, so it's sufficient to toggle
1889                  * IFCAP_TSOx only.
1890                  */
1891                 if (mask & IFCAP_TSO4) {
1892                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1893                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1894                                 if_printf(ifp, "enable txcsum first.\n");
1895                                 rc = EAGAIN;
1896                                 goto fail;
1897                         }
1898                         ifp->if_capenable ^= IFCAP_TSO4;
1899                 }
1900                 if (mask & IFCAP_TSO6) {
1901                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1902                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1903                                 if_printf(ifp, "enable txcsum6 first.\n");
1904                                 rc = EAGAIN;
1905                                 goto fail;
1906                         }
1907                         ifp->if_capenable ^= IFCAP_TSO6;
1908                 }
1909                 if (mask & IFCAP_LRO) {
1910 #if defined(INET) || defined(INET6)
1911                         int i;
1912                         struct sge_rxq *rxq;
1913
1914                         ifp->if_capenable ^= IFCAP_LRO;
1915                         for_each_rxq(vi, i, rxq) {
1916                                 if (ifp->if_capenable & IFCAP_LRO)
1917                                         rxq->iq.flags |= IQ_LRO_ENABLED;
1918                                 else
1919                                         rxq->iq.flags &= ~IQ_LRO_ENABLED;
1920                         }
1921 #endif
1922                 }
1923 #ifdef TCP_OFFLOAD
1924                 if (mask & IFCAP_TOE) {
1925                         int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1926
1927                         rc = toe_capability(vi, enable);
1928                         if (rc != 0)
1929                                 goto fail;
1930
1931                         ifp->if_capenable ^= mask;
1932                 }
1933 #endif
1934                 if (mask & IFCAP_VLAN_HWTAGGING) {
1935                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1936                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1937                                 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1938                 }
1939                 if (mask & IFCAP_VLAN_MTU) {
1940                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
1941
1942                         /* Need to find out how to disable auto-mtu-inflation */
1943                 }
1944                 if (mask & IFCAP_VLAN_HWTSO)
1945                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1946                 if (mask & IFCAP_VLAN_HWCSUM)
1947                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1948
1949 #ifdef VLAN_CAPABILITIES
1950                 VLAN_CAPABILITIES(ifp);
1951 #endif
1952 fail:
1953                 end_synchronized_op(sc, 0);
1954                 break;
1955
1956         case SIOCSIFMEDIA:
1957         case SIOCGIFMEDIA:
1958         case SIOCGIFXMEDIA:
1959                 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1960                 break;
1961
1962         case SIOCGI2C: {
1963                 struct ifi2creq i2c;
1964
1965                 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
1966                 if (rc != 0)
1967                         break;
1968                 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1969                         rc = EPERM;
1970                         break;
1971                 }
1972                 if (i2c.len > sizeof(i2c.data)) {
1973                         rc = EINVAL;
1974                         break;
1975                 }
1976                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1977                 if (rc)
1978                         return (rc);
1979                 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1980                     i2c.offset, i2c.len, &i2c.data[0]);
1981                 end_synchronized_op(sc, 0);
1982                 if (rc == 0)
1983                         rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
1984                 break;
1985         }
1986
1987         default:
1988                 rc = ether_ioctl(ifp, cmd, data);
1989         }
1990
1991         return (rc);
1992 }
1993
1994 static int
1995 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1996 {
1997         struct vi_info *vi = ifp->if_softc;
1998         struct port_info *pi = vi->pi;
1999         struct adapter *sc = pi->adapter;
2000         struct sge_txq *txq;
2001         void *items[1];
2002         int rc;
2003
2004         M_ASSERTPKTHDR(m);
2005         MPASS(m->m_nextpkt == NULL);    /* not quite ready for this yet */
2006
2007         if (__predict_false(pi->link_cfg.link_ok == false)) {
2008                 m_freem(m);
2009                 return (ENETDOWN);
2010         }
2011
2012         rc = parse_pkt(sc, &m);
2013         if (__predict_false(rc != 0)) {
2014                 MPASS(m == NULL);                       /* was freed already */
2015                 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2016                 return (rc);
2017         }
2018
2019         /* Select a txq. */
2020         txq = &sc->sge.txq[vi->first_txq];
2021         if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2022                 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2023                     vi->rsrv_noflowq);
2024
2025         items[0] = m;
2026         rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2027         if (__predict_false(rc != 0))
2028                 m_freem(m);
2029
2030         return (rc);
2031 }
2032
2033 static void
2034 cxgbe_qflush(struct ifnet *ifp)
2035 {
2036         struct vi_info *vi = ifp->if_softc;
2037         struct sge_txq *txq;
2038         int i;
2039
2040         /* queues do not exist if !VI_INIT_DONE. */
2041         if (vi->flags & VI_INIT_DONE) {
2042                 for_each_txq(vi, i, txq) {
2043                         TXQ_LOCK(txq);
2044                         txq->eq.flags |= EQ_QFLUSH;
2045                         TXQ_UNLOCK(txq);
2046                         while (!mp_ring_is_idle(txq->r)) {
2047                                 mp_ring_check_drainage(txq->r, 0);
2048                                 pause("qflush", 1);
2049                         }
2050                         TXQ_LOCK(txq);
2051                         txq->eq.flags &= ~EQ_QFLUSH;
2052                         TXQ_UNLOCK(txq);
2053                 }
2054         }
2055         if_qflush(ifp);
2056 }
2057
2058 static uint64_t
2059 vi_get_counter(struct ifnet *ifp, ift_counter c)
2060 {
2061         struct vi_info *vi = ifp->if_softc;
2062         struct fw_vi_stats_vf *s = &vi->stats;
2063
2064         vi_refresh_stats(vi->pi->adapter, vi);
2065
2066         switch (c) {
2067         case IFCOUNTER_IPACKETS:
2068                 return (s->rx_bcast_frames + s->rx_mcast_frames +
2069                     s->rx_ucast_frames);
2070         case IFCOUNTER_IERRORS:
2071                 return (s->rx_err_frames);
2072         case IFCOUNTER_OPACKETS:
2073                 return (s->tx_bcast_frames + s->tx_mcast_frames +
2074                     s->tx_ucast_frames + s->tx_offload_frames);
2075         case IFCOUNTER_OERRORS:
2076                 return (s->tx_drop_frames);
2077         case IFCOUNTER_IBYTES:
2078                 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2079                     s->rx_ucast_bytes);
2080         case IFCOUNTER_OBYTES:
2081                 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2082                     s->tx_ucast_bytes + s->tx_offload_bytes);
2083         case IFCOUNTER_IMCASTS:
2084                 return (s->rx_mcast_frames);
2085         case IFCOUNTER_OMCASTS:
2086                 return (s->tx_mcast_frames);
2087         case IFCOUNTER_OQDROPS: {
2088                 uint64_t drops;
2089
2090                 drops = 0;
2091                 if (vi->flags & VI_INIT_DONE) {
2092                         int i;
2093                         struct sge_txq *txq;
2094
2095                         for_each_txq(vi, i, txq)
2096                                 drops += counter_u64_fetch(txq->r->drops);
2097                 }
2098
2099                 return (drops);
2100
2101         }
2102
2103         default:
2104                 return (if_get_counter_default(ifp, c));
2105         }
2106 }
2107
2108 uint64_t
2109 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2110 {
2111         struct vi_info *vi = ifp->if_softc;
2112         struct port_info *pi = vi->pi;
2113         struct adapter *sc = pi->adapter;
2114         struct port_stats *s = &pi->stats;
2115
2116         if (pi->nvi > 1 || sc->flags & IS_VF)
2117                 return (vi_get_counter(ifp, c));
2118
2119         cxgbe_refresh_stats(sc, pi);
2120
2121         switch (c) {
2122         case IFCOUNTER_IPACKETS:
2123                 return (s->rx_frames);
2124
2125         case IFCOUNTER_IERRORS:
2126                 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2127                     s->rx_fcs_err + s->rx_len_err);
2128
2129         case IFCOUNTER_OPACKETS:
2130                 return (s->tx_frames);
2131
2132         case IFCOUNTER_OERRORS:
2133                 return (s->tx_error_frames);
2134
2135         case IFCOUNTER_IBYTES:
2136                 return (s->rx_octets);
2137
2138         case IFCOUNTER_OBYTES:
2139                 return (s->tx_octets);
2140
2141         case IFCOUNTER_IMCASTS:
2142                 return (s->rx_mcast_frames);
2143
2144         case IFCOUNTER_OMCASTS:
2145                 return (s->tx_mcast_frames);
2146
2147         case IFCOUNTER_IQDROPS:
2148                 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2149                     s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2150                     s->rx_trunc3 + pi->tnl_cong_drops);
2151
2152         case IFCOUNTER_OQDROPS: {
2153                 uint64_t drops;
2154
2155                 drops = s->tx_drop;
2156                 if (vi->flags & VI_INIT_DONE) {
2157                         int i;
2158                         struct sge_txq *txq;
2159
2160                         for_each_txq(vi, i, txq)
2161                                 drops += counter_u64_fetch(txq->r->drops);
2162                 }
2163
2164                 return (drops);
2165
2166         }
2167
2168         default:
2169                 return (if_get_counter_default(ifp, c));
2170         }
2171 }
2172
2173 /*
2174  * The kernel picks a media from the list we had provided but we still validate
2175  * the requeste.
2176  */
2177 static int
2178 cxgbe_media_change(struct ifnet *ifp)
2179 {
2180         struct vi_info *vi = ifp->if_softc;
2181         struct port_info *pi = vi->pi;
2182         struct ifmedia *ifm = &pi->media;
2183         struct link_config *lc = &pi->link_cfg;
2184         struct adapter *sc = pi->adapter;
2185         int rc;
2186
2187         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2188         if (rc != 0)
2189                 return (rc);
2190         PORT_LOCK(pi);
2191         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2192                 /* ifconfig .. media autoselect */
2193                 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2194                         rc = ENOTSUP; /* AN not supported by transceiver */
2195                         goto done;
2196                 }
2197                 lc->requested_aneg = AUTONEG_ENABLE;
2198                 lc->requested_speed = 0;
2199                 lc->requested_fc |= PAUSE_AUTONEG;
2200         } else {
2201                 lc->requested_aneg = AUTONEG_DISABLE;
2202                 lc->requested_speed =
2203                     ifmedia_baudrate(ifm->ifm_media) / 1000000;
2204                 lc->requested_fc = 0;
2205                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2206                         lc->requested_fc |= PAUSE_RX;
2207                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2208                         lc->requested_fc |= PAUSE_TX;
2209         }
2210         if (pi->up_vis > 0) {
2211                 fixup_link_config(pi);
2212                 rc = apply_link_config(pi);
2213         }
2214 done:
2215         PORT_UNLOCK(pi);
2216         end_synchronized_op(sc, 0);
2217         return (rc);
2218 }
2219
2220 /*
2221  * Base media word (without ETHER, pause, link active, etc.) for the port at the
2222  * given speed.
2223  */
2224 static int
2225 port_mword(struct port_info *pi, uint32_t speed)
2226 {
2227
2228         MPASS(speed & M_FW_PORT_CAP32_SPEED);
2229         MPASS(powerof2(speed));
2230
2231         switch(pi->port_type) {
2232         case FW_PORT_TYPE_BT_SGMII:
2233         case FW_PORT_TYPE_BT_XFI:
2234         case FW_PORT_TYPE_BT_XAUI:
2235                 /* BaseT */
2236                 switch (speed) {
2237                 case FW_PORT_CAP32_SPEED_100M:
2238                         return (IFM_100_T);
2239                 case FW_PORT_CAP32_SPEED_1G:
2240                         return (IFM_1000_T);
2241                 case FW_PORT_CAP32_SPEED_10G:
2242                         return (IFM_10G_T);
2243                 }
2244                 break;
2245         case FW_PORT_TYPE_KX4:
2246                 if (speed == FW_PORT_CAP32_SPEED_10G)
2247                         return (IFM_10G_KX4);
2248                 break;
2249         case FW_PORT_TYPE_CX4:
2250                 if (speed == FW_PORT_CAP32_SPEED_10G)
2251                         return (IFM_10G_CX4);
2252                 break;
2253         case FW_PORT_TYPE_KX:
2254                 if (speed == FW_PORT_CAP32_SPEED_1G)
2255                         return (IFM_1000_KX);
2256                 break;
2257         case FW_PORT_TYPE_KR:
2258         case FW_PORT_TYPE_BP_AP:
2259         case FW_PORT_TYPE_BP4_AP:
2260         case FW_PORT_TYPE_BP40_BA:
2261         case FW_PORT_TYPE_KR4_100G:
2262         case FW_PORT_TYPE_KR_SFP28:
2263         case FW_PORT_TYPE_KR_XLAUI:
2264                 switch (speed) {
2265                 case FW_PORT_CAP32_SPEED_1G:
2266                         return (IFM_1000_KX);
2267                 case FW_PORT_CAP32_SPEED_10G:
2268                         return (IFM_10G_KR);
2269                 case FW_PORT_CAP32_SPEED_25G:
2270                         return (IFM_25G_KR);
2271                 case FW_PORT_CAP32_SPEED_40G:
2272                         return (IFM_40G_KR4);
2273                 case FW_PORT_CAP32_SPEED_50G:
2274                         return (IFM_50G_KR2);
2275                 case FW_PORT_CAP32_SPEED_100G:
2276                         return (IFM_100G_KR4);
2277                 }
2278                 break;
2279         case FW_PORT_TYPE_FIBER_XFI:
2280         case FW_PORT_TYPE_FIBER_XAUI:
2281         case FW_PORT_TYPE_SFP:
2282         case FW_PORT_TYPE_QSFP_10G:
2283         case FW_PORT_TYPE_QSA:
2284         case FW_PORT_TYPE_QSFP:
2285         case FW_PORT_TYPE_CR4_QSFP:
2286         case FW_PORT_TYPE_CR_QSFP:
2287         case FW_PORT_TYPE_CR2_QSFP:
2288         case FW_PORT_TYPE_SFP28:
2289                 /* Pluggable transceiver */
2290                 switch (pi->mod_type) {
2291                 case FW_PORT_MOD_TYPE_LR:
2292                         switch (speed) {
2293                         case FW_PORT_CAP32_SPEED_1G:
2294                                 return (IFM_1000_LX);
2295                         case FW_PORT_CAP32_SPEED_10G:
2296                                 return (IFM_10G_LR);
2297                         case FW_PORT_CAP32_SPEED_25G:
2298                                 return (IFM_25G_LR);
2299                         case FW_PORT_CAP32_SPEED_40G:
2300                                 return (IFM_40G_LR4);
2301                         case FW_PORT_CAP32_SPEED_50G:
2302                                 return (IFM_50G_LR2);
2303                         case FW_PORT_CAP32_SPEED_100G:
2304                                 return (IFM_100G_LR4);
2305                         }
2306                         break;
2307                 case FW_PORT_MOD_TYPE_SR:
2308                         switch (speed) {
2309                         case FW_PORT_CAP32_SPEED_1G:
2310                                 return (IFM_1000_SX);
2311                         case FW_PORT_CAP32_SPEED_10G:
2312                                 return (IFM_10G_SR);
2313                         case FW_PORT_CAP32_SPEED_25G:
2314                                 return (IFM_25G_SR);
2315                         case FW_PORT_CAP32_SPEED_40G:
2316                                 return (IFM_40G_SR4);
2317                         case FW_PORT_CAP32_SPEED_50G:
2318                                 return (IFM_50G_SR2);
2319                         case FW_PORT_CAP32_SPEED_100G:
2320                                 return (IFM_100G_SR4);
2321                         }
2322                         break;
2323                 case FW_PORT_MOD_TYPE_ER:
2324                         if (speed == FW_PORT_CAP32_SPEED_10G)
2325                                 return (IFM_10G_ER);
2326                         break;
2327                 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2328                 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2329                         switch (speed) {
2330                         case FW_PORT_CAP32_SPEED_1G:
2331                                 return (IFM_1000_CX);
2332                         case FW_PORT_CAP32_SPEED_10G:
2333                                 return (IFM_10G_TWINAX);
2334                         case FW_PORT_CAP32_SPEED_25G:
2335                                 return (IFM_25G_CR);
2336                         case FW_PORT_CAP32_SPEED_40G:
2337                                 return (IFM_40G_CR4);
2338                         case FW_PORT_CAP32_SPEED_50G:
2339                                 return (IFM_50G_CR2);
2340                         case FW_PORT_CAP32_SPEED_100G:
2341                                 return (IFM_100G_CR4);
2342                         }
2343                         break;
2344                 case FW_PORT_MOD_TYPE_LRM:
2345                         if (speed == FW_PORT_CAP32_SPEED_10G)
2346                                 return (IFM_10G_LRM);
2347                         break;
2348                 case FW_PORT_MOD_TYPE_NA:
2349                         MPASS(0);       /* Not pluggable? */
2350                         /* fall throough */
2351                 case FW_PORT_MOD_TYPE_ERROR:
2352                 case FW_PORT_MOD_TYPE_UNKNOWN:
2353                 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2354                         break;
2355                 case FW_PORT_MOD_TYPE_NONE:
2356                         return (IFM_NONE);
2357                 }
2358                 break;
2359         case FW_PORT_TYPE_NONE:
2360                 return (IFM_NONE);
2361         }
2362
2363         return (IFM_UNKNOWN);
2364 }
2365
2366 static void
2367 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2368 {
2369         struct vi_info *vi = ifp->if_softc;
2370         struct port_info *pi = vi->pi;
2371         struct adapter *sc = pi->adapter;
2372         struct link_config *lc = &pi->link_cfg;
2373
2374         if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2375                 return;
2376         PORT_LOCK(pi);
2377
2378         if (pi->up_vis == 0) {
2379                 /*
2380                  * If all the interfaces are administratively down the firmware
2381                  * does not report transceiver changes.  Refresh port info here
2382                  * so that ifconfig displays accurate ifmedia at all times.
2383                  * This is the only reason we have a synchronized op in this
2384                  * function.  Just PORT_LOCK would have been enough otherwise.
2385                  */
2386                 t4_update_port_info(pi);
2387                 build_medialist(pi);
2388         }
2389
2390         /* ifm_status */
2391         ifmr->ifm_status = IFM_AVALID;
2392         if (lc->link_ok == false)
2393                 goto done;
2394         ifmr->ifm_status |= IFM_ACTIVE;
2395
2396         /* ifm_active */
2397         ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2398         ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2399         if (lc->fc & PAUSE_RX)
2400                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2401         if (lc->fc & PAUSE_TX)
2402                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2403         ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2404 done:
2405         PORT_UNLOCK(pi);
2406         end_synchronized_op(sc, 0);
2407 }
2408
2409 static int
2410 vcxgbe_probe(device_t dev)
2411 {
2412         char buf[128];
2413         struct vi_info *vi = device_get_softc(dev);
2414
2415         snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2416             vi - vi->pi->vi);
2417         device_set_desc_copy(dev, buf);
2418
2419         return (BUS_PROBE_DEFAULT);
2420 }
2421
2422 static int
2423 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2424 {
2425         int func, index, rc;
2426         uint32_t param, val;
2427
2428         ASSERT_SYNCHRONIZED_OP(sc);
2429
2430         index = vi - pi->vi;
2431         MPASS(index > 0);       /* This function deals with _extra_ VIs only */
2432         KASSERT(index < nitems(vi_mac_funcs),
2433             ("%s: VI %s doesn't have a MAC func", __func__,
2434             device_get_nameunit(vi->dev)));
2435         func = vi_mac_funcs[index];
2436         rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2437             vi->hw_addr, &vi->rss_size, func, 0);
2438         if (rc < 0) {
2439                 device_printf(vi->dev, "failed to allocate virtual interface %d"
2440                     "for port %d: %d\n", index, pi->port_id, -rc);
2441                 return (-rc);
2442         }
2443         vi->viid = rc;
2444         if (chip_id(sc) <= CHELSIO_T5)
2445                 vi->smt_idx = (rc & 0x7f) << 1;
2446         else
2447                 vi->smt_idx = (rc & 0x7f);
2448
2449         if (vi->rss_size == 1) {
2450                 /*
2451                  * This VI didn't get a slice of the RSS table.  Reduce the
2452                  * number of VIs being created (hw.cxgbe.num_vis) or modify the
2453                  * configuration file (nvi, rssnvi for this PF) if this is a
2454                  * problem.
2455                  */
2456                 device_printf(vi->dev, "RSS table not available.\n");
2457                 vi->rss_base = 0xffff;
2458
2459                 return (0);
2460         }
2461
2462         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2463             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2464             V_FW_PARAMS_PARAM_YZ(vi->viid);
2465         rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
2466         if (rc)
2467                 vi->rss_base = 0xffff;
2468         else {
2469                 MPASS((val >> 16) == vi->rss_size);
2470                 vi->rss_base = val & 0xffff;
2471         }
2472
2473         return (0);
2474 }
2475
2476 static int
2477 vcxgbe_attach(device_t dev)
2478 {
2479         struct vi_info *vi;
2480         struct port_info *pi;
2481         struct adapter *sc;
2482         int rc;
2483
2484         vi = device_get_softc(dev);
2485         pi = vi->pi;
2486         sc = pi->adapter;
2487
2488         rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2489         if (rc)
2490                 return (rc);
2491         rc = alloc_extra_vi(sc, pi, vi);
2492         end_synchronized_op(sc, 0);
2493         if (rc)
2494                 return (rc);
2495
2496         rc = cxgbe_vi_attach(dev, vi);
2497         if (rc) {
2498                 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2499                 return (rc);
2500         }
2501         return (0);
2502 }
2503
2504 static int
2505 vcxgbe_detach(device_t dev)
2506 {
2507         struct vi_info *vi;
2508         struct adapter *sc;
2509
2510         vi = device_get_softc(dev);
2511         sc = vi->pi->adapter;
2512
2513         doom_vi(sc, vi);
2514
2515         cxgbe_vi_detach(vi);
2516         t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2517
2518         end_synchronized_op(sc, 0);
2519
2520         return (0);
2521 }
2522
2523 void
2524 t4_fatal_err(struct adapter *sc)
2525 {
2526         t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2527         t4_intr_disable(sc);
2528         log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2529             device_get_nameunit(sc->dev));
2530 }
2531
2532 void
2533 t4_add_adapter(struct adapter *sc)
2534 {
2535         sx_xlock(&t4_list_lock);
2536         SLIST_INSERT_HEAD(&t4_list, sc, link);
2537         sx_xunlock(&t4_list_lock);
2538 }
2539
2540 int
2541 t4_map_bars_0_and_4(struct adapter *sc)
2542 {
2543         sc->regs_rid = PCIR_BAR(0);
2544         sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2545             &sc->regs_rid, RF_ACTIVE);
2546         if (sc->regs_res == NULL) {
2547                 device_printf(sc->dev, "cannot map registers.\n");
2548                 return (ENXIO);
2549         }
2550         sc->bt = rman_get_bustag(sc->regs_res);
2551         sc->bh = rman_get_bushandle(sc->regs_res);
2552         sc->mmio_len = rman_get_size(sc->regs_res);
2553         setbit(&sc->doorbells, DOORBELL_KDB);
2554
2555         sc->msix_rid = PCIR_BAR(4);
2556         sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2557             &sc->msix_rid, RF_ACTIVE);
2558         if (sc->msix_res == NULL) {
2559                 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2560                 return (ENXIO);
2561         }
2562
2563         return (0);
2564 }
2565
2566 int
2567 t4_map_bar_2(struct adapter *sc)
2568 {
2569
2570         /*
2571          * T4: only iWARP driver uses the userspace doorbells.  There is no need
2572          * to map it if RDMA is disabled.
2573          */
2574         if (is_t4(sc) && sc->rdmacaps == 0)
2575                 return (0);
2576
2577         sc->udbs_rid = PCIR_BAR(2);
2578         sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2579             &sc->udbs_rid, RF_ACTIVE);
2580         if (sc->udbs_res == NULL) {
2581                 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2582                 return (ENXIO);
2583         }
2584         sc->udbs_base = rman_get_virtual(sc->udbs_res);
2585
2586         if (chip_id(sc) >= CHELSIO_T5) {
2587                 setbit(&sc->doorbells, DOORBELL_UDB);
2588 #if defined(__i386__) || defined(__amd64__)
2589                 if (t5_write_combine) {
2590                         int rc, mode;
2591
2592                         /*
2593                          * Enable write combining on BAR2.  This is the
2594                          * userspace doorbell BAR and is split into 128B
2595                          * (UDBS_SEG_SIZE) doorbell regions, each associated
2596                          * with an egress queue.  The first 64B has the doorbell
2597                          * and the second 64B can be used to submit a tx work
2598                          * request with an implicit doorbell.
2599                          */
2600
2601                         rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2602                             rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2603                         if (rc == 0) {
2604                                 clrbit(&sc->doorbells, DOORBELL_UDB);
2605                                 setbit(&sc->doorbells, DOORBELL_WCWR);
2606                                 setbit(&sc->doorbells, DOORBELL_UDBWC);
2607                         } else {
2608                                 device_printf(sc->dev,
2609                                     "couldn't enable write combining: %d\n",
2610                                     rc);
2611                         }
2612
2613                         mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2614                         t4_write_reg(sc, A_SGE_STAT_CFG,
2615                             V_STATSOURCE_T5(7) | mode);
2616                 }
2617 #endif
2618         }
2619         sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2620
2621         return (0);
2622 }
2623
2624 struct memwin_init {
2625         uint32_t base;
2626         uint32_t aperture;
2627 };
2628
2629 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2630         { MEMWIN0_BASE, MEMWIN0_APERTURE },
2631         { MEMWIN1_BASE, MEMWIN1_APERTURE },
2632         { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2633 };
2634
2635 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2636         { MEMWIN0_BASE, MEMWIN0_APERTURE },
2637         { MEMWIN1_BASE, MEMWIN1_APERTURE },
2638         { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2639 };
2640
2641 static void
2642 setup_memwin(struct adapter *sc)
2643 {
2644         const struct memwin_init *mw_init;
2645         struct memwin *mw;
2646         int i;
2647         uint32_t bar0;
2648
2649         if (is_t4(sc)) {
2650                 /*
2651                  * Read low 32b of bar0 indirectly via the hardware backdoor
2652                  * mechanism.  Works from within PCI passthrough environments
2653                  * too, where rman_get_start() can return a different value.  We
2654                  * need to program the T4 memory window decoders with the actual
2655                  * addresses that will be coming across the PCIe link.
2656                  */
2657                 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2658                 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2659
2660                 mw_init = &t4_memwin[0];
2661         } else {
2662                 /* T5+ use the relative offset inside the PCIe BAR */
2663                 bar0 = 0;
2664
2665                 mw_init = &t5_memwin[0];
2666         }
2667
2668         for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2669                 rw_init(&mw->mw_lock, "memory window access");
2670                 mw->mw_base = mw_init->base;
2671                 mw->mw_aperture = mw_init->aperture;
2672                 mw->mw_curpos = 0;
2673                 t4_write_reg(sc,
2674                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2675                     (mw->mw_base + bar0) | V_BIR(0) |
2676                     V_WINDOW(ilog2(mw->mw_aperture) - 10));
2677                 rw_wlock(&mw->mw_lock);
2678                 position_memwin(sc, i, 0);
2679                 rw_wunlock(&mw->mw_lock);
2680         }
2681
2682         /* flush */
2683         t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2684 }
2685
2686 /*
2687  * Positions the memory window at the given address in the card's address space.
2688  * There are some alignment requirements and the actual position may be at an
2689  * address prior to the requested address.  mw->mw_curpos always has the actual
2690  * position of the window.
2691  */
2692 static void
2693 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2694 {
2695         struct memwin *mw;
2696         uint32_t pf;
2697         uint32_t reg;
2698
2699         MPASS(idx >= 0 && idx < NUM_MEMWIN);
2700         mw = &sc->memwin[idx];
2701         rw_assert(&mw->mw_lock, RA_WLOCKED);
2702
2703         if (is_t4(sc)) {
2704                 pf = 0;
2705                 mw->mw_curpos = addr & ~0xf;    /* start must be 16B aligned */
2706         } else {
2707                 pf = V_PFNUM(sc->pf);
2708                 mw->mw_curpos = addr & ~0x7f;   /* start must be 128B aligned */
2709         }
2710         reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2711         t4_write_reg(sc, reg, mw->mw_curpos | pf);
2712         t4_read_reg(sc, reg);   /* flush */
2713 }
2714
2715 static int
2716 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2717     int len, int rw)
2718 {
2719         struct memwin *mw;
2720         uint32_t mw_end, v;
2721
2722         MPASS(idx >= 0 && idx < NUM_MEMWIN);
2723
2724         /* Memory can only be accessed in naturally aligned 4 byte units */
2725         if (addr & 3 || len & 3 || len <= 0)
2726                 return (EINVAL);
2727
2728         mw = &sc->memwin[idx];
2729         while (len > 0) {
2730                 rw_rlock(&mw->mw_lock);
2731                 mw_end = mw->mw_curpos + mw->mw_aperture;
2732                 if (addr >= mw_end || addr < mw->mw_curpos) {
2733                         /* Will need to reposition the window */
2734                         if (!rw_try_upgrade(&mw->mw_lock)) {
2735                                 rw_runlock(&mw->mw_lock);
2736                                 rw_wlock(&mw->mw_lock);
2737                         }
2738                         rw_assert(&mw->mw_lock, RA_WLOCKED);
2739                         position_memwin(sc, idx, addr);
2740                         rw_downgrade(&mw->mw_lock);
2741                         mw_end = mw->mw_curpos + mw->mw_aperture;
2742                 }
2743                 rw_assert(&mw->mw_lock, RA_RLOCKED);
2744                 while (addr < mw_end && len > 0) {
2745                         if (rw == 0) {
2746                                 v = t4_read_reg(sc, mw->mw_base + addr -
2747                                     mw->mw_curpos);
2748                                 *val++ = le32toh(v);
2749                         } else {
2750                                 v = *val++;
2751                                 t4_write_reg(sc, mw->mw_base + addr -
2752                                     mw->mw_curpos, htole32(v));
2753                         }
2754                         addr += 4;
2755                         len -= 4;
2756                 }
2757                 rw_runlock(&mw->mw_lock);
2758         }
2759
2760         return (0);
2761 }
2762
2763 static inline int
2764 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2765     int len)
2766 {
2767
2768         return (rw_via_memwin(sc, idx, addr, val, len, 0));
2769 }
2770
2771 static inline int
2772 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2773     const uint32_t *val, int len)
2774 {
2775
2776         return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2777 }
2778
2779 static int
2780 t4_range_cmp(const void *a, const void *b)
2781 {
2782         return ((const struct t4_range *)a)->start -
2783                ((const struct t4_range *)b)->start;
2784 }
2785
2786 /*
2787  * Verify that the memory range specified by the addr/len pair is valid within
2788  * the card's address space.
2789  */
2790 static int
2791 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2792 {
2793         struct t4_range mem_ranges[4], *r, *next;
2794         uint32_t em, addr_len;
2795         int i, n, remaining;
2796
2797         /* Memory can only be accessed in naturally aligned 4 byte units */
2798         if (addr & 3 || len & 3 || len == 0)
2799                 return (EINVAL);
2800
2801         /* Enabled memories */
2802         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2803
2804         r = &mem_ranges[0];
2805         n = 0;
2806         bzero(r, sizeof(mem_ranges));
2807         if (em & F_EDRAM0_ENABLE) {
2808                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2809                 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2810                 if (r->size > 0) {
2811                         r->start = G_EDRAM0_BASE(addr_len) << 20;
2812                         if (addr >= r->start &&
2813                             addr + len <= r->start + r->size)
2814                                 return (0);
2815                         r++;
2816                         n++;
2817                 }
2818         }
2819         if (em & F_EDRAM1_ENABLE) {
2820                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2821                 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2822                 if (r->size > 0) {
2823                         r->start = G_EDRAM1_BASE(addr_len) << 20;
2824                         if (addr >= r->start &&
2825                             addr + len <= r->start + r->size)
2826                                 return (0);
2827                         r++;
2828                         n++;
2829                 }
2830         }
2831         if (em & F_EXT_MEM_ENABLE) {
2832                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2833                 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2834                 if (r->size > 0) {
2835                         r->start = G_EXT_MEM_BASE(addr_len) << 20;
2836                         if (addr >= r->start &&
2837                             addr + len <= r->start + r->size)
2838                                 return (0);
2839                         r++;
2840                         n++;
2841                 }
2842         }
2843         if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2844                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2845                 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2846                 if (r->size > 0) {
2847                         r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2848                         if (addr >= r->start &&
2849                             addr + len <= r->start + r->size)
2850                                 return (0);
2851                         r++;
2852                         n++;
2853                 }
2854         }
2855         MPASS(n <= nitems(mem_ranges));
2856
2857         if (n > 1) {
2858                 /* Sort and merge the ranges. */
2859                 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2860
2861                 /* Start from index 0 and examine the next n - 1 entries. */
2862                 r = &mem_ranges[0];
2863                 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2864
2865                         MPASS(r->size > 0);     /* r is a valid entry. */
2866                         next = r + 1;
2867                         MPASS(next->size > 0);  /* and so is the next one. */
2868
2869                         while (r->start + r->size >= next->start) {
2870                                 /* Merge the next one into the current entry. */
2871                                 r->size = max(r->start + r->size,
2872                                     next->start + next->size) - r->start;
2873                                 n--;    /* One fewer entry in total. */
2874                                 if (--remaining == 0)
2875                                         goto done;      /* short circuit */
2876                                 next++;
2877                         }
2878                         if (next != r + 1) {
2879                                 /*
2880                                  * Some entries were merged into r and next
2881                                  * points to the first valid entry that couldn't
2882                                  * be merged.
2883                                  */
2884                                 MPASS(next->size > 0);  /* must be valid */
2885                                 memcpy(r + 1, next, remaining * sizeof(*r));
2886 #ifdef INVARIANTS
2887                                 /*
2888                                  * This so that the foo->size assertion in the
2889                                  * next iteration of the loop do the right
2890                                  * thing for entries that were pulled up and are
2891                                  * no longer valid.
2892                                  */
2893                                 MPASS(n < nitems(mem_ranges));
2894                                 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2895                                     sizeof(struct t4_range));
2896 #endif
2897                         }
2898                 }
2899 done:
2900                 /* Done merging the ranges. */
2901                 MPASS(n > 0);
2902                 r = &mem_ranges[0];
2903                 for (i = 0; i < n; i++, r++) {
2904                         if (addr >= r->start &&
2905                             addr + len <= r->start + r->size)
2906                                 return (0);
2907                 }
2908         }
2909
2910         return (EFAULT);
2911 }
2912
2913 static int
2914 fwmtype_to_hwmtype(int mtype)
2915 {
2916
2917         switch (mtype) {
2918         case FW_MEMTYPE_EDC0:
2919                 return (MEM_EDC0);
2920         case FW_MEMTYPE_EDC1:
2921                 return (MEM_EDC1);
2922         case FW_MEMTYPE_EXTMEM:
2923                 return (MEM_MC0);
2924         case FW_MEMTYPE_EXTMEM1:
2925                 return (MEM_MC1);
2926         default:
2927                 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2928         }
2929 }
2930
2931 /*
2932  * Verify that the memory range specified by the memtype/offset/len pair is
2933  * valid and lies entirely within the memtype specified.  The global address of
2934  * the start of the range is returned in addr.
2935  */
2936 static int
2937 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
2938     uint32_t *addr)
2939 {
2940         uint32_t em, addr_len, maddr;
2941
2942         /* Memory can only be accessed in naturally aligned 4 byte units */
2943         if (off & 3 || len & 3 || len == 0)
2944                 return (EINVAL);
2945
2946         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2947         switch (fwmtype_to_hwmtype(mtype)) {
2948         case MEM_EDC0:
2949                 if (!(em & F_EDRAM0_ENABLE))
2950                         return (EINVAL);
2951                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2952                 maddr = G_EDRAM0_BASE(addr_len) << 20;
2953                 break;
2954         case MEM_EDC1:
2955                 if (!(em & F_EDRAM1_ENABLE))
2956                         return (EINVAL);
2957                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2958                 maddr = G_EDRAM1_BASE(addr_len) << 20;
2959                 break;
2960         case MEM_MC:
2961                 if (!(em & F_EXT_MEM_ENABLE))
2962                         return (EINVAL);
2963                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2964                 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2965                 break;
2966         case MEM_MC1:
2967                 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2968                         return (EINVAL);
2969                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2970                 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2971                 break;
2972         default:
2973                 return (EINVAL);
2974         }
2975
2976         *addr = maddr + off;    /* global address */
2977         return (validate_mem_range(sc, *addr, len));
2978 }
2979
2980 static int
2981 fixup_devlog_params(struct adapter *sc)
2982 {
2983         struct devlog_params *dparams = &sc->params.devlog;
2984         int rc;
2985
2986         rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2987             dparams->size, &dparams->addr);
2988
2989         return (rc);
2990 }
2991
2992 static void
2993 update_nirq(struct intrs_and_queues *iaq, int nports)
2994 {
2995         int extra = T4_EXTRA_INTR;
2996
2997         iaq->nirq = extra;
2998         iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
2999         iaq->nirq += nports * (iaq->num_vis - 1) *
3000             max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3001         iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3002 }
3003
3004 /*
3005  * Adjust requirements to fit the number of interrupts available.
3006  */
3007 static void
3008 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3009     int navail)
3010 {
3011         int old_nirq;
3012         const int nports = sc->params.nports;
3013
3014         MPASS(nports > 0);
3015         MPASS(navail > 0);
3016
3017         bzero(iaq, sizeof(*iaq));
3018         iaq->intr_type = itype;
3019         iaq->num_vis = t4_num_vis;
3020         iaq->ntxq = t4_ntxq;
3021         iaq->ntxq_vi = t4_ntxq_vi;
3022         iaq->nrxq = t4_nrxq;
3023         iaq->nrxq_vi = t4_nrxq_vi;
3024 #ifdef TCP_OFFLOAD
3025         if (is_offload(sc)) {
3026                 iaq->nofldtxq = t4_nofldtxq;
3027                 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3028                 iaq->nofldrxq = t4_nofldrxq;
3029                 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3030         }
3031 #endif
3032 #ifdef DEV_NETMAP
3033         iaq->nnmtxq_vi = t4_nnmtxq_vi;
3034         iaq->nnmrxq_vi = t4_nnmrxq_vi;
3035 #endif
3036
3037         update_nirq(iaq, nports);
3038         if (iaq->nirq <= navail &&
3039             (itype != INTR_MSI || powerof2(iaq->nirq))) {
3040                 /*
3041                  * This is the normal case -- there are enough interrupts for
3042                  * everything.
3043                  */
3044                 goto done;
3045         }
3046
3047         /*
3048          * If extra VIs have been configured try reducing their count and see if
3049          * that works.
3050          */
3051         while (iaq->num_vis > 1) {
3052                 iaq->num_vis--;
3053                 update_nirq(iaq, nports);
3054                 if (iaq->nirq <= navail &&
3055                     (itype != INTR_MSI || powerof2(iaq->nirq))) {
3056                         device_printf(sc->dev, "virtual interfaces per port "
3057                             "reduced to %d from %d.  nrxq=%u, nofldrxq=%u, "
3058                             "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u.  "
3059                             "itype %d, navail %u, nirq %d.\n",
3060                             iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3061                             iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3062                             itype, navail, iaq->nirq);
3063                         goto done;
3064                 }
3065         }
3066
3067         /*
3068          * Extra VIs will not be created.  Log a message if they were requested.
3069          */
3070         MPASS(iaq->num_vis == 1);
3071         iaq->ntxq_vi = iaq->nrxq_vi = 0;
3072         iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3073         iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3074         if (iaq->num_vis != t4_num_vis) {
3075                 device_printf(sc->dev, "extra virtual interfaces disabled.  "
3076                     "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3077                     "nnmrxq_vi=%u.  itype %d, navail %u, nirq %d.\n",
3078                     iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3079                     iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3080         }
3081
3082         /*
3083          * Keep reducing the number of NIC rx queues to the next lower power of
3084          * 2 (for even RSS distribution) and halving the TOE rx queues and see
3085          * if that works.
3086          */
3087         do {
3088                 if (iaq->nrxq > 1) {
3089                         do {
3090                                 iaq->nrxq--;
3091                         } while (!powerof2(iaq->nrxq));
3092                 }
3093                 if (iaq->nofldrxq > 1)
3094                         iaq->nofldrxq >>= 1;
3095
3096                 old_nirq = iaq->nirq;
3097                 update_nirq(iaq, nports);
3098                 if (iaq->nirq <= navail &&
3099                     (itype != INTR_MSI || powerof2(iaq->nirq))) {
3100                         device_printf(sc->dev, "running with reduced number of "
3101                             "rx queues because of shortage of interrupts.  "
3102                             "nrxq=%u, nofldrxq=%u.  "
3103                             "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3104                             iaq->nofldrxq, itype, navail, iaq->nirq);
3105                         goto done;
3106                 }
3107         } while (old_nirq != iaq->nirq);
3108
3109         /* One interrupt for everything.  Ugh. */
3110         device_printf(sc->dev, "running with minimal number of queues.  "
3111             "itype %d, navail %u.\n", itype, navail);
3112         iaq->nirq = 1;
3113         MPASS(iaq->nrxq == 1);
3114         iaq->ntxq = 1;
3115         if (iaq->nofldrxq > 1)
3116                 iaq->nofldtxq = 1;
3117 done:
3118         MPASS(iaq->num_vis > 0);
3119         if (iaq->num_vis > 1) {
3120                 MPASS(iaq->nrxq_vi > 0);
3121                 MPASS(iaq->ntxq_vi > 0);
3122         }
3123         MPASS(iaq->nirq > 0);
3124         MPASS(iaq->nrxq > 0);
3125         MPASS(iaq->ntxq > 0);
3126         if (itype == INTR_MSI) {
3127                 MPASS(powerof2(iaq->nirq));
3128         }
3129 }
3130
3131 static int
3132 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3133 {
3134         int rc, itype, navail, nalloc;
3135
3136         for (itype = INTR_MSIX; itype; itype >>= 1) {
3137
3138                 if ((itype & t4_intr_types) == 0)
3139                         continue;       /* not allowed */
3140
3141                 if (itype == INTR_MSIX)
3142                         navail = pci_msix_count(sc->dev);
3143                 else if (itype == INTR_MSI)
3144                         navail = pci_msi_count(sc->dev);
3145                 else
3146                         navail = 1;
3147 restart:
3148                 if (navail == 0)
3149                         continue;
3150
3151                 calculate_iaq(sc, iaq, itype, navail);
3152                 nalloc = iaq->nirq;
3153                 rc = 0;
3154                 if (itype == INTR_MSIX)
3155                         rc = pci_alloc_msix(sc->dev, &nalloc);
3156                 else if (itype == INTR_MSI)
3157                         rc = pci_alloc_msi(sc->dev, &nalloc);
3158
3159                 if (rc == 0 && nalloc > 0) {
3160                         if (nalloc == iaq->nirq)
3161                                 return (0);
3162
3163                         /*
3164                          * Didn't get the number requested.  Use whatever number
3165                          * the kernel is willing to allocate.
3166                          */
3167                         device_printf(sc->dev, "fewer vectors than requested, "
3168                             "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3169                             itype, iaq->nirq, nalloc);
3170                         pci_release_msi(sc->dev);
3171                         navail = nalloc;
3172                         goto restart;
3173                 }
3174
3175                 device_printf(sc->dev,
3176                     "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3177                     itype, rc, iaq->nirq, nalloc);
3178         }
3179
3180         device_printf(sc->dev,
3181             "failed to find a usable interrupt type.  "
3182             "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3183             pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3184
3185         return (ENXIO);
3186 }
3187
3188 #define FW_VERSION(chip) ( \
3189     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3190     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3191     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3192     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3193 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3194
3195 struct fw_info {
3196         uint8_t chip;
3197         char *kld_name;
3198         char *fw_mod_name;
3199         struct fw_hdr fw_hdr;   /* XXX: waste of space, need a sparse struct */
3200 } fw_info[] = {
3201         {
3202                 .chip = CHELSIO_T4,
3203                 .kld_name = "t4fw_cfg",
3204                 .fw_mod_name = "t4fw",
3205                 .fw_hdr = {
3206                         .chip = FW_HDR_CHIP_T4,
3207                         .fw_ver = htobe32(FW_VERSION(T4)),
3208                         .intfver_nic = FW_INTFVER(T4, NIC),
3209                         .intfver_vnic = FW_INTFVER(T4, VNIC),
3210                         .intfver_ofld = FW_INTFVER(T4, OFLD),
3211                         .intfver_ri = FW_INTFVER(T4, RI),
3212                         .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3213                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3214                         .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3215                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
3216                 },
3217         }, {
3218                 .chip = CHELSIO_T5,
3219                 .kld_name = "t5fw_cfg",
3220                 .fw_mod_name = "t5fw",
3221                 .fw_hdr = {
3222                         .chip = FW_HDR_CHIP_T5,
3223                         .fw_ver = htobe32(FW_VERSION(T5)),
3224                         .intfver_nic = FW_INTFVER(T5, NIC),
3225                         .intfver_vnic = FW_INTFVER(T5, VNIC),
3226                         .intfver_ofld = FW_INTFVER(T5, OFLD),
3227                         .intfver_ri = FW_INTFVER(T5, RI),
3228                         .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3229                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3230                         .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3231                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
3232                 },
3233         }, {
3234                 .chip = CHELSIO_T6,
3235                 .kld_name = "t6fw_cfg",
3236                 .fw_mod_name = "t6fw",
3237                 .fw_hdr = {
3238                         .chip = FW_HDR_CHIP_T6,
3239                         .fw_ver = htobe32(FW_VERSION(T6)),
3240                         .intfver_nic = FW_INTFVER(T6, NIC),
3241                         .intfver_vnic = FW_INTFVER(T6, VNIC),
3242                         .intfver_ofld = FW_INTFVER(T6, OFLD),
3243                         .intfver_ri = FW_INTFVER(T6, RI),
3244                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3245                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3246                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3247                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
3248                 },
3249         }
3250 };
3251
3252 static struct fw_info *
3253 find_fw_info(int chip)
3254 {
3255         int i;
3256
3257         for (i = 0; i < nitems(fw_info); i++) {
3258                 if (fw_info[i].chip == chip)
3259                         return (&fw_info[i]);
3260         }
3261         return (NULL);
3262 }
3263
3264 /*
3265  * Is the given firmware API compatible with the one the driver was compiled
3266  * with?
3267  */
3268 static int
3269 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3270 {
3271
3272         /* short circuit if it's the exact same firmware version */
3273         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3274                 return (1);
3275
3276         /*
3277          * XXX: Is this too conservative?  Perhaps I should limit this to the
3278          * features that are supported in the driver.
3279          */
3280 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3281         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3282             SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3283             SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3284                 return (1);
3285 #undef SAME_INTF
3286
3287         return (0);
3288 }
3289
3290 /*
3291  * The firmware in the KLD is usable, but should it be installed?  This routine
3292  * explains itself in detail if it indicates the KLD firmware should be
3293  * installed.
3294  */
3295 static int
3296 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
3297 {
3298         const char *reason;
3299
3300         if (!card_fw_usable) {
3301                 reason = "incompatible or unusable";
3302                 goto install;
3303         }
3304
3305         if (k > c) {
3306                 reason = "older than the version bundled with this driver";
3307                 goto install;
3308         }
3309
3310         if (t4_fw_install == 2 && k != c) {
3311                 reason = "different than the version bundled with this driver";
3312                 goto install;
3313         }
3314
3315         return (0);
3316
3317 install:
3318         if (t4_fw_install == 0) {
3319                 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3320                     "but the driver is prohibited from installing a different "
3321                     "firmware on the card.\n",
3322                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3323                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3324
3325                 return (0);
3326         }
3327
3328         device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3329             "installing firmware %u.%u.%u.%u on card.\n",
3330             G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3331             G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3332             G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3333             G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3334
3335         return (1);
3336 }
3337
3338 /*
3339  * Establish contact with the firmware and determine if we are the master driver
3340  * or not, and whether we are responsible for chip initialization.
3341  */
3342 static int
3343 prep_firmware(struct adapter *sc)
3344 {
3345         const struct firmware *fw = NULL, *default_cfg;
3346         int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
3347         enum dev_state state;
3348         struct fw_info *fw_info;
3349         struct fw_hdr *card_fw;         /* fw on the card */
3350         const struct fw_hdr *kld_fw;    /* fw in the KLD */
3351         const struct fw_hdr *drv_fw;    /* fw header the driver was compiled
3352                                            against */
3353
3354         /* This is the firmware whose headers the driver was compiled against */
3355         fw_info = find_fw_info(chip_id(sc));
3356         if (fw_info == NULL) {
3357                 device_printf(sc->dev,
3358                     "unable to look up firmware information for chip %d.\n",
3359                     chip_id(sc));
3360                 return (EINVAL);
3361         }
3362         drv_fw = &fw_info->fw_hdr;
3363
3364         /*
3365          * The firmware KLD contains many modules.  The KLD name is also the
3366          * name of the module that contains the default config file.
3367          */
3368         default_cfg = firmware_get(fw_info->kld_name);
3369
3370         /* This is the firmware in the KLD */
3371         fw = firmware_get(fw_info->fw_mod_name);
3372         if (fw != NULL) {
3373                 kld_fw = (const void *)fw->data;
3374                 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3375         } else {
3376                 kld_fw = NULL;
3377                 kld_fw_usable = 0;
3378         }
3379
3380         /* Read the header of the firmware on the card */
3381         card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3382         rc = -t4_read_flash(sc, FLASH_FW_START,
3383             sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3384         if (rc == 0) {
3385                 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3386                 if (card_fw->fw_ver == be32toh(0xffffffff)) {
3387                         uint32_t d = be32toh(kld_fw->fw_ver);
3388
3389                         if (!kld_fw_usable) {
3390                                 device_printf(sc->dev,
3391                                     "no firmware on the card and no usable "
3392                                     "firmware bundled with the driver.\n");
3393                                 rc = EIO;
3394                                 goto done;
3395                         } else if (t4_fw_install == 0) {
3396                                 device_printf(sc->dev,
3397                                     "no firmware on the card and the driver "
3398                                     "is prohibited from installing new "
3399                                     "firmware.\n");
3400                                 rc = EIO;
3401                                 goto done;
3402                         }
3403
3404                         device_printf(sc->dev, "no firmware on the card, "
3405                             "installing firmware %d.%d.%d.%d\n",
3406                             G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3407                             G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3408                         rc = t4_fw_forceinstall(sc, fw->data, fw->datasize);
3409                         if (rc < 0) {
3410                                 rc = -rc;
3411                                 device_printf(sc->dev,
3412                                     "firmware install failed: %d.\n", rc);
3413                                 goto done;
3414                         }
3415                         memcpy(card_fw, kld_fw, sizeof(*card_fw));
3416                         card_fw_usable = 1;
3417                         need_fw_reset = 0;
3418                 }
3419         } else {
3420                 device_printf(sc->dev,
3421                     "Unable to read card's firmware header: %d\n", rc);
3422                 card_fw_usable = 0;
3423         }
3424
3425         /* Contact firmware. */
3426         rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3427         if (rc < 0 || state == DEV_STATE_ERR) {
3428                 rc = -rc;
3429                 device_printf(sc->dev,
3430                     "failed to connect to the firmware: %d, %d.\n", rc, state);
3431                 goto done;
3432         }
3433         pf = rc;
3434         if (pf == sc->mbox)
3435                 sc->flags |= MASTER_PF;
3436         else if (state == DEV_STATE_UNINIT) {
3437                 /*
3438                  * We didn't get to be the master so we definitely won't be
3439                  * configuring the chip.  It's a bug if someone else hasn't
3440                  * configured it already.
3441                  */
3442                 device_printf(sc->dev, "couldn't be master(%d), "
3443                     "device not already initialized either(%d).\n", rc, state);
3444                 rc = EPROTO;
3445                 goto done;
3446         }
3447
3448         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3449             (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3450                 /*
3451                  * Common case: the firmware on the card is an exact match and
3452                  * the KLD is an exact match too, or the KLD is
3453                  * absent/incompatible.  Note that t4_fw_install = 2 is ignored
3454                  * here -- use cxgbetool loadfw if you want to reinstall the
3455                  * same firmware as the one on the card.
3456                  */
3457         } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3458             should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3459             be32toh(card_fw->fw_ver))) {
3460
3461                 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3462                 if (rc != 0) {
3463                         device_printf(sc->dev,
3464                             "failed to install firmware: %d\n", rc);
3465                         goto done;
3466                 }
3467
3468                 /* Installed successfully, update the cached header too. */
3469                 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3470                 card_fw_usable = 1;
3471                 need_fw_reset = 0;      /* already reset as part of load_fw */
3472         }
3473
3474         if (!card_fw_usable) {
3475                 uint32_t d, c, k;
3476
3477                 d = ntohl(drv_fw->fw_ver);
3478                 c = ntohl(card_fw->fw_ver);
3479                 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3480
3481                 device_printf(sc->dev, "Cannot find a usable firmware: "
3482                     "fw_install %d, chip state %d, "
3483                     "driver compiled with %d.%d.%d.%d, "
3484                     "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3485                     t4_fw_install, state,
3486                     G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3487                     G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3488                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3489                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3490                     G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3491                     G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3492                 rc = EINVAL;
3493                 goto done;
3494         }
3495
3496         /* Reset device */
3497         if (need_fw_reset &&
3498             (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3499                 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3500                 if (rc != ETIMEDOUT && rc != EIO)
3501                         t4_fw_bye(sc, sc->mbox);
3502                 goto done;
3503         }
3504         sc->flags |= FW_OK;
3505
3506         rc = get_params__pre_init(sc);
3507         if (rc != 0)
3508                 goto done; /* error message displayed already */
3509
3510         /* Partition adapter resources as specified in the config file. */
3511         if (state == DEV_STATE_UNINIT) {
3512
3513                 KASSERT(sc->flags & MASTER_PF,
3514                     ("%s: trying to change chip settings when not master.",
3515                     __func__));
3516
3517                 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3518                 if (rc != 0)
3519                         goto done;      /* error message displayed already */
3520
3521                 t4_tweak_chip_settings(sc);
3522
3523                 /* get basic stuff going */
3524                 rc = -t4_fw_initialize(sc, sc->mbox);
3525                 if (rc != 0) {
3526                         device_printf(sc->dev, "fw init failed: %d.\n", rc);
3527                         goto done;
3528                 }
3529         } else {
3530                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3531                 sc->cfcsum = 0;
3532         }
3533
3534 done:
3535         free(card_fw, M_CXGBE);
3536         if (fw != NULL)
3537                 firmware_put(fw, FIRMWARE_UNLOAD);
3538         if (default_cfg != NULL)
3539                 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3540
3541         return (rc);
3542 }
3543
3544 #define FW_PARAM_DEV(param) \
3545         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3546          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3547 #define FW_PARAM_PFVF(param) \
3548         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3549          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3550
3551 /*
3552  * Partition chip resources for use between various PFs, VFs, etc.
3553  */
3554 static int
3555 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3556     const char *name_prefix)
3557 {
3558         const struct firmware *cfg = NULL;
3559         int rc = 0;
3560         struct fw_caps_config_cmd caps;
3561         uint32_t mtype, moff, finicsum, cfcsum;
3562
3563         /*
3564          * Figure out what configuration file to use.  Pick the default config
3565          * file for the card if the user hasn't specified one explicitly.
3566          */
3567         snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3568         if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3569                 /* Card specific overrides go here. */
3570                 if (pci_get_device(sc->dev) == 0x440a)
3571                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3572                 if (is_fpga(sc))
3573                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3574         } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0)
3575                 goto use_built_in_config;       /* go straight to config. */
3576
3577         /*
3578          * We need to load another module if the profile is anything except
3579          * "default" or "flash".
3580          */
3581         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3582             strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3583                 char s[32];
3584
3585                 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3586                 cfg = firmware_get(s);
3587                 if (cfg == NULL) {
3588                         if (default_cfg != NULL) {
3589                                 device_printf(sc->dev,
3590                                     "unable to load module \"%s\" for "
3591                                     "configuration profile \"%s\", will use "
3592                                     "the default config file instead.\n",
3593                                     s, sc->cfg_file);
3594                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3595                                     "%s", DEFAULT_CF);
3596                         } else {
3597                                 device_printf(sc->dev,
3598                                     "unable to load module \"%s\" for "
3599                                     "configuration profile \"%s\", will use "
3600                                     "the config file on the card's flash "
3601                                     "instead.\n", s, sc->cfg_file);
3602                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3603                                     "%s", FLASH_CF);
3604                         }
3605                 }
3606         }
3607
3608         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3609             default_cfg == NULL) {
3610                 device_printf(sc->dev,
3611                     "default config file not available, will use the config "
3612                     "file on the card's flash instead.\n");
3613                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3614         }
3615
3616         if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3617                 u_int cflen;
3618                 const uint32_t *cfdata;
3619                 uint32_t param, val, addr;
3620
3621                 KASSERT(cfg != NULL || default_cfg != NULL,
3622                     ("%s: no config to upload", __func__));
3623
3624                 /*
3625                  * Ask the firmware where it wants us to upload the config file.
3626                  */
3627                 param = FW_PARAM_DEV(CF);
3628                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3629                 if (rc != 0) {
3630                         /* No support for config file?  Shouldn't happen. */
3631                         device_printf(sc->dev,
3632                             "failed to query config file location: %d.\n", rc);
3633                         goto done;
3634                 }
3635                 mtype = G_FW_PARAMS_PARAM_Y(val);
3636                 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3637
3638                 /*
3639                  * XXX: sheer laziness.  We deliberately added 4 bytes of
3640                  * useless stuffing/comments at the end of the config file so
3641                  * it's ok to simply throw away the last remaining bytes when
3642                  * the config file is not an exact multiple of 4.  This also
3643                  * helps with the validate_mt_off_len check.
3644                  */
3645                 if (cfg != NULL) {
3646                         cflen = cfg->datasize & ~3;
3647                         cfdata = cfg->data;
3648                 } else {
3649                         cflen = default_cfg->datasize & ~3;
3650                         cfdata = default_cfg->data;
3651                 }
3652
3653                 if (cflen > FLASH_CFG_MAX_SIZE) {
3654                         device_printf(sc->dev,
3655                             "config file too long (%d, max allowed is %d).  "
3656                             "Will try to use the config on the card, if any.\n",
3657                             cflen, FLASH_CFG_MAX_SIZE);
3658                         goto use_config_on_flash;
3659                 }
3660
3661                 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3662                 if (rc != 0) {
3663                         device_printf(sc->dev,
3664                             "%s: addr (%d/0x%x) or len %d is not valid: %d.  "
3665                             "Will try to use the config on the card, if any.\n",
3666                             __func__, mtype, moff, cflen, rc);
3667                         goto use_config_on_flash;
3668                 }
3669                 write_via_memwin(sc, 2, addr, cfdata, cflen);
3670         } else {
3671 use_config_on_flash:
3672                 mtype = FW_MEMTYPE_FLASH;
3673                 moff = t4_flash_cfg_addr(sc);
3674         }
3675
3676         bzero(&caps, sizeof(caps));
3677         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3678             F_FW_CMD_REQUEST | F_FW_CMD_READ);
3679         caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3680             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3681             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3682         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3683         if (rc != 0) {
3684                 device_printf(sc->dev,
3685                     "failed to pre-process config file: %d "
3686                     "(mtype %d, moff 0x%x).  Will reset the firmware and retry "
3687                     "with the built-in configuration.\n", rc, mtype, moff);
3688
3689                 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3690                 if (rc != 0) {
3691                         device_printf(sc->dev,
3692                             "firmware reset failed: %d.\n", rc);
3693                         if (rc != ETIMEDOUT && rc != EIO) {
3694                                 t4_fw_bye(sc, sc->mbox);
3695                                 sc->flags &= ~FW_OK;
3696                         }
3697                         goto done;
3698                 }
3699                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in");
3700 use_built_in_config:
3701                 bzero(&caps, sizeof(caps));
3702                 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3703                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
3704                 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3705                 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3706                 if (rc != 0) {
3707                         device_printf(sc->dev,
3708                             "built-in configuration failed: %d.\n", rc);
3709                         goto done;
3710                 }
3711         }
3712
3713         finicsum = be32toh(caps.finicsum);
3714         cfcsum = be32toh(caps.cfcsum);
3715         if (finicsum != cfcsum) {
3716                 device_printf(sc->dev,
3717                     "WARNING: config file checksum mismatch: %08x %08x\n",
3718                     finicsum, cfcsum);
3719         }
3720         sc->cfcsum = cfcsum;
3721
3722 #define LIMIT_CAPS(x) do { \
3723         caps.x &= htobe16(t4_##x##_allowed); \
3724 } while (0)
3725
3726         /*
3727          * Let the firmware know what features will (not) be used so it can tune
3728          * things accordingly.
3729          */
3730         LIMIT_CAPS(nbmcaps);
3731         LIMIT_CAPS(linkcaps);
3732         LIMIT_CAPS(switchcaps);
3733         LIMIT_CAPS(niccaps);
3734         LIMIT_CAPS(toecaps);
3735         LIMIT_CAPS(rdmacaps);
3736         LIMIT_CAPS(cryptocaps);
3737         LIMIT_CAPS(iscsicaps);
3738         LIMIT_CAPS(fcoecaps);
3739 #undef LIMIT_CAPS
3740
3741         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3742             F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3743         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3744         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3745         if (rc != 0) {
3746                 device_printf(sc->dev,
3747                     "failed to process config file: %d.\n", rc);
3748         }
3749 done:
3750         if (cfg != NULL)
3751                 firmware_put(cfg, FIRMWARE_UNLOAD);
3752         return (rc);
3753 }
3754
3755 /*
3756  * Retrieve parameters that are needed (or nice to have) very early.
3757  */
3758 static int
3759 get_params__pre_init(struct adapter *sc)
3760 {
3761         int rc;
3762         uint32_t param[2], val[2];
3763
3764         t4_get_version_info(sc);
3765
3766         snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3767             G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3768             G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3769             G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3770             G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3771
3772         snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3773             G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3774             G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3775             G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3776             G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3777
3778         snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3779             G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3780             G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3781             G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3782             G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3783
3784         snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3785             G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3786             G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3787             G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3788             G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3789
3790         param[0] = FW_PARAM_DEV(PORTVEC);
3791         param[1] = FW_PARAM_DEV(CCLK);
3792         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3793         if (rc != 0) {
3794                 device_printf(sc->dev,
3795                     "failed to query parameters (pre_init): %d.\n", rc);
3796                 return (rc);
3797         }
3798
3799         sc->params.portvec = val[0];
3800         sc->params.nports = bitcount32(val[0]);
3801         sc->params.vpd.cclk = val[1];
3802
3803         /* Read device log parameters. */
3804         rc = -t4_init_devlog_params(sc, 1);
3805         if (rc == 0)
3806                 fixup_devlog_params(sc);
3807         else {
3808                 device_printf(sc->dev,
3809                     "failed to get devlog parameters: %d.\n", rc);
3810                 rc = 0; /* devlog isn't critical for device operation */
3811         }
3812
3813         return (rc);
3814 }
3815
3816 /*
3817  * Retrieve various parameters that are of interest to the driver.  The device
3818  * has been initialized by the firmware at this point.
3819  */
3820 static int
3821 get_params__post_init(struct adapter *sc)
3822 {
3823         int rc;
3824         uint32_t param[7], val[7];
3825         struct fw_caps_config_cmd caps;
3826
3827         param[0] = FW_PARAM_PFVF(IQFLINT_START);
3828         param[1] = FW_PARAM_PFVF(EQ_START);
3829         param[2] = FW_PARAM_PFVF(FILTER_START);
3830         param[3] = FW_PARAM_PFVF(FILTER_END);
3831         param[4] = FW_PARAM_PFVF(L2T_START);
3832         param[5] = FW_PARAM_PFVF(L2T_END);
3833         param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3834             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
3835             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
3836         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
3837         if (rc != 0) {
3838                 device_printf(sc->dev,
3839                     "failed to query parameters (post_init): %d.\n", rc);
3840                 return (rc);
3841         }
3842
3843         sc->sge.iq_start = val[0];
3844         sc->sge.eq_start = val[1];
3845         sc->tids.ftid_base = val[2];
3846         sc->tids.nftids = val[3] - val[2] + 1;
3847         sc->params.ftid_min = val[2];
3848         sc->params.ftid_max = val[3];
3849         sc->vres.l2t.start = val[4];
3850         sc->vres.l2t.size = val[5] - val[4] + 1;
3851         KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3852             ("%s: L2 table size (%u) larger than expected (%u)",
3853             __func__, sc->vres.l2t.size, L2T_SIZE));
3854         sc->params.core_vdd = val[6];
3855
3856         /*
3857          * MPSBGMAP is queried separately because only recent firmwares support
3858          * it as a parameter and we don't want the compound query above to fail
3859          * on older firmwares.
3860          */
3861         param[0] = FW_PARAM_DEV(MPSBGMAP);
3862         val[0] = 0;
3863         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3864         if (rc == 0)
3865                 sc->params.mps_bg_map = val[0];
3866         else
3867                 sc->params.mps_bg_map = 0;
3868
3869         /* get capabilites */
3870         bzero(&caps, sizeof(caps));
3871         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3872             F_FW_CMD_REQUEST | F_FW_CMD_READ);
3873         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3874         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3875         if (rc != 0) {
3876                 device_printf(sc->dev,
3877                     "failed to get card capabilities: %d.\n", rc);
3878                 return (rc);
3879         }
3880
3881 #define READ_CAPS(x) do { \
3882         sc->x = htobe16(caps.x); \
3883 } while (0)
3884         READ_CAPS(nbmcaps);
3885         READ_CAPS(linkcaps);
3886         READ_CAPS(switchcaps);
3887         READ_CAPS(niccaps);
3888         READ_CAPS(toecaps);
3889         READ_CAPS(rdmacaps);
3890         READ_CAPS(cryptocaps);
3891         READ_CAPS(iscsicaps);
3892         READ_CAPS(fcoecaps);
3893
3894         /*
3895          * The firmware attempts memfree TOE configuration for -SO cards and
3896          * will report toecaps=0 if it runs out of resources (this depends on
3897          * the config file).  It may not report 0 for other capabilities
3898          * dependent on the TOE in this case.  Set them to 0 here so that the
3899          * driver doesn't bother tracking resources that will never be used.
3900          */
3901         if (sc->toecaps == 0) {
3902                 sc->iscsicaps = 0;
3903                 sc->rdmacaps = 0;
3904         }
3905
3906         if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3907                 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3908                 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3909                 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3910                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3911                 if (rc != 0) {
3912                         device_printf(sc->dev,
3913                             "failed to query NIC parameters: %d.\n", rc);
3914                         return (rc);
3915                 }
3916                 sc->tids.etid_base = val[0];
3917                 sc->params.etid_min = val[0];
3918                 sc->tids.netids = val[1] - val[0] + 1;
3919                 sc->params.netids = sc->tids.netids;
3920                 sc->params.eo_wr_cred = val[2];
3921                 sc->params.ethoffload = 1;
3922         }
3923
3924         if (sc->toecaps) {
3925                 /* query offload-related parameters */
3926                 param[0] = FW_PARAM_DEV(NTID);
3927                 param[1] = FW_PARAM_PFVF(SERVER_START);
3928                 param[2] = FW_PARAM_PFVF(SERVER_END);
3929                 param[3] = FW_PARAM_PFVF(TDDP_START);
3930                 param[4] = FW_PARAM_PFVF(TDDP_END);
3931                 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3932                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3933                 if (rc != 0) {
3934                         device_printf(sc->dev,
3935                             "failed to query TOE parameters: %d.\n", rc);
3936                         return (rc);
3937                 }
3938                 sc->tids.ntids = val[0];
3939                 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3940                 sc->tids.stid_base = val[1];
3941                 sc->tids.nstids = val[2] - val[1] + 1;
3942                 sc->vres.ddp.start = val[3];
3943                 sc->vres.ddp.size = val[4] - val[3] + 1;
3944                 sc->params.ofldq_wr_cred = val[5];
3945                 sc->params.offload = 1;
3946         }
3947         if (sc->rdmacaps) {
3948                 param[0] = FW_PARAM_PFVF(STAG_START);
3949                 param[1] = FW_PARAM_PFVF(STAG_END);
3950                 param[2] = FW_PARAM_PFVF(RQ_START);
3951                 param[3] = FW_PARAM_PFVF(RQ_END);
3952                 param[4] = FW_PARAM_PFVF(PBL_START);
3953                 param[5] = FW_PARAM_PFVF(PBL_END);
3954                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3955                 if (rc != 0) {
3956                         device_printf(sc->dev,
3957                             "failed to query RDMA parameters(1): %d.\n", rc);
3958                         return (rc);
3959                 }
3960                 sc->vres.stag.start = val[0];
3961                 sc->vres.stag.size = val[1] - val[0] + 1;
3962                 sc->vres.rq.start = val[2];
3963                 sc->vres.rq.size = val[3] - val[2] + 1;
3964                 sc->vres.pbl.start = val[4];
3965                 sc->vres.pbl.size = val[5] - val[4] + 1;
3966
3967                 param[0] = FW_PARAM_PFVF(SQRQ_START);
3968                 param[1] = FW_PARAM_PFVF(SQRQ_END);
3969                 param[2] = FW_PARAM_PFVF(CQ_START);
3970                 param[3] = FW_PARAM_PFVF(CQ_END);
3971                 param[4] = FW_PARAM_PFVF(OCQ_START);
3972                 param[5] = FW_PARAM_PFVF(OCQ_END);
3973                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3974                 if (rc != 0) {
3975                         device_printf(sc->dev,
3976                             "failed to query RDMA parameters(2): %d.\n", rc);
3977                         return (rc);
3978                 }
3979                 sc->vres.qp.start = val[0];
3980                 sc->vres.qp.size = val[1] - val[0] + 1;
3981                 sc->vres.cq.start = val[2];
3982                 sc->vres.cq.size = val[3] - val[2] + 1;
3983                 sc->vres.ocq.start = val[4];
3984                 sc->vres.ocq.size = val[5] - val[4] + 1;
3985
3986                 param[0] = FW_PARAM_PFVF(SRQ_START);
3987                 param[1] = FW_PARAM_PFVF(SRQ_END);
3988                 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
3989                 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3990                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
3991                 if (rc != 0) {
3992                         device_printf(sc->dev,
3993                             "failed to query RDMA parameters(3): %d.\n", rc);
3994                         return (rc);
3995                 }
3996                 sc->vres.srq.start = val[0];
3997                 sc->vres.srq.size = val[1] - val[0] + 1;
3998                 sc->params.max_ordird_qp = val[2];
3999                 sc->params.max_ird_adapter = val[3];
4000         }
4001         if (sc->iscsicaps) {
4002                 param[0] = FW_PARAM_PFVF(ISCSI_START);
4003                 param[1] = FW_PARAM_PFVF(ISCSI_END);
4004                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4005                 if (rc != 0) {
4006                         device_printf(sc->dev,
4007                             "failed to query iSCSI parameters: %d.\n", rc);
4008                         return (rc);
4009                 }
4010                 sc->vres.iscsi.start = val[0];
4011                 sc->vres.iscsi.size = val[1] - val[0] + 1;
4012         }
4013         if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4014                 param[0] = FW_PARAM_PFVF(TLS_START);
4015                 param[1] = FW_PARAM_PFVF(TLS_END);
4016                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4017                 if (rc != 0) {
4018                         device_printf(sc->dev,
4019                             "failed to query TLS parameters: %d.\n", rc);
4020                         return (rc);
4021                 }
4022                 sc->vres.key.start = val[0];
4023                 sc->vres.key.size = val[1] - val[0] + 1;
4024         }
4025
4026         t4_init_sge_params(sc);
4027
4028         /*
4029          * We've got the params we wanted to query via the firmware.  Now grab
4030          * some others directly from the chip.
4031          */
4032         rc = t4_read_chip_settings(sc);
4033
4034         return (rc);
4035 }
4036
4037 static int
4038 set_params__post_init(struct adapter *sc)
4039 {
4040         uint32_t param, val;
4041 #ifdef TCP_OFFLOAD
4042         int i, v, shift;
4043 #endif
4044
4045         /* ask for encapsulated CPLs */
4046         param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4047         val = 1;
4048         (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
4049
4050         /* Enable 32b port caps if the firmware supports it. */
4051         param = FW_PARAM_PFVF(PORT_CAPS32);
4052         val = 1;
4053         if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val) == 0)
4054                 sc->params.port_caps32 = 1;
4055
4056 #ifdef TCP_OFFLOAD
4057         /*
4058          * Override the TOE timers with user provided tunables.  This is not the
4059          * recommended way to change the timers (the firmware config file is) so
4060          * these tunables are not documented.
4061          *
4062          * All the timer tunables are in microseconds.
4063          */
4064         if (t4_toe_keepalive_idle != 0) {
4065                 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4066                 v &= M_KEEPALIVEIDLE;
4067                 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4068                     V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4069         }
4070         if (t4_toe_keepalive_interval != 0) {
4071                 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4072                 v &= M_KEEPALIVEINTVL;
4073                 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4074                     V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4075         }
4076         if (t4_toe_keepalive_count != 0) {
4077                 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4078                 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4079                     V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4080                     V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4081                     V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4082         }
4083         if (t4_toe_rexmt_min != 0) {
4084                 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4085                 v &= M_RXTMIN;
4086                 t4_set_reg_field(sc, A_TP_RXT_MIN,
4087                     V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4088         }
4089         if (t4_toe_rexmt_max != 0) {
4090                 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4091                 v &= M_RXTMAX;
4092                 t4_set_reg_field(sc, A_TP_RXT_MAX,
4093                     V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4094         }
4095         if (t4_toe_rexmt_count != 0) {
4096                 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4097                 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4098                     V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4099                     V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4100                     V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4101         }
4102         for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4103                 if (t4_toe_rexmt_backoff[i] != -1) {
4104                         v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4105                         shift = (i & 3) << 3;
4106                         t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4107                             M_TIMERBACKOFFINDEX0 << shift, v << shift);
4108                 }
4109         }
4110 #endif
4111         return (0);
4112 }
4113
4114 #undef FW_PARAM_PFVF
4115 #undef FW_PARAM_DEV
4116
4117 static void
4118 t4_set_desc(struct adapter *sc)
4119 {
4120         char buf[128];
4121         struct adapter_params *p = &sc->params;
4122
4123         snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4124
4125         device_set_desc_copy(sc->dev, buf);
4126 }
4127
4128 static inline void
4129 ifmedia_add4(struct ifmedia *ifm, int m)
4130 {
4131
4132         ifmedia_add(ifm, m, 0, NULL);
4133         ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4134         ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4135         ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4136 }
4137
4138 /*
4139  * This is the selected media, which is not quite the same as the active media.
4140  * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4141  * and active are not the same, and "media: Ethernet selected" otherwise.
4142  */
4143 static void
4144 set_current_media(struct port_info *pi)
4145 {
4146         struct link_config *lc;
4147         struct ifmedia *ifm;
4148         int mword;
4149         u_int speed;
4150
4151         PORT_LOCK_ASSERT_OWNED(pi);
4152
4153         /* Leave current media alone if it's already set to IFM_NONE. */
4154         ifm = &pi->media;
4155         if (ifm->ifm_cur != NULL &&
4156             IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4157                 return;
4158
4159         lc = &pi->link_cfg;
4160         if (lc->requested_aneg != AUTONEG_DISABLE &&
4161             lc->supported & FW_PORT_CAP32_ANEG) {
4162                 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4163                 return;
4164         }
4165         mword = IFM_ETHER | IFM_FDX;
4166         if (lc->requested_fc & PAUSE_TX)
4167                 mword |= IFM_ETH_TXPAUSE;
4168         if (lc->requested_fc & PAUSE_RX)
4169                 mword |= IFM_ETH_RXPAUSE;
4170         if (lc->requested_speed == 0)
4171                 speed = port_top_speed(pi) * 1000;      /* Gbps -> Mbps */
4172         else
4173                 speed = lc->requested_speed;
4174         mword |= port_mword(pi, speed_to_fwcap(speed));
4175         ifmedia_set(ifm, mword);
4176 }
4177
4178 /*
4179  * Returns true if the ifmedia list for the port cannot change.
4180  */
4181 static bool
4182 fixed_ifmedia(struct port_info *pi)
4183 {
4184
4185         return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4186             pi->port_type == FW_PORT_TYPE_BT_XFI ||
4187             pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4188             pi->port_type == FW_PORT_TYPE_KX4 ||
4189             pi->port_type == FW_PORT_TYPE_KX ||
4190             pi->port_type == FW_PORT_TYPE_KR ||
4191             pi->port_type == FW_PORT_TYPE_BP_AP ||
4192             pi->port_type == FW_PORT_TYPE_BP4_AP ||
4193             pi->port_type == FW_PORT_TYPE_BP40_BA ||
4194             pi->port_type == FW_PORT_TYPE_KR4_100G ||
4195             pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4196             pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4197 }
4198
4199 static void
4200 build_medialist(struct port_info *pi)
4201 {
4202         uint32_t ss, speed;
4203         int unknown, mword, bit;
4204         struct link_config *lc;
4205         struct ifmedia *ifm;
4206
4207         PORT_LOCK_ASSERT_OWNED(pi);
4208
4209         if (pi->flags & FIXED_IFMEDIA)
4210                 return;
4211
4212         /*
4213          * Rebuild the ifmedia list.
4214          */
4215         ifm = &pi->media;
4216         ifmedia_removeall(ifm);
4217         lc = &pi->link_cfg;
4218         ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4219         if (__predict_false(ss == 0)) { /* not supposed to happen. */
4220                 MPASS(ss != 0);
4221 no_media:
4222                 MPASS(LIST_EMPTY(&ifm->ifm_list));
4223                 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4224                 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4225                 return;
4226         }
4227
4228         unknown = 0;
4229         for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4230                 speed = 1 << bit;
4231                 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4232                 if (ss & speed) {
4233                         mword = port_mword(pi, speed);
4234                         if (mword == IFM_NONE) {
4235                                 goto no_media;
4236                         } else if (mword == IFM_UNKNOWN)
4237                                 unknown++;
4238                         else
4239                                 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4240                 }
4241         }
4242         if (unknown > 0) /* Add one unknown for all unknown media types. */
4243                 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4244         if (lc->supported & FW_PORT_CAP32_ANEG)
4245                 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4246
4247         set_current_media(pi);
4248 }
4249
4250 /*
4251  * Initialize the requested fields in the link config based on driver tunables.
4252  */
4253 static void
4254 init_link_config(struct port_info *pi)
4255 {
4256         struct link_config *lc = &pi->link_cfg;
4257
4258         PORT_LOCK_ASSERT_OWNED(pi);
4259
4260         lc->requested_speed = 0;
4261
4262         if (t4_autoneg == 0)
4263                 lc->requested_aneg = AUTONEG_DISABLE;
4264         else if (t4_autoneg == 1)
4265                 lc->requested_aneg = AUTONEG_ENABLE;
4266         else
4267                 lc->requested_aneg = AUTONEG_AUTO;
4268
4269         lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4270             PAUSE_AUTONEG);
4271
4272         if (t4_fec == -1 || t4_fec & FEC_AUTO)
4273                 lc->requested_fec = FEC_AUTO;
4274         else {
4275                 lc->requested_fec = FEC_NONE;
4276                 if (t4_fec & FEC_RS)
4277                         lc->requested_fec |= FEC_RS;
4278                 if (t4_fec & FEC_BASER_RS)
4279                         lc->requested_fec |= FEC_BASER_RS;
4280         }
4281 }
4282
4283 /*
4284  * Makes sure that all requested settings comply with what's supported by the
4285  * port.  Returns the number of settings that were invalid and had to be fixed.
4286  */
4287 static int
4288 fixup_link_config(struct port_info *pi)
4289 {
4290         int n = 0;
4291         struct link_config *lc = &pi->link_cfg;
4292         uint32_t fwspeed;
4293
4294         PORT_LOCK_ASSERT_OWNED(pi);
4295
4296         /* Speed (when not autonegotiating) */
4297         if (lc->requested_speed != 0) {
4298                 fwspeed = speed_to_fwcap(lc->requested_speed);
4299                 if ((fwspeed & lc->supported) == 0) {
4300                         n++;
4301                         lc->requested_speed = 0;
4302                 }
4303         }
4304
4305         /* Link autonegotiation */
4306         MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4307             lc->requested_aneg == AUTONEG_DISABLE ||
4308             lc->requested_aneg == AUTONEG_AUTO);
4309         if (lc->requested_aneg == AUTONEG_ENABLE &&
4310             !(lc->supported & FW_PORT_CAP32_ANEG)) {
4311                 n++;
4312                 lc->requested_aneg = AUTONEG_AUTO;
4313         }
4314
4315         /* Flow control */
4316         MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4317         if (lc->requested_fc & PAUSE_TX &&
4318             !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4319                 n++;
4320                 lc->requested_fc &= ~PAUSE_TX;
4321         }
4322         if (lc->requested_fc & PAUSE_RX &&
4323             !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4324                 n++;
4325                 lc->requested_fc &= ~PAUSE_RX;
4326         }
4327         if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4328             !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4329                 n++;
4330                 lc->requested_fc |= PAUSE_AUTONEG;
4331         }
4332
4333         /* FEC */
4334         if ((lc->requested_fec & FEC_RS &&
4335             !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4336             (lc->requested_fec & FEC_BASER_RS &&
4337             !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4338                 n++;
4339                 lc->requested_fec = FEC_AUTO;
4340         }
4341
4342         return (n);
4343 }
4344
4345 /*
4346  * Apply the requested L1 settings, which are expected to be valid, to the
4347  * hardware.
4348  */
4349 static int
4350 apply_link_config(struct port_info *pi)
4351 {
4352         struct adapter *sc = pi->adapter;
4353         struct link_config *lc = &pi->link_cfg;
4354         int rc;
4355
4356 #ifdef INVARIANTS
4357         ASSERT_SYNCHRONIZED_OP(sc);
4358         PORT_LOCK_ASSERT_OWNED(pi);
4359
4360         if (lc->requested_aneg == AUTONEG_ENABLE)
4361                 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4362         if (!(lc->requested_fc & PAUSE_AUTONEG))
4363                 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4364         if (lc->requested_fc & PAUSE_TX)
4365                 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4366         if (lc->requested_fc & PAUSE_RX)
4367                 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4368         if (lc->requested_fec & FEC_RS)
4369                 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4370         if (lc->requested_fec & FEC_BASER_RS)
4371                 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4372 #endif
4373         rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4374         if (rc != 0) {
4375                 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4376         } else {
4377                 /*
4378                  * An L1_CFG will almost always result in a link-change event if
4379                  * the link is up, and the driver will refresh the actual
4380                  * fec/fc/etc. when the notification is processed.  If the link
4381                  * is down then the actual settings are meaningless.
4382                  *
4383                  * This takes care of the case where a change in the L1 settings
4384                  * may not result in a notification.
4385                  */
4386                 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4387                         lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4388         }
4389         return (rc);
4390 }
4391
4392 #define FW_MAC_EXACT_CHUNK      7
4393
4394 /*
4395  * Program the port's XGMAC based on parameters in ifnet.  The caller also
4396  * indicates which parameters should be programmed (the rest are left alone).
4397  */
4398 int
4399 update_mac_settings(struct ifnet *ifp, int flags)
4400 {
4401         int rc = 0;
4402         struct vi_info *vi = ifp->if_softc;
4403         struct port_info *pi = vi->pi;
4404         struct adapter *sc = pi->adapter;
4405         int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4406
4407         ASSERT_SYNCHRONIZED_OP(sc);
4408         KASSERT(flags, ("%s: not told what to update.", __func__));
4409
4410         if (flags & XGMAC_MTU)
4411                 mtu = ifp->if_mtu;
4412
4413         if (flags & XGMAC_PROMISC)
4414                 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4415
4416         if (flags & XGMAC_ALLMULTI)
4417                 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4418
4419         if (flags & XGMAC_VLANEX)
4420                 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4421
4422         if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4423                 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4424                     allmulti, 1, vlanex, false);
4425                 if (rc) {
4426                         if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4427                             rc);
4428                         return (rc);
4429                 }
4430         }
4431
4432         if (flags & XGMAC_UCADDR) {
4433                 uint8_t ucaddr[ETHER_ADDR_LEN];
4434
4435                 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4436                 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4437                     ucaddr, true, true);
4438                 if (rc < 0) {
4439                         rc = -rc;
4440                         if_printf(ifp, "change_mac failed: %d\n", rc);
4441                         return (rc);
4442                 } else {
4443                         vi->xact_addr_filt = rc;
4444                         rc = 0;
4445                 }
4446         }
4447
4448         if (flags & XGMAC_MCADDRS) {
4449                 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4450                 int del = 1;
4451                 uint64_t hash = 0;
4452                 struct ifmultiaddr *ifma;
4453                 int i = 0, j;
4454
4455                 if_maddr_rlock(ifp);
4456                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4457                         if (ifma->ifma_addr->sa_family != AF_LINK)
4458                                 continue;
4459                         mcaddr[i] =
4460                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4461                         MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4462                         i++;
4463
4464                         if (i == FW_MAC_EXACT_CHUNK) {
4465                                 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4466                                     del, i, mcaddr, NULL, &hash, 0);
4467                                 if (rc < 0) {
4468                                         rc = -rc;
4469                                         for (j = 0; j < i; j++) {
4470                                                 if_printf(ifp,
4471                                                     "failed to add mc address"
4472                                                     " %02x:%02x:%02x:"
4473                                                     "%02x:%02x:%02x rc=%d\n",
4474                                                     mcaddr[j][0], mcaddr[j][1],
4475                                                     mcaddr[j][2], mcaddr[j][3],
4476                                                     mcaddr[j][4], mcaddr[j][5],
4477                                                     rc);
4478                                         }
4479                                         goto mcfail;
4480                                 }
4481                                 del = 0;
4482                                 i = 0;
4483                         }
4484                 }
4485                 if (i > 0) {
4486                         rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4487                             mcaddr, NULL, &hash, 0);
4488                         if (rc < 0) {
4489                                 rc = -rc;
4490                                 for (j = 0; j < i; j++) {
4491                                         if_printf(ifp,
4492                                             "failed to add mc address"
4493                                             " %02x:%02x:%02x:"
4494                                             "%02x:%02x:%02x rc=%d\n",
4495                                             mcaddr[j][0], mcaddr[j][1],
4496                                             mcaddr[j][2], mcaddr[j][3],
4497                                             mcaddr[j][4], mcaddr[j][5],
4498                                             rc);
4499                                 }
4500                                 goto mcfail;
4501                         }
4502                 }
4503
4504                 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4505                 if (rc != 0)
4506                         if_printf(ifp, "failed to set mc address hash: %d", rc);
4507 mcfail:
4508                 if_maddr_runlock(ifp);
4509         }
4510
4511         return (rc);
4512 }
4513
4514 /*
4515  * {begin|end}_synchronized_op must be called from the same thread.
4516  */
4517 int
4518 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4519     char *wmesg)
4520 {
4521         int rc, pri;
4522
4523 #ifdef WITNESS
4524         /* the caller thinks it's ok to sleep, but is it really? */
4525         if (flags & SLEEP_OK)
4526                 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4527                     "begin_synchronized_op");
4528 #endif
4529
4530         if (INTR_OK)
4531                 pri = PCATCH;
4532         else
4533                 pri = 0;
4534
4535         ADAPTER_LOCK(sc);
4536         for (;;) {
4537
4538                 if (vi && IS_DOOMED(vi)) {
4539                         rc = ENXIO;
4540                         goto done;
4541                 }
4542
4543                 if (!IS_BUSY(sc)) {
4544                         rc = 0;
4545                         break;
4546                 }
4547
4548                 if (!(flags & SLEEP_OK)) {
4549                         rc = EBUSY;
4550                         goto done;
4551                 }
4552
4553                 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4554                         rc = EINTR;
4555                         goto done;
4556                 }
4557         }
4558
4559         KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4560         SET_BUSY(sc);
4561 #ifdef INVARIANTS
4562         sc->last_op = wmesg;
4563         sc->last_op_thr = curthread;
4564         sc->last_op_flags = flags;
4565 #endif
4566
4567 done:
4568         if (!(flags & HOLD_LOCK) || rc)
4569                 ADAPTER_UNLOCK(sc);
4570
4571         return (rc);
4572 }
4573
4574 /*
4575  * Tell if_ioctl and if_init that the VI is going away.  This is
4576  * special variant of begin_synchronized_op and must be paired with a
4577  * call to end_synchronized_op.
4578  */
4579 void
4580 doom_vi(struct adapter *sc, struct vi_info *vi)
4581 {
4582
4583         ADAPTER_LOCK(sc);
4584         SET_DOOMED(vi);
4585         wakeup(&sc->flags);
4586         while (IS_BUSY(sc))
4587                 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4588         SET_BUSY(sc);
4589 #ifdef INVARIANTS
4590         sc->last_op = "t4detach";
4591         sc->last_op_thr = curthread;
4592         sc->last_op_flags = 0;
4593 #endif
4594         ADAPTER_UNLOCK(sc);
4595 }
4596
4597 /*
4598  * {begin|end}_synchronized_op must be called from the same thread.
4599  */
4600 void
4601 end_synchronized_op(struct adapter *sc, int flags)
4602 {
4603
4604         if (flags & LOCK_HELD)
4605                 ADAPTER_LOCK_ASSERT_OWNED(sc);
4606         else
4607                 ADAPTER_LOCK(sc);
4608
4609         KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4610         CLR_BUSY(sc);
4611         wakeup(&sc->flags);
4612         ADAPTER_UNLOCK(sc);
4613 }
4614
4615 static int
4616 cxgbe_init_synchronized(struct vi_info *vi)
4617 {
4618         struct port_info *pi = vi->pi;
4619         struct adapter *sc = pi->adapter;
4620         struct ifnet *ifp = vi->ifp;
4621         int rc = 0, i;
4622         struct sge_txq *txq;
4623
4624         ASSERT_SYNCHRONIZED_OP(sc);
4625
4626         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4627                 return (0);     /* already running */
4628
4629         if (!(sc->flags & FULL_INIT_DONE) &&
4630             ((rc = adapter_full_init(sc)) != 0))
4631                 return (rc);    /* error message displayed already */
4632
4633         if (!(vi->flags & VI_INIT_DONE) &&
4634             ((rc = vi_full_init(vi)) != 0))
4635                 return (rc); /* error message displayed already */
4636
4637         rc = update_mac_settings(ifp, XGMAC_ALL);
4638         if (rc)
4639                 goto done;      /* error message displayed already */
4640
4641         PORT_LOCK(pi);
4642         if (pi->up_vis == 0) {
4643                 t4_update_port_info(pi);
4644                 fixup_link_config(pi);
4645                 build_medialist(pi);
4646                 apply_link_config(pi);
4647         }
4648
4649         rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4650         if (rc != 0) {
4651                 if_printf(ifp, "enable_vi failed: %d\n", rc);
4652                 PORT_UNLOCK(pi);
4653                 goto done;
4654         }
4655
4656         /*
4657          * Can't fail from this point onwards.  Review cxgbe_uninit_synchronized
4658          * if this changes.
4659          */
4660
4661         for_each_txq(vi, i, txq) {
4662                 TXQ_LOCK(txq);
4663                 txq->eq.flags |= EQ_ENABLED;
4664                 TXQ_UNLOCK(txq);
4665         }
4666
4667         /*
4668          * The first iq of the first port to come up is used for tracing.
4669          */
4670         if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4671                 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4672                 t4_write_reg(sc, is_t4(sc) ?  A_MPS_TRC_RSS_CONTROL :
4673                     A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4674                     V_QUEUENUMBER(sc->traceq));
4675                 pi->flags |= HAS_TRACEQ;
4676         }
4677
4678         /* all ok */
4679         pi->up_vis++;
4680         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4681
4682         if (pi->nvi > 1 || sc->flags & IS_VF)
4683                 callout_reset(&vi->tick, hz, vi_tick, vi);
4684         else
4685                 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4686         PORT_UNLOCK(pi);
4687 done:
4688         if (rc != 0)
4689                 cxgbe_uninit_synchronized(vi);
4690
4691         return (rc);
4692 }
4693
4694 /*
4695  * Idempotent.
4696  */
4697 static int
4698 cxgbe_uninit_synchronized(struct vi_info *vi)
4699 {
4700         struct port_info *pi = vi->pi;
4701         struct adapter *sc = pi->adapter;
4702         struct ifnet *ifp = vi->ifp;
4703         int rc, i;
4704         struct sge_txq *txq;
4705
4706         ASSERT_SYNCHRONIZED_OP(sc);
4707
4708         if (!(vi->flags & VI_INIT_DONE)) {
4709                 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4710                         KASSERT(0, ("uninited VI is running"));
4711                         if_printf(ifp, "uninited VI with running ifnet.  "
4712                             "vi->flags 0x%016lx, if_flags 0x%08x, "
4713                             "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
4714                             ifp->if_drv_flags);
4715                 }
4716                 return (0);
4717         }
4718
4719         /*
4720          * Disable the VI so that all its data in either direction is discarded
4721          * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
4722          * tick) intact as the TP can deliver negative advice or data that it's
4723          * holding in its RAM (for an offloaded connection) even after the VI is
4724          * disabled.
4725          */
4726         rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4727         if (rc) {
4728                 if_printf(ifp, "disable_vi failed: %d\n", rc);
4729                 return (rc);
4730         }
4731
4732         for_each_txq(vi, i, txq) {
4733                 TXQ_LOCK(txq);
4734                 txq->eq.flags &= ~EQ_ENABLED;
4735                 TXQ_UNLOCK(txq);
4736         }
4737
4738         PORT_LOCK(pi);
4739         if (pi->nvi > 1 || sc->flags & IS_VF)
4740                 callout_stop(&vi->tick);
4741         else
4742                 callout_stop(&pi->tick);
4743         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4744                 PORT_UNLOCK(pi);
4745                 return (0);
4746         }
4747         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4748         pi->up_vis--;
4749         if (pi->up_vis > 0) {
4750                 PORT_UNLOCK(pi);
4751                 return (0);
4752         }
4753
4754         pi->link_cfg.link_ok = false;
4755         pi->link_cfg.speed = 0;
4756         pi->link_cfg.link_down_rc = 255;
4757         t4_os_link_changed(pi);
4758         PORT_UNLOCK(pi);
4759
4760         return (0);
4761 }
4762
4763 /*
4764  * It is ok for this function to fail midway and return right away.  t4_detach
4765  * will walk the entire sc->irq list and clean up whatever is valid.
4766  */
4767 int
4768 t4_setup_intr_handlers(struct adapter *sc)
4769 {
4770         int rc, rid, p, q, v;
4771         char s[8];
4772         struct irq *irq;
4773         struct port_info *pi;
4774         struct vi_info *vi;
4775         struct sge *sge = &sc->sge;
4776         struct sge_rxq *rxq;
4777 #ifdef TCP_OFFLOAD
4778         struct sge_ofld_rxq *ofld_rxq;
4779 #endif
4780 #ifdef DEV_NETMAP
4781         struct sge_nm_rxq *nm_rxq;
4782 #endif
4783 #ifdef RSS
4784         int nbuckets = rss_getnumbuckets();
4785 #endif
4786
4787         /*
4788          * Setup interrupts.
4789          */
4790         irq = &sc->irq[0];
4791         rid = sc->intr_type == INTR_INTX ? 0 : 1;
4792         if (forwarding_intr_to_fwq(sc))
4793                 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4794
4795         /* Multiple interrupts. */
4796         if (sc->flags & IS_VF)
4797                 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4798                     ("%s: too few intr.", __func__));
4799         else
4800                 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4801                     ("%s: too few intr.", __func__));
4802
4803         /* The first one is always error intr on PFs */
4804         if (!(sc->flags & IS_VF)) {
4805                 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4806                 if (rc != 0)
4807                         return (rc);
4808                 irq++;
4809                 rid++;
4810         }
4811
4812         /* The second one is always the firmware event queue (first on VFs) */
4813         rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4814         if (rc != 0)
4815                 return (rc);
4816         irq++;
4817         rid++;
4818
4819         for_each_port(sc, p) {
4820                 pi = sc->port[p];
4821                 for_each_vi(pi, v, vi) {
4822                         vi->first_intr = rid - 1;
4823
4824                         if (vi->nnmrxq > 0) {
4825                                 int n = max(vi->nrxq, vi->nnmrxq);
4826
4827                                 rxq = &sge->rxq[vi->first_rxq];
4828 #ifdef DEV_NETMAP
4829                                 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4830 #endif
4831                                 for (q = 0; q < n; q++) {
4832                                         snprintf(s, sizeof(s), "%x%c%x", p,
4833                                             'a' + v, q);
4834                                         if (q < vi->nrxq)
4835                                                 irq->rxq = rxq++;
4836 #ifdef DEV_NETMAP
4837                                         if (q < vi->nnmrxq)
4838                                                 irq->nm_rxq = nm_rxq++;
4839 #endif
4840                                         rc = t4_alloc_irq(sc, irq, rid,
4841                                             t4_vi_intr, irq, s);
4842                                         if (rc != 0)
4843                                                 return (rc);
4844 #ifdef RSS
4845                                         if (q < vi->nrxq) {
4846                                                 bus_bind_intr(sc->dev, irq->res,
4847                                                     rss_getcpu(q % nbuckets));
4848                                         }
4849 #endif
4850                                         irq++;
4851                                         rid++;
4852                                         vi->nintr++;
4853                                 }
4854                         } else {
4855                                 for_each_rxq(vi, q, rxq) {
4856                                         snprintf(s, sizeof(s), "%x%c%x", p,
4857                                             'a' + v, q);
4858                                         rc = t4_alloc_irq(sc, irq, rid,
4859                                             t4_intr, rxq, s);
4860                                         if (rc != 0)
4861                                                 return (rc);
4862 #ifdef RSS
4863                                         bus_bind_intr(sc->dev, irq->res,
4864                                             rss_getcpu(q % nbuckets));
4865 #endif
4866                                         irq++;
4867                                         rid++;
4868                                         vi->nintr++;
4869                                 }
4870                         }
4871 #ifdef TCP_OFFLOAD
4872                         for_each_ofld_rxq(vi, q, ofld_rxq) {
4873                                 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
4874                                 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
4875                                     ofld_rxq, s);
4876                                 if (rc != 0)
4877                                         return (rc);
4878                                 irq++;
4879                                 rid++;
4880                                 vi->nintr++;
4881                         }
4882 #endif
4883                 }
4884         }
4885         MPASS(irq == &sc->irq[sc->intr_count]);
4886
4887         return (0);
4888 }
4889
4890 int
4891 adapter_full_init(struct adapter *sc)
4892 {
4893         int rc, i;
4894 #ifdef RSS
4895         uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4896         uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4897 #endif
4898
4899         ASSERT_SYNCHRONIZED_OP(sc);
4900         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4901         KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4902             ("%s: FULL_INIT_DONE already", __func__));
4903
4904         /*
4905          * queues that belong to the adapter (not any particular port).
4906          */
4907         rc = t4_setup_adapter_queues(sc);
4908         if (rc != 0)
4909                 goto done;
4910
4911         for (i = 0; i < nitems(sc->tq); i++) {
4912                 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4913                     taskqueue_thread_enqueue, &sc->tq[i]);
4914                 if (sc->tq[i] == NULL) {
4915                         device_printf(sc->dev,
4916                             "failed to allocate task queue %d\n", i);
4917                         rc = ENOMEM;
4918                         goto done;
4919                 }
4920                 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4921                     device_get_nameunit(sc->dev), i);
4922         }
4923 #ifdef RSS
4924         MPASS(RSS_KEYSIZE == 40);
4925         rss_getkey((void *)&raw_rss_key[0]);
4926         for (i = 0; i < nitems(rss_key); i++) {
4927                 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4928         }
4929         t4_write_rss_key(sc, &rss_key[0], -1, 1);
4930 #endif
4931
4932         if (!(sc->flags & IS_VF))
4933                 t4_intr_enable(sc);
4934         sc->flags |= FULL_INIT_DONE;
4935 done:
4936         if (rc != 0)
4937                 adapter_full_uninit(sc);
4938
4939         return (rc);
4940 }
4941
4942 int
4943 adapter_full_uninit(struct adapter *sc)
4944 {
4945         int i;
4946
4947         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4948
4949         t4_teardown_adapter_queues(sc);
4950
4951         for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4952                 taskqueue_free(sc->tq[i]);
4953                 sc->tq[i] = NULL;
4954         }
4955
4956         sc->flags &= ~FULL_INIT_DONE;
4957
4958         return (0);
4959 }
4960
4961 #ifdef RSS
4962 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4963     RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4964     RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4965     RSS_HASHTYPE_RSS_UDP_IPV6)
4966
4967 /* Translates kernel hash types to hardware. */
4968 static int
4969 hashconfig_to_hashen(int hashconfig)
4970 {
4971         int hashen = 0;
4972
4973         if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4974                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4975         if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4976                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4977         if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4978                 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4979                     F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4980         }
4981         if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4982                 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4983                     F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4984         }
4985         if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4986                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4987         if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4988                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4989
4990         return (hashen);
4991 }
4992
4993 /* Translates hardware hash types to kernel. */
4994 static int
4995 hashen_to_hashconfig(int hashen)
4996 {
4997         int hashconfig = 0;
4998
4999         if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5000                 /*
5001                  * If UDP hashing was enabled it must have been enabled for
5002                  * either IPv4 or IPv6 (inclusive or).  Enabling UDP without
5003                  * enabling any 4-tuple hash is nonsense configuration.
5004                  */
5005                 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5006                     F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5007
5008                 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5009                         hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5010                 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5011                         hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5012         }
5013         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5014                 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5015         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5016                 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5017         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5018                 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5019         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5020                 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5021
5022         return (hashconfig);
5023 }
5024 #endif
5025
5026 int
5027 vi_full_init(struct vi_info *vi)
5028 {
5029         struct adapter *sc = vi->pi->adapter;
5030         struct ifnet *ifp = vi->ifp;
5031         uint16_t *rss;
5032         struct sge_rxq *rxq;
5033         int rc, i, j, hashen;
5034 #ifdef RSS
5035         int nbuckets = rss_getnumbuckets();
5036         int hashconfig = rss_gethashconfig();
5037         int extra;
5038 #endif
5039
5040         ASSERT_SYNCHRONIZED_OP(sc);
5041         KASSERT((vi->flags & VI_INIT_DONE) == 0,
5042             ("%s: VI_INIT_DONE already", __func__));
5043
5044         sysctl_ctx_init(&vi->ctx);
5045         vi->flags |= VI_SYSCTL_CTX;
5046
5047         /*
5048          * Allocate tx/rx/fl queues for this VI.
5049          */
5050         rc = t4_setup_vi_queues(vi);
5051         if (rc != 0)
5052                 goto done;      /* error message displayed already */
5053
5054         /*
5055          * Setup RSS for this VI.  Save a copy of the RSS table for later use.
5056          */
5057         if (vi->nrxq > vi->rss_size) {
5058                 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5059                     "some queues will never receive traffic.\n", vi->nrxq,
5060                     vi->rss_size);
5061         } else if (vi->rss_size % vi->nrxq) {
5062                 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5063                     "expect uneven traffic distribution.\n", vi->nrxq,
5064                     vi->rss_size);
5065         }
5066 #ifdef RSS
5067         if (vi->nrxq != nbuckets) {
5068                 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5069                     "performance will be impacted.\n", vi->nrxq, nbuckets);
5070         }
5071 #endif
5072         rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5073         for (i = 0; i < vi->rss_size;) {
5074 #ifdef RSS
5075                 j = rss_get_indirection_to_bucket(i);
5076                 j %= vi->nrxq;
5077                 rxq = &sc->sge.rxq[vi->first_rxq + j];
5078                 rss[i++] = rxq->iq.abs_id;
5079 #else
5080                 for_each_rxq(vi, j, rxq) {
5081                         rss[i++] = rxq->iq.abs_id;
5082                         if (i == vi->rss_size)
5083                                 break;
5084                 }
5085 #endif
5086         }
5087
5088         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5089             vi->rss_size);
5090         if (rc != 0) {
5091                 if_printf(ifp, "rss_config failed: %d\n", rc);
5092                 goto done;
5093         }
5094
5095 #ifdef RSS
5096         hashen = hashconfig_to_hashen(hashconfig);
5097
5098         /*
5099          * We may have had to enable some hashes even though the global config
5100          * wants them disabled.  This is a potential problem that must be
5101          * reported to the user.
5102          */
5103         extra = hashen_to_hashconfig(hashen) ^ hashconfig;
5104
5105         /*
5106          * If we consider only the supported hash types, then the enabled hashes
5107          * are a superset of the requested hashes.  In other words, there cannot
5108          * be any supported hash that was requested but not enabled, but there
5109          * can be hashes that were not requested but had to be enabled.
5110          */
5111         extra &= SUPPORTED_RSS_HASHTYPES;
5112         MPASS((extra & hashconfig) == 0);
5113
5114         if (extra) {
5115                 if_printf(ifp,
5116                     "global RSS config (0x%x) cannot be accommodated.\n",
5117                     hashconfig);
5118         }
5119         if (extra & RSS_HASHTYPE_RSS_IPV4)
5120                 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5121         if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5122                 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5123         if (extra & RSS_HASHTYPE_RSS_IPV6)
5124                 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5125         if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5126                 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5127         if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5128                 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5129         if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5130                 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5131 #else
5132         hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5133             F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5134             F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5135             F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5136 #endif
5137         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
5138         if (rc != 0) {
5139                 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5140                 goto done;
5141         }
5142
5143         vi->rss = rss;
5144         vi->flags |= VI_INIT_DONE;
5145 done:
5146         if (rc != 0)
5147                 vi_full_uninit(vi);
5148
5149         return (rc);
5150 }
5151
5152 /*
5153  * Idempotent.
5154  */
5155 int
5156 vi_full_uninit(struct vi_info *vi)
5157 {
5158         struct port_info *pi = vi->pi;
5159         struct adapter *sc = pi->adapter;
5160         int i;
5161         struct sge_rxq *rxq;
5162         struct sge_txq *txq;
5163 #ifdef TCP_OFFLOAD
5164         struct sge_ofld_rxq *ofld_rxq;
5165         struct sge_wrq *ofld_txq;
5166 #endif
5167
5168         if (vi->flags & VI_INIT_DONE) {
5169
5170                 /* Need to quiesce queues.  */
5171
5172                 /* XXX: Only for the first VI? */
5173                 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5174                         quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5175
5176                 for_each_txq(vi, i, txq) {
5177                         quiesce_txq(sc, txq);
5178                 }
5179
5180 #ifdef TCP_OFFLOAD
5181                 for_each_ofld_txq(vi, i, ofld_txq) {
5182                         quiesce_wrq(sc, ofld_txq);
5183                 }
5184 #endif
5185
5186                 for_each_rxq(vi, i, rxq) {
5187                         quiesce_iq(sc, &rxq->iq);
5188                         quiesce_fl(sc, &rxq->fl);
5189                 }
5190
5191 #ifdef TCP_OFFLOAD
5192                 for_each_ofld_rxq(vi, i, ofld_rxq) {
5193                         quiesce_iq(sc, &ofld_rxq->iq);
5194                         quiesce_fl(sc, &ofld_rxq->fl);
5195                 }
5196 #endif
5197                 free(vi->rss, M_CXGBE);
5198                 free(vi->nm_rss, M_CXGBE);
5199         }
5200
5201         t4_teardown_vi_queues(vi);
5202         vi->flags &= ~VI_INIT_DONE;
5203
5204         return (0);
5205 }
5206
5207 static void
5208 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5209 {
5210         struct sge_eq *eq = &txq->eq;
5211         struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5212
5213         (void) sc;      /* unused */
5214
5215 #ifdef INVARIANTS
5216         TXQ_LOCK(txq);
5217         MPASS((eq->flags & EQ_ENABLED) == 0);
5218         TXQ_UNLOCK(txq);
5219 #endif
5220
5221         /* Wait for the mp_ring to empty. */
5222         while (!mp_ring_is_idle(txq->r)) {
5223                 mp_ring_check_drainage(txq->r, 0);
5224                 pause("rquiesce", 1);
5225         }
5226
5227         /* Then wait for the hardware to finish. */
5228         while (spg->cidx != htobe16(eq->pidx))
5229                 pause("equiesce", 1);
5230
5231         /* Finally, wait for the driver to reclaim all descriptors. */
5232         while (eq->cidx != eq->pidx)
5233                 pause("dquiesce", 1);
5234 }
5235
5236 static void
5237 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5238 {
5239
5240         /* XXXTX */
5241 }
5242
5243 static void
5244 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5245 {
5246         (void) sc;      /* unused */
5247
5248         /* Synchronize with the interrupt handler */
5249         while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5250                 pause("iqfree", 1);
5251 }
5252
5253 static void
5254 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5255 {
5256         mtx_lock(&sc->sfl_lock);
5257         FL_LOCK(fl);
5258         fl->flags |= FL_DOOMED;
5259         FL_UNLOCK(fl);
5260         callout_stop(&sc->sfl_callout);
5261         mtx_unlock(&sc->sfl_lock);
5262
5263         KASSERT((fl->flags & FL_STARVING) == 0,
5264             ("%s: still starving", __func__));
5265 }
5266
5267 static int
5268 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5269     driver_intr_t *handler, void *arg, char *name)
5270 {
5271         int rc;
5272
5273         irq->rid = rid;
5274         irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5275             RF_SHAREABLE | RF_ACTIVE);
5276         if (irq->res == NULL) {
5277                 device_printf(sc->dev,
5278                     "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5279                 return (ENOMEM);
5280         }
5281
5282         rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5283             NULL, handler, arg, &irq->tag);
5284         if (rc != 0) {
5285                 device_printf(sc->dev,
5286                     "failed to setup interrupt for rid %d, name %s: %d\n",
5287                     rid, name, rc);
5288         } else if (name)
5289                 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5290
5291         return (rc);
5292 }
5293
5294 static int
5295 t4_free_irq(struct adapter *sc, struct irq *irq)
5296 {
5297         if (irq->tag)
5298                 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5299         if (irq->res)
5300                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5301
5302         bzero(irq, sizeof(*irq));
5303
5304         return (0);
5305 }
5306
5307 static void
5308 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5309 {
5310
5311         regs->version = chip_id(sc) | chip_rev(sc) << 10;
5312         t4_get_regs(sc, buf, regs->len);
5313 }
5314
5315 #define A_PL_INDIR_CMD  0x1f8
5316
5317 #define S_PL_AUTOINC    31
5318 #define M_PL_AUTOINC    0x1U
5319 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5320 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5321
5322 #define S_PL_VFID       20
5323 #define M_PL_VFID       0xffU
5324 #define V_PL_VFID(x)    ((x) << S_PL_VFID)
5325 #define G_PL_VFID(x)    (((x) >> S_PL_VFID) & M_PL_VFID)
5326
5327 #define S_PL_ADDR       0
5328 #define M_PL_ADDR       0xfffffU
5329 #define V_PL_ADDR(x)    ((x) << S_PL_ADDR)
5330 #define G_PL_ADDR(x)    (((x) >> S_PL_ADDR) & M_PL_ADDR)
5331
5332 #define A_PL_INDIR_DATA 0x1fc
5333
5334 static uint64_t
5335 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5336 {
5337         u32 stats[2];
5338
5339         mtx_assert(&sc->reg_lock, MA_OWNED);
5340         if (sc->flags & IS_VF) {
5341                 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5342                 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5343         } else {
5344                 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5345                     V_PL_VFID(G_FW_VIID_VIN(viid)) |
5346                     V_PL_ADDR(VF_MPS_REG(reg)));
5347                 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5348                 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5349         }
5350         return (((uint64_t)stats[1]) << 32 | stats[0]);
5351 }
5352
5353 static void
5354 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5355     struct fw_vi_stats_vf *stats)
5356 {
5357
5358 #define GET_STAT(name) \
5359         read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5360
5361         stats->tx_bcast_bytes    = GET_STAT(TX_VF_BCAST_BYTES);
5362         stats->tx_bcast_frames   = GET_STAT(TX_VF_BCAST_FRAMES);
5363         stats->tx_mcast_bytes    = GET_STAT(TX_VF_MCAST_BYTES);
5364         stats->tx_mcast_frames   = GET_STAT(TX_VF_MCAST_FRAMES);
5365         stats->tx_ucast_bytes    = GET_STAT(TX_VF_UCAST_BYTES);
5366         stats->tx_ucast_frames   = GET_STAT(TX_VF_UCAST_FRAMES);
5367         stats->tx_drop_frames    = GET_STAT(TX_VF_DROP_FRAMES);
5368         stats->tx_offload_bytes  = GET_STAT(TX_VF_OFFLOAD_BYTES);
5369         stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5370         stats->rx_bcast_bytes    = GET_STAT(RX_VF_BCAST_BYTES);
5371         stats->rx_bcast_frames   = GET_STAT(RX_VF_BCAST_FRAMES);
5372         stats->rx_mcast_bytes    = GET_STAT(RX_VF_MCAST_BYTES);
5373         stats->rx_mcast_frames   = GET_STAT(RX_VF_MCAST_FRAMES);
5374         stats->rx_ucast_bytes    = GET_STAT(RX_VF_UCAST_BYTES);
5375         stats->rx_ucast_frames   = GET_STAT(RX_VF_UCAST_FRAMES);
5376         stats->rx_err_frames     = GET_STAT(RX_VF_ERR_FRAMES);
5377
5378 #undef GET_STAT
5379 }
5380
5381 static void
5382 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5383 {
5384         int reg;
5385
5386         t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5387             V_PL_VFID(G_FW_VIID_VIN(viid)) |
5388             V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5389         for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5390              reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5391                 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5392 }
5393
5394 static void
5395 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5396 {
5397         struct timeval tv;
5398         const struct timeval interval = {0, 250000};    /* 250ms */
5399
5400         if (!(vi->flags & VI_INIT_DONE))
5401                 return;
5402
5403         getmicrotime(&tv);
5404         timevalsub(&tv, &interval);
5405         if (timevalcmp(&tv, &vi->last_refreshed, <))
5406                 return;
5407
5408         mtx_lock(&sc->reg_lock);
5409         t4_get_vi_stats(sc, vi->viid, &vi->stats);
5410         getmicrotime(&vi->last_refreshed);
5411         mtx_unlock(&sc->reg_lock);
5412 }
5413
5414 static void
5415 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5416 {
5417         u_int i, v, tnl_cong_drops, bg_map;
5418         struct timeval tv;
5419         const struct timeval interval = {0, 250000};    /* 250ms */
5420
5421         getmicrotime(&tv);
5422         timevalsub(&tv, &interval);
5423         if (timevalcmp(&tv, &pi->last_refreshed, <))
5424                 return;
5425
5426         tnl_cong_drops = 0;
5427         t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5428         bg_map = pi->mps_bg_map;
5429         while (bg_map) {
5430                 i = ffs(bg_map) - 1;
5431                 mtx_lock(&sc->reg_lock);
5432                 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5433                     A_TP_MIB_TNL_CNG_DROP_0 + i);
5434                 mtx_unlock(&sc->reg_lock);
5435                 tnl_cong_drops += v;
5436                 bg_map &= ~(1 << i);
5437         }
5438         pi->tnl_cong_drops = tnl_cong_drops;
5439         getmicrotime(&pi->last_refreshed);
5440 }
5441
5442 static void
5443 cxgbe_tick(void *arg)
5444 {
5445         struct port_info *pi = arg;
5446         struct adapter *sc = pi->adapter;
5447
5448         PORT_LOCK_ASSERT_OWNED(pi);
5449         cxgbe_refresh_stats(sc, pi);
5450
5451         callout_schedule(&pi->tick, hz);
5452 }
5453
5454 void
5455 vi_tick(void *arg)
5456 {
5457         struct vi_info *vi = arg;
5458         struct adapter *sc = vi->pi->adapter;
5459
5460         vi_refresh_stats(sc, vi);
5461
5462         callout_schedule(&vi->tick, hz);
5463 }
5464
5465 static void
5466 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
5467 {
5468         struct ifnet *vlan;
5469
5470         if (arg != ifp || ifp->if_type != IFT_ETHER)
5471                 return;
5472
5473         vlan = VLAN_DEVAT(ifp, vid);
5474         VLAN_SETCOOKIE(vlan, ifp);
5475 }
5476
5477 /*
5478  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5479  */
5480 static char *caps_decoder[] = {
5481         "\20\001IPMI\002NCSI",                          /* 0: NBM */
5482         "\20\001PPP\002QFC\003DCBX",                    /* 1: link */
5483         "\20\001INGRESS\002EGRESS",                     /* 2: switch */
5484         "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"      /* 3: NIC */
5485             "\006HASHFILTER\007ETHOFLD",
5486         "\20\001TOE",                                   /* 4: TOE */
5487         "\20\001RDDP\002RDMAC",                         /* 5: RDMA */
5488         "\20\001INITIATOR_PDU\002TARGET_PDU"            /* 6: iSCSI */
5489             "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5490             "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5491             "\007T10DIF"
5492             "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5493         "\20\001LOOKASIDE\002TLSKEYS",                  /* 7: Crypto */
5494         "\20\001INITIATOR\002TARGET\003CTRL_OFLD"       /* 8: FCoE */
5495                     "\004PO_INITIATOR\005PO_TARGET",
5496 };
5497
5498 void
5499 t4_sysctls(struct adapter *sc)
5500 {
5501         struct sysctl_ctx_list *ctx;
5502         struct sysctl_oid *oid;
5503         struct sysctl_oid_list *children, *c0;
5504         static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5505
5506         ctx = device_get_sysctl_ctx(sc->dev);
5507
5508         /*
5509          * dev.t4nex.X.
5510          */
5511         oid = device_get_sysctl_tree(sc->dev);
5512         c0 = children = SYSCTL_CHILDREN(oid);
5513
5514         sc->sc_do_rxcopy = 1;
5515         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5516             &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5517
5518         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5519             sc->params.nports, "# of ports");
5520
5521         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5522             CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
5523             sysctl_bitfield, "A", "available doorbells");
5524
5525         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5526             sc->params.vpd.cclk, "core clock frequency (in KHz)");
5527
5528         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5529             CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5530             sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5531             "interrupt holdoff timer values (us)");
5532
5533         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5534             CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5535             sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5536             "interrupt holdoff packet counter values");
5537
5538         t4_sge_sysctls(sc, ctx, children);
5539
5540         sc->lro_timeout = 100;
5541         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5542             &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5543
5544         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5545             &sc->debug_flags, 0, "flags to enable runtime debugging");
5546
5547         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5548             CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5549
5550         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5551             CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5552
5553         if (sc->flags & IS_VF)
5554                 return;
5555
5556         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5557             NULL, chip_rev(sc), "chip hardware revision");
5558
5559         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5560             CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5561
5562         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5563             CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5564
5565         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5566             CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5567
5568         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5569             CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5570
5571         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5572             CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5573
5574         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5575             sc->er_version, 0, "expansion ROM version");
5576
5577         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5578             sc->bs_version, 0, "bootstrap firmware version");
5579
5580         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5581             NULL, sc->params.scfg_vers, "serial config version");
5582
5583         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5584             NULL, sc->params.vpd_vers, "VPD version");
5585
5586         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5587             CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5588
5589         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5590             sc->cfcsum, "config file checksum");
5591
5592 #define SYSCTL_CAP(name, n, text) \
5593         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5594             CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
5595             sysctl_bitfield, "A", "available " text " capabilities")
5596
5597         SYSCTL_CAP(nbmcaps, 0, "NBM");
5598         SYSCTL_CAP(linkcaps, 1, "link");
5599         SYSCTL_CAP(switchcaps, 2, "switch");
5600         SYSCTL_CAP(niccaps, 3, "NIC");
5601         SYSCTL_CAP(toecaps, 4, "TCP offload");
5602         SYSCTL_CAP(rdmacaps, 5, "RDMA");
5603         SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5604         SYSCTL_CAP(cryptocaps, 7, "crypto");
5605         SYSCTL_CAP(fcoecaps, 8, "FCoE");
5606 #undef SYSCTL_CAP
5607
5608         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5609             NULL, sc->tids.nftids, "number of filters");
5610
5611         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5612             CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5613             "chip temperature (in Celsius)");
5614
5615         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5616             CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5617             "microprocessor load averages (debug firmwares only)");
5618
5619         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5620             &sc->params.core_vdd, 0, "core Vdd (in mV)");
5621
5622 #ifdef SBUF_DRAIN
5623         /*
5624          * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
5625          */
5626         oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5627             CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5628             "logs and miscellaneous information");
5629         children = SYSCTL_CHILDREN(oid);
5630
5631         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5632             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5633             sysctl_cctrl, "A", "congestion control");
5634
5635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5636             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5637             sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5638
5639         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5640             CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5641             sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5642
5643         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5644             CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5645             sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5646
5647         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5648             CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5649             sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5650
5651         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5652             CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5653             sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5654
5655         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5656             CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5657             sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5658
5659         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5660             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5661             chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5662             "A", "CIM logic analyzer");
5663
5664         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5665             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5666             sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5667
5668         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5669             CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5670             sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5671
5672         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5673             CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5674             sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5675
5676         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5677             CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5678             sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5679
5680         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5681             CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5682             sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5683
5684         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5685             CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5686             sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5687
5688         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5689             CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5690             sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5691
5692         if (chip_id(sc) > CHELSIO_T4) {
5693                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5694                     CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5695                     sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5696
5697                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5698                     CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5699                     sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5700         }
5701
5702         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5703             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5704             sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5705
5706         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5707             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5708             sysctl_cim_qcfg, "A", "CIM queue configuration");
5709
5710         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5711             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5712             sysctl_cpl_stats, "A", "CPL statistics");
5713
5714         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5715             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5716             sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5717
5718         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5719             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5720             sysctl_devlog, "A", "firmware's device log");
5721
5722         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5723             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5724             sysctl_fcoe_stats, "A", "FCoE statistics");
5725
5726         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5727             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5728             sysctl_hw_sched, "A", "hardware scheduler ");
5729
5730         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5731             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5732             sysctl_l2t, "A", "hardware L2 table");
5733
5734         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5735             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5736             sysctl_lb_stats, "A", "loopback statistics");
5737
5738         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5739             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5740             sysctl_meminfo, "A", "memory regions");
5741
5742         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5743             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5744             chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5745             "A", "MPS TCAM entries");
5746
5747         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5748             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5749             sysctl_path_mtus, "A", "path MTUs");
5750
5751         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5752             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5753             sysctl_pm_stats, "A", "PM statistics");
5754
5755         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5756             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5757             sysctl_rdma_stats, "A", "RDMA statistics");
5758
5759         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5760             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5761             sysctl_tcp_stats, "A", "TCP statistics");
5762
5763         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5764             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5765             sysctl_tids, "A", "TID information");
5766
5767         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5768             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5769             sysctl_tp_err_stats, "A", "TP error statistics");
5770
5771         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5772             CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5773             "TP logic analyzer event capture mask");
5774
5775         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5776             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5777             sysctl_tp_la, "A", "TP logic analyzer");
5778
5779         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5780             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5781             sysctl_tx_rate, "A", "Tx rate");
5782
5783         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5784             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5785             sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5786
5787         if (chip_id(sc) >= CHELSIO_T5) {
5788                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5789                     CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5790                     sysctl_wcwr_stats, "A", "write combined work requests");
5791         }
5792 #endif
5793
5794 #ifdef TCP_OFFLOAD
5795         if (is_offload(sc)) {
5796                 int i;
5797                 char s[4];
5798
5799                 /*
5800                  * dev.t4nex.X.toe.
5801                  */
5802                 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5803                     NULL, "TOE parameters");
5804                 children = SYSCTL_CHILDREN(oid);
5805
5806                 sc->tt.cong_algorithm = -1;
5807                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
5808                     CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
5809                     "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
5810                     "3 = highspeed)");
5811
5812                 sc->tt.sndbuf = 256 * 1024;
5813                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5814                     &sc->tt.sndbuf, 0, "max hardware send buffer size");
5815
5816                 sc->tt.ddp = 0;
5817                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5818                     &sc->tt.ddp, 0, "DDP allowed");
5819
5820                 sc->tt.rx_coalesce = 1;
5821                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5822                     CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5823
5824                 sc->tt.tls = 0;
5825                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
5826                     &sc->tt.tls, 0, "Inline TLS allowed");
5827
5828                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
5829                     CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
5830                     "I", "TCP ports that use inline TLS+TOE RX");
5831
5832                 sc->tt.tx_align = 1;
5833                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
5834                     CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
5835
5836                 sc->tt.tx_zcopy = 0;
5837                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
5838                     CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
5839                     "Enable zero-copy aio_write(2)");
5840
5841                 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
5842                 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5843                     "cop_managed_offloading", CTLFLAG_RW,
5844                     &sc->tt.cop_managed_offloading, 0,
5845                     "COP (Connection Offload Policy) controls all TOE offload");
5846
5847                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
5848                     CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
5849                     "TP timer tick (us)");
5850
5851                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
5852                     CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
5853                     "TCP timestamp tick (us)");
5854
5855                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5856                     CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5857                     "DACK tick (us)");
5858
5859                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5860                     CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5861                     "IU", "DACK timer (us)");
5862
5863                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5864                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5865                     sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
5866
5867                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5868                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5869                     sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
5870
5871                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5872                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5873                     sysctl_tp_timer, "LU", "Persist timer min (us)");
5874
5875                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5876                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5877                     sysctl_tp_timer, "LU", "Persist timer max (us)");
5878
5879                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5880                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5881                     sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
5882
5883                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
5884                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5885                     sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
5886
5887                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5888                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5889                     sysctl_tp_timer, "LU", "Initial SRTT (us)");
5890
5891                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5892                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5893                     sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5894
5895                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
5896                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
5897                     sysctl_tp_shift_cnt, "IU",
5898                     "Number of SYN retransmissions before abort");
5899
5900                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
5901                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
5902                     sysctl_tp_shift_cnt, "IU",
5903                     "Number of retransmissions before abort");
5904
5905                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
5906                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
5907                     sysctl_tp_shift_cnt, "IU",
5908                     "Number of keepalive probes before abort");
5909
5910                 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
5911                     CTLFLAG_RD, NULL, "TOE retransmit backoffs");
5912                 children = SYSCTL_CHILDREN(oid);
5913                 for (i = 0; i < 16; i++) {
5914                         snprintf(s, sizeof(s), "%u", i);
5915                         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
5916                             CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
5917                             "IU", "TOE retransmit backoff");
5918                 }
5919         }
5920 #endif
5921 }
5922
5923 void
5924 vi_sysctls(struct vi_info *vi)
5925 {
5926         struct sysctl_ctx_list *ctx;
5927         struct sysctl_oid *oid;
5928         struct sysctl_oid_list *children;
5929
5930         ctx = device_get_sysctl_ctx(vi->dev);
5931
5932         /*
5933          * dev.v?(cxgbe|cxl).X.
5934          */
5935         oid = device_get_sysctl_tree(vi->dev);
5936         children = SYSCTL_CHILDREN(oid);
5937
5938         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5939             vi->viid, "VI identifer");
5940         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5941             &vi->nrxq, 0, "# of rx queues");
5942         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5943             &vi->ntxq, 0, "# of tx queues");
5944         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5945             &vi->first_rxq, 0, "index of first rx queue");
5946         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5947             &vi->first_txq, 0, "index of first tx queue");
5948         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5949             vi->rss_size, "size of RSS indirection table");
5950
5951         if (IS_MAIN_VI(vi)) {
5952                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5953                     CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5954                     "Reserve queue 0 for non-flowid packets");
5955         }
5956
5957 #ifdef TCP_OFFLOAD
5958         if (vi->nofldrxq != 0) {
5959                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5960                     &vi->nofldrxq, 0,
5961                     "# of rx queues for offloaded TCP connections");
5962                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5963                     &vi->nofldtxq, 0,
5964                     "# of tx queues for offloaded TCP connections");
5965                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5966                     CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5967                     "index of first TOE rx queue");
5968                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5969                     CTLFLAG_RD, &vi->first_ofld_txq, 0,
5970                     "index of first TOE tx queue");
5971                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
5972                     CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5973                     sysctl_holdoff_tmr_idx_ofld, "I",
5974                     "holdoff timer index for TOE queues");
5975                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
5976                     CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5977                     sysctl_holdoff_pktc_idx_ofld, "I",
5978                     "holdoff packet counter index for TOE queues");
5979         }
5980 #endif
5981 #ifdef DEV_NETMAP
5982         if (vi->nnmrxq != 0) {
5983                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5984                     &vi->nnmrxq, 0, "# of netmap rx queues");
5985                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5986                     &vi->nnmtxq, 0, "# of netmap tx queues");
5987                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5988                     CTLFLAG_RD, &vi->first_nm_rxq, 0,
5989                     "index of first netmap rx queue");
5990                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5991                     CTLFLAG_RD, &vi->first_nm_txq, 0,
5992                     "index of first netmap tx queue");
5993         }
5994 #endif
5995
5996         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5997             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5998             "holdoff timer index");
5999         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6000             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6001             "holdoff packet counter index");
6002
6003         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6004             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6005             "rx queue size");
6006         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6007             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6008             "tx queue size");
6009 }
6010
6011 static void
6012 cxgbe_sysctls(struct port_info *pi)
6013 {
6014         struct sysctl_ctx_list *ctx;
6015         struct sysctl_oid *oid;
6016         struct sysctl_oid_list *children, *children2;
6017         struct adapter *sc = pi->adapter;
6018         int i;
6019         char name[16];
6020
6021         ctx = device_get_sysctl_ctx(pi->dev);
6022
6023         /*
6024          * dev.cxgbe.X.
6025          */
6026         oid = device_get_sysctl_tree(pi->dev);
6027         children = SYSCTL_CHILDREN(oid);
6028
6029         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6030            CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6031         if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6032                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6033                     CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6034                     "PHY temperature (in Celsius)");
6035                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6036                     CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6037                     "PHY firmware version");
6038         }
6039
6040         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6041             CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6042     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6043         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6044             CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6045             "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6046         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6047             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6048             "autonegotiation (-1 = not supported)");
6049
6050         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6051             port_top_speed(pi), "max speed (in Gbps)");
6052         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6053             pi->mps_bg_map, "MPS buffer group map");
6054         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6055             NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6056
6057         if (sc->flags & IS_VF)
6058                 return;
6059
6060         /*
6061          * dev.(cxgbe|cxl).X.tc.
6062          */
6063         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6064             "Tx scheduler traffic classes (cl_rl)");
6065         for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6066                 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6067
6068                 snprintf(name, sizeof(name), "%d", i);
6069                 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6070                     SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6071                     "traffic class"));
6072                 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
6073                     &tc->flags, 0, "flags");
6074                 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6075                     CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6076 #ifdef SBUF_DRAIN
6077                 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6078                     CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6079                     sysctl_tc_params, "A", "traffic class parameters");
6080 #endif
6081         }
6082
6083         /*
6084          * dev.cxgbe.X.stats.
6085          */
6086         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6087             NULL, "port statistics");
6088         children = SYSCTL_CHILDREN(oid);
6089         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6090             &pi->tx_parse_error, 0,
6091             "# of tx packets with invalid length or # of segments");
6092
6093 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6094         SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6095             CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6096             sysctl_handle_t4_reg64, "QU", desc)
6097
6098         SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6099             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6100         SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6101             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6102         SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6103             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6104         SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6105             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6106         SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6107             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6108         SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6109             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6110         SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6111             "# of tx frames in this range",
6112             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6113         SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6114             "# of tx frames in this range",
6115             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6116         SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6117             "# of tx frames in this range",
6118             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6119         SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6120             "# of tx frames in this range",
6121             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6122         SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6123             "# of tx frames in this range",
6124             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6125         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6126             "# of tx frames in this range",
6127             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6128         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6129             "# of tx frames in this range",
6130             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6131         SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6132             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6133         SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6134             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6135         SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6136             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6137         SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6138             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6139         SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6140             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6141         SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6142             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6143         SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6144             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6145         SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6146             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6147         SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6148             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6149         SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6150             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6151
6152         SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6153             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6154         SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6155             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6156         SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6157             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6158         SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6159             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6160         SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6161             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6162         SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6163             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6164         SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6165             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6166         SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6167             "# of frames received with bad FCS",
6168             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6169         SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6170             "# of frames received with length error",
6171             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6172         SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6173             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6174         SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6175             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6176         SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6177             "# of rx frames in this range",
6178             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6179         SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6180             "# of rx frames in this range",
6181             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6182         SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6183             "# of rx frames in this range",
6184             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6185         SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6186             "# of rx frames in this range",
6187             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6188         SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6189             "# of rx frames in this range",
6190             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6191         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6192             "# of rx frames in this range",
6193             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6194         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6195             "# of rx frames in this range",
6196             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6197         SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6198             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6199         SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6200             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6201         SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6202             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6203         SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6204             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6205         SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6206             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6207         SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6208             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6209         SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6210             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6211         SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6212             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6213         SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6214             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6215
6216 #undef SYSCTL_ADD_T4_REG64
6217
6218 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6219         SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6220             &pi->stats.name, desc)
6221
6222         /* We get these from port_stats and they may be stale by up to 1s */
6223         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6224             "# drops due to buffer-group 0 overflows");
6225         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6226             "# drops due to buffer-group 1 overflows");
6227         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6228             "# drops due to buffer-group 2 overflows");
6229         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6230             "# drops due to buffer-group 3 overflows");
6231         SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6232             "# of buffer-group 0 truncated packets");
6233         SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6234             "# of buffer-group 1 truncated packets");
6235         SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6236             "# of buffer-group 2 truncated packets");
6237         SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6238             "# of buffer-group 3 truncated packets");
6239
6240 #undef SYSCTL_ADD_T4_PORTSTAT
6241
6242         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6243             CTLFLAG_RD, &pi->tx_tls_records,
6244             "# of TLS records transmitted");
6245         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6246             CTLFLAG_RD, &pi->tx_tls_octets,
6247             "# of payload octets in transmitted TLS records");
6248         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6249             CTLFLAG_RD, &pi->rx_tls_records,
6250             "# of TLS records received");
6251         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6252             CTLFLAG_RD, &pi->rx_tls_octets,
6253             "# of payload octets in received TLS records");
6254 }
6255
6256 static int
6257 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6258 {
6259         int rc, *i, space = 0;
6260         struct sbuf sb;
6261
6262         sbuf_new_for_sysctl(&sb, NULL, 64, req);
6263         for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6264                 if (space)
6265                         sbuf_printf(&sb, " ");
6266                 sbuf_printf(&sb, "%d", *i);
6267                 space = 1;
6268         }
6269         rc = sbuf_finish(&sb);
6270         sbuf_delete(&sb);
6271         return (rc);
6272 }
6273
6274 static int
6275 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
6276 {
6277         int rc;
6278         struct sbuf *sb;
6279
6280         rc = sysctl_wire_old_buffer(req, 0);
6281         if (rc != 0)
6282                 return(rc);
6283
6284         sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6285         if (sb == NULL)
6286                 return (ENOMEM);
6287
6288         sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
6289         rc = sbuf_finish(sb);
6290         sbuf_delete(sb);
6291
6292         return (rc);
6293 }
6294
6295 static int
6296 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6297 {
6298         struct port_info *pi = arg1;
6299         int op = arg2;
6300         struct adapter *sc = pi->adapter;
6301         u_int v;
6302         int rc;
6303
6304         rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6305         if (rc)
6306                 return (rc);
6307         /* XXX: magic numbers */
6308         rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6309             &v);
6310         end_synchronized_op(sc, 0);
6311         if (rc)
6312                 return (rc);
6313         if (op == 0)
6314                 v /= 256;
6315
6316         rc = sysctl_handle_int(oidp, &v, 0, req);
6317         return (rc);
6318 }
6319
6320 static int
6321 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6322 {
6323         struct vi_info *vi = arg1;
6324         int rc, val;
6325
6326         val = vi->rsrv_noflowq;
6327         rc = sysctl_handle_int(oidp, &val, 0, req);
6328         if (rc != 0 || req->newptr == NULL)
6329                 return (rc);
6330
6331         if ((val >= 1) && (vi->ntxq > 1))
6332                 vi->rsrv_noflowq = 1;
6333         else
6334                 vi->rsrv_noflowq = 0;
6335
6336         return (rc);
6337 }
6338
6339 static int
6340 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6341 {
6342         struct vi_info *vi = arg1;
6343         struct adapter *sc = vi->pi->adapter;
6344         int idx, rc, i;
6345         struct sge_rxq *rxq;
6346         uint8_t v;
6347
6348         idx = vi->tmr_idx;
6349
6350         rc = sysctl_handle_int(oidp, &idx, 0, req);
6351         if (rc != 0 || req->newptr == NULL)
6352                 return (rc);
6353
6354         if (idx < 0 || idx >= SGE_NTIMERS)
6355                 return (EINVAL);
6356
6357         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6358             "t4tmr");
6359         if (rc)
6360                 return (rc);
6361
6362         v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6363         for_each_rxq(vi, i, rxq) {
6364 #ifdef atomic_store_rel_8
6365                 atomic_store_rel_8(&rxq->iq.intr_params, v);
6366 #else
6367                 rxq->iq.intr_params = v;
6368 #endif
6369         }
6370         vi->tmr_idx = idx;
6371
6372         end_synchronized_op(sc, LOCK_HELD);
6373         return (0);
6374 }
6375
6376 static int
6377 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6378 {
6379         struct vi_info *vi = arg1;
6380         struct adapter *sc = vi->pi->adapter;
6381         int idx, rc;
6382
6383         idx = vi->pktc_idx;
6384
6385         rc = sysctl_handle_int(oidp, &idx, 0, req);
6386         if (rc != 0 || req->newptr == NULL)
6387                 return (rc);
6388
6389         if (idx < -1 || idx >= SGE_NCOUNTERS)
6390                 return (EINVAL);
6391
6392         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6393             "t4pktc");
6394         if (rc)
6395                 return (rc);
6396
6397         if (vi->flags & VI_INIT_DONE)
6398                 rc = EBUSY; /* cannot be changed once the queues are created */
6399         else
6400                 vi->pktc_idx = idx;
6401
6402         end_synchronized_op(sc, LOCK_HELD);
6403         return (rc);
6404 }
6405
6406 static int
6407 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6408 {
6409         struct vi_info *vi = arg1;
6410         struct adapter *sc = vi->pi->adapter;
6411         int qsize, rc;
6412
6413         qsize = vi->qsize_rxq;
6414
6415         rc = sysctl_handle_int(oidp, &qsize, 0, req);
6416         if (rc != 0 || req->newptr == NULL)
6417                 return (rc);
6418
6419         if (qsize < 128 || (qsize & 7))
6420                 return (EINVAL);
6421
6422         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6423             "t4rxqs");
6424         if (rc)
6425                 return (rc);
6426
6427         if (vi->flags & VI_INIT_DONE)
6428                 rc = EBUSY; /* cannot be changed once the queues are created */
6429         else
6430                 vi->qsize_rxq = qsize;
6431
6432         end_synchronized_op(sc, LOCK_HELD);
6433         return (rc);
6434 }
6435
6436 static int
6437 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6438 {
6439         struct vi_info *vi = arg1;
6440         struct adapter *sc = vi->pi->adapter;
6441         int qsize, rc;
6442
6443         qsize = vi->qsize_txq;
6444
6445         rc = sysctl_handle_int(oidp, &qsize, 0, req);
6446         if (rc != 0 || req->newptr == NULL)
6447                 return (rc);
6448
6449         if (qsize < 128 || qsize > 65536)
6450                 return (EINVAL);
6451
6452         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6453             "t4txqs");
6454         if (rc)
6455                 return (rc);
6456
6457         if (vi->flags & VI_INIT_DONE)
6458                 rc = EBUSY; /* cannot be changed once the queues are created */
6459         else
6460                 vi->qsize_txq = qsize;
6461
6462         end_synchronized_op(sc, LOCK_HELD);
6463         return (rc);
6464 }
6465
6466 static int
6467 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6468 {
6469         struct port_info *pi = arg1;
6470         struct adapter *sc = pi->adapter;
6471         struct link_config *lc = &pi->link_cfg;
6472         int rc;
6473
6474         if (req->newptr == NULL) {
6475                 struct sbuf *sb;
6476                 static char *bits = "\20\1RX\2TX\3AUTO";
6477
6478                 rc = sysctl_wire_old_buffer(req, 0);
6479                 if (rc != 0)
6480                         return(rc);
6481
6482                 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6483                 if (sb == NULL)
6484                         return (ENOMEM);
6485
6486                 if (lc->link_ok) {
6487                         sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6488                             (lc->requested_fc & PAUSE_AUTONEG), bits);
6489                 } else {
6490                         sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6491                             PAUSE_RX | PAUSE_AUTONEG), bits);
6492                 }
6493                 rc = sbuf_finish(sb);
6494                 sbuf_delete(sb);
6495         } else {
6496                 char s[2];
6497                 int n;
6498
6499                 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6500                     PAUSE_AUTONEG));
6501                 s[1] = 0;
6502
6503                 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6504                 if (rc != 0)
6505                         return(rc);
6506
6507                 if (s[1] != 0)
6508                         return (EINVAL);
6509                 if (s[0] < '0' || s[0] > '9')
6510                         return (EINVAL);        /* not a number */
6511                 n = s[0] - '0';
6512                 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6513                         return (EINVAL);        /* some other bit is set too */
6514
6515                 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6516                     "t4PAUSE");
6517                 if (rc)
6518                         return (rc);
6519                 PORT_LOCK(pi);
6520                 lc->requested_fc = n;
6521                 fixup_link_config(pi);
6522                 if (pi->up_vis > 0)
6523                         rc = apply_link_config(pi);
6524                 set_current_media(pi);
6525                 PORT_UNLOCK(pi);
6526                 end_synchronized_op(sc, 0);
6527         }
6528
6529         return (rc);
6530 }
6531
6532 static int
6533 sysctl_fec(SYSCTL_HANDLER_ARGS)
6534 {
6535         struct port_info *pi = arg1;
6536         struct adapter *sc = pi->adapter;
6537         struct link_config *lc = &pi->link_cfg;
6538         int rc;
6539         int8_t old;
6540
6541         if (req->newptr == NULL) {
6542                 struct sbuf *sb;
6543                 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
6544
6545                 rc = sysctl_wire_old_buffer(req, 0);
6546                 if (rc != 0)
6547                         return(rc);
6548
6549                 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6550                 if (sb == NULL)
6551                         return (ENOMEM);
6552
6553                 /*
6554                  * Display the requested_fec when the link is down -- the actual
6555                  * FEC makes sense only when the link is up.
6556                  */
6557                 if (lc->link_ok) {
6558                         sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
6559                             (lc->requested_fec & FEC_AUTO), bits);
6560                 } else {
6561                         sbuf_printf(sb, "%b", lc->requested_fec, bits);
6562                 }
6563                 rc = sbuf_finish(sb);
6564                 sbuf_delete(sb);
6565         } else {
6566                 char s[3];
6567                 int n;
6568
6569                 snprintf(s, sizeof(s), "%d",
6570                     lc->requested_fec == FEC_AUTO ? -1 :
6571                     lc->requested_fec & M_FW_PORT_CAP32_FEC);
6572
6573                 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6574                 if (rc != 0)
6575                         return(rc);
6576
6577                 n = strtol(&s[0], NULL, 0);
6578                 if (n < 0 || n & FEC_AUTO)
6579                         n = FEC_AUTO;
6580                 else {
6581                         if (n & ~M_FW_PORT_CAP32_FEC)
6582                                 return (EINVAL);/* some other bit is set too */
6583                         if (!powerof2(n))
6584                                 return (EINVAL);/* one bit can be set at most */
6585                 }
6586
6587                 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6588                     "t4fec");
6589                 if (rc)
6590                         return (rc);
6591                 PORT_LOCK(pi);
6592                 old = lc->requested_fec;
6593                 if (n == FEC_AUTO)
6594                         lc->requested_fec = FEC_AUTO;
6595                 else if (n == 0)
6596                         lc->requested_fec = FEC_NONE;
6597                 else {
6598                         if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
6599                             lc->supported) {
6600                                 rc = ENOTSUP;
6601                                 goto done;
6602                         }
6603                         lc->requested_fec = n;
6604                 }
6605                 fixup_link_config(pi);
6606                 if (pi->up_vis > 0) {
6607                         rc = apply_link_config(pi);
6608                         if (rc != 0) {
6609                                 lc->requested_fec = old;
6610                                 if (rc == FW_EPROTO)
6611                                         rc = ENOTSUP;
6612                         }
6613                 }
6614 done:
6615                 PORT_UNLOCK(pi);
6616                 end_synchronized_op(sc, 0);
6617         }
6618
6619         return (rc);
6620 }
6621
6622 static int
6623 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
6624 {
6625         struct port_info *pi = arg1;
6626         struct adapter *sc = pi->adapter;
6627         struct link_config *lc = &pi->link_cfg;
6628         int rc, val;
6629
6630         if (lc->supported & FW_PORT_CAP32_ANEG)
6631                 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
6632         else
6633                 val = -1;
6634         rc = sysctl_handle_int(oidp, &val, 0, req);
6635         if (rc != 0 || req->newptr == NULL)
6636                 return (rc);
6637         if (val == 0)
6638                 val = AUTONEG_DISABLE;
6639         else if (val == 1)
6640                 val = AUTONEG_ENABLE;
6641         else
6642                 val = AUTONEG_AUTO;
6643
6644         rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6645             "t4aneg");
6646         if (rc)
6647                 return (rc);
6648         PORT_LOCK(pi);
6649         if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
6650                 rc = ENOTSUP;
6651                 goto done;
6652         }
6653         lc->requested_aneg = val;
6654         fixup_link_config(pi);
6655         if (pi->up_vis > 0)
6656                 rc = apply_link_config(pi);
6657         set_current_media(pi);
6658 done:
6659         PORT_UNLOCK(pi);
6660         end_synchronized_op(sc, 0);
6661         return (rc);
6662 }
6663
6664 static int
6665 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
6666 {
6667         struct adapter *sc = arg1;
6668         int reg = arg2;
6669         uint64_t val;
6670
6671         val = t4_read_reg64(sc, reg);
6672
6673         return (sysctl_handle_64(oidp, &val, 0, req));
6674 }
6675
6676 static int
6677 sysctl_temperature(SYSCTL_HANDLER_ARGS)
6678 {
6679         struct adapter *sc = arg1;
6680         int rc, t;
6681         uint32_t param, val;
6682
6683         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
6684         if (rc)
6685                 return (rc);
6686         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6687             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
6688             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
6689         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6690         end_synchronized_op(sc, 0);
6691         if (rc)
6692                 return (rc);
6693
6694         /* unknown is returned as 0 but we display -1 in that case */
6695         t = val == 0 ? -1 : val;
6696
6697         rc = sysctl_handle_int(oidp, &t, 0, req);
6698         return (rc);
6699 }
6700
6701 #ifdef SBUF_DRAIN
6702 static int
6703 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
6704 {
6705         struct adapter *sc = arg1;
6706         struct sbuf *sb;
6707         int rc;
6708         uint32_t param, val;
6709
6710         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
6711         if (rc)
6712                 return (rc);
6713         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6714             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
6715         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6716         end_synchronized_op(sc, 0);
6717         if (rc)
6718                 return (rc);
6719
6720         rc = sysctl_wire_old_buffer(req, 0);
6721         if (rc != 0)
6722                 return (rc);
6723
6724         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6725         if (sb == NULL)
6726                 return (ENOMEM);
6727
6728         if (val == 0xffffffff) {
6729                 /* Only debug and custom firmwares report load averages. */
6730                 sbuf_printf(sb, "not available");
6731         } else {
6732                 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
6733                     (val >> 16) & 0xff);
6734         }
6735         rc = sbuf_finish(sb);
6736         sbuf_delete(sb);
6737
6738         return (rc);
6739 }
6740
6741 static int
6742 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6743 {
6744         struct adapter *sc = arg1;
6745         struct sbuf *sb;
6746         int rc, i;
6747         uint16_t incr[NMTUS][NCCTRL_WIN];
6748         static const char *dec_fac[] = {
6749                 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6750                 "0.9375"
6751         };
6752
6753         rc = sysctl_wire_old_buffer(req, 0);
6754         if (rc != 0)
6755                 return (rc);
6756
6757         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6758         if (sb == NULL)
6759                 return (ENOMEM);
6760
6761         t4_read_cong_tbl(sc, incr);
6762
6763         for (i = 0; i < NCCTRL_WIN; ++i) {
6764                 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6765                     incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6766                     incr[5][i], incr[6][i], incr[7][i]);
6767                 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6768                     incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6769                     incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6770                     sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6771         }
6772
6773         rc = sbuf_finish(sb);
6774         sbuf_delete(sb);
6775
6776         return (rc);
6777 }
6778
6779 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6780         "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",   /* ibq's */
6781         "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6782         "SGE0-RX", "SGE1-RX"    /* additional obq's (T5 onwards) */
6783 };
6784
6785 static int
6786 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6787 {
6788         struct adapter *sc = arg1;
6789         struct sbuf *sb;
6790         int rc, i, n, qid = arg2;
6791         uint32_t *buf, *p;
6792         char *qtype;
6793         u_int cim_num_obq = sc->chip_params->cim_num_obq;
6794
6795         KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6796             ("%s: bad qid %d\n", __func__, qid));
6797
6798         if (qid < CIM_NUM_IBQ) {
6799                 /* inbound queue */
6800                 qtype = "IBQ";
6801                 n = 4 * CIM_IBQ_SIZE;
6802                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6803                 rc = t4_read_cim_ibq(sc, qid, buf, n);
6804         } else {
6805                 /* outbound queue */
6806                 qtype = "OBQ";
6807                 qid -= CIM_NUM_IBQ;
6808                 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
6809                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6810                 rc = t4_read_cim_obq(sc, qid, buf, n);
6811         }
6812
6813         if (rc < 0) {
6814                 rc = -rc;
6815                 goto done;
6816         }
6817         n = rc * sizeof(uint32_t);      /* rc has # of words actually read */
6818
6819         rc = sysctl_wire_old_buffer(req, 0);
6820         if (rc != 0)
6821                 goto done;
6822
6823         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6824         if (sb == NULL) {
6825                 rc = ENOMEM;
6826                 goto done;
6827         }
6828
6829         sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
6830         for (i = 0, p = buf; i < n; i += 16, p += 4)
6831                 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
6832                     p[2], p[3]);
6833
6834         rc = sbuf_finish(sb);
6835         sbuf_delete(sb);
6836 done:
6837         free(buf, M_CXGBE);
6838         return (rc);
6839 }
6840
6841 static int
6842 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
6843 {
6844         struct adapter *sc = arg1;
6845         u_int cfg;
6846         struct sbuf *sb;
6847         uint32_t *buf, *p;
6848         int rc;
6849
6850         MPASS(chip_id(sc) <= CHELSIO_T5);
6851
6852         rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6853         if (rc != 0)
6854                 return (rc);
6855
6856         rc = sysctl_wire_old_buffer(req, 0);
6857         if (rc != 0)
6858                 return (rc);
6859
6860         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6861         if (sb == NULL)
6862                 return (ENOMEM);
6863
6864         buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6865             M_ZERO | M_WAITOK);
6866
6867         rc = -t4_cim_read_la(sc, buf, NULL);
6868         if (rc != 0)
6869                 goto done;
6870
6871         sbuf_printf(sb, "Status   Data      PC%s",
6872             cfg & F_UPDBGLACAPTPCONLY ? "" :
6873             "     LS0Stat  LS0Addr             LS0Data");
6874
6875         for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
6876                 if (cfg & F_UPDBGLACAPTPCONLY) {
6877                         sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
6878                             p[6], p[7]);
6879                         sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
6880                             (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
6881                             p[4] & 0xff, p[5] >> 8);
6882                         sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
6883                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6884                             p[1] & 0xf, p[2] >> 4);
6885                 } else {
6886                         sbuf_printf(sb,
6887                             "\n  %02x   %x%07x %x%07x %08x %08x "
6888                             "%08x%08x%08x%08x",
6889                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6890                             p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
6891                             p[6], p[7]);
6892                 }
6893         }
6894
6895         rc = sbuf_finish(sb);
6896         sbuf_delete(sb);
6897 done:
6898         free(buf, M_CXGBE);
6899         return (rc);
6900 }
6901
6902 static int
6903 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
6904 {
6905         struct adapter *sc = arg1;
6906         u_int cfg;
6907         struct sbuf *sb;
6908         uint32_t *buf, *p;
6909         int rc;
6910
6911         MPASS(chip_id(sc) > CHELSIO_T5);
6912
6913         rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6914         if (rc != 0)
6915                 return (rc);
6916
6917         rc = sysctl_wire_old_buffer(req, 0);
6918         if (rc != 0)
6919                 return (rc);
6920
6921         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6922         if (sb == NULL)
6923                 return (ENOMEM);
6924
6925         buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6926             M_ZERO | M_WAITOK);
6927
6928         rc = -t4_cim_read_la(sc, buf, NULL);
6929         if (rc != 0)
6930                 goto done;
6931
6932         sbuf_printf(sb, "Status   Inst    Data      PC%s",
6933             cfg & F_UPDBGLACAPTPCONLY ? "" :
6934             "     LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data");
6935
6936         for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
6937                 if (cfg & F_UPDBGLACAPTPCONLY) {
6938                         sbuf_printf(sb, "\n  %02x   %08x %08x %08x",
6939                             p[3] & 0xff, p[2], p[1], p[0]);
6940                         sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x %02x%06x",
6941                             (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
6942                             p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
6943                         sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x",
6944                             (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
6945                             p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
6946                             p[6] >> 16);
6947                 } else {
6948                         sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x "
6949                             "%08x %08x %08x %08x %08x %08x",
6950                             (p[9] >> 16) & 0xff,
6951                             p[9] & 0xffff, p[8] >> 16,
6952                             p[8] & 0xffff, p[7] >> 16,
6953                             p[7] & 0xffff, p[6] >> 16,
6954                             p[2], p[1], p[0], p[5], p[4], p[3]);
6955                 }
6956         }
6957
6958         rc = sbuf_finish(sb);
6959         sbuf_delete(sb);
6960 done:
6961         free(buf, M_CXGBE);
6962         return (rc);
6963 }
6964
6965 static int
6966 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
6967 {
6968         struct adapter *sc = arg1;
6969         u_int i;
6970         struct sbuf *sb;
6971         uint32_t *buf, *p;
6972         int rc;
6973
6974         rc = sysctl_wire_old_buffer(req, 0);
6975         if (rc != 0)
6976                 return (rc);
6977
6978         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6979         if (sb == NULL)
6980                 return (ENOMEM);
6981
6982         buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6983             M_ZERO | M_WAITOK);
6984
6985         t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6986         p = buf;
6987
6988         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6989                 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6990                     p[1], p[0]);
6991         }
6992
6993         sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
6994         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6995                 sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
6996                     (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6997                     (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6998                     (p[1] >> 2) | ((p[2] & 3) << 30),
6999                     (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7000                     p[0] & 1);
7001         }
7002
7003         rc = sbuf_finish(sb);
7004         sbuf_delete(sb);
7005         free(buf, M_CXGBE);
7006         return (rc);
7007 }
7008
7009 static int
7010 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7011 {
7012         struct adapter *sc = arg1;
7013         u_int i;
7014         struct sbuf *sb;
7015         uint32_t *buf, *p;
7016         int rc;
7017
7018         rc = sysctl_wire_old_buffer(req, 0);
7019         if (rc != 0)
7020                 return (rc);
7021
7022         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7023         if (sb == NULL)
7024                 return (ENOMEM);
7025
7026         buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7027             M_ZERO | M_WAITOK);
7028
7029         t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7030         p = buf;
7031
7032         sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
7033         for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7034                 sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
7035                     (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7036                     p[4], p[3], p[2], p[1], p[0]);
7037         }
7038
7039         sbuf_printf(sb, "\n\nCntl ID               Data");
7040         for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7041                 sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
7042                     (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7043         }
7044
7045         rc = sbuf_finish(sb);
7046         sbuf_delete(sb);
7047         free(buf, M_CXGBE);
7048         return (rc);
7049 }
7050
7051 static int
7052 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7053 {
7054         struct adapter *sc = arg1;
7055         struct sbuf *sb;
7056         int rc, i;
7057         uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7058         uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7059         uint16_t thres[CIM_NUM_IBQ];
7060         uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7061         uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7062         u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7063
7064         cim_num_obq = sc->chip_params->cim_num_obq;
7065         if (is_t4(sc)) {
7066                 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7067                 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7068         } else {
7069                 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7070                 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7071         }
7072         nq = CIM_NUM_IBQ + cim_num_obq;
7073
7074         rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7075         if (rc == 0)
7076                 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7077         if (rc != 0)
7078                 return (rc);
7079
7080         t4_read_cimq_cfg(sc, base, size, thres);
7081
7082         rc = sysctl_wire_old_buffer(req, 0);
7083         if (rc != 0)
7084                 return (rc);
7085
7086         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7087         if (sb == NULL)
7088                 return (ENOMEM);
7089
7090         sbuf_printf(sb,
7091             "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
7092
7093         for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7094                 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
7095                     qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7096                     G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7097                     G_QUEREMFLITS(p[2]) * 16);
7098         for ( ; i < nq; i++, p += 4, wr += 2)
7099                 sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
7100                     base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7101                     wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7102                     G_QUEREMFLITS(p[2]) * 16);
7103
7104         rc = sbuf_finish(sb);
7105         sbuf_delete(sb);
7106
7107         return (rc);
7108 }
7109
7110 static int
7111 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7112 {
7113         struct adapter *sc = arg1;
7114         struct sbuf *sb;
7115         int rc;
7116         struct tp_cpl_stats stats;
7117
7118         rc = sysctl_wire_old_buffer(req, 0);
7119         if (rc != 0)
7120                 return (rc);
7121
7122         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7123         if (sb == NULL)
7124                 return (ENOMEM);
7125
7126         mtx_lock(&sc->reg_lock);
7127         t4_tp_get_cpl_stats(sc, &stats, 0);
7128         mtx_unlock(&sc->reg_lock);
7129
7130         if (sc->chip_params->nchan > 2) {
7131                 sbuf_printf(sb, "                 channel 0  channel 1"
7132                     "  channel 2  channel 3");
7133                 sbuf_printf(sb, "\nCPL requests:   %10u %10u %10u %10u",
7134                     stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7135                 sbuf_printf(sb, "\nCPL responses:   %10u %10u %10u %10u",
7136                     stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7137         } else {
7138                 sbuf_printf(sb, "                 channel 0  channel 1");
7139                 sbuf_printf(sb, "\nCPL requests:   %10u %10u",
7140                     stats.req[0], stats.req[1]);
7141                 sbuf_printf(sb, "\nCPL responses:   %10u %10u",
7142                     stats.rsp[0], stats.rsp[1]);
7143         }
7144
7145         rc = sbuf_finish(sb);
7146         sbuf_delete(sb);
7147
7148         return (rc);
7149 }
7150
7151 static int
7152 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7153 {
7154         struct adapter *sc = arg1;
7155         struct sbuf *sb;
7156         int rc;
7157         struct tp_usm_stats stats;
7158
7159         rc = sysctl_wire_old_buffer(req, 0);
7160         if (rc != 0)
7161                 return(rc);
7162
7163         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7164         if (sb == NULL)
7165                 return (ENOMEM);
7166
7167         t4_get_usm_stats(sc, &stats, 1);
7168
7169         sbuf_printf(sb, "Frames: %u\n", stats.frames);
7170         sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7171         sbuf_printf(sb, "Drops:  %u", stats.drops);
7172
7173         rc = sbuf_finish(sb);
7174         sbuf_delete(sb);
7175
7176         return (rc);
7177 }
7178
7179 static const char * const devlog_level_strings[] = {
7180         [FW_DEVLOG_LEVEL_EMERG]         = "EMERG",
7181         [FW_DEVLOG_LEVEL_CRIT]          = "CRIT",
7182         [FW_DEVLOG_LEVEL_ERR]           = "ERR",
7183         [FW_DEVLOG_LEVEL_NOTICE]        = "NOTICE",
7184         [FW_DEVLOG_LEVEL_INFO]          = "INFO",
7185         [FW_DEVLOG_LEVEL_DEBUG]         = "DEBUG"
7186 };
7187
7188 static const char * const devlog_facility_strings[] = {
7189         [FW_DEVLOG_FACILITY_CORE]       = "CORE",
7190         [FW_DEVLOG_FACILITY_CF]         = "CF",
7191         [FW_DEVLOG_FACILITY_SCHED]      = "SCHED",
7192         [FW_DEVLOG_FACILITY_TIMER]      = "TIMER",
7193         [FW_DEVLOG_FACILITY_RES]        = "RES",
7194         [FW_DEVLOG_FACILITY_HW]         = "HW",
7195         [FW_DEVLOG_FACILITY_FLR]        = "FLR",
7196         [FW_DEVLOG_FACILITY_DMAQ]       = "DMAQ",
7197         [FW_DEVLOG_FACILITY_PHY]        = "PHY",
7198         [FW_DEVLOG_FACILITY_MAC]        = "MAC",
7199         [FW_DEVLOG_FACILITY_PORT]       = "PORT",
7200         [FW_DEVLOG_FACILITY_VI]         = "VI",
7201         [FW_DEVLOG_FACILITY_FILTER]     = "FILTER",
7202         [FW_DEVLOG_FACILITY_ACL]        = "ACL",
7203         [FW_DEVLOG_FACILITY_TM]         = "TM",
7204         [FW_DEVLOG_FACILITY_QFC]        = "QFC",
7205         [FW_DEVLOG_FACILITY_DCB]        = "DCB",
7206         [FW_DEVLOG_FACILITY_ETH]        = "ETH",
7207         [FW_DEVLOG_FACILITY_OFLD]       = "OFLD",
7208         [FW_DEVLOG_FACILITY_RI]         = "RI",
7209         [FW_DEVLOG_FACILITY_ISCSI]      = "ISCSI",
7210         [FW_DEVLOG_FACILITY_FCOE]       = "FCOE",
7211         [FW_DEVLOG_FACILITY_FOISCSI]    = "FOISCSI",
7212         [FW_DEVLOG_FACILITY_FOFCOE]     = "FOFCOE",
7213         [FW_DEVLOG_FACILITY_CHNET]      = "CHNET",
7214 };
7215
7216 static int
7217 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7218 {
7219         struct adapter *sc = arg1;
7220         struct devlog_params *dparams = &sc->params.devlog;
7221         struct fw_devlog_e *buf, *e;
7222         int i, j, rc, nentries, first = 0;
7223         struct sbuf *sb;
7224         uint64_t ftstamp = UINT64_MAX;
7225
7226         if (dparams->addr == 0)
7227                 return (ENXIO);
7228
7229         buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
7230         if (buf == NULL)
7231                 return (ENOMEM);
7232
7233         rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7234         if (rc != 0)
7235                 goto done;
7236
7237         nentries = dparams->size / sizeof(struct fw_devlog_e);
7238         for (i = 0; i < nentries; i++) {
7239                 e = &buf[i];
7240
7241                 if (e->timestamp == 0)
7242                         break;  /* end */
7243
7244                 e->timestamp = be64toh(e->timestamp);
7245                 e->seqno = be32toh(e->seqno);
7246                 for (j = 0; j < 8; j++)
7247                         e->params[j] = be32toh(e->params[j]);
7248
7249                 if (e->timestamp < ftstamp) {
7250                         ftstamp = e->timestamp;
7251                         first = i;
7252                 }
7253         }
7254
7255         if (buf[first].timestamp == 0)
7256                 goto done;      /* nothing in the log */
7257
7258         rc = sysctl_wire_old_buffer(req, 0);
7259         if (rc != 0)
7260                 goto done;
7261
7262         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7263         if (sb == NULL) {
7264                 rc = ENOMEM;
7265                 goto done;
7266         }
7267         sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
7268             "Seq#", "Tstamp", "Level", "Facility", "Message");
7269
7270         i = first;
7271         do {
7272                 e = &buf[i];
7273                 if (e->timestamp == 0)
7274                         break;  /* end */
7275
7276                 sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
7277                     e->seqno, e->timestamp,
7278                     (e->level < nitems(devlog_level_strings) ?
7279                         devlog_level_strings[e->level] : "UNKNOWN"),
7280                     (e->facility < nitems(devlog_facility_strings) ?
7281                         devlog_facility_strings[e->facility] : "UNKNOWN"));
7282                 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7283                     e->params[2], e->params[3], e->params[4],
7284                     e->params[5], e->params[6], e->params[7]);
7285
7286                 if (++i == nentries)
7287                         i = 0;
7288         } while (i != first);
7289
7290         rc = sbuf_finish(sb);
7291         sbuf_delete(sb);
7292 done:
7293         free(buf, M_CXGBE);
7294         return (rc);
7295 }
7296
7297 static int
7298 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7299 {
7300         struct adapter *sc = arg1;
7301         struct sbuf *sb;
7302         int rc;
7303         struct tp_fcoe_stats stats[MAX_NCHAN];
7304         int i, nchan = sc->chip_params->nchan;
7305
7306         rc = sysctl_wire_old_buffer(req, 0);
7307         if (rc != 0)
7308                 return (rc);
7309
7310         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7311         if (sb == NULL)
7312                 return (ENOMEM);
7313
7314         for (i = 0; i < nchan; i++)
7315                 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7316
7317         if (nchan > 2) {
7318                 sbuf_printf(sb, "                   channel 0        channel 1"
7319                     "        channel 2        channel 3");
7320                 sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju %16ju %16ju",
7321                     stats[0].octets_ddp, stats[1].octets_ddp,
7322                     stats[2].octets_ddp, stats[3].octets_ddp);
7323                 sbuf_printf(sb, "\nframesDDP:  %16u %16u %16u %16u",
7324                     stats[0].frames_ddp, stats[1].frames_ddp,
7325                     stats[2].frames_ddp, stats[3].frames_ddp);
7326                 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7327                     stats[0].frames_drop, stats[1].frames_drop,
7328                     stats[2].frames_drop, stats[3].frames_drop);
7329         } else {
7330                 sbuf_printf(sb, "                   channel 0        channel 1");
7331                 sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju",
7332                     stats[0].octets_ddp, stats[1].octets_ddp);
7333                 sbuf_printf(sb, "\nframesDDP:  %16u %16u",
7334                     stats[0].frames_ddp, stats[1].frames_ddp);
7335                 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7336                     stats[0].frames_drop, stats[1].frames_drop);
7337         }
7338
7339         rc = sbuf_finish(sb);
7340         sbuf_delete(sb);
7341
7342         return (rc);
7343 }
7344
7345 static int
7346 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7347 {
7348         struct adapter *sc = arg1;
7349         struct sbuf *sb;
7350         int rc, i;
7351         unsigned int map, kbps, ipg, mode;
7352         unsigned int pace_tab[NTX_SCHED];
7353
7354         rc = sysctl_wire_old_buffer(req, 0);
7355         if (rc != 0)
7356                 return (rc);
7357
7358         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7359         if (sb == NULL)
7360                 return (ENOMEM);
7361
7362         map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7363         mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7364         t4_read_pace_tbl(sc, pace_tab);
7365
7366         sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
7367             "Class IPG (0.1 ns)   Flow IPG (us)");
7368
7369         for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7370                 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7371                 sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
7372                     (mode & (1 << i)) ? "flow" : "class", map & 3);
7373                 if (kbps)
7374                         sbuf_printf(sb, "%9u     ", kbps);
7375                 else
7376                         sbuf_printf(sb, " disabled     ");
7377
7378                 if (ipg)
7379                         sbuf_printf(sb, "%13u        ", ipg);
7380                 else
7381                         sbuf_printf(sb, "     disabled        ");
7382
7383                 if (pace_tab[i])
7384                         sbuf_printf(sb, "%10u", pace_tab[i]);
7385                 else
7386                         sbuf_printf(sb, "  disabled");
7387         }
7388
7389         rc = sbuf_finish(sb);
7390         sbuf_delete(sb);
7391
7392         return (rc);
7393 }
7394
7395 static int
7396 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7397 {
7398         struct adapter *sc = arg1;
7399         struct sbuf *sb;
7400         int rc, i, j;
7401         uint64_t *p0, *p1;
7402         struct lb_port_stats s[2];
7403         static const char *stat_name[] = {
7404                 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7405                 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7406                 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7407                 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7408                 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7409                 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7410                 "BG2FramesTrunc:", "BG3FramesTrunc:"
7411         };
7412
7413         rc = sysctl_wire_old_buffer(req, 0);
7414         if (rc != 0)
7415                 return (rc);
7416
7417         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7418         if (sb == NULL)
7419                 return (ENOMEM);
7420
7421         memset(s, 0, sizeof(s));
7422
7423         for (i = 0; i < sc->chip_params->nchan; i += 2) {
7424                 t4_get_lb_stats(sc, i, &s[0]);
7425                 t4_get_lb_stats(sc, i + 1, &s[1]);
7426
7427                 p0 = &s[0].octets;
7428                 p1 = &s[1].octets;
7429                 sbuf_printf(sb, "%s                       Loopback %u"
7430                     "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7431
7432                 for (j = 0; j < nitems(stat_name); j++)
7433                         sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7434                                    *p0++, *p1++);
7435         }
7436
7437         rc = sbuf_finish(sb);
7438         sbuf_delete(sb);
7439
7440         return (rc);
7441 }
7442
7443 static int
7444 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7445 {
7446         int rc = 0;
7447         struct port_info *pi = arg1;
7448         struct link_config *lc = &pi->link_cfg;
7449         struct sbuf *sb;
7450
7451         rc = sysctl_wire_old_buffer(req, 0);
7452         if (rc != 0)
7453                 return(rc);
7454         sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7455         if (sb == NULL)
7456                 return (ENOMEM);
7457
7458         if (lc->link_ok || lc->link_down_rc == 255)
7459                 sbuf_printf(sb, "n/a");
7460         else
7461                 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7462
7463         rc = sbuf_finish(sb);
7464         sbuf_delete(sb);
7465
7466         return (rc);
7467 }
7468
7469 struct mem_desc {
7470         unsigned int base;
7471         unsigned int limit;
7472         unsigned int idx;
7473 };
7474
7475 static int
7476 mem_desc_cmp(const void *a, const void *b)
7477 {
7478         return ((const struct mem_desc *)a)->base -
7479                ((const struct mem_desc *)b)->base;
7480 }
7481
7482 static void
7483 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7484     unsigned int to)
7485 {
7486         unsigned int size;
7487
7488         if (from == to)
7489                 return;
7490
7491         size = to - from + 1;
7492         if (size == 0)
7493                 return;
7494
7495         /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7496         sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7497 }
7498
7499 static int
7500 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7501 {
7502         struct adapter *sc = arg1;
7503         struct sbuf *sb;
7504         int rc, i, n;
7505         uint32_t lo, hi, used, alloc;
7506         static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7507         static const char *region[] = {
7508                 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7509                 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7510                 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7511                 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7512                 "RQUDP region:", "PBL region:", "TXPBL region:",
7513                 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7514                 "On-chip queues:", "TLS keys:",
7515         };
7516         struct mem_desc avail[4];
7517         struct mem_desc mem[nitems(region) + 3];        /* up to 3 holes */
7518         struct mem_desc *md = mem;
7519
7520         rc = sysctl_wire_old_buffer(req, 0);
7521         if (rc != 0)
7522                 return (rc);
7523
7524         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7525         if (sb == NULL)
7526                 return (ENOMEM);
7527
7528         for (i = 0; i < nitems(mem); i++) {
7529                 mem[i].limit = 0;
7530                 mem[i].idx = i;
7531         }
7532
7533         /* Find and sort the populated memory ranges */
7534         i = 0;
7535         lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7536         if (lo & F_EDRAM0_ENABLE) {
7537                 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7538                 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7539                 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7540                 avail[i].idx = 0;
7541                 i++;
7542         }
7543         if (lo & F_EDRAM1_ENABLE) {
7544                 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7545                 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7546                 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7547                 avail[i].idx = 1;
7548                 i++;
7549         }
7550         if (lo & F_EXT_MEM_ENABLE) {
7551                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7552                 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7553                 avail[i].limit = avail[i].base +
7554                     (G_EXT_MEM_SIZE(hi) << 20);
7555                 avail[i].idx = is_t5(sc) ? 3 : 2;       /* Call it MC0 for T5 */
7556                 i++;
7557         }
7558         if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7559                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7560                 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7561                 avail[i].limit = avail[i].base +
7562                     (G_EXT_MEM1_SIZE(hi) << 20);
7563                 avail[i].idx = 4;
7564                 i++;
7565         }
7566         if (!i)                                    /* no memory available */
7567                 return 0;
7568         qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
7569
7570         (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
7571         (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
7572         (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
7573         (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7574         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
7575         (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
7576         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
7577         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
7578         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
7579
7580         /* the next few have explicit upper bounds */
7581         md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
7582         md->limit = md->base - 1 +
7583                     t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
7584                     G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
7585         md++;
7586
7587         md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
7588         md->limit = md->base - 1 +
7589                     t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
7590                     G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
7591         md++;
7592
7593         if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7594                 if (chip_id(sc) <= CHELSIO_T5)
7595                         md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
7596                 else
7597                         md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
7598                 md->limit = 0;
7599         } else {
7600                 md->base = 0;
7601                 md->idx = nitems(region);  /* hide it */
7602         }
7603         md++;
7604
7605 #define ulp_region(reg) \
7606         md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
7607         (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
7608
7609         ulp_region(RX_ISCSI);
7610         ulp_region(RX_TDDP);
7611         ulp_region(TX_TPT);
7612         ulp_region(RX_STAG);
7613         ulp_region(RX_RQ);
7614         ulp_region(RX_RQUDP);
7615         ulp_region(RX_PBL);
7616         ulp_region(TX_PBL);
7617 #undef ulp_region
7618
7619         md->base = 0;
7620         md->idx = nitems(region);
7621         if (!is_t4(sc)) {
7622                 uint32_t size = 0;
7623                 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
7624                 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
7625
7626                 if (is_t5(sc)) {
7627                         if (sge_ctrl & F_VFIFO_ENABLE)
7628                                 size = G_DBVFIFO_SIZE(fifo_size);
7629                 } else
7630                         size = G_T6_DBVFIFO_SIZE(fifo_size);
7631
7632                 if (size) {
7633                         md->base = G_BASEADDR(t4_read_reg(sc,
7634                             A_SGE_DBVFIFO_BADDR));
7635                         md->limit = md->base + (size << 2) - 1;
7636                 }
7637         }
7638         md++;
7639
7640         md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
7641         md->limit = 0;
7642         md++;
7643         md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
7644         md->limit = 0;
7645         md++;
7646
7647         md->base = sc->vres.ocq.start;
7648         if (sc->vres.ocq.size)
7649                 md->limit = md->base + sc->vres.ocq.size - 1;
7650         else
7651                 md->idx = nitems(region);  /* hide it */
7652         md++;
7653
7654         md->base = sc->vres.key.start;
7655         if (sc->vres.key.size)
7656                 md->limit = md->base + sc->vres.key.size - 1;
7657         else
7658                 md->idx = nitems(region);  /* hide it */
7659         md++;
7660
7661         /* add any address-space holes, there can be up to 3 */
7662         for (n = 0; n < i - 1; n++)
7663                 if (avail[n].limit < avail[n + 1].base)
7664                         (md++)->base = avail[n].limit;
7665         if (avail[n].limit)
7666                 (md++)->base = avail[n].limit;
7667
7668         n = md - mem;
7669         qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
7670
7671         for (lo = 0; lo < i; lo++)
7672                 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
7673                                 avail[lo].limit - 1);
7674
7675         sbuf_printf(sb, "\n");
7676         for (i = 0; i < n; i++) {
7677                 if (mem[i].idx >= nitems(region))
7678                         continue;                        /* skip holes */
7679                 if (!mem[i].limit)
7680                         mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
7681                 mem_region_show(sb, region[mem[i].idx], mem[i].base,
7682                                 mem[i].limit);
7683         }
7684
7685         sbuf_printf(sb, "\n");
7686         lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
7687         hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
7688         mem_region_show(sb, "uP RAM:", lo, hi);
7689
7690         lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
7691         hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
7692         mem_region_show(sb, "uP Extmem2:", lo, hi);
7693
7694         lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
7695         sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
7696                    G_PMRXMAXPAGE(lo),
7697                    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
7698                    (lo & F_PMRXNUMCHN) ? 2 : 1);
7699
7700         lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
7701         hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
7702         sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
7703                    G_PMTXMAXPAGE(lo),
7704                    hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
7705                    hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
7706         sbuf_printf(sb, "%u p-structs\n",
7707                    t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
7708
7709         for (i = 0; i < 4; i++) {
7710                 if (chip_id(sc) > CHELSIO_T5)
7711                         lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
7712                 else
7713                         lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
7714                 if (is_t5(sc)) {
7715                         used = G_T5_USED(lo);
7716                         alloc = G_T5_ALLOC(lo);
7717                 } else {
7718                         used = G_USED(lo);
7719                         alloc = G_ALLOC(lo);
7720                 }
7721                 /* For T6 these are MAC buffer groups */
7722                 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
7723                     i, used, alloc);
7724         }
7725         for (i = 0; i < sc->chip_params->nchan; i++) {
7726                 if (chip_id(sc) > CHELSIO_T5)
7727                         lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
7728                 else
7729                         lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
7730                 if (is_t5(sc)) {
7731                         used = G_T5_USED(lo);
7732                         alloc = G_T5_ALLOC(lo);
7733                 } else {
7734                         used = G_USED(lo);
7735                         alloc = G_ALLOC(lo);
7736                 }
7737                 /* For T6 these are MAC buffer groups */
7738                 sbuf_printf(sb,
7739                     "\nLoopback %d using %u pages out of %u allocated",
7740                     i, used, alloc);
7741         }
7742
7743         rc = sbuf_finish(sb);
7744         sbuf_delete(sb);
7745
7746         return (rc);
7747 }
7748
7749 static inline void
7750 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7751 {
7752         *mask = x | y;
7753         y = htobe64(y);
7754         memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7755 }
7756
7757 static int
7758 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7759 {
7760         struct adapter *sc = arg1;
7761         struct sbuf *sb;
7762         int rc, i;
7763
7764         MPASS(chip_id(sc) <= CHELSIO_T5);
7765
7766         rc = sysctl_wire_old_buffer(req, 0);
7767         if (rc != 0)
7768                 return (rc);
7769
7770         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7771         if (sb == NULL)
7772                 return (ENOMEM);
7773
7774         sbuf_printf(sb,
7775             "Idx  Ethernet address     Mask     Vld Ports PF"
7776             "  VF              Replication             P0 P1 P2 P3  ML");
7777         for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7778                 uint64_t tcamx, tcamy, mask;
7779                 uint32_t cls_lo, cls_hi;
7780                 uint8_t addr[ETHER_ADDR_LEN];
7781
7782                 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7783                 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7784                 if (tcamx & tcamy)
7785                         continue;
7786                 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7787                 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7788                 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7789                 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7790                            "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
7791                            addr[3], addr[4], addr[5], (uintmax_t)mask,
7792                            (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7793                            G_PORTMAP(cls_hi), G_PF(cls_lo),
7794                            (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7795
7796                 if (cls_lo & F_REPLICATE) {
7797                         struct fw_ldst_cmd ldst_cmd;
7798
7799                         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7800                         ldst_cmd.op_to_addrspace =
7801                             htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7802                                 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7803                                 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7804                         ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7805                         ldst_cmd.u.mps.rplc.fid_idx =
7806                             htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7807                                 V_FW_LDST_CMD_IDX(i));
7808
7809                         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7810                             "t4mps");
7811                         if (rc)
7812                                 break;
7813                         rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7814                             sizeof(ldst_cmd), &ldst_cmd);
7815                         end_synchronized_op(sc, 0);
7816
7817                         if (rc != 0) {
7818                                 sbuf_printf(sb, "%36d", rc);
7819                                 rc = 0;
7820                         } else {
7821                                 sbuf_printf(sb, " %08x %08x %08x %08x",
7822                                     be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7823                                     be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7824                                     be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7825                                     be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7826                         }
7827                 } else
7828                         sbuf_printf(sb, "%36s", "");
7829
7830                 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
7831                     G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
7832                     G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
7833         }
7834
7835         if (rc)
7836                 (void) sbuf_finish(sb);
7837         else
7838                 rc = sbuf_finish(sb);
7839         sbuf_delete(sb);
7840
7841         return (rc);
7842 }
7843
7844 static int
7845 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
7846 {
7847         struct adapter *sc = arg1;
7848         struct sbuf *sb;
7849         int rc, i;
7850
7851         MPASS(chip_id(sc) > CHELSIO_T5);
7852
7853         rc = sysctl_wire_old_buffer(req, 0);
7854         if (rc != 0)
7855                 return (rc);
7856
7857         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7858         if (sb == NULL)
7859                 return (ENOMEM);
7860
7861         sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
7862             "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
7863             "                           Replication"
7864             "                                    P0 P1 P2 P3  ML\n");
7865
7866         for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7867                 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
7868                 uint16_t ivlan;
7869                 uint64_t tcamx, tcamy, val, mask;
7870                 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
7871                 uint8_t addr[ETHER_ADDR_LEN];
7872
7873                 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
7874                 if (i < 256)
7875                         ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
7876                 else
7877                         ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
7878                 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7879                 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7880                 tcamy = G_DMACH(val) << 32;
7881                 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7882                 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7883                 lookup_type = G_DATALKPTYPE(data2);
7884                 port_num = G_DATAPORTNUM(data2);
7885                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7886                         /* Inner header VNI */
7887                         vniy = ((data2 & F_DATAVIDH2) << 23) |
7888                                        (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7889                         dip_hit = data2 & F_DATADIPHIT;
7890                         vlan_vld = 0;
7891                 } else {
7892                         vniy = 0;
7893                         dip_hit = 0;
7894                         vlan_vld = data2 & F_DATAVIDH2;
7895                         ivlan = G_VIDL(val);
7896                 }
7897
7898                 ctl |= V_CTLXYBITSEL(1);
7899                 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7900                 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7901                 tcamx = G_DMACH(val) << 32;
7902                 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7903                 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7904                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7905                         /* Inner header VNI mask */
7906                         vnix = ((data2 & F_DATAVIDH2) << 23) |
7907                                (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7908                 } else
7909                         vnix = 0;
7910
7911                 if (tcamx & tcamy)
7912                         continue;
7913                 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7914
7915                 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7916                 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7917
7918                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7919                         sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7920                             "%012jx %06x %06x    -    -   %3c"
7921                             "      'I'  %4x   %3c   %#x%4u%4d", i, addr[0],
7922                             addr[1], addr[2], addr[3], addr[4], addr[5],
7923                             (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
7924                             port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7925                             G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7926                             cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7927                 } else {
7928                         sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7929                             "%012jx    -       -   ", i, addr[0], addr[1],
7930                             addr[2], addr[3], addr[4], addr[5],
7931                             (uintmax_t)mask);
7932
7933                         if (vlan_vld)
7934                                 sbuf_printf(sb, "%4u   Y     ", ivlan);
7935                         else
7936                                 sbuf_printf(sb, "  -    N     ");
7937
7938                         sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
7939                             lookup_type ? 'I' : 'O', port_num,
7940                             cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7941                             G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7942                             cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7943                 }
7944
7945
7946                 if (cls_lo & F_T6_REPLICATE) {
7947                         struct fw_ldst_cmd ldst_cmd;
7948
7949                         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7950                         ldst_cmd.op_to_addrspace =
7951                             htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7952                                 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7953                                 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7954                         ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7955                         ldst_cmd.u.mps.rplc.fid_idx =
7956                             htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7957                                 V_FW_LDST_CMD_IDX(i));
7958
7959                         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7960                             "t6mps");
7961                         if (rc)
7962                                 break;
7963                         rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7964                             sizeof(ldst_cmd), &ldst_cmd);
7965                         end_synchronized_op(sc, 0);
7966
7967                         if (rc != 0) {
7968                                 sbuf_printf(sb, "%72d", rc);
7969                                 rc = 0;
7970                         } else {
7971                                 sbuf_printf(sb, " %08x %08x %08x %08x"
7972                                     " %08x %08x %08x %08x",
7973                                     be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
7974                                     be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
7975                                     be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
7976                                     be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
7977                                     be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7978                                     be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7979                                     be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7980                                     be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7981                         }
7982                 } else
7983                         sbuf_printf(sb, "%72s", "");
7984
7985                 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
7986                     G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
7987                     G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7988                     (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7989         }
7990
7991         if (rc)
7992                 (void) sbuf_finish(sb);
7993         else
7994                 rc = sbuf_finish(sb);
7995         sbuf_delete(sb);
7996
7997         return (rc);
7998 }
7999
8000 static int
8001 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8002 {
8003         struct adapter *sc = arg1;
8004         struct sbuf *sb;
8005         int rc;
8006         uint16_t mtus[NMTUS];
8007
8008         rc = sysctl_wire_old_buffer(req, 0);
8009         if (rc != 0)
8010                 return (rc);
8011
8012         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8013         if (sb == NULL)
8014                 return (ENOMEM);
8015
8016         t4_read_mtu_tbl(sc, mtus, NULL);
8017
8018         sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8019             mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8020             mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8021             mtus[14], mtus[15]);
8022
8023         rc = sbuf_finish(sb);
8024         sbuf_delete(sb);
8025
8026         return (rc);
8027 }
8028
8029 static int
8030 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8031 {
8032         struct adapter *sc = arg1;
8033         struct sbuf *sb;
8034         int rc, i;
8035         uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8036         uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8037         static const char *tx_stats[MAX_PM_NSTATS] = {
8038                 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8039                 "Tx FIFO wait", NULL, "Tx latency"
8040         };
8041         static const char *rx_stats[MAX_PM_NSTATS] = {
8042                 "Read:", "Write bypass:", "Write mem:", "Flush:",
8043                 "Rx FIFO wait", NULL, "Rx latency"
8044         };
8045
8046         rc = sysctl_wire_old_buffer(req, 0);
8047         if (rc != 0)
8048                 return (rc);
8049
8050         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8051         if (sb == NULL)
8052                 return (ENOMEM);
8053
8054         t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8055         t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8056
8057         sbuf_printf(sb, "                Tx pcmds             Tx bytes");
8058         for (i = 0; i < 4; i++) {
8059                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8060                     tx_cyc[i]);
8061         }
8062
8063         sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
8064         for (i = 0; i < 4; i++) {
8065                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8066                     rx_cyc[i]);
8067         }
8068
8069         if (chip_id(sc) > CHELSIO_T5) {
8070                 sbuf_printf(sb,
8071                     "\n              Total wait      Total occupancy");
8072                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8073                     tx_cyc[i]);
8074                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8075                     rx_cyc[i]);
8076
8077                 i += 2;
8078                 MPASS(i < nitems(tx_stats));
8079
8080                 sbuf_printf(sb,
8081                     "\n                   Reads           Total wait");
8082                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8083                     tx_cyc[i]);
8084                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8085                     rx_cyc[i]);
8086         }
8087
8088         rc = sbuf_finish(sb);
8089         sbuf_delete(sb);
8090
8091         return (rc);
8092 }
8093
8094 static int
8095 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8096 {
8097         struct adapter *sc = arg1;
8098         struct sbuf *sb;
8099         int rc;
8100         struct tp_rdma_stats stats;
8101
8102         rc = sysctl_wire_old_buffer(req, 0);
8103         if (rc != 0)
8104                 return (rc);
8105
8106         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8107         if (sb == NULL)
8108                 return (ENOMEM);
8109
8110         mtx_lock(&sc->reg_lock);
8111         t4_tp_get_rdma_stats(sc, &stats, 0);
8112         mtx_unlock(&sc->reg_lock);
8113
8114         sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8115         sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8116
8117         rc = sbuf_finish(sb);
8118         sbuf_delete(sb);
8119
8120         return (rc);
8121 }
8122
8123 static int
8124 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8125 {
8126         struct adapter *sc = arg1;
8127         struct sbuf *sb;
8128         int rc;
8129         struct tp_tcp_stats v4, v6;
8130
8131         rc = sysctl_wire_old_buffer(req, 0);
8132         if (rc != 0)
8133                 return (rc);
8134
8135         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8136         if (sb == NULL)
8137                 return (ENOMEM);
8138
8139         mtx_lock(&sc->reg_lock);
8140         t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8141         mtx_unlock(&sc->reg_lock);
8142
8143         sbuf_printf(sb,
8144             "                                IP                 IPv6\n");
8145         sbuf_printf(sb, "OutRsts:      %20u %20u\n",
8146             v4.tcp_out_rsts, v6.tcp_out_rsts);
8147         sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
8148             v4.tcp_in_segs, v6.tcp_in_segs);
8149         sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
8150             v4.tcp_out_segs, v6.tcp_out_segs);
8151         sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
8152             v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8153
8154         rc = sbuf_finish(sb);
8155         sbuf_delete(sb);
8156
8157         return (rc);
8158 }
8159
8160 static int
8161 sysctl_tids(SYSCTL_HANDLER_ARGS)
8162 {
8163         struct adapter *sc = arg1;
8164         struct sbuf *sb;
8165         int rc;
8166         struct tid_info *t = &sc->tids;
8167
8168         rc = sysctl_wire_old_buffer(req, 0);
8169         if (rc != 0)
8170                 return (rc);
8171
8172         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8173         if (sb == NULL)
8174                 return (ENOMEM);
8175
8176         if (t->natids) {
8177                 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8178                     t->atids_in_use);
8179         }
8180
8181         if (t->ntids) {
8182                 sbuf_printf(sb, "TID range: ");
8183                 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8184                         uint32_t b, hb;
8185
8186                         if (chip_id(sc) <= CHELSIO_T5) {
8187                                 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8188                                 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8189                         } else {
8190                                 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8191                                 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8192                         }
8193
8194                         if (b)
8195                                 sbuf_printf(sb, "0-%u, ", b - 1);
8196                         sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8197                 } else
8198                         sbuf_printf(sb, "0-%u", t->ntids - 1);
8199                 sbuf_printf(sb, ", in use: %u\n",
8200                     atomic_load_acq_int(&t->tids_in_use));
8201         }
8202
8203         if (t->nstids) {
8204                 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8205                     t->stid_base + t->nstids - 1, t->stids_in_use);
8206         }
8207
8208         if (t->nftids) {
8209                 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
8210                     t->ftid_base + t->nftids - 1);
8211         }
8212
8213         if (t->netids) {
8214                 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
8215                     t->etid_base + t->netids - 1);
8216         }
8217
8218         sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8219             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8220             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8221
8222         rc = sbuf_finish(sb);
8223         sbuf_delete(sb);
8224
8225         return (rc);
8226 }
8227
8228 static int
8229 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8230 {
8231         struct adapter *sc = arg1;
8232         struct sbuf *sb;
8233         int rc;
8234         struct tp_err_stats stats;
8235
8236         rc = sysctl_wire_old_buffer(req, 0);
8237         if (rc != 0)
8238                 return (rc);
8239
8240         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8241         if (sb == NULL)
8242                 return (ENOMEM);
8243
8244         mtx_lock(&sc->reg_lock);
8245         t4_tp_get_err_stats(sc, &stats, 0);
8246         mtx_unlock(&sc->reg_lock);
8247
8248         if (sc->chip_params->nchan > 2) {
8249                 sbuf_printf(sb, "                 channel 0  channel 1"
8250                     "  channel 2  channel 3\n");
8251                 sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
8252                     stats.mac_in_errs[0], stats.mac_in_errs[1],
8253                     stats.mac_in_errs[2], stats.mac_in_errs[3]);
8254                 sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
8255                     stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8256                     stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8257                 sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
8258                     stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8259                     stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8260                 sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
8261                     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8262                     stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8263                 sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
8264                     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8265                     stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8266                 sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
8267                     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8268                     stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8269                 sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
8270                     stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8271                     stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8272                 sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
8273                     stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8274                     stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8275         } else {
8276                 sbuf_printf(sb, "                 channel 0  channel 1\n");
8277                 sbuf_printf(sb, "macInErrs:      %10u %10u\n",
8278                     stats.mac_in_errs[0], stats.mac_in_errs[1]);
8279                 sbuf_printf(sb, "hdrInErrs:      %10u %10u\n",
8280                     stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8281                 sbuf_printf(sb, "tcpInErrs:      %10u %10u\n",
8282                     stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8283                 sbuf_printf(sb, "tcp6InErrs:     %10u %10u\n",
8284                     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8285                 sbuf_printf(sb, "tnlCongDrops:   %10u %10u\n",
8286                     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8287                 sbuf_printf(sb, "tnlTxDrops:     %10u %10u\n",
8288                     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8289                 sbuf_printf(sb, "ofldVlanDrops:  %10u %10u\n",
8290                     stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8291                 sbuf_printf(sb, "ofldChanDrops:  %10u %10u\n\n",
8292                     stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8293         }
8294
8295         sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
8296             stats.ofld_no_neigh, stats.ofld_cong_defer);
8297
8298         rc = sbuf_finish(sb);
8299         sbuf_delete(sb);
8300
8301         return (rc);
8302 }
8303
8304 static int
8305 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8306 {
8307         struct adapter *sc = arg1;
8308         struct tp_params *tpp = &sc->params.tp;
8309         u_int mask;
8310         int rc;
8311
8312         mask = tpp->la_mask >> 16;
8313         rc = sysctl_handle_int(oidp, &mask, 0, req);
8314         if (rc != 0 || req->newptr == NULL)
8315                 return (rc);
8316         if (mask > 0xffff)
8317                 return (EINVAL);
8318         tpp->la_mask = mask << 16;
8319         t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8320
8321         return (0);
8322 }
8323
8324 struct field_desc {
8325         const char *name;
8326         u_int start;
8327         u_int width;
8328 };
8329
8330 static void
8331 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8332 {
8333         char buf[32];
8334         int line_size = 0;
8335
8336         while (f->name) {
8337                 uint64_t mask = (1ULL << f->width) - 1;
8338                 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8339                     ((uintmax_t)v >> f->start) & mask);
8340
8341                 if (line_size + len >= 79) {
8342                         line_size = 8;
8343                         sbuf_printf(sb, "\n        ");
8344                 }
8345                 sbuf_printf(sb, "%s ", buf);
8346                 line_size += len + 1;
8347                 f++;
8348         }
8349         sbuf_printf(sb, "\n");
8350 }
8351
8352 static const struct field_desc tp_la0[] = {
8353         { "RcfOpCodeOut", 60, 4 },
8354         { "State", 56, 4 },
8355         { "WcfState", 52, 4 },
8356         { "RcfOpcSrcOut", 50, 2 },
8357         { "CRxError", 49, 1 },
8358         { "ERxError", 48, 1 },
8359         { "SanityFailed", 47, 1 },
8360         { "SpuriousMsg", 46, 1 },
8361         { "FlushInputMsg", 45, 1 },
8362         { "FlushInputCpl", 44, 1 },
8363         { "RssUpBit", 43, 1 },
8364         { "RssFilterHit", 42, 1 },
8365         { "Tid", 32, 10 },
8366         { "InitTcb", 31, 1 },
8367         { "LineNumber", 24, 7 },
8368         { "Emsg", 23, 1 },
8369         { "EdataOut", 22, 1 },
8370         { "Cmsg", 21, 1 },
8371         { "CdataOut", 20, 1 },
8372         { "EreadPdu", 19, 1 },
8373         { "CreadPdu", 18, 1 },
8374         { "TunnelPkt", 17, 1 },
8375         { "RcfPeerFin", 16, 1 },
8376         { "RcfReasonOut", 12, 4 },
8377         { "TxCchannel", 10, 2 },
8378         { "RcfTxChannel", 8, 2 },
8379         { "RxEchannel", 6, 2 },
8380         { "RcfRxChannel", 5, 1 },
8381         { "RcfDataOutSrdy", 4, 1 },
8382         { "RxDvld", 3, 1 },
8383         { "RxOoDvld", 2, 1 },
8384         { "RxCongestion", 1, 1 },
8385         { "TxCongestion", 0, 1 },
8386         { NULL }
8387 };
8388
8389 static const struct field_desc tp_la1[] = {
8390         { "CplCmdIn", 56, 8 },
8391         { "CplCmdOut", 48, 8 },
8392         { "ESynOut", 47, 1 },
8393         { "EAckOut", 46, 1 },
8394         { "EFinOut", 45, 1 },
8395         { "ERstOut", 44, 1 },
8396         { "SynIn", 43, 1 },
8397         { "AckIn", 42, 1 },
8398         { "FinIn", 41, 1 },
8399         { "RstIn", 40, 1 },
8400         { "DataIn", 39, 1 },
8401         { "DataInVld", 38, 1 },
8402         { "PadIn", 37, 1 },
8403         { "RxBufEmpty", 36, 1 },
8404         { "RxDdp", 35, 1 },
8405         { "RxFbCongestion", 34, 1 },
8406         { "TxFbCongestion", 33, 1 },
8407         { "TxPktSumSrdy", 32, 1 },
8408         { "RcfUlpType", 28, 4 },
8409         { "Eread", 27, 1 },
8410         { "Ebypass", 26, 1 },
8411         { "Esave", 25, 1 },
8412         { "Static0", 24, 1 },
8413         { "Cread", 23, 1 },
8414         { "Cbypass", 22, 1 },
8415         { "Csave", 21, 1 },
8416         { "CPktOut", 20, 1 },
8417         { "RxPagePoolFull", 18, 2 },
8418         { "RxLpbkPkt", 17, 1 },
8419         { "TxLpbkPkt", 16, 1 },
8420         { "RxVfValid", 15, 1 },
8421         { "SynLearned", 14, 1 },
8422         { "SetDelEntry", 13, 1 },
8423         { "SetInvEntry", 12, 1 },
8424         { "CpcmdDvld", 11, 1 },
8425         { "CpcmdSave", 10, 1 },
8426         { "RxPstructsFull", 8, 2 },
8427         { "EpcmdDvld", 7, 1 },
8428         { "EpcmdFlush", 6, 1 },
8429         { "EpcmdTrimPrefix", 5, 1 },
8430         { "EpcmdTrimPostfix", 4, 1 },
8431         { "ERssIp4Pkt", 3, 1 },
8432         { "ERssIp6Pkt", 2, 1 },
8433         { "ERssTcpUdpPkt", 1, 1 },
8434         { "ERssFceFipPkt", 0, 1 },
8435         { NULL }
8436 };
8437
8438 static const struct field_desc tp_la2[] = {
8439         { "CplCmdIn", 56, 8 },
8440         { "MpsVfVld", 55, 1 },
8441         { "MpsPf", 52, 3 },
8442         { "MpsVf", 44, 8 },
8443         { "SynIn", 43, 1 },
8444         { "AckIn", 42, 1 },
8445         { "FinIn", 41, 1 },
8446         { "RstIn", 40, 1 },
8447         { "DataIn", 39, 1 },
8448         { "DataInVld", 38, 1 },
8449         { "PadIn", 37, 1 },
8450         { "RxBufEmpty", 36, 1 },
8451         { "RxDdp", 35, 1 },
8452         { "RxFbCongestion", 34, 1 },
8453         { "TxFbCongestion", 33, 1 },
8454         { "TxPktSumSrdy", 32, 1 },
8455         { "RcfUlpType", 28, 4 },
8456         { "Eread", 27, 1 },
8457         { "Ebypass", 26, 1 },
8458         { "Esave", 25, 1 },
8459         { "Static0", 24, 1 },
8460         { "Cread", 23, 1 },
8461         { "Cbypass", 22, 1 },
8462         { "Csave", 21, 1 },
8463         { "CPktOut", 20, 1 },
8464         { "RxPagePoolFull", 18, 2 },
8465         { "RxLpbkPkt", 17, 1 },
8466         { "TxLpbkPkt", 16, 1 },
8467         { "RxVfValid", 15, 1 },
8468         { "SynLearned", 14, 1 },
8469         { "SetDelEntry", 13, 1 },
8470         { "SetInvEntry", 12, 1 },
8471         { "CpcmdDvld", 11, 1 },
8472         { "CpcmdSave", 10, 1 },
8473         { "RxPstructsFull", 8, 2 },
8474         { "EpcmdDvld", 7, 1 },
8475         { "EpcmdFlush", 6, 1 },
8476         { "EpcmdTrimPrefix", 5, 1 },
8477         { "EpcmdTrimPostfix", 4, 1 },
8478         { "ERssIp4Pkt", 3, 1 },
8479         { "ERssIp6Pkt", 2, 1 },
8480         { "ERssTcpUdpPkt", 1, 1 },
8481         { "ERssFceFipPkt", 0, 1 },
8482         { NULL }
8483 };
8484
8485 static void
8486 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8487 {
8488
8489         field_desc_show(sb, *p, tp_la0);
8490 }
8491
8492 static void
8493 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8494 {
8495
8496         if (idx)
8497                 sbuf_printf(sb, "\n");
8498         field_desc_show(sb, p[0], tp_la0);
8499         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8500                 field_desc_show(sb, p[1], tp_la0);
8501 }
8502
8503 static void
8504 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8505 {
8506
8507         if (idx)
8508                 sbuf_printf(sb, "\n");
8509         field_desc_show(sb, p[0], tp_la0);
8510         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8511                 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8512 }
8513
8514 static int
8515 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8516 {
8517         struct adapter *sc = arg1;
8518         struct sbuf *sb;
8519         uint64_t *buf, *p;
8520         int rc;
8521         u_int i, inc;
8522         void (*show_func)(struct sbuf *, uint64_t *, int);
8523
8524         rc = sysctl_wire_old_buffer(req, 0);
8525         if (rc != 0)
8526                 return (rc);
8527
8528         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8529         if (sb == NULL)
8530                 return (ENOMEM);
8531
8532         buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8533
8534         t4_tp_read_la(sc, buf, NULL);
8535         p = buf;
8536
8537         switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8538         case 2:
8539                 inc = 2;
8540                 show_func = tp_la_show2;
8541                 break;
8542         case 3:
8543                 inc = 2;
8544                 show_func = tp_la_show3;
8545                 break;
8546         default:
8547                 inc = 1;
8548                 show_func = tp_la_show;
8549         }
8550
8551         for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8552                 (*show_func)(sb, p, i);
8553
8554         rc = sbuf_finish(sb);
8555         sbuf_delete(sb);
8556         free(buf, M_CXGBE);
8557         return (rc);
8558 }
8559
8560 static int
8561 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
8562 {
8563         struct adapter *sc = arg1;
8564         struct sbuf *sb;
8565         int rc;
8566         u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
8567
8568         rc = sysctl_wire_old_buffer(req, 0);
8569         if (rc != 0)
8570                 return (rc);
8571
8572         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8573         if (sb == NULL)
8574                 return (ENOMEM);
8575
8576         t4_get_chan_txrate(sc, nrate, orate);
8577
8578         if (sc->chip_params->nchan > 2) {
8579                 sbuf_printf(sb, "              channel 0   channel 1"
8580                     "   channel 2   channel 3\n");
8581                 sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
8582                     nrate[0], nrate[1], nrate[2], nrate[3]);
8583                 sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
8584                     orate[0], orate[1], orate[2], orate[3]);
8585         } else {
8586                 sbuf_printf(sb, "              channel 0   channel 1\n");
8587                 sbuf_printf(sb, "NIC B/s:     %10ju  %10ju\n",
8588                     nrate[0], nrate[1]);
8589                 sbuf_printf(sb, "Offload B/s: %10ju  %10ju",
8590                     orate[0], orate[1]);
8591         }
8592
8593         rc = sbuf_finish(sb);
8594         sbuf_delete(sb);
8595
8596         return (rc);
8597 }
8598
8599 static int
8600 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
8601 {
8602         struct adapter *sc = arg1;
8603         struct sbuf *sb;
8604         uint32_t *buf, *p;
8605         int rc, i;
8606
8607         rc = sysctl_wire_old_buffer(req, 0);
8608         if (rc != 0)
8609                 return (rc);
8610
8611         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8612         if (sb == NULL)
8613                 return (ENOMEM);
8614
8615         buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
8616             M_ZERO | M_WAITOK);
8617
8618         t4_ulprx_read_la(sc, buf);
8619         p = buf;
8620
8621         sbuf_printf(sb, "      Pcmd        Type   Message"
8622             "                Data");
8623         for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
8624                 sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
8625                     p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
8626         }
8627
8628         rc = sbuf_finish(sb);
8629         sbuf_delete(sb);
8630         free(buf, M_CXGBE);
8631         return (rc);
8632 }
8633
8634 static int
8635 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
8636 {
8637         struct adapter *sc = arg1;
8638         struct sbuf *sb;
8639         int rc, v;
8640
8641         MPASS(chip_id(sc) >= CHELSIO_T5);
8642
8643         rc = sysctl_wire_old_buffer(req, 0);
8644         if (rc != 0)
8645                 return (rc);
8646
8647         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8648         if (sb == NULL)
8649                 return (ENOMEM);
8650
8651         v = t4_read_reg(sc, A_SGE_STAT_CFG);
8652         if (G_STATSOURCE_T5(v) == 7) {
8653                 int mode;
8654
8655                 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
8656                 if (mode == 0) {
8657                         sbuf_printf(sb, "total %d, incomplete %d",
8658                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
8659                             t4_read_reg(sc, A_SGE_STAT_MATCH));
8660                 } else if (mode == 1) {
8661                         sbuf_printf(sb, "total %d, data overflow %d",
8662                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
8663                             t4_read_reg(sc, A_SGE_STAT_MATCH));
8664                 } else {
8665                         sbuf_printf(sb, "unknown mode %d", mode);
8666                 }
8667         }
8668         rc = sbuf_finish(sb);
8669         sbuf_delete(sb);
8670
8671         return (rc);
8672 }
8673
8674 static int
8675 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
8676 {
8677         struct adapter *sc = arg1;
8678         struct tx_cl_rl_params tc;
8679         struct sbuf *sb;
8680         int i, rc, port_id, mbps, gbps;
8681
8682         rc = sysctl_wire_old_buffer(req, 0);
8683         if (rc != 0)
8684                 return (rc);
8685
8686         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8687         if (sb == NULL)
8688                 return (ENOMEM);
8689
8690         port_id = arg2 >> 16;
8691         MPASS(port_id < sc->params.nports);
8692         MPASS(sc->port[port_id] != NULL);
8693         i = arg2 & 0xffff;
8694         MPASS(i < sc->chip_params->nsched_cls);
8695
8696         mtx_lock(&sc->tc_lock);
8697         tc = sc->port[port_id]->sched_params->cl_rl[i];
8698         mtx_unlock(&sc->tc_lock);
8699
8700         if (tc.flags & TX_CLRL_ERROR) {
8701                 sbuf_printf(sb, "error");
8702                 goto done;
8703         }
8704
8705         if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) {
8706                 /* XXX: top speed or actual link speed? */
8707                 gbps = port_top_speed(sc->port[port_id]);
8708                 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps);
8709         } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) {
8710                 switch (tc.rateunit) {
8711                 case SCHED_CLASS_RATEUNIT_BITS:
8712                         mbps = tc.maxrate / 1000;
8713                         gbps = tc.maxrate / 1000000;
8714                         if (tc.maxrate == gbps * 1000000)
8715                                 sbuf_printf(sb, " %uGbps", gbps);
8716                         else if (tc.maxrate == mbps * 1000)
8717                                 sbuf_printf(sb, " %uMbps", mbps);
8718                         else
8719                                 sbuf_printf(sb, " %uKbps", tc.maxrate);
8720                         break;
8721                 case SCHED_CLASS_RATEUNIT_PKTS:
8722                         sbuf_printf(sb, " %upps", tc.maxrate);
8723                         break;
8724                 default:
8725                         rc = ENXIO;
8726                         goto done;
8727                 }
8728         }
8729
8730         switch (tc.mode) {
8731         case SCHED_CLASS_MODE_CLASS:
8732                 sbuf_printf(sb, " aggregate");
8733                 break;
8734         case SCHED_CLASS_MODE_FLOW:
8735                 sbuf_printf(sb, " per-flow");
8736                 break;
8737         default:
8738                 rc = ENXIO;
8739                 goto done;
8740         }
8741
8742 done:
8743         if (rc == 0)
8744                 rc = sbuf_finish(sb);
8745         sbuf_delete(sb);
8746
8747         return (rc);
8748 }
8749 #endif
8750
8751 #ifdef TCP_OFFLOAD
8752 static int
8753 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
8754 {
8755         struct adapter *sc = arg1;
8756         int *old_ports, *new_ports;
8757         int i, new_count, rc;
8758
8759         if (req->newptr == NULL && req->oldptr == NULL)
8760                 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
8761                     sizeof(sc->tt.tls_rx_ports[0])));
8762
8763         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
8764         if (rc)
8765                 return (rc);
8766
8767         if (sc->tt.num_tls_rx_ports == 0) {
8768                 i = -1;
8769                 rc = SYSCTL_OUT(req, &i, sizeof(i));
8770         } else
8771                 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
8772                     sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
8773         if (rc == 0 && req->newptr != NULL) {
8774                 new_count = req->newlen / sizeof(new_ports[0]);
8775                 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
8776                     M_WAITOK);
8777                 rc = SYSCTL_IN(req, new_ports, new_count *
8778                     sizeof(new_ports[0]));
8779                 if (rc)
8780                         goto err;
8781
8782                 /* Allow setting to a single '-1' to clear the list. */
8783                 if (new_count == 1 && new_ports[0] == -1) {
8784                         ADAPTER_LOCK(sc);
8785                         old_ports = sc->tt.tls_rx_ports;
8786                         sc->tt.tls_rx_ports = NULL;
8787                         sc->tt.num_tls_rx_ports = 0;
8788                         ADAPTER_UNLOCK(sc);
8789                         free(old_ports, M_CXGBE);
8790                 } else {
8791                         for (i = 0; i < new_count; i++) {
8792                                 if (new_ports[i] < 1 ||
8793                                     new_ports[i] > IPPORT_MAX) {
8794                                         rc = EINVAL;
8795                                         goto err;
8796                                 }
8797                         }
8798
8799                         ADAPTER_LOCK(sc);
8800                         old_ports = sc->tt.tls_rx_ports;
8801                         sc->tt.tls_rx_ports = new_ports;
8802                         sc->tt.num_tls_rx_ports = new_count;
8803                         ADAPTER_UNLOCK(sc);
8804                         free(old_ports, M_CXGBE);
8805                         new_ports = NULL;
8806                 }
8807         err:
8808                 free(new_ports, M_CXGBE);
8809         }
8810         end_synchronized_op(sc, 0);
8811         return (rc);
8812 }
8813
8814 static void
8815 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8816 {
8817         u_int rem = val % factor;
8818
8819         if (rem == 0)
8820                 snprintf(buf, len, "%u", val / factor);
8821         else {
8822                 while (rem % 10 == 0)
8823                         rem /= 10;
8824                 snprintf(buf, len, "%u.%u", val / factor, rem);
8825         }
8826 }
8827
8828 static int
8829 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8830 {
8831         struct adapter *sc = arg1;
8832         char buf[16];
8833         u_int res, re;
8834         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8835
8836         res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8837         switch (arg2) {
8838         case 0:
8839                 /* timer_tick */
8840                 re = G_TIMERRESOLUTION(res);
8841                 break;
8842         case 1:
8843                 /* TCP timestamp tick */
8844                 re = G_TIMESTAMPRESOLUTION(res);
8845                 break;
8846         case 2:
8847                 /* DACK tick */
8848                 re = G_DELAYEDACKRESOLUTION(res);
8849                 break;
8850         default:
8851                 return (EDOOFUS);
8852         }
8853
8854         unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
8855
8856         return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
8857 }
8858
8859 static int
8860 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
8861 {
8862         struct adapter *sc = arg1;
8863         u_int res, dack_re, v;
8864         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8865
8866         res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8867         dack_re = G_DELAYEDACKRESOLUTION(res);
8868         v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
8869
8870         return (sysctl_handle_int(oidp, &v, 0, req));
8871 }
8872
8873 static int
8874 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
8875 {
8876         struct adapter *sc = arg1;
8877         int reg = arg2;
8878         u_int tre;
8879         u_long tp_tick_us, v;
8880         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8881
8882         MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
8883             reg == A_TP_PERS_MIN  || reg == A_TP_PERS_MAX ||
8884             reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
8885             reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
8886
8887         tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
8888         tp_tick_us = (cclk_ps << tre) / 1000000;
8889
8890         if (reg == A_TP_INIT_SRTT)
8891                 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
8892         else
8893                 v = tp_tick_us * t4_read_reg(sc, reg);
8894
8895         return (sysctl_handle_long(oidp, &v, 0, req));
8896 }
8897
8898 /*
8899  * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
8900  * passed to this function.
8901  */
8902 static int
8903 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
8904 {
8905         struct adapter *sc = arg1;
8906         int idx = arg2;
8907         u_int v;
8908
8909         MPASS(idx >= 0 && idx <= 24);
8910
8911         v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
8912
8913         return (sysctl_handle_int(oidp, &v, 0, req));
8914 }
8915
8916 static int
8917 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
8918 {
8919         struct adapter *sc = arg1;
8920         int idx = arg2;
8921         u_int shift, v, r;
8922
8923         MPASS(idx >= 0 && idx < 16);
8924
8925         r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
8926         shift = (idx & 3) << 3;
8927         v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
8928
8929         return (sysctl_handle_int(oidp, &v, 0, req));
8930 }
8931
8932 static int
8933 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
8934 {
8935         struct vi_info *vi = arg1;
8936         struct adapter *sc = vi->pi->adapter;
8937         int idx, rc, i;
8938         struct sge_ofld_rxq *ofld_rxq;
8939         uint8_t v;
8940
8941         idx = vi->ofld_tmr_idx;
8942
8943         rc = sysctl_handle_int(oidp, &idx, 0, req);
8944         if (rc != 0 || req->newptr == NULL)
8945                 return (rc);
8946
8947         if (idx < 0 || idx >= SGE_NTIMERS)
8948                 return (EINVAL);
8949
8950         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8951             "t4otmr");
8952         if (rc)
8953                 return (rc);
8954
8955         v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
8956         for_each_ofld_rxq(vi, i, ofld_rxq) {
8957 #ifdef atomic_store_rel_8
8958                 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
8959 #else
8960                 ofld_rxq->iq.intr_params = v;
8961 #endif
8962         }
8963         vi->ofld_tmr_idx = idx;
8964
8965         end_synchronized_op(sc, LOCK_HELD);
8966         return (0);
8967 }
8968
8969 static int
8970 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
8971 {
8972         struct vi_info *vi = arg1;
8973         struct adapter *sc = vi->pi->adapter;
8974         int idx, rc;
8975
8976         idx = vi->ofld_pktc_idx;
8977
8978         rc = sysctl_handle_int(oidp, &idx, 0, req);
8979         if (rc != 0 || req->newptr == NULL)
8980                 return (rc);
8981
8982         if (idx < -1 || idx >= SGE_NCOUNTERS)
8983                 return (EINVAL);
8984
8985         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8986             "t4opktc");
8987         if (rc)
8988                 return (rc);
8989
8990         if (vi->flags & VI_INIT_DONE)
8991                 rc = EBUSY; /* cannot be changed once the queues are created */
8992         else
8993                 vi->ofld_pktc_idx = idx;
8994
8995         end_synchronized_op(sc, LOCK_HELD);
8996         return (rc);
8997 }
8998 #endif
8999
9000 static uint32_t
9001 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
9002 {
9003         uint32_t mode;
9004
9005         mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
9006             T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
9007
9008         if (fconf & F_FRAGMENTATION)
9009                 mode |= T4_FILTER_IP_FRAGMENT;
9010
9011         if (fconf & F_MPSHITTYPE)
9012                 mode |= T4_FILTER_MPS_HIT_TYPE;
9013
9014         if (fconf & F_MACMATCH)
9015                 mode |= T4_FILTER_MAC_IDX;
9016
9017         if (fconf & F_ETHERTYPE)
9018                 mode |= T4_FILTER_ETH_TYPE;
9019
9020         if (fconf & F_PROTOCOL)
9021                 mode |= T4_FILTER_IP_PROTO;
9022
9023         if (fconf & F_TOS)
9024                 mode |= T4_FILTER_IP_TOS;
9025
9026         if (fconf & F_VLAN)
9027                 mode |= T4_FILTER_VLAN;
9028
9029         if (fconf & F_VNIC_ID) {
9030                 mode |= T4_FILTER_VNIC;
9031                 if (iconf & F_VNIC)
9032                         mode |= T4_FILTER_IC_VNIC;
9033         }
9034
9035         if (fconf & F_PORT)
9036                 mode |= T4_FILTER_PORT;
9037
9038         if (fconf & F_FCOE)
9039                 mode |= T4_FILTER_FCoE;
9040
9041         return (mode);
9042 }
9043
9044 static uint32_t
9045 mode_to_fconf(uint32_t mode)
9046 {
9047         uint32_t fconf = 0;
9048
9049         if (mode & T4_FILTER_IP_FRAGMENT)
9050                 fconf |= F_FRAGMENTATION;
9051
9052         if (mode & T4_FILTER_MPS_HIT_TYPE)
9053                 fconf |= F_MPSHITTYPE;
9054
9055         if (mode & T4_FILTER_MAC_IDX)
9056                 fconf |= F_MACMATCH;
9057
9058         if (mode & T4_FILTER_ETH_TYPE)
9059                 fconf |= F_ETHERTYPE;
9060
9061         if (mode & T4_FILTER_IP_PROTO)
9062                 fconf |= F_PROTOCOL;
9063
9064         if (mode & T4_FILTER_IP_TOS)
9065                 fconf |= F_TOS;
9066
9067         if (mode & T4_FILTER_VLAN)
9068                 fconf |= F_VLAN;
9069
9070         if (mode & T4_FILTER_VNIC)
9071                 fconf |= F_VNIC_ID;
9072
9073         if (mode & T4_FILTER_PORT)
9074                 fconf |= F_PORT;
9075
9076         if (mode & T4_FILTER_FCoE)
9077                 fconf |= F_FCOE;
9078
9079         return (fconf);
9080 }
9081
9082 static uint32_t
9083 mode_to_iconf(uint32_t mode)
9084 {
9085
9086         if (mode & T4_FILTER_IC_VNIC)
9087                 return (F_VNIC);
9088         return (0);
9089 }
9090
9091 static int check_fspec_against_fconf_iconf(struct adapter *sc,
9092     struct t4_filter_specification *fs)
9093 {
9094         struct tp_params *tpp = &sc->params.tp;
9095         uint32_t fconf = 0;
9096
9097         if (fs->val.frag || fs->mask.frag)
9098                 fconf |= F_FRAGMENTATION;
9099
9100         if (fs->val.matchtype || fs->mask.matchtype)
9101                 fconf |= F_MPSHITTYPE;
9102
9103         if (fs->val.macidx || fs->mask.macidx)
9104                 fconf |= F_MACMATCH;
9105
9106         if (fs->val.ethtype || fs->mask.ethtype)
9107                 fconf |= F_ETHERTYPE;
9108
9109         if (fs->val.proto || fs->mask.proto)
9110                 fconf |= F_PROTOCOL;
9111
9112         if (fs->val.tos || fs->mask.tos)
9113                 fconf |= F_TOS;
9114
9115         if (fs->val.vlan_vld || fs->mask.vlan_vld)
9116                 fconf |= F_VLAN;
9117
9118         if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
9119                 fconf |= F_VNIC_ID;
9120                 if (tpp->ingress_config & F_VNIC)
9121                         return (EINVAL);
9122         }
9123
9124         if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
9125                 fconf |= F_VNIC_ID;
9126                 if ((tpp->ingress_config & F_VNIC) == 0)
9127                         return (EINVAL);
9128         }
9129
9130         if (fs->val.iport || fs->mask.iport)
9131                 fconf |= F_PORT;
9132
9133         if (fs->val.fcoe || fs->mask.fcoe)
9134                 fconf |= F_FCOE;
9135
9136         if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
9137                 return (E2BIG);
9138
9139         return (0);
9140 }
9141
9142 static int
9143 get_filter_mode(struct adapter *sc, uint32_t *mode)
9144 {
9145         struct tp_params *tpp = &sc->params.tp;
9146
9147         /*
9148          * We trust the cached values of the relevant TP registers.  This means
9149          * things work reliably only if writes to those registers are always via
9150          * t4_set_filter_mode.
9151          */
9152         *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
9153
9154         return (0);
9155 }
9156
9157 static int
9158 set_filter_mode(struct adapter *sc, uint32_t mode)
9159 {
9160         struct tp_params *tpp = &sc->params.tp;
9161         uint32_t fconf, iconf;
9162         int rc;
9163
9164         iconf = mode_to_iconf(mode);
9165         if ((iconf ^ tpp->ingress_config) & F_VNIC) {
9166                 /*
9167                  * For now we just complain if A_TP_INGRESS_CONFIG is not
9168                  * already set to the correct value for the requested filter
9169                  * mode.  It's not clear if it's safe to write to this register
9170                  * on the fly.  (And we trust the cached value of the register).
9171                  */
9172                 return (EBUSY);
9173         }
9174
9175         fconf = mode_to_fconf(mode);
9176
9177         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
9178             "t4setfm");
9179         if (rc)
9180                 return (rc);
9181
9182         if (sc->tids.ftids_in_use > 0) {
9183                 rc = EBUSY;
9184                 goto done;
9185         }
9186
9187 #ifdef TCP_OFFLOAD
9188         if (uld_active(sc, ULD_TOM)) {
9189                 rc = EBUSY;
9190                 goto done;
9191         }
9192 #endif
9193
9194         rc = -t4_set_filter_mode(sc, fconf, true);
9195 done:
9196         end_synchronized_op(sc, LOCK_HELD);
9197         return (rc);
9198 }
9199
9200 static inline uint64_t
9201 get_filter_hits(struct adapter *sc, uint32_t fid)
9202 {
9203         uint32_t tcb_addr;
9204
9205         tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
9206             (fid + sc->tids.ftid_base) * TCB_SIZE;
9207
9208         if (is_t4(sc)) {
9209                 uint64_t hits;
9210
9211                 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
9212                 return (be64toh(hits));
9213         } else {
9214                 uint32_t hits;
9215
9216                 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
9217                 return (be32toh(hits));
9218         }
9219 }
9220
9221 static int
9222 get_filter(struct adapter *sc, struct t4_filter *t)
9223 {
9224         int i, rc, nfilters = sc->tids.nftids;
9225         struct filter_entry *f;
9226
9227         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
9228             "t4getf");
9229         if (rc)
9230                 return (rc);
9231
9232         if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
9233             t->idx >= nfilters) {
9234                 t->idx = 0xffffffff;
9235                 goto done;
9236         }
9237
9238         f = &sc->tids.ftid_tab[t->idx];
9239         for (i = t->idx; i < nfilters; i++, f++) {
9240                 if (f->valid) {
9241                         t->idx = i;
9242                         t->l2tidx = f->l2t ? f->l2t->idx : 0;
9243                         t->smtidx = f->smtidx;
9244                         if (f->fs.hitcnts)
9245                                 t->hits = get_filter_hits(sc, t->idx);
9246                         else
9247                                 t->hits = UINT64_MAX;
9248                         t->fs = f->fs;
9249
9250                         goto done;
9251                 }
9252         }
9253
9254         t->idx = 0xffffffff;
9255 done:
9256         end_synchronized_op(sc, LOCK_HELD);
9257         return (0);
9258 }
9259
9260 static int
9261 set_filter(struct adapter *sc, struct t4_filter *t)
9262 {
9263         unsigned int nfilters, nports;
9264         struct filter_entry *f;
9265         int i, rc;
9266
9267         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
9268         if (rc)
9269                 return (rc);
9270
9271         nfilters = sc->tids.nftids;
9272         nports = sc->params.nports;
9273
9274         if (nfilters == 0) {
9275                 rc = ENOTSUP;
9276                 goto done;
9277         }
9278
9279         if (t->idx >= nfilters) {
9280                 rc = EINVAL;
9281                 goto done;
9282         }
9283
9284         /* Validate against the global filter mode and ingress config */
9285         rc = check_fspec_against_fconf_iconf(sc, &t->fs);
9286         if (rc != 0)
9287                 goto done;
9288
9289         if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
9290                 rc = EINVAL;
9291                 goto done;
9292         }
9293
9294         if (t->fs.val.iport >= nports) {
9295                 rc = EINVAL;
9296                 goto done;
9297         }
9298
9299         /* Can't specify an iq if not steering to it */
9300         if (!t->fs.dirsteer && t->fs.iq) {
9301                 rc = EINVAL;
9302                 goto done;
9303         }
9304
9305         /* IPv6 filter idx must be 4 aligned */
9306         if (t->fs.type == 1 &&
9307             ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
9308                 rc = EINVAL;
9309                 goto done;
9310         }
9311
9312         if (!(sc->flags & FULL_INIT_DONE) &&
9313             ((rc = adapter_full_init(sc)) != 0))
9314                 goto done;
9315
9316         if (sc->tids.ftid_tab == NULL) {
9317                 KASSERT(sc->tids.ftids_in_use == 0,
9318                     ("%s: no memory allocated but filters_in_use > 0",
9319                     __func__));
9320
9321                 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
9322                     nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
9323                 if (sc->tids.ftid_tab == NULL) {
9324                         rc = ENOMEM;
9325                         goto done;
9326                 }
9327                 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
9328         }
9329
9330         for (i = 0; i < 4; i++) {
9331                 f = &sc->tids.ftid_tab[t->idx + i];
9332
9333                 if (f->pending || f->valid) {
9334                         rc = EBUSY;
9335                         goto done;
9336                 }
9337                 if (f->locked) {
9338                         rc = EPERM;
9339                         goto done;
9340                 }
9341
9342                 if (t->fs.type == 0)
9343                         break;
9344         }
9345
9346         f = &sc->tids.ftid_tab[t->idx];
9347         f->fs = t->fs;
9348
9349         rc = set_filter_wr(sc, t->idx);
9350 done:
9351         end_synchronized_op(sc, 0);
9352
9353         if (rc == 0) {
9354                 mtx_lock(&sc->tids.ftid_lock);
9355                 for (;;) {
9356                         if (f->pending == 0) {
9357                                 rc = f->valid ? 0 : EIO;
9358                                 break;
9359                         }
9360
9361                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
9362                             PCATCH, "t4setfw", 0)) {
9363                                 rc = EINPROGRESS;
9364                                 break;
9365                         }
9366                 }
9367                 mtx_unlock(&sc->tids.ftid_lock);
9368         }
9369         return (rc);
9370 }
9371
9372 static int
9373 del_filter(struct adapter *sc, struct t4_filter *t)
9374 {
9375         unsigned int nfilters;
9376         struct filter_entry *f;
9377         int rc;
9378
9379         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
9380         if (rc)
9381                 return (rc);
9382
9383         nfilters = sc->tids.nftids;
9384
9385         if (nfilters == 0) {
9386                 rc = ENOTSUP;
9387                 goto done;
9388         }
9389
9390         if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
9391             t->idx >= nfilters) {
9392                 rc = EINVAL;
9393                 goto done;
9394         }
9395
9396         if (!(sc->flags & FULL_INIT_DONE)) {
9397                 rc = EAGAIN;
9398                 goto done;
9399         }
9400
9401         f = &sc->tids.ftid_tab[t->idx];
9402
9403         if (f->pending) {
9404                 rc = EBUSY;
9405                 goto done;
9406         }
9407         if (f->locked) {
9408                 rc = EPERM;
9409                 goto done;
9410         }
9411
9412         if (f->valid) {
9413                 t->fs = f->fs;  /* extra info for the caller */
9414                 rc = del_filter_wr(sc, t->idx);
9415         }
9416
9417 done:
9418         end_synchronized_op(sc, 0);
9419
9420         if (rc == 0) {
9421                 mtx_lock(&sc->tids.ftid_lock);
9422                 for (;;) {
9423                         if (f->pending == 0) {
9424                                 rc = f->valid ? EIO : 0;
9425                                 break;
9426                         }
9427
9428                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
9429                             PCATCH, "t4delfw", 0)) {
9430                                 rc = EINPROGRESS;
9431                                 break;
9432                         }
9433                 }
9434                 mtx_unlock(&sc->tids.ftid_lock);
9435         }
9436
9437         return (rc);
9438 }
9439
9440 static void
9441 clear_filter(struct filter_entry *f)
9442 {
9443         if (f->l2t)
9444                 t4_l2t_release(f->l2t);
9445
9446         bzero(f, sizeof (*f));
9447 }
9448
9449 static int
9450 set_filter_wr(struct adapter *sc, int fidx)
9451 {
9452         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
9453         struct fw_filter_wr *fwr;
9454         unsigned int ftid, vnic_vld, vnic_vld_mask;
9455         struct wrq_cookie cookie;
9456
9457         ASSERT_SYNCHRONIZED_OP(sc);
9458
9459         if (f->fs.newdmac || f->fs.newvlan) {
9460                 /* This filter needs an L2T entry; allocate one. */
9461                 f->l2t = t4_l2t_alloc_switching(sc->l2t);
9462                 if (f->l2t == NULL)
9463                         return (EAGAIN);
9464                 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
9465                     f->fs.dmac)) {
9466                         t4_l2t_release(f->l2t);
9467                         f->l2t = NULL;
9468                         return (ENOMEM);
9469                 }
9470         }
9471
9472         /* Already validated against fconf, iconf */
9473         MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
9474         MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
9475         if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
9476                 vnic_vld = 1;
9477         else
9478                 vnic_vld = 0;
9479         if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
9480                 vnic_vld_mask = 1;
9481         else
9482                 vnic_vld_mask = 0;
9483
9484         ftid = sc->tids.ftid_base + fidx;
9485
9486         fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
9487         if (fwr == NULL)
9488                 return (ENOMEM);
9489         bzero(fwr, sizeof(*fwr));
9490
9491         fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
9492         fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
9493         fwr->tid_to_iq =
9494             htobe32(V_FW_FILTER_WR_TID(ftid) |
9495                 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
9496                 V_FW_FILTER_WR_NOREPLY(0) |
9497                 V_FW_FILTER_WR_IQ(f->fs.iq));
9498         fwr->del_filter_to_l2tix =
9499             htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
9500                 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
9501                 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
9502                 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
9503                 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
9504                 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
9505                 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
9506                 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
9507                 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
9508                     f->fs.newvlan == VLAN_REWRITE) |
9509                 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
9510                     f->fs.newvlan == VLAN_REWRITE) |
9511                 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
9512                 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
9513                 V_FW_FILTER_WR_PRIO(f->fs.prio) |
9514                 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
9515         fwr->ethtype = htobe16(f->fs.val.ethtype);
9516         fwr->ethtypem = htobe16(f->fs.mask.ethtype);
9517         fwr->frag_to_ovlan_vldm =
9518             (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
9519                 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
9520                 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
9521                 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
9522                 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
9523                 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
9524         fwr->smac_sel = 0;
9525         fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
9526             V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
9527         fwr->maci_to_matchtypem =
9528             htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
9529                 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
9530                 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
9531                 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
9532                 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
9533                 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
9534                 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
9535                 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
9536         fwr->ptcl = f->fs.val.proto;
9537         fwr->ptclm = f->fs.mask.proto;
9538         fwr->ttyp = f->fs.val.tos;
9539         fwr->ttypm = f->fs.mask.tos;
9540         fwr->ivlan = htobe16(f->fs.val.vlan);
9541         fwr->ivlanm = htobe16(f->fs.mask.vlan);
9542         fwr->ovlan = htobe16(f->fs.val.vnic);
9543         fwr->ovlanm = htobe16(f->fs.mask.vnic);
9544         bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
9545         bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
9546         bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
9547         bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
9548         fwr->lp = htobe16(f->fs.val.dport);
9549         fwr->lpm = htobe16(f->fs.mask.dport);
9550         fwr->fp = htobe16(f->fs.val.sport);
9551         fwr->fpm = htobe16(f->fs.mask.sport);
9552         if (f->fs.newsmac)
9553                 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
9554
9555         f->pending = 1;
9556         sc->tids.ftids_in_use++;
9557
9558         commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
9559         return (0);
9560 }
9561
9562 static int
9563 del_filter_wr(struct adapter *sc, int fidx)
9564 {
9565         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
9566         struct fw_filter_wr *fwr;
9567         unsigned int ftid;
9568         struct wrq_cookie cookie;
9569
9570         ftid = sc->tids.ftid_base + fidx;
9571
9572         fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
9573         if (fwr == NULL)
9574                 return (ENOMEM);
9575         bzero(fwr, sizeof (*fwr));
9576
9577         t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
9578
9579         f->pending = 1;
9580         commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
9581         return (0);
9582 }
9583
9584 int
9585 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9586 {
9587         struct adapter *sc = iq->adapter;
9588         const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
9589         unsigned int idx = GET_TID(rpl);
9590         unsigned int rc;
9591         struct filter_entry *f;
9592
9593         KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
9594             rss->opcode));
9595         MPASS(iq == &sc->sge.fwq);
9596         MPASS(is_ftid(sc, idx));
9597
9598         idx -= sc->tids.ftid_base;
9599         f = &sc->tids.ftid_tab[idx];
9600         rc = G_COOKIE(rpl->cookie);
9601
9602         mtx_lock(&sc->tids.ftid_lock);
9603         if (rc == FW_FILTER_WR_FLT_ADDED) {
9604                 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
9605                     __func__, idx));
9606                 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
9607                 f->pending = 0;  /* asynchronous setup completed */
9608                 f->valid = 1;
9609         } else {
9610                 if (rc != FW_FILTER_WR_FLT_DELETED) {
9611                         /* Add or delete failed, display an error */
9612                         log(LOG_ERR,
9613                             "filter %u setup failed with error %u\n",
9614                             idx, rc);
9615                 }
9616
9617                 clear_filter(f);
9618                 sc->tids.ftids_in_use--;
9619         }
9620         wakeup(&sc->tids.ftid_tab);
9621         mtx_unlock(&sc->tids.ftid_lock);
9622
9623         return (0);
9624 }
9625
9626 static int
9627 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9628 {
9629
9630         MPASS(iq->set_tcb_rpl != NULL);
9631         return (iq->set_tcb_rpl(iq, rss, m));
9632 }
9633
9634 static int
9635 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9636 {
9637
9638         MPASS(iq->l2t_write_rpl != NULL);
9639         return (iq->l2t_write_rpl(iq, rss, m));
9640 }
9641
9642 static int
9643 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9644 {
9645         int rc;
9646
9647         if (cntxt->cid > M_CTXTQID)
9648                 return (EINVAL);
9649
9650         if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9651             cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9652                 return (EINVAL);
9653
9654         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9655         if (rc)
9656                 return (rc);
9657
9658         if (sc->flags & FW_OK) {
9659                 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9660                     &cntxt->data[0]);
9661                 if (rc == 0)
9662                         goto done;
9663         }
9664
9665         /*
9666          * Read via firmware failed or wasn't even attempted.  Read directly via
9667          * the backdoor.
9668          */
9669         rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9670 done:
9671         end_synchronized_op(sc, 0);
9672         return (rc);
9673 }
9674
9675 static int
9676 load_fw(struct adapter *sc, struct t4_data *fw)
9677 {
9678         int rc;
9679         uint8_t *fw_data;
9680
9681         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9682         if (rc)
9683                 return (rc);
9684
9685         /*
9686          * The firmware, with the sole exception of the memory parity error
9687          * handler, runs from memory and not flash.  It is almost always safe to
9688          * install a new firmware on a running system.  Just set bit 1 in
9689          * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9690          */
9691         if (sc->flags & FULL_INIT_DONE &&
9692             (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9693                 rc = EBUSY;
9694                 goto done;
9695         }
9696
9697         fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9698         if (fw_data == NULL) {
9699                 rc = ENOMEM;
9700                 goto done;
9701         }
9702
9703         rc = copyin(fw->data, fw_data, fw->len);
9704         if (rc == 0)
9705                 rc = -t4_load_fw(sc, fw_data, fw->len);
9706
9707         free(fw_data, M_CXGBE);
9708 done:
9709         end_synchronized_op(sc, 0);
9710         return (rc);
9711 }
9712
9713 static int
9714 load_cfg(struct adapter *sc, struct t4_data *cfg)
9715 {
9716         int rc;
9717         uint8_t *cfg_data = NULL;
9718
9719         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9720         if (rc)
9721                 return (rc);
9722
9723         if (cfg->len == 0) {
9724                 /* clear */
9725                 rc = -t4_load_cfg(sc, NULL, 0);
9726                 goto done;
9727         }
9728
9729         cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9730         if (cfg_data == NULL) {
9731                 rc = ENOMEM;
9732                 goto done;
9733         }
9734
9735         rc = copyin(cfg->data, cfg_data, cfg->len);
9736         if (rc == 0)
9737                 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9738
9739         free(cfg_data, M_CXGBE);
9740 done:
9741         end_synchronized_op(sc, 0);
9742         return (rc);
9743 }
9744
9745 static int
9746 load_boot(struct adapter *sc, struct t4_bootrom *br)
9747 {
9748         int rc;
9749         uint8_t *br_data = NULL;
9750         u_int offset;
9751
9752         if (br->len > 1024 * 1024)
9753                 return (EFBIG);
9754
9755         if (br->pf_offset == 0) {
9756                 /* pfidx */
9757                 if (br->pfidx_addr > 7)
9758                         return (EINVAL);
9759                 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9760                     A_PCIE_PF_EXPROM_OFST)));
9761         } else if (br->pf_offset == 1) {
9762                 /* offset */
9763                 offset = G_OFFSET(br->pfidx_addr);
9764         } else {
9765                 return (EINVAL);
9766         }
9767
9768         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9769         if (rc)
9770                 return (rc);
9771
9772         if (br->len == 0) {
9773                 /* clear */
9774                 rc = -t4_load_boot(sc, NULL, offset, 0);
9775                 goto done;
9776         }
9777
9778         br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9779         if (br_data == NULL) {
9780                 rc = ENOMEM;
9781                 goto done;
9782         }
9783
9784         rc = copyin(br->data, br_data, br->len);
9785         if (rc == 0)
9786                 rc = -t4_load_boot(sc, br_data, offset, br->len);
9787
9788         free(br_data, M_CXGBE);
9789 done:
9790         end_synchronized_op(sc, 0);
9791         return (rc);
9792 }
9793
9794 static int
9795 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9796 {
9797         int rc;
9798         uint8_t *bc_data = NULL;
9799
9800         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9801         if (rc)
9802                 return (rc);
9803
9804         if (bc->len == 0) {
9805                 /* clear */
9806                 rc = -t4_load_bootcfg(sc, NULL, 0);
9807                 goto done;
9808         }
9809
9810         bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9811         if (bc_data == NULL) {
9812                 rc = ENOMEM;
9813                 goto done;
9814         }
9815
9816         rc = copyin(bc->data, bc_data, bc->len);
9817         if (rc == 0)
9818                 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9819
9820         free(bc_data, M_CXGBE);
9821 done:
9822         end_synchronized_op(sc, 0);
9823         return (rc);
9824 }
9825
9826 static int
9827 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9828 {
9829         int rc;
9830         struct cudbg_init *cudbg;
9831         void *handle, *buf;
9832
9833         /* buf is large, don't block if no memory is available */
9834         buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9835         if (buf == NULL)
9836                 return (ENOMEM);
9837
9838         handle = cudbg_alloc_handle();
9839         if (handle == NULL) {
9840                 rc = ENOMEM;
9841                 goto done;
9842         }
9843
9844         cudbg = cudbg_get_init(handle);
9845         cudbg->adap = sc;
9846         cudbg->print = (cudbg_print_cb)printf;
9847
9848 #ifndef notyet
9849         device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9850             __func__, dump->wr_flash, dump->len, dump->data);
9851 #endif
9852
9853         if (dump->wr_flash)
9854                 cudbg->use_flash = 1;
9855         MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9856         memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9857
9858         rc = cudbg_collect(handle, buf, &dump->len);
9859         if (rc != 0)
9860                 goto done;
9861
9862         rc = copyout(buf, dump->data, dump->len);
9863 done:
9864         cudbg_free_handle(handle);
9865         free(buf, M_CXGBE);
9866         return (rc);
9867 }
9868
9869 static void
9870 free_offload_policy(struct t4_offload_policy *op)
9871 {
9872         struct offload_rule *r;
9873         int i;
9874
9875         if (op == NULL)
9876                 return;
9877
9878         r = &op->rule[0];
9879         for (i = 0; i < op->nrules; i++, r++) {
9880                 free(r->bpf_prog.bf_insns, M_CXGBE);
9881         }
9882         free(op->rule, M_CXGBE);
9883         free(op, M_CXGBE);
9884 }
9885
9886 static int
9887 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9888 {
9889         int i, rc, len;
9890         struct t4_offload_policy *op, *old;
9891         struct bpf_program *bf;
9892         const struct offload_settings *s;
9893         struct offload_rule *r;
9894         void *u;
9895
9896         if (!is_offload(sc))
9897                 return (ENODEV);
9898
9899         if (uop->nrules == 0) {
9900                 /* Delete installed policies. */
9901                 op = NULL;
9902                 goto set_policy;
9903         } if (uop->nrules > 256) { /* arbitrary */
9904                 return (E2BIG);
9905         }
9906
9907         /* Copy userspace offload policy to kernel */
9908         op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9909         op->nrules = uop->nrules;
9910         len = op->nrules * sizeof(struct offload_rule);
9911         op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9912         rc = copyin(uop->rule, op->rule, len);
9913         if (rc) {
9914                 free(op->rule, M_CXGBE);
9915                 free(op, M_CXGBE);
9916                 return (rc);
9917         }
9918
9919         r = &op->rule[0];
9920         for (i = 0; i < op->nrules; i++, r++) {
9921
9922                 /* Validate open_type */
9923                 if (r->open_type != OPEN_TYPE_LISTEN &&
9924                     r->open_type != OPEN_TYPE_ACTIVE &&
9925                     r->open_type != OPEN_TYPE_PASSIVE &&
9926                     r->open_type != OPEN_TYPE_DONTCARE) {
9927 error:
9928                         /*
9929                          * Rules 0 to i have malloc'd filters that need to be
9930                          * freed.  Rules i+1 to nrules have userspace pointers
9931                          * and should be left alone.
9932                          */
9933                         op->nrules = i;
9934                         free_offload_policy(op);
9935                         return (rc);
9936                 }
9937
9938                 /* Validate settings */
9939                 s = &r->settings;
9940                 if ((s->offload != 0 && s->offload != 1) ||
9941                     s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9942                     s->sched_class < -1 ||
9943                     s->sched_class >= sc->chip_params->nsched_cls) {
9944                         rc = EINVAL;
9945                         goto error;
9946                 }
9947
9948                 bf = &r->bpf_prog;
9949                 u = bf->bf_insns;       /* userspace ptr */
9950                 bf->bf_insns = NULL;
9951                 if (bf->bf_len == 0) {
9952                         /* legal, matches everything */
9953                         continue;
9954                 }
9955                 len = bf->bf_len * sizeof(*bf->bf_insns);
9956                 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9957                 rc = copyin(u, bf->bf_insns, len);
9958                 if (rc != 0)
9959                         goto error;
9960
9961                 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9962                         rc = EINVAL;
9963                         goto error;
9964                 }
9965         }
9966 set_policy:
9967         rw_wlock(&sc->policy_lock);
9968         old = sc->policy;
9969         sc->policy = op;
9970         rw_wunlock(&sc->policy_lock);
9971         free_offload_policy(old);
9972
9973         return (0);
9974 }
9975
9976 #define MAX_READ_BUF_SIZE (128 * 1024)
9977 static int
9978 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9979 {
9980         uint32_t addr, remaining, n;
9981         uint32_t *buf;
9982         int rc;
9983         uint8_t *dst;
9984
9985         rc = validate_mem_range(sc, mr->addr, mr->len);
9986         if (rc != 0)
9987                 return (rc);
9988
9989         buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9990         addr = mr->addr;
9991         remaining = mr->len;
9992         dst = (void *)mr->data;
9993
9994         while (remaining) {
9995                 n = min(remaining, MAX_READ_BUF_SIZE);
9996                 read_via_memwin(sc, 2, addr, buf, n);
9997
9998                 rc = copyout(buf, dst, n);
9999                 if (rc != 0)
10000                         break;
10001
10002                 dst += n;
10003                 remaining -= n;
10004                 addr += n;
10005         }
10006
10007         free(buf, M_CXGBE);
10008         return (rc);
10009 }
10010 #undef MAX_READ_BUF_SIZE
10011
10012 static int
10013 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
10014 {
10015         int rc;
10016
10017         if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
10018                 return (EINVAL);
10019
10020         if (i2cd->len > sizeof(i2cd->data))
10021                 return (EFBIG);
10022
10023         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
10024         if (rc)
10025                 return (rc);
10026         rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
10027             i2cd->offset, i2cd->len, &i2cd->data[0]);
10028         end_synchronized_op(sc, 0);
10029
10030         return (rc);
10031 }
10032
10033 int
10034 t4_os_find_pci_capability(struct adapter *sc, int cap)
10035 {
10036         int i;
10037
10038         return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
10039 }
10040
10041 int
10042 t4_os_pci_save_state(struct adapter *sc)
10043 {
10044         device_t dev;
10045         struct pci_devinfo *dinfo;
10046
10047         dev = sc->dev;
10048         dinfo = device_get_ivars(dev);
10049
10050         pci_cfg_save(dev, dinfo, 0);
10051         return (0);
10052 }
10053
10054 int
10055 t4_os_pci_restore_state(struct adapter *sc)
10056 {
10057         device_t dev;
10058         struct pci_devinfo *dinfo;
10059
10060         dev = sc->dev;
10061         dinfo = device_get_ivars(dev);
10062
10063         pci_cfg_restore(dev, dinfo);
10064         return (0);
10065 }
10066
10067 void
10068 t4_os_portmod_changed(struct port_info *pi)
10069 {
10070         struct adapter *sc = pi->adapter;
10071         struct vi_info *vi;
10072         struct ifnet *ifp;
10073         static const char *mod_str[] = {
10074                 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
10075         };
10076
10077         KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
10078             ("%s: port_type %u", __func__, pi->port_type));
10079
10080         vi = &pi->vi[0];
10081         if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
10082                 PORT_LOCK(pi);
10083                 build_medialist(pi);
10084                 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
10085                         fixup_link_config(pi);
10086                         apply_link_config(pi);
10087                 }
10088                 PORT_UNLOCK(pi);
10089                 end_synchronized_op(sc, LOCK_HELD);
10090         }
10091
10092         ifp = vi->ifp;
10093         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
10094                 if_printf(ifp, "transceiver unplugged.\n");
10095         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
10096                 if_printf(ifp, "unknown transceiver inserted.\n");
10097         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
10098                 if_printf(ifp, "unsupported transceiver inserted.\n");
10099         else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
10100                 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
10101                     port_top_speed(pi), mod_str[pi->mod_type]);
10102         } else {
10103                 if_printf(ifp, "transceiver (type %d) inserted.\n",
10104                     pi->mod_type);
10105         }
10106 }
10107
10108 void
10109 t4_os_link_changed(struct port_info *pi)
10110 {
10111         struct vi_info *vi;
10112         struct ifnet *ifp;
10113         struct link_config *lc;
10114         int v;
10115
10116         PORT_LOCK_ASSERT_OWNED(pi);
10117
10118         for_each_vi(pi, v, vi) {
10119                 ifp = vi->ifp;
10120                 if (ifp == NULL)
10121                         continue;
10122
10123                 lc = &pi->link_cfg;
10124                 if (lc->link_ok) {
10125                         ifp->if_baudrate = IF_Mbps(lc->speed);
10126                         if_link_state_change(ifp, LINK_STATE_UP);
10127                 } else {
10128                         if_link_state_change(ifp, LINK_STATE_DOWN);
10129                 }
10130         }
10131 }
10132
10133 void
10134 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
10135 {
10136         struct adapter *sc;
10137
10138         sx_slock(&t4_list_lock);
10139         SLIST_FOREACH(sc, &t4_list, link) {
10140                 /*
10141                  * func should not make any assumptions about what state sc is
10142                  * in - the only guarantee is that sc->sc_lock is a valid lock.
10143                  */
10144                 func(sc, arg);
10145         }
10146         sx_sunlock(&t4_list_lock);
10147 }
10148
10149 static int
10150 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
10151     struct thread *td)
10152 {
10153         int rc;
10154         struct adapter *sc = dev->si_drv1;
10155
10156         rc = priv_check(td, PRIV_DRIVER);
10157         if (rc != 0)
10158                 return (rc);
10159
10160         switch (cmd) {
10161         case CHELSIO_T4_GETREG: {
10162                 struct t4_reg *edata = (struct t4_reg *)data;
10163
10164                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10165                         return (EFAULT);
10166
10167                 if (edata->size == 4)
10168                         edata->val = t4_read_reg(sc, edata->addr);
10169                 else if (edata->size == 8)
10170                         edata->val = t4_read_reg64(sc, edata->addr);
10171                 else
10172                         return (EINVAL);
10173
10174                 break;
10175         }
10176         case CHELSIO_T4_SETREG: {
10177                 struct t4_reg *edata = (struct t4_reg *)data;
10178
10179                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10180                         return (EFAULT);
10181
10182                 if (edata->size == 4) {
10183                         if (edata->val & 0xffffffff00000000)
10184                                 return (EINVAL);
10185                         t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
10186                 } else if (edata->size == 8)
10187                         t4_write_reg64(sc, edata->addr, edata->val);
10188                 else
10189                         return (EINVAL);
10190                 break;
10191         }
10192         case CHELSIO_T4_REGDUMP: {
10193                 struct t4_regdump *regs = (struct t4_regdump *)data;
10194                 int reglen = t4_get_regs_len(sc);
10195                 uint8_t *buf;
10196
10197                 if (regs->len < reglen) {
10198                         regs->len = reglen; /* hint to the caller */
10199                         return (ENOBUFS);
10200                 }
10201
10202                 regs->len = reglen;
10203                 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
10204                 get_regs(sc, regs, buf);
10205                 rc = copyout(buf, regs->data, reglen);
10206                 free(buf, M_CXGBE);
10207                 break;
10208         }
10209         case CHELSIO_T4_GET_FILTER_MODE:
10210                 rc = get_filter_mode(sc, (uint32_t *)data);
10211                 break;
10212         case CHELSIO_T4_SET_FILTER_MODE:
10213                 rc = set_filter_mode(sc, *(uint32_t *)data);
10214                 break;
10215         case CHELSIO_T4_GET_FILTER:
10216                 rc = get_filter(sc, (struct t4_filter *)data);
10217                 break;
10218         case CHELSIO_T4_SET_FILTER:
10219                 rc = set_filter(sc, (struct t4_filter *)data);
10220                 break;
10221         case CHELSIO_T4_DEL_FILTER:
10222                 rc = del_filter(sc, (struct t4_filter *)data);
10223                 break;
10224         case CHELSIO_T4_GET_SGE_CONTEXT:
10225                 rc = get_sge_context(sc, (struct t4_sge_context *)data);
10226                 break;
10227         case CHELSIO_T4_LOAD_FW:
10228                 rc = load_fw(sc, (struct t4_data *)data);
10229                 break;
10230         case CHELSIO_T4_GET_MEM:
10231                 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
10232                 break;
10233         case CHELSIO_T4_GET_I2C:
10234                 rc = read_i2c(sc, (struct t4_i2c_data *)data);
10235                 break;
10236         case CHELSIO_T4_CLEAR_STATS: {
10237                 int i, v, bg_map;
10238                 u_int port_id = *(uint32_t *)data;
10239                 struct port_info *pi;
10240                 struct vi_info *vi;
10241
10242                 if (port_id >= sc->params.nports)
10243                         return (EINVAL);
10244                 pi = sc->port[port_id];
10245                 if (pi == NULL)
10246                         return (EIO);
10247
10248                 /* MAC stats */
10249                 t4_clr_port_stats(sc, pi->tx_chan);
10250                 pi->tx_parse_error = 0;
10251                 pi->tnl_cong_drops = 0;
10252                 mtx_lock(&sc->reg_lock);
10253                 for_each_vi(pi, v, vi) {
10254                         if (vi->flags & VI_INIT_DONE)
10255                                 t4_clr_vi_stats(sc, vi->viid);
10256                 }
10257                 bg_map = pi->mps_bg_map;
10258                 v = 0;  /* reuse */
10259                 while (bg_map) {
10260                         i = ffs(bg_map) - 1;
10261                         t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10262                             1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10263                         bg_map &= ~(1 << i);
10264                 }
10265                 mtx_unlock(&sc->reg_lock);
10266
10267                 /*
10268                  * Since this command accepts a port, clear stats for
10269                  * all VIs on this port.
10270                  */
10271                 for_each_vi(pi, v, vi) {
10272                         if (vi->flags & VI_INIT_DONE) {
10273                                 struct sge_rxq *rxq;
10274                                 struct sge_txq *txq;
10275                                 struct sge_wrq *wrq;
10276
10277                                 for_each_rxq(vi, i, rxq) {
10278 #if defined(INET) || defined(INET6)
10279                                         rxq->lro.lro_queued = 0;
10280                                         rxq->lro.lro_flushed = 0;
10281 #endif
10282                                         rxq->rxcsum = 0;
10283                                         rxq->vlan_extraction = 0;
10284                                 }
10285
10286                                 for_each_txq(vi, i, txq) {
10287                                         txq->txcsum = 0;
10288                                         txq->tso_wrs = 0;
10289                                         txq->vlan_insertion = 0;
10290                                         txq->imm_wrs = 0;
10291                                         txq->sgl_wrs = 0;
10292                                         txq->txpkt_wrs = 0;
10293                                         txq->txpkts0_wrs = 0;
10294                                         txq->txpkts1_wrs = 0;
10295                                         txq->txpkts0_pkts = 0;
10296                                         txq->txpkts1_pkts = 0;
10297                                         mp_ring_reset_stats(txq->r);
10298                                 }
10299
10300 #ifdef TCP_OFFLOAD
10301                                 /* nothing to clear for each ofld_rxq */
10302
10303                                 for_each_ofld_txq(vi, i, wrq) {
10304                                         wrq->tx_wrs_direct = 0;
10305                                         wrq->tx_wrs_copied = 0;
10306                                 }
10307 #endif
10308
10309                                 if (IS_MAIN_VI(vi)) {
10310                                         wrq = &sc->sge.ctrlq[pi->port_id];
10311                                         wrq->tx_wrs_direct = 0;
10312                                         wrq->tx_wrs_copied = 0;
10313                                 }
10314                         }
10315                 }
10316                 break;
10317         }
10318         case CHELSIO_T4_SCHED_CLASS:
10319                 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10320                 break;
10321         case CHELSIO_T4_SCHED_QUEUE:
10322                 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10323                 break;
10324         case CHELSIO_T4_GET_TRACER:
10325                 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10326                 break;
10327         case CHELSIO_T4_SET_TRACER:
10328                 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10329                 break;
10330         case CHELSIO_T4_LOAD_CFG:
10331                 rc = load_cfg(sc, (struct t4_data *)data);
10332                 break;
10333         case CHELSIO_T4_LOAD_BOOT:
10334                 rc = load_boot(sc, (struct t4_bootrom *)data);
10335                 break;
10336         case CHELSIO_T4_LOAD_BOOTCFG:
10337                 rc = load_bootcfg(sc, (struct t4_data *)data);
10338                 break;
10339         case CHELSIO_T4_CUDBG_DUMP:
10340                 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10341                 break;
10342         case CHELSIO_T4_SET_OFLD_POLICY:
10343                 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10344                 break;
10345         default:
10346                 rc = ENOTTY;
10347         }
10348
10349         return (rc);
10350 }
10351
10352 void
10353 t4_db_full(struct adapter *sc)
10354 {
10355
10356         CXGBE_UNIMPLEMENTED(__func__);
10357 }
10358
10359 void
10360 t4_db_dropped(struct adapter *sc)
10361 {
10362
10363         CXGBE_UNIMPLEMENTED(__func__);
10364 }
10365
10366 #ifdef TCP_OFFLOAD
10367 void
10368 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
10369 {
10370
10371         t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
10372         t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
10373                 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
10374                 V_HPZ3(pgsz_order[3]));
10375 }
10376
10377 static int
10378 toe_capability(struct vi_info *vi, int enable)
10379 {
10380         int rc;
10381         struct port_info *pi = vi->pi;
10382         struct adapter *sc = pi->adapter;
10383
10384         ASSERT_SYNCHRONIZED_OP(sc);
10385
10386         if (!is_offload(sc))
10387                 return (ENODEV);
10388
10389         if (enable) {
10390                 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10391                         /* TOE is already enabled. */
10392                         return (0);
10393                 }
10394
10395                 /*
10396                  * We need the port's queues around so that we're able to send
10397                  * and receive CPLs to/from the TOE even if the ifnet for this
10398                  * port has never been UP'd administratively.
10399                  */
10400                 if (!(vi->flags & VI_INIT_DONE)) {
10401                         rc = vi_full_init(vi);
10402                         if (rc)
10403                                 return (rc);
10404                 }
10405                 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10406                         rc = vi_full_init(&pi->vi[0]);
10407                         if (rc)
10408                                 return (rc);
10409                 }
10410
10411                 if (isset(&sc->offload_map, pi->port_id)) {
10412                         /* TOE is enabled on another VI of this port. */
10413                         pi->uld_vis++;
10414                         return (0);
10415                 }
10416
10417                 if (!uld_active(sc, ULD_TOM)) {
10418                         rc = t4_activate_uld(sc, ULD_TOM);
10419                         if (rc == EAGAIN) {
10420                                 log(LOG_WARNING,
10421                                     "You must kldload t4_tom.ko before trying "
10422                                     "to enable TOE on a cxgbe interface.\n");
10423                         }
10424                         if (rc != 0)
10425                                 return (rc);
10426                         KASSERT(sc->tom_softc != NULL,
10427                             ("%s: TOM activated but softc NULL", __func__));
10428                         KASSERT(uld_active(sc, ULD_TOM),
10429                             ("%s: TOM activated but flag not set", __func__));
10430                 }
10431
10432                 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10433                 if (!uld_active(sc, ULD_IWARP))
10434                         (void) t4_activate_uld(sc, ULD_IWARP);
10435                 if (!uld_active(sc, ULD_ISCSI))
10436                         (void) t4_activate_uld(sc, ULD_ISCSI);
10437
10438                 pi->uld_vis++;
10439                 setbit(&sc->offload_map, pi->port_id);
10440         } else {
10441                 pi->uld_vis--;
10442
10443                 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10444                         return (0);
10445
10446                 KASSERT(uld_active(sc, ULD_TOM),
10447                     ("%s: TOM never initialized?", __func__));
10448                 clrbit(&sc->offload_map, pi->port_id);
10449         }
10450
10451         return (0);
10452 }
10453
10454 /*
10455  * Add an upper layer driver to the global list.
10456  */
10457 int
10458 t4_register_uld(struct uld_info *ui)
10459 {
10460         int rc = 0;
10461         struct uld_info *u;
10462
10463         sx_xlock(&t4_uld_list_lock);
10464         SLIST_FOREACH(u, &t4_uld_list, link) {
10465             if (u->uld_id == ui->uld_id) {
10466                     rc = EEXIST;
10467                     goto done;
10468             }
10469         }
10470
10471         SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10472         ui->refcount = 0;
10473 done:
10474         sx_xunlock(&t4_uld_list_lock);
10475         return (rc);
10476 }
10477
10478 int
10479 t4_unregister_uld(struct uld_info *ui)
10480 {
10481         int rc = EINVAL;
10482         struct uld_info *u;
10483
10484         sx_xlock(&t4_uld_list_lock);
10485
10486         SLIST_FOREACH(u, &t4_uld_list, link) {
10487             if (u == ui) {
10488                     if (ui->refcount > 0) {
10489                             rc = EBUSY;
10490                             goto done;
10491                     }
10492
10493                     SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10494                     rc = 0;
10495                     goto done;
10496             }
10497         }
10498 done:
10499         sx_xunlock(&t4_uld_list_lock);
10500         return (rc);
10501 }
10502
10503 int
10504 t4_activate_uld(struct adapter *sc, int id)
10505 {
10506         int rc;
10507         struct uld_info *ui;
10508
10509         ASSERT_SYNCHRONIZED_OP(sc);
10510
10511         if (id < 0 || id > ULD_MAX)
10512                 return (EINVAL);
10513         rc = EAGAIN;    /* kldoad the module with this ULD and try again. */
10514
10515         sx_slock(&t4_uld_list_lock);
10516
10517         SLIST_FOREACH(ui, &t4_uld_list, link) {
10518                 if (ui->uld_id == id) {
10519                         if (!(sc->flags & FULL_INIT_DONE)) {
10520                                 rc = adapter_full_init(sc);
10521                                 if (rc != 0)
10522                                         break;
10523                         }
10524
10525                         rc = ui->activate(sc);
10526                         if (rc == 0) {
10527                                 setbit(&sc->active_ulds, id);
10528                                 ui->refcount++;
10529                         }
10530                         break;
10531                 }
10532         }
10533
10534         sx_sunlock(&t4_uld_list_lock);
10535
10536         return (rc);
10537 }
10538
10539 int
10540 t4_deactivate_uld(struct adapter *sc, int id)
10541 {
10542         int rc;
10543         struct uld_info *ui;
10544
10545         ASSERT_SYNCHRONIZED_OP(sc);
10546
10547         if (id < 0 || id > ULD_MAX)
10548                 return (EINVAL);
10549         rc = ENXIO;
10550
10551         sx_slock(&t4_uld_list_lock);
10552
10553         SLIST_FOREACH(ui, &t4_uld_list, link) {
10554                 if (ui->uld_id == id) {
10555                         rc = ui->deactivate(sc);
10556                         if (rc == 0) {
10557                                 clrbit(&sc->active_ulds, id);
10558                                 ui->refcount--;
10559                         }
10560                         break;
10561                 }
10562         }
10563
10564         sx_sunlock(&t4_uld_list_lock);
10565
10566         return (rc);
10567 }
10568
10569 int
10570 uld_active(struct adapter *sc, int uld_id)
10571 {
10572
10573         MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10574
10575         return (isset(&sc->active_ulds, uld_id));
10576 }
10577 #endif
10578
10579 /*
10580  * t  = ptr to tunable.
10581  * nc = number of CPUs.
10582  * c  = compiled in default for that tunable.
10583  */
10584 static void
10585 calculate_nqueues(int *t, int nc, const int c)
10586 {
10587         int nq;
10588
10589         if (*t > 0)
10590                 return;
10591         nq = *t < 0 ? -*t : c;
10592         *t = min(nc, nq);
10593 }
10594
10595 /*
10596  * Come up with reasonable defaults for some of the tunables, provided they're
10597  * not set by the user (in which case we'll use the values as is).
10598  */
10599 static void
10600 tweak_tunables(void)
10601 {
10602         int nc = mp_ncpus;      /* our snapshot of the number of CPUs */
10603
10604         if (t4_ntxq < 1) {
10605 #ifdef RSS
10606                 t4_ntxq = rss_getnumbuckets();
10607 #else
10608                 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10609 #endif
10610         }
10611
10612         calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10613
10614         if (t4_nrxq < 1) {
10615 #ifdef RSS
10616                 t4_nrxq = rss_getnumbuckets();
10617 #else
10618                 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10619 #endif
10620         }
10621
10622         calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10623
10624 #ifdef TCP_OFFLOAD
10625         calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10626         calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10627         calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10628         calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10629
10630         if (t4_toecaps_allowed == -1)
10631                 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10632
10633         if (t4_rdmacaps_allowed == -1) {
10634                 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10635                     FW_CAPS_CONFIG_RDMA_RDMAC;
10636         }
10637
10638         if (t4_iscsicaps_allowed == -1) {
10639                 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10640                     FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10641                     FW_CAPS_CONFIG_ISCSI_T10DIF;
10642         }
10643
10644         if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10645                 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10646
10647         if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10648                 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10649 #else
10650         if (t4_toecaps_allowed == -1)
10651                 t4_toecaps_allowed = 0;
10652
10653         if (t4_rdmacaps_allowed == -1)
10654                 t4_rdmacaps_allowed = 0;
10655
10656         if (t4_iscsicaps_allowed == -1)
10657                 t4_iscsicaps_allowed = 0;
10658 #endif
10659
10660 #ifdef DEV_NETMAP
10661         calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10662         calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10663 #endif
10664
10665         if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10666                 t4_tmr_idx = TMR_IDX;
10667
10668         if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10669                 t4_pktc_idx = PKTC_IDX;
10670
10671         if (t4_qsize_txq < 128)
10672                 t4_qsize_txq = 128;
10673
10674         if (t4_qsize_rxq < 128)
10675                 t4_qsize_rxq = 128;
10676         while (t4_qsize_rxq & 7)
10677                 t4_qsize_rxq++;
10678
10679         t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10680
10681         /*
10682          * Number of VIs to create per-port.  The first VI is the "main" regular
10683          * VI for the port.  The rest are additional virtual interfaces on the
10684          * same physical port.  Note that the main VI does not have native
10685          * netmap support but the extra VIs do.
10686          *
10687          * Limit the number of VIs per port to the number of available
10688          * MAC addresses per port.
10689          */
10690         if (t4_num_vis < 1)
10691                 t4_num_vis = 1;
10692         if (t4_num_vis > nitems(vi_mac_funcs)) {
10693                 t4_num_vis = nitems(vi_mac_funcs);
10694                 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10695         }
10696
10697         if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10698                 pcie_relaxed_ordering = 1;
10699 #if defined(__i386__) || defined(__amd64__)
10700                 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10701                         pcie_relaxed_ordering = 0;
10702 #endif
10703         }
10704 }
10705
10706 #ifdef DDB
10707 static void
10708 t4_dump_tcb(struct adapter *sc, int tid)
10709 {
10710         uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10711
10712         reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10713         save = t4_read_reg(sc, reg);
10714         base = sc->memwin[2].mw_base;
10715
10716         /* Dump TCB for the tid */
10717         tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10718         tcb_addr += tid * TCB_SIZE;
10719
10720         if (is_t4(sc)) {
10721                 pf = 0;
10722                 win_pos = tcb_addr & ~0xf;      /* start must be 16B aligned */
10723         } else {
10724                 pf = V_PFNUM(sc->pf);
10725                 win_pos = tcb_addr & ~0x7f;     /* start must be 128B aligned */
10726         }
10727         t4_write_reg(sc, reg, win_pos | pf);
10728         t4_read_reg(sc, reg);
10729
10730         off = tcb_addr - win_pos;
10731         for (i = 0; i < 4; i++) {
10732                 uint32_t buf[8];
10733                 for (j = 0; j < 8; j++, off += 4)
10734                         buf[j] = htonl(t4_read_reg(sc, base + off));
10735
10736                 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10737                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10738                     buf[7]);
10739         }
10740
10741         t4_write_reg(sc, reg, save);
10742         t4_read_reg(sc, reg);
10743 }
10744
10745 static void
10746 t4_dump_devlog(struct adapter *sc)
10747 {
10748         struct devlog_params *dparams = &sc->params.devlog;
10749         struct fw_devlog_e e;
10750         int i, first, j, m, nentries, rc;
10751         uint64_t ftstamp = UINT64_MAX;
10752
10753         if (dparams->start == 0) {
10754                 db_printf("devlog params not valid\n");
10755                 return;
10756         }
10757
10758         nentries = dparams->size / sizeof(struct fw_devlog_e);
10759         m = fwmtype_to_hwmtype(dparams->memtype);
10760
10761         /* Find the first entry. */
10762         first = -1;
10763         for (i = 0; i < nentries && !db_pager_quit; i++) {
10764                 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10765                     sizeof(e), (void *)&e);
10766                 if (rc != 0)
10767                         break;
10768
10769                 if (e.timestamp == 0)
10770                         break;
10771
10772                 e.timestamp = be64toh(e.timestamp);
10773                 if (e.timestamp < ftstamp) {
10774                         ftstamp = e.timestamp;
10775                         first = i;
10776                 }
10777         }
10778
10779         if (first == -1)
10780                 return;
10781
10782         i = first;
10783         do {
10784                 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10785                     sizeof(e), (void *)&e);
10786                 if (rc != 0)
10787                         return;
10788
10789                 if (e.timestamp == 0)
10790                         return;
10791
10792                 e.timestamp = be64toh(e.timestamp);
10793                 e.seqno = be32toh(e.seqno);
10794                 for (j = 0; j < 8; j++)
10795                         e.params[j] = be32toh(e.params[j]);
10796
10797                 db_printf("%10d  %15ju  %8s  %8s  ",
10798                     e.seqno, e.timestamp,
10799                     (e.level < nitems(devlog_level_strings) ?
10800                         devlog_level_strings[e.level] : "UNKNOWN"),
10801                     (e.facility < nitems(devlog_facility_strings) ?
10802                         devlog_facility_strings[e.facility] : "UNKNOWN"));
10803                 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10804                     e.params[3], e.params[4], e.params[5], e.params[6],
10805                     e.params[7]);
10806
10807                 if (++i == nentries)
10808                         i = 0;
10809         } while (i != first && !db_pager_quit);
10810 }
10811
10812 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10813 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10814
10815 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10816 {
10817         device_t dev;
10818         int t;
10819         bool valid;
10820
10821         valid = false;
10822         t = db_read_token();
10823         if (t == tIDENT) {
10824                 dev = device_lookup_by_name(db_tok_string);
10825                 valid = true;
10826         }
10827         db_skip_to_eol();
10828         if (!valid) {
10829                 db_printf("usage: show t4 devlog <nexus>\n");
10830                 return;
10831         }
10832
10833         if (dev == NULL) {
10834                 db_printf("device not found\n");
10835                 return;
10836         }
10837
10838         t4_dump_devlog(device_get_softc(dev));
10839 }
10840
10841 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10842 {
10843         device_t dev;
10844         int radix, tid, t;
10845         bool valid;
10846
10847         valid = false;
10848         radix = db_radix;
10849         db_radix = 10;
10850         t = db_read_token();
10851         if (t == tIDENT) {
10852                 dev = device_lookup_by_name(db_tok_string);
10853                 t = db_read_token();
10854                 if (t == tNUMBER) {
10855                         tid = db_tok_number;
10856                         valid = true;
10857                 }
10858         }
10859         db_radix = radix;
10860         db_skip_to_eol();
10861         if (!valid) {
10862                 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10863                 return;
10864         }
10865
10866         if (dev == NULL) {
10867                 db_printf("device not found\n");
10868                 return;
10869         }
10870         if (tid < 0) {
10871                 db_printf("invalid tid\n");
10872                 return;
10873         }
10874
10875         t4_dump_tcb(device_get_softc(dev), tid);
10876 }
10877 #endif
10878
10879 /*
10880  * Borrowed from cesa_prep_aes_key().
10881  *
10882  * NB: The crypto engine wants the words in the decryption key in reverse
10883  * order.
10884  */
10885 void
10886 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10887 {
10888         uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10889         uint32_t *dkey;
10890         int i;
10891
10892         rijndaelKeySetupEnc(ek, enc_key, kbits);
10893         dkey = dec_key;
10894         dkey += (kbits / 8) / 4;
10895
10896         switch (kbits) {
10897         case 128:
10898                 for (i = 0; i < 4; i++)
10899                         *--dkey = htobe32(ek[4 * 10 + i]);
10900                 break;
10901         case 192:
10902                 for (i = 0; i < 2; i++)
10903                         *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10904                 for (i = 0; i < 4; i++)
10905                         *--dkey = htobe32(ek[4 * 12 + i]);
10906                 break;
10907         case 256:
10908                 for (i = 0; i < 4; i++)
10909                         *--dkey = htobe32(ek[4 * 13 + i]);
10910                 for (i = 0; i < 4; i++)
10911                         *--dkey = htobe32(ek[4 * 14 + i]);
10912                 break;
10913         }
10914         MPASS(dkey == dec_key);
10915 }
10916
10917 static struct sx mlu;   /* mod load unload */
10918 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10919
10920 static int
10921 mod_event(module_t mod, int cmd, void *arg)
10922 {
10923         int rc = 0;
10924         static int loaded = 0;
10925
10926         switch (cmd) {
10927         case MOD_LOAD:
10928                 sx_xlock(&mlu);
10929                 if (loaded++ == 0) {
10930                         t4_sge_modload();
10931                         t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
10932                         t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
10933                         t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10934                         t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10935                         sx_init(&t4_list_lock, "T4/T5 adapters");
10936                         SLIST_INIT(&t4_list);
10937 #ifdef TCP_OFFLOAD
10938                         sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10939                         SLIST_INIT(&t4_uld_list);
10940 #endif
10941                         t4_tracer_modload();
10942                         tweak_tunables();
10943                 }
10944                 sx_xunlock(&mlu);
10945                 break;
10946
10947         case MOD_UNLOAD:
10948                 sx_xlock(&mlu);
10949                 if (--loaded == 0) {
10950                         int tries;
10951
10952                         sx_slock(&t4_list_lock);
10953                         if (!SLIST_EMPTY(&t4_list)) {
10954                                 rc = EBUSY;
10955                                 sx_sunlock(&t4_list_lock);
10956                                 goto done_unload;
10957                         }
10958 #ifdef TCP_OFFLOAD
10959                         sx_slock(&t4_uld_list_lock);
10960                         if (!SLIST_EMPTY(&t4_uld_list)) {
10961                                 rc = EBUSY;
10962                                 sx_sunlock(&t4_uld_list_lock);
10963                                 sx_sunlock(&t4_list_lock);
10964                                 goto done_unload;
10965                         }
10966 #endif
10967                         tries = 0;
10968                         while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10969                                 uprintf("%ju clusters with custom free routine "
10970                                     "still is use.\n", t4_sge_extfree_refs());
10971                                 pause("t4unload", 2 * hz);
10972                         }
10973 #ifdef TCP_OFFLOAD
10974                         sx_sunlock(&t4_uld_list_lock);
10975 #endif
10976                         sx_sunlock(&t4_list_lock);
10977
10978                         if (t4_sge_extfree_refs() == 0) {
10979                                 t4_tracer_modunload();
10980 #ifdef TCP_OFFLOAD
10981                                 sx_destroy(&t4_uld_list_lock);
10982 #endif
10983                                 sx_destroy(&t4_list_lock);
10984                                 t4_sge_modunload();
10985                                 loaded = 0;
10986                         } else {
10987                                 rc = EBUSY;
10988                                 loaded++;       /* undo earlier decrement */
10989                         }
10990                 }
10991 done_unload:
10992                 sx_xunlock(&mlu);
10993                 break;
10994         }
10995
10996         return (rc);
10997 }
10998
10999 static devclass_t t4_devclass, t5_devclass, t6_devclass;
11000 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
11001 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
11002
11003 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
11004 MODULE_VERSION(t4nex, 1);
11005 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
11006 #ifdef DEV_NETMAP
11007 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
11008 #endif /* DEV_NETMAP */
11009
11010 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
11011 MODULE_VERSION(t5nex, 1);
11012 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
11013 #ifdef DEV_NETMAP
11014 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
11015 #endif /* DEV_NETMAP */
11016
11017 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
11018 MODULE_VERSION(t6nex, 1);
11019 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
11020 #ifdef DEV_NETMAP
11021 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
11022 #endif /* DEV_NETMAP */
11023
11024 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
11025 MODULE_VERSION(cxgbe, 1);
11026
11027 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
11028 MODULE_VERSION(cxl, 1);
11029
11030 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
11031 MODULE_VERSION(cc, 1);
11032
11033 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
11034 MODULE_VERSION(vcxgbe, 1);
11035
11036 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
11037 MODULE_VERSION(vcxl, 1);
11038
11039 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
11040 MODULE_VERSION(vcc, 1);