2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
74 #include <crypto/rijndael/rijndael.h>
77 #include <ddb/db_lex.h>
80 #include "common/common.h"
81 #include "common/t4_msg.h"
82 #include "common/t4_regs.h"
83 #include "common/t4_regs_values.h"
84 #include "cudbg/cudbg.h"
88 #include "t4_mp_ring.h"
92 /* T4 bus driver interface */
93 static int t4_probe(device_t);
94 static int t4_attach(device_t);
95 static int t4_detach(device_t);
96 static int t4_child_location_str(device_t, device_t, char *, size_t);
97 static int t4_ready(device_t);
98 static int t4_read_port_device(device_t, int, device_t *);
99 static device_method_t t4_methods[] = {
100 DEVMETHOD(device_probe, t4_probe),
101 DEVMETHOD(device_attach, t4_attach),
102 DEVMETHOD(device_detach, t4_detach),
104 DEVMETHOD(bus_child_location_str, t4_child_location_str),
106 DEVMETHOD(t4_is_main_ready, t4_ready),
107 DEVMETHOD(t4_read_port_device, t4_read_port_device),
111 static driver_t t4_driver = {
114 sizeof(struct adapter)
118 /* T4 port (cxgbe) interface */
119 static int cxgbe_probe(device_t);
120 static int cxgbe_attach(device_t);
121 static int cxgbe_detach(device_t);
122 device_method_t cxgbe_methods[] = {
123 DEVMETHOD(device_probe, cxgbe_probe),
124 DEVMETHOD(device_attach, cxgbe_attach),
125 DEVMETHOD(device_detach, cxgbe_detach),
128 static driver_t cxgbe_driver = {
131 sizeof(struct port_info)
134 /* T4 VI (vcxgbe) interface */
135 static int vcxgbe_probe(device_t);
136 static int vcxgbe_attach(device_t);
137 static int vcxgbe_detach(device_t);
138 static device_method_t vcxgbe_methods[] = {
139 DEVMETHOD(device_probe, vcxgbe_probe),
140 DEVMETHOD(device_attach, vcxgbe_attach),
141 DEVMETHOD(device_detach, vcxgbe_detach),
144 static driver_t vcxgbe_driver = {
147 sizeof(struct vi_info)
150 static d_ioctl_t t4_ioctl;
152 static struct cdevsw t4_cdevsw = {
153 .d_version = D_VERSION,
158 /* T5 bus driver interface */
159 static int t5_probe(device_t);
160 static device_method_t t5_methods[] = {
161 DEVMETHOD(device_probe, t5_probe),
162 DEVMETHOD(device_attach, t4_attach),
163 DEVMETHOD(device_detach, t4_detach),
165 DEVMETHOD(bus_child_location_str, t4_child_location_str),
167 DEVMETHOD(t4_is_main_ready, t4_ready),
168 DEVMETHOD(t4_read_port_device, t4_read_port_device),
172 static driver_t t5_driver = {
175 sizeof(struct adapter)
179 /* T5 port (cxl) interface */
180 static driver_t cxl_driver = {
183 sizeof(struct port_info)
186 /* T5 VI (vcxl) interface */
187 static driver_t vcxl_driver = {
190 sizeof(struct vi_info)
193 /* T6 bus driver interface */
194 static int t6_probe(device_t);
195 static device_method_t t6_methods[] = {
196 DEVMETHOD(device_probe, t6_probe),
197 DEVMETHOD(device_attach, t4_attach),
198 DEVMETHOD(device_detach, t4_detach),
200 DEVMETHOD(bus_child_location_str, t4_child_location_str),
202 DEVMETHOD(t4_is_main_ready, t4_ready),
203 DEVMETHOD(t4_read_port_device, t4_read_port_device),
207 static driver_t t6_driver = {
210 sizeof(struct adapter)
214 /* T6 port (cc) interface */
215 static driver_t cc_driver = {
218 sizeof(struct port_info)
221 /* T6 VI (vcc) interface */
222 static driver_t vcc_driver = {
225 sizeof(struct vi_info)
228 /* ifnet interface */
229 static void cxgbe_init(void *);
230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
231 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
232 static void cxgbe_qflush(struct ifnet *);
234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
237 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
238 * then ADAPTER_LOCK, then t4_uld_list_lock.
240 static struct sx t4_list_lock;
241 SLIST_HEAD(, adapter) t4_list;
243 static struct sx t4_uld_list_lock;
244 SLIST_HEAD(, uld_info) t4_uld_list;
248 * Tunables. See tweak_tunables() too.
250 * Each tunable is set to a default value here if it's known at compile-time.
251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
252 * provide a reasonable default (upto n) when the driver is loaded.
254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
255 * T5 are under hw.cxl.
257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
262 * Number of queues for tx and rx, NIC and offload.
266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
267 "Number of TX queues per port");
268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
273 "Number of RX queues per port");
274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
277 static int t4_ntxq_vi = -NTXQ_VI;
278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
279 "Number of TX queues per VI");
282 static int t4_nrxq_vi = -NRXQ_VI;
283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
284 "Number of RX queues per VI");
286 static int t4_rsrv_noflowq = 0;
287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
288 0, "Reserve TX queue 0 of each VI for non-flowid packets");
290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
292 static int t4_nofldtxq = -NOFLDTXQ;
293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
294 "Number of offload TX queues per port");
297 static int t4_nofldrxq = -NOFLDRXQ;
298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
299 "Number of offload RX queues per port");
301 #define NOFLDTXQ_VI 1
302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
304 "Number of offload TX queues per VI");
306 #define NOFLDRXQ_VI 1
307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
309 "Number of offload RX queues per VI");
311 #define TMR_IDX_OFLD 1
312 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
316 #define PKTC_IDX_OFLD (-1)
317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
321 /* 0 means chip/fw default, non-zero number is value in microseconds */
322 static u_long t4_toe_keepalive_idle = 0;
323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
326 /* 0 means chip/fw default, non-zero number is value in microseconds */
327 static u_long t4_toe_keepalive_interval = 0;
328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
332 static int t4_toe_keepalive_count = 0;
333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
336 /* 0 means chip/fw default, non-zero number is value in microseconds */
337 static u_long t4_toe_rexmt_min = 0;
338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
341 /* 0 means chip/fw default, non-zero number is value in microseconds */
342 static u_long t4_toe_rexmt_max = 0;
343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
347 static int t4_toe_rexmt_count = 0;
348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
351 /* -1 means chip/fw default, other values are raw backoff values to use */
352 static int t4_toe_rexmt_backoff[16] = {
353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
356 "cxgbe(4) TOE retransmit backoff values");
357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
358 &t4_toe_rexmt_backoff[0], 0, "");
359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
360 &t4_toe_rexmt_backoff[1], 0, "");
361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
362 &t4_toe_rexmt_backoff[2], 0, "");
363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
364 &t4_toe_rexmt_backoff[3], 0, "");
365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
366 &t4_toe_rexmt_backoff[4], 0, "");
367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
368 &t4_toe_rexmt_backoff[5], 0, "");
369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
370 &t4_toe_rexmt_backoff[6], 0, "");
371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
372 &t4_toe_rexmt_backoff[7], 0, "");
373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_backoff[8], 0, "");
375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_backoff[9], 0, "");
377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
378 &t4_toe_rexmt_backoff[10], 0, "");
379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
380 &t4_toe_rexmt_backoff[11], 0, "");
381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
382 &t4_toe_rexmt_backoff[12], 0, "");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[13], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[14], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[15], 0, "");
393 static int t4_nnmtxq_vi = -NNMTXQ_VI;
394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
395 "Number of netmap TX queues per VI");
398 static int t4_nnmrxq_vi = -NNMRXQ_VI;
399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
400 "Number of netmap RX queues per VI");
404 * Holdoff parameters for ports.
407 int t4_tmr_idx = TMR_IDX;
408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
409 0, "Holdoff timer index");
410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
412 #define PKTC_IDX (-1)
413 int t4_pktc_idx = PKTC_IDX;
414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
415 0, "Holdoff packet counter index");
416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
419 * Size (# of entries) of each tx and rx queue.
421 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
423 "Number of descriptors in each TX queue");
425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
427 "Number of descriptors in each RX queue");
430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
437 * Configuration file. All the _CF names here are special.
439 #define DEFAULT_CF "default"
440 #define BUILTIN_CF "built-in"
441 #define FLASH_CF "flash"
442 #define UWIRE_CF "uwire"
443 #define FPGA_CF "fpga"
444 static char t4_cfg_file[32] = DEFAULT_CF;
445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
446 sizeof(t4_cfg_file), "Firmware configuration file");
449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
452 * mark or when signalled to do so, 0 to never emit PAUSE.
453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
454 * negotiated settings will override rx_pause/tx_pause.
455 * Otherwise rx_pause/tx_pause are applied forcibly.
457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
459 &t4_pause_settings, 0,
460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
467 static int t4_fec = -1;
468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
472 * Link autonegotiation.
473 * -1 to run with the firmware default.
477 static int t4_autoneg = -1;
478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
479 "Link autonegotiation");
482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
483 * encouraged respectively). '-n' is the same as 'n' except the firmware
484 * version used in the checks is read from the firmware bundled with the driver.
486 static int t4_fw_install = 1;
487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
491 * ASIC features that will be used. Disable the ones you don't want so that the
492 * chip resources aren't wasted on features that will not be used.
494 static int t4_nbmcaps_allowed = 0;
495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
500 &t4_linkcaps_allowed, 0, "Default link capabilities");
502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
503 FW_CAPS_CONFIG_SWITCH_EGRESS;
504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
505 &t4_switchcaps_allowed, 0, "Default switch capabilities");
508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
512 FW_CAPS_CONFIG_NIC_HASHFILTER;
514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
515 &t4_niccaps_allowed, 0, "Default NIC capabilities");
517 static int t4_toecaps_allowed = -1;
518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
521 static int t4_rdmacaps_allowed = -1;
522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
525 static int t4_cryptocaps_allowed = -1;
526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
529 static int t4_iscsicaps_allowed = -1;
530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
533 static int t4_fcoecaps_allowed = 0;
534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
537 static int t5_write_combine = 0;
538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
539 0, "Use WC instead of UC for BAR2");
541 static int t4_num_vis = 1;
542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
543 "Number of VIs per port");
546 * PCIe Relaxed Ordering.
547 * -1: driver should figure out a good value.
552 static int pcie_relaxed_ordering = -1;
553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
554 &pcie_relaxed_ordering, 0,
555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
557 static int t4_panic_on_fatal_err = 0;
558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
559 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
565 static int t4_cop_managed_offloading = 0;
566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
567 &t4_cop_managed_offloading, 0,
568 "COP (Connection Offload Policy) controls all TOE offload");
571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
572 static int vi_mac_funcs[] = {
576 FW_VI_FUNC_OPENISCSI,
582 struct intrs_and_queues {
583 uint16_t intr_type; /* INTx, MSI, or MSI-X */
584 uint16_t num_vis; /* number of VIs for each port */
585 uint16_t nirq; /* Total # of vectors */
586 uint16_t ntxq; /* # of NIC txq's for each port */
587 uint16_t nrxq; /* # of NIC rxq's for each port */
588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
589 uint16_t nofldrxq; /* # of TOE rxq's for each port */
591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
592 uint16_t ntxq_vi; /* # of NIC txq's */
593 uint16_t nrxq_vi; /* # of NIC rxq's */
594 uint16_t nofldtxq_vi; /* # of TOE txq's */
595 uint16_t nofldrxq_vi; /* # of TOE rxq's */
596 uint16_t nnmtxq_vi; /* # of netmap txq's */
597 uint16_t nnmrxq_vi; /* # of netmap rxq's */
600 static void setup_memwin(struct adapter *);
601 static void position_memwin(struct adapter *, int, uint32_t);
602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
603 static int fwmtype_to_hwmtype(int);
604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
606 static int fixup_devlog_params(struct adapter *);
607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
608 static int contact_firmware(struct adapter *);
609 static int partition_resources(struct adapter *);
610 static int get_params__pre_init(struct adapter *);
611 static int set_params__pre_init(struct adapter *);
612 static int get_params__post_init(struct adapter *);
613 static int set_params__post_init(struct adapter *);
614 static void t4_set_desc(struct adapter *);
615 static bool fixed_ifmedia(struct port_info *);
616 static void build_medialist(struct port_info *);
617 static void init_link_config(struct port_info *);
618 static int fixup_link_config(struct port_info *);
619 static int apply_link_config(struct port_info *);
620 static int cxgbe_init_synchronized(struct vi_info *);
621 static int cxgbe_uninit_synchronized(struct vi_info *);
622 static void quiesce_txq(struct adapter *, struct sge_txq *);
623 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
624 static void quiesce_iq(struct adapter *, struct sge_iq *);
625 static void quiesce_fl(struct adapter *, struct sge_fl *);
626 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
627 driver_intr_t *, void *, char *);
628 static int t4_free_irq(struct adapter *, struct irq *);
629 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
630 static void vi_refresh_stats(struct adapter *, struct vi_info *);
631 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
632 static void cxgbe_tick(void *);
633 static void cxgbe_sysctls(struct port_info *);
634 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
635 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
636 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
637 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
638 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
639 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
640 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
641 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
642 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
643 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
644 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
645 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
646 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
647 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
648 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
649 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
650 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
651 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
652 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
653 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
654 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
655 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
656 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
657 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
658 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
659 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
660 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
661 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
662 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
663 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
664 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
665 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
666 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
667 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
668 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
669 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
670 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
671 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
672 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
673 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
674 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
675 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
676 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
677 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
679 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
680 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
681 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
682 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
683 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
684 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
685 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
686 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
688 static int get_sge_context(struct adapter *, struct t4_sge_context *);
689 static int load_fw(struct adapter *, struct t4_data *);
690 static int load_cfg(struct adapter *, struct t4_data *);
691 static int load_boot(struct adapter *, struct t4_bootrom *);
692 static int load_bootcfg(struct adapter *, struct t4_data *);
693 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
694 static void free_offload_policy(struct t4_offload_policy *);
695 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
696 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
697 static int read_i2c(struct adapter *, struct t4_i2c_data *);
698 static int clear_stats(struct adapter *, u_int);
700 static int toe_capability(struct vi_info *, int);
702 static int mod_event(module_t, int, void *);
703 static int notify_siblings(device_t, int);
709 {0xa000, "Chelsio Terminator 4 FPGA"},
710 {0x4400, "Chelsio T440-dbg"},
711 {0x4401, "Chelsio T420-CR"},
712 {0x4402, "Chelsio T422-CR"},
713 {0x4403, "Chelsio T440-CR"},
714 {0x4404, "Chelsio T420-BCH"},
715 {0x4405, "Chelsio T440-BCH"},
716 {0x4406, "Chelsio T440-CH"},
717 {0x4407, "Chelsio T420-SO"},
718 {0x4408, "Chelsio T420-CX"},
719 {0x4409, "Chelsio T420-BT"},
720 {0x440a, "Chelsio T404-BT"},
721 {0x440e, "Chelsio T440-LP-CR"},
723 {0xb000, "Chelsio Terminator 5 FPGA"},
724 {0x5400, "Chelsio T580-dbg"},
725 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
726 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
727 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
728 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
729 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
730 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
731 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
732 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
733 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
734 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
735 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
736 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
737 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
738 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
739 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
740 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
741 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
744 {0x5483, "Custom T540-CR"},
745 {0x5484, "Custom T540-BT"},
747 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
748 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
749 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
750 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
751 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
752 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
753 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
754 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
755 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
756 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
757 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
758 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
759 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
760 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
761 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
762 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
765 {0x6480, "Custom T6225-CR"},
766 {0x6481, "Custom T62100-CR"},
767 {0x6482, "Custom T6225-CR"},
768 {0x6483, "Custom T62100-CR"},
769 {0x6484, "Custom T64100-CR"},
770 {0x6485, "Custom T6240-SO"},
771 {0x6486, "Custom T6225-SO-CR"},
772 {0x6487, "Custom T6225-CR"},
777 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
778 * be exactly the same for both rxq and ofld_rxq.
780 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
781 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
783 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
786 t4_probe(device_t dev)
789 uint16_t v = pci_get_vendor(dev);
790 uint16_t d = pci_get_device(dev);
791 uint8_t f = pci_get_function(dev);
793 if (v != PCI_VENDOR_ID_CHELSIO)
796 /* Attach only to PF0 of the FPGA */
797 if (d == 0xa000 && f != 0)
800 for (i = 0; i < nitems(t4_pciids); i++) {
801 if (d == t4_pciids[i].device) {
802 device_set_desc(dev, t4_pciids[i].desc);
803 return (BUS_PROBE_DEFAULT);
811 t5_probe(device_t dev)
814 uint16_t v = pci_get_vendor(dev);
815 uint16_t d = pci_get_device(dev);
816 uint8_t f = pci_get_function(dev);
818 if (v != PCI_VENDOR_ID_CHELSIO)
821 /* Attach only to PF0 of the FPGA */
822 if (d == 0xb000 && f != 0)
825 for (i = 0; i < nitems(t5_pciids); i++) {
826 if (d == t5_pciids[i].device) {
827 device_set_desc(dev, t5_pciids[i].desc);
828 return (BUS_PROBE_DEFAULT);
836 t6_probe(device_t dev)
839 uint16_t v = pci_get_vendor(dev);
840 uint16_t d = pci_get_device(dev);
842 if (v != PCI_VENDOR_ID_CHELSIO)
845 for (i = 0; i < nitems(t6_pciids); i++) {
846 if (d == t6_pciids[i].device) {
847 device_set_desc(dev, t6_pciids[i].desc);
848 return (BUS_PROBE_DEFAULT);
856 t5_attribute_workaround(device_t dev)
862 * The T5 chips do not properly echo the No Snoop and Relaxed
863 * Ordering attributes when replying to a TLP from a Root
864 * Port. As a workaround, find the parent Root Port and
865 * disable No Snoop and Relaxed Ordering. Note that this
866 * affects all devices under this root port.
868 root_port = pci_find_pcie_root_port(dev);
869 if (root_port == NULL) {
870 device_printf(dev, "Unable to find parent root port\n");
874 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
875 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
876 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
878 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
879 device_get_nameunit(root_port));
882 static const struct devnames devnames[] = {
884 .nexus_name = "t4nex",
885 .ifnet_name = "cxgbe",
886 .vi_ifnet_name = "vcxgbe",
887 .pf03_drv_name = "t4iov",
888 .vf_nexus_name = "t4vf",
889 .vf_ifnet_name = "cxgbev"
891 .nexus_name = "t5nex",
893 .vi_ifnet_name = "vcxl",
894 .pf03_drv_name = "t5iov",
895 .vf_nexus_name = "t5vf",
896 .vf_ifnet_name = "cxlv"
898 .nexus_name = "t6nex",
900 .vi_ifnet_name = "vcc",
901 .pf03_drv_name = "t6iov",
902 .vf_nexus_name = "t6vf",
903 .vf_ifnet_name = "ccv"
908 t4_init_devnames(struct adapter *sc)
913 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
914 sc->names = &devnames[id - CHELSIO_T4];
916 device_printf(sc->dev, "chip id %d is not supported.\n", id);
922 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
924 const char *parent, *name;
929 parent = device_get_nameunit(sc->dev);
930 name = sc->names->ifnet_name;
931 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
932 if (resource_long_value(name, unit, "port", &value) == 0 &&
933 value == pi->port_id)
940 t4_attach(device_t dev)
943 int rc = 0, i, j, rqidx, tqidx, nports;
944 struct make_dev_args mda;
945 struct intrs_and_queues iaq;
948 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
955 int nm_rqidx, nm_tqidx;
959 sc = device_get_softc(dev);
961 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
963 if ((pci_get_device(dev) & 0xff00) == 0x5400)
964 t5_attribute_workaround(dev);
965 pci_enable_busmaster(dev);
966 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
969 pci_set_max_read_req(dev, 4096);
970 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
971 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
972 if (pcie_relaxed_ordering == 0 &&
973 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
974 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
975 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
976 } else if (pcie_relaxed_ordering == 1 &&
977 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
978 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
979 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
983 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
984 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
986 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
987 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
988 device_get_nameunit(dev));
990 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
991 device_get_nameunit(dev));
992 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
995 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
996 TAILQ_INIT(&sc->sfl);
997 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
999 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1002 rw_init(&sc->policy_lock, "connection offload policy");
1004 rc = t4_map_bars_0_and_4(sc);
1006 goto done; /* error message displayed already */
1008 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1010 /* Prepare the adapter for operation. */
1011 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1012 rc = -t4_prep_adapter(sc, buf);
1015 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1020 * This is the real PF# to which we're attaching. Works from within PCI
1021 * passthrough environments too, where pci_get_function() could return a
1022 * different PF# depending on the passthrough configuration. We need to
1023 * use the real PF# in all our communication with the firmware.
1025 j = t4_read_reg(sc, A_PL_WHOAMI);
1026 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1029 t4_init_devnames(sc);
1030 if (sc->names == NULL) {
1032 goto done; /* error message displayed already */
1036 * Do this really early, with the memory windows set up even before the
1037 * character device. The userland tool's register i/o and mem read
1038 * will work even in "recovery mode".
1041 if (t4_init_devlog_params(sc, 0) == 0)
1042 fixup_devlog_params(sc);
1043 make_dev_args_init(&mda);
1044 mda.mda_devsw = &t4_cdevsw;
1045 mda.mda_uid = UID_ROOT;
1046 mda.mda_gid = GID_WHEEL;
1047 mda.mda_mode = 0600;
1048 mda.mda_si_drv1 = sc;
1049 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1051 device_printf(dev, "failed to create nexus char device: %d.\n",
1054 /* Go no further if recovery mode has been requested. */
1055 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1056 device_printf(dev, "recovery mode.\n");
1060 #if defined(__i386__)
1061 if ((cpu_feature & CPUID_CX8) == 0) {
1062 device_printf(dev, "64 bit atomics not available.\n");
1068 /* Contact the firmware and try to become the master driver. */
1069 rc = contact_firmware(sc);
1071 goto done; /* error message displayed already */
1072 MPASS(sc->flags & FW_OK);
1074 rc = get_params__pre_init(sc);
1076 goto done; /* error message displayed already */
1078 if (sc->flags & MASTER_PF) {
1079 rc = partition_resources(sc);
1081 goto done; /* error message displayed already */
1085 rc = get_params__post_init(sc);
1087 goto done; /* error message displayed already */
1089 rc = set_params__post_init(sc);
1091 goto done; /* error message displayed already */
1093 rc = t4_map_bar_2(sc);
1095 goto done; /* error message displayed already */
1097 rc = t4_create_dma_tag(sc);
1099 goto done; /* error message displayed already */
1102 * First pass over all the ports - allocate VIs and initialize some
1103 * basic parameters like mac address, port type, etc.
1105 for_each_port(sc, i) {
1106 struct port_info *pi;
1108 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1111 /* These must be set before t4_port_init */
1115 * XXX: vi[0] is special so we can't delay this allocation until
1116 * pi->nvi's final value is known.
1118 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1122 * Allocate the "main" VI and initialize parameters
1125 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1127 device_printf(dev, "unable to initialize port %d: %d\n",
1129 free(pi->vi, M_CXGBE);
1135 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1136 device_get_nameunit(dev), i);
1137 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1138 sc->chan_map[pi->tx_chan] = i;
1140 /* All VIs on this port share this media. */
1141 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1142 cxgbe_media_status);
1145 init_link_config(pi);
1146 fixup_link_config(pi);
1147 build_medialist(pi);
1148 if (fixed_ifmedia(pi))
1149 pi->flags |= FIXED_IFMEDIA;
1152 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1153 t4_ifnet_unit(sc, pi));
1154 if (pi->dev == NULL) {
1156 "failed to add device for port %d.\n", i);
1160 pi->vi[0].dev = pi->dev;
1161 device_set_softc(pi->dev, pi);
1165 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1167 nports = sc->params.nports;
1168 rc = cfg_itype_and_nqueues(sc, &iaq);
1170 goto done; /* error message displayed already */
1172 num_vis = iaq.num_vis;
1173 sc->intr_type = iaq.intr_type;
1174 sc->intr_count = iaq.nirq;
1177 s->nrxq = nports * iaq.nrxq;
1178 s->ntxq = nports * iaq.ntxq;
1180 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1181 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1183 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1184 s->neq += nports; /* ctrl queues: 1 per port */
1185 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1186 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1187 if (is_offload(sc) || is_ethoffload(sc)) {
1188 s->nofldtxq = nports * iaq.nofldtxq;
1190 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1191 s->neq += s->nofldtxq;
1193 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1194 M_CXGBE, M_ZERO | M_WAITOK);
1198 if (is_offload(sc)) {
1199 s->nofldrxq = nports * iaq.nofldrxq;
1201 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1202 s->neq += s->nofldrxq; /* free list */
1203 s->niq += s->nofldrxq;
1205 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1206 M_CXGBE, M_ZERO | M_WAITOK);
1211 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1212 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1214 s->neq += s->nnmtxq + s->nnmrxq;
1215 s->niq += s->nnmrxq;
1217 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1218 M_CXGBE, M_ZERO | M_WAITOK);
1219 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1220 M_CXGBE, M_ZERO | M_WAITOK);
1223 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1225 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1227 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1229 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1231 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1234 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1237 t4_init_l2t(sc, M_WAITOK);
1238 t4_init_smt(sc, M_WAITOK);
1239 t4_init_tx_sched(sc);
1241 t4_init_etid_table(sc);
1244 t4_init_clip_table(sc);
1246 if (sc->vres.key.size != 0)
1247 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1248 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1251 * Second pass over the ports. This time we know the number of rx and
1252 * tx queues that each port should get.
1255 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1262 nm_rqidx = nm_tqidx = 0;
1264 for_each_port(sc, i) {
1265 struct port_info *pi = sc->port[i];
1272 for_each_vi(pi, j, vi) {
1274 vi->qsize_rxq = t4_qsize_rxq;
1275 vi->qsize_txq = t4_qsize_txq;
1277 vi->first_rxq = rqidx;
1278 vi->first_txq = tqidx;
1279 vi->tmr_idx = t4_tmr_idx;
1280 vi->pktc_idx = t4_pktc_idx;
1281 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1282 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1287 if (j == 0 && vi->ntxq > 1)
1288 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1290 vi->rsrv_noflowq = 0;
1292 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1293 vi->first_ofld_txq = ofld_tqidx;
1294 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1295 ofld_tqidx += vi->nofldtxq;
1298 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1299 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1300 vi->first_ofld_rxq = ofld_rqidx;
1301 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1303 ofld_rqidx += vi->nofldrxq;
1307 vi->first_nm_rxq = nm_rqidx;
1308 vi->first_nm_txq = nm_tqidx;
1309 vi->nnmrxq = iaq.nnmrxq_vi;
1310 vi->nnmtxq = iaq.nnmtxq_vi;
1311 nm_rqidx += vi->nnmrxq;
1312 nm_tqidx += vi->nnmtxq;
1318 rc = t4_setup_intr_handlers(sc);
1321 "failed to setup interrupt handlers: %d\n", rc);
1325 rc = bus_generic_probe(dev);
1327 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1332 * Ensure thread-safe mailbox access (in debug builds).
1334 * So far this was the only thread accessing the mailbox but various
1335 * ifnets and sysctls are about to be created and their handlers/ioctls
1336 * will access the mailbox from different threads.
1338 sc->flags |= CHK_MBOX_ACCESS;
1340 rc = bus_generic_attach(dev);
1343 "failed to attach all child ports: %d\n", rc);
1348 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1349 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1350 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1351 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1352 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1356 notify_siblings(dev, 0);
1359 if (rc != 0 && sc->cdev) {
1360 /* cdev was created and so cxgbetool works; recover that way. */
1362 "error during attach, adapter is now in recovery mode.\n");
1367 t4_detach_common(dev);
1375 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1378 struct port_info *pi;
1381 sc = device_get_softc(bus);
1383 for_each_port(sc, i) {
1385 if (pi != NULL && pi->dev == dev) {
1386 snprintf(buf, buflen, "port=%d", pi->port_id);
1394 t4_ready(device_t dev)
1398 sc = device_get_softc(dev);
1399 if (sc->flags & FW_OK)
1405 t4_read_port_device(device_t dev, int port, device_t *child)
1408 struct port_info *pi;
1410 sc = device_get_softc(dev);
1411 if (port < 0 || port >= MAX_NPORTS)
1413 pi = sc->port[port];
1414 if (pi == NULL || pi->dev == NULL)
1421 notify_siblings(device_t dev, int detaching)
1427 for (i = 0; i < PCI_FUNCMAX; i++) {
1428 if (i == pci_get_function(dev))
1430 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1431 pci_get_slot(dev), i);
1432 if (sibling == NULL || !device_is_attached(sibling))
1435 error = T4_DETACH_CHILD(sibling);
1437 (void)T4_ATTACH_CHILD(sibling);
1448 t4_detach(device_t dev)
1453 sc = device_get_softc(dev);
1455 rc = notify_siblings(dev, 1);
1458 "failed to detach sibling devices: %d\n", rc);
1462 return (t4_detach_common(dev));
1466 t4_detach_common(device_t dev)
1469 struct port_info *pi;
1472 sc = device_get_softc(dev);
1475 destroy_dev(sc->cdev);
1479 sx_xlock(&t4_list_lock);
1480 SLIST_REMOVE(&t4_list, sc, adapter, link);
1481 sx_xunlock(&t4_list_lock);
1483 sc->flags &= ~CHK_MBOX_ACCESS;
1484 if (sc->flags & FULL_INIT_DONE) {
1485 if (!(sc->flags & IS_VF))
1486 t4_intr_disable(sc);
1489 if (device_is_attached(dev)) {
1490 rc = bus_generic_detach(dev);
1493 "failed to detach child devices: %d\n", rc);
1498 for (i = 0; i < sc->intr_count; i++)
1499 t4_free_irq(sc, &sc->irq[i]);
1501 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1502 t4_free_tx_sched(sc);
1504 for (i = 0; i < MAX_NPORTS; i++) {
1507 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1509 device_delete_child(dev, pi->dev);
1511 mtx_destroy(&pi->pi_lock);
1512 free(pi->vi, M_CXGBE);
1517 device_delete_children(dev);
1519 if (sc->flags & FULL_INIT_DONE)
1520 adapter_full_uninit(sc);
1522 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1523 t4_fw_bye(sc, sc->mbox);
1525 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1526 pci_release_msi(dev);
1529 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1533 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1537 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1541 t4_free_l2t(sc->l2t);
1543 t4_free_smt(sc->smt);
1545 t4_free_etid_table(sc);
1548 vmem_destroy(sc->key_map);
1550 t4_destroy_clip_table(sc);
1553 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1554 free(sc->sge.ofld_txq, M_CXGBE);
1557 free(sc->sge.ofld_rxq, M_CXGBE);
1560 free(sc->sge.nm_rxq, M_CXGBE);
1561 free(sc->sge.nm_txq, M_CXGBE);
1563 free(sc->irq, M_CXGBE);
1564 free(sc->sge.rxq, M_CXGBE);
1565 free(sc->sge.txq, M_CXGBE);
1566 free(sc->sge.ctrlq, M_CXGBE);
1567 free(sc->sge.iqmap, M_CXGBE);
1568 free(sc->sge.eqmap, M_CXGBE);
1569 free(sc->tids.ftid_tab, M_CXGBE);
1570 free(sc->tids.hpftid_tab, M_CXGBE);
1571 free_hftid_hash(&sc->tids);
1572 free(sc->tids.atid_tab, M_CXGBE);
1573 free(sc->tids.tid_tab, M_CXGBE);
1574 free(sc->tt.tls_rx_ports, M_CXGBE);
1575 t4_destroy_dma_tag(sc);
1577 callout_drain(&sc->sfl_callout);
1578 if (mtx_initialized(&sc->tids.ftid_lock)) {
1579 mtx_destroy(&sc->tids.ftid_lock);
1580 cv_destroy(&sc->tids.ftid_cv);
1582 if (mtx_initialized(&sc->tids.atid_lock))
1583 mtx_destroy(&sc->tids.atid_lock);
1584 if (mtx_initialized(&sc->ifp_lock))
1585 mtx_destroy(&sc->ifp_lock);
1587 if (rw_initialized(&sc->policy_lock)) {
1588 rw_destroy(&sc->policy_lock);
1590 if (sc->policy != NULL)
1591 free_offload_policy(sc->policy);
1595 for (i = 0; i < NUM_MEMWIN; i++) {
1596 struct memwin *mw = &sc->memwin[i];
1598 if (rw_initialized(&mw->mw_lock))
1599 rw_destroy(&mw->mw_lock);
1602 mtx_destroy(&sc->sfl_lock);
1603 mtx_destroy(&sc->reg_lock);
1604 mtx_destroy(&sc->sc_lock);
1606 bzero(sc, sizeof(*sc));
1612 cxgbe_probe(device_t dev)
1615 struct port_info *pi = device_get_softc(dev);
1617 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1618 device_set_desc_copy(dev, buf);
1620 return (BUS_PROBE_DEFAULT);
1623 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1624 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1625 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1627 #define T4_CAP_ENABLE (T4_CAP)
1630 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1635 vi->xact_addr_filt = -1;
1636 callout_init(&vi->tick, 1);
1638 /* Allocate an ifnet and set it up */
1639 ifp = if_alloc(IFT_ETHER);
1641 device_printf(dev, "Cannot allocate ifnet\n");
1647 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1648 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1650 ifp->if_init = cxgbe_init;
1651 ifp->if_ioctl = cxgbe_ioctl;
1652 ifp->if_transmit = cxgbe_transmit;
1653 ifp->if_qflush = cxgbe_qflush;
1654 ifp->if_get_counter = cxgbe_get_counter;
1656 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1657 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1658 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1659 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1662 ifp->if_capabilities = T4_CAP;
1663 ifp->if_capenable = T4_CAP_ENABLE;
1665 if (vi->nofldrxq != 0)
1666 ifp->if_capabilities |= IFCAP_TOE;
1669 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1670 ifp->if_capabilities |= IFCAP_TXRTLMT;
1671 ifp->if_capenable |= IFCAP_TXRTLMT;
1674 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1675 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1677 ifp->if_hw_tsomax = IP_MAXPACKET;
1678 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1680 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1681 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1683 ifp->if_hw_tsomaxsegsize = 65536;
1685 ether_ifattach(ifp, vi->hw_addr);
1687 if (vi->nnmrxq != 0)
1688 cxgbe_nm_attach(vi);
1690 sb = sbuf_new_auto();
1691 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1692 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1693 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1695 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1697 case IFCAP_TOE | IFCAP_TXRTLMT:
1698 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1701 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1706 if (ifp->if_capabilities & IFCAP_TOE)
1707 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1710 if (ifp->if_capabilities & IFCAP_NETMAP)
1711 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1712 vi->nnmtxq, vi->nnmrxq);
1715 device_printf(dev, "%s\n", sbuf_data(sb));
1724 cxgbe_attach(device_t dev)
1726 struct port_info *pi = device_get_softc(dev);
1727 struct adapter *sc = pi->adapter;
1731 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1733 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1737 for_each_vi(pi, i, vi) {
1740 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1741 if (vi->dev == NULL) {
1742 device_printf(dev, "failed to add VI %d\n", i);
1745 device_set_softc(vi->dev, vi);
1750 bus_generic_attach(dev);
1756 cxgbe_vi_detach(struct vi_info *vi)
1758 struct ifnet *ifp = vi->ifp;
1760 ether_ifdetach(ifp);
1762 /* Let detach proceed even if these fail. */
1764 if (ifp->if_capabilities & IFCAP_NETMAP)
1765 cxgbe_nm_detach(vi);
1767 cxgbe_uninit_synchronized(vi);
1768 callout_drain(&vi->tick);
1776 cxgbe_detach(device_t dev)
1778 struct port_info *pi = device_get_softc(dev);
1779 struct adapter *sc = pi->adapter;
1782 /* Detach the extra VIs first. */
1783 rc = bus_generic_detach(dev);
1786 device_delete_children(dev);
1788 doom_vi(sc, &pi->vi[0]);
1790 if (pi->flags & HAS_TRACEQ) {
1791 sc->traceq = -1; /* cloner should not create ifnet */
1792 t4_tracer_port_detach(sc);
1795 cxgbe_vi_detach(&pi->vi[0]);
1796 callout_drain(&pi->tick);
1797 ifmedia_removeall(&pi->media);
1799 end_synchronized_op(sc, 0);
1805 cxgbe_init(void *arg)
1807 struct vi_info *vi = arg;
1808 struct adapter *sc = vi->pi->adapter;
1810 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1812 cxgbe_init_synchronized(vi);
1813 end_synchronized_op(sc, 0);
1817 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1819 int rc = 0, mtu, flags;
1820 struct vi_info *vi = ifp->if_softc;
1821 struct port_info *pi = vi->pi;
1822 struct adapter *sc = pi->adapter;
1823 struct ifreq *ifr = (struct ifreq *)data;
1829 if (mtu < ETHERMIN || mtu > MAX_MTU)
1832 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1836 if (vi->flags & VI_INIT_DONE) {
1837 t4_update_fl_bufsize(ifp);
1838 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1839 rc = update_mac_settings(ifp, XGMAC_MTU);
1841 end_synchronized_op(sc, 0);
1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1849 if (ifp->if_flags & IFF_UP) {
1850 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1851 flags = vi->if_flags;
1852 if ((ifp->if_flags ^ flags) &
1853 (IFF_PROMISC | IFF_ALLMULTI)) {
1854 rc = update_mac_settings(ifp,
1855 XGMAC_PROMISC | XGMAC_ALLMULTI);
1858 rc = cxgbe_init_synchronized(vi);
1860 vi->if_flags = ifp->if_flags;
1861 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1862 rc = cxgbe_uninit_synchronized(vi);
1864 end_synchronized_op(sc, 0);
1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1873 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1874 end_synchronized_op(sc, 0);
1878 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1882 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1883 if (mask & IFCAP_TXCSUM) {
1884 ifp->if_capenable ^= IFCAP_TXCSUM;
1885 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1887 if (IFCAP_TSO4 & ifp->if_capenable &&
1888 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1889 ifp->if_capenable &= ~IFCAP_TSO4;
1891 "tso4 disabled due to -txcsum.\n");
1894 if (mask & IFCAP_TXCSUM_IPV6) {
1895 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1896 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1898 if (IFCAP_TSO6 & ifp->if_capenable &&
1899 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1900 ifp->if_capenable &= ~IFCAP_TSO6;
1902 "tso6 disabled due to -txcsum6.\n");
1905 if (mask & IFCAP_RXCSUM)
1906 ifp->if_capenable ^= IFCAP_RXCSUM;
1907 if (mask & IFCAP_RXCSUM_IPV6)
1908 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1911 * Note that we leave CSUM_TSO alone (it is always set). The
1912 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1913 * sending a TSO request our way, so it's sufficient to toggle
1916 if (mask & IFCAP_TSO4) {
1917 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1918 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1919 if_printf(ifp, "enable txcsum first.\n");
1923 ifp->if_capenable ^= IFCAP_TSO4;
1925 if (mask & IFCAP_TSO6) {
1926 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1927 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1928 if_printf(ifp, "enable txcsum6 first.\n");
1932 ifp->if_capenable ^= IFCAP_TSO6;
1934 if (mask & IFCAP_LRO) {
1935 #if defined(INET) || defined(INET6)
1937 struct sge_rxq *rxq;
1939 ifp->if_capenable ^= IFCAP_LRO;
1940 for_each_rxq(vi, i, rxq) {
1941 if (ifp->if_capenable & IFCAP_LRO)
1942 rxq->iq.flags |= IQ_LRO_ENABLED;
1944 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1949 if (mask & IFCAP_TOE) {
1950 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1952 rc = toe_capability(vi, enable);
1956 ifp->if_capenable ^= mask;
1959 if (mask & IFCAP_VLAN_HWTAGGING) {
1960 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1961 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1962 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1964 if (mask & IFCAP_VLAN_MTU) {
1965 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1967 /* Need to find out how to disable auto-mtu-inflation */
1969 if (mask & IFCAP_VLAN_HWTSO)
1970 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1971 if (mask & IFCAP_VLAN_HWCSUM)
1972 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1974 if (mask & IFCAP_TXRTLMT)
1975 ifp->if_capenable ^= IFCAP_TXRTLMT;
1977 if (mask & IFCAP_HWRXTSTMP) {
1979 struct sge_rxq *rxq;
1981 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
1982 for_each_rxq(vi, i, rxq) {
1983 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
1984 rxq->iq.flags |= IQ_RX_TIMESTAMP;
1986 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
1990 #ifdef VLAN_CAPABILITIES
1991 VLAN_CAPABILITIES(ifp);
1994 end_synchronized_op(sc, 0);
2000 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
2004 struct ifi2creq i2c;
2006 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2009 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2013 if (i2c.len > sizeof(i2c.data)) {
2017 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2020 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2021 i2c.offset, i2c.len, &i2c.data[0]);
2022 end_synchronized_op(sc, 0);
2024 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2029 rc = ether_ioctl(ifp, cmd, data);
2036 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2038 struct vi_info *vi = ifp->if_softc;
2039 struct port_info *pi = vi->pi;
2040 struct adapter *sc = pi->adapter;
2041 struct sge_txq *txq;
2046 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2048 if (__predict_false(pi->link_cfg.link_ok == false)) {
2053 rc = parse_pkt(sc, &m);
2054 if (__predict_false(rc != 0)) {
2055 MPASS(m == NULL); /* was freed already */
2056 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2060 if (m->m_pkthdr.snd_tag != NULL) {
2061 /* EAGAIN tells the stack we are not the correct interface. */
2062 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) {
2067 return (ethofld_transmit(ifp, m));
2072 txq = &sc->sge.txq[vi->first_txq];
2073 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2074 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2078 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2079 if (__predict_false(rc != 0))
2086 cxgbe_qflush(struct ifnet *ifp)
2088 struct vi_info *vi = ifp->if_softc;
2089 struct sge_txq *txq;
2092 /* queues do not exist if !VI_INIT_DONE. */
2093 if (vi->flags & VI_INIT_DONE) {
2094 for_each_txq(vi, i, txq) {
2096 txq->eq.flags |= EQ_QFLUSH;
2098 while (!mp_ring_is_idle(txq->r)) {
2099 mp_ring_check_drainage(txq->r, 0);
2103 txq->eq.flags &= ~EQ_QFLUSH;
2111 vi_get_counter(struct ifnet *ifp, ift_counter c)
2113 struct vi_info *vi = ifp->if_softc;
2114 struct fw_vi_stats_vf *s = &vi->stats;
2116 vi_refresh_stats(vi->pi->adapter, vi);
2119 case IFCOUNTER_IPACKETS:
2120 return (s->rx_bcast_frames + s->rx_mcast_frames +
2121 s->rx_ucast_frames);
2122 case IFCOUNTER_IERRORS:
2123 return (s->rx_err_frames);
2124 case IFCOUNTER_OPACKETS:
2125 return (s->tx_bcast_frames + s->tx_mcast_frames +
2126 s->tx_ucast_frames + s->tx_offload_frames);
2127 case IFCOUNTER_OERRORS:
2128 return (s->tx_drop_frames);
2129 case IFCOUNTER_IBYTES:
2130 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2132 case IFCOUNTER_OBYTES:
2133 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2134 s->tx_ucast_bytes + s->tx_offload_bytes);
2135 case IFCOUNTER_IMCASTS:
2136 return (s->rx_mcast_frames);
2137 case IFCOUNTER_OMCASTS:
2138 return (s->tx_mcast_frames);
2139 case IFCOUNTER_OQDROPS: {
2143 if (vi->flags & VI_INIT_DONE) {
2145 struct sge_txq *txq;
2147 for_each_txq(vi, i, txq)
2148 drops += counter_u64_fetch(txq->r->drops);
2156 return (if_get_counter_default(ifp, c));
2161 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2163 struct vi_info *vi = ifp->if_softc;
2164 struct port_info *pi = vi->pi;
2165 struct adapter *sc = pi->adapter;
2166 struct port_stats *s = &pi->stats;
2168 if (pi->nvi > 1 || sc->flags & IS_VF)
2169 return (vi_get_counter(ifp, c));
2171 cxgbe_refresh_stats(sc, pi);
2174 case IFCOUNTER_IPACKETS:
2175 return (s->rx_frames);
2177 case IFCOUNTER_IERRORS:
2178 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2179 s->rx_fcs_err + s->rx_len_err);
2181 case IFCOUNTER_OPACKETS:
2182 return (s->tx_frames);
2184 case IFCOUNTER_OERRORS:
2185 return (s->tx_error_frames);
2187 case IFCOUNTER_IBYTES:
2188 return (s->rx_octets);
2190 case IFCOUNTER_OBYTES:
2191 return (s->tx_octets);
2193 case IFCOUNTER_IMCASTS:
2194 return (s->rx_mcast_frames);
2196 case IFCOUNTER_OMCASTS:
2197 return (s->tx_mcast_frames);
2199 case IFCOUNTER_IQDROPS:
2200 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2201 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2202 s->rx_trunc3 + pi->tnl_cong_drops);
2204 case IFCOUNTER_OQDROPS: {
2208 if (vi->flags & VI_INIT_DONE) {
2210 struct sge_txq *txq;
2212 for_each_txq(vi, i, txq)
2213 drops += counter_u64_fetch(txq->r->drops);
2221 return (if_get_counter_default(ifp, c));
2226 * The kernel picks a media from the list we had provided but we still validate
2230 cxgbe_media_change(struct ifnet *ifp)
2232 struct vi_info *vi = ifp->if_softc;
2233 struct port_info *pi = vi->pi;
2234 struct ifmedia *ifm = &pi->media;
2235 struct link_config *lc = &pi->link_cfg;
2236 struct adapter *sc = pi->adapter;
2239 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2243 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2244 /* ifconfig .. media autoselect */
2245 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2246 rc = ENOTSUP; /* AN not supported by transceiver */
2249 lc->requested_aneg = AUTONEG_ENABLE;
2250 lc->requested_speed = 0;
2251 lc->requested_fc |= PAUSE_AUTONEG;
2253 lc->requested_aneg = AUTONEG_DISABLE;
2254 lc->requested_speed =
2255 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2256 lc->requested_fc = 0;
2257 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2258 lc->requested_fc |= PAUSE_RX;
2259 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2260 lc->requested_fc |= PAUSE_TX;
2262 if (pi->up_vis > 0) {
2263 fixup_link_config(pi);
2264 rc = apply_link_config(pi);
2268 end_synchronized_op(sc, 0);
2273 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2277 port_mword(struct port_info *pi, uint32_t speed)
2280 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2281 MPASS(powerof2(speed));
2283 switch(pi->port_type) {
2284 case FW_PORT_TYPE_BT_SGMII:
2285 case FW_PORT_TYPE_BT_XFI:
2286 case FW_PORT_TYPE_BT_XAUI:
2289 case FW_PORT_CAP32_SPEED_100M:
2291 case FW_PORT_CAP32_SPEED_1G:
2292 return (IFM_1000_T);
2293 case FW_PORT_CAP32_SPEED_10G:
2297 case FW_PORT_TYPE_KX4:
2298 if (speed == FW_PORT_CAP32_SPEED_10G)
2299 return (IFM_10G_KX4);
2301 case FW_PORT_TYPE_CX4:
2302 if (speed == FW_PORT_CAP32_SPEED_10G)
2303 return (IFM_10G_CX4);
2305 case FW_PORT_TYPE_KX:
2306 if (speed == FW_PORT_CAP32_SPEED_1G)
2307 return (IFM_1000_KX);
2309 case FW_PORT_TYPE_KR:
2310 case FW_PORT_TYPE_BP_AP:
2311 case FW_PORT_TYPE_BP4_AP:
2312 case FW_PORT_TYPE_BP40_BA:
2313 case FW_PORT_TYPE_KR4_100G:
2314 case FW_PORT_TYPE_KR_SFP28:
2315 case FW_PORT_TYPE_KR_XLAUI:
2317 case FW_PORT_CAP32_SPEED_1G:
2318 return (IFM_1000_KX);
2319 case FW_PORT_CAP32_SPEED_10G:
2320 return (IFM_10G_KR);
2321 case FW_PORT_CAP32_SPEED_25G:
2322 return (IFM_25G_KR);
2323 case FW_PORT_CAP32_SPEED_40G:
2324 return (IFM_40G_KR4);
2325 case FW_PORT_CAP32_SPEED_50G:
2326 return (IFM_50G_KR2);
2327 case FW_PORT_CAP32_SPEED_100G:
2328 return (IFM_100G_KR4);
2331 case FW_PORT_TYPE_FIBER_XFI:
2332 case FW_PORT_TYPE_FIBER_XAUI:
2333 case FW_PORT_TYPE_SFP:
2334 case FW_PORT_TYPE_QSFP_10G:
2335 case FW_PORT_TYPE_QSA:
2336 case FW_PORT_TYPE_QSFP:
2337 case FW_PORT_TYPE_CR4_QSFP:
2338 case FW_PORT_TYPE_CR_QSFP:
2339 case FW_PORT_TYPE_CR2_QSFP:
2340 case FW_PORT_TYPE_SFP28:
2341 /* Pluggable transceiver */
2342 switch (pi->mod_type) {
2343 case FW_PORT_MOD_TYPE_LR:
2345 case FW_PORT_CAP32_SPEED_1G:
2346 return (IFM_1000_LX);
2347 case FW_PORT_CAP32_SPEED_10G:
2348 return (IFM_10G_LR);
2349 case FW_PORT_CAP32_SPEED_25G:
2350 return (IFM_25G_LR);
2351 case FW_PORT_CAP32_SPEED_40G:
2352 return (IFM_40G_LR4);
2353 case FW_PORT_CAP32_SPEED_50G:
2354 return (IFM_50G_LR2);
2355 case FW_PORT_CAP32_SPEED_100G:
2356 return (IFM_100G_LR4);
2359 case FW_PORT_MOD_TYPE_SR:
2361 case FW_PORT_CAP32_SPEED_1G:
2362 return (IFM_1000_SX);
2363 case FW_PORT_CAP32_SPEED_10G:
2364 return (IFM_10G_SR);
2365 case FW_PORT_CAP32_SPEED_25G:
2366 return (IFM_25G_SR);
2367 case FW_PORT_CAP32_SPEED_40G:
2368 return (IFM_40G_SR4);
2369 case FW_PORT_CAP32_SPEED_50G:
2370 return (IFM_50G_SR2);
2371 case FW_PORT_CAP32_SPEED_100G:
2372 return (IFM_100G_SR4);
2375 case FW_PORT_MOD_TYPE_ER:
2376 if (speed == FW_PORT_CAP32_SPEED_10G)
2377 return (IFM_10G_ER);
2379 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2380 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2382 case FW_PORT_CAP32_SPEED_1G:
2383 return (IFM_1000_CX);
2384 case FW_PORT_CAP32_SPEED_10G:
2385 return (IFM_10G_TWINAX);
2386 case FW_PORT_CAP32_SPEED_25G:
2387 return (IFM_25G_CR);
2388 case FW_PORT_CAP32_SPEED_40G:
2389 return (IFM_40G_CR4);
2390 case FW_PORT_CAP32_SPEED_50G:
2391 return (IFM_50G_CR2);
2392 case FW_PORT_CAP32_SPEED_100G:
2393 return (IFM_100G_CR4);
2396 case FW_PORT_MOD_TYPE_LRM:
2397 if (speed == FW_PORT_CAP32_SPEED_10G)
2398 return (IFM_10G_LRM);
2400 case FW_PORT_MOD_TYPE_NA:
2401 MPASS(0); /* Not pluggable? */
2403 case FW_PORT_MOD_TYPE_ERROR:
2404 case FW_PORT_MOD_TYPE_UNKNOWN:
2405 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2407 case FW_PORT_MOD_TYPE_NONE:
2411 case FW_PORT_TYPE_NONE:
2415 return (IFM_UNKNOWN);
2419 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2421 struct vi_info *vi = ifp->if_softc;
2422 struct port_info *pi = vi->pi;
2423 struct adapter *sc = pi->adapter;
2424 struct link_config *lc = &pi->link_cfg;
2426 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2430 if (pi->up_vis == 0) {
2432 * If all the interfaces are administratively down the firmware
2433 * does not report transceiver changes. Refresh port info here
2434 * so that ifconfig displays accurate ifmedia at all times.
2435 * This is the only reason we have a synchronized op in this
2436 * function. Just PORT_LOCK would have been enough otherwise.
2438 t4_update_port_info(pi);
2439 build_medialist(pi);
2443 ifmr->ifm_status = IFM_AVALID;
2444 if (lc->link_ok == false)
2446 ifmr->ifm_status |= IFM_ACTIVE;
2449 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2450 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2451 if (lc->fc & PAUSE_RX)
2452 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2453 if (lc->fc & PAUSE_TX)
2454 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2455 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2458 end_synchronized_op(sc, 0);
2462 vcxgbe_probe(device_t dev)
2465 struct vi_info *vi = device_get_softc(dev);
2467 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2469 device_set_desc_copy(dev, buf);
2471 return (BUS_PROBE_DEFAULT);
2475 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2477 int func, index, rc;
2478 uint32_t param, val;
2480 ASSERT_SYNCHRONIZED_OP(sc);
2482 index = vi - pi->vi;
2483 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2484 KASSERT(index < nitems(vi_mac_funcs),
2485 ("%s: VI %s doesn't have a MAC func", __func__,
2486 device_get_nameunit(vi->dev)));
2487 func = vi_mac_funcs[index];
2488 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2489 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
2491 device_printf(vi->dev, "failed to allocate virtual interface %d"
2492 "for port %d: %d\n", index, pi->port_id, -rc);
2497 if (vi->rss_size == 1) {
2499 * This VI didn't get a slice of the RSS table. Reduce the
2500 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2501 * configuration file (nvi, rssnvi for this PF) if this is a
2504 device_printf(vi->dev, "RSS table not available.\n");
2505 vi->rss_base = 0xffff;
2510 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2511 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2512 V_FW_PARAMS_PARAM_YZ(vi->viid);
2513 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2515 vi->rss_base = 0xffff;
2517 MPASS((val >> 16) == vi->rss_size);
2518 vi->rss_base = val & 0xffff;
2525 vcxgbe_attach(device_t dev)
2528 struct port_info *pi;
2532 vi = device_get_softc(dev);
2536 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2539 rc = alloc_extra_vi(sc, pi, vi);
2540 end_synchronized_op(sc, 0);
2544 rc = cxgbe_vi_attach(dev, vi);
2546 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2553 vcxgbe_detach(device_t dev)
2558 vi = device_get_softc(dev);
2559 sc = vi->pi->adapter;
2563 cxgbe_vi_detach(vi);
2564 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2566 end_synchronized_op(sc, 0);
2571 static struct callout fatal_callout;
2574 delayed_panic(void *arg)
2576 struct adapter *sc = arg;
2578 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
2582 t4_fatal_err(struct adapter *sc, bool fw_error)
2585 t4_shutdown_adapter(sc);
2586 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2587 device_get_nameunit(sc->dev));
2589 ASSERT_SYNCHRONIZED_OP(sc);
2590 sc->flags |= ADAP_ERR;
2593 sc->flags |= ADAP_ERR;
2597 if (t4_panic_on_fatal_err) {
2598 log(LOG_ALERT, "%s: panic on fatal error after 30s",
2599 device_get_nameunit(sc->dev));
2600 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
2605 t4_add_adapter(struct adapter *sc)
2607 sx_xlock(&t4_list_lock);
2608 SLIST_INSERT_HEAD(&t4_list, sc, link);
2609 sx_xunlock(&t4_list_lock);
2613 t4_map_bars_0_and_4(struct adapter *sc)
2615 sc->regs_rid = PCIR_BAR(0);
2616 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2617 &sc->regs_rid, RF_ACTIVE);
2618 if (sc->regs_res == NULL) {
2619 device_printf(sc->dev, "cannot map registers.\n");
2622 sc->bt = rman_get_bustag(sc->regs_res);
2623 sc->bh = rman_get_bushandle(sc->regs_res);
2624 sc->mmio_len = rman_get_size(sc->regs_res);
2625 setbit(&sc->doorbells, DOORBELL_KDB);
2627 sc->msix_rid = PCIR_BAR(4);
2628 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2629 &sc->msix_rid, RF_ACTIVE);
2630 if (sc->msix_res == NULL) {
2631 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2639 t4_map_bar_2(struct adapter *sc)
2643 * T4: only iWARP driver uses the userspace doorbells. There is no need
2644 * to map it if RDMA is disabled.
2646 if (is_t4(sc) && sc->rdmacaps == 0)
2649 sc->udbs_rid = PCIR_BAR(2);
2650 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2651 &sc->udbs_rid, RF_ACTIVE);
2652 if (sc->udbs_res == NULL) {
2653 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2656 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2658 if (chip_id(sc) >= CHELSIO_T5) {
2659 setbit(&sc->doorbells, DOORBELL_UDB);
2660 #if defined(__i386__) || defined(__amd64__)
2661 if (t5_write_combine) {
2665 * Enable write combining on BAR2. This is the
2666 * userspace doorbell BAR and is split into 128B
2667 * (UDBS_SEG_SIZE) doorbell regions, each associated
2668 * with an egress queue. The first 64B has the doorbell
2669 * and the second 64B can be used to submit a tx work
2670 * request with an implicit doorbell.
2673 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2674 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2676 clrbit(&sc->doorbells, DOORBELL_UDB);
2677 setbit(&sc->doorbells, DOORBELL_WCWR);
2678 setbit(&sc->doorbells, DOORBELL_UDBWC);
2680 device_printf(sc->dev,
2681 "couldn't enable write combining: %d\n",
2685 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2686 t4_write_reg(sc, A_SGE_STAT_CFG,
2687 V_STATSOURCE_T5(7) | mode);
2691 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2696 struct memwin_init {
2701 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2702 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2703 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2704 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2707 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2708 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2709 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2710 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2714 setup_memwin(struct adapter *sc)
2716 const struct memwin_init *mw_init;
2723 * Read low 32b of bar0 indirectly via the hardware backdoor
2724 * mechanism. Works from within PCI passthrough environments
2725 * too, where rman_get_start() can return a different value. We
2726 * need to program the T4 memory window decoders with the actual
2727 * addresses that will be coming across the PCIe link.
2729 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2730 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2732 mw_init = &t4_memwin[0];
2734 /* T5+ use the relative offset inside the PCIe BAR */
2737 mw_init = &t5_memwin[0];
2740 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2741 rw_init(&mw->mw_lock, "memory window access");
2742 mw->mw_base = mw_init->base;
2743 mw->mw_aperture = mw_init->aperture;
2746 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2747 (mw->mw_base + bar0) | V_BIR(0) |
2748 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2749 rw_wlock(&mw->mw_lock);
2750 position_memwin(sc, i, 0);
2751 rw_wunlock(&mw->mw_lock);
2755 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2759 * Positions the memory window at the given address in the card's address space.
2760 * There are some alignment requirements and the actual position may be at an
2761 * address prior to the requested address. mw->mw_curpos always has the actual
2762 * position of the window.
2765 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2771 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2772 mw = &sc->memwin[idx];
2773 rw_assert(&mw->mw_lock, RA_WLOCKED);
2777 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2779 pf = V_PFNUM(sc->pf);
2780 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2782 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2783 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2784 t4_read_reg(sc, reg); /* flush */
2788 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2794 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2796 /* Memory can only be accessed in naturally aligned 4 byte units */
2797 if (addr & 3 || len & 3 || len <= 0)
2800 mw = &sc->memwin[idx];
2802 rw_rlock(&mw->mw_lock);
2803 mw_end = mw->mw_curpos + mw->mw_aperture;
2804 if (addr >= mw_end || addr < mw->mw_curpos) {
2805 /* Will need to reposition the window */
2806 if (!rw_try_upgrade(&mw->mw_lock)) {
2807 rw_runlock(&mw->mw_lock);
2808 rw_wlock(&mw->mw_lock);
2810 rw_assert(&mw->mw_lock, RA_WLOCKED);
2811 position_memwin(sc, idx, addr);
2812 rw_downgrade(&mw->mw_lock);
2813 mw_end = mw->mw_curpos + mw->mw_aperture;
2815 rw_assert(&mw->mw_lock, RA_RLOCKED);
2816 while (addr < mw_end && len > 0) {
2818 v = t4_read_reg(sc, mw->mw_base + addr -
2820 *val++ = le32toh(v);
2823 t4_write_reg(sc, mw->mw_base + addr -
2824 mw->mw_curpos, htole32(v));
2829 rw_runlock(&mw->mw_lock);
2836 alloc_atid_tab(struct tid_info *t, int flags)
2840 MPASS(t->natids > 0);
2841 MPASS(t->atid_tab == NULL);
2843 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2845 if (t->atid_tab == NULL)
2847 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2848 t->afree = t->atid_tab;
2849 t->atids_in_use = 0;
2850 for (i = 1; i < t->natids; i++)
2851 t->atid_tab[i - 1].next = &t->atid_tab[i];
2852 t->atid_tab[t->natids - 1].next = NULL;
2858 free_atid_tab(struct tid_info *t)
2861 KASSERT(t->atids_in_use == 0,
2862 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2864 if (mtx_initialized(&t->atid_lock))
2865 mtx_destroy(&t->atid_lock);
2866 free(t->atid_tab, M_CXGBE);
2871 alloc_atid(struct adapter *sc, void *ctx)
2873 struct tid_info *t = &sc->tids;
2876 mtx_lock(&t->atid_lock);
2878 union aopen_entry *p = t->afree;
2880 atid = p - t->atid_tab;
2881 MPASS(atid <= M_TID_TID);
2886 mtx_unlock(&t->atid_lock);
2891 lookup_atid(struct adapter *sc, int atid)
2893 struct tid_info *t = &sc->tids;
2895 return (t->atid_tab[atid].data);
2899 free_atid(struct adapter *sc, int atid)
2901 struct tid_info *t = &sc->tids;
2902 union aopen_entry *p = &t->atid_tab[atid];
2904 mtx_lock(&t->atid_lock);
2908 mtx_unlock(&t->atid_lock);
2912 queue_tid_release(struct adapter *sc, int tid)
2915 CXGBE_UNIMPLEMENTED("deferred tid release");
2919 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
2922 struct cpl_tid_release *req;
2924 wr = alloc_wrqe(sizeof(*req), ctrlq);
2926 queue_tid_release(sc, tid); /* defer */
2931 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
2937 t4_range_cmp(const void *a, const void *b)
2939 return ((const struct t4_range *)a)->start -
2940 ((const struct t4_range *)b)->start;
2944 * Verify that the memory range specified by the addr/len pair is valid within
2945 * the card's address space.
2948 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2950 struct t4_range mem_ranges[4], *r, *next;
2951 uint32_t em, addr_len;
2952 int i, n, remaining;
2954 /* Memory can only be accessed in naturally aligned 4 byte units */
2955 if (addr & 3 || len & 3 || len == 0)
2958 /* Enabled memories */
2959 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2963 bzero(r, sizeof(mem_ranges));
2964 if (em & F_EDRAM0_ENABLE) {
2965 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2966 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2968 r->start = G_EDRAM0_BASE(addr_len) << 20;
2969 if (addr >= r->start &&
2970 addr + len <= r->start + r->size)
2976 if (em & F_EDRAM1_ENABLE) {
2977 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2978 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2980 r->start = G_EDRAM1_BASE(addr_len) << 20;
2981 if (addr >= r->start &&
2982 addr + len <= r->start + r->size)
2988 if (em & F_EXT_MEM_ENABLE) {
2989 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2990 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2992 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2993 if (addr >= r->start &&
2994 addr + len <= r->start + r->size)
3000 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
3001 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3002 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
3004 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
3005 if (addr >= r->start &&
3006 addr + len <= r->start + r->size)
3012 MPASS(n <= nitems(mem_ranges));
3015 /* Sort and merge the ranges. */
3016 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3018 /* Start from index 0 and examine the next n - 1 entries. */
3020 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3022 MPASS(r->size > 0); /* r is a valid entry. */
3024 MPASS(next->size > 0); /* and so is the next one. */
3026 while (r->start + r->size >= next->start) {
3027 /* Merge the next one into the current entry. */
3028 r->size = max(r->start + r->size,
3029 next->start + next->size) - r->start;
3030 n--; /* One fewer entry in total. */
3031 if (--remaining == 0)
3032 goto done; /* short circuit */
3035 if (next != r + 1) {
3037 * Some entries were merged into r and next
3038 * points to the first valid entry that couldn't
3041 MPASS(next->size > 0); /* must be valid */
3042 memcpy(r + 1, next, remaining * sizeof(*r));
3045 * This so that the foo->size assertion in the
3046 * next iteration of the loop do the right
3047 * thing for entries that were pulled up and are
3050 MPASS(n < nitems(mem_ranges));
3051 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3052 sizeof(struct t4_range));
3057 /* Done merging the ranges. */
3060 for (i = 0; i < n; i++, r++) {
3061 if (addr >= r->start &&
3062 addr + len <= r->start + r->size)
3071 fwmtype_to_hwmtype(int mtype)
3075 case FW_MEMTYPE_EDC0:
3077 case FW_MEMTYPE_EDC1:
3079 case FW_MEMTYPE_EXTMEM:
3081 case FW_MEMTYPE_EXTMEM1:
3084 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3089 * Verify that the memory range specified by the memtype/offset/len pair is
3090 * valid and lies entirely within the memtype specified. The global address of
3091 * the start of the range is returned in addr.
3094 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3097 uint32_t em, addr_len, maddr;
3099 /* Memory can only be accessed in naturally aligned 4 byte units */
3100 if (off & 3 || len & 3 || len == 0)
3103 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3104 switch (fwmtype_to_hwmtype(mtype)) {
3106 if (!(em & F_EDRAM0_ENABLE))
3108 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3109 maddr = G_EDRAM0_BASE(addr_len) << 20;
3112 if (!(em & F_EDRAM1_ENABLE))
3114 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3115 maddr = G_EDRAM1_BASE(addr_len) << 20;
3118 if (!(em & F_EXT_MEM_ENABLE))
3120 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3121 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3124 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3126 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3127 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3133 *addr = maddr + off; /* global address */
3134 return (validate_mem_range(sc, *addr, len));
3138 fixup_devlog_params(struct adapter *sc)
3140 struct devlog_params *dparams = &sc->params.devlog;
3143 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3144 dparams->size, &dparams->addr);
3150 update_nirq(struct intrs_and_queues *iaq, int nports)
3152 int extra = T4_EXTRA_INTR;
3155 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
3156 iaq->nirq += nports * (iaq->num_vis - 1) *
3157 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3158 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3162 * Adjust requirements to fit the number of interrupts available.
3165 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3169 const int nports = sc->params.nports;
3174 bzero(iaq, sizeof(*iaq));
3175 iaq->intr_type = itype;
3176 iaq->num_vis = t4_num_vis;
3177 iaq->ntxq = t4_ntxq;
3178 iaq->ntxq_vi = t4_ntxq_vi;
3179 iaq->nrxq = t4_nrxq;
3180 iaq->nrxq_vi = t4_nrxq_vi;
3181 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3182 if (is_offload(sc) || is_ethoffload(sc)) {
3183 iaq->nofldtxq = t4_nofldtxq;
3184 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3188 if (is_offload(sc)) {
3189 iaq->nofldrxq = t4_nofldrxq;
3190 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3194 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3195 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3198 update_nirq(iaq, nports);
3199 if (iaq->nirq <= navail &&
3200 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3202 * This is the normal case -- there are enough interrupts for
3209 * If extra VIs have been configured try reducing their count and see if
3212 while (iaq->num_vis > 1) {
3214 update_nirq(iaq, nports);
3215 if (iaq->nirq <= navail &&
3216 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3217 device_printf(sc->dev, "virtual interfaces per port "
3218 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3219 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3220 "itype %d, navail %u, nirq %d.\n",
3221 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3222 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3223 itype, navail, iaq->nirq);
3229 * Extra VIs will not be created. Log a message if they were requested.
3231 MPASS(iaq->num_vis == 1);
3232 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3233 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3234 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3235 if (iaq->num_vis != t4_num_vis) {
3236 device_printf(sc->dev, "extra virtual interfaces disabled. "
3237 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3238 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3239 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3240 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3244 * Keep reducing the number of NIC rx queues to the next lower power of
3245 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3249 if (iaq->nrxq > 1) {
3252 } while (!powerof2(iaq->nrxq));
3254 if (iaq->nofldrxq > 1)
3255 iaq->nofldrxq >>= 1;
3257 old_nirq = iaq->nirq;
3258 update_nirq(iaq, nports);
3259 if (iaq->nirq <= navail &&
3260 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3261 device_printf(sc->dev, "running with reduced number of "
3262 "rx queues because of shortage of interrupts. "
3263 "nrxq=%u, nofldrxq=%u. "
3264 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3265 iaq->nofldrxq, itype, navail, iaq->nirq);
3268 } while (old_nirq != iaq->nirq);
3270 /* One interrupt for everything. Ugh. */
3271 device_printf(sc->dev, "running with minimal number of queues. "
3272 "itype %d, navail %u.\n", itype, navail);
3274 MPASS(iaq->nrxq == 1);
3276 if (iaq->nofldrxq > 1)
3279 MPASS(iaq->num_vis > 0);
3280 if (iaq->num_vis > 1) {
3281 MPASS(iaq->nrxq_vi > 0);
3282 MPASS(iaq->ntxq_vi > 0);
3284 MPASS(iaq->nirq > 0);
3285 MPASS(iaq->nrxq > 0);
3286 MPASS(iaq->ntxq > 0);
3287 if (itype == INTR_MSI) {
3288 MPASS(powerof2(iaq->nirq));
3293 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3295 int rc, itype, navail, nalloc;
3297 for (itype = INTR_MSIX; itype; itype >>= 1) {
3299 if ((itype & t4_intr_types) == 0)
3300 continue; /* not allowed */
3302 if (itype == INTR_MSIX)
3303 navail = pci_msix_count(sc->dev);
3304 else if (itype == INTR_MSI)
3305 navail = pci_msi_count(sc->dev);
3312 calculate_iaq(sc, iaq, itype, navail);
3315 if (itype == INTR_MSIX)
3316 rc = pci_alloc_msix(sc->dev, &nalloc);
3317 else if (itype == INTR_MSI)
3318 rc = pci_alloc_msi(sc->dev, &nalloc);
3320 if (rc == 0 && nalloc > 0) {
3321 if (nalloc == iaq->nirq)
3325 * Didn't get the number requested. Use whatever number
3326 * the kernel is willing to allocate.
3328 device_printf(sc->dev, "fewer vectors than requested, "
3329 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3330 itype, iaq->nirq, nalloc);
3331 pci_release_msi(sc->dev);
3336 device_printf(sc->dev,
3337 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3338 itype, rc, iaq->nirq, nalloc);
3341 device_printf(sc->dev,
3342 "failed to find a usable interrupt type. "
3343 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3344 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3349 #define FW_VERSION(chip) ( \
3350 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3351 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3352 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3353 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3354 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3356 /* Just enough of fw_hdr to cover all version info. */
3362 __be32 tp_microcode_ver;
3367 __u8 intfver_iscsipdu;
3369 __u8 intfver_fcoepdu;
3372 /* Spot check a couple of fields. */
3373 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3374 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3375 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3385 .kld_name = "t4fw_cfg",
3386 .fw_mod_name = "t4fw",
3388 .chip = FW_HDR_CHIP_T4,
3389 .fw_ver = htobe32(FW_VERSION(T4)),
3390 .intfver_nic = FW_INTFVER(T4, NIC),
3391 .intfver_vnic = FW_INTFVER(T4, VNIC),
3392 .intfver_ofld = FW_INTFVER(T4, OFLD),
3393 .intfver_ri = FW_INTFVER(T4, RI),
3394 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3395 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3396 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3397 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3401 .kld_name = "t5fw_cfg",
3402 .fw_mod_name = "t5fw",
3404 .chip = FW_HDR_CHIP_T5,
3405 .fw_ver = htobe32(FW_VERSION(T5)),
3406 .intfver_nic = FW_INTFVER(T5, NIC),
3407 .intfver_vnic = FW_INTFVER(T5, VNIC),
3408 .intfver_ofld = FW_INTFVER(T5, OFLD),
3409 .intfver_ri = FW_INTFVER(T5, RI),
3410 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3411 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3412 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3413 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3417 .kld_name = "t6fw_cfg",
3418 .fw_mod_name = "t6fw",
3420 .chip = FW_HDR_CHIP_T6,
3421 .fw_ver = htobe32(FW_VERSION(T6)),
3422 .intfver_nic = FW_INTFVER(T6, NIC),
3423 .intfver_vnic = FW_INTFVER(T6, VNIC),
3424 .intfver_ofld = FW_INTFVER(T6, OFLD),
3425 .intfver_ri = FW_INTFVER(T6, RI),
3426 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3427 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3428 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3429 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3434 static struct fw_info *
3435 find_fw_info(int chip)
3439 for (i = 0; i < nitems(fw_info); i++) {
3440 if (fw_info[i].chip == chip)
3441 return (&fw_info[i]);
3447 * Is the given firmware API compatible with the one the driver was compiled
3451 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3454 /* short circuit if it's the exact same firmware version */
3455 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3459 * XXX: Is this too conservative? Perhaps I should limit this to the
3460 * features that are supported in the driver.
3462 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3463 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3464 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3465 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3473 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3474 const struct firmware **fw)
3476 struct fw_info *fw_info;
3482 fw_info = find_fw_info(chip_id(sc));
3483 if (fw_info == NULL) {
3484 device_printf(sc->dev,
3485 "unable to look up firmware information for chip %d.\n",
3490 *dcfg = firmware_get(fw_info->kld_name);
3491 if (*dcfg != NULL) {
3493 *fw = firmware_get(fw_info->fw_mod_name);
3501 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3502 const struct firmware *fw)
3506 firmware_put(fw, FIRMWARE_UNLOAD);
3508 firmware_put(dcfg, FIRMWARE_UNLOAD);
3513 * 0 means no firmware install attempted.
3514 * ERESTART means a firmware install was attempted and was successful.
3515 * +ve errno means a firmware install was attempted but failed.
3518 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3519 const struct fw_h *drv_fw, const char *reason, int *already)
3521 const struct firmware *cfg, *fw;
3522 const uint32_t c = be32toh(card_fw->fw_ver);
3525 struct fw_h bundled_fw;
3526 bool load_attempted;
3529 load_attempted = false;
3530 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3532 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3533 if (t4_fw_install < 0) {
3534 rc = load_fw_module(sc, &cfg, &fw);
3535 if (rc != 0 || fw == NULL) {
3536 device_printf(sc->dev,
3537 "failed to load firmware module: %d. cfg %p, fw %p;"
3538 " will use compiled-in firmware version for"
3539 "hw.cxgbe.fw_install checks.\n",
3542 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3544 load_attempted = true;
3546 d = be32toh(bundled_fw.fw_ver);
3551 if ((sc->flags & FW_OK) == 0) {
3553 if (c == 0xffffffff) {
3562 if (!fw_compatible(card_fw, &bundled_fw)) {
3563 reason = "incompatible or unusable";
3568 reason = "older than the version bundled with this driver";
3572 if (fw_install == 2 && d != c) {
3573 reason = "different than the version bundled with this driver";
3577 /* No reason to do anything to the firmware already on the card. */
3586 if (fw_install == 0) {
3587 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3588 "but the driver is prohibited from installing a firmware "
3590 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3591 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3597 * We'll attempt to install a firmware. Load the module first (if it
3598 * hasn't been loaded already).
3600 if (!load_attempted) {
3601 rc = load_fw_module(sc, &cfg, &fw);
3602 if (rc != 0 || fw == NULL) {
3603 device_printf(sc->dev,
3604 "failed to load firmware module: %d. cfg %p, fw %p\n",
3610 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3611 "but the driver cannot take corrective action because it "
3612 "is unable to load the firmware module.\n",
3613 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3614 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3615 rc = sc->flags & FW_OK ? 0 : ENOENT;
3618 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3620 MPASS(t4_fw_install > 0);
3621 device_printf(sc->dev,
3622 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3623 "expecting (%u.%u.%u.%u) and will not be used.\n",
3624 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3625 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3626 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3627 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3628 rc = sc->flags & FW_OK ? 0 : EINVAL;
3632 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3633 "installing firmware %u.%u.%u.%u on card.\n",
3634 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3635 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3636 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3637 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3639 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3641 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3643 /* Installed successfully, update the cached header too. */
3645 memcpy(card_fw, fw->data, sizeof(*card_fw));
3648 unload_fw_module(sc, cfg, fw);
3654 * Establish contact with the firmware and attempt to become the master driver.
3656 * A firmware will be installed to the card if needed (if the driver is allowed
3660 contact_firmware(struct adapter *sc)
3662 int rc, already = 0;
3663 enum dev_state state;
3664 struct fw_info *fw_info;
3665 struct fw_hdr *card_fw; /* fw on the card */
3666 const struct fw_h *drv_fw;
3668 fw_info = find_fw_info(chip_id(sc));
3669 if (fw_info == NULL) {
3670 device_printf(sc->dev,
3671 "unable to look up firmware information for chip %d.\n",
3675 drv_fw = &fw_info->fw_h;
3677 /* Read the header of the firmware on the card */
3678 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3680 rc = -t4_get_fw_hdr(sc, card_fw);
3682 device_printf(sc->dev,
3683 "unable to read firmware header from card's flash: %d\n",
3688 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3695 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3696 if (rc < 0 || state == DEV_STATE_ERR) {
3698 device_printf(sc->dev,
3699 "failed to connect to the firmware: %d, %d. "
3700 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3702 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3703 "not responding properly to HELLO", &already) == ERESTART)
3708 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3709 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3712 sc->flags |= MASTER_PF;
3713 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3719 } else if (state == DEV_STATE_UNINIT) {
3721 * We didn't get to be the master so we definitely won't be
3722 * configuring the chip. It's a bug if someone else hasn't
3723 * configured it already.
3725 device_printf(sc->dev, "couldn't be master(%d), "
3726 "device not already initialized either(%d). "
3727 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3732 * Some other PF is the master and has configured the chip.
3733 * This is allowed but untested.
3735 device_printf(sc->dev, "PF%d is master, device state %d. "
3736 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3737 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3742 if (rc != 0 && sc->flags & FW_OK) {
3743 t4_fw_bye(sc, sc->mbox);
3744 sc->flags &= ~FW_OK;
3746 free(card_fw, M_CXGBE);
3751 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3752 uint32_t mtype, uint32_t moff)
3754 struct fw_info *fw_info;
3755 const struct firmware *dcfg, *rcfg = NULL;
3756 const uint32_t *cfdata;
3757 uint32_t cflen, addr;
3760 load_fw_module(sc, &dcfg, NULL);
3762 /* Card specific interpretation of "default". */
3763 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3764 if (pci_get_device(sc->dev) == 0x440a)
3765 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3767 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3770 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3772 device_printf(sc->dev,
3773 "KLD with default config is not available.\n");
3777 cfdata = dcfg->data;
3778 cflen = dcfg->datasize & ~3;
3782 fw_info = find_fw_info(chip_id(sc));
3783 if (fw_info == NULL) {
3784 device_printf(sc->dev,
3785 "unable to look up firmware information for chip %d.\n",
3790 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
3792 rcfg = firmware_get(s);
3794 device_printf(sc->dev,
3795 "unable to load module \"%s\" for configuration "
3796 "profile \"%s\".\n", s, cfg_file);
3800 cfdata = rcfg->data;
3801 cflen = rcfg->datasize & ~3;
3804 if (cflen > FLASH_CFG_MAX_SIZE) {
3805 device_printf(sc->dev,
3806 "config file too long (%d, max allowed is %d).\n",
3807 cflen, FLASH_CFG_MAX_SIZE);
3812 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3814 device_printf(sc->dev,
3815 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
3816 __func__, mtype, moff, cflen, rc);
3820 write_via_memwin(sc, 2, addr, cfdata, cflen);
3823 firmware_put(rcfg, FIRMWARE_UNLOAD);
3824 unload_fw_module(sc, dcfg, NULL);
3828 struct caps_allowed {
3831 uint16_t switchcaps;
3835 uint16_t cryptocaps;
3840 #define FW_PARAM_DEV(param) \
3841 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3842 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3843 #define FW_PARAM_PFVF(param) \
3844 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3845 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3848 * Provide a configuration profile to the firmware and have it initialize the
3849 * chip accordingly. This may involve uploading a configuration file to the
3853 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
3854 const struct caps_allowed *caps_allowed)
3857 struct fw_caps_config_cmd caps;
3858 uint32_t mtype, moff, finicsum, cfcsum, param, val;
3860 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3862 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3866 bzero(&caps, sizeof(caps));
3867 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3868 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3869 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
3872 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3873 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
3874 mtype = FW_MEMTYPE_FLASH;
3875 moff = t4_flash_cfg_addr(sc);
3876 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3877 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3878 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3882 * Ask the firmware where it wants us to upload the config file.
3884 param = FW_PARAM_DEV(CF);
3885 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3887 /* No support for config file? Shouldn't happen. */
3888 device_printf(sc->dev,
3889 "failed to query config file location: %d.\n", rc);
3892 mtype = G_FW_PARAMS_PARAM_Y(val);
3893 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3894 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3895 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3896 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3899 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
3901 device_printf(sc->dev,
3902 "failed to upload config file to card: %d.\n", rc);
3906 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3908 device_printf(sc->dev, "failed to pre-process config file: %d "
3909 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3913 finicsum = be32toh(caps.finicsum);
3914 cfcsum = be32toh(caps.cfcsum); /* actual */
3915 if (finicsum != cfcsum) {
3916 device_printf(sc->dev,
3917 "WARNING: config file checksum mismatch: %08x %08x\n",
3920 sc->cfcsum = cfcsum;
3921 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
3924 * Let the firmware know what features will (not) be used so it can tune
3925 * things accordingly.
3927 #define LIMIT_CAPS(x) do { \
3928 caps.x##caps &= htobe16(caps_allowed->x##caps); \
3940 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
3942 * TOE and hashfilters are mutually exclusive. It is a config
3943 * file or firmware bug if both are reported as available. Try
3944 * to cope with the situation in non-debug builds by disabling
3947 MPASS(caps.toecaps == 0);
3954 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3955 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3956 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3957 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3959 device_printf(sc->dev,
3960 "failed to process config file: %d.\n", rc);
3964 t4_tweak_chip_settings(sc);
3965 set_params__pre_init(sc);
3967 /* get basic stuff going */
3968 rc = -t4_fw_initialize(sc, sc->mbox);
3970 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
3978 * Partition chip resources for use between various PFs, VFs, etc.
3981 partition_resources(struct adapter *sc)
3983 char cfg_file[sizeof(t4_cfg_file)];
3984 struct caps_allowed caps_allowed;
3988 /* Only the master driver gets to configure the chip resources. */
3989 MPASS(sc->flags & MASTER_PF);
3991 #define COPY_CAPS(x) do { \
3992 caps_allowed.x##caps = t4_##x##caps_allowed; \
3994 bzero(&caps_allowed, sizeof(caps_allowed));
4004 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
4005 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
4007 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
4008 if (rc != 0 && fallback) {
4009 device_printf(sc->dev,
4010 "failed (%d) to configure card with \"%s\" profile, "
4011 "will fall back to a basic configuration and retry.\n",
4013 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
4014 bzero(&caps_allowed, sizeof(caps_allowed));
4016 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
4025 * Retrieve parameters that are needed (or nice to have) very early.
4028 get_params__pre_init(struct adapter *sc)
4031 uint32_t param[2], val[2];
4033 t4_get_version_info(sc);
4035 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4036 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4037 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4038 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4039 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4041 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4042 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4043 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4044 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4045 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4047 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4048 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4049 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4050 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4051 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4053 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4054 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4055 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4056 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4057 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4059 param[0] = FW_PARAM_DEV(PORTVEC);
4060 param[1] = FW_PARAM_DEV(CCLK);
4061 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4063 device_printf(sc->dev,
4064 "failed to query parameters (pre_init): %d.\n", rc);
4068 sc->params.portvec = val[0];
4069 sc->params.nports = bitcount32(val[0]);
4070 sc->params.vpd.cclk = val[1];
4072 /* Read device log parameters. */
4073 rc = -t4_init_devlog_params(sc, 1);
4075 fixup_devlog_params(sc);
4077 device_printf(sc->dev,
4078 "failed to get devlog parameters: %d.\n", rc);
4079 rc = 0; /* devlog isn't critical for device operation */
4086 * Any params that need to be set before FW_INITIALIZE.
4089 set_params__pre_init(struct adapter *sc)
4092 uint32_t param, val;
4094 if (chip_id(sc) >= CHELSIO_T6) {
4095 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
4097 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4098 /* firmwares < 1.20.1.0 do not have this param. */
4099 if (rc == FW_EINVAL && sc->params.fw_vers <
4100 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4101 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) {
4105 device_printf(sc->dev,
4106 "failed to enable high priority filters :%d.\n",
4111 /* Enable opaque VIIDs with firmwares that support it. */
4112 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4114 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4115 if (rc == 0 && val == 1)
4116 sc->params.viid_smt_extn_support = true;
4118 sc->params.viid_smt_extn_support = false;
4124 * Retrieve various parameters that are of interest to the driver. The device
4125 * has been initialized by the firmware at this point.
4128 get_params__post_init(struct adapter *sc)
4131 uint32_t param[7], val[7];
4132 struct fw_caps_config_cmd caps;
4134 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4135 param[1] = FW_PARAM_PFVF(EQ_START);
4136 param[2] = FW_PARAM_PFVF(FILTER_START);
4137 param[3] = FW_PARAM_PFVF(FILTER_END);
4138 param[4] = FW_PARAM_PFVF(L2T_START);
4139 param[5] = FW_PARAM_PFVF(L2T_END);
4140 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4141 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4142 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4143 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4145 device_printf(sc->dev,
4146 "failed to query parameters (post_init): %d.\n", rc);
4150 sc->sge.iq_start = val[0];
4151 sc->sge.eq_start = val[1];
4152 if ((int)val[3] > (int)val[2]) {
4153 sc->tids.ftid_base = val[2];
4154 sc->tids.ftid_end = val[3];
4155 sc->tids.nftids = val[3] - val[2] + 1;
4157 sc->vres.l2t.start = val[4];
4158 sc->vres.l2t.size = val[5] - val[4] + 1;
4159 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4160 ("%s: L2 table size (%u) larger than expected (%u)",
4161 __func__, sc->vres.l2t.size, L2T_SIZE));
4162 sc->params.core_vdd = val[6];
4164 if (chip_id(sc) >= CHELSIO_T6) {
4166 sc->tids.tid_base = t4_read_reg(sc,
4167 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4169 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4170 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4171 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4173 device_printf(sc->dev,
4174 "failed to query hpfilter parameters: %d.\n", rc);
4177 if ((int)val[1] > (int)val[0]) {
4178 sc->tids.hpftid_base = val[0];
4179 sc->tids.hpftid_end = val[1];
4180 sc->tids.nhpftids = val[1] - val[0] + 1;
4183 * These should go off if the layout changes and the
4184 * driver needs to catch up.
4186 MPASS(sc->tids.hpftid_base == 0);
4187 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4192 * MPSBGMAP is queried separately because only recent firmwares support
4193 * it as a parameter and we don't want the compound query above to fail
4194 * on older firmwares.
4196 param[0] = FW_PARAM_DEV(MPSBGMAP);
4198 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4200 sc->params.mps_bg_map = val[0];
4202 sc->params.mps_bg_map = 0;
4205 * Determine whether the firmware supports the filter2 work request.
4206 * This is queried separately for the same reason as MPSBGMAP above.
4208 param[0] = FW_PARAM_DEV(FILTER2_WR);
4210 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4212 sc->params.filter2_wr_support = val[0] != 0;
4214 sc->params.filter2_wr_support = 0;
4217 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4218 * This is queried separately for the same reason as other params above.
4220 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4222 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4224 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4226 sc->params.ulptx_memwrite_dsgl = false;
4228 /* get capabilites */
4229 bzero(&caps, sizeof(caps));
4230 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4231 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4232 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4233 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4235 device_printf(sc->dev,
4236 "failed to get card capabilities: %d.\n", rc);
4240 #define READ_CAPS(x) do { \
4241 sc->x = htobe16(caps.x); \
4244 READ_CAPS(linkcaps);
4245 READ_CAPS(switchcaps);
4248 READ_CAPS(rdmacaps);
4249 READ_CAPS(cryptocaps);
4250 READ_CAPS(iscsicaps);
4251 READ_CAPS(fcoecaps);
4253 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4254 MPASS(chip_id(sc) > CHELSIO_T4);
4255 MPASS(sc->toecaps == 0);
4258 param[0] = FW_PARAM_DEV(NTID);
4259 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4261 device_printf(sc->dev,
4262 "failed to query HASHFILTER parameters: %d.\n", rc);
4265 sc->tids.ntids = val[0];
4266 if (sc->params.fw_vers <
4267 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4268 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4269 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4270 sc->tids.ntids -= sc->tids.nhpftids;
4272 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4273 sc->params.hash_filter = 1;
4275 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4276 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4277 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4278 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4279 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4281 device_printf(sc->dev,
4282 "failed to query NIC parameters: %d.\n", rc);
4285 if ((int)val[1] > (int)val[0]) {
4286 sc->tids.etid_base = val[0];
4287 sc->tids.etid_end = val[1];
4288 sc->tids.netids = val[1] - val[0] + 1;
4289 sc->params.eo_wr_cred = val[2];
4290 sc->params.ethoffload = 1;
4294 /* query offload-related parameters */
4295 param[0] = FW_PARAM_DEV(NTID);
4296 param[1] = FW_PARAM_PFVF(SERVER_START);
4297 param[2] = FW_PARAM_PFVF(SERVER_END);
4298 param[3] = FW_PARAM_PFVF(TDDP_START);
4299 param[4] = FW_PARAM_PFVF(TDDP_END);
4300 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4301 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4303 device_printf(sc->dev,
4304 "failed to query TOE parameters: %d.\n", rc);
4307 sc->tids.ntids = val[0];
4308 if (sc->params.fw_vers <
4309 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4310 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4311 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4312 sc->tids.ntids -= sc->tids.nhpftids;
4314 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4315 if ((int)val[2] > (int)val[1]) {
4316 sc->tids.stid_base = val[1];
4317 sc->tids.nstids = val[2] - val[1] + 1;
4319 sc->vres.ddp.start = val[3];
4320 sc->vres.ddp.size = val[4] - val[3] + 1;
4321 sc->params.ofldq_wr_cred = val[5];
4322 sc->params.offload = 1;
4325 * The firmware attempts memfree TOE configuration for -SO cards
4326 * and will report toecaps=0 if it runs out of resources (this
4327 * depends on the config file). It may not report 0 for other
4328 * capabilities dependent on the TOE in this case. Set them to
4329 * 0 here so that the driver doesn't bother tracking resources
4330 * that will never be used.
4336 param[0] = FW_PARAM_PFVF(STAG_START);
4337 param[1] = FW_PARAM_PFVF(STAG_END);
4338 param[2] = FW_PARAM_PFVF(RQ_START);
4339 param[3] = FW_PARAM_PFVF(RQ_END);
4340 param[4] = FW_PARAM_PFVF(PBL_START);
4341 param[5] = FW_PARAM_PFVF(PBL_END);
4342 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4344 device_printf(sc->dev,
4345 "failed to query RDMA parameters(1): %d.\n", rc);
4348 sc->vres.stag.start = val[0];
4349 sc->vres.stag.size = val[1] - val[0] + 1;
4350 sc->vres.rq.start = val[2];
4351 sc->vres.rq.size = val[3] - val[2] + 1;
4352 sc->vres.pbl.start = val[4];
4353 sc->vres.pbl.size = val[5] - val[4] + 1;
4355 param[0] = FW_PARAM_PFVF(SQRQ_START);
4356 param[1] = FW_PARAM_PFVF(SQRQ_END);
4357 param[2] = FW_PARAM_PFVF(CQ_START);
4358 param[3] = FW_PARAM_PFVF(CQ_END);
4359 param[4] = FW_PARAM_PFVF(OCQ_START);
4360 param[5] = FW_PARAM_PFVF(OCQ_END);
4361 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4363 device_printf(sc->dev,
4364 "failed to query RDMA parameters(2): %d.\n", rc);
4367 sc->vres.qp.start = val[0];
4368 sc->vres.qp.size = val[1] - val[0] + 1;
4369 sc->vres.cq.start = val[2];
4370 sc->vres.cq.size = val[3] - val[2] + 1;
4371 sc->vres.ocq.start = val[4];
4372 sc->vres.ocq.size = val[5] - val[4] + 1;
4374 param[0] = FW_PARAM_PFVF(SRQ_START);
4375 param[1] = FW_PARAM_PFVF(SRQ_END);
4376 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4377 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4378 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4380 device_printf(sc->dev,
4381 "failed to query RDMA parameters(3): %d.\n", rc);
4384 sc->vres.srq.start = val[0];
4385 sc->vres.srq.size = val[1] - val[0] + 1;
4386 sc->params.max_ordird_qp = val[2];
4387 sc->params.max_ird_adapter = val[3];
4389 if (sc->iscsicaps) {
4390 param[0] = FW_PARAM_PFVF(ISCSI_START);
4391 param[1] = FW_PARAM_PFVF(ISCSI_END);
4392 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4394 device_printf(sc->dev,
4395 "failed to query iSCSI parameters: %d.\n", rc);
4398 sc->vres.iscsi.start = val[0];
4399 sc->vres.iscsi.size = val[1] - val[0] + 1;
4401 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4402 param[0] = FW_PARAM_PFVF(TLS_START);
4403 param[1] = FW_PARAM_PFVF(TLS_END);
4404 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4406 device_printf(sc->dev,
4407 "failed to query TLS parameters: %d.\n", rc);
4410 sc->vres.key.start = val[0];
4411 sc->vres.key.size = val[1] - val[0] + 1;
4414 t4_init_sge_params(sc);
4417 * We've got the params we wanted to query via the firmware. Now grab
4418 * some others directly from the chip.
4420 rc = t4_read_chip_settings(sc);
4426 set_params__post_init(struct adapter *sc)
4428 uint32_t param, val;
4433 /* ask for encapsulated CPLs */
4434 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4436 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4438 /* Enable 32b port caps if the firmware supports it. */
4439 param = FW_PARAM_PFVF(PORT_CAPS32);
4441 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4442 sc->params.port_caps32 = 1;
4444 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4445 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4446 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4447 V_MASKFILTER(val - 1));
4451 * Override the TOE timers with user provided tunables. This is not the
4452 * recommended way to change the timers (the firmware config file is) so
4453 * these tunables are not documented.
4455 * All the timer tunables are in microseconds.
4457 if (t4_toe_keepalive_idle != 0) {
4458 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4459 v &= M_KEEPALIVEIDLE;
4460 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4461 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4463 if (t4_toe_keepalive_interval != 0) {
4464 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4465 v &= M_KEEPALIVEINTVL;
4466 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4467 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4469 if (t4_toe_keepalive_count != 0) {
4470 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4471 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4472 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4473 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4474 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4476 if (t4_toe_rexmt_min != 0) {
4477 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4479 t4_set_reg_field(sc, A_TP_RXT_MIN,
4480 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4482 if (t4_toe_rexmt_max != 0) {
4483 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4485 t4_set_reg_field(sc, A_TP_RXT_MAX,
4486 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4488 if (t4_toe_rexmt_count != 0) {
4489 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4490 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4491 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4492 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4493 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4495 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4496 if (t4_toe_rexmt_backoff[i] != -1) {
4497 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4498 shift = (i & 3) << 3;
4499 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4500 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4507 #undef FW_PARAM_PFVF
4511 t4_set_desc(struct adapter *sc)
4514 struct adapter_params *p = &sc->params;
4516 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4518 device_set_desc_copy(sc->dev, buf);
4522 ifmedia_add4(struct ifmedia *ifm, int m)
4525 ifmedia_add(ifm, m, 0, NULL);
4526 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4527 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4528 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4532 * This is the selected media, which is not quite the same as the active media.
4533 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4534 * and active are not the same, and "media: Ethernet selected" otherwise.
4537 set_current_media(struct port_info *pi)
4539 struct link_config *lc;
4540 struct ifmedia *ifm;
4544 PORT_LOCK_ASSERT_OWNED(pi);
4546 /* Leave current media alone if it's already set to IFM_NONE. */
4548 if (ifm->ifm_cur != NULL &&
4549 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4553 if (lc->requested_aneg != AUTONEG_DISABLE &&
4554 lc->supported & FW_PORT_CAP32_ANEG) {
4555 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4558 mword = IFM_ETHER | IFM_FDX;
4559 if (lc->requested_fc & PAUSE_TX)
4560 mword |= IFM_ETH_TXPAUSE;
4561 if (lc->requested_fc & PAUSE_RX)
4562 mword |= IFM_ETH_RXPAUSE;
4563 if (lc->requested_speed == 0)
4564 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4566 speed = lc->requested_speed;
4567 mword |= port_mword(pi, speed_to_fwcap(speed));
4568 ifmedia_set(ifm, mword);
4572 * Returns true if the ifmedia list for the port cannot change.
4575 fixed_ifmedia(struct port_info *pi)
4578 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4579 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4580 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4581 pi->port_type == FW_PORT_TYPE_KX4 ||
4582 pi->port_type == FW_PORT_TYPE_KX ||
4583 pi->port_type == FW_PORT_TYPE_KR ||
4584 pi->port_type == FW_PORT_TYPE_BP_AP ||
4585 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4586 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4587 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4588 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4589 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4593 build_medialist(struct port_info *pi)
4596 int unknown, mword, bit;
4597 struct link_config *lc;
4598 struct ifmedia *ifm;
4600 PORT_LOCK_ASSERT_OWNED(pi);
4602 if (pi->flags & FIXED_IFMEDIA)
4606 * Rebuild the ifmedia list.
4609 ifmedia_removeall(ifm);
4611 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4612 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4615 MPASS(LIST_EMPTY(&ifm->ifm_list));
4616 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4617 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4622 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4624 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4626 mword = port_mword(pi, speed);
4627 if (mword == IFM_NONE) {
4629 } else if (mword == IFM_UNKNOWN)
4632 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4635 if (unknown > 0) /* Add one unknown for all unknown media types. */
4636 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4637 if (lc->supported & FW_PORT_CAP32_ANEG)
4638 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4640 set_current_media(pi);
4644 * Initialize the requested fields in the link config based on driver tunables.
4647 init_link_config(struct port_info *pi)
4649 struct link_config *lc = &pi->link_cfg;
4651 PORT_LOCK_ASSERT_OWNED(pi);
4653 lc->requested_speed = 0;
4655 if (t4_autoneg == 0)
4656 lc->requested_aneg = AUTONEG_DISABLE;
4657 else if (t4_autoneg == 1)
4658 lc->requested_aneg = AUTONEG_ENABLE;
4660 lc->requested_aneg = AUTONEG_AUTO;
4662 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4665 if (t4_fec == -1 || t4_fec & FEC_AUTO)
4666 lc->requested_fec = FEC_AUTO;
4668 lc->requested_fec = FEC_NONE;
4669 if (t4_fec & FEC_RS)
4670 lc->requested_fec |= FEC_RS;
4671 if (t4_fec & FEC_BASER_RS)
4672 lc->requested_fec |= FEC_BASER_RS;
4677 * Makes sure that all requested settings comply with what's supported by the
4678 * port. Returns the number of settings that were invalid and had to be fixed.
4681 fixup_link_config(struct port_info *pi)
4684 struct link_config *lc = &pi->link_cfg;
4687 PORT_LOCK_ASSERT_OWNED(pi);
4689 /* Speed (when not autonegotiating) */
4690 if (lc->requested_speed != 0) {
4691 fwspeed = speed_to_fwcap(lc->requested_speed);
4692 if ((fwspeed & lc->supported) == 0) {
4694 lc->requested_speed = 0;
4698 /* Link autonegotiation */
4699 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4700 lc->requested_aneg == AUTONEG_DISABLE ||
4701 lc->requested_aneg == AUTONEG_AUTO);
4702 if (lc->requested_aneg == AUTONEG_ENABLE &&
4703 !(lc->supported & FW_PORT_CAP32_ANEG)) {
4705 lc->requested_aneg = AUTONEG_AUTO;
4709 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4710 if (lc->requested_fc & PAUSE_TX &&
4711 !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4713 lc->requested_fc &= ~PAUSE_TX;
4715 if (lc->requested_fc & PAUSE_RX &&
4716 !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4718 lc->requested_fc &= ~PAUSE_RX;
4720 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4721 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4723 lc->requested_fc |= PAUSE_AUTONEG;
4727 if ((lc->requested_fec & FEC_RS &&
4728 !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4729 (lc->requested_fec & FEC_BASER_RS &&
4730 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4732 lc->requested_fec = FEC_AUTO;
4739 * Apply the requested L1 settings, which are expected to be valid, to the
4743 apply_link_config(struct port_info *pi)
4745 struct adapter *sc = pi->adapter;
4746 struct link_config *lc = &pi->link_cfg;
4750 ASSERT_SYNCHRONIZED_OP(sc);
4751 PORT_LOCK_ASSERT_OWNED(pi);
4753 if (lc->requested_aneg == AUTONEG_ENABLE)
4754 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4755 if (!(lc->requested_fc & PAUSE_AUTONEG))
4756 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4757 if (lc->requested_fc & PAUSE_TX)
4758 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4759 if (lc->requested_fc & PAUSE_RX)
4760 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4761 if (lc->requested_fec & FEC_RS)
4762 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4763 if (lc->requested_fec & FEC_BASER_RS)
4764 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4766 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4768 /* Don't complain if the VF driver gets back an EPERM. */
4769 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
4770 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4773 * An L1_CFG will almost always result in a link-change event if
4774 * the link is up, and the driver will refresh the actual
4775 * fec/fc/etc. when the notification is processed. If the link
4776 * is down then the actual settings are meaningless.
4778 * This takes care of the case where a change in the L1 settings
4779 * may not result in a notification.
4781 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4782 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4787 #define FW_MAC_EXACT_CHUNK 7
4790 * Program the port's XGMAC based on parameters in ifnet. The caller also
4791 * indicates which parameters should be programmed (the rest are left alone).
4794 update_mac_settings(struct ifnet *ifp, int flags)
4797 struct vi_info *vi = ifp->if_softc;
4798 struct port_info *pi = vi->pi;
4799 struct adapter *sc = pi->adapter;
4800 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4802 ASSERT_SYNCHRONIZED_OP(sc);
4803 KASSERT(flags, ("%s: not told what to update.", __func__));
4805 if (flags & XGMAC_MTU)
4808 if (flags & XGMAC_PROMISC)
4809 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4811 if (flags & XGMAC_ALLMULTI)
4812 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4814 if (flags & XGMAC_VLANEX)
4815 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4817 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4818 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4819 allmulti, 1, vlanex, false);
4821 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4827 if (flags & XGMAC_UCADDR) {
4828 uint8_t ucaddr[ETHER_ADDR_LEN];
4830 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4831 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4832 ucaddr, true, &vi->smt_idx);
4835 if_printf(ifp, "change_mac failed: %d\n", rc);
4838 vi->xact_addr_filt = rc;
4843 if (flags & XGMAC_MCADDRS) {
4844 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4847 struct ifmultiaddr *ifma;
4850 if_maddr_rlock(ifp);
4851 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4852 if (ifma->ifma_addr->sa_family != AF_LINK)
4855 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4856 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4859 if (i == FW_MAC_EXACT_CHUNK) {
4860 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4861 del, i, mcaddr, NULL, &hash, 0);
4864 for (j = 0; j < i; j++) {
4866 "failed to add mc address"
4868 "%02x:%02x:%02x rc=%d\n",
4869 mcaddr[j][0], mcaddr[j][1],
4870 mcaddr[j][2], mcaddr[j][3],
4871 mcaddr[j][4], mcaddr[j][5],
4881 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4882 mcaddr, NULL, &hash, 0);
4885 for (j = 0; j < i; j++) {
4887 "failed to add mc address"
4889 "%02x:%02x:%02x rc=%d\n",
4890 mcaddr[j][0], mcaddr[j][1],
4891 mcaddr[j][2], mcaddr[j][3],
4892 mcaddr[j][4], mcaddr[j][5],
4899 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4901 if_printf(ifp, "failed to set mc address hash: %d", rc);
4903 if_maddr_runlock(ifp);
4910 * {begin|end}_synchronized_op must be called from the same thread.
4913 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4919 /* the caller thinks it's ok to sleep, but is it really? */
4920 if (flags & SLEEP_OK)
4921 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4922 "begin_synchronized_op");
4933 if (vi && IS_DOOMED(vi)) {
4943 if (!(flags & SLEEP_OK)) {
4948 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4954 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4957 sc->last_op = wmesg;
4958 sc->last_op_thr = curthread;
4959 sc->last_op_flags = flags;
4963 if (!(flags & HOLD_LOCK) || rc)
4970 * Tell if_ioctl and if_init that the VI is going away. This is
4971 * special variant of begin_synchronized_op and must be paired with a
4972 * call to end_synchronized_op.
4975 doom_vi(struct adapter *sc, struct vi_info *vi)
4982 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4985 sc->last_op = "t4detach";
4986 sc->last_op_thr = curthread;
4987 sc->last_op_flags = 0;
4993 * {begin|end}_synchronized_op must be called from the same thread.
4996 end_synchronized_op(struct adapter *sc, int flags)
4999 if (flags & LOCK_HELD)
5000 ADAPTER_LOCK_ASSERT_OWNED(sc);
5004 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
5011 cxgbe_init_synchronized(struct vi_info *vi)
5013 struct port_info *pi = vi->pi;
5014 struct adapter *sc = pi->adapter;
5015 struct ifnet *ifp = vi->ifp;
5017 struct sge_txq *txq;
5019 ASSERT_SYNCHRONIZED_OP(sc);
5021 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5022 return (0); /* already running */
5024 if (!(sc->flags & FULL_INIT_DONE) &&
5025 ((rc = adapter_full_init(sc)) != 0))
5026 return (rc); /* error message displayed already */
5028 if (!(vi->flags & VI_INIT_DONE) &&
5029 ((rc = vi_full_init(vi)) != 0))
5030 return (rc); /* error message displayed already */
5032 rc = update_mac_settings(ifp, XGMAC_ALL);
5034 goto done; /* error message displayed already */
5037 if (pi->up_vis == 0) {
5038 t4_update_port_info(pi);
5039 fixup_link_config(pi);
5040 build_medialist(pi);
5041 apply_link_config(pi);
5044 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5046 if_printf(ifp, "enable_vi failed: %d\n", rc);
5052 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5056 for_each_txq(vi, i, txq) {
5058 txq->eq.flags |= EQ_ENABLED;
5063 * The first iq of the first port to come up is used for tracing.
5065 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5066 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5067 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5068 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5069 V_QUEUENUMBER(sc->traceq));
5070 pi->flags |= HAS_TRACEQ;
5075 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5077 if (pi->nvi > 1 || sc->flags & IS_VF)
5078 callout_reset(&vi->tick, hz, vi_tick, vi);
5080 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5081 if (pi->link_cfg.link_ok)
5082 t4_os_link_changed(pi);
5086 cxgbe_uninit_synchronized(vi);
5095 cxgbe_uninit_synchronized(struct vi_info *vi)
5097 struct port_info *pi = vi->pi;
5098 struct adapter *sc = pi->adapter;
5099 struct ifnet *ifp = vi->ifp;
5101 struct sge_txq *txq;
5103 ASSERT_SYNCHRONIZED_OP(sc);
5105 if (!(vi->flags & VI_INIT_DONE)) {
5106 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5107 KASSERT(0, ("uninited VI is running"));
5108 if_printf(ifp, "uninited VI with running ifnet. "
5109 "vi->flags 0x%016lx, if_flags 0x%08x, "
5110 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5117 * Disable the VI so that all its data in either direction is discarded
5118 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5119 * tick) intact as the TP can deliver negative advice or data that it's
5120 * holding in its RAM (for an offloaded connection) even after the VI is
5123 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5125 if_printf(ifp, "disable_vi failed: %d\n", rc);
5129 for_each_txq(vi, i, txq) {
5131 txq->eq.flags &= ~EQ_ENABLED;
5136 if (pi->nvi > 1 || sc->flags & IS_VF)
5137 callout_stop(&vi->tick);
5139 callout_stop(&pi->tick);
5140 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5144 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5146 if (pi->up_vis > 0) {
5151 pi->link_cfg.link_ok = false;
5152 pi->link_cfg.speed = 0;
5153 pi->link_cfg.link_down_rc = 255;
5154 t4_os_link_changed(pi);
5161 * It is ok for this function to fail midway and return right away. t4_detach
5162 * will walk the entire sc->irq list and clean up whatever is valid.
5165 t4_setup_intr_handlers(struct adapter *sc)
5167 int rc, rid, p, q, v;
5170 struct port_info *pi;
5172 struct sge *sge = &sc->sge;
5173 struct sge_rxq *rxq;
5175 struct sge_ofld_rxq *ofld_rxq;
5178 struct sge_nm_rxq *nm_rxq;
5181 int nbuckets = rss_getnumbuckets();
5188 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5189 if (forwarding_intr_to_fwq(sc))
5190 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5192 /* Multiple interrupts. */
5193 if (sc->flags & IS_VF)
5194 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5195 ("%s: too few intr.", __func__));
5197 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5198 ("%s: too few intr.", __func__));
5200 /* The first one is always error intr on PFs */
5201 if (!(sc->flags & IS_VF)) {
5202 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5209 /* The second one is always the firmware event queue (first on VFs) */
5210 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5216 for_each_port(sc, p) {
5218 for_each_vi(pi, v, vi) {
5219 vi->first_intr = rid - 1;
5221 if (vi->nnmrxq > 0) {
5222 int n = max(vi->nrxq, vi->nnmrxq);
5224 rxq = &sge->rxq[vi->first_rxq];
5226 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5228 for (q = 0; q < n; q++) {
5229 snprintf(s, sizeof(s), "%x%c%x", p,
5235 irq->nm_rxq = nm_rxq++;
5237 if (irq->nm_rxq != NULL &&
5239 /* Netmap rx only */
5240 rc = t4_alloc_irq(sc, irq, rid,
5241 t4_nm_intr, irq->nm_rxq, s);
5243 if (irq->nm_rxq != NULL &&
5245 /* NIC and Netmap rx */
5246 rc = t4_alloc_irq(sc, irq, rid,
5247 t4_vi_intr, irq, s);
5250 if (irq->rxq != NULL &&
5251 irq->nm_rxq == NULL) {
5253 rc = t4_alloc_irq(sc, irq, rid,
5254 t4_intr, irq->rxq, s);
5260 bus_bind_intr(sc->dev, irq->res,
5261 rss_getcpu(q % nbuckets));
5269 for_each_rxq(vi, q, rxq) {
5270 snprintf(s, sizeof(s), "%x%c%x", p,
5272 rc = t4_alloc_irq(sc, irq, rid,
5277 bus_bind_intr(sc->dev, irq->res,
5278 rss_getcpu(q % nbuckets));
5286 for_each_ofld_rxq(vi, q, ofld_rxq) {
5287 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5288 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5299 MPASS(irq == &sc->irq[sc->intr_count]);
5305 adapter_full_init(struct adapter *sc)
5309 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5310 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5313 ASSERT_SYNCHRONIZED_OP(sc);
5314 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5315 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5316 ("%s: FULL_INIT_DONE already", __func__));
5319 * queues that belong to the adapter (not any particular port).
5321 rc = t4_setup_adapter_queues(sc);
5325 for (i = 0; i < nitems(sc->tq); i++) {
5326 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5327 taskqueue_thread_enqueue, &sc->tq[i]);
5328 if (sc->tq[i] == NULL) {
5329 device_printf(sc->dev,
5330 "failed to allocate task queue %d\n", i);
5334 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5335 device_get_nameunit(sc->dev), i);
5338 MPASS(RSS_KEYSIZE == 40);
5339 rss_getkey((void *)&raw_rss_key[0]);
5340 for (i = 0; i < nitems(rss_key); i++) {
5341 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5343 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5346 if (!(sc->flags & IS_VF))
5348 sc->flags |= FULL_INIT_DONE;
5351 adapter_full_uninit(sc);
5357 adapter_full_uninit(struct adapter *sc)
5361 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5363 t4_teardown_adapter_queues(sc);
5365 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5366 taskqueue_free(sc->tq[i]);
5370 sc->flags &= ~FULL_INIT_DONE;
5376 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5377 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5378 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5379 RSS_HASHTYPE_RSS_UDP_IPV6)
5381 /* Translates kernel hash types to hardware. */
5383 hashconfig_to_hashen(int hashconfig)
5387 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5388 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5389 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5390 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5391 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5392 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5393 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5395 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5396 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5397 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5399 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5400 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5401 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5402 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5407 /* Translates hardware hash types to kernel. */
5409 hashen_to_hashconfig(int hashen)
5413 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5415 * If UDP hashing was enabled it must have been enabled for
5416 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5417 * enabling any 4-tuple hash is nonsense configuration.
5419 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5420 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5422 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5423 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5424 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5425 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5427 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5428 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5429 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5430 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5431 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5432 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5433 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5434 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5436 return (hashconfig);
5441 vi_full_init(struct vi_info *vi)
5443 struct adapter *sc = vi->pi->adapter;
5444 struct ifnet *ifp = vi->ifp;
5446 struct sge_rxq *rxq;
5449 int nbuckets = rss_getnumbuckets();
5450 int hashconfig = rss_gethashconfig();
5454 ASSERT_SYNCHRONIZED_OP(sc);
5455 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5456 ("%s: VI_INIT_DONE already", __func__));
5458 sysctl_ctx_init(&vi->ctx);
5459 vi->flags |= VI_SYSCTL_CTX;
5462 * Allocate tx/rx/fl queues for this VI.
5464 rc = t4_setup_vi_queues(vi);
5466 goto done; /* error message displayed already */
5469 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5471 if (vi->nrxq > vi->rss_size) {
5472 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5473 "some queues will never receive traffic.\n", vi->nrxq,
5475 } else if (vi->rss_size % vi->nrxq) {
5476 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5477 "expect uneven traffic distribution.\n", vi->nrxq,
5481 if (vi->nrxq != nbuckets) {
5482 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5483 "performance will be impacted.\n", vi->nrxq, nbuckets);
5486 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5487 for (i = 0; i < vi->rss_size;) {
5489 j = rss_get_indirection_to_bucket(i);
5491 rxq = &sc->sge.rxq[vi->first_rxq + j];
5492 rss[i++] = rxq->iq.abs_id;
5494 for_each_rxq(vi, j, rxq) {
5495 rss[i++] = rxq->iq.abs_id;
5496 if (i == vi->rss_size)
5502 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5506 if_printf(ifp, "rss_config failed: %d\n", rc);
5511 vi->hashen = hashconfig_to_hashen(hashconfig);
5514 * We may have had to enable some hashes even though the global config
5515 * wants them disabled. This is a potential problem that must be
5516 * reported to the user.
5518 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5521 * If we consider only the supported hash types, then the enabled hashes
5522 * are a superset of the requested hashes. In other words, there cannot
5523 * be any supported hash that was requested but not enabled, but there
5524 * can be hashes that were not requested but had to be enabled.
5526 extra &= SUPPORTED_RSS_HASHTYPES;
5527 MPASS((extra & hashconfig) == 0);
5531 "global RSS config (0x%x) cannot be accommodated.\n",
5534 if (extra & RSS_HASHTYPE_RSS_IPV4)
5535 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5536 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5537 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5538 if (extra & RSS_HASHTYPE_RSS_IPV6)
5539 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5540 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5541 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5542 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5543 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5544 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5545 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5547 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5548 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5549 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5550 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5552 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5555 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5560 vi->flags |= VI_INIT_DONE;
5572 vi_full_uninit(struct vi_info *vi)
5574 struct port_info *pi = vi->pi;
5575 struct adapter *sc = pi->adapter;
5577 struct sge_rxq *rxq;
5578 struct sge_txq *txq;
5580 struct sge_ofld_rxq *ofld_rxq;
5582 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5583 struct sge_wrq *ofld_txq;
5586 if (vi->flags & VI_INIT_DONE) {
5588 /* Need to quiesce queues. */
5590 /* XXX: Only for the first VI? */
5591 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5592 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5594 for_each_txq(vi, i, txq) {
5595 quiesce_txq(sc, txq);
5598 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5599 for_each_ofld_txq(vi, i, ofld_txq) {
5600 quiesce_wrq(sc, ofld_txq);
5604 for_each_rxq(vi, i, rxq) {
5605 quiesce_iq(sc, &rxq->iq);
5606 quiesce_fl(sc, &rxq->fl);
5610 for_each_ofld_rxq(vi, i, ofld_rxq) {
5611 quiesce_iq(sc, &ofld_rxq->iq);
5612 quiesce_fl(sc, &ofld_rxq->fl);
5615 free(vi->rss, M_CXGBE);
5616 free(vi->nm_rss, M_CXGBE);
5619 t4_teardown_vi_queues(vi);
5620 vi->flags &= ~VI_INIT_DONE;
5626 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5628 struct sge_eq *eq = &txq->eq;
5629 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5631 (void) sc; /* unused */
5635 MPASS((eq->flags & EQ_ENABLED) == 0);
5639 /* Wait for the mp_ring to empty. */
5640 while (!mp_ring_is_idle(txq->r)) {
5641 mp_ring_check_drainage(txq->r, 0);
5642 pause("rquiesce", 1);
5645 /* Then wait for the hardware to finish. */
5646 while (spg->cidx != htobe16(eq->pidx))
5647 pause("equiesce", 1);
5649 /* Finally, wait for the driver to reclaim all descriptors. */
5650 while (eq->cidx != eq->pidx)
5651 pause("dquiesce", 1);
5655 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5662 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5664 (void) sc; /* unused */
5666 /* Synchronize with the interrupt handler */
5667 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5672 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5674 mtx_lock(&sc->sfl_lock);
5676 fl->flags |= FL_DOOMED;
5678 callout_stop(&sc->sfl_callout);
5679 mtx_unlock(&sc->sfl_lock);
5681 KASSERT((fl->flags & FL_STARVING) == 0,
5682 ("%s: still starving", __func__));
5686 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5687 driver_intr_t *handler, void *arg, char *name)
5692 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5693 RF_SHAREABLE | RF_ACTIVE);
5694 if (irq->res == NULL) {
5695 device_printf(sc->dev,
5696 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5700 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5701 NULL, handler, arg, &irq->tag);
5703 device_printf(sc->dev,
5704 "failed to setup interrupt for rid %d, name %s: %d\n",
5707 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5713 t4_free_irq(struct adapter *sc, struct irq *irq)
5716 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5718 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5720 bzero(irq, sizeof(*irq));
5726 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5729 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5730 t4_get_regs(sc, buf, regs->len);
5733 #define A_PL_INDIR_CMD 0x1f8
5735 #define S_PL_AUTOINC 31
5736 #define M_PL_AUTOINC 0x1U
5737 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5738 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5740 #define S_PL_VFID 20
5741 #define M_PL_VFID 0xffU
5742 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5743 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5746 #define M_PL_ADDR 0xfffffU
5747 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5748 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5750 #define A_PL_INDIR_DATA 0x1fc
5753 read_vf_stat(struct adapter *sc, u_int vin, int reg)
5757 mtx_assert(&sc->reg_lock, MA_OWNED);
5758 if (sc->flags & IS_VF) {
5759 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5760 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5762 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5763 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
5764 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5765 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5767 return (((uint64_t)stats[1]) << 32 | stats[0]);
5771 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
5774 #define GET_STAT(name) \
5775 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
5777 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5778 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5779 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5780 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5781 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5782 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5783 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5784 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5785 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5786 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5787 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5788 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5789 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5790 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5791 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5792 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5798 t4_clr_vi_stats(struct adapter *sc, u_int vin)
5802 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
5803 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5804 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5805 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5806 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5810 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5813 const struct timeval interval = {0, 250000}; /* 250ms */
5815 if (!(vi->flags & VI_INIT_DONE))
5819 timevalsub(&tv, &interval);
5820 if (timevalcmp(&tv, &vi->last_refreshed, <))
5823 mtx_lock(&sc->reg_lock);
5824 t4_get_vi_stats(sc, vi->vin, &vi->stats);
5825 getmicrotime(&vi->last_refreshed);
5826 mtx_unlock(&sc->reg_lock);
5830 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5832 u_int i, v, tnl_cong_drops, bg_map;
5834 const struct timeval interval = {0, 250000}; /* 250ms */
5837 timevalsub(&tv, &interval);
5838 if (timevalcmp(&tv, &pi->last_refreshed, <))
5842 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5843 bg_map = pi->mps_bg_map;
5845 i = ffs(bg_map) - 1;
5846 mtx_lock(&sc->reg_lock);
5847 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5848 A_TP_MIB_TNL_CNG_DROP_0 + i);
5849 mtx_unlock(&sc->reg_lock);
5850 tnl_cong_drops += v;
5851 bg_map &= ~(1 << i);
5853 pi->tnl_cong_drops = tnl_cong_drops;
5854 getmicrotime(&pi->last_refreshed);
5858 cxgbe_tick(void *arg)
5860 struct port_info *pi = arg;
5861 struct adapter *sc = pi->adapter;
5863 PORT_LOCK_ASSERT_OWNED(pi);
5864 cxgbe_refresh_stats(sc, pi);
5866 callout_schedule(&pi->tick, hz);
5872 struct vi_info *vi = arg;
5873 struct adapter *sc = vi->pi->adapter;
5875 vi_refresh_stats(sc, vi);
5877 callout_schedule(&vi->tick, hz);
5881 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5883 static char *caps_decoder[] = {
5884 "\20\001IPMI\002NCSI", /* 0: NBM */
5885 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5886 "\20\001INGRESS\002EGRESS", /* 2: switch */
5887 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5888 "\006HASHFILTER\007ETHOFLD",
5889 "\20\001TOE", /* 4: TOE */
5890 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5891 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5892 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5893 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5895 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5896 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5897 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5898 "\004PO_INITIATOR\005PO_TARGET",
5902 t4_sysctls(struct adapter *sc)
5904 struct sysctl_ctx_list *ctx;
5905 struct sysctl_oid *oid;
5906 struct sysctl_oid_list *children, *c0;
5907 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5909 ctx = device_get_sysctl_ctx(sc->dev);
5914 oid = device_get_sysctl_tree(sc->dev);
5915 c0 = children = SYSCTL_CHILDREN(oid);
5917 sc->sc_do_rxcopy = 1;
5918 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5919 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5921 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5922 sc->params.nports, "# of ports");
5924 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5925 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
5926 sysctl_bitfield_8b, "A", "available doorbells");
5928 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5929 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5932 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5933 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5934 "interrupt holdoff timer values (us)");
5936 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5937 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5938 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5939 "interrupt holdoff packet counter values");
5941 t4_sge_sysctls(sc, ctx, children);
5943 sc->lro_timeout = 100;
5944 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5945 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5947 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5948 &sc->debug_flags, 0, "flags to enable runtime debugging");
5950 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5951 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5953 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5954 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5956 if (sc->flags & IS_VF)
5959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5960 NULL, chip_rev(sc), "chip hardware revision");
5962 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5963 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5965 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5966 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5968 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5969 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5971 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5972 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5974 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5975 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5977 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5978 sc->er_version, 0, "expansion ROM version");
5980 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5981 sc->bs_version, 0, "bootstrap firmware version");
5983 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5984 NULL, sc->params.scfg_vers, "serial config version");
5986 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5987 NULL, sc->params.vpd_vers, "VPD version");
5989 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5990 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5992 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5993 sc->cfcsum, "config file checksum");
5995 #define SYSCTL_CAP(name, n, text) \
5996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5997 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
5998 sysctl_bitfield_16b, "A", "available " text " capabilities")
6000 SYSCTL_CAP(nbmcaps, 0, "NBM");
6001 SYSCTL_CAP(linkcaps, 1, "link");
6002 SYSCTL_CAP(switchcaps, 2, "switch");
6003 SYSCTL_CAP(niccaps, 3, "NIC");
6004 SYSCTL_CAP(toecaps, 4, "TCP offload");
6005 SYSCTL_CAP(rdmacaps, 5, "RDMA");
6006 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
6007 SYSCTL_CAP(cryptocaps, 7, "crypto");
6008 SYSCTL_CAP(fcoecaps, 8, "FCoE");
6011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
6012 NULL, sc->tids.nftids, "number of filters");
6014 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
6015 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
6016 "chip temperature (in Celsius)");
6018 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
6019 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
6020 "microprocessor load averages (debug firmwares only)");
6022 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", CTLTYPE_INT |
6023 CTLFLAG_RD, sc, 0, sysctl_vdd, "I", "core Vdd (in mV)");
6025 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
6026 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
6027 sysctl_cpus, "A", "local CPUs");
6029 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
6030 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
6031 sysctl_cpus, "A", "preferred CPUs for interrupts");
6033 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
6034 &sc->swintr, 0, "software triggered interrupts");
6037 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
6039 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
6040 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
6041 "logs and miscellaneous information");
6042 children = SYSCTL_CHILDREN(oid);
6044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6045 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6046 sysctl_cctrl, "A", "congestion control");
6048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6049 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6050 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6052 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6053 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
6054 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6056 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6057 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
6058 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6060 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6061 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
6062 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6064 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6065 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
6066 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6068 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6069 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
6070 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6072 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6073 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la,
6074 "A", "CIM logic analyzer");
6076 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6077 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6078 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6080 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6081 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
6082 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6084 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6085 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
6086 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6088 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6089 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
6090 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6092 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6093 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
6094 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6096 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6097 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
6098 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6100 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6101 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
6102 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6104 if (chip_id(sc) > CHELSIO_T4) {
6105 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6106 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
6107 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
6109 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6110 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
6111 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
6114 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6115 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6116 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6118 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6119 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6120 sysctl_cim_qcfg, "A", "CIM queue configuration");
6122 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6123 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6124 sysctl_cpl_stats, "A", "CPL statistics");
6126 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6127 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6128 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6130 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6131 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6132 sysctl_devlog, "A", "firmware's device log");
6134 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6135 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6136 sysctl_fcoe_stats, "A", "FCoE statistics");
6138 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6139 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6140 sysctl_hw_sched, "A", "hardware scheduler ");
6142 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6143 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6144 sysctl_l2t, "A", "hardware L2 table");
6146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6147 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6148 sysctl_smt, "A", "hardware source MAC table");
6151 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6152 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6153 sysctl_clip, "A", "active CLIP table entries");
6156 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6157 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6158 sysctl_lb_stats, "A", "loopback statistics");
6160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6161 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6162 sysctl_meminfo, "A", "memory regions");
6164 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6165 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6166 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6167 "A", "MPS TCAM entries");
6169 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6170 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6171 sysctl_path_mtus, "A", "path MTUs");
6173 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6174 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6175 sysctl_pm_stats, "A", "PM statistics");
6177 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6178 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6179 sysctl_rdma_stats, "A", "RDMA statistics");
6181 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6182 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6183 sysctl_tcp_stats, "A", "TCP statistics");
6185 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6186 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6187 sysctl_tids, "A", "TID information");
6189 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6190 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6191 sysctl_tp_err_stats, "A", "TP error statistics");
6193 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6194 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
6195 "TP logic analyzer event capture mask");
6197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6198 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6199 sysctl_tp_la, "A", "TP logic analyzer");
6201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6202 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6203 sysctl_tx_rate, "A", "Tx rate");
6205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6206 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6207 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6209 if (chip_id(sc) >= CHELSIO_T5) {
6210 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6211 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6212 sysctl_wcwr_stats, "A", "write combined work requests");
6216 if (is_offload(sc)) {
6223 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
6224 NULL, "TOE parameters");
6225 children = SYSCTL_CHILDREN(oid);
6227 sc->tt.cong_algorithm = -1;
6228 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6229 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6230 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6234 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6235 &sc->tt.sndbuf, 0, "hardware send buffer");
6238 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
6239 &sc->tt.ddp, 0, "DDP allowed");
6241 sc->tt.rx_coalesce = -1;
6242 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6243 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6246 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6247 &sc->tt.tls, 0, "Inline TLS allowed");
6249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6250 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
6251 "I", "TCP ports that use inline TLS+TOE RX");
6253 sc->tt.tx_align = -1;
6254 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6255 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6257 sc->tt.tx_zcopy = 0;
6258 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6259 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6260 "Enable zero-copy aio_write(2)");
6262 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6263 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6264 "cop_managed_offloading", CTLFLAG_RW,
6265 &sc->tt.cop_managed_offloading, 0,
6266 "COP (Connection Offload Policy) controls all TOE offload");
6268 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6269 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6270 "TP timer tick (us)");
6272 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6273 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6274 "TCP timestamp tick (us)");
6276 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6277 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6280 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6281 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6282 "IU", "DACK timer (us)");
6284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6285 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6286 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6289 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6290 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6293 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6294 sysctl_tp_timer, "LU", "Persist timer min (us)");
6296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6297 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6298 sysctl_tp_timer, "LU", "Persist timer max (us)");
6300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6301 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6302 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6305 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6306 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6309 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6310 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6313 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6314 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6317 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6318 sysctl_tp_shift_cnt, "IU",
6319 "Number of SYN retransmissions before abort");
6321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6322 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6323 sysctl_tp_shift_cnt, "IU",
6324 "Number of retransmissions before abort");
6326 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6327 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6328 sysctl_tp_shift_cnt, "IU",
6329 "Number of keepalive probes before abort");
6331 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6332 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6333 children = SYSCTL_CHILDREN(oid);
6334 for (i = 0; i < 16; i++) {
6335 snprintf(s, sizeof(s), "%u", i);
6336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6337 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6338 "IU", "TOE retransmit backoff");
6345 vi_sysctls(struct vi_info *vi)
6347 struct sysctl_ctx_list *ctx;
6348 struct sysctl_oid *oid;
6349 struct sysctl_oid_list *children;
6351 ctx = device_get_sysctl_ctx(vi->dev);
6354 * dev.v?(cxgbe|cxl).X.
6356 oid = device_get_sysctl_tree(vi->dev);
6357 children = SYSCTL_CHILDREN(oid);
6359 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6360 vi->viid, "VI identifer");
6361 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6362 &vi->nrxq, 0, "# of rx queues");
6363 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6364 &vi->ntxq, 0, "# of tx queues");
6365 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6366 &vi->first_rxq, 0, "index of first rx queue");
6367 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6368 &vi->first_txq, 0, "index of first tx queue");
6369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6370 vi->rss_base, "start of RSS indirection table");
6371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6372 vi->rss_size, "size of RSS indirection table");
6374 if (IS_MAIN_VI(vi)) {
6375 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6376 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6377 "Reserve queue 0 for non-flowid packets");
6381 if (vi->nofldrxq != 0) {
6382 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6384 "# of rx queues for offloaded TCP connections");
6385 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6386 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6387 "index of first TOE rx queue");
6388 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6389 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6390 sysctl_holdoff_tmr_idx_ofld, "I",
6391 "holdoff timer index for TOE queues");
6392 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6393 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6394 sysctl_holdoff_pktc_idx_ofld, "I",
6395 "holdoff packet counter index for TOE queues");
6398 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6399 if (vi->nofldtxq != 0) {
6400 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6402 "# of tx queues for TOE/ETHOFLD");
6403 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6404 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6405 "index of first TOE/ETHOFLD tx queue");
6409 if (vi->nnmrxq != 0) {
6410 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6411 &vi->nnmrxq, 0, "# of netmap rx queues");
6412 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6413 &vi->nnmtxq, 0, "# of netmap tx queues");
6414 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6415 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6416 "index of first netmap rx queue");
6417 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6418 CTLFLAG_RD, &vi->first_nm_txq, 0,
6419 "index of first netmap tx queue");
6423 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6424 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6425 "holdoff timer index");
6426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6427 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6428 "holdoff packet counter index");
6430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6431 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6434 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6439 cxgbe_sysctls(struct port_info *pi)
6441 struct sysctl_ctx_list *ctx;
6442 struct sysctl_oid *oid;
6443 struct sysctl_oid_list *children, *children2;
6444 struct adapter *sc = pi->adapter;
6447 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6449 ctx = device_get_sysctl_ctx(pi->dev);
6454 oid = device_get_sysctl_tree(pi->dev);
6455 children = SYSCTL_CHILDREN(oid);
6457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6458 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6459 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6460 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6461 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6462 "PHY temperature (in Celsius)");
6463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6464 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6465 "PHY firmware version");
6468 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6469 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6470 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6472 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6473 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6474 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6475 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6476 "autonegotiation (-1 = not supported)");
6478 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6479 port_top_speed(pi), "max speed (in Gbps)");
6480 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6481 pi->mps_bg_map, "MPS buffer group map");
6482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6483 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6485 if (sc->flags & IS_VF)
6489 * dev.(cxgbe|cxl).X.tc.
6491 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6492 "Tx scheduler traffic classes (cl_rl)");
6493 children2 = SYSCTL_CHILDREN(oid);
6494 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6495 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6496 "pktsize for per-flow cl-rl (0 means up to the driver )");
6497 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6498 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6499 "burstsize for per-flow cl-rl (0 means up to the driver)");
6500 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6501 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6503 snprintf(name, sizeof(name), "%d", i);
6504 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6505 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6507 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6508 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6509 sysctl_bitfield_8b, "A", "flags");
6510 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6511 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6512 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6513 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6514 sysctl_tc_params, "A", "traffic class parameters");
6518 * dev.cxgbe.X.stats.
6520 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6521 NULL, "port statistics");
6522 children = SYSCTL_CHILDREN(oid);
6523 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6524 &pi->tx_parse_error, 0,
6525 "# of tx packets with invalid length or # of segments");
6527 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6528 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6529 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6530 sysctl_handle_t4_reg64, "QU", desc)
6532 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6533 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6534 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6536 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6538 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6540 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6542 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6543 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6544 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6545 "# of tx frames in this range",
6546 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6547 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6548 "# of tx frames in this range",
6549 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6550 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6551 "# of tx frames in this range",
6552 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6553 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6554 "# of tx frames in this range",
6555 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6556 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6557 "# of tx frames in this range",
6558 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6559 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6560 "# of tx frames in this range",
6561 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6562 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6563 "# of tx frames in this range",
6564 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6565 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6566 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6567 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6568 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6569 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6571 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6573 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6574 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6575 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6577 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6579 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6580 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6581 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6583 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6584 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6586 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6587 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6588 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6590 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6592 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6594 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6596 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6598 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6600 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6601 "# of frames received with bad FCS",
6602 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6603 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6604 "# of frames received with length error",
6605 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6606 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6607 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6608 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6609 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6610 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6611 "# of rx frames in this range",
6612 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6613 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6614 "# of rx frames in this range",
6615 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6616 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6617 "# of rx frames in this range",
6618 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6619 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6620 "# of rx frames in this range",
6621 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6622 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6623 "# of rx frames in this range",
6624 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6625 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6626 "# of rx frames in this range",
6627 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6628 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6629 "# of rx frames in this range",
6630 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6631 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6632 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6633 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6635 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6637 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6639 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6641 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6643 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6645 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6646 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6647 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6648 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6650 #undef SYSCTL_ADD_T4_REG64
6652 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6653 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6654 &pi->stats.name, desc)
6656 /* We get these from port_stats and they may be stale by up to 1s */
6657 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6658 "# drops due to buffer-group 0 overflows");
6659 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6660 "# drops due to buffer-group 1 overflows");
6661 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6662 "# drops due to buffer-group 2 overflows");
6663 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6664 "# drops due to buffer-group 3 overflows");
6665 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6666 "# of buffer-group 0 truncated packets");
6667 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6668 "# of buffer-group 1 truncated packets");
6669 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6670 "# of buffer-group 2 truncated packets");
6671 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6672 "# of buffer-group 3 truncated packets");
6674 #undef SYSCTL_ADD_T4_PORTSTAT
6676 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6677 CTLFLAG_RD, &pi->tx_tls_records,
6678 "# of TLS records transmitted");
6679 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6680 CTLFLAG_RD, &pi->tx_tls_octets,
6681 "# of payload octets in transmitted TLS records");
6682 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6683 CTLFLAG_RD, &pi->rx_tls_records,
6684 "# of TLS records received");
6685 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6686 CTLFLAG_RD, &pi->rx_tls_octets,
6687 "# of payload octets in received TLS records");
6691 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6693 int rc, *i, space = 0;
6696 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6697 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6699 sbuf_printf(&sb, " ");
6700 sbuf_printf(&sb, "%d", *i);
6703 rc = sbuf_finish(&sb);
6709 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6714 rc = sysctl_wire_old_buffer(req, 0);
6718 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6722 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6723 rc = sbuf_finish(sb);
6730 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6735 rc = sysctl_wire_old_buffer(req, 0);
6739 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6743 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6744 rc = sbuf_finish(sb);
6751 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6753 struct port_info *pi = arg1;
6755 struct adapter *sc = pi->adapter;
6759 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6762 /* XXX: magic numbers */
6763 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6765 end_synchronized_op(sc, 0);
6771 rc = sysctl_handle_int(oidp, &v, 0, req);
6776 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6778 struct vi_info *vi = arg1;
6781 val = vi->rsrv_noflowq;
6782 rc = sysctl_handle_int(oidp, &val, 0, req);
6783 if (rc != 0 || req->newptr == NULL)
6786 if ((val >= 1) && (vi->ntxq > 1))
6787 vi->rsrv_noflowq = 1;
6789 vi->rsrv_noflowq = 0;
6795 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6797 struct vi_info *vi = arg1;
6798 struct adapter *sc = vi->pi->adapter;
6800 struct sge_rxq *rxq;
6805 rc = sysctl_handle_int(oidp, &idx, 0, req);
6806 if (rc != 0 || req->newptr == NULL)
6809 if (idx < 0 || idx >= SGE_NTIMERS)
6812 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6817 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6818 for_each_rxq(vi, i, rxq) {
6819 #ifdef atomic_store_rel_8
6820 atomic_store_rel_8(&rxq->iq.intr_params, v);
6822 rxq->iq.intr_params = v;
6827 end_synchronized_op(sc, LOCK_HELD);
6832 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6834 struct vi_info *vi = arg1;
6835 struct adapter *sc = vi->pi->adapter;
6840 rc = sysctl_handle_int(oidp, &idx, 0, req);
6841 if (rc != 0 || req->newptr == NULL)
6844 if (idx < -1 || idx >= SGE_NCOUNTERS)
6847 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6852 if (vi->flags & VI_INIT_DONE)
6853 rc = EBUSY; /* cannot be changed once the queues are created */
6857 end_synchronized_op(sc, LOCK_HELD);
6862 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6864 struct vi_info *vi = arg1;
6865 struct adapter *sc = vi->pi->adapter;
6868 qsize = vi->qsize_rxq;
6870 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6871 if (rc != 0 || req->newptr == NULL)
6874 if (qsize < 128 || (qsize & 7))
6877 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6882 if (vi->flags & VI_INIT_DONE)
6883 rc = EBUSY; /* cannot be changed once the queues are created */
6885 vi->qsize_rxq = qsize;
6887 end_synchronized_op(sc, LOCK_HELD);
6892 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6894 struct vi_info *vi = arg1;
6895 struct adapter *sc = vi->pi->adapter;
6898 qsize = vi->qsize_txq;
6900 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6901 if (rc != 0 || req->newptr == NULL)
6904 if (qsize < 128 || qsize > 65536)
6907 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6912 if (vi->flags & VI_INIT_DONE)
6913 rc = EBUSY; /* cannot be changed once the queues are created */
6915 vi->qsize_txq = qsize;
6917 end_synchronized_op(sc, LOCK_HELD);
6922 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6924 struct port_info *pi = arg1;
6925 struct adapter *sc = pi->adapter;
6926 struct link_config *lc = &pi->link_cfg;
6929 if (req->newptr == NULL) {
6931 static char *bits = "\20\1RX\2TX\3AUTO";
6933 rc = sysctl_wire_old_buffer(req, 0);
6937 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6942 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6943 (lc->requested_fc & PAUSE_AUTONEG), bits);
6945 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6946 PAUSE_RX | PAUSE_AUTONEG), bits);
6948 rc = sbuf_finish(sb);
6954 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6958 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6964 if (s[0] < '0' || s[0] > '9')
6965 return (EINVAL); /* not a number */
6967 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6968 return (EINVAL); /* some other bit is set too */
6970 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6975 lc->requested_fc = n;
6976 fixup_link_config(pi);
6978 rc = apply_link_config(pi);
6979 set_current_media(pi);
6981 end_synchronized_op(sc, 0);
6988 sysctl_fec(SYSCTL_HANDLER_ARGS)
6990 struct port_info *pi = arg1;
6991 struct adapter *sc = pi->adapter;
6992 struct link_config *lc = &pi->link_cfg;
6996 if (req->newptr == NULL) {
6998 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
7000 rc = sysctl_wire_old_buffer(req, 0);
7004 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7009 * Display the requested_fec when the link is down -- the actual
7010 * FEC makes sense only when the link is up.
7013 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
7014 (lc->requested_fec & FEC_AUTO), bits);
7016 sbuf_printf(sb, "%b", lc->requested_fec, bits);
7018 rc = sbuf_finish(sb);
7024 snprintf(s, sizeof(s), "%d",
7025 lc->requested_fec == FEC_AUTO ? -1 :
7026 lc->requested_fec & M_FW_PORT_CAP32_FEC);
7028 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7032 n = strtol(&s[0], NULL, 0);
7033 if (n < 0 || n & FEC_AUTO)
7036 if (n & ~M_FW_PORT_CAP32_FEC)
7037 return (EINVAL);/* some other bit is set too */
7039 return (EINVAL);/* one bit can be set at most */
7042 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7047 old = lc->requested_fec;
7049 lc->requested_fec = FEC_AUTO;
7051 lc->requested_fec = FEC_NONE;
7053 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
7058 lc->requested_fec = n;
7060 fixup_link_config(pi);
7061 if (pi->up_vis > 0) {
7062 rc = apply_link_config(pi);
7064 lc->requested_fec = old;
7065 if (rc == FW_EPROTO)
7071 end_synchronized_op(sc, 0);
7078 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7080 struct port_info *pi = arg1;
7081 struct adapter *sc = pi->adapter;
7082 struct link_config *lc = &pi->link_cfg;
7085 if (lc->supported & FW_PORT_CAP32_ANEG)
7086 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7089 rc = sysctl_handle_int(oidp, &val, 0, req);
7090 if (rc != 0 || req->newptr == NULL)
7093 val = AUTONEG_DISABLE;
7095 val = AUTONEG_ENABLE;
7099 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7104 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
7108 lc->requested_aneg = val;
7109 fixup_link_config(pi);
7111 rc = apply_link_config(pi);
7112 set_current_media(pi);
7115 end_synchronized_op(sc, 0);
7120 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7122 struct adapter *sc = arg1;
7126 val = t4_read_reg64(sc, reg);
7128 return (sysctl_handle_64(oidp, &val, 0, req));
7132 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7134 struct adapter *sc = arg1;
7136 uint32_t param, val;
7138 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7141 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7142 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7143 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7144 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7145 end_synchronized_op(sc, 0);
7149 /* unknown is returned as 0 but we display -1 in that case */
7150 t = val == 0 ? -1 : val;
7152 rc = sysctl_handle_int(oidp, &t, 0, req);
7157 sysctl_vdd(SYSCTL_HANDLER_ARGS)
7159 struct adapter *sc = arg1;
7161 uint32_t param, val;
7163 if (sc->params.core_vdd == 0) {
7164 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7168 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7169 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7170 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
7171 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7172 end_synchronized_op(sc, 0);
7175 sc->params.core_vdd = val;
7178 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
7182 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7184 struct adapter *sc = arg1;
7187 uint32_t param, val;
7189 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7192 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7193 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7194 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7195 end_synchronized_op(sc, 0);
7199 rc = sysctl_wire_old_buffer(req, 0);
7203 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7207 if (val == 0xffffffff) {
7208 /* Only debug and custom firmwares report load averages. */
7209 sbuf_printf(sb, "not available");
7211 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7212 (val >> 16) & 0xff);
7214 rc = sbuf_finish(sb);
7221 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7223 struct adapter *sc = arg1;
7226 uint16_t incr[NMTUS][NCCTRL_WIN];
7227 static const char *dec_fac[] = {
7228 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7232 rc = sysctl_wire_old_buffer(req, 0);
7236 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7240 t4_read_cong_tbl(sc, incr);
7242 for (i = 0; i < NCCTRL_WIN; ++i) {
7243 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7244 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7245 incr[5][i], incr[6][i], incr[7][i]);
7246 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7247 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7248 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7249 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7252 rc = sbuf_finish(sb);
7258 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7259 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7260 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7261 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7265 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7267 struct adapter *sc = arg1;
7269 int rc, i, n, qid = arg2;
7272 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7274 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7275 ("%s: bad qid %d\n", __func__, qid));
7277 if (qid < CIM_NUM_IBQ) {
7280 n = 4 * CIM_IBQ_SIZE;
7281 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7282 rc = t4_read_cim_ibq(sc, qid, buf, n);
7284 /* outbound queue */
7287 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7288 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7289 rc = t4_read_cim_obq(sc, qid, buf, n);
7296 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7298 rc = sysctl_wire_old_buffer(req, 0);
7302 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7308 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7309 for (i = 0, p = buf; i < n; i += 16, p += 4)
7310 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7313 rc = sbuf_finish(sb);
7321 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7325 sbuf_printf(sb, "Status Data PC%s",
7326 cfg & F_UPDBGLACAPTPCONLY ? "" :
7327 " LS0Stat LS0Addr LS0Data");
7329 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7330 if (cfg & F_UPDBGLACAPTPCONLY) {
7331 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7333 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7334 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7335 p[4] & 0xff, p[5] >> 8);
7336 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7337 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7338 p[1] & 0xf, p[2] >> 4);
7341 "\n %02x %x%07x %x%07x %08x %08x "
7343 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7344 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7351 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7355 sbuf_printf(sb, "Status Inst Data PC%s",
7356 cfg & F_UPDBGLACAPTPCONLY ? "" :
7357 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7359 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7360 if (cfg & F_UPDBGLACAPTPCONLY) {
7361 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7362 p[3] & 0xff, p[2], p[1], p[0]);
7363 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7364 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7365 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7366 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7367 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7368 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7371 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7372 "%08x %08x %08x %08x %08x %08x",
7373 (p[9] >> 16) & 0xff,
7374 p[9] & 0xffff, p[8] >> 16,
7375 p[8] & 0xffff, p[7] >> 16,
7376 p[7] & 0xffff, p[6] >> 16,
7377 p[2], p[1], p[0], p[5], p[4], p[3]);
7383 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
7388 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7392 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7393 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7398 rc = -t4_cim_read_la(sc, buf, NULL);
7401 if (chip_id(sc) < CHELSIO_T6)
7402 sbuf_cim_la4(sc, sb, buf, cfg);
7404 sbuf_cim_la6(sc, sb, buf, cfg);
7412 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7414 struct adapter *sc = arg1;
7418 rc = sysctl_wire_old_buffer(req, 0);
7421 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7425 rc = sbuf_cim_la(sc, sb, M_WAITOK);
7427 rc = sbuf_finish(sb);
7433 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose)
7438 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7440 rc = sbuf_cim_la(sc, &sb, M_NOWAIT);
7442 rc = sbuf_finish(&sb);
7444 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s",
7445 device_get_nameunit(sc->dev), sbuf_data(&sb));
7453 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7455 struct adapter *sc = arg1;
7461 rc = sysctl_wire_old_buffer(req, 0);
7465 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7469 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7472 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7475 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7476 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7480 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7481 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7482 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7483 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7484 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7485 (p[1] >> 2) | ((p[2] & 3) << 30),
7486 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7490 rc = sbuf_finish(sb);
7497 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7499 struct adapter *sc = arg1;
7505 rc = sysctl_wire_old_buffer(req, 0);
7509 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7513 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7516 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7519 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7520 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7521 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7522 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7523 p[4], p[3], p[2], p[1], p[0]);
7526 sbuf_printf(sb, "\n\nCntl ID Data");
7527 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7528 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7529 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7532 rc = sbuf_finish(sb);
7539 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7541 struct adapter *sc = arg1;
7544 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7545 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7546 uint16_t thres[CIM_NUM_IBQ];
7547 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7548 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7549 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7551 cim_num_obq = sc->chip_params->cim_num_obq;
7553 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7554 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7556 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7557 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7559 nq = CIM_NUM_IBQ + cim_num_obq;
7561 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7563 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7567 t4_read_cimq_cfg(sc, base, size, thres);
7569 rc = sysctl_wire_old_buffer(req, 0);
7573 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7578 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7580 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7581 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7582 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7583 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7584 G_QUEREMFLITS(p[2]) * 16);
7585 for ( ; i < nq; i++, p += 4, wr += 2)
7586 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7587 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7588 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7589 G_QUEREMFLITS(p[2]) * 16);
7591 rc = sbuf_finish(sb);
7598 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7600 struct adapter *sc = arg1;
7603 struct tp_cpl_stats stats;
7605 rc = sysctl_wire_old_buffer(req, 0);
7609 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7613 mtx_lock(&sc->reg_lock);
7614 t4_tp_get_cpl_stats(sc, &stats, 0);
7615 mtx_unlock(&sc->reg_lock);
7617 if (sc->chip_params->nchan > 2) {
7618 sbuf_printf(sb, " channel 0 channel 1"
7619 " channel 2 channel 3");
7620 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7621 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7622 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7623 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7625 sbuf_printf(sb, " channel 0 channel 1");
7626 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7627 stats.req[0], stats.req[1]);
7628 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7629 stats.rsp[0], stats.rsp[1]);
7632 rc = sbuf_finish(sb);
7639 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7641 struct adapter *sc = arg1;
7644 struct tp_usm_stats stats;
7646 rc = sysctl_wire_old_buffer(req, 0);
7650 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7654 t4_get_usm_stats(sc, &stats, 1);
7656 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7657 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7658 sbuf_printf(sb, "Drops: %u", stats.drops);
7660 rc = sbuf_finish(sb);
7666 static const char * const devlog_level_strings[] = {
7667 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7668 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7669 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7670 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7671 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7672 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7675 static const char * const devlog_facility_strings[] = {
7676 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7677 [FW_DEVLOG_FACILITY_CF] = "CF",
7678 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7679 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7680 [FW_DEVLOG_FACILITY_RES] = "RES",
7681 [FW_DEVLOG_FACILITY_HW] = "HW",
7682 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7683 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7684 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7685 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7686 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7687 [FW_DEVLOG_FACILITY_VI] = "VI",
7688 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7689 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7690 [FW_DEVLOG_FACILITY_TM] = "TM",
7691 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7692 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7693 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7694 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7695 [FW_DEVLOG_FACILITY_RI] = "RI",
7696 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7697 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7698 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7699 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7700 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7704 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
7706 int i, j, rc, nentries, first = 0;
7707 struct devlog_params *dparams = &sc->params.devlog;
7708 struct fw_devlog_e *buf, *e;
7709 uint64_t ftstamp = UINT64_MAX;
7711 if (dparams->addr == 0)
7714 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7715 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
7719 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7723 nentries = dparams->size / sizeof(struct fw_devlog_e);
7724 for (i = 0; i < nentries; i++) {
7727 if (e->timestamp == 0)
7730 e->timestamp = be64toh(e->timestamp);
7731 e->seqno = be32toh(e->seqno);
7732 for (j = 0; j < 8; j++)
7733 e->params[j] = be32toh(e->params[j]);
7735 if (e->timestamp < ftstamp) {
7736 ftstamp = e->timestamp;
7741 if (buf[first].timestamp == 0)
7742 goto done; /* nothing in the log */
7744 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7745 "Seq#", "Tstamp", "Level", "Facility", "Message");
7750 if (e->timestamp == 0)
7753 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7754 e->seqno, e->timestamp,
7755 (e->level < nitems(devlog_level_strings) ?
7756 devlog_level_strings[e->level] : "UNKNOWN"),
7757 (e->facility < nitems(devlog_facility_strings) ?
7758 devlog_facility_strings[e->facility] : "UNKNOWN"));
7759 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7760 e->params[2], e->params[3], e->params[4],
7761 e->params[5], e->params[6], e->params[7]);
7763 if (++i == nentries)
7765 } while (i != first);
7772 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7774 struct adapter *sc = arg1;
7778 rc = sysctl_wire_old_buffer(req, 0);
7781 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7785 rc = sbuf_devlog(sc, sb, M_WAITOK);
7787 rc = sbuf_finish(sb);
7793 t4_os_dump_devlog(struct adapter *sc)
7798 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7800 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
7802 rc = sbuf_finish(&sb);
7804 log(LOG_DEBUG, "%s: device log follows.\n%s",
7805 device_get_nameunit(sc->dev), sbuf_data(&sb));
7812 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7814 struct adapter *sc = arg1;
7817 struct tp_fcoe_stats stats[MAX_NCHAN];
7818 int i, nchan = sc->chip_params->nchan;
7820 rc = sysctl_wire_old_buffer(req, 0);
7824 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7828 for (i = 0; i < nchan; i++)
7829 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7832 sbuf_printf(sb, " channel 0 channel 1"
7833 " channel 2 channel 3");
7834 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7835 stats[0].octets_ddp, stats[1].octets_ddp,
7836 stats[2].octets_ddp, stats[3].octets_ddp);
7837 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7838 stats[0].frames_ddp, stats[1].frames_ddp,
7839 stats[2].frames_ddp, stats[3].frames_ddp);
7840 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7841 stats[0].frames_drop, stats[1].frames_drop,
7842 stats[2].frames_drop, stats[3].frames_drop);
7844 sbuf_printf(sb, " channel 0 channel 1");
7845 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7846 stats[0].octets_ddp, stats[1].octets_ddp);
7847 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7848 stats[0].frames_ddp, stats[1].frames_ddp);
7849 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7850 stats[0].frames_drop, stats[1].frames_drop);
7853 rc = sbuf_finish(sb);
7860 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7862 struct adapter *sc = arg1;
7865 unsigned int map, kbps, ipg, mode;
7866 unsigned int pace_tab[NTX_SCHED];
7868 rc = sysctl_wire_old_buffer(req, 0);
7872 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7876 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7877 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7878 t4_read_pace_tbl(sc, pace_tab);
7880 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
7881 "Class IPG (0.1 ns) Flow IPG (us)");
7883 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7884 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7885 sbuf_printf(sb, "\n %u %-5s %u ", i,
7886 (mode & (1 << i)) ? "flow" : "class", map & 3);
7888 sbuf_printf(sb, "%9u ", kbps);
7890 sbuf_printf(sb, " disabled ");
7893 sbuf_printf(sb, "%13u ", ipg);
7895 sbuf_printf(sb, " disabled ");
7898 sbuf_printf(sb, "%10u", pace_tab[i]);
7900 sbuf_printf(sb, " disabled");
7903 rc = sbuf_finish(sb);
7910 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7912 struct adapter *sc = arg1;
7916 struct lb_port_stats s[2];
7917 static const char *stat_name[] = {
7918 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7919 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7920 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7921 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7922 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7923 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7924 "BG2FramesTrunc:", "BG3FramesTrunc:"
7927 rc = sysctl_wire_old_buffer(req, 0);
7931 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7935 memset(s, 0, sizeof(s));
7937 for (i = 0; i < sc->chip_params->nchan; i += 2) {
7938 t4_get_lb_stats(sc, i, &s[0]);
7939 t4_get_lb_stats(sc, i + 1, &s[1]);
7943 sbuf_printf(sb, "%s Loopback %u"
7944 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7946 for (j = 0; j < nitems(stat_name); j++)
7947 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7951 rc = sbuf_finish(sb);
7958 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7961 struct port_info *pi = arg1;
7962 struct link_config *lc = &pi->link_cfg;
7965 rc = sysctl_wire_old_buffer(req, 0);
7968 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7972 if (lc->link_ok || lc->link_down_rc == 255)
7973 sbuf_printf(sb, "n/a");
7975 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7977 rc = sbuf_finish(sb);
7990 mem_desc_cmp(const void *a, const void *b)
7992 return ((const struct mem_desc *)a)->base -
7993 ((const struct mem_desc *)b)->base;
7997 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
8005 size = to - from + 1;
8009 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
8010 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
8014 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
8016 struct adapter *sc = arg1;
8019 uint32_t lo, hi, used, alloc;
8020 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
8021 static const char *region[] = {
8022 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
8023 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
8024 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
8025 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
8026 "RQUDP region:", "PBL region:", "TXPBL region:",
8027 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
8028 "On-chip queues:", "TLS keys:",
8030 struct mem_desc avail[4];
8031 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
8032 struct mem_desc *md = mem;
8034 rc = sysctl_wire_old_buffer(req, 0);
8038 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8042 for (i = 0; i < nitems(mem); i++) {
8047 /* Find and sort the populated memory ranges */
8049 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
8050 if (lo & F_EDRAM0_ENABLE) {
8051 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
8052 avail[i].base = G_EDRAM0_BASE(hi) << 20;
8053 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
8057 if (lo & F_EDRAM1_ENABLE) {
8058 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
8059 avail[i].base = G_EDRAM1_BASE(hi) << 20;
8060 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
8064 if (lo & F_EXT_MEM_ENABLE) {
8065 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
8066 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
8067 avail[i].limit = avail[i].base +
8068 (G_EXT_MEM_SIZE(hi) << 20);
8069 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
8072 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
8073 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
8074 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
8075 avail[i].limit = avail[i].base +
8076 (G_EXT_MEM1_SIZE(hi) << 20);
8080 if (!i) /* no memory available */
8082 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8084 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8085 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8086 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8087 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8088 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8089 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8090 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8091 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8092 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8094 /* the next few have explicit upper bounds */
8095 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8096 md->limit = md->base - 1 +
8097 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8098 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8101 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8102 md->limit = md->base - 1 +
8103 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8104 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8107 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8108 if (chip_id(sc) <= CHELSIO_T5)
8109 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8111 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8115 md->idx = nitems(region); /* hide it */
8119 #define ulp_region(reg) \
8120 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8121 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8123 ulp_region(RX_ISCSI);
8124 ulp_region(RX_TDDP);
8126 ulp_region(RX_STAG);
8128 ulp_region(RX_RQUDP);
8134 md->idx = nitems(region);
8137 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8138 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8141 if (sge_ctrl & F_VFIFO_ENABLE)
8142 size = G_DBVFIFO_SIZE(fifo_size);
8144 size = G_T6_DBVFIFO_SIZE(fifo_size);
8147 md->base = G_BASEADDR(t4_read_reg(sc,
8148 A_SGE_DBVFIFO_BADDR));
8149 md->limit = md->base + (size << 2) - 1;
8154 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8157 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8161 md->base = sc->vres.ocq.start;
8162 if (sc->vres.ocq.size)
8163 md->limit = md->base + sc->vres.ocq.size - 1;
8165 md->idx = nitems(region); /* hide it */
8168 md->base = sc->vres.key.start;
8169 if (sc->vres.key.size)
8170 md->limit = md->base + sc->vres.key.size - 1;
8172 md->idx = nitems(region); /* hide it */
8175 /* add any address-space holes, there can be up to 3 */
8176 for (n = 0; n < i - 1; n++)
8177 if (avail[n].limit < avail[n + 1].base)
8178 (md++)->base = avail[n].limit;
8180 (md++)->base = avail[n].limit;
8183 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8185 for (lo = 0; lo < i; lo++)
8186 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8187 avail[lo].limit - 1);
8189 sbuf_printf(sb, "\n");
8190 for (i = 0; i < n; i++) {
8191 if (mem[i].idx >= nitems(region))
8192 continue; /* skip holes */
8194 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8195 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8199 sbuf_printf(sb, "\n");
8200 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8201 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8202 mem_region_show(sb, "uP RAM:", lo, hi);
8204 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8205 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8206 mem_region_show(sb, "uP Extmem2:", lo, hi);
8208 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8209 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8211 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8212 (lo & F_PMRXNUMCHN) ? 2 : 1);
8214 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8215 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8216 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8218 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8219 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8220 sbuf_printf(sb, "%u p-structs\n",
8221 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8223 for (i = 0; i < 4; i++) {
8224 if (chip_id(sc) > CHELSIO_T5)
8225 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8227 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8229 used = G_T5_USED(lo);
8230 alloc = G_T5_ALLOC(lo);
8233 alloc = G_ALLOC(lo);
8235 /* For T6 these are MAC buffer groups */
8236 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8239 for (i = 0; i < sc->chip_params->nchan; i++) {
8240 if (chip_id(sc) > CHELSIO_T5)
8241 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8243 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8245 used = G_T5_USED(lo);
8246 alloc = G_T5_ALLOC(lo);
8249 alloc = G_ALLOC(lo);
8251 /* For T6 these are MAC buffer groups */
8253 "\nLoopback %d using %u pages out of %u allocated",
8257 rc = sbuf_finish(sb);
8264 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8268 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8272 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8274 struct adapter *sc = arg1;
8278 MPASS(chip_id(sc) <= CHELSIO_T5);
8280 rc = sysctl_wire_old_buffer(req, 0);
8284 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8289 "Idx Ethernet address Mask Vld Ports PF"
8290 " VF Replication P0 P1 P2 P3 ML");
8291 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8292 uint64_t tcamx, tcamy, mask;
8293 uint32_t cls_lo, cls_hi;
8294 uint8_t addr[ETHER_ADDR_LEN];
8296 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8297 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8300 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8301 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8302 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8303 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8304 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8305 addr[3], addr[4], addr[5], (uintmax_t)mask,
8306 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8307 G_PORTMAP(cls_hi), G_PF(cls_lo),
8308 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8310 if (cls_lo & F_REPLICATE) {
8311 struct fw_ldst_cmd ldst_cmd;
8313 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8314 ldst_cmd.op_to_addrspace =
8315 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8316 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8317 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8318 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8319 ldst_cmd.u.mps.rplc.fid_idx =
8320 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8321 V_FW_LDST_CMD_IDX(i));
8323 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8327 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8328 sizeof(ldst_cmd), &ldst_cmd);
8329 end_synchronized_op(sc, 0);
8332 sbuf_printf(sb, "%36d", rc);
8335 sbuf_printf(sb, " %08x %08x %08x %08x",
8336 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8337 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8338 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8339 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8342 sbuf_printf(sb, "%36s", "");
8344 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8345 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8346 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8350 (void) sbuf_finish(sb);
8352 rc = sbuf_finish(sb);
8359 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8361 struct adapter *sc = arg1;
8365 MPASS(chip_id(sc) > CHELSIO_T5);
8367 rc = sysctl_wire_old_buffer(req, 0);
8371 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8375 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8376 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8378 " P0 P1 P2 P3 ML\n");
8380 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8381 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8383 uint64_t tcamx, tcamy, val, mask;
8384 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8385 uint8_t addr[ETHER_ADDR_LEN];
8387 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8389 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8391 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8392 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8393 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8394 tcamy = G_DMACH(val) << 32;
8395 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8396 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8397 lookup_type = G_DATALKPTYPE(data2);
8398 port_num = G_DATAPORTNUM(data2);
8399 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8400 /* Inner header VNI */
8401 vniy = ((data2 & F_DATAVIDH2) << 23) |
8402 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8403 dip_hit = data2 & F_DATADIPHIT;
8408 vlan_vld = data2 & F_DATAVIDH2;
8409 ivlan = G_VIDL(val);
8412 ctl |= V_CTLXYBITSEL(1);
8413 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8414 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8415 tcamx = G_DMACH(val) << 32;
8416 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8417 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8418 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8419 /* Inner header VNI mask */
8420 vnix = ((data2 & F_DATAVIDH2) << 23) |
8421 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8427 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8429 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8430 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8432 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8433 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8434 "%012jx %06x %06x - - %3c"
8435 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8436 addr[1], addr[2], addr[3], addr[4], addr[5],
8437 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8438 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8439 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8440 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8442 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8443 "%012jx - - ", i, addr[0], addr[1],
8444 addr[2], addr[3], addr[4], addr[5],
8448 sbuf_printf(sb, "%4u Y ", ivlan);
8450 sbuf_printf(sb, " - N ");
8452 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8453 lookup_type ? 'I' : 'O', port_num,
8454 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8455 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8456 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8460 if (cls_lo & F_T6_REPLICATE) {
8461 struct fw_ldst_cmd ldst_cmd;
8463 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8464 ldst_cmd.op_to_addrspace =
8465 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8466 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8467 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8468 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8469 ldst_cmd.u.mps.rplc.fid_idx =
8470 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8471 V_FW_LDST_CMD_IDX(i));
8473 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8477 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8478 sizeof(ldst_cmd), &ldst_cmd);
8479 end_synchronized_op(sc, 0);
8482 sbuf_printf(sb, "%72d", rc);
8485 sbuf_printf(sb, " %08x %08x %08x %08x"
8486 " %08x %08x %08x %08x",
8487 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8488 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8489 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8490 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8491 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8492 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8493 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8494 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8497 sbuf_printf(sb, "%72s", "");
8499 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8500 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8501 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8502 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8506 (void) sbuf_finish(sb);
8508 rc = sbuf_finish(sb);
8515 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8517 struct adapter *sc = arg1;
8520 uint16_t mtus[NMTUS];
8522 rc = sysctl_wire_old_buffer(req, 0);
8526 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8530 t4_read_mtu_tbl(sc, mtus, NULL);
8532 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8533 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8534 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8535 mtus[14], mtus[15]);
8537 rc = sbuf_finish(sb);
8544 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8546 struct adapter *sc = arg1;
8549 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8550 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8551 static const char *tx_stats[MAX_PM_NSTATS] = {
8552 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8553 "Tx FIFO wait", NULL, "Tx latency"
8555 static const char *rx_stats[MAX_PM_NSTATS] = {
8556 "Read:", "Write bypass:", "Write mem:", "Flush:",
8557 "Rx FIFO wait", NULL, "Rx latency"
8560 rc = sysctl_wire_old_buffer(req, 0);
8564 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8568 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8569 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8571 sbuf_printf(sb, " Tx pcmds Tx bytes");
8572 for (i = 0; i < 4; i++) {
8573 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8577 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8578 for (i = 0; i < 4; i++) {
8579 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8583 if (chip_id(sc) > CHELSIO_T5) {
8585 "\n Total wait Total occupancy");
8586 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8588 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8592 MPASS(i < nitems(tx_stats));
8595 "\n Reads Total wait");
8596 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8598 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8602 rc = sbuf_finish(sb);
8609 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8611 struct adapter *sc = arg1;
8614 struct tp_rdma_stats stats;
8616 rc = sysctl_wire_old_buffer(req, 0);
8620 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8624 mtx_lock(&sc->reg_lock);
8625 t4_tp_get_rdma_stats(sc, &stats, 0);
8626 mtx_unlock(&sc->reg_lock);
8628 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8629 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8631 rc = sbuf_finish(sb);
8638 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8640 struct adapter *sc = arg1;
8643 struct tp_tcp_stats v4, v6;
8645 rc = sysctl_wire_old_buffer(req, 0);
8649 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8653 mtx_lock(&sc->reg_lock);
8654 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8655 mtx_unlock(&sc->reg_lock);
8659 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8660 v4.tcp_out_rsts, v6.tcp_out_rsts);
8661 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8662 v4.tcp_in_segs, v6.tcp_in_segs);
8663 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8664 v4.tcp_out_segs, v6.tcp_out_segs);
8665 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8666 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8668 rc = sbuf_finish(sb);
8675 sysctl_tids(SYSCTL_HANDLER_ARGS)
8677 struct adapter *sc = arg1;
8680 struct tid_info *t = &sc->tids;
8682 rc = sysctl_wire_old_buffer(req, 0);
8686 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8691 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8696 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
8697 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
8701 sbuf_printf(sb, "TID range: ");
8702 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8705 if (chip_id(sc) <= CHELSIO_T5) {
8706 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8707 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8709 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8710 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8714 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
8715 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8717 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
8718 sbuf_printf(sb, ", in use: %u\n",
8719 atomic_load_acq_int(&t->tids_in_use));
8723 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8724 t->stid_base + t->nstids - 1, t->stids_in_use);
8728 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
8729 t->ftid_end, t->ftids_in_use);
8733 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8734 t->etid_base + t->netids - 1, t->etids_in_use);
8737 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8738 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8739 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8741 rc = sbuf_finish(sb);
8748 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8750 struct adapter *sc = arg1;
8753 struct tp_err_stats stats;
8755 rc = sysctl_wire_old_buffer(req, 0);
8759 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8763 mtx_lock(&sc->reg_lock);
8764 t4_tp_get_err_stats(sc, &stats, 0);
8765 mtx_unlock(&sc->reg_lock);
8767 if (sc->chip_params->nchan > 2) {
8768 sbuf_printf(sb, " channel 0 channel 1"
8769 " channel 2 channel 3\n");
8770 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8771 stats.mac_in_errs[0], stats.mac_in_errs[1],
8772 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8773 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8774 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8775 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8776 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8777 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8778 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8779 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8780 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8781 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8782 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8783 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8784 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8785 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8786 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8787 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8788 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8789 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8790 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8791 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8792 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8793 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8795 sbuf_printf(sb, " channel 0 channel 1\n");
8796 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8797 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8798 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8799 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8800 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8801 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8802 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8803 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8804 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8805 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8806 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8807 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8808 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8809 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8810 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8811 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8814 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8815 stats.ofld_no_neigh, stats.ofld_cong_defer);
8817 rc = sbuf_finish(sb);
8824 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8826 struct adapter *sc = arg1;
8827 struct tp_params *tpp = &sc->params.tp;
8831 mask = tpp->la_mask >> 16;
8832 rc = sysctl_handle_int(oidp, &mask, 0, req);
8833 if (rc != 0 || req->newptr == NULL)
8837 tpp->la_mask = mask << 16;
8838 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8850 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8856 uint64_t mask = (1ULL << f->width) - 1;
8857 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8858 ((uintmax_t)v >> f->start) & mask);
8860 if (line_size + len >= 79) {
8862 sbuf_printf(sb, "\n ");
8864 sbuf_printf(sb, "%s ", buf);
8865 line_size += len + 1;
8868 sbuf_printf(sb, "\n");
8871 static const struct field_desc tp_la0[] = {
8872 { "RcfOpCodeOut", 60, 4 },
8874 { "WcfState", 52, 4 },
8875 { "RcfOpcSrcOut", 50, 2 },
8876 { "CRxError", 49, 1 },
8877 { "ERxError", 48, 1 },
8878 { "SanityFailed", 47, 1 },
8879 { "SpuriousMsg", 46, 1 },
8880 { "FlushInputMsg", 45, 1 },
8881 { "FlushInputCpl", 44, 1 },
8882 { "RssUpBit", 43, 1 },
8883 { "RssFilterHit", 42, 1 },
8885 { "InitTcb", 31, 1 },
8886 { "LineNumber", 24, 7 },
8888 { "EdataOut", 22, 1 },
8890 { "CdataOut", 20, 1 },
8891 { "EreadPdu", 19, 1 },
8892 { "CreadPdu", 18, 1 },
8893 { "TunnelPkt", 17, 1 },
8894 { "RcfPeerFin", 16, 1 },
8895 { "RcfReasonOut", 12, 4 },
8896 { "TxCchannel", 10, 2 },
8897 { "RcfTxChannel", 8, 2 },
8898 { "RxEchannel", 6, 2 },
8899 { "RcfRxChannel", 5, 1 },
8900 { "RcfDataOutSrdy", 4, 1 },
8902 { "RxOoDvld", 2, 1 },
8903 { "RxCongestion", 1, 1 },
8904 { "TxCongestion", 0, 1 },
8908 static const struct field_desc tp_la1[] = {
8909 { "CplCmdIn", 56, 8 },
8910 { "CplCmdOut", 48, 8 },
8911 { "ESynOut", 47, 1 },
8912 { "EAckOut", 46, 1 },
8913 { "EFinOut", 45, 1 },
8914 { "ERstOut", 44, 1 },
8919 { "DataIn", 39, 1 },
8920 { "DataInVld", 38, 1 },
8922 { "RxBufEmpty", 36, 1 },
8924 { "RxFbCongestion", 34, 1 },
8925 { "TxFbCongestion", 33, 1 },
8926 { "TxPktSumSrdy", 32, 1 },
8927 { "RcfUlpType", 28, 4 },
8929 { "Ebypass", 26, 1 },
8931 { "Static0", 24, 1 },
8933 { "Cbypass", 22, 1 },
8935 { "CPktOut", 20, 1 },
8936 { "RxPagePoolFull", 18, 2 },
8937 { "RxLpbkPkt", 17, 1 },
8938 { "TxLpbkPkt", 16, 1 },
8939 { "RxVfValid", 15, 1 },
8940 { "SynLearned", 14, 1 },
8941 { "SetDelEntry", 13, 1 },
8942 { "SetInvEntry", 12, 1 },
8943 { "CpcmdDvld", 11, 1 },
8944 { "CpcmdSave", 10, 1 },
8945 { "RxPstructsFull", 8, 2 },
8946 { "EpcmdDvld", 7, 1 },
8947 { "EpcmdFlush", 6, 1 },
8948 { "EpcmdTrimPrefix", 5, 1 },
8949 { "EpcmdTrimPostfix", 4, 1 },
8950 { "ERssIp4Pkt", 3, 1 },
8951 { "ERssIp6Pkt", 2, 1 },
8952 { "ERssTcpUdpPkt", 1, 1 },
8953 { "ERssFceFipPkt", 0, 1 },
8957 static const struct field_desc tp_la2[] = {
8958 { "CplCmdIn", 56, 8 },
8959 { "MpsVfVld", 55, 1 },
8966 { "DataIn", 39, 1 },
8967 { "DataInVld", 38, 1 },
8969 { "RxBufEmpty", 36, 1 },
8971 { "RxFbCongestion", 34, 1 },
8972 { "TxFbCongestion", 33, 1 },
8973 { "TxPktSumSrdy", 32, 1 },
8974 { "RcfUlpType", 28, 4 },
8976 { "Ebypass", 26, 1 },
8978 { "Static0", 24, 1 },
8980 { "Cbypass", 22, 1 },
8982 { "CPktOut", 20, 1 },
8983 { "RxPagePoolFull", 18, 2 },
8984 { "RxLpbkPkt", 17, 1 },
8985 { "TxLpbkPkt", 16, 1 },
8986 { "RxVfValid", 15, 1 },
8987 { "SynLearned", 14, 1 },
8988 { "SetDelEntry", 13, 1 },
8989 { "SetInvEntry", 12, 1 },
8990 { "CpcmdDvld", 11, 1 },
8991 { "CpcmdSave", 10, 1 },
8992 { "RxPstructsFull", 8, 2 },
8993 { "EpcmdDvld", 7, 1 },
8994 { "EpcmdFlush", 6, 1 },
8995 { "EpcmdTrimPrefix", 5, 1 },
8996 { "EpcmdTrimPostfix", 4, 1 },
8997 { "ERssIp4Pkt", 3, 1 },
8998 { "ERssIp6Pkt", 2, 1 },
8999 { "ERssTcpUdpPkt", 1, 1 },
9000 { "ERssFceFipPkt", 0, 1 },
9005 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
9008 field_desc_show(sb, *p, tp_la0);
9012 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
9016 sbuf_printf(sb, "\n");
9017 field_desc_show(sb, p[0], tp_la0);
9018 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9019 field_desc_show(sb, p[1], tp_la0);
9023 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
9027 sbuf_printf(sb, "\n");
9028 field_desc_show(sb, p[0], tp_la0);
9029 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9030 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
9034 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
9036 struct adapter *sc = arg1;
9041 void (*show_func)(struct sbuf *, uint64_t *, int);
9043 rc = sysctl_wire_old_buffer(req, 0);
9047 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9051 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
9053 t4_tp_read_la(sc, buf, NULL);
9056 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
9059 show_func = tp_la_show2;
9063 show_func = tp_la_show3;
9067 show_func = tp_la_show;
9070 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
9071 (*show_func)(sb, p, i);
9073 rc = sbuf_finish(sb);
9080 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9082 struct adapter *sc = arg1;
9085 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9087 rc = sysctl_wire_old_buffer(req, 0);
9091 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9095 t4_get_chan_txrate(sc, nrate, orate);
9097 if (sc->chip_params->nchan > 2) {
9098 sbuf_printf(sb, " channel 0 channel 1"
9099 " channel 2 channel 3\n");
9100 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9101 nrate[0], nrate[1], nrate[2], nrate[3]);
9102 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9103 orate[0], orate[1], orate[2], orate[3]);
9105 sbuf_printf(sb, " channel 0 channel 1\n");
9106 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9107 nrate[0], nrate[1]);
9108 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9109 orate[0], orate[1]);
9112 rc = sbuf_finish(sb);
9119 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9121 struct adapter *sc = arg1;
9126 rc = sysctl_wire_old_buffer(req, 0);
9130 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9134 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9137 t4_ulprx_read_la(sc, buf);
9140 sbuf_printf(sb, " Pcmd Type Message"
9142 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9143 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9144 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9147 rc = sbuf_finish(sb);
9154 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9156 struct adapter *sc = arg1;
9160 MPASS(chip_id(sc) >= CHELSIO_T5);
9162 rc = sysctl_wire_old_buffer(req, 0);
9166 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9170 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9171 if (G_STATSOURCE_T5(v) == 7) {
9174 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9176 sbuf_printf(sb, "total %d, incomplete %d",
9177 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9178 t4_read_reg(sc, A_SGE_STAT_MATCH));
9179 } else if (mode == 1) {
9180 sbuf_printf(sb, "total %d, data overflow %d",
9181 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9182 t4_read_reg(sc, A_SGE_STAT_MATCH));
9184 sbuf_printf(sb, "unknown mode %d", mode);
9187 rc = sbuf_finish(sb);
9194 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9196 struct adapter *sc = arg1;
9197 enum cpu_sets op = arg2;
9202 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9205 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9209 rc = sysctl_wire_old_buffer(req, 0);
9213 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9218 sbuf_printf(sb, "%d ", i);
9219 rc = sbuf_finish(sb);
9227 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9229 struct adapter *sc = arg1;
9230 int *old_ports, *new_ports;
9231 int i, new_count, rc;
9233 if (req->newptr == NULL && req->oldptr == NULL)
9234 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9235 sizeof(sc->tt.tls_rx_ports[0])));
9237 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9241 if (sc->tt.num_tls_rx_ports == 0) {
9243 rc = SYSCTL_OUT(req, &i, sizeof(i));
9245 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9246 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9247 if (rc == 0 && req->newptr != NULL) {
9248 new_count = req->newlen / sizeof(new_ports[0]);
9249 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9251 rc = SYSCTL_IN(req, new_ports, new_count *
9252 sizeof(new_ports[0]));
9256 /* Allow setting to a single '-1' to clear the list. */
9257 if (new_count == 1 && new_ports[0] == -1) {
9259 old_ports = sc->tt.tls_rx_ports;
9260 sc->tt.tls_rx_ports = NULL;
9261 sc->tt.num_tls_rx_ports = 0;
9263 free(old_ports, M_CXGBE);
9265 for (i = 0; i < new_count; i++) {
9266 if (new_ports[i] < 1 ||
9267 new_ports[i] > IPPORT_MAX) {
9274 old_ports = sc->tt.tls_rx_ports;
9275 sc->tt.tls_rx_ports = new_ports;
9276 sc->tt.num_tls_rx_ports = new_count;
9278 free(old_ports, M_CXGBE);
9282 free(new_ports, M_CXGBE);
9284 end_synchronized_op(sc, 0);
9289 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9291 u_int rem = val % factor;
9294 snprintf(buf, len, "%u", val / factor);
9296 while (rem % 10 == 0)
9298 snprintf(buf, len, "%u.%u", val / factor, rem);
9303 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9305 struct adapter *sc = arg1;
9308 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9310 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9314 re = G_TIMERRESOLUTION(res);
9317 /* TCP timestamp tick */
9318 re = G_TIMESTAMPRESOLUTION(res);
9322 re = G_DELAYEDACKRESOLUTION(res);
9328 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9330 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9334 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9336 struct adapter *sc = arg1;
9337 u_int res, dack_re, v;
9338 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9340 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9341 dack_re = G_DELAYEDACKRESOLUTION(res);
9342 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9344 return (sysctl_handle_int(oidp, &v, 0, req));
9348 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9350 struct adapter *sc = arg1;
9353 u_long tp_tick_us, v;
9354 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9356 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9357 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9358 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9359 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9361 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9362 tp_tick_us = (cclk_ps << tre) / 1000000;
9364 if (reg == A_TP_INIT_SRTT)
9365 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9367 v = tp_tick_us * t4_read_reg(sc, reg);
9369 return (sysctl_handle_long(oidp, &v, 0, req));
9373 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9374 * passed to this function.
9377 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9379 struct adapter *sc = arg1;
9383 MPASS(idx >= 0 && idx <= 24);
9385 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9387 return (sysctl_handle_int(oidp, &v, 0, req));
9391 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9393 struct adapter *sc = arg1;
9397 MPASS(idx >= 0 && idx < 16);
9399 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9400 shift = (idx & 3) << 3;
9401 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9403 return (sysctl_handle_int(oidp, &v, 0, req));
9407 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9409 struct vi_info *vi = arg1;
9410 struct adapter *sc = vi->pi->adapter;
9412 struct sge_ofld_rxq *ofld_rxq;
9415 idx = vi->ofld_tmr_idx;
9417 rc = sysctl_handle_int(oidp, &idx, 0, req);
9418 if (rc != 0 || req->newptr == NULL)
9421 if (idx < 0 || idx >= SGE_NTIMERS)
9424 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9429 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9430 for_each_ofld_rxq(vi, i, ofld_rxq) {
9431 #ifdef atomic_store_rel_8
9432 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9434 ofld_rxq->iq.intr_params = v;
9437 vi->ofld_tmr_idx = idx;
9439 end_synchronized_op(sc, LOCK_HELD);
9444 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9446 struct vi_info *vi = arg1;
9447 struct adapter *sc = vi->pi->adapter;
9450 idx = vi->ofld_pktc_idx;
9452 rc = sysctl_handle_int(oidp, &idx, 0, req);
9453 if (rc != 0 || req->newptr == NULL)
9456 if (idx < -1 || idx >= SGE_NCOUNTERS)
9459 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9464 if (vi->flags & VI_INIT_DONE)
9465 rc = EBUSY; /* cannot be changed once the queues are created */
9467 vi->ofld_pktc_idx = idx;
9469 end_synchronized_op(sc, LOCK_HELD);
9475 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9479 if (cntxt->cid > M_CTXTQID)
9482 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9483 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9486 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9490 if (sc->flags & FW_OK) {
9491 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9498 * Read via firmware failed or wasn't even attempted. Read directly via
9501 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9503 end_synchronized_op(sc, 0);
9508 load_fw(struct adapter *sc, struct t4_data *fw)
9513 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9518 * The firmware, with the sole exception of the memory parity error
9519 * handler, runs from memory and not flash. It is almost always safe to
9520 * install a new firmware on a running system. Just set bit 1 in
9521 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9523 if (sc->flags & FULL_INIT_DONE &&
9524 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9529 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9530 if (fw_data == NULL) {
9535 rc = copyin(fw->data, fw_data, fw->len);
9537 rc = -t4_load_fw(sc, fw_data, fw->len);
9539 free(fw_data, M_CXGBE);
9541 end_synchronized_op(sc, 0);
9546 load_cfg(struct adapter *sc, struct t4_data *cfg)
9549 uint8_t *cfg_data = NULL;
9551 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9555 if (cfg->len == 0) {
9557 rc = -t4_load_cfg(sc, NULL, 0);
9561 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9562 if (cfg_data == NULL) {
9567 rc = copyin(cfg->data, cfg_data, cfg->len);
9569 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9571 free(cfg_data, M_CXGBE);
9573 end_synchronized_op(sc, 0);
9578 load_boot(struct adapter *sc, struct t4_bootrom *br)
9581 uint8_t *br_data = NULL;
9584 if (br->len > 1024 * 1024)
9587 if (br->pf_offset == 0) {
9589 if (br->pfidx_addr > 7)
9591 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9592 A_PCIE_PF_EXPROM_OFST)));
9593 } else if (br->pf_offset == 1) {
9595 offset = G_OFFSET(br->pfidx_addr);
9600 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9606 rc = -t4_load_boot(sc, NULL, offset, 0);
9610 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9611 if (br_data == NULL) {
9616 rc = copyin(br->data, br_data, br->len);
9618 rc = -t4_load_boot(sc, br_data, offset, br->len);
9620 free(br_data, M_CXGBE);
9622 end_synchronized_op(sc, 0);
9627 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9630 uint8_t *bc_data = NULL;
9632 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9638 rc = -t4_load_bootcfg(sc, NULL, 0);
9642 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9643 if (bc_data == NULL) {
9648 rc = copyin(bc->data, bc_data, bc->len);
9650 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9652 free(bc_data, M_CXGBE);
9654 end_synchronized_op(sc, 0);
9659 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9662 struct cudbg_init *cudbg;
9665 /* buf is large, don't block if no memory is available */
9666 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9670 handle = cudbg_alloc_handle();
9671 if (handle == NULL) {
9676 cudbg = cudbg_get_init(handle);
9678 cudbg->print = (cudbg_print_cb)printf;
9681 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9682 __func__, dump->wr_flash, dump->len, dump->data);
9686 cudbg->use_flash = 1;
9687 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9688 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9690 rc = cudbg_collect(handle, buf, &dump->len);
9694 rc = copyout(buf, dump->data, dump->len);
9696 cudbg_free_handle(handle);
9702 free_offload_policy(struct t4_offload_policy *op)
9704 struct offload_rule *r;
9711 for (i = 0; i < op->nrules; i++, r++) {
9712 free(r->bpf_prog.bf_insns, M_CXGBE);
9714 free(op->rule, M_CXGBE);
9719 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9722 struct t4_offload_policy *op, *old;
9723 struct bpf_program *bf;
9724 const struct offload_settings *s;
9725 struct offload_rule *r;
9728 if (!is_offload(sc))
9731 if (uop->nrules == 0) {
9732 /* Delete installed policies. */
9735 } if (uop->nrules > 256) { /* arbitrary */
9739 /* Copy userspace offload policy to kernel */
9740 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9741 op->nrules = uop->nrules;
9742 len = op->nrules * sizeof(struct offload_rule);
9743 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9744 rc = copyin(uop->rule, op->rule, len);
9746 free(op->rule, M_CXGBE);
9752 for (i = 0; i < op->nrules; i++, r++) {
9754 /* Validate open_type */
9755 if (r->open_type != OPEN_TYPE_LISTEN &&
9756 r->open_type != OPEN_TYPE_ACTIVE &&
9757 r->open_type != OPEN_TYPE_PASSIVE &&
9758 r->open_type != OPEN_TYPE_DONTCARE) {
9761 * Rules 0 to i have malloc'd filters that need to be
9762 * freed. Rules i+1 to nrules have userspace pointers
9763 * and should be left alone.
9766 free_offload_policy(op);
9770 /* Validate settings */
9772 if ((s->offload != 0 && s->offload != 1) ||
9773 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9774 s->sched_class < -1 ||
9775 s->sched_class >= sc->chip_params->nsched_cls) {
9781 u = bf->bf_insns; /* userspace ptr */
9782 bf->bf_insns = NULL;
9783 if (bf->bf_len == 0) {
9784 /* legal, matches everything */
9787 len = bf->bf_len * sizeof(*bf->bf_insns);
9788 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9789 rc = copyin(u, bf->bf_insns, len);
9793 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9799 rw_wlock(&sc->policy_lock);
9802 rw_wunlock(&sc->policy_lock);
9803 free_offload_policy(old);
9808 #define MAX_READ_BUF_SIZE (128 * 1024)
9810 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9812 uint32_t addr, remaining, n;
9817 rc = validate_mem_range(sc, mr->addr, mr->len);
9821 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9823 remaining = mr->len;
9824 dst = (void *)mr->data;
9827 n = min(remaining, MAX_READ_BUF_SIZE);
9828 read_via_memwin(sc, 2, addr, buf, n);
9830 rc = copyout(buf, dst, n);
9842 #undef MAX_READ_BUF_SIZE
9845 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9849 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9852 if (i2cd->len > sizeof(i2cd->data))
9855 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9858 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9859 i2cd->offset, i2cd->len, &i2cd->data[0]);
9860 end_synchronized_op(sc, 0);
9866 clear_stats(struct adapter *sc, u_int port_id)
9869 struct port_info *pi;
9871 struct sge_rxq *rxq;
9872 struct sge_txq *txq;
9873 struct sge_wrq *wrq;
9875 struct sge_ofld_rxq *ofld_rxq;
9878 if (port_id >= sc->params.nports)
9880 pi = sc->port[port_id];
9885 t4_clr_port_stats(sc, pi->tx_chan);
9886 pi->tx_parse_error = 0;
9887 pi->tnl_cong_drops = 0;
9888 mtx_lock(&sc->reg_lock);
9889 for_each_vi(pi, v, vi) {
9890 if (vi->flags & VI_INIT_DONE)
9891 t4_clr_vi_stats(sc, vi->vin);
9893 bg_map = pi->mps_bg_map;
9896 i = ffs(bg_map) - 1;
9897 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
9898 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
9899 bg_map &= ~(1 << i);
9901 mtx_unlock(&sc->reg_lock);
9904 * Since this command accepts a port, clear stats for
9905 * all VIs on this port.
9907 for_each_vi(pi, v, vi) {
9908 if (vi->flags & VI_INIT_DONE) {
9910 for_each_rxq(vi, i, rxq) {
9911 #if defined(INET) || defined(INET6)
9912 rxq->lro.lro_queued = 0;
9913 rxq->lro.lro_flushed = 0;
9916 rxq->vlan_extraction = 0;
9918 rxq->fl.mbuf_allocated = 0;
9919 rxq->fl.mbuf_inlined = 0;
9920 rxq->fl.cl_allocated = 0;
9921 rxq->fl.cl_recycled = 0;
9922 rxq->fl.cl_fast_recycled = 0;
9925 for_each_txq(vi, i, txq) {
9928 txq->vlan_insertion = 0;
9932 txq->txpkts0_wrs = 0;
9933 txq->txpkts1_wrs = 0;
9934 txq->txpkts0_pkts = 0;
9935 txq->txpkts1_pkts = 0;
9937 mp_ring_reset_stats(txq->r);
9940 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
9941 for_each_ofld_txq(vi, i, wrq) {
9942 wrq->tx_wrs_direct = 0;
9943 wrq->tx_wrs_copied = 0;
9947 for_each_ofld_rxq(vi, i, ofld_rxq) {
9948 ofld_rxq->fl.mbuf_allocated = 0;
9949 ofld_rxq->fl.mbuf_inlined = 0;
9950 ofld_rxq->fl.cl_allocated = 0;
9951 ofld_rxq->fl.cl_recycled = 0;
9952 ofld_rxq->fl.cl_fast_recycled = 0;
9956 if (IS_MAIN_VI(vi)) {
9957 wrq = &sc->sge.ctrlq[pi->port_id];
9958 wrq->tx_wrs_direct = 0;
9959 wrq->tx_wrs_copied = 0;
9968 t4_os_find_pci_capability(struct adapter *sc, int cap)
9972 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9976 t4_os_pci_save_state(struct adapter *sc)
9979 struct pci_devinfo *dinfo;
9982 dinfo = device_get_ivars(dev);
9984 pci_cfg_save(dev, dinfo, 0);
9989 t4_os_pci_restore_state(struct adapter *sc)
9992 struct pci_devinfo *dinfo;
9995 dinfo = device_get_ivars(dev);
9997 pci_cfg_restore(dev, dinfo);
10002 t4_os_portmod_changed(struct port_info *pi)
10004 struct adapter *sc = pi->adapter;
10005 struct vi_info *vi;
10007 static const char *mod_str[] = {
10008 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
10011 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
10012 ("%s: port_type %u", __func__, pi->port_type));
10015 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
10017 build_medialist(pi);
10018 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
10019 fixup_link_config(pi);
10020 apply_link_config(pi);
10023 end_synchronized_op(sc, LOCK_HELD);
10027 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
10028 if_printf(ifp, "transceiver unplugged.\n");
10029 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
10030 if_printf(ifp, "unknown transceiver inserted.\n");
10031 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
10032 if_printf(ifp, "unsupported transceiver inserted.\n");
10033 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
10034 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
10035 port_top_speed(pi), mod_str[pi->mod_type]);
10037 if_printf(ifp, "transceiver (type %d) inserted.\n",
10043 t4_os_link_changed(struct port_info *pi)
10045 struct vi_info *vi;
10047 struct link_config *lc;
10050 PORT_LOCK_ASSERT_OWNED(pi);
10052 for_each_vi(pi, v, vi) {
10057 lc = &pi->link_cfg;
10059 ifp->if_baudrate = IF_Mbps(lc->speed);
10060 if_link_state_change(ifp, LINK_STATE_UP);
10062 if_link_state_change(ifp, LINK_STATE_DOWN);
10068 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
10070 struct adapter *sc;
10072 sx_slock(&t4_list_lock);
10073 SLIST_FOREACH(sc, &t4_list, link) {
10075 * func should not make any assumptions about what state sc is
10076 * in - the only guarantee is that sc->sc_lock is a valid lock.
10080 sx_sunlock(&t4_list_lock);
10084 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
10088 struct adapter *sc = dev->si_drv1;
10090 rc = priv_check(td, PRIV_DRIVER);
10095 case CHELSIO_T4_GETREG: {
10096 struct t4_reg *edata = (struct t4_reg *)data;
10098 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10101 if (edata->size == 4)
10102 edata->val = t4_read_reg(sc, edata->addr);
10103 else if (edata->size == 8)
10104 edata->val = t4_read_reg64(sc, edata->addr);
10110 case CHELSIO_T4_SETREG: {
10111 struct t4_reg *edata = (struct t4_reg *)data;
10113 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10116 if (edata->size == 4) {
10117 if (edata->val & 0xffffffff00000000)
10119 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
10120 } else if (edata->size == 8)
10121 t4_write_reg64(sc, edata->addr, edata->val);
10126 case CHELSIO_T4_REGDUMP: {
10127 struct t4_regdump *regs = (struct t4_regdump *)data;
10128 int reglen = t4_get_regs_len(sc);
10131 if (regs->len < reglen) {
10132 regs->len = reglen; /* hint to the caller */
10136 regs->len = reglen;
10137 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
10138 get_regs(sc, regs, buf);
10139 rc = copyout(buf, regs->data, reglen);
10140 free(buf, M_CXGBE);
10143 case CHELSIO_T4_GET_FILTER_MODE:
10144 rc = get_filter_mode(sc, (uint32_t *)data);
10146 case CHELSIO_T4_SET_FILTER_MODE:
10147 rc = set_filter_mode(sc, *(uint32_t *)data);
10149 case CHELSIO_T4_GET_FILTER:
10150 rc = get_filter(sc, (struct t4_filter *)data);
10152 case CHELSIO_T4_SET_FILTER:
10153 rc = set_filter(sc, (struct t4_filter *)data);
10155 case CHELSIO_T4_DEL_FILTER:
10156 rc = del_filter(sc, (struct t4_filter *)data);
10158 case CHELSIO_T4_GET_SGE_CONTEXT:
10159 rc = get_sge_context(sc, (struct t4_sge_context *)data);
10161 case CHELSIO_T4_LOAD_FW:
10162 rc = load_fw(sc, (struct t4_data *)data);
10164 case CHELSIO_T4_GET_MEM:
10165 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
10167 case CHELSIO_T4_GET_I2C:
10168 rc = read_i2c(sc, (struct t4_i2c_data *)data);
10170 case CHELSIO_T4_CLEAR_STATS:
10171 rc = clear_stats(sc, *(uint32_t *)data);
10173 case CHELSIO_T4_SCHED_CLASS:
10174 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10176 case CHELSIO_T4_SCHED_QUEUE:
10177 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10179 case CHELSIO_T4_GET_TRACER:
10180 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10182 case CHELSIO_T4_SET_TRACER:
10183 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10185 case CHELSIO_T4_LOAD_CFG:
10186 rc = load_cfg(sc, (struct t4_data *)data);
10188 case CHELSIO_T4_LOAD_BOOT:
10189 rc = load_boot(sc, (struct t4_bootrom *)data);
10191 case CHELSIO_T4_LOAD_BOOTCFG:
10192 rc = load_bootcfg(sc, (struct t4_data *)data);
10194 case CHELSIO_T4_CUDBG_DUMP:
10195 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10197 case CHELSIO_T4_SET_OFLD_POLICY:
10198 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10209 toe_capability(struct vi_info *vi, int enable)
10212 struct port_info *pi = vi->pi;
10213 struct adapter *sc = pi->adapter;
10215 ASSERT_SYNCHRONIZED_OP(sc);
10217 if (!is_offload(sc))
10221 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10222 /* TOE is already enabled. */
10227 * We need the port's queues around so that we're able to send
10228 * and receive CPLs to/from the TOE even if the ifnet for this
10229 * port has never been UP'd administratively.
10231 if (!(vi->flags & VI_INIT_DONE)) {
10232 rc = vi_full_init(vi);
10236 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10237 rc = vi_full_init(&pi->vi[0]);
10242 if (isset(&sc->offload_map, pi->port_id)) {
10243 /* TOE is enabled on another VI of this port. */
10248 if (!uld_active(sc, ULD_TOM)) {
10249 rc = t4_activate_uld(sc, ULD_TOM);
10250 if (rc == EAGAIN) {
10252 "You must kldload t4_tom.ko before trying "
10253 "to enable TOE on a cxgbe interface.\n");
10257 KASSERT(sc->tom_softc != NULL,
10258 ("%s: TOM activated but softc NULL", __func__));
10259 KASSERT(uld_active(sc, ULD_TOM),
10260 ("%s: TOM activated but flag not set", __func__));
10263 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10264 if (!uld_active(sc, ULD_IWARP))
10265 (void) t4_activate_uld(sc, ULD_IWARP);
10266 if (!uld_active(sc, ULD_ISCSI))
10267 (void) t4_activate_uld(sc, ULD_ISCSI);
10270 setbit(&sc->offload_map, pi->port_id);
10274 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10277 KASSERT(uld_active(sc, ULD_TOM),
10278 ("%s: TOM never initialized?", __func__));
10279 clrbit(&sc->offload_map, pi->port_id);
10286 * Add an upper layer driver to the global list.
10289 t4_register_uld(struct uld_info *ui)
10292 struct uld_info *u;
10294 sx_xlock(&t4_uld_list_lock);
10295 SLIST_FOREACH(u, &t4_uld_list, link) {
10296 if (u->uld_id == ui->uld_id) {
10302 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10305 sx_xunlock(&t4_uld_list_lock);
10310 t4_unregister_uld(struct uld_info *ui)
10313 struct uld_info *u;
10315 sx_xlock(&t4_uld_list_lock);
10317 SLIST_FOREACH(u, &t4_uld_list, link) {
10319 if (ui->refcount > 0) {
10324 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10330 sx_xunlock(&t4_uld_list_lock);
10335 t4_activate_uld(struct adapter *sc, int id)
10338 struct uld_info *ui;
10340 ASSERT_SYNCHRONIZED_OP(sc);
10342 if (id < 0 || id > ULD_MAX)
10344 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10346 sx_slock(&t4_uld_list_lock);
10348 SLIST_FOREACH(ui, &t4_uld_list, link) {
10349 if (ui->uld_id == id) {
10350 if (!(sc->flags & FULL_INIT_DONE)) {
10351 rc = adapter_full_init(sc);
10356 rc = ui->activate(sc);
10358 setbit(&sc->active_ulds, id);
10365 sx_sunlock(&t4_uld_list_lock);
10371 t4_deactivate_uld(struct adapter *sc, int id)
10374 struct uld_info *ui;
10376 ASSERT_SYNCHRONIZED_OP(sc);
10378 if (id < 0 || id > ULD_MAX)
10382 sx_slock(&t4_uld_list_lock);
10384 SLIST_FOREACH(ui, &t4_uld_list, link) {
10385 if (ui->uld_id == id) {
10386 rc = ui->deactivate(sc);
10388 clrbit(&sc->active_ulds, id);
10395 sx_sunlock(&t4_uld_list_lock);
10401 uld_active(struct adapter *sc, int uld_id)
10404 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10406 return (isset(&sc->active_ulds, uld_id));
10411 * t = ptr to tunable.
10412 * nc = number of CPUs.
10413 * c = compiled in default for that tunable.
10416 calculate_nqueues(int *t, int nc, const int c)
10422 nq = *t < 0 ? -*t : c;
10427 * Come up with reasonable defaults for some of the tunables, provided they're
10428 * not set by the user (in which case we'll use the values as is).
10431 tweak_tunables(void)
10433 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10437 t4_ntxq = rss_getnumbuckets();
10439 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10443 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10447 t4_nrxq = rss_getnumbuckets();
10449 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10453 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10455 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10456 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10457 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10460 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10461 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10463 if (t4_toecaps_allowed == -1)
10464 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10466 if (t4_rdmacaps_allowed == -1) {
10467 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10468 FW_CAPS_CONFIG_RDMA_RDMAC;
10471 if (t4_iscsicaps_allowed == -1) {
10472 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10473 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10474 FW_CAPS_CONFIG_ISCSI_T10DIF;
10477 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10478 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10480 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10481 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10483 if (t4_toecaps_allowed == -1)
10484 t4_toecaps_allowed = 0;
10486 if (t4_rdmacaps_allowed == -1)
10487 t4_rdmacaps_allowed = 0;
10489 if (t4_iscsicaps_allowed == -1)
10490 t4_iscsicaps_allowed = 0;
10494 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10495 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10498 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10499 t4_tmr_idx = TMR_IDX;
10501 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10502 t4_pktc_idx = PKTC_IDX;
10504 if (t4_qsize_txq < 128)
10505 t4_qsize_txq = 128;
10507 if (t4_qsize_rxq < 128)
10508 t4_qsize_rxq = 128;
10509 while (t4_qsize_rxq & 7)
10512 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10515 * Number of VIs to create per-port. The first VI is the "main" regular
10516 * VI for the port. The rest are additional virtual interfaces on the
10517 * same physical port. Note that the main VI does not have native
10518 * netmap support but the extra VIs do.
10520 * Limit the number of VIs per port to the number of available
10521 * MAC addresses per port.
10523 if (t4_num_vis < 1)
10525 if (t4_num_vis > nitems(vi_mac_funcs)) {
10526 t4_num_vis = nitems(vi_mac_funcs);
10527 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10530 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10531 pcie_relaxed_ordering = 1;
10532 #if defined(__i386__) || defined(__amd64__)
10533 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10534 pcie_relaxed_ordering = 0;
10541 t4_dump_tcb(struct adapter *sc, int tid)
10543 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10545 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10546 save = t4_read_reg(sc, reg);
10547 base = sc->memwin[2].mw_base;
10549 /* Dump TCB for the tid */
10550 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10551 tcb_addr += tid * TCB_SIZE;
10555 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10557 pf = V_PFNUM(sc->pf);
10558 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10560 t4_write_reg(sc, reg, win_pos | pf);
10561 t4_read_reg(sc, reg);
10563 off = tcb_addr - win_pos;
10564 for (i = 0; i < 4; i++) {
10566 for (j = 0; j < 8; j++, off += 4)
10567 buf[j] = htonl(t4_read_reg(sc, base + off));
10569 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10570 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10574 t4_write_reg(sc, reg, save);
10575 t4_read_reg(sc, reg);
10579 t4_dump_devlog(struct adapter *sc)
10581 struct devlog_params *dparams = &sc->params.devlog;
10582 struct fw_devlog_e e;
10583 int i, first, j, m, nentries, rc;
10584 uint64_t ftstamp = UINT64_MAX;
10586 if (dparams->start == 0) {
10587 db_printf("devlog params not valid\n");
10591 nentries = dparams->size / sizeof(struct fw_devlog_e);
10592 m = fwmtype_to_hwmtype(dparams->memtype);
10594 /* Find the first entry. */
10596 for (i = 0; i < nentries && !db_pager_quit; i++) {
10597 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10598 sizeof(e), (void *)&e);
10602 if (e.timestamp == 0)
10605 e.timestamp = be64toh(e.timestamp);
10606 if (e.timestamp < ftstamp) {
10607 ftstamp = e.timestamp;
10617 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10618 sizeof(e), (void *)&e);
10622 if (e.timestamp == 0)
10625 e.timestamp = be64toh(e.timestamp);
10626 e.seqno = be32toh(e.seqno);
10627 for (j = 0; j < 8; j++)
10628 e.params[j] = be32toh(e.params[j]);
10630 db_printf("%10d %15ju %8s %8s ",
10631 e.seqno, e.timestamp,
10632 (e.level < nitems(devlog_level_strings) ?
10633 devlog_level_strings[e.level] : "UNKNOWN"),
10634 (e.facility < nitems(devlog_facility_strings) ?
10635 devlog_facility_strings[e.facility] : "UNKNOWN"));
10636 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10637 e.params[3], e.params[4], e.params[5], e.params[6],
10640 if (++i == nentries)
10642 } while (i != first && !db_pager_quit);
10645 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10646 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10648 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10655 t = db_read_token();
10657 dev = device_lookup_by_name(db_tok_string);
10662 db_printf("usage: show t4 devlog <nexus>\n");
10667 db_printf("device not found\n");
10671 t4_dump_devlog(device_get_softc(dev));
10674 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10683 t = db_read_token();
10685 dev = device_lookup_by_name(db_tok_string);
10686 t = db_read_token();
10687 if (t == tNUMBER) {
10688 tid = db_tok_number;
10695 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10700 db_printf("device not found\n");
10704 db_printf("invalid tid\n");
10708 t4_dump_tcb(device_get_softc(dev), tid);
10713 * Borrowed from cesa_prep_aes_key().
10715 * NB: The crypto engine wants the words in the decryption key in reverse
10719 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10721 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10725 rijndaelKeySetupEnc(ek, enc_key, kbits);
10727 dkey += (kbits / 8) / 4;
10731 for (i = 0; i < 4; i++)
10732 *--dkey = htobe32(ek[4 * 10 + i]);
10735 for (i = 0; i < 2; i++)
10736 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10737 for (i = 0; i < 4; i++)
10738 *--dkey = htobe32(ek[4 * 12 + i]);
10741 for (i = 0; i < 4; i++)
10742 *--dkey = htobe32(ek[4 * 13 + i]);
10743 for (i = 0; i < 4; i++)
10744 *--dkey = htobe32(ek[4 * 14 + i]);
10747 MPASS(dkey == dec_key);
10750 static struct sx mlu; /* mod load unload */
10751 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10754 mod_event(module_t mod, int cmd, void *arg)
10757 static int loaded = 0;
10762 if (loaded++ == 0) {
10764 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10765 t4_filter_rpl, CPL_COOKIE_FILTER);
10766 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10767 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10768 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10769 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10770 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10771 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10772 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10773 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10774 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10775 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10776 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10778 sx_init(&t4_list_lock, "T4/T5 adapters");
10779 SLIST_INIT(&t4_list);
10780 callout_init(&fatal_callout, 1);
10782 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10783 SLIST_INIT(&t4_uld_list);
10788 t4_tracer_modload();
10796 if (--loaded == 0) {
10799 sx_slock(&t4_list_lock);
10800 if (!SLIST_EMPTY(&t4_list)) {
10802 sx_sunlock(&t4_list_lock);
10806 sx_slock(&t4_uld_list_lock);
10807 if (!SLIST_EMPTY(&t4_uld_list)) {
10809 sx_sunlock(&t4_uld_list_lock);
10810 sx_sunlock(&t4_list_lock);
10815 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10816 uprintf("%ju clusters with custom free routine "
10817 "still is use.\n", t4_sge_extfree_refs());
10818 pause("t4unload", 2 * hz);
10821 sx_sunlock(&t4_uld_list_lock);
10823 sx_sunlock(&t4_list_lock);
10825 if (t4_sge_extfree_refs() == 0) {
10826 t4_tracer_modunload();
10828 t4_clip_modunload();
10831 sx_destroy(&t4_uld_list_lock);
10833 sx_destroy(&t4_list_lock);
10834 t4_sge_modunload();
10838 loaded++; /* undo earlier decrement */
10849 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10850 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10851 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10853 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10854 MODULE_VERSION(t4nex, 1);
10855 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10857 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10858 #endif /* DEV_NETMAP */
10860 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10861 MODULE_VERSION(t5nex, 1);
10862 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10864 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10865 #endif /* DEV_NETMAP */
10867 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10868 MODULE_VERSION(t6nex, 1);
10869 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10871 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10872 #endif /* DEV_NETMAP */
10874 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10875 MODULE_VERSION(cxgbe, 1);
10877 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10878 MODULE_VERSION(cxl, 1);
10880 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10881 MODULE_VERSION(cc, 1);
10883 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10884 MODULE_VERSION(vcxgbe, 1);
10886 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10887 MODULE_VERSION(vcxl, 1);
10889 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10890 MODULE_VERSION(vcc, 1);