sys/dev/cxgbe/t4_main.c

   1 /*-
   2  * Copyright (c) 2011 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  * Written by: Navdeep Parhar <np@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_ddb.h"
  32 #include "opt_inet.h"
  33 #include "opt_inet6.h"
  34 #include "opt_rss.h"
  35
  36 #include <sys/param.h>
  37 #include <sys/conf.h>
  38 #include <sys/priv.h>
  39 #include <sys/kernel.h>
  40 #include <sys/bus.h>
  41 #include <sys/module.h>
  42 #include <sys/malloc.h>
  43 #include <sys/queue.h>
  44 #include <sys/taskqueue.h>
  45 #include <sys/pciio.h>
  46 #include <dev/pci/pcireg.h>
  47 #include <dev/pci/pcivar.h>
  48 #include <dev/pci/pci_private.h>
  49 #include <sys/firmware.h>
  50 #include <sys/sbuf.h>
  51 #include <sys/smp.h>
  52 #include <sys/socket.h>
  53 #include <sys/sockio.h>
  54 #include <sys/sysctl.h>
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_types.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_vlan_var.h>
  60 #ifdef RSS
  61 #include <net/rss_config.h>
  62 #endif
  63 #if defined(__i386__) || defined(__amd64__)
  64 #include <machine/md_var.h>
  65 #include <machine/cputypes.h>
  66 #include <vm/vm.h>
  67 #include <vm/pmap.h>
  68 #endif
  69 #ifdef DDB
  70 #include <ddb/ddb.h>
  71 #include <ddb/db_lex.h>
  72 #endif
  73
  74 #include "common/common.h"
  75 #include "common/t4_msg.h"
  76 #include "common/t4_regs.h"
  77 #include "common/t4_regs_values.h"
  78 #include "cudbg/cudbg.h"
  79 #include "t4_ioctl.h"
  80 #include "t4_l2t.h"
  81 #include "t4_mp_ring.h"
  82 #include "t4_if.h"
  83
  84 /* T4 bus driver interface */
  85 static int t4_probe(device_t);
  86 static int t4_attach(device_t);
  87 static int t4_detach(device_t);
  88 static int t4_child_location_str(device_t, device_t, char *, size_t);
  89 static int t4_ready(device_t);
  90 static int t4_read_port_device(device_t, int, device_t *);
  91 static device_method_t t4_methods[] = {
  92         DEVMETHOD(device_probe,         t4_probe),
  93         DEVMETHOD(device_attach,        t4_attach),
  94         DEVMETHOD(device_detach,        t4_detach),
  95
  96         DEVMETHOD(bus_child_location_str, t4_child_location_str),
  97
  98         DEVMETHOD(t4_is_main_ready,     t4_ready),
  99         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 100
 101         DEVMETHOD_END
 102 };
 103 static driver_t t4_driver = {
 104         "t4nex",
 105         t4_methods,
 106         sizeof(struct adapter)
 107 };
 108
 109
 110 /* T4 port (cxgbe) interface */
 111 static int cxgbe_probe(device_t);
 112 static int cxgbe_attach(device_t);
 113 static int cxgbe_detach(device_t);
 114 device_method_t cxgbe_methods[] = {
 115         DEVMETHOD(device_probe,         cxgbe_probe),
 116         DEVMETHOD(device_attach,        cxgbe_attach),
 117         DEVMETHOD(device_detach,        cxgbe_detach),
 118         { 0, 0 }
 119 };
 120 static driver_t cxgbe_driver = {
 121         "cxgbe",
 122         cxgbe_methods,
 123         sizeof(struct port_info)
 124 };
 125
 126 /* T4 VI (vcxgbe) interface */
 127 static int vcxgbe_probe(device_t);
 128 static int vcxgbe_attach(device_t);
 129 static int vcxgbe_detach(device_t);
 130 static device_method_t vcxgbe_methods[] = {
 131         DEVMETHOD(device_probe,         vcxgbe_probe),
 132         DEVMETHOD(device_attach,        vcxgbe_attach),
 133         DEVMETHOD(device_detach,        vcxgbe_detach),
 134         { 0, 0 }
 135 };
 136 static driver_t vcxgbe_driver = {
 137         "vcxgbe",
 138         vcxgbe_methods,
 139         sizeof(struct vi_info)
 140 };
 141
 142 static d_ioctl_t t4_ioctl;
 143
 144 static struct cdevsw t4_cdevsw = {
 145        .d_version = D_VERSION,
 146        .d_ioctl = t4_ioctl,
 147        .d_name = "t4nex",
 148 };
 149
 150 /* T5 bus driver interface */
 151 static int t5_probe(device_t);
 152 static device_method_t t5_methods[] = {
 153         DEVMETHOD(device_probe,         t5_probe),
 154         DEVMETHOD(device_attach,        t4_attach),
 155         DEVMETHOD(device_detach,        t4_detach),
 156
 157         DEVMETHOD(bus_child_location_str, t4_child_location_str),
 158
 159         DEVMETHOD(t4_is_main_ready,     t4_ready),
 160         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 161
 162         DEVMETHOD_END
 163 };
 164 static driver_t t5_driver = {
 165         "t5nex",
 166         t5_methods,
 167         sizeof(struct adapter)
 168 };
 169
 170
 171 /* T5 port (cxl) interface */
 172 static driver_t cxl_driver = {
 173         "cxl",
 174         cxgbe_methods,
 175         sizeof(struct port_info)
 176 };
 177
 178 /* T5 VI (vcxl) interface */
 179 static driver_t vcxl_driver = {
 180         "vcxl",
 181         vcxgbe_methods,
 182         sizeof(struct vi_info)
 183 };
 184
 185 /* T6 bus driver interface */
 186 static int t6_probe(device_t);
 187 static device_method_t t6_methods[] = {
 188         DEVMETHOD(device_probe,         t6_probe),
 189         DEVMETHOD(device_attach,        t4_attach),
 190         DEVMETHOD(device_detach,        t4_detach),
 191
 192         DEVMETHOD(bus_child_location_str, t4_child_location_str),
 193
 194         DEVMETHOD(t4_is_main_ready,     t4_ready),
 195         DEVMETHOD(t4_read_port_device,  t4_read_port_device),
 196
 197         DEVMETHOD_END
 198 };
 199 static driver_t t6_driver = {
 200         "t6nex",
 201         t6_methods,
 202         sizeof(struct adapter)
 203 };
 204
 205
 206 /* T6 port (cc) interface */
 207 static driver_t cc_driver = {
 208         "cc",
 209         cxgbe_methods,
 210         sizeof(struct port_info)
 211 };
 212
 213 /* T6 VI (vcc) interface */
 214 static driver_t vcc_driver = {
 215         "vcc",
 216         vcxgbe_methods,
 217         sizeof(struct vi_info)
 218 };
 219
 220 /* ifnet + media interface */
 221 static void cxgbe_init(void *);
 222 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
 223 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
 224 static void cxgbe_qflush(struct ifnet *);
 225 static int cxgbe_media_change(struct ifnet *);
 226 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
 227
 228 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
 229
 230 /*
 231  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
 232  * then ADAPTER_LOCK, then t4_uld_list_lock.
 233  */
 234 static struct sx t4_list_lock;
 235 SLIST_HEAD(, adapter) t4_list;
 236 #ifdef TCP_OFFLOAD
 237 static struct sx t4_uld_list_lock;
 238 SLIST_HEAD(, uld_info) t4_uld_list;
 239 #endif
 240
 241 /*
 242  * Tunables.  See tweak_tunables() too.
 243  *
 244  * Each tunable is set to a default value here if it's known at compile-time.
 245  * Otherwise it is set to -n as an indication to tweak_tunables() that it should
 246  * provide a reasonable default (upto n) when the driver is loaded.
 247  *
 248  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
 249  * T5 are under hw.cxl.
 250  */
 251 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
 252 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
 253 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
 254
 255 /*
 256  * Number of queues for tx and rx, NIC and offload.
 257  */
 258 #define NTXQ 16
 259 int t4_ntxq = -NTXQ;
 260 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
 261     "Number of TX queues per port");
 262 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq);      /* Old name, undocumented */
 263
 264 #define NRXQ 8
 265 int t4_nrxq = -NRXQ;
 266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
 267     "Number of RX queues per port");
 268 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq);      /* Old name, undocumented */
 269
 270 #define NTXQ_VI 1
 271 static int t4_ntxq_vi = -NTXQ_VI;
 272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
 273     "Number of TX queues per VI");
 274
 275 #define NRXQ_VI 1
 276 static int t4_nrxq_vi = -NRXQ_VI;
 277 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
 278     "Number of RX queues per VI");
 279
 280 static int t4_rsrv_noflowq = 0;
 281 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
 282     0, "Reserve TX queue 0 of each VI for non-flowid packets");
 283
 284 #ifdef TCP_OFFLOAD
 285 #define NOFLDTXQ 8
 286 static int t4_nofldtxq = -NOFLDTXQ;
 287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
 288     "Number of offload TX queues per port");
 289
 290 #define NOFLDRXQ 2
 291 static int t4_nofldrxq = -NOFLDRXQ;
 292 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
 293     "Number of offload RX queues per port");
 294
 295 #define NOFLDTXQ_VI 1
 296 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
 297 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
 298     "Number of offload TX queues per VI");
 299
 300 #define NOFLDRXQ_VI 1
 301 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
 302 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
 303     "Number of offload RX queues per VI");
 304
 305 #define TMR_IDX_OFLD 1
 306 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
 307 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
 308     &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
 309
 310 #define PKTC_IDX_OFLD (-1)
 311 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
 312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
 313     &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
 314
 315 /* 0 means chip/fw default, non-zero number is value in microseconds */
 316 static u_long t4_toe_keepalive_idle = 0;
 317 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
 318     &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
 319
 320 /* 0 means chip/fw default, non-zero number is value in microseconds */
 321 static u_long t4_toe_keepalive_interval = 0;
 322 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
 323     &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
 324
 325 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
 326 static int t4_toe_keepalive_count = 0;
 327 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
 328     &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
 329
 330 /* 0 means chip/fw default, non-zero number is value in microseconds */
 331 static u_long t4_toe_rexmt_min = 0;
 332 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
 333     &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
 334
 335 /* 0 means chip/fw default, non-zero number is value in microseconds */
 336 static u_long t4_toe_rexmt_max = 0;
 337 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
 338     &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
 339
 340 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
 341 static int t4_toe_rexmt_count = 0;
 342 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
 343     &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
 344
 345 /* -1 means chip/fw default, other values are raw backoff values to use */
 346 static int t4_toe_rexmt_backoff[16] = {
 347         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 348 };
 349 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
 350     "cxgbe(4) TOE retransmit backoff values");
 351 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
 352     &t4_toe_rexmt_backoff[0], 0, "");
 353 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
 354     &t4_toe_rexmt_backoff[1], 0, "");
 355 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
 356     &t4_toe_rexmt_backoff[2], 0, "");
 357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
 358     &t4_toe_rexmt_backoff[3], 0, "");
 359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
 360     &t4_toe_rexmt_backoff[4], 0, "");
 361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
 362     &t4_toe_rexmt_backoff[5], 0, "");
 363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
 364     &t4_toe_rexmt_backoff[6], 0, "");
 365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
 366     &t4_toe_rexmt_backoff[7], 0, "");
 367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
 368     &t4_toe_rexmt_backoff[8], 0, "");
 369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
 370     &t4_toe_rexmt_backoff[9], 0, "");
 371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
 372     &t4_toe_rexmt_backoff[10], 0, "");
 373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
 374     &t4_toe_rexmt_backoff[11], 0, "");
 375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
 376     &t4_toe_rexmt_backoff[12], 0, "");
 377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
 378     &t4_toe_rexmt_backoff[13], 0, "");
 379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
 380     &t4_toe_rexmt_backoff[14], 0, "");
 381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
 382     &t4_toe_rexmt_backoff[15], 0, "");
 383 #endif
 384
 385 #ifdef DEV_NETMAP
 386 #define NNMTXQ_VI 2
 387 static int t4_nnmtxq_vi = -NNMTXQ_VI;
 388 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
 389     "Number of netmap TX queues per VI");
 390
 391 #define NNMRXQ_VI 2
 392 static int t4_nnmrxq_vi = -NNMRXQ_VI;
 393 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
 394     "Number of netmap RX queues per VI");
 395 #endif
 396
 397 /*
 398  * Holdoff parameters for ports.
 399  */
 400 #define TMR_IDX 1
 401 int t4_tmr_idx = TMR_IDX;
 402 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
 403     0, "Holdoff timer index");
 404 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx);     /* Old name */
 405
 406 #define PKTC_IDX (-1)
 407 int t4_pktc_idx = PKTC_IDX;
 408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
 409     0, "Holdoff packet counter index");
 410 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx);     /* Old name */
 411
 412 /*
 413  * Size (# of entries) of each tx and rx queue.
 414  */
 415 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
 416 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
 417     "Number of descriptors in each TX queue");
 418
 419 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
 420 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
 421     "Number of descriptors in each RX queue");
 422
 423 /*
 424  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
 425  */
 426 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
 427 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
 428     0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
 429
 430 /*
 431  * Configuration file.  All the _CF names here are special.
 432  */
 433 #define DEFAULT_CF      "default"
 434 #define BUILTIN_CF      "built-in"
 435 #define FLASH_CF        "flash"
 436 #define UWIRE_CF        "uwire"
 437 #define FPGA_CF         "fpga"
 438 static char t4_cfg_file[32] = DEFAULT_CF;
 439 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
 440     sizeof(t4_cfg_file), "Firmware configuration file");
 441
 442 /*
 443  * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
 444  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
 445  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
 446  *            mark or when signalled to do so, 0 to never emit PAUSE.
 447  * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
 448  *                 negotiated settings will override rx_pause/tx_pause.
 449  *                 Otherwise rx_pause/tx_pause are applied forcibly.
 450  */
 451 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
 452 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
 453     &t4_pause_settings, 0,
 454     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
 455
 456 /*
 457  * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
 458  * -1 to run with the firmware default.  Same as FEC_AUTO (bit 5)
 459  *  0 to disable FEC.
 460  */
 461 static int t4_fec = -1;
 462 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
 463     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
 464
 465 /*
 466  * Link autonegotiation.
 467  * -1 to run with the firmware default.
 468  *  0 to disable.
 469  *  1 to enable.
 470  */
 471 static int t4_autoneg = -1;
 472 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
 473     "Link autonegotiation");
 474
 475 /*
 476  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
 477  * encouraged respectively).
 478  */
 479 static unsigned int t4_fw_install = 1;
 480 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
 481     "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
 482
 483 /*
 484  * ASIC features that will be used.  Disable the ones you don't want so that the
 485  * chip resources aren't wasted on features that will not be used.
 486  */
 487 static int t4_nbmcaps_allowed = 0;
 488 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
 489     &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
 490
 491 static int t4_linkcaps_allowed = 0;     /* No DCBX, PPP, etc. by default */
 492 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
 493     &t4_linkcaps_allowed, 0, "Default link capabilities");
 494
 495 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
 496     FW_CAPS_CONFIG_SWITCH_EGRESS;
 497 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
 498     &t4_switchcaps_allowed, 0, "Default switch capabilities");
 499
 500 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
 501 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
 502     &t4_niccaps_allowed, 0, "Default NIC capabilities");
 503
 504 static int t4_toecaps_allowed = -1;
 505 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
 506     &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
 507
 508 static int t4_rdmacaps_allowed = -1;
 509 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
 510     &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
 511
 512 static int t4_cryptocaps_allowed = -1;
 513 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
 514     &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
 515
 516 static int t4_iscsicaps_allowed = -1;
 517 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
 518     &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
 519
 520 static int t4_fcoecaps_allowed = 0;
 521 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
 522     &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
 523
 524 static int t5_write_combine = 0;
 525 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
 526     0, "Use WC instead of UC for BAR2");
 527
 528 static int t4_num_vis = 1;
 529 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
 530     "Number of VIs per port");
 531
 532 /*
 533  * PCIe Relaxed Ordering.
 534  * -1: driver should figure out a good value.
 535  * 0: disable RO.
 536  * 1: enable RO.
 537  * 2: leave RO alone.
 538  */
 539 static int pcie_relaxed_ordering = -1;
 540 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
 541     &pcie_relaxed_ordering, 0,
 542     "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
 543
 544
 545 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
 546 static int vi_mac_funcs[] = {
 547         FW_VI_FUNC_ETH,
 548         FW_VI_FUNC_OFLD,
 549         FW_VI_FUNC_IWARP,
 550         FW_VI_FUNC_OPENISCSI,
 551         FW_VI_FUNC_OPENFCOE,
 552         FW_VI_FUNC_FOISCSI,
 553         FW_VI_FUNC_FOFCOE,
 554 };
 555
 556 struct intrs_and_queues {
 557         uint16_t intr_type;     /* INTx, MSI, or MSI-X */
 558         uint16_t num_vis;       /* number of VIs for each port */
 559         uint16_t nirq;          /* Total # of vectors */
 560         uint16_t ntxq;          /* # of NIC txq's for each port */
 561         uint16_t nrxq;          /* # of NIC rxq's for each port */
 562         uint16_t nofldtxq;      /* # of TOE txq's for each port */
 563         uint16_t nofldrxq;      /* # of TOE rxq's for each port */
 564
 565         /* The vcxgbe/vcxl interfaces use these and not the ones above. */
 566         uint16_t ntxq_vi;       /* # of NIC txq's */
 567         uint16_t nrxq_vi;       /* # of NIC rxq's */
 568         uint16_t nofldtxq_vi;   /* # of TOE txq's */
 569         uint16_t nofldrxq_vi;   /* # of TOE rxq's */
 570         uint16_t nnmtxq_vi;     /* # of netmap txq's */
 571         uint16_t nnmrxq_vi;     /* # of netmap rxq's */
 572 };
 573
 574 struct filter_entry {
 575         uint32_t valid:1;       /* filter allocated and valid */
 576         uint32_t locked:1;      /* filter is administratively locked */
 577         uint32_t pending:1;     /* filter action is pending firmware reply */
 578         uint32_t smtidx:8;      /* Source MAC Table index for smac */
 579         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 580
 581         struct t4_filter_specification fs;
 582 };
 583
 584 static void setup_memwin(struct adapter *);
 585 static void position_memwin(struct adapter *, int, uint32_t);
 586 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
 587 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
 588     int);
 589 static inline int write_via_memwin(struct adapter *, int, uint32_t,
 590     const uint32_t *, int);
 591 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
 592 static int fwmtype_to_hwmtype(int);
 593 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
 594     uint32_t *);
 595 static int fixup_devlog_params(struct adapter *);
 596 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
 597 static int prep_firmware(struct adapter *);
 598 static int partition_resources(struct adapter *, const struct firmware *,
 599     const char *);
 600 static int get_params__pre_init(struct adapter *);
 601 static int get_params__post_init(struct adapter *);
 602 static int set_params__post_init(struct adapter *);
 603 static void t4_set_desc(struct adapter *);
 604 static bool fixed_ifmedia(struct port_info *);
 605 static void build_medialist(struct port_info *);
 606 static void init_link_config(struct port_info *);
 607 static int fixup_link_config(struct port_info *);
 608 static int apply_link_config(struct port_info *);
 609 static int cxgbe_init_synchronized(struct vi_info *);
 610 static int cxgbe_uninit_synchronized(struct vi_info *);
 611 static void quiesce_txq(struct adapter *, struct sge_txq *);
 612 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
 613 static void quiesce_iq(struct adapter *, struct sge_iq *);
 614 static void quiesce_fl(struct adapter *, struct sge_fl *);
 615 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
 616     driver_intr_t *, void *, char *);
 617 static int t4_free_irq(struct adapter *, struct irq *);
 618 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
 619 static void vi_refresh_stats(struct adapter *, struct vi_info *);
 620 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
 621 static void cxgbe_tick(void *);
 622 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
 623 static void cxgbe_sysctls(struct port_info *);
 624 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
 625 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
 626 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
 627 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
 628 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
 629 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
 630 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
 631 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
 632 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
 633 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
 634 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
 635 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
 636 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
 637 #ifdef SBUF_DRAIN
 638 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
 639 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
 640 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
 641 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
 642 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
 643 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
 644 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
 645 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
 646 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
 647 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
 648 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
 649 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
 650 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
 651 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
 652 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
 653 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
 654 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
 655 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
 656 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
 657 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
 658 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
 659 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
 660 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
 661 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
 662 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
 663 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
 664 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
 665 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
 666 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
 667 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
 668 #endif
 669 #ifdef TCP_OFFLOAD
 670 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
 671 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
 672 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
 673 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
 674 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
 675 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
 676 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
 677 #endif
 678 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
 679 static uint32_t mode_to_fconf(uint32_t);
 680 static uint32_t mode_to_iconf(uint32_t);
 681 static int check_fspec_against_fconf_iconf(struct adapter *,
 682     struct t4_filter_specification *);
 683 static int get_filter_mode(struct adapter *, uint32_t *);
 684 static int set_filter_mode(struct adapter *, uint32_t);
 685 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
 686 static int get_filter(struct adapter *, struct t4_filter *);
 687 static int set_filter(struct adapter *, struct t4_filter *);
 688 static int del_filter(struct adapter *, struct t4_filter *);
 689 static void clear_filter(struct filter_entry *);
 690 static int set_filter_wr(struct adapter *, int);
 691 static int del_filter_wr(struct adapter *, int);
 692 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
 693     struct mbuf *);
 694 static int get_sge_context(struct adapter *, struct t4_sge_context *);
 695 static int load_fw(struct adapter *, struct t4_data *);
 696 static int load_cfg(struct adapter *, struct t4_data *);
 697 static int load_boot(struct adapter *, struct t4_bootrom *);
 698 static int load_bootcfg(struct adapter *, struct t4_data *);
 699 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
 700 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
 701 static int read_i2c(struct adapter *, struct t4_i2c_data *);
 702 #ifdef TCP_OFFLOAD
 703 static int toe_capability(struct vi_info *, int);
 704 #endif
 705 static int mod_event(module_t, int, void *);
 706 static int notify_siblings(device_t, int);
 707
 708 struct {
 709         uint16_t device;
 710         char *desc;
 711 } t4_pciids[] = {
 712         {0xa000, "Chelsio Terminator 4 FPGA"},
 713         {0x4400, "Chelsio T440-dbg"},
 714         {0x4401, "Chelsio T420-CR"},
 715         {0x4402, "Chelsio T422-CR"},
 716         {0x4403, "Chelsio T440-CR"},
 717         {0x4404, "Chelsio T420-BCH"},
 718         {0x4405, "Chelsio T440-BCH"},
 719         {0x4406, "Chelsio T440-CH"},
 720         {0x4407, "Chelsio T420-SO"},
 721         {0x4408, "Chelsio T420-CX"},
 722         {0x4409, "Chelsio T420-BT"},
 723         {0x440a, "Chelsio T404-BT"},
 724         {0x440e, "Chelsio T440-LP-CR"},
 725 }, t5_pciids[] = {
 726         {0xb000, "Chelsio Terminator 5 FPGA"},
 727         {0x5400, "Chelsio T580-dbg"},
 728         {0x5401,  "Chelsio T520-CR"},           /* 2 x 10G */
 729         {0x5402,  "Chelsio T522-CR"},           /* 2 x 10G, 2 X 1G */
 730         {0x5403,  "Chelsio T540-CR"},           /* 4 x 10G */
 731         {0x5407,  "Chelsio T520-SO"},           /* 2 x 10G, nomem */
 732         {0x5409,  "Chelsio T520-BT"},           /* 2 x 10GBaseT */
 733         {0x540a,  "Chelsio T504-BT"},           /* 4 x 1G */
 734         {0x540d,  "Chelsio T580-CR"},           /* 2 x 40G */
 735         {0x540e,  "Chelsio T540-LP-CR"},        /* 4 x 10G */
 736         {0x5410,  "Chelsio T580-LP-CR"},        /* 2 x 40G */
 737         {0x5411,  "Chelsio T520-LL-CR"},        /* 2 x 10G */
 738         {0x5412,  "Chelsio T560-CR"},           /* 1 x 40G, 2 x 10G */
 739         {0x5414,  "Chelsio T580-LP-SO-CR"},     /* 2 x 40G, nomem */
 740         {0x5415,  "Chelsio T502-BT"},           /* 2 x 1G */
 741         {0x5418,  "Chelsio T540-BT"},           /* 4 x 10GBaseT */
 742         {0x5419,  "Chelsio T540-LP-BT"},        /* 4 x 10GBaseT */
 743         {0x541a,  "Chelsio T540-SO-BT"},        /* 4 x 10GBaseT, nomem */
 744         {0x541b,  "Chelsio T540-SO-CR"},        /* 4 x 10G, nomem */
 745
 746         /* Custom */
 747         {0x5483, "Custom T540-CR"},
 748         {0x5484, "Custom T540-BT"},
 749 }, t6_pciids[] = {
 750         {0xc006, "Chelsio Terminator 6 FPGA"},  /* T6 PE10K6 FPGA (PF0) */
 751         {0x6400, "Chelsio T6-DBG-25"},          /* 2 x 10/25G, debug */
 752         {0x6401, "Chelsio T6225-CR"},           /* 2 x 10/25G */
 753         {0x6402, "Chelsio T6225-SO-CR"},        /* 2 x 10/25G, nomem */
 754         {0x6403, "Chelsio T6425-CR"},           /* 4 x 10/25G */
 755         {0x6404, "Chelsio T6425-SO-CR"},        /* 4 x 10/25G, nomem */
 756         {0x6405, "Chelsio T6225-OCP-SO"},       /* 2 x 10/25G, nomem */
 757         {0x6406, "Chelsio T62100-OCP-SO"},      /* 2 x 40/50/100G, nomem */
 758         {0x6407, "Chelsio T62100-LP-CR"},       /* 2 x 40/50/100G */
 759         {0x6408, "Chelsio T62100-SO-CR"},       /* 2 x 40/50/100G, nomem */
 760         {0x6409, "Chelsio T6210-BT"},           /* 2 x 10GBASE-T */
 761         {0x640d, "Chelsio T62100-CR"},          /* 2 x 40/50/100G */
 762         {0x6410, "Chelsio T6-DBG-100"},         /* 2 x 40/50/100G, debug */
 763         {0x6411, "Chelsio T6225-LL-CR"},        /* 2 x 10/25G */
 764         {0x6414, "Chelsio T61100-OCP-SO"},      /* 1 x 40/50/100G, nomem */
 765         {0x6415, "Chelsio T6201-BT"},           /* 2 x 1000BASE-T */
 766
 767         /* Custom */
 768         {0x6480, "Custom T6225-CR"},
 769         {0x6481, "Custom T62100-CR"},
 770         {0x6482, "Custom T6225-CR"},
 771         {0x6483, "Custom T62100-CR"},
 772         {0x6484, "Custom T64100-CR"},
 773         {0x6485, "Custom T6240-SO"},
 774         {0x6486, "Custom T6225-SO-CR"},
 775         {0x6487, "Custom T6225-CR"},
 776 };
 777
 778 #ifdef TCP_OFFLOAD
 779 /*
 780  * service_iq() has an iq and needs the fl.  Offset of fl from the iq should be
 781  * exactly the same for both rxq and ofld_rxq.
 782  */
 783 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
 784 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
 785 #endif
 786 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
 787
 788 static int
 789 t4_probe(device_t dev)
 790 {
 791         int i;
 792         uint16_t v = pci_get_vendor(dev);
 793         uint16_t d = pci_get_device(dev);
 794         uint8_t f = pci_get_function(dev);
 795
 796         if (v != PCI_VENDOR_ID_CHELSIO)
 797                 return (ENXIO);
 798
 799         /* Attach only to PF0 of the FPGA */
 800         if (d == 0xa000 && f != 0)
 801                 return (ENXIO);
 802
 803         for (i = 0; i < nitems(t4_pciids); i++) {
 804                 if (d == t4_pciids[i].device) {
 805                         device_set_desc(dev, t4_pciids[i].desc);
 806                         return (BUS_PROBE_DEFAULT);
 807                 }
 808         }
 809
 810         return (ENXIO);
 811 }
 812
 813 static int
 814 t5_probe(device_t dev)
 815 {
 816         int i;
 817         uint16_t v = pci_get_vendor(dev);
 818         uint16_t d = pci_get_device(dev);
 819         uint8_t f = pci_get_function(dev);
 820
 821         if (v != PCI_VENDOR_ID_CHELSIO)
 822                 return (ENXIO);
 823
 824         /* Attach only to PF0 of the FPGA */
 825         if (d == 0xb000 && f != 0)
 826                 return (ENXIO);
 827
 828         for (i = 0; i < nitems(t5_pciids); i++) {
 829                 if (d == t5_pciids[i].device) {
 830                         device_set_desc(dev, t5_pciids[i].desc);
 831                         return (BUS_PROBE_DEFAULT);
 832                 }
 833         }
 834
 835         return (ENXIO);
 836 }
 837
 838 static int
 839 t6_probe(device_t dev)
 840 {
 841         int i;
 842         uint16_t v = pci_get_vendor(dev);
 843         uint16_t d = pci_get_device(dev);
 844
 845         if (v != PCI_VENDOR_ID_CHELSIO)
 846                 return (ENXIO);
 847
 848         for (i = 0; i < nitems(t6_pciids); i++) {
 849                 if (d == t6_pciids[i].device) {
 850                         device_set_desc(dev, t6_pciids[i].desc);
 851                         return (BUS_PROBE_DEFAULT);
 852                 }
 853         }
 854
 855         return (ENXIO);
 856 }
 857
 858 static void
 859 t5_attribute_workaround(device_t dev)
 860 {
 861         device_t root_port;
 862         uint32_t v;
 863
 864         /*
 865          * The T5 chips do not properly echo the No Snoop and Relaxed
 866          * Ordering attributes when replying to a TLP from a Root
 867          * Port.  As a workaround, find the parent Root Port and
 868          * disable No Snoop and Relaxed Ordering.  Note that this
 869          * affects all devices under this root port.
 870          */
 871         root_port = pci_find_pcie_root_port(dev);
 872         if (root_port == NULL) {
 873                 device_printf(dev, "Unable to find parent root port\n");
 874                 return;
 875         }
 876
 877         v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
 878             PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
 879         if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
 880             0)
 881                 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
 882                     device_get_nameunit(root_port));
 883 }
 884
 885 static const struct devnames devnames[] = {
 886         {
 887                 .nexus_name = "t4nex",
 888                 .ifnet_name = "cxgbe",
 889                 .vi_ifnet_name = "vcxgbe",
 890                 .pf03_drv_name = "t4iov",
 891                 .vf_nexus_name = "t4vf",
 892                 .vf_ifnet_name = "cxgbev"
 893         }, {
 894                 .nexus_name = "t5nex",
 895                 .ifnet_name = "cxl",
 896                 .vi_ifnet_name = "vcxl",
 897                 .pf03_drv_name = "t5iov",
 898                 .vf_nexus_name = "t5vf",
 899                 .vf_ifnet_name = "cxlv"
 900         }, {
 901                 .nexus_name = "t6nex",
 902                 .ifnet_name = "cc",
 903                 .vi_ifnet_name = "vcc",
 904                 .pf03_drv_name = "t6iov",
 905                 .vf_nexus_name = "t6vf",
 906                 .vf_ifnet_name = "ccv"
 907         }
 908 };
 909
 910 void
 911 t4_init_devnames(struct adapter *sc)
 912 {
 913         int id;
 914
 915         id = chip_id(sc);
 916         if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
 917                 sc->names = &devnames[id - CHELSIO_T4];
 918         else {
 919                 device_printf(sc->dev, "chip id %d is not supported.\n", id);
 920                 sc->names = NULL;
 921         }
 922 }
 923
 924 static int
 925 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
 926 {
 927         const char *parent, *name;
 928         long value;
 929         int line, unit;
 930
 931         line = 0;
 932         parent = device_get_nameunit(sc->dev);
 933         name = sc->names->ifnet_name;
 934         while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
 935                 if (resource_long_value(name, unit, "port", &value) == 0 &&
 936                     value == pi->port_id)
 937                         return (unit);
 938         }
 939         return (-1);
 940 }
 941
 942 static int
 943 t4_attach(device_t dev)
 944 {
 945         struct adapter *sc;
 946         int rc = 0, i, j, rqidx, tqidx, nports;
 947         struct make_dev_args mda;
 948         struct intrs_and_queues iaq;
 949         struct sge *s;
 950         uint32_t *buf;
 951 #ifdef TCP_OFFLOAD
 952         int ofld_rqidx, ofld_tqidx;
 953 #endif
 954 #ifdef DEV_NETMAP
 955         int nm_rqidx, nm_tqidx;
 956 #endif
 957         int num_vis;
 958
 959         sc = device_get_softc(dev);
 960         sc->dev = dev;
 961         TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
 962
 963         if ((pci_get_device(dev) & 0xff00) == 0x5400)
 964                 t5_attribute_workaround(dev);
 965         pci_enable_busmaster(dev);
 966         if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
 967                 uint32_t v;
 968
 969                 pci_set_max_read_req(dev, 4096);
 970                 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
 971                 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
 972                 if (pcie_relaxed_ordering == 0 &&
 973                     (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
 974                         v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
 975                         pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
 976                 } else if (pcie_relaxed_ordering == 1 &&
 977                     (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
 978                         v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
 979                         pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
 980                 }
 981         }
 982
 983         sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
 984         sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
 985         sc->traceq = -1;
 986         mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
 987         snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
 988             device_get_nameunit(dev));
 989
 990         snprintf(sc->lockname, sizeof(sc->lockname), "%s",
 991             device_get_nameunit(dev));
 992         mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
 993         t4_add_adapter(sc);
 994
 995         mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
 996         TAILQ_INIT(&sc->sfl);
 997         callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
 998
 999         mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1000
1001         rc = t4_map_bars_0_and_4(sc);
1002         if (rc != 0)
1003                 goto done; /* error message displayed already */
1004
1005         memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1006
1007         /* Prepare the adapter for operation. */
1008         buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1009         rc = -t4_prep_adapter(sc, buf);
1010         free(buf, M_CXGBE);
1011         if (rc != 0) {
1012                 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1013                 goto done;
1014         }
1015
1016         /*
1017          * This is the real PF# to which we're attaching.  Works from within PCI
1018          * passthrough environments too, where pci_get_function() could return a
1019          * different PF# depending on the passthrough configuration.  We need to
1020          * use the real PF# in all our communication with the firmware.
1021          */
1022         j = t4_read_reg(sc, A_PL_WHOAMI);
1023         sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1024         sc->mbox = sc->pf;
1025
1026         t4_init_devnames(sc);
1027         if (sc->names == NULL) {
1028                 rc = ENOTSUP;
1029                 goto done; /* error message displayed already */
1030         }
1031
1032         /*
1033          * Do this really early, with the memory windows set up even before the
1034          * character device.  The userland tool's register i/o and mem read
1035          * will work even in "recovery mode".
1036          */
1037         setup_memwin(sc);
1038         if (t4_init_devlog_params(sc, 0) == 0)
1039                 fixup_devlog_params(sc);
1040         make_dev_args_init(&mda);
1041         mda.mda_devsw = &t4_cdevsw;
1042         mda.mda_uid = UID_ROOT;
1043         mda.mda_gid = GID_WHEEL;
1044         mda.mda_mode = 0600;
1045         mda.mda_si_drv1 = sc;
1046         rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1047         if (rc != 0)
1048                 device_printf(dev, "failed to create nexus char device: %d.\n",
1049                     rc);
1050
1051         /* Go no further if recovery mode has been requested. */
1052         if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1053                 device_printf(dev, "recovery mode.\n");
1054                 goto done;
1055         }
1056
1057 #if defined(__i386__)
1058         if ((cpu_feature & CPUID_CX8) == 0) {
1059                 device_printf(dev, "64 bit atomics not available.\n");
1060                 rc = ENOTSUP;
1061                 goto done;
1062         }
1063 #endif
1064
1065         /* Prepare the firmware for operation */
1066         rc = prep_firmware(sc);
1067         if (rc != 0)
1068                 goto done; /* error message displayed already */
1069
1070         rc = get_params__post_init(sc);
1071         if (rc != 0)
1072                 goto done; /* error message displayed already */
1073
1074         rc = set_params__post_init(sc);
1075         if (rc != 0)
1076                 goto done; /* error message displayed already */
1077
1078         rc = t4_map_bar_2(sc);
1079         if (rc != 0)
1080                 goto done; /* error message displayed already */
1081
1082         rc = t4_create_dma_tag(sc);
1083         if (rc != 0)
1084                 goto done; /* error message displayed already */
1085
1086         /*
1087          * First pass over all the ports - allocate VIs and initialize some
1088          * basic parameters like mac address, port type, etc.
1089          */
1090         for_each_port(sc, i) {
1091                 struct port_info *pi;
1092
1093                 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1094                 sc->port[i] = pi;
1095
1096                 /* These must be set before t4_port_init */
1097                 pi->adapter = sc;
1098                 pi->port_id = i;
1099                 /*
1100                  * XXX: vi[0] is special so we can't delay this allocation until
1101                  * pi->nvi's final value is known.
1102                  */
1103                 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1104                     M_ZERO | M_WAITOK);
1105
1106                 /*
1107                  * Allocate the "main" VI and initialize parameters
1108                  * like mac addr.
1109                  */
1110                 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1111                 if (rc != 0) {
1112                         device_printf(dev, "unable to initialize port %d: %d\n",
1113                             i, rc);
1114                         free(pi->vi, M_CXGBE);
1115                         free(pi, M_CXGBE);
1116                         sc->port[i] = NULL;
1117                         goto done;
1118                 }
1119
1120                 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1121                     device_get_nameunit(dev), i);
1122                 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1123                 sc->chan_map[pi->tx_chan] = i;
1124
1125                 /* All VIs on this port share this media. */
1126                 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1127                     cxgbe_media_status);
1128
1129                 PORT_LOCK(pi);
1130                 init_link_config(pi);
1131                 fixup_link_config(pi);
1132                 build_medialist(pi);
1133                 if (fixed_ifmedia(pi))
1134                         pi->flags |= FIXED_IFMEDIA;
1135                 PORT_UNLOCK(pi);
1136
1137                 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1138                     t4_ifnet_unit(sc, pi));
1139                 if (pi->dev == NULL) {
1140                         device_printf(dev,
1141                             "failed to add device for port %d.\n", i);
1142                         rc = ENXIO;
1143                         goto done;
1144                 }
1145                 pi->vi[0].dev = pi->dev;
1146                 device_set_softc(pi->dev, pi);
1147         }
1148
1149         /*
1150          * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1151          */
1152         nports = sc->params.nports;
1153         rc = cfg_itype_and_nqueues(sc, &iaq);
1154         if (rc != 0)
1155                 goto done; /* error message displayed already */
1156
1157         num_vis = iaq.num_vis;
1158         sc->intr_type = iaq.intr_type;
1159         sc->intr_count = iaq.nirq;
1160
1161         s = &sc->sge;
1162         s->nrxq = nports * iaq.nrxq;
1163         s->ntxq = nports * iaq.ntxq;
1164         if (num_vis > 1) {
1165                 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1166                 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1167         }
1168         s->neq = s->ntxq + s->nrxq;     /* the free list in an rxq is an eq */
1169         s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1170         s->niq = s->nrxq + 1;           /* 1 extra for firmware event queue */
1171 #ifdef TCP_OFFLOAD
1172         if (is_offload(sc)) {
1173                 s->nofldrxq = nports * iaq.nofldrxq;
1174                 s->nofldtxq = nports * iaq.nofldtxq;
1175                 if (num_vis > 1) {
1176                         s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1177                         s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1178                 }
1179                 s->neq += s->nofldtxq + s->nofldrxq;
1180                 s->niq += s->nofldrxq;
1181
1182                 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1183                     M_CXGBE, M_ZERO | M_WAITOK);
1184                 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1185                     M_CXGBE, M_ZERO | M_WAITOK);
1186         }
1187 #endif
1188 #ifdef DEV_NETMAP
1189         if (num_vis > 1) {
1190                 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1191                 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1192         }
1193         s->neq += s->nnmtxq + s->nnmrxq;
1194         s->niq += s->nnmrxq;
1195
1196         s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1197             M_CXGBE, M_ZERO | M_WAITOK);
1198         s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1199             M_CXGBE, M_ZERO | M_WAITOK);
1200 #endif
1201
1202         s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1203             M_ZERO | M_WAITOK);
1204         s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1205             M_ZERO | M_WAITOK);
1206         s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1207             M_ZERO | M_WAITOK);
1208         s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1209             M_ZERO | M_WAITOK);
1210         s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1211             M_ZERO | M_WAITOK);
1212
1213         sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1214             M_ZERO | M_WAITOK);
1215
1216         t4_init_l2t(sc, M_WAITOK);
1217         t4_init_tx_sched(sc);
1218
1219         /*
1220          * Second pass over the ports.  This time we know the number of rx and
1221          * tx queues that each port should get.
1222          */
1223         rqidx = tqidx = 0;
1224 #ifdef TCP_OFFLOAD
1225         ofld_rqidx = ofld_tqidx = 0;
1226 #endif
1227 #ifdef DEV_NETMAP
1228         nm_rqidx = nm_tqidx = 0;
1229 #endif
1230         for_each_port(sc, i) {
1231                 struct port_info *pi = sc->port[i];
1232                 struct vi_info *vi;
1233
1234                 if (pi == NULL)
1235                         continue;
1236
1237                 pi->nvi = num_vis;
1238                 for_each_vi(pi, j, vi) {
1239                         vi->pi = pi;
1240                         vi->qsize_rxq = t4_qsize_rxq;
1241                         vi->qsize_txq = t4_qsize_txq;
1242
1243                         vi->first_rxq = rqidx;
1244                         vi->first_txq = tqidx;
1245                         vi->tmr_idx = t4_tmr_idx;
1246                         vi->pktc_idx = t4_pktc_idx;
1247                         vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1248                         vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1249
1250                         rqidx += vi->nrxq;
1251                         tqidx += vi->ntxq;
1252
1253                         if (j == 0 && vi->ntxq > 1)
1254                                 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1255                         else
1256                                 vi->rsrv_noflowq = 0;
1257
1258 #ifdef TCP_OFFLOAD
1259                         vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1260                         vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1261                         vi->first_ofld_rxq = ofld_rqidx;
1262                         vi->first_ofld_txq = ofld_tqidx;
1263                         vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1264                         vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1265
1266                         ofld_rqidx += vi->nofldrxq;
1267                         ofld_tqidx += vi->nofldtxq;
1268 #endif
1269 #ifdef DEV_NETMAP
1270                         if (j > 0) {
1271                                 vi->first_nm_rxq = nm_rqidx;
1272                                 vi->first_nm_txq = nm_tqidx;
1273                                 vi->nnmrxq = iaq.nnmrxq_vi;
1274                                 vi->nnmtxq = iaq.nnmtxq_vi;
1275                                 nm_rqidx += vi->nnmrxq;
1276                                 nm_tqidx += vi->nnmtxq;
1277                         }
1278 #endif
1279                 }
1280         }
1281
1282         rc = t4_setup_intr_handlers(sc);
1283         if (rc != 0) {
1284                 device_printf(dev,
1285                     "failed to setup interrupt handlers: %d\n", rc);
1286                 goto done;
1287         }
1288
1289         rc = bus_generic_probe(dev);
1290         if (rc != 0) {
1291                 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1292                 goto done;
1293         }
1294
1295         /*
1296          * Ensure thread-safe mailbox access (in debug builds).
1297          *
1298          * So far this was the only thread accessing the mailbox but various
1299          * ifnets and sysctls are about to be created and their handlers/ioctls
1300          * will access the mailbox from different threads.
1301          */
1302         sc->flags |= CHK_MBOX_ACCESS;
1303
1304         rc = bus_generic_attach(dev);
1305         if (rc != 0) {
1306                 device_printf(dev,
1307                     "failed to attach all child ports: %d\n", rc);
1308                 goto done;
1309         }
1310
1311         device_printf(dev,
1312             "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1313             sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1314             sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1315             (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1316             sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1317
1318         t4_set_desc(sc);
1319
1320         notify_siblings(dev, 0);
1321
1322 done:
1323         if (rc != 0 && sc->cdev) {
1324                 /* cdev was created and so cxgbetool works; recover that way. */
1325                 device_printf(dev,
1326                     "error during attach, adapter is now in recovery mode.\n");
1327                 rc = 0;
1328         }
1329
1330         if (rc != 0)
1331                 t4_detach_common(dev);
1332         else
1333                 t4_sysctls(sc);
1334
1335         return (rc);
1336 }
1337
1338 static int
1339 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1340 {
1341         struct adapter *sc;
1342         struct port_info *pi;
1343         int i;
1344
1345         sc = device_get_softc(bus);
1346         buf[0] = '\0';
1347         for_each_port(sc, i) {
1348                 pi = sc->port[i];
1349                 if (pi != NULL && pi->dev == dev) {
1350                         snprintf(buf, buflen, "port=%d", pi->port_id);
1351                         break;
1352                 }
1353         }
1354         return (0);
1355 }
1356
1357 static int
1358 t4_ready(device_t dev)
1359 {
1360         struct adapter *sc;
1361
1362         sc = device_get_softc(dev);
1363         if (sc->flags & FW_OK)
1364                 return (0);
1365         return (ENXIO);
1366 }
1367
1368 static int
1369 t4_read_port_device(device_t dev, int port, device_t *child)
1370 {
1371         struct adapter *sc;
1372         struct port_info *pi;
1373
1374         sc = device_get_softc(dev);
1375         if (port < 0 || port >= MAX_NPORTS)
1376                 return (EINVAL);
1377         pi = sc->port[port];
1378         if (pi == NULL || pi->dev == NULL)
1379                 return (ENXIO);
1380         *child = pi->dev;
1381         return (0);
1382 }
1383
1384 static int
1385 notify_siblings(device_t dev, int detaching)
1386 {
1387         device_t sibling;
1388         int error, i;
1389
1390         error = 0;
1391         for (i = 0; i < PCI_FUNCMAX; i++) {
1392                 if (i == pci_get_function(dev))
1393                         continue;
1394                 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1395                     pci_get_slot(dev), i);
1396                 if (sibling == NULL || !device_is_attached(sibling))
1397                         continue;
1398                 if (detaching)
1399                         error = T4_DETACH_CHILD(sibling);
1400                 else
1401                         (void)T4_ATTACH_CHILD(sibling);
1402                 if (error)
1403                         break;
1404         }
1405         return (error);
1406 }
1407
1408 /*
1409  * Idempotent
1410  */
1411 static int
1412 t4_detach(device_t dev)
1413 {
1414         struct adapter *sc;
1415         int rc;
1416
1417         sc = device_get_softc(dev);
1418
1419         rc = notify_siblings(dev, 1);
1420         if (rc) {
1421                 device_printf(dev,
1422                     "failed to detach sibling devices: %d\n", rc);
1423                 return (rc);
1424         }
1425
1426         return (t4_detach_common(dev));
1427 }
1428
1429 int
1430 t4_detach_common(device_t dev)
1431 {
1432         struct adapter *sc;
1433         struct port_info *pi;
1434         int i, rc;
1435
1436         sc = device_get_softc(dev);
1437
1438         if (sc->cdev) {
1439                 destroy_dev(sc->cdev);
1440                 sc->cdev = NULL;
1441         }
1442
1443         sc->flags &= ~CHK_MBOX_ACCESS;
1444         if (sc->flags & FULL_INIT_DONE) {
1445                 if (!(sc->flags & IS_VF))
1446                         t4_intr_disable(sc);
1447         }
1448
1449         if (device_is_attached(dev)) {
1450                 rc = bus_generic_detach(dev);
1451                 if (rc) {
1452                         device_printf(dev,
1453                             "failed to detach child devices: %d\n", rc);
1454                         return (rc);
1455                 }
1456         }
1457
1458         for (i = 0; i < sc->intr_count; i++)
1459                 t4_free_irq(sc, &sc->irq[i]);
1460
1461         if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1462                 t4_free_tx_sched(sc);
1463
1464         for (i = 0; i < MAX_NPORTS; i++) {
1465                 pi = sc->port[i];
1466                 if (pi) {
1467                         t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1468                         if (pi->dev)
1469                                 device_delete_child(dev, pi->dev);
1470
1471                         mtx_destroy(&pi->pi_lock);
1472                         free(pi->vi, M_CXGBE);
1473                         free(pi, M_CXGBE);
1474                 }
1475         }
1476
1477         device_delete_children(dev);
1478
1479         if (sc->flags & FULL_INIT_DONE)
1480                 adapter_full_uninit(sc);
1481
1482         if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1483                 t4_fw_bye(sc, sc->mbox);
1484
1485         if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1486                 pci_release_msi(dev);
1487
1488         if (sc->regs_res)
1489                 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1490                     sc->regs_res);
1491
1492         if (sc->udbs_res)
1493                 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1494                     sc->udbs_res);
1495
1496         if (sc->msix_res)
1497                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1498                     sc->msix_res);
1499
1500         if (sc->l2t)
1501                 t4_free_l2t(sc->l2t);
1502
1503 #ifdef TCP_OFFLOAD
1504         free(sc->sge.ofld_rxq, M_CXGBE);
1505         free(sc->sge.ofld_txq, M_CXGBE);
1506 #endif
1507 #ifdef DEV_NETMAP
1508         free(sc->sge.nm_rxq, M_CXGBE);
1509         free(sc->sge.nm_txq, M_CXGBE);
1510 #endif
1511         free(sc->irq, M_CXGBE);
1512         free(sc->sge.rxq, M_CXGBE);
1513         free(sc->sge.txq, M_CXGBE);
1514         free(sc->sge.ctrlq, M_CXGBE);
1515         free(sc->sge.iqmap, M_CXGBE);
1516         free(sc->sge.eqmap, M_CXGBE);
1517         free(sc->tids.ftid_tab, M_CXGBE);
1518         t4_destroy_dma_tag(sc);
1519         if (mtx_initialized(&sc->sc_lock)) {
1520                 sx_xlock(&t4_list_lock);
1521                 SLIST_REMOVE(&t4_list, sc, adapter, link);
1522                 sx_xunlock(&t4_list_lock);
1523                 mtx_destroy(&sc->sc_lock);
1524         }
1525
1526         callout_drain(&sc->sfl_callout);
1527         if (mtx_initialized(&sc->tids.ftid_lock))
1528                 mtx_destroy(&sc->tids.ftid_lock);
1529         if (mtx_initialized(&sc->sfl_lock))
1530                 mtx_destroy(&sc->sfl_lock);
1531         if (mtx_initialized(&sc->ifp_lock))
1532                 mtx_destroy(&sc->ifp_lock);
1533         if (mtx_initialized(&sc->reg_lock))
1534                 mtx_destroy(&sc->reg_lock);
1535
1536         for (i = 0; i < NUM_MEMWIN; i++) {
1537                 struct memwin *mw = &sc->memwin[i];
1538
1539                 if (rw_initialized(&mw->mw_lock))
1540                         rw_destroy(&mw->mw_lock);
1541         }
1542
1543         bzero(sc, sizeof(*sc));
1544
1545         return (0);
1546 }
1547
1548 static int
1549 cxgbe_probe(device_t dev)
1550 {
1551         char buf[128];
1552         struct port_info *pi = device_get_softc(dev);
1553
1554         snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1555         device_set_desc_copy(dev, buf);
1556
1557         return (BUS_PROBE_DEFAULT);
1558 }
1559
1560 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1561     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1562     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1563 #define T4_CAP_ENABLE (T4_CAP)
1564
1565 static int
1566 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1567 {
1568         struct ifnet *ifp;
1569         struct sbuf *sb;
1570
1571         vi->xact_addr_filt = -1;
1572         callout_init(&vi->tick, 1);
1573
1574         /* Allocate an ifnet and set it up */
1575         ifp = if_alloc(IFT_ETHER);
1576         if (ifp == NULL) {
1577                 device_printf(dev, "Cannot allocate ifnet\n");
1578                 return (ENOMEM);
1579         }
1580         vi->ifp = ifp;
1581         ifp->if_softc = vi;
1582
1583         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1584         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1585
1586         ifp->if_init = cxgbe_init;
1587         ifp->if_ioctl = cxgbe_ioctl;
1588         ifp->if_transmit = cxgbe_transmit;
1589         ifp->if_qflush = cxgbe_qflush;
1590         ifp->if_get_counter = cxgbe_get_counter;
1591
1592         ifp->if_capabilities = T4_CAP;
1593 #ifdef TCP_OFFLOAD
1594         if (vi->nofldrxq != 0)
1595                 ifp->if_capabilities |= IFCAP_TOE;
1596 #endif
1597         ifp->if_capenable = T4_CAP_ENABLE;
1598         ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1599             CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1600
1601         ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1602         ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1603         ifp->if_hw_tsomaxsegsize = 65536;
1604
1605         vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1606             EVENTHANDLER_PRI_ANY);
1607
1608         ether_ifattach(ifp, vi->hw_addr);
1609 #ifdef DEV_NETMAP
1610         if (vi->nnmrxq != 0)
1611                 cxgbe_nm_attach(vi);
1612 #endif
1613         sb = sbuf_new_auto();
1614         sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1615 #ifdef TCP_OFFLOAD
1616         if (ifp->if_capabilities & IFCAP_TOE)
1617                 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1618                     vi->nofldtxq, vi->nofldrxq);
1619 #endif
1620 #ifdef DEV_NETMAP
1621         if (ifp->if_capabilities & IFCAP_NETMAP)
1622                 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1623                     vi->nnmtxq, vi->nnmrxq);
1624 #endif
1625         sbuf_finish(sb);
1626         device_printf(dev, "%s\n", sbuf_data(sb));
1627         sbuf_delete(sb);
1628
1629         vi_sysctls(vi);
1630
1631         return (0);
1632 }
1633
1634 static int
1635 cxgbe_attach(device_t dev)
1636 {
1637         struct port_info *pi = device_get_softc(dev);
1638         struct adapter *sc = pi->adapter;
1639         struct vi_info *vi;
1640         int i, rc;
1641
1642         callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1643
1644         rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1645         if (rc)
1646                 return (rc);
1647
1648         for_each_vi(pi, i, vi) {
1649                 if (i == 0)
1650                         continue;
1651                 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1652                 if (vi->dev == NULL) {
1653                         device_printf(dev, "failed to add VI %d\n", i);
1654                         continue;
1655                 }
1656                 device_set_softc(vi->dev, vi);
1657         }
1658
1659         cxgbe_sysctls(pi);
1660
1661         bus_generic_attach(dev);
1662
1663         return (0);
1664 }
1665
1666 static void
1667 cxgbe_vi_detach(struct vi_info *vi)
1668 {
1669         struct ifnet *ifp = vi->ifp;
1670
1671         ether_ifdetach(ifp);
1672
1673         if (vi->vlan_c)
1674                 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1675
1676         /* Let detach proceed even if these fail. */
1677 #ifdef DEV_NETMAP
1678         if (ifp->if_capabilities & IFCAP_NETMAP)
1679                 cxgbe_nm_detach(vi);
1680 #endif
1681         cxgbe_uninit_synchronized(vi);
1682         callout_drain(&vi->tick);
1683         vi_full_uninit(vi);
1684
1685         if_free(vi->ifp);
1686         vi->ifp = NULL;
1687 }
1688
1689 static int
1690 cxgbe_detach(device_t dev)
1691 {
1692         struct port_info *pi = device_get_softc(dev);
1693         struct adapter *sc = pi->adapter;
1694         int rc;
1695
1696         /* Detach the extra VIs first. */
1697         rc = bus_generic_detach(dev);
1698         if (rc)
1699                 return (rc);
1700         device_delete_children(dev);
1701
1702         doom_vi(sc, &pi->vi[0]);
1703
1704         if (pi->flags & HAS_TRACEQ) {
1705                 sc->traceq = -1;        /* cloner should not create ifnet */
1706                 t4_tracer_port_detach(sc);
1707         }
1708
1709         cxgbe_vi_detach(&pi->vi[0]);
1710         callout_drain(&pi->tick);
1711         ifmedia_removeall(&pi->media);
1712
1713         end_synchronized_op(sc, 0);
1714
1715         return (0);
1716 }
1717
1718 static void
1719 cxgbe_init(void *arg)
1720 {
1721         struct vi_info *vi = arg;
1722         struct adapter *sc = vi->pi->adapter;
1723
1724         if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1725                 return;
1726         cxgbe_init_synchronized(vi);
1727         end_synchronized_op(sc, 0);
1728 }
1729
1730 static int
1731 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1732 {
1733         int rc = 0, mtu, can_sleep, if_flags, if_drv_flags, vi_if_flags;
1734         struct vi_info *vi = ifp->if_softc;
1735         struct port_info *pi = vi->pi;
1736         struct adapter *sc = pi->adapter;
1737         struct ifreq *ifr = (struct ifreq *)data;
1738         uint32_t mask;
1739
1740         switch (cmd) {
1741         case SIOCSIFMTU:
1742                 mtu = ifr->ifr_mtu;
1743                 if (mtu < ETHERMIN || mtu > MAX_MTU)
1744                         return (EINVAL);
1745
1746                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1747                 if (rc)
1748                         return (rc);
1749                 ifp->if_mtu = mtu;
1750                 if (vi->flags & VI_INIT_DONE) {
1751                         t4_update_fl_bufsize(ifp);
1752                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1753                                 rc = update_mac_settings(ifp, XGMAC_MTU);
1754                 }
1755                 end_synchronized_op(sc, 0);
1756                 break;
1757
1758         case SIOCSIFFLAGS:
1759                 /*
1760                  * Decide what to do, with the port lock held.
1761                  */
1762                 PORT_LOCK(pi);
1763                 if_flags = ifp->if_flags;
1764                 if_drv_flags = ifp->if_drv_flags;
1765                 vi_if_flags = vi->if_flags;
1766                 if (if_flags & IFF_UP && if_drv_flags & IFF_DRV_RUNNING &&
1767                     (vi_if_flags ^ if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) {
1768                         can_sleep = 0;
1769                 } else {
1770                         can_sleep = 1;
1771                 }
1772                 PORT_UNLOCK(pi);
1773
1774                 /*
1775                  * ifp/vi flags may change here but we'll just do what our local
1776                  * copy of the flags indicates and then update the driver owned
1777                  * ifp/vi flags (in a synch-op and with the port lock held) to
1778                  * reflect what we did.
1779                  */
1780
1781                 rc = begin_synchronized_op(sc, vi,
1782                     can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1783                 if (rc) {
1784                         if_printf(ifp, "%ssleepable synch operation failed: %d."
1785                             "  if_flags 0x%08x, if_drv_flags 0x%08x\n",
1786                             can_sleep ? "" : "non-", rc, if_flags,
1787                             if_drv_flags);
1788                         return (rc);
1789                 }
1790
1791                 if (if_flags & IFF_UP) {
1792                         if (if_drv_flags & IFF_DRV_RUNNING) {
1793                                 if ((if_flags ^ vi_if_flags) &
1794                                     (IFF_PROMISC | IFF_ALLMULTI)) {
1795                                         MPASS(can_sleep == 0);
1796                                         rc = update_mac_settings(ifp,
1797                                             XGMAC_PROMISC | XGMAC_ALLMULTI);
1798                                 }
1799                         } else {
1800                                 MPASS(can_sleep == 1);
1801                                 rc = cxgbe_init_synchronized(vi);
1802                         }
1803                 } else if (if_drv_flags & IFF_DRV_RUNNING) {
1804                         MPASS(can_sleep == 1);
1805                         rc = cxgbe_uninit_synchronized(vi);
1806                 }
1807                 PORT_LOCK(pi);
1808                 vi->if_flags = if_flags;
1809                 PORT_UNLOCK(pi);
1810                 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1811                 break;
1812
1813         case SIOCADDMULTI:
1814         case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1815                 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1816                 if (rc)
1817                         return (rc);
1818                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1819                         rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1820                 end_synchronized_op(sc, LOCK_HELD);
1821                 break;
1822
1823         case SIOCSIFCAP:
1824                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1825                 if (rc)
1826                         return (rc);
1827
1828                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1829                 if (mask & IFCAP_TXCSUM) {
1830                         ifp->if_capenable ^= IFCAP_TXCSUM;
1831                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1832
1833                         if (IFCAP_TSO4 & ifp->if_capenable &&
1834                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1835                                 ifp->if_capenable &= ~IFCAP_TSO4;
1836                                 if_printf(ifp,
1837                                     "tso4 disabled due to -txcsum.\n");
1838                         }
1839                 }
1840                 if (mask & IFCAP_TXCSUM_IPV6) {
1841                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1842                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1843
1844                         if (IFCAP_TSO6 & ifp->if_capenable &&
1845                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1846                                 ifp->if_capenable &= ~IFCAP_TSO6;
1847                                 if_printf(ifp,
1848                                     "tso6 disabled due to -txcsum6.\n");
1849                         }
1850                 }
1851                 if (mask & IFCAP_RXCSUM)
1852                         ifp->if_capenable ^= IFCAP_RXCSUM;
1853                 if (mask & IFCAP_RXCSUM_IPV6)
1854                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1855
1856                 /*
1857                  * Note that we leave CSUM_TSO alone (it is always set).  The
1858                  * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1859                  * sending a TSO request our way, so it's sufficient to toggle
1860                  * IFCAP_TSOx only.
1861                  */
1862                 if (mask & IFCAP_TSO4) {
1863                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1864                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1865                                 if_printf(ifp, "enable txcsum first.\n");
1866                                 rc = EAGAIN;
1867                                 goto fail;
1868                         }
1869                         ifp->if_capenable ^= IFCAP_TSO4;
1870                 }
1871                 if (mask & IFCAP_TSO6) {
1872                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1873                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1874                                 if_printf(ifp, "enable txcsum6 first.\n");
1875                                 rc = EAGAIN;
1876                                 goto fail;
1877                         }
1878                         ifp->if_capenable ^= IFCAP_TSO6;
1879                 }
1880                 if (mask & IFCAP_LRO) {
1881 #if defined(INET) || defined(INET6)
1882                         int i;
1883                         struct sge_rxq *rxq;
1884
1885                         ifp->if_capenable ^= IFCAP_LRO;
1886                         for_each_rxq(vi, i, rxq) {
1887                                 if (ifp->if_capenable & IFCAP_LRO)
1888                                         rxq->iq.flags |= IQ_LRO_ENABLED;
1889                                 else
1890                                         rxq->iq.flags &= ~IQ_LRO_ENABLED;
1891                         }
1892 #endif
1893                 }
1894 #ifdef TCP_OFFLOAD
1895                 if (mask & IFCAP_TOE) {
1896                         int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1897
1898                         rc = toe_capability(vi, enable);
1899                         if (rc != 0)
1900                                 goto fail;
1901
1902                         ifp->if_capenable ^= mask;
1903                 }
1904 #endif
1905                 if (mask & IFCAP_VLAN_HWTAGGING) {
1906                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1907                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1908                                 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1909                 }
1910                 if (mask & IFCAP_VLAN_MTU) {
1911                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
1912
1913                         /* Need to find out how to disable auto-mtu-inflation */
1914                 }
1915                 if (mask & IFCAP_VLAN_HWTSO)
1916                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1917                 if (mask & IFCAP_VLAN_HWCSUM)
1918                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1919
1920 #ifdef VLAN_CAPABILITIES
1921                 VLAN_CAPABILITIES(ifp);
1922 #endif
1923 fail:
1924                 end_synchronized_op(sc, 0);
1925                 break;
1926
1927         case SIOCSIFMEDIA:
1928         case SIOCGIFMEDIA:
1929         case SIOCGIFXMEDIA:
1930                 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1931                 break;
1932
1933         case SIOCGI2C: {
1934                 struct ifi2creq i2c;
1935
1936                 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
1937                 if (rc != 0)
1938                         break;
1939                 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1940                         rc = EPERM;
1941                         break;
1942                 }
1943                 if (i2c.len > sizeof(i2c.data)) {
1944                         rc = EINVAL;
1945                         break;
1946                 }
1947                 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1948                 if (rc)
1949                         return (rc);
1950                 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1951                     i2c.offset, i2c.len, &i2c.data[0]);
1952                 end_synchronized_op(sc, 0);
1953                 if (rc == 0)
1954                         rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
1955                 break;
1956         }
1957
1958         default:
1959                 rc = ether_ioctl(ifp, cmd, data);
1960         }
1961
1962         return (rc);
1963 }
1964
1965 static int
1966 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1967 {
1968         struct vi_info *vi = ifp->if_softc;
1969         struct port_info *pi = vi->pi;
1970         struct adapter *sc = pi->adapter;
1971         struct sge_txq *txq;
1972         void *items[1];
1973         int rc;
1974
1975         M_ASSERTPKTHDR(m);
1976         MPASS(m->m_nextpkt == NULL);    /* not quite ready for this yet */
1977
1978         if (__predict_false(pi->link_cfg.link_ok == false)) {
1979                 m_freem(m);
1980                 return (ENETDOWN);
1981         }
1982
1983         rc = parse_pkt(sc, &m);
1984         if (__predict_false(rc != 0)) {
1985                 MPASS(m == NULL);                       /* was freed already */
1986                 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1987                 return (rc);
1988         }
1989
1990         /* Select a txq. */
1991         txq = &sc->sge.txq[vi->first_txq];
1992         if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1993                 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1994                     vi->rsrv_noflowq);
1995
1996         items[0] = m;
1997         rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1998         if (__predict_false(rc != 0))
1999                 m_freem(m);
2000
2001         return (rc);
2002 }
2003
2004 static void
2005 cxgbe_qflush(struct ifnet *ifp)
2006 {
2007         struct vi_info *vi = ifp->if_softc;
2008         struct sge_txq *txq;
2009         int i;
2010
2011         /* queues do not exist if !VI_INIT_DONE. */
2012         if (vi->flags & VI_INIT_DONE) {
2013                 for_each_txq(vi, i, txq) {
2014                         TXQ_LOCK(txq);
2015                         txq->eq.flags |= EQ_QFLUSH;
2016                         TXQ_UNLOCK(txq);
2017                         while (!mp_ring_is_idle(txq->r)) {
2018                                 mp_ring_check_drainage(txq->r, 0);
2019                                 pause("qflush", 1);
2020                         }
2021                         TXQ_LOCK(txq);
2022                         txq->eq.flags &= ~EQ_QFLUSH;
2023                         TXQ_UNLOCK(txq);
2024                 }
2025         }
2026         if_qflush(ifp);
2027 }
2028
2029 static uint64_t
2030 vi_get_counter(struct ifnet *ifp, ift_counter c)
2031 {
2032         struct vi_info *vi = ifp->if_softc;
2033         struct fw_vi_stats_vf *s = &vi->stats;
2034
2035         vi_refresh_stats(vi->pi->adapter, vi);
2036
2037         switch (c) {
2038         case IFCOUNTER_IPACKETS:
2039                 return (s->rx_bcast_frames + s->rx_mcast_frames +
2040                     s->rx_ucast_frames);
2041         case IFCOUNTER_IERRORS:
2042                 return (s->rx_err_frames);
2043         case IFCOUNTER_OPACKETS:
2044                 return (s->tx_bcast_frames + s->tx_mcast_frames +
2045                     s->tx_ucast_frames + s->tx_offload_frames);
2046         case IFCOUNTER_OERRORS:
2047                 return (s->tx_drop_frames);
2048         case IFCOUNTER_IBYTES:
2049                 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2050                     s->rx_ucast_bytes);
2051         case IFCOUNTER_OBYTES:
2052                 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2053                     s->tx_ucast_bytes + s->tx_offload_bytes);
2054         case IFCOUNTER_IMCASTS:
2055                 return (s->rx_mcast_frames);
2056         case IFCOUNTER_OMCASTS:
2057                 return (s->tx_mcast_frames);
2058         case IFCOUNTER_OQDROPS: {
2059                 uint64_t drops;
2060
2061                 drops = 0;
2062                 if (vi->flags & VI_INIT_DONE) {
2063                         int i;
2064                         struct sge_txq *txq;
2065
2066                         for_each_txq(vi, i, txq)
2067                                 drops += counter_u64_fetch(txq->r->drops);
2068                 }
2069
2070                 return (drops);
2071
2072         }
2073
2074         default:
2075                 return (if_get_counter_default(ifp, c));
2076         }
2077 }
2078
2079 uint64_t
2080 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2081 {
2082         struct vi_info *vi = ifp->if_softc;
2083         struct port_info *pi = vi->pi;
2084         struct adapter *sc = pi->adapter;
2085         struct port_stats *s = &pi->stats;
2086
2087         if (pi->nvi > 1 || sc->flags & IS_VF)
2088                 return (vi_get_counter(ifp, c));
2089
2090         cxgbe_refresh_stats(sc, pi);
2091
2092         switch (c) {
2093         case IFCOUNTER_IPACKETS:
2094                 return (s->rx_frames);
2095
2096         case IFCOUNTER_IERRORS:
2097                 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2098                     s->rx_fcs_err + s->rx_len_err);
2099
2100         case IFCOUNTER_OPACKETS:
2101                 return (s->tx_frames);
2102
2103         case IFCOUNTER_OERRORS:
2104                 return (s->tx_error_frames);
2105
2106         case IFCOUNTER_IBYTES:
2107                 return (s->rx_octets);
2108
2109         case IFCOUNTER_OBYTES:
2110                 return (s->tx_octets);
2111
2112         case IFCOUNTER_IMCASTS:
2113                 return (s->rx_mcast_frames);
2114
2115         case IFCOUNTER_OMCASTS:
2116                 return (s->tx_mcast_frames);
2117
2118         case IFCOUNTER_IQDROPS:
2119                 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2120                     s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2121                     s->rx_trunc3 + pi->tnl_cong_drops);
2122
2123         case IFCOUNTER_OQDROPS: {
2124                 uint64_t drops;
2125
2126                 drops = s->tx_drop;
2127                 if (vi->flags & VI_INIT_DONE) {
2128                         int i;
2129                         struct sge_txq *txq;
2130
2131                         for_each_txq(vi, i, txq)
2132                                 drops += counter_u64_fetch(txq->r->drops);
2133                 }
2134
2135                 return (drops);
2136
2137         }
2138
2139         default:
2140                 return (if_get_counter_default(ifp, c));
2141         }
2142 }
2143
2144 /*
2145  * The kernel picks a media from the list we had provided but we still validate
2146  * the requeste.
2147  */
2148 static int
2149 cxgbe_media_change(struct ifnet *ifp)
2150 {
2151         struct vi_info *vi = ifp->if_softc;
2152         struct port_info *pi = vi->pi;
2153         struct ifmedia *ifm = &pi->media;
2154         struct link_config *lc = &pi->link_cfg;
2155         struct adapter *sc = pi->adapter;
2156         int rc;
2157
2158         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2159         if (rc != 0)
2160                 return (rc);
2161         PORT_LOCK(pi);
2162         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2163                 /* ifconfig .. media autoselect */
2164                 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2165                         rc = ENOTSUP; /* AN not supported by transceiver */
2166                         goto done;
2167                 }
2168                 lc->requested_aneg = AUTONEG_ENABLE;
2169                 lc->requested_speed = 0;
2170                 lc->requested_fc |= PAUSE_AUTONEG;
2171         } else {
2172                 lc->requested_aneg = AUTONEG_DISABLE;
2173                 lc->requested_speed =
2174                     ifmedia_baudrate(ifm->ifm_media) / 1000000;
2175                 lc->requested_fc = 0;
2176                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2177                         lc->requested_fc |= PAUSE_RX;
2178                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2179                         lc->requested_fc |= PAUSE_TX;
2180         }
2181         if (pi->up_vis > 0) {
2182                 fixup_link_config(pi);
2183                 rc = apply_link_config(pi);
2184         }
2185 done:
2186         PORT_UNLOCK(pi);
2187         end_synchronized_op(sc, 0);
2188         return (rc);
2189 }
2190
2191 /*
2192  * Base media word (without ETHER, pause, link active, etc.) for the port at the
2193  * given speed.
2194  */
2195 static int
2196 port_mword(struct port_info *pi, uint32_t speed)
2197 {
2198
2199         MPASS(speed & M_FW_PORT_CAP32_SPEED);
2200         MPASS(powerof2(speed));
2201
2202         switch(pi->port_type) {
2203         case FW_PORT_TYPE_BT_SGMII:
2204         case FW_PORT_TYPE_BT_XFI:
2205         case FW_PORT_TYPE_BT_XAUI:
2206                 /* BaseT */
2207                 switch (speed) {
2208                 case FW_PORT_CAP32_SPEED_100M:
2209                         return (IFM_100_T);
2210                 case FW_PORT_CAP32_SPEED_1G:
2211                         return (IFM_1000_T);
2212                 case FW_PORT_CAP32_SPEED_10G:
2213                         return (IFM_10G_T);
2214                 }
2215                 break;
2216         case FW_PORT_TYPE_KX4:
2217                 if (speed == FW_PORT_CAP32_SPEED_10G)
2218                         return (IFM_10G_KX4);
2219                 break;
2220         case FW_PORT_TYPE_CX4:
2221                 if (speed == FW_PORT_CAP32_SPEED_10G)
2222                         return (IFM_10G_CX4);
2223                 break;
2224         case FW_PORT_TYPE_KX:
2225                 if (speed == FW_PORT_CAP32_SPEED_1G)
2226                         return (IFM_1000_KX);
2227                 break;
2228         case FW_PORT_TYPE_KR:
2229         case FW_PORT_TYPE_BP_AP:
2230         case FW_PORT_TYPE_BP4_AP:
2231         case FW_PORT_TYPE_BP40_BA:
2232         case FW_PORT_TYPE_KR4_100G:
2233         case FW_PORT_TYPE_KR_SFP28:
2234         case FW_PORT_TYPE_KR_XLAUI:
2235                 switch (speed) {
2236                 case FW_PORT_CAP32_SPEED_1G:
2237                         return (IFM_1000_KX);
2238                 case FW_PORT_CAP32_SPEED_10G:
2239                         return (IFM_10G_KR);
2240                 case FW_PORT_CAP32_SPEED_25G:
2241                         return (IFM_25G_KR);
2242                 case FW_PORT_CAP32_SPEED_40G:
2243                         return (IFM_40G_KR4);
2244                 case FW_PORT_CAP32_SPEED_50G:
2245                         return (IFM_50G_KR2);
2246                 case FW_PORT_CAP32_SPEED_100G:
2247                         return (IFM_100G_KR4);
2248                 }
2249                 break;
2250         case FW_PORT_TYPE_FIBER_XFI:
2251         case FW_PORT_TYPE_FIBER_XAUI:
2252         case FW_PORT_TYPE_SFP:
2253         case FW_PORT_TYPE_QSFP_10G:
2254         case FW_PORT_TYPE_QSA:
2255         case FW_PORT_TYPE_QSFP:
2256         case FW_PORT_TYPE_CR4_QSFP:
2257         case FW_PORT_TYPE_CR_QSFP:
2258         case FW_PORT_TYPE_CR2_QSFP:
2259         case FW_PORT_TYPE_SFP28:
2260                 /* Pluggable transceiver */
2261                 switch (pi->mod_type) {
2262                 case FW_PORT_MOD_TYPE_LR:
2263                         switch (speed) {
2264                         case FW_PORT_CAP32_SPEED_1G:
2265                                 return (IFM_1000_LX);
2266                         case FW_PORT_CAP32_SPEED_10G:
2267                                 return (IFM_10G_LR);
2268                         case FW_PORT_CAP32_SPEED_25G:
2269                                 return (IFM_25G_LR);
2270                         case FW_PORT_CAP32_SPEED_40G:
2271                                 return (IFM_40G_LR4);
2272                         case FW_PORT_CAP32_SPEED_50G:
2273                                 return (IFM_50G_LR2);
2274                         case FW_PORT_CAP32_SPEED_100G:
2275                                 return (IFM_100G_LR4);
2276                         }
2277                         break;
2278                 case FW_PORT_MOD_TYPE_SR:
2279                         switch (speed) {
2280                         case FW_PORT_CAP32_SPEED_1G:
2281                                 return (IFM_1000_SX);
2282                         case FW_PORT_CAP32_SPEED_10G:
2283                                 return (IFM_10G_SR);
2284                         case FW_PORT_CAP32_SPEED_25G:
2285                                 return (IFM_25G_SR);
2286                         case FW_PORT_CAP32_SPEED_40G:
2287                                 return (IFM_40G_SR4);
2288                         case FW_PORT_CAP32_SPEED_50G:
2289                                 return (IFM_50G_SR2);
2290                         case FW_PORT_CAP32_SPEED_100G:
2291                                 return (IFM_100G_SR4);
2292                         }
2293                         break;
2294                 case FW_PORT_MOD_TYPE_ER:
2295                         if (speed == FW_PORT_CAP32_SPEED_10G)
2296                                 return (IFM_10G_ER);
2297                         break;
2298                 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2299                 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2300                         switch (speed) {
2301                         case FW_PORT_CAP32_SPEED_1G:
2302                                 return (IFM_1000_CX);
2303                         case FW_PORT_CAP32_SPEED_10G:
2304                                 return (IFM_10G_TWINAX);
2305                         case FW_PORT_CAP32_SPEED_25G:
2306                                 return (IFM_25G_CR);
2307                         case FW_PORT_CAP32_SPEED_40G:
2308                                 return (IFM_40G_CR4);
2309                         case FW_PORT_CAP32_SPEED_50G:
2310                                 return (IFM_50G_CR2);
2311                         case FW_PORT_CAP32_SPEED_100G:
2312                                 return (IFM_100G_CR4);
2313                         }
2314                         break;
2315                 case FW_PORT_MOD_TYPE_LRM:
2316                         if (speed == FW_PORT_CAP32_SPEED_10G)
2317                                 return (IFM_10G_LRM);
2318                         break;
2319                 case FW_PORT_MOD_TYPE_NA:
2320                         MPASS(0);       /* Not pluggable? */
2321                         /* fall throough */
2322                 case FW_PORT_MOD_TYPE_ERROR:
2323                 case FW_PORT_MOD_TYPE_UNKNOWN:
2324                 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2325                         break;
2326                 case FW_PORT_MOD_TYPE_NONE:
2327                         return (IFM_NONE);
2328                 }
2329                 break;
2330         case FW_PORT_TYPE_NONE:
2331                 return (IFM_NONE);
2332         }
2333
2334         return (IFM_UNKNOWN);
2335 }
2336
2337 static void
2338 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2339 {
2340         struct vi_info *vi = ifp->if_softc;
2341         struct port_info *pi = vi->pi;
2342         struct adapter *sc = pi->adapter;
2343         struct link_config *lc = &pi->link_cfg;
2344
2345         if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2346                 return;
2347         PORT_LOCK(pi);
2348
2349         if (pi->up_vis == 0) {
2350                 /*
2351                  * If all the interfaces are administratively down the firmware
2352                  * does not report transceiver changes.  Refresh port info here
2353                  * so that ifconfig displays accurate ifmedia at all times.
2354                  * This is the only reason we have a synchronized op in this
2355                  * function.  Just PORT_LOCK would have been enough otherwise.
2356                  */
2357                 t4_update_port_info(pi);
2358                 build_medialist(pi);
2359         }
2360
2361         /* ifm_status */
2362         ifmr->ifm_status = IFM_AVALID;
2363         if (lc->link_ok == false)
2364                 goto done;
2365         ifmr->ifm_status |= IFM_ACTIVE;
2366
2367         /* ifm_active */
2368         ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2369         ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2370         if (lc->fc & PAUSE_RX)
2371                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2372         if (lc->fc & PAUSE_TX)
2373                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2374         ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2375 done:
2376         PORT_UNLOCK(pi);
2377         end_synchronized_op(sc, 0);
2378 }
2379
2380 static int
2381 vcxgbe_probe(device_t dev)
2382 {
2383         char buf[128];
2384         struct vi_info *vi = device_get_softc(dev);
2385
2386         snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2387             vi - vi->pi->vi);
2388         device_set_desc_copy(dev, buf);
2389
2390         return (BUS_PROBE_DEFAULT);
2391 }
2392
2393 static int
2394 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2395 {
2396         int func, index, rc;
2397         uint32_t param, val;
2398
2399         ASSERT_SYNCHRONIZED_OP(sc);
2400
2401         index = vi - pi->vi;
2402         MPASS(index > 0);       /* This function deals with _extra_ VIs only */
2403         KASSERT(index < nitems(vi_mac_funcs),
2404             ("%s: VI %s doesn't have a MAC func", __func__,
2405             device_get_nameunit(vi->dev)));
2406         func = vi_mac_funcs[index];
2407         rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2408             vi->hw_addr, &vi->rss_size, func, 0);
2409         if (rc < 0) {
2410                 device_printf(vi->dev, "failed to allocate virtual interface %d"
2411                     "for port %d: %d\n", index, pi->port_id, -rc);
2412                 return (-rc);
2413         }
2414         vi->viid = rc;
2415         if (chip_id(sc) <= CHELSIO_T5)
2416                 vi->smt_idx = (rc & 0x7f) << 1;
2417         else
2418                 vi->smt_idx = (rc & 0x7f);
2419
2420         if (vi->rss_size == 1) {
2421                 /*
2422                  * This VI didn't get a slice of the RSS table.  Reduce the
2423                  * number of VIs being created (hw.cxgbe.num_vis) or modify the
2424                  * configuration file (nvi, rssnvi for this PF) if this is a
2425                  * problem.
2426                  */
2427                 device_printf(vi->dev, "RSS table not available.\n");
2428                 vi->rss_base = 0xffff;
2429
2430                 return (0);
2431         }
2432
2433         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2434             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2435             V_FW_PARAMS_PARAM_YZ(vi->viid);
2436         rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
2437         if (rc)
2438                 vi->rss_base = 0xffff;
2439         else {
2440                 MPASS((val >> 16) == vi->rss_size);
2441                 vi->rss_base = val & 0xffff;
2442         }
2443
2444         return (0);
2445 }
2446
2447 static int
2448 vcxgbe_attach(device_t dev)
2449 {
2450         struct vi_info *vi;
2451         struct port_info *pi;
2452         struct adapter *sc;
2453         int rc;
2454
2455         vi = device_get_softc(dev);
2456         pi = vi->pi;
2457         sc = pi->adapter;
2458
2459         rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2460         if (rc)
2461                 return (rc);
2462         rc = alloc_extra_vi(sc, pi, vi);
2463         end_synchronized_op(sc, 0);
2464         if (rc)
2465                 return (rc);
2466
2467         rc = cxgbe_vi_attach(dev, vi);
2468         if (rc) {
2469                 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2470                 return (rc);
2471         }
2472         return (0);
2473 }
2474
2475 static int
2476 vcxgbe_detach(device_t dev)
2477 {
2478         struct vi_info *vi;
2479         struct adapter *sc;
2480
2481         vi = device_get_softc(dev);
2482         sc = vi->pi->adapter;
2483
2484         doom_vi(sc, vi);
2485
2486         cxgbe_vi_detach(vi);
2487         t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2488
2489         end_synchronized_op(sc, 0);
2490
2491         return (0);
2492 }
2493
2494 void
2495 t4_fatal_err(struct adapter *sc)
2496 {
2497         t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2498         t4_intr_disable(sc);
2499         log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2500             device_get_nameunit(sc->dev));
2501 }
2502
2503 void
2504 t4_add_adapter(struct adapter *sc)
2505 {
2506         sx_xlock(&t4_list_lock);
2507         SLIST_INSERT_HEAD(&t4_list, sc, link);
2508         sx_xunlock(&t4_list_lock);
2509 }
2510
2511 int
2512 t4_map_bars_0_and_4(struct adapter *sc)
2513 {
2514         sc->regs_rid = PCIR_BAR(0);
2515         sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2516             &sc->regs_rid, RF_ACTIVE);
2517         if (sc->regs_res == NULL) {
2518                 device_printf(sc->dev, "cannot map registers.\n");
2519                 return (ENXIO);
2520         }
2521         sc->bt = rman_get_bustag(sc->regs_res);
2522         sc->bh = rman_get_bushandle(sc->regs_res);
2523         sc->mmio_len = rman_get_size(sc->regs_res);
2524         setbit(&sc->doorbells, DOORBELL_KDB);
2525
2526         sc->msix_rid = PCIR_BAR(4);
2527         sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2528             &sc->msix_rid, RF_ACTIVE);
2529         if (sc->msix_res == NULL) {
2530                 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2531                 return (ENXIO);
2532         }
2533
2534         return (0);
2535 }
2536
2537 int
2538 t4_map_bar_2(struct adapter *sc)
2539 {
2540
2541         /*
2542          * T4: only iWARP driver uses the userspace doorbells.  There is no need
2543          * to map it if RDMA is disabled.
2544          */
2545         if (is_t4(sc) && sc->rdmacaps == 0)
2546                 return (0);
2547
2548         sc->udbs_rid = PCIR_BAR(2);
2549         sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2550             &sc->udbs_rid, RF_ACTIVE);
2551         if (sc->udbs_res == NULL) {
2552                 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2553                 return (ENXIO);
2554         }
2555         sc->udbs_base = rman_get_virtual(sc->udbs_res);
2556
2557         if (chip_id(sc) >= CHELSIO_T5) {
2558                 setbit(&sc->doorbells, DOORBELL_UDB);
2559 #if defined(__i386__) || defined(__amd64__)
2560                 if (t5_write_combine) {
2561                         int rc, mode;
2562
2563                         /*
2564                          * Enable write combining on BAR2.  This is the
2565                          * userspace doorbell BAR and is split into 128B
2566                          * (UDBS_SEG_SIZE) doorbell regions, each associated
2567                          * with an egress queue.  The first 64B has the doorbell
2568                          * and the second 64B can be used to submit a tx work
2569                          * request with an implicit doorbell.
2570                          */
2571
2572                         rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2573                             rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2574                         if (rc == 0) {
2575                                 clrbit(&sc->doorbells, DOORBELL_UDB);
2576                                 setbit(&sc->doorbells, DOORBELL_WCWR);
2577                                 setbit(&sc->doorbells, DOORBELL_UDBWC);
2578                         } else {
2579                                 device_printf(sc->dev,
2580                                     "couldn't enable write combining: %d\n",
2581                                     rc);
2582                         }
2583
2584                         mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2585                         t4_write_reg(sc, A_SGE_STAT_CFG,
2586                             V_STATSOURCE_T5(7) | mode);
2587                 }
2588 #endif
2589         }
2590         sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2591
2592         return (0);
2593 }
2594
2595 struct memwin_init {
2596         uint32_t base;
2597         uint32_t aperture;
2598 };
2599
2600 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2601         { MEMWIN0_BASE, MEMWIN0_APERTURE },
2602         { MEMWIN1_BASE, MEMWIN1_APERTURE },
2603         { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2604 };
2605
2606 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2607         { MEMWIN0_BASE, MEMWIN0_APERTURE },
2608         { MEMWIN1_BASE, MEMWIN1_APERTURE },
2609         { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2610 };
2611
2612 static void
2613 setup_memwin(struct adapter *sc)
2614 {
2615         const struct memwin_init *mw_init;
2616         struct memwin *mw;
2617         int i;
2618         uint32_t bar0;
2619
2620         if (is_t4(sc)) {
2621                 /*
2622                  * Read low 32b of bar0 indirectly via the hardware backdoor
2623                  * mechanism.  Works from within PCI passthrough environments
2624                  * too, where rman_get_start() can return a different value.  We
2625                  * need to program the T4 memory window decoders with the actual
2626                  * addresses that will be coming across the PCIe link.
2627                  */
2628                 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2629                 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2630
2631                 mw_init = &t4_memwin[0];
2632         } else {
2633                 /* T5+ use the relative offset inside the PCIe BAR */
2634                 bar0 = 0;
2635
2636                 mw_init = &t5_memwin[0];
2637         }
2638
2639         for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2640                 rw_init(&mw->mw_lock, "memory window access");
2641                 mw->mw_base = mw_init->base;
2642                 mw->mw_aperture = mw_init->aperture;
2643                 mw->mw_curpos = 0;
2644                 t4_write_reg(sc,
2645                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2646                     (mw->mw_base + bar0) | V_BIR(0) |
2647                     V_WINDOW(ilog2(mw->mw_aperture) - 10));
2648                 rw_wlock(&mw->mw_lock);
2649                 position_memwin(sc, i, 0);
2650                 rw_wunlock(&mw->mw_lock);
2651         }
2652
2653         /* flush */
2654         t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2655 }
2656
2657 /*
2658  * Positions the memory window at the given address in the card's address space.
2659  * There are some alignment requirements and the actual position may be at an
2660  * address prior to the requested address.  mw->mw_curpos always has the actual
2661  * position of the window.
2662  */
2663 static void
2664 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2665 {
2666         struct memwin *mw;
2667         uint32_t pf;
2668         uint32_t reg;
2669
2670         MPASS(idx >= 0 && idx < NUM_MEMWIN);
2671         mw = &sc->memwin[idx];
2672         rw_assert(&mw->mw_lock, RA_WLOCKED);
2673
2674         if (is_t4(sc)) {
2675                 pf = 0;
2676                 mw->mw_curpos = addr & ~0xf;    /* start must be 16B aligned */
2677         } else {
2678                 pf = V_PFNUM(sc->pf);
2679                 mw->mw_curpos = addr & ~0x7f;   /* start must be 128B aligned */
2680         }
2681         reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2682         t4_write_reg(sc, reg, mw->mw_curpos | pf);
2683         t4_read_reg(sc, reg);   /* flush */
2684 }
2685
2686 static int
2687 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2688     int len, int rw)
2689 {
2690         struct memwin *mw;
2691         uint32_t mw_end, v;
2692
2693         MPASS(idx >= 0 && idx < NUM_MEMWIN);
2694
2695         /* Memory can only be accessed in naturally aligned 4 byte units */
2696         if (addr & 3 || len & 3 || len <= 0)
2697                 return (EINVAL);
2698
2699         mw = &sc->memwin[idx];
2700         while (len > 0) {
2701                 rw_rlock(&mw->mw_lock);
2702                 mw_end = mw->mw_curpos + mw->mw_aperture;
2703                 if (addr >= mw_end || addr < mw->mw_curpos) {
2704                         /* Will need to reposition the window */
2705                         if (!rw_try_upgrade(&mw->mw_lock)) {
2706                                 rw_runlock(&mw->mw_lock);
2707                                 rw_wlock(&mw->mw_lock);
2708                         }
2709                         rw_assert(&mw->mw_lock, RA_WLOCKED);
2710                         position_memwin(sc, idx, addr);
2711                         rw_downgrade(&mw->mw_lock);
2712                         mw_end = mw->mw_curpos + mw->mw_aperture;
2713                 }
2714                 rw_assert(&mw->mw_lock, RA_RLOCKED);
2715                 while (addr < mw_end && len > 0) {
2716                         if (rw == 0) {
2717                                 v = t4_read_reg(sc, mw->mw_base + addr -
2718                                     mw->mw_curpos);
2719                                 *val++ = le32toh(v);
2720                         } else {
2721                                 v = *val++;
2722                                 t4_write_reg(sc, mw->mw_base + addr -
2723                                     mw->mw_curpos, htole32(v));
2724                         }
2725                         addr += 4;
2726                         len -= 4;
2727                 }
2728                 rw_runlock(&mw->mw_lock);
2729         }
2730
2731         return (0);
2732 }
2733
2734 static inline int
2735 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2736     int len)
2737 {
2738
2739         return (rw_via_memwin(sc, idx, addr, val, len, 0));
2740 }
2741
2742 static inline int
2743 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2744     const uint32_t *val, int len)
2745 {
2746
2747         return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2748 }
2749
2750 static int
2751 t4_range_cmp(const void *a, const void *b)
2752 {
2753         return ((const struct t4_range *)a)->start -
2754                ((const struct t4_range *)b)->start;
2755 }
2756
2757 /*
2758  * Verify that the memory range specified by the addr/len pair is valid within
2759  * the card's address space.
2760  */
2761 static int
2762 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2763 {
2764         struct t4_range mem_ranges[4], *r, *next;
2765         uint32_t em, addr_len;
2766         int i, n, remaining;
2767
2768         /* Memory can only be accessed in naturally aligned 4 byte units */
2769         if (addr & 3 || len & 3 || len == 0)
2770                 return (EINVAL);
2771
2772         /* Enabled memories */
2773         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2774
2775         r = &mem_ranges[0];
2776         n = 0;
2777         bzero(r, sizeof(mem_ranges));
2778         if (em & F_EDRAM0_ENABLE) {
2779                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2780                 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2781                 if (r->size > 0) {
2782                         r->start = G_EDRAM0_BASE(addr_len) << 20;
2783                         if (addr >= r->start &&
2784                             addr + len <= r->start + r->size)
2785                                 return (0);
2786                         r++;
2787                         n++;
2788                 }
2789         }
2790         if (em & F_EDRAM1_ENABLE) {
2791                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2792                 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2793                 if (r->size > 0) {
2794                         r->start = G_EDRAM1_BASE(addr_len) << 20;
2795                         if (addr >= r->start &&
2796                             addr + len <= r->start + r->size)
2797                                 return (0);
2798                         r++;
2799                         n++;
2800                 }
2801         }
2802         if (em & F_EXT_MEM_ENABLE) {
2803                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2804                 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2805                 if (r->size > 0) {
2806                         r->start = G_EXT_MEM_BASE(addr_len) << 20;
2807                         if (addr >= r->start &&
2808                             addr + len <= r->start + r->size)
2809                                 return (0);
2810                         r++;
2811                         n++;
2812                 }
2813         }
2814         if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2815                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2816                 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2817                 if (r->size > 0) {
2818                         r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2819                         if (addr >= r->start &&
2820                             addr + len <= r->start + r->size)
2821                                 return (0);
2822                         r++;
2823                         n++;
2824                 }
2825         }
2826         MPASS(n <= nitems(mem_ranges));
2827
2828         if (n > 1) {
2829                 /* Sort and merge the ranges. */
2830                 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2831
2832                 /* Start from index 0 and examine the next n - 1 entries. */
2833                 r = &mem_ranges[0];
2834                 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2835
2836                         MPASS(r->size > 0);     /* r is a valid entry. */
2837                         next = r + 1;
2838                         MPASS(next->size > 0);  /* and so is the next one. */
2839
2840                         while (r->start + r->size >= next->start) {
2841                                 /* Merge the next one into the current entry. */
2842                                 r->size = max(r->start + r->size,
2843                                     next->start + next->size) - r->start;
2844                                 n--;    /* One fewer entry in total. */
2845                                 if (--remaining == 0)
2846                                         goto done;      /* short circuit */
2847                                 next++;
2848                         }
2849                         if (next != r + 1) {
2850                                 /*
2851                                  * Some entries were merged into r and next
2852                                  * points to the first valid entry that couldn't
2853                                  * be merged.
2854                                  */
2855                                 MPASS(next->size > 0);  /* must be valid */
2856                                 memcpy(r + 1, next, remaining * sizeof(*r));
2857 #ifdef INVARIANTS
2858                                 /*
2859                                  * This so that the foo->size assertion in the
2860                                  * next iteration of the loop do the right
2861                                  * thing for entries that were pulled up and are
2862                                  * no longer valid.
2863                                  */
2864                                 MPASS(n < nitems(mem_ranges));
2865                                 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2866                                     sizeof(struct t4_range));
2867 #endif
2868                         }
2869                 }
2870 done:
2871                 /* Done merging the ranges. */
2872                 MPASS(n > 0);
2873                 r = &mem_ranges[0];
2874                 for (i = 0; i < n; i++, r++) {
2875                         if (addr >= r->start &&
2876                             addr + len <= r->start + r->size)
2877                                 return (0);
2878                 }
2879         }
2880
2881         return (EFAULT);
2882 }
2883
2884 static int
2885 fwmtype_to_hwmtype(int mtype)
2886 {
2887
2888         switch (mtype) {
2889         case FW_MEMTYPE_EDC0:
2890                 return (MEM_EDC0);
2891         case FW_MEMTYPE_EDC1:
2892                 return (MEM_EDC1);
2893         case FW_MEMTYPE_EXTMEM:
2894                 return (MEM_MC0);
2895         case FW_MEMTYPE_EXTMEM1:
2896                 return (MEM_MC1);
2897         default:
2898                 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2899         }
2900 }
2901
2902 /*
2903  * Verify that the memory range specified by the memtype/offset/len pair is
2904  * valid and lies entirely within the memtype specified.  The global address of
2905  * the start of the range is returned in addr.
2906  */
2907 static int
2908 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
2909     uint32_t *addr)
2910 {
2911         uint32_t em, addr_len, maddr;
2912
2913         /* Memory can only be accessed in naturally aligned 4 byte units */
2914         if (off & 3 || len & 3 || len == 0)
2915                 return (EINVAL);
2916
2917         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2918         switch (fwmtype_to_hwmtype(mtype)) {
2919         case MEM_EDC0:
2920                 if (!(em & F_EDRAM0_ENABLE))
2921                         return (EINVAL);
2922                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2923                 maddr = G_EDRAM0_BASE(addr_len) << 20;
2924                 break;
2925         case MEM_EDC1:
2926                 if (!(em & F_EDRAM1_ENABLE))
2927                         return (EINVAL);
2928                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2929                 maddr = G_EDRAM1_BASE(addr_len) << 20;
2930                 break;
2931         case MEM_MC:
2932                 if (!(em & F_EXT_MEM_ENABLE))
2933                         return (EINVAL);
2934                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2935                 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2936                 break;
2937         case MEM_MC1:
2938                 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2939                         return (EINVAL);
2940                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2941                 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2942                 break;
2943         default:
2944                 return (EINVAL);
2945         }
2946
2947         *addr = maddr + off;    /* global address */
2948         return (validate_mem_range(sc, *addr, len));
2949 }
2950
2951 static int
2952 fixup_devlog_params(struct adapter *sc)
2953 {
2954         struct devlog_params *dparams = &sc->params.devlog;
2955         int rc;
2956
2957         rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2958             dparams->size, &dparams->addr);
2959
2960         return (rc);
2961 }
2962
2963 static void
2964 update_nirq(struct intrs_and_queues *iaq, int nports)
2965 {
2966         int extra = T4_EXTRA_INTR;
2967
2968         iaq->nirq = extra;
2969         iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
2970         iaq->nirq += nports * (iaq->num_vis - 1) *
2971             max(iaq->nrxq_vi, iaq->nnmrxq_vi);
2972         iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
2973 }
2974
2975 /*
2976  * Adjust requirements to fit the number of interrupts available.
2977  */
2978 static void
2979 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
2980     int navail)
2981 {
2982         int old_nirq;
2983         const int nports = sc->params.nports;
2984
2985         MPASS(nports > 0);
2986         MPASS(navail > 0);
2987
2988         bzero(iaq, sizeof(*iaq));
2989         iaq->intr_type = itype;
2990         iaq->num_vis = t4_num_vis;
2991         iaq->ntxq = t4_ntxq;
2992         iaq->ntxq_vi = t4_ntxq_vi;
2993         iaq->nrxq = t4_nrxq;
2994         iaq->nrxq_vi = t4_nrxq_vi;
2995 #ifdef TCP_OFFLOAD
2996         if (is_offload(sc)) {
2997                 iaq->nofldtxq = t4_nofldtxq;
2998                 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2999                 iaq->nofldrxq = t4_nofldrxq;
3000                 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3001         }
3002 #endif
3003 #ifdef DEV_NETMAP
3004         iaq->nnmtxq_vi = t4_nnmtxq_vi;
3005         iaq->nnmrxq_vi = t4_nnmrxq_vi;
3006 #endif
3007
3008         update_nirq(iaq, nports);
3009         if (iaq->nirq <= navail &&
3010             (itype != INTR_MSI || powerof2(iaq->nirq))) {
3011                 /*
3012                  * This is the normal case -- there are enough interrupts for
3013                  * everything.
3014                  */
3015                 goto done;
3016         }
3017
3018         /*
3019          * If extra VIs have been configured try reducing their count and see if
3020          * that works.
3021          */
3022         while (iaq->num_vis > 1) {
3023                 iaq->num_vis--;
3024                 update_nirq(iaq, nports);
3025                 if (iaq->nirq <= navail &&
3026                     (itype != INTR_MSI || powerof2(iaq->nirq))) {
3027                         device_printf(sc->dev, "virtual interfaces per port "
3028                             "reduced to %d from %d.  nrxq=%u, nofldrxq=%u, "
3029                             "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u.  "
3030                             "itype %d, navail %u, nirq %d.\n",
3031                             iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3032                             iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3033                             itype, navail, iaq->nirq);
3034                         goto done;
3035                 }
3036         }
3037
3038         /*
3039          * Extra VIs will not be created.  Log a message if they were requested.
3040          */
3041         MPASS(iaq->num_vis == 1);
3042         iaq->ntxq_vi = iaq->nrxq_vi = 0;
3043         iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3044         iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3045         if (iaq->num_vis != t4_num_vis) {
3046                 device_printf(sc->dev, "extra virtual interfaces disabled.  "
3047                     "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3048                     "nnmrxq_vi=%u.  itype %d, navail %u, nirq %d.\n",
3049                     iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3050                     iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3051         }
3052
3053         /*
3054          * Keep reducing the number of NIC rx queues to the next lower power of
3055          * 2 (for even RSS distribution) and halving the TOE rx queues and see
3056          * if that works.
3057          */
3058         do {
3059                 if (iaq->nrxq > 1) {
3060                         do {
3061                                 iaq->nrxq--;
3062                         } while (!powerof2(iaq->nrxq));
3063                 }
3064                 if (iaq->nofldrxq > 1)
3065                         iaq->nofldrxq >>= 1;
3066
3067                 old_nirq = iaq->nirq;
3068                 update_nirq(iaq, nports);
3069                 if (iaq->nirq <= navail &&
3070                     (itype != INTR_MSI || powerof2(iaq->nirq))) {
3071                         device_printf(sc->dev, "running with reduced number of "
3072                             "rx queues because of shortage of interrupts.  "
3073                             "nrxq=%u, nofldrxq=%u.  "
3074                             "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3075                             iaq->nofldrxq, itype, navail, iaq->nirq);
3076                         goto done;
3077                 }
3078         } while (old_nirq != iaq->nirq);
3079
3080         /* One interrupt for everything.  Ugh. */
3081         device_printf(sc->dev, "running with minimal number of queues.  "
3082             "itype %d, navail %u.\n", itype, navail);
3083         iaq->nirq = 1;
3084         MPASS(iaq->nrxq == 1);
3085         iaq->ntxq = 1;
3086         if (iaq->nofldrxq > 1)
3087                 iaq->nofldtxq = 1;
3088 done:
3089         MPASS(iaq->num_vis > 0);
3090         if (iaq->num_vis > 1) {
3091                 MPASS(iaq->nrxq_vi > 0);
3092                 MPASS(iaq->ntxq_vi > 0);
3093         }
3094         MPASS(iaq->nirq > 0);
3095         MPASS(iaq->nrxq > 0);
3096         MPASS(iaq->ntxq > 0);
3097         if (itype == INTR_MSI) {
3098                 MPASS(powerof2(iaq->nirq));
3099         }
3100 }
3101
3102 static int
3103 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3104 {
3105         int rc, itype, navail, nalloc;
3106
3107         for (itype = INTR_MSIX; itype; itype >>= 1) {
3108
3109                 if ((itype & t4_intr_types) == 0)
3110                         continue;       /* not allowed */
3111
3112                 if (itype == INTR_MSIX)
3113                         navail = pci_msix_count(sc->dev);
3114                 else if (itype == INTR_MSI)
3115                         navail = pci_msi_count(sc->dev);
3116                 else
3117                         navail = 1;
3118 restart:
3119                 if (navail == 0)
3120                         continue;
3121
3122                 calculate_iaq(sc, iaq, itype, navail);
3123                 nalloc = iaq->nirq;
3124                 rc = 0;
3125                 if (itype == INTR_MSIX)
3126                         rc = pci_alloc_msix(sc->dev, &nalloc);
3127                 else if (itype == INTR_MSI)
3128                         rc = pci_alloc_msi(sc->dev, &nalloc);
3129
3130                 if (rc == 0 && nalloc > 0) {
3131                         if (nalloc == iaq->nirq)
3132                                 return (0);
3133
3134                         /*
3135                          * Didn't get the number requested.  Use whatever number
3136                          * the kernel is willing to allocate.
3137                          */
3138                         device_printf(sc->dev, "fewer vectors than requested, "
3139                             "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3140                             itype, iaq->nirq, nalloc);
3141                         pci_release_msi(sc->dev);
3142                         navail = nalloc;
3143                         goto restart;
3144                 }
3145
3146                 device_printf(sc->dev,
3147                     "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3148                     itype, rc, iaq->nirq, nalloc);
3149         }
3150
3151         device_printf(sc->dev,
3152             "failed to find a usable interrupt type.  "
3153             "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3154             pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3155
3156         return (ENXIO);
3157 }
3158
3159 #define FW_VERSION(chip) ( \
3160     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3161     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3162     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3163     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3164 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3165
3166 struct fw_info {
3167         uint8_t chip;
3168         char *kld_name;
3169         char *fw_mod_name;
3170         struct fw_hdr fw_hdr;   /* XXX: waste of space, need a sparse struct */
3171 } fw_info[] = {
3172         {
3173                 .chip = CHELSIO_T4,
3174                 .kld_name = "t4fw_cfg",
3175                 .fw_mod_name = "t4fw",
3176                 .fw_hdr = {
3177                         .chip = FW_HDR_CHIP_T4,
3178                         .fw_ver = htobe32(FW_VERSION(T4)),
3179                         .intfver_nic = FW_INTFVER(T4, NIC),
3180                         .intfver_vnic = FW_INTFVER(T4, VNIC),
3181                         .intfver_ofld = FW_INTFVER(T4, OFLD),
3182                         .intfver_ri = FW_INTFVER(T4, RI),
3183                         .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3184                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3185                         .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3186                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
3187                 },
3188         }, {
3189                 .chip = CHELSIO_T5,
3190                 .kld_name = "t5fw_cfg",
3191                 .fw_mod_name = "t5fw",
3192                 .fw_hdr = {
3193                         .chip = FW_HDR_CHIP_T5,
3194                         .fw_ver = htobe32(FW_VERSION(T5)),
3195                         .intfver_nic = FW_INTFVER(T5, NIC),
3196                         .intfver_vnic = FW_INTFVER(T5, VNIC),
3197                         .intfver_ofld = FW_INTFVER(T5, OFLD),
3198                         .intfver_ri = FW_INTFVER(T5, RI),
3199                         .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3200                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3201                         .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3202                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
3203                 },
3204         }, {
3205                 .chip = CHELSIO_T6,
3206                 .kld_name = "t6fw_cfg",
3207                 .fw_mod_name = "t6fw",
3208                 .fw_hdr = {
3209                         .chip = FW_HDR_CHIP_T6,
3210                         .fw_ver = htobe32(FW_VERSION(T6)),
3211                         .intfver_nic = FW_INTFVER(T6, NIC),
3212                         .intfver_vnic = FW_INTFVER(T6, VNIC),
3213                         .intfver_ofld = FW_INTFVER(T6, OFLD),
3214                         .intfver_ri = FW_INTFVER(T6, RI),
3215                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3216                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3217                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3218                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
3219                 },
3220         }
3221 };
3222
3223 static struct fw_info *
3224 find_fw_info(int chip)
3225 {
3226         int i;
3227
3228         for (i = 0; i < nitems(fw_info); i++) {
3229                 if (fw_info[i].chip == chip)
3230                         return (&fw_info[i]);
3231         }
3232         return (NULL);
3233 }
3234
3235 /*
3236  * Is the given firmware API compatible with the one the driver was compiled
3237  * with?
3238  */
3239 static int
3240 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3241 {
3242
3243         /* short circuit if it's the exact same firmware version */
3244         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3245                 return (1);
3246
3247         /*
3248          * XXX: Is this too conservative?  Perhaps I should limit this to the
3249          * features that are supported in the driver.
3250          */
3251 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3252         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3253             SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3254             SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3255                 return (1);
3256 #undef SAME_INTF
3257
3258         return (0);
3259 }
3260
3261 /*
3262  * The firmware in the KLD is usable, but should it be installed?  This routine
3263  * explains itself in detail if it indicates the KLD firmware should be
3264  * installed.
3265  */
3266 static int
3267 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
3268 {
3269         const char *reason;
3270
3271         if (!card_fw_usable) {
3272                 reason = "incompatible or unusable";
3273                 goto install;
3274         }
3275
3276         if (k > c) {
3277                 reason = "older than the version bundled with this driver";
3278                 goto install;
3279         }
3280
3281         if (t4_fw_install == 2 && k != c) {
3282                 reason = "different than the version bundled with this driver";
3283                 goto install;
3284         }
3285
3286         return (0);
3287
3288 install:
3289         if (t4_fw_install == 0) {
3290                 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3291                     "but the driver is prohibited from installing a different "
3292                     "firmware on the card.\n",
3293                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3294                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3295
3296                 return (0);
3297         }
3298
3299         device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3300             "installing firmware %u.%u.%u.%u on card.\n",
3301             G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3302             G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3303             G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3304             G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3305
3306         return (1);
3307 }
3308
3309 /*
3310  * Establish contact with the firmware and determine if we are the master driver
3311  * or not, and whether we are responsible for chip initialization.
3312  */
3313 static int
3314 prep_firmware(struct adapter *sc)
3315 {
3316         const struct firmware *fw = NULL, *default_cfg;
3317         int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
3318         enum dev_state state;
3319         struct fw_info *fw_info;
3320         struct fw_hdr *card_fw;         /* fw on the card */
3321         const struct fw_hdr *kld_fw;    /* fw in the KLD */
3322         const struct fw_hdr *drv_fw;    /* fw header the driver was compiled
3323                                            against */
3324
3325         /* This is the firmware whose headers the driver was compiled against */
3326         fw_info = find_fw_info(chip_id(sc));
3327         if (fw_info == NULL) {
3328                 device_printf(sc->dev,
3329                     "unable to look up firmware information for chip %d.\n",
3330                     chip_id(sc));
3331                 return (EINVAL);
3332         }
3333         drv_fw = &fw_info->fw_hdr;
3334
3335         /*
3336          * The firmware KLD contains many modules.  The KLD name is also the
3337          * name of the module that contains the default config file.
3338          */
3339         default_cfg = firmware_get(fw_info->kld_name);
3340
3341         /* This is the firmware in the KLD */
3342         fw = firmware_get(fw_info->fw_mod_name);
3343         if (fw != NULL) {
3344                 kld_fw = (const void *)fw->data;
3345                 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3346         } else {
3347                 kld_fw = NULL;
3348                 kld_fw_usable = 0;
3349         }
3350
3351         /* Read the header of the firmware on the card */
3352         card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3353         rc = -t4_read_flash(sc, FLASH_FW_START,
3354             sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3355         if (rc == 0) {
3356                 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3357                 if (card_fw->fw_ver == be32toh(0xffffffff)) {
3358                         uint32_t d = be32toh(kld_fw->fw_ver);
3359
3360                         if (!kld_fw_usable) {
3361                                 device_printf(sc->dev,
3362                                     "no firmware on the card and no usable "
3363                                     "firmware bundled with the driver.\n");
3364                                 rc = EIO;
3365                                 goto done;
3366                         } else if (t4_fw_install == 0) {
3367                                 device_printf(sc->dev,
3368                                     "no firmware on the card and the driver "
3369                                     "is prohibited from installing new "
3370                                     "firmware.\n");
3371                                 rc = EIO;
3372                                 goto done;
3373                         }
3374
3375                         device_printf(sc->dev, "no firmware on the card, "
3376                             "installing firmware %d.%d.%d.%d\n",
3377                             G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3378                             G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3379                         rc = t4_fw_forceinstall(sc, fw->data, fw->datasize);
3380                         if (rc < 0) {
3381                                 rc = -rc;
3382                                 device_printf(sc->dev,
3383                                     "firmware install failed: %d.\n", rc);
3384                                 goto done;
3385                         }
3386                         memcpy(card_fw, kld_fw, sizeof(*card_fw));
3387                         card_fw_usable = 1;
3388                         need_fw_reset = 0;
3389                 }
3390         } else {
3391                 device_printf(sc->dev,
3392                     "Unable to read card's firmware header: %d\n", rc);
3393                 card_fw_usable = 0;
3394         }
3395
3396         /* Contact firmware. */
3397         rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3398         if (rc < 0 || state == DEV_STATE_ERR) {
3399                 rc = -rc;
3400                 device_printf(sc->dev,
3401                     "failed to connect to the firmware: %d, %d.\n", rc, state);
3402                 goto done;
3403         }
3404         pf = rc;
3405         if (pf == sc->mbox)
3406                 sc->flags |= MASTER_PF;
3407         else if (state == DEV_STATE_UNINIT) {
3408                 /*
3409                  * We didn't get to be the master so we definitely won't be
3410                  * configuring the chip.  It's a bug if someone else hasn't
3411                  * configured it already.
3412                  */
3413                 device_printf(sc->dev, "couldn't be master(%d), "
3414                     "device not already initialized either(%d).\n", rc, state);
3415                 rc = EPROTO;
3416                 goto done;
3417         }
3418
3419         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3420             (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3421                 /*
3422                  * Common case: the firmware on the card is an exact match and
3423                  * the KLD is an exact match too, or the KLD is
3424                  * absent/incompatible.  Note that t4_fw_install = 2 is ignored
3425                  * here -- use cxgbetool loadfw if you want to reinstall the
3426                  * same firmware as the one on the card.
3427                  */
3428         } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3429             should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3430             be32toh(card_fw->fw_ver))) {
3431
3432                 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3433                 if (rc != 0) {
3434                         device_printf(sc->dev,
3435                             "failed to install firmware: %d\n", rc);
3436                         goto done;
3437                 }
3438
3439                 /* Installed successfully, update the cached header too. */
3440                 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3441                 card_fw_usable = 1;
3442                 need_fw_reset = 0;      /* already reset as part of load_fw */
3443         }
3444
3445         if (!card_fw_usable) {
3446                 uint32_t d, c, k;
3447
3448                 d = ntohl(drv_fw->fw_ver);
3449                 c = ntohl(card_fw->fw_ver);
3450                 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3451
3452                 device_printf(sc->dev, "Cannot find a usable firmware: "
3453                     "fw_install %d, chip state %d, "
3454                     "driver compiled with %d.%d.%d.%d, "
3455                     "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3456                     t4_fw_install, state,
3457                     G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3458                     G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3459                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3460                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3461                     G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3462                     G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3463                 rc = EINVAL;
3464                 goto done;
3465         }
3466
3467         /* Reset device */
3468         if (need_fw_reset &&
3469             (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3470                 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3471                 if (rc != ETIMEDOUT && rc != EIO)
3472                         t4_fw_bye(sc, sc->mbox);
3473                 goto done;
3474         }
3475         sc->flags |= FW_OK;
3476
3477         rc = get_params__pre_init(sc);
3478         if (rc != 0)
3479                 goto done; /* error message displayed already */
3480
3481         /* Partition adapter resources as specified in the config file. */
3482         if (state == DEV_STATE_UNINIT) {
3483
3484                 KASSERT(sc->flags & MASTER_PF,
3485                     ("%s: trying to change chip settings when not master.",
3486                     __func__));
3487
3488                 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3489                 if (rc != 0)
3490                         goto done;      /* error message displayed already */
3491
3492                 t4_tweak_chip_settings(sc);
3493
3494                 /* get basic stuff going */
3495                 rc = -t4_fw_initialize(sc, sc->mbox);
3496                 if (rc != 0) {
3497                         device_printf(sc->dev, "fw init failed: %d.\n", rc);
3498                         goto done;
3499                 }
3500         } else {
3501                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3502                 sc->cfcsum = 0;
3503         }
3504
3505 done:
3506         free(card_fw, M_CXGBE);
3507         if (fw != NULL)
3508                 firmware_put(fw, FIRMWARE_UNLOAD);
3509         if (default_cfg != NULL)
3510                 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3511
3512         return (rc);
3513 }
3514
3515 #define FW_PARAM_DEV(param) \
3516         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3517          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3518 #define FW_PARAM_PFVF(param) \
3519         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3520          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3521
3522 /*
3523  * Partition chip resources for use between various PFs, VFs, etc.
3524  */
3525 static int
3526 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3527     const char *name_prefix)
3528 {
3529         const struct firmware *cfg = NULL;
3530         int rc = 0;
3531         struct fw_caps_config_cmd caps;
3532         uint32_t mtype, moff, finicsum, cfcsum;
3533
3534         /*
3535          * Figure out what configuration file to use.  Pick the default config
3536          * file for the card if the user hasn't specified one explicitly.
3537          */
3538         snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3539         if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3540                 /* Card specific overrides go here. */
3541                 if (pci_get_device(sc->dev) == 0x440a)
3542                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3543                 if (is_fpga(sc))
3544                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3545         } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0)
3546                 goto use_built_in_config;       /* go straight to config. */
3547
3548         /*
3549          * We need to load another module if the profile is anything except
3550          * "default" or "flash".
3551          */
3552         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3553             strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3554                 char s[32];
3555
3556                 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3557                 cfg = firmware_get(s);
3558                 if (cfg == NULL) {
3559                         if (default_cfg != NULL) {
3560                                 device_printf(sc->dev,
3561                                     "unable to load module \"%s\" for "
3562                                     "configuration profile \"%s\", will use "
3563                                     "the default config file instead.\n",
3564                                     s, sc->cfg_file);
3565                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3566                                     "%s", DEFAULT_CF);
3567                         } else {
3568                                 device_printf(sc->dev,
3569                                     "unable to load module \"%s\" for "
3570                                     "configuration profile \"%s\", will use "
3571                                     "the config file on the card's flash "
3572                                     "instead.\n", s, sc->cfg_file);
3573                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3574                                     "%s", FLASH_CF);
3575                         }
3576                 }
3577         }
3578
3579         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3580             default_cfg == NULL) {
3581                 device_printf(sc->dev,
3582                     "default config file not available, will use the config "
3583                     "file on the card's flash instead.\n");
3584                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3585         }
3586
3587         if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3588                 u_int cflen;
3589                 const uint32_t *cfdata;
3590                 uint32_t param, val, addr;
3591
3592                 KASSERT(cfg != NULL || default_cfg != NULL,
3593                     ("%s: no config to upload", __func__));
3594
3595                 /*
3596                  * Ask the firmware where it wants us to upload the config file.
3597                  */
3598                 param = FW_PARAM_DEV(CF);
3599                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
3600                 if (rc != 0) {
3601                         /* No support for config file?  Shouldn't happen. */
3602                         device_printf(sc->dev,
3603                             "failed to query config file location: %d.\n", rc);
3604                         goto done;
3605                 }
3606                 mtype = G_FW_PARAMS_PARAM_Y(val);
3607                 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3608
3609                 /*
3610                  * XXX: sheer laziness.  We deliberately added 4 bytes of
3611                  * useless stuffing/comments at the end of the config file so
3612                  * it's ok to simply throw away the last remaining bytes when
3613                  * the config file is not an exact multiple of 4.  This also
3614                  * helps with the validate_mt_off_len check.
3615                  */
3616                 if (cfg != NULL) {
3617                         cflen = cfg->datasize & ~3;
3618                         cfdata = cfg->data;
3619                 } else {
3620                         cflen = default_cfg->datasize & ~3;
3621                         cfdata = default_cfg->data;
3622                 }
3623
3624                 if (cflen > FLASH_CFG_MAX_SIZE) {
3625                         device_printf(sc->dev,
3626                             "config file too long (%d, max allowed is %d).  "
3627                             "Will try to use the config on the card, if any.\n",
3628                             cflen, FLASH_CFG_MAX_SIZE);
3629                         goto use_config_on_flash;
3630                 }
3631
3632                 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3633                 if (rc != 0) {
3634                         device_printf(sc->dev,
3635                             "%s: addr (%d/0x%x) or len %d is not valid: %d.  "
3636                             "Will try to use the config on the card, if any.\n",
3637                             __func__, mtype, moff, cflen, rc);
3638                         goto use_config_on_flash;
3639                 }
3640                 write_via_memwin(sc, 2, addr, cfdata, cflen);
3641         } else {
3642 use_config_on_flash:
3643                 mtype = FW_MEMTYPE_FLASH;
3644                 moff = t4_flash_cfg_addr(sc);
3645         }
3646
3647         bzero(&caps, sizeof(caps));
3648         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3649             F_FW_CMD_REQUEST | F_FW_CMD_READ);
3650         caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3651             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3652             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3653         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3654         if (rc != 0) {
3655                 device_printf(sc->dev,
3656                     "failed to pre-process config file: %d "
3657                     "(mtype %d, moff 0x%x).  Will reset the firmware and retry "
3658                     "with the built-in configuration.\n", rc, mtype, moff);
3659
3660                 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3661                 if (rc != 0) {
3662                         device_printf(sc->dev,
3663                             "firmware reset failed: %d.\n", rc);
3664                         if (rc != ETIMEDOUT && rc != EIO) {
3665                                 t4_fw_bye(sc, sc->mbox);
3666                                 sc->flags &= ~FW_OK;
3667                         }
3668                         goto done;
3669                 }
3670                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in");
3671 use_built_in_config:
3672                 bzero(&caps, sizeof(caps));
3673                 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3674                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
3675                 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3676                 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3677                 if (rc != 0) {
3678                         device_printf(sc->dev,
3679                             "built-in configuration failed: %d.\n", rc);
3680                         goto done;
3681                 }
3682         }
3683
3684         finicsum = be32toh(caps.finicsum);
3685         cfcsum = be32toh(caps.cfcsum);
3686         if (finicsum != cfcsum) {
3687                 device_printf(sc->dev,
3688                     "WARNING: config file checksum mismatch: %08x %08x\n",
3689                     finicsum, cfcsum);
3690         }
3691         sc->cfcsum = cfcsum;
3692
3693 #define LIMIT_CAPS(x) do { \
3694         caps.x &= htobe16(t4_##x##_allowed); \
3695 } while (0)
3696
3697         /*
3698          * Let the firmware know what features will (not) be used so it can tune
3699          * things accordingly.
3700          */
3701         LIMIT_CAPS(nbmcaps);
3702         LIMIT_CAPS(linkcaps);
3703         LIMIT_CAPS(switchcaps);
3704         LIMIT_CAPS(niccaps);
3705         LIMIT_CAPS(toecaps);
3706         LIMIT_CAPS(rdmacaps);
3707         LIMIT_CAPS(cryptocaps);
3708         LIMIT_CAPS(iscsicaps);
3709         LIMIT_CAPS(fcoecaps);
3710 #undef LIMIT_CAPS
3711
3712         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3713             F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3714         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3715         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3716         if (rc != 0) {
3717                 device_printf(sc->dev,
3718                     "failed to process config file: %d.\n", rc);
3719         }
3720 done:
3721         if (cfg != NULL)
3722                 firmware_put(cfg, FIRMWARE_UNLOAD);
3723         return (rc);
3724 }
3725
3726 /*
3727  * Retrieve parameters that are needed (or nice to have) very early.
3728  */
3729 static int
3730 get_params__pre_init(struct adapter *sc)
3731 {
3732         int rc;
3733         uint32_t param[2], val[2];
3734
3735         t4_get_version_info(sc);
3736
3737         snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3738             G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3739             G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3740             G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3741             G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3742
3743         snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3744             G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3745             G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3746             G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3747             G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3748
3749         snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3750             G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3751             G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3752             G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3753             G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3754
3755         snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3756             G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3757             G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3758             G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3759             G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3760
3761         param[0] = FW_PARAM_DEV(PORTVEC);
3762         param[1] = FW_PARAM_DEV(CCLK);
3763         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3764         if (rc != 0) {
3765                 device_printf(sc->dev,
3766                     "failed to query parameters (pre_init): %d.\n", rc);
3767                 return (rc);
3768         }
3769
3770         sc->params.portvec = val[0];
3771         sc->params.nports = bitcount32(val[0]);
3772         sc->params.vpd.cclk = val[1];
3773
3774         /* Read device log parameters. */
3775         rc = -t4_init_devlog_params(sc, 1);
3776         if (rc == 0)
3777                 fixup_devlog_params(sc);
3778         else {
3779                 device_printf(sc->dev,
3780                     "failed to get devlog parameters: %d.\n", rc);
3781                 rc = 0; /* devlog isn't critical for device operation */
3782         }
3783
3784         return (rc);
3785 }
3786
3787 /*
3788  * Retrieve various parameters that are of interest to the driver.  The device
3789  * has been initialized by the firmware at this point.
3790  */
3791 static int
3792 get_params__post_init(struct adapter *sc)
3793 {
3794         int rc;
3795         uint32_t param[7], val[7];
3796         struct fw_caps_config_cmd caps;
3797
3798         param[0] = FW_PARAM_PFVF(IQFLINT_START);
3799         param[1] = FW_PARAM_PFVF(EQ_START);
3800         param[2] = FW_PARAM_PFVF(FILTER_START);
3801         param[3] = FW_PARAM_PFVF(FILTER_END);
3802         param[4] = FW_PARAM_PFVF(L2T_START);
3803         param[5] = FW_PARAM_PFVF(L2T_END);
3804         param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3805             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
3806             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
3807         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
3808         if (rc != 0) {
3809                 device_printf(sc->dev,
3810                     "failed to query parameters (post_init): %d.\n", rc);
3811                 return (rc);
3812         }
3813
3814         sc->sge.iq_start = val[0];
3815         sc->sge.eq_start = val[1];
3816         sc->tids.ftid_base = val[2];
3817         sc->tids.nftids = val[3] - val[2] + 1;
3818         sc->params.ftid_min = val[2];
3819         sc->params.ftid_max = val[3];
3820         sc->vres.l2t.start = val[4];
3821         sc->vres.l2t.size = val[5] - val[4] + 1;
3822         KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3823             ("%s: L2 table size (%u) larger than expected (%u)",
3824             __func__, sc->vres.l2t.size, L2T_SIZE));
3825         sc->params.core_vdd = val[6];
3826
3827         /*
3828          * MPSBGMAP is queried separately because only recent firmwares support
3829          * it as a parameter and we don't want the compound query above to fail
3830          * on older firmwares.
3831          */
3832         param[0] = FW_PARAM_DEV(MPSBGMAP);
3833         val[0] = 0;
3834         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3835         if (rc == 0)
3836                 sc->params.mps_bg_map = val[0];
3837         else
3838                 sc->params.mps_bg_map = 0;
3839
3840         /* get capabilites */
3841         bzero(&caps, sizeof(caps));
3842         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3843             F_FW_CMD_REQUEST | F_FW_CMD_READ);
3844         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3845         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3846         if (rc != 0) {
3847                 device_printf(sc->dev,
3848                     "failed to get card capabilities: %d.\n", rc);
3849                 return (rc);
3850         }
3851
3852 #define READ_CAPS(x) do { \
3853         sc->x = htobe16(caps.x); \
3854 } while (0)
3855         READ_CAPS(nbmcaps);
3856         READ_CAPS(linkcaps);
3857         READ_CAPS(switchcaps);
3858         READ_CAPS(niccaps);
3859         READ_CAPS(toecaps);
3860         READ_CAPS(rdmacaps);
3861         READ_CAPS(cryptocaps);
3862         READ_CAPS(iscsicaps);
3863         READ_CAPS(fcoecaps);
3864
3865         /*
3866          * The firmware attempts memfree TOE configuration for -SO cards and
3867          * will report toecaps=0 if it runs out of resources (this depends on
3868          * the config file).  It may not report 0 for other capabilities
3869          * dependent on the TOE in this case.  Set them to 0 here so that the
3870          * driver doesn't bother tracking resources that will never be used.
3871          */
3872         if (sc->toecaps == 0) {
3873                 sc->iscsicaps = 0;
3874                 sc->rdmacaps = 0;
3875         }
3876
3877         if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3878                 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3879                 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3880                 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3881                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3882                 if (rc != 0) {
3883                         device_printf(sc->dev,
3884                             "failed to query NIC parameters: %d.\n", rc);
3885                         return (rc);
3886                 }
3887                 sc->tids.etid_base = val[0];
3888                 sc->params.etid_min = val[0];
3889                 sc->tids.netids = val[1] - val[0] + 1;
3890                 sc->params.netids = sc->tids.netids;
3891                 sc->params.eo_wr_cred = val[2];
3892                 sc->params.ethoffload = 1;
3893         }
3894
3895         if (sc->toecaps) {
3896                 /* query offload-related parameters */
3897                 param[0] = FW_PARAM_DEV(NTID);
3898                 param[1] = FW_PARAM_PFVF(SERVER_START);
3899                 param[2] = FW_PARAM_PFVF(SERVER_END);
3900                 param[3] = FW_PARAM_PFVF(TDDP_START);
3901                 param[4] = FW_PARAM_PFVF(TDDP_END);
3902                 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3903                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3904                 if (rc != 0) {
3905                         device_printf(sc->dev,
3906                             "failed to query TOE parameters: %d.\n", rc);
3907                         return (rc);
3908                 }
3909                 sc->tids.ntids = val[0];
3910                 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3911                 sc->tids.stid_base = val[1];
3912                 sc->tids.nstids = val[2] - val[1] + 1;
3913                 sc->vres.ddp.start = val[3];
3914                 sc->vres.ddp.size = val[4] - val[3] + 1;
3915                 sc->params.ofldq_wr_cred = val[5];
3916                 sc->params.offload = 1;
3917         }
3918         if (sc->rdmacaps) {
3919                 param[0] = FW_PARAM_PFVF(STAG_START);
3920                 param[1] = FW_PARAM_PFVF(STAG_END);
3921                 param[2] = FW_PARAM_PFVF(RQ_START);
3922                 param[3] = FW_PARAM_PFVF(RQ_END);
3923                 param[4] = FW_PARAM_PFVF(PBL_START);
3924                 param[5] = FW_PARAM_PFVF(PBL_END);
3925                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3926                 if (rc != 0) {
3927                         device_printf(sc->dev,
3928                             "failed to query RDMA parameters(1): %d.\n", rc);
3929                         return (rc);
3930                 }
3931                 sc->vres.stag.start = val[0];
3932                 sc->vres.stag.size = val[1] - val[0] + 1;
3933                 sc->vres.rq.start = val[2];
3934                 sc->vres.rq.size = val[3] - val[2] + 1;
3935                 sc->vres.pbl.start = val[4];
3936                 sc->vres.pbl.size = val[5] - val[4] + 1;
3937
3938                 param[0] = FW_PARAM_PFVF(SQRQ_START);
3939                 param[1] = FW_PARAM_PFVF(SQRQ_END);
3940                 param[2] = FW_PARAM_PFVF(CQ_START);
3941                 param[3] = FW_PARAM_PFVF(CQ_END);
3942                 param[4] = FW_PARAM_PFVF(OCQ_START);
3943                 param[5] = FW_PARAM_PFVF(OCQ_END);
3944                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3945                 if (rc != 0) {
3946                         device_printf(sc->dev,
3947                             "failed to query RDMA parameters(2): %d.\n", rc);
3948                         return (rc);
3949                 }
3950                 sc->vres.qp.start = val[0];
3951                 sc->vres.qp.size = val[1] - val[0] + 1;
3952                 sc->vres.cq.start = val[2];
3953                 sc->vres.cq.size = val[3] - val[2] + 1;
3954                 sc->vres.ocq.start = val[4];
3955                 sc->vres.ocq.size = val[5] - val[4] + 1;
3956
3957                 param[0] = FW_PARAM_PFVF(SRQ_START);
3958                 param[1] = FW_PARAM_PFVF(SRQ_END);
3959                 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
3960                 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3961                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
3962                 if (rc != 0) {
3963                         device_printf(sc->dev,
3964                             "failed to query RDMA parameters(3): %d.\n", rc);
3965                         return (rc);
3966                 }
3967                 sc->vres.srq.start = val[0];
3968                 sc->vres.srq.size = val[1] - val[0] + 1;
3969                 sc->params.max_ordird_qp = val[2];
3970                 sc->params.max_ird_adapter = val[3];
3971         }
3972         if (sc->iscsicaps) {
3973                 param[0] = FW_PARAM_PFVF(ISCSI_START);
3974                 param[1] = FW_PARAM_PFVF(ISCSI_END);
3975                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3976                 if (rc != 0) {
3977                         device_printf(sc->dev,
3978                             "failed to query iSCSI parameters: %d.\n", rc);
3979                         return (rc);
3980                 }
3981                 sc->vres.iscsi.start = val[0];
3982                 sc->vres.iscsi.size = val[1] - val[0] + 1;
3983         }
3984
3985         t4_init_sge_params(sc);
3986
3987         /*
3988          * We've got the params we wanted to query via the firmware.  Now grab
3989          * some others directly from the chip.
3990          */
3991         rc = t4_read_chip_settings(sc);
3992
3993         return (rc);
3994 }
3995
3996 static int
3997 set_params__post_init(struct adapter *sc)
3998 {
3999         uint32_t param, val;
4000 #ifdef TCP_OFFLOAD
4001         int i, v, shift;
4002 #endif
4003
4004         /* ask for encapsulated CPLs */
4005         param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4006         val = 1;
4007         (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
4008
4009         /* Enable 32b port caps if the firmware supports it. */
4010         param = FW_PARAM_PFVF(PORT_CAPS32);
4011         val = 1;
4012         if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val) == 0)
4013                 sc->params.port_caps32 = 1;
4014
4015 #ifdef TCP_OFFLOAD
4016         /*
4017          * Override the TOE timers with user provided tunables.  This is not the
4018          * recommended way to change the timers (the firmware config file is) so
4019          * these tunables are not documented.
4020          *
4021          * All the timer tunables are in microseconds.
4022          */
4023         if (t4_toe_keepalive_idle != 0) {
4024                 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4025                 v &= M_KEEPALIVEIDLE;
4026                 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4027                     V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4028         }
4029         if (t4_toe_keepalive_interval != 0) {
4030                 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4031                 v &= M_KEEPALIVEINTVL;
4032                 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4033                     V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4034         }
4035         if (t4_toe_keepalive_count != 0) {
4036                 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4037                 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4038                     V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4039                     V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4040                     V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4041         }
4042         if (t4_toe_rexmt_min != 0) {
4043                 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4044                 v &= M_RXTMIN;
4045                 t4_set_reg_field(sc, A_TP_RXT_MIN,
4046                     V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4047         }
4048         if (t4_toe_rexmt_max != 0) {
4049                 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4050                 v &= M_RXTMAX;
4051                 t4_set_reg_field(sc, A_TP_RXT_MAX,
4052                     V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4053         }
4054         if (t4_toe_rexmt_count != 0) {
4055                 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4056                 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4057                     V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4058                     V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4059                     V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4060         }
4061         for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4062                 if (t4_toe_rexmt_backoff[i] != -1) {
4063                         v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4064                         shift = (i & 3) << 3;
4065                         t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4066                             M_TIMERBACKOFFINDEX0 << shift, v << shift);
4067                 }
4068         }
4069 #endif
4070         return (0);
4071 }
4072
4073 #undef FW_PARAM_PFVF
4074 #undef FW_PARAM_DEV
4075
4076 static void
4077 t4_set_desc(struct adapter *sc)
4078 {
4079         char buf[128];
4080         struct adapter_params *p = &sc->params;
4081
4082         snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4083
4084         device_set_desc_copy(sc->dev, buf);
4085 }
4086
4087 static inline void
4088 ifmedia_add4(struct ifmedia *ifm, int m)
4089 {
4090
4091         ifmedia_add(ifm, m, 0, NULL);
4092         ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4093         ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4094         ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4095 }
4096
4097 /*
4098  * This is the selected media, which is not quite the same as the active media.
4099  * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4100  * and active are not the same, and "media: Ethernet selected" otherwise.
4101  */
4102 static void
4103 set_current_media(struct port_info *pi)
4104 {
4105         struct link_config *lc;
4106         struct ifmedia *ifm;
4107         int mword;
4108         u_int speed;
4109
4110         PORT_LOCK_ASSERT_OWNED(pi);
4111
4112         /* Leave current media alone if it's already set to IFM_NONE. */
4113         ifm = &pi->media;
4114         if (ifm->ifm_cur != NULL &&
4115             IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4116                 return;
4117
4118         lc = &pi->link_cfg;
4119         if (lc->requested_aneg != AUTONEG_DISABLE &&
4120             lc->supported & FW_PORT_CAP32_ANEG) {
4121                 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4122                 return;
4123         }
4124         mword = IFM_ETHER | IFM_FDX;
4125         if (lc->requested_fc & PAUSE_TX)
4126                 mword |= IFM_ETH_TXPAUSE;
4127         if (lc->requested_fc & PAUSE_RX)
4128                 mword |= IFM_ETH_RXPAUSE;
4129         if (lc->requested_speed == 0)
4130                 speed = port_top_speed(pi) * 1000;      /* Gbps -> Mbps */
4131         else
4132                 speed = lc->requested_speed;
4133         mword |= port_mword(pi, speed_to_fwcap(speed));
4134         ifmedia_set(ifm, mword);
4135 }
4136
4137 /*
4138  * Returns true if the ifmedia list for the port cannot change.
4139  */
4140 static bool
4141 fixed_ifmedia(struct port_info *pi)
4142 {
4143
4144         return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4145             pi->port_type == FW_PORT_TYPE_BT_XFI ||
4146             pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4147             pi->port_type == FW_PORT_TYPE_KX4 ||
4148             pi->port_type == FW_PORT_TYPE_KX ||
4149             pi->port_type == FW_PORT_TYPE_KR ||
4150             pi->port_type == FW_PORT_TYPE_BP_AP ||
4151             pi->port_type == FW_PORT_TYPE_BP4_AP ||
4152             pi->port_type == FW_PORT_TYPE_BP40_BA ||
4153             pi->port_type == FW_PORT_TYPE_KR4_100G ||
4154             pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4155             pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4156 }
4157
4158 static void
4159 build_medialist(struct port_info *pi)
4160 {
4161         uint32_t ss, speed;
4162         int unknown, mword, bit;
4163         struct link_config *lc;
4164         struct ifmedia *ifm;
4165
4166         PORT_LOCK_ASSERT_OWNED(pi);
4167
4168         if (pi->flags & FIXED_IFMEDIA)
4169                 return;
4170
4171         /*
4172          * Rebuild the ifmedia list.
4173          */
4174         ifm = &pi->media;
4175         ifmedia_removeall(ifm);
4176         lc = &pi->link_cfg;
4177         ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4178         if (__predict_false(ss == 0)) { /* not supposed to happen. */
4179                 MPASS(ss != 0);
4180 no_media:
4181                 MPASS(LIST_EMPTY(&ifm->ifm_list));
4182                 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4183                 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4184                 return;
4185         }
4186
4187         unknown = 0;
4188         for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4189                 speed = 1 << bit;
4190                 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4191                 if (ss & speed) {
4192                         mword = port_mword(pi, speed);
4193                         if (mword == IFM_NONE) {
4194                                 goto no_media;
4195                         } else if (mword == IFM_UNKNOWN)
4196                                 unknown++;
4197                         else
4198                                 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4199                 }
4200         }
4201         if (unknown > 0) /* Add one unknown for all unknown media types. */
4202                 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4203         if (lc->supported & FW_PORT_CAP32_ANEG)
4204                 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4205
4206         set_current_media(pi);
4207 }
4208
4209 /*
4210  * Initialize the requested fields in the link config based on driver tunables.
4211  */
4212 static void
4213 init_link_config(struct port_info *pi)
4214 {
4215         struct link_config *lc = &pi->link_cfg;
4216
4217         PORT_LOCK_ASSERT_OWNED(pi);
4218
4219         lc->requested_speed = 0;
4220
4221         if (t4_autoneg == 0)
4222                 lc->requested_aneg = AUTONEG_DISABLE;
4223         else if (t4_autoneg == 1)
4224                 lc->requested_aneg = AUTONEG_ENABLE;
4225         else
4226                 lc->requested_aneg = AUTONEG_AUTO;
4227
4228         lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4229             PAUSE_AUTONEG);
4230
4231         if (t4_fec == -1 || t4_fec & FEC_AUTO)
4232                 lc->requested_fec = FEC_AUTO;
4233         else {
4234                 lc->requested_fec = FEC_NONE;
4235                 if (t4_fec & FEC_RS)
4236                         lc->requested_fec |= FEC_RS;
4237                 if (t4_fec & FEC_BASER_RS)
4238                         lc->requested_fec |= FEC_BASER_RS;
4239         }
4240 }
4241
4242 /*
4243  * Makes sure that all requested settings comply with what's supported by the
4244  * port.  Returns the number of settings that were invalid and had to be fixed.
4245  */
4246 static int
4247 fixup_link_config(struct port_info *pi)
4248 {
4249         int n = 0;
4250         struct link_config *lc = &pi->link_cfg;
4251         uint32_t fwspeed;
4252
4253         PORT_LOCK_ASSERT_OWNED(pi);
4254
4255         /* Speed (when not autonegotiating) */
4256         if (lc->requested_speed != 0) {
4257                 fwspeed = speed_to_fwcap(lc->requested_speed);
4258                 if ((fwspeed & lc->supported) == 0) {
4259                         n++;
4260                         lc->requested_speed = 0;
4261                 }
4262         }
4263
4264         /* Link autonegotiation */
4265         MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4266             lc->requested_aneg == AUTONEG_DISABLE ||
4267             lc->requested_aneg == AUTONEG_AUTO);
4268         if (lc->requested_aneg == AUTONEG_ENABLE &&
4269             !(lc->supported & FW_PORT_CAP32_ANEG)) {
4270                 n++;
4271                 lc->requested_aneg = AUTONEG_AUTO;
4272         }
4273
4274         /* Flow control */
4275         MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4276         if (lc->requested_fc & PAUSE_TX &&
4277             !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4278                 n++;
4279                 lc->requested_fc &= ~PAUSE_TX;
4280         }
4281         if (lc->requested_fc & PAUSE_RX &&
4282             !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4283                 n++;
4284                 lc->requested_fc &= ~PAUSE_RX;
4285         }
4286         if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4287             !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4288                 n++;
4289                 lc->requested_fc |= PAUSE_AUTONEG;
4290         }
4291
4292         /* FEC */
4293         if ((lc->requested_fec & FEC_RS &&
4294             !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4295             (lc->requested_fec & FEC_BASER_RS &&
4296             !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4297                 n++;
4298                 lc->requested_fec = FEC_AUTO;
4299         }
4300
4301         return (n);
4302 }
4303
4304 /*
4305  * Apply the requested L1 settings, which are expected to be valid, to the
4306  * hardware.
4307  */
4308 static int
4309 apply_link_config(struct port_info *pi)
4310 {
4311         struct adapter *sc = pi->adapter;
4312         struct link_config *lc = &pi->link_cfg;
4313         int rc;
4314
4315 #ifdef INVARIANTS
4316         ASSERT_SYNCHRONIZED_OP(sc);
4317         PORT_LOCK_ASSERT_OWNED(pi);
4318
4319         if (lc->requested_aneg == AUTONEG_ENABLE)
4320                 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4321         if (!(lc->requested_fc & PAUSE_AUTONEG))
4322                 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4323         if (lc->requested_fc & PAUSE_TX)
4324                 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4325         if (lc->requested_fc & PAUSE_RX)
4326                 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4327         if (lc->requested_fec & FEC_RS)
4328                 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4329         if (lc->requested_fec & FEC_BASER_RS)
4330                 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4331 #endif
4332         rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4333         if (rc != 0) {
4334                 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4335         } else {
4336                 /*
4337                  * An L1_CFG will almost always result in a link-change event if
4338                  * the link is up, and the driver will refresh the actual
4339                  * fec/fc/etc. when the notification is processed.  If the link
4340                  * is down then the actual settings are meaningless.
4341                  *
4342                  * This takes care of the case where a change in the L1 settings
4343                  * may not result in a notification.
4344                  */
4345                 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4346                         lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4347         }
4348         return (rc);
4349 }
4350
4351 #define FW_MAC_EXACT_CHUNK      7
4352
4353 /*
4354  * Program the port's XGMAC based on parameters in ifnet.  The caller also
4355  * indicates which parameters should be programmed (the rest are left alone).
4356  */
4357 int
4358 update_mac_settings(struct ifnet *ifp, int flags)
4359 {
4360         int rc = 0;
4361         struct vi_info *vi = ifp->if_softc;
4362         struct port_info *pi = vi->pi;
4363         struct adapter *sc = pi->adapter;
4364         int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4365
4366         ASSERT_SYNCHRONIZED_OP(sc);
4367         KASSERT(flags, ("%s: not told what to update.", __func__));
4368
4369         if (flags & XGMAC_MTU)
4370                 mtu = ifp->if_mtu;
4371
4372         if (flags & XGMAC_PROMISC)
4373                 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4374
4375         if (flags & XGMAC_ALLMULTI)
4376                 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4377
4378         if (flags & XGMAC_VLANEX)
4379                 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4380
4381         if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4382                 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4383                     allmulti, 1, vlanex, false);
4384                 if (rc) {
4385                         if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4386                             rc);
4387                         return (rc);
4388                 }
4389         }
4390
4391         if (flags & XGMAC_UCADDR) {
4392                 uint8_t ucaddr[ETHER_ADDR_LEN];
4393
4394                 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4395                 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4396                     ucaddr, true, true);
4397                 if (rc < 0) {
4398                         rc = -rc;
4399                         if_printf(ifp, "change_mac failed: %d\n", rc);
4400                         return (rc);
4401                 } else {
4402                         vi->xact_addr_filt = rc;
4403                         rc = 0;
4404                 }
4405         }
4406
4407         if (flags & XGMAC_MCADDRS) {
4408                 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4409                 int del = 1;
4410                 uint64_t hash = 0;
4411                 struct ifmultiaddr *ifma;
4412                 int i = 0, j;
4413
4414                 if_maddr_rlock(ifp);
4415                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4416                         if (ifma->ifma_addr->sa_family != AF_LINK)
4417                                 continue;
4418                         mcaddr[i] =
4419                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4420                         MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4421                         i++;
4422
4423                         if (i == FW_MAC_EXACT_CHUNK) {
4424                                 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4425                                     del, i, mcaddr, NULL, &hash, 0);
4426                                 if (rc < 0) {
4427                                         rc = -rc;
4428                                         for (j = 0; j < i; j++) {
4429                                                 if_printf(ifp,
4430                                                     "failed to add mc address"
4431                                                     " %02x:%02x:%02x:"
4432                                                     "%02x:%02x:%02x rc=%d\n",
4433                                                     mcaddr[j][0], mcaddr[j][1],
4434                                                     mcaddr[j][2], mcaddr[j][3],
4435                                                     mcaddr[j][4], mcaddr[j][5],
4436                                                     rc);
4437                                         }
4438                                         goto mcfail;
4439                                 }
4440                                 del = 0;
4441                                 i = 0;
4442                         }
4443                 }
4444                 if (i > 0) {
4445                         rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4446                             mcaddr, NULL, &hash, 0);
4447                         if (rc < 0) {
4448                                 rc = -rc;
4449                                 for (j = 0; j < i; j++) {
4450                                         if_printf(ifp,
4451                                             "failed to add mc address"
4452                                             " %02x:%02x:%02x:"
4453                                             "%02x:%02x:%02x rc=%d\n",
4454                                             mcaddr[j][0], mcaddr[j][1],
4455                                             mcaddr[j][2], mcaddr[j][3],
4456                                             mcaddr[j][4], mcaddr[j][5],
4457                                             rc);
4458                                 }
4459                                 goto mcfail;
4460                         }
4461                 }
4462
4463                 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4464                 if (rc != 0)
4465                         if_printf(ifp, "failed to set mc address hash: %d", rc);
4466 mcfail:
4467                 if_maddr_runlock(ifp);
4468         }
4469
4470         return (rc);
4471 }
4472
4473 /*
4474  * {begin|end}_synchronized_op must be called from the same thread.
4475  */
4476 int
4477 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4478     char *wmesg)
4479 {
4480         int rc, pri;
4481
4482 #ifdef WITNESS
4483         /* the caller thinks it's ok to sleep, but is it really? */
4484         if (flags & SLEEP_OK)
4485                 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4486                     "begin_synchronized_op");
4487 #endif
4488
4489         if (INTR_OK)
4490                 pri = PCATCH;
4491         else
4492                 pri = 0;
4493
4494         ADAPTER_LOCK(sc);
4495         for (;;) {
4496
4497                 if (vi && IS_DOOMED(vi)) {
4498                         rc = ENXIO;
4499                         goto done;
4500                 }
4501
4502                 if (!IS_BUSY(sc)) {
4503                         rc = 0;
4504                         break;
4505                 }
4506
4507                 if (!(flags & SLEEP_OK)) {
4508                         rc = EBUSY;
4509                         goto done;
4510                 }
4511
4512                 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4513                         rc = EINTR;
4514                         goto done;
4515                 }
4516         }
4517
4518         KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4519         SET_BUSY(sc);
4520 #ifdef INVARIANTS
4521         sc->last_op = wmesg;
4522         sc->last_op_thr = curthread;
4523         sc->last_op_flags = flags;
4524 #endif
4525
4526 done:
4527         if (!(flags & HOLD_LOCK) || rc)
4528                 ADAPTER_UNLOCK(sc);
4529
4530         return (rc);
4531 }
4532
4533 /*
4534  * Tell if_ioctl and if_init that the VI is going away.  This is
4535  * special variant of begin_synchronized_op and must be paired with a
4536  * call to end_synchronized_op.
4537  */
4538 void
4539 doom_vi(struct adapter *sc, struct vi_info *vi)
4540 {
4541
4542         ADAPTER_LOCK(sc);
4543         SET_DOOMED(vi);
4544         wakeup(&sc->flags);
4545         while (IS_BUSY(sc))
4546                 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4547         SET_BUSY(sc);
4548 #ifdef INVARIANTS
4549         sc->last_op = "t4detach";
4550         sc->last_op_thr = curthread;
4551         sc->last_op_flags = 0;
4552 #endif
4553         ADAPTER_UNLOCK(sc);
4554 }
4555
4556 /*
4557  * {begin|end}_synchronized_op must be called from the same thread.
4558  */
4559 void
4560 end_synchronized_op(struct adapter *sc, int flags)
4561 {
4562
4563         if (flags & LOCK_HELD)
4564                 ADAPTER_LOCK_ASSERT_OWNED(sc);
4565         else
4566                 ADAPTER_LOCK(sc);
4567
4568         KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4569         CLR_BUSY(sc);
4570         wakeup(&sc->flags);
4571         ADAPTER_UNLOCK(sc);
4572 }
4573
4574 static int
4575 cxgbe_init_synchronized(struct vi_info *vi)
4576 {
4577         struct port_info *pi = vi->pi;
4578         struct adapter *sc = pi->adapter;
4579         struct ifnet *ifp = vi->ifp;
4580         int rc = 0, i;
4581         struct sge_txq *txq;
4582
4583         ASSERT_SYNCHRONIZED_OP(sc);
4584
4585         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4586                 return (0);     /* already running */
4587
4588         if (!(sc->flags & FULL_INIT_DONE) &&
4589             ((rc = adapter_full_init(sc)) != 0))
4590                 return (rc);    /* error message displayed already */
4591
4592         if (!(vi->flags & VI_INIT_DONE) &&
4593             ((rc = vi_full_init(vi)) != 0))
4594                 return (rc); /* error message displayed already */
4595
4596         rc = update_mac_settings(ifp, XGMAC_ALL);
4597         if (rc)
4598                 goto done;      /* error message displayed already */
4599
4600         PORT_LOCK(pi);
4601         if (pi->up_vis == 0) {
4602                 t4_update_port_info(pi);
4603                 fixup_link_config(pi);
4604                 build_medialist(pi);
4605                 apply_link_config(pi);
4606         }
4607
4608         rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4609         if (rc != 0) {
4610                 if_printf(ifp, "enable_vi failed: %d\n", rc);
4611                 PORT_UNLOCK(pi);
4612                 goto done;
4613         }
4614
4615         /*
4616          * Can't fail from this point onwards.  Review cxgbe_uninit_synchronized
4617          * if this changes.
4618          */
4619
4620         for_each_txq(vi, i, txq) {
4621                 TXQ_LOCK(txq);
4622                 txq->eq.flags |= EQ_ENABLED;
4623                 TXQ_UNLOCK(txq);
4624         }
4625
4626         /*
4627          * The first iq of the first port to come up is used for tracing.
4628          */
4629         if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4630                 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4631                 t4_write_reg(sc, is_t4(sc) ?  A_MPS_TRC_RSS_CONTROL :
4632                     A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4633                     V_QUEUENUMBER(sc->traceq));
4634                 pi->flags |= HAS_TRACEQ;
4635         }
4636
4637         /* all ok */
4638         pi->up_vis++;
4639         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4640
4641         if (pi->nvi > 1 || sc->flags & IS_VF)
4642                 callout_reset(&vi->tick, hz, vi_tick, vi);
4643         else
4644                 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4645         PORT_UNLOCK(pi);
4646 done:
4647         if (rc != 0)
4648                 cxgbe_uninit_synchronized(vi);
4649
4650         return (rc);
4651 }
4652
4653 /*
4654  * Idempotent.
4655  */
4656 static int
4657 cxgbe_uninit_synchronized(struct vi_info *vi)
4658 {
4659         struct port_info *pi = vi->pi;
4660         struct adapter *sc = pi->adapter;
4661         struct ifnet *ifp = vi->ifp;
4662         int rc, i;
4663         struct sge_txq *txq;
4664
4665         ASSERT_SYNCHRONIZED_OP(sc);
4666
4667         if (!(vi->flags & VI_INIT_DONE)) {
4668                 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4669                         KASSERT(0, ("uninited VI is running"));
4670                         if_printf(ifp, "uninited VI with running ifnet.  "
4671                             "vi->flags 0x%016lx, if_flags 0x%08x, "
4672                             "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
4673                             ifp->if_drv_flags);
4674                 }
4675                 return (0);
4676         }
4677
4678         /*
4679          * Disable the VI so that all its data in either direction is discarded
4680          * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
4681          * tick) intact as the TP can deliver negative advice or data that it's
4682          * holding in its RAM (for an offloaded connection) even after the VI is
4683          * disabled.
4684          */
4685         rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4686         if (rc) {
4687                 if_printf(ifp, "disable_vi failed: %d\n", rc);
4688                 return (rc);
4689         }
4690
4691         for_each_txq(vi, i, txq) {
4692                 TXQ_LOCK(txq);
4693                 txq->eq.flags &= ~EQ_ENABLED;
4694                 TXQ_UNLOCK(txq);
4695         }
4696
4697         PORT_LOCK(pi);
4698         if (pi->nvi > 1 || sc->flags & IS_VF)
4699                 callout_stop(&vi->tick);
4700         else
4701                 callout_stop(&pi->tick);
4702         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4703                 PORT_UNLOCK(pi);
4704                 return (0);
4705         }
4706         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4707         pi->up_vis--;
4708         if (pi->up_vis > 0) {
4709                 PORT_UNLOCK(pi);
4710                 return (0);
4711         }
4712
4713         pi->link_cfg.link_ok = false;
4714         pi->link_cfg.speed = 0;
4715         pi->link_cfg.link_down_rc = 255;
4716         t4_os_link_changed(pi);
4717         PORT_UNLOCK(pi);
4718
4719         return (0);
4720 }
4721
4722 /*
4723  * It is ok for this function to fail midway and return right away.  t4_detach
4724  * will walk the entire sc->irq list and clean up whatever is valid.
4725  */
4726 int
4727 t4_setup_intr_handlers(struct adapter *sc)
4728 {
4729         int rc, rid, p, q, v;
4730         char s[8];
4731         struct irq *irq;
4732         struct port_info *pi;
4733         struct vi_info *vi;
4734         struct sge *sge = &sc->sge;
4735         struct sge_rxq *rxq;
4736 #ifdef TCP_OFFLOAD
4737         struct sge_ofld_rxq *ofld_rxq;
4738 #endif
4739 #ifdef DEV_NETMAP
4740         struct sge_nm_rxq *nm_rxq;
4741 #endif
4742 #ifdef RSS
4743         int nbuckets = rss_getnumbuckets();
4744 #endif
4745
4746         /*
4747          * Setup interrupts.
4748          */
4749         irq = &sc->irq[0];
4750         rid = sc->intr_type == INTR_INTX ? 0 : 1;
4751         if (forwarding_intr_to_fwq(sc))
4752                 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4753
4754         /* Multiple interrupts. */
4755         if (sc->flags & IS_VF)
4756                 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4757                     ("%s: too few intr.", __func__));
4758         else
4759                 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4760                     ("%s: too few intr.", __func__));
4761
4762         /* The first one is always error intr on PFs */
4763         if (!(sc->flags & IS_VF)) {
4764                 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4765                 if (rc != 0)
4766                         return (rc);
4767                 irq++;
4768                 rid++;
4769         }
4770
4771         /* The second one is always the firmware event queue (first on VFs) */
4772         rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4773         if (rc != 0)
4774                 return (rc);
4775         irq++;
4776         rid++;
4777
4778         for_each_port(sc, p) {
4779                 pi = sc->port[p];
4780                 for_each_vi(pi, v, vi) {
4781                         vi->first_intr = rid - 1;
4782
4783                         if (vi->nnmrxq > 0) {
4784                                 int n = max(vi->nrxq, vi->nnmrxq);
4785
4786                                 rxq = &sge->rxq[vi->first_rxq];
4787 #ifdef DEV_NETMAP
4788                                 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4789 #endif
4790                                 for (q = 0; q < n; q++) {
4791                                         snprintf(s, sizeof(s), "%x%c%x", p,
4792                                             'a' + v, q);
4793                                         if (q < vi->nrxq)
4794                                                 irq->rxq = rxq++;
4795 #ifdef DEV_NETMAP
4796                                         if (q < vi->nnmrxq)
4797                                                 irq->nm_rxq = nm_rxq++;
4798 #endif
4799                                         rc = t4_alloc_irq(sc, irq, rid,
4800                                             t4_vi_intr, irq, s);
4801                                         if (rc != 0)
4802                                                 return (rc);
4803 #ifdef RSS
4804                                         if (q < vi->nrxq) {
4805                                                 bus_bind_intr(sc->dev, irq->res,
4806                                                     rss_getcpu(q % nbuckets));
4807                                         }
4808 #endif
4809                                         irq++;
4810                                         rid++;
4811                                         vi->nintr++;
4812                                 }
4813                         } else {
4814                                 for_each_rxq(vi, q, rxq) {
4815                                         snprintf(s, sizeof(s), "%x%c%x", p,
4816                                             'a' + v, q);
4817                                         rc = t4_alloc_irq(sc, irq, rid,
4818                                             t4_intr, rxq, s);
4819                                         if (rc != 0)
4820                                                 return (rc);
4821 #ifdef RSS
4822                                         bus_bind_intr(sc->dev, irq->res,
4823                                             rss_getcpu(q % nbuckets));
4824 #endif
4825                                         irq++;
4826                                         rid++;
4827                                         vi->nintr++;
4828                                 }
4829                         }
4830 #ifdef TCP_OFFLOAD
4831                         for_each_ofld_rxq(vi, q, ofld_rxq) {
4832                                 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
4833                                 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
4834                                     ofld_rxq, s);
4835                                 if (rc != 0)
4836                                         return (rc);
4837                                 irq++;
4838                                 rid++;
4839                                 vi->nintr++;
4840                         }
4841 #endif
4842                 }
4843         }
4844         MPASS(irq == &sc->irq[sc->intr_count]);
4845
4846         return (0);
4847 }
4848
4849 int
4850 adapter_full_init(struct adapter *sc)
4851 {
4852         int rc, i;
4853 #ifdef RSS
4854         uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4855         uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4856 #endif
4857
4858         ASSERT_SYNCHRONIZED_OP(sc);
4859         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4860         KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4861             ("%s: FULL_INIT_DONE already", __func__));
4862
4863         /*
4864          * queues that belong to the adapter (not any particular port).
4865          */
4866         rc = t4_setup_adapter_queues(sc);
4867         if (rc != 0)
4868                 goto done;
4869
4870         for (i = 0; i < nitems(sc->tq); i++) {
4871                 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4872                     taskqueue_thread_enqueue, &sc->tq[i]);
4873                 if (sc->tq[i] == NULL) {
4874                         device_printf(sc->dev,
4875                             "failed to allocate task queue %d\n", i);
4876                         rc = ENOMEM;
4877                         goto done;
4878                 }
4879                 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4880                     device_get_nameunit(sc->dev), i);
4881         }
4882 #ifdef RSS
4883         MPASS(RSS_KEYSIZE == 40);
4884         rss_getkey((void *)&raw_rss_key[0]);
4885         for (i = 0; i < nitems(rss_key); i++) {
4886                 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4887         }
4888         t4_write_rss_key(sc, &rss_key[0], -1, 1);
4889 #endif
4890
4891         if (!(sc->flags & IS_VF))
4892                 t4_intr_enable(sc);
4893         sc->flags |= FULL_INIT_DONE;
4894 done:
4895         if (rc != 0)
4896                 adapter_full_uninit(sc);
4897
4898         return (rc);
4899 }
4900
4901 int
4902 adapter_full_uninit(struct adapter *sc)
4903 {
4904         int i;
4905
4906         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4907
4908         t4_teardown_adapter_queues(sc);
4909
4910         for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4911                 taskqueue_free(sc->tq[i]);
4912                 sc->tq[i] = NULL;
4913         }
4914
4915         sc->flags &= ~FULL_INIT_DONE;
4916
4917         return (0);
4918 }
4919
4920 #ifdef RSS
4921 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4922     RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4923     RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4924     RSS_HASHTYPE_RSS_UDP_IPV6)
4925
4926 /* Translates kernel hash types to hardware. */
4927 static int
4928 hashconfig_to_hashen(int hashconfig)
4929 {
4930         int hashen = 0;
4931
4932         if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4933                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4934         if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4935                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4936         if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4937                 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4938                     F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4939         }
4940         if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4941                 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4942                     F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4943         }
4944         if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4945                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4946         if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4947                 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4948
4949         return (hashen);
4950 }
4951
4952 /* Translates hardware hash types to kernel. */
4953 static int
4954 hashen_to_hashconfig(int hashen)
4955 {
4956         int hashconfig = 0;
4957
4958         if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4959                 /*
4960                  * If UDP hashing was enabled it must have been enabled for
4961                  * either IPv4 or IPv6 (inclusive or).  Enabling UDP without
4962                  * enabling any 4-tuple hash is nonsense configuration.
4963                  */
4964                 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4965                     F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4966
4967                 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4968                         hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4969                 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4970                         hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4971         }
4972         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4973                 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4974         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4975                 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4976         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4977                 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4978         if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4979                 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4980
4981         return (hashconfig);
4982 }
4983 #endif
4984
4985 int
4986 vi_full_init(struct vi_info *vi)
4987 {
4988         struct adapter *sc = vi->pi->adapter;
4989         struct ifnet *ifp = vi->ifp;
4990         uint16_t *rss;
4991         struct sge_rxq *rxq;
4992         int rc, i, j, hashen;
4993 #ifdef RSS
4994         int nbuckets = rss_getnumbuckets();
4995         int hashconfig = rss_gethashconfig();
4996         int extra;
4997 #endif
4998
4999         ASSERT_SYNCHRONIZED_OP(sc);
5000         KASSERT((vi->flags & VI_INIT_DONE) == 0,
5001             ("%s: VI_INIT_DONE already", __func__));
5002
5003         sysctl_ctx_init(&vi->ctx);
5004         vi->flags |= VI_SYSCTL_CTX;
5005
5006         /*
5007          * Allocate tx/rx/fl queues for this VI.
5008          */
5009         rc = t4_setup_vi_queues(vi);
5010         if (rc != 0)
5011                 goto done;      /* error message displayed already */
5012
5013         /*
5014          * Setup RSS for this VI.  Save a copy of the RSS table for later use.
5015          */
5016         if (vi->nrxq > vi->rss_size) {
5017                 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5018                     "some queues will never receive traffic.\n", vi->nrxq,
5019                     vi->rss_size);
5020         } else if (vi->rss_size % vi->nrxq) {
5021                 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5022                     "expect uneven traffic distribution.\n", vi->nrxq,
5023                     vi->rss_size);
5024         }
5025 #ifdef RSS
5026         if (vi->nrxq != nbuckets) {
5027                 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5028                     "performance will be impacted.\n", vi->nrxq, nbuckets);
5029         }
5030 #endif
5031         rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5032         for (i = 0; i < vi->rss_size;) {
5033 #ifdef RSS
5034                 j = rss_get_indirection_to_bucket(i);
5035                 j %= vi->nrxq;
5036                 rxq = &sc->sge.rxq[vi->first_rxq + j];
5037                 rss[i++] = rxq->iq.abs_id;
5038 #else
5039                 for_each_rxq(vi, j, rxq) {
5040                         rss[i++] = rxq->iq.abs_id;
5041                         if (i == vi->rss_size)
5042                                 break;
5043                 }
5044 #endif
5045         }
5046
5047         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5048             vi->rss_size);
5049         if (rc != 0) {
5050                 if_printf(ifp, "rss_config failed: %d\n", rc);
5051                 goto done;
5052         }
5053
5054 #ifdef RSS
5055         hashen = hashconfig_to_hashen(hashconfig);
5056
5057         /*
5058          * We may have had to enable some hashes even though the global config
5059          * wants them disabled.  This is a potential problem that must be
5060          * reported to the user.
5061          */
5062         extra = hashen_to_hashconfig(hashen) ^ hashconfig;
5063
5064         /*
5065          * If we consider only the supported hash types, then the enabled hashes
5066          * are a superset of the requested hashes.  In other words, there cannot
5067          * be any supported hash that was requested but not enabled, but there
5068          * can be hashes that were not requested but had to be enabled.
5069          */
5070         extra &= SUPPORTED_RSS_HASHTYPES;
5071         MPASS((extra & hashconfig) == 0);
5072
5073         if (extra) {
5074                 if_printf(ifp,
5075                     "global RSS config (0x%x) cannot be accommodated.\n",
5076                     hashconfig);
5077         }
5078         if (extra & RSS_HASHTYPE_RSS_IPV4)
5079                 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5080         if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5081                 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5082         if (extra & RSS_HASHTYPE_RSS_IPV6)
5083                 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5084         if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5085                 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5086         if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5087                 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5088         if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5089                 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5090 #else
5091         hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5092             F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5093             F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5094             F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5095 #endif
5096         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
5097         if (rc != 0) {
5098                 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5099                 goto done;
5100         }
5101
5102         vi->rss = rss;
5103         vi->flags |= VI_INIT_DONE;
5104 done:
5105         if (rc != 0)
5106                 vi_full_uninit(vi);
5107
5108         return (rc);
5109 }
5110
5111 /*
5112  * Idempotent.
5113  */
5114 int
5115 vi_full_uninit(struct vi_info *vi)
5116 {
5117         struct port_info *pi = vi->pi;
5118         struct adapter *sc = pi->adapter;
5119         int i;
5120         struct sge_rxq *rxq;
5121         struct sge_txq *txq;
5122 #ifdef TCP_OFFLOAD
5123         struct sge_ofld_rxq *ofld_rxq;
5124         struct sge_wrq *ofld_txq;
5125 #endif
5126
5127         if (vi->flags & VI_INIT_DONE) {
5128
5129                 /* Need to quiesce queues.  */
5130
5131                 /* XXX: Only for the first VI? */
5132                 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5133                         quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5134
5135                 for_each_txq(vi, i, txq) {
5136                         quiesce_txq(sc, txq);
5137                 }
5138
5139 #ifdef TCP_OFFLOAD
5140                 for_each_ofld_txq(vi, i, ofld_txq) {
5141                         quiesce_wrq(sc, ofld_txq);
5142                 }
5143 #endif
5144
5145                 for_each_rxq(vi, i, rxq) {
5146                         quiesce_iq(sc, &rxq->iq);
5147                         quiesce_fl(sc, &rxq->fl);
5148                 }
5149
5150 #ifdef TCP_OFFLOAD
5151                 for_each_ofld_rxq(vi, i, ofld_rxq) {
5152                         quiesce_iq(sc, &ofld_rxq->iq);
5153                         quiesce_fl(sc, &ofld_rxq->fl);
5154                 }
5155 #endif
5156                 free(vi->rss, M_CXGBE);
5157                 free(vi->nm_rss, M_CXGBE);
5158         }
5159
5160         t4_teardown_vi_queues(vi);
5161         vi->flags &= ~VI_INIT_DONE;
5162
5163         return (0);
5164 }
5165
5166 static void
5167 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5168 {
5169         struct sge_eq *eq = &txq->eq;
5170         struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5171
5172         (void) sc;      /* unused */
5173
5174 #ifdef INVARIANTS
5175         TXQ_LOCK(txq);
5176         MPASS((eq->flags & EQ_ENABLED) == 0);
5177         TXQ_UNLOCK(txq);
5178 #endif
5179
5180         /* Wait for the mp_ring to empty. */
5181         while (!mp_ring_is_idle(txq->r)) {
5182                 mp_ring_check_drainage(txq->r, 0);
5183                 pause("rquiesce", 1);
5184         }
5185
5186         /* Then wait for the hardware to finish. */
5187         while (spg->cidx != htobe16(eq->pidx))
5188                 pause("equiesce", 1);
5189
5190         /* Finally, wait for the driver to reclaim all descriptors. */
5191         while (eq->cidx != eq->pidx)
5192                 pause("dquiesce", 1);
5193 }
5194
5195 static void
5196 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5197 {
5198
5199         /* XXXTX */
5200 }
5201
5202 static void
5203 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5204 {
5205         (void) sc;      /* unused */
5206
5207         /* Synchronize with the interrupt handler */
5208         while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5209                 pause("iqfree", 1);
5210 }
5211
5212 static void
5213 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5214 {
5215         mtx_lock(&sc->sfl_lock);
5216         FL_LOCK(fl);
5217         fl->flags |= FL_DOOMED;
5218         FL_UNLOCK(fl);
5219         callout_stop(&sc->sfl_callout);
5220         mtx_unlock(&sc->sfl_lock);
5221
5222         KASSERT((fl->flags & FL_STARVING) == 0,
5223             ("%s: still starving", __func__));
5224 }
5225
5226 static int
5227 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5228     driver_intr_t *handler, void *arg, char *name)
5229 {
5230         int rc;
5231
5232         irq->rid = rid;
5233         irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5234             RF_SHAREABLE | RF_ACTIVE);
5235         if (irq->res == NULL) {
5236                 device_printf(sc->dev,
5237                     "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5238                 return (ENOMEM);
5239         }
5240
5241         rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5242             NULL, handler, arg, &irq->tag);
5243         if (rc != 0) {
5244                 device_printf(sc->dev,
5245                     "failed to setup interrupt for rid %d, name %s: %d\n",
5246                     rid, name, rc);
5247         } else if (name)
5248                 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5249
5250         return (rc);
5251 }
5252
5253 static int
5254 t4_free_irq(struct adapter *sc, struct irq *irq)
5255 {
5256         if (irq->tag)
5257                 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5258         if (irq->res)
5259                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5260
5261         bzero(irq, sizeof(*irq));
5262
5263         return (0);
5264 }
5265
5266 static void
5267 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5268 {
5269
5270         regs->version = chip_id(sc) | chip_rev(sc) << 10;
5271         t4_get_regs(sc, buf, regs->len);
5272 }
5273
5274 #define A_PL_INDIR_CMD  0x1f8
5275
5276 #define S_PL_AUTOINC    31
5277 #define M_PL_AUTOINC    0x1U
5278 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5279 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5280
5281 #define S_PL_VFID       20
5282 #define M_PL_VFID       0xffU
5283 #define V_PL_VFID(x)    ((x) << S_PL_VFID)
5284 #define G_PL_VFID(x)    (((x) >> S_PL_VFID) & M_PL_VFID)
5285
5286 #define S_PL_ADDR       0
5287 #define M_PL_ADDR       0xfffffU
5288 #define V_PL_ADDR(x)    ((x) << S_PL_ADDR)
5289 #define G_PL_ADDR(x)    (((x) >> S_PL_ADDR) & M_PL_ADDR)
5290
5291 #define A_PL_INDIR_DATA 0x1fc
5292
5293 static uint64_t
5294 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5295 {
5296         u32 stats[2];
5297
5298         mtx_assert(&sc->reg_lock, MA_OWNED);
5299         if (sc->flags & IS_VF) {
5300                 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5301                 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5302         } else {
5303                 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5304                     V_PL_VFID(G_FW_VIID_VIN(viid)) |
5305                     V_PL_ADDR(VF_MPS_REG(reg)));
5306                 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5307                 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5308         }
5309         return (((uint64_t)stats[1]) << 32 | stats[0]);
5310 }
5311
5312 static void
5313 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5314     struct fw_vi_stats_vf *stats)
5315 {
5316
5317 #define GET_STAT(name) \
5318         read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5319
5320         stats->tx_bcast_bytes    = GET_STAT(TX_VF_BCAST_BYTES);
5321         stats->tx_bcast_frames   = GET_STAT(TX_VF_BCAST_FRAMES);
5322         stats->tx_mcast_bytes    = GET_STAT(TX_VF_MCAST_BYTES);
5323         stats->tx_mcast_frames   = GET_STAT(TX_VF_MCAST_FRAMES);
5324         stats->tx_ucast_bytes    = GET_STAT(TX_VF_UCAST_BYTES);
5325         stats->tx_ucast_frames   = GET_STAT(TX_VF_UCAST_FRAMES);
5326         stats->tx_drop_frames    = GET_STAT(TX_VF_DROP_FRAMES);
5327         stats->tx_offload_bytes  = GET_STAT(TX_VF_OFFLOAD_BYTES);
5328         stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5329         stats->rx_bcast_bytes    = GET_STAT(RX_VF_BCAST_BYTES);
5330         stats->rx_bcast_frames   = GET_STAT(RX_VF_BCAST_FRAMES);
5331         stats->rx_mcast_bytes    = GET_STAT(RX_VF_MCAST_BYTES);
5332         stats->rx_mcast_frames   = GET_STAT(RX_VF_MCAST_FRAMES);
5333         stats->rx_ucast_bytes    = GET_STAT(RX_VF_UCAST_BYTES);
5334         stats->rx_ucast_frames   = GET_STAT(RX_VF_UCAST_FRAMES);
5335         stats->rx_err_frames     = GET_STAT(RX_VF_ERR_FRAMES);
5336
5337 #undef GET_STAT
5338 }
5339
5340 static void
5341 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5342 {
5343         int reg;
5344
5345         t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5346             V_PL_VFID(G_FW_VIID_VIN(viid)) |
5347             V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5348         for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5349              reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5350                 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5351 }
5352
5353 static void
5354 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5355 {
5356         struct timeval tv;
5357         const struct timeval interval = {0, 250000};    /* 250ms */
5358
5359         if (!(vi->flags & VI_INIT_DONE))
5360                 return;
5361
5362         getmicrotime(&tv);
5363         timevalsub(&tv, &interval);
5364         if (timevalcmp(&tv, &vi->last_refreshed, <))
5365                 return;
5366
5367         mtx_lock(&sc->reg_lock);
5368         t4_get_vi_stats(sc, vi->viid, &vi->stats);
5369         getmicrotime(&vi->last_refreshed);
5370         mtx_unlock(&sc->reg_lock);
5371 }
5372
5373 static void
5374 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5375 {
5376         u_int i, v, tnl_cong_drops, bg_map;
5377         struct timeval tv;
5378         const struct timeval interval = {0, 250000};    /* 250ms */
5379
5380         getmicrotime(&tv);
5381         timevalsub(&tv, &interval);
5382         if (timevalcmp(&tv, &pi->last_refreshed, <))
5383                 return;
5384
5385         tnl_cong_drops = 0;
5386         t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5387         bg_map = pi->mps_bg_map;
5388         while (bg_map) {
5389                 i = ffs(bg_map) - 1;
5390                 mtx_lock(&sc->reg_lock);
5391                 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5392                     A_TP_MIB_TNL_CNG_DROP_0 + i);
5393                 mtx_unlock(&sc->reg_lock);
5394                 tnl_cong_drops += v;
5395                 bg_map &= ~(1 << i);
5396         }
5397         pi->tnl_cong_drops = tnl_cong_drops;
5398         getmicrotime(&pi->last_refreshed);
5399 }
5400
5401 static void
5402 cxgbe_tick(void *arg)
5403 {
5404         struct port_info *pi = arg;
5405         struct adapter *sc = pi->adapter;
5406
5407         PORT_LOCK_ASSERT_OWNED(pi);
5408         cxgbe_refresh_stats(sc, pi);
5409
5410         callout_schedule(&pi->tick, hz);
5411 }
5412
5413 void
5414 vi_tick(void *arg)
5415 {
5416         struct vi_info *vi = arg;
5417         struct adapter *sc = vi->pi->adapter;
5418
5419         vi_refresh_stats(sc, vi);
5420
5421         callout_schedule(&vi->tick, hz);
5422 }
5423
5424 static void
5425 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
5426 {
5427         struct ifnet *vlan;
5428
5429         if (arg != ifp || ifp->if_type != IFT_ETHER)
5430                 return;
5431
5432         vlan = VLAN_DEVAT(ifp, vid);
5433         VLAN_SETCOOKIE(vlan, ifp);
5434 }
5435
5436 /*
5437  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5438  */
5439 static char *caps_decoder[] = {
5440         "\20\001IPMI\002NCSI",                          /* 0: NBM */
5441         "\20\001PPP\002QFC\003DCBX",                    /* 1: link */
5442         "\20\001INGRESS\002EGRESS",                     /* 2: switch */
5443         "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"      /* 3: NIC */
5444             "\006HASHFILTER\007ETHOFLD",
5445         "\20\001TOE",                                   /* 4: TOE */
5446         "\20\001RDDP\002RDMAC",                         /* 5: RDMA */
5447         "\20\001INITIATOR_PDU\002TARGET_PDU"            /* 6: iSCSI */
5448             "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5449             "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5450             "\007T10DIF"
5451             "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5452         "\20\001LOOKASIDE\002TLSKEYS",                  /* 7: Crypto */
5453         "\20\001INITIATOR\002TARGET\003CTRL_OFLD"       /* 8: FCoE */
5454                     "\004PO_INITIATOR\005PO_TARGET",
5455 };
5456
5457 void
5458 t4_sysctls(struct adapter *sc)
5459 {
5460         struct sysctl_ctx_list *ctx;
5461         struct sysctl_oid *oid;
5462         struct sysctl_oid_list *children, *c0;
5463         static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5464
5465         ctx = device_get_sysctl_ctx(sc->dev);
5466
5467         /*
5468          * dev.t4nex.X.
5469          */
5470         oid = device_get_sysctl_tree(sc->dev);
5471         c0 = children = SYSCTL_CHILDREN(oid);
5472
5473         sc->sc_do_rxcopy = 1;
5474         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5475             &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5476
5477         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5478             sc->params.nports, "# of ports");
5479
5480         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5481             CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
5482             sysctl_bitfield, "A", "available doorbells");
5483
5484         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5485             sc->params.vpd.cclk, "core clock frequency (in KHz)");
5486
5487         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5488             CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5489             sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5490             "interrupt holdoff timer values (us)");
5491
5492         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5493             CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5494             sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5495             "interrupt holdoff packet counter values");
5496
5497         t4_sge_sysctls(sc, ctx, children);
5498
5499         sc->lro_timeout = 100;
5500         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5501             &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5502
5503         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5504             &sc->debug_flags, 0, "flags to enable runtime debugging");
5505
5506         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5507             CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5508
5509         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5510             CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5511
5512         if (sc->flags & IS_VF)
5513                 return;
5514
5515         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5516             NULL, chip_rev(sc), "chip hardware revision");
5517
5518         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5519             CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5520
5521         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5522             CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5523
5524         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5525             CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5526
5527         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5528             CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5529
5530         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5531             CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5532
5533         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5534             sc->er_version, 0, "expansion ROM version");
5535
5536         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5537             sc->bs_version, 0, "bootstrap firmware version");
5538
5539         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5540             NULL, sc->params.scfg_vers, "serial config version");
5541
5542         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5543             NULL, sc->params.vpd_vers, "VPD version");
5544
5545         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5546             CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5547
5548         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5549             sc->cfcsum, "config file checksum");
5550
5551 #define SYSCTL_CAP(name, n, text) \
5552         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5553             CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
5554             sysctl_bitfield, "A", "available " text " capabilities")
5555
5556         SYSCTL_CAP(nbmcaps, 0, "NBM");
5557         SYSCTL_CAP(linkcaps, 1, "link");
5558         SYSCTL_CAP(switchcaps, 2, "switch");
5559         SYSCTL_CAP(niccaps, 3, "NIC");
5560         SYSCTL_CAP(toecaps, 4, "TCP offload");
5561         SYSCTL_CAP(rdmacaps, 5, "RDMA");
5562         SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5563         SYSCTL_CAP(cryptocaps, 7, "crypto");
5564         SYSCTL_CAP(fcoecaps, 8, "FCoE");
5565 #undef SYSCTL_CAP
5566
5567         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5568             NULL, sc->tids.nftids, "number of filters");
5569
5570         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5571             CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5572             "chip temperature (in Celsius)");
5573
5574         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5575             CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5576             "microprocessor load averages (debug firmwares only)");
5577
5578         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5579             &sc->params.core_vdd, 0, "core Vdd (in mV)");
5580
5581 #ifdef SBUF_DRAIN
5582         /*
5583          * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
5584          */
5585         oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5586             CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5587             "logs and miscellaneous information");
5588         children = SYSCTL_CHILDREN(oid);
5589
5590         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5591             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5592             sysctl_cctrl, "A", "congestion control");
5593
5594         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5595             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5596             sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5597
5598         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5599             CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5600             sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5601
5602         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5603             CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5604             sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5605
5606         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5607             CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5608             sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5609
5610         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5611             CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5612             sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5613
5614         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5615             CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5616             sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5617
5618         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5619             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5620             chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5621             "A", "CIM logic analyzer");
5622
5623         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5624             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5625             sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5626
5627         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5628             CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5629             sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5630
5631         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5632             CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5633             sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5634
5635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5636             CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5637             sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5638
5639         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5640             CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5641             sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5642
5643         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5644             CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5645             sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5646
5647         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5648             CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5649             sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5650
5651         if (chip_id(sc) > CHELSIO_T4) {
5652                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5653                     CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5654                     sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5655
5656                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5657                     CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5658                     sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5659         }
5660
5661         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5662             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5663             sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5664
5665         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5666             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5667             sysctl_cim_qcfg, "A", "CIM queue configuration");
5668
5669         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5670             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5671             sysctl_cpl_stats, "A", "CPL statistics");
5672
5673         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5674             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5675             sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5676
5677         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5678             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5679             sysctl_devlog, "A", "firmware's device log");
5680
5681         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5682             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5683             sysctl_fcoe_stats, "A", "FCoE statistics");
5684
5685         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5686             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5687             sysctl_hw_sched, "A", "hardware scheduler ");
5688
5689         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5690             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5691             sysctl_l2t, "A", "hardware L2 table");
5692
5693         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5694             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5695             sysctl_lb_stats, "A", "loopback statistics");
5696
5697         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5698             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5699             sysctl_meminfo, "A", "memory regions");
5700
5701         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5702             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5703             chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5704             "A", "MPS TCAM entries");
5705
5706         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5707             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5708             sysctl_path_mtus, "A", "path MTUs");
5709
5710         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5711             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5712             sysctl_pm_stats, "A", "PM statistics");
5713
5714         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5715             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5716             sysctl_rdma_stats, "A", "RDMA statistics");
5717
5718         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5719             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5720             sysctl_tcp_stats, "A", "TCP statistics");
5721
5722         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5723             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5724             sysctl_tids, "A", "TID information");
5725
5726         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5727             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5728             sysctl_tp_err_stats, "A", "TP error statistics");
5729
5730         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5731             CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5732             "TP logic analyzer event capture mask");
5733
5734         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5735             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5736             sysctl_tp_la, "A", "TP logic analyzer");
5737
5738         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5739             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5740             sysctl_tx_rate, "A", "Tx rate");
5741
5742         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5743             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5744             sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5745
5746         if (chip_id(sc) >= CHELSIO_T5) {
5747                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5748                     CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5749                     sysctl_wcwr_stats, "A", "write combined work requests");
5750         }
5751 #endif
5752
5753 #ifdef TCP_OFFLOAD
5754         if (is_offload(sc)) {
5755                 int i;
5756                 char s[4];
5757
5758                 /*
5759                  * dev.t4nex.X.toe.
5760                  */
5761                 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5762                     NULL, "TOE parameters");
5763                 children = SYSCTL_CHILDREN(oid);
5764
5765                 sc->tt.cong_algorithm = -1;
5766                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
5767                     CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
5768                     "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
5769                     "3 = highspeed)");
5770
5771                 sc->tt.sndbuf = 256 * 1024;
5772                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5773                     &sc->tt.sndbuf, 0, "max hardware send buffer size");
5774
5775                 sc->tt.ddp = 0;
5776                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5777                     &sc->tt.ddp, 0, "DDP allowed");
5778
5779                 sc->tt.rx_coalesce = 1;
5780                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5781                     CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5782
5783                 sc->tt.tx_align = 1;
5784                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
5785                     CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
5786
5787                 sc->tt.tx_zcopy = 0;
5788                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
5789                     CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
5790                     "Enable zero-copy aio_write(2)");
5791
5792                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
5793                     CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
5794                     "TP timer tick (us)");
5795
5796                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
5797                     CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
5798                     "TCP timestamp tick (us)");
5799
5800                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5801                     CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5802                     "DACK tick (us)");
5803
5804                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5805                     CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5806                     "IU", "DACK timer (us)");
5807
5808                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5809                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5810                     sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
5811
5812                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5813                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5814                     sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
5815
5816                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5817                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5818                     sysctl_tp_timer, "LU", "Persist timer min (us)");
5819
5820                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5821                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5822                     sysctl_tp_timer, "LU", "Persist timer max (us)");
5823
5824                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5825                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5826                     sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
5827
5828                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
5829                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5830                     sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
5831
5832                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5833                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5834                     sysctl_tp_timer, "LU", "Initial SRTT (us)");
5835
5836                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5837                     CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5838                     sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5839
5840                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
5841                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
5842                     sysctl_tp_shift_cnt, "IU",
5843                     "Number of SYN retransmissions before abort");
5844
5845                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
5846                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
5847                     sysctl_tp_shift_cnt, "IU",
5848                     "Number of retransmissions before abort");
5849
5850                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
5851                     CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
5852                     sysctl_tp_shift_cnt, "IU",
5853                     "Number of keepalive probes before abort");
5854
5855                 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
5856                     CTLFLAG_RD, NULL, "TOE retransmit backoffs");
5857                 children = SYSCTL_CHILDREN(oid);
5858                 for (i = 0; i < 16; i++) {
5859                         snprintf(s, sizeof(s), "%u", i);
5860                         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
5861                             CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
5862                             "IU", "TOE retransmit backoff");
5863                 }
5864         }
5865 #endif
5866 }
5867
5868 void
5869 vi_sysctls(struct vi_info *vi)
5870 {
5871         struct sysctl_ctx_list *ctx;
5872         struct sysctl_oid *oid;
5873         struct sysctl_oid_list *children;
5874
5875         ctx = device_get_sysctl_ctx(vi->dev);
5876
5877         /*
5878          * dev.v?(cxgbe|cxl).X.
5879          */
5880         oid = device_get_sysctl_tree(vi->dev);
5881         children = SYSCTL_CHILDREN(oid);
5882
5883         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5884             vi->viid, "VI identifer");
5885         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5886             &vi->nrxq, 0, "# of rx queues");
5887         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5888             &vi->ntxq, 0, "# of tx queues");
5889         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5890             &vi->first_rxq, 0, "index of first rx queue");
5891         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5892             &vi->first_txq, 0, "index of first tx queue");
5893         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5894             vi->rss_size, "size of RSS indirection table");
5895
5896         if (IS_MAIN_VI(vi)) {
5897                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5898                     CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5899                     "Reserve queue 0 for non-flowid packets");
5900         }
5901
5902 #ifdef TCP_OFFLOAD
5903         if (vi->nofldrxq != 0) {
5904                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5905                     &vi->nofldrxq, 0,
5906                     "# of rx queues for offloaded TCP connections");
5907                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5908                     &vi->nofldtxq, 0,
5909                     "# of tx queues for offloaded TCP connections");
5910                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5911                     CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5912                     "index of first TOE rx queue");
5913                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5914                     CTLFLAG_RD, &vi->first_ofld_txq, 0,
5915                     "index of first TOE tx queue");
5916                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
5917                     CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5918                     sysctl_holdoff_tmr_idx_ofld, "I",
5919                     "holdoff timer index for TOE queues");
5920                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
5921                     CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5922                     sysctl_holdoff_pktc_idx_ofld, "I",
5923                     "holdoff packet counter index for TOE queues");
5924         }
5925 #endif
5926 #ifdef DEV_NETMAP
5927         if (vi->nnmrxq != 0) {
5928                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5929                     &vi->nnmrxq, 0, "# of netmap rx queues");
5930                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5931                     &vi->nnmtxq, 0, "# of netmap tx queues");
5932                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5933                     CTLFLAG_RD, &vi->first_nm_rxq, 0,
5934                     "index of first netmap rx queue");
5935                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5936                     CTLFLAG_RD, &vi->first_nm_txq, 0,
5937                     "index of first netmap tx queue");
5938         }
5939 #endif
5940
5941         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5942             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5943             "holdoff timer index");
5944         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5945             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5946             "holdoff packet counter index");
5947
5948         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5949             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5950             "rx queue size");
5951         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5952             CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5953             "tx queue size");
5954 }
5955
5956 static void
5957 cxgbe_sysctls(struct port_info *pi)
5958 {
5959         struct sysctl_ctx_list *ctx;
5960         struct sysctl_oid *oid;
5961         struct sysctl_oid_list *children, *children2;
5962         struct adapter *sc = pi->adapter;
5963         int i;
5964         char name[16];
5965
5966         ctx = device_get_sysctl_ctx(pi->dev);
5967
5968         /*
5969          * dev.cxgbe.X.
5970          */
5971         oid = device_get_sysctl_tree(pi->dev);
5972         children = SYSCTL_CHILDREN(oid);
5973
5974         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5975            CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5976         if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5977                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5978                     CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5979                     "PHY temperature (in Celsius)");
5980                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5981                     CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5982                     "PHY firmware version");
5983         }
5984
5985         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5986             CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
5987     "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
5988         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
5989             CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
5990             "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
5991         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
5992             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
5993             "autonegotiation (-1 = not supported)");
5994
5995         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5996             port_top_speed(pi), "max speed (in Gbps)");
5997         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
5998             pi->mps_bg_map, "MPS buffer group map");
5999         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6000             NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6001
6002         if (sc->flags & IS_VF)
6003                 return;
6004
6005         /*
6006          * dev.(cxgbe|cxl).X.tc.
6007          */
6008         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6009             "Tx scheduler traffic classes (cl_rl)");
6010         for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6011                 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6012
6013                 snprintf(name, sizeof(name), "%d", i);
6014                 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6015                     SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6016                     "traffic class"));
6017                 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
6018                     &tc->flags, 0, "flags");
6019                 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6020                     CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6021 #ifdef SBUF_DRAIN
6022                 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6023                     CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6024                     sysctl_tc_params, "A", "traffic class parameters");
6025 #endif
6026         }
6027
6028         /*
6029          * dev.cxgbe.X.stats.
6030          */
6031         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6032             NULL, "port statistics");
6033         children = SYSCTL_CHILDREN(oid);
6034         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6035             &pi->tx_parse_error, 0,
6036             "# of tx packets with invalid length or # of segments");
6037
6038 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6039         SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6040             CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6041             sysctl_handle_t4_reg64, "QU", desc)
6042
6043         SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6044             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6045         SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6046             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6047         SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6048             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6049         SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6050             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6051         SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6052             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6053         SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6054             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6055         SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6056             "# of tx frames in this range",
6057             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6058         SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6059             "# of tx frames in this range",
6060             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6061         SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6062             "# of tx frames in this range",
6063             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6064         SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6065             "# of tx frames in this range",
6066             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6067         SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6068             "# of tx frames in this range",
6069             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6070         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6071             "# of tx frames in this range",
6072             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6073         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6074             "# of tx frames in this range",
6075             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6076         SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6077             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6078         SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6079             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6080         SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6081             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6082         SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6083             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6084         SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6085             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6086         SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6087             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6088         SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6089             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6090         SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6091             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6092         SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6093             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6094         SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6095             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6096
6097         SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6098             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6099         SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6100             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6101         SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6102             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6103         SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6104             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6105         SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6106             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6107         SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6108             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6109         SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6110             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6111         SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6112             "# of frames received with bad FCS",
6113             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6114         SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6115             "# of frames received with length error",
6116             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6117         SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6118             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6119         SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6120             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6121         SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6122             "# of rx frames in this range",
6123             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6124         SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6125             "# of rx frames in this range",
6126             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6127         SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6128             "# of rx frames in this range",
6129             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6130         SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6131             "# of rx frames in this range",
6132             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6133         SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6134             "# of rx frames in this range",
6135             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6136         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6137             "# of rx frames in this range",
6138             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6139         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6140             "# of rx frames in this range",
6141             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6142         SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6143             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6144         SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6145             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6146         SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6147             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6148         SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6149             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6150         SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6151             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6152         SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6153             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6154         SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6155             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6156         SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6157             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6158         SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6159             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6160
6161 #undef SYSCTL_ADD_T4_REG64
6162
6163 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6164         SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6165             &pi->stats.name, desc)
6166
6167         /* We get these from port_stats and they may be stale by up to 1s */
6168         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6169             "# drops due to buffer-group 0 overflows");
6170         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6171             "# drops due to buffer-group 1 overflows");
6172         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6173             "# drops due to buffer-group 2 overflows");
6174         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6175             "# drops due to buffer-group 3 overflows");
6176         SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6177             "# of buffer-group 0 truncated packets");
6178         SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6179             "# of buffer-group 1 truncated packets");
6180         SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6181             "# of buffer-group 2 truncated packets");
6182         SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6183             "# of buffer-group 3 truncated packets");
6184
6185 #undef SYSCTL_ADD_T4_PORTSTAT
6186 }
6187
6188 static int
6189 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6190 {
6191         int rc, *i, space = 0;
6192         struct sbuf sb;
6193
6194         sbuf_new_for_sysctl(&sb, NULL, 64, req);
6195         for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6196                 if (space)
6197                         sbuf_printf(&sb, " ");
6198                 sbuf_printf(&sb, "%d", *i);
6199                 space = 1;
6200         }
6201         rc = sbuf_finish(&sb);
6202         sbuf_delete(&sb);
6203         return (rc);
6204 }
6205
6206 static int
6207 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
6208 {
6209         int rc;
6210         struct sbuf *sb;
6211
6212         rc = sysctl_wire_old_buffer(req, 0);
6213         if (rc != 0)
6214                 return(rc);
6215
6216         sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6217         if (sb == NULL)
6218                 return (ENOMEM);
6219
6220         sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
6221         rc = sbuf_finish(sb);
6222         sbuf_delete(sb);
6223
6224         return (rc);
6225 }
6226
6227 static int
6228 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6229 {
6230         struct port_info *pi = arg1;
6231         int op = arg2;
6232         struct adapter *sc = pi->adapter;
6233         u_int v;
6234         int rc;
6235
6236         rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6237         if (rc)
6238                 return (rc);
6239         /* XXX: magic numbers */
6240         rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6241             &v);
6242         end_synchronized_op(sc, 0);
6243         if (rc)
6244                 return (rc);
6245         if (op == 0)
6246                 v /= 256;
6247
6248         rc = sysctl_handle_int(oidp, &v, 0, req);
6249         return (rc);
6250 }
6251
6252 static int
6253 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6254 {
6255         struct vi_info *vi = arg1;
6256         int rc, val;
6257
6258         val = vi->rsrv_noflowq;
6259         rc = sysctl_handle_int(oidp, &val, 0, req);
6260         if (rc != 0 || req->newptr == NULL)
6261                 return (rc);
6262
6263         if ((val >= 1) && (vi->ntxq > 1))
6264                 vi->rsrv_noflowq = 1;
6265         else
6266                 vi->rsrv_noflowq = 0;
6267
6268         return (rc);
6269 }
6270
6271 static int
6272 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6273 {
6274         struct vi_info *vi = arg1;
6275         struct adapter *sc = vi->pi->adapter;
6276         int idx, rc, i;
6277         struct sge_rxq *rxq;
6278         uint8_t v;
6279
6280         idx = vi->tmr_idx;
6281
6282         rc = sysctl_handle_int(oidp, &idx, 0, req);
6283         if (rc != 0 || req->newptr == NULL)
6284                 return (rc);
6285
6286         if (idx < 0 || idx >= SGE_NTIMERS)
6287                 return (EINVAL);
6288
6289         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6290             "t4tmr");
6291         if (rc)
6292                 return (rc);
6293
6294         v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6295         for_each_rxq(vi, i, rxq) {
6296 #ifdef atomic_store_rel_8
6297                 atomic_store_rel_8(&rxq->iq.intr_params, v);
6298 #else
6299                 rxq->iq.intr_params = v;
6300 #endif
6301         }
6302         vi->tmr_idx = idx;
6303
6304         end_synchronized_op(sc, LOCK_HELD);
6305         return (0);
6306 }
6307
6308 static int
6309 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6310 {
6311         struct vi_info *vi = arg1;
6312         struct adapter *sc = vi->pi->adapter;
6313         int idx, rc;
6314
6315         idx = vi->pktc_idx;
6316
6317         rc = sysctl_handle_int(oidp, &idx, 0, req);
6318         if (rc != 0 || req->newptr == NULL)
6319                 return (rc);
6320
6321         if (idx < -1 || idx >= SGE_NCOUNTERS)
6322                 return (EINVAL);
6323
6324         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6325             "t4pktc");
6326         if (rc)
6327                 return (rc);
6328
6329         if (vi->flags & VI_INIT_DONE)
6330                 rc = EBUSY; /* cannot be changed once the queues are created */
6331         else
6332                 vi->pktc_idx = idx;
6333
6334         end_synchronized_op(sc, LOCK_HELD);
6335         return (rc);
6336 }
6337
6338 static int
6339 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6340 {
6341         struct vi_info *vi = arg1;
6342         struct adapter *sc = vi->pi->adapter;
6343         int qsize, rc;
6344
6345         qsize = vi->qsize_rxq;
6346
6347         rc = sysctl_handle_int(oidp, &qsize, 0, req);
6348         if (rc != 0 || req->newptr == NULL)
6349                 return (rc);
6350
6351         if (qsize < 128 || (qsize & 7))
6352                 return (EINVAL);
6353
6354         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6355             "t4rxqs");
6356         if (rc)
6357                 return (rc);
6358
6359         if (vi->flags & VI_INIT_DONE)
6360                 rc = EBUSY; /* cannot be changed once the queues are created */
6361         else
6362                 vi->qsize_rxq = qsize;
6363
6364         end_synchronized_op(sc, LOCK_HELD);
6365         return (rc);
6366 }
6367
6368 static int
6369 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6370 {
6371         struct vi_info *vi = arg1;
6372         struct adapter *sc = vi->pi->adapter;
6373         int qsize, rc;
6374
6375         qsize = vi->qsize_txq;
6376
6377         rc = sysctl_handle_int(oidp, &qsize, 0, req);
6378         if (rc != 0 || req->newptr == NULL)
6379                 return (rc);
6380
6381         if (qsize < 128 || qsize > 65536)
6382                 return (EINVAL);
6383
6384         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6385             "t4txqs");
6386         if (rc)
6387                 return (rc);
6388
6389         if (vi->flags & VI_INIT_DONE)
6390                 rc = EBUSY; /* cannot be changed once the queues are created */
6391         else
6392                 vi->qsize_txq = qsize;
6393
6394         end_synchronized_op(sc, LOCK_HELD);
6395         return (rc);
6396 }
6397
6398 static int
6399 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6400 {
6401         struct port_info *pi = arg1;
6402         struct adapter *sc = pi->adapter;
6403         struct link_config *lc = &pi->link_cfg;
6404         int rc;
6405
6406         if (req->newptr == NULL) {
6407                 struct sbuf *sb;
6408                 static char *bits = "\20\1RX\2TX\3AUTO";
6409
6410                 rc = sysctl_wire_old_buffer(req, 0);
6411                 if (rc != 0)
6412                         return(rc);
6413
6414                 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6415                 if (sb == NULL)
6416                         return (ENOMEM);
6417
6418                 if (lc->link_ok) {
6419                         sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6420                             (lc->requested_fc & PAUSE_AUTONEG), bits);
6421                 } else {
6422                         sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6423                             PAUSE_RX | PAUSE_AUTONEG), bits);
6424                 }
6425                 rc = sbuf_finish(sb);
6426                 sbuf_delete(sb);
6427         } else {
6428                 char s[2];
6429                 int n;
6430
6431                 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6432                     PAUSE_AUTONEG));
6433                 s[1] = 0;
6434
6435                 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6436                 if (rc != 0)
6437                         return(rc);
6438
6439                 if (s[1] != 0)
6440                         return (EINVAL);
6441                 if (s[0] < '0' || s[0] > '9')
6442                         return (EINVAL);        /* not a number */
6443                 n = s[0] - '0';
6444                 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6445                         return (EINVAL);        /* some other bit is set too */
6446
6447                 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6448                     "t4PAUSE");
6449                 if (rc)
6450                         return (rc);
6451                 PORT_LOCK(pi);
6452                 lc->requested_fc = n;
6453                 fixup_link_config(pi);
6454                 if (pi->up_vis > 0)
6455                         rc = apply_link_config(pi);
6456                 set_current_media(pi);
6457                 PORT_UNLOCK(pi);
6458                 end_synchronized_op(sc, 0);
6459         }
6460
6461         return (rc);
6462 }
6463
6464 static int
6465 sysctl_fec(SYSCTL_HANDLER_ARGS)
6466 {
6467         struct port_info *pi = arg1;
6468         struct adapter *sc = pi->adapter;
6469         struct link_config *lc = &pi->link_cfg;
6470         int rc;
6471         int8_t old;
6472
6473         if (req->newptr == NULL) {
6474                 struct sbuf *sb;
6475                 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
6476
6477                 rc = sysctl_wire_old_buffer(req, 0);
6478                 if (rc != 0)
6479                         return(rc);
6480
6481                 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6482                 if (sb == NULL)
6483                         return (ENOMEM);
6484
6485                 /*
6486                  * Display the requested_fec when the link is down -- the actual
6487                  * FEC makes sense only when the link is up.
6488                  */
6489                 if (lc->link_ok) {
6490                         sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
6491                             (lc->requested_fec & FEC_AUTO), bits);
6492                 } else {
6493                         sbuf_printf(sb, "%b", lc->requested_fec, bits);
6494                 }
6495                 rc = sbuf_finish(sb);
6496                 sbuf_delete(sb);
6497         } else {
6498                 char s[3];
6499                 int n;
6500
6501                 snprintf(s, sizeof(s), "%d",
6502                     lc->requested_fec == FEC_AUTO ? -1 :
6503                     lc->requested_fec & M_FW_PORT_CAP32_FEC);
6504
6505                 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6506                 if (rc != 0)
6507                         return(rc);
6508
6509                 n = strtol(&s[0], NULL, 0);
6510                 if (n < 0 || n & FEC_AUTO)
6511                         n = FEC_AUTO;
6512                 else {
6513                         if (n & ~M_FW_PORT_CAP32_FEC)
6514                                 return (EINVAL);/* some other bit is set too */
6515                         if (!powerof2(n))
6516                                 return (EINVAL);/* one bit can be set at most */
6517                 }
6518
6519                 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6520                     "t4fec");
6521                 if (rc)
6522                         return (rc);
6523                 PORT_LOCK(pi);
6524                 old = lc->requested_fec;
6525                 if (n == FEC_AUTO)
6526                         lc->requested_fec = FEC_AUTO;
6527                 else if (n == 0)
6528                         lc->requested_fec = FEC_NONE;
6529                 else {
6530                         if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
6531                             lc->supported) {
6532                                 rc = ENOTSUP;
6533                                 goto done;
6534                         }
6535                         lc->requested_fec = n;
6536                 }
6537                 fixup_link_config(pi);
6538                 if (pi->up_vis > 0) {
6539                         rc = apply_link_config(pi);
6540                         if (rc != 0) {
6541                                 lc->requested_fec = old;
6542                                 if (rc == FW_EPROTO)
6543                                         rc = ENOTSUP;
6544                         }
6545                 }
6546 done:
6547                 PORT_UNLOCK(pi);
6548                 end_synchronized_op(sc, 0);
6549         }
6550
6551         return (rc);
6552 }
6553
6554 static int
6555 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
6556 {
6557         struct port_info *pi = arg1;
6558         struct adapter *sc = pi->adapter;
6559         struct link_config *lc = &pi->link_cfg;
6560         int rc, val;
6561
6562         if (lc->supported & FW_PORT_CAP32_ANEG)
6563                 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
6564         else
6565                 val = -1;
6566         rc = sysctl_handle_int(oidp, &val, 0, req);
6567         if (rc != 0 || req->newptr == NULL)
6568                 return (rc);
6569         if (val == 0)
6570                 val = AUTONEG_DISABLE;
6571         else if (val == 1)
6572                 val = AUTONEG_ENABLE;
6573         else
6574                 val = AUTONEG_AUTO;
6575
6576         rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6577             "t4aneg");
6578         if (rc)
6579                 return (rc);
6580         PORT_LOCK(pi);
6581         if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
6582                 rc = ENOTSUP;
6583                 goto done;
6584         }
6585         lc->requested_aneg = val;
6586         fixup_link_config(pi);
6587         if (pi->up_vis > 0)
6588                 rc = apply_link_config(pi);
6589         set_current_media(pi);
6590 done:
6591         PORT_UNLOCK(pi);
6592         end_synchronized_op(sc, 0);
6593         return (rc);
6594 }
6595
6596 static int
6597 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
6598 {
6599         struct adapter *sc = arg1;
6600         int reg = arg2;
6601         uint64_t val;
6602
6603         val = t4_read_reg64(sc, reg);
6604
6605         return (sysctl_handle_64(oidp, &val, 0, req));
6606 }
6607
6608 static int
6609 sysctl_temperature(SYSCTL_HANDLER_ARGS)
6610 {
6611         struct adapter *sc = arg1;
6612         int rc, t;
6613         uint32_t param, val;
6614
6615         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
6616         if (rc)
6617                 return (rc);
6618         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6619             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
6620             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
6621         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6622         end_synchronized_op(sc, 0);
6623         if (rc)
6624                 return (rc);
6625
6626         /* unknown is returned as 0 but we display -1 in that case */
6627         t = val == 0 ? -1 : val;
6628
6629         rc = sysctl_handle_int(oidp, &t, 0, req);
6630         return (rc);
6631 }
6632
6633 #ifdef SBUF_DRAIN
6634 static int
6635 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
6636 {
6637         struct adapter *sc = arg1;
6638         struct sbuf *sb;
6639         int rc;
6640         uint32_t param, val;
6641
6642         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
6643         if (rc)
6644                 return (rc);
6645         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6646             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
6647         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
6648         end_synchronized_op(sc, 0);
6649         if (rc)
6650                 return (rc);
6651
6652         rc = sysctl_wire_old_buffer(req, 0);
6653         if (rc != 0)
6654                 return (rc);
6655
6656         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6657         if (sb == NULL)
6658                 return (ENOMEM);
6659
6660         if (val == 0xffffffff) {
6661                 /* Only debug and custom firmwares report load averages. */
6662                 sbuf_printf(sb, "not available");
6663         } else {
6664                 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
6665                     (val >> 16) & 0xff);
6666         }
6667         rc = sbuf_finish(sb);
6668         sbuf_delete(sb);
6669
6670         return (rc);
6671 }
6672
6673 static int
6674 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6675 {
6676         struct adapter *sc = arg1;
6677         struct sbuf *sb;
6678         int rc, i;
6679         uint16_t incr[NMTUS][NCCTRL_WIN];
6680         static const char *dec_fac[] = {
6681                 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6682                 "0.9375"
6683         };
6684
6685         rc = sysctl_wire_old_buffer(req, 0);
6686         if (rc != 0)
6687                 return (rc);
6688
6689         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6690         if (sb == NULL)
6691                 return (ENOMEM);
6692
6693         t4_read_cong_tbl(sc, incr);
6694
6695         for (i = 0; i < NCCTRL_WIN; ++i) {
6696                 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6697                     incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6698                     incr[5][i], incr[6][i], incr[7][i]);
6699                 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6700                     incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6701                     incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6702                     sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6703         }
6704
6705         rc = sbuf_finish(sb);
6706         sbuf_delete(sb);
6707
6708         return (rc);
6709 }
6710
6711 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6712         "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",   /* ibq's */
6713         "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6714         "SGE0-RX", "SGE1-RX"    /* additional obq's (T5 onwards) */
6715 };
6716
6717 static int
6718 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6719 {
6720         struct adapter *sc = arg1;
6721         struct sbuf *sb;
6722         int rc, i, n, qid = arg2;
6723         uint32_t *buf, *p;
6724         char *qtype;
6725         u_int cim_num_obq = sc->chip_params->cim_num_obq;
6726
6727         KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6728             ("%s: bad qid %d\n", __func__, qid));
6729
6730         if (qid < CIM_NUM_IBQ) {
6731                 /* inbound queue */
6732                 qtype = "IBQ";
6733                 n = 4 * CIM_IBQ_SIZE;
6734                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6735                 rc = t4_read_cim_ibq(sc, qid, buf, n);
6736         } else {
6737                 /* outbound queue */
6738                 qtype = "OBQ";
6739                 qid -= CIM_NUM_IBQ;
6740                 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
6741                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6742                 rc = t4_read_cim_obq(sc, qid, buf, n);
6743         }
6744
6745         if (rc < 0) {
6746                 rc = -rc;
6747                 goto done;
6748         }
6749         n = rc * sizeof(uint32_t);      /* rc has # of words actually read */
6750
6751         rc = sysctl_wire_old_buffer(req, 0);
6752         if (rc != 0)
6753                 goto done;
6754
6755         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6756         if (sb == NULL) {
6757                 rc = ENOMEM;
6758                 goto done;
6759         }
6760
6761         sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
6762         for (i = 0, p = buf; i < n; i += 16, p += 4)
6763                 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
6764                     p[2], p[3]);
6765
6766         rc = sbuf_finish(sb);
6767         sbuf_delete(sb);
6768 done:
6769         free(buf, M_CXGBE);
6770         return (rc);
6771 }
6772
6773 static int
6774 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
6775 {
6776         struct adapter *sc = arg1;
6777         u_int cfg;
6778         struct sbuf *sb;
6779         uint32_t *buf, *p;
6780         int rc;
6781
6782         MPASS(chip_id(sc) <= CHELSIO_T5);
6783
6784         rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6785         if (rc != 0)
6786                 return (rc);
6787
6788         rc = sysctl_wire_old_buffer(req, 0);
6789         if (rc != 0)
6790                 return (rc);
6791
6792         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6793         if (sb == NULL)
6794                 return (ENOMEM);
6795
6796         buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6797             M_ZERO | M_WAITOK);
6798
6799         rc = -t4_cim_read_la(sc, buf, NULL);
6800         if (rc != 0)
6801                 goto done;
6802
6803         sbuf_printf(sb, "Status   Data      PC%s",
6804             cfg & F_UPDBGLACAPTPCONLY ? "" :
6805             "     LS0Stat  LS0Addr             LS0Data");
6806
6807         for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
6808                 if (cfg & F_UPDBGLACAPTPCONLY) {
6809                         sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
6810                             p[6], p[7]);
6811                         sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
6812                             (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
6813                             p[4] & 0xff, p[5] >> 8);
6814                         sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
6815                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6816                             p[1] & 0xf, p[2] >> 4);
6817                 } else {
6818                         sbuf_printf(sb,
6819                             "\n  %02x   %x%07x %x%07x %08x %08x "
6820                             "%08x%08x%08x%08x",
6821                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6822                             p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
6823                             p[6], p[7]);
6824                 }
6825         }
6826
6827         rc = sbuf_finish(sb);
6828         sbuf_delete(sb);
6829 done:
6830         free(buf, M_CXGBE);
6831         return (rc);
6832 }
6833
6834 static int
6835 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
6836 {
6837         struct adapter *sc = arg1;
6838         u_int cfg;
6839         struct sbuf *sb;
6840         uint32_t *buf, *p;
6841         int rc;
6842
6843         MPASS(chip_id(sc) > CHELSIO_T5);
6844
6845         rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6846         if (rc != 0)
6847                 return (rc);
6848
6849         rc = sysctl_wire_old_buffer(req, 0);
6850         if (rc != 0)
6851                 return (rc);
6852
6853         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6854         if (sb == NULL)
6855                 return (ENOMEM);
6856
6857         buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6858             M_ZERO | M_WAITOK);
6859
6860         rc = -t4_cim_read_la(sc, buf, NULL);
6861         if (rc != 0)
6862                 goto done;
6863
6864         sbuf_printf(sb, "Status   Inst    Data      PC%s",
6865             cfg & F_UPDBGLACAPTPCONLY ? "" :
6866             "     LS0Stat  LS0Addr  LS0Data  LS1Stat  LS1Addr  LS1Data");
6867
6868         for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
6869                 if (cfg & F_UPDBGLACAPTPCONLY) {
6870                         sbuf_printf(sb, "\n  %02x   %08x %08x %08x",
6871                             p[3] & 0xff, p[2], p[1], p[0]);
6872                         sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x %02x%06x",
6873                             (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
6874                             p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
6875                         sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x",
6876                             (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
6877                             p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
6878                             p[6] >> 16);
6879                 } else {
6880                         sbuf_printf(sb, "\n  %02x   %04x%04x %04x%04x %04x%04x "
6881                             "%08x %08x %08x %08x %08x %08x",
6882                             (p[9] >> 16) & 0xff,
6883                             p[9] & 0xffff, p[8] >> 16,
6884                             p[8] & 0xffff, p[7] >> 16,
6885                             p[7] & 0xffff, p[6] >> 16,
6886                             p[2], p[1], p[0], p[5], p[4], p[3]);
6887                 }
6888         }
6889
6890         rc = sbuf_finish(sb);
6891         sbuf_delete(sb);
6892 done:
6893         free(buf, M_CXGBE);
6894         return (rc);
6895 }
6896
6897 static int
6898 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
6899 {
6900         struct adapter *sc = arg1;
6901         u_int i;
6902         struct sbuf *sb;
6903         uint32_t *buf, *p;
6904         int rc;
6905
6906         rc = sysctl_wire_old_buffer(req, 0);
6907         if (rc != 0)
6908                 return (rc);
6909
6910         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6911         if (sb == NULL)
6912                 return (ENOMEM);
6913
6914         buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6915             M_ZERO | M_WAITOK);
6916
6917         t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6918         p = buf;
6919
6920         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6921                 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6922                     p[1], p[0]);
6923         }
6924
6925         sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
6926         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6927                 sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
6928                     (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6929                     (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6930                     (p[1] >> 2) | ((p[2] & 3) << 30),
6931                     (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
6932                     p[0] & 1);
6933         }
6934
6935         rc = sbuf_finish(sb);
6936         sbuf_delete(sb);
6937         free(buf, M_CXGBE);
6938         return (rc);
6939 }
6940
6941 static int
6942 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
6943 {
6944         struct adapter *sc = arg1;
6945         u_int i;
6946         struct sbuf *sb;
6947         uint32_t *buf, *p;
6948         int rc;
6949
6950         rc = sysctl_wire_old_buffer(req, 0);
6951         if (rc != 0)
6952                 return (rc);
6953
6954         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6955         if (sb == NULL)
6956                 return (ENOMEM);
6957
6958         buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
6959             M_ZERO | M_WAITOK);
6960
6961         t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
6962         p = buf;
6963
6964         sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
6965         for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6966                 sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
6967                     (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
6968                     p[4], p[3], p[2], p[1], p[0]);
6969         }
6970
6971         sbuf_printf(sb, "\n\nCntl ID               Data");
6972         for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6973                 sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
6974                     (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
6975         }
6976
6977         rc = sbuf_finish(sb);
6978         sbuf_delete(sb);
6979         free(buf, M_CXGBE);
6980         return (rc);
6981 }
6982
6983 static int
6984 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
6985 {
6986         struct adapter *sc = arg1;
6987         struct sbuf *sb;
6988         int rc, i;
6989         uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6990         uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6991         uint16_t thres[CIM_NUM_IBQ];
6992         uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
6993         uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
6994         u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
6995
6996         cim_num_obq = sc->chip_params->cim_num_obq;
6997         if (is_t4(sc)) {
6998                 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
6999                 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7000         } else {
7001                 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7002                 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7003         }
7004         nq = CIM_NUM_IBQ + cim_num_obq;
7005
7006         rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7007         if (rc == 0)
7008                 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7009         if (rc != 0)
7010                 return (rc);
7011
7012         t4_read_cimq_cfg(sc, base, size, thres);
7013
7014         rc = sysctl_wire_old_buffer(req, 0);
7015         if (rc != 0)
7016                 return (rc);
7017
7018         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7019         if (sb == NULL)
7020                 return (ENOMEM);
7021
7022         sbuf_printf(sb,
7023             "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
7024
7025         for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7026                 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
7027                     qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7028                     G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7029                     G_QUEREMFLITS(p[2]) * 16);
7030         for ( ; i < nq; i++, p += 4, wr += 2)
7031                 sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
7032                     base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7033                     wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7034                     G_QUEREMFLITS(p[2]) * 16);
7035
7036         rc = sbuf_finish(sb);
7037         sbuf_delete(sb);
7038
7039         return (rc);
7040 }
7041
7042 static int
7043 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7044 {
7045         struct adapter *sc = arg1;
7046         struct sbuf *sb;
7047         int rc;
7048         struct tp_cpl_stats stats;
7049
7050         rc = sysctl_wire_old_buffer(req, 0);
7051         if (rc != 0)
7052                 return (rc);
7053
7054         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7055         if (sb == NULL)
7056                 return (ENOMEM);
7057
7058         mtx_lock(&sc->reg_lock);
7059         t4_tp_get_cpl_stats(sc, &stats, 0);
7060         mtx_unlock(&sc->reg_lock);
7061
7062         if (sc->chip_params->nchan > 2) {
7063                 sbuf_printf(sb, "                 channel 0  channel 1"
7064                     "  channel 2  channel 3");
7065                 sbuf_printf(sb, "\nCPL requests:   %10u %10u %10u %10u",
7066                     stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7067                 sbuf_printf(sb, "\nCPL responses:   %10u %10u %10u %10u",
7068                     stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7069         } else {
7070                 sbuf_printf(sb, "                 channel 0  channel 1");
7071                 sbuf_printf(sb, "\nCPL requests:   %10u %10u",
7072                     stats.req[0], stats.req[1]);
7073                 sbuf_printf(sb, "\nCPL responses:   %10u %10u",
7074                     stats.rsp[0], stats.rsp[1]);
7075         }
7076
7077         rc = sbuf_finish(sb);
7078         sbuf_delete(sb);
7079
7080         return (rc);
7081 }
7082
7083 static int
7084 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7085 {
7086         struct adapter *sc = arg1;
7087         struct sbuf *sb;
7088         int rc;
7089         struct tp_usm_stats stats;
7090
7091         rc = sysctl_wire_old_buffer(req, 0);
7092         if (rc != 0)
7093                 return(rc);
7094
7095         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7096         if (sb == NULL)
7097                 return (ENOMEM);
7098
7099         t4_get_usm_stats(sc, &stats, 1);
7100
7101         sbuf_printf(sb, "Frames: %u\n", stats.frames);
7102         sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7103         sbuf_printf(sb, "Drops:  %u", stats.drops);
7104
7105         rc = sbuf_finish(sb);
7106         sbuf_delete(sb);
7107
7108         return (rc);
7109 }
7110
7111 static const char * const devlog_level_strings[] = {
7112         [FW_DEVLOG_LEVEL_EMERG]         = "EMERG",
7113         [FW_DEVLOG_LEVEL_CRIT]          = "CRIT",
7114         [FW_DEVLOG_LEVEL_ERR]           = "ERR",
7115         [FW_DEVLOG_LEVEL_NOTICE]        = "NOTICE",
7116         [FW_DEVLOG_LEVEL_INFO]          = "INFO",
7117         [FW_DEVLOG_LEVEL_DEBUG]         = "DEBUG"
7118 };
7119
7120 static const char * const devlog_facility_strings[] = {
7121         [FW_DEVLOG_FACILITY_CORE]       = "CORE",
7122         [FW_DEVLOG_FACILITY_CF]         = "CF",
7123         [FW_DEVLOG_FACILITY_SCHED]      = "SCHED",
7124         [FW_DEVLOG_FACILITY_TIMER]      = "TIMER",
7125         [FW_DEVLOG_FACILITY_RES]        = "RES",
7126         [FW_DEVLOG_FACILITY_HW]         = "HW",
7127         [FW_DEVLOG_FACILITY_FLR]        = "FLR",
7128         [FW_DEVLOG_FACILITY_DMAQ]       = "DMAQ",
7129         [FW_DEVLOG_FACILITY_PHY]        = "PHY",
7130         [FW_DEVLOG_FACILITY_MAC]        = "MAC",
7131         [FW_DEVLOG_FACILITY_PORT]       = "PORT",
7132         [FW_DEVLOG_FACILITY_VI]         = "VI",
7133         [FW_DEVLOG_FACILITY_FILTER]     = "FILTER",
7134         [FW_DEVLOG_FACILITY_ACL]        = "ACL",
7135         [FW_DEVLOG_FACILITY_TM]         = "TM",
7136         [FW_DEVLOG_FACILITY_QFC]        = "QFC",
7137         [FW_DEVLOG_FACILITY_DCB]        = "DCB",
7138         [FW_DEVLOG_FACILITY_ETH]        = "ETH",
7139         [FW_DEVLOG_FACILITY_OFLD]       = "OFLD",
7140         [FW_DEVLOG_FACILITY_RI]         = "RI",
7141         [FW_DEVLOG_FACILITY_ISCSI]      = "ISCSI",
7142         [FW_DEVLOG_FACILITY_FCOE]       = "FCOE",
7143         [FW_DEVLOG_FACILITY_FOISCSI]    = "FOISCSI",
7144         [FW_DEVLOG_FACILITY_FOFCOE]     = "FOFCOE",
7145         [FW_DEVLOG_FACILITY_CHNET]      = "CHNET",
7146 };
7147
7148 static int
7149 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7150 {
7151         struct adapter *sc = arg1;
7152         struct devlog_params *dparams = &sc->params.devlog;
7153         struct fw_devlog_e *buf, *e;
7154         int i, j, rc, nentries, first = 0;
7155         struct sbuf *sb;
7156         uint64_t ftstamp = UINT64_MAX;
7157
7158         if (dparams->addr == 0)
7159                 return (ENXIO);
7160
7161         buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
7162         if (buf == NULL)
7163                 return (ENOMEM);
7164
7165         rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7166         if (rc != 0)
7167                 goto done;
7168
7169         nentries = dparams->size / sizeof(struct fw_devlog_e);
7170         for (i = 0; i < nentries; i++) {
7171                 e = &buf[i];
7172
7173                 if (e->timestamp == 0)
7174                         break;  /* end */
7175
7176                 e->timestamp = be64toh(e->timestamp);
7177                 e->seqno = be32toh(e->seqno);
7178                 for (j = 0; j < 8; j++)
7179                         e->params[j] = be32toh(e->params[j]);
7180
7181                 if (e->timestamp < ftstamp) {
7182                         ftstamp = e->timestamp;
7183                         first = i;
7184                 }
7185         }
7186
7187         if (buf[first].timestamp == 0)
7188                 goto done;      /* nothing in the log */
7189
7190         rc = sysctl_wire_old_buffer(req, 0);
7191         if (rc != 0)
7192                 goto done;
7193
7194         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7195         if (sb == NULL) {
7196                 rc = ENOMEM;
7197                 goto done;
7198         }
7199         sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
7200             "Seq#", "Tstamp", "Level", "Facility", "Message");
7201
7202         i = first;
7203         do {
7204                 e = &buf[i];
7205                 if (e->timestamp == 0)
7206                         break;  /* end */
7207
7208                 sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
7209                     e->seqno, e->timestamp,
7210                     (e->level < nitems(devlog_level_strings) ?
7211                         devlog_level_strings[e->level] : "UNKNOWN"),
7212                     (e->facility < nitems(devlog_facility_strings) ?
7213                         devlog_facility_strings[e->facility] : "UNKNOWN"));
7214                 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7215                     e->params[2], e->params[3], e->params[4],
7216                     e->params[5], e->params[6], e->params[7]);
7217
7218                 if (++i == nentries)
7219                         i = 0;
7220         } while (i != first);
7221
7222         rc = sbuf_finish(sb);
7223         sbuf_delete(sb);
7224 done:
7225         free(buf, M_CXGBE);
7226         return (rc);
7227 }
7228
7229 static int
7230 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7231 {
7232         struct adapter *sc = arg1;
7233         struct sbuf *sb;
7234         int rc;
7235         struct tp_fcoe_stats stats[MAX_NCHAN];
7236         int i, nchan = sc->chip_params->nchan;
7237
7238         rc = sysctl_wire_old_buffer(req, 0);
7239         if (rc != 0)
7240                 return (rc);
7241
7242         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7243         if (sb == NULL)
7244                 return (ENOMEM);
7245
7246         for (i = 0; i < nchan; i++)
7247                 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7248
7249         if (nchan > 2) {
7250                 sbuf_printf(sb, "                   channel 0        channel 1"
7251                     "        channel 2        channel 3");
7252                 sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju %16ju %16ju",
7253                     stats[0].octets_ddp, stats[1].octets_ddp,
7254                     stats[2].octets_ddp, stats[3].octets_ddp);
7255                 sbuf_printf(sb, "\nframesDDP:  %16u %16u %16u %16u",
7256                     stats[0].frames_ddp, stats[1].frames_ddp,
7257                     stats[2].frames_ddp, stats[3].frames_ddp);
7258                 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7259                     stats[0].frames_drop, stats[1].frames_drop,
7260                     stats[2].frames_drop, stats[3].frames_drop);
7261         } else {
7262                 sbuf_printf(sb, "                   channel 0        channel 1");
7263                 sbuf_printf(sb, "\noctetsDDP:  %16ju %16ju",
7264                     stats[0].octets_ddp, stats[1].octets_ddp);
7265                 sbuf_printf(sb, "\nframesDDP:  %16u %16u",
7266                     stats[0].frames_ddp, stats[1].frames_ddp);
7267                 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7268                     stats[0].frames_drop, stats[1].frames_drop);
7269         }
7270
7271         rc = sbuf_finish(sb);
7272         sbuf_delete(sb);
7273
7274         return (rc);
7275 }
7276
7277 static int
7278 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7279 {
7280         struct adapter *sc = arg1;
7281         struct sbuf *sb;
7282         int rc, i;
7283         unsigned int map, kbps, ipg, mode;
7284         unsigned int pace_tab[NTX_SCHED];
7285
7286         rc = sysctl_wire_old_buffer(req, 0);
7287         if (rc != 0)
7288                 return (rc);
7289
7290         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7291         if (sb == NULL)
7292                 return (ENOMEM);
7293
7294         map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7295         mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7296         t4_read_pace_tbl(sc, pace_tab);
7297
7298         sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
7299             "Class IPG (0.1 ns)   Flow IPG (us)");
7300
7301         for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7302                 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7303                 sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
7304                     (mode & (1 << i)) ? "flow" : "class", map & 3);
7305                 if (kbps)
7306                         sbuf_printf(sb, "%9u     ", kbps);
7307                 else
7308                         sbuf_printf(sb, " disabled     ");
7309
7310                 if (ipg)
7311                         sbuf_printf(sb, "%13u        ", ipg);
7312                 else
7313                         sbuf_printf(sb, "     disabled        ");
7314
7315                 if (pace_tab[i])
7316                         sbuf_printf(sb, "%10u", pace_tab[i]);
7317                 else
7318                         sbuf_printf(sb, "  disabled");
7319         }
7320
7321         rc = sbuf_finish(sb);
7322         sbuf_delete(sb);
7323
7324         return (rc);
7325 }
7326
7327 static int
7328 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7329 {
7330         struct adapter *sc = arg1;
7331         struct sbuf *sb;
7332         int rc, i, j;
7333         uint64_t *p0, *p1;
7334         struct lb_port_stats s[2];
7335         static const char *stat_name[] = {
7336                 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7337                 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7338                 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7339                 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7340                 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7341                 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7342                 "BG2FramesTrunc:", "BG3FramesTrunc:"
7343         };
7344
7345         rc = sysctl_wire_old_buffer(req, 0);
7346         if (rc != 0)
7347                 return (rc);
7348
7349         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7350         if (sb == NULL)
7351                 return (ENOMEM);
7352
7353         memset(s, 0, sizeof(s));
7354
7355         for (i = 0; i < sc->chip_params->nchan; i += 2) {
7356                 t4_get_lb_stats(sc, i, &s[0]);
7357                 t4_get_lb_stats(sc, i + 1, &s[1]);
7358
7359                 p0 = &s[0].octets;
7360                 p1 = &s[1].octets;
7361                 sbuf_printf(sb, "%s                       Loopback %u"
7362                     "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7363
7364                 for (j = 0; j < nitems(stat_name); j++)
7365                         sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7366                                    *p0++, *p1++);
7367         }
7368
7369         rc = sbuf_finish(sb);
7370         sbuf_delete(sb);
7371
7372         return (rc);
7373 }
7374
7375 static int
7376 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7377 {
7378         int rc = 0;
7379         struct port_info *pi = arg1;
7380         struct link_config *lc = &pi->link_cfg;
7381         struct sbuf *sb;
7382
7383         rc = sysctl_wire_old_buffer(req, 0);
7384         if (rc != 0)
7385                 return(rc);
7386         sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7387         if (sb == NULL)
7388                 return (ENOMEM);
7389
7390         if (lc->link_ok || lc->link_down_rc == 255)
7391                 sbuf_printf(sb, "n/a");
7392         else
7393                 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7394
7395         rc = sbuf_finish(sb);
7396         sbuf_delete(sb);
7397
7398         return (rc);
7399 }
7400
7401 struct mem_desc {
7402         unsigned int base;
7403         unsigned int limit;
7404         unsigned int idx;
7405 };
7406
7407 static int
7408 mem_desc_cmp(const void *a, const void *b)
7409 {
7410         return ((const struct mem_desc *)a)->base -
7411                ((const struct mem_desc *)b)->base;
7412 }
7413
7414 static void
7415 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7416     unsigned int to)
7417 {
7418         unsigned int size;
7419
7420         if (from == to)
7421                 return;
7422
7423         size = to - from + 1;
7424         if (size == 0)
7425                 return;
7426
7427         /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7428         sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7429 }
7430
7431 static int
7432 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7433 {
7434         struct adapter *sc = arg1;
7435         struct sbuf *sb;
7436         int rc, i, n;
7437         uint32_t lo, hi, used, alloc;
7438         static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7439         static const char *region[] = {
7440                 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7441                 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7442                 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7443                 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7444                 "RQUDP region:", "PBL region:", "TXPBL region:",
7445                 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7446                 "On-chip queues:"
7447         };
7448         struct mem_desc avail[4];
7449         struct mem_desc mem[nitems(region) + 3];        /* up to 3 holes */
7450         struct mem_desc *md = mem;
7451
7452         rc = sysctl_wire_old_buffer(req, 0);
7453         if (rc != 0)
7454                 return (rc);
7455
7456         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7457         if (sb == NULL)
7458                 return (ENOMEM);
7459
7460         for (i = 0; i < nitems(mem); i++) {
7461                 mem[i].limit = 0;
7462                 mem[i].idx = i;
7463         }
7464
7465         /* Find and sort the populated memory ranges */
7466         i = 0;
7467         lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7468         if (lo & F_EDRAM0_ENABLE) {
7469                 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7470                 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7471                 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7472                 avail[i].idx = 0;
7473                 i++;
7474         }
7475         if (lo & F_EDRAM1_ENABLE) {
7476                 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7477                 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7478                 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7479                 avail[i].idx = 1;
7480                 i++;
7481         }
7482         if (lo & F_EXT_MEM_ENABLE) {
7483                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7484                 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7485                 avail[i].limit = avail[i].base +
7486                     (G_EXT_MEM_SIZE(hi) << 20);
7487                 avail[i].idx = is_t5(sc) ? 3 : 2;       /* Call it MC0 for T5 */
7488                 i++;
7489         }
7490         if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7491                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7492                 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7493                 avail[i].limit = avail[i].base +
7494                     (G_EXT_MEM1_SIZE(hi) << 20);
7495                 avail[i].idx = 4;
7496                 i++;
7497         }
7498         if (!i)                                    /* no memory available */
7499                 return 0;
7500         qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
7501
7502         (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
7503         (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
7504         (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
7505         (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7506         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
7507         (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
7508         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
7509         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
7510         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
7511
7512         /* the next few have explicit upper bounds */
7513         md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
7514         md->limit = md->base - 1 +
7515                     t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
7516                     G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
7517         md++;
7518
7519         md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
7520         md->limit = md->base - 1 +
7521                     t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
7522                     G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
7523         md++;
7524
7525         if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7526                 if (chip_id(sc) <= CHELSIO_T5)
7527                         md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
7528                 else
7529                         md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
7530                 md->limit = 0;
7531         } else {
7532                 md->base = 0;
7533                 md->idx = nitems(region);  /* hide it */
7534         }
7535         md++;
7536
7537 #define ulp_region(reg) \
7538         md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
7539         (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
7540
7541         ulp_region(RX_ISCSI);
7542         ulp_region(RX_TDDP);
7543         ulp_region(TX_TPT);
7544         ulp_region(RX_STAG);
7545         ulp_region(RX_RQ);
7546         ulp_region(RX_RQUDP);
7547         ulp_region(RX_PBL);
7548         ulp_region(TX_PBL);
7549 #undef ulp_region
7550
7551         md->base = 0;
7552         md->idx = nitems(region);
7553         if (!is_t4(sc)) {
7554                 uint32_t size = 0;
7555                 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
7556                 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
7557
7558                 if (is_t5(sc)) {
7559                         if (sge_ctrl & F_VFIFO_ENABLE)
7560                                 size = G_DBVFIFO_SIZE(fifo_size);
7561                 } else
7562                         size = G_T6_DBVFIFO_SIZE(fifo_size);
7563
7564                 if (size) {
7565                         md->base = G_BASEADDR(t4_read_reg(sc,
7566                             A_SGE_DBVFIFO_BADDR));
7567                         md->limit = md->base + (size << 2) - 1;
7568                 }
7569         }
7570         md++;
7571
7572         md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
7573         md->limit = 0;
7574         md++;
7575         md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
7576         md->limit = 0;
7577         md++;
7578
7579         md->base = sc->vres.ocq.start;
7580         if (sc->vres.ocq.size)
7581                 md->limit = md->base + sc->vres.ocq.size - 1;
7582         else
7583                 md->idx = nitems(region);  /* hide it */
7584         md++;
7585
7586         /* add any address-space holes, there can be up to 3 */
7587         for (n = 0; n < i - 1; n++)
7588                 if (avail[n].limit < avail[n + 1].base)
7589                         (md++)->base = avail[n].limit;
7590         if (avail[n].limit)
7591                 (md++)->base = avail[n].limit;
7592
7593         n = md - mem;
7594         qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
7595
7596         for (lo = 0; lo < i; lo++)
7597                 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
7598                                 avail[lo].limit - 1);
7599
7600         sbuf_printf(sb, "\n");
7601         for (i = 0; i < n; i++) {
7602                 if (mem[i].idx >= nitems(region))
7603                         continue;                        /* skip holes */
7604                 if (!mem[i].limit)
7605                         mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
7606                 mem_region_show(sb, region[mem[i].idx], mem[i].base,
7607                                 mem[i].limit);
7608         }
7609
7610         sbuf_printf(sb, "\n");
7611         lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
7612         hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
7613         mem_region_show(sb, "uP RAM:", lo, hi);
7614
7615         lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
7616         hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
7617         mem_region_show(sb, "uP Extmem2:", lo, hi);
7618
7619         lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
7620         sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
7621                    G_PMRXMAXPAGE(lo),
7622                    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
7623                    (lo & F_PMRXNUMCHN) ? 2 : 1);
7624
7625         lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
7626         hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
7627         sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
7628                    G_PMTXMAXPAGE(lo),
7629                    hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
7630                    hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
7631         sbuf_printf(sb, "%u p-structs\n",
7632                    t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
7633
7634         for (i = 0; i < 4; i++) {
7635                 if (chip_id(sc) > CHELSIO_T5)
7636                         lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
7637                 else
7638                         lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
7639                 if (is_t5(sc)) {
7640                         used = G_T5_USED(lo);
7641                         alloc = G_T5_ALLOC(lo);
7642                 } else {
7643                         used = G_USED(lo);
7644                         alloc = G_ALLOC(lo);
7645                 }
7646                 /* For T6 these are MAC buffer groups */
7647                 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
7648                     i, used, alloc);
7649         }
7650         for (i = 0; i < sc->chip_params->nchan; i++) {
7651                 if (chip_id(sc) > CHELSIO_T5)
7652                         lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
7653                 else
7654                         lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
7655                 if (is_t5(sc)) {
7656                         used = G_T5_USED(lo);
7657                         alloc = G_T5_ALLOC(lo);
7658                 } else {
7659                         used = G_USED(lo);
7660                         alloc = G_ALLOC(lo);
7661                 }
7662                 /* For T6 these are MAC buffer groups */
7663                 sbuf_printf(sb,
7664                     "\nLoopback %d using %u pages out of %u allocated",
7665                     i, used, alloc);
7666         }
7667
7668         rc = sbuf_finish(sb);
7669         sbuf_delete(sb);
7670
7671         return (rc);
7672 }
7673
7674 static inline void
7675 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7676 {
7677         *mask = x | y;
7678         y = htobe64(y);
7679         memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7680 }
7681
7682 static int
7683 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7684 {
7685         struct adapter *sc = arg1;
7686         struct sbuf *sb;
7687         int rc, i;
7688
7689         MPASS(chip_id(sc) <= CHELSIO_T5);
7690
7691         rc = sysctl_wire_old_buffer(req, 0);
7692         if (rc != 0)
7693                 return (rc);
7694
7695         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7696         if (sb == NULL)
7697                 return (ENOMEM);
7698
7699         sbuf_printf(sb,
7700             "Idx  Ethernet address     Mask     Vld Ports PF"
7701             "  VF              Replication             P0 P1 P2 P3  ML");
7702         for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7703                 uint64_t tcamx, tcamy, mask;
7704                 uint32_t cls_lo, cls_hi;
7705                 uint8_t addr[ETHER_ADDR_LEN];
7706
7707                 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7708                 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7709                 if (tcamx & tcamy)
7710                         continue;
7711                 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7712                 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7713                 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7714                 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7715                            "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
7716                            addr[3], addr[4], addr[5], (uintmax_t)mask,
7717                            (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7718                            G_PORTMAP(cls_hi), G_PF(cls_lo),
7719                            (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7720
7721                 if (cls_lo & F_REPLICATE) {
7722                         struct fw_ldst_cmd ldst_cmd;
7723
7724                         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7725                         ldst_cmd.op_to_addrspace =
7726                             htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7727                                 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7728                                 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7729                         ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7730                         ldst_cmd.u.mps.rplc.fid_idx =
7731                             htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7732                                 V_FW_LDST_CMD_IDX(i));
7733
7734                         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7735                             "t4mps");
7736                         if (rc)
7737                                 break;
7738                         rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7739                             sizeof(ldst_cmd), &ldst_cmd);
7740                         end_synchronized_op(sc, 0);
7741
7742                         if (rc != 0) {
7743                                 sbuf_printf(sb, "%36d", rc);
7744                                 rc = 0;
7745                         } else {
7746                                 sbuf_printf(sb, " %08x %08x %08x %08x",
7747                                     be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7748                                     be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7749                                     be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7750                                     be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7751                         }
7752                 } else
7753                         sbuf_printf(sb, "%36s", "");
7754
7755                 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
7756                     G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
7757                     G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
7758         }
7759
7760         if (rc)
7761                 (void) sbuf_finish(sb);
7762         else
7763                 rc = sbuf_finish(sb);
7764         sbuf_delete(sb);
7765
7766         return (rc);
7767 }
7768
7769 static int
7770 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
7771 {
7772         struct adapter *sc = arg1;
7773         struct sbuf *sb;
7774         int rc, i;
7775
7776         MPASS(chip_id(sc) > CHELSIO_T5);
7777
7778         rc = sysctl_wire_old_buffer(req, 0);
7779         if (rc != 0)
7780                 return (rc);
7781
7782         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7783         if (sb == NULL)
7784                 return (ENOMEM);
7785
7786         sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
7787             "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
7788             "                           Replication"
7789             "                                    P0 P1 P2 P3  ML\n");
7790
7791         for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7792                 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
7793                 uint16_t ivlan;
7794                 uint64_t tcamx, tcamy, val, mask;
7795                 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
7796                 uint8_t addr[ETHER_ADDR_LEN];
7797
7798                 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
7799                 if (i < 256)
7800                         ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
7801                 else
7802                         ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
7803                 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7804                 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7805                 tcamy = G_DMACH(val) << 32;
7806                 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7807                 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7808                 lookup_type = G_DATALKPTYPE(data2);
7809                 port_num = G_DATAPORTNUM(data2);
7810                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7811                         /* Inner header VNI */
7812                         vniy = ((data2 & F_DATAVIDH2) << 23) |
7813                                        (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7814                         dip_hit = data2 & F_DATADIPHIT;
7815                         vlan_vld = 0;
7816                 } else {
7817                         vniy = 0;
7818                         dip_hit = 0;
7819                         vlan_vld = data2 & F_DATAVIDH2;
7820                         ivlan = G_VIDL(val);
7821                 }
7822
7823                 ctl |= V_CTLXYBITSEL(1);
7824                 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7825                 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7826                 tcamx = G_DMACH(val) << 32;
7827                 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7828                 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7829                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7830                         /* Inner header VNI mask */
7831                         vnix = ((data2 & F_DATAVIDH2) << 23) |
7832                                (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7833                 } else
7834                         vnix = 0;
7835
7836                 if (tcamx & tcamy)
7837                         continue;
7838                 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7839
7840                 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7841                 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7842
7843                 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7844                         sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7845                             "%012jx %06x %06x    -    -   %3c"
7846                             "      'I'  %4x   %3c   %#x%4u%4d", i, addr[0],
7847                             addr[1], addr[2], addr[3], addr[4], addr[5],
7848                             (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
7849                             port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7850                             G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7851                             cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7852                 } else {
7853                         sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7854                             "%012jx    -       -   ", i, addr[0], addr[1],
7855                             addr[2], addr[3], addr[4], addr[5],
7856                             (uintmax_t)mask);
7857
7858                         if (vlan_vld)
7859                                 sbuf_printf(sb, "%4u   Y     ", ivlan);
7860                         else
7861                                 sbuf_printf(sb, "  -    N     ");
7862
7863                         sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
7864                             lookup_type ? 'I' : 'O', port_num,
7865                             cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7866                             G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7867                             cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7868                 }
7869
7870
7871                 if (cls_lo & F_T6_REPLICATE) {
7872                         struct fw_ldst_cmd ldst_cmd;
7873
7874                         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7875                         ldst_cmd.op_to_addrspace =
7876                             htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7877                                 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7878                                 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7879                         ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7880                         ldst_cmd.u.mps.rplc.fid_idx =
7881                             htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7882                                 V_FW_LDST_CMD_IDX(i));
7883
7884                         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7885                             "t6mps");
7886                         if (rc)
7887                                 break;
7888                         rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7889                             sizeof(ldst_cmd), &ldst_cmd);
7890                         end_synchronized_op(sc, 0);
7891
7892                         if (rc != 0) {
7893                                 sbuf_printf(sb, "%72d", rc);
7894                                 rc = 0;
7895                         } else {
7896                                 sbuf_printf(sb, " %08x %08x %08x %08x"
7897                                     " %08x %08x %08x %08x",
7898                                     be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
7899                                     be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
7900                                     be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
7901                                     be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
7902                                     be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7903                                     be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7904                                     be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7905                                     be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7906                         }
7907                 } else
7908                         sbuf_printf(sb, "%72s", "");
7909
7910                 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
7911                     G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
7912                     G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7913                     (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7914         }
7915
7916         if (rc)
7917                 (void) sbuf_finish(sb);
7918         else
7919                 rc = sbuf_finish(sb);
7920         sbuf_delete(sb);
7921
7922         return (rc);
7923 }
7924
7925 static int
7926 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
7927 {
7928         struct adapter *sc = arg1;
7929         struct sbuf *sb;
7930         int rc;
7931         uint16_t mtus[NMTUS];
7932
7933         rc = sysctl_wire_old_buffer(req, 0);
7934         if (rc != 0)
7935                 return (rc);
7936
7937         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7938         if (sb == NULL)
7939                 return (ENOMEM);
7940
7941         t4_read_mtu_tbl(sc, mtus, NULL);
7942
7943         sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
7944             mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
7945             mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
7946             mtus[14], mtus[15]);
7947
7948         rc = sbuf_finish(sb);
7949         sbuf_delete(sb);
7950
7951         return (rc);
7952 }
7953
7954 static int
7955 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
7956 {
7957         struct adapter *sc = arg1;
7958         struct sbuf *sb;
7959         int rc, i;
7960         uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
7961         uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
7962         static const char *tx_stats[MAX_PM_NSTATS] = {
7963                 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
7964                 "Tx FIFO wait", NULL, "Tx latency"
7965         };
7966         static const char *rx_stats[MAX_PM_NSTATS] = {
7967                 "Read:", "Write bypass:", "Write mem:", "Flush:",
7968                 "Rx FIFO wait", NULL, "Rx latency"
7969         };
7970
7971         rc = sysctl_wire_old_buffer(req, 0);
7972         if (rc != 0)
7973                 return (rc);
7974
7975         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7976         if (sb == NULL)
7977                 return (ENOMEM);
7978
7979         t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
7980         t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
7981
7982         sbuf_printf(sb, "                Tx pcmds             Tx bytes");
7983         for (i = 0; i < 4; i++) {
7984                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7985                     tx_cyc[i]);
7986         }
7987
7988         sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
7989         for (i = 0; i < 4; i++) {
7990                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7991                     rx_cyc[i]);
7992         }
7993
7994         if (chip_id(sc) > CHELSIO_T5) {
7995                 sbuf_printf(sb,
7996                     "\n              Total wait      Total occupancy");
7997                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7998                     tx_cyc[i]);
7999                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8000                     rx_cyc[i]);
8001
8002                 i += 2;
8003                 MPASS(i < nitems(tx_stats));
8004
8005                 sbuf_printf(sb,
8006                     "\n                   Reads           Total wait");
8007                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8008                     tx_cyc[i]);
8009                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8010                     rx_cyc[i]);
8011         }
8012
8013         rc = sbuf_finish(sb);
8014         sbuf_delete(sb);
8015
8016         return (rc);
8017 }
8018
8019 static int
8020 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8021 {
8022         struct adapter *sc = arg1;
8023         struct sbuf *sb;
8024         int rc;
8025         struct tp_rdma_stats stats;
8026
8027         rc = sysctl_wire_old_buffer(req, 0);
8028         if (rc != 0)
8029                 return (rc);
8030
8031         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8032         if (sb == NULL)
8033                 return (ENOMEM);
8034
8035         mtx_lock(&sc->reg_lock);
8036         t4_tp_get_rdma_stats(sc, &stats, 0);
8037         mtx_unlock(&sc->reg_lock);
8038
8039         sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8040         sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8041
8042         rc = sbuf_finish(sb);
8043         sbuf_delete(sb);
8044
8045         return (rc);
8046 }
8047
8048 static int
8049 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8050 {
8051         struct adapter *sc = arg1;
8052         struct sbuf *sb;
8053         int rc;
8054         struct tp_tcp_stats v4, v6;
8055
8056         rc = sysctl_wire_old_buffer(req, 0);
8057         if (rc != 0)
8058                 return (rc);
8059
8060         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8061         if (sb == NULL)
8062                 return (ENOMEM);
8063
8064         mtx_lock(&sc->reg_lock);
8065         t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8066         mtx_unlock(&sc->reg_lock);
8067
8068         sbuf_printf(sb,
8069             "                                IP                 IPv6\n");
8070         sbuf_printf(sb, "OutRsts:      %20u %20u\n",
8071             v4.tcp_out_rsts, v6.tcp_out_rsts);
8072         sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
8073             v4.tcp_in_segs, v6.tcp_in_segs);
8074         sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
8075             v4.tcp_out_segs, v6.tcp_out_segs);
8076         sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
8077             v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8078
8079         rc = sbuf_finish(sb);
8080         sbuf_delete(sb);
8081
8082         return (rc);
8083 }
8084
8085 static int
8086 sysctl_tids(SYSCTL_HANDLER_ARGS)
8087 {
8088         struct adapter *sc = arg1;
8089         struct sbuf *sb;
8090         int rc;
8091         struct tid_info *t = &sc->tids;
8092
8093         rc = sysctl_wire_old_buffer(req, 0);
8094         if (rc != 0)
8095                 return (rc);
8096
8097         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8098         if (sb == NULL)
8099                 return (ENOMEM);
8100
8101         if (t->natids) {
8102                 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8103                     t->atids_in_use);
8104         }
8105
8106         if (t->ntids) {
8107                 sbuf_printf(sb, "TID range: ");
8108                 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8109                         uint32_t b, hb;
8110
8111                         if (chip_id(sc) <= CHELSIO_T5) {
8112                                 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8113                                 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8114                         } else {
8115                                 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8116                                 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8117                         }
8118
8119                         if (b)
8120                                 sbuf_printf(sb, "0-%u, ", b - 1);
8121                         sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8122                 } else
8123                         sbuf_printf(sb, "0-%u", t->ntids - 1);
8124                 sbuf_printf(sb, ", in use: %u\n",
8125                     atomic_load_acq_int(&t->tids_in_use));
8126         }
8127
8128         if (t->nstids) {
8129                 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8130                     t->stid_base + t->nstids - 1, t->stids_in_use);
8131         }
8132
8133         if (t->nftids) {
8134                 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
8135                     t->ftid_base + t->nftids - 1);
8136         }
8137
8138         if (t->netids) {
8139                 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
8140                     t->etid_base + t->netids - 1);
8141         }
8142
8143         sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8144             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8145             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8146
8147         rc = sbuf_finish(sb);
8148         sbuf_delete(sb);
8149
8150         return (rc);
8151 }
8152
8153 static int
8154 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8155 {
8156         struct adapter *sc = arg1;
8157         struct sbuf *sb;
8158         int rc;
8159         struct tp_err_stats stats;
8160
8161         rc = sysctl_wire_old_buffer(req, 0);
8162         if (rc != 0)
8163                 return (rc);
8164
8165         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8166         if (sb == NULL)
8167                 return (ENOMEM);
8168
8169         mtx_lock(&sc->reg_lock);
8170         t4_tp_get_err_stats(sc, &stats, 0);
8171         mtx_unlock(&sc->reg_lock);
8172
8173         if (sc->chip_params->nchan > 2) {
8174                 sbuf_printf(sb, "                 channel 0  channel 1"
8175                     "  channel 2  channel 3\n");
8176                 sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
8177                     stats.mac_in_errs[0], stats.mac_in_errs[1],
8178                     stats.mac_in_errs[2], stats.mac_in_errs[3]);
8179                 sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
8180                     stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8181                     stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8182                 sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
8183                     stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8184                     stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8185                 sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
8186                     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8187                     stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8188                 sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
8189                     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8190                     stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8191                 sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
8192                     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8193                     stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8194                 sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
8195                     stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8196                     stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8197                 sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
8198                     stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8199                     stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8200         } else {
8201                 sbuf_printf(sb, "                 channel 0  channel 1\n");
8202                 sbuf_printf(sb, "macInErrs:      %10u %10u\n",
8203                     stats.mac_in_errs[0], stats.mac_in_errs[1]);
8204                 sbuf_printf(sb, "hdrInErrs:      %10u %10u\n",
8205                     stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8206                 sbuf_printf(sb, "tcpInErrs:      %10u %10u\n",
8207                     stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8208                 sbuf_printf(sb, "tcp6InErrs:     %10u %10u\n",
8209                     stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8210                 sbuf_printf(sb, "tnlCongDrops:   %10u %10u\n",
8211                     stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8212                 sbuf_printf(sb, "tnlTxDrops:     %10u %10u\n",
8213                     stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8214                 sbuf_printf(sb, "ofldVlanDrops:  %10u %10u\n",
8215                     stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8216                 sbuf_printf(sb, "ofldChanDrops:  %10u %10u\n\n",
8217                     stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8218         }
8219
8220         sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
8221             stats.ofld_no_neigh, stats.ofld_cong_defer);
8222
8223         rc = sbuf_finish(sb);
8224         sbuf_delete(sb);
8225
8226         return (rc);
8227 }
8228
8229 static int
8230 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8231 {
8232         struct adapter *sc = arg1;
8233         struct tp_params *tpp = &sc->params.tp;
8234         u_int mask;
8235         int rc;
8236
8237         mask = tpp->la_mask >> 16;
8238         rc = sysctl_handle_int(oidp, &mask, 0, req);
8239         if (rc != 0 || req->newptr == NULL)
8240                 return (rc);
8241         if (mask > 0xffff)
8242                 return (EINVAL);
8243         tpp->la_mask = mask << 16;
8244         t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8245
8246         return (0);
8247 }
8248
8249 struct field_desc {
8250         const char *name;
8251         u_int start;
8252         u_int width;
8253 };
8254
8255 static void
8256 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8257 {
8258         char buf[32];
8259         int line_size = 0;
8260
8261         while (f->name) {
8262                 uint64_t mask = (1ULL << f->width) - 1;
8263                 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8264                     ((uintmax_t)v >> f->start) & mask);
8265
8266                 if (line_size + len >= 79) {
8267                         line_size = 8;
8268                         sbuf_printf(sb, "\n        ");
8269                 }
8270                 sbuf_printf(sb, "%s ", buf);
8271                 line_size += len + 1;
8272                 f++;
8273         }
8274         sbuf_printf(sb, "\n");
8275 }
8276
8277 static const struct field_desc tp_la0[] = {
8278         { "RcfOpCodeOut", 60, 4 },
8279         { "State", 56, 4 },
8280         { "WcfState", 52, 4 },
8281         { "RcfOpcSrcOut", 50, 2 },
8282         { "CRxError", 49, 1 },
8283         { "ERxError", 48, 1 },
8284         { "SanityFailed", 47, 1 },
8285         { "SpuriousMsg", 46, 1 },
8286         { "FlushInputMsg", 45, 1 },
8287         { "FlushInputCpl", 44, 1 },
8288         { "RssUpBit", 43, 1 },
8289         { "RssFilterHit", 42, 1 },
8290         { "Tid", 32, 10 },
8291         { "InitTcb", 31, 1 },
8292         { "LineNumber", 24, 7 },
8293         { "Emsg", 23, 1 },
8294         { "EdataOut", 22, 1 },
8295         { "Cmsg", 21, 1 },
8296         { "CdataOut", 20, 1 },
8297         { "EreadPdu", 19, 1 },
8298         { "CreadPdu", 18, 1 },
8299         { "TunnelPkt", 17, 1 },
8300         { "RcfPeerFin", 16, 1 },
8301         { "RcfReasonOut", 12, 4 },
8302         { "TxCchannel", 10, 2 },
8303         { "RcfTxChannel", 8, 2 },
8304         { "RxEchannel", 6, 2 },
8305         { "RcfRxChannel", 5, 1 },
8306         { "RcfDataOutSrdy", 4, 1 },
8307         { "RxDvld", 3, 1 },
8308         { "RxOoDvld", 2, 1 },
8309         { "RxCongestion", 1, 1 },
8310         { "TxCongestion", 0, 1 },
8311         { NULL }
8312 };
8313
8314 static const struct field_desc tp_la1[] = {
8315         { "CplCmdIn", 56, 8 },
8316         { "CplCmdOut", 48, 8 },
8317         { "ESynOut", 47, 1 },
8318         { "EAckOut", 46, 1 },
8319         { "EFinOut", 45, 1 },
8320         { "ERstOut", 44, 1 },
8321         { "SynIn", 43, 1 },
8322         { "AckIn", 42, 1 },
8323         { "FinIn", 41, 1 },
8324         { "RstIn", 40, 1 },
8325         { "DataIn", 39, 1 },
8326         { "DataInVld", 38, 1 },
8327         { "PadIn", 37, 1 },
8328         { "RxBufEmpty", 36, 1 },
8329         { "RxDdp", 35, 1 },
8330         { "RxFbCongestion", 34, 1 },
8331         { "TxFbCongestion", 33, 1 },
8332         { "TxPktSumSrdy", 32, 1 },
8333         { "RcfUlpType", 28, 4 },
8334         { "Eread", 27, 1 },
8335         { "Ebypass", 26, 1 },
8336         { "Esave", 25, 1 },
8337         { "Static0", 24, 1 },
8338         { "Cread", 23, 1 },
8339         { "Cbypass", 22, 1 },
8340         { "Csave", 21, 1 },
8341         { "CPktOut", 20, 1 },
8342         { "RxPagePoolFull", 18, 2 },
8343         { "RxLpbkPkt", 17, 1 },
8344         { "TxLpbkPkt", 16, 1 },
8345         { "RxVfValid", 15, 1 },
8346         { "SynLearned", 14, 1 },
8347         { "SetDelEntry", 13, 1 },
8348         { "SetInvEntry", 12, 1 },
8349         { "CpcmdDvld", 11, 1 },
8350         { "CpcmdSave", 10, 1 },
8351         { "RxPstructsFull", 8, 2 },
8352         { "EpcmdDvld", 7, 1 },
8353         { "EpcmdFlush", 6, 1 },
8354         { "EpcmdTrimPrefix", 5, 1 },
8355         { "EpcmdTrimPostfix", 4, 1 },
8356         { "ERssIp4Pkt", 3, 1 },
8357         { "ERssIp6Pkt", 2, 1 },
8358         { "ERssTcpUdpPkt", 1, 1 },
8359         { "ERssFceFipPkt", 0, 1 },
8360         { NULL }
8361 };
8362
8363 static const struct field_desc tp_la2[] = {
8364         { "CplCmdIn", 56, 8 },
8365         { "MpsVfVld", 55, 1 },
8366         { "MpsPf", 52, 3 },
8367         { "MpsVf", 44, 8 },
8368         { "SynIn", 43, 1 },
8369         { "AckIn", 42, 1 },
8370         { "FinIn", 41, 1 },
8371         { "RstIn", 40, 1 },
8372         { "DataIn", 39, 1 },
8373         { "DataInVld", 38, 1 },
8374         { "PadIn", 37, 1 },
8375         { "RxBufEmpty", 36, 1 },
8376         { "RxDdp", 35, 1 },
8377         { "RxFbCongestion", 34, 1 },
8378         { "TxFbCongestion", 33, 1 },
8379         { "TxPktSumSrdy", 32, 1 },
8380         { "RcfUlpType", 28, 4 },
8381         { "Eread", 27, 1 },
8382         { "Ebypass", 26, 1 },
8383         { "Esave", 25, 1 },
8384         { "Static0", 24, 1 },
8385         { "Cread", 23, 1 },
8386         { "Cbypass", 22, 1 },
8387         { "Csave", 21, 1 },
8388         { "CPktOut", 20, 1 },
8389         { "RxPagePoolFull", 18, 2 },
8390         { "RxLpbkPkt", 17, 1 },
8391         { "TxLpbkPkt", 16, 1 },
8392         { "RxVfValid", 15, 1 },
8393         { "SynLearned", 14, 1 },
8394         { "SetDelEntry", 13, 1 },
8395         { "SetInvEntry", 12, 1 },
8396         { "CpcmdDvld", 11, 1 },
8397         { "CpcmdSave", 10, 1 },
8398         { "RxPstructsFull", 8, 2 },
8399         { "EpcmdDvld", 7, 1 },
8400         { "EpcmdFlush", 6, 1 },
8401         { "EpcmdTrimPrefix", 5, 1 },
8402         { "EpcmdTrimPostfix", 4, 1 },
8403         { "ERssIp4Pkt", 3, 1 },
8404         { "ERssIp6Pkt", 2, 1 },
8405         { "ERssTcpUdpPkt", 1, 1 },
8406         { "ERssFceFipPkt", 0, 1 },
8407         { NULL }
8408 };
8409
8410 static void
8411 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8412 {
8413
8414         field_desc_show(sb, *p, tp_la0);
8415 }
8416
8417 static void
8418 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8419 {
8420
8421         if (idx)
8422                 sbuf_printf(sb, "\n");
8423         field_desc_show(sb, p[0], tp_la0);
8424         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8425                 field_desc_show(sb, p[1], tp_la0);
8426 }
8427
8428 static void
8429 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8430 {
8431
8432         if (idx)
8433                 sbuf_printf(sb, "\n");
8434         field_desc_show(sb, p[0], tp_la0);
8435         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8436                 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8437 }
8438
8439 static int
8440 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8441 {
8442         struct adapter *sc = arg1;
8443         struct sbuf *sb;
8444         uint64_t *buf, *p;
8445         int rc;
8446         u_int i, inc;
8447         void (*show_func)(struct sbuf *, uint64_t *, int);
8448
8449         rc = sysctl_wire_old_buffer(req, 0);
8450         if (rc != 0)
8451                 return (rc);
8452
8453         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8454         if (sb == NULL)
8455                 return (ENOMEM);
8456
8457         buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8458
8459         t4_tp_read_la(sc, buf, NULL);
8460         p = buf;
8461
8462         switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8463         case 2:
8464                 inc = 2;
8465                 show_func = tp_la_show2;
8466                 break;
8467         case 3:
8468                 inc = 2;
8469                 show_func = tp_la_show3;
8470                 break;
8471         default:
8472                 inc = 1;
8473                 show_func = tp_la_show;
8474         }
8475
8476         for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8477                 (*show_func)(sb, p, i);
8478
8479         rc = sbuf_finish(sb);
8480         sbuf_delete(sb);
8481         free(buf, M_CXGBE);
8482         return (rc);
8483 }
8484
8485 static int
8486 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
8487 {
8488         struct adapter *sc = arg1;
8489         struct sbuf *sb;
8490         int rc;
8491         u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
8492
8493         rc = sysctl_wire_old_buffer(req, 0);
8494         if (rc != 0)
8495                 return (rc);
8496
8497         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8498         if (sb == NULL)
8499                 return (ENOMEM);
8500
8501         t4_get_chan_txrate(sc, nrate, orate);
8502
8503         if (sc->chip_params->nchan > 2) {
8504                 sbuf_printf(sb, "              channel 0   channel 1"
8505                     "   channel 2   channel 3\n");
8506                 sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
8507                     nrate[0], nrate[1], nrate[2], nrate[3]);
8508                 sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
8509                     orate[0], orate[1], orate[2], orate[3]);
8510         } else {
8511                 sbuf_printf(sb, "              channel 0   channel 1\n");
8512                 sbuf_printf(sb, "NIC B/s:     %10ju  %10ju\n",
8513                     nrate[0], nrate[1]);
8514                 sbuf_printf(sb, "Offload B/s: %10ju  %10ju",
8515                     orate[0], orate[1]);
8516         }
8517
8518         rc = sbuf_finish(sb);
8519         sbuf_delete(sb);
8520
8521         return (rc);
8522 }
8523
8524 static int
8525 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
8526 {
8527         struct adapter *sc = arg1;
8528         struct sbuf *sb;
8529         uint32_t *buf, *p;
8530         int rc, i;
8531
8532         rc = sysctl_wire_old_buffer(req, 0);
8533         if (rc != 0)
8534                 return (rc);
8535
8536         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8537         if (sb == NULL)
8538                 return (ENOMEM);
8539
8540         buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
8541             M_ZERO | M_WAITOK);
8542
8543         t4_ulprx_read_la(sc, buf);
8544         p = buf;
8545
8546         sbuf_printf(sb, "      Pcmd        Type   Message"
8547             "                Data");
8548         for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
8549                 sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
8550                     p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
8551         }
8552
8553         rc = sbuf_finish(sb);
8554         sbuf_delete(sb);
8555         free(buf, M_CXGBE);
8556         return (rc);
8557 }
8558
8559 static int
8560 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
8561 {
8562         struct adapter *sc = arg1;
8563         struct sbuf *sb;
8564         int rc, v;
8565
8566         MPASS(chip_id(sc) >= CHELSIO_T5);
8567
8568         rc = sysctl_wire_old_buffer(req, 0);
8569         if (rc != 0)
8570                 return (rc);
8571
8572         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8573         if (sb == NULL)
8574                 return (ENOMEM);
8575
8576         v = t4_read_reg(sc, A_SGE_STAT_CFG);
8577         if (G_STATSOURCE_T5(v) == 7) {
8578                 int mode;
8579
8580                 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
8581                 if (mode == 0) {
8582                         sbuf_printf(sb, "total %d, incomplete %d",
8583                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
8584                             t4_read_reg(sc, A_SGE_STAT_MATCH));
8585                 } else if (mode == 1) {
8586                         sbuf_printf(sb, "total %d, data overflow %d",
8587                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
8588                             t4_read_reg(sc, A_SGE_STAT_MATCH));
8589                 } else {
8590                         sbuf_printf(sb, "unknown mode %d", mode);
8591                 }
8592         }
8593         rc = sbuf_finish(sb);
8594         sbuf_delete(sb);
8595
8596         return (rc);
8597 }
8598
8599 static int
8600 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
8601 {
8602         struct adapter *sc = arg1;
8603         struct tx_cl_rl_params tc;
8604         struct sbuf *sb;
8605         int i, rc, port_id, mbps, gbps;
8606
8607         rc = sysctl_wire_old_buffer(req, 0);
8608         if (rc != 0)
8609                 return (rc);
8610
8611         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8612         if (sb == NULL)
8613                 return (ENOMEM);
8614
8615         port_id = arg2 >> 16;
8616         MPASS(port_id < sc->params.nports);
8617         MPASS(sc->port[port_id] != NULL);
8618         i = arg2 & 0xffff;
8619         MPASS(i < sc->chip_params->nsched_cls);
8620
8621         mtx_lock(&sc->tc_lock);
8622         tc = sc->port[port_id]->sched_params->cl_rl[i];
8623         mtx_unlock(&sc->tc_lock);
8624
8625         if (tc.flags & TX_CLRL_ERROR) {
8626                 sbuf_printf(sb, "error");
8627                 goto done;
8628         }
8629
8630         if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) {
8631                 /* XXX: top speed or actual link speed? */
8632                 gbps = port_top_speed(sc->port[port_id]);
8633                 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps);
8634         } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) {
8635                 switch (tc.rateunit) {
8636                 case SCHED_CLASS_RATEUNIT_BITS:
8637                         mbps = tc.maxrate / 1000;
8638                         gbps = tc.maxrate / 1000000;
8639                         if (tc.maxrate == gbps * 1000000)
8640                                 sbuf_printf(sb, " %uGbps", gbps);
8641                         else if (tc.maxrate == mbps * 1000)
8642                                 sbuf_printf(sb, " %uMbps", mbps);
8643                         else
8644                                 sbuf_printf(sb, " %uKbps", tc.maxrate);
8645                         break;
8646                 case SCHED_CLASS_RATEUNIT_PKTS:
8647                         sbuf_printf(sb, " %upps", tc.maxrate);
8648                         break;
8649                 default:
8650                         rc = ENXIO;
8651                         goto done;
8652                 }
8653         }
8654
8655         switch (tc.mode) {
8656         case SCHED_CLASS_MODE_CLASS:
8657                 sbuf_printf(sb, " aggregate");
8658                 break;
8659         case SCHED_CLASS_MODE_FLOW:
8660                 sbuf_printf(sb, " per-flow");
8661                 break;
8662         default:
8663                 rc = ENXIO;
8664                 goto done;
8665         }
8666
8667 done:
8668         if (rc == 0)
8669                 rc = sbuf_finish(sb);
8670         sbuf_delete(sb);
8671
8672         return (rc);
8673 }
8674 #endif
8675
8676 #ifdef TCP_OFFLOAD
8677 static void
8678 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8679 {
8680         u_int rem = val % factor;
8681
8682         if (rem == 0)
8683                 snprintf(buf, len, "%u", val / factor);
8684         else {
8685                 while (rem % 10 == 0)
8686                         rem /= 10;
8687                 snprintf(buf, len, "%u.%u", val / factor, rem);
8688         }
8689 }
8690
8691 static int
8692 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8693 {
8694         struct adapter *sc = arg1;
8695         char buf[16];
8696         u_int res, re;
8697         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8698
8699         res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8700         switch (arg2) {
8701         case 0:
8702                 /* timer_tick */
8703                 re = G_TIMERRESOLUTION(res);
8704                 break;
8705         case 1:
8706                 /* TCP timestamp tick */
8707                 re = G_TIMESTAMPRESOLUTION(res);
8708                 break;
8709         case 2:
8710                 /* DACK tick */
8711                 re = G_DELAYEDACKRESOLUTION(res);
8712                 break;
8713         default:
8714                 return (EDOOFUS);
8715         }
8716
8717         unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
8718
8719         return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
8720 }
8721
8722 static int
8723 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
8724 {
8725         struct adapter *sc = arg1;
8726         u_int res, dack_re, v;
8727         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8728
8729         res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8730         dack_re = G_DELAYEDACKRESOLUTION(res);
8731         v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
8732
8733         return (sysctl_handle_int(oidp, &v, 0, req));
8734 }
8735
8736 static int
8737 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
8738 {
8739         struct adapter *sc = arg1;
8740         int reg = arg2;
8741         u_int tre;
8742         u_long tp_tick_us, v;
8743         u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8744
8745         MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
8746             reg == A_TP_PERS_MIN  || reg == A_TP_PERS_MAX ||
8747             reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
8748             reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
8749
8750         tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
8751         tp_tick_us = (cclk_ps << tre) / 1000000;
8752
8753         if (reg == A_TP_INIT_SRTT)
8754                 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
8755         else
8756                 v = tp_tick_us * t4_read_reg(sc, reg);
8757
8758         return (sysctl_handle_long(oidp, &v, 0, req));
8759 }
8760
8761 /*
8762  * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
8763  * passed to this function.
8764  */
8765 static int
8766 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
8767 {
8768         struct adapter *sc = arg1;
8769         int idx = arg2;
8770         u_int v;
8771
8772         MPASS(idx >= 0 && idx <= 24);
8773
8774         v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
8775
8776         return (sysctl_handle_int(oidp, &v, 0, req));
8777 }
8778
8779 static int
8780 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
8781 {
8782         struct adapter *sc = arg1;
8783         int idx = arg2;
8784         u_int shift, v, r;
8785
8786         MPASS(idx >= 0 && idx < 16);
8787
8788         r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
8789         shift = (idx & 3) << 3;
8790         v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
8791
8792         return (sysctl_handle_int(oidp, &v, 0, req));
8793 }
8794
8795 static int
8796 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
8797 {
8798         struct vi_info *vi = arg1;
8799         struct adapter *sc = vi->pi->adapter;
8800         int idx, rc, i;
8801         struct sge_ofld_rxq *ofld_rxq;
8802         uint8_t v;
8803
8804         idx = vi->ofld_tmr_idx;
8805
8806         rc = sysctl_handle_int(oidp, &idx, 0, req);
8807         if (rc != 0 || req->newptr == NULL)
8808                 return (rc);
8809
8810         if (idx < 0 || idx >= SGE_NTIMERS)
8811                 return (EINVAL);
8812
8813         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8814             "t4otmr");
8815         if (rc)
8816                 return (rc);
8817
8818         v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
8819         for_each_ofld_rxq(vi, i, ofld_rxq) {
8820 #ifdef atomic_store_rel_8
8821                 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
8822 #else
8823                 ofld_rxq->iq.intr_params = v;
8824 #endif
8825         }
8826         vi->ofld_tmr_idx = idx;
8827
8828         end_synchronized_op(sc, LOCK_HELD);
8829         return (0);
8830 }
8831
8832 static int
8833 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
8834 {
8835         struct vi_info *vi = arg1;
8836         struct adapter *sc = vi->pi->adapter;
8837         int idx, rc;
8838
8839         idx = vi->ofld_pktc_idx;
8840
8841         rc = sysctl_handle_int(oidp, &idx, 0, req);
8842         if (rc != 0 || req->newptr == NULL)
8843                 return (rc);
8844
8845         if (idx < -1 || idx >= SGE_NCOUNTERS)
8846                 return (EINVAL);
8847
8848         rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8849             "t4opktc");
8850         if (rc)
8851                 return (rc);
8852
8853         if (vi->flags & VI_INIT_DONE)
8854                 rc = EBUSY; /* cannot be changed once the queues are created */
8855         else
8856                 vi->ofld_pktc_idx = idx;
8857
8858         end_synchronized_op(sc, LOCK_HELD);
8859         return (rc);
8860 }
8861 #endif
8862
8863 static uint32_t
8864 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
8865 {
8866         uint32_t mode;
8867
8868         mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
8869             T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
8870
8871         if (fconf & F_FRAGMENTATION)
8872                 mode |= T4_FILTER_IP_FRAGMENT;
8873
8874         if (fconf & F_MPSHITTYPE)
8875                 mode |= T4_FILTER_MPS_HIT_TYPE;
8876
8877         if (fconf & F_MACMATCH)
8878                 mode |= T4_FILTER_MAC_IDX;
8879
8880         if (fconf & F_ETHERTYPE)
8881                 mode |= T4_FILTER_ETH_TYPE;
8882
8883         if (fconf & F_PROTOCOL)
8884                 mode |= T4_FILTER_IP_PROTO;
8885
8886         if (fconf & F_TOS)
8887                 mode |= T4_FILTER_IP_TOS;
8888
8889         if (fconf & F_VLAN)
8890                 mode |= T4_FILTER_VLAN;
8891
8892         if (fconf & F_VNIC_ID) {
8893                 mode |= T4_FILTER_VNIC;
8894                 if (iconf & F_VNIC)
8895                         mode |= T4_FILTER_IC_VNIC;
8896         }
8897
8898         if (fconf & F_PORT)
8899                 mode |= T4_FILTER_PORT;
8900
8901         if (fconf & F_FCOE)
8902                 mode |= T4_FILTER_FCoE;
8903
8904         return (mode);
8905 }
8906
8907 static uint32_t
8908 mode_to_fconf(uint32_t mode)
8909 {
8910         uint32_t fconf = 0;
8911
8912         if (mode & T4_FILTER_IP_FRAGMENT)
8913                 fconf |= F_FRAGMENTATION;
8914
8915         if (mode & T4_FILTER_MPS_HIT_TYPE)
8916                 fconf |= F_MPSHITTYPE;
8917
8918         if (mode & T4_FILTER_MAC_IDX)
8919                 fconf |= F_MACMATCH;
8920
8921         if (mode & T4_FILTER_ETH_TYPE)
8922                 fconf |= F_ETHERTYPE;
8923
8924         if (mode & T4_FILTER_IP_PROTO)
8925                 fconf |= F_PROTOCOL;
8926
8927         if (mode & T4_FILTER_IP_TOS)
8928                 fconf |= F_TOS;
8929
8930         if (mode & T4_FILTER_VLAN)
8931                 fconf |= F_VLAN;
8932
8933         if (mode & T4_FILTER_VNIC)
8934                 fconf |= F_VNIC_ID;
8935
8936         if (mode & T4_FILTER_PORT)
8937                 fconf |= F_PORT;
8938
8939         if (mode & T4_FILTER_FCoE)
8940                 fconf |= F_FCOE;
8941
8942         return (fconf);
8943 }
8944
8945 static uint32_t
8946 mode_to_iconf(uint32_t mode)
8947 {
8948
8949         if (mode & T4_FILTER_IC_VNIC)
8950                 return (F_VNIC);
8951         return (0);
8952 }
8953
8954 static int check_fspec_against_fconf_iconf(struct adapter *sc,
8955     struct t4_filter_specification *fs)
8956 {
8957         struct tp_params *tpp = &sc->params.tp;
8958         uint32_t fconf = 0;
8959
8960         if (fs->val.frag || fs->mask.frag)
8961                 fconf |= F_FRAGMENTATION;
8962
8963         if (fs->val.matchtype || fs->mask.matchtype)
8964                 fconf |= F_MPSHITTYPE;
8965
8966         if (fs->val.macidx || fs->mask.macidx)
8967                 fconf |= F_MACMATCH;
8968
8969         if (fs->val.ethtype || fs->mask.ethtype)
8970                 fconf |= F_ETHERTYPE;
8971
8972         if (fs->val.proto || fs->mask.proto)
8973                 fconf |= F_PROTOCOL;
8974
8975         if (fs->val.tos || fs->mask.tos)
8976                 fconf |= F_TOS;
8977
8978         if (fs->val.vlan_vld || fs->mask.vlan_vld)
8979                 fconf |= F_VLAN;
8980
8981         if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
8982                 fconf |= F_VNIC_ID;
8983                 if (tpp->ingress_config & F_VNIC)
8984                         return (EINVAL);
8985         }
8986
8987         if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
8988                 fconf |= F_VNIC_ID;
8989                 if ((tpp->ingress_config & F_VNIC) == 0)
8990                         return (EINVAL);
8991         }
8992
8993         if (fs->val.iport || fs->mask.iport)
8994                 fconf |= F_PORT;
8995
8996         if (fs->val.fcoe || fs->mask.fcoe)
8997                 fconf |= F_FCOE;
8998
8999         if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
9000                 return (E2BIG);
9001
9002         return (0);
9003 }
9004
9005 static int
9006 get_filter_mode(struct adapter *sc, uint32_t *mode)
9007 {
9008         struct tp_params *tpp = &sc->params.tp;
9009
9010         /*
9011          * We trust the cached values of the relevant TP registers.  This means
9012          * things work reliably only if writes to those registers are always via
9013          * t4_set_filter_mode.
9014          */
9015         *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
9016
9017         return (0);
9018 }
9019
9020 static int
9021 set_filter_mode(struct adapter *sc, uint32_t mode)
9022 {
9023         struct tp_params *tpp = &sc->params.tp;
9024         uint32_t fconf, iconf;
9025         int rc;
9026
9027         iconf = mode_to_iconf(mode);
9028         if ((iconf ^ tpp->ingress_config) & F_VNIC) {
9029                 /*
9030                  * For now we just complain if A_TP_INGRESS_CONFIG is not
9031                  * already set to the correct value for the requested filter
9032                  * mode.  It's not clear if it's safe to write to this register
9033                  * on the fly.  (And we trust the cached value of the register).
9034                  */
9035                 return (EBUSY);
9036         }
9037
9038         fconf = mode_to_fconf(mode);
9039
9040         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
9041             "t4setfm");
9042         if (rc)
9043                 return (rc);
9044
9045         if (sc->tids.ftids_in_use > 0) {
9046                 rc = EBUSY;
9047                 goto done;
9048         }
9049
9050 #ifdef TCP_OFFLOAD
9051         if (uld_active(sc, ULD_TOM)) {
9052                 rc = EBUSY;
9053                 goto done;
9054         }
9055 #endif
9056
9057         rc = -t4_set_filter_mode(sc, fconf, true);
9058 done:
9059         end_synchronized_op(sc, LOCK_HELD);
9060         return (rc);
9061 }
9062
9063 static inline uint64_t
9064 get_filter_hits(struct adapter *sc, uint32_t fid)
9065 {
9066         uint32_t tcb_addr;
9067
9068         tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
9069             (fid + sc->tids.ftid_base) * TCB_SIZE;
9070
9071         if (is_t4(sc)) {
9072                 uint64_t hits;
9073
9074                 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
9075                 return (be64toh(hits));
9076         } else {
9077                 uint32_t hits;
9078
9079                 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
9080                 return (be32toh(hits));
9081         }
9082 }
9083
9084 static int
9085 get_filter(struct adapter *sc, struct t4_filter *t)
9086 {
9087         int i, rc, nfilters = sc->tids.nftids;
9088         struct filter_entry *f;
9089
9090         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
9091             "t4getf");
9092         if (rc)
9093                 return (rc);
9094
9095         if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
9096             t->idx >= nfilters) {
9097                 t->idx = 0xffffffff;
9098                 goto done;
9099         }
9100
9101         f = &sc->tids.ftid_tab[t->idx];
9102         for (i = t->idx; i < nfilters; i++, f++) {
9103                 if (f->valid) {
9104                         t->idx = i;
9105                         t->l2tidx = f->l2t ? f->l2t->idx : 0;
9106                         t->smtidx = f->smtidx;
9107                         if (f->fs.hitcnts)
9108                                 t->hits = get_filter_hits(sc, t->idx);
9109                         else
9110                                 t->hits = UINT64_MAX;
9111                         t->fs = f->fs;
9112
9113                         goto done;
9114                 }
9115         }
9116
9117         t->idx = 0xffffffff;
9118 done:
9119         end_synchronized_op(sc, LOCK_HELD);
9120         return (0);
9121 }
9122
9123 static int
9124 set_filter(struct adapter *sc, struct t4_filter *t)
9125 {
9126         unsigned int nfilters, nports;
9127         struct filter_entry *f;
9128         int i, rc;
9129
9130         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
9131         if (rc)
9132                 return (rc);
9133
9134         nfilters = sc->tids.nftids;
9135         nports = sc->params.nports;
9136
9137         if (nfilters == 0) {
9138                 rc = ENOTSUP;
9139                 goto done;
9140         }
9141
9142         if (t->idx >= nfilters) {
9143                 rc = EINVAL;
9144                 goto done;
9145         }
9146
9147         /* Validate against the global filter mode and ingress config */
9148         rc = check_fspec_against_fconf_iconf(sc, &t->fs);
9149         if (rc != 0)
9150                 goto done;
9151
9152         if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
9153                 rc = EINVAL;
9154                 goto done;
9155         }
9156
9157         if (t->fs.val.iport >= nports) {
9158                 rc = EINVAL;
9159                 goto done;
9160         }
9161
9162         /* Can't specify an iq if not steering to it */
9163         if (!t->fs.dirsteer && t->fs.iq) {
9164                 rc = EINVAL;
9165                 goto done;
9166         }
9167
9168         /* IPv6 filter idx must be 4 aligned */
9169         if (t->fs.type == 1 &&
9170             ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
9171                 rc = EINVAL;
9172                 goto done;
9173         }
9174
9175         if (!(sc->flags & FULL_INIT_DONE) &&
9176             ((rc = adapter_full_init(sc)) != 0))
9177                 goto done;
9178
9179         if (sc->tids.ftid_tab == NULL) {
9180                 KASSERT(sc->tids.ftids_in_use == 0,
9181                     ("%s: no memory allocated but filters_in_use > 0",
9182                     __func__));
9183
9184                 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
9185                     nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
9186                 if (sc->tids.ftid_tab == NULL) {
9187                         rc = ENOMEM;
9188                         goto done;
9189                 }
9190                 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
9191         }
9192
9193         for (i = 0; i < 4; i++) {
9194                 f = &sc->tids.ftid_tab[t->idx + i];
9195
9196                 if (f->pending || f->valid) {
9197                         rc = EBUSY;
9198                         goto done;
9199                 }
9200                 if (f->locked) {
9201                         rc = EPERM;
9202                         goto done;
9203                 }
9204
9205                 if (t->fs.type == 0)
9206                         break;
9207         }
9208
9209         f = &sc->tids.ftid_tab[t->idx];
9210         f->fs = t->fs;
9211
9212         rc = set_filter_wr(sc, t->idx);
9213 done:
9214         end_synchronized_op(sc, 0);
9215
9216         if (rc == 0) {
9217                 mtx_lock(&sc->tids.ftid_lock);
9218                 for (;;) {
9219                         if (f->pending == 0) {
9220                                 rc = f->valid ? 0 : EIO;
9221                                 break;
9222                         }
9223
9224                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
9225                             PCATCH, "t4setfw", 0)) {
9226                                 rc = EINPROGRESS;
9227                                 break;
9228                         }
9229                 }
9230                 mtx_unlock(&sc->tids.ftid_lock);
9231         }
9232         return (rc);
9233 }
9234
9235 static int
9236 del_filter(struct adapter *sc, struct t4_filter *t)
9237 {
9238         unsigned int nfilters;
9239         struct filter_entry *f;
9240         int rc;
9241
9242         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
9243         if (rc)
9244                 return (rc);
9245
9246         nfilters = sc->tids.nftids;
9247
9248         if (nfilters == 0) {
9249                 rc = ENOTSUP;
9250                 goto done;
9251         }
9252
9253         if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
9254             t->idx >= nfilters) {
9255                 rc = EINVAL;
9256                 goto done;
9257         }
9258
9259         if (!(sc->flags & FULL_INIT_DONE)) {
9260                 rc = EAGAIN;
9261                 goto done;
9262         }
9263
9264         f = &sc->tids.ftid_tab[t->idx];
9265
9266         if (f->pending) {
9267                 rc = EBUSY;
9268                 goto done;
9269         }
9270         if (f->locked) {
9271                 rc = EPERM;
9272                 goto done;
9273         }
9274
9275         if (f->valid) {
9276                 t->fs = f->fs;  /* extra info for the caller */
9277                 rc = del_filter_wr(sc, t->idx);
9278         }
9279
9280 done:
9281         end_synchronized_op(sc, 0);
9282
9283         if (rc == 0) {
9284                 mtx_lock(&sc->tids.ftid_lock);
9285                 for (;;) {
9286                         if (f->pending == 0) {
9287                                 rc = f->valid ? EIO : 0;
9288                                 break;
9289                         }
9290
9291                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
9292                             PCATCH, "t4delfw", 0)) {
9293                                 rc = EINPROGRESS;
9294                                 break;
9295                         }
9296                 }
9297                 mtx_unlock(&sc->tids.ftid_lock);
9298         }
9299
9300         return (rc);
9301 }
9302
9303 static void
9304 clear_filter(struct filter_entry *f)
9305 {
9306         if (f->l2t)
9307                 t4_l2t_release(f->l2t);
9308
9309         bzero(f, sizeof (*f));
9310 }
9311
9312 static int
9313 set_filter_wr(struct adapter *sc, int fidx)
9314 {
9315         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
9316         struct fw_filter_wr *fwr;
9317         unsigned int ftid, vnic_vld, vnic_vld_mask;
9318         struct wrq_cookie cookie;
9319
9320         ASSERT_SYNCHRONIZED_OP(sc);
9321
9322         if (f->fs.newdmac || f->fs.newvlan) {
9323                 /* This filter needs an L2T entry; allocate one. */
9324                 f->l2t = t4_l2t_alloc_switching(sc->l2t);
9325                 if (f->l2t == NULL)
9326                         return (EAGAIN);
9327                 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
9328                     f->fs.dmac)) {
9329                         t4_l2t_release(f->l2t);
9330                         f->l2t = NULL;
9331                         return (ENOMEM);
9332                 }
9333         }
9334
9335         /* Already validated against fconf, iconf */
9336         MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
9337         MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
9338         if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
9339                 vnic_vld = 1;
9340         else
9341                 vnic_vld = 0;
9342         if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
9343                 vnic_vld_mask = 1;
9344         else
9345                 vnic_vld_mask = 0;
9346
9347         ftid = sc->tids.ftid_base + fidx;
9348
9349         fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
9350         if (fwr == NULL)
9351                 return (ENOMEM);
9352         bzero(fwr, sizeof(*fwr));
9353
9354         fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
9355         fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
9356         fwr->tid_to_iq =
9357             htobe32(V_FW_FILTER_WR_TID(ftid) |
9358                 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
9359                 V_FW_FILTER_WR_NOREPLY(0) |
9360                 V_FW_FILTER_WR_IQ(f->fs.iq));
9361         fwr->del_filter_to_l2tix =
9362             htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
9363                 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
9364                 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
9365                 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
9366                 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
9367                 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
9368                 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
9369                 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
9370                 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
9371                     f->fs.newvlan == VLAN_REWRITE) |
9372                 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
9373                     f->fs.newvlan == VLAN_REWRITE) |
9374                 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
9375                 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
9376                 V_FW_FILTER_WR_PRIO(f->fs.prio) |
9377                 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
9378         fwr->ethtype = htobe16(f->fs.val.ethtype);
9379         fwr->ethtypem = htobe16(f->fs.mask.ethtype);
9380         fwr->frag_to_ovlan_vldm =
9381             (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
9382                 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
9383                 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
9384                 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
9385                 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
9386                 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
9387         fwr->smac_sel = 0;
9388         fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
9389             V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
9390         fwr->maci_to_matchtypem =
9391             htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
9392                 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
9393                 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
9394                 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
9395                 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
9396                 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
9397                 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
9398                 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
9399         fwr->ptcl = f->fs.val.proto;
9400         fwr->ptclm = f->fs.mask.proto;
9401         fwr->ttyp = f->fs.val.tos;
9402         fwr->ttypm = f->fs.mask.tos;
9403         fwr->ivlan = htobe16(f->fs.val.vlan);
9404         fwr->ivlanm = htobe16(f->fs.mask.vlan);
9405         fwr->ovlan = htobe16(f->fs.val.vnic);
9406         fwr->ovlanm = htobe16(f->fs.mask.vnic);
9407         bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
9408         bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
9409         bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
9410         bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
9411         fwr->lp = htobe16(f->fs.val.dport);
9412         fwr->lpm = htobe16(f->fs.mask.dport);
9413         fwr->fp = htobe16(f->fs.val.sport);
9414         fwr->fpm = htobe16(f->fs.mask.sport);
9415         if (f->fs.newsmac)
9416                 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
9417
9418         f->pending = 1;
9419         sc->tids.ftids_in_use++;
9420
9421         commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
9422         return (0);
9423 }
9424
9425 static int
9426 del_filter_wr(struct adapter *sc, int fidx)
9427 {
9428         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
9429         struct fw_filter_wr *fwr;
9430         unsigned int ftid;
9431         struct wrq_cookie cookie;
9432
9433         ftid = sc->tids.ftid_base + fidx;
9434
9435         fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
9436         if (fwr == NULL)
9437                 return (ENOMEM);
9438         bzero(fwr, sizeof (*fwr));
9439
9440         t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
9441
9442         f->pending = 1;
9443         commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
9444         return (0);
9445 }
9446
9447 int
9448 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9449 {
9450         struct adapter *sc = iq->adapter;
9451         const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
9452         unsigned int idx = GET_TID(rpl);
9453         unsigned int rc;
9454         struct filter_entry *f;
9455
9456         KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
9457             rss->opcode));
9458         MPASS(iq == &sc->sge.fwq);
9459         MPASS(is_ftid(sc, idx));
9460
9461         idx -= sc->tids.ftid_base;
9462         f = &sc->tids.ftid_tab[idx];
9463         rc = G_COOKIE(rpl->cookie);
9464
9465         mtx_lock(&sc->tids.ftid_lock);
9466         if (rc == FW_FILTER_WR_FLT_ADDED) {
9467                 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
9468                     __func__, idx));
9469                 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
9470                 f->pending = 0;  /* asynchronous setup completed */
9471                 f->valid = 1;
9472         } else {
9473                 if (rc != FW_FILTER_WR_FLT_DELETED) {
9474                         /* Add or delete failed, display an error */
9475                         log(LOG_ERR,
9476                             "filter %u setup failed with error %u\n",
9477                             idx, rc);
9478                 }
9479
9480                 clear_filter(f);
9481                 sc->tids.ftids_in_use--;
9482         }
9483         wakeup(&sc->tids.ftid_tab);
9484         mtx_unlock(&sc->tids.ftid_lock);
9485
9486         return (0);
9487 }
9488
9489 static int
9490 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9491 {
9492
9493         MPASS(iq->set_tcb_rpl != NULL);
9494         return (iq->set_tcb_rpl(iq, rss, m));
9495 }
9496
9497 static int
9498 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9499 {
9500
9501         MPASS(iq->l2t_write_rpl != NULL);
9502         return (iq->l2t_write_rpl(iq, rss, m));
9503 }
9504
9505 static int
9506 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9507 {
9508         int rc;
9509
9510         if (cntxt->cid > M_CTXTQID)
9511                 return (EINVAL);
9512
9513         if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9514             cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9515                 return (EINVAL);
9516
9517         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9518         if (rc)
9519                 return (rc);
9520
9521         if (sc->flags & FW_OK) {
9522                 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9523                     &cntxt->data[0]);
9524                 if (rc == 0)
9525                         goto done;
9526         }
9527
9528         /*
9529          * Read via firmware failed or wasn't even attempted.  Read directly via
9530          * the backdoor.
9531          */
9532         rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9533 done:
9534         end_synchronized_op(sc, 0);
9535         return (rc);
9536 }
9537
9538 static int
9539 load_fw(struct adapter *sc, struct t4_data *fw)
9540 {
9541         int rc;
9542         uint8_t *fw_data;
9543
9544         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9545         if (rc)
9546                 return (rc);
9547
9548         /*
9549          * The firmware, with the sole exception of the memory parity error
9550          * handler, runs from memory and not flash.  It is almost always safe to
9551          * install a new firmware on a running system.  Just set bit 1 in
9552          * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9553          */
9554         if (sc->flags & FULL_INIT_DONE &&
9555             (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9556                 rc = EBUSY;
9557                 goto done;
9558         }
9559
9560         fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9561         if (fw_data == NULL) {
9562                 rc = ENOMEM;
9563                 goto done;
9564         }
9565
9566         rc = copyin(fw->data, fw_data, fw->len);
9567         if (rc == 0)
9568                 rc = -t4_load_fw(sc, fw_data, fw->len);
9569
9570         free(fw_data, M_CXGBE);
9571 done:
9572         end_synchronized_op(sc, 0);
9573         return (rc);
9574 }
9575
9576 static int
9577 load_cfg(struct adapter *sc, struct t4_data *cfg)
9578 {
9579         int rc;
9580         uint8_t *cfg_data = NULL;
9581
9582         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9583         if (rc)
9584                 return (rc);
9585
9586         if (cfg->len == 0) {
9587                 /* clear */
9588                 rc = -t4_load_cfg(sc, NULL, 0);
9589                 goto done;
9590         }
9591
9592         cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9593         if (cfg_data == NULL) {
9594                 rc = ENOMEM;
9595                 goto done;
9596         }
9597
9598         rc = copyin(cfg->data, cfg_data, cfg->len);
9599         if (rc == 0)
9600                 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9601
9602         free(cfg_data, M_CXGBE);
9603 done:
9604         end_synchronized_op(sc, 0);
9605         return (rc);
9606 }
9607
9608 static int
9609 load_boot(struct adapter *sc, struct t4_bootrom *br)
9610 {
9611         int rc;
9612         uint8_t *br_data = NULL;
9613         u_int offset;
9614
9615         if (br->len > 1024 * 1024)
9616                 return (EFBIG);
9617
9618         if (br->pf_offset == 0) {
9619                 /* pfidx */
9620                 if (br->pfidx_addr > 7)
9621                         return (EINVAL);
9622                 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9623                     A_PCIE_PF_EXPROM_OFST)));
9624         } else if (br->pf_offset == 1) {
9625                 /* offset */
9626                 offset = G_OFFSET(br->pfidx_addr);
9627         } else {
9628                 return (EINVAL);
9629         }
9630
9631         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9632         if (rc)
9633                 return (rc);
9634
9635         if (br->len == 0) {
9636                 /* clear */
9637                 rc = -t4_load_boot(sc, NULL, offset, 0);
9638                 goto done;
9639         }
9640
9641         br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9642         if (br_data == NULL) {
9643                 rc = ENOMEM;
9644                 goto done;
9645         }
9646
9647         rc = copyin(br->data, br_data, br->len);
9648         if (rc == 0)
9649                 rc = -t4_load_boot(sc, br_data, offset, br->len);
9650
9651         free(br_data, M_CXGBE);
9652 done:
9653         end_synchronized_op(sc, 0);
9654         return (rc);
9655 }
9656
9657 static int
9658 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9659 {
9660         int rc;
9661         uint8_t *bc_data = NULL;
9662
9663         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9664         if (rc)
9665                 return (rc);
9666
9667         if (bc->len == 0) {
9668                 /* clear */
9669                 rc = -t4_load_bootcfg(sc, NULL, 0);
9670                 goto done;
9671         }
9672
9673         bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9674         if (bc_data == NULL) {
9675                 rc = ENOMEM;
9676                 goto done;
9677         }
9678
9679         rc = copyin(bc->data, bc_data, bc->len);
9680         if (rc == 0)
9681                 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9682
9683         free(bc_data, M_CXGBE);
9684 done:
9685         end_synchronized_op(sc, 0);
9686         return (rc);
9687 }
9688
9689 static int
9690 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9691 {
9692         int rc;
9693         struct cudbg_init *cudbg;
9694         void *handle, *buf;
9695
9696         /* buf is large, don't block if no memory is available */
9697         buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9698         if (buf == NULL)
9699                 return (ENOMEM);
9700
9701         handle = cudbg_alloc_handle();
9702         if (handle == NULL) {
9703                 rc = ENOMEM;
9704                 goto done;
9705         }
9706
9707         cudbg = cudbg_get_init(handle);
9708         cudbg->adap = sc;
9709         cudbg->print = (cudbg_print_cb)printf;
9710
9711 #ifndef notyet
9712         device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9713             __func__, dump->wr_flash, dump->len, dump->data);
9714 #endif
9715
9716         if (dump->wr_flash)
9717                 cudbg->use_flash = 1;
9718         MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9719         memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9720
9721         rc = cudbg_collect(handle, buf, &dump->len);
9722         if (rc != 0)
9723                 goto done;
9724
9725         rc = copyout(buf, dump->data, dump->len);
9726 done:
9727         cudbg_free_handle(handle);
9728         free(buf, M_CXGBE);
9729         return (rc);
9730 }
9731
9732 #define MAX_READ_BUF_SIZE (128 * 1024)
9733 static int
9734 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9735 {
9736         uint32_t addr, remaining, n;
9737         uint32_t *buf;
9738         int rc;
9739         uint8_t *dst;
9740
9741         rc = validate_mem_range(sc, mr->addr, mr->len);
9742         if (rc != 0)
9743                 return (rc);
9744
9745         buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9746         addr = mr->addr;
9747         remaining = mr->len;
9748         dst = (void *)mr->data;
9749
9750         while (remaining) {
9751                 n = min(remaining, MAX_READ_BUF_SIZE);
9752                 read_via_memwin(sc, 2, addr, buf, n);
9753
9754                 rc = copyout(buf, dst, n);
9755                 if (rc != 0)
9756                         break;
9757
9758                 dst += n;
9759                 remaining -= n;
9760                 addr += n;
9761         }
9762
9763         free(buf, M_CXGBE);
9764         return (rc);
9765 }
9766 #undef MAX_READ_BUF_SIZE
9767
9768 static int
9769 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9770 {
9771         int rc;
9772
9773         if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9774                 return (EINVAL);
9775
9776         if (i2cd->len > sizeof(i2cd->data))
9777                 return (EFBIG);
9778
9779         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9780         if (rc)
9781                 return (rc);
9782         rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9783             i2cd->offset, i2cd->len, &i2cd->data[0]);
9784         end_synchronized_op(sc, 0);
9785
9786         return (rc);
9787 }
9788
9789 int
9790 t4_os_find_pci_capability(struct adapter *sc, int cap)
9791 {
9792         int i;
9793
9794         return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9795 }
9796
9797 int
9798 t4_os_pci_save_state(struct adapter *sc)
9799 {
9800         device_t dev;
9801         struct pci_devinfo *dinfo;
9802
9803         dev = sc->dev;
9804         dinfo = device_get_ivars(dev);
9805
9806         pci_cfg_save(dev, dinfo, 0);
9807         return (0);
9808 }
9809
9810 int
9811 t4_os_pci_restore_state(struct adapter *sc)
9812 {
9813         device_t dev;
9814         struct pci_devinfo *dinfo;
9815
9816         dev = sc->dev;
9817         dinfo = device_get_ivars(dev);
9818
9819         pci_cfg_restore(dev, dinfo);
9820         return (0);
9821 }
9822
9823 void
9824 t4_os_portmod_changed(struct port_info *pi)
9825 {
9826         struct adapter *sc = pi->adapter;
9827         struct vi_info *vi;
9828         struct ifnet *ifp;
9829         static const char *mod_str[] = {
9830                 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9831         };
9832
9833         KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
9834             ("%s: port_type %u", __func__, pi->port_type));
9835
9836         vi = &pi->vi[0];
9837         if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9838                 PORT_LOCK(pi);
9839                 build_medialist(pi);
9840                 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
9841                         fixup_link_config(pi);
9842                         apply_link_config(pi);
9843                 }
9844                 PORT_UNLOCK(pi);
9845                 end_synchronized_op(sc, LOCK_HELD);
9846         }
9847
9848         ifp = vi->ifp;
9849         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9850                 if_printf(ifp, "transceiver unplugged.\n");
9851         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9852                 if_printf(ifp, "unknown transceiver inserted.\n");
9853         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9854                 if_printf(ifp, "unsupported transceiver inserted.\n");
9855         else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9856                 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9857                     port_top_speed(pi), mod_str[pi->mod_type]);
9858         } else {
9859                 if_printf(ifp, "transceiver (type %d) inserted.\n",
9860                     pi->mod_type);
9861         }
9862 }
9863
9864 void
9865 t4_os_link_changed(struct port_info *pi)
9866 {
9867         struct vi_info *vi;
9868         struct ifnet *ifp;
9869         struct link_config *lc;
9870         int v;
9871
9872         PORT_LOCK_ASSERT_OWNED(pi);
9873
9874         for_each_vi(pi, v, vi) {
9875                 ifp = vi->ifp;
9876                 if (ifp == NULL)
9877                         continue;
9878
9879                 lc = &pi->link_cfg;
9880                 if (lc->link_ok) {
9881                         ifp->if_baudrate = IF_Mbps(lc->speed);
9882                         if_link_state_change(ifp, LINK_STATE_UP);
9883                 } else {
9884                         if_link_state_change(ifp, LINK_STATE_DOWN);
9885                 }
9886         }
9887 }
9888
9889 void
9890 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9891 {
9892         struct adapter *sc;
9893
9894         sx_slock(&t4_list_lock);
9895         SLIST_FOREACH(sc, &t4_list, link) {
9896                 /*
9897                  * func should not make any assumptions about what state sc is
9898                  * in - the only guarantee is that sc->sc_lock is a valid lock.
9899                  */
9900                 func(sc, arg);
9901         }
9902         sx_sunlock(&t4_list_lock);
9903 }
9904
9905 static int
9906 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9907     struct thread *td)
9908 {
9909         int rc;
9910         struct adapter *sc = dev->si_drv1;
9911
9912         rc = priv_check(td, PRIV_DRIVER);
9913         if (rc != 0)
9914                 return (rc);
9915
9916         switch (cmd) {
9917         case CHELSIO_T4_GETREG: {
9918                 struct t4_reg *edata = (struct t4_reg *)data;
9919
9920                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9921                         return (EFAULT);
9922
9923                 if (edata->size == 4)
9924                         edata->val = t4_read_reg(sc, edata->addr);
9925                 else if (edata->size == 8)
9926                         edata->val = t4_read_reg64(sc, edata->addr);
9927                 else
9928                         return (EINVAL);
9929
9930                 break;
9931         }
9932         case CHELSIO_T4_SETREG: {
9933                 struct t4_reg *edata = (struct t4_reg *)data;
9934
9935                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9936                         return (EFAULT);
9937
9938                 if (edata->size == 4) {
9939                         if (edata->val & 0xffffffff00000000)
9940                                 return (EINVAL);
9941                         t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9942                 } else if (edata->size == 8)
9943                         t4_write_reg64(sc, edata->addr, edata->val);
9944                 else
9945                         return (EINVAL);
9946                 break;
9947         }
9948         case CHELSIO_T4_REGDUMP: {
9949                 struct t4_regdump *regs = (struct t4_regdump *)data;
9950                 int reglen = t4_get_regs_len(sc);
9951                 uint8_t *buf;
9952
9953                 if (regs->len < reglen) {
9954                         regs->len = reglen; /* hint to the caller */
9955                         return (ENOBUFS);
9956                 }
9957
9958                 regs->len = reglen;
9959                 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9960                 get_regs(sc, regs, buf);
9961                 rc = copyout(buf, regs->data, reglen);
9962                 free(buf, M_CXGBE);
9963                 break;
9964         }
9965         case CHELSIO_T4_GET_FILTER_MODE:
9966                 rc = get_filter_mode(sc, (uint32_t *)data);
9967                 break;
9968         case CHELSIO_T4_SET_FILTER_MODE:
9969                 rc = set_filter_mode(sc, *(uint32_t *)data);
9970                 break;
9971         case CHELSIO_T4_GET_FILTER:
9972                 rc = get_filter(sc, (struct t4_filter *)data);
9973                 break;
9974         case CHELSIO_T4_SET_FILTER:
9975                 rc = set_filter(sc, (struct t4_filter *)data);
9976                 break;
9977         case CHELSIO_T4_DEL_FILTER:
9978                 rc = del_filter(sc, (struct t4_filter *)data);
9979                 break;
9980         case CHELSIO_T4_GET_SGE_CONTEXT:
9981                 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9982                 break;
9983         case CHELSIO_T4_LOAD_FW:
9984                 rc = load_fw(sc, (struct t4_data *)data);
9985                 break;
9986         case CHELSIO_T4_GET_MEM:
9987                 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9988                 break;
9989         case CHELSIO_T4_GET_I2C:
9990                 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9991                 break;
9992         case CHELSIO_T4_CLEAR_STATS: {
9993                 int i, v, bg_map;
9994                 u_int port_id = *(uint32_t *)data;
9995                 struct port_info *pi;
9996                 struct vi_info *vi;
9997
9998                 if (port_id >= sc->params.nports)
9999                         return (EINVAL);
10000                 pi = sc->port[port_id];
10001                 if (pi == NULL)
10002                         return (EIO);
10003
10004                 /* MAC stats */
10005                 t4_clr_port_stats(sc, pi->tx_chan);
10006                 pi->tx_parse_error = 0;
10007                 pi->tnl_cong_drops = 0;
10008                 mtx_lock(&sc->reg_lock);
10009                 for_each_vi(pi, v, vi) {
10010                         if (vi->flags & VI_INIT_DONE)
10011                                 t4_clr_vi_stats(sc, vi->viid);
10012                 }
10013                 bg_map = pi->mps_bg_map;
10014                 v = 0;  /* reuse */
10015                 while (bg_map) {
10016                         i = ffs(bg_map) - 1;
10017                         t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10018                             1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10019                         bg_map &= ~(1 << i);
10020                 }
10021                 mtx_unlock(&sc->reg_lock);
10022
10023                 /*
10024                  * Since this command accepts a port, clear stats for
10025                  * all VIs on this port.
10026                  */
10027                 for_each_vi(pi, v, vi) {
10028                         if (vi->flags & VI_INIT_DONE) {
10029                                 struct sge_rxq *rxq;
10030                                 struct sge_txq *txq;
10031                                 struct sge_wrq *wrq;
10032
10033                                 for_each_rxq(vi, i, rxq) {
10034 #if defined(INET) || defined(INET6)
10035                                         rxq->lro.lro_queued = 0;
10036                                         rxq->lro.lro_flushed = 0;
10037 #endif
10038                                         rxq->rxcsum = 0;
10039                                         rxq->vlan_extraction = 0;
10040                                 }
10041
10042                                 for_each_txq(vi, i, txq) {
10043                                         txq->txcsum = 0;
10044                                         txq->tso_wrs = 0;
10045                                         txq->vlan_insertion = 0;
10046                                         txq->imm_wrs = 0;
10047                                         txq->sgl_wrs = 0;
10048                                         txq->txpkt_wrs = 0;
10049                                         txq->txpkts0_wrs = 0;
10050                                         txq->txpkts1_wrs = 0;
10051                                         txq->txpkts0_pkts = 0;
10052                                         txq->txpkts1_pkts = 0;
10053                                         mp_ring_reset_stats(txq->r);
10054                                 }
10055
10056 #ifdef TCP_OFFLOAD
10057                                 /* nothing to clear for each ofld_rxq */
10058
10059                                 for_each_ofld_txq(vi, i, wrq) {
10060                                         wrq->tx_wrs_direct = 0;
10061                                         wrq->tx_wrs_copied = 0;
10062                                 }
10063 #endif
10064
10065                                 if (IS_MAIN_VI(vi)) {
10066                                         wrq = &sc->sge.ctrlq[pi->port_id];
10067                                         wrq->tx_wrs_direct = 0;
10068                                         wrq->tx_wrs_copied = 0;
10069                                 }
10070                         }
10071                 }
10072                 break;
10073         }
10074         case CHELSIO_T4_SCHED_CLASS:
10075                 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10076                 break;
10077         case CHELSIO_T4_SCHED_QUEUE:
10078                 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10079                 break;
10080         case CHELSIO_T4_GET_TRACER:
10081                 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10082                 break;
10083         case CHELSIO_T4_SET_TRACER:
10084                 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10085                 break;
10086         case CHELSIO_T4_LOAD_CFG:
10087                 rc = load_cfg(sc, (struct t4_data *)data);
10088                 break;
10089         case CHELSIO_T4_LOAD_BOOT:
10090                 rc = load_boot(sc, (struct t4_bootrom *)data);
10091                 break;
10092         case CHELSIO_T4_LOAD_BOOTCFG:
10093                 rc = load_bootcfg(sc, (struct t4_data *)data);
10094                 break;
10095         case CHELSIO_T4_CUDBG_DUMP:
10096                 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10097                 break;
10098         default:
10099                 rc = ENOTTY;
10100         }
10101
10102         return (rc);
10103 }
10104
10105 void
10106 t4_db_full(struct adapter *sc)
10107 {
10108
10109         CXGBE_UNIMPLEMENTED(__func__);
10110 }
10111
10112 void
10113 t4_db_dropped(struct adapter *sc)
10114 {
10115
10116         CXGBE_UNIMPLEMENTED(__func__);
10117 }
10118
10119 #ifdef TCP_OFFLOAD
10120 void
10121 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
10122 {
10123
10124         t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
10125         t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
10126                 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
10127                 V_HPZ3(pgsz_order[3]));
10128 }
10129
10130 static int
10131 toe_capability(struct vi_info *vi, int enable)
10132 {
10133         int rc;
10134         struct port_info *pi = vi->pi;
10135         struct adapter *sc = pi->adapter;
10136
10137         ASSERT_SYNCHRONIZED_OP(sc);
10138
10139         if (!is_offload(sc))
10140                 return (ENODEV);
10141
10142         if (enable) {
10143                 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10144                         /* TOE is already enabled. */
10145                         return (0);
10146                 }
10147
10148                 /*
10149                  * We need the port's queues around so that we're able to send
10150                  * and receive CPLs to/from the TOE even if the ifnet for this
10151                  * port has never been UP'd administratively.
10152                  */
10153                 if (!(vi->flags & VI_INIT_DONE)) {
10154                         rc = vi_full_init(vi);
10155                         if (rc)
10156                                 return (rc);
10157                 }
10158                 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10159                         rc = vi_full_init(&pi->vi[0]);
10160                         if (rc)
10161                                 return (rc);
10162                 }
10163
10164                 if (isset(&sc->offload_map, pi->port_id)) {
10165                         /* TOE is enabled on another VI of this port. */
10166                         pi->uld_vis++;
10167                         return (0);
10168                 }
10169
10170                 if (!uld_active(sc, ULD_TOM)) {
10171                         rc = t4_activate_uld(sc, ULD_TOM);
10172                         if (rc == EAGAIN) {
10173                                 log(LOG_WARNING,
10174                                     "You must kldload t4_tom.ko before trying "
10175                                     "to enable TOE on a cxgbe interface.\n");
10176                         }
10177                         if (rc != 0)
10178                                 return (rc);
10179                         KASSERT(sc->tom_softc != NULL,
10180                             ("%s: TOM activated but softc NULL", __func__));
10181                         KASSERT(uld_active(sc, ULD_TOM),
10182                             ("%s: TOM activated but flag not set", __func__));
10183                 }
10184
10185                 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10186                 if (!uld_active(sc, ULD_IWARP))
10187                         (void) t4_activate_uld(sc, ULD_IWARP);
10188                 if (!uld_active(sc, ULD_ISCSI))
10189                         (void) t4_activate_uld(sc, ULD_ISCSI);
10190
10191                 pi->uld_vis++;
10192                 setbit(&sc->offload_map, pi->port_id);
10193         } else {
10194                 pi->uld_vis--;
10195
10196                 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10197                         return (0);
10198
10199                 KASSERT(uld_active(sc, ULD_TOM),
10200                     ("%s: TOM never initialized?", __func__));
10201                 clrbit(&sc->offload_map, pi->port_id);
10202         }
10203
10204         return (0);
10205 }
10206
10207 /*
10208  * Add an upper layer driver to the global list.
10209  */
10210 int
10211 t4_register_uld(struct uld_info *ui)
10212 {
10213         int rc = 0;
10214         struct uld_info *u;
10215
10216         sx_xlock(&t4_uld_list_lock);
10217         SLIST_FOREACH(u, &t4_uld_list, link) {
10218             if (u->uld_id == ui->uld_id) {
10219                     rc = EEXIST;
10220                     goto done;
10221             }
10222         }
10223
10224         SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10225         ui->refcount = 0;
10226 done:
10227         sx_xunlock(&t4_uld_list_lock);
10228         return (rc);
10229 }
10230
10231 int
10232 t4_unregister_uld(struct uld_info *ui)
10233 {
10234         int rc = EINVAL;
10235         struct uld_info *u;
10236
10237         sx_xlock(&t4_uld_list_lock);
10238
10239         SLIST_FOREACH(u, &t4_uld_list, link) {
10240             if (u == ui) {
10241                     if (ui->refcount > 0) {
10242                             rc = EBUSY;
10243                             goto done;
10244                     }
10245
10246                     SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10247                     rc = 0;
10248                     goto done;
10249             }
10250         }
10251 done:
10252         sx_xunlock(&t4_uld_list_lock);
10253         return (rc);
10254 }
10255
10256 int
10257 t4_activate_uld(struct adapter *sc, int id)
10258 {
10259         int rc;
10260         struct uld_info *ui;
10261
10262         ASSERT_SYNCHRONIZED_OP(sc);
10263
10264         if (id < 0 || id > ULD_MAX)
10265                 return (EINVAL);
10266         rc = EAGAIN;    /* kldoad the module with this ULD and try again. */
10267
10268         sx_slock(&t4_uld_list_lock);
10269
10270         SLIST_FOREACH(ui, &t4_uld_list, link) {
10271                 if (ui->uld_id == id) {
10272                         if (!(sc->flags & FULL_INIT_DONE)) {
10273                                 rc = adapter_full_init(sc);
10274                                 if (rc != 0)
10275                                         break;
10276                         }
10277
10278                         rc = ui->activate(sc);
10279                         if (rc == 0) {
10280                                 setbit(&sc->active_ulds, id);
10281                                 ui->refcount++;
10282                         }
10283                         break;
10284                 }
10285         }
10286
10287         sx_sunlock(&t4_uld_list_lock);
10288
10289         return (rc);
10290 }
10291
10292 int
10293 t4_deactivate_uld(struct adapter *sc, int id)
10294 {
10295         int rc;
10296         struct uld_info *ui;
10297
10298         ASSERT_SYNCHRONIZED_OP(sc);
10299
10300         if (id < 0 || id > ULD_MAX)
10301                 return (EINVAL);
10302         rc = ENXIO;
10303
10304         sx_slock(&t4_uld_list_lock);
10305
10306         SLIST_FOREACH(ui, &t4_uld_list, link) {
10307                 if (ui->uld_id == id) {
10308                         rc = ui->deactivate(sc);
10309                         if (rc == 0) {
10310                                 clrbit(&sc->active_ulds, id);
10311                                 ui->refcount--;
10312                         }
10313                         break;
10314                 }
10315         }
10316
10317         sx_sunlock(&t4_uld_list_lock);
10318
10319         return (rc);
10320 }
10321
10322 int
10323 uld_active(struct adapter *sc, int uld_id)
10324 {
10325
10326         MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10327
10328         return (isset(&sc->active_ulds, uld_id));
10329 }
10330 #endif
10331
10332 /*
10333  * t  = ptr to tunable.
10334  * nc = number of CPUs.
10335  * c  = compiled in default for that tunable.
10336  */
10337 static void
10338 calculate_nqueues(int *t, int nc, const int c)
10339 {
10340         int nq;
10341
10342         if (*t > 0)
10343                 return;
10344         nq = *t < 0 ? -*t : c;
10345         *t = min(nc, nq);
10346 }
10347
10348 /*
10349  * Come up with reasonable defaults for some of the tunables, provided they're
10350  * not set by the user (in which case we'll use the values as is).
10351  */
10352 static void
10353 tweak_tunables(void)
10354 {
10355         int nc = mp_ncpus;      /* our snapshot of the number of CPUs */
10356
10357         if (t4_ntxq < 1) {
10358 #ifdef RSS
10359                 t4_ntxq = rss_getnumbuckets();
10360 #else
10361                 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10362 #endif
10363         }
10364
10365         calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10366
10367         if (t4_nrxq < 1) {
10368 #ifdef RSS
10369                 t4_nrxq = rss_getnumbuckets();
10370 #else
10371                 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10372 #endif
10373         }
10374
10375         calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10376
10377 #ifdef TCP_OFFLOAD
10378         calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10379         calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10380         calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10381         calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10382
10383         if (t4_toecaps_allowed == -1)
10384                 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10385
10386         if (t4_rdmacaps_allowed == -1) {
10387                 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10388                     FW_CAPS_CONFIG_RDMA_RDMAC;
10389         }
10390
10391         if (t4_iscsicaps_allowed == -1) {
10392                 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10393                     FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10394                     FW_CAPS_CONFIG_ISCSI_T10DIF;
10395         }
10396
10397         if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10398                 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10399
10400         if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10401                 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10402 #else
10403         if (t4_toecaps_allowed == -1)
10404                 t4_toecaps_allowed = 0;
10405
10406         if (t4_rdmacaps_allowed == -1)
10407                 t4_rdmacaps_allowed = 0;
10408
10409         if (t4_iscsicaps_allowed == -1)
10410                 t4_iscsicaps_allowed = 0;
10411 #endif
10412
10413 #ifdef DEV_NETMAP
10414         calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10415         calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10416 #endif
10417
10418         if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10419                 t4_tmr_idx = TMR_IDX;
10420
10421         if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10422                 t4_pktc_idx = PKTC_IDX;
10423
10424         if (t4_qsize_txq < 128)
10425                 t4_qsize_txq = 128;
10426
10427         if (t4_qsize_rxq < 128)
10428                 t4_qsize_rxq = 128;
10429         while (t4_qsize_rxq & 7)
10430                 t4_qsize_rxq++;
10431
10432         t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10433
10434         /*
10435          * Number of VIs to create per-port.  The first VI is the "main" regular
10436          * VI for the port.  The rest are additional virtual interfaces on the
10437          * same physical port.  Note that the main VI does not have native
10438          * netmap support but the extra VIs do.
10439          *
10440          * Limit the number of VIs per port to the number of available
10441          * MAC addresses per port.
10442          */
10443         if (t4_num_vis < 1)
10444                 t4_num_vis = 1;
10445         if (t4_num_vis > nitems(vi_mac_funcs)) {
10446                 t4_num_vis = nitems(vi_mac_funcs);
10447                 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10448         }
10449
10450         if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10451                 pcie_relaxed_ordering = 1;
10452 #if defined(__i386__) || defined(__amd64__)
10453                 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10454                         pcie_relaxed_ordering = 0;
10455 #endif
10456         }
10457 }
10458
10459 #ifdef DDB
10460 static void
10461 t4_dump_tcb(struct adapter *sc, int tid)
10462 {
10463         uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10464
10465         reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10466         save = t4_read_reg(sc, reg);
10467         base = sc->memwin[2].mw_base;
10468
10469         /* Dump TCB for the tid */
10470         tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10471         tcb_addr += tid * TCB_SIZE;
10472
10473         if (is_t4(sc)) {
10474                 pf = 0;
10475                 win_pos = tcb_addr & ~0xf;      /* start must be 16B aligned */
10476         } else {
10477                 pf = V_PFNUM(sc->pf);
10478                 win_pos = tcb_addr & ~0x7f;     /* start must be 128B aligned */
10479         }
10480         t4_write_reg(sc, reg, win_pos | pf);
10481         t4_read_reg(sc, reg);
10482
10483         off = tcb_addr - win_pos;
10484         for (i = 0; i < 4; i++) {
10485                 uint32_t buf[8];
10486                 for (j = 0; j < 8; j++, off += 4)
10487                         buf[j] = htonl(t4_read_reg(sc, base + off));
10488
10489                 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10490                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10491                     buf[7]);
10492         }
10493
10494         t4_write_reg(sc, reg, save);
10495         t4_read_reg(sc, reg);
10496 }
10497
10498 static void
10499 t4_dump_devlog(struct adapter *sc)
10500 {
10501         struct devlog_params *dparams = &sc->params.devlog;
10502         struct fw_devlog_e e;
10503         int i, first, j, m, nentries, rc;
10504         uint64_t ftstamp = UINT64_MAX;
10505
10506         if (dparams->start == 0) {
10507                 db_printf("devlog params not valid\n");
10508                 return;
10509         }
10510
10511         nentries = dparams->size / sizeof(struct fw_devlog_e);
10512         m = fwmtype_to_hwmtype(dparams->memtype);
10513
10514         /* Find the first entry. */
10515         first = -1;
10516         for (i = 0; i < nentries && !db_pager_quit; i++) {
10517                 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10518                     sizeof(e), (void *)&e);
10519                 if (rc != 0)
10520                         break;
10521
10522                 if (e.timestamp == 0)
10523                         break;
10524
10525                 e.timestamp = be64toh(e.timestamp);
10526                 if (e.timestamp < ftstamp) {
10527                         ftstamp = e.timestamp;
10528                         first = i;
10529                 }
10530         }
10531
10532         if (first == -1)
10533                 return;
10534
10535         i = first;
10536         do {
10537                 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10538                     sizeof(e), (void *)&e);
10539                 if (rc != 0)
10540                         return;
10541
10542                 if (e.timestamp == 0)
10543                         return;
10544
10545                 e.timestamp = be64toh(e.timestamp);
10546                 e.seqno = be32toh(e.seqno);
10547                 for (j = 0; j < 8; j++)
10548                         e.params[j] = be32toh(e.params[j]);
10549
10550                 db_printf("%10d  %15ju  %8s  %8s  ",
10551                     e.seqno, e.timestamp,
10552                     (e.level < nitems(devlog_level_strings) ?
10553                         devlog_level_strings[e.level] : "UNKNOWN"),
10554                     (e.facility < nitems(devlog_facility_strings) ?
10555                         devlog_facility_strings[e.facility] : "UNKNOWN"));
10556                 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10557                     e.params[3], e.params[4], e.params[5], e.params[6],
10558                     e.params[7]);
10559
10560                 if (++i == nentries)
10561                         i = 0;
10562         } while (i != first && !db_pager_quit);
10563 }
10564
10565 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10566 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10567
10568 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10569 {
10570         device_t dev;
10571         int t;
10572         bool valid;
10573
10574         valid = false;
10575         t = db_read_token();
10576         if (t == tIDENT) {
10577                 dev = device_lookup_by_name(db_tok_string);
10578                 valid = true;
10579         }
10580         db_skip_to_eol();
10581         if (!valid) {
10582                 db_printf("usage: show t4 devlog <nexus>\n");
10583                 return;
10584         }
10585
10586         if (dev == NULL) {
10587                 db_printf("device not found\n");
10588                 return;
10589         }
10590
10591         t4_dump_devlog(device_get_softc(dev));
10592 }
10593
10594 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10595 {
10596         device_t dev;
10597         int radix, tid, t;
10598         bool valid;
10599
10600         valid = false;
10601         radix = db_radix;
10602         db_radix = 10;
10603         t = db_read_token();
10604         if (t == tIDENT) {
10605                 dev = device_lookup_by_name(db_tok_string);
10606                 t = db_read_token();
10607                 if (t == tNUMBER) {
10608                         tid = db_tok_number;
10609                         valid = true;
10610                 }
10611         }
10612         db_radix = radix;
10613         db_skip_to_eol();
10614         if (!valid) {
10615                 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10616                 return;
10617         }
10618
10619         if (dev == NULL) {
10620                 db_printf("device not found\n");
10621                 return;
10622         }
10623         if (tid < 0) {
10624                 db_printf("invalid tid\n");
10625                 return;
10626         }
10627
10628         t4_dump_tcb(device_get_softc(dev), tid);
10629 }
10630 #endif
10631
10632 static struct sx mlu;   /* mod load unload */
10633 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10634
10635 static int
10636 mod_event(module_t mod, int cmd, void *arg)
10637 {
10638         int rc = 0;
10639         static int loaded = 0;
10640
10641         switch (cmd) {
10642         case MOD_LOAD:
10643                 sx_xlock(&mlu);
10644                 if (loaded++ == 0) {
10645                         t4_sge_modload();
10646                         t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
10647                         t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
10648                         t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10649                         t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10650                         sx_init(&t4_list_lock, "T4/T5 adapters");
10651                         SLIST_INIT(&t4_list);
10652 #ifdef TCP_OFFLOAD
10653                         sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10654                         SLIST_INIT(&t4_uld_list);
10655 #endif
10656                         t4_tracer_modload();
10657                         tweak_tunables();
10658                 }
10659                 sx_xunlock(&mlu);
10660                 break;
10661
10662         case MOD_UNLOAD:
10663                 sx_xlock(&mlu);
10664                 if (--loaded == 0) {
10665                         int tries;
10666
10667                         sx_slock(&t4_list_lock);
10668                         if (!SLIST_EMPTY(&t4_list)) {
10669                                 rc = EBUSY;
10670                                 sx_sunlock(&t4_list_lock);
10671                                 goto done_unload;
10672                         }
10673 #ifdef TCP_OFFLOAD
10674                         sx_slock(&t4_uld_list_lock);
10675                         if (!SLIST_EMPTY(&t4_uld_list)) {
10676                                 rc = EBUSY;
10677                                 sx_sunlock(&t4_uld_list_lock);
10678                                 sx_sunlock(&t4_list_lock);
10679                                 goto done_unload;
10680                         }
10681 #endif
10682                         tries = 0;
10683                         while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10684                                 uprintf("%ju clusters with custom free routine "
10685                                     "still is use.\n", t4_sge_extfree_refs());
10686                                 pause("t4unload", 2 * hz);
10687                         }
10688 #ifdef TCP_OFFLOAD
10689                         sx_sunlock(&t4_uld_list_lock);
10690 #endif
10691                         sx_sunlock(&t4_list_lock);
10692
10693                         if (t4_sge_extfree_refs() == 0) {
10694                                 t4_tracer_modunload();
10695 #ifdef TCP_OFFLOAD
10696                                 sx_destroy(&t4_uld_list_lock);
10697 #endif
10698                                 sx_destroy(&t4_list_lock);
10699                                 t4_sge_modunload();
10700                                 loaded = 0;
10701                         } else {
10702                                 rc = EBUSY;
10703                                 loaded++;       /* undo earlier decrement */
10704                         }
10705                 }
10706 done_unload:
10707                 sx_xunlock(&mlu);
10708                 break;
10709         }
10710
10711         return (rc);
10712 }
10713
10714 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10715 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10716 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10717
10718 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10719 MODULE_VERSION(t4nex, 1);
10720 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10721 #ifdef DEV_NETMAP
10722 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10723 #endif /* DEV_NETMAP */
10724
10725 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10726 MODULE_VERSION(t5nex, 1);
10727 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10728 #ifdef DEV_NETMAP
10729 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10730 #endif /* DEV_NETMAP */
10731
10732 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10733 MODULE_VERSION(t6nex, 1);
10734 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10735 #ifdef DEV_NETMAP
10736 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10737 #endif /* DEV_NETMAP */
10738
10739 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10740 MODULE_VERSION(cxgbe, 1);
10741
10742 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10743 MODULE_VERSION(cxl, 1);
10744
10745 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10746 MODULE_VERSION(cc, 1);
10747
10748 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10749 MODULE_VERSION(vcxgbe, 1);
10750
10751 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10752 MODULE_VERSION(vcxl, 1);
10753
10754 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10755 MODULE_VERSION(vcc, 1);