2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/param.h>
37 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
41 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
43 #include <sys/pciio.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pci_private.h>
47 #include <sys/firmware.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <net/ethernet.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
57 #include <net/if_vlan_var.h>
58 #if defined(__i386__) || defined(__amd64__)
63 #include "common/common.h"
64 #include "common/t4_msg.h"
65 #include "common/t4_regs.h"
66 #include "common/t4_regs_values.h"
70 /* T4 bus driver interface */
71 static int t4_probe(device_t);
72 static int t4_attach(device_t);
73 static int t4_detach(device_t);
74 static device_method_t t4_methods[] = {
75 DEVMETHOD(device_probe, t4_probe),
76 DEVMETHOD(device_attach, t4_attach),
77 DEVMETHOD(device_detach, t4_detach),
81 static driver_t t4_driver = {
84 sizeof(struct adapter)
88 /* T4 port (cxgbe) interface */
89 static int cxgbe_probe(device_t);
90 static int cxgbe_attach(device_t);
91 static int cxgbe_detach(device_t);
92 static device_method_t cxgbe_methods[] = {
93 DEVMETHOD(device_probe, cxgbe_probe),
94 DEVMETHOD(device_attach, cxgbe_attach),
95 DEVMETHOD(device_detach, cxgbe_detach),
98 static driver_t cxgbe_driver = {
101 sizeof(struct port_info)
104 static d_ioctl_t t4_ioctl;
105 static d_open_t t4_open;
106 static d_close_t t4_close;
108 static struct cdevsw t4_cdevsw = {
109 .d_version = D_VERSION,
117 /* T5 bus driver interface */
118 static int t5_probe(device_t);
119 static device_method_t t5_methods[] = {
120 DEVMETHOD(device_probe, t5_probe),
121 DEVMETHOD(device_attach, t4_attach),
122 DEVMETHOD(device_detach, t4_detach),
126 static driver_t t5_driver = {
129 sizeof(struct adapter)
133 /* T5 port (cxl) interface */
134 static driver_t cxl_driver = {
137 sizeof(struct port_info)
140 static struct cdevsw t5_cdevsw = {
141 .d_version = D_VERSION,
149 /* ifnet + media interface */
150 static void cxgbe_init(void *);
151 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
152 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
153 static void cxgbe_qflush(struct ifnet *);
154 static int cxgbe_media_change(struct ifnet *);
155 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
157 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
160 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
161 * then ADAPTER_LOCK, then t4_uld_list_lock.
163 static struct sx t4_list_lock;
164 static SLIST_HEAD(, adapter) t4_list;
166 static struct sx t4_uld_list_lock;
167 static SLIST_HEAD(, uld_info) t4_uld_list;
171 * Tunables. See tweak_tunables() too.
173 * Each tunable is set to a default value here if it's known at compile-time.
174 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
175 * provide a reasonable default when the driver is loaded.
177 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
178 * T5 are under hw.cxl.
182 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
185 static int t4_ntxq10g = -1;
186 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
189 static int t4_nrxq10g = -1;
190 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
193 static int t4_ntxq1g = -1;
194 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
197 static int t4_nrxq1g = -1;
198 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
201 #define NOFLDTXQ_10G 8
202 static int t4_nofldtxq10g = -1;
203 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
205 #define NOFLDRXQ_10G 2
206 static int t4_nofldrxq10g = -1;
207 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
209 #define NOFLDTXQ_1G 2
210 static int t4_nofldtxq1g = -1;
211 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
213 #define NOFLDRXQ_1G 1
214 static int t4_nofldrxq1g = -1;
215 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
219 * Holdoff parameters for 10G and 1G ports.
221 #define TMR_IDX_10G 1
222 static int t4_tmr_idx_10g = TMR_IDX_10G;
223 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
225 #define PKTC_IDX_10G (-1)
226 static int t4_pktc_idx_10g = PKTC_IDX_10G;
227 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
230 static int t4_tmr_idx_1g = TMR_IDX_1G;
231 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
233 #define PKTC_IDX_1G (-1)
234 static int t4_pktc_idx_1g = PKTC_IDX_1G;
235 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
238 * Size (# of entries) of each tx and rx queue.
240 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
241 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
243 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
244 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
247 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
249 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
250 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
253 * Configuration file.
255 #define DEFAULT_CF "default"
256 #define FLASH_CF "flash"
257 #define UWIRE_CF "uwire"
258 #define FPGA_CF "fpga"
259 static char t4_cfg_file[32] = DEFAULT_CF;
260 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
263 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
264 * encouraged respectively).
266 static unsigned int t4_fw_install = 1;
267 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
270 * ASIC features that will be used. Disable the ones you don't want so that the
271 * chip resources aren't wasted on features that will not be used.
273 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
274 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
276 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
277 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
279 static int t4_toecaps_allowed = -1;
280 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
282 static int t4_rdmacaps_allowed = 0;
283 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
285 static int t4_iscsicaps_allowed = 0;
286 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
288 static int t4_fcoecaps_allowed = 0;
289 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
291 static int t5_write_combine = 0;
292 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
294 struct intrs_and_queues {
295 int intr_type; /* INTx, MSI, or MSI-X */
296 int nirq; /* Number of vectors */
298 int ntxq10g; /* # of NIC txq's for each 10G port */
299 int nrxq10g; /* # of NIC rxq's for each 10G port */
300 int ntxq1g; /* # of NIC txq's for each 1G port */
301 int nrxq1g; /* # of NIC rxq's for each 1G port */
303 int nofldtxq10g; /* # of TOE txq's for each 10G port */
304 int nofldrxq10g; /* # of TOE rxq's for each 10G port */
305 int nofldtxq1g; /* # of TOE txq's for each 1G port */
306 int nofldrxq1g; /* # of TOE rxq's for each 1G port */
310 struct filter_entry {
311 uint32_t valid:1; /* filter allocated and valid */
312 uint32_t locked:1; /* filter is administratively locked */
313 uint32_t pending:1; /* filter action is pending firmware reply */
314 uint32_t smtidx:8; /* Source MAC Table index for smac */
315 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
317 struct t4_filter_specification fs;
321 XGMAC_MTU = (1 << 0),
322 XGMAC_PROMISC = (1 << 1),
323 XGMAC_ALLMULTI = (1 << 2),
324 XGMAC_VLANEX = (1 << 3),
325 XGMAC_UCADDR = (1 << 4),
326 XGMAC_MCADDRS = (1 << 5),
331 static int map_bars_0_and_4(struct adapter *);
332 static int map_bar_2(struct adapter *);
333 static void setup_memwin(struct adapter *);
334 static int validate_mem_range(struct adapter *, uint32_t, int);
335 static int fwmtype_to_hwmtype(int);
336 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
338 static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
339 static uint32_t position_memwin(struct adapter *, int, uint32_t);
340 static int cfg_itype_and_nqueues(struct adapter *, int, int,
341 struct intrs_and_queues *);
342 static int prep_firmware(struct adapter *);
343 static int partition_resources(struct adapter *, const struct firmware *,
345 static int get_params__pre_init(struct adapter *);
346 static int get_params__post_init(struct adapter *);
347 static int set_params__post_init(struct adapter *);
348 static void t4_set_desc(struct adapter *);
349 static void build_medialist(struct port_info *);
350 static int update_mac_settings(struct port_info *, int);
351 static int cxgbe_init_synchronized(struct port_info *);
352 static int cxgbe_uninit_synchronized(struct port_info *);
353 static int setup_intr_handlers(struct adapter *);
354 static int adapter_full_init(struct adapter *);
355 static int adapter_full_uninit(struct adapter *);
356 static int port_full_init(struct port_info *);
357 static int port_full_uninit(struct port_info *);
358 static void quiesce_eq(struct adapter *, struct sge_eq *);
359 static void quiesce_iq(struct adapter *, struct sge_iq *);
360 static void quiesce_fl(struct adapter *, struct sge_fl *);
361 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
362 driver_intr_t *, void *, char *);
363 static int t4_free_irq(struct adapter *, struct irq *);
364 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
366 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
367 static void cxgbe_tick(void *);
368 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
369 static int cpl_not_handled(struct sge_iq *, const struct rss_header *,
371 static int an_not_handled(struct sge_iq *, const struct rsp_ctrl *);
372 static int fw_msg_not_handled(struct adapter *, const __be64 *);
373 static int t4_sysctls(struct adapter *);
374 static int cxgbe_sysctls(struct port_info *);
375 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
376 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
377 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
378 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
379 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
380 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
381 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
382 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
383 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
385 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
386 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
387 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
388 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
389 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
390 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
391 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
392 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
393 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
394 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
395 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
396 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
397 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
398 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
399 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
400 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
401 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
402 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
403 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
404 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
405 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
406 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
407 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
408 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
409 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
411 static inline void txq_start(struct ifnet *, struct sge_txq *);
412 static uint32_t fconf_to_mode(uint32_t);
413 static uint32_t mode_to_fconf(uint32_t);
414 static uint32_t fspec_to_fconf(struct t4_filter_specification *);
415 static int get_filter_mode(struct adapter *, uint32_t *);
416 static int set_filter_mode(struct adapter *, uint32_t);
417 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
418 static int get_filter(struct adapter *, struct t4_filter *);
419 static int set_filter(struct adapter *, struct t4_filter *);
420 static int del_filter(struct adapter *, struct t4_filter *);
421 static void clear_filter(struct filter_entry *);
422 static int set_filter_wr(struct adapter *, int);
423 static int del_filter_wr(struct adapter *, int);
424 static int get_sge_context(struct adapter *, struct t4_sge_context *);
425 static int load_fw(struct adapter *, struct t4_data *);
426 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
427 static int read_i2c(struct adapter *, struct t4_i2c_data *);
429 static int toe_capability(struct port_info *, int);
431 static int mod_event(module_t, int, void *);
437 {0xa000, "Chelsio Terminator 4 FPGA"},
438 {0x4400, "Chelsio T440-dbg"},
439 {0x4401, "Chelsio T420-CR"},
440 {0x4402, "Chelsio T422-CR"},
441 {0x4403, "Chelsio T440-CR"},
442 {0x4404, "Chelsio T420-BCH"},
443 {0x4405, "Chelsio T440-BCH"},
444 {0x4406, "Chelsio T440-CH"},
445 {0x4407, "Chelsio T420-SO"},
446 {0x4408, "Chelsio T420-CX"},
447 {0x4409, "Chelsio T420-BT"},
448 {0x440a, "Chelsio T404-BT"},
449 {0x440e, "Chelsio T440-LP-CR"},
451 {0xb000, "Chelsio Terminator 5 FPGA"},
452 {0x5400, "Chelsio T580-dbg"},
453 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
454 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
455 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
456 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
457 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
458 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
459 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
460 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
461 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
462 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
463 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
464 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
466 {0x5404, "Chelsio T520-BCH"},
467 {0x5405, "Chelsio T540-BCH"},
468 {0x5406, "Chelsio T540-CH"},
469 {0x5408, "Chelsio T520-CX"},
470 {0x540b, "Chelsio B520-SR"},
471 {0x540c, "Chelsio B504-BT"},
472 {0x540f, "Chelsio Amsterdam"},
473 {0x5413, "Chelsio T580-CHR"},
479 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
480 * exactly the same for both rxq and ofld_rxq.
482 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
483 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
486 /* No easy way to include t4_msg.h before adapter.h so we check this way */
487 CTASSERT(nitems(((struct adapter *)0)->cpl_handler) == NUM_CPL_CMDS);
488 CTASSERT(nitems(((struct adapter *)0)->fw_msg_handler) == NUM_FW6_TYPES);
491 t4_probe(device_t dev)
494 uint16_t v = pci_get_vendor(dev);
495 uint16_t d = pci_get_device(dev);
496 uint8_t f = pci_get_function(dev);
498 if (v != PCI_VENDOR_ID_CHELSIO)
501 /* Attach only to PF0 of the FPGA */
502 if (d == 0xa000 && f != 0)
505 for (i = 0; i < nitems(t4_pciids); i++) {
506 if (d == t4_pciids[i].device) {
507 device_set_desc(dev, t4_pciids[i].desc);
508 return (BUS_PROBE_DEFAULT);
516 t5_probe(device_t dev)
519 uint16_t v = pci_get_vendor(dev);
520 uint16_t d = pci_get_device(dev);
521 uint8_t f = pci_get_function(dev);
523 if (v != PCI_VENDOR_ID_CHELSIO)
526 /* Attach only to PF0 of the FPGA */
527 if (d == 0xb000 && f != 0)
530 for (i = 0; i < nitems(t5_pciids); i++) {
531 if (d == t5_pciids[i].device) {
532 device_set_desc(dev, t5_pciids[i].desc);
533 return (BUS_PROBE_DEFAULT);
541 t4_attach(device_t dev)
544 int rc = 0, i, n10g, n1g, rqidx, tqidx;
545 struct intrs_and_queues iaq;
548 int ofld_rqidx, ofld_tqidx;
551 sc = device_get_softc(dev);
554 pci_enable_busmaster(dev);
555 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
558 pci_set_max_read_req(dev, 4096);
559 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
560 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
561 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
565 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
566 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
567 device_get_nameunit(dev));
569 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
570 device_get_nameunit(dev));
571 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
572 sx_xlock(&t4_list_lock);
573 SLIST_INSERT_HEAD(&t4_list, sc, link);
574 sx_xunlock(&t4_list_lock);
576 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
577 TAILQ_INIT(&sc->sfl);
578 callout_init(&sc->sfl_callout, CALLOUT_MPSAFE);
580 rc = map_bars_0_and_4(sc);
582 goto done; /* error message displayed already */
585 * This is the real PF# to which we're attaching. Works from within PCI
586 * passthrough environments too, where pci_get_function() could return a
587 * different PF# depending on the passthrough configuration. We need to
588 * use the real PF# in all our communication with the firmware.
590 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
593 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
594 sc->an_handler = an_not_handled;
595 for (i = 0; i < nitems(sc->cpl_handler); i++)
596 sc->cpl_handler[i] = cpl_not_handled;
597 for (i = 0; i < nitems(sc->fw_msg_handler); i++)
598 sc->fw_msg_handler[i] = fw_msg_not_handled;
599 t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl);
600 t4_register_cpl_handler(sc, CPL_TRACE_PKT, t4_trace_pkt);
601 t4_register_cpl_handler(sc, CPL_TRACE_PKT_T5, t5_trace_pkt);
602 t4_init_sge_cpl_handlers(sc);
604 /* Prepare the adapter for operation */
605 rc = -t4_prep_adapter(sc);
607 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
612 * Do this really early, with the memory windows set up even before the
613 * character device. The userland tool's register i/o and mem read
614 * will work even in "recovery mode".
617 sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw,
618 device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s",
619 device_get_nameunit(dev));
620 if (sc->cdev == NULL)
621 device_printf(dev, "failed to create nexus char device.\n");
623 sc->cdev->si_drv1 = sc;
625 /* Go no further if recovery mode has been requested. */
626 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
627 device_printf(dev, "recovery mode.\n");
631 /* Prepare the firmware for operation */
632 rc = prep_firmware(sc);
634 goto done; /* error message displayed already */
636 rc = get_params__post_init(sc);
638 goto done; /* error message displayed already */
640 rc = set_params__post_init(sc);
642 goto done; /* error message displayed already */
646 goto done; /* error message displayed already */
648 rc = t4_create_dma_tag(sc);
650 goto done; /* error message displayed already */
653 * First pass over all the ports - allocate VIs and initialize some
654 * basic parameters like mac address, port type, etc. We also figure
655 * out whether a port is 10G or 1G and use that information when
656 * calculating how many interrupts to attempt to allocate.
659 for_each_port(sc, i) {
660 struct port_info *pi;
662 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
665 /* These must be set before t4_port_init */
669 /* Allocate the vi and initialize parameters like mac addr */
670 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0);
672 device_printf(dev, "unable to initialize port %d: %d\n",
679 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
680 device_get_nameunit(dev), i);
681 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
682 sc->chan_map[pi->tx_chan] = i;
684 if (is_10G_port(pi) || is_40G_port(pi)) {
686 pi->tmr_idx = t4_tmr_idx_10g;
687 pi->pktc_idx = t4_pktc_idx_10g;
690 pi->tmr_idx = t4_tmr_idx_1g;
691 pi->pktc_idx = t4_pktc_idx_1g;
694 pi->xact_addr_filt = -1;
697 pi->qsize_rxq = t4_qsize_rxq;
698 pi->qsize_txq = t4_qsize_txq;
700 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
701 if (pi->dev == NULL) {
703 "failed to add device for port %d.\n", i);
707 device_set_softc(pi->dev, pi);
711 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
713 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
715 goto done; /* error message displayed already */
717 sc->intr_type = iaq.intr_type;
718 sc->intr_count = iaq.nirq;
719 sc->flags |= iaq.intr_flags;
722 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
723 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
724 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
725 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
726 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
729 if (is_offload(sc)) {
731 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
732 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
733 s->neq += s->nofldtxq + s->nofldrxq;
734 s->niq += s->nofldrxq;
736 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
737 M_CXGBE, M_ZERO | M_WAITOK);
738 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
739 M_CXGBE, M_ZERO | M_WAITOK);
743 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
745 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
747 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
749 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
751 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
754 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
757 t4_init_l2t(sc, M_WAITOK);
760 * Second pass over the ports. This time we know the number of rx and
761 * tx queues that each port should get.
765 ofld_rqidx = ofld_tqidx = 0;
767 for_each_port(sc, i) {
768 struct port_info *pi = sc->port[i];
773 pi->first_rxq = rqidx;
774 pi->first_txq = tqidx;
775 if (is_10G_port(pi) || is_40G_port(pi)) {
776 pi->nrxq = iaq.nrxq10g;
777 pi->ntxq = iaq.ntxq10g;
779 pi->nrxq = iaq.nrxq1g;
780 pi->ntxq = iaq.ntxq1g;
787 if (is_offload(sc)) {
788 pi->first_ofld_rxq = ofld_rqidx;
789 pi->first_ofld_txq = ofld_tqidx;
790 if (is_10G_port(pi) || is_40G_port(pi)) {
791 pi->nofldrxq = iaq.nofldrxq10g;
792 pi->nofldtxq = iaq.nofldtxq10g;
794 pi->nofldrxq = iaq.nofldrxq1g;
795 pi->nofldtxq = iaq.nofldtxq1g;
797 ofld_rqidx += pi->nofldrxq;
798 ofld_tqidx += pi->nofldtxq;
803 rc = setup_intr_handlers(sc);
806 "failed to setup interrupt handlers: %d\n", rc);
810 rc = bus_generic_attach(dev);
813 "failed to attach all child ports: %d\n", rc);
818 "PCIe x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
819 sc->params.pci.width, sc->params.nports, sc->intr_count,
820 sc->intr_type == INTR_MSIX ? "MSI-X" :
821 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
822 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
827 if (rc != 0 && sc->cdev) {
828 /* cdev was created and so cxgbetool works; recover that way. */
830 "error during attach, adapter is now in recovery mode.\n");
846 t4_detach(device_t dev)
849 struct port_info *pi;
852 sc = device_get_softc(dev);
854 if (sc->flags & FULL_INIT_DONE)
858 destroy_dev(sc->cdev);
862 rc = bus_generic_detach(dev);
865 "failed to detach child devices: %d\n", rc);
869 for (i = 0; i < sc->intr_count; i++)
870 t4_free_irq(sc, &sc->irq[i]);
872 for (i = 0; i < MAX_NPORTS; i++) {
875 t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid);
877 device_delete_child(dev, pi->dev);
879 mtx_destroy(&pi->pi_lock);
884 if (sc->flags & FULL_INIT_DONE)
885 adapter_full_uninit(sc);
887 if (sc->flags & FW_OK)
888 t4_fw_bye(sc, sc->mbox);
890 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
891 pci_release_msi(dev);
894 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
898 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
902 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
906 t4_free_l2t(sc->l2t);
909 free(sc->sge.ofld_rxq, M_CXGBE);
910 free(sc->sge.ofld_txq, M_CXGBE);
912 free(sc->irq, M_CXGBE);
913 free(sc->sge.rxq, M_CXGBE);
914 free(sc->sge.txq, M_CXGBE);
915 free(sc->sge.ctrlq, M_CXGBE);
916 free(sc->sge.iqmap, M_CXGBE);
917 free(sc->sge.eqmap, M_CXGBE);
918 free(sc->tids.ftid_tab, M_CXGBE);
919 t4_destroy_dma_tag(sc);
920 if (mtx_initialized(&sc->sc_lock)) {
921 sx_xlock(&t4_list_lock);
922 SLIST_REMOVE(&t4_list, sc, adapter, link);
923 sx_xunlock(&t4_list_lock);
924 mtx_destroy(&sc->sc_lock);
927 if (mtx_initialized(&sc->tids.ftid_lock))
928 mtx_destroy(&sc->tids.ftid_lock);
929 if (mtx_initialized(&sc->sfl_lock))
930 mtx_destroy(&sc->sfl_lock);
931 if (mtx_initialized(&sc->ifp_lock))
932 mtx_destroy(&sc->ifp_lock);
934 bzero(sc, sizeof(*sc));
941 cxgbe_probe(device_t dev)
944 struct port_info *pi = device_get_softc(dev);
946 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
947 device_set_desc_copy(dev, buf);
949 return (BUS_PROBE_DEFAULT);
952 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
953 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
954 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
955 #define T4_CAP_ENABLE (T4_CAP)
958 cxgbe_attach(device_t dev)
960 struct port_info *pi = device_get_softc(dev);
963 /* Allocate an ifnet and set it up */
964 ifp = if_alloc(IFT_ETHER);
966 device_printf(dev, "Cannot allocate ifnet\n");
972 callout_init(&pi->tick, CALLOUT_MPSAFE);
974 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
975 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
977 ifp->if_init = cxgbe_init;
978 ifp->if_ioctl = cxgbe_ioctl;
979 ifp->if_transmit = cxgbe_transmit;
980 ifp->if_qflush = cxgbe_qflush;
982 ifp->if_capabilities = T4_CAP;
984 if (is_offload(pi->adapter))
985 ifp->if_capabilities |= IFCAP_TOE;
987 ifp->if_capenable = T4_CAP_ENABLE;
988 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
989 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
991 /* Initialize ifmedia for this port */
992 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
996 pi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
997 EVENTHANDLER_PRI_ANY);
999 ether_ifattach(ifp, pi->hw_addr);
1002 if (is_offload(pi->adapter)) {
1004 "%d txq, %d rxq (NIC); %d txq, %d rxq (TOE)\n",
1005 pi->ntxq, pi->nrxq, pi->nofldtxq, pi->nofldrxq);
1008 device_printf(dev, "%d txq, %d rxq\n", pi->ntxq, pi->nrxq);
1016 cxgbe_detach(device_t dev)
1018 struct port_info *pi = device_get_softc(dev);
1019 struct adapter *sc = pi->adapter;
1020 struct ifnet *ifp = pi->ifp;
1022 /* Tell if_ioctl and if_init that the port is going away */
1027 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
1030 sc->last_op = "t4detach";
1031 sc->last_op_thr = curthread;
1035 if (pi->flags & HAS_TRACEQ) {
1036 sc->traceq = -1; /* cloner should not create ifnet */
1037 t4_tracer_port_detach(sc);
1041 EVENTHANDLER_DEREGISTER(vlan_config, pi->vlan_c);
1044 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1045 callout_stop(&pi->tick);
1047 callout_drain(&pi->tick);
1049 /* Let detach proceed even if these fail. */
1050 cxgbe_uninit_synchronized(pi);
1051 port_full_uninit(pi);
1053 ifmedia_removeall(&pi->media);
1054 ether_ifdetach(pi->ifp);
1066 cxgbe_init(void *arg)
1068 struct port_info *pi = arg;
1069 struct adapter *sc = pi->adapter;
1071 if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4init") != 0)
1073 cxgbe_init_synchronized(pi);
1074 end_synchronized_op(sc, 0);
1078 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1080 int rc = 0, mtu, flags;
1081 struct port_info *pi = ifp->if_softc;
1082 struct adapter *sc = pi->adapter;
1083 struct ifreq *ifr = (struct ifreq *)data;
1089 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1092 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4mtu");
1096 if (pi->flags & PORT_INIT_DONE) {
1097 t4_update_fl_bufsize(ifp);
1098 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1099 rc = update_mac_settings(pi, XGMAC_MTU);
1101 end_synchronized_op(sc, 0);
1105 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4flg");
1109 if (ifp->if_flags & IFF_UP) {
1110 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1111 flags = pi->if_flags;
1112 if ((ifp->if_flags ^ flags) &
1113 (IFF_PROMISC | IFF_ALLMULTI)) {
1114 rc = update_mac_settings(pi,
1115 XGMAC_PROMISC | XGMAC_ALLMULTI);
1118 rc = cxgbe_init_synchronized(pi);
1119 pi->if_flags = ifp->if_flags;
1120 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1121 rc = cxgbe_uninit_synchronized(pi);
1122 end_synchronized_op(sc, 0);
1126 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1127 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4multi");
1130 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1131 rc = update_mac_settings(pi, XGMAC_MCADDRS);
1132 end_synchronized_op(sc, LOCK_HELD);
1136 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4cap");
1140 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1141 if (mask & IFCAP_TXCSUM) {
1142 ifp->if_capenable ^= IFCAP_TXCSUM;
1143 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1145 if (IFCAP_TSO4 & ifp->if_capenable &&
1146 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1147 ifp->if_capenable &= ~IFCAP_TSO4;
1149 "tso4 disabled due to -txcsum.\n");
1152 if (mask & IFCAP_TXCSUM_IPV6) {
1153 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1154 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1156 if (IFCAP_TSO6 & ifp->if_capenable &&
1157 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1158 ifp->if_capenable &= ~IFCAP_TSO6;
1160 "tso6 disabled due to -txcsum6.\n");
1163 if (mask & IFCAP_RXCSUM)
1164 ifp->if_capenable ^= IFCAP_RXCSUM;
1165 if (mask & IFCAP_RXCSUM_IPV6)
1166 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1169 * Note that we leave CSUM_TSO alone (it is always set). The
1170 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1171 * sending a TSO request our way, so it's sufficient to toggle
1174 if (mask & IFCAP_TSO4) {
1175 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1176 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1177 if_printf(ifp, "enable txcsum first.\n");
1181 ifp->if_capenable ^= IFCAP_TSO4;
1183 if (mask & IFCAP_TSO6) {
1184 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1185 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1186 if_printf(ifp, "enable txcsum6 first.\n");
1190 ifp->if_capenable ^= IFCAP_TSO6;
1192 if (mask & IFCAP_LRO) {
1193 #if defined(INET) || defined(INET6)
1195 struct sge_rxq *rxq;
1197 ifp->if_capenable ^= IFCAP_LRO;
1198 for_each_rxq(pi, i, rxq) {
1199 if (ifp->if_capenable & IFCAP_LRO)
1200 rxq->iq.flags |= IQ_LRO_ENABLED;
1202 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1207 if (mask & IFCAP_TOE) {
1208 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1210 rc = toe_capability(pi, enable);
1214 ifp->if_capenable ^= mask;
1217 if (mask & IFCAP_VLAN_HWTAGGING) {
1218 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1219 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1220 rc = update_mac_settings(pi, XGMAC_VLANEX);
1222 if (mask & IFCAP_VLAN_MTU) {
1223 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1225 /* Need to find out how to disable auto-mtu-inflation */
1227 if (mask & IFCAP_VLAN_HWTSO)
1228 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1229 if (mask & IFCAP_VLAN_HWCSUM)
1230 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1232 #ifdef VLAN_CAPABILITIES
1233 VLAN_CAPABILITIES(ifp);
1236 end_synchronized_op(sc, 0);
1241 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1245 rc = ether_ioctl(ifp, cmd, data);
1252 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1254 struct port_info *pi = ifp->if_softc;
1255 struct adapter *sc = pi->adapter;
1256 struct sge_txq *txq = &sc->sge.txq[pi->first_txq];
1257 struct buf_ring *br;
1262 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1267 if (m->m_flags & M_FLOWID)
1268 txq += (m->m_pkthdr.flowid % pi->ntxq);
1271 if (TXQ_TRYLOCK(txq) == 0) {
1272 struct sge_eq *eq = &txq->eq;
1275 * It is possible that t4_eth_tx finishes up and releases the
1276 * lock between the TRYLOCK above and the drbr_enqueue here. We
1277 * need to make sure that this mbuf doesn't just sit there in
1281 rc = drbr_enqueue(ifp, br, m);
1282 if (rc == 0 && callout_pending(&eq->tx_callout) == 0 &&
1283 !(eq->flags & EQ_DOOMED))
1284 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
1289 * txq->m is the mbuf that is held up due to a temporary shortage of
1290 * resources and it should be put on the wire first. Then what's in
1291 * drbr and finally the mbuf that was just passed in to us.
1293 * Return code should indicate the fate of the mbuf that was passed in
1297 TXQ_LOCK_ASSERT_OWNED(txq);
1298 if (drbr_needs_enqueue(ifp, br) || txq->m) {
1300 /* Queued for transmission. */
1302 rc = drbr_enqueue(ifp, br, m);
1303 m = txq->m ? txq->m : drbr_dequeue(ifp, br);
1304 (void) t4_eth_tx(ifp, txq, m);
1309 /* Direct transmission. */
1310 rc = t4_eth_tx(ifp, txq, m);
1311 if (rc != 0 && txq->m)
1312 rc = 0; /* held, will be transmitted soon (hopefully) */
1319 cxgbe_qflush(struct ifnet *ifp)
1321 struct port_info *pi = ifp->if_softc;
1322 struct sge_txq *txq;
1326 /* queues do not exist if !PORT_INIT_DONE. */
1327 if (pi->flags & PORT_INIT_DONE) {
1328 for_each_txq(pi, i, txq) {
1332 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
1341 cxgbe_media_change(struct ifnet *ifp)
1343 struct port_info *pi = ifp->if_softc;
1345 device_printf(pi->dev, "%s unimplemented.\n", __func__);
1347 return (EOPNOTSUPP);
1351 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1353 struct port_info *pi = ifp->if_softc;
1354 struct ifmedia_entry *cur = pi->media.ifm_cur;
1355 int speed = pi->link_cfg.speed;
1356 int data = (pi->port_type << 8) | pi->mod_type;
1358 if (cur->ifm_data != data) {
1359 build_medialist(pi);
1360 cur = pi->media.ifm_cur;
1363 ifmr->ifm_status = IFM_AVALID;
1364 if (!pi->link_cfg.link_ok)
1367 ifmr->ifm_status |= IFM_ACTIVE;
1369 /* active and current will differ iff current media is autoselect. */
1370 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1373 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1374 if (speed == SPEED_10000)
1375 ifmr->ifm_active |= IFM_10G_T;
1376 else if (speed == SPEED_1000)
1377 ifmr->ifm_active |= IFM_1000_T;
1378 else if (speed == SPEED_100)
1379 ifmr->ifm_active |= IFM_100_TX;
1380 else if (speed == SPEED_10)
1381 ifmr->ifm_active |= IFM_10_T;
1383 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1388 t4_fatal_err(struct adapter *sc)
1390 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1391 t4_intr_disable(sc);
1392 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1393 device_get_nameunit(sc->dev));
1397 map_bars_0_and_4(struct adapter *sc)
1399 sc->regs_rid = PCIR_BAR(0);
1400 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1401 &sc->regs_rid, RF_ACTIVE);
1402 if (sc->regs_res == NULL) {
1403 device_printf(sc->dev, "cannot map registers.\n");
1406 sc->bt = rman_get_bustag(sc->regs_res);
1407 sc->bh = rman_get_bushandle(sc->regs_res);
1408 sc->mmio_len = rman_get_size(sc->regs_res);
1409 setbit(&sc->doorbells, DOORBELL_KDB);
1411 sc->msix_rid = PCIR_BAR(4);
1412 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1413 &sc->msix_rid, RF_ACTIVE);
1414 if (sc->msix_res == NULL) {
1415 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1423 map_bar_2(struct adapter *sc)
1427 * T4: only iWARP driver uses the userspace doorbells. There is no need
1428 * to map it if RDMA is disabled.
1430 if (is_t4(sc) && sc->rdmacaps == 0)
1433 sc->udbs_rid = PCIR_BAR(2);
1434 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1435 &sc->udbs_rid, RF_ACTIVE);
1436 if (sc->udbs_res == NULL) {
1437 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1440 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1443 setbit(&sc->doorbells, DOORBELL_UDB);
1444 #if defined(__i386__) || defined(__amd64__)
1445 if (t5_write_combine) {
1449 * Enable write combining on BAR2. This is the
1450 * userspace doorbell BAR and is split into 128B
1451 * (UDBS_SEG_SIZE) doorbell regions, each associated
1452 * with an egress queue. The first 64B has the doorbell
1453 * and the second 64B can be used to submit a tx work
1454 * request with an implicit doorbell.
1457 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1458 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1460 clrbit(&sc->doorbells, DOORBELL_UDB);
1461 setbit(&sc->doorbells, DOORBELL_WCWR);
1462 setbit(&sc->doorbells, DOORBELL_UDBWC);
1464 device_printf(sc->dev,
1465 "couldn't enable write combining: %d\n",
1469 t4_write_reg(sc, A_SGE_STAT_CFG,
1470 V_STATSOURCE_T5(7) | V_STATMODE(0));
1478 static const struct memwin t4_memwin[] = {
1479 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1480 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1481 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1484 static const struct memwin t5_memwin[] = {
1485 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1486 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1487 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1491 setup_memwin(struct adapter *sc)
1493 const struct memwin *mw;
1499 * Read low 32b of bar0 indirectly via the hardware backdoor
1500 * mechanism. Works from within PCI passthrough environments
1501 * too, where rman_get_start() can return a different value. We
1502 * need to program the T4 memory window decoders with the actual
1503 * addresses that will be coming across the PCIe link.
1505 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1506 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1509 n = nitems(t4_memwin);
1511 /* T5 uses the relative offset inside the PCIe BAR */
1515 n = nitems(t5_memwin);
1518 for (i = 0; i < n; i++, mw++) {
1520 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1521 (mw->base + bar0) | V_BIR(0) |
1522 V_WINDOW(ilog2(mw->aperture) - 10));
1526 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1530 * Verify that the memory range specified by the addr/len pair is valid and lies
1531 * entirely within a single region (EDCx or MCx).
1534 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
1536 uint32_t em, addr_len, maddr, mlen;
1538 /* Memory can only be accessed in naturally aligned 4 byte units */
1539 if (addr & 3 || len & 3 || len == 0)
1542 /* Enabled memories */
1543 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
1544 if (em & F_EDRAM0_ENABLE) {
1545 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
1546 maddr = G_EDRAM0_BASE(addr_len) << 20;
1547 mlen = G_EDRAM0_SIZE(addr_len) << 20;
1548 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1549 addr + len <= maddr + mlen)
1552 if (em & F_EDRAM1_ENABLE) {
1553 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
1554 maddr = G_EDRAM1_BASE(addr_len) << 20;
1555 mlen = G_EDRAM1_SIZE(addr_len) << 20;
1556 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1557 addr + len <= maddr + mlen)
1560 if (em & F_EXT_MEM_ENABLE) {
1561 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
1562 maddr = G_EXT_MEM_BASE(addr_len) << 20;
1563 mlen = G_EXT_MEM_SIZE(addr_len) << 20;
1564 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1565 addr + len <= maddr + mlen)
1568 if (!is_t4(sc) && em & F_EXT_MEM1_ENABLE) {
1569 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
1570 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
1571 mlen = G_EXT_MEM1_SIZE(addr_len) << 20;
1572 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1573 addr + len <= maddr + mlen)
1581 fwmtype_to_hwmtype(int mtype)
1585 case FW_MEMTYPE_EDC0:
1587 case FW_MEMTYPE_EDC1:
1589 case FW_MEMTYPE_EXTMEM:
1591 case FW_MEMTYPE_EXTMEM1:
1594 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
1599 * Verify that the memory range specified by the memtype/offset/len pair is
1600 * valid and lies entirely within the memtype specified. The global address of
1601 * the start of the range is returned in addr.
1604 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
1607 uint32_t em, addr_len, maddr, mlen;
1609 /* Memory can only be accessed in naturally aligned 4 byte units */
1610 if (off & 3 || len & 3 || len == 0)
1613 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
1614 switch (fwmtype_to_hwmtype(mtype)) {
1616 if (!(em & F_EDRAM0_ENABLE))
1618 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
1619 maddr = G_EDRAM0_BASE(addr_len) << 20;
1620 mlen = G_EDRAM0_SIZE(addr_len) << 20;
1623 if (!(em & F_EDRAM1_ENABLE))
1625 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
1626 maddr = G_EDRAM1_BASE(addr_len) << 20;
1627 mlen = G_EDRAM1_SIZE(addr_len) << 20;
1630 if (!(em & F_EXT_MEM_ENABLE))
1632 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
1633 maddr = G_EXT_MEM_BASE(addr_len) << 20;
1634 mlen = G_EXT_MEM_SIZE(addr_len) << 20;
1637 if (is_t4(sc) || !(em & F_EXT_MEM1_ENABLE))
1639 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
1640 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
1641 mlen = G_EXT_MEM1_SIZE(addr_len) << 20;
1647 if (mlen > 0 && off < mlen && off + len <= mlen) {
1648 *addr = maddr + off; /* global address */
1656 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture)
1658 const struct memwin *mw;
1661 KASSERT(win >= 0 && win < nitems(t4_memwin),
1662 ("%s: incorrect memwin# (%d)", __func__, win));
1663 mw = &t4_memwin[win];
1665 KASSERT(win >= 0 && win < nitems(t5_memwin),
1666 ("%s: incorrect memwin# (%d)", __func__, win));
1667 mw = &t5_memwin[win];
1672 if (aperture != NULL)
1673 *aperture = mw->aperture;
1677 * Positions the memory window such that it can be used to access the specified
1678 * address in the chip's address space. The return value is the offset of addr
1679 * from the start of the window.
1682 position_memwin(struct adapter *sc, int n, uint32_t addr)
1687 KASSERT(n >= 0 && n <= 3,
1688 ("%s: invalid window %d.", __func__, n));
1689 KASSERT((addr & 3) == 0,
1690 ("%s: addr (0x%x) is not at a 4B boundary.", __func__, addr));
1694 start = addr & ~0xf; /* start must be 16B aligned */
1696 pf = V_PFNUM(sc->pf);
1697 start = addr & ~0x7f; /* start must be 128B aligned */
1699 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n);
1701 t4_write_reg(sc, reg, start | pf);
1702 t4_read_reg(sc, reg);
1704 return (addr - start);
1708 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
1709 struct intrs_and_queues *iaq)
1711 int rc, itype, navail, nrxq10g, nrxq1g, n;
1712 int nofldrxq10g = 0, nofldrxq1g = 0;
1714 bzero(iaq, sizeof(*iaq));
1716 iaq->ntxq10g = t4_ntxq10g;
1717 iaq->ntxq1g = t4_ntxq1g;
1718 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
1719 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
1721 if (is_offload(sc)) {
1722 iaq->nofldtxq10g = t4_nofldtxq10g;
1723 iaq->nofldtxq1g = t4_nofldtxq1g;
1724 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
1725 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
1729 for (itype = INTR_MSIX; itype; itype >>= 1) {
1731 if ((itype & t4_intr_types) == 0)
1732 continue; /* not allowed */
1734 if (itype == INTR_MSIX)
1735 navail = pci_msix_count(sc->dev);
1736 else if (itype == INTR_MSI)
1737 navail = pci_msi_count(sc->dev);
1744 iaq->intr_type = itype;
1745 iaq->intr_flags = 0;
1748 * Best option: an interrupt vector for errors, one for the
1749 * firmware event queue, and one each for each rxq (NIC as well
1752 iaq->nirq = T4_EXTRA_INTR;
1753 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
1754 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
1755 if (iaq->nirq <= navail &&
1756 (itype != INTR_MSI || powerof2(iaq->nirq))) {
1757 iaq->intr_flags |= INTR_DIRECT;
1762 * Second best option: an interrupt vector for errors, one for
1763 * the firmware event queue, and one each for either NIC or
1766 iaq->nirq = T4_EXTRA_INTR;
1767 iaq->nirq += n10g * max(nrxq10g, nofldrxq10g);
1768 iaq->nirq += n1g * max(nrxq1g, nofldrxq1g);
1769 if (iaq->nirq <= navail &&
1770 (itype != INTR_MSI || powerof2(iaq->nirq)))
1774 * Next best option: an interrupt vector for errors, one for the
1775 * firmware event queue, and at least one per port. At this
1776 * point we know we'll have to downsize nrxq or nofldrxq to fit
1777 * what's available to us.
1779 iaq->nirq = T4_EXTRA_INTR;
1780 iaq->nirq += n10g + n1g;
1781 if (iaq->nirq <= navail) {
1782 int leftover = navail - iaq->nirq;
1785 int target = max(nrxq10g, nofldrxq10g);
1788 while (n < target && leftover >= n10g) {
1793 iaq->nrxq10g = min(n, nrxq10g);
1796 iaq->nofldrxq10g = min(n, nofldrxq10g);
1801 int target = max(nrxq1g, nofldrxq1g);
1804 while (n < target && leftover >= n1g) {
1809 iaq->nrxq1g = min(n, nrxq1g);
1812 iaq->nofldrxq1g = min(n, nofldrxq1g);
1816 if (itype != INTR_MSI || powerof2(iaq->nirq))
1821 * Least desirable option: one interrupt vector for everything.
1823 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
1826 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
1832 if (itype == INTR_MSIX)
1833 rc = pci_alloc_msix(sc->dev, &navail);
1834 else if (itype == INTR_MSI)
1835 rc = pci_alloc_msi(sc->dev, &navail);
1838 if (navail == iaq->nirq)
1842 * Didn't get the number requested. Use whatever number
1843 * the kernel is willing to allocate (it's in navail).
1845 device_printf(sc->dev, "fewer vectors than requested, "
1846 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
1847 itype, iaq->nirq, navail);
1848 pci_release_msi(sc->dev);
1852 device_printf(sc->dev,
1853 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
1854 itype, rc, iaq->nirq, navail);
1857 device_printf(sc->dev,
1858 "failed to find a usable interrupt type. "
1859 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
1860 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
1865 #define FW_VERSION(chip) ( \
1866 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
1867 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
1868 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
1869 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
1870 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
1876 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
1880 .kld_name = "t4fw_cfg",
1881 .fw_mod_name = "t4fw",
1883 .chip = FW_HDR_CHIP_T4,
1884 .fw_ver = htobe32_const(FW_VERSION(T4)),
1885 .intfver_nic = FW_INTFVER(T4, NIC),
1886 .intfver_vnic = FW_INTFVER(T4, VNIC),
1887 .intfver_ofld = FW_INTFVER(T4, OFLD),
1888 .intfver_ri = FW_INTFVER(T4, RI),
1889 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
1890 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
1891 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
1892 .intfver_fcoe = FW_INTFVER(T4, FCOE),
1896 .kld_name = "t5fw_cfg",
1897 .fw_mod_name = "t5fw",
1899 .chip = FW_HDR_CHIP_T5,
1900 .fw_ver = htobe32_const(FW_VERSION(T5)),
1901 .intfver_nic = FW_INTFVER(T5, NIC),
1902 .intfver_vnic = FW_INTFVER(T5, VNIC),
1903 .intfver_ofld = FW_INTFVER(T5, OFLD),
1904 .intfver_ri = FW_INTFVER(T5, RI),
1905 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
1906 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
1907 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
1908 .intfver_fcoe = FW_INTFVER(T5, FCOE),
1913 static struct fw_info *
1914 find_fw_info(int chip)
1918 for (i = 0; i < nitems(fw_info); i++) {
1919 if (fw_info[i].chip == chip)
1920 return (&fw_info[i]);
1926 * Is the given firmware API compatible with the one the driver was compiled
1930 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
1933 /* short circuit if it's the exact same firmware version */
1934 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
1938 * XXX: Is this too conservative? Perhaps I should limit this to the
1939 * features that are supported in the driver.
1941 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
1942 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
1943 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
1944 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
1952 * The firmware in the KLD is usable, but should it be installed? This routine
1953 * explains itself in detail if it indicates the KLD firmware should be
1957 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
1961 if (!card_fw_usable) {
1962 reason = "incompatible or unusable";
1967 reason = "older than the version bundled with this driver";
1971 if (t4_fw_install == 2 && k != c) {
1972 reason = "different than the version bundled with this driver";
1979 if (t4_fw_install == 0) {
1980 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
1981 "but the driver is prohibited from installing a different "
1982 "firmware on the card.\n",
1983 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
1984 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
1989 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
1990 "installing firmware %u.%u.%u.%u on card.\n",
1991 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
1992 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
1993 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
1994 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
1999 * Establish contact with the firmware and determine if we are the master driver
2000 * or not, and whether we are responsible for chip initialization.
2003 prep_firmware(struct adapter *sc)
2005 const struct firmware *fw = NULL, *default_cfg;
2006 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2007 enum dev_state state;
2008 struct fw_info *fw_info;
2009 struct fw_hdr *card_fw; /* fw on the card */
2010 const struct fw_hdr *kld_fw; /* fw in the KLD */
2011 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2014 /* Contact firmware. */
2015 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2016 if (rc < 0 || state == DEV_STATE_ERR) {
2018 device_printf(sc->dev,
2019 "failed to connect to the firmware: %d, %d.\n", rc, state);
2024 sc->flags |= MASTER_PF;
2025 else if (state == DEV_STATE_UNINIT) {
2027 * We didn't get to be the master so we definitely won't be
2028 * configuring the chip. It's a bug if someone else hasn't
2029 * configured it already.
2031 device_printf(sc->dev, "couldn't be master(%d), "
2032 "device not already initialized either(%d).\n", rc, state);
2036 /* This is the firmware whose headers the driver was compiled against */
2037 fw_info = find_fw_info(chip_id(sc));
2038 if (fw_info == NULL) {
2039 device_printf(sc->dev,
2040 "unable to look up firmware information for chip %d.\n",
2044 drv_fw = &fw_info->fw_hdr;
2047 * The firmware KLD contains many modules. The KLD name is also the
2048 * name of the module that contains the default config file.
2050 default_cfg = firmware_get(fw_info->kld_name);
2052 /* Read the header of the firmware on the card */
2053 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2054 rc = -t4_read_flash(sc, FLASH_FW_START,
2055 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2057 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2059 device_printf(sc->dev,
2060 "Unable to read card's firmware header: %d\n", rc);
2064 /* This is the firmware in the KLD */
2065 fw = firmware_get(fw_info->fw_mod_name);
2067 kld_fw = (const void *)fw->data;
2068 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2074 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2075 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2077 * Common case: the firmware on the card is an exact match and
2078 * the KLD is an exact match too, or the KLD is
2079 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2080 * here -- use cxgbetool loadfw if you want to reinstall the
2081 * same firmware as the one on the card.
2083 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2084 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2085 be32toh(card_fw->fw_ver))) {
2087 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2089 device_printf(sc->dev,
2090 "failed to install firmware: %d\n", rc);
2094 /* Installed successfully, update the cached header too. */
2095 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2097 need_fw_reset = 0; /* already reset as part of load_fw */
2100 if (!card_fw_usable) {
2103 d = ntohl(drv_fw->fw_ver);
2104 c = ntohl(card_fw->fw_ver);
2105 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2107 device_printf(sc->dev, "Cannot find a usable firmware: "
2108 "fw_install %d, chip state %d, "
2109 "driver compiled with %d.%d.%d.%d, "
2110 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2111 t4_fw_install, state,
2112 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2113 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2114 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2115 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2116 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2117 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2122 /* We're using whatever's on the card and it's known to be good. */
2123 sc->params.fw_vers = ntohl(card_fw->fw_ver);
2124 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2125 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2126 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2127 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2128 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2129 t4_get_tp_version(sc, &sc->params.tp_vers);
2132 if (need_fw_reset &&
2133 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2134 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2135 if (rc != ETIMEDOUT && rc != EIO)
2136 t4_fw_bye(sc, sc->mbox);
2141 rc = get_params__pre_init(sc);
2143 goto done; /* error message displayed already */
2145 /* Partition adapter resources as specified in the config file. */
2146 if (state == DEV_STATE_UNINIT) {
2148 KASSERT(sc->flags & MASTER_PF,
2149 ("%s: trying to change chip settings when not master.",
2152 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2154 goto done; /* error message displayed already */
2156 t4_tweak_chip_settings(sc);
2158 /* get basic stuff going */
2159 rc = -t4_fw_initialize(sc, sc->mbox);
2161 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2165 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2170 free(card_fw, M_CXGBE);
2172 firmware_put(fw, FIRMWARE_UNLOAD);
2173 if (default_cfg != NULL)
2174 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2179 #define FW_PARAM_DEV(param) \
2180 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2181 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2182 #define FW_PARAM_PFVF(param) \
2183 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2184 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2187 * Partition chip resources for use between various PFs, VFs, etc.
2190 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2191 const char *name_prefix)
2193 const struct firmware *cfg = NULL;
2195 struct fw_caps_config_cmd caps;
2196 uint32_t mtype, moff, finicsum, cfcsum;
2199 * Figure out what configuration file to use. Pick the default config
2200 * file for the card if the user hasn't specified one explicitly.
2202 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2203 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2204 /* Card specific overrides go here. */
2205 if (pci_get_device(sc->dev) == 0x440a)
2206 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2208 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2212 * We need to load another module if the profile is anything except
2213 * "default" or "flash".
2215 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2216 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2219 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2220 cfg = firmware_get(s);
2222 if (default_cfg != NULL) {
2223 device_printf(sc->dev,
2224 "unable to load module \"%s\" for "
2225 "configuration profile \"%s\", will use "
2226 "the default config file instead.\n",
2228 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2231 device_printf(sc->dev,
2232 "unable to load module \"%s\" for "
2233 "configuration profile \"%s\", will use "
2234 "the config file on the card's flash "
2235 "instead.\n", s, sc->cfg_file);
2236 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2242 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2243 default_cfg == NULL) {
2244 device_printf(sc->dev,
2245 "default config file not available, will use the config "
2246 "file on the card's flash instead.\n");
2247 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2250 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2252 const uint32_t *cfdata;
2253 uint32_t param, val, addr, off, mw_base, mw_aperture;
2255 KASSERT(cfg != NULL || default_cfg != NULL,
2256 ("%s: no config to upload", __func__));
2259 * Ask the firmware where it wants us to upload the config file.
2261 param = FW_PARAM_DEV(CF);
2262 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2264 /* No support for config file? Shouldn't happen. */
2265 device_printf(sc->dev,
2266 "failed to query config file location: %d.\n", rc);
2269 mtype = G_FW_PARAMS_PARAM_Y(val);
2270 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2273 * XXX: sheer laziness. We deliberately added 4 bytes of
2274 * useless stuffing/comments at the end of the config file so
2275 * it's ok to simply throw away the last remaining bytes when
2276 * the config file is not an exact multiple of 4. This also
2277 * helps with the validate_mt_off_len check.
2280 cflen = cfg->datasize & ~3;
2283 cflen = default_cfg->datasize & ~3;
2284 cfdata = default_cfg->data;
2287 if (cflen > FLASH_CFG_MAX_SIZE) {
2288 device_printf(sc->dev,
2289 "config file too long (%d, max allowed is %d). "
2290 "Will try to use the config on the card, if any.\n",
2291 cflen, FLASH_CFG_MAX_SIZE);
2292 goto use_config_on_flash;
2295 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2297 device_printf(sc->dev,
2298 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
2299 "Will try to use the config on the card, if any.\n",
2300 __func__, mtype, moff, cflen, rc);
2301 goto use_config_on_flash;
2304 memwin_info(sc, 2, &mw_base, &mw_aperture);
2306 off = position_memwin(sc, 2, addr);
2307 n = min(cflen, mw_aperture - off);
2308 for (i = 0; i < n; i += 4)
2309 t4_write_reg(sc, mw_base + off + i, *cfdata++);
2314 use_config_on_flash:
2315 mtype = FW_MEMTYPE_FLASH;
2316 moff = t4_flash_cfg_addr(sc);
2319 bzero(&caps, sizeof(caps));
2320 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2321 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2322 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2323 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2324 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2325 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2327 device_printf(sc->dev,
2328 "failed to pre-process config file: %d "
2329 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2333 finicsum = be32toh(caps.finicsum);
2334 cfcsum = be32toh(caps.cfcsum);
2335 if (finicsum != cfcsum) {
2336 device_printf(sc->dev,
2337 "WARNING: config file checksum mismatch: %08x %08x\n",
2340 sc->cfcsum = cfcsum;
2342 #define LIMIT_CAPS(x) do { \
2343 caps.x &= htobe16(t4_##x##_allowed); \
2344 sc->x = htobe16(caps.x); \
2348 * Let the firmware know what features will (not) be used so it can tune
2349 * things accordingly.
2351 LIMIT_CAPS(linkcaps);
2352 LIMIT_CAPS(niccaps);
2353 LIMIT_CAPS(toecaps);
2354 LIMIT_CAPS(rdmacaps);
2355 LIMIT_CAPS(iscsicaps);
2356 LIMIT_CAPS(fcoecaps);
2359 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2360 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2361 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2362 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2364 device_printf(sc->dev,
2365 "failed to process config file: %d.\n", rc);
2369 firmware_put(cfg, FIRMWARE_UNLOAD);
2374 * Retrieve parameters that are needed (or nice to have) very early.
2377 get_params__pre_init(struct adapter *sc)
2380 uint32_t param[2], val[2];
2381 struct fw_devlog_cmd cmd;
2382 struct devlog_params *dlog = &sc->params.devlog;
2384 param[0] = FW_PARAM_DEV(PORTVEC);
2385 param[1] = FW_PARAM_DEV(CCLK);
2386 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2388 device_printf(sc->dev,
2389 "failed to query parameters (pre_init): %d.\n", rc);
2393 sc->params.portvec = val[0];
2394 sc->params.nports = bitcount32(val[0]);
2395 sc->params.vpd.cclk = val[1];
2397 /* Read device log parameters. */
2398 bzero(&cmd, sizeof(cmd));
2399 cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
2400 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2401 cmd.retval_len16 = htobe32(FW_LEN16(cmd));
2402 rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
2404 device_printf(sc->dev,
2405 "failed to get devlog parameters: %d.\n", rc);
2406 bzero(dlog, sizeof (*dlog));
2407 rc = 0; /* devlog isn't critical for device operation */
2409 val[0] = be32toh(cmd.memtype_devlog_memaddr16_devlog);
2410 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]);
2411 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4;
2412 dlog->size = be32toh(cmd.memsize_devlog);
2419 * Retrieve various parameters that are of interest to the driver. The device
2420 * has been initialized by the firmware at this point.
2423 get_params__post_init(struct adapter *sc)
2426 uint32_t param[7], val[7];
2427 struct fw_caps_config_cmd caps;
2429 param[0] = FW_PARAM_PFVF(IQFLINT_START);
2430 param[1] = FW_PARAM_PFVF(EQ_START);
2431 param[2] = FW_PARAM_PFVF(FILTER_START);
2432 param[3] = FW_PARAM_PFVF(FILTER_END);
2433 param[4] = FW_PARAM_PFVF(L2T_START);
2434 param[5] = FW_PARAM_PFVF(L2T_END);
2435 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2437 device_printf(sc->dev,
2438 "failed to query parameters (post_init): %d.\n", rc);
2442 sc->sge.iq_start = val[0];
2443 sc->sge.eq_start = val[1];
2444 sc->tids.ftid_base = val[2];
2445 sc->tids.nftids = val[3] - val[2] + 1;
2446 sc->vres.l2t.start = val[4];
2447 sc->vres.l2t.size = val[5] - val[4] + 1;
2448 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
2449 ("%s: L2 table size (%u) larger than expected (%u)",
2450 __func__, sc->vres.l2t.size, L2T_SIZE));
2452 /* get capabilites */
2453 bzero(&caps, sizeof(caps));
2454 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2455 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2456 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2457 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2459 device_printf(sc->dev,
2460 "failed to get card capabilities: %d.\n", rc);
2465 /* query offload-related parameters */
2466 param[0] = FW_PARAM_DEV(NTID);
2467 param[1] = FW_PARAM_PFVF(SERVER_START);
2468 param[2] = FW_PARAM_PFVF(SERVER_END);
2469 param[3] = FW_PARAM_PFVF(TDDP_START);
2470 param[4] = FW_PARAM_PFVF(TDDP_END);
2471 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
2472 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2474 device_printf(sc->dev,
2475 "failed to query TOE parameters: %d.\n", rc);
2478 sc->tids.ntids = val[0];
2479 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
2480 sc->tids.stid_base = val[1];
2481 sc->tids.nstids = val[2] - val[1] + 1;
2482 sc->vres.ddp.start = val[3];
2483 sc->vres.ddp.size = val[4] - val[3] + 1;
2484 sc->params.ofldq_wr_cred = val[5];
2485 sc->params.offload = 1;
2487 if (caps.rdmacaps) {
2488 param[0] = FW_PARAM_PFVF(STAG_START);
2489 param[1] = FW_PARAM_PFVF(STAG_END);
2490 param[2] = FW_PARAM_PFVF(RQ_START);
2491 param[3] = FW_PARAM_PFVF(RQ_END);
2492 param[4] = FW_PARAM_PFVF(PBL_START);
2493 param[5] = FW_PARAM_PFVF(PBL_END);
2494 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2496 device_printf(sc->dev,
2497 "failed to query RDMA parameters(1): %d.\n", rc);
2500 sc->vres.stag.start = val[0];
2501 sc->vres.stag.size = val[1] - val[0] + 1;
2502 sc->vres.rq.start = val[2];
2503 sc->vres.rq.size = val[3] - val[2] + 1;
2504 sc->vres.pbl.start = val[4];
2505 sc->vres.pbl.size = val[5] - val[4] + 1;
2507 param[0] = FW_PARAM_PFVF(SQRQ_START);
2508 param[1] = FW_PARAM_PFVF(SQRQ_END);
2509 param[2] = FW_PARAM_PFVF(CQ_START);
2510 param[3] = FW_PARAM_PFVF(CQ_END);
2511 param[4] = FW_PARAM_PFVF(OCQ_START);
2512 param[5] = FW_PARAM_PFVF(OCQ_END);
2513 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2515 device_printf(sc->dev,
2516 "failed to query RDMA parameters(2): %d.\n", rc);
2519 sc->vres.qp.start = val[0];
2520 sc->vres.qp.size = val[1] - val[0] + 1;
2521 sc->vres.cq.start = val[2];
2522 sc->vres.cq.size = val[3] - val[2] + 1;
2523 sc->vres.ocq.start = val[4];
2524 sc->vres.ocq.size = val[5] - val[4] + 1;
2526 if (caps.iscsicaps) {
2527 param[0] = FW_PARAM_PFVF(ISCSI_START);
2528 param[1] = FW_PARAM_PFVF(ISCSI_END);
2529 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2531 device_printf(sc->dev,
2532 "failed to query iSCSI parameters: %d.\n", rc);
2535 sc->vres.iscsi.start = val[0];
2536 sc->vres.iscsi.size = val[1] - val[0] + 1;
2540 * We've got the params we wanted to query via the firmware. Now grab
2541 * some others directly from the chip.
2543 rc = t4_read_chip_settings(sc);
2549 set_params__post_init(struct adapter *sc)
2551 uint32_t param, val;
2553 /* ask for encapsulated CPLs */
2554 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
2556 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2561 #undef FW_PARAM_PFVF
2565 t4_set_desc(struct adapter *sc)
2568 struct adapter_params *p = &sc->params;
2570 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
2571 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
2572 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
2574 device_set_desc_copy(sc->dev, buf);
2578 build_medialist(struct port_info *pi)
2580 struct ifmedia *media = &pi->media;
2585 ifmedia_removeall(media);
2587 m = IFM_ETHER | IFM_FDX;
2588 data = (pi->port_type << 8) | pi->mod_type;
2590 switch(pi->port_type) {
2591 case FW_PORT_TYPE_BT_XFI:
2592 ifmedia_add(media, m | IFM_10G_T, data, NULL);
2595 case FW_PORT_TYPE_BT_XAUI:
2596 ifmedia_add(media, m | IFM_10G_T, data, NULL);
2599 case FW_PORT_TYPE_BT_SGMII:
2600 ifmedia_add(media, m | IFM_1000_T, data, NULL);
2601 ifmedia_add(media, m | IFM_100_TX, data, NULL);
2602 ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL);
2603 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
2606 case FW_PORT_TYPE_CX4:
2607 ifmedia_add(media, m | IFM_10G_CX4, data, NULL);
2608 ifmedia_set(media, m | IFM_10G_CX4);
2611 case FW_PORT_TYPE_SFP:
2612 case FW_PORT_TYPE_FIBER_XFI:
2613 case FW_PORT_TYPE_FIBER_XAUI:
2614 switch (pi->mod_type) {
2616 case FW_PORT_MOD_TYPE_LR:
2617 ifmedia_add(media, m | IFM_10G_LR, data, NULL);
2618 ifmedia_set(media, m | IFM_10G_LR);
2621 case FW_PORT_MOD_TYPE_SR:
2622 ifmedia_add(media, m | IFM_10G_SR, data, NULL);
2623 ifmedia_set(media, m | IFM_10G_SR);
2626 case FW_PORT_MOD_TYPE_LRM:
2627 ifmedia_add(media, m | IFM_10G_LRM, data, NULL);
2628 ifmedia_set(media, m | IFM_10G_LRM);
2631 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2632 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2633 ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL);
2634 ifmedia_set(media, m | IFM_10G_TWINAX);
2637 case FW_PORT_MOD_TYPE_NONE:
2639 ifmedia_add(media, m | IFM_NONE, data, NULL);
2640 ifmedia_set(media, m | IFM_NONE);
2643 case FW_PORT_MOD_TYPE_NA:
2644 case FW_PORT_MOD_TYPE_ER:
2646 device_printf(pi->dev,
2647 "unknown port_type (%d), mod_type (%d)\n",
2648 pi->port_type, pi->mod_type);
2649 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2650 ifmedia_set(media, m | IFM_UNKNOWN);
2655 case FW_PORT_TYPE_QSFP:
2656 switch (pi->mod_type) {
2658 case FW_PORT_MOD_TYPE_LR:
2659 ifmedia_add(media, m | IFM_40G_LR4, data, NULL);
2660 ifmedia_set(media, m | IFM_40G_LR4);
2663 case FW_PORT_MOD_TYPE_SR:
2664 ifmedia_add(media, m | IFM_40G_SR4, data, NULL);
2665 ifmedia_set(media, m | IFM_40G_SR4);
2668 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2669 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2670 ifmedia_add(media, m | IFM_40G_CR4, data, NULL);
2671 ifmedia_set(media, m | IFM_40G_CR4);
2674 case FW_PORT_MOD_TYPE_NONE:
2676 ifmedia_add(media, m | IFM_NONE, data, NULL);
2677 ifmedia_set(media, m | IFM_NONE);
2681 device_printf(pi->dev,
2682 "unknown port_type (%d), mod_type (%d)\n",
2683 pi->port_type, pi->mod_type);
2684 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2685 ifmedia_set(media, m | IFM_UNKNOWN);
2691 device_printf(pi->dev,
2692 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
2694 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2695 ifmedia_set(media, m | IFM_UNKNOWN);
2702 #define FW_MAC_EXACT_CHUNK 7
2705 * Program the port's XGMAC based on parameters in ifnet. The caller also
2706 * indicates which parameters should be programmed (the rest are left alone).
2709 update_mac_settings(struct port_info *pi, int flags)
2712 struct ifnet *ifp = pi->ifp;
2713 struct adapter *sc = pi->adapter;
2714 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
2716 ASSERT_SYNCHRONIZED_OP(sc);
2717 KASSERT(flags, ("%s: not told what to update.", __func__));
2719 if (flags & XGMAC_MTU)
2722 if (flags & XGMAC_PROMISC)
2723 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
2725 if (flags & XGMAC_ALLMULTI)
2726 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
2728 if (flags & XGMAC_VLANEX)
2729 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
2731 rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1,
2734 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc);
2738 if (flags & XGMAC_UCADDR) {
2739 uint8_t ucaddr[ETHER_ADDR_LEN];
2741 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
2742 rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt,
2743 ucaddr, true, true);
2746 if_printf(ifp, "change_mac failed: %d\n", rc);
2749 pi->xact_addr_filt = rc;
2754 if (flags & XGMAC_MCADDRS) {
2755 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
2758 struct ifmultiaddr *ifma;
2761 if_maddr_rlock(ifp);
2762 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2763 if (ifma->ifma_addr->sa_family != AF_LINK)
2766 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2768 if (i == FW_MAC_EXACT_CHUNK) {
2769 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid,
2770 del, i, mcaddr, NULL, &hash, 0);
2773 for (j = 0; j < i; j++) {
2775 "failed to add mc address"
2777 "%02x:%02x:%02x rc=%d\n",
2778 mcaddr[j][0], mcaddr[j][1],
2779 mcaddr[j][2], mcaddr[j][3],
2780 mcaddr[j][4], mcaddr[j][5],
2790 rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid,
2791 del, i, mcaddr, NULL, &hash, 0);
2794 for (j = 0; j < i; j++) {
2796 "failed to add mc address"
2798 "%02x:%02x:%02x rc=%d\n",
2799 mcaddr[j][0], mcaddr[j][1],
2800 mcaddr[j][2], mcaddr[j][3],
2801 mcaddr[j][4], mcaddr[j][5],
2808 rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0);
2810 if_printf(ifp, "failed to set mc address hash: %d", rc);
2812 if_maddr_runlock(ifp);
2819 begin_synchronized_op(struct adapter *sc, struct port_info *pi, int flags,
2825 /* the caller thinks it's ok to sleep, but is it really? */
2826 if (flags & SLEEP_OK)
2827 pause("t4slptst", 1);
2838 if (pi && IS_DOOMED(pi)) {
2848 if (!(flags & SLEEP_OK)) {
2853 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
2859 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
2862 sc->last_op = wmesg;
2863 sc->last_op_thr = curthread;
2867 if (!(flags & HOLD_LOCK) || rc)
2874 end_synchronized_op(struct adapter *sc, int flags)
2877 if (flags & LOCK_HELD)
2878 ADAPTER_LOCK_ASSERT_OWNED(sc);
2882 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
2889 cxgbe_init_synchronized(struct port_info *pi)
2891 struct adapter *sc = pi->adapter;
2892 struct ifnet *ifp = pi->ifp;
2895 ASSERT_SYNCHRONIZED_OP(sc);
2897 if (isset(&sc->open_device_map, pi->port_id)) {
2898 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING,
2899 ("mismatch between open_device_map and if_drv_flags"));
2900 return (0); /* already running */
2903 if (!(sc->flags & FULL_INIT_DONE) &&
2904 ((rc = adapter_full_init(sc)) != 0))
2905 return (rc); /* error message displayed already */
2907 if (!(pi->flags & PORT_INIT_DONE) &&
2908 ((rc = port_full_init(pi)) != 0))
2909 return (rc); /* error message displayed already */
2911 rc = update_mac_settings(pi, XGMAC_ALL);
2913 goto done; /* error message displayed already */
2915 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
2917 if_printf(ifp, "start_link failed: %d\n", rc);
2921 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true);
2923 if_printf(ifp, "enable_vi failed: %d\n", rc);
2928 * The first iq of the first port to come up is used for tracing.
2930 if (sc->traceq < 0) {
2931 sc->traceq = sc->sge.rxq[pi->first_rxq].iq.abs_id;
2932 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
2933 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
2934 V_QUEUENUMBER(sc->traceq));
2935 pi->flags |= HAS_TRACEQ;
2939 setbit(&sc->open_device_map, pi->port_id);
2941 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2944 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
2947 cxgbe_uninit_synchronized(pi);
2956 cxgbe_uninit_synchronized(struct port_info *pi)
2958 struct adapter *sc = pi->adapter;
2959 struct ifnet *ifp = pi->ifp;
2962 ASSERT_SYNCHRONIZED_OP(sc);
2965 * Disable the VI so that all its data in either direction is discarded
2966 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
2967 * tick) intact as the TP can deliver negative advice or data that it's
2968 * holding in its RAM (for an offloaded connection) even after the VI is
2971 rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false);
2973 if_printf(ifp, "disable_vi failed: %d\n", rc);
2977 clrbit(&sc->open_device_map, pi->port_id);
2979 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2982 pi->link_cfg.link_ok = 0;
2983 pi->link_cfg.speed = 0;
2985 t4_os_link_changed(sc, pi->port_id, 0, -1);
2991 * It is ok for this function to fail midway and return right away. t4_detach
2992 * will walk the entire sc->irq list and clean up whatever is valid.
2995 setup_intr_handlers(struct adapter *sc)
3000 struct port_info *pi;
3001 struct sge_rxq *rxq;
3003 struct sge_ofld_rxq *ofld_rxq;
3010 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3011 if (sc->intr_count == 1) {
3012 KASSERT(!(sc->flags & INTR_DIRECT),
3013 ("%s: single interrupt && INTR_DIRECT?", __func__));
3015 rc = t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all");
3019 /* Multiple interrupts. */
3020 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3021 ("%s: too few intr.", __func__));
3023 /* The first one is always error intr */
3024 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3030 /* The second one is always the firmware event queue */
3031 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sc->sge.fwq,
3039 * Note that if INTR_DIRECT is not set then either the NIC rx
3040 * queues or (exclusive or) the TOE rx queueus will be taking
3041 * direct interrupts.
3043 * There is no need to check for is_offload(sc) as nofldrxq
3044 * will be 0 if offload is disabled.
3046 for_each_port(sc, p) {
3051 * Skip over the NIC queues if they aren't taking direct
3054 if (!(sc->flags & INTR_DIRECT) &&
3055 pi->nofldrxq > pi->nrxq)
3058 rxq = &sc->sge.rxq[pi->first_rxq];
3059 for (q = 0; q < pi->nrxq; q++, rxq++) {
3060 snprintf(s, sizeof(s), "%d.%d", p, q);
3061 rc = t4_alloc_irq(sc, irq, rid, t4_intr, rxq,
3071 * Skip over the offload queues if they aren't taking
3072 * direct interrupts.
3074 if (!(sc->flags & INTR_DIRECT))
3077 ofld_rxq = &sc->sge.ofld_rxq[pi->first_ofld_rxq];
3078 for (q = 0; q < pi->nofldrxq; q++, ofld_rxq++) {
3079 snprintf(s, sizeof(s), "%d,%d", p, q);
3080 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
3095 adapter_full_init(struct adapter *sc)
3099 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3100 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3101 ("%s: FULL_INIT_DONE already", __func__));
3104 * queues that belong to the adapter (not any particular port).
3106 rc = t4_setup_adapter_queues(sc);
3110 for (i = 0; i < nitems(sc->tq); i++) {
3111 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3112 taskqueue_thread_enqueue, &sc->tq[i]);
3113 if (sc->tq[i] == NULL) {
3114 device_printf(sc->dev,
3115 "failed to allocate task queue %d\n", i);
3119 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3120 device_get_nameunit(sc->dev), i);
3124 sc->flags |= FULL_INIT_DONE;
3127 adapter_full_uninit(sc);
3133 adapter_full_uninit(struct adapter *sc)
3137 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3139 t4_teardown_adapter_queues(sc);
3141 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3142 taskqueue_free(sc->tq[i]);
3146 sc->flags &= ~FULL_INIT_DONE;
3152 port_full_init(struct port_info *pi)
3154 struct adapter *sc = pi->adapter;
3155 struct ifnet *ifp = pi->ifp;
3157 struct sge_rxq *rxq;
3160 ASSERT_SYNCHRONIZED_OP(sc);
3161 KASSERT((pi->flags & PORT_INIT_DONE) == 0,
3162 ("%s: PORT_INIT_DONE already", __func__));
3164 sysctl_ctx_init(&pi->ctx);
3165 pi->flags |= PORT_SYSCTL_CTX;
3168 * Allocate tx/rx/fl queues for this port.
3170 rc = t4_setup_port_queues(pi);
3172 goto done; /* error message displayed already */
3175 * Setup RSS for this port.
3177 rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE,
3179 for_each_rxq(pi, i, rxq) {
3180 rss[i] = rxq->iq.abs_id;
3182 rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0,
3183 pi->rss_size, rss, pi->nrxq);
3186 if_printf(ifp, "rss_config failed: %d\n", rc);
3190 pi->flags |= PORT_INIT_DONE;
3193 port_full_uninit(pi);
3202 port_full_uninit(struct port_info *pi)
3204 struct adapter *sc = pi->adapter;
3206 struct sge_rxq *rxq;
3207 struct sge_txq *txq;
3209 struct sge_ofld_rxq *ofld_rxq;
3210 struct sge_wrq *ofld_txq;
3213 if (pi->flags & PORT_INIT_DONE) {
3215 /* Need to quiesce queues. XXX: ctrl queues? */
3217 for_each_txq(pi, i, txq) {
3218 quiesce_eq(sc, &txq->eq);
3222 for_each_ofld_txq(pi, i, ofld_txq) {
3223 quiesce_eq(sc, &ofld_txq->eq);
3227 for_each_rxq(pi, i, rxq) {
3228 quiesce_iq(sc, &rxq->iq);
3229 quiesce_fl(sc, &rxq->fl);
3233 for_each_ofld_rxq(pi, i, ofld_rxq) {
3234 quiesce_iq(sc, &ofld_rxq->iq);
3235 quiesce_fl(sc, &ofld_rxq->fl);
3240 t4_teardown_port_queues(pi);
3241 pi->flags &= ~PORT_INIT_DONE;
3247 quiesce_eq(struct adapter *sc, struct sge_eq *eq)
3250 eq->flags |= EQ_DOOMED;
3253 * Wait for the response to a credit flush if one's
3256 while (eq->flags & EQ_CRFLUSHED)
3257 mtx_sleep(eq, &eq->eq_lock, 0, "crflush", 0);
3260 callout_drain(&eq->tx_callout); /* XXX: iffy */
3261 pause("callout", 10); /* Still iffy */
3263 taskqueue_drain(sc->tq[eq->tx_chan], &eq->tx_task);
3267 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
3269 (void) sc; /* unused */
3271 /* Synchronize with the interrupt handler */
3272 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
3277 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
3279 mtx_lock(&sc->sfl_lock);
3281 fl->flags |= FL_DOOMED;
3283 mtx_unlock(&sc->sfl_lock);
3285 callout_drain(&sc->sfl_callout);
3286 KASSERT((fl->flags & FL_STARVING) == 0,
3287 ("%s: still starving", __func__));
3291 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
3292 driver_intr_t *handler, void *arg, char *name)
3297 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
3298 RF_SHAREABLE | RF_ACTIVE);
3299 if (irq->res == NULL) {
3300 device_printf(sc->dev,
3301 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
3305 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
3306 NULL, handler, arg, &irq->tag);
3308 device_printf(sc->dev,
3309 "failed to setup interrupt for rid %d, name %s: %d\n",
3312 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
3318 t4_free_irq(struct adapter *sc, struct irq *irq)
3321 bus_teardown_intr(sc->dev, irq->res, irq->tag);
3323 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
3325 bzero(irq, sizeof(*irq));
3331 reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start,
3334 uint32_t *p = (uint32_t *)(buf + start);
3336 for ( ; start <= end; start += sizeof(uint32_t))
3337 *p++ = t4_read_reg(sc, start);
3341 t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
3344 const unsigned int *reg_ranges;
3345 static const unsigned int t4_reg_ranges[] = {
3564 static const unsigned int t5_reg_ranges[] = {
4004 reg_ranges = &t4_reg_ranges[0];
4005 n = nitems(t4_reg_ranges);
4007 reg_ranges = &t5_reg_ranges[0];
4008 n = nitems(t5_reg_ranges);
4011 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4012 for (i = 0; i < n; i += 2)
4013 reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]);
4017 cxgbe_tick(void *arg)
4019 struct port_info *pi = arg;
4020 struct ifnet *ifp = pi->ifp;
4021 struct sge_txq *txq;
4023 struct port_stats *s = &pi->stats;
4026 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4028 return; /* without scheduling another callout */
4031 t4_get_port_stats(pi->adapter, pi->tx_chan, s);
4033 ifp->if_opackets = s->tx_frames - s->tx_pause;
4034 ifp->if_ipackets = s->rx_frames - s->rx_pause;
4035 ifp->if_obytes = s->tx_octets - s->tx_pause * 64;
4036 ifp->if_ibytes = s->rx_octets - s->rx_pause * 64;
4037 ifp->if_omcasts = s->tx_mcast_frames - s->tx_pause;
4038 ifp->if_imcasts = s->rx_mcast_frames - s->rx_pause;
4039 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4040 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4044 for_each_txq(pi, i, txq)
4045 drops += txq->br->br_drops;
4046 ifp->if_snd.ifq_drops = drops;
4048 ifp->if_oerrors = s->tx_error_frames;
4049 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4050 s->rx_fcs_err + s->rx_len_err;
4052 callout_schedule(&pi->tick, hz);
4057 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4061 if (arg != ifp || ifp->if_type != IFT_ETHER)
4064 vlan = VLAN_DEVAT(ifp, vid);
4065 VLAN_SETCOOKIE(vlan, ifp);
4069 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4073 panic("%s: opcode 0x%02x on iq %p with payload %p",
4074 __func__, rss->opcode, iq, m);
4076 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
4077 __func__, rss->opcode, iq, m);
4084 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h)
4086 uintptr_t *loc, new;
4088 if (opcode >= nitems(sc->cpl_handler))
4091 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
4092 loc = (uintptr_t *) &sc->cpl_handler[opcode];
4093 atomic_store_rel_ptr(loc, new);
4099 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
4103 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
4105 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
4106 __func__, iq, ctrl);
4112 t4_register_an_handler(struct adapter *sc, an_handler_t h)
4114 uintptr_t *loc, new;
4116 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
4117 loc = (uintptr_t *) &sc->an_handler;
4118 atomic_store_rel_ptr(loc, new);
4124 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
4126 const struct cpl_fw6_msg *cpl =
4127 __containerof(rpl, struct cpl_fw6_msg, data[0]);
4130 panic("%s: fw_msg type %d", __func__, cpl->type);
4132 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
4138 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h)
4140 uintptr_t *loc, new;
4142 if (type >= nitems(sc->fw_msg_handler))
4146 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
4147 * handler dispatch table. Reject any attempt to install a handler for
4150 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
4153 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
4154 loc = (uintptr_t *) &sc->fw_msg_handler[type];
4155 atomic_store_rel_ptr(loc, new);
4161 t4_sysctls(struct adapter *sc)
4163 struct sysctl_ctx_list *ctx;
4164 struct sysctl_oid *oid;
4165 struct sysctl_oid_list *children, *c0;
4166 static char *caps[] = {
4167 "\20\1PPP\2QFC\3DCBX", /* caps[0] linkcaps */
4168 "\20\1NIC\2VM\3IDS\4UM\5UM_ISGL", /* caps[1] niccaps */
4169 "\20\1TOE", /* caps[2] toecaps */
4170 "\20\1RDDP\2RDMAC", /* caps[3] rdmacaps */
4171 "\20\1INITIATOR_PDU\2TARGET_PDU" /* caps[4] iscsicaps */
4172 "\3INITIATOR_CNXOFLD\4TARGET_CNXOFLD"
4173 "\5INITIATOR_SSNOFLD\6TARGET_SSNOFLD",
4174 "\20\1INITIATOR\2TARGET\3CTRL_OFLD" /* caps[5] fcoecaps */
4176 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4178 ctx = device_get_sysctl_ctx(sc->dev);
4183 oid = device_get_sysctl_tree(sc->dev);
4184 c0 = children = SYSCTL_CHILDREN(oid);
4186 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4187 sc->params.nports, "# of ports");
4189 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4190 NULL, chip_rev(sc), "chip hardware revision");
4192 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4193 CTLFLAG_RD, &sc->fw_version, 0, "firmware version");
4195 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4196 CTLFLAG_RD, &sc->cfg_file, 0, "configuration file");
4198 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4199 sc->cfcsum, "config file checksum");
4201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4202 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4203 sysctl_bitfield, "A", "available doorbells");
4205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkcaps",
4206 CTLTYPE_STRING | CTLFLAG_RD, caps[0], sc->linkcaps,
4207 sysctl_bitfield, "A", "available link capabilities");
4209 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "niccaps",
4210 CTLTYPE_STRING | CTLFLAG_RD, caps[1], sc->niccaps,
4211 sysctl_bitfield, "A", "available NIC capabilities");
4213 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "toecaps",
4214 CTLTYPE_STRING | CTLFLAG_RD, caps[2], sc->toecaps,
4215 sysctl_bitfield, "A", "available TCP offload capabilities");
4217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdmacaps",
4218 CTLTYPE_STRING | CTLFLAG_RD, caps[3], sc->rdmacaps,
4219 sysctl_bitfield, "A", "available RDMA capabilities");
4221 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "iscsicaps",
4222 CTLTYPE_STRING | CTLFLAG_RD, caps[4], sc->iscsicaps,
4223 sysctl_bitfield, "A", "available iSCSI capabilities");
4225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoecaps",
4226 CTLTYPE_STRING | CTLFLAG_RD, caps[5], sc->fcoecaps,
4227 sysctl_bitfield, "A", "available FCoE capabilities");
4229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4230 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4232 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4233 CTLTYPE_STRING | CTLFLAG_RD, sc->sge.timer_val,
4234 sizeof(sc->sge.timer_val), sysctl_int_array, "A",
4235 "interrupt holdoff timer values (us)");
4237 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4238 CTLTYPE_STRING | CTLFLAG_RD, sc->sge.counter_val,
4239 sizeof(sc->sge.counter_val), sysctl_int_array, "A",
4240 "interrupt holdoff packet counter values");
4242 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4243 NULL, sc->tids.nftids, "number of filters");
4245 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4246 CTLFLAG_RD, sc, 0, sysctl_temperature, "A",
4247 "chip temperature (in Celsius)");
4249 t4_sge_sysctls(sc, ctx, children);
4251 sc->lro_timeout = 100;
4252 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4253 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4257 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4259 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4260 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4261 "logs and miscellaneous information");
4262 children = SYSCTL_CHILDREN(oid);
4264 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4265 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4266 sysctl_cctrl, "A", "congestion control");
4268 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4269 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4270 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4272 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4273 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4274 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4276 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4277 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4278 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4280 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4281 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4282 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4285 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4286 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4289 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4290 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4293 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4294 sysctl_cim_la, "A", "CIM logic analyzer");
4296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4297 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4298 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4301 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4302 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4305 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4306 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4309 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4310 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4313 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4314 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4317 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4318 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4321 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4322 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4326 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4327 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4329 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4330 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4331 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4334 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4335 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4336 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4338 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4339 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4340 sysctl_cim_qcfg, "A", "CIM queue configuration");
4342 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4343 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4344 sysctl_cpl_stats, "A", "CPL statistics");
4346 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4347 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4348 sysctl_ddp_stats, "A", "DDP statistics");
4350 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4351 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4352 sysctl_devlog, "A", "firmware's device log");
4354 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4355 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4356 sysctl_fcoe_stats, "A", "FCoE statistics");
4358 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4359 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4360 sysctl_hw_sched, "A", "hardware scheduler ");
4362 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4363 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4364 sysctl_l2t, "A", "hardware L2 table");
4366 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4367 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4368 sysctl_lb_stats, "A", "loopback statistics");
4370 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4371 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4372 sysctl_meminfo, "A", "memory regions");
4374 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4375 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4376 sysctl_mps_tcam, "A", "MPS TCAM entries");
4378 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4379 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4380 sysctl_path_mtus, "A", "path MTUs");
4382 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4383 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4384 sysctl_pm_stats, "A", "PM statistics");
4386 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4387 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4388 sysctl_rdma_stats, "A", "RDMA statistics");
4390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4391 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4392 sysctl_tcp_stats, "A", "TCP statistics");
4394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4395 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4396 sysctl_tids, "A", "TID information");
4398 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4399 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4400 sysctl_tp_err_stats, "A", "TP error statistics");
4402 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4403 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4404 sysctl_tp_la, "A", "TP logic analyzer");
4406 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4407 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4408 sysctl_tx_rate, "A", "Tx rate");
4410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4411 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4412 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4415 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4416 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4417 sysctl_wcwr_stats, "A", "write combined work requests");
4422 if (is_offload(sc)) {
4426 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4427 NULL, "TOE parameters");
4428 children = SYSCTL_CHILDREN(oid);
4430 sc->tt.sndbuf = 256 * 1024;
4431 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4432 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4435 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4436 &sc->tt.ddp, 0, "DDP allowed");
4438 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4439 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4440 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4443 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4444 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4445 &sc->tt.ddp_thres, 0, "DDP threshold");
4447 sc->tt.rx_coalesce = 1;
4448 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4449 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4458 cxgbe_sysctls(struct port_info *pi)
4460 struct sysctl_ctx_list *ctx;
4461 struct sysctl_oid *oid;
4462 struct sysctl_oid_list *children;
4464 ctx = device_get_sysctl_ctx(pi->dev);
4469 oid = device_get_sysctl_tree(pi->dev);
4470 children = SYSCTL_CHILDREN(oid);
4472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4473 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4474 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4476 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4477 "PHY temperature (in Celsius)");
4478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4479 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4480 "PHY firmware version");
4482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4483 &pi->nrxq, 0, "# of rx queues");
4484 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4485 &pi->ntxq, 0, "# of tx queues");
4486 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4487 &pi->first_rxq, 0, "index of first rx queue");
4488 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4489 &pi->first_txq, 0, "index of first tx queue");
4492 if (is_offload(pi->adapter)) {
4493 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4495 "# of rx queues for offloaded TCP connections");
4496 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4498 "# of tx queues for offloaded TCP connections");
4499 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4500 CTLFLAG_RD, &pi->first_ofld_rxq, 0,
4501 "index of first TOE rx queue");
4502 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4503 CTLFLAG_RD, &pi->first_ofld_txq, 0,
4504 "index of first TOE tx queue");
4508 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4509 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I",
4510 "holdoff timer index");
4511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4512 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I",
4513 "holdoff packet counter index");
4515 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4516 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I",
4518 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4519 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I",
4523 * dev.cxgbe.X.stats.
4525 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4526 NULL, "port statistics");
4527 children = SYSCTL_CHILDREN(oid);
4529 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4530 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4531 CTLTYPE_U64 | CTLFLAG_RD, pi->adapter, reg, \
4532 sysctl_handle_t4_reg64, "QU", desc)
4534 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4536 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4538 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4540 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4542 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4543 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4544 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4545 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4546 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4547 "# of tx frames in this range",
4548 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4549 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4550 "# of tx frames in this range",
4551 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4552 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4553 "# of tx frames in this range",
4554 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
4555 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
4556 "# of tx frames in this range",
4557 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
4558 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
4559 "# of tx frames in this range",
4560 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
4561 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
4562 "# of tx frames in this range",
4563 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
4564 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
4565 "# of tx frames in this range",
4566 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
4567 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
4568 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
4569 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
4570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
4571 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
4572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
4573 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
4574 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
4575 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
4576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
4577 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
4578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
4579 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
4580 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
4581 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
4582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
4583 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
4584 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
4585 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
4586 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
4588 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
4589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
4590 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
4591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
4592 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
4593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
4594 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
4595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
4596 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
4597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
4598 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
4599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
4600 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
4601 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
4602 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
4603 "# of frames received with bad FCS",
4604 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
4605 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
4606 "# of frames received with length error",
4607 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
4608 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
4609 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
4610 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
4611 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
4612 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
4613 "# of rx frames in this range",
4614 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
4615 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
4616 "# of rx frames in this range",
4617 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
4618 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
4619 "# of rx frames in this range",
4620 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
4621 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
4622 "# of rx frames in this range",
4623 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
4624 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
4625 "# of rx frames in this range",
4626 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
4627 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
4628 "# of rx frames in this range",
4629 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
4630 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
4631 "# of rx frames in this range",
4632 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
4633 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
4634 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
4635 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
4636 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
4637 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
4638 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
4639 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
4640 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
4641 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
4642 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
4643 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
4644 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
4645 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
4646 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
4647 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
4648 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
4649 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
4650 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
4652 #undef SYSCTL_ADD_T4_REG64
4654 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
4655 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
4656 &pi->stats.name, desc)
4658 /* We get these from port_stats and they may be stale by upto 1s */
4659 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
4660 "# drops due to buffer-group 0 overflows");
4661 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
4662 "# drops due to buffer-group 1 overflows");
4663 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
4664 "# drops due to buffer-group 2 overflows");
4665 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
4666 "# drops due to buffer-group 3 overflows");
4667 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
4668 "# of buffer-group 0 truncated packets");
4669 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
4670 "# of buffer-group 1 truncated packets");
4671 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
4672 "# of buffer-group 2 truncated packets");
4673 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
4674 "# of buffer-group 3 truncated packets");
4676 #undef SYSCTL_ADD_T4_PORTSTAT
4682 sysctl_int_array(SYSCTL_HANDLER_ARGS)
4687 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4688 for (i = arg1; arg2; arg2 -= sizeof(int), i++)
4689 sbuf_printf(&sb, "%d ", *i);
4692 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
4698 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
4703 rc = sysctl_wire_old_buffer(req, 0);
4707 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
4711 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
4712 rc = sbuf_finish(sb);
4719 sysctl_btphy(SYSCTL_HANDLER_ARGS)
4721 struct port_info *pi = arg1;
4723 struct adapter *sc = pi->adapter;
4727 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4btt");
4730 /* XXX: magic numbers */
4731 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
4733 end_synchronized_op(sc, 0);
4739 rc = sysctl_handle_int(oidp, &v, 0, req);
4744 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
4746 struct port_info *pi = arg1;
4747 struct adapter *sc = pi->adapter;
4749 struct sge_rxq *rxq;
4751 struct sge_ofld_rxq *ofld_rxq;
4757 rc = sysctl_handle_int(oidp, &idx, 0, req);
4758 if (rc != 0 || req->newptr == NULL)
4761 if (idx < 0 || idx >= SGE_NTIMERS)
4764 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
4769 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(pi->pktc_idx != -1);
4770 for_each_rxq(pi, i, rxq) {
4771 #ifdef atomic_store_rel_8
4772 atomic_store_rel_8(&rxq->iq.intr_params, v);
4774 rxq->iq.intr_params = v;
4778 for_each_ofld_rxq(pi, i, ofld_rxq) {
4779 #ifdef atomic_store_rel_8
4780 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
4782 ofld_rxq->iq.intr_params = v;
4788 end_synchronized_op(sc, LOCK_HELD);
4793 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
4795 struct port_info *pi = arg1;
4796 struct adapter *sc = pi->adapter;
4801 rc = sysctl_handle_int(oidp, &idx, 0, req);
4802 if (rc != 0 || req->newptr == NULL)
4805 if (idx < -1 || idx >= SGE_NCOUNTERS)
4808 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
4813 if (pi->flags & PORT_INIT_DONE)
4814 rc = EBUSY; /* cannot be changed once the queues are created */
4818 end_synchronized_op(sc, LOCK_HELD);
4823 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
4825 struct port_info *pi = arg1;
4826 struct adapter *sc = pi->adapter;
4829 qsize = pi->qsize_rxq;
4831 rc = sysctl_handle_int(oidp, &qsize, 0, req);
4832 if (rc != 0 || req->newptr == NULL)
4835 if (qsize < 128 || (qsize & 7))
4838 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
4843 if (pi->flags & PORT_INIT_DONE)
4844 rc = EBUSY; /* cannot be changed once the queues are created */
4846 pi->qsize_rxq = qsize;
4848 end_synchronized_op(sc, LOCK_HELD);
4853 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
4855 struct port_info *pi = arg1;
4856 struct adapter *sc = pi->adapter;
4859 qsize = pi->qsize_txq;
4861 rc = sysctl_handle_int(oidp, &qsize, 0, req);
4862 if (rc != 0 || req->newptr == NULL)
4865 /* bufring size must be powerof2 */
4866 if (qsize < 128 || !powerof2(qsize))
4869 rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
4874 if (pi->flags & PORT_INIT_DONE)
4875 rc = EBUSY; /* cannot be changed once the queues are created */
4877 pi->qsize_txq = qsize;
4879 end_synchronized_op(sc, LOCK_HELD);
4884 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
4886 struct adapter *sc = arg1;
4890 val = t4_read_reg64(sc, reg);
4892 return (sysctl_handle_64(oidp, &val, 0, req));
4896 sysctl_temperature(SYSCTL_HANDLER_ARGS)
4898 struct adapter *sc = arg1;
4900 uint32_t param, val;
4902 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
4905 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4906 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4907 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
4908 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4909 end_synchronized_op(sc, 0);
4913 /* unknown is returned as 0 but we display -1 in that case */
4914 t = val == 0 ? -1 : val;
4916 rc = sysctl_handle_int(oidp, &t, 0, req);
4922 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
4924 struct adapter *sc = arg1;
4927 uint16_t incr[NMTUS][NCCTRL_WIN];
4928 static const char *dec_fac[] = {
4929 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
4933 rc = sysctl_wire_old_buffer(req, 0);
4937 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
4941 t4_read_cong_tbl(sc, incr);
4943 for (i = 0; i < NCCTRL_WIN; ++i) {
4944 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
4945 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
4946 incr[5][i], incr[6][i], incr[7][i]);
4947 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
4948 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
4949 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
4950 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
4953 rc = sbuf_finish(sb);
4959 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
4960 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
4961 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
4962 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
4966 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
4968 struct adapter *sc = arg1;
4970 int rc, i, n, qid = arg2;
4973 u_int cim_num_obq = is_t4(sc) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
4975 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
4976 ("%s: bad qid %d\n", __func__, qid));
4978 if (qid < CIM_NUM_IBQ) {
4981 n = 4 * CIM_IBQ_SIZE;
4982 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
4983 rc = t4_read_cim_ibq(sc, qid, buf, n);
4985 /* outbound queue */
4988 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
4989 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
4990 rc = t4_read_cim_obq(sc, qid, buf, n);
4997 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
4999 rc = sysctl_wire_old_buffer(req, 0);
5003 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5009 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5010 for (i = 0, p = buf; i < n; i += 16, p += 4)
5011 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5014 rc = sbuf_finish(sb);
5022 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5024 struct adapter *sc = arg1;
5030 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5034 rc = sysctl_wire_old_buffer(req, 0);
5038 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5042 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5045 rc = -t4_cim_read_la(sc, buf, NULL);
5049 sbuf_printf(sb, "Status Data PC%s",
5050 cfg & F_UPDBGLACAPTPCONLY ? "" :
5051 " LS0Stat LS0Addr LS0Data");
5053 KASSERT((sc->params.cim_la_size & 7) == 0,
5054 ("%s: p will walk off the end of buf", __func__));
5056 for (p = buf; p < &buf[sc->params.cim_la_size]; p += 8) {
5057 if (cfg & F_UPDBGLACAPTPCONLY) {
5058 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5060 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5061 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5062 p[4] & 0xff, p[5] >> 8);
5063 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5064 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5065 p[1] & 0xf, p[2] >> 4);
5068 "\n %02x %x%07x %x%07x %08x %08x "
5070 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5071 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5076 rc = sbuf_finish(sb);
5084 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5086 struct adapter *sc = arg1;
5092 rc = sysctl_wire_old_buffer(req, 0);
5096 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5100 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5103 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5106 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5107 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5111 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5112 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5113 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5114 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5115 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5116 (p[1] >> 2) | ((p[2] & 3) << 30),
5117 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5121 rc = sbuf_finish(sb);
5128 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5130 struct adapter *sc = arg1;
5136 rc = sysctl_wire_old_buffer(req, 0);
5140 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5144 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5147 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5150 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5151 for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) {
5152 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5153 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5154 p[4], p[3], p[2], p[1], p[0]);
5157 sbuf_printf(sb, "\n\nCntl ID Data");
5158 for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) {
5159 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5160 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5163 rc = sbuf_finish(sb);
5170 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5172 struct adapter *sc = arg1;
5175 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5176 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5177 uint16_t thres[CIM_NUM_IBQ];
5178 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5179 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5180 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5183 cim_num_obq = CIM_NUM_OBQ;
5184 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5185 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5187 cim_num_obq = CIM_NUM_OBQ_T5;
5188 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5189 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5191 nq = CIM_NUM_IBQ + cim_num_obq;
5193 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5195 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5199 t4_read_cimq_cfg(sc, base, size, thres);
5201 rc = sysctl_wire_old_buffer(req, 0);
5205 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5209 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5211 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5212 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5213 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5214 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5215 G_QUEREMFLITS(p[2]) * 16);
5216 for ( ; i < nq; i++, p += 4, wr += 2)
5217 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5218 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5219 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5220 G_QUEREMFLITS(p[2]) * 16);
5222 rc = sbuf_finish(sb);
5229 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5231 struct adapter *sc = arg1;
5234 struct tp_cpl_stats stats;
5236 rc = sysctl_wire_old_buffer(req, 0);
5240 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5244 t4_tp_get_cpl_stats(sc, &stats);
5246 sbuf_printf(sb, " channel 0 channel 1 channel 2 "
5248 sbuf_printf(sb, "CPL requests: %10u %10u %10u %10u\n",
5249 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5250 sbuf_printf(sb, "CPL responses: %10u %10u %10u %10u",
5251 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5253 rc = sbuf_finish(sb);
5260 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5262 struct adapter *sc = arg1;
5265 struct tp_usm_stats stats;
5267 rc = sysctl_wire_old_buffer(req, 0);
5271 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5275 t4_get_usm_stats(sc, &stats);
5277 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5278 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5279 sbuf_printf(sb, "Drops: %u", stats.drops);
5281 rc = sbuf_finish(sb);
5287 const char *devlog_level_strings[] = {
5288 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5289 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5290 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5291 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5292 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5293 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5296 const char *devlog_facility_strings[] = {
5297 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5298 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5299 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5300 [FW_DEVLOG_FACILITY_RES] = "RES",
5301 [FW_DEVLOG_FACILITY_HW] = "HW",
5302 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5303 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5304 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5305 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5306 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5307 [FW_DEVLOG_FACILITY_VI] = "VI",
5308 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5309 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5310 [FW_DEVLOG_FACILITY_TM] = "TM",
5311 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5312 [FW_DEVLOG_FACILITY_DCB] = "DCB",
5313 [FW_DEVLOG_FACILITY_ETH] = "ETH",
5314 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
5315 [FW_DEVLOG_FACILITY_RI] = "RI",
5316 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
5317 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
5318 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
5319 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE"
5323 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5325 struct adapter *sc = arg1;
5326 struct devlog_params *dparams = &sc->params.devlog;
5327 struct fw_devlog_e *buf, *e;
5328 int i, j, rc, nentries, first = 0, m;
5330 uint64_t ftstamp = UINT64_MAX;
5332 if (dparams->start == 0) {
5333 dparams->memtype = FW_MEMTYPE_EDC0;
5334 dparams->start = 0x84000;
5335 dparams->size = 32768;
5338 nentries = dparams->size / sizeof(struct fw_devlog_e);
5340 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5344 m = fwmtype_to_hwmtype(dparams->memtype);
5345 rc = -t4_mem_read(sc, m, dparams->start, dparams->size, (void *)buf);
5349 for (i = 0; i < nentries; i++) {
5352 if (e->timestamp == 0)
5355 e->timestamp = be64toh(e->timestamp);
5356 e->seqno = be32toh(e->seqno);
5357 for (j = 0; j < 8; j++)
5358 e->params[j] = be32toh(e->params[j]);
5360 if (e->timestamp < ftstamp) {
5361 ftstamp = e->timestamp;
5366 if (buf[first].timestamp == 0)
5367 goto done; /* nothing in the log */
5369 rc = sysctl_wire_old_buffer(req, 0);
5373 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5378 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
5379 "Seq#", "Tstamp", "Level", "Facility", "Message");
5384 if (e->timestamp == 0)
5387 sbuf_printf(sb, "%10d %15ju %8s %8s ",
5388 e->seqno, e->timestamp,
5389 (e->level < nitems(devlog_level_strings) ?
5390 devlog_level_strings[e->level] : "UNKNOWN"),
5391 (e->facility < nitems(devlog_facility_strings) ?
5392 devlog_facility_strings[e->facility] : "UNKNOWN"));
5393 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5394 e->params[2], e->params[3], e->params[4],
5395 e->params[5], e->params[6], e->params[7]);
5397 if (++i == nentries)
5399 } while (i != first);
5401 rc = sbuf_finish(sb);
5409 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
5411 struct adapter *sc = arg1;
5414 struct tp_fcoe_stats stats[4];
5416 rc = sysctl_wire_old_buffer(req, 0);
5420 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5424 t4_get_fcoe_stats(sc, 0, &stats[0]);
5425 t4_get_fcoe_stats(sc, 1, &stats[1]);
5426 t4_get_fcoe_stats(sc, 2, &stats[2]);
5427 t4_get_fcoe_stats(sc, 3, &stats[3]);
5429 sbuf_printf(sb, " channel 0 channel 1 "
5430 "channel 2 channel 3\n");
5431 sbuf_printf(sb, "octetsDDP: %16ju %16ju %16ju %16ju\n",
5432 stats[0].octetsDDP, stats[1].octetsDDP, stats[2].octetsDDP,
5433 stats[3].octetsDDP);
5434 sbuf_printf(sb, "framesDDP: %16u %16u %16u %16u\n", stats[0].framesDDP,
5435 stats[1].framesDDP, stats[2].framesDDP, stats[3].framesDDP);
5436 sbuf_printf(sb, "framesDrop: %16u %16u %16u %16u",
5437 stats[0].framesDrop, stats[1].framesDrop, stats[2].framesDrop,
5438 stats[3].framesDrop);
5440 rc = sbuf_finish(sb);
5447 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
5449 struct adapter *sc = arg1;
5452 unsigned int map, kbps, ipg, mode;
5453 unsigned int pace_tab[NTX_SCHED];
5455 rc = sysctl_wire_old_buffer(req, 0);
5459 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5463 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
5464 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
5465 t4_read_pace_tbl(sc, pace_tab);
5467 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
5468 "Class IPG (0.1 ns) Flow IPG (us)");
5470 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
5471 t4_get_tx_sched(sc, i, &kbps, &ipg);
5472 sbuf_printf(sb, "\n %u %-5s %u ", i,
5473 (mode & (1 << i)) ? "flow" : "class", map & 3);
5475 sbuf_printf(sb, "%9u ", kbps);
5477 sbuf_printf(sb, " disabled ");
5480 sbuf_printf(sb, "%13u ", ipg);
5482 sbuf_printf(sb, " disabled ");
5485 sbuf_printf(sb, "%10u", pace_tab[i]);
5487 sbuf_printf(sb, " disabled");
5490 rc = sbuf_finish(sb);
5497 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
5499 struct adapter *sc = arg1;
5503 struct lb_port_stats s[2];
5504 static const char *stat_name[] = {
5505 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
5506 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
5507 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
5508 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
5509 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
5510 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
5511 "BG2FramesTrunc:", "BG3FramesTrunc:"
5514 rc = sysctl_wire_old_buffer(req, 0);
5518 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5522 memset(s, 0, sizeof(s));
5524 for (i = 0; i < 4; i += 2) {
5525 t4_get_lb_stats(sc, i, &s[0]);
5526 t4_get_lb_stats(sc, i + 1, &s[1]);
5530 sbuf_printf(sb, "%s Loopback %u"
5531 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
5533 for (j = 0; j < nitems(stat_name); j++)
5534 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
5538 rc = sbuf_finish(sb);
5545 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
5548 struct port_info *pi = arg1;
5550 static const char *linkdnreasons[] = {
5551 "non-specific", "remote fault", "autoneg failed", "reserved3",
5552 "PHY overheated", "unknown", "rx los", "reserved7"
5555 rc = sysctl_wire_old_buffer(req, 0);
5558 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
5562 if (pi->linkdnrc < 0)
5563 sbuf_printf(sb, "n/a");
5564 else if (pi->linkdnrc < nitems(linkdnreasons))
5565 sbuf_printf(sb, "%s", linkdnreasons[pi->linkdnrc]);
5567 sbuf_printf(sb, "%d", pi->linkdnrc);
5569 rc = sbuf_finish(sb);
5582 mem_desc_cmp(const void *a, const void *b)
5584 return ((const struct mem_desc *)a)->base -
5585 ((const struct mem_desc *)b)->base;
5589 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
5594 size = to - from + 1;
5598 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
5599 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
5603 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
5605 struct adapter *sc = arg1;
5608 uint32_t lo, hi, used, alloc;
5609 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
5610 static const char *region[] = {
5611 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
5612 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
5613 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
5614 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
5615 "RQUDP region:", "PBL region:", "TXPBL region:",
5616 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
5619 struct mem_desc avail[4];
5620 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
5621 struct mem_desc *md = mem;
5623 rc = sysctl_wire_old_buffer(req, 0);
5627 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5631 for (i = 0; i < nitems(mem); i++) {
5636 /* Find and sort the populated memory ranges */
5638 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
5639 if (lo & F_EDRAM0_ENABLE) {
5640 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
5641 avail[i].base = G_EDRAM0_BASE(hi) << 20;
5642 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
5646 if (lo & F_EDRAM1_ENABLE) {
5647 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
5648 avail[i].base = G_EDRAM1_BASE(hi) << 20;
5649 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
5653 if (lo & F_EXT_MEM_ENABLE) {
5654 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
5655 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
5656 avail[i].limit = avail[i].base +
5657 (G_EXT_MEM_SIZE(hi) << 20);
5658 avail[i].idx = is_t4(sc) ? 2 : 3; /* Call it MC for T4 */
5661 if (!is_t4(sc) && lo & F_EXT_MEM1_ENABLE) {
5662 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
5663 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
5664 avail[i].limit = avail[i].base +
5665 (G_EXT_MEM1_SIZE(hi) << 20);
5669 if (!i) /* no memory available */
5671 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
5673 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
5674 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
5675 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
5676 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
5677 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
5678 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
5679 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
5680 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
5681 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
5683 /* the next few have explicit upper bounds */
5684 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
5685 md->limit = md->base - 1 +
5686 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
5687 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
5690 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
5691 md->limit = md->base - 1 +
5692 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
5693 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
5696 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
5697 hi = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
5698 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
5699 md->limit = (sc->tids.ntids - hi) * 16 + md->base - 1;
5702 md->idx = nitems(region); /* hide it */
5706 #define ulp_region(reg) \
5707 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
5708 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
5710 ulp_region(RX_ISCSI);
5711 ulp_region(RX_TDDP);
5713 ulp_region(RX_STAG);
5715 ulp_region(RX_RQUDP);
5721 md->idx = nitems(region);
5722 if (!is_t4(sc) && t4_read_reg(sc, A_SGE_CONTROL2) & F_VFIFO_ENABLE) {
5723 md->base = G_BASEADDR(t4_read_reg(sc, A_SGE_DBVFIFO_BADDR));
5724 md->limit = md->base + (G_DBVFIFO_SIZE((t4_read_reg(sc,
5725 A_SGE_DBVFIFO_SIZE))) << 2) - 1;
5729 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
5730 md->limit = md->base + sc->tids.ntids - 1;
5732 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
5733 md->limit = md->base + sc->tids.ntids - 1;
5736 md->base = sc->vres.ocq.start;
5737 if (sc->vres.ocq.size)
5738 md->limit = md->base + sc->vres.ocq.size - 1;
5740 md->idx = nitems(region); /* hide it */
5743 /* add any address-space holes, there can be up to 3 */
5744 for (n = 0; n < i - 1; n++)
5745 if (avail[n].limit < avail[n + 1].base)
5746 (md++)->base = avail[n].limit;
5748 (md++)->base = avail[n].limit;
5751 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
5753 for (lo = 0; lo < i; lo++)
5754 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
5755 avail[lo].limit - 1);
5757 sbuf_printf(sb, "\n");
5758 for (i = 0; i < n; i++) {
5759 if (mem[i].idx >= nitems(region))
5760 continue; /* skip holes */
5762 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
5763 mem_region_show(sb, region[mem[i].idx], mem[i].base,
5767 sbuf_printf(sb, "\n");
5768 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
5769 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
5770 mem_region_show(sb, "uP RAM:", lo, hi);
5772 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
5773 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
5774 mem_region_show(sb, "uP Extmem2:", lo, hi);
5776 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
5777 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
5779 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
5780 (lo & F_PMRXNUMCHN) ? 2 : 1);
5782 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
5783 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
5784 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
5786 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
5787 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
5788 sbuf_printf(sb, "%u p-structs\n",
5789 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
5791 for (i = 0; i < 4; i++) {
5792 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
5795 alloc = G_ALLOC(lo);
5797 used = G_T5_USED(lo);
5798 alloc = G_T5_ALLOC(lo);
5800 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
5803 for (i = 0; i < 4; i++) {
5804 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
5807 alloc = G_ALLOC(lo);
5809 used = G_T5_USED(lo);
5810 alloc = G_T5_ALLOC(lo);
5813 "\nLoopback %d using %u pages out of %u allocated",
5817 rc = sbuf_finish(sb);
5824 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
5828 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
5832 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
5834 struct adapter *sc = arg1;
5838 rc = sysctl_wire_old_buffer(req, 0);
5842 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5847 "Idx Ethernet address Mask Vld Ports PF"
5848 " VF Replication P0 P1 P2 P3 ML");
5849 n = is_t4(sc) ? NUM_MPS_CLS_SRAM_L_INSTANCES :
5850 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
5851 for (i = 0; i < n; i++) {
5852 uint64_t tcamx, tcamy, mask;
5853 uint32_t cls_lo, cls_hi;
5854 uint8_t addr[ETHER_ADDR_LEN];
5856 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
5857 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
5858 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
5859 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
5864 tcamxy2valmask(tcamx, tcamy, addr, &mask);
5865 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
5866 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
5867 addr[3], addr[4], addr[5], (uintmax_t)mask,
5868 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
5869 G_PORTMAP(cls_hi), G_PF(cls_lo),
5870 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
5872 if (cls_lo & F_REPLICATE) {
5873 struct fw_ldst_cmd ldst_cmd;
5875 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
5876 ldst_cmd.op_to_addrspace =
5877 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
5878 F_FW_CMD_REQUEST | F_FW_CMD_READ |
5879 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
5880 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
5881 ldst_cmd.u.mps.fid_ctl =
5882 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
5883 V_FW_LDST_CMD_CTL(i));
5885 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
5889 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
5890 sizeof(ldst_cmd), &ldst_cmd);
5891 end_synchronized_op(sc, 0);
5895 " ------------ error %3u ------------", rc);
5898 sbuf_printf(sb, " %08x %08x %08x %08x",
5899 be32toh(ldst_cmd.u.mps.rplc127_96),
5900 be32toh(ldst_cmd.u.mps.rplc95_64),
5901 be32toh(ldst_cmd.u.mps.rplc63_32),
5902 be32toh(ldst_cmd.u.mps.rplc31_0));
5905 sbuf_printf(sb, "%36s", "");
5907 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
5908 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
5909 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
5913 (void) sbuf_finish(sb);
5915 rc = sbuf_finish(sb);
5922 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
5924 struct adapter *sc = arg1;
5927 uint16_t mtus[NMTUS];
5929 rc = sysctl_wire_old_buffer(req, 0);
5933 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5937 t4_read_mtu_tbl(sc, mtus, NULL);
5939 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
5940 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
5941 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
5942 mtus[14], mtus[15]);
5944 rc = sbuf_finish(sb);
5951 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
5953 struct adapter *sc = arg1;
5956 uint32_t tx_cnt[PM_NSTATS], rx_cnt[PM_NSTATS];
5957 uint64_t tx_cyc[PM_NSTATS], rx_cyc[PM_NSTATS];
5958 static const char *pm_stats[] = {
5959 "Read:", "Write bypass:", "Write mem:", "Flush:", "FIFO wait:"
5962 rc = sysctl_wire_old_buffer(req, 0);
5966 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5970 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
5971 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
5973 sbuf_printf(sb, " Tx count Tx cycles "
5974 "Rx count Rx cycles");
5975 for (i = 0; i < PM_NSTATS; i++)
5976 sbuf_printf(sb, "\n%-13s %10u %20ju %10u %20ju",
5977 pm_stats[i], tx_cnt[i], tx_cyc[i], rx_cnt[i], rx_cyc[i]);
5979 rc = sbuf_finish(sb);
5986 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
5988 struct adapter *sc = arg1;
5991 struct tp_rdma_stats stats;
5993 rc = sysctl_wire_old_buffer(req, 0);
5997 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6001 t4_tp_get_rdma_stats(sc, &stats);
6002 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6003 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6005 rc = sbuf_finish(sb);
6012 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6014 struct adapter *sc = arg1;
6017 struct tp_tcp_stats v4, v6;
6019 rc = sysctl_wire_old_buffer(req, 0);
6023 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6027 t4_tp_get_tcp_stats(sc, &v4, &v6);
6030 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6031 v4.tcpOutRsts, v6.tcpOutRsts);
6032 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6033 v4.tcpInSegs, v6.tcpInSegs);
6034 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6035 v4.tcpOutSegs, v6.tcpOutSegs);
6036 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6037 v4.tcpRetransSegs, v6.tcpRetransSegs);
6039 rc = sbuf_finish(sb);
6046 sysctl_tids(SYSCTL_HANDLER_ARGS)
6048 struct adapter *sc = arg1;
6051 struct tid_info *t = &sc->tids;
6053 rc = sysctl_wire_old_buffer(req, 0);
6057 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6062 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6067 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6068 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6071 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6072 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6075 sbuf_printf(sb, "TID range: %u-%u",
6076 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6080 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6081 sbuf_printf(sb, ", in use: %u\n",
6082 atomic_load_acq_int(&t->tids_in_use));
6086 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6087 t->stid_base + t->nstids - 1, t->stids_in_use);
6091 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6092 t->ftid_base + t->nftids - 1);
6095 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6096 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6097 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6099 rc = sbuf_finish(sb);
6106 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6108 struct adapter *sc = arg1;
6111 struct tp_err_stats stats;
6113 rc = sysctl_wire_old_buffer(req, 0);
6117 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6121 t4_tp_get_err_stats(sc, &stats);
6123 sbuf_printf(sb, " channel 0 channel 1 channel 2 "
6125 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
6126 stats.macInErrs[0], stats.macInErrs[1], stats.macInErrs[2],
6127 stats.macInErrs[3]);
6128 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
6129 stats.hdrInErrs[0], stats.hdrInErrs[1], stats.hdrInErrs[2],
6130 stats.hdrInErrs[3]);
6131 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
6132 stats.tcpInErrs[0], stats.tcpInErrs[1], stats.tcpInErrs[2],
6133 stats.tcpInErrs[3]);
6134 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
6135 stats.tcp6InErrs[0], stats.tcp6InErrs[1], stats.tcp6InErrs[2],
6136 stats.tcp6InErrs[3]);
6137 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
6138 stats.tnlCongDrops[0], stats.tnlCongDrops[1], stats.tnlCongDrops[2],
6139 stats.tnlCongDrops[3]);
6140 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
6141 stats.tnlTxDrops[0], stats.tnlTxDrops[1], stats.tnlTxDrops[2],
6142 stats.tnlTxDrops[3]);
6143 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
6144 stats.ofldVlanDrops[0], stats.ofldVlanDrops[1],
6145 stats.ofldVlanDrops[2], stats.ofldVlanDrops[3]);
6146 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
6147 stats.ofldChanDrops[0], stats.ofldChanDrops[1],
6148 stats.ofldChanDrops[2], stats.ofldChanDrops[3]);
6149 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
6150 stats.ofldNoNeigh, stats.ofldCongDefer);
6152 rc = sbuf_finish(sb);
6165 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
6171 uint64_t mask = (1ULL << f->width) - 1;
6172 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
6173 ((uintmax_t)v >> f->start) & mask);
6175 if (line_size + len >= 79) {
6177 sbuf_printf(sb, "\n ");
6179 sbuf_printf(sb, "%s ", buf);
6180 line_size += len + 1;
6183 sbuf_printf(sb, "\n");
6186 static struct field_desc tp_la0[] = {
6187 { "RcfOpCodeOut", 60, 4 },
6189 { "WcfState", 52, 4 },
6190 { "RcfOpcSrcOut", 50, 2 },
6191 { "CRxError", 49, 1 },
6192 { "ERxError", 48, 1 },
6193 { "SanityFailed", 47, 1 },
6194 { "SpuriousMsg", 46, 1 },
6195 { "FlushInputMsg", 45, 1 },
6196 { "FlushInputCpl", 44, 1 },
6197 { "RssUpBit", 43, 1 },
6198 { "RssFilterHit", 42, 1 },
6200 { "InitTcb", 31, 1 },
6201 { "LineNumber", 24, 7 },
6203 { "EdataOut", 22, 1 },
6205 { "CdataOut", 20, 1 },
6206 { "EreadPdu", 19, 1 },
6207 { "CreadPdu", 18, 1 },
6208 { "TunnelPkt", 17, 1 },
6209 { "RcfPeerFin", 16, 1 },
6210 { "RcfReasonOut", 12, 4 },
6211 { "TxCchannel", 10, 2 },
6212 { "RcfTxChannel", 8, 2 },
6213 { "RxEchannel", 6, 2 },
6214 { "RcfRxChannel", 5, 1 },
6215 { "RcfDataOutSrdy", 4, 1 },
6217 { "RxOoDvld", 2, 1 },
6218 { "RxCongestion", 1, 1 },
6219 { "TxCongestion", 0, 1 },
6223 static struct field_desc tp_la1[] = {
6224 { "CplCmdIn", 56, 8 },
6225 { "CplCmdOut", 48, 8 },
6226 { "ESynOut", 47, 1 },
6227 { "EAckOut", 46, 1 },
6228 { "EFinOut", 45, 1 },
6229 { "ERstOut", 44, 1 },
6234 { "DataIn", 39, 1 },
6235 { "DataInVld", 38, 1 },
6237 { "RxBufEmpty", 36, 1 },
6239 { "RxFbCongestion", 34, 1 },
6240 { "TxFbCongestion", 33, 1 },
6241 { "TxPktSumSrdy", 32, 1 },
6242 { "RcfUlpType", 28, 4 },
6244 { "Ebypass", 26, 1 },
6246 { "Static0", 24, 1 },
6248 { "Cbypass", 22, 1 },
6250 { "CPktOut", 20, 1 },
6251 { "RxPagePoolFull", 18, 2 },
6252 { "RxLpbkPkt", 17, 1 },
6253 { "TxLpbkPkt", 16, 1 },
6254 { "RxVfValid", 15, 1 },
6255 { "SynLearned", 14, 1 },
6256 { "SetDelEntry", 13, 1 },
6257 { "SetInvEntry", 12, 1 },
6258 { "CpcmdDvld", 11, 1 },
6259 { "CpcmdSave", 10, 1 },
6260 { "RxPstructsFull", 8, 2 },
6261 { "EpcmdDvld", 7, 1 },
6262 { "EpcmdFlush", 6, 1 },
6263 { "EpcmdTrimPrefix", 5, 1 },
6264 { "EpcmdTrimPostfix", 4, 1 },
6265 { "ERssIp4Pkt", 3, 1 },
6266 { "ERssIp6Pkt", 2, 1 },
6267 { "ERssTcpUdpPkt", 1, 1 },
6268 { "ERssFceFipPkt", 0, 1 },
6272 static struct field_desc tp_la2[] = {
6273 { "CplCmdIn", 56, 8 },
6274 { "MpsVfVld", 55, 1 },
6281 { "DataIn", 39, 1 },
6282 { "DataInVld", 38, 1 },
6284 { "RxBufEmpty", 36, 1 },
6286 { "RxFbCongestion", 34, 1 },
6287 { "TxFbCongestion", 33, 1 },
6288 { "TxPktSumSrdy", 32, 1 },
6289 { "RcfUlpType", 28, 4 },
6291 { "Ebypass", 26, 1 },
6293 { "Static0", 24, 1 },
6295 { "Cbypass", 22, 1 },
6297 { "CPktOut", 20, 1 },
6298 { "RxPagePoolFull", 18, 2 },
6299 { "RxLpbkPkt", 17, 1 },
6300 { "TxLpbkPkt", 16, 1 },
6301 { "RxVfValid", 15, 1 },
6302 { "SynLearned", 14, 1 },
6303 { "SetDelEntry", 13, 1 },
6304 { "SetInvEntry", 12, 1 },
6305 { "CpcmdDvld", 11, 1 },
6306 { "CpcmdSave", 10, 1 },
6307 { "RxPstructsFull", 8, 2 },
6308 { "EpcmdDvld", 7, 1 },
6309 { "EpcmdFlush", 6, 1 },
6310 { "EpcmdTrimPrefix", 5, 1 },
6311 { "EpcmdTrimPostfix", 4, 1 },
6312 { "ERssIp4Pkt", 3, 1 },
6313 { "ERssIp6Pkt", 2, 1 },
6314 { "ERssTcpUdpPkt", 1, 1 },
6315 { "ERssFceFipPkt", 0, 1 },
6320 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
6323 field_desc_show(sb, *p, tp_la0);
6327 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
6331 sbuf_printf(sb, "\n");
6332 field_desc_show(sb, p[0], tp_la0);
6333 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
6334 field_desc_show(sb, p[1], tp_la0);
6338 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
6342 sbuf_printf(sb, "\n");
6343 field_desc_show(sb, p[0], tp_la0);
6344 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
6345 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
6349 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
6351 struct adapter *sc = arg1;
6356 void (*show_func)(struct sbuf *, uint64_t *, int);
6358 rc = sysctl_wire_old_buffer(req, 0);
6362 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6366 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
6368 t4_tp_read_la(sc, buf, NULL);
6371 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
6374 show_func = tp_la_show2;
6378 show_func = tp_la_show3;
6382 show_func = tp_la_show;
6385 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
6386 (*show_func)(sb, p, i);
6388 rc = sbuf_finish(sb);
6395 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
6397 struct adapter *sc = arg1;
6400 u64 nrate[NCHAN], orate[NCHAN];
6402 rc = sysctl_wire_old_buffer(req, 0);
6406 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6410 t4_get_chan_txrate(sc, nrate, orate);
6411 sbuf_printf(sb, " channel 0 channel 1 channel 2 "
6413 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
6414 nrate[0], nrate[1], nrate[2], nrate[3]);
6415 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
6416 orate[0], orate[1], orate[2], orate[3]);
6418 rc = sbuf_finish(sb);
6425 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
6427 struct adapter *sc = arg1;
6432 rc = sysctl_wire_old_buffer(req, 0);
6436 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6440 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
6443 t4_ulprx_read_la(sc, buf);
6446 sbuf_printf(sb, " Pcmd Type Message"
6448 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
6449 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
6450 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
6453 rc = sbuf_finish(sb);
6460 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
6462 struct adapter *sc = arg1;
6466 rc = sysctl_wire_old_buffer(req, 0);
6470 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6474 v = t4_read_reg(sc, A_SGE_STAT_CFG);
6475 if (G_STATSOURCE_T5(v) == 7) {
6476 if (G_STATMODE(v) == 0) {
6477 sbuf_printf(sb, "total %d, incomplete %d",
6478 t4_read_reg(sc, A_SGE_STAT_TOTAL),
6479 t4_read_reg(sc, A_SGE_STAT_MATCH));
6480 } else if (G_STATMODE(v) == 1) {
6481 sbuf_printf(sb, "total %d, data overflow %d",
6482 t4_read_reg(sc, A_SGE_STAT_TOTAL),
6483 t4_read_reg(sc, A_SGE_STAT_MATCH));
6486 rc = sbuf_finish(sb);
6494 txq_start(struct ifnet *ifp, struct sge_txq *txq)
6496 struct buf_ring *br;
6499 TXQ_LOCK_ASSERT_OWNED(txq);
6502 m = txq->m ? txq->m : drbr_dequeue(ifp, br);
6504 t4_eth_tx(ifp, txq, m);
6508 t4_tx_callout(void *arg)
6510 struct sge_eq *eq = arg;
6513 if (EQ_TRYLOCK(eq) == 0)
6516 if (eq->flags & EQ_STALLED && !can_resume_tx(eq)) {
6519 if (__predict_true(!(eq->flags && EQ_DOOMED)))
6520 callout_schedule(&eq->tx_callout, 1);
6524 EQ_LOCK_ASSERT_OWNED(eq);
6526 if (__predict_true((eq->flags & EQ_DOOMED) == 0)) {
6528 if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
6529 struct sge_txq *txq = arg;
6530 struct port_info *pi = txq->ifp->if_softc;
6534 struct sge_wrq *wrq = arg;
6539 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
6546 t4_tx_task(void *arg, int count)
6548 struct sge_eq *eq = arg;
6551 if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
6552 struct sge_txq *txq = arg;
6553 txq_start(txq->ifp, txq);
6555 struct sge_wrq *wrq = arg;
6556 t4_wrq_tx_locked(wrq->adapter, wrq, NULL);
6562 fconf_to_mode(uint32_t fconf)
6566 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
6567 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
6569 if (fconf & F_FRAGMENTATION)
6570 mode |= T4_FILTER_IP_FRAGMENT;
6572 if (fconf & F_MPSHITTYPE)
6573 mode |= T4_FILTER_MPS_HIT_TYPE;
6575 if (fconf & F_MACMATCH)
6576 mode |= T4_FILTER_MAC_IDX;
6578 if (fconf & F_ETHERTYPE)
6579 mode |= T4_FILTER_ETH_TYPE;
6581 if (fconf & F_PROTOCOL)
6582 mode |= T4_FILTER_IP_PROTO;
6585 mode |= T4_FILTER_IP_TOS;
6588 mode |= T4_FILTER_VLAN;
6590 if (fconf & F_VNIC_ID)
6591 mode |= T4_FILTER_VNIC;
6594 mode |= T4_FILTER_PORT;
6597 mode |= T4_FILTER_FCoE;
6603 mode_to_fconf(uint32_t mode)
6607 if (mode & T4_FILTER_IP_FRAGMENT)
6608 fconf |= F_FRAGMENTATION;
6610 if (mode & T4_FILTER_MPS_HIT_TYPE)
6611 fconf |= F_MPSHITTYPE;
6613 if (mode & T4_FILTER_MAC_IDX)
6614 fconf |= F_MACMATCH;
6616 if (mode & T4_FILTER_ETH_TYPE)
6617 fconf |= F_ETHERTYPE;
6619 if (mode & T4_FILTER_IP_PROTO)
6620 fconf |= F_PROTOCOL;
6622 if (mode & T4_FILTER_IP_TOS)
6625 if (mode & T4_FILTER_VLAN)
6628 if (mode & T4_FILTER_VNIC)
6631 if (mode & T4_FILTER_PORT)
6634 if (mode & T4_FILTER_FCoE)
6641 fspec_to_fconf(struct t4_filter_specification *fs)
6645 if (fs->val.frag || fs->mask.frag)
6646 fconf |= F_FRAGMENTATION;
6648 if (fs->val.matchtype || fs->mask.matchtype)
6649 fconf |= F_MPSHITTYPE;
6651 if (fs->val.macidx || fs->mask.macidx)
6652 fconf |= F_MACMATCH;
6654 if (fs->val.ethtype || fs->mask.ethtype)
6655 fconf |= F_ETHERTYPE;
6657 if (fs->val.proto || fs->mask.proto)
6658 fconf |= F_PROTOCOL;
6660 if (fs->val.tos || fs->mask.tos)
6663 if (fs->val.vlan_vld || fs->mask.vlan_vld)
6666 if (fs->val.vnic_vld || fs->mask.vnic_vld)
6669 if (fs->val.iport || fs->mask.iport)
6672 if (fs->val.fcoe || fs->mask.fcoe)
6679 get_filter_mode(struct adapter *sc, uint32_t *mode)
6684 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
6689 t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1,
6692 if (sc->params.tp.vlan_pri_map != fconf) {
6693 log(LOG_WARNING, "%s: cached filter mode out of sync %x %x.\n",
6694 device_get_nameunit(sc->dev), sc->params.tp.vlan_pri_map,
6696 sc->params.tp.vlan_pri_map = fconf;
6699 *mode = fconf_to_mode(sc->params.tp.vlan_pri_map);
6701 end_synchronized_op(sc, LOCK_HELD);
6706 set_filter_mode(struct adapter *sc, uint32_t mode)
6711 fconf = mode_to_fconf(mode);
6713 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
6718 if (sc->tids.ftids_in_use > 0) {
6724 if (sc->offload_map) {
6731 rc = -t4_set_filter_mode(sc, fconf);
6733 sc->filter_mode = fconf;
6739 end_synchronized_op(sc, LOCK_HELD);
6743 static inline uint64_t
6744 get_filter_hits(struct adapter *sc, uint32_t fid)
6746 uint32_t mw_base, off, tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6749 memwin_info(sc, 0, &mw_base, NULL);
6750 off = position_memwin(sc, 0,
6751 tcb_base + (fid + sc->tids.ftid_base) * TCB_SIZE);
6753 hits = t4_read_reg64(sc, mw_base + off + 16);
6754 hits = be64toh(hits);
6756 hits = t4_read_reg(sc, mw_base + off + 24);
6757 hits = be32toh(hits);
6764 get_filter(struct adapter *sc, struct t4_filter *t)
6766 int i, rc, nfilters = sc->tids.nftids;
6767 struct filter_entry *f;
6769 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
6774 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
6775 t->idx >= nfilters) {
6776 t->idx = 0xffffffff;
6780 f = &sc->tids.ftid_tab[t->idx];
6781 for (i = t->idx; i < nfilters; i++, f++) {
6784 t->l2tidx = f->l2t ? f->l2t->idx : 0;
6785 t->smtidx = f->smtidx;
6787 t->hits = get_filter_hits(sc, t->idx);
6789 t->hits = UINT64_MAX;
6796 t->idx = 0xffffffff;
6798 end_synchronized_op(sc, LOCK_HELD);
6803 set_filter(struct adapter *sc, struct t4_filter *t)
6805 unsigned int nfilters, nports;
6806 struct filter_entry *f;
6809 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
6813 nfilters = sc->tids.nftids;
6814 nports = sc->params.nports;
6816 if (nfilters == 0) {
6821 if (!(sc->flags & FULL_INIT_DONE)) {
6826 if (t->idx >= nfilters) {
6831 /* Validate against the global filter mode */
6832 if ((sc->params.tp.vlan_pri_map | fspec_to_fconf(&t->fs)) !=
6833 sc->params.tp.vlan_pri_map) {
6838 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
6843 if (t->fs.val.iport >= nports) {
6848 /* Can't specify an iq if not steering to it */
6849 if (!t->fs.dirsteer && t->fs.iq) {
6854 /* IPv6 filter idx must be 4 aligned */
6855 if (t->fs.type == 1 &&
6856 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
6861 if (sc->tids.ftid_tab == NULL) {
6862 KASSERT(sc->tids.ftids_in_use == 0,
6863 ("%s: no memory allocated but filters_in_use > 0",
6866 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
6867 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
6868 if (sc->tids.ftid_tab == NULL) {
6872 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
6875 for (i = 0; i < 4; i++) {
6876 f = &sc->tids.ftid_tab[t->idx + i];
6878 if (f->pending || f->valid) {
6887 if (t->fs.type == 0)
6891 f = &sc->tids.ftid_tab[t->idx];
6894 rc = set_filter_wr(sc, t->idx);
6896 end_synchronized_op(sc, 0);
6899 mtx_lock(&sc->tids.ftid_lock);
6901 if (f->pending == 0) {
6902 rc = f->valid ? 0 : EIO;
6906 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
6907 PCATCH, "t4setfw", 0)) {
6912 mtx_unlock(&sc->tids.ftid_lock);
6918 del_filter(struct adapter *sc, struct t4_filter *t)
6920 unsigned int nfilters;
6921 struct filter_entry *f;
6924 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
6928 nfilters = sc->tids.nftids;
6930 if (nfilters == 0) {
6935 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
6936 t->idx >= nfilters) {
6941 if (!(sc->flags & FULL_INIT_DONE)) {
6946 f = &sc->tids.ftid_tab[t->idx];
6958 t->fs = f->fs; /* extra info for the caller */
6959 rc = del_filter_wr(sc, t->idx);
6963 end_synchronized_op(sc, 0);
6966 mtx_lock(&sc->tids.ftid_lock);
6968 if (f->pending == 0) {
6969 rc = f->valid ? EIO : 0;
6973 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
6974 PCATCH, "t4delfw", 0)) {
6979 mtx_unlock(&sc->tids.ftid_lock);
6986 clear_filter(struct filter_entry *f)
6989 t4_l2t_release(f->l2t);
6991 bzero(f, sizeof (*f));
6995 set_filter_wr(struct adapter *sc, int fidx)
6997 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
6999 struct fw_filter_wr *fwr;
7002 ASSERT_SYNCHRONIZED_OP(sc);
7004 if (f->fs.newdmac || f->fs.newvlan) {
7005 /* This filter needs an L2T entry; allocate one. */
7006 f->l2t = t4_l2t_alloc_switching(sc->l2t);
7009 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
7011 t4_l2t_release(f->l2t);
7017 ftid = sc->tids.ftid_base + fidx;
7019 wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq);
7024 bzero(fwr, sizeof (*fwr));
7026 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
7027 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
7029 htobe32(V_FW_FILTER_WR_TID(ftid) |
7030 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
7031 V_FW_FILTER_WR_NOREPLY(0) |
7032 V_FW_FILTER_WR_IQ(f->fs.iq));
7033 fwr->del_filter_to_l2tix =
7034 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
7035 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
7036 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
7037 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
7038 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
7039 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
7040 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
7041 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
7042 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
7043 f->fs.newvlan == VLAN_REWRITE) |
7044 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
7045 f->fs.newvlan == VLAN_REWRITE) |
7046 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
7047 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
7048 V_FW_FILTER_WR_PRIO(f->fs.prio) |
7049 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
7050 fwr->ethtype = htobe16(f->fs.val.ethtype);
7051 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
7052 fwr->frag_to_ovlan_vldm =
7053 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
7054 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
7055 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
7056 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.vnic_vld) |
7057 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
7058 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.vnic_vld));
7060 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
7061 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
7062 fwr->maci_to_matchtypem =
7063 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
7064 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
7065 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
7066 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
7067 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
7068 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
7069 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
7070 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
7071 fwr->ptcl = f->fs.val.proto;
7072 fwr->ptclm = f->fs.mask.proto;
7073 fwr->ttyp = f->fs.val.tos;
7074 fwr->ttypm = f->fs.mask.tos;
7075 fwr->ivlan = htobe16(f->fs.val.vlan);
7076 fwr->ivlanm = htobe16(f->fs.mask.vlan);
7077 fwr->ovlan = htobe16(f->fs.val.vnic);
7078 fwr->ovlanm = htobe16(f->fs.mask.vnic);
7079 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
7080 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
7081 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
7082 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
7083 fwr->lp = htobe16(f->fs.val.dport);
7084 fwr->lpm = htobe16(f->fs.mask.dport);
7085 fwr->fp = htobe16(f->fs.val.sport);
7086 fwr->fpm = htobe16(f->fs.mask.sport);
7088 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
7091 sc->tids.ftids_in_use++;
7098 del_filter_wr(struct adapter *sc, int fidx)
7100 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7102 struct fw_filter_wr *fwr;
7105 ftid = sc->tids.ftid_base + fidx;
7107 wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq);
7111 bzero(fwr, sizeof (*fwr));
7113 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
7121 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
7123 struct adapter *sc = iq->adapter;
7124 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
7125 unsigned int idx = GET_TID(rpl);
7127 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
7130 if (idx >= sc->tids.ftid_base &&
7131 (idx -= sc->tids.ftid_base) < sc->tids.nftids) {
7132 unsigned int rc = G_COOKIE(rpl->cookie);
7133 struct filter_entry *f = &sc->tids.ftid_tab[idx];
7135 mtx_lock(&sc->tids.ftid_lock);
7136 if (rc == FW_FILTER_WR_FLT_ADDED) {
7137 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
7139 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
7140 f->pending = 0; /* asynchronous setup completed */
7143 if (rc != FW_FILTER_WR_FLT_DELETED) {
7144 /* Add or delete failed, display an error */
7146 "filter %u setup failed with error %u\n",
7151 sc->tids.ftids_in_use--;
7153 wakeup(&sc->tids.ftid_tab);
7154 mtx_unlock(&sc->tids.ftid_lock);
7161 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
7165 if (cntxt->cid > M_CTXTQID)
7168 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
7169 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
7172 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
7176 if (sc->flags & FW_OK) {
7177 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
7184 * Read via firmware failed or wasn't even attempted. Read directly via
7187 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
7189 end_synchronized_op(sc, 0);
7194 load_fw(struct adapter *sc, struct t4_data *fw)
7199 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
7203 if (sc->flags & FULL_INIT_DONE) {
7208 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
7209 if (fw_data == NULL) {
7214 rc = copyin(fw->data, fw_data, fw->len);
7216 rc = -t4_load_fw(sc, fw_data, fw->len);
7218 free(fw_data, M_CXGBE);
7220 end_synchronized_op(sc, 0);
7225 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
7227 uint32_t addr, off, remaining, i, n;
7229 uint32_t mw_base, mw_aperture;
7233 rc = validate_mem_range(sc, mr->addr, mr->len);
7237 memwin_info(sc, win, &mw_base, &mw_aperture);
7238 buf = b = malloc(min(mr->len, mw_aperture), M_CXGBE, M_WAITOK);
7240 remaining = mr->len;
7241 dst = (void *)mr->data;
7244 off = position_memwin(sc, win, addr);
7246 /* number of bytes that we'll copy in the inner loop */
7247 n = min(remaining, mw_aperture - off);
7248 for (i = 0; i < n; i += 4)
7249 *b++ = t4_read_reg(sc, mw_base + off + i);
7251 rc = copyout(buf, dst, n);
7266 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
7270 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
7273 if (i2cd->len > 1) {
7274 /* XXX: need fw support for longer reads in one go */
7278 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
7281 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
7282 i2cd->offset, &i2cd->data[0]);
7283 end_synchronized_op(sc, 0);
7289 t4_os_find_pci_capability(struct adapter *sc, int cap)
7293 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
7297 t4_os_pci_save_state(struct adapter *sc)
7300 struct pci_devinfo *dinfo;
7303 dinfo = device_get_ivars(dev);
7305 pci_cfg_save(dev, dinfo, 0);
7310 t4_os_pci_restore_state(struct adapter *sc)
7313 struct pci_devinfo *dinfo;
7316 dinfo = device_get_ivars(dev);
7318 pci_cfg_restore(dev, dinfo);
7323 t4_os_portmod_changed(const struct adapter *sc, int idx)
7325 struct port_info *pi = sc->port[idx];
7326 static const char *mod_str[] = {
7327 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
7330 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
7331 if_printf(pi->ifp, "transceiver unplugged.\n");
7332 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
7333 if_printf(pi->ifp, "unknown transceiver inserted.\n");
7334 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
7335 if_printf(pi->ifp, "unsupported transceiver inserted.\n");
7336 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
7337 if_printf(pi->ifp, "%s transceiver inserted.\n",
7338 mod_str[pi->mod_type]);
7340 if_printf(pi->ifp, "transceiver (type %d) inserted.\n",
7346 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
7348 struct port_info *pi = sc->port[idx];
7349 struct ifnet *ifp = pi->ifp;
7353 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
7354 if_link_state_change(ifp, LINK_STATE_UP);
7357 pi->linkdnrc = reason;
7358 if_link_state_change(ifp, LINK_STATE_DOWN);
7363 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
7367 sx_slock(&t4_list_lock);
7368 SLIST_FOREACH(sc, &t4_list, link) {
7370 * func should not make any assumptions about what state sc is
7371 * in - the only guarantee is that sc->sc_lock is a valid lock.
7375 sx_sunlock(&t4_list_lock);
7379 t4_open(struct cdev *dev, int flags, int type, struct thread *td)
7385 t4_close(struct cdev *dev, int flags, int type, struct thread *td)
7391 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
7395 struct adapter *sc = dev->si_drv1;
7397 rc = priv_check(td, PRIV_DRIVER);
7402 case CHELSIO_T4_GETREG: {
7403 struct t4_reg *edata = (struct t4_reg *)data;
7405 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
7408 if (edata->size == 4)
7409 edata->val = t4_read_reg(sc, edata->addr);
7410 else if (edata->size == 8)
7411 edata->val = t4_read_reg64(sc, edata->addr);
7417 case CHELSIO_T4_SETREG: {
7418 struct t4_reg *edata = (struct t4_reg *)data;
7420 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
7423 if (edata->size == 4) {
7424 if (edata->val & 0xffffffff00000000)
7426 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
7427 } else if (edata->size == 8)
7428 t4_write_reg64(sc, edata->addr, edata->val);
7433 case CHELSIO_T4_REGDUMP: {
7434 struct t4_regdump *regs = (struct t4_regdump *)data;
7435 int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE;
7438 if (regs->len < reglen) {
7439 regs->len = reglen; /* hint to the caller */
7444 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
7445 t4_get_regs(sc, regs, buf);
7446 rc = copyout(buf, regs->data, reglen);
7450 case CHELSIO_T4_GET_FILTER_MODE:
7451 rc = get_filter_mode(sc, (uint32_t *)data);
7453 case CHELSIO_T4_SET_FILTER_MODE:
7454 rc = set_filter_mode(sc, *(uint32_t *)data);
7456 case CHELSIO_T4_GET_FILTER:
7457 rc = get_filter(sc, (struct t4_filter *)data);
7459 case CHELSIO_T4_SET_FILTER:
7460 rc = set_filter(sc, (struct t4_filter *)data);
7462 case CHELSIO_T4_DEL_FILTER:
7463 rc = del_filter(sc, (struct t4_filter *)data);
7465 case CHELSIO_T4_GET_SGE_CONTEXT:
7466 rc = get_sge_context(sc, (struct t4_sge_context *)data);
7468 case CHELSIO_T4_LOAD_FW:
7469 rc = load_fw(sc, (struct t4_data *)data);
7471 case CHELSIO_T4_GET_MEM:
7472 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
7474 case CHELSIO_T4_GET_I2C:
7475 rc = read_i2c(sc, (struct t4_i2c_data *)data);
7477 case CHELSIO_T4_CLEAR_STATS: {
7479 u_int port_id = *(uint32_t *)data;
7480 struct port_info *pi;
7482 if (port_id >= sc->params.nports)
7486 t4_clr_port_stats(sc, port_id);
7488 pi = sc->port[port_id];
7489 if (pi->flags & PORT_INIT_DONE) {
7490 struct sge_rxq *rxq;
7491 struct sge_txq *txq;
7492 struct sge_wrq *wrq;
7494 for_each_rxq(pi, i, rxq) {
7495 #if defined(INET) || defined(INET6)
7496 rxq->lro.lro_queued = 0;
7497 rxq->lro.lro_flushed = 0;
7500 rxq->vlan_extraction = 0;
7503 for_each_txq(pi, i, txq) {
7506 txq->vlan_insertion = 0;
7510 txq->txpkts_wrs = 0;
7511 txq->txpkts_pkts = 0;
7512 txq->br->br_drops = 0;
7518 /* nothing to clear for each ofld_rxq */
7520 for_each_ofld_txq(pi, i, wrq) {
7525 wrq = &sc->sge.ctrlq[pi->port_id];
7531 case CHELSIO_T4_GET_TRACER:
7532 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
7534 case CHELSIO_T4_SET_TRACER:
7535 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
7546 toe_capability(struct port_info *pi, int enable)
7549 struct adapter *sc = pi->adapter;
7551 ASSERT_SYNCHRONIZED_OP(sc);
7553 if (!is_offload(sc))
7557 if (!(sc->flags & FULL_INIT_DONE)) {
7558 rc = cxgbe_init_synchronized(pi);
7563 if (isset(&sc->offload_map, pi->port_id))
7566 if (!(sc->flags & TOM_INIT_DONE)) {
7567 rc = t4_activate_uld(sc, ULD_TOM);
7570 "You must kldload t4_tom.ko before trying "
7571 "to enable TOE on a cxgbe interface.\n");
7575 KASSERT(sc->tom_softc != NULL,
7576 ("%s: TOM activated but softc NULL", __func__));
7577 KASSERT(sc->flags & TOM_INIT_DONE,
7578 ("%s: TOM activated but flag not set", __func__));
7581 setbit(&sc->offload_map, pi->port_id);
7583 if (!isset(&sc->offload_map, pi->port_id))
7586 KASSERT(sc->flags & TOM_INIT_DONE,
7587 ("%s: TOM never initialized?", __func__));
7588 clrbit(&sc->offload_map, pi->port_id);
7595 * Add an upper layer driver to the global list.
7598 t4_register_uld(struct uld_info *ui)
7603 sx_xlock(&t4_uld_list_lock);
7604 SLIST_FOREACH(u, &t4_uld_list, link) {
7605 if (u->uld_id == ui->uld_id) {
7611 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
7614 sx_xunlock(&t4_uld_list_lock);
7619 t4_unregister_uld(struct uld_info *ui)
7624 sx_xlock(&t4_uld_list_lock);
7626 SLIST_FOREACH(u, &t4_uld_list, link) {
7628 if (ui->refcount > 0) {
7633 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
7639 sx_xunlock(&t4_uld_list_lock);
7644 t4_activate_uld(struct adapter *sc, int id)
7647 struct uld_info *ui;
7649 ASSERT_SYNCHRONIZED_OP(sc);
7651 sx_slock(&t4_uld_list_lock);
7653 SLIST_FOREACH(ui, &t4_uld_list, link) {
7654 if (ui->uld_id == id) {
7655 rc = ui->activate(sc);
7662 sx_sunlock(&t4_uld_list_lock);
7668 t4_deactivate_uld(struct adapter *sc, int id)
7671 struct uld_info *ui;
7673 ASSERT_SYNCHRONIZED_OP(sc);
7675 sx_slock(&t4_uld_list_lock);
7677 SLIST_FOREACH(ui, &t4_uld_list, link) {
7678 if (ui->uld_id == id) {
7679 rc = ui->deactivate(sc);
7686 sx_sunlock(&t4_uld_list_lock);
7693 * Come up with reasonable defaults for some of the tunables, provided they're
7694 * not set by the user (in which case we'll use the values as is).
7697 tweak_tunables(void)
7699 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
7702 t4_ntxq10g = min(nc, NTXQ_10G);
7705 t4_ntxq1g = min(nc, NTXQ_1G);
7708 t4_nrxq10g = min(nc, NRXQ_10G);
7711 t4_nrxq1g = min(nc, NRXQ_1G);
7714 if (t4_nofldtxq10g < 1)
7715 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
7717 if (t4_nofldtxq1g < 1)
7718 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
7720 if (t4_nofldrxq10g < 1)
7721 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
7723 if (t4_nofldrxq1g < 1)
7724 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
7726 if (t4_toecaps_allowed == -1)
7727 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
7729 if (t4_toecaps_allowed == -1)
7730 t4_toecaps_allowed = 0;
7733 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
7734 t4_tmr_idx_10g = TMR_IDX_10G;
7736 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
7737 t4_pktc_idx_10g = PKTC_IDX_10G;
7739 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
7740 t4_tmr_idx_1g = TMR_IDX_1G;
7742 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
7743 t4_pktc_idx_1g = PKTC_IDX_1G;
7745 if (t4_qsize_txq < 128)
7748 if (t4_qsize_rxq < 128)
7750 while (t4_qsize_rxq & 7)
7753 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
7757 mod_event(module_t mod, int cmd, void *arg)
7760 static int loaded = 0;
7764 if (atomic_fetchadd_int(&loaded, 1))
7767 sx_init(&t4_list_lock, "T4/T5 adapters");
7768 SLIST_INIT(&t4_list);
7770 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
7771 SLIST_INIT(&t4_uld_list);
7773 t4_tracer_modload();
7778 if (atomic_fetchadd_int(&loaded, -1) > 1)
7780 t4_tracer_modunload();
7782 sx_slock(&t4_uld_list_lock);
7783 if (!SLIST_EMPTY(&t4_uld_list)) {
7785 sx_sunlock(&t4_uld_list_lock);
7788 sx_sunlock(&t4_uld_list_lock);
7789 sx_destroy(&t4_uld_list_lock);
7791 sx_slock(&t4_list_lock);
7792 if (!SLIST_EMPTY(&t4_list)) {
7794 sx_sunlock(&t4_list_lock);
7797 sx_sunlock(&t4_list_lock);
7798 sx_destroy(&t4_list_lock);
7805 static devclass_t t4_devclass, t5_devclass;
7806 static devclass_t cxgbe_devclass, cxl_devclass;
7808 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
7809 MODULE_VERSION(t4nex, 1);
7810 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
7812 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
7813 MODULE_VERSION(t5nex, 1);
7814 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
7816 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
7817 MODULE_VERSION(cxgbe, 1);
7819 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
7820 MODULE_VERSION(cxl, 1);