2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_kern_tls.h"
37 #include "opt_ratelimit.h"
40 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/eventhandler.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/queue.h>
49 #include <sys/taskqueue.h>
50 #include <sys/pciio.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pci_private.h>
54 #include <sys/firmware.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/sysctl.h>
60 #include <net/ethernet.h>
62 #include <net/if_types.h>
63 #include <net/if_dl.h>
64 #include <net/if_vlan_var.h>
66 #include <net/rss_config.h>
68 #include <netinet/in.h>
69 #include <netinet/ip.h>
71 #include <netinet/tcp_seq.h>
73 #if defined(__i386__) || defined(__amd64__)
74 #include <machine/md_var.h>
75 #include <machine/cputypes.h>
81 #include <ddb/db_lex.h>
84 #include "common/common.h"
85 #include "common/t4_msg.h"
86 #include "common/t4_regs.h"
87 #include "common/t4_regs_values.h"
88 #include "cudbg/cudbg.h"
92 #include "t4_mp_ring.h"
96 /* T4 bus driver interface */
97 static int t4_probe(device_t);
98 static int t4_attach(device_t);
99 static int t4_detach(device_t);
100 static int t4_child_location(device_t, device_t, struct sbuf *);
101 static int t4_ready(device_t);
102 static int t4_read_port_device(device_t, int, device_t *);
103 static int t4_suspend(device_t);
104 static int t4_resume(device_t);
105 static int t4_reset_prepare(device_t, device_t);
106 static int t4_reset_post(device_t, device_t);
107 static device_method_t t4_methods[] = {
108 DEVMETHOD(device_probe, t4_probe),
109 DEVMETHOD(device_attach, t4_attach),
110 DEVMETHOD(device_detach, t4_detach),
111 DEVMETHOD(device_suspend, t4_suspend),
112 DEVMETHOD(device_resume, t4_resume),
114 DEVMETHOD(bus_child_location, t4_child_location),
115 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
116 DEVMETHOD(bus_reset_post, t4_reset_post),
118 DEVMETHOD(t4_is_main_ready, t4_ready),
119 DEVMETHOD(t4_read_port_device, t4_read_port_device),
123 static driver_t t4_driver = {
126 sizeof(struct adapter)
130 /* T4 port (cxgbe) interface */
131 static int cxgbe_probe(device_t);
132 static int cxgbe_attach(device_t);
133 static int cxgbe_detach(device_t);
134 device_method_t cxgbe_methods[] = {
135 DEVMETHOD(device_probe, cxgbe_probe),
136 DEVMETHOD(device_attach, cxgbe_attach),
137 DEVMETHOD(device_detach, cxgbe_detach),
140 static driver_t cxgbe_driver = {
143 sizeof(struct port_info)
146 /* T4 VI (vcxgbe) interface */
147 static int vcxgbe_probe(device_t);
148 static int vcxgbe_attach(device_t);
149 static int vcxgbe_detach(device_t);
150 static device_method_t vcxgbe_methods[] = {
151 DEVMETHOD(device_probe, vcxgbe_probe),
152 DEVMETHOD(device_attach, vcxgbe_attach),
153 DEVMETHOD(device_detach, vcxgbe_detach),
156 static driver_t vcxgbe_driver = {
159 sizeof(struct vi_info)
162 static d_ioctl_t t4_ioctl;
164 static struct cdevsw t4_cdevsw = {
165 .d_version = D_VERSION,
170 /* T5 bus driver interface */
171 static int t5_probe(device_t);
172 static device_method_t t5_methods[] = {
173 DEVMETHOD(device_probe, t5_probe),
174 DEVMETHOD(device_attach, t4_attach),
175 DEVMETHOD(device_detach, t4_detach),
176 DEVMETHOD(device_suspend, t4_suspend),
177 DEVMETHOD(device_resume, t4_resume),
179 DEVMETHOD(bus_child_location, t4_child_location),
180 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
181 DEVMETHOD(bus_reset_post, t4_reset_post),
183 DEVMETHOD(t4_is_main_ready, t4_ready),
184 DEVMETHOD(t4_read_port_device, t4_read_port_device),
188 static driver_t t5_driver = {
191 sizeof(struct adapter)
195 /* T5 port (cxl) interface */
196 static driver_t cxl_driver = {
199 sizeof(struct port_info)
202 /* T5 VI (vcxl) interface */
203 static driver_t vcxl_driver = {
206 sizeof(struct vi_info)
209 /* T6 bus driver interface */
210 static int t6_probe(device_t);
211 static device_method_t t6_methods[] = {
212 DEVMETHOD(device_probe, t6_probe),
213 DEVMETHOD(device_attach, t4_attach),
214 DEVMETHOD(device_detach, t4_detach),
215 DEVMETHOD(device_suspend, t4_suspend),
216 DEVMETHOD(device_resume, t4_resume),
218 DEVMETHOD(bus_child_location, t4_child_location),
219 DEVMETHOD(bus_reset_prepare, t4_reset_prepare),
220 DEVMETHOD(bus_reset_post, t4_reset_post),
222 DEVMETHOD(t4_is_main_ready, t4_ready),
223 DEVMETHOD(t4_read_port_device, t4_read_port_device),
227 static driver_t t6_driver = {
230 sizeof(struct adapter)
234 /* T6 port (cc) interface */
235 static driver_t cc_driver = {
238 sizeof(struct port_info)
241 /* T6 VI (vcc) interface */
242 static driver_t vcc_driver = {
245 sizeof(struct vi_info)
248 /* ifnet interface */
249 static void cxgbe_init(void *);
250 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
251 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
252 static void cxgbe_qflush(struct ifnet *);
253 #if defined(KERN_TLS) || defined(RATELIMIT)
254 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
255 struct m_snd_tag **);
258 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
261 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
262 * then ADAPTER_LOCK, then t4_uld_list_lock.
264 static struct sx t4_list_lock;
265 SLIST_HEAD(, adapter) t4_list;
267 static struct sx t4_uld_list_lock;
268 SLIST_HEAD(, uld_info) t4_uld_list;
272 * Tunables. See tweak_tunables() too.
274 * Each tunable is set to a default value here if it's known at compile-time.
275 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
276 * provide a reasonable default (upto n) when the driver is loaded.
278 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
279 * T5 are under hw.cxl.
281 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
282 "cxgbe(4) parameters");
283 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
284 "cxgbe(4) T5+ parameters");
285 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
286 "cxgbe(4) TOE parameters");
289 * Number of queues for tx and rx, NIC and offload.
293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
294 "Number of TX queues per port");
295 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
300 "Number of RX queues per port");
301 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
304 static int t4_ntxq_vi = -NTXQ_VI;
305 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
306 "Number of TX queues per VI");
309 static int t4_nrxq_vi = -NRXQ_VI;
310 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
311 "Number of RX queues per VI");
313 static int t4_rsrv_noflowq = 0;
314 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
315 0, "Reserve TX queue 0 of each VI for non-flowid packets");
317 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
319 static int t4_nofldtxq = -NOFLDTXQ;
320 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
321 "Number of offload TX queues per port");
324 static int t4_nofldrxq = -NOFLDRXQ;
325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
326 "Number of offload RX queues per port");
328 #define NOFLDTXQ_VI 1
329 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
330 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
331 "Number of offload TX queues per VI");
333 #define NOFLDRXQ_VI 1
334 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
335 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
336 "Number of offload RX queues per VI");
338 #define TMR_IDX_OFLD 1
339 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
340 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
341 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
343 #define PKTC_IDX_OFLD (-1)
344 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
345 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
346 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
348 /* 0 means chip/fw default, non-zero number is value in microseconds */
349 static u_long t4_toe_keepalive_idle = 0;
350 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
351 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
353 /* 0 means chip/fw default, non-zero number is value in microseconds */
354 static u_long t4_toe_keepalive_interval = 0;
355 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
356 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
358 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
359 static int t4_toe_keepalive_count = 0;
360 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
361 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
363 /* 0 means chip/fw default, non-zero number is value in microseconds */
364 static u_long t4_toe_rexmt_min = 0;
365 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
366 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
368 /* 0 means chip/fw default, non-zero number is value in microseconds */
369 static u_long t4_toe_rexmt_max = 0;
370 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
371 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
373 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
374 static int t4_toe_rexmt_count = 0;
375 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
378 /* -1 means chip/fw default, other values are raw backoff values to use */
379 static int t4_toe_rexmt_backoff[16] = {
380 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
382 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
384 "cxgbe(4) TOE retransmit backoff values");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[0], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[1], 0, "");
389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
390 &t4_toe_rexmt_backoff[2], 0, "");
391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
392 &t4_toe_rexmt_backoff[3], 0, "");
393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
394 &t4_toe_rexmt_backoff[4], 0, "");
395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
396 &t4_toe_rexmt_backoff[5], 0, "");
397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
398 &t4_toe_rexmt_backoff[6], 0, "");
399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
400 &t4_toe_rexmt_backoff[7], 0, "");
401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
402 &t4_toe_rexmt_backoff[8], 0, "");
403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
404 &t4_toe_rexmt_backoff[9], 0, "");
405 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
406 &t4_toe_rexmt_backoff[10], 0, "");
407 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
408 &t4_toe_rexmt_backoff[11], 0, "");
409 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
410 &t4_toe_rexmt_backoff[12], 0, "");
411 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
412 &t4_toe_rexmt_backoff[13], 0, "");
413 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
414 &t4_toe_rexmt_backoff[14], 0, "");
415 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
416 &t4_toe_rexmt_backoff[15], 0, "");
418 static int t4_toe_tls_rx_timeout = 5;
419 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, tls_rx_timeout, CTLFLAG_RDTUN,
420 &t4_toe_tls_rx_timeout, 0,
421 "Timeout in seconds to downgrade TLS sockets to plain TOE");
425 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */
426 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */
427 static int t4_native_netmap = NN_EXTRA_VI;
428 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
429 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs");
432 static int t4_nnmtxq = -NNMTXQ;
433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
434 "Number of netmap TX queues");
437 static int t4_nnmrxq = -NNMRXQ;
438 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
439 "Number of netmap RX queues");
442 static int t4_nnmtxq_vi = -NNMTXQ_VI;
443 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
444 "Number of netmap TX queues per VI");
447 static int t4_nnmrxq_vi = -NNMRXQ_VI;
448 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
449 "Number of netmap RX queues per VI");
453 * Holdoff parameters for ports.
456 int t4_tmr_idx = TMR_IDX;
457 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
458 0, "Holdoff timer index");
459 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
461 #define PKTC_IDX (-1)
462 int t4_pktc_idx = PKTC_IDX;
463 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
464 0, "Holdoff packet counter index");
465 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
468 * Size (# of entries) of each tx and rx queue.
470 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
471 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
472 "Number of descriptors in each TX queue");
474 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
475 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
476 "Number of descriptors in each RX queue");
479 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
481 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
482 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
483 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
486 * Configuration file. All the _CF names here are special.
488 #define DEFAULT_CF "default"
489 #define BUILTIN_CF "built-in"
490 #define FLASH_CF "flash"
491 #define UWIRE_CF "uwire"
492 #define FPGA_CF "fpga"
493 static char t4_cfg_file[32] = DEFAULT_CF;
494 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
495 sizeof(t4_cfg_file), "Firmware configuration file");
498 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
499 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
500 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
501 * mark or when signalled to do so, 0 to never emit PAUSE.
502 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
503 * negotiated settings will override rx_pause/tx_pause.
504 * Otherwise rx_pause/tx_pause are applied forcibly.
506 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
507 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
508 &t4_pause_settings, 0,
509 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
512 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
513 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
516 static int t4_fec = -1;
517 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
518 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
521 * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
522 * issues to the firmware. If the firmware doesn't support FORCE_FEC then the
523 * driver runs as if this is set to 0.
524 * -1 to set FORCE_FEC iff requested_fec != AUTO. Multiple FEC bits are okay.
525 * 0 to never set FORCE_FEC. requested_fec = AUTO means use the hint from the
526 * transceiver. Multiple FEC bits may not be okay but will be passed on to
527 * the firmware anyway (may result in l1cfg errors with old firmwares).
528 * 1 to always set FORCE_FEC. Multiple FEC bits are okay. requested_fec = AUTO
529 * means set all FEC bits that are valid for the speed.
531 static int t4_force_fec = -1;
532 SYSCTL_INT(_hw_cxgbe, OID_AUTO, force_fec, CTLFLAG_RDTUN, &t4_force_fec, 0,
533 "Controls the use of FORCE_FEC bit in L1 configuration.");
536 * Link autonegotiation.
537 * -1 to run with the firmware default.
541 static int t4_autoneg = -1;
542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
543 "Link autonegotiation");
546 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
547 * encouraged respectively). '-n' is the same as 'n' except the firmware
548 * version used in the checks is read from the firmware bundled with the driver.
550 static int t4_fw_install = 1;
551 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
552 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
555 * ASIC features that will be used. Disable the ones you don't want so that the
556 * chip resources aren't wasted on features that will not be used.
558 static int t4_nbmcaps_allowed = 0;
559 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
560 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
562 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
563 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
564 &t4_linkcaps_allowed, 0, "Default link capabilities");
566 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
567 FW_CAPS_CONFIG_SWITCH_EGRESS;
568 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
569 &t4_switchcaps_allowed, 0, "Default switch capabilities");
572 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
573 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
575 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
576 FW_CAPS_CONFIG_NIC_HASHFILTER;
578 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
579 &t4_niccaps_allowed, 0, "Default NIC capabilities");
581 static int t4_toecaps_allowed = -1;
582 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
583 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
585 static int t4_rdmacaps_allowed = -1;
586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
587 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
589 static int t4_cryptocaps_allowed = -1;
590 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
591 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
593 static int t4_iscsicaps_allowed = -1;
594 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
595 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
597 static int t4_fcoecaps_allowed = 0;
598 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
599 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
601 static int t5_write_combine = 0;
602 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
603 0, "Use WC instead of UC for BAR2");
605 static int t4_num_vis = 1;
606 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
607 "Number of VIs per port");
610 * PCIe Relaxed Ordering.
611 * -1: driver should figure out a good value.
616 static int pcie_relaxed_ordering = -1;
617 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
618 &pcie_relaxed_ordering, 0,
619 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
621 static int t4_panic_on_fatal_err = 0;
622 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RWTUN,
623 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
625 static int t4_reset_on_fatal_err = 0;
626 SYSCTL_INT(_hw_cxgbe, OID_AUTO, reset_on_fatal_err, CTLFLAG_RWTUN,
627 &t4_reset_on_fatal_err, 0, "reset adapter on fatal errors");
629 static int t4_tx_vm_wr = 0;
630 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_vm_wr, CTLFLAG_RWTUN, &t4_tx_vm_wr, 0,
631 "Use VM work requests to transmit packets.");
634 * Set to non-zero to enable the attack filter. A packet that matches any of
635 * these conditions will get dropped on ingress:
636 * 1) IP && source address == destination address.
637 * 2) TCP/IP && source address is not a unicast address.
638 * 3) TCP/IP && destination address is not a unicast address.
639 * 4) IP && source address is loopback (127.x.y.z).
640 * 5) IP && destination address is loopback (127.x.y.z).
641 * 6) IPv6 && source address == destination address.
642 * 7) IPv6 && source address is not a unicast address.
643 * 8) IPv6 && source address is loopback (::1/128).
644 * 9) IPv6 && destination address is loopback (::1/128).
645 * 10) IPv6 && source address is unspecified (::/128).
646 * 11) IPv6 && destination address is unspecified (::/128).
647 * 12) TCP/IPv6 && source address is multicast (ff00::/8).
648 * 13) TCP/IPv6 && destination address is multicast (ff00::/8).
650 static int t4_attack_filter = 0;
651 SYSCTL_INT(_hw_cxgbe, OID_AUTO, attack_filter, CTLFLAG_RDTUN,
652 &t4_attack_filter, 0, "Drop suspicious traffic");
654 static int t4_drop_ip_fragments = 0;
655 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_ip_fragments, CTLFLAG_RDTUN,
656 &t4_drop_ip_fragments, 0, "Drop IP fragments");
658 static int t4_drop_pkts_with_l2_errors = 1;
659 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l2_errors, CTLFLAG_RDTUN,
660 &t4_drop_pkts_with_l2_errors, 0,
661 "Drop all frames with Layer 2 length or checksum errors");
663 static int t4_drop_pkts_with_l3_errors = 0;
664 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l3_errors, CTLFLAG_RDTUN,
665 &t4_drop_pkts_with_l3_errors, 0,
666 "Drop all frames with IP version, length, or checksum errors");
668 static int t4_drop_pkts_with_l4_errors = 0;
669 SYSCTL_INT(_hw_cxgbe, OID_AUTO, drop_pkts_with_l4_errors, CTLFLAG_RDTUN,
670 &t4_drop_pkts_with_l4_errors, 0,
671 "Drop all frames with Layer 4 length, checksum, or other errors");
677 static int t4_cop_managed_offloading = 0;
678 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
679 &t4_cop_managed_offloading, 0,
680 "COP (Connection Offload Policy) controls all TOE offload");
685 * This enables KERN_TLS for all adapters if set.
687 static int t4_kern_tls = 0;
688 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
689 "Enable KERN_TLS mode for all supported adapters");
691 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
692 "cxgbe(4) KERN_TLS parameters");
694 static int t4_tls_inline_keys = 0;
695 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
696 &t4_tls_inline_keys, 0,
697 "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
700 static int t4_tls_combo_wrs = 0;
701 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
702 0, "Attempt to combine TCB field updates with TLS record work requests.");
705 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
706 static int vi_mac_funcs[] = {
710 FW_VI_FUNC_OPENISCSI,
716 struct intrs_and_queues {
717 uint16_t intr_type; /* INTx, MSI, or MSI-X */
718 uint16_t num_vis; /* number of VIs for each port */
719 uint16_t nirq; /* Total # of vectors */
720 uint16_t ntxq; /* # of NIC txq's for each port */
721 uint16_t nrxq; /* # of NIC rxq's for each port */
722 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
723 uint16_t nofldrxq; /* # of TOE rxq's for each port */
724 uint16_t nnmtxq; /* # of netmap txq's */
725 uint16_t nnmrxq; /* # of netmap rxq's */
727 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
728 uint16_t ntxq_vi; /* # of NIC txq's */
729 uint16_t nrxq_vi; /* # of NIC rxq's */
730 uint16_t nofldtxq_vi; /* # of TOE txq's */
731 uint16_t nofldrxq_vi; /* # of TOE rxq's */
732 uint16_t nnmtxq_vi; /* # of netmap txq's */
733 uint16_t nnmrxq_vi; /* # of netmap rxq's */
736 static void setup_memwin(struct adapter *);
737 static void position_memwin(struct adapter *, int, uint32_t);
738 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
739 static int fwmtype_to_hwmtype(int);
740 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
742 static int fixup_devlog_params(struct adapter *);
743 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
744 static int contact_firmware(struct adapter *);
745 static int partition_resources(struct adapter *);
746 static int get_params__pre_init(struct adapter *);
747 static int set_params__pre_init(struct adapter *);
748 static int get_params__post_init(struct adapter *);
749 static int set_params__post_init(struct adapter *);
750 static void t4_set_desc(struct adapter *);
751 static bool fixed_ifmedia(struct port_info *);
752 static void build_medialist(struct port_info *);
753 static void init_link_config(struct port_info *);
754 static int fixup_link_config(struct port_info *);
755 static int apply_link_config(struct port_info *);
756 static int cxgbe_init_synchronized(struct vi_info *);
757 static int cxgbe_uninit_synchronized(struct vi_info *);
758 static int adapter_full_init(struct adapter *);
759 static void adapter_full_uninit(struct adapter *);
760 static int vi_full_init(struct vi_info *);
761 static void vi_full_uninit(struct vi_info *);
762 static int alloc_extra_vi(struct adapter *, struct port_info *, struct vi_info *);
763 static void quiesce_txq(struct sge_txq *);
764 static void quiesce_wrq(struct sge_wrq *);
765 static void quiesce_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
766 static void quiesce_vi(struct vi_info *);
767 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
768 driver_intr_t *, void *, char *);
769 static int t4_free_irq(struct adapter *, struct irq *);
770 static void t4_init_atid_table(struct adapter *);
771 static void t4_free_atid_table(struct adapter *);
772 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
773 static void vi_refresh_stats(struct vi_info *);
774 static void cxgbe_refresh_stats(struct vi_info *);
775 static void cxgbe_tick(void *);
776 static void vi_tick(void *);
777 static void cxgbe_sysctls(struct port_info *);
778 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
779 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
780 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
781 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
782 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
783 static int sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS);
784 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
785 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
786 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
787 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
788 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
789 static int sysctl_link_fec(SYSCTL_HANDLER_ARGS);
790 static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
791 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
792 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
793 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
794 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
795 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
796 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
797 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
798 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
799 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
800 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
801 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
802 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
803 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
804 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
805 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
806 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
807 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
808 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
809 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
810 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
811 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
812 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
813 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
814 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
815 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
816 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
817 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
818 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
819 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
820 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
821 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
822 static int sysctl_tnl_stats(SYSCTL_HANDLER_ARGS);
823 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
824 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
825 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
826 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
827 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
828 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
829 static int sysctl_reset(SYSCTL_HANDLER_ARGS);
831 static int sysctl_tls(SYSCTL_HANDLER_ARGS);
832 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
833 static int sysctl_tls_rx_timeout(SYSCTL_HANDLER_ARGS);
834 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
835 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
836 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
837 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
838 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
839 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
840 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
842 static int get_sge_context(struct adapter *, struct t4_sge_context *);
843 static int load_fw(struct adapter *, struct t4_data *);
844 static int load_cfg(struct adapter *, struct t4_data *);
845 static int load_boot(struct adapter *, struct t4_bootrom *);
846 static int load_bootcfg(struct adapter *, struct t4_data *);
847 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
848 static void free_offload_policy(struct t4_offload_policy *);
849 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
850 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
851 static int read_i2c(struct adapter *, struct t4_i2c_data *);
852 static int clear_stats(struct adapter *, u_int);
853 static int hold_clip_addr(struct adapter *, struct t4_clip_addr *);
854 static int release_clip_addr(struct adapter *, struct t4_clip_addr *);
856 static int toe_capability(struct vi_info *, bool);
857 static void t4_async_event(struct adapter *);
860 static int ktls_capability(struct adapter *, bool);
862 static int mod_event(module_t, int, void *);
863 static int notify_siblings(device_t, int);
864 static uint64_t vi_get_counter(struct ifnet *, ift_counter);
865 static uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
866 static void enable_vxlan_rx(struct adapter *);
867 static void reset_adapter_task(void *, int);
868 static void fatal_error_task(void *, int);
869 static void dump_devlog(struct adapter *);
870 static void dump_cim_regs(struct adapter *);
871 static void dump_cimla(struct adapter *);
877 {0xa000, "Chelsio Terminator 4 FPGA"},
878 {0x4400, "Chelsio T440-dbg"},
879 {0x4401, "Chelsio T420-CR"},
880 {0x4402, "Chelsio T422-CR"},
881 {0x4403, "Chelsio T440-CR"},
882 {0x4404, "Chelsio T420-BCH"},
883 {0x4405, "Chelsio T440-BCH"},
884 {0x4406, "Chelsio T440-CH"},
885 {0x4407, "Chelsio T420-SO"},
886 {0x4408, "Chelsio T420-CX"},
887 {0x4409, "Chelsio T420-BT"},
888 {0x440a, "Chelsio T404-BT"},
889 {0x440e, "Chelsio T440-LP-CR"},
891 {0xb000, "Chelsio Terminator 5 FPGA"},
892 {0x5400, "Chelsio T580-dbg"},
893 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
894 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
895 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
896 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
897 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
898 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
899 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
900 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
901 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
902 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
903 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
904 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
905 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
906 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
907 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
908 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
909 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
912 {0x5483, "Custom T540-CR"},
913 {0x5484, "Custom T540-BT"},
915 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
916 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
917 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
918 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
919 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
920 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
921 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
922 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
923 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
924 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
925 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
926 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
927 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
928 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
929 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
930 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
933 {0x6480, "Custom T6225-CR"},
934 {0x6481, "Custom T62100-CR"},
935 {0x6482, "Custom T6225-CR"},
936 {0x6483, "Custom T62100-CR"},
937 {0x6484, "Custom T64100-CR"},
938 {0x6485, "Custom T6240-SO"},
939 {0x6486, "Custom T6225-SO-CR"},
940 {0x6487, "Custom T6225-CR"},
945 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
946 * be exactly the same for both rxq and ofld_rxq.
948 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
949 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
951 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
954 t4_probe(device_t dev)
957 uint16_t v = pci_get_vendor(dev);
958 uint16_t d = pci_get_device(dev);
959 uint8_t f = pci_get_function(dev);
961 if (v != PCI_VENDOR_ID_CHELSIO)
964 /* Attach only to PF0 of the FPGA */
965 if (d == 0xa000 && f != 0)
968 for (i = 0; i < nitems(t4_pciids); i++) {
969 if (d == t4_pciids[i].device) {
970 device_set_desc(dev, t4_pciids[i].desc);
971 return (BUS_PROBE_DEFAULT);
979 t5_probe(device_t dev)
982 uint16_t v = pci_get_vendor(dev);
983 uint16_t d = pci_get_device(dev);
984 uint8_t f = pci_get_function(dev);
986 if (v != PCI_VENDOR_ID_CHELSIO)
989 /* Attach only to PF0 of the FPGA */
990 if (d == 0xb000 && f != 0)
993 for (i = 0; i < nitems(t5_pciids); i++) {
994 if (d == t5_pciids[i].device) {
995 device_set_desc(dev, t5_pciids[i].desc);
996 return (BUS_PROBE_DEFAULT);
1004 t6_probe(device_t dev)
1007 uint16_t v = pci_get_vendor(dev);
1008 uint16_t d = pci_get_device(dev);
1010 if (v != PCI_VENDOR_ID_CHELSIO)
1013 for (i = 0; i < nitems(t6_pciids); i++) {
1014 if (d == t6_pciids[i].device) {
1015 device_set_desc(dev, t6_pciids[i].desc);
1016 return (BUS_PROBE_DEFAULT);
1024 t5_attribute_workaround(device_t dev)
1030 * The T5 chips do not properly echo the No Snoop and Relaxed
1031 * Ordering attributes when replying to a TLP from a Root
1032 * Port. As a workaround, find the parent Root Port and
1033 * disable No Snoop and Relaxed Ordering. Note that this
1034 * affects all devices under this root port.
1036 root_port = pci_find_pcie_root_port(dev);
1037 if (root_port == NULL) {
1038 device_printf(dev, "Unable to find parent root port\n");
1042 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
1043 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
1044 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
1046 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
1047 device_get_nameunit(root_port));
1050 static const struct devnames devnames[] = {
1052 .nexus_name = "t4nex",
1053 .ifnet_name = "cxgbe",
1054 .vi_ifnet_name = "vcxgbe",
1055 .pf03_drv_name = "t4iov",
1056 .vf_nexus_name = "t4vf",
1057 .vf_ifnet_name = "cxgbev"
1059 .nexus_name = "t5nex",
1060 .ifnet_name = "cxl",
1061 .vi_ifnet_name = "vcxl",
1062 .pf03_drv_name = "t5iov",
1063 .vf_nexus_name = "t5vf",
1064 .vf_ifnet_name = "cxlv"
1066 .nexus_name = "t6nex",
1068 .vi_ifnet_name = "vcc",
1069 .pf03_drv_name = "t6iov",
1070 .vf_nexus_name = "t6vf",
1071 .vf_ifnet_name = "ccv"
1076 t4_init_devnames(struct adapter *sc)
1081 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
1082 sc->names = &devnames[id - CHELSIO_T4];
1084 device_printf(sc->dev, "chip id %d is not supported.\n", id);
1090 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
1092 const char *parent, *name;
1097 parent = device_get_nameunit(sc->dev);
1098 name = sc->names->ifnet_name;
1099 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
1100 if (resource_long_value(name, unit, "port", &value) == 0 &&
1101 value == pi->port_id)
1108 t4_attach(device_t dev)
1111 int rc = 0, i, j, rqidx, tqidx, nports;
1112 struct make_dev_args mda;
1113 struct intrs_and_queues iaq;
1116 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1123 int nm_rqidx, nm_tqidx;
1127 sc = device_get_softc(dev);
1129 sysctl_ctx_init(&sc->ctx);
1130 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1132 if ((pci_get_device(dev) & 0xff00) == 0x5400)
1133 t5_attribute_workaround(dev);
1134 pci_enable_busmaster(dev);
1135 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1138 pci_set_max_read_req(dev, 4096);
1139 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1140 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1141 if (pcie_relaxed_ordering == 0 &&
1142 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1143 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1144 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1145 } else if (pcie_relaxed_ordering == 1 &&
1146 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1147 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1148 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1152 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1153 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1155 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1156 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1157 device_get_nameunit(dev));
1159 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1160 device_get_nameunit(dev));
1161 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1164 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1165 TAILQ_INIT(&sc->sfl);
1166 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1168 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1171 rw_init(&sc->policy_lock, "connection offload policy");
1173 callout_init(&sc->ktls_tick, 1);
1175 refcount_init(&sc->vxlan_refcount, 0);
1177 TASK_INIT(&sc->reset_task, 0, reset_adapter_task, sc);
1178 TASK_INIT(&sc->fatal_error_task, 0, fatal_error_task, sc);
1180 sc->ctrlq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1181 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "ctrlq",
1182 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1183 sc->fwq_oid = SYSCTL_ADD_NODE(&sc->ctx,
1184 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "fwq",
1185 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
1187 rc = t4_map_bars_0_and_4(sc);
1189 goto done; /* error message displayed already */
1191 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1193 /* Prepare the adapter for operation. */
1194 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1195 rc = -t4_prep_adapter(sc, buf);
1198 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1203 * This is the real PF# to which we're attaching. Works from within PCI
1204 * passthrough environments too, where pci_get_function() could return a
1205 * different PF# depending on the passthrough configuration. We need to
1206 * use the real PF# in all our communication with the firmware.
1208 j = t4_read_reg(sc, A_PL_WHOAMI);
1209 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1212 t4_init_devnames(sc);
1213 if (sc->names == NULL) {
1215 goto done; /* error message displayed already */
1219 * Do this really early, with the memory windows set up even before the
1220 * character device. The userland tool's register i/o and mem read
1221 * will work even in "recovery mode".
1224 if (t4_init_devlog_params(sc, 0) == 0)
1225 fixup_devlog_params(sc);
1226 make_dev_args_init(&mda);
1227 mda.mda_devsw = &t4_cdevsw;
1228 mda.mda_uid = UID_ROOT;
1229 mda.mda_gid = GID_WHEEL;
1230 mda.mda_mode = 0600;
1231 mda.mda_si_drv1 = sc;
1232 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1234 device_printf(dev, "failed to create nexus char device: %d.\n",
1237 /* Go no further if recovery mode has been requested. */
1238 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1239 device_printf(dev, "recovery mode.\n");
1243 #if defined(__i386__)
1244 if ((cpu_feature & CPUID_CX8) == 0) {
1245 device_printf(dev, "64 bit atomics not available.\n");
1251 /* Contact the firmware and try to become the master driver. */
1252 rc = contact_firmware(sc);
1254 goto done; /* error message displayed already */
1255 MPASS(sc->flags & FW_OK);
1257 rc = get_params__pre_init(sc);
1259 goto done; /* error message displayed already */
1261 if (sc->flags & MASTER_PF) {
1262 rc = partition_resources(sc);
1264 goto done; /* error message displayed already */
1268 rc = get_params__post_init(sc);
1270 goto done; /* error message displayed already */
1272 rc = set_params__post_init(sc);
1274 goto done; /* error message displayed already */
1276 rc = t4_map_bar_2(sc);
1278 goto done; /* error message displayed already */
1280 rc = t4_create_dma_tag(sc);
1282 goto done; /* error message displayed already */
1285 * First pass over all the ports - allocate VIs and initialize some
1286 * basic parameters like mac address, port type, etc.
1288 for_each_port(sc, i) {
1289 struct port_info *pi;
1291 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1294 /* These must be set before t4_port_init */
1298 * XXX: vi[0] is special so we can't delay this allocation until
1299 * pi->nvi's final value is known.
1301 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1305 * Allocate the "main" VI and initialize parameters
1308 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1310 device_printf(dev, "unable to initialize port %d: %d\n",
1312 free(pi->vi, M_CXGBE);
1318 if (is_bt(pi->port_type))
1319 setbit(&sc->bt_map, pi->tx_chan);
1321 MPASS(!isset(&sc->bt_map, pi->tx_chan));
1323 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1324 device_get_nameunit(dev), i);
1325 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1326 sc->chan_map[pi->tx_chan] = i;
1329 * The MPS counter for FCS errors doesn't work correctly on the
1330 * T6 so we use the MAC counter here. Which MAC is in use
1331 * depends on the link settings which will be known when the
1336 } else if (is_t4(sc)) {
1337 pi->fcs_reg = PORT_REG(pi->tx_chan,
1338 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
1340 pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
1341 A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
1345 /* All VIs on this port share this media. */
1346 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1347 cxgbe_media_status);
1350 init_link_config(pi);
1351 fixup_link_config(pi);
1352 build_medialist(pi);
1353 if (fixed_ifmedia(pi))
1354 pi->flags |= FIXED_IFMEDIA;
1357 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1358 t4_ifnet_unit(sc, pi));
1359 if (pi->dev == NULL) {
1361 "failed to add device for port %d.\n", i);
1365 pi->vi[0].dev = pi->dev;
1366 device_set_softc(pi->dev, pi);
1370 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1372 nports = sc->params.nports;
1373 rc = cfg_itype_and_nqueues(sc, &iaq);
1375 goto done; /* error message displayed already */
1377 num_vis = iaq.num_vis;
1378 sc->intr_type = iaq.intr_type;
1379 sc->intr_count = iaq.nirq;
1382 s->nrxq = nports * iaq.nrxq;
1383 s->ntxq = nports * iaq.ntxq;
1385 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1386 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1388 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1389 s->neq += nports; /* ctrl queues: 1 per port */
1390 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1391 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1392 if (is_offload(sc) || is_ethoffload(sc)) {
1393 s->nofldtxq = nports * iaq.nofldtxq;
1395 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1396 s->neq += s->nofldtxq;
1398 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_ofld_txq),
1399 M_CXGBE, M_ZERO | M_WAITOK);
1403 if (is_offload(sc)) {
1404 s->nofldrxq = nports * iaq.nofldrxq;
1406 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1407 s->neq += s->nofldrxq; /* free list */
1408 s->niq += s->nofldrxq;
1410 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1411 M_CXGBE, M_ZERO | M_WAITOK);
1417 if (t4_native_netmap & NN_MAIN_VI) {
1418 s->nnmrxq += nports * iaq.nnmrxq;
1419 s->nnmtxq += nports * iaq.nnmtxq;
1421 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1422 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1423 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1425 s->neq += s->nnmtxq + s->nnmrxq;
1426 s->niq += s->nnmrxq;
1428 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1429 M_CXGBE, M_ZERO | M_WAITOK);
1430 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1431 M_CXGBE, M_ZERO | M_WAITOK);
1433 MPASS(s->niq <= s->iqmap_sz);
1434 MPASS(s->neq <= s->eqmap_sz);
1436 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1438 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1440 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1442 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
1444 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
1447 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1450 t4_init_l2t(sc, M_WAITOK);
1451 t4_init_smt(sc, M_WAITOK);
1452 t4_init_tx_sched(sc);
1453 t4_init_atid_table(sc);
1455 t4_init_etid_table(sc);
1458 t4_init_clip_table(sc);
1460 if (sc->vres.key.size != 0)
1461 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1462 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1465 * Second pass over the ports. This time we know the number of rx and
1466 * tx queues that each port should get.
1469 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1476 nm_rqidx = nm_tqidx = 0;
1478 for_each_port(sc, i) {
1479 struct port_info *pi = sc->port[i];
1486 for_each_vi(pi, j, vi) {
1489 vi->first_intr = -1;
1490 vi->qsize_rxq = t4_qsize_rxq;
1491 vi->qsize_txq = t4_qsize_txq;
1493 vi->first_rxq = rqidx;
1494 vi->first_txq = tqidx;
1495 vi->tmr_idx = t4_tmr_idx;
1496 vi->pktc_idx = t4_pktc_idx;
1497 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1498 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1503 if (j == 0 && vi->ntxq > 1)
1504 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1506 vi->rsrv_noflowq = 0;
1508 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1509 vi->first_ofld_txq = ofld_tqidx;
1510 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1511 ofld_tqidx += vi->nofldtxq;
1514 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1515 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1516 vi->first_ofld_rxq = ofld_rqidx;
1517 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1519 ofld_rqidx += vi->nofldrxq;
1522 vi->first_nm_rxq = nm_rqidx;
1523 vi->first_nm_txq = nm_tqidx;
1525 vi->nnmrxq = iaq.nnmrxq;
1526 vi->nnmtxq = iaq.nnmtxq;
1528 vi->nnmrxq = iaq.nnmrxq_vi;
1529 vi->nnmtxq = iaq.nnmtxq_vi;
1531 nm_rqidx += vi->nnmrxq;
1532 nm_tqidx += vi->nnmtxq;
1537 rc = t4_setup_intr_handlers(sc);
1540 "failed to setup interrupt handlers: %d\n", rc);
1544 rc = bus_generic_probe(dev);
1546 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1551 * Ensure thread-safe mailbox access (in debug builds).
1553 * So far this was the only thread accessing the mailbox but various
1554 * ifnets and sysctls are about to be created and their handlers/ioctls
1555 * will access the mailbox from different threads.
1557 sc->flags |= CHK_MBOX_ACCESS;
1559 rc = bus_generic_attach(dev);
1562 "failed to attach all child ports: %d\n", rc);
1567 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1568 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1569 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1570 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1571 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1575 notify_siblings(dev, 0);
1578 if (rc != 0 && sc->cdev) {
1579 /* cdev was created and so cxgbetool works; recover that way. */
1581 "error during attach, adapter is now in recovery mode.\n");
1586 t4_detach_common(dev);
1594 t4_child_location(device_t bus, device_t dev, struct sbuf *sb)
1597 struct port_info *pi;
1600 sc = device_get_softc(bus);
1601 for_each_port(sc, i) {
1603 if (pi != NULL && pi->dev == dev) {
1604 sbuf_printf(sb, "port=%d", pi->port_id);
1612 t4_ready(device_t dev)
1616 sc = device_get_softc(dev);
1617 if (sc->flags & FW_OK)
1623 t4_read_port_device(device_t dev, int port, device_t *child)
1626 struct port_info *pi;
1628 sc = device_get_softc(dev);
1629 if (port < 0 || port >= MAX_NPORTS)
1631 pi = sc->port[port];
1632 if (pi == NULL || pi->dev == NULL)
1639 notify_siblings(device_t dev, int detaching)
1645 for (i = 0; i < PCI_FUNCMAX; i++) {
1646 if (i == pci_get_function(dev))
1648 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1649 pci_get_slot(dev), i);
1650 if (sibling == NULL || !device_is_attached(sibling))
1653 error = T4_DETACH_CHILD(sibling);
1655 (void)T4_ATTACH_CHILD(sibling);
1666 t4_detach(device_t dev)
1670 rc = notify_siblings(dev, 1);
1673 "failed to detach sibling devices: %d\n", rc);
1677 return (t4_detach_common(dev));
1681 t4_detach_common(device_t dev)
1684 struct port_info *pi;
1687 sc = device_get_softc(dev);
1690 destroy_dev(sc->cdev);
1694 sx_xlock(&t4_list_lock);
1695 SLIST_REMOVE(&t4_list, sc, adapter, link);
1696 sx_xunlock(&t4_list_lock);
1698 sc->flags &= ~CHK_MBOX_ACCESS;
1699 if (sc->flags & FULL_INIT_DONE) {
1700 if (!(sc->flags & IS_VF))
1701 t4_intr_disable(sc);
1704 if (device_is_attached(dev)) {
1705 rc = bus_generic_detach(dev);
1708 "failed to detach child devices: %d\n", rc);
1713 for (i = 0; i < sc->intr_count; i++)
1714 t4_free_irq(sc, &sc->irq[i]);
1716 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1717 t4_free_tx_sched(sc);
1719 for (i = 0; i < MAX_NPORTS; i++) {
1722 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1724 device_delete_child(dev, pi->dev);
1726 mtx_destroy(&pi->pi_lock);
1727 free(pi->vi, M_CXGBE);
1732 device_delete_children(dev);
1733 sysctl_ctx_free(&sc->ctx);
1734 adapter_full_uninit(sc);
1736 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1737 t4_fw_bye(sc, sc->mbox);
1739 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1740 pci_release_msi(dev);
1743 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1747 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1751 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1755 t4_free_l2t(sc->l2t);
1757 t4_free_smt(sc->smt);
1758 t4_free_atid_table(sc);
1760 t4_free_etid_table(sc);
1763 vmem_destroy(sc->key_map);
1765 t4_destroy_clip_table(sc);
1768 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1769 free(sc->sge.ofld_txq, M_CXGBE);
1772 free(sc->sge.ofld_rxq, M_CXGBE);
1775 free(sc->sge.nm_rxq, M_CXGBE);
1776 free(sc->sge.nm_txq, M_CXGBE);
1778 free(sc->irq, M_CXGBE);
1779 free(sc->sge.rxq, M_CXGBE);
1780 free(sc->sge.txq, M_CXGBE);
1781 free(sc->sge.ctrlq, M_CXGBE);
1782 free(sc->sge.iqmap, M_CXGBE);
1783 free(sc->sge.eqmap, M_CXGBE);
1784 free(sc->tids.ftid_tab, M_CXGBE);
1785 free(sc->tids.hpftid_tab, M_CXGBE);
1786 free_hftid_hash(&sc->tids);
1787 free(sc->tids.tid_tab, M_CXGBE);
1788 free(sc->tt.tls_rx_ports, M_CXGBE);
1789 t4_destroy_dma_tag(sc);
1791 callout_drain(&sc->ktls_tick);
1792 callout_drain(&sc->sfl_callout);
1793 if (mtx_initialized(&sc->tids.ftid_lock)) {
1794 mtx_destroy(&sc->tids.ftid_lock);
1795 cv_destroy(&sc->tids.ftid_cv);
1797 if (mtx_initialized(&sc->tids.atid_lock))
1798 mtx_destroy(&sc->tids.atid_lock);
1799 if (mtx_initialized(&sc->ifp_lock))
1800 mtx_destroy(&sc->ifp_lock);
1802 if (rw_initialized(&sc->policy_lock)) {
1803 rw_destroy(&sc->policy_lock);
1805 if (sc->policy != NULL)
1806 free_offload_policy(sc->policy);
1810 for (i = 0; i < NUM_MEMWIN; i++) {
1811 struct memwin *mw = &sc->memwin[i];
1813 if (rw_initialized(&mw->mw_lock))
1814 rw_destroy(&mw->mw_lock);
1817 mtx_destroy(&sc->sfl_lock);
1818 mtx_destroy(&sc->reg_lock);
1819 mtx_destroy(&sc->sc_lock);
1821 bzero(sc, sizeof(*sc));
1827 ok_to_reset(struct adapter *sc)
1829 struct tid_info *t = &sc->tids;
1830 struct port_info *pi;
1833 const int caps = IFCAP_TOE | IFCAP_TXTLS | IFCAP_NETMAP | IFCAP_TXRTLMT;
1835 ASSERT_SYNCHRONIZED_OP(sc);
1836 MPASS(!(sc->flags & IS_VF));
1838 for_each_port(sc, i) {
1840 for_each_vi(pi, j, vi) {
1841 if (vi->ifp->if_capenable & caps)
1846 if (atomic_load_int(&t->tids_in_use) > 0)
1848 if (atomic_load_int(&t->stids_in_use) > 0)
1850 if (atomic_load_int(&t->atids_in_use) > 0)
1852 if (atomic_load_int(&t->ftids_in_use) > 0)
1854 if (atomic_load_int(&t->hpftids_in_use) > 0)
1856 if (atomic_load_int(&t->etids_in_use) > 0)
1863 stop_adapter(struct adapter *sc)
1865 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_STOPPED)))
1866 return (1); /* Already stopped. */
1867 return (t4_shutdown_adapter(sc));
1871 t4_suspend(device_t dev)
1873 struct adapter *sc = device_get_softc(dev);
1874 struct port_info *pi;
1877 struct sge_rxq *rxq;
1878 struct sge_txq *txq;
1879 struct sge_wrq *wrq;
1881 struct sge_ofld_rxq *ofld_rxq;
1883 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1884 struct sge_ofld_txq *ofld_txq;
1888 CH_ALERT(sc, "suspend requested\n");
1890 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4sus");
1894 /* XXX: Can the kernel call suspend repeatedly without resume? */
1895 MPASS(!hw_off_limits(sc));
1897 if (!ok_to_reset(sc)) {
1898 /* XXX: should list what resource is preventing suspend. */
1899 CH_ERR(sc, "not safe to suspend.\n");
1904 /* No more DMA or interrupts. */
1907 /* Quiesce all activity. */
1908 for_each_port(sc, i) {
1910 pi->vxlan_tcam_entry = false;
1913 if (pi->up_vis > 0) {
1915 * t4_shutdown_adapter has already shut down all the
1916 * PHYs but it also disables interrupts and DMA so there
1917 * won't be a link interrupt. So we update the state
1918 * manually and inform the kernel.
1920 pi->link_cfg.link_ok = false;
1921 t4_os_link_changed(pi);
1925 for_each_vi(pi, j, vi) {
1926 vi->xact_addr_filt = -1;
1927 mtx_lock(&vi->tick_mtx);
1928 vi->flags |= VI_SKIP_STATS;
1929 mtx_unlock(&vi->tick_mtx);
1930 if (!(vi->flags & VI_INIT_DONE))
1934 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1935 mtx_lock(&vi->tick_mtx);
1936 callout_stop(&vi->tick);
1937 mtx_unlock(&vi->tick_mtx);
1938 callout_drain(&vi->tick);
1942 * Note that the HW is not available.
1944 for_each_txq(vi, k, txq) {
1946 txq->eq.flags &= ~(EQ_ENABLED | EQ_HW_ALLOCATED);
1949 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1950 for_each_ofld_txq(vi, k, ofld_txq) {
1951 ofld_txq->wrq.eq.flags &= ~EQ_HW_ALLOCATED;
1954 for_each_rxq(vi, k, rxq) {
1955 rxq->iq.flags &= ~IQ_HW_ALLOCATED;
1957 #if defined(TCP_OFFLOAD)
1958 for_each_ofld_rxq(vi, k, ofld_rxq) {
1959 ofld_rxq->iq.flags &= ~IQ_HW_ALLOCATED;
1966 if (sc->flags & FULL_INIT_DONE) {
1968 wrq = &sc->sge.ctrlq[i];
1969 wrq->eq.flags &= ~EQ_HW_ALLOCATED;
1973 if (sc->flags & FULL_INIT_DONE) {
1974 /* Firmware event queue */
1975 sc->sge.fwq.flags &= ~IQ_HW_ALLOCATED;
1976 quiesce_iq_fl(sc, &sc->sge.fwq, NULL);
1979 /* Mark the adapter totally off limits. */
1980 mtx_lock(&sc->reg_lock);
1981 atomic_set_int(&sc->error_flags, HW_OFF_LIMITS);
1982 sc->flags &= ~(FW_OK | MASTER_PF);
1983 sc->reset_thread = NULL;
1984 mtx_unlock(&sc->reg_lock);
1986 CH_ALERT(sc, "suspend completed.\n");
1988 end_synchronized_op(sc, 0);
1992 struct adapter_pre_reset_state {
1996 uint16_t switchcaps;
2000 uint16_t cryptocaps;
2007 struct adapter_params params;
2008 struct t4_virt_res vres;
2009 struct tid_info tids;
2018 save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2021 ASSERT_SYNCHRONIZED_OP(sc);
2023 o->flags = sc->flags;
2025 o->nbmcaps = sc->nbmcaps;
2026 o->linkcaps = sc->linkcaps;
2027 o->switchcaps = sc->switchcaps;
2028 o->niccaps = sc->niccaps;
2029 o->toecaps = sc->toecaps;
2030 o->rdmacaps = sc->rdmacaps;
2031 o->cryptocaps = sc->cryptocaps;
2032 o->iscsicaps = sc->iscsicaps;
2033 o->fcoecaps = sc->fcoecaps;
2035 o->cfcsum = sc->cfcsum;
2036 MPASS(sizeof(o->cfg_file) == sizeof(sc->cfg_file));
2037 memcpy(o->cfg_file, sc->cfg_file, sizeof(o->cfg_file));
2039 o->params = sc->params;
2044 o->rawf_base = sc->rawf_base;
2045 o->nrawf = sc->nrawf;
2049 compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
2053 ASSERT_SYNCHRONIZED_OP(sc);
2056 #define COMPARE_CAPS(c) do { \
2057 if (o->c##caps != sc->c##caps) { \
2058 CH_ERR(sc, "%scaps 0x%04x -> 0x%04x.\n", #c, o->c##caps, \
2065 COMPARE_CAPS(switch);
2069 COMPARE_CAPS(crypto);
2070 COMPARE_CAPS(iscsi);
2074 /* Firmware config file */
2075 if (o->cfcsum != sc->cfcsum) {
2076 CH_ERR(sc, "config file %s (0x%x) -> %s (0x%x)\n", o->cfg_file,
2077 o->cfcsum, sc->cfg_file, sc->cfcsum);
2081 #define COMPARE_PARAM(p, name) do { \
2082 if (o->p != sc->p) { \
2083 CH_ERR(sc, #name " %d -> %d\n", o->p, sc->p); \
2087 COMPARE_PARAM(sge.iq_start, iq_start);
2088 COMPARE_PARAM(sge.eq_start, eq_start);
2089 COMPARE_PARAM(tids.ftid_base, ftid_base);
2090 COMPARE_PARAM(tids.ftid_end, ftid_end);
2091 COMPARE_PARAM(tids.nftids, nftids);
2092 COMPARE_PARAM(vres.l2t.start, l2t_start);
2093 COMPARE_PARAM(vres.l2t.size, l2t_size);
2094 COMPARE_PARAM(sge.iqmap_sz, iqmap_sz);
2095 COMPARE_PARAM(sge.eqmap_sz, eqmap_sz);
2096 COMPARE_PARAM(tids.tid_base, tid_base);
2097 COMPARE_PARAM(tids.hpftid_base, hpftid_base);
2098 COMPARE_PARAM(tids.hpftid_end, hpftid_end);
2099 COMPARE_PARAM(tids.nhpftids, nhpftids);
2100 COMPARE_PARAM(rawf_base, rawf_base);
2101 COMPARE_PARAM(nrawf, nrawf);
2102 COMPARE_PARAM(params.mps_bg_map, mps_bg_map);
2103 COMPARE_PARAM(params.filter2_wr_support, filter2_wr_support);
2104 COMPARE_PARAM(params.ulptx_memwrite_dsgl, ulptx_memwrite_dsgl);
2105 COMPARE_PARAM(params.fr_nsmr_tpte_wr_support, fr_nsmr_tpte_wr_support);
2106 COMPARE_PARAM(params.max_pkts_per_eth_tx_pkts_wr, max_pkts_per_eth_tx_pkts_wr);
2107 COMPARE_PARAM(tids.ntids, ntids);
2108 COMPARE_PARAM(tids.etid_base, etid_base);
2109 COMPARE_PARAM(tids.etid_end, etid_end);
2110 COMPARE_PARAM(tids.netids, netids);
2111 COMPARE_PARAM(params.eo_wr_cred, eo_wr_cred);
2112 COMPARE_PARAM(params.ethoffload, ethoffload);
2113 COMPARE_PARAM(tids.natids, natids);
2114 COMPARE_PARAM(tids.stid_base, stid_base);
2115 COMPARE_PARAM(vres.ddp.start, ddp_start);
2116 COMPARE_PARAM(vres.ddp.size, ddp_size);
2117 COMPARE_PARAM(params.ofldq_wr_cred, ofldq_wr_cred);
2118 COMPARE_PARAM(vres.stag.start, stag_start);
2119 COMPARE_PARAM(vres.stag.size, stag_size);
2120 COMPARE_PARAM(vres.rq.start, rq_start);
2121 COMPARE_PARAM(vres.rq.size, rq_size);
2122 COMPARE_PARAM(vres.pbl.start, pbl_start);
2123 COMPARE_PARAM(vres.pbl.size, pbl_size);
2124 COMPARE_PARAM(vres.qp.start, qp_start);
2125 COMPARE_PARAM(vres.qp.size, qp_size);
2126 COMPARE_PARAM(vres.cq.start, cq_start);
2127 COMPARE_PARAM(vres.cq.size, cq_size);
2128 COMPARE_PARAM(vres.ocq.start, ocq_start);
2129 COMPARE_PARAM(vres.ocq.size, ocq_size);
2130 COMPARE_PARAM(vres.srq.start, srq_start);
2131 COMPARE_PARAM(vres.srq.size, srq_size);
2132 COMPARE_PARAM(params.max_ordird_qp, max_ordird_qp);
2133 COMPARE_PARAM(params.max_ird_adapter, max_ird_adapter);
2134 COMPARE_PARAM(vres.iscsi.start, iscsi_start);
2135 COMPARE_PARAM(vres.iscsi.size, iscsi_size);
2136 COMPARE_PARAM(vres.key.start, key_start);
2137 COMPARE_PARAM(vres.key.size, key_size);
2138 #undef COMPARE_PARAM
2144 t4_resume(device_t dev)
2146 struct adapter *sc = device_get_softc(dev);
2147 struct adapter_pre_reset_state *old_state = NULL;
2148 struct port_info *pi;
2151 struct sge_txq *txq;
2154 CH_ALERT(sc, "resume requested.\n");
2156 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4res");
2159 MPASS(hw_off_limits(sc));
2160 MPASS((sc->flags & FW_OK) == 0);
2161 MPASS((sc->flags & MASTER_PF) == 0);
2162 MPASS(sc->reset_thread == NULL);
2163 sc->reset_thread = curthread;
2165 /* Register access is expected to work by the time we're here. */
2166 if (t4_read_reg(sc, A_PL_WHOAMI) == 0xffffffff) {
2167 CH_ERR(sc, "%s: can't read device registers\n", __func__);
2172 /* Note that HW_OFF_LIMITS is cleared a bit later. */
2173 atomic_clear_int(&sc->error_flags, ADAP_FATAL_ERR | ADAP_STOPPED);
2175 /* Restore memory window. */
2178 /* Go no further if recovery mode has been requested. */
2179 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
2180 CH_ALERT(sc, "recovery mode on resume.\n");
2182 mtx_lock(&sc->reg_lock);
2183 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2184 mtx_unlock(&sc->reg_lock);
2188 old_state = malloc(sizeof(*old_state), M_CXGBE, M_ZERO | M_WAITOK);
2189 save_caps_and_params(sc, old_state);
2191 /* Reestablish contact with firmware and become the primary PF. */
2192 rc = contact_firmware(sc);
2194 goto done; /* error message displayed already */
2195 MPASS(sc->flags & FW_OK);
2197 if (sc->flags & MASTER_PF) {
2198 rc = partition_resources(sc);
2200 goto done; /* error message displayed already */
2204 rc = get_params__post_init(sc);
2206 goto done; /* error message displayed already */
2208 rc = set_params__post_init(sc);
2210 goto done; /* error message displayed already */
2212 rc = compare_caps_and_params(sc, old_state);
2214 goto done; /* error message displayed already */
2216 for_each_port(sc, i) {
2219 MPASS(pi->vi != NULL);
2220 MPASS(pi->vi[0].dev == pi->dev);
2222 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
2225 "failed to re-initialize port %d: %d\n", i, rc);
2228 MPASS(sc->chan_map[pi->tx_chan] == i);
2231 fixup_link_config(pi);
2232 build_medialist(pi);
2234 for_each_vi(pi, j, vi) {
2237 rc = alloc_extra_vi(sc, pi, vi);
2240 "failed to re-allocate extra VI: %d\n", rc);
2247 * Interrupts and queues are about to be enabled and other threads will
2248 * want to access the hardware too. It is safe to do so. Note that
2249 * this thread is still in the middle of a synchronized_op.
2251 mtx_lock(&sc->reg_lock);
2252 atomic_clear_int(&sc->error_flags, HW_OFF_LIMITS);
2253 mtx_unlock(&sc->reg_lock);
2255 if (sc->flags & FULL_INIT_DONE) {
2256 rc = adapter_full_init(sc);
2258 CH_ERR(sc, "failed to re-initialize adapter: %d\n", rc);
2262 if (sc->vxlan_refcount > 0)
2263 enable_vxlan_rx(sc);
2265 for_each_port(sc, i) {
2267 for_each_vi(pi, j, vi) {
2268 mtx_lock(&vi->tick_mtx);
2269 vi->flags &= ~VI_SKIP_STATS;
2270 mtx_unlock(&vi->tick_mtx);
2271 if (!(vi->flags & VI_INIT_DONE))
2273 rc = vi_full_init(vi);
2275 CH_ERR(vi, "failed to re-initialize "
2276 "interface: %d\n", rc);
2281 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2284 * Note that we do not setup multicast addresses
2285 * in the first pass. This ensures that the
2286 * unicast DMACs for all VIs on all ports get an
2289 rc = update_mac_settings(ifp, XGMAC_ALL &
2292 CH_ERR(vi, "failed to re-configure MAC: %d\n", rc);
2295 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true,
2298 CH_ERR(vi, "failed to re-enable VI: %d\n", rc);
2301 for_each_txq(vi, k, txq) {
2303 txq->eq.flags |= EQ_ENABLED;
2306 mtx_lock(&vi->tick_mtx);
2307 callout_schedule(&vi->tick, hz);
2308 mtx_unlock(&vi->tick_mtx);
2311 if (pi->up_vis > 0) {
2312 t4_update_port_info(pi);
2313 fixup_link_config(pi);
2314 build_medialist(pi);
2315 apply_link_config(pi);
2316 if (pi->link_cfg.link_ok)
2317 t4_os_link_changed(pi);
2322 /* Now reprogram the L2 multicast addresses. */
2323 for_each_port(sc, i) {
2325 for_each_vi(pi, j, vi) {
2326 if (!(vi->flags & VI_INIT_DONE))
2329 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2331 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2333 CH_ERR(vi, "failed to re-configure MCAST MACs: %d\n", rc);
2334 rc = 0; /* carry on */
2342 CH_ALERT(sc, "resume completed.\n");
2344 end_synchronized_op(sc, 0);
2345 free(old_state, M_CXGBE);
2350 t4_reset_prepare(device_t dev, device_t child)
2352 struct adapter *sc = device_get_softc(dev);
2354 CH_ALERT(sc, "reset_prepare.\n");
2359 t4_reset_post(device_t dev, device_t child)
2361 struct adapter *sc = device_get_softc(dev);
2363 CH_ALERT(sc, "reset_post.\n");
2368 reset_adapter(struct adapter *sc)
2370 int rc, oldinc, error_flags;
2372 CH_ALERT(sc, "reset requested.\n");
2374 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst1");
2378 if (hw_off_limits(sc)) {
2379 CH_ERR(sc, "adapter is suspended, use resume (not reset).\n");
2384 if (!ok_to_reset(sc)) {
2385 /* XXX: should list what resource is preventing reset. */
2386 CH_ERR(sc, "not safe to reset.\n");
2392 oldinc = sc->incarnation;
2393 end_synchronized_op(sc, 0);
2395 return (rc); /* Error logged already. */
2397 atomic_add_int(&sc->num_resets, 1);
2399 rc = BUS_RESET_CHILD(device_get_parent(sc->dev), sc->dev, 0);
2402 CH_ERR(sc, "bus_reset_child failed: %d.\n", rc);
2404 rc = begin_synchronized_op(sc, NULL, SLEEP_OK, "t4rst2");
2407 error_flags = atomic_load_int(&sc->error_flags);
2408 if (sc->incarnation > oldinc && error_flags == 0) {
2409 CH_ALERT(sc, "bus_reset_child succeeded.\n");
2411 CH_ERR(sc, "adapter did not reset properly, flags "
2412 "0x%08x, error_flags 0x%08x.\n", sc->flags,
2416 end_synchronized_op(sc, 0);
2423 reset_adapter_task(void *arg, int pending)
2425 /* XXX: t4_async_event here? */
2430 cxgbe_probe(device_t dev)
2433 struct port_info *pi = device_get_softc(dev);
2435 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
2436 device_set_desc_copy(dev, buf);
2438 return (BUS_PROBE_DEFAULT);
2441 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
2442 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
2443 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
2444 IFCAP_HWRXTSTMP | IFCAP_MEXTPG)
2445 #define T4_CAP_ENABLE (T4_CAP)
2448 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
2452 struct sysctl_ctx_list *ctx = &vi->ctx;
2453 struct sysctl_oid_list *children;
2454 struct pfil_head_args pa;
2455 struct adapter *sc = vi->adapter;
2457 sysctl_ctx_init(ctx);
2458 children = SYSCTL_CHILDREN(device_get_sysctl_tree(vi->dev));
2459 vi->rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rxq",
2460 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC rx queues");
2461 vi->txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "txq",
2462 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NIC tx queues");
2464 vi->nm_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_rxq",
2465 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap rx queues");
2466 vi->nm_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "nm_txq",
2467 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queues");
2470 vi->ofld_rxq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_rxq",
2471 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE rx queues");
2473 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2474 vi->ofld_txq_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "ofld_txq",
2475 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE/ETHOFLD tx queues");
2478 vi->xact_addr_filt = -1;
2479 mtx_init(&vi->tick_mtx, "vi tick", NULL, MTX_DEF);
2480 callout_init_mtx(&vi->tick, &vi->tick_mtx, 0);
2481 if (sc->flags & IS_VF || t4_tx_vm_wr != 0)
2482 vi->flags |= TX_USES_VM_WR;
2484 /* Allocate an ifnet and set it up */
2485 ifp = if_alloc_dev(IFT_ETHER, dev);
2487 device_printf(dev, "Cannot allocate ifnet\n");
2493 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2494 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2496 ifp->if_init = cxgbe_init;
2497 ifp->if_ioctl = cxgbe_ioctl;
2498 ifp->if_transmit = cxgbe_transmit;
2499 ifp->if_qflush = cxgbe_qflush;
2500 if (vi->pi->nvi > 1 || sc->flags & IS_VF)
2501 ifp->if_get_counter = vi_get_counter;
2503 ifp->if_get_counter = cxgbe_get_counter;
2504 #if defined(KERN_TLS) || defined(RATELIMIT)
2505 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
2508 ifp->if_ratelimit_query = cxgbe_ratelimit_query;
2511 ifp->if_capabilities = T4_CAP;
2512 ifp->if_capenable = T4_CAP_ENABLE;
2513 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
2514 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
2515 if (chip_id(sc) >= CHELSIO_T6) {
2516 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO;
2517 ifp->if_capenable |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO;
2518 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
2519 CSUM_INNER_IP6_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2520 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_ENCAP_VXLAN;
2524 if (vi->nofldrxq != 0)
2525 ifp->if_capabilities |= IFCAP_TOE;
2528 if (is_ethoffload(sc) && vi->nofldtxq != 0) {
2529 ifp->if_capabilities |= IFCAP_TXRTLMT;
2530 ifp->if_capenable |= IFCAP_TXRTLMT;
2534 ifp->if_hw_tsomax = IP_MAXPACKET;
2535 if (vi->flags & TX_USES_VM_WR)
2536 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO;
2538 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
2540 if (is_ethoffload(sc) && vi->nofldtxq != 0)
2541 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
2543 ifp->if_hw_tsomaxsegsize = 65536;
2546 ifp->if_capabilities |= IFCAP_TXTLS;
2547 if (sc->flags & KERN_TLS_ON)
2548 ifp->if_capenable |= IFCAP_TXTLS;
2552 ether_ifattach(ifp, vi->hw_addr);
2554 if (vi->nnmrxq != 0)
2555 cxgbe_nm_attach(vi);
2557 sb = sbuf_new_auto();
2558 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
2559 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
2560 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
2562 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
2564 case IFCAP_TOE | IFCAP_TXRTLMT:
2565 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
2568 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
2573 if (ifp->if_capabilities & IFCAP_TOE)
2574 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
2577 if (ifp->if_capabilities & IFCAP_NETMAP)
2578 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
2579 vi->nnmtxq, vi->nnmrxq);
2582 device_printf(dev, "%s\n", sbuf_data(sb));
2587 pa.pa_version = PFIL_VERSION;
2588 pa.pa_flags = PFIL_IN;
2589 pa.pa_type = PFIL_TYPE_ETHERNET;
2590 pa.pa_headname = ifp->if_xname;
2591 vi->pfil = pfil_head_register(&pa);
2597 cxgbe_attach(device_t dev)
2599 struct port_info *pi = device_get_softc(dev);
2600 struct adapter *sc = pi->adapter;
2604 sysctl_ctx_init(&pi->ctx);
2606 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
2610 for_each_vi(pi, i, vi) {
2613 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
2614 if (vi->dev == NULL) {
2615 device_printf(dev, "failed to add VI %d\n", i);
2618 device_set_softc(vi->dev, vi);
2623 bus_generic_attach(dev);
2629 cxgbe_vi_detach(struct vi_info *vi)
2631 struct ifnet *ifp = vi->ifp;
2633 if (vi->pfil != NULL) {
2634 pfil_head_unregister(vi->pfil);
2638 ether_ifdetach(ifp);
2640 /* Let detach proceed even if these fail. */
2642 if (ifp->if_capabilities & IFCAP_NETMAP)
2643 cxgbe_nm_detach(vi);
2645 cxgbe_uninit_synchronized(vi);
2646 callout_drain(&vi->tick);
2647 sysctl_ctx_free(&vi->ctx);
2655 cxgbe_detach(device_t dev)
2657 struct port_info *pi = device_get_softc(dev);
2658 struct adapter *sc = pi->adapter;
2661 /* Detach the extra VIs first. */
2662 rc = bus_generic_detach(dev);
2665 device_delete_children(dev);
2667 sysctl_ctx_free(&pi->ctx);
2668 doom_vi(sc, &pi->vi[0]);
2670 if (pi->flags & HAS_TRACEQ) {
2671 sc->traceq = -1; /* cloner should not create ifnet */
2672 t4_tracer_port_detach(sc);
2675 cxgbe_vi_detach(&pi->vi[0]);
2676 ifmedia_removeall(&pi->media);
2678 end_synchronized_op(sc, 0);
2684 cxgbe_init(void *arg)
2686 struct vi_info *vi = arg;
2687 struct adapter *sc = vi->adapter;
2689 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
2691 cxgbe_init_synchronized(vi);
2692 end_synchronized_op(sc, 0);
2696 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
2698 int rc = 0, mtu, flags;
2699 struct vi_info *vi = ifp->if_softc;
2700 struct port_info *pi = vi->pi;
2701 struct adapter *sc = pi->adapter;
2702 struct ifreq *ifr = (struct ifreq *)data;
2708 if (mtu < ETHERMIN || mtu > MAX_MTU)
2711 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
2715 if (vi->flags & VI_INIT_DONE) {
2716 t4_update_fl_bufsize(ifp);
2717 if (!hw_off_limits(sc) &&
2718 ifp->if_drv_flags & IFF_DRV_RUNNING)
2719 rc = update_mac_settings(ifp, XGMAC_MTU);
2721 end_synchronized_op(sc, 0);
2725 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
2729 if (hw_off_limits(sc)) {
2734 if (ifp->if_flags & IFF_UP) {
2735 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2736 flags = vi->if_flags;
2737 if ((ifp->if_flags ^ flags) &
2738 (IFF_PROMISC | IFF_ALLMULTI)) {
2739 rc = update_mac_settings(ifp,
2740 XGMAC_PROMISC | XGMAC_ALLMULTI);
2743 rc = cxgbe_init_synchronized(vi);
2745 vi->if_flags = ifp->if_flags;
2746 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2747 rc = cxgbe_uninit_synchronized(vi);
2749 end_synchronized_op(sc, 0);
2754 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
2757 if (!hw_off_limits(sc) && ifp->if_drv_flags & IFF_DRV_RUNNING)
2758 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
2759 end_synchronized_op(sc, 0);
2763 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
2767 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2768 if (mask & IFCAP_TXCSUM) {
2769 ifp->if_capenable ^= IFCAP_TXCSUM;
2770 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2772 if (IFCAP_TSO4 & ifp->if_capenable &&
2773 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2774 mask &= ~IFCAP_TSO4;
2775 ifp->if_capenable &= ~IFCAP_TSO4;
2777 "tso4 disabled due to -txcsum.\n");
2780 if (mask & IFCAP_TXCSUM_IPV6) {
2781 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2782 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2784 if (IFCAP_TSO6 & ifp->if_capenable &&
2785 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2786 mask &= ~IFCAP_TSO6;
2787 ifp->if_capenable &= ~IFCAP_TSO6;
2789 "tso6 disabled due to -txcsum6.\n");
2792 if (mask & IFCAP_RXCSUM)
2793 ifp->if_capenable ^= IFCAP_RXCSUM;
2794 if (mask & IFCAP_RXCSUM_IPV6)
2795 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2798 * Note that we leave CSUM_TSO alone (it is always set). The
2799 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
2800 * sending a TSO request our way, so it's sufficient to toggle
2803 if (mask & IFCAP_TSO4) {
2804 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2805 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2806 if_printf(ifp, "enable txcsum first.\n");
2810 ifp->if_capenable ^= IFCAP_TSO4;
2812 if (mask & IFCAP_TSO6) {
2813 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2814 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2815 if_printf(ifp, "enable txcsum6 first.\n");
2819 ifp->if_capenable ^= IFCAP_TSO6;
2821 if (mask & IFCAP_LRO) {
2822 #if defined(INET) || defined(INET6)
2824 struct sge_rxq *rxq;
2826 ifp->if_capenable ^= IFCAP_LRO;
2827 for_each_rxq(vi, i, rxq) {
2828 if (ifp->if_capenable & IFCAP_LRO)
2829 rxq->iq.flags |= IQ_LRO_ENABLED;
2831 rxq->iq.flags &= ~IQ_LRO_ENABLED;
2836 if (mask & IFCAP_TOE) {
2837 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
2839 rc = toe_capability(vi, enable);
2843 ifp->if_capenable ^= mask;
2846 if (mask & IFCAP_VLAN_HWTAGGING) {
2847 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2848 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2849 rc = update_mac_settings(ifp, XGMAC_VLANEX);
2851 if (mask & IFCAP_VLAN_MTU) {
2852 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2854 /* Need to find out how to disable auto-mtu-inflation */
2856 if (mask & IFCAP_VLAN_HWTSO)
2857 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2858 if (mask & IFCAP_VLAN_HWCSUM)
2859 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2861 if (mask & IFCAP_TXRTLMT)
2862 ifp->if_capenable ^= IFCAP_TXRTLMT;
2864 if (mask & IFCAP_HWRXTSTMP) {
2866 struct sge_rxq *rxq;
2868 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2869 for_each_rxq(vi, i, rxq) {
2870 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
2871 rxq->iq.flags |= IQ_RX_TIMESTAMP;
2873 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
2876 if (mask & IFCAP_MEXTPG)
2877 ifp->if_capenable ^= IFCAP_MEXTPG;
2880 if (mask & IFCAP_TXTLS) {
2881 int enable = (ifp->if_capenable ^ mask) & IFCAP_TXTLS;
2883 rc = ktls_capability(sc, enable);
2887 ifp->if_capenable ^= (mask & IFCAP_TXTLS);
2890 if (mask & IFCAP_VXLAN_HWCSUM) {
2891 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM;
2892 ifp->if_hwassist ^= CSUM_INNER_IP6_UDP |
2893 CSUM_INNER_IP6_TCP | CSUM_INNER_IP |
2894 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP;
2896 if (mask & IFCAP_VXLAN_HWTSO) {
2897 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO;
2898 ifp->if_hwassist ^= CSUM_INNER_IP6_TSO |
2902 #ifdef VLAN_CAPABILITIES
2903 VLAN_CAPABILITIES(ifp);
2906 end_synchronized_op(sc, 0);
2912 rc = ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
2916 struct ifi2creq i2c;
2918 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2921 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2925 if (i2c.len > sizeof(i2c.data)) {
2929 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2932 if (hw_off_limits(sc))
2935 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2936 i2c.offset, i2c.len, &i2c.data[0]);
2937 end_synchronized_op(sc, 0);
2939 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2944 rc = ether_ioctl(ifp, cmd, data);
2951 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2953 struct vi_info *vi = ifp->if_softc;
2954 struct port_info *pi = vi->pi;
2956 struct sge_txq *txq;
2961 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2962 #if defined(KERN_TLS) || defined(RATELIMIT)
2963 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
2964 MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
2967 if (__predict_false(pi->link_cfg.link_ok == false)) {
2972 rc = parse_pkt(&m, vi->flags & TX_USES_VM_WR);
2973 if (__predict_false(rc != 0)) {
2974 MPASS(m == NULL); /* was freed already */
2975 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2979 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) {
2980 if (m->m_pkthdr.snd_tag->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT)
2981 return (ethofld_transmit(ifp, m));
2987 txq = &sc->sge.txq[vi->first_txq];
2988 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2989 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2993 rc = mp_ring_enqueue(txq->r, items, 1, 256);
2994 if (__predict_false(rc != 0))
3001 cxgbe_qflush(struct ifnet *ifp)
3003 struct vi_info *vi = ifp->if_softc;
3004 struct sge_txq *txq;
3007 /* queues do not exist if !VI_INIT_DONE. */
3008 if (vi->flags & VI_INIT_DONE) {
3009 for_each_txq(vi, i, txq) {
3011 txq->eq.flags |= EQ_QFLUSH;
3013 while (!mp_ring_is_idle(txq->r)) {
3014 mp_ring_check_drainage(txq->r, 4096);
3018 txq->eq.flags &= ~EQ_QFLUSH;
3026 vi_get_counter(struct ifnet *ifp, ift_counter c)
3028 struct vi_info *vi = ifp->if_softc;
3029 struct fw_vi_stats_vf *s = &vi->stats;
3031 mtx_lock(&vi->tick_mtx);
3032 vi_refresh_stats(vi);
3033 mtx_unlock(&vi->tick_mtx);
3036 case IFCOUNTER_IPACKETS:
3037 return (s->rx_bcast_frames + s->rx_mcast_frames +
3038 s->rx_ucast_frames);
3039 case IFCOUNTER_IERRORS:
3040 return (s->rx_err_frames);
3041 case IFCOUNTER_OPACKETS:
3042 return (s->tx_bcast_frames + s->tx_mcast_frames +
3043 s->tx_ucast_frames + s->tx_offload_frames);
3044 case IFCOUNTER_OERRORS:
3045 return (s->tx_drop_frames);
3046 case IFCOUNTER_IBYTES:
3047 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
3049 case IFCOUNTER_OBYTES:
3050 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
3051 s->tx_ucast_bytes + s->tx_offload_bytes);
3052 case IFCOUNTER_IMCASTS:
3053 return (s->rx_mcast_frames);
3054 case IFCOUNTER_OMCASTS:
3055 return (s->tx_mcast_frames);
3056 case IFCOUNTER_OQDROPS: {
3060 if (vi->flags & VI_INIT_DONE) {
3062 struct sge_txq *txq;
3064 for_each_txq(vi, i, txq)
3065 drops += counter_u64_fetch(txq->r->dropped);
3073 return (if_get_counter_default(ifp, c));
3078 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
3080 struct vi_info *vi = ifp->if_softc;
3081 struct port_info *pi = vi->pi;
3082 struct port_stats *s = &pi->stats;
3084 mtx_lock(&vi->tick_mtx);
3085 cxgbe_refresh_stats(vi);
3086 mtx_unlock(&vi->tick_mtx);
3089 case IFCOUNTER_IPACKETS:
3090 return (s->rx_frames);
3092 case IFCOUNTER_IERRORS:
3093 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
3094 s->rx_fcs_err + s->rx_len_err);
3096 case IFCOUNTER_OPACKETS:
3097 return (s->tx_frames);
3099 case IFCOUNTER_OERRORS:
3100 return (s->tx_error_frames);
3102 case IFCOUNTER_IBYTES:
3103 return (s->rx_octets);
3105 case IFCOUNTER_OBYTES:
3106 return (s->tx_octets);
3108 case IFCOUNTER_IMCASTS:
3109 return (s->rx_mcast_frames);
3111 case IFCOUNTER_OMCASTS:
3112 return (s->tx_mcast_frames);
3114 case IFCOUNTER_IQDROPS:
3115 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
3116 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
3117 s->rx_trunc3 + pi->tnl_cong_drops);
3119 case IFCOUNTER_OQDROPS: {
3123 if (vi->flags & VI_INIT_DONE) {
3125 struct sge_txq *txq;
3127 for_each_txq(vi, i, txq)
3128 drops += counter_u64_fetch(txq->r->dropped);
3136 return (if_get_counter_default(ifp, c));
3140 #if defined(KERN_TLS) || defined(RATELIMIT)
3142 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
3143 struct m_snd_tag **pt)
3147 switch (params->hdr.type) {
3149 case IF_SND_TAG_TYPE_RATE_LIMIT:
3150 error = cxgbe_rate_tag_alloc(ifp, params, pt);
3154 case IF_SND_TAG_TYPE_TLS:
3155 error = cxgbe_tls_tag_alloc(ifp, params, pt);
3166 * The kernel picks a media from the list we had provided but we still validate
3170 cxgbe_media_change(struct ifnet *ifp)
3172 struct vi_info *vi = ifp->if_softc;
3173 struct port_info *pi = vi->pi;
3174 struct ifmedia *ifm = &pi->media;
3175 struct link_config *lc = &pi->link_cfg;
3176 struct adapter *sc = pi->adapter;
3179 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
3183 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
3184 /* ifconfig .. media autoselect */
3185 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
3186 rc = ENOTSUP; /* AN not supported by transceiver */
3189 lc->requested_aneg = AUTONEG_ENABLE;
3190 lc->requested_speed = 0;
3191 lc->requested_fc |= PAUSE_AUTONEG;
3193 lc->requested_aneg = AUTONEG_DISABLE;
3194 lc->requested_speed =
3195 ifmedia_baudrate(ifm->ifm_media) / 1000000;
3196 lc->requested_fc = 0;
3197 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
3198 lc->requested_fc |= PAUSE_RX;
3199 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
3200 lc->requested_fc |= PAUSE_TX;
3202 if (pi->up_vis > 0 && !hw_off_limits(sc)) {
3203 fixup_link_config(pi);
3204 rc = apply_link_config(pi);
3208 end_synchronized_op(sc, 0);
3213 * Base media word (without ETHER, pause, link active, etc.) for the port at the
3217 port_mword(struct port_info *pi, uint32_t speed)
3220 MPASS(speed & M_FW_PORT_CAP32_SPEED);
3221 MPASS(powerof2(speed));
3223 switch(pi->port_type) {
3224 case FW_PORT_TYPE_BT_SGMII:
3225 case FW_PORT_TYPE_BT_XFI:
3226 case FW_PORT_TYPE_BT_XAUI:
3229 case FW_PORT_CAP32_SPEED_100M:
3231 case FW_PORT_CAP32_SPEED_1G:
3232 return (IFM_1000_T);
3233 case FW_PORT_CAP32_SPEED_10G:
3237 case FW_PORT_TYPE_KX4:
3238 if (speed == FW_PORT_CAP32_SPEED_10G)
3239 return (IFM_10G_KX4);
3241 case FW_PORT_TYPE_CX4:
3242 if (speed == FW_PORT_CAP32_SPEED_10G)
3243 return (IFM_10G_CX4);
3245 case FW_PORT_TYPE_KX:
3246 if (speed == FW_PORT_CAP32_SPEED_1G)
3247 return (IFM_1000_KX);
3249 case FW_PORT_TYPE_KR:
3250 case FW_PORT_TYPE_BP_AP:
3251 case FW_PORT_TYPE_BP4_AP:
3252 case FW_PORT_TYPE_BP40_BA:
3253 case FW_PORT_TYPE_KR4_100G:
3254 case FW_PORT_TYPE_KR_SFP28:
3255 case FW_PORT_TYPE_KR_XLAUI:
3257 case FW_PORT_CAP32_SPEED_1G:
3258 return (IFM_1000_KX);
3259 case FW_PORT_CAP32_SPEED_10G:
3260 return (IFM_10G_KR);
3261 case FW_PORT_CAP32_SPEED_25G:
3262 return (IFM_25G_KR);
3263 case FW_PORT_CAP32_SPEED_40G:
3264 return (IFM_40G_KR4);
3265 case FW_PORT_CAP32_SPEED_50G:
3266 return (IFM_50G_KR2);
3267 case FW_PORT_CAP32_SPEED_100G:
3268 return (IFM_100G_KR4);
3271 case FW_PORT_TYPE_FIBER_XFI:
3272 case FW_PORT_TYPE_FIBER_XAUI:
3273 case FW_PORT_TYPE_SFP:
3274 case FW_PORT_TYPE_QSFP_10G:
3275 case FW_PORT_TYPE_QSA:
3276 case FW_PORT_TYPE_QSFP:
3277 case FW_PORT_TYPE_CR4_QSFP:
3278 case FW_PORT_TYPE_CR_QSFP:
3279 case FW_PORT_TYPE_CR2_QSFP:
3280 case FW_PORT_TYPE_SFP28:
3281 /* Pluggable transceiver */
3282 switch (pi->mod_type) {
3283 case FW_PORT_MOD_TYPE_LR:
3285 case FW_PORT_CAP32_SPEED_1G:
3286 return (IFM_1000_LX);
3287 case FW_PORT_CAP32_SPEED_10G:
3288 return (IFM_10G_LR);
3289 case FW_PORT_CAP32_SPEED_25G:
3290 return (IFM_25G_LR);
3291 case FW_PORT_CAP32_SPEED_40G:
3292 return (IFM_40G_LR4);
3293 case FW_PORT_CAP32_SPEED_50G:
3294 return (IFM_50G_LR2);
3295 case FW_PORT_CAP32_SPEED_100G:
3296 return (IFM_100G_LR4);
3299 case FW_PORT_MOD_TYPE_SR:
3301 case FW_PORT_CAP32_SPEED_1G:
3302 return (IFM_1000_SX);
3303 case FW_PORT_CAP32_SPEED_10G:
3304 return (IFM_10G_SR);
3305 case FW_PORT_CAP32_SPEED_25G:
3306 return (IFM_25G_SR);
3307 case FW_PORT_CAP32_SPEED_40G:
3308 return (IFM_40G_SR4);
3309 case FW_PORT_CAP32_SPEED_50G:
3310 return (IFM_50G_SR2);
3311 case FW_PORT_CAP32_SPEED_100G:
3312 return (IFM_100G_SR4);
3315 case FW_PORT_MOD_TYPE_ER:
3316 if (speed == FW_PORT_CAP32_SPEED_10G)
3317 return (IFM_10G_ER);
3319 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3320 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3322 case FW_PORT_CAP32_SPEED_1G:
3323 return (IFM_1000_CX);
3324 case FW_PORT_CAP32_SPEED_10G:
3325 return (IFM_10G_TWINAX);
3326 case FW_PORT_CAP32_SPEED_25G:
3327 return (IFM_25G_CR);
3328 case FW_PORT_CAP32_SPEED_40G:
3329 return (IFM_40G_CR4);
3330 case FW_PORT_CAP32_SPEED_50G:
3331 return (IFM_50G_CR2);
3332 case FW_PORT_CAP32_SPEED_100G:
3333 return (IFM_100G_CR4);
3336 case FW_PORT_MOD_TYPE_LRM:
3337 if (speed == FW_PORT_CAP32_SPEED_10G)
3338 return (IFM_10G_LRM);
3340 case FW_PORT_MOD_TYPE_NA:
3341 MPASS(0); /* Not pluggable? */
3343 case FW_PORT_MOD_TYPE_ERROR:
3344 case FW_PORT_MOD_TYPE_UNKNOWN:
3345 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
3347 case FW_PORT_MOD_TYPE_NONE:
3351 case FW_PORT_TYPE_NONE:
3355 return (IFM_UNKNOWN);
3359 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
3361 struct vi_info *vi = ifp->if_softc;
3362 struct port_info *pi = vi->pi;
3363 struct adapter *sc = pi->adapter;
3364 struct link_config *lc = &pi->link_cfg;
3366 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
3370 if (pi->up_vis == 0 && !hw_off_limits(sc)) {
3372 * If all the interfaces are administratively down the firmware
3373 * does not report transceiver changes. Refresh port info here
3374 * so that ifconfig displays accurate ifmedia at all times.
3375 * This is the only reason we have a synchronized op in this
3376 * function. Just PORT_LOCK would have been enough otherwise.
3378 t4_update_port_info(pi);
3379 build_medialist(pi);
3383 ifmr->ifm_status = IFM_AVALID;
3384 if (lc->link_ok == false)
3386 ifmr->ifm_status |= IFM_ACTIVE;
3389 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3390 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
3391 if (lc->fc & PAUSE_RX)
3392 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3393 if (lc->fc & PAUSE_TX)
3394 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3395 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
3398 end_synchronized_op(sc, 0);
3402 vcxgbe_probe(device_t dev)
3405 struct vi_info *vi = device_get_softc(dev);
3407 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
3409 device_set_desc_copy(dev, buf);
3411 return (BUS_PROBE_DEFAULT);
3415 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
3417 int func, index, rc;
3418 uint32_t param, val;
3420 ASSERT_SYNCHRONIZED_OP(sc);
3422 index = vi - pi->vi;
3423 MPASS(index > 0); /* This function deals with _extra_ VIs only */
3424 KASSERT(index < nitems(vi_mac_funcs),
3425 ("%s: VI %s doesn't have a MAC func", __func__,
3426 device_get_nameunit(vi->dev)));
3427 func = vi_mac_funcs[index];
3428 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
3429 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
3431 CH_ERR(vi, "failed to allocate virtual interface %d"
3432 "for port %d: %d\n", index, pi->port_id, -rc);
3437 if (vi->rss_size == 1) {
3439 * This VI didn't get a slice of the RSS table. Reduce the
3440 * number of VIs being created (hw.cxgbe.num_vis) or modify the
3441 * configuration file (nvi, rssnvi for this PF) if this is a
3444 device_printf(vi->dev, "RSS table not available.\n");
3445 vi->rss_base = 0xffff;
3450 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3451 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
3452 V_FW_PARAMS_PARAM_YZ(vi->viid);
3453 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3455 vi->rss_base = 0xffff;
3457 MPASS((val >> 16) == vi->rss_size);
3458 vi->rss_base = val & 0xffff;
3465 vcxgbe_attach(device_t dev)
3468 struct port_info *pi;
3472 vi = device_get_softc(dev);
3476 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
3479 rc = alloc_extra_vi(sc, pi, vi);
3480 end_synchronized_op(sc, 0);
3484 rc = cxgbe_vi_attach(dev, vi);
3486 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3493 vcxgbe_detach(device_t dev)
3498 vi = device_get_softc(dev);
3503 cxgbe_vi_detach(vi);
3504 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
3506 end_synchronized_op(sc, 0);
3511 static struct callout fatal_callout;
3512 static struct taskqueue *reset_tq;
3515 delayed_panic(void *arg)
3517 struct adapter *sc = arg;
3519 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
3523 fatal_error_task(void *arg, int pending)
3525 struct adapter *sc = arg;
3531 if (atomic_testandclear_int(&sc->error_flags, ilog2(ADAP_CIM_ERR))) {
3537 if (t4_reset_on_fatal_err) {
3538 CH_ALERT(sc, "resetting on fatal error.\n");
3539 rc = reset_adapter(sc);
3540 if (rc == 0 && t4_panic_on_fatal_err) {
3541 CH_ALERT(sc, "reset was successful, "
3542 "system will NOT panic.\n");
3547 if (t4_panic_on_fatal_err) {
3548 CH_ALERT(sc, "panicking on fatal error (after 30s).\n");
3549 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
3554 t4_fatal_err(struct adapter *sc, bool fw_error)
3556 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
3559 if (atomic_testandset_int(&sc->error_flags, ilog2(ADAP_FATAL_ERR)))
3563 * We are here because of a firmware error/timeout and not
3564 * because of a hardware interrupt. It is possible (although
3565 * not very likely) that an error interrupt was also raised but
3566 * this thread ran first and inhibited t4_intr_err. We walk the
3567 * main INT_CAUSE registers here to make sure we haven't missed
3568 * anything interesting.
3570 t4_slow_intr_handler(sc, verbose);
3571 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
3573 t4_report_fw_error(sc);
3574 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped (%d).\n",
3575 device_get_nameunit(sc->dev), fw_error);
3576 taskqueue_enqueue(reset_tq, &sc->fatal_error_task);
3580 t4_add_adapter(struct adapter *sc)
3582 sx_xlock(&t4_list_lock);
3583 SLIST_INSERT_HEAD(&t4_list, sc, link);
3584 sx_xunlock(&t4_list_lock);
3588 t4_map_bars_0_and_4(struct adapter *sc)
3590 sc->regs_rid = PCIR_BAR(0);
3591 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3592 &sc->regs_rid, RF_ACTIVE);
3593 if (sc->regs_res == NULL) {
3594 device_printf(sc->dev, "cannot map registers.\n");
3597 sc->bt = rman_get_bustag(sc->regs_res);
3598 sc->bh = rman_get_bushandle(sc->regs_res);
3599 sc->mmio_len = rman_get_size(sc->regs_res);
3600 setbit(&sc->doorbells, DOORBELL_KDB);
3602 sc->msix_rid = PCIR_BAR(4);
3603 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3604 &sc->msix_rid, RF_ACTIVE);
3605 if (sc->msix_res == NULL) {
3606 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
3614 t4_map_bar_2(struct adapter *sc)
3618 * T4: only iWARP driver uses the userspace doorbells. There is no need
3619 * to map it if RDMA is disabled.
3621 if (is_t4(sc) && sc->rdmacaps == 0)
3624 sc->udbs_rid = PCIR_BAR(2);
3625 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3626 &sc->udbs_rid, RF_ACTIVE);
3627 if (sc->udbs_res == NULL) {
3628 device_printf(sc->dev, "cannot map doorbell BAR.\n");
3631 sc->udbs_base = rman_get_virtual(sc->udbs_res);
3633 if (chip_id(sc) >= CHELSIO_T5) {
3634 setbit(&sc->doorbells, DOORBELL_UDB);
3635 #if defined(__i386__) || defined(__amd64__)
3636 if (t5_write_combine) {
3640 * Enable write combining on BAR2. This is the
3641 * userspace doorbell BAR and is split into 128B
3642 * (UDBS_SEG_SIZE) doorbell regions, each associated
3643 * with an egress queue. The first 64B has the doorbell
3644 * and the second 64B can be used to submit a tx work
3645 * request with an implicit doorbell.
3648 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
3649 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
3651 clrbit(&sc->doorbells, DOORBELL_UDB);
3652 setbit(&sc->doorbells, DOORBELL_WCWR);
3653 setbit(&sc->doorbells, DOORBELL_UDBWC);
3655 device_printf(sc->dev,
3656 "couldn't enable write combining: %d\n",
3660 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
3661 t4_write_reg(sc, A_SGE_STAT_CFG,
3662 V_STATSOURCE_T5(7) | mode);
3666 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
3671 struct memwin_init {
3676 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
3677 { MEMWIN0_BASE, MEMWIN0_APERTURE },
3678 { MEMWIN1_BASE, MEMWIN1_APERTURE },
3679 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
3682 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
3683 { MEMWIN0_BASE, MEMWIN0_APERTURE },
3684 { MEMWIN1_BASE, MEMWIN1_APERTURE },
3685 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
3689 setup_memwin(struct adapter *sc)
3691 const struct memwin_init *mw_init;
3698 * Read low 32b of bar0 indirectly via the hardware backdoor
3699 * mechanism. Works from within PCI passthrough environments
3700 * too, where rman_get_start() can return a different value. We
3701 * need to program the T4 memory window decoders with the actual
3702 * addresses that will be coming across the PCIe link.
3704 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
3705 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
3707 mw_init = &t4_memwin[0];
3709 /* T5+ use the relative offset inside the PCIe BAR */
3712 mw_init = &t5_memwin[0];
3715 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
3716 if (!rw_initialized(&mw->mw_lock)) {
3717 rw_init(&mw->mw_lock, "memory window access");
3718 mw->mw_base = mw_init->base;
3719 mw->mw_aperture = mw_init->aperture;
3723 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
3724 (mw->mw_base + bar0) | V_BIR(0) |
3725 V_WINDOW(ilog2(mw->mw_aperture) - 10));
3726 rw_wlock(&mw->mw_lock);
3727 position_memwin(sc, i, mw->mw_curpos);
3728 rw_wunlock(&mw->mw_lock);
3732 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
3736 * Positions the memory window at the given address in the card's address space.
3737 * There are some alignment requirements and the actual position may be at an
3738 * address prior to the requested address. mw->mw_curpos always has the actual
3739 * position of the window.
3742 position_memwin(struct adapter *sc, int idx, uint32_t addr)
3748 MPASS(idx >= 0 && idx < NUM_MEMWIN);
3749 mw = &sc->memwin[idx];
3750 rw_assert(&mw->mw_lock, RA_WLOCKED);
3754 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
3756 pf = V_PFNUM(sc->pf);
3757 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
3759 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
3760 t4_write_reg(sc, reg, mw->mw_curpos | pf);
3761 t4_read_reg(sc, reg); /* flush */
3765 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
3771 MPASS(idx >= 0 && idx < NUM_MEMWIN);
3773 /* Memory can only be accessed in naturally aligned 4 byte units */
3774 if (addr & 3 || len & 3 || len <= 0)
3777 mw = &sc->memwin[idx];
3779 rw_rlock(&mw->mw_lock);
3780 mw_end = mw->mw_curpos + mw->mw_aperture;
3781 if (addr >= mw_end || addr < mw->mw_curpos) {
3782 /* Will need to reposition the window */
3783 if (!rw_try_upgrade(&mw->mw_lock)) {
3784 rw_runlock(&mw->mw_lock);
3785 rw_wlock(&mw->mw_lock);
3787 rw_assert(&mw->mw_lock, RA_WLOCKED);
3788 position_memwin(sc, idx, addr);
3789 rw_downgrade(&mw->mw_lock);
3790 mw_end = mw->mw_curpos + mw->mw_aperture;
3792 rw_assert(&mw->mw_lock, RA_RLOCKED);
3793 while (addr < mw_end && len > 0) {
3795 v = t4_read_reg(sc, mw->mw_base + addr -
3797 *val++ = le32toh(v);
3800 t4_write_reg(sc, mw->mw_base + addr -
3801 mw->mw_curpos, htole32(v));
3806 rw_runlock(&mw->mw_lock);
3813 t4_init_atid_table(struct adapter *sc)
3822 MPASS(t->atid_tab == NULL);
3824 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
3826 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
3827 t->afree = t->atid_tab;
3828 t->atids_in_use = 0;
3829 for (i = 1; i < t->natids; i++)
3830 t->atid_tab[i - 1].next = &t->atid_tab[i];
3831 t->atid_tab[t->natids - 1].next = NULL;
3835 t4_free_atid_table(struct adapter *sc)
3841 KASSERT(t->atids_in_use == 0,
3842 ("%s: %d atids still in use.", __func__, t->atids_in_use));
3844 if (mtx_initialized(&t->atid_lock))
3845 mtx_destroy(&t->atid_lock);
3846 free(t->atid_tab, M_CXGBE);
3851 alloc_atid(struct adapter *sc, void *ctx)
3853 struct tid_info *t = &sc->tids;
3856 mtx_lock(&t->atid_lock);
3858 union aopen_entry *p = t->afree;
3860 atid = p - t->atid_tab;
3861 MPASS(atid <= M_TID_TID);
3866 mtx_unlock(&t->atid_lock);
3871 lookup_atid(struct adapter *sc, int atid)
3873 struct tid_info *t = &sc->tids;
3875 return (t->atid_tab[atid].data);
3879 free_atid(struct adapter *sc, int atid)
3881 struct tid_info *t = &sc->tids;
3882 union aopen_entry *p = &t->atid_tab[atid];
3884 mtx_lock(&t->atid_lock);
3888 mtx_unlock(&t->atid_lock);
3892 queue_tid_release(struct adapter *sc, int tid)
3895 CXGBE_UNIMPLEMENTED("deferred tid release");
3899 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
3902 struct cpl_tid_release *req;
3904 wr = alloc_wrqe(sizeof(*req), ctrlq);
3906 queue_tid_release(sc, tid); /* defer */
3911 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
3917 t4_range_cmp(const void *a, const void *b)
3919 return ((const struct t4_range *)a)->start -
3920 ((const struct t4_range *)b)->start;
3924 * Verify that the memory range specified by the addr/len pair is valid within
3925 * the card's address space.
3928 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
3930 struct t4_range mem_ranges[4], *r, *next;
3931 uint32_t em, addr_len;
3932 int i, n, remaining;
3934 /* Memory can only be accessed in naturally aligned 4 byte units */
3935 if (addr & 3 || len & 3 || len == 0)
3938 /* Enabled memories */
3939 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3943 bzero(r, sizeof(mem_ranges));
3944 if (em & F_EDRAM0_ENABLE) {
3945 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3946 r->size = G_EDRAM0_SIZE(addr_len) << 20;
3948 r->start = G_EDRAM0_BASE(addr_len) << 20;
3949 if (addr >= r->start &&
3950 addr + len <= r->start + r->size)
3956 if (em & F_EDRAM1_ENABLE) {
3957 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3958 r->size = G_EDRAM1_SIZE(addr_len) << 20;
3960 r->start = G_EDRAM1_BASE(addr_len) << 20;
3961 if (addr >= r->start &&
3962 addr + len <= r->start + r->size)
3968 if (em & F_EXT_MEM_ENABLE) {
3969 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3970 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
3972 r->start = G_EXT_MEM_BASE(addr_len) << 20;
3973 if (addr >= r->start &&
3974 addr + len <= r->start + r->size)
3980 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
3981 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3982 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
3984 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
3985 if (addr >= r->start &&
3986 addr + len <= r->start + r->size)
3992 MPASS(n <= nitems(mem_ranges));
3995 /* Sort and merge the ranges. */
3996 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3998 /* Start from index 0 and examine the next n - 1 entries. */
4000 for (remaining = n - 1; remaining > 0; remaining--, r++) {
4002 MPASS(r->size > 0); /* r is a valid entry. */
4004 MPASS(next->size > 0); /* and so is the next one. */
4006 while (r->start + r->size >= next->start) {
4007 /* Merge the next one into the current entry. */
4008 r->size = max(r->start + r->size,
4009 next->start + next->size) - r->start;
4010 n--; /* One fewer entry in total. */
4011 if (--remaining == 0)
4012 goto done; /* short circuit */
4015 if (next != r + 1) {
4017 * Some entries were merged into r and next
4018 * points to the first valid entry that couldn't
4021 MPASS(next->size > 0); /* must be valid */
4022 memcpy(r + 1, next, remaining * sizeof(*r));
4025 * This so that the foo->size assertion in the
4026 * next iteration of the loop do the right
4027 * thing for entries that were pulled up and are
4030 MPASS(n < nitems(mem_ranges));
4031 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
4032 sizeof(struct t4_range));
4037 /* Done merging the ranges. */
4040 for (i = 0; i < n; i++, r++) {
4041 if (addr >= r->start &&
4042 addr + len <= r->start + r->size)
4051 fwmtype_to_hwmtype(int mtype)
4055 case FW_MEMTYPE_EDC0:
4057 case FW_MEMTYPE_EDC1:
4059 case FW_MEMTYPE_EXTMEM:
4061 case FW_MEMTYPE_EXTMEM1:
4064 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
4069 * Verify that the memory range specified by the memtype/offset/len pair is
4070 * valid and lies entirely within the memtype specified. The global address of
4071 * the start of the range is returned in addr.
4074 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
4077 uint32_t em, addr_len, maddr;
4079 /* Memory can only be accessed in naturally aligned 4 byte units */
4080 if (off & 3 || len & 3 || len == 0)
4083 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
4084 switch (fwmtype_to_hwmtype(mtype)) {
4086 if (!(em & F_EDRAM0_ENABLE))
4088 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
4089 maddr = G_EDRAM0_BASE(addr_len) << 20;
4092 if (!(em & F_EDRAM1_ENABLE))
4094 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
4095 maddr = G_EDRAM1_BASE(addr_len) << 20;
4098 if (!(em & F_EXT_MEM_ENABLE))
4100 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
4101 maddr = G_EXT_MEM_BASE(addr_len) << 20;
4104 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
4106 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
4107 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
4113 *addr = maddr + off; /* global address */
4114 return (validate_mem_range(sc, *addr, len));
4118 fixup_devlog_params(struct adapter *sc)
4120 struct devlog_params *dparams = &sc->params.devlog;
4123 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
4124 dparams->size, &dparams->addr);
4130 update_nirq(struct intrs_and_queues *iaq, int nports)
4133 iaq->nirq = T4_EXTRA_INTR;
4134 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4135 iaq->nirq += nports * iaq->nofldrxq;
4136 iaq->nirq += nports * (iaq->num_vis - 1) *
4137 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
4138 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4142 * Adjust requirements to fit the number of interrupts available.
4145 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
4149 const int nports = sc->params.nports;
4154 bzero(iaq, sizeof(*iaq));
4155 iaq->intr_type = itype;
4156 iaq->num_vis = t4_num_vis;
4157 iaq->ntxq = t4_ntxq;
4158 iaq->ntxq_vi = t4_ntxq_vi;
4159 iaq->nrxq = t4_nrxq;
4160 iaq->nrxq_vi = t4_nrxq_vi;
4161 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4162 if (is_offload(sc) || is_ethoffload(sc)) {
4163 iaq->nofldtxq = t4_nofldtxq;
4164 iaq->nofldtxq_vi = t4_nofldtxq_vi;
4168 if (is_offload(sc)) {
4169 iaq->nofldrxq = t4_nofldrxq;
4170 iaq->nofldrxq_vi = t4_nofldrxq_vi;
4174 if (t4_native_netmap & NN_MAIN_VI) {
4175 iaq->nnmtxq = t4_nnmtxq;
4176 iaq->nnmrxq = t4_nnmrxq;
4178 if (t4_native_netmap & NN_EXTRA_VI) {
4179 iaq->nnmtxq_vi = t4_nnmtxq_vi;
4180 iaq->nnmrxq_vi = t4_nnmrxq_vi;
4184 update_nirq(iaq, nports);
4185 if (iaq->nirq <= navail &&
4186 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4188 * This is the normal case -- there are enough interrupts for
4195 * If extra VIs have been configured try reducing their count and see if
4198 while (iaq->num_vis > 1) {
4200 update_nirq(iaq, nports);
4201 if (iaq->nirq <= navail &&
4202 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4203 device_printf(sc->dev, "virtual interfaces per port "
4204 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
4205 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
4206 "itype %d, navail %u, nirq %d.\n",
4207 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
4208 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
4209 itype, navail, iaq->nirq);
4215 * Extra VIs will not be created. Log a message if they were requested.
4217 MPASS(iaq->num_vis == 1);
4218 iaq->ntxq_vi = iaq->nrxq_vi = 0;
4219 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
4220 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
4221 if (iaq->num_vis != t4_num_vis) {
4222 device_printf(sc->dev, "extra virtual interfaces disabled. "
4223 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
4224 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
4225 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
4226 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
4230 * Keep reducing the number of NIC rx queues to the next lower power of
4231 * 2 (for even RSS distribution) and halving the TOE rx queues and see
4235 if (iaq->nrxq > 1) {
4238 } while (!powerof2(iaq->nrxq));
4239 if (iaq->nnmrxq > iaq->nrxq)
4240 iaq->nnmrxq = iaq->nrxq;
4242 if (iaq->nofldrxq > 1)
4243 iaq->nofldrxq >>= 1;
4245 old_nirq = iaq->nirq;
4246 update_nirq(iaq, nports);
4247 if (iaq->nirq <= navail &&
4248 (itype != INTR_MSI || powerof2(iaq->nirq))) {
4249 device_printf(sc->dev, "running with reduced number of "
4250 "rx queues because of shortage of interrupts. "
4251 "nrxq=%u, nofldrxq=%u. "
4252 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
4253 iaq->nofldrxq, itype, navail, iaq->nirq);
4256 } while (old_nirq != iaq->nirq);
4258 /* One interrupt for everything. Ugh. */
4259 device_printf(sc->dev, "running with minimal number of queues. "
4260 "itype %d, navail %u.\n", itype, navail);
4264 if (iaq->nofldrxq > 0) {
4271 MPASS(iaq->num_vis > 0);
4272 if (iaq->num_vis > 1) {
4273 MPASS(iaq->nrxq_vi > 0);
4274 MPASS(iaq->ntxq_vi > 0);
4276 MPASS(iaq->nirq > 0);
4277 MPASS(iaq->nrxq > 0);
4278 MPASS(iaq->ntxq > 0);
4279 if (itype == INTR_MSI) {
4280 MPASS(powerof2(iaq->nirq));
4285 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
4287 int rc, itype, navail, nalloc;
4289 for (itype = INTR_MSIX; itype; itype >>= 1) {
4291 if ((itype & t4_intr_types) == 0)
4292 continue; /* not allowed */
4294 if (itype == INTR_MSIX)
4295 navail = pci_msix_count(sc->dev);
4296 else if (itype == INTR_MSI)
4297 navail = pci_msi_count(sc->dev);
4304 calculate_iaq(sc, iaq, itype, navail);
4307 if (itype == INTR_MSIX)
4308 rc = pci_alloc_msix(sc->dev, &nalloc);
4309 else if (itype == INTR_MSI)
4310 rc = pci_alloc_msi(sc->dev, &nalloc);
4312 if (rc == 0 && nalloc > 0) {
4313 if (nalloc == iaq->nirq)
4317 * Didn't get the number requested. Use whatever number
4318 * the kernel is willing to allocate.
4320 device_printf(sc->dev, "fewer vectors than requested, "
4321 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
4322 itype, iaq->nirq, nalloc);
4323 pci_release_msi(sc->dev);
4328 device_printf(sc->dev,
4329 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
4330 itype, rc, iaq->nirq, nalloc);
4333 device_printf(sc->dev,
4334 "failed to find a usable interrupt type. "
4335 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
4336 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
4341 #define FW_VERSION(chip) ( \
4342 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
4343 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
4344 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
4345 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
4346 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
4348 /* Just enough of fw_hdr to cover all version info. */
4354 __be32 tp_microcode_ver;
4359 __u8 intfver_iscsipdu;
4361 __u8 intfver_fcoepdu;
4364 /* Spot check a couple of fields. */
4365 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
4366 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
4367 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
4377 .kld_name = "t4fw_cfg",
4378 .fw_mod_name = "t4fw",
4380 .chip = FW_HDR_CHIP_T4,
4381 .fw_ver = htobe32(FW_VERSION(T4)),
4382 .intfver_nic = FW_INTFVER(T4, NIC),
4383 .intfver_vnic = FW_INTFVER(T4, VNIC),
4384 .intfver_ofld = FW_INTFVER(T4, OFLD),
4385 .intfver_ri = FW_INTFVER(T4, RI),
4386 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
4387 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4388 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
4389 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4393 .kld_name = "t5fw_cfg",
4394 .fw_mod_name = "t5fw",
4396 .chip = FW_HDR_CHIP_T5,
4397 .fw_ver = htobe32(FW_VERSION(T5)),
4398 .intfver_nic = FW_INTFVER(T5, NIC),
4399 .intfver_vnic = FW_INTFVER(T5, VNIC),
4400 .intfver_ofld = FW_INTFVER(T5, OFLD),
4401 .intfver_ri = FW_INTFVER(T5, RI),
4402 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
4403 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4404 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
4405 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4409 .kld_name = "t6fw_cfg",
4410 .fw_mod_name = "t6fw",
4412 .chip = FW_HDR_CHIP_T6,
4413 .fw_ver = htobe32(FW_VERSION(T6)),
4414 .intfver_nic = FW_INTFVER(T6, NIC),
4415 .intfver_vnic = FW_INTFVER(T6, VNIC),
4416 .intfver_ofld = FW_INTFVER(T6, OFLD),
4417 .intfver_ri = FW_INTFVER(T6, RI),
4418 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4419 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4420 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4421 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4426 static struct fw_info *
4427 find_fw_info(int chip)
4431 for (i = 0; i < nitems(fw_info); i++) {
4432 if (fw_info[i].chip == chip)
4433 return (&fw_info[i]);
4439 * Is the given firmware API compatible with the one the driver was compiled
4443 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
4446 /* short circuit if it's the exact same firmware version */
4447 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
4451 * XXX: Is this too conservative? Perhaps I should limit this to the
4452 * features that are supported in the driver.
4454 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
4455 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
4456 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
4457 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
4465 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
4466 const struct firmware **fw)
4468 struct fw_info *fw_info;
4474 fw_info = find_fw_info(chip_id(sc));
4475 if (fw_info == NULL) {
4476 device_printf(sc->dev,
4477 "unable to look up firmware information for chip %d.\n",
4482 *dcfg = firmware_get(fw_info->kld_name);
4483 if (*dcfg != NULL) {
4485 *fw = firmware_get(fw_info->fw_mod_name);
4493 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
4494 const struct firmware *fw)
4498 firmware_put(fw, FIRMWARE_UNLOAD);
4500 firmware_put(dcfg, FIRMWARE_UNLOAD);
4505 * 0 means no firmware install attempted.
4506 * ERESTART means a firmware install was attempted and was successful.
4507 * +ve errno means a firmware install was attempted but failed.
4510 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
4511 const struct fw_h *drv_fw, const char *reason, int *already)
4513 const struct firmware *cfg, *fw;
4514 const uint32_t c = be32toh(card_fw->fw_ver);
4517 struct fw_h bundled_fw;
4518 bool load_attempted;
4521 load_attempted = false;
4522 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
4524 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
4525 if (t4_fw_install < 0) {
4526 rc = load_fw_module(sc, &cfg, &fw);
4527 if (rc != 0 || fw == NULL) {
4528 device_printf(sc->dev,
4529 "failed to load firmware module: %d. cfg %p, fw %p;"
4530 " will use compiled-in firmware version for"
4531 "hw.cxgbe.fw_install checks.\n",
4534 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
4536 load_attempted = true;
4538 d = be32toh(bundled_fw.fw_ver);
4543 if ((sc->flags & FW_OK) == 0) {
4545 if (c == 0xffffffff) {
4554 if (!fw_compatible(card_fw, &bundled_fw)) {
4555 reason = "incompatible or unusable";
4560 reason = "older than the version bundled with this driver";
4564 if (fw_install == 2 && d != c) {
4565 reason = "different than the version bundled with this driver";
4569 /* No reason to do anything to the firmware already on the card. */
4578 if (fw_install == 0) {
4579 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4580 "but the driver is prohibited from installing a firmware "
4582 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4583 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
4589 * We'll attempt to install a firmware. Load the module first (if it
4590 * hasn't been loaded already).
4592 if (!load_attempted) {
4593 rc = load_fw_module(sc, &cfg, &fw);
4594 if (rc != 0 || fw == NULL) {
4595 device_printf(sc->dev,
4596 "failed to load firmware module: %d. cfg %p, fw %p\n",
4602 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4603 "but the driver cannot take corrective action because it "
4604 "is unable to load the firmware module.\n",
4605 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4606 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
4607 rc = sc->flags & FW_OK ? 0 : ENOENT;
4610 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
4612 MPASS(t4_fw_install > 0);
4613 device_printf(sc->dev,
4614 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
4615 "expecting (%u.%u.%u.%u) and will not be used.\n",
4616 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
4617 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
4618 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
4619 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
4620 rc = sc->flags & FW_OK ? 0 : EINVAL;
4624 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
4625 "installing firmware %u.%u.%u.%u on card.\n",
4626 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
4627 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
4628 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
4629 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
4631 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
4633 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
4635 /* Installed successfully, update the cached header too. */
4637 memcpy(card_fw, fw->data, sizeof(*card_fw));
4640 unload_fw_module(sc, cfg, fw);
4646 * Establish contact with the firmware and attempt to become the master driver.
4648 * A firmware will be installed to the card if needed (if the driver is allowed
4652 contact_firmware(struct adapter *sc)
4654 int rc, already = 0;
4655 enum dev_state state;
4656 struct fw_info *fw_info;
4657 struct fw_hdr *card_fw; /* fw on the card */
4658 const struct fw_h *drv_fw;
4660 fw_info = find_fw_info(chip_id(sc));
4661 if (fw_info == NULL) {
4662 device_printf(sc->dev,
4663 "unable to look up firmware information for chip %d.\n",
4667 drv_fw = &fw_info->fw_h;
4669 /* Read the header of the firmware on the card */
4670 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
4672 rc = -t4_get_fw_hdr(sc, card_fw);
4674 device_printf(sc->dev,
4675 "unable to read firmware header from card's flash: %d\n",
4680 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
4687 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
4688 if (rc < 0 || state == DEV_STATE_ERR) {
4690 device_printf(sc->dev,
4691 "failed to connect to the firmware: %d, %d. "
4692 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4694 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
4695 "not responding properly to HELLO", &already) == ERESTART)
4700 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
4701 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
4704 sc->flags |= MASTER_PF;
4705 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
4711 } else if (state == DEV_STATE_UNINIT) {
4713 * We didn't get to be the master so we definitely won't be
4714 * configuring the chip. It's a bug if someone else hasn't
4715 * configured it already.
4717 device_printf(sc->dev, "couldn't be master(%d), "
4718 "device not already initialized either(%d). "
4719 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4724 * Some other PF is the master and has configured the chip.
4725 * This is allowed but untested.
4727 device_printf(sc->dev, "PF%d is master, device state %d. "
4728 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
4729 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
4734 if (rc != 0 && sc->flags & FW_OK) {
4735 t4_fw_bye(sc, sc->mbox);
4736 sc->flags &= ~FW_OK;
4738 free(card_fw, M_CXGBE);
4743 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
4744 uint32_t mtype, uint32_t moff)
4746 struct fw_info *fw_info;
4747 const struct firmware *dcfg, *rcfg = NULL;
4748 const uint32_t *cfdata;
4749 uint32_t cflen, addr;
4752 load_fw_module(sc, &dcfg, NULL);
4754 /* Card specific interpretation of "default". */
4755 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
4756 if (pci_get_device(sc->dev) == 0x440a)
4757 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
4759 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
4762 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
4764 device_printf(sc->dev,
4765 "KLD with default config is not available.\n");
4769 cfdata = dcfg->data;
4770 cflen = dcfg->datasize & ~3;
4774 fw_info = find_fw_info(chip_id(sc));
4775 if (fw_info == NULL) {
4776 device_printf(sc->dev,
4777 "unable to look up firmware information for chip %d.\n",
4782 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
4784 rcfg = firmware_get(s);
4786 device_printf(sc->dev,
4787 "unable to load module \"%s\" for configuration "
4788 "profile \"%s\".\n", s, cfg_file);
4792 cfdata = rcfg->data;
4793 cflen = rcfg->datasize & ~3;
4796 if (cflen > FLASH_CFG_MAX_SIZE) {
4797 device_printf(sc->dev,
4798 "config file too long (%d, max allowed is %d).\n",
4799 cflen, FLASH_CFG_MAX_SIZE);
4804 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
4806 device_printf(sc->dev,
4807 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
4808 __func__, mtype, moff, cflen, rc);
4812 write_via_memwin(sc, 2, addr, cfdata, cflen);
4815 firmware_put(rcfg, FIRMWARE_UNLOAD);
4816 unload_fw_module(sc, dcfg, NULL);
4820 struct caps_allowed {
4823 uint16_t switchcaps;
4827 uint16_t cryptocaps;
4832 #define FW_PARAM_DEV(param) \
4833 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4834 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4835 #define FW_PARAM_PFVF(param) \
4836 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4837 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
4840 * Provide a configuration profile to the firmware and have it initialize the
4841 * chip accordingly. This may involve uploading a configuration file to the
4845 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
4846 const struct caps_allowed *caps_allowed)
4849 struct fw_caps_config_cmd caps;
4850 uint32_t mtype, moff, finicsum, cfcsum, param, val;
4852 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
4854 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
4858 bzero(&caps, sizeof(caps));
4859 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4860 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4861 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
4864 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4865 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
4866 mtype = FW_MEMTYPE_FLASH;
4867 moff = t4_flash_cfg_addr(sc);
4868 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4869 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4870 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4874 * Ask the firmware where it wants us to upload the config file.
4876 param = FW_PARAM_DEV(CF);
4877 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4879 /* No support for config file? Shouldn't happen. */
4880 device_printf(sc->dev,
4881 "failed to query config file location: %d.\n", rc);
4884 mtype = G_FW_PARAMS_PARAM_Y(val);
4885 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
4886 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4887 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4888 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4891 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
4893 device_printf(sc->dev,
4894 "failed to upload config file to card: %d.\n", rc);
4898 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4900 device_printf(sc->dev, "failed to pre-process config file: %d "
4901 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
4905 finicsum = be32toh(caps.finicsum);
4906 cfcsum = be32toh(caps.cfcsum); /* actual */
4907 if (finicsum != cfcsum) {
4908 device_printf(sc->dev,
4909 "WARNING: config file checksum mismatch: %08x %08x\n",
4912 sc->cfcsum = cfcsum;
4913 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
4916 * Let the firmware know what features will (not) be used so it can tune
4917 * things accordingly.
4919 #define LIMIT_CAPS(x) do { \
4920 caps.x##caps &= htobe16(caps_allowed->x##caps); \
4932 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4934 * TOE and hashfilters are mutually exclusive. It is a config
4935 * file or firmware bug if both are reported as available. Try
4936 * to cope with the situation in non-debug builds by disabling
4939 MPASS(caps.toecaps == 0);
4946 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4947 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4948 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4949 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
4951 device_printf(sc->dev,
4952 "failed to process config file: %d.\n", rc);
4956 t4_tweak_chip_settings(sc);
4957 set_params__pre_init(sc);
4959 /* get basic stuff going */
4960 rc = -t4_fw_initialize(sc, sc->mbox);
4962 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
4970 * Partition chip resources for use between various PFs, VFs, etc.
4973 partition_resources(struct adapter *sc)
4975 char cfg_file[sizeof(t4_cfg_file)];
4976 struct caps_allowed caps_allowed;
4980 /* Only the master driver gets to configure the chip resources. */
4981 MPASS(sc->flags & MASTER_PF);
4983 #define COPY_CAPS(x) do { \
4984 caps_allowed.x##caps = t4_##x##caps_allowed; \
4986 bzero(&caps_allowed, sizeof(caps_allowed));
4996 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
4997 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
4999 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
5000 if (rc != 0 && fallback) {
5001 device_printf(sc->dev,
5002 "failed (%d) to configure card with \"%s\" profile, "
5003 "will fall back to a basic configuration and retry.\n",
5005 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
5006 bzero(&caps_allowed, sizeof(caps_allowed));
5008 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
5017 * Retrieve parameters that are needed (or nice to have) very early.
5020 get_params__pre_init(struct adapter *sc)
5023 uint32_t param[2], val[2];
5025 t4_get_version_info(sc);
5027 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
5028 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
5029 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
5030 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
5031 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
5033 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
5034 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
5035 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
5036 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
5037 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
5039 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
5040 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
5041 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
5042 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
5043 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
5045 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
5046 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
5047 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
5048 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
5049 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
5051 param[0] = FW_PARAM_DEV(PORTVEC);
5052 param[1] = FW_PARAM_DEV(CCLK);
5053 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5055 device_printf(sc->dev,
5056 "failed to query parameters (pre_init): %d.\n", rc);
5060 sc->params.portvec = val[0];
5061 sc->params.nports = bitcount32(val[0]);
5062 sc->params.vpd.cclk = val[1];
5064 /* Read device log parameters. */
5065 rc = -t4_init_devlog_params(sc, 1);
5067 fixup_devlog_params(sc);
5069 device_printf(sc->dev,
5070 "failed to get devlog parameters: %d.\n", rc);
5071 rc = 0; /* devlog isn't critical for device operation */
5078 * Any params that need to be set before FW_INITIALIZE.
5081 set_params__pre_init(struct adapter *sc)
5084 uint32_t param, val;
5086 if (chip_id(sc) >= CHELSIO_T6) {
5087 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
5089 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5090 /* firmwares < 1.20.1.0 do not have this param. */
5091 if (rc == FW_EINVAL &&
5092 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
5096 device_printf(sc->dev,
5097 "failed to enable high priority filters :%d.\n",
5102 /* Enable opaque VIIDs with firmwares that support it. */
5103 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
5105 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5106 if (rc == 0 && val == 1)
5107 sc->params.viid_smt_extn_support = true;
5109 sc->params.viid_smt_extn_support = false;
5115 * Retrieve various parameters that are of interest to the driver. The device
5116 * has been initialized by the firmware at this point.
5119 get_params__post_init(struct adapter *sc)
5122 uint32_t param[7], val[7];
5123 struct fw_caps_config_cmd caps;
5125 param[0] = FW_PARAM_PFVF(IQFLINT_START);
5126 param[1] = FW_PARAM_PFVF(EQ_START);
5127 param[2] = FW_PARAM_PFVF(FILTER_START);
5128 param[3] = FW_PARAM_PFVF(FILTER_END);
5129 param[4] = FW_PARAM_PFVF(L2T_START);
5130 param[5] = FW_PARAM_PFVF(L2T_END);
5131 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5132 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5133 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
5134 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
5136 device_printf(sc->dev,
5137 "failed to query parameters (post_init): %d.\n", rc);
5141 sc->sge.iq_start = val[0];
5142 sc->sge.eq_start = val[1];
5143 if ((int)val[3] > (int)val[2]) {
5144 sc->tids.ftid_base = val[2];
5145 sc->tids.ftid_end = val[3];
5146 sc->tids.nftids = val[3] - val[2] + 1;
5148 sc->vres.l2t.start = val[4];
5149 sc->vres.l2t.size = val[5] - val[4] + 1;
5150 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
5151 ("%s: L2 table size (%u) larger than expected (%u)",
5152 __func__, sc->vres.l2t.size, L2T_SIZE));
5153 sc->params.core_vdd = val[6];
5155 param[0] = FW_PARAM_PFVF(IQFLINT_END);
5156 param[1] = FW_PARAM_PFVF(EQ_END);
5157 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5159 device_printf(sc->dev,
5160 "failed to query parameters (post_init2): %d.\n", rc);
5163 MPASS((int)val[0] >= sc->sge.iq_start);
5164 sc->sge.iqmap_sz = val[0] - sc->sge.iq_start + 1;
5165 MPASS((int)val[1] >= sc->sge.eq_start);
5166 sc->sge.eqmap_sz = val[1] - sc->sge.eq_start + 1;
5168 if (chip_id(sc) >= CHELSIO_T6) {
5170 sc->tids.tid_base = t4_read_reg(sc,
5171 A_LE_DB_ACTIVE_TABLE_START_INDEX);
5173 param[0] = FW_PARAM_PFVF(HPFILTER_START);
5174 param[1] = FW_PARAM_PFVF(HPFILTER_END);
5175 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5177 device_printf(sc->dev,
5178 "failed to query hpfilter parameters: %d.\n", rc);
5181 if ((int)val[1] > (int)val[0]) {
5182 sc->tids.hpftid_base = val[0];
5183 sc->tids.hpftid_end = val[1];
5184 sc->tids.nhpftids = val[1] - val[0] + 1;
5187 * These should go off if the layout changes and the
5188 * driver needs to catch up.
5190 MPASS(sc->tids.hpftid_base == 0);
5191 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
5194 param[0] = FW_PARAM_PFVF(RAWF_START);
5195 param[1] = FW_PARAM_PFVF(RAWF_END);
5196 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5198 device_printf(sc->dev,
5199 "failed to query rawf parameters: %d.\n", rc);
5202 if ((int)val[1] > (int)val[0]) {
5203 sc->rawf_base = val[0];
5204 sc->nrawf = val[1] - val[0] + 1;
5209 * MPSBGMAP is queried separately because only recent firmwares support
5210 * it as a parameter and we don't want the compound query above to fail
5211 * on older firmwares.
5213 param[0] = FW_PARAM_DEV(MPSBGMAP);
5215 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5217 sc->params.mps_bg_map = val[0];
5219 sc->params.mps_bg_map = 0;
5222 * Determine whether the firmware supports the filter2 work request.
5223 * This is queried separately for the same reason as MPSBGMAP above.
5225 param[0] = FW_PARAM_DEV(FILTER2_WR);
5227 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5229 sc->params.filter2_wr_support = val[0] != 0;
5231 sc->params.filter2_wr_support = 0;
5234 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
5235 * This is queried separately for the same reason as other params above.
5237 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5239 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5241 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
5243 sc->params.ulptx_memwrite_dsgl = false;
5245 /* FW_RI_FR_NSMR_TPTE_WR support */
5246 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
5247 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5249 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
5251 sc->params.fr_nsmr_tpte_wr_support = false;
5253 /* Support for 512 SGL entries per FR MR. */
5254 param[0] = FW_PARAM_DEV(DEV_512SGL_MR);
5255 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5257 sc->params.dev_512sgl_mr = val[0] != 0;
5259 sc->params.dev_512sgl_mr = false;
5261 param[0] = FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
5262 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5264 sc->params.max_pkts_per_eth_tx_pkts_wr = val[0];
5266 sc->params.max_pkts_per_eth_tx_pkts_wr = 15;
5268 param[0] = FW_PARAM_DEV(NUM_TM_CLASS);
5269 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5271 MPASS(val[0] > 0 && val[0] < 256); /* nsched_cls is 8b */
5272 sc->params.nsched_cls = val[0];
5274 sc->params.nsched_cls = sc->chip_params->nsched_cls;
5276 /* get capabilites */
5277 bzero(&caps, sizeof(caps));
5278 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5279 F_FW_CMD_REQUEST | F_FW_CMD_READ);
5280 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
5281 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
5283 device_printf(sc->dev,
5284 "failed to get card capabilities: %d.\n", rc);
5288 #define READ_CAPS(x) do { \
5289 sc->x = htobe16(caps.x); \
5292 READ_CAPS(linkcaps);
5293 READ_CAPS(switchcaps);
5296 READ_CAPS(rdmacaps);
5297 READ_CAPS(cryptocaps);
5298 READ_CAPS(iscsicaps);
5299 READ_CAPS(fcoecaps);
5301 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
5302 MPASS(chip_id(sc) > CHELSIO_T4);
5303 MPASS(sc->toecaps == 0);
5306 param[0] = FW_PARAM_DEV(NTID);
5307 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
5309 device_printf(sc->dev,
5310 "failed to query HASHFILTER parameters: %d.\n", rc);
5313 sc->tids.ntids = val[0];
5314 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5315 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5316 sc->tids.ntids -= sc->tids.nhpftids;
5318 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5319 sc->params.hash_filter = 1;
5321 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
5322 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
5323 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
5324 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5325 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
5327 device_printf(sc->dev,
5328 "failed to query NIC parameters: %d.\n", rc);
5331 if ((int)val[1] > (int)val[0]) {
5332 sc->tids.etid_base = val[0];
5333 sc->tids.etid_end = val[1];
5334 sc->tids.netids = val[1] - val[0] + 1;
5335 sc->params.eo_wr_cred = val[2];
5336 sc->params.ethoffload = 1;
5340 /* query offload-related parameters */
5341 param[0] = FW_PARAM_DEV(NTID);
5342 param[1] = FW_PARAM_PFVF(SERVER_START);
5343 param[2] = FW_PARAM_PFVF(SERVER_END);
5344 param[3] = FW_PARAM_PFVF(TDDP_START);
5345 param[4] = FW_PARAM_PFVF(TDDP_END);
5346 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5347 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5349 device_printf(sc->dev,
5350 "failed to query TOE parameters: %d.\n", rc);
5353 sc->tids.ntids = val[0];
5354 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
5355 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
5356 sc->tids.ntids -= sc->tids.nhpftids;
5358 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
5359 if ((int)val[2] > (int)val[1]) {
5360 sc->tids.stid_base = val[1];
5361 sc->tids.nstids = val[2] - val[1] + 1;
5363 sc->vres.ddp.start = val[3];
5364 sc->vres.ddp.size = val[4] - val[3] + 1;
5365 sc->params.ofldq_wr_cred = val[5];
5366 sc->params.offload = 1;
5369 * The firmware attempts memfree TOE configuration for -SO cards
5370 * and will report toecaps=0 if it runs out of resources (this
5371 * depends on the config file). It may not report 0 for other
5372 * capabilities dependent on the TOE in this case. Set them to
5373 * 0 here so that the driver doesn't bother tracking resources
5374 * that will never be used.
5380 param[0] = FW_PARAM_PFVF(STAG_START);
5381 param[1] = FW_PARAM_PFVF(STAG_END);
5382 param[2] = FW_PARAM_PFVF(RQ_START);
5383 param[3] = FW_PARAM_PFVF(RQ_END);
5384 param[4] = FW_PARAM_PFVF(PBL_START);
5385 param[5] = FW_PARAM_PFVF(PBL_END);
5386 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5388 device_printf(sc->dev,
5389 "failed to query RDMA parameters(1): %d.\n", rc);
5392 sc->vres.stag.start = val[0];
5393 sc->vres.stag.size = val[1] - val[0] + 1;
5394 sc->vres.rq.start = val[2];
5395 sc->vres.rq.size = val[3] - val[2] + 1;
5396 sc->vres.pbl.start = val[4];
5397 sc->vres.pbl.size = val[5] - val[4] + 1;
5399 param[0] = FW_PARAM_PFVF(SQRQ_START);
5400 param[1] = FW_PARAM_PFVF(SQRQ_END);
5401 param[2] = FW_PARAM_PFVF(CQ_START);
5402 param[3] = FW_PARAM_PFVF(CQ_END);
5403 param[4] = FW_PARAM_PFVF(OCQ_START);
5404 param[5] = FW_PARAM_PFVF(OCQ_END);
5405 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
5407 device_printf(sc->dev,
5408 "failed to query RDMA parameters(2): %d.\n", rc);
5411 sc->vres.qp.start = val[0];
5412 sc->vres.qp.size = val[1] - val[0] + 1;
5413 sc->vres.cq.start = val[2];
5414 sc->vres.cq.size = val[3] - val[2] + 1;
5415 sc->vres.ocq.start = val[4];
5416 sc->vres.ocq.size = val[5] - val[4] + 1;
5418 param[0] = FW_PARAM_PFVF(SRQ_START);
5419 param[1] = FW_PARAM_PFVF(SRQ_END);
5420 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
5421 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5422 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
5424 device_printf(sc->dev,
5425 "failed to query RDMA parameters(3): %d.\n", rc);
5428 sc->vres.srq.start = val[0];
5429 sc->vres.srq.size = val[1] - val[0] + 1;
5430 sc->params.max_ordird_qp = val[2];
5431 sc->params.max_ird_adapter = val[3];
5433 if (sc->iscsicaps) {
5434 param[0] = FW_PARAM_PFVF(ISCSI_START);
5435 param[1] = FW_PARAM_PFVF(ISCSI_END);
5436 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5438 device_printf(sc->dev,
5439 "failed to query iSCSI parameters: %d.\n", rc);
5442 sc->vres.iscsi.start = val[0];
5443 sc->vres.iscsi.size = val[1] - val[0] + 1;
5445 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
5446 param[0] = FW_PARAM_PFVF(TLS_START);
5447 param[1] = FW_PARAM_PFVF(TLS_END);
5448 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
5450 device_printf(sc->dev,
5451 "failed to query TLS parameters: %d.\n", rc);
5454 sc->vres.key.start = val[0];
5455 sc->vres.key.size = val[1] - val[0] + 1;
5459 * We've got the params we wanted to query directly from the firmware.
5460 * Grab some others via other means.
5462 t4_init_sge_params(sc);
5463 t4_init_tp_params(sc);
5464 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
5465 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
5467 rc = t4_verify_chip_settings(sc);
5470 t4_init_rx_buf_info(sc);
5477 ktls_tick(void *arg)
5483 tstamp = tcp_ts_getticks();
5484 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
5485 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
5486 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
5490 t4_config_kern_tls(struct adapter *sc, bool enable)
5493 uint32_t param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5494 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_KTLS_HW) |
5495 V_FW_PARAMS_PARAM_Y(enable ? 1 : 0) |
5496 V_FW_PARAMS_PARAM_Z(FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE);
5498 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, ¶m);
5500 CH_ERR(sc, "failed to %s NIC TLS: %d\n",
5501 enable ? "enable" : "disable", rc);
5506 sc->flags |= KERN_TLS_ON;
5507 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
5510 sc->flags &= ~KERN_TLS_ON;
5511 callout_stop(&sc->ktls_tick);
5519 set_params__post_init(struct adapter *sc)
5521 uint32_t mask, param, val;
5526 /* ask for encapsulated CPLs */
5527 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5529 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5531 /* Enable 32b port caps if the firmware supports it. */
5532 param = FW_PARAM_PFVF(PORT_CAPS32);
5534 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
5535 sc->params.port_caps32 = 1;
5537 /* Let filter + maskhash steer to a part of the VI's RSS region. */
5538 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
5539 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
5540 V_MASKFILTER(val - 1));
5542 mask = F_DROPERRORANY | F_DROPERRORMAC | F_DROPERRORIPVER |
5543 F_DROPERRORFRAG | F_DROPERRORATTACK | F_DROPERRORETHHDRLEN |
5544 F_DROPERRORIPHDRLEN | F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
5545 F_DROPERRORTCPOPT | F_DROPERRORCSUMIP | F_DROPERRORCSUM;
5547 if (chip_id(sc) < CHELSIO_T6 && t4_attack_filter != 0) {
5548 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_ATTACKFILTERENABLE,
5549 F_ATTACKFILTERENABLE);
5550 val |= F_DROPERRORATTACK;
5552 if (t4_drop_ip_fragments != 0) {
5553 t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, F_FRAGMENTDROP,
5555 val |= F_DROPERRORFRAG;
5557 if (t4_drop_pkts_with_l2_errors != 0)
5558 val |= F_DROPERRORMAC | F_DROPERRORETHHDRLEN;
5559 if (t4_drop_pkts_with_l3_errors != 0) {
5560 val |= F_DROPERRORIPVER | F_DROPERRORIPHDRLEN |
5563 if (t4_drop_pkts_with_l4_errors != 0) {
5564 val |= F_DROPERRORTCPHDRLEN | F_DROPERRORPKTLEN |
5565 F_DROPERRORTCPOPT | F_DROPERRORCSUM;
5567 t4_set_reg_field(sc, A_TP_ERR_CONFIG, mask, val);
5571 * Override the TOE timers with user provided tunables. This is not the
5572 * recommended way to change the timers (the firmware config file is) so
5573 * these tunables are not documented.
5575 * All the timer tunables are in microseconds.
5577 if (t4_toe_keepalive_idle != 0) {
5578 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
5579 v &= M_KEEPALIVEIDLE;
5580 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
5581 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
5583 if (t4_toe_keepalive_interval != 0) {
5584 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
5585 v &= M_KEEPALIVEINTVL;
5586 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
5587 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
5589 if (t4_toe_keepalive_count != 0) {
5590 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
5591 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
5592 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
5593 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
5594 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
5596 if (t4_toe_rexmt_min != 0) {
5597 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
5599 t4_set_reg_field(sc, A_TP_RXT_MIN,
5600 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
5602 if (t4_toe_rexmt_max != 0) {
5603 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
5605 t4_set_reg_field(sc, A_TP_RXT_MAX,
5606 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
5608 if (t4_toe_rexmt_count != 0) {
5609 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
5610 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
5611 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
5612 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
5613 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
5615 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
5616 if (t4_toe_rexmt_backoff[i] != -1) {
5617 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
5618 shift = (i & 3) << 3;
5619 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
5620 M_TIMERBACKOFFINDEX0 << shift, v << shift);
5626 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
5627 sc->toecaps & FW_CAPS_CONFIG_TOE) {
5629 * Limit TOE connections to 2 reassembly "islands". This is
5630 * required for TOE TLS connections to downgrade to plain TOE
5631 * connections if an unsupported TLS version or ciphersuite is
5634 t4_tp_wr_bits_indirect(sc, A_TP_FRAG_CONFIG,
5635 V_PASSMODE(M_PASSMODE), V_PASSMODE(2));
5637 sc->tlst.inline_keys = t4_tls_inline_keys;
5638 sc->tlst.combo_wrs = t4_tls_combo_wrs;
5639 if (t4_kern_tls != 0)
5640 t4_config_kern_tls(sc, true);
5647 #undef FW_PARAM_PFVF
5651 t4_set_desc(struct adapter *sc)
5654 struct adapter_params *p = &sc->params;
5656 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
5658 device_set_desc_copy(sc->dev, buf);
5662 ifmedia_add4(struct ifmedia *ifm, int m)
5665 ifmedia_add(ifm, m, 0, NULL);
5666 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
5667 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
5668 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
5672 * This is the selected media, which is not quite the same as the active media.
5673 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
5674 * and active are not the same, and "media: Ethernet selected" otherwise.
5677 set_current_media(struct port_info *pi)
5679 struct link_config *lc;
5680 struct ifmedia *ifm;
5684 PORT_LOCK_ASSERT_OWNED(pi);
5686 /* Leave current media alone if it's already set to IFM_NONE. */
5688 if (ifm->ifm_cur != NULL &&
5689 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
5693 if (lc->requested_aneg != AUTONEG_DISABLE &&
5694 lc->pcaps & FW_PORT_CAP32_ANEG) {
5695 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
5698 mword = IFM_ETHER | IFM_FDX;
5699 if (lc->requested_fc & PAUSE_TX)
5700 mword |= IFM_ETH_TXPAUSE;
5701 if (lc->requested_fc & PAUSE_RX)
5702 mword |= IFM_ETH_RXPAUSE;
5703 if (lc->requested_speed == 0)
5704 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
5706 speed = lc->requested_speed;
5707 mword |= port_mword(pi, speed_to_fwcap(speed));
5708 ifmedia_set(ifm, mword);
5712 * Returns true if the ifmedia list for the port cannot change.
5715 fixed_ifmedia(struct port_info *pi)
5718 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
5719 pi->port_type == FW_PORT_TYPE_BT_XFI ||
5720 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
5721 pi->port_type == FW_PORT_TYPE_KX4 ||
5722 pi->port_type == FW_PORT_TYPE_KX ||
5723 pi->port_type == FW_PORT_TYPE_KR ||
5724 pi->port_type == FW_PORT_TYPE_BP_AP ||
5725 pi->port_type == FW_PORT_TYPE_BP4_AP ||
5726 pi->port_type == FW_PORT_TYPE_BP40_BA ||
5727 pi->port_type == FW_PORT_TYPE_KR4_100G ||
5728 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
5729 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
5733 build_medialist(struct port_info *pi)
5736 int unknown, mword, bit;
5737 struct link_config *lc;
5738 struct ifmedia *ifm;
5740 PORT_LOCK_ASSERT_OWNED(pi);
5742 if (pi->flags & FIXED_IFMEDIA)
5746 * Rebuild the ifmedia list.
5749 ifmedia_removeall(ifm);
5751 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
5752 if (__predict_false(ss == 0)) { /* not supposed to happen. */
5755 MPASS(LIST_EMPTY(&ifm->ifm_list));
5756 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
5757 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
5762 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
5764 MPASS(speed & M_FW_PORT_CAP32_SPEED);
5766 mword = port_mword(pi, speed);
5767 if (mword == IFM_NONE) {
5769 } else if (mword == IFM_UNKNOWN)
5772 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
5775 if (unknown > 0) /* Add one unknown for all unknown media types. */
5776 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
5777 if (lc->pcaps & FW_PORT_CAP32_ANEG)
5778 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
5780 set_current_media(pi);
5784 * Initialize the requested fields in the link config based on driver tunables.
5787 init_link_config(struct port_info *pi)
5789 struct link_config *lc = &pi->link_cfg;
5791 PORT_LOCK_ASSERT_OWNED(pi);
5793 lc->requested_caps = 0;
5794 lc->requested_speed = 0;
5796 if (t4_autoneg == 0)
5797 lc->requested_aneg = AUTONEG_DISABLE;
5798 else if (t4_autoneg == 1)
5799 lc->requested_aneg = AUTONEG_ENABLE;
5801 lc->requested_aneg = AUTONEG_AUTO;
5803 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
5806 if (t4_fec & FEC_AUTO)
5807 lc->requested_fec = FEC_AUTO;
5808 else if (t4_fec == 0)
5809 lc->requested_fec = FEC_NONE;
5811 /* -1 is handled by the FEC_AUTO block above and not here. */
5812 lc->requested_fec = t4_fec &
5813 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
5814 if (lc->requested_fec == 0)
5815 lc->requested_fec = FEC_AUTO;
5817 if (t4_force_fec < 0)
5819 else if (t4_force_fec > 0)
5826 * Makes sure that all requested settings comply with what's supported by the
5827 * port. Returns the number of settings that were invalid and had to be fixed.
5830 fixup_link_config(struct port_info *pi)
5833 struct link_config *lc = &pi->link_cfg;
5836 PORT_LOCK_ASSERT_OWNED(pi);
5838 /* Speed (when not autonegotiating) */
5839 if (lc->requested_speed != 0) {
5840 fwspeed = speed_to_fwcap(lc->requested_speed);
5841 if ((fwspeed & lc->pcaps) == 0) {
5843 lc->requested_speed = 0;
5847 /* Link autonegotiation */
5848 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
5849 lc->requested_aneg == AUTONEG_DISABLE ||
5850 lc->requested_aneg == AUTONEG_AUTO);
5851 if (lc->requested_aneg == AUTONEG_ENABLE &&
5852 !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
5854 lc->requested_aneg = AUTONEG_AUTO;
5858 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
5859 if (lc->requested_fc & PAUSE_TX &&
5860 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
5862 lc->requested_fc &= ~PAUSE_TX;
5864 if (lc->requested_fc & PAUSE_RX &&
5865 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
5867 lc->requested_fc &= ~PAUSE_RX;
5869 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
5870 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
5872 lc->requested_fc |= PAUSE_AUTONEG;
5876 if ((lc->requested_fec & FEC_RS &&
5877 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
5878 (lc->requested_fec & FEC_BASER_RS &&
5879 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
5881 lc->requested_fec = FEC_AUTO;
5888 * Apply the requested L1 settings, which are expected to be valid, to the
5892 apply_link_config(struct port_info *pi)
5894 struct adapter *sc = pi->adapter;
5895 struct link_config *lc = &pi->link_cfg;
5899 ASSERT_SYNCHRONIZED_OP(sc);
5900 PORT_LOCK_ASSERT_OWNED(pi);
5902 if (lc->requested_aneg == AUTONEG_ENABLE)
5903 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
5904 if (!(lc->requested_fc & PAUSE_AUTONEG))
5905 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
5906 if (lc->requested_fc & PAUSE_TX)
5907 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
5908 if (lc->requested_fc & PAUSE_RX)
5909 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
5910 if (lc->requested_fec & FEC_RS)
5911 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
5912 if (lc->requested_fec & FEC_BASER_RS)
5913 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
5915 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5917 /* Don't complain if the VF driver gets back an EPERM. */
5918 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
5919 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
5922 * An L1_CFG will almost always result in a link-change event if
5923 * the link is up, and the driver will refresh the actual
5924 * fec/fc/etc. when the notification is processed. If the link
5925 * is down then the actual settings are meaningless.
5927 * This takes care of the case where a change in the L1 settings
5928 * may not result in a notification.
5930 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
5931 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
5936 #define FW_MAC_EXACT_CHUNK 7
5939 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
5947 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
5949 struct mcaddr_ctx *ctx = arg;
5950 struct vi_info *vi = ctx->ifp->if_softc;
5951 struct port_info *pi = vi->pi;
5952 struct adapter *sc = pi->adapter;
5957 ctx->mcaddr[ctx->i] = LLADDR(sdl);
5958 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
5961 if (ctx->i == FW_MAC_EXACT_CHUNK) {
5962 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
5963 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
5967 for (j = 0; j < ctx->i; j++) {
5969 "failed to add mc address"
5971 "%02x:%02x:%02x rc=%d\n",
5972 ctx->mcaddr[j][0], ctx->mcaddr[j][1],
5973 ctx->mcaddr[j][2], ctx->mcaddr[j][3],
5974 ctx->mcaddr[j][4], ctx->mcaddr[j][5],
5987 * Program the port's XGMAC based on parameters in ifnet. The caller also
5988 * indicates which parameters should be programmed (the rest are left alone).
5991 update_mac_settings(struct ifnet *ifp, int flags)
5994 struct vi_info *vi = ifp->if_softc;
5995 struct port_info *pi = vi->pi;
5996 struct adapter *sc = pi->adapter;
5997 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
5998 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
6000 ASSERT_SYNCHRONIZED_OP(sc);
6001 KASSERT(flags, ("%s: not told what to update.", __func__));
6003 if (flags & XGMAC_MTU)
6006 if (flags & XGMAC_PROMISC)
6007 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
6009 if (flags & XGMAC_ALLMULTI)
6010 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
6012 if (flags & XGMAC_VLANEX)
6013 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
6015 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
6016 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
6017 allmulti, 1, vlanex, false);
6019 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
6025 if (flags & XGMAC_UCADDR) {
6026 uint8_t ucaddr[ETHER_ADDR_LEN];
6028 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
6029 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
6030 ucaddr, true, &vi->smt_idx);
6033 if_printf(ifp, "change_mac failed: %d\n", rc);
6036 vi->xact_addr_filt = rc;
6041 if (flags & XGMAC_MCADDRS) {
6042 struct epoch_tracker et;
6043 struct mcaddr_ctx ctx;
6052 * Unlike other drivers, we accumulate list of pointers into
6053 * interface address lists and we need to keep it safe even
6054 * after if_foreach_llmaddr() returns, thus we must enter the
6057 NET_EPOCH_ENTER(et);
6058 if_foreach_llmaddr(ifp, add_maddr, &ctx);
6065 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
6066 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
6070 for (j = 0; j < ctx.i; j++) {
6072 "failed to add mcast address"
6074 "%02x:%02x:%02x rc=%d\n",
6075 ctx.mcaddr[j][0], ctx.mcaddr[j][1],
6076 ctx.mcaddr[j][2], ctx.mcaddr[j][3],
6077 ctx.mcaddr[j][4], ctx.mcaddr[j][5],
6086 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
6088 if_printf(ifp, "failed to set mcast address hash: %d\n",
6091 /* We clobbered the VXLAN entry if there was one. */
6092 pi->vxlan_tcam_entry = false;
6096 if (IS_MAIN_VI(vi) && sc->vxlan_refcount > 0 &&
6097 pi->vxlan_tcam_entry == false) {
6098 rc = t4_alloc_raw_mac_filt(sc, vi->viid, match_all_mac,
6099 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
6103 if_printf(ifp, "failed to add VXLAN TCAM entry: %d.\n",
6106 MPASS(rc == sc->rawf_base + pi->port_id);
6108 pi->vxlan_tcam_entry = true;
6116 * {begin|end}_synchronized_op must be called from the same thread.
6119 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
6125 /* the caller thinks it's ok to sleep, but is it really? */
6126 if (flags & SLEEP_OK)
6127 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
6128 "begin_synchronized_op");
6139 if (vi && IS_DOOMED(vi)) {
6149 if (!(flags & SLEEP_OK)) {
6154 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
6160 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
6163 sc->last_op = wmesg;
6164 sc->last_op_thr = curthread;
6165 sc->last_op_flags = flags;
6169 if (!(flags & HOLD_LOCK) || rc)
6176 * Tell if_ioctl and if_init that the VI is going away. This is
6177 * special variant of begin_synchronized_op and must be paired with a
6178 * call to end_synchronized_op.
6181 doom_vi(struct adapter *sc, struct vi_info *vi)
6188 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
6191 sc->last_op = "t4detach";
6192 sc->last_op_thr = curthread;
6193 sc->last_op_flags = 0;
6199 * {begin|end}_synchronized_op must be called from the same thread.
6202 end_synchronized_op(struct adapter *sc, int flags)
6205 if (flags & LOCK_HELD)
6206 ADAPTER_LOCK_ASSERT_OWNED(sc);
6210 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
6217 cxgbe_init_synchronized(struct vi_info *vi)
6219 struct port_info *pi = vi->pi;
6220 struct adapter *sc = pi->adapter;
6221 struct ifnet *ifp = vi->ifp;
6223 struct sge_txq *txq;
6225 ASSERT_SYNCHRONIZED_OP(sc);
6227 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6228 return (0); /* already running */
6230 if (!(sc->flags & FULL_INIT_DONE) && ((rc = adapter_init(sc)) != 0))
6231 return (rc); /* error message displayed already */
6233 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
6234 return (rc); /* error message displayed already */
6236 rc = update_mac_settings(ifp, XGMAC_ALL);
6238 goto done; /* error message displayed already */
6241 if (pi->up_vis == 0) {
6242 t4_update_port_info(pi);
6243 fixup_link_config(pi);
6244 build_medialist(pi);
6245 apply_link_config(pi);
6248 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
6250 if_printf(ifp, "enable_vi failed: %d\n", rc);
6256 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
6260 for_each_txq(vi, i, txq) {
6262 txq->eq.flags |= EQ_ENABLED;
6267 * The first iq of the first port to come up is used for tracing.
6269 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
6270 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
6271 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
6272 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
6273 V_QUEUENUMBER(sc->traceq));
6274 pi->flags |= HAS_TRACEQ;
6279 ifp->if_drv_flags |= IFF_DRV_RUNNING;
6280 if (pi->link_cfg.link_ok)
6281 t4_os_link_changed(pi);
6284 mtx_lock(&vi->tick_mtx);
6285 if (ifp->if_get_counter == vi_get_counter)
6286 callout_reset(&vi->tick, hz, vi_tick, vi);
6288 callout_reset(&vi->tick, hz, cxgbe_tick, vi);
6289 mtx_unlock(&vi->tick_mtx);
6292 cxgbe_uninit_synchronized(vi);
6301 cxgbe_uninit_synchronized(struct vi_info *vi)
6303 struct port_info *pi = vi->pi;
6304 struct adapter *sc = pi->adapter;
6305 struct ifnet *ifp = vi->ifp;
6307 struct sge_txq *txq;
6309 ASSERT_SYNCHRONIZED_OP(sc);
6311 if (!(vi->flags & VI_INIT_DONE)) {
6312 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
6313 KASSERT(0, ("uninited VI is running"));
6314 if_printf(ifp, "uninited VI with running ifnet. "
6315 "vi->flags 0x%016lx, if_flags 0x%08x, "
6316 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
6323 * Disable the VI so that all its data in either direction is discarded
6324 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
6325 * tick) intact as the TP can deliver negative advice or data that it's
6326 * holding in its RAM (for an offloaded connection) even after the VI is
6329 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
6331 if_printf(ifp, "disable_vi failed: %d\n", rc);
6335 for_each_txq(vi, i, txq) {
6337 txq->eq.flags &= ~EQ_ENABLED;
6341 mtx_lock(&vi->tick_mtx);
6342 callout_stop(&vi->tick);
6343 mtx_unlock(&vi->tick_mtx);
6346 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
6350 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
6352 if (pi->up_vis > 0) {
6357 pi->link_cfg.link_ok = false;
6358 pi->link_cfg.speed = 0;
6359 pi->link_cfg.link_down_rc = 255;
6360 t4_os_link_changed(pi);
6367 * It is ok for this function to fail midway and return right away. t4_detach
6368 * will walk the entire sc->irq list and clean up whatever is valid.
6371 t4_setup_intr_handlers(struct adapter *sc)
6373 int rc, rid, p, q, v;
6376 struct port_info *pi;
6378 struct sge *sge = &sc->sge;
6379 struct sge_rxq *rxq;
6381 struct sge_ofld_rxq *ofld_rxq;
6384 struct sge_nm_rxq *nm_rxq;
6387 int nbuckets = rss_getnumbuckets();
6394 rid = sc->intr_type == INTR_INTX ? 0 : 1;
6395 if (forwarding_intr_to_fwq(sc))
6396 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
6398 /* Multiple interrupts. */
6399 if (sc->flags & IS_VF)
6400 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6401 ("%s: too few intr.", __func__));
6403 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6404 ("%s: too few intr.", __func__));
6406 /* The first one is always error intr on PFs */
6407 if (!(sc->flags & IS_VF)) {
6408 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
6415 /* The second one is always the firmware event queue (first on VFs) */
6416 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
6422 for_each_port(sc, p) {
6424 for_each_vi(pi, v, vi) {
6425 vi->first_intr = rid - 1;
6427 if (vi->nnmrxq > 0) {
6428 int n = max(vi->nrxq, vi->nnmrxq);
6430 rxq = &sge->rxq[vi->first_rxq];
6432 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
6434 for (q = 0; q < n; q++) {
6435 snprintf(s, sizeof(s), "%x%c%x", p,
6441 irq->nm_rxq = nm_rxq++;
6443 if (irq->nm_rxq != NULL &&
6445 /* Netmap rx only */
6446 rc = t4_alloc_irq(sc, irq, rid,
6447 t4_nm_intr, irq->nm_rxq, s);
6449 if (irq->nm_rxq != NULL &&
6451 /* NIC and Netmap rx */
6452 rc = t4_alloc_irq(sc, irq, rid,
6453 t4_vi_intr, irq, s);
6456 if (irq->rxq != NULL &&
6457 irq->nm_rxq == NULL) {
6459 rc = t4_alloc_irq(sc, irq, rid,
6460 t4_intr, irq->rxq, s);
6466 bus_bind_intr(sc->dev, irq->res,
6467 rss_getcpu(q % nbuckets));
6475 for_each_rxq(vi, q, rxq) {
6476 snprintf(s, sizeof(s), "%x%c%x", p,
6478 rc = t4_alloc_irq(sc, irq, rid,
6483 bus_bind_intr(sc->dev, irq->res,
6484 rss_getcpu(q % nbuckets));
6492 for_each_ofld_rxq(vi, q, ofld_rxq) {
6493 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
6494 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
6505 MPASS(irq == &sc->irq[sc->intr_count]);
6511 write_global_rss_key(struct adapter *sc)
6515 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
6516 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
6518 CTASSERT(RSS_KEYSIZE == 40);
6520 rss_getkey((void *)&raw_rss_key[0]);
6521 for (i = 0; i < nitems(rss_key); i++) {
6522 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
6524 t4_write_rss_key(sc, &rss_key[0], -1, 1);
6532 adapter_full_init(struct adapter *sc)
6536 ASSERT_SYNCHRONIZED_OP(sc);
6539 * queues that belong to the adapter (not any particular port).
6541 rc = t4_setup_adapter_queues(sc);
6545 for (i = 0; i < nitems(sc->tq); i++) {
6546 if (sc->tq[i] != NULL)
6548 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
6549 taskqueue_thread_enqueue, &sc->tq[i]);
6550 if (sc->tq[i] == NULL) {
6551 CH_ERR(sc, "failed to allocate task queue %d\n", i);
6554 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
6555 device_get_nameunit(sc->dev), i);
6558 if (!(sc->flags & IS_VF)) {
6559 write_global_rss_key(sc);
6566 adapter_init(struct adapter *sc)
6570 ASSERT_SYNCHRONIZED_OP(sc);
6571 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
6572 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
6573 ("%s: FULL_INIT_DONE already", __func__));
6575 rc = adapter_full_init(sc);
6577 adapter_full_uninit(sc);
6579 sc->flags |= FULL_INIT_DONE;
6588 adapter_full_uninit(struct adapter *sc)
6592 t4_teardown_adapter_queues(sc);
6594 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
6595 taskqueue_free(sc->tq[i]);
6599 sc->flags &= ~FULL_INIT_DONE;
6603 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
6604 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
6605 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
6606 RSS_HASHTYPE_RSS_UDP_IPV6)
6608 /* Translates kernel hash types to hardware. */
6610 hashconfig_to_hashen(int hashconfig)
6614 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
6615 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
6616 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
6617 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
6618 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
6619 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
6620 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
6622 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
6623 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
6624 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
6626 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
6627 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
6628 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
6629 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
6634 /* Translates hardware hash types to kernel. */
6636 hashen_to_hashconfig(int hashen)
6640 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
6642 * If UDP hashing was enabled it must have been enabled for
6643 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
6644 * enabling any 4-tuple hash is nonsense configuration.
6646 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
6647 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
6649 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6650 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
6651 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6652 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
6654 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
6655 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
6656 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
6657 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
6658 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
6659 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
6660 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
6661 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
6663 return (hashconfig);
6671 vi_full_init(struct vi_info *vi)
6673 struct adapter *sc = vi->adapter;
6674 struct sge_rxq *rxq;
6677 int nbuckets = rss_getnumbuckets();
6678 int hashconfig = rss_gethashconfig();
6682 ASSERT_SYNCHRONIZED_OP(sc);
6685 * Allocate tx/rx/fl queues for this VI.
6687 rc = t4_setup_vi_queues(vi);
6692 * Setup RSS for this VI. Save a copy of the RSS table for later use.
6694 if (vi->nrxq > vi->rss_size) {
6695 CH_ALERT(vi, "nrxq (%d) > hw RSS table size (%d); "
6696 "some queues will never receive traffic.\n", vi->nrxq,
6698 } else if (vi->rss_size % vi->nrxq) {
6699 CH_ALERT(vi, "nrxq (%d), hw RSS table size (%d); "
6700 "expect uneven traffic distribution.\n", vi->nrxq,
6704 if (vi->nrxq != nbuckets) {
6705 CH_ALERT(vi, "nrxq (%d) != kernel RSS buckets (%d);"
6706 "performance will be impacted.\n", vi->nrxq, nbuckets);
6709 if (vi->rss == NULL)
6710 vi->rss = malloc(vi->rss_size * sizeof (*vi->rss), M_CXGBE,
6712 for (i = 0; i < vi->rss_size;) {
6714 j = rss_get_indirection_to_bucket(i);
6716 rxq = &sc->sge.rxq[vi->first_rxq + j];
6717 vi->rss[i++] = rxq->iq.abs_id;
6719 for_each_rxq(vi, j, rxq) {
6720 vi->rss[i++] = rxq->iq.abs_id;
6721 if (i == vi->rss_size)
6727 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
6728 vi->rss, vi->rss_size);
6730 CH_ERR(vi, "rss_config failed: %d\n", rc);
6735 vi->hashen = hashconfig_to_hashen(hashconfig);
6738 * We may have had to enable some hashes even though the global config
6739 * wants them disabled. This is a potential problem that must be
6740 * reported to the user.
6742 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
6745 * If we consider only the supported hash types, then the enabled hashes
6746 * are a superset of the requested hashes. In other words, there cannot
6747 * be any supported hash that was requested but not enabled, but there
6748 * can be hashes that were not requested but had to be enabled.
6750 extra &= SUPPORTED_RSS_HASHTYPES;
6751 MPASS((extra & hashconfig) == 0);
6755 "global RSS config (0x%x) cannot be accommodated.\n",
6758 if (extra & RSS_HASHTYPE_RSS_IPV4)
6759 CH_ALERT(vi, "IPv4 2-tuple hashing forced on.\n");
6760 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
6761 CH_ALERT(vi, "TCP/IPv4 4-tuple hashing forced on.\n");
6762 if (extra & RSS_HASHTYPE_RSS_IPV6)
6763 CH_ALERT(vi, "IPv6 2-tuple hashing forced on.\n");
6764 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
6765 CH_ALERT(vi, "TCP/IPv6 4-tuple hashing forced on.\n");
6766 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
6767 CH_ALERT(vi, "UDP/IPv4 4-tuple hashing forced on.\n");
6768 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
6769 CH_ALERT(vi, "UDP/IPv6 4-tuple hashing forced on.\n");
6771 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
6772 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
6773 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
6774 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
6776 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0],
6779 CH_ERR(vi, "rss hash/defaultq config failed: %d\n", rc);
6787 vi_init(struct vi_info *vi)
6791 ASSERT_SYNCHRONIZED_OP(vi->adapter);
6792 KASSERT((vi->flags & VI_INIT_DONE) == 0,
6793 ("%s: VI_INIT_DONE already", __func__));
6795 rc = vi_full_init(vi);
6799 vi->flags |= VI_INIT_DONE;
6808 vi_full_uninit(struct vi_info *vi)
6811 if (vi->flags & VI_INIT_DONE) {
6813 free(vi->rss, M_CXGBE);
6814 free(vi->nm_rss, M_CXGBE);
6817 t4_teardown_vi_queues(vi);
6818 vi->flags &= ~VI_INIT_DONE;
6822 quiesce_txq(struct sge_txq *txq)
6824 struct sge_eq *eq = &txq->eq;
6825 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6827 MPASS(eq->flags & EQ_SW_ALLOCATED);
6828 MPASS(!(eq->flags & EQ_ENABLED));
6830 /* Wait for the mp_ring to empty. */
6831 while (!mp_ring_is_idle(txq->r)) {
6832 mp_ring_check_drainage(txq->r, 4096);
6833 pause("rquiesce", 1);
6835 MPASS(txq->txp.npkt == 0);
6837 if (eq->flags & EQ_HW_ALLOCATED) {
6839 * Hardware is alive and working normally. Wait for it to
6840 * finish and then wait for the driver to catch up and reclaim
6843 while (spg->cidx != htobe16(eq->pidx))
6844 pause("equiesce", 1);
6845 while (eq->cidx != eq->pidx)
6846 pause("dquiesce", 1);
6849 * Hardware is unavailable. Discard all pending tx and reclaim
6850 * descriptors directly.
6853 while (eq->cidx != eq->pidx) {
6854 struct mbuf *m, *nextpkt;
6855 struct tx_sdesc *txsd;
6857 txsd = &txq->sdesc[eq->cidx];
6858 for (m = txsd->m; m != NULL; m = nextpkt) {
6859 nextpkt = m->m_nextpkt;
6860 m->m_nextpkt = NULL;
6863 IDXINCR(eq->cidx, txsd->desc_used, eq->sidx);
6865 spg->pidx = spg->cidx = htobe16(eq->cidx);
6871 quiesce_wrq(struct sge_wrq *wrq)
6878 quiesce_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
6880 /* Synchronize with the interrupt handler */
6881 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
6885 MPASS(iq->flags & IQ_HAS_FL);
6887 mtx_lock(&sc->sfl_lock);
6889 fl->flags |= FL_DOOMED;
6891 callout_stop(&sc->sfl_callout);
6892 mtx_unlock(&sc->sfl_lock);
6894 KASSERT((fl->flags & FL_STARVING) == 0,
6895 ("%s: still starving", __func__));
6897 /* Release all buffers if hardware is no longer available. */
6898 if (!(iq->flags & IQ_HW_ALLOCATED))
6899 free_fl_buffers(sc, fl);
6904 * Wait for all activity on all the queues of the VI to complete. It is assumed
6905 * that no new work is being enqueued by the hardware or the driver. That part
6906 * should be arranged before calling this function.
6909 quiesce_vi(struct vi_info *vi)
6912 struct adapter *sc = vi->adapter;
6913 struct sge_rxq *rxq;
6914 struct sge_txq *txq;
6916 struct sge_ofld_rxq *ofld_rxq;
6918 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6919 struct sge_ofld_txq *ofld_txq;
6922 if (!(vi->flags & VI_INIT_DONE))
6925 for_each_txq(vi, i, txq) {
6929 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6930 for_each_ofld_txq(vi, i, ofld_txq) {
6931 quiesce_wrq(&ofld_txq->wrq);
6935 for_each_rxq(vi, i, rxq) {
6936 quiesce_iq_fl(sc, &rxq->iq, &rxq->fl);
6940 for_each_ofld_rxq(vi, i, ofld_rxq) {
6941 quiesce_iq_fl(sc, &ofld_rxq->iq, &ofld_rxq->fl);
6947 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
6948 driver_intr_t *handler, void *arg, char *name)
6953 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
6954 RF_SHAREABLE | RF_ACTIVE);
6955 if (irq->res == NULL) {
6956 device_printf(sc->dev,
6957 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
6961 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
6962 NULL, handler, arg, &irq->tag);
6964 device_printf(sc->dev,
6965 "failed to setup interrupt for rid %d, name %s: %d\n",
6968 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
6974 t4_free_irq(struct adapter *sc, struct irq *irq)
6977 bus_teardown_intr(sc->dev, irq->res, irq->tag);
6979 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
6981 bzero(irq, sizeof(*irq));
6987 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
6990 regs->version = chip_id(sc) | chip_rev(sc) << 10;
6991 t4_get_regs(sc, buf, regs->len);
6994 #define A_PL_INDIR_CMD 0x1f8
6996 #define S_PL_AUTOINC 31
6997 #define M_PL_AUTOINC 0x1U
6998 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
6999 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
7001 #define S_PL_VFID 20
7002 #define M_PL_VFID 0xffU
7003 #define V_PL_VFID(x) ((x) << S_PL_VFID)
7004 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
7007 #define M_PL_ADDR 0xfffffU
7008 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
7009 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
7011 #define A_PL_INDIR_DATA 0x1fc
7014 read_vf_stat(struct adapter *sc, u_int vin, int reg)
7018 if (sc->flags & IS_VF) {
7019 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
7020 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
7022 mtx_assert(&sc->reg_lock, MA_OWNED);
7023 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
7024 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
7025 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
7026 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
7028 return (((uint64_t)stats[1]) << 32 | stats[0]);
7032 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
7035 #define GET_STAT(name) \
7036 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
7038 if (!(sc->flags & IS_VF))
7039 mtx_lock(&sc->reg_lock);
7040 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
7041 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
7042 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
7043 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
7044 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
7045 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
7046 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
7047 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
7048 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
7049 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
7050 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
7051 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
7052 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
7053 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
7054 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
7055 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
7056 if (!(sc->flags & IS_VF))
7057 mtx_unlock(&sc->reg_lock);
7063 t4_clr_vi_stats(struct adapter *sc, u_int vin)
7067 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
7068 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
7069 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
7070 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
7071 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
7075 vi_refresh_stats(struct vi_info *vi)
7078 const struct timeval interval = {0, 250000}; /* 250ms */
7080 mtx_assert(&vi->tick_mtx, MA_OWNED);
7082 if (vi->flags & VI_SKIP_STATS)
7086 timevalsub(&tv, &interval);
7087 if (timevalcmp(&tv, &vi->last_refreshed, <))
7090 t4_get_vi_stats(vi->adapter, vi->vin, &vi->stats);
7091 getmicrotime(&vi->last_refreshed);
7095 cxgbe_refresh_stats(struct vi_info *vi)
7097 u_int i, v, tnl_cong_drops, chan_map;
7099 const struct timeval interval = {0, 250000}; /* 250ms */
7100 struct port_info *pi;
7103 mtx_assert(&vi->tick_mtx, MA_OWNED);
7105 if (vi->flags & VI_SKIP_STATS)
7109 timevalsub(&tv, &interval);
7110 if (timevalcmp(&tv, &vi->last_refreshed, <))
7116 t4_get_port_stats(sc, pi->port_id, &pi->stats);
7117 chan_map = pi->rx_e_chan_map;
7119 i = ffs(chan_map) - 1;
7120 mtx_lock(&sc->reg_lock);
7121 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
7122 A_TP_MIB_TNL_CNG_DROP_0 + i);
7123 mtx_unlock(&sc->reg_lock);
7124 tnl_cong_drops += v;
7125 chan_map &= ~(1 << i);
7127 pi->tnl_cong_drops = tnl_cong_drops;
7128 getmicrotime(&vi->last_refreshed);
7132 cxgbe_tick(void *arg)
7134 struct vi_info *vi = arg;
7136 MPASS(IS_MAIN_VI(vi));
7137 mtx_assert(&vi->tick_mtx, MA_OWNED);
7139 cxgbe_refresh_stats(vi);
7140 callout_schedule(&vi->tick, hz);
7146 struct vi_info *vi = arg;
7148 mtx_assert(&vi->tick_mtx, MA_OWNED);
7150 vi_refresh_stats(vi);
7151 callout_schedule(&vi->tick, hz);
7155 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
7157 static char *caps_decoder[] = {
7158 "\20\001IPMI\002NCSI", /* 0: NBM */
7159 "\20\001PPP\002QFC\003DCBX", /* 1: link */
7160 "\20\001INGRESS\002EGRESS", /* 2: switch */
7161 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
7162 "\006HASHFILTER\007ETHOFLD",
7163 "\20\001TOE", /* 4: TOE */
7164 "\20\001RDDP\002RDMAC", /* 5: RDMA */
7165 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
7166 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
7167 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
7169 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
7170 "\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE" /* 7: Crypto */
7172 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
7173 "\004PO_INITIATOR\005PO_TARGET",
7177 t4_sysctls(struct adapter *sc)
7179 struct sysctl_ctx_list *ctx = &sc->ctx;
7180 struct sysctl_oid *oid;
7181 struct sysctl_oid_list *children, *c0;
7182 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
7187 oid = device_get_sysctl_tree(sc->dev);
7188 c0 = children = SYSCTL_CHILDREN(oid);
7190 sc->sc_do_rxcopy = 1;
7191 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
7192 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
7194 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7195 sc->params.nports, "# of ports");
7197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
7198 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, doorbells,
7199 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
7200 "available doorbells");
7202 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
7203 sc->params.vpd.cclk, "core clock frequency (in KHz)");
7205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
7206 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7207 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
7208 sysctl_int_array, "A", "interrupt holdoff timer values (us)");
7210 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
7211 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
7212 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
7213 sysctl_int_array, "A", "interrupt holdoff packet counter values");
7215 t4_sge_sysctls(sc, ctx, children);
7217 sc->lro_timeout = 100;
7218 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
7219 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
7221 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
7222 &sc->debug_flags, 0, "flags to enable runtime debugging");
7224 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
7225 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
7227 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
7228 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
7230 if (sc->flags & IS_VF)
7233 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
7234 NULL, chip_rev(sc), "chip hardware revision");
7236 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
7237 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
7239 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
7240 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
7242 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
7243 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
7245 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
7246 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
7248 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
7249 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
7251 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
7252 sc->er_version, 0, "expansion ROM version");
7254 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
7255 sc->bs_version, 0, "bootstrap firmware version");
7257 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
7258 NULL, sc->params.scfg_vers, "serial config version");
7260 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
7261 NULL, sc->params.vpd_vers, "VPD version");
7263 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
7264 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
7266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
7267 sc->cfcsum, "config file checksum");
7269 #define SYSCTL_CAP(name, n, text) \
7270 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
7271 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, caps_decoder[n], \
7272 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
7273 "available " text " capabilities")
7275 SYSCTL_CAP(nbmcaps, 0, "NBM");
7276 SYSCTL_CAP(linkcaps, 1, "link");
7277 SYSCTL_CAP(switchcaps, 2, "switch");
7278 SYSCTL_CAP(niccaps, 3, "NIC");
7279 SYSCTL_CAP(toecaps, 4, "TCP offload");
7280 SYSCTL_CAP(rdmacaps, 5, "RDMA");
7281 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
7282 SYSCTL_CAP(cryptocaps, 7, "crypto");
7283 SYSCTL_CAP(fcoecaps, 8, "FCoE");
7286 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
7287 NULL, sc->tids.nftids, "number of filters");
7289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7290 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7291 sysctl_temperature, "I", "chip temperature (in Celsius)");
7292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
7293 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7294 sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
7296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg",
7297 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7298 sysctl_loadavg, "A",
7299 "microprocessor load averages (debug firmwares only)");
7301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
7302 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
7303 "I", "core Vdd (in mV)");
7305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
7306 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, LOCAL_CPUS,
7307 sysctl_cpus, "A", "local CPUs");
7309 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
7310 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, INTR_CPUS,
7311 sysctl_cpus, "A", "preferred CPUs for interrupts");
7313 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
7314 &sc->swintr, 0, "software triggered interrupts");
7316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset",
7317 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_reset, "I",
7318 "1 = reset adapter, 0 = zero reset counter");
7321 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
7323 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
7324 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
7325 "logs and miscellaneous information");
7326 children = SYSCTL_CHILDREN(oid);
7328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
7329 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7330 sysctl_cctrl, "A", "congestion control");
7332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
7333 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7334 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
7336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
7337 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
7338 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
7340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
7341 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
7342 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
7344 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
7345 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3,
7346 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
7348 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
7349 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4,
7350 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
7352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
7353 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5,
7354 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
7356 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
7357 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7358 sysctl_cim_la, "A", "CIM logic analyzer");
7360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
7361 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7362 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
7364 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
7365 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7366 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
7368 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
7369 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7370 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
7372 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
7373 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7374 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
7376 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
7377 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7378 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
7380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
7381 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7382 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
7384 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
7385 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7386 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
7388 if (chip_id(sc) > CHELSIO_T4) {
7389 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
7390 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7391 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
7392 "CIM OBQ 6 (SGE0-RX)");
7394 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
7395 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7396 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
7397 "CIM OBQ 7 (SGE1-RX)");
7400 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
7401 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7402 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
7404 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
7405 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7406 sysctl_cim_qcfg, "A", "CIM queue configuration");
7408 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
7409 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7410 sysctl_cpl_stats, "A", "CPL statistics");
7412 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
7413 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7414 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
7416 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tid_stats",
7417 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7418 sysctl_tid_stats, "A", "tid stats");
7420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
7421 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7422 sysctl_devlog, "A", "firmware's device log");
7424 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
7425 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7426 sysctl_fcoe_stats, "A", "FCoE statistics");
7428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
7429 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7430 sysctl_hw_sched, "A", "hardware scheduler ");
7432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
7433 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7434 sysctl_l2t, "A", "hardware L2 table");
7436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
7437 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7438 sysctl_smt, "A", "hardware source MAC table");
7441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
7442 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7443 sysctl_clip, "A", "active CLIP table entries");
7446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
7447 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7448 sysctl_lb_stats, "A", "loopback statistics");
7450 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
7451 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7452 sysctl_meminfo, "A", "memory regions");
7454 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
7455 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7456 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
7457 "A", "MPS TCAM entries");
7459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
7460 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7461 sysctl_path_mtus, "A", "path MTUs");
7463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
7464 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7465 sysctl_pm_stats, "A", "PM statistics");
7467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
7468 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7469 sysctl_rdma_stats, "A", "RDMA statistics");
7471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
7472 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7473 sysctl_tcp_stats, "A", "TCP statistics");
7475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
7476 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7477 sysctl_tids, "A", "TID information");
7479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
7480 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7481 sysctl_tp_err_stats, "A", "TP error statistics");
7483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tnl_stats",
7484 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7485 sysctl_tnl_stats, "A", "TP tunnel statistics");
7487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
7488 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7489 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
7491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
7492 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7493 sysctl_tp_la, "A", "TP logic analyzer");
7495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
7496 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7497 sysctl_tx_rate, "A", "Tx rate");
7499 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
7500 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7501 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
7503 if (chip_id(sc) >= CHELSIO_T5) {
7504 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
7505 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7506 sysctl_wcwr_stats, "A", "write combined work requests");
7514 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
7515 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
7516 children = SYSCTL_CHILDREN(oid);
7518 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
7519 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
7520 "keys in work requests (1) or attempt to store TLS keys "
7522 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
7523 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to combine "
7524 "TCB field updates with TLS record work requests.");
7529 if (is_offload(sc)) {
7536 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
7537 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
7538 children = SYSCTL_CHILDREN(oid);
7540 sc->tt.cong_algorithm = -1;
7541 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
7542 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
7543 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
7547 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
7548 &sc->tt.sndbuf, 0, "hardware send buffer");
7551 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
7552 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
7553 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
7554 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
7556 sc->tt.rx_coalesce = -1;
7557 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
7558 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
7561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls", CTLTYPE_INT |
7562 CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, sysctl_tls, "I",
7563 "Inline TLS allowed");
7565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
7566 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7567 sysctl_tls_rx_ports, "I",
7568 "TCP ports that use inline TLS+TOE RX");
7570 sc->tt.tls_rx_timeout = t4_toe_tls_rx_timeout;
7571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_timeout",
7572 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
7573 sysctl_tls_rx_timeout, "I",
7574 "Timeout in seconds to downgrade TLS sockets to plain TOE");
7576 sc->tt.tx_align = -1;
7577 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
7578 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
7580 sc->tt.tx_zcopy = 0;
7581 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
7582 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
7583 "Enable zero-copy aio_write(2)");
7585 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
7586 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7587 "cop_managed_offloading", CTLFLAG_RW,
7588 &sc->tt.cop_managed_offloading, 0,
7589 "COP (Connection Offload Policy) controls all TOE offload");
7591 sc->tt.autorcvbuf_inc = 16 * 1024;
7592 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
7593 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
7594 "autorcvbuf increment");
7596 sc->tt.update_hc_on_pmtu_change = 1;
7597 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7598 "update_hc_on_pmtu_change", CTLFLAG_RW,
7599 &sc->tt.update_hc_on_pmtu_change, 0,
7600 "Update hostcache entry if the PMTU changes");
7603 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "iso", CTLFLAG_RW,
7604 &sc->tt.iso, 0, "Enable iSCSI segmentation offload");
7606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
7607 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7608 sysctl_tp_tick, "A", "TP timer tick (us)");
7610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
7611 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
7612 sysctl_tp_tick, "A", "TCP timestamp tick (us)");
7614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
7615 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
7616 sysctl_tp_tick, "A", "DACK tick (us)");
7618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
7619 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
7620 sysctl_tp_dack_timer, "IU", "DACK timer (us)");
7622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
7623 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7624 A_TP_RXT_MIN, sysctl_tp_timer, "LU",
7625 "Minimum retransmit interval (us)");
7627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
7628 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7629 A_TP_RXT_MAX, sysctl_tp_timer, "LU",
7630 "Maximum retransmit interval (us)");
7632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
7633 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7634 A_TP_PERS_MIN, sysctl_tp_timer, "LU",
7635 "Persist timer min (us)");
7637 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
7638 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7639 A_TP_PERS_MAX, sysctl_tp_timer, "LU",
7640 "Persist timer max (us)");
7642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
7643 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7644 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
7645 "Keepalive idle timer (us)");
7647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
7648 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7649 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
7650 "Keepalive interval timer (us)");
7652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
7653 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7654 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
7656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
7657 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7658 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
7659 "FINWAIT2 timer (us)");
7661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
7662 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7663 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
7664 "Number of SYN retransmissions before abort");
7666 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
7667 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7668 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
7669 "Number of retransmissions before abort");
7671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
7672 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7673 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
7674 "Number of keepalive probes before abort");
7676 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
7677 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
7678 "TOE retransmit backoffs");
7679 children = SYSCTL_CHILDREN(oid);
7680 for (i = 0; i < 16; i++) {
7681 snprintf(s, sizeof(s), "%u", i);
7682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
7683 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7684 i, sysctl_tp_backoff, "IU",
7685 "TOE retransmit backoff");
7692 vi_sysctls(struct vi_info *vi)
7694 struct sysctl_ctx_list *ctx = &vi->ctx;
7695 struct sysctl_oid *oid;
7696 struct sysctl_oid_list *children;
7699 * dev.v?(cxgbe|cxl).X.
7701 oid = device_get_sysctl_tree(vi->dev);
7702 children = SYSCTL_CHILDREN(oid);
7704 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
7705 vi->viid, "VI identifer");
7706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
7707 &vi->nrxq, 0, "# of rx queues");
7708 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
7709 &vi->ntxq, 0, "# of tx queues");
7710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
7711 &vi->first_rxq, 0, "index of first rx queue");
7712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
7713 &vi->first_txq, 0, "index of first tx queue");
7714 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
7715 vi->rss_base, "start of RSS indirection table");
7716 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
7717 vi->rss_size, "size of RSS indirection table");
7719 if (IS_MAIN_VI(vi)) {
7720 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
7721 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7722 sysctl_noflowq, "IU",
7723 "Reserve queue 0 for non-flowid packets");
7726 if (vi->adapter->flags & IS_VF) {
7727 MPASS(vi->flags & TX_USES_VM_WR);
7728 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_vm_wr", CTLFLAG_RD,
7729 NULL, 1, "use VM work requests for transmit");
7731 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_vm_wr",
7732 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7733 sysctl_tx_vm_wr, "I", "use VM work requestes for transmit");
7737 if (vi->nofldrxq != 0) {
7738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
7740 "# of rx queues for offloaded TCP connections");
7741 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
7742 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
7743 "index of first TOE rx queue");
7744 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
7745 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7746 sysctl_holdoff_tmr_idx_ofld, "I",
7747 "holdoff timer index for TOE queues");
7748 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
7749 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7750 sysctl_holdoff_pktc_idx_ofld, "I",
7751 "holdoff packet counter index for TOE queues");
7754 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
7755 if (vi->nofldtxq != 0) {
7756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
7758 "# of tx queues for TOE/ETHOFLD");
7759 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
7760 CTLFLAG_RD, &vi->first_ofld_txq, 0,
7761 "index of first TOE/ETHOFLD tx queue");
7765 if (vi->nnmrxq != 0) {
7766 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
7767 &vi->nnmrxq, 0, "# of netmap rx queues");
7768 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
7769 &vi->nnmtxq, 0, "# of netmap tx queues");
7770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
7771 CTLFLAG_RD, &vi->first_nm_rxq, 0,
7772 "index of first netmap rx queue");
7773 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
7774 CTLFLAG_RD, &vi->first_nm_txq, 0,
7775 "index of first netmap tx queue");
7779 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
7780 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7781 sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
7782 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
7783 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7784 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
7786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
7787 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7788 sysctl_qsize_rxq, "I", "rx queue size");
7789 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
7790 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, 0,
7791 sysctl_qsize_txq, "I", "tx queue size");
7795 cxgbe_sysctls(struct port_info *pi)
7797 struct sysctl_ctx_list *ctx = &pi->ctx;
7798 struct sysctl_oid *oid;
7799 struct sysctl_oid_list *children, *children2;
7800 struct adapter *sc = pi->adapter;
7803 static char *tc_flags = {"\20\1USER"};
7808 oid = device_get_sysctl_tree(pi->dev);
7809 children = SYSCTL_CHILDREN(oid);
7811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
7812 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
7813 sysctl_linkdnrc, "A", "reason why link is down");
7814 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
7815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
7816 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 0,
7817 sysctl_btphy, "I", "PHY temperature (in Celsius)");
7818 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
7819 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, 1,
7820 sysctl_btphy, "I", "PHY firmware version");
7823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
7824 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7825 sysctl_pause_settings, "A",
7826 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
7827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_fec",
7828 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_link_fec, "A",
7829 "FEC in use on the link");
7830 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "requested_fec",
7831 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7832 sysctl_requested_fec, "A",
7833 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
7834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
7835 CTLTYPE_STRING | CTLFLAG_MPSAFE, pi, 0, sysctl_module_fec, "A",
7836 "FEC recommended by the cable/transceiver");
7837 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
7838 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7839 sysctl_autoneg, "I",
7840 "autonegotiation (-1 = not supported)");
7841 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "force_fec",
7842 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, pi, 0,
7843 sysctl_force_fec, "I", "when to use FORCE_FEC bit for link config");
7845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rcaps", CTLFLAG_RD,
7846 &pi->link_cfg.requested_caps, 0, "L1 config requested by driver");
7847 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
7848 &pi->link_cfg.pcaps, 0, "port capabilities");
7849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
7850 &pi->link_cfg.acaps, 0, "advertised capabilities");
7851 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
7852 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
7854 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
7855 port_top_speed(pi), "max speed (in Gbps)");
7856 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
7857 pi->mps_bg_map, "MPS buffer group map");
7858 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
7859 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
7860 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_c_chan", CTLFLAG_RD, NULL,
7861 pi->rx_c_chan, "TP rx c-channel");
7863 if (sc->flags & IS_VF)
7867 * dev.(cxgbe|cxl).X.tc.
7869 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
7870 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
7871 "Tx scheduler traffic classes (cl_rl)");
7872 children2 = SYSCTL_CHILDREN(oid);
7873 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
7874 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
7875 "pktsize for per-flow cl-rl (0 means up to the driver )");
7876 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
7877 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
7878 "burstsize for per-flow cl-rl (0 means up to the driver)");
7879 for (i = 0; i < sc->params.nsched_cls; i++) {
7880 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
7882 snprintf(name, sizeof(name), "%d", i);
7883 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
7884 SYSCTL_CHILDREN(oid), OID_AUTO, name,
7885 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
7886 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "state",
7887 CTLFLAG_RD, &tc->state, 0, "current state");
7888 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
7889 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, tc_flags,
7890 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
7891 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
7892 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
7893 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
7894 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
7895 (pi->port_id << 16) | i, sysctl_tc_params, "A",
7896 "traffic class parameters");
7900 * dev.cxgbe.X.stats.
7902 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
7903 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
7904 children = SYSCTL_CHILDREN(oid);
7905 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
7906 &pi->tx_parse_error, 0,
7907 "# of tx packets with invalid length or # of segments");
7909 #define T4_REGSTAT(name, stat, desc) \
7910 SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
7911 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
7912 (is_t4(sc) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L) : \
7913 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##stat##_L)), \
7914 sysctl_handle_t4_reg64, "QU", desc)
7916 /* We get these from port_stats and they may be stale by up to 1s */
7917 #define T4_PORTSTAT(name, desc) \
7918 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
7919 &pi->stats.name, desc)
7921 T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
7922 T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
7923 T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
7924 T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
7925 T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
7926 T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
7927 T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
7928 T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
7929 T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
7930 T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
7931 T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
7932 T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
7933 T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
7934 T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
7935 T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
7936 T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
7937 T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
7938 T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
7939 T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
7940 T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
7941 T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
7942 T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
7943 T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
7945 T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
7946 T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
7947 T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
7948 T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
7949 T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
7950 T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
7951 T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
7953 T4_PORTSTAT(rx_fcs_err,
7954 "# of frames received with bad FCS since last link up");
7956 T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
7957 "# of frames received with bad FCS");
7959 T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
7960 T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
7961 T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
7962 T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
7963 T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
7964 T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
7965 T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
7966 T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
7967 T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
7968 T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
7969 T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
7970 T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
7971 T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
7972 T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
7973 T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
7974 T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
7975 T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
7976 T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
7977 T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
7979 T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows");
7980 T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows");
7981 T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows");
7982 T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows");
7983 T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets");
7984 T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets");
7985 T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets");
7986 T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets");
7993 sysctl_int_array(SYSCTL_HANDLER_ARGS)
7995 int rc, *i, space = 0;
7998 sbuf_new_for_sysctl(&sb, NULL, 64, req);
7999 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
8001 sbuf_printf(&sb, " ");
8002 sbuf_printf(&sb, "%d", *i);
8005 rc = sbuf_finish(&sb);
8011 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
8016 rc = sysctl_wire_old_buffer(req, 0);
8020 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8024 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
8025 rc = sbuf_finish(sb);
8032 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
8037 rc = sysctl_wire_old_buffer(req, 0);
8041 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8045 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
8046 rc = sbuf_finish(sb);
8053 sysctl_btphy(SYSCTL_HANDLER_ARGS)
8055 struct port_info *pi = arg1;
8057 struct adapter *sc = pi->adapter;
8061 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
8064 if (hw_off_limits(sc))
8067 /* XXX: magic numbers */
8068 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e,
8069 op ? 0x20 : 0xc820, &v);
8071 end_synchronized_op(sc, 0);
8077 rc = sysctl_handle_int(oidp, &v, 0, req);
8082 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
8084 struct vi_info *vi = arg1;
8087 val = vi->rsrv_noflowq;
8088 rc = sysctl_handle_int(oidp, &val, 0, req);
8089 if (rc != 0 || req->newptr == NULL)
8092 if ((val >= 1) && (vi->ntxq > 1))
8093 vi->rsrv_noflowq = 1;
8095 vi->rsrv_noflowq = 0;
8101 sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
8103 struct vi_info *vi = arg1;
8104 struct adapter *sc = vi->adapter;
8107 MPASS(!(sc->flags & IS_VF));
8109 val = vi->flags & TX_USES_VM_WR ? 1 : 0;
8110 rc = sysctl_handle_int(oidp, &val, 0, req);
8111 if (rc != 0 || req->newptr == NULL)
8114 if (val != 0 && val != 1)
8117 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8121 if (hw_off_limits(sc))
8123 else if (vi->ifp->if_drv_flags & IFF_DRV_RUNNING) {
8125 * We don't want parse_pkt to run with one setting (VF or PF)
8126 * and then eth_tx to see a different setting but still use
8127 * stale information calculated by parse_pkt.
8131 struct port_info *pi = vi->pi;
8132 struct sge_txq *txq;
8134 uint8_t npkt = sc->params.max_pkts_per_eth_tx_pkts_wr;
8137 vi->flags |= TX_USES_VM_WR;
8138 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_VM_TSO;
8139 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8140 V_TXPKT_INTF(pi->tx_chan));
8141 if (!(sc->flags & IS_VF))
8144 vi->flags &= ~TX_USES_VM_WR;
8145 vi->ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
8146 ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
8147 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
8148 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
8150 for_each_txq(vi, i, txq) {
8151 txq->cpl_ctrl0 = ctrl0;
8152 txq->txp.max_npkt = npkt;
8155 end_synchronized_op(sc, LOCK_HELD);
8160 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
8162 struct vi_info *vi = arg1;
8163 struct adapter *sc = vi->adapter;
8165 struct sge_rxq *rxq;
8170 rc = sysctl_handle_int(oidp, &idx, 0, req);
8171 if (rc != 0 || req->newptr == NULL)
8174 if (idx < 0 || idx >= SGE_NTIMERS)
8177 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8182 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
8183 for_each_rxq(vi, i, rxq) {
8184 #ifdef atomic_store_rel_8
8185 atomic_store_rel_8(&rxq->iq.intr_params, v);
8187 rxq->iq.intr_params = v;
8192 end_synchronized_op(sc, LOCK_HELD);
8197 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
8199 struct vi_info *vi = arg1;
8200 struct adapter *sc = vi->adapter;
8205 rc = sysctl_handle_int(oidp, &idx, 0, req);
8206 if (rc != 0 || req->newptr == NULL)
8209 if (idx < -1 || idx >= SGE_NCOUNTERS)
8212 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8217 if (vi->flags & VI_INIT_DONE)
8218 rc = EBUSY; /* cannot be changed once the queues are created */
8222 end_synchronized_op(sc, LOCK_HELD);
8227 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
8229 struct vi_info *vi = arg1;
8230 struct adapter *sc = vi->adapter;
8233 qsize = vi->qsize_rxq;
8235 rc = sysctl_handle_int(oidp, &qsize, 0, req);
8236 if (rc != 0 || req->newptr == NULL)
8239 if (qsize < 128 || (qsize & 7))
8242 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8247 if (vi->flags & VI_INIT_DONE)
8248 rc = EBUSY; /* cannot be changed once the queues are created */
8250 vi->qsize_rxq = qsize;
8252 end_synchronized_op(sc, LOCK_HELD);
8257 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
8259 struct vi_info *vi = arg1;
8260 struct adapter *sc = vi->adapter;
8263 qsize = vi->qsize_txq;
8265 rc = sysctl_handle_int(oidp, &qsize, 0, req);
8266 if (rc != 0 || req->newptr == NULL)
8269 if (qsize < 128 || qsize > 65536)
8272 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8277 if (vi->flags & VI_INIT_DONE)
8278 rc = EBUSY; /* cannot be changed once the queues are created */
8280 vi->qsize_txq = qsize;
8282 end_synchronized_op(sc, LOCK_HELD);
8287 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
8289 struct port_info *pi = arg1;
8290 struct adapter *sc = pi->adapter;
8291 struct link_config *lc = &pi->link_cfg;
8294 if (req->newptr == NULL) {
8296 static char *bits = "\20\1RX\2TX\3AUTO";
8298 rc = sysctl_wire_old_buffer(req, 0);
8302 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8307 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
8308 (lc->requested_fc & PAUSE_AUTONEG), bits);
8310 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
8311 PAUSE_RX | PAUSE_AUTONEG), bits);
8313 rc = sbuf_finish(sb);
8319 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
8323 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8329 if (s[0] < '0' || s[0] > '9')
8330 return (EINVAL); /* not a number */
8332 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
8333 return (EINVAL); /* some other bit is set too */
8335 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8339 if (!hw_off_limits(sc)) {
8341 lc->requested_fc = n;
8342 fixup_link_config(pi);
8344 rc = apply_link_config(pi);
8345 set_current_media(pi);
8348 end_synchronized_op(sc, 0);
8355 sysctl_link_fec(SYSCTL_HANDLER_ARGS)
8357 struct port_info *pi = arg1;
8358 struct link_config *lc = &pi->link_cfg;
8361 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2";
8363 rc = sysctl_wire_old_buffer(req, 0);
8367 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8371 sbuf_printf(sb, "%b", lc->fec, bits);
8373 sbuf_printf(sb, "no link");
8374 rc = sbuf_finish(sb);
8381 sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
8383 struct port_info *pi = arg1;
8384 struct adapter *sc = pi->adapter;
8385 struct link_config *lc = &pi->link_cfg;
8389 if (req->newptr == NULL) {
8391 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2"
8392 "\5RSVD3\6auto\7module";
8394 rc = sysctl_wire_old_buffer(req, 0);
8398 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8402 sbuf_printf(sb, "%b", lc->requested_fec, bits);
8403 rc = sbuf_finish(sb);
8409 snprintf(s, sizeof(s), "%d",
8410 lc->requested_fec == FEC_AUTO ? -1 :
8411 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
8413 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
8417 n = strtol(&s[0], NULL, 0);
8418 if (n < 0 || n & FEC_AUTO)
8420 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
8421 return (EINVAL);/* some other bit is set too */
8423 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8428 old = lc->requested_fec;
8430 lc->requested_fec = FEC_AUTO;
8431 else if (n == 0 || n == FEC_NONE)
8432 lc->requested_fec = FEC_NONE;
8435 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
8440 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
8443 if (!hw_off_limits(sc)) {
8444 fixup_link_config(pi);
8445 if (pi->up_vis > 0) {
8446 rc = apply_link_config(pi);
8448 lc->requested_fec = old;
8449 if (rc == FW_EPROTO)
8456 end_synchronized_op(sc, 0);
8463 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
8465 struct port_info *pi = arg1;
8466 struct adapter *sc = pi->adapter;
8467 struct link_config *lc = &pi->link_cfg;
8471 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3";
8473 rc = sysctl_wire_old_buffer(req, 0);
8477 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
8481 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0) {
8485 if (hw_off_limits(sc)) {
8490 if (pi->up_vis == 0) {
8492 * If all the interfaces are administratively down the firmware
8493 * does not report transceiver changes. Refresh port info here.
8494 * This is the only reason we have a synchronized op in this
8495 * function. Just PORT_LOCK would have been enough otherwise.
8497 t4_update_port_info(pi);
8501 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
8502 !fec_supported(lc->pcaps)) {
8503 sbuf_printf(sb, "n/a");
8507 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits);
8509 rc = sbuf_finish(sb);
8513 end_synchronized_op(sc, 0);
8519 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
8521 struct port_info *pi = arg1;
8522 struct adapter *sc = pi->adapter;
8523 struct link_config *lc = &pi->link_cfg;
8526 if (lc->pcaps & FW_PORT_CAP32_ANEG)
8527 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
8530 rc = sysctl_handle_int(oidp, &val, 0, req);
8531 if (rc != 0 || req->newptr == NULL)
8534 val = AUTONEG_DISABLE;
8536 val = AUTONEG_ENABLE;
8540 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
8545 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
8549 lc->requested_aneg = val;
8550 if (!hw_off_limits(sc)) {
8551 fixup_link_config(pi);
8553 rc = apply_link_config(pi);
8554 set_current_media(pi);
8558 end_synchronized_op(sc, 0);
8563 sysctl_force_fec(SYSCTL_HANDLER_ARGS)
8565 struct port_info *pi = arg1;
8566 struct adapter *sc = pi->adapter;
8567 struct link_config *lc = &pi->link_cfg;
8570 val = lc->force_fec;
8571 MPASS(val >= -1 && val <= 1);
8572 rc = sysctl_handle_int(oidp, &val, 0, req);
8573 if (rc != 0 || req->newptr == NULL)
8575 if (!(lc->pcaps & FW_PORT_CAP32_FORCE_FEC))
8577 if (val < -1 || val > 1)
8580 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4ff");
8584 lc->force_fec = val;
8585 if (!hw_off_limits(sc)) {
8586 fixup_link_config(pi);
8588 rc = apply_link_config(pi);
8591 end_synchronized_op(sc, 0);
8596 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
8598 struct adapter *sc = arg1;
8602 mtx_lock(&sc->reg_lock);
8603 if (hw_off_limits(sc))
8607 val = t4_read_reg64(sc, reg);
8609 mtx_unlock(&sc->reg_lock);
8611 rc = sysctl_handle_64(oidp, &val, 0, req);
8616 sysctl_temperature(SYSCTL_HANDLER_ARGS)
8618 struct adapter *sc = arg1;
8620 uint32_t param, val;
8622 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
8625 if (hw_off_limits(sc))
8628 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8629 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8630 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
8631 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8633 end_synchronized_op(sc, 0);
8637 /* unknown is returned as 0 but we display -1 in that case */
8638 t = val == 0 ? -1 : val;
8640 rc = sysctl_handle_int(oidp, &t, 0, req);
8645 sysctl_vdd(SYSCTL_HANDLER_ARGS)
8647 struct adapter *sc = arg1;
8649 uint32_t param, val;
8651 if (sc->params.core_vdd == 0) {
8652 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8656 if (hw_off_limits(sc))
8659 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8660 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8661 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
8662 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1,
8665 end_synchronized_op(sc, 0);
8668 sc->params.core_vdd = val;
8671 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
8675 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
8677 struct adapter *sc = arg1;
8679 uint32_t param, val;
8681 v = sc->sensor_resets;
8682 rc = sysctl_handle_int(oidp, &v, 0, req);
8683 if (rc != 0 || req->newptr == NULL || v <= 0)
8686 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
8687 chip_id(sc) < CHELSIO_T5)
8690 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
8693 if (hw_off_limits(sc))
8696 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8697 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
8698 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
8700 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8702 end_synchronized_op(sc, 0);
8704 sc->sensor_resets++;
8709 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
8711 struct adapter *sc = arg1;
8714 uint32_t param, val;
8716 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
8719 if (hw_off_limits(sc))
8722 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8723 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
8724 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
8726 end_synchronized_op(sc, 0);
8730 rc = sysctl_wire_old_buffer(req, 0);
8734 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8738 if (val == 0xffffffff) {
8739 /* Only debug and custom firmwares report load averages. */
8740 sbuf_printf(sb, "not available");
8742 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
8743 (val >> 16) & 0xff);
8745 rc = sbuf_finish(sb);
8752 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
8754 struct adapter *sc = arg1;
8757 uint16_t incr[NMTUS][NCCTRL_WIN];
8758 static const char *dec_fac[] = {
8759 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
8763 rc = sysctl_wire_old_buffer(req, 0);
8767 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8771 mtx_lock(&sc->reg_lock);
8772 if (hw_off_limits(sc))
8775 t4_read_cong_tbl(sc, incr);
8776 mtx_unlock(&sc->reg_lock);
8780 for (i = 0; i < NCCTRL_WIN; ++i) {
8781 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
8782 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
8783 incr[5][i], incr[6][i], incr[7][i]);
8784 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
8785 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
8786 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
8787 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
8790 rc = sbuf_finish(sb);
8796 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
8797 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
8798 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
8799 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
8803 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
8805 struct adapter *sc = arg1;
8807 int rc, i, n, qid = arg2;
8810 u_int cim_num_obq = sc->chip_params->cim_num_obq;
8812 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
8813 ("%s: bad qid %d\n", __func__, qid));
8815 if (qid < CIM_NUM_IBQ) {
8818 n = 4 * CIM_IBQ_SIZE;
8819 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
8820 mtx_lock(&sc->reg_lock);
8821 if (hw_off_limits(sc))
8824 rc = t4_read_cim_ibq(sc, qid, buf, n);
8825 mtx_unlock(&sc->reg_lock);
8827 /* outbound queue */
8830 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
8831 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
8832 mtx_lock(&sc->reg_lock);
8833 if (hw_off_limits(sc))
8836 rc = t4_read_cim_obq(sc, qid, buf, n);
8837 mtx_unlock(&sc->reg_lock);
8844 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
8846 rc = sysctl_wire_old_buffer(req, 0);
8850 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
8856 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
8857 for (i = 0, p = buf; i < n; i += 16, p += 4)
8858 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
8861 rc = sbuf_finish(sb);
8869 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
8873 sbuf_printf(sb, "Status Data PC%s",
8874 cfg & F_UPDBGLACAPTPCONLY ? "" :
8875 " LS0Stat LS0Addr LS0Data");
8877 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
8878 if (cfg & F_UPDBGLACAPTPCONLY) {
8879 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
8881 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
8882 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
8883 p[4] & 0xff, p[5] >> 8);
8884 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
8885 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
8886 p[1] & 0xf, p[2] >> 4);
8889 "\n %02x %x%07x %x%07x %08x %08x "
8891 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
8892 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
8899 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
8903 sbuf_printf(sb, "Status Inst Data PC%s",
8904 cfg & F_UPDBGLACAPTPCONLY ? "" :
8905 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
8907 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
8908 if (cfg & F_UPDBGLACAPTPCONLY) {
8909 sbuf_printf(sb, "\n %02x %08x %08x %08x",
8910 p[3] & 0xff, p[2], p[1], p[0]);
8911 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
8912 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
8913 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
8914 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
8915 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
8916 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
8919 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
8920 "%08x %08x %08x %08x %08x %08x",
8921 (p[9] >> 16) & 0xff,
8922 p[9] & 0xffff, p[8] >> 16,
8923 p[8] & 0xffff, p[7] >> 16,
8924 p[7] & 0xffff, p[6] >> 16,
8925 p[2], p[1], p[0], p[5], p[4], p[3]);
8931 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
8936 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
8937 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
8942 mtx_lock(&sc->reg_lock);
8943 if (hw_off_limits(sc))
8946 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8948 rc = -t4_cim_read_la(sc, buf, NULL);
8950 mtx_unlock(&sc->reg_lock);
8952 if (chip_id(sc) < CHELSIO_T6)
8953 sbuf_cim_la4(sc, sb, buf, cfg);
8955 sbuf_cim_la6(sc, sb, buf, cfg);
8962 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
8964 struct adapter *sc = arg1;
8968 rc = sysctl_wire_old_buffer(req, 0);
8971 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8975 rc = sbuf_cim_la(sc, sb, M_WAITOK);
8977 rc = sbuf_finish(sb);
8983 dump_cim_regs(struct adapter *sc)
8985 log(LOG_DEBUG, "%s: CIM debug regs1 %08x %08x %08x %08x %08x\n",
8986 device_get_nameunit(sc->dev),
8987 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
8988 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
8989 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA2),
8990 t4_read_reg(sc, A_EDC_H_BIST_DATA_PATTERN),
8991 t4_read_reg(sc, A_EDC_H_BIST_STATUS_RDATA));
8992 log(LOG_DEBUG, "%s: CIM debug regs2 %08x %08x %08x %08x %08x\n",
8993 device_get_nameunit(sc->dev),
8994 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0),
8995 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1),
8996 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA0 + 0x800),
8997 t4_read_reg(sc, A_EDC_H_BIST_USER_WDATA1 + 0x800),
8998 t4_read_reg(sc, A_EDC_H_BIST_CMD_LEN));
9002 dump_cimla(struct adapter *sc)
9007 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9008 log(LOG_DEBUG, "%s: failed to generate CIM LA dump.\n",
9009 device_get_nameunit(sc->dev));
9012 rc = sbuf_cim_la(sc, &sb, M_WAITOK);
9014 rc = sbuf_finish(&sb);
9016 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s\n",
9017 device_get_nameunit(sc->dev), sbuf_data(&sb));
9024 t4_os_cim_err(struct adapter *sc)
9026 atomic_set_int(&sc->error_flags, ADAP_CIM_ERR);
9030 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
9032 struct adapter *sc = arg1;
9038 rc = sysctl_wire_old_buffer(req, 0);
9042 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9046 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
9049 mtx_lock(&sc->reg_lock);
9050 if (hw_off_limits(sc))
9053 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
9054 mtx_unlock(&sc->reg_lock);
9059 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9060 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
9064 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
9065 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
9066 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
9067 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
9068 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
9069 (p[1] >> 2) | ((p[2] & 3) << 30),
9070 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
9073 rc = sbuf_finish(sb);
9081 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
9083 struct adapter *sc = arg1;
9089 rc = sysctl_wire_old_buffer(req, 0);
9093 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9097 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
9100 mtx_lock(&sc->reg_lock);
9101 if (hw_off_limits(sc))
9104 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
9105 mtx_unlock(&sc->reg_lock);
9110 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
9111 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9112 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
9113 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
9114 p[4], p[3], p[2], p[1], p[0]);
9117 sbuf_printf(sb, "\n\nCntl ID Data");
9118 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
9119 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
9120 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
9123 rc = sbuf_finish(sb);
9131 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
9133 struct adapter *sc = arg1;
9136 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9137 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
9138 uint16_t thres[CIM_NUM_IBQ];
9139 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
9140 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
9141 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
9143 cim_num_obq = sc->chip_params->cim_num_obq;
9145 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
9146 obq_rdaddr = A_UP_OBQ_0_REALADDR;
9148 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
9149 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
9151 nq = CIM_NUM_IBQ + cim_num_obq;
9153 mtx_lock(&sc->reg_lock);
9154 if (hw_off_limits(sc))
9157 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
9159 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq,
9162 t4_read_cimq_cfg(sc, base, size, thres);
9165 mtx_unlock(&sc->reg_lock);
9169 rc = sysctl_wire_old_buffer(req, 0);
9173 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
9178 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
9180 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
9181 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
9182 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
9183 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9184 G_QUEREMFLITS(p[2]) * 16);
9185 for ( ; i < nq; i++, p += 4, wr += 2)
9186 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
9187 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
9188 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
9189 G_QUEREMFLITS(p[2]) * 16);
9191 rc = sbuf_finish(sb);
9198 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
9200 struct adapter *sc = arg1;
9203 struct tp_cpl_stats stats;
9205 rc = sysctl_wire_old_buffer(req, 0);
9209 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9213 mtx_lock(&sc->reg_lock);
9214 if (hw_off_limits(sc))
9217 t4_tp_get_cpl_stats(sc, &stats, 0);
9218 mtx_unlock(&sc->reg_lock);
9222 if (sc->chip_params->nchan > 2) {
9223 sbuf_printf(sb, " channel 0 channel 1"
9224 " channel 2 channel 3");
9225 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
9226 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
9227 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
9228 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
9230 sbuf_printf(sb, " channel 0 channel 1");
9231 sbuf_printf(sb, "\nCPL requests: %10u %10u",
9232 stats.req[0], stats.req[1]);
9233 sbuf_printf(sb, "\nCPL responses: %10u %10u",
9234 stats.rsp[0], stats.rsp[1]);
9237 rc = sbuf_finish(sb);
9244 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
9246 struct adapter *sc = arg1;
9249 struct tp_usm_stats stats;
9251 rc = sysctl_wire_old_buffer(req, 0);
9255 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9259 mtx_lock(&sc->reg_lock);
9260 if (hw_off_limits(sc))
9263 t4_get_usm_stats(sc, &stats, 1);
9264 mtx_unlock(&sc->reg_lock);
9266 sbuf_printf(sb, "Frames: %u\n", stats.frames);
9267 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
9268 sbuf_printf(sb, "Drops: %u", stats.drops);
9269 rc = sbuf_finish(sb);
9277 sysctl_tid_stats(SYSCTL_HANDLER_ARGS)
9279 struct adapter *sc = arg1;
9282 struct tp_tid_stats stats;
9284 rc = sysctl_wire_old_buffer(req, 0);
9288 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9292 mtx_lock(&sc->reg_lock);
9293 if (hw_off_limits(sc))
9296 t4_tp_get_tid_stats(sc, &stats, 1);
9297 mtx_unlock(&sc->reg_lock);
9299 sbuf_printf(sb, "Delete: %u\n", stats.del);
9300 sbuf_printf(sb, "Invalidate: %u\n", stats.inv);
9301 sbuf_printf(sb, "Active: %u\n", stats.act);
9302 sbuf_printf(sb, "Passive: %u", stats.pas);
9303 rc = sbuf_finish(sb);
9310 static const char * const devlog_level_strings[] = {
9311 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
9312 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
9313 [FW_DEVLOG_LEVEL_ERR] = "ERR",
9314 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
9315 [FW_DEVLOG_LEVEL_INFO] = "INFO",
9316 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
9319 static const char * const devlog_facility_strings[] = {
9320 [FW_DEVLOG_FACILITY_CORE] = "CORE",
9321 [FW_DEVLOG_FACILITY_CF] = "CF",
9322 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
9323 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
9324 [FW_DEVLOG_FACILITY_RES] = "RES",
9325 [FW_DEVLOG_FACILITY_HW] = "HW",
9326 [FW_DEVLOG_FACILITY_FLR] = "FLR",
9327 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
9328 [FW_DEVLOG_FACILITY_PHY] = "PHY",
9329 [FW_DEVLOG_FACILITY_MAC] = "MAC",
9330 [FW_DEVLOG_FACILITY_PORT] = "PORT",
9331 [FW_DEVLOG_FACILITY_VI] = "VI",
9332 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
9333 [FW_DEVLOG_FACILITY_ACL] = "ACL",
9334 [FW_DEVLOG_FACILITY_TM] = "TM",
9335 [FW_DEVLOG_FACILITY_QFC] = "QFC",
9336 [FW_DEVLOG_FACILITY_DCB] = "DCB",
9337 [FW_DEVLOG_FACILITY_ETH] = "ETH",
9338 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
9339 [FW_DEVLOG_FACILITY_RI] = "RI",
9340 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
9341 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
9342 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
9343 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
9344 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
9348 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
9350 int i, j, rc, nentries, first = 0;
9351 struct devlog_params *dparams = &sc->params.devlog;
9352 struct fw_devlog_e *buf, *e;
9353 uint64_t ftstamp = UINT64_MAX;
9355 if (dparams->addr == 0)
9358 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
9359 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
9363 mtx_lock(&sc->reg_lock);
9364 if (hw_off_limits(sc))
9367 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf,
9369 mtx_unlock(&sc->reg_lock);
9373 nentries = dparams->size / sizeof(struct fw_devlog_e);
9374 for (i = 0; i < nentries; i++) {
9377 if (e->timestamp == 0)
9380 e->timestamp = be64toh(e->timestamp);
9381 e->seqno = be32toh(e->seqno);
9382 for (j = 0; j < 8; j++)
9383 e->params[j] = be32toh(e->params[j]);
9385 if (e->timestamp < ftstamp) {
9386 ftstamp = e->timestamp;
9391 if (buf[first].timestamp == 0)
9392 goto done; /* nothing in the log */
9394 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
9395 "Seq#", "Tstamp", "Level", "Facility", "Message");
9400 if (e->timestamp == 0)
9403 sbuf_printf(sb, "%10d %15ju %8s %8s ",
9404 e->seqno, e->timestamp,
9405 (e->level < nitems(devlog_level_strings) ?
9406 devlog_level_strings[e->level] : "UNKNOWN"),
9407 (e->facility < nitems(devlog_facility_strings) ?
9408 devlog_facility_strings[e->facility] : "UNKNOWN"));
9409 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
9410 e->params[2], e->params[3], e->params[4],
9411 e->params[5], e->params[6], e->params[7]);
9413 if (++i == nentries)
9415 } while (i != first);
9422 sysctl_devlog(SYSCTL_HANDLER_ARGS)
9424 struct adapter *sc = arg1;
9428 rc = sysctl_wire_old_buffer(req, 0);
9431 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9435 rc = sbuf_devlog(sc, sb, M_WAITOK);
9437 rc = sbuf_finish(sb);
9443 dump_devlog(struct adapter *sc)
9448 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
9449 log(LOG_DEBUG, "%s: failed to generate devlog dump.\n",
9450 device_get_nameunit(sc->dev));
9453 rc = sbuf_devlog(sc, &sb, M_WAITOK);
9455 rc = sbuf_finish(&sb);
9457 log(LOG_DEBUG, "%s: device log follows.\n%s",
9458 device_get_nameunit(sc->dev), sbuf_data(&sb));
9465 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
9467 struct adapter *sc = arg1;
9470 struct tp_fcoe_stats stats[MAX_NCHAN];
9471 int i, nchan = sc->chip_params->nchan;
9473 rc = sysctl_wire_old_buffer(req, 0);
9477 mtx_lock(&sc->reg_lock);
9478 if (hw_off_limits(sc))
9481 for (i = 0; i < nchan; i++)
9482 t4_get_fcoe_stats(sc, i, &stats[i], 1);
9484 mtx_unlock(&sc->reg_lock);
9488 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9493 sbuf_printf(sb, " channel 0 channel 1"
9494 " channel 2 channel 3");
9495 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
9496 stats[0].octets_ddp, stats[1].octets_ddp,
9497 stats[2].octets_ddp, stats[3].octets_ddp);
9498 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
9499 stats[0].frames_ddp, stats[1].frames_ddp,
9500 stats[2].frames_ddp, stats[3].frames_ddp);
9501 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
9502 stats[0].frames_drop, stats[1].frames_drop,
9503 stats[2].frames_drop, stats[3].frames_drop);
9505 sbuf_printf(sb, " channel 0 channel 1");
9506 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
9507 stats[0].octets_ddp, stats[1].octets_ddp);
9508 sbuf_printf(sb, "\nframesDDP: %16u %16u",
9509 stats[0].frames_ddp, stats[1].frames_ddp);
9510 sbuf_printf(sb, "\nframesDrop: %16u %16u",
9511 stats[0].frames_drop, stats[1].frames_drop);
9514 rc = sbuf_finish(sb);
9521 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
9523 struct adapter *sc = arg1;
9526 unsigned int map, kbps, ipg, mode;
9527 unsigned int pace_tab[NTX_SCHED];
9529 rc = sysctl_wire_old_buffer(req, 0);
9533 sb = sbuf_new_for_sysctl(NULL, NULL, 512, req);
9537 mtx_lock(&sc->reg_lock);
9538 if (hw_off_limits(sc)) {
9543 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
9544 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
9545 t4_read_pace_tbl(sc, pace_tab);
9547 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
9548 "Class IPG (0.1 ns) Flow IPG (us)");
9550 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
9551 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
9552 sbuf_printf(sb, "\n %u %-5s %u ", i,
9553 (mode & (1 << i)) ? "flow" : "class", map & 3);
9555 sbuf_printf(sb, "%9u ", kbps);
9557 sbuf_printf(sb, " disabled ");
9560 sbuf_printf(sb, "%13u ", ipg);
9562 sbuf_printf(sb, " disabled ");
9565 sbuf_printf(sb, "%10u", pace_tab[i]);
9567 sbuf_printf(sb, " disabled");
9569 rc = sbuf_finish(sb);
9571 mtx_unlock(&sc->reg_lock);
9577 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
9579 struct adapter *sc = arg1;
9583 struct lb_port_stats s[2];
9584 static const char *stat_name[] = {
9585 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
9586 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
9587 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
9588 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
9589 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
9590 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
9591 "BG2FramesTrunc:", "BG3FramesTrunc:"
9594 rc = sysctl_wire_old_buffer(req, 0);
9598 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9602 memset(s, 0, sizeof(s));
9604 for (i = 0; i < sc->chip_params->nchan; i += 2) {
9605 mtx_lock(&sc->reg_lock);
9606 if (hw_off_limits(sc))
9609 t4_get_lb_stats(sc, i, &s[0]);
9610 t4_get_lb_stats(sc, i + 1, &s[1]);
9612 mtx_unlock(&sc->reg_lock);
9618 sbuf_printf(sb, "%s Loopback %u"
9619 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
9621 for (j = 0; j < nitems(stat_name); j++)
9622 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
9626 rc = sbuf_finish(sb);
9633 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
9636 struct port_info *pi = arg1;
9637 struct link_config *lc = &pi->link_cfg;
9640 rc = sysctl_wire_old_buffer(req, 0);
9643 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
9647 if (lc->link_ok || lc->link_down_rc == 255)
9648 sbuf_printf(sb, "n/a");
9650 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
9652 rc = sbuf_finish(sb);
9665 mem_desc_cmp(const void *a, const void *b)
9667 const u_int v1 = ((const struct mem_desc *)a)->base;
9668 const u_int v2 = ((const struct mem_desc *)b)->base;
9679 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
9687 size = to - from + 1;
9691 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
9692 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
9696 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
9698 struct adapter *sc = arg1;
9701 uint32_t lo, hi, used, free, alloc;
9702 static const char *memory[] = {
9703 "EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
9705 static const char *region[] = {
9706 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
9707 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
9708 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
9709 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
9710 "RQUDP region:", "PBL region:", "TXPBL region:",
9711 "TLSKey region:", "DBVFIFO region:", "ULPRX state:",
9712 "ULPTX state:", "On-chip queues:",
9714 struct mem_desc avail[4];
9715 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
9716 struct mem_desc *md = mem;
9718 rc = sysctl_wire_old_buffer(req, 0);
9722 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9726 for (i = 0; i < nitems(mem); i++) {
9731 mtx_lock(&sc->reg_lock);
9732 if (hw_off_limits(sc)) {
9737 /* Find and sort the populated memory ranges */
9739 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
9740 if (lo & F_EDRAM0_ENABLE) {
9741 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
9742 avail[i].base = G_EDRAM0_BASE(hi) << 20;
9743 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
9747 if (lo & F_EDRAM1_ENABLE) {
9748 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
9749 avail[i].base = G_EDRAM1_BASE(hi) << 20;
9750 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
9754 if (lo & F_EXT_MEM_ENABLE) {
9755 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
9756 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
9757 avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20);
9758 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
9761 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
9762 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
9763 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
9764 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
9768 if (is_t6(sc) && lo & F_HMA_MUX) {
9769 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
9770 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
9771 avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
9775 MPASS(i <= nitems(avail));
9776 if (!i) /* no memory available */
9778 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
9780 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
9781 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
9782 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
9783 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9784 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
9785 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
9786 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
9787 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
9788 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
9790 /* the next few have explicit upper bounds */
9791 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
9792 md->limit = md->base - 1 +
9793 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
9794 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
9797 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
9798 md->limit = md->base - 1 +
9799 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
9800 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
9803 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
9804 if (chip_id(sc) <= CHELSIO_T5)
9805 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
9807 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
9811 md->idx = nitems(region); /* hide it */
9815 #define ulp_region(reg) \
9816 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
9817 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
9819 ulp_region(RX_ISCSI);
9820 ulp_region(RX_TDDP);
9822 ulp_region(RX_STAG);
9824 ulp_region(RX_RQUDP);
9827 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS)
9828 ulp_region(RX_TLS_KEY);
9833 md->idx = nitems(region);
9836 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
9837 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
9840 if (sge_ctrl & F_VFIFO_ENABLE)
9841 size = fifo_size << 2;
9843 size = G_T6_DBVFIFO_SIZE(fifo_size) << 6;
9846 md->base = t4_read_reg(sc, A_SGE_DBVFIFO_BADDR);
9847 md->limit = md->base + size - 1;
9849 md->idx = nitems(region);
9853 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
9856 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
9860 md->base = sc->vres.ocq.start;
9861 if (sc->vres.ocq.size)
9862 md->limit = md->base + sc->vres.ocq.size - 1;
9864 md->idx = nitems(region); /* hide it */
9867 /* add any address-space holes, there can be up to 3 */
9868 for (n = 0; n < i - 1; n++)
9869 if (avail[n].limit < avail[n + 1].base)
9870 (md++)->base = avail[n].limit;
9872 (md++)->base = avail[n].limit;
9875 MPASS(n <= nitems(mem));
9876 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
9878 for (lo = 0; lo < i; lo++)
9879 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
9880 avail[lo].limit - 1);
9882 sbuf_printf(sb, "\n");
9883 for (i = 0; i < n; i++) {
9884 if (mem[i].idx >= nitems(region))
9885 continue; /* skip holes */
9887 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
9888 mem_region_show(sb, region[mem[i].idx], mem[i].base,
9892 sbuf_printf(sb, "\n");
9893 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
9894 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
9895 mem_region_show(sb, "uP RAM:", lo, hi);
9897 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
9898 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
9899 mem_region_show(sb, "uP Extmem2:", lo, hi);
9901 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
9902 for (i = 0, free = 0; i < 2; i++)
9903 free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
9904 sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
9905 G_PMRXMAXPAGE(lo), free,
9906 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
9907 (lo & F_PMRXNUMCHN) ? 2 : 1);
9909 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
9910 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
9911 for (i = 0, free = 0; i < 4; i++)
9912 free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
9913 sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
9914 G_PMTXMAXPAGE(lo), free,
9915 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
9916 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
9917 sbuf_printf(sb, "%u p-structs (%u free)\n",
9918 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
9919 G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
9921 for (i = 0; i < 4; i++) {
9922 if (chip_id(sc) > CHELSIO_T5)
9923 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
9925 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
9927 used = G_T5_USED(lo);
9928 alloc = G_T5_ALLOC(lo);
9931 alloc = G_ALLOC(lo);
9933 /* For T6 these are MAC buffer groups */
9934 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
9937 for (i = 0; i < sc->chip_params->nchan; i++) {
9938 if (chip_id(sc) > CHELSIO_T5)
9939 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
9941 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
9943 used = G_T5_USED(lo);
9944 alloc = G_T5_ALLOC(lo);
9947 alloc = G_ALLOC(lo);
9949 /* For T6 these are MAC buffer groups */
9951 "\nLoopback %d using %u pages out of %u allocated",
9955 mtx_unlock(&sc->reg_lock);
9957 rc = sbuf_finish(sb);
9963 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
9967 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
9971 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
9973 struct adapter *sc = arg1;
9977 MPASS(chip_id(sc) <= CHELSIO_T5);
9979 rc = sysctl_wire_old_buffer(req, 0);
9983 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9988 "Idx Ethernet address Mask Vld Ports PF"
9989 " VF Replication P0 P1 P2 P3 ML");
9990 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
9991 uint64_t tcamx, tcamy, mask;
9992 uint32_t cls_lo, cls_hi;
9993 uint8_t addr[ETHER_ADDR_LEN];
9995 mtx_lock(&sc->reg_lock);
9996 if (hw_off_limits(sc))
9999 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
10000 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
10002 mtx_unlock(&sc->reg_lock);
10007 tcamxy2valmask(tcamx, tcamy, addr, &mask);
10008 mtx_lock(&sc->reg_lock);
10009 if (hw_off_limits(sc))
10012 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10013 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10015 mtx_unlock(&sc->reg_lock);
10018 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
10019 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
10020 addr[3], addr[4], addr[5], (uintmax_t)mask,
10021 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10022 G_PORTMAP(cls_hi), G_PF(cls_lo),
10023 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10025 if (cls_lo & F_REPLICATE) {
10026 struct fw_ldst_cmd ldst_cmd;
10028 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10029 ldst_cmd.op_to_addrspace =
10030 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10031 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10032 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10033 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10034 ldst_cmd.u.mps.rplc.fid_idx =
10035 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10036 V_FW_LDST_CMD_IDX(i));
10038 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10042 if (hw_off_limits(sc))
10045 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10046 sizeof(ldst_cmd), &ldst_cmd);
10047 end_synchronized_op(sc, 0);
10051 sbuf_printf(sb, " %08x %08x %08x %08x",
10052 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10053 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10054 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10055 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10058 sbuf_printf(sb, "%36s", "");
10060 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10061 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10062 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10066 (void) sbuf_finish(sb);
10068 rc = sbuf_finish(sb);
10075 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
10077 struct adapter *sc = arg1;
10081 MPASS(chip_id(sc) > CHELSIO_T5);
10083 rc = sysctl_wire_old_buffer(req, 0);
10087 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10091 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
10092 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
10094 " P0 P1 P2 P3 ML\n");
10096 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
10097 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
10099 uint64_t tcamx, tcamy, val, mask;
10100 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
10101 uint8_t addr[ETHER_ADDR_LEN];
10103 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
10105 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
10107 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
10108 mtx_lock(&sc->reg_lock);
10109 if (hw_off_limits(sc))
10112 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10113 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10114 tcamy = G_DMACH(val) << 32;
10115 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10116 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10118 mtx_unlock(&sc->reg_lock);
10122 lookup_type = G_DATALKPTYPE(data2);
10123 port_num = G_DATAPORTNUM(data2);
10124 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10125 /* Inner header VNI */
10126 vniy = ((data2 & F_DATAVIDH2) << 23) |
10127 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10128 dip_hit = data2 & F_DATADIPHIT;
10133 vlan_vld = data2 & F_DATAVIDH2;
10134 ivlan = G_VIDL(val);
10137 ctl |= V_CTLXYBITSEL(1);
10138 mtx_lock(&sc->reg_lock);
10139 if (hw_off_limits(sc))
10142 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
10143 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
10144 tcamx = G_DMACH(val) << 32;
10145 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
10146 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
10148 mtx_unlock(&sc->reg_lock);
10152 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10153 /* Inner header VNI mask */
10154 vnix = ((data2 & F_DATAVIDH2) << 23) |
10155 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
10161 tcamxy2valmask(tcamx, tcamy, addr, &mask);
10163 mtx_lock(&sc->reg_lock);
10164 if (hw_off_limits(sc))
10167 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10168 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
10170 mtx_unlock(&sc->reg_lock);
10174 if (lookup_type && lookup_type != M_DATALKPTYPE) {
10175 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
10176 "%012jx %06x %06x - - %3c"
10177 " I %4x %3c %#x%4u%4d", i, addr[0],
10178 addr[1], addr[2], addr[3], addr[4], addr[5],
10179 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
10180 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
10181 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
10182 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
10184 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
10185 "%012jx - - ", i, addr[0], addr[1],
10186 addr[2], addr[3], addr[4], addr[5],
10190 sbuf_printf(sb, "%4u Y ", ivlan);
10192 sbuf_printf(sb, " - N ");
10194 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
10195 lookup_type ? 'I' : 'O', port_num,
10196 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
10197 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
10198 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
10202 if (cls_lo & F_T6_REPLICATE) {
10203 struct fw_ldst_cmd ldst_cmd;
10205 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10206 ldst_cmd.op_to_addrspace =
10207 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
10208 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10209 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
10210 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
10211 ldst_cmd.u.mps.rplc.fid_idx =
10212 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
10213 V_FW_LDST_CMD_IDX(i));
10215 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
10219 if (hw_off_limits(sc))
10222 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
10223 sizeof(ldst_cmd), &ldst_cmd);
10224 end_synchronized_op(sc, 0);
10228 sbuf_printf(sb, " %08x %08x %08x %08x"
10229 " %08x %08x %08x %08x",
10230 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
10231 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
10232 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
10233 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
10234 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
10235 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
10236 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
10237 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
10240 sbuf_printf(sb, "%72s", "");
10242 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
10243 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
10244 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
10245 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
10249 (void) sbuf_finish(sb);
10251 rc = sbuf_finish(sb);
10258 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
10260 struct adapter *sc = arg1;
10263 uint16_t mtus[NMTUS];
10265 rc = sysctl_wire_old_buffer(req, 0);
10269 mtx_lock(&sc->reg_lock);
10270 if (hw_off_limits(sc))
10273 t4_read_mtu_tbl(sc, mtus, NULL);
10274 mtx_unlock(&sc->reg_lock);
10278 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10282 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
10283 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
10284 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
10285 mtus[14], mtus[15]);
10287 rc = sbuf_finish(sb);
10294 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
10296 struct adapter *sc = arg1;
10299 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
10300 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
10301 static const char *tx_stats[MAX_PM_NSTATS] = {
10302 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
10303 "Tx FIFO wait", NULL, "Tx latency"
10305 static const char *rx_stats[MAX_PM_NSTATS] = {
10306 "Read:", "Write bypass:", "Write mem:", "Flush:",
10307 "Rx FIFO wait", NULL, "Rx latency"
10310 rc = sysctl_wire_old_buffer(req, 0);
10314 mtx_lock(&sc->reg_lock);
10315 if (hw_off_limits(sc))
10318 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
10319 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
10321 mtx_unlock(&sc->reg_lock);
10325 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10329 sbuf_printf(sb, " Tx pcmds Tx bytes");
10330 for (i = 0; i < 4; i++) {
10331 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10335 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
10336 for (i = 0; i < 4; i++) {
10337 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10341 if (chip_id(sc) > CHELSIO_T5) {
10343 "\n Total wait Total occupancy");
10344 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10346 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10350 MPASS(i < nitems(tx_stats));
10353 "\n Reads Total wait");
10354 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
10356 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
10360 rc = sbuf_finish(sb);
10367 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
10369 struct adapter *sc = arg1;
10372 struct tp_rdma_stats stats;
10374 rc = sysctl_wire_old_buffer(req, 0);
10378 mtx_lock(&sc->reg_lock);
10379 if (hw_off_limits(sc))
10382 t4_tp_get_rdma_stats(sc, &stats, 0);
10383 mtx_unlock(&sc->reg_lock);
10387 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10391 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
10392 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
10394 rc = sbuf_finish(sb);
10401 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
10403 struct adapter *sc = arg1;
10406 struct tp_tcp_stats v4, v6;
10408 rc = sysctl_wire_old_buffer(req, 0);
10412 mtx_lock(&sc->reg_lock);
10413 if (hw_off_limits(sc))
10416 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
10417 mtx_unlock(&sc->reg_lock);
10421 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10427 sbuf_printf(sb, "OutRsts: %20u %20u\n",
10428 v4.tcp_out_rsts, v6.tcp_out_rsts);
10429 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
10430 v4.tcp_in_segs, v6.tcp_in_segs);
10431 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
10432 v4.tcp_out_segs, v6.tcp_out_segs);
10433 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
10434 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
10436 rc = sbuf_finish(sb);
10443 sysctl_tids(SYSCTL_HANDLER_ARGS)
10445 struct adapter *sc = arg1;
10449 struct tid_info *t = &sc->tids;
10451 rc = sysctl_wire_old_buffer(req, 0);
10455 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10460 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
10465 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
10466 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
10470 bool hashen = false;
10472 mtx_lock(&sc->reg_lock);
10473 if (hw_off_limits(sc))
10475 else if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
10477 if (chip_id(sc) <= CHELSIO_T5) {
10478 x = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
10479 y = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
10481 x = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
10482 y = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
10485 mtx_unlock(&sc->reg_lock);
10489 sbuf_printf(sb, "TID range: ");
10492 sbuf_printf(sb, "%u-%u, ", t->tid_base, x - 1);
10493 sbuf_printf(sb, "%u-%u", y, t->ntids - 1);
10495 sbuf_printf(sb, "%u-%u", t->tid_base, t->tid_base +
10498 sbuf_printf(sb, ", in use: %u\n",
10499 atomic_load_acq_int(&t->tids_in_use));
10503 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
10504 t->stid_base + t->nstids - 1, t->stids_in_use);
10508 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
10509 t->ftid_end, t->ftids_in_use);
10513 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
10514 t->etid_base + t->netids - 1, t->etids_in_use);
10517 mtx_lock(&sc->reg_lock);
10518 if (hw_off_limits(sc))
10521 x = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4);
10522 y = t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6);
10524 mtx_unlock(&sc->reg_lock);
10527 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", x, y);
10530 rc = sbuf_finish(sb);
10532 (void)sbuf_finish(sb);
10539 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
10541 struct adapter *sc = arg1;
10544 struct tp_err_stats stats;
10546 rc = sysctl_wire_old_buffer(req, 0);
10550 mtx_lock(&sc->reg_lock);
10551 if (hw_off_limits(sc))
10554 t4_tp_get_err_stats(sc, &stats, 0);
10555 mtx_unlock(&sc->reg_lock);
10559 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10563 if (sc->chip_params->nchan > 2) {
10564 sbuf_printf(sb, " channel 0 channel 1"
10565 " channel 2 channel 3\n");
10566 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
10567 stats.mac_in_errs[0], stats.mac_in_errs[1],
10568 stats.mac_in_errs[2], stats.mac_in_errs[3]);
10569 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
10570 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
10571 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
10572 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
10573 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
10574 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
10575 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
10576 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
10577 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
10578 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
10579 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
10580 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
10581 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
10582 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
10583 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
10584 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
10585 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
10586 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
10587 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
10588 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
10589 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
10591 sbuf_printf(sb, " channel 0 channel 1\n");
10592 sbuf_printf(sb, "macInErrs: %10u %10u\n",
10593 stats.mac_in_errs[0], stats.mac_in_errs[1]);
10594 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
10595 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
10596 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
10597 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
10598 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
10599 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
10600 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
10601 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
10602 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
10603 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
10604 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
10605 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
10606 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
10607 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
10610 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
10611 stats.ofld_no_neigh, stats.ofld_cong_defer);
10613 rc = sbuf_finish(sb);
10620 sysctl_tnl_stats(SYSCTL_HANDLER_ARGS)
10622 struct adapter *sc = arg1;
10625 struct tp_tnl_stats stats;
10627 rc = sysctl_wire_old_buffer(req, 0);
10631 mtx_lock(&sc->reg_lock);
10632 if (hw_off_limits(sc))
10635 t4_tp_get_tnl_stats(sc, &stats, 1);
10636 mtx_unlock(&sc->reg_lock);
10640 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10644 if (sc->chip_params->nchan > 2) {
10645 sbuf_printf(sb, " channel 0 channel 1"
10646 " channel 2 channel 3\n");
10647 sbuf_printf(sb, "OutPkts: %10u %10u %10u %10u\n",
10648 stats.out_pkt[0], stats.out_pkt[1],
10649 stats.out_pkt[2], stats.out_pkt[3]);
10650 sbuf_printf(sb, "InPkts: %10u %10u %10u %10u",
10651 stats.in_pkt[0], stats.in_pkt[1],
10652 stats.in_pkt[2], stats.in_pkt[3]);
10654 sbuf_printf(sb, " channel 0 channel 1\n");
10655 sbuf_printf(sb, "OutPkts: %10u %10u\n",
10656 stats.out_pkt[0], stats.out_pkt[1]);
10657 sbuf_printf(sb, "InPkts: %10u %10u",
10658 stats.in_pkt[0], stats.in_pkt[1]);
10661 rc = sbuf_finish(sb);
10668 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
10670 struct adapter *sc = arg1;
10671 struct tp_params *tpp = &sc->params.tp;
10675 mask = tpp->la_mask >> 16;
10676 rc = sysctl_handle_int(oidp, &mask, 0, req);
10677 if (rc != 0 || req->newptr == NULL)
10681 mtx_lock(&sc->reg_lock);
10682 if (hw_off_limits(sc))
10685 tpp->la_mask = mask << 16;
10686 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U,
10689 mtx_unlock(&sc->reg_lock);
10694 struct field_desc {
10701 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
10707 uint64_t mask = (1ULL << f->width) - 1;
10708 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
10709 ((uintmax_t)v >> f->start) & mask);
10711 if (line_size + len >= 79) {
10713 sbuf_printf(sb, "\n ");
10715 sbuf_printf(sb, "%s ", buf);
10716 line_size += len + 1;
10719 sbuf_printf(sb, "\n");
10722 static const struct field_desc tp_la0[] = {
10723 { "RcfOpCodeOut", 60, 4 },
10724 { "State", 56, 4 },
10725 { "WcfState", 52, 4 },
10726 { "RcfOpcSrcOut", 50, 2 },
10727 { "CRxError", 49, 1 },
10728 { "ERxError", 48, 1 },
10729 { "SanityFailed", 47, 1 },
10730 { "SpuriousMsg", 46, 1 },
10731 { "FlushInputMsg", 45, 1 },
10732 { "FlushInputCpl", 44, 1 },
10733 { "RssUpBit", 43, 1 },
10734 { "RssFilterHit", 42, 1 },
10736 { "InitTcb", 31, 1 },
10737 { "LineNumber", 24, 7 },
10739 { "EdataOut", 22, 1 },
10741 { "CdataOut", 20, 1 },
10742 { "EreadPdu", 19, 1 },
10743 { "CreadPdu", 18, 1 },
10744 { "TunnelPkt", 17, 1 },
10745 { "RcfPeerFin", 16, 1 },
10746 { "RcfReasonOut", 12, 4 },
10747 { "TxCchannel", 10, 2 },
10748 { "RcfTxChannel", 8, 2 },
10749 { "RxEchannel", 6, 2 },
10750 { "RcfRxChannel", 5, 1 },
10751 { "RcfDataOutSrdy", 4, 1 },
10752 { "RxDvld", 3, 1 },
10753 { "RxOoDvld", 2, 1 },
10754 { "RxCongestion", 1, 1 },
10755 { "TxCongestion", 0, 1 },
10759 static const struct field_desc tp_la1[] = {
10760 { "CplCmdIn", 56, 8 },
10761 { "CplCmdOut", 48, 8 },
10762 { "ESynOut", 47, 1 },
10763 { "EAckOut", 46, 1 },
10764 { "EFinOut", 45, 1 },
10765 { "ERstOut", 44, 1 },
10766 { "SynIn", 43, 1 },
10767 { "AckIn", 42, 1 },
10768 { "FinIn", 41, 1 },
10769 { "RstIn", 40, 1 },
10770 { "DataIn", 39, 1 },
10771 { "DataInVld", 38, 1 },
10772 { "PadIn", 37, 1 },
10773 { "RxBufEmpty", 36, 1 },
10774 { "RxDdp", 35, 1 },
10775 { "RxFbCongestion", 34, 1 },
10776 { "TxFbCongestion", 33, 1 },
10777 { "TxPktSumSrdy", 32, 1 },
10778 { "RcfUlpType", 28, 4 },
10779 { "Eread", 27, 1 },
10780 { "Ebypass", 26, 1 },
10781 { "Esave", 25, 1 },
10782 { "Static0", 24, 1 },
10783 { "Cread", 23, 1 },
10784 { "Cbypass", 22, 1 },
10785 { "Csave", 21, 1 },
10786 { "CPktOut", 20, 1 },
10787 { "RxPagePoolFull", 18, 2 },
10788 { "RxLpbkPkt", 17, 1 },
10789 { "TxLpbkPkt", 16, 1 },
10790 { "RxVfValid", 15, 1 },
10791 { "SynLearned", 14, 1 },
10792 { "SetDelEntry", 13, 1 },
10793 { "SetInvEntry", 12, 1 },
10794 { "CpcmdDvld", 11, 1 },
10795 { "CpcmdSave", 10, 1 },
10796 { "RxPstructsFull", 8, 2 },
10797 { "EpcmdDvld", 7, 1 },
10798 { "EpcmdFlush", 6, 1 },
10799 { "EpcmdTrimPrefix", 5, 1 },
10800 { "EpcmdTrimPostfix", 4, 1 },
10801 { "ERssIp4Pkt", 3, 1 },
10802 { "ERssIp6Pkt", 2, 1 },
10803 { "ERssTcpUdpPkt", 1, 1 },
10804 { "ERssFceFipPkt", 0, 1 },
10808 static const struct field_desc tp_la2[] = {
10809 { "CplCmdIn", 56, 8 },
10810 { "MpsVfVld", 55, 1 },
10811 { "MpsPf", 52, 3 },
10812 { "MpsVf", 44, 8 },
10813 { "SynIn", 43, 1 },
10814 { "AckIn", 42, 1 },
10815 { "FinIn", 41, 1 },
10816 { "RstIn", 40, 1 },
10817 { "DataIn", 39, 1 },
10818 { "DataInVld", 38, 1 },
10819 { "PadIn", 37, 1 },
10820 { "RxBufEmpty", 36, 1 },
10821 { "RxDdp", 35, 1 },
10822 { "RxFbCongestion", 34, 1 },
10823 { "TxFbCongestion", 33, 1 },
10824 { "TxPktSumSrdy", 32, 1 },
10825 { "RcfUlpType", 28, 4 },
10826 { "Eread", 27, 1 },
10827 { "Ebypass", 26, 1 },
10828 { "Esave", 25, 1 },
10829 { "Static0", 24, 1 },
10830 { "Cread", 23, 1 },
10831 { "Cbypass", 22, 1 },
10832 { "Csave", 21, 1 },
10833 { "CPktOut", 20, 1 },
10834 { "RxPagePoolFull", 18, 2 },
10835 { "RxLpbkPkt", 17, 1 },
10836 { "TxLpbkPkt", 16, 1 },
10837 { "RxVfValid", 15, 1 },
10838 { "SynLearned", 14, 1 },
10839 { "SetDelEntry", 13, 1 },
10840 { "SetInvEntry", 12, 1 },
10841 { "CpcmdDvld", 11, 1 },
10842 { "CpcmdSave", 10, 1 },
10843 { "RxPstructsFull", 8, 2 },
10844 { "EpcmdDvld", 7, 1 },
10845 { "EpcmdFlush", 6, 1 },
10846 { "EpcmdTrimPrefix", 5, 1 },
10847 { "EpcmdTrimPostfix", 4, 1 },
10848 { "ERssIp4Pkt", 3, 1 },
10849 { "ERssIp6Pkt", 2, 1 },
10850 { "ERssTcpUdpPkt", 1, 1 },
10851 { "ERssFceFipPkt", 0, 1 },
10856 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
10859 field_desc_show(sb, *p, tp_la0);
10863 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
10867 sbuf_printf(sb, "\n");
10868 field_desc_show(sb, p[0], tp_la0);
10869 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
10870 field_desc_show(sb, p[1], tp_la0);
10874 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
10878 sbuf_printf(sb, "\n");
10879 field_desc_show(sb, p[0], tp_la0);
10880 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
10881 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
10885 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
10887 struct adapter *sc = arg1;
10892 void (*show_func)(struct sbuf *, uint64_t *, int);
10894 rc = sysctl_wire_old_buffer(req, 0);
10898 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10902 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
10904 mtx_lock(&sc->reg_lock);
10905 if (hw_off_limits(sc))
10908 t4_tp_read_la(sc, buf, NULL);
10909 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
10912 show_func = tp_la_show2;
10916 show_func = tp_la_show3;
10920 show_func = tp_la_show;
10923 mtx_unlock(&sc->reg_lock);
10928 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
10929 (*show_func)(sb, p, i);
10930 rc = sbuf_finish(sb);
10933 free(buf, M_CXGBE);
10938 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
10940 struct adapter *sc = arg1;
10943 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
10945 rc = sysctl_wire_old_buffer(req, 0);
10949 mtx_lock(&sc->reg_lock);
10950 if (hw_off_limits(sc))
10953 t4_get_chan_txrate(sc, nrate, orate);
10954 mtx_unlock(&sc->reg_lock);
10958 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
10962 if (sc->chip_params->nchan > 2) {
10963 sbuf_printf(sb, " channel 0 channel 1"
10964 " channel 2 channel 3\n");
10965 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
10966 nrate[0], nrate[1], nrate[2], nrate[3]);
10967 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
10968 orate[0], orate[1], orate[2], orate[3]);
10970 sbuf_printf(sb, " channel 0 channel 1\n");
10971 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
10972 nrate[0], nrate[1]);
10973 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
10974 orate[0], orate[1]);
10977 rc = sbuf_finish(sb);
10984 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
10986 struct adapter *sc = arg1;
10991 rc = sysctl_wire_old_buffer(req, 0);
10995 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
10999 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
11000 M_ZERO | M_WAITOK);
11002 mtx_lock(&sc->reg_lock);
11003 if (hw_off_limits(sc))
11006 t4_ulprx_read_la(sc, buf);
11007 mtx_unlock(&sc->reg_lock);
11012 sbuf_printf(sb, " Pcmd Type Message"
11014 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
11015 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
11016 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
11018 rc = sbuf_finish(sb);
11021 free(buf, M_CXGBE);
11026 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
11028 struct adapter *sc = arg1;
11031 uint32_t cfg, s1, s2;
11033 MPASS(chip_id(sc) >= CHELSIO_T5);
11035 rc = sysctl_wire_old_buffer(req, 0);
11039 mtx_lock(&sc->reg_lock);
11040 if (hw_off_limits(sc))
11043 cfg = t4_read_reg(sc, A_SGE_STAT_CFG);
11044 s1 = t4_read_reg(sc, A_SGE_STAT_TOTAL);
11045 s2 = t4_read_reg(sc, A_SGE_STAT_MATCH);
11047 mtx_unlock(&sc->reg_lock);
11051 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11055 if (G_STATSOURCE_T5(cfg) == 7) {
11058 mode = is_t5(sc) ? G_STATMODE(cfg) : G_T6_STATMODE(cfg);
11060 sbuf_printf(sb, "total %d, incomplete %d", s1, s2);
11061 else if (mode == 1)
11062 sbuf_printf(sb, "total %d, data overflow %d", s1, s2);
11064 sbuf_printf(sb, "unknown mode %d", mode);
11066 rc = sbuf_finish(sb);
11073 sysctl_cpus(SYSCTL_HANDLER_ARGS)
11075 struct adapter *sc = arg1;
11076 enum cpu_sets op = arg2;
11081 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
11084 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
11088 rc = sysctl_wire_old_buffer(req, 0);
11092 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
11097 sbuf_printf(sb, "%d ", i);
11098 rc = sbuf_finish(sb);
11105 sysctl_reset(SYSCTL_HANDLER_ARGS)
11107 struct adapter *sc = arg1;
11111 val = atomic_load_int(&sc->num_resets);
11112 rc = sysctl_handle_int(oidp, &val, 0, req);
11113 if (rc != 0 || req->newptr == NULL)
11117 /* Zero out the counter that tracks reset. */
11118 atomic_store_int(&sc->num_resets, 0);
11123 return (EINVAL); /* 0 or 1 are the only legal values */
11125 if (hw_off_limits(sc)) /* harmless race */
11128 taskqueue_enqueue(reset_tq, &sc->reset_task);
11134 sysctl_tls(SYSCTL_HANDLER_ARGS)
11136 struct adapter *sc = arg1;
11138 struct vi_info *vi;
11141 rc = sysctl_handle_int(oidp, &v, 0, req);
11142 if (rc != 0 || req->newptr == NULL)
11145 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
11148 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4stls");
11151 if (hw_off_limits(sc))
11155 for_each_port(sc, i) {
11156 for_each_vi(sc->port[i], j, vi) {
11157 if (vi->flags & VI_INIT_DONE)
11158 t4_update_fl_bufsize(vi->ifp);
11162 end_synchronized_op(sc, 0);
11169 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
11171 struct adapter *sc = arg1;
11172 int *old_ports, *new_ports;
11173 int i, new_count, rc;
11175 if (req->newptr == NULL && req->oldptr == NULL)
11176 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
11177 sizeof(sc->tt.tls_rx_ports[0])));
11179 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
11183 if (hw_off_limits(sc)) {
11188 if (sc->tt.num_tls_rx_ports == 0) {
11190 rc = SYSCTL_OUT(req, &i, sizeof(i));
11192 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
11193 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
11194 if (rc == 0 && req->newptr != NULL) {
11195 new_count = req->newlen / sizeof(new_ports[0]);
11196 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
11198 rc = SYSCTL_IN(req, new_ports, new_count *
11199 sizeof(new_ports[0]));
11203 /* Allow setting to a single '-1' to clear the list. */
11204 if (new_count == 1 && new_ports[0] == -1) {
11206 old_ports = sc->tt.tls_rx_ports;
11207 sc->tt.tls_rx_ports = NULL;
11208 sc->tt.num_tls_rx_ports = 0;
11209 ADAPTER_UNLOCK(sc);
11210 free(old_ports, M_CXGBE);
11212 for (i = 0; i < new_count; i++) {
11213 if (new_ports[i] < 1 ||
11214 new_ports[i] > IPPORT_MAX) {
11221 old_ports = sc->tt.tls_rx_ports;
11222 sc->tt.tls_rx_ports = new_ports;
11223 sc->tt.num_tls_rx_ports = new_count;
11224 ADAPTER_UNLOCK(sc);
11225 free(old_ports, M_CXGBE);
11229 free(new_ports, M_CXGBE);
11232 end_synchronized_op(sc, 0);
11237 sysctl_tls_rx_timeout(SYSCTL_HANDLER_ARGS)
11239 struct adapter *sc = arg1;
11242 v = sc->tt.tls_rx_timeout;
11243 rc = sysctl_handle_int(oidp, &v, 0, req);
11244 if (rc != 0 || req->newptr == NULL)
11250 if (v != 0 && !(sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS))
11253 sc->tt.tls_rx_timeout = v;
11260 unit_conv(char *buf, size_t len, u_int val, u_int factor)
11262 u_int rem = val % factor;
11265 snprintf(buf, len, "%u", val / factor);
11267 while (rem % 10 == 0)
11269 snprintf(buf, len, "%u.%u", val / factor, rem);
11274 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
11276 struct adapter *sc = arg1;
11279 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11281 mtx_lock(&sc->reg_lock);
11282 if (hw_off_limits(sc))
11285 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
11286 mtx_unlock(&sc->reg_lock);
11287 if (res == (u_int)-1)
11293 re = G_TIMERRESOLUTION(res);
11296 /* TCP timestamp tick */
11297 re = G_TIMESTAMPRESOLUTION(res);
11301 re = G_DELAYEDACKRESOLUTION(res);
11307 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
11309 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
11313 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
11315 struct adapter *sc = arg1;
11317 u_int dack_tmr, dack_re, v;
11318 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11320 mtx_lock(&sc->reg_lock);
11321 if (hw_off_limits(sc))
11325 dack_re = G_DELAYEDACKRESOLUTION(t4_read_reg(sc,
11326 A_TP_TIMER_RESOLUTION));
11327 dack_tmr = t4_read_reg(sc, A_TP_DACK_TIMER);
11329 mtx_unlock(&sc->reg_lock);
11333 v = ((cclk_ps << dack_re) / 1000000) * dack_tmr;
11335 return (sysctl_handle_int(oidp, &v, 0, req));
11339 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
11341 struct adapter *sc = arg1;
11342 int rc, reg = arg2;
11344 u_long tp_tick_us, v;
11345 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
11347 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
11348 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
11349 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
11350 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
11352 mtx_lock(&sc->reg_lock);
11353 if (hw_off_limits(sc))
11357 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
11358 tp_tick_us = (cclk_ps << tre) / 1000000;
11359 if (reg == A_TP_INIT_SRTT)
11360 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
11362 v = tp_tick_us * t4_read_reg(sc, reg);
11364 mtx_unlock(&sc->reg_lock);
11368 return (sysctl_handle_long(oidp, &v, 0, req));
11372 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
11373 * passed to this function.
11376 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
11378 struct adapter *sc = arg1;
11379 int rc, idx = arg2;
11382 MPASS(idx >= 0 && idx <= 24);
11384 mtx_lock(&sc->reg_lock);
11385 if (hw_off_limits(sc))
11389 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
11391 mtx_unlock(&sc->reg_lock);
11395 return (sysctl_handle_int(oidp, &v, 0, req));
11399 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
11401 struct adapter *sc = arg1;
11402 int rc, idx = arg2;
11405 MPASS(idx >= 0 && idx < 16);
11407 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
11408 shift = (idx & 3) << 3;
11409 mtx_lock(&sc->reg_lock);
11410 if (hw_off_limits(sc))
11414 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
11416 mtx_unlock(&sc->reg_lock);
11420 return (sysctl_handle_int(oidp, &v, 0, req));
11424 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
11426 struct vi_info *vi = arg1;
11427 struct adapter *sc = vi->adapter;
11429 struct sge_ofld_rxq *ofld_rxq;
11432 idx = vi->ofld_tmr_idx;
11434 rc = sysctl_handle_int(oidp, &idx, 0, req);
11435 if (rc != 0 || req->newptr == NULL)
11438 if (idx < 0 || idx >= SGE_NTIMERS)
11441 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
11446 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
11447 for_each_ofld_rxq(vi, i, ofld_rxq) {
11448 #ifdef atomic_store_rel_8
11449 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
11451 ofld_rxq->iq.intr_params = v;
11454 vi->ofld_tmr_idx = idx;
11456 end_synchronized_op(sc, LOCK_HELD);
11461 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
11463 struct vi_info *vi = arg1;
11464 struct adapter *sc = vi->adapter;
11467 idx = vi->ofld_pktc_idx;
11469 rc = sysctl_handle_int(oidp, &idx, 0, req);
11470 if (rc != 0 || req->newptr == NULL)
11473 if (idx < -1 || idx >= SGE_NCOUNTERS)
11476 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
11481 if (vi->flags & VI_INIT_DONE)
11482 rc = EBUSY; /* cannot be changed once the queues are created */
11484 vi->ofld_pktc_idx = idx;
11486 end_synchronized_op(sc, LOCK_HELD);
11492 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
11496 if (cntxt->cid > M_CTXTQID)
11499 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
11500 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
11503 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
11507 if (hw_off_limits(sc)) {
11512 if (sc->flags & FW_OK) {
11513 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
11520 * Read via firmware failed or wasn't even attempted. Read directly via
11523 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
11525 end_synchronized_op(sc, 0);
11530 load_fw(struct adapter *sc, struct t4_data *fw)
11535 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
11539 if (hw_off_limits(sc)) {
11545 * The firmware, with the sole exception of the memory parity error
11546 * handler, runs from memory and not flash. It is almost always safe to
11547 * install a new firmware on a running system. Just set bit 1 in
11548 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
11550 if (sc->flags & FULL_INIT_DONE &&
11551 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
11556 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
11558 rc = copyin(fw->data, fw_data, fw->len);
11560 rc = -t4_load_fw(sc, fw_data, fw->len);
11562 free(fw_data, M_CXGBE);
11564 end_synchronized_op(sc, 0);
11569 load_cfg(struct adapter *sc, struct t4_data *cfg)
11572 uint8_t *cfg_data = NULL;
11574 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
11578 if (hw_off_limits(sc)) {
11583 if (cfg->len == 0) {
11585 rc = -t4_load_cfg(sc, NULL, 0);
11589 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
11591 rc = copyin(cfg->data, cfg_data, cfg->len);
11593 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
11595 free(cfg_data, M_CXGBE);
11597 end_synchronized_op(sc, 0);
11602 load_boot(struct adapter *sc, struct t4_bootrom *br)
11605 uint8_t *br_data = NULL;
11608 if (br->len > 1024 * 1024)
11611 if (br->pf_offset == 0) {
11613 if (br->pfidx_addr > 7)
11615 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
11616 A_PCIE_PF_EXPROM_OFST)));
11617 } else if (br->pf_offset == 1) {
11619 offset = G_OFFSET(br->pfidx_addr);
11624 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
11628 if (hw_off_limits(sc)) {
11633 if (br->len == 0) {
11635 rc = -t4_load_boot(sc, NULL, offset, 0);
11639 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
11641 rc = copyin(br->data, br_data, br->len);
11643 rc = -t4_load_boot(sc, br_data, offset, br->len);
11645 free(br_data, M_CXGBE);
11647 end_synchronized_op(sc, 0);
11652 load_bootcfg(struct adapter *sc, struct t4_data *bc)
11655 uint8_t *bc_data = NULL;
11657 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
11661 if (hw_off_limits(sc)) {
11666 if (bc->len == 0) {
11668 rc = -t4_load_bootcfg(sc, NULL, 0);
11672 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
11674 rc = copyin(bc->data, bc_data, bc->len);
11676 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
11678 free(bc_data, M_CXGBE);
11680 end_synchronized_op(sc, 0);
11685 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
11688 struct cudbg_init *cudbg;
11689 void *handle, *buf;
11691 /* buf is large, don't block if no memory is available */
11692 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
11696 handle = cudbg_alloc_handle();
11697 if (handle == NULL) {
11702 cudbg = cudbg_get_init(handle);
11704 cudbg->print = (cudbg_print_cb)printf;
11707 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
11708 __func__, dump->wr_flash, dump->len, dump->data);
11711 if (dump->wr_flash)
11712 cudbg->use_flash = 1;
11713 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
11714 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
11716 rc = cudbg_collect(handle, buf, &dump->len);
11720 rc = copyout(buf, dump->data, dump->len);
11722 cudbg_free_handle(handle);
11723 free(buf, M_CXGBE);
11728 free_offload_policy(struct t4_offload_policy *op)
11730 struct offload_rule *r;
11737 for (i = 0; i < op->nrules; i++, r++) {
11738 free(r->bpf_prog.bf_insns, M_CXGBE);
11740 free(op->rule, M_CXGBE);
11745 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
11748 struct t4_offload_policy *op, *old;
11749 struct bpf_program *bf;
11750 const struct offload_settings *s;
11751 struct offload_rule *r;
11754 if (!is_offload(sc))
11757 if (uop->nrules == 0) {
11758 /* Delete installed policies. */
11761 } else if (uop->nrules > 256) { /* arbitrary */
11765 /* Copy userspace offload policy to kernel */
11766 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
11767 op->nrules = uop->nrules;
11768 len = op->nrules * sizeof(struct offload_rule);
11769 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
11770 rc = copyin(uop->rule, op->rule, len);
11772 free(op->rule, M_CXGBE);
11778 for (i = 0; i < op->nrules; i++, r++) {
11780 /* Validate open_type */
11781 if (r->open_type != OPEN_TYPE_LISTEN &&
11782 r->open_type != OPEN_TYPE_ACTIVE &&
11783 r->open_type != OPEN_TYPE_PASSIVE &&
11784 r->open_type != OPEN_TYPE_DONTCARE) {
11787 * Rules 0 to i have malloc'd filters that need to be
11788 * freed. Rules i+1 to nrules have userspace pointers
11789 * and should be left alone.
11792 free_offload_policy(op);
11796 /* Validate settings */
11798 if ((s->offload != 0 && s->offload != 1) ||
11799 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
11800 s->sched_class < -1 ||
11801 s->sched_class >= sc->params.nsched_cls) {
11807 u = bf->bf_insns; /* userspace ptr */
11808 bf->bf_insns = NULL;
11809 if (bf->bf_len == 0) {
11810 /* legal, matches everything */
11813 len = bf->bf_len * sizeof(*bf->bf_insns);
11814 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
11815 rc = copyin(u, bf->bf_insns, len);
11819 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
11825 rw_wlock(&sc->policy_lock);
11828 rw_wunlock(&sc->policy_lock);
11829 free_offload_policy(old);
11834 #define MAX_READ_BUF_SIZE (128 * 1024)
11836 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
11838 uint32_t addr, remaining, n;
11843 mtx_lock(&sc->reg_lock);
11844 if (hw_off_limits(sc))
11847 rc = validate_mem_range(sc, mr->addr, mr->len);
11848 mtx_unlock(&sc->reg_lock);
11852 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
11854 remaining = mr->len;
11855 dst = (void *)mr->data;
11857 while (remaining) {
11858 n = min(remaining, MAX_READ_BUF_SIZE);
11859 mtx_lock(&sc->reg_lock);
11860 if (hw_off_limits(sc))
11863 read_via_memwin(sc, 2, addr, buf, n);
11864 mtx_unlock(&sc->reg_lock);
11868 rc = copyout(buf, dst, n);
11877 free(buf, M_CXGBE);
11880 #undef MAX_READ_BUF_SIZE
11883 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
11887 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
11890 if (i2cd->len > sizeof(i2cd->data))
11893 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
11896 if (hw_off_limits(sc))
11899 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
11900 i2cd->offset, i2cd->len, &i2cd->data[0]);
11901 end_synchronized_op(sc, 0);
11907 clear_stats(struct adapter *sc, u_int port_id)
11909 int i, v, chan_map;
11910 struct port_info *pi;
11911 struct vi_info *vi;
11912 struct sge_rxq *rxq;
11913 struct sge_txq *txq;
11914 struct sge_wrq *wrq;
11915 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
11916 struct sge_ofld_txq *ofld_txq;
11919 struct sge_ofld_rxq *ofld_rxq;
11922 if (port_id >= sc->params.nports)
11924 pi = sc->port[port_id];
11928 mtx_lock(&sc->reg_lock);
11929 if (!hw_off_limits(sc)) {
11931 t4_clr_port_stats(sc, pi->tx_chan);
11933 if (pi->fcs_reg != -1)
11934 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
11936 pi->stats.rx_fcs_err = 0;
11938 for_each_vi(pi, v, vi) {
11939 if (vi->flags & VI_INIT_DONE)
11940 t4_clr_vi_stats(sc, vi->vin);
11942 chan_map = pi->rx_e_chan_map;
11945 i = ffs(chan_map) - 1;
11946 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
11947 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
11948 chan_map &= ~(1 << i);
11951 mtx_unlock(&sc->reg_lock);
11952 pi->tx_parse_error = 0;
11953 pi->tnl_cong_drops = 0;
11956 * Since this command accepts a port, clear stats for
11957 * all VIs on this port.
11959 for_each_vi(pi, v, vi) {
11960 if (vi->flags & VI_INIT_DONE) {
11962 for_each_rxq(vi, i, rxq) {
11963 #if defined(INET) || defined(INET6)
11964 rxq->lro.lro_queued = 0;
11965 rxq->lro.lro_flushed = 0;
11968 rxq->vlan_extraction = 0;
11969 rxq->vxlan_rxcsum = 0;
11971 rxq->fl.cl_allocated = 0;
11972 rxq->fl.cl_recycled = 0;
11973 rxq->fl.cl_fast_recycled = 0;
11976 for_each_txq(vi, i, txq) {
11979 txq->vlan_insertion = 0;
11982 txq->txpkt_wrs = 0;
11983 txq->txpkts0_wrs = 0;
11984 txq->txpkts1_wrs = 0;
11985 txq->txpkts0_pkts = 0;
11986 txq->txpkts1_pkts = 0;
11987 txq->txpkts_flush = 0;
11989 txq->vxlan_tso_wrs = 0;
11990 txq->vxlan_txcsum = 0;
11991 txq->kern_tls_records = 0;
11992 txq->kern_tls_short = 0;
11993 txq->kern_tls_partial = 0;
11994 txq->kern_tls_full = 0;
11995 txq->kern_tls_octets = 0;
11996 txq->kern_tls_waste = 0;
11997 txq->kern_tls_options = 0;
11998 txq->kern_tls_header = 0;
11999 txq->kern_tls_fin = 0;
12000 txq->kern_tls_fin_short = 0;
12001 txq->kern_tls_cbc = 0;
12002 txq->kern_tls_gcm = 0;
12003 mp_ring_reset_stats(txq->r);
12006 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12007 for_each_ofld_txq(vi, i, ofld_txq) {
12008 ofld_txq->wrq.tx_wrs_direct = 0;
12009 ofld_txq->wrq.tx_wrs_copied = 0;
12010 counter_u64_zero(ofld_txq->tx_iscsi_pdus);
12011 counter_u64_zero(ofld_txq->tx_iscsi_octets);
12012 counter_u64_zero(ofld_txq->tx_iscsi_iso_wrs);
12013 counter_u64_zero(ofld_txq->tx_toe_tls_records);
12014 counter_u64_zero(ofld_txq->tx_toe_tls_octets);
12018 for_each_ofld_rxq(vi, i, ofld_rxq) {
12019 ofld_rxq->fl.cl_allocated = 0;
12020 ofld_rxq->fl.cl_recycled = 0;
12021 ofld_rxq->fl.cl_fast_recycled = 0;
12023 ofld_rxq->rx_iscsi_ddp_setup_ok);
12025 ofld_rxq->rx_iscsi_ddp_setup_error);
12026 ofld_rxq->rx_iscsi_ddp_pdus = 0;
12027 ofld_rxq->rx_iscsi_ddp_octets = 0;
12028 ofld_rxq->rx_iscsi_fl_pdus = 0;
12029 ofld_rxq->rx_iscsi_fl_octets = 0;
12030 ofld_rxq->rx_toe_tls_records = 0;
12031 ofld_rxq->rx_toe_tls_octets = 0;
12035 if (IS_MAIN_VI(vi)) {
12036 wrq = &sc->sge.ctrlq[pi->port_id];
12037 wrq->tx_wrs_direct = 0;
12038 wrq->tx_wrs_copied = 0;
12047 hold_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
12050 struct in6_addr in6;
12052 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
12053 if (t4_get_clip_entry(sc, &in6, true) != NULL)
12063 release_clip_addr(struct adapter *sc, struct t4_clip_addr *ca)
12066 struct in6_addr in6;
12068 bcopy(&ca->addr[0], &in6.s6_addr[0], sizeof(in6.s6_addr));
12069 return (t4_release_clip_addr(sc, &in6));
12076 t4_os_find_pci_capability(struct adapter *sc, int cap)
12080 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
12084 t4_os_pci_save_state(struct adapter *sc)
12087 struct pci_devinfo *dinfo;
12090 dinfo = device_get_ivars(dev);
12092 pci_cfg_save(dev, dinfo, 0);
12097 t4_os_pci_restore_state(struct adapter *sc)
12100 struct pci_devinfo *dinfo;
12103 dinfo = device_get_ivars(dev);
12105 pci_cfg_restore(dev, dinfo);
12110 t4_os_portmod_changed(struct port_info *pi)
12112 struct adapter *sc = pi->adapter;
12113 struct vi_info *vi;
12115 static const char *mod_str[] = {
12116 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
12119 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
12120 ("%s: port_type %u", __func__, pi->port_type));
12123 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
12125 build_medialist(pi);
12126 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
12127 fixup_link_config(pi);
12128 apply_link_config(pi);
12131 end_synchronized_op(sc, LOCK_HELD);
12135 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
12136 if_printf(ifp, "transceiver unplugged.\n");
12137 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
12138 if_printf(ifp, "unknown transceiver inserted.\n");
12139 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
12140 if_printf(ifp, "unsupported transceiver inserted.\n");
12141 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
12142 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
12143 port_top_speed(pi), mod_str[pi->mod_type]);
12145 if_printf(ifp, "transceiver (type %d) inserted.\n",
12151 t4_os_link_changed(struct port_info *pi)
12153 struct vi_info *vi;
12155 struct link_config *lc = &pi->link_cfg;
12156 struct adapter *sc = pi->adapter;
12159 PORT_LOCK_ASSERT_OWNED(pi);
12163 if (lc->speed > 25000 ||
12164 (lc->speed == 25000 && lc->fec == FEC_RS)) {
12165 pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
12166 A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS);
12168 pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
12169 A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS);
12171 pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
12172 pi->stats.rx_fcs_err = 0;
12177 MPASS(pi->fcs_reg != -1);
12178 MPASS(pi->fcs_base == 0);
12181 for_each_vi(pi, v, vi) {
12187 ifp->if_baudrate = IF_Mbps(lc->speed);
12188 if_link_state_change(ifp, LINK_STATE_UP);
12190 if_link_state_change(ifp, LINK_STATE_DOWN);
12196 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
12198 struct adapter *sc;
12200 sx_slock(&t4_list_lock);
12201 SLIST_FOREACH(sc, &t4_list, link) {
12203 * func should not make any assumptions about what state sc is
12204 * in - the only guarantee is that sc->sc_lock is a valid lock.
12208 sx_sunlock(&t4_list_lock);
12212 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
12216 struct adapter *sc = dev->si_drv1;
12218 rc = priv_check(td, PRIV_DRIVER);
12223 case CHELSIO_T4_GETREG: {
12224 struct t4_reg *edata = (struct t4_reg *)data;
12226 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
12229 mtx_lock(&sc->reg_lock);
12230 if (hw_off_limits(sc))
12232 else if (edata->size == 4)
12233 edata->val = t4_read_reg(sc, edata->addr);
12234 else if (edata->size == 8)
12235 edata->val = t4_read_reg64(sc, edata->addr);
12238 mtx_unlock(&sc->reg_lock);
12242 case CHELSIO_T4_SETREG: {
12243 struct t4_reg *edata = (struct t4_reg *)data;
12245 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
12248 mtx_lock(&sc->reg_lock);
12249 if (hw_off_limits(sc))
12251 else if (edata->size == 4) {
12252 if (edata->val & 0xffffffff00000000)
12254 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
12255 } else if (edata->size == 8)
12256 t4_write_reg64(sc, edata->addr, edata->val);
12259 mtx_unlock(&sc->reg_lock);
12263 case CHELSIO_T4_REGDUMP: {
12264 struct t4_regdump *regs = (struct t4_regdump *)data;
12265 int reglen = t4_get_regs_len(sc);
12268 if (regs->len < reglen) {
12269 regs->len = reglen; /* hint to the caller */
12273 regs->len = reglen;
12274 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
12275 mtx_lock(&sc->reg_lock);
12276 if (hw_off_limits(sc))
12279 get_regs(sc, regs, buf);
12280 mtx_unlock(&sc->reg_lock);
12282 rc = copyout(buf, regs->data, reglen);
12283 free(buf, M_CXGBE);
12286 case CHELSIO_T4_GET_FILTER_MODE:
12287 rc = get_filter_mode(sc, (uint32_t *)data);
12289 case CHELSIO_T4_SET_FILTER_MODE:
12290 rc = set_filter_mode(sc, *(uint32_t *)data);
12292 case CHELSIO_T4_SET_FILTER_MASK:
12293 rc = set_filter_mask(sc, *(uint32_t *)data);
12295 case CHELSIO_T4_GET_FILTER:
12296 rc = get_filter(sc, (struct t4_filter *)data);
12298 case CHELSIO_T4_SET_FILTER:
12299 rc = set_filter(sc, (struct t4_filter *)data);
12301 case CHELSIO_T4_DEL_FILTER:
12302 rc = del_filter(sc, (struct t4_filter *)data);
12304 case CHELSIO_T4_GET_SGE_CONTEXT:
12305 rc = get_sge_context(sc, (struct t4_sge_context *)data);
12307 case CHELSIO_T4_LOAD_FW:
12308 rc = load_fw(sc, (struct t4_data *)data);
12310 case CHELSIO_T4_GET_MEM:
12311 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
12313 case CHELSIO_T4_GET_I2C:
12314 rc = read_i2c(sc, (struct t4_i2c_data *)data);
12316 case CHELSIO_T4_CLEAR_STATS:
12317 rc = clear_stats(sc, *(uint32_t *)data);
12319 case CHELSIO_T4_SCHED_CLASS:
12320 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
12322 case CHELSIO_T4_SCHED_QUEUE:
12323 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
12325 case CHELSIO_T4_GET_TRACER:
12326 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
12328 case CHELSIO_T4_SET_TRACER:
12329 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
12331 case CHELSIO_T4_LOAD_CFG:
12332 rc = load_cfg(sc, (struct t4_data *)data);
12334 case CHELSIO_T4_LOAD_BOOT:
12335 rc = load_boot(sc, (struct t4_bootrom *)data);
12337 case CHELSIO_T4_LOAD_BOOTCFG:
12338 rc = load_bootcfg(sc, (struct t4_data *)data);
12340 case CHELSIO_T4_CUDBG_DUMP:
12341 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
12343 case CHELSIO_T4_SET_OFLD_POLICY:
12344 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
12346 case CHELSIO_T4_HOLD_CLIP_ADDR:
12347 rc = hold_clip_addr(sc, (struct t4_clip_addr *)data);
12349 case CHELSIO_T4_RELEASE_CLIP_ADDR:
12350 rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
12361 toe_capability(struct vi_info *vi, bool enable)
12364 struct port_info *pi = vi->pi;
12365 struct adapter *sc = pi->adapter;
12367 ASSERT_SYNCHRONIZED_OP(sc);
12369 if (!is_offload(sc))
12371 if (hw_off_limits(sc))
12376 if (sc->flags & KERN_TLS_ON) {
12378 struct port_info *p;
12382 * Reconfigure hardware for TOE if TXTLS is not enabled
12386 for_each_port(sc, i) {
12388 for_each_vi(p, j, v) {
12389 if (v->ifp->if_capenable & IFCAP_TXTLS) {
12391 "%s has NIC TLS enabled.\n",
12392 device_get_nameunit(v->dev));
12398 CH_WARN(sc, "Disable NIC TLS on all interfaces "
12399 "associated with this adapter before "
12400 "trying to enable TOE.\n");
12403 rc = t4_config_kern_tls(sc, false);
12408 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
12409 /* TOE is already enabled. */
12414 * We need the port's queues around so that we're able to send
12415 * and receive CPLs to/from the TOE even if the ifnet for this
12416 * port has never been UP'd administratively.
12418 if (!(vi->flags & VI_INIT_DONE) && ((rc = vi_init(vi)) != 0))
12420 if (!(pi->vi[0].flags & VI_INIT_DONE) &&
12421 ((rc = vi_init(&pi->vi[0])) != 0))
12424 if (isset(&sc->offload_map, pi->port_id)) {
12425 /* TOE is enabled on another VI of this port. */
12430 if (!uld_active(sc, ULD_TOM)) {
12431 rc = t4_activate_uld(sc, ULD_TOM);
12432 if (rc == EAGAIN) {
12434 "You must kldload t4_tom.ko before trying "
12435 "to enable TOE on a cxgbe interface.\n");
12439 KASSERT(sc->tom_softc != NULL,
12440 ("%s: TOM activated but softc NULL", __func__));
12441 KASSERT(uld_active(sc, ULD_TOM),
12442 ("%s: TOM activated but flag not set", __func__));
12445 /* Activate iWARP and iSCSI too, if the modules are loaded. */
12446 if (!uld_active(sc, ULD_IWARP))
12447 (void) t4_activate_uld(sc, ULD_IWARP);
12448 if (!uld_active(sc, ULD_ISCSI))
12449 (void) t4_activate_uld(sc, ULD_ISCSI);
12452 setbit(&sc->offload_map, pi->port_id);
12456 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
12459 KASSERT(uld_active(sc, ULD_TOM),
12460 ("%s: TOM never initialized?", __func__));
12461 clrbit(&sc->offload_map, pi->port_id);
12468 * Add an upper layer driver to the global list.
12471 t4_register_uld(struct uld_info *ui)
12474 struct uld_info *u;
12476 sx_xlock(&t4_uld_list_lock);
12477 SLIST_FOREACH(u, &t4_uld_list, link) {
12478 if (u->uld_id == ui->uld_id) {
12484 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
12487 sx_xunlock(&t4_uld_list_lock);
12492 t4_unregister_uld(struct uld_info *ui)
12495 struct uld_info *u;
12497 sx_xlock(&t4_uld_list_lock);
12499 SLIST_FOREACH(u, &t4_uld_list, link) {
12501 if (ui->refcount > 0) {
12506 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
12512 sx_xunlock(&t4_uld_list_lock);
12517 t4_activate_uld(struct adapter *sc, int id)
12520 struct uld_info *ui;
12522 ASSERT_SYNCHRONIZED_OP(sc);
12524 if (id < 0 || id > ULD_MAX)
12526 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
12528 sx_slock(&t4_uld_list_lock);
12530 SLIST_FOREACH(ui, &t4_uld_list, link) {
12531 if (ui->uld_id == id) {
12532 if (!(sc->flags & FULL_INIT_DONE)) {
12533 rc = adapter_init(sc);
12538 rc = ui->activate(sc);
12540 setbit(&sc->active_ulds, id);
12547 sx_sunlock(&t4_uld_list_lock);
12553 t4_deactivate_uld(struct adapter *sc, int id)
12556 struct uld_info *ui;
12558 ASSERT_SYNCHRONIZED_OP(sc);
12560 if (id < 0 || id > ULD_MAX)
12564 sx_slock(&t4_uld_list_lock);
12566 SLIST_FOREACH(ui, &t4_uld_list, link) {
12567 if (ui->uld_id == id) {
12568 rc = ui->deactivate(sc);
12570 clrbit(&sc->active_ulds, id);
12577 sx_sunlock(&t4_uld_list_lock);
12583 t4_async_event(struct adapter *sc)
12585 struct uld_info *ui;
12587 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0)
12589 sx_slock(&t4_uld_list_lock);
12590 SLIST_FOREACH(ui, &t4_uld_list, link) {
12591 if (ui->uld_id == ULD_IWARP) {
12592 ui->async_event(sc);
12596 sx_sunlock(&t4_uld_list_lock);
12597 end_synchronized_op(sc, 0);
12601 uld_active(struct adapter *sc, int uld_id)
12604 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
12606 return (isset(&sc->active_ulds, uld_id));
12612 ktls_capability(struct adapter *sc, bool enable)
12614 ASSERT_SYNCHRONIZED_OP(sc);
12618 if (hw_off_limits(sc))
12622 if (sc->flags & KERN_TLS_ON)
12623 return (0); /* already on */
12624 if (sc->offload_map != 0) {
12626 "Disable TOE on all interfaces associated with "
12627 "this adapter before trying to enable NIC TLS.\n");
12630 return (t4_config_kern_tls(sc, true));
12633 * Nothing to do for disable. If TOE is enabled sometime later
12634 * then toe_capability will reconfigure the hardware.
12642 * t = ptr to tunable.
12643 * nc = number of CPUs.
12644 * c = compiled in default for that tunable.
12647 calculate_nqueues(int *t, int nc, const int c)
12653 nq = *t < 0 ? -*t : c;
12658 * Come up with reasonable defaults for some of the tunables, provided they're
12659 * not set by the user (in which case we'll use the values as is).
12662 tweak_tunables(void)
12664 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
12668 t4_ntxq = rss_getnumbuckets();
12670 calculate_nqueues(&t4_ntxq, nc, NTXQ);
12674 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
12678 t4_nrxq = rss_getnumbuckets();
12680 calculate_nqueues(&t4_nrxq, nc, NRXQ);
12684 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
12686 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
12687 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
12688 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
12691 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
12692 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
12695 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
12696 if (t4_toecaps_allowed == -1)
12697 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
12699 if (t4_toecaps_allowed == -1)
12700 t4_toecaps_allowed = 0;
12704 if (t4_rdmacaps_allowed == -1) {
12705 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
12706 FW_CAPS_CONFIG_RDMA_RDMAC;
12709 if (t4_iscsicaps_allowed == -1) {
12710 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
12711 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
12712 FW_CAPS_CONFIG_ISCSI_T10DIF;
12715 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
12716 t4_tmr_idx_ofld = TMR_IDX_OFLD;
12718 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
12719 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
12721 if (t4_toe_tls_rx_timeout < 0)
12722 t4_toe_tls_rx_timeout = 0;
12724 if (t4_rdmacaps_allowed == -1)
12725 t4_rdmacaps_allowed = 0;
12727 if (t4_iscsicaps_allowed == -1)
12728 t4_iscsicaps_allowed = 0;
12732 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
12733 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
12734 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
12735 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
12738 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
12739 t4_tmr_idx = TMR_IDX;
12741 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
12742 t4_pktc_idx = PKTC_IDX;
12744 if (t4_qsize_txq < 128)
12745 t4_qsize_txq = 128;
12747 if (t4_qsize_rxq < 128)
12748 t4_qsize_rxq = 128;
12749 while (t4_qsize_rxq & 7)
12752 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
12755 * Number of VIs to create per-port. The first VI is the "main" regular
12756 * VI for the port. The rest are additional virtual interfaces on the
12757 * same physical port. Note that the main VI does not have native
12758 * netmap support but the extra VIs do.
12760 * Limit the number of VIs per port to the number of available
12761 * MAC addresses per port.
12763 if (t4_num_vis < 1)
12765 if (t4_num_vis > nitems(vi_mac_funcs)) {
12766 t4_num_vis = nitems(vi_mac_funcs);
12767 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
12770 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
12771 pcie_relaxed_ordering = 1;
12772 #if defined(__i386__) || defined(__amd64__)
12773 if (cpu_vendor_id == CPU_VENDOR_INTEL)
12774 pcie_relaxed_ordering = 0;
12781 t4_dump_tcb(struct adapter *sc, int tid)
12783 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
12785 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
12786 save = t4_read_reg(sc, reg);
12787 base = sc->memwin[2].mw_base;
12789 /* Dump TCB for the tid */
12790 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
12791 tcb_addr += tid * TCB_SIZE;
12795 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
12797 pf = V_PFNUM(sc->pf);
12798 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
12800 t4_write_reg(sc, reg, win_pos | pf);
12801 t4_read_reg(sc, reg);
12803 off = tcb_addr - win_pos;
12804 for (i = 0; i < 4; i++) {
12806 for (j = 0; j < 8; j++, off += 4)
12807 buf[j] = htonl(t4_read_reg(sc, base + off));
12809 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
12810 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
12814 t4_write_reg(sc, reg, save);
12815 t4_read_reg(sc, reg);
12819 t4_dump_devlog(struct adapter *sc)
12821 struct devlog_params *dparams = &sc->params.devlog;
12822 struct fw_devlog_e e;
12823 int i, first, j, m, nentries, rc;
12824 uint64_t ftstamp = UINT64_MAX;
12826 if (dparams->start == 0) {
12827 db_printf("devlog params not valid\n");
12831 nentries = dparams->size / sizeof(struct fw_devlog_e);
12832 m = fwmtype_to_hwmtype(dparams->memtype);
12834 /* Find the first entry. */
12836 for (i = 0; i < nentries && !db_pager_quit; i++) {
12837 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
12838 sizeof(e), (void *)&e);
12842 if (e.timestamp == 0)
12845 e.timestamp = be64toh(e.timestamp);
12846 if (e.timestamp < ftstamp) {
12847 ftstamp = e.timestamp;
12857 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
12858 sizeof(e), (void *)&e);
12862 if (e.timestamp == 0)
12865 e.timestamp = be64toh(e.timestamp);
12866 e.seqno = be32toh(e.seqno);
12867 for (j = 0; j < 8; j++)
12868 e.params[j] = be32toh(e.params[j]);
12870 db_printf("%10d %15ju %8s %8s ",
12871 e.seqno, e.timestamp,
12872 (e.level < nitems(devlog_level_strings) ?
12873 devlog_level_strings[e.level] : "UNKNOWN"),
12874 (e.facility < nitems(devlog_facility_strings) ?
12875 devlog_facility_strings[e.facility] : "UNKNOWN"));
12876 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
12877 e.params[3], e.params[4], e.params[5], e.params[6],
12880 if (++i == nentries)
12882 } while (i != first && !db_pager_quit);
12885 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
12886 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
12888 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
12895 t = db_read_token();
12897 dev = device_lookup_by_name(db_tok_string);
12902 db_printf("usage: show t4 devlog <nexus>\n");
12907 db_printf("device not found\n");
12911 t4_dump_devlog(device_get_softc(dev));
12914 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
12923 t = db_read_token();
12925 dev = device_lookup_by_name(db_tok_string);
12926 t = db_read_token();
12927 if (t == tNUMBER) {
12928 tid = db_tok_number;
12935 db_printf("usage: show t4 tcb <nexus> <tid>\n");
12940 db_printf("device not found\n");
12944 db_printf("invalid tid\n");
12948 t4_dump_tcb(device_get_softc(dev), tid);
12952 static eventhandler_tag vxlan_start_evtag;
12953 static eventhandler_tag vxlan_stop_evtag;
12955 struct vxlan_evargs {
12961 enable_vxlan_rx(struct adapter *sc)
12964 struct port_info *pi;
12965 uint8_t match_all_mac[ETHER_ADDR_LEN] = {0};
12967 ASSERT_SYNCHRONIZED_OP(sc);
12969 t4_write_reg(sc, A_MPS_RX_VXLAN_TYPE, V_VXLAN(sc->vxlan_port) |
12971 for_each_port(sc, i) {
12973 if (pi->vxlan_tcam_entry == true)
12975 rc = t4_alloc_raw_mac_filt(sc, pi->vi[0].viid, match_all_mac,
12976 match_all_mac, sc->rawf_base + pi->port_id, 1, pi->port_id,
12981 "failed to add VXLAN TCAM entry: %d.\n", rc);
12983 MPASS(rc == sc->rawf_base + pi->port_id);
12984 pi->vxlan_tcam_entry = true;
12990 t4_vxlan_start(struct adapter *sc, void *arg)
12992 struct vxlan_evargs *v = arg;
12994 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
12996 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxst") != 0)
12999 if (sc->vxlan_refcount == 0) {
13000 sc->vxlan_port = v->port;
13001 sc->vxlan_refcount = 1;
13002 if (!hw_off_limits(sc))
13003 enable_vxlan_rx(sc);
13004 } else if (sc->vxlan_port == v->port) {
13005 sc->vxlan_refcount++;
13007 CH_ERR(sc, "VXLAN already configured on port %d; "
13008 "ignoring attempt to configure it on port %d\n",
13009 sc->vxlan_port, v->port);
13011 end_synchronized_op(sc, 0);
13015 t4_vxlan_stop(struct adapter *sc, void *arg)
13017 struct vxlan_evargs *v = arg;
13019 if (sc->nrawf == 0 || chip_id(sc) <= CHELSIO_T5)
13021 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4vxsp") != 0)
13025 * VXLANs may have been configured before the driver was loaded so we
13026 * may see more stops than starts. This is not handled cleanly but at
13027 * least we keep the refcount sane.
13029 if (sc->vxlan_port != v->port)
13031 if (sc->vxlan_refcount == 0) {
13032 CH_ERR(sc, "VXLAN operation on port %d was stopped earlier; "
13033 "ignoring attempt to stop it again.\n", sc->vxlan_port);
13034 } else if (--sc->vxlan_refcount == 0 && !hw_off_limits(sc))
13035 t4_set_reg_field(sc, A_MPS_RX_VXLAN_TYPE, F_VXLAN_EN, 0);
13037 end_synchronized_op(sc, 0);
13041 t4_vxlan_start_handler(void *arg __unused, struct ifnet *ifp,
13042 sa_family_t family, u_int port)
13044 struct vxlan_evargs v;
13046 MPASS(family == AF_INET || family == AF_INET6);
13050 t4_iterate(t4_vxlan_start, &v);
13054 t4_vxlan_stop_handler(void *arg __unused, struct ifnet *ifp, sa_family_t family,
13057 struct vxlan_evargs v;
13059 MPASS(family == AF_INET || family == AF_INET6);
13063 t4_iterate(t4_vxlan_stop, &v);
13067 static struct sx mlu; /* mod load unload */
13068 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
13071 mod_event(module_t mod, int cmd, void *arg)
13074 static int loaded = 0;
13079 if (loaded++ == 0) {
13081 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
13082 t4_filter_rpl, CPL_COOKIE_FILTER);
13083 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
13084 do_l2t_write_rpl, CPL_COOKIE_FILTER);
13085 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
13086 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
13087 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
13088 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
13089 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
13090 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
13091 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
13092 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
13093 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
13095 sx_init(&t4_list_lock, "T4/T5 adapters");
13096 SLIST_INIT(&t4_list);
13097 callout_init(&fatal_callout, 1);
13099 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
13100 SLIST_INIT(&t4_uld_list);
13108 t4_tracer_modload();
13110 vxlan_start_evtag =
13111 EVENTHANDLER_REGISTER(vxlan_start,
13112 t4_vxlan_start_handler, NULL,
13113 EVENTHANDLER_PRI_ANY);
13115 EVENTHANDLER_REGISTER(vxlan_stop,
13116 t4_vxlan_stop_handler, NULL,
13117 EVENTHANDLER_PRI_ANY);
13118 reset_tq = taskqueue_create("t4_rst_tq", M_WAITOK,
13119 taskqueue_thread_enqueue, &reset_tq);
13120 taskqueue_start_threads(&reset_tq, 1, PI_SOFT,
13128 if (--loaded == 0) {
13131 taskqueue_free(reset_tq);
13132 sx_slock(&t4_list_lock);
13133 if (!SLIST_EMPTY(&t4_list)) {
13135 sx_sunlock(&t4_list_lock);
13139 sx_slock(&t4_uld_list_lock);
13140 if (!SLIST_EMPTY(&t4_uld_list)) {
13142 sx_sunlock(&t4_uld_list_lock);
13143 sx_sunlock(&t4_list_lock);
13148 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
13149 uprintf("%ju clusters with custom free routine "
13150 "still is use.\n", t4_sge_extfree_refs());
13151 pause("t4unload", 2 * hz);
13154 sx_sunlock(&t4_uld_list_lock);
13156 sx_sunlock(&t4_list_lock);
13158 if (t4_sge_extfree_refs() == 0) {
13159 EVENTHANDLER_DEREGISTER(vxlan_start,
13160 vxlan_start_evtag);
13161 EVENTHANDLER_DEREGISTER(vxlan_stop,
13163 t4_tracer_modunload();
13165 t6_ktls_modunload();
13168 t4_clip_modunload();
13171 sx_destroy(&t4_uld_list_lock);
13173 sx_destroy(&t4_list_lock);
13174 t4_sge_modunload();
13178 loaded++; /* undo earlier decrement */
13189 static devclass_t t4_devclass, t5_devclass, t6_devclass;
13190 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
13191 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
13193 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
13194 MODULE_VERSION(t4nex, 1);
13195 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
13197 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
13198 #endif /* DEV_NETMAP */
13200 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
13201 MODULE_VERSION(t5nex, 1);
13202 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
13204 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
13205 #endif /* DEV_NETMAP */
13207 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
13208 MODULE_VERSION(t6nex, 1);
13209 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
13211 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
13212 #endif /* DEV_NETMAP */
13214 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
13215 MODULE_VERSION(cxgbe, 1);
13217 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
13218 MODULE_VERSION(cxl, 1);
13220 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
13221 MODULE_VERSION(cc, 1);
13223 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
13224 MODULE_VERSION(vcxgbe, 1);
13226 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
13227 MODULE_VERSION(vcxl, 1);
13229 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
13230 MODULE_VERSION(vcc, 1);