2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
74 #include <crypto/rijndael/rijndael.h>
77 #include <ddb/db_lex.h>
80 #include "common/common.h"
81 #include "common/t4_msg.h"
82 #include "common/t4_regs.h"
83 #include "common/t4_regs_values.h"
84 #include "cudbg/cudbg.h"
88 #include "t4_mp_ring.h"
92 /* T4 bus driver interface */
93 static int t4_probe(device_t);
94 static int t4_attach(device_t);
95 static int t4_detach(device_t);
96 static int t4_child_location_str(device_t, device_t, char *, size_t);
97 static int t4_ready(device_t);
98 static int t4_read_port_device(device_t, int, device_t *);
99 static device_method_t t4_methods[] = {
100 DEVMETHOD(device_probe, t4_probe),
101 DEVMETHOD(device_attach, t4_attach),
102 DEVMETHOD(device_detach, t4_detach),
104 DEVMETHOD(bus_child_location_str, t4_child_location_str),
106 DEVMETHOD(t4_is_main_ready, t4_ready),
107 DEVMETHOD(t4_read_port_device, t4_read_port_device),
111 static driver_t t4_driver = {
114 sizeof(struct adapter)
118 /* T4 port (cxgbe) interface */
119 static int cxgbe_probe(device_t);
120 static int cxgbe_attach(device_t);
121 static int cxgbe_detach(device_t);
122 device_method_t cxgbe_methods[] = {
123 DEVMETHOD(device_probe, cxgbe_probe),
124 DEVMETHOD(device_attach, cxgbe_attach),
125 DEVMETHOD(device_detach, cxgbe_detach),
128 static driver_t cxgbe_driver = {
131 sizeof(struct port_info)
134 /* T4 VI (vcxgbe) interface */
135 static int vcxgbe_probe(device_t);
136 static int vcxgbe_attach(device_t);
137 static int vcxgbe_detach(device_t);
138 static device_method_t vcxgbe_methods[] = {
139 DEVMETHOD(device_probe, vcxgbe_probe),
140 DEVMETHOD(device_attach, vcxgbe_attach),
141 DEVMETHOD(device_detach, vcxgbe_detach),
144 static driver_t vcxgbe_driver = {
147 sizeof(struct vi_info)
150 static d_ioctl_t t4_ioctl;
152 static struct cdevsw t4_cdevsw = {
153 .d_version = D_VERSION,
158 /* T5 bus driver interface */
159 static int t5_probe(device_t);
160 static device_method_t t5_methods[] = {
161 DEVMETHOD(device_probe, t5_probe),
162 DEVMETHOD(device_attach, t4_attach),
163 DEVMETHOD(device_detach, t4_detach),
165 DEVMETHOD(bus_child_location_str, t4_child_location_str),
167 DEVMETHOD(t4_is_main_ready, t4_ready),
168 DEVMETHOD(t4_read_port_device, t4_read_port_device),
172 static driver_t t5_driver = {
175 sizeof(struct adapter)
179 /* T5 port (cxl) interface */
180 static driver_t cxl_driver = {
183 sizeof(struct port_info)
186 /* T5 VI (vcxl) interface */
187 static driver_t vcxl_driver = {
190 sizeof(struct vi_info)
193 /* T6 bus driver interface */
194 static int t6_probe(device_t);
195 static device_method_t t6_methods[] = {
196 DEVMETHOD(device_probe, t6_probe),
197 DEVMETHOD(device_attach, t4_attach),
198 DEVMETHOD(device_detach, t4_detach),
200 DEVMETHOD(bus_child_location_str, t4_child_location_str),
202 DEVMETHOD(t4_is_main_ready, t4_ready),
203 DEVMETHOD(t4_read_port_device, t4_read_port_device),
207 static driver_t t6_driver = {
210 sizeof(struct adapter)
214 /* T6 port (cc) interface */
215 static driver_t cc_driver = {
218 sizeof(struct port_info)
221 /* T6 VI (vcc) interface */
222 static driver_t vcc_driver = {
225 sizeof(struct vi_info)
228 /* ifnet interface */
229 static void cxgbe_init(void *);
230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
231 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
232 static void cxgbe_qflush(struct ifnet *);
234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
237 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
238 * then ADAPTER_LOCK, then t4_uld_list_lock.
240 static struct sx t4_list_lock;
241 SLIST_HEAD(, adapter) t4_list;
243 static struct sx t4_uld_list_lock;
244 SLIST_HEAD(, uld_info) t4_uld_list;
248 * Tunables. See tweak_tunables() too.
250 * Each tunable is set to a default value here if it's known at compile-time.
251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
252 * provide a reasonable default (upto n) when the driver is loaded.
254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
255 * T5 are under hw.cxl.
257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
262 * Number of queues for tx and rx, NIC and offload.
266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
267 "Number of TX queues per port");
268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
273 "Number of RX queues per port");
274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
277 static int t4_ntxq_vi = -NTXQ_VI;
278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
279 "Number of TX queues per VI");
282 static int t4_nrxq_vi = -NRXQ_VI;
283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
284 "Number of RX queues per VI");
286 static int t4_rsrv_noflowq = 0;
287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
288 0, "Reserve TX queue 0 of each VI for non-flowid packets");
290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
292 static int t4_nofldtxq = -NOFLDTXQ;
293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
294 "Number of offload TX queues per port");
297 static int t4_nofldrxq = -NOFLDRXQ;
298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
299 "Number of offload RX queues per port");
301 #define NOFLDTXQ_VI 1
302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
304 "Number of offload TX queues per VI");
306 #define NOFLDRXQ_VI 1
307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
309 "Number of offload RX queues per VI");
311 #define TMR_IDX_OFLD 1
312 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
316 #define PKTC_IDX_OFLD (-1)
317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
321 /* 0 means chip/fw default, non-zero number is value in microseconds */
322 static u_long t4_toe_keepalive_idle = 0;
323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
326 /* 0 means chip/fw default, non-zero number is value in microseconds */
327 static u_long t4_toe_keepalive_interval = 0;
328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
332 static int t4_toe_keepalive_count = 0;
333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
336 /* 0 means chip/fw default, non-zero number is value in microseconds */
337 static u_long t4_toe_rexmt_min = 0;
338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
341 /* 0 means chip/fw default, non-zero number is value in microseconds */
342 static u_long t4_toe_rexmt_max = 0;
343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
347 static int t4_toe_rexmt_count = 0;
348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
351 /* -1 means chip/fw default, other values are raw backoff values to use */
352 static int t4_toe_rexmt_backoff[16] = {
353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
356 "cxgbe(4) TOE retransmit backoff values");
357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
358 &t4_toe_rexmt_backoff[0], 0, "");
359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
360 &t4_toe_rexmt_backoff[1], 0, "");
361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
362 &t4_toe_rexmt_backoff[2], 0, "");
363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
364 &t4_toe_rexmt_backoff[3], 0, "");
365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
366 &t4_toe_rexmt_backoff[4], 0, "");
367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
368 &t4_toe_rexmt_backoff[5], 0, "");
369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
370 &t4_toe_rexmt_backoff[6], 0, "");
371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
372 &t4_toe_rexmt_backoff[7], 0, "");
373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_backoff[8], 0, "");
375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_backoff[9], 0, "");
377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
378 &t4_toe_rexmt_backoff[10], 0, "");
379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
380 &t4_toe_rexmt_backoff[11], 0, "");
381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
382 &t4_toe_rexmt_backoff[12], 0, "");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[13], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[14], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[15], 0, "");
393 static int t4_nnmtxq_vi = -NNMTXQ_VI;
394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
395 "Number of netmap TX queues per VI");
398 static int t4_nnmrxq_vi = -NNMRXQ_VI;
399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
400 "Number of netmap RX queues per VI");
404 * Holdoff parameters for ports.
407 int t4_tmr_idx = TMR_IDX;
408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
409 0, "Holdoff timer index");
410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
412 #define PKTC_IDX (-1)
413 int t4_pktc_idx = PKTC_IDX;
414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
415 0, "Holdoff packet counter index");
416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
419 * Size (# of entries) of each tx and rx queue.
421 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
423 "Number of descriptors in each TX queue");
425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
427 "Number of descriptors in each RX queue");
430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
437 * Configuration file. All the _CF names here are special.
439 #define DEFAULT_CF "default"
440 #define BUILTIN_CF "built-in"
441 #define FLASH_CF "flash"
442 #define UWIRE_CF "uwire"
443 #define FPGA_CF "fpga"
444 static char t4_cfg_file[32] = DEFAULT_CF;
445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
446 sizeof(t4_cfg_file), "Firmware configuration file");
449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
452 * mark or when signalled to do so, 0 to never emit PAUSE.
453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
454 * negotiated settings will override rx_pause/tx_pause.
455 * Otherwise rx_pause/tx_pause are applied forcibly.
457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
459 &t4_pause_settings, 0,
460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
467 static int t4_fec = -1;
468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
472 * Link autonegotiation.
473 * -1 to run with the firmware default.
477 static int t4_autoneg = -1;
478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
479 "Link autonegotiation");
482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
483 * encouraged respectively). '-n' is the same as 'n' except the firmware
484 * version used in the checks is read from the firmware bundled with the driver.
486 static int t4_fw_install = 1;
487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
491 * ASIC features that will be used. Disable the ones you don't want so that the
492 * chip resources aren't wasted on features that will not be used.
494 static int t4_nbmcaps_allowed = 0;
495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
500 &t4_linkcaps_allowed, 0, "Default link capabilities");
502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
503 FW_CAPS_CONFIG_SWITCH_EGRESS;
504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
505 &t4_switchcaps_allowed, 0, "Default switch capabilities");
508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
512 FW_CAPS_CONFIG_NIC_HASHFILTER;
514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
515 &t4_niccaps_allowed, 0, "Default NIC capabilities");
517 static int t4_toecaps_allowed = -1;
518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
521 static int t4_rdmacaps_allowed = -1;
522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
525 static int t4_cryptocaps_allowed = -1;
526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
529 static int t4_iscsicaps_allowed = -1;
530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
533 static int t4_fcoecaps_allowed = 0;
534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
537 static int t5_write_combine = 0;
538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
539 0, "Use WC instead of UC for BAR2");
541 static int t4_num_vis = 1;
542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
543 "Number of VIs per port");
546 * PCIe Relaxed Ordering.
547 * -1: driver should figure out a good value.
552 static int pcie_relaxed_ordering = -1;
553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
554 &pcie_relaxed_ordering, 0,
555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
557 static int t4_panic_on_fatal_err = 0;
558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
559 &t4_panic_on_fatal_err, 0, "panic on fatal firmware errors");
565 static int t4_cop_managed_offloading = 0;
566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
567 &t4_cop_managed_offloading, 0,
568 "COP (Connection Offload Policy) controls all TOE offload");
571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
572 static int vi_mac_funcs[] = {
576 FW_VI_FUNC_OPENISCSI,
582 struct intrs_and_queues {
583 uint16_t intr_type; /* INTx, MSI, or MSI-X */
584 uint16_t num_vis; /* number of VIs for each port */
585 uint16_t nirq; /* Total # of vectors */
586 uint16_t ntxq; /* # of NIC txq's for each port */
587 uint16_t nrxq; /* # of NIC rxq's for each port */
588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
589 uint16_t nofldrxq; /* # of TOE rxq's for each port */
591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
592 uint16_t ntxq_vi; /* # of NIC txq's */
593 uint16_t nrxq_vi; /* # of NIC rxq's */
594 uint16_t nofldtxq_vi; /* # of TOE txq's */
595 uint16_t nofldrxq_vi; /* # of TOE rxq's */
596 uint16_t nnmtxq_vi; /* # of netmap txq's */
597 uint16_t nnmrxq_vi; /* # of netmap rxq's */
600 static void setup_memwin(struct adapter *);
601 static void position_memwin(struct adapter *, int, uint32_t);
602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
603 static int fwmtype_to_hwmtype(int);
604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
606 static int fixup_devlog_params(struct adapter *);
607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
608 static int contact_firmware(struct adapter *);
609 static int partition_resources(struct adapter *);
610 static int get_params__pre_init(struct adapter *);
611 static int get_params__post_init(struct adapter *);
612 static int set_params__post_init(struct adapter *);
613 static void t4_set_desc(struct adapter *);
614 static bool fixed_ifmedia(struct port_info *);
615 static void build_medialist(struct port_info *);
616 static void init_link_config(struct port_info *);
617 static int fixup_link_config(struct port_info *);
618 static int apply_link_config(struct port_info *);
619 static int cxgbe_init_synchronized(struct vi_info *);
620 static int cxgbe_uninit_synchronized(struct vi_info *);
621 static void quiesce_txq(struct adapter *, struct sge_txq *);
622 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
623 static void quiesce_iq(struct adapter *, struct sge_iq *);
624 static void quiesce_fl(struct adapter *, struct sge_fl *);
625 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
626 driver_intr_t *, void *, char *);
627 static int t4_free_irq(struct adapter *, struct irq *);
628 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
629 static void vi_refresh_stats(struct adapter *, struct vi_info *);
630 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
631 static void cxgbe_tick(void *);
632 static void cxgbe_sysctls(struct port_info *);
633 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
634 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
635 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
636 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
637 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
638 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
639 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
640 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
641 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
642 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
643 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
644 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
645 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
646 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
647 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
648 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
649 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
650 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
651 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
652 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
653 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
654 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
655 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
656 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
657 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
658 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
659 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
660 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
661 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
662 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
663 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
664 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
665 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
666 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
667 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
668 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
669 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
670 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
671 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
672 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
673 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
674 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
675 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
676 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
678 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
679 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
680 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
681 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
682 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
683 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
684 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
685 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
687 static int get_sge_context(struct adapter *, struct t4_sge_context *);
688 static int load_fw(struct adapter *, struct t4_data *);
689 static int load_cfg(struct adapter *, struct t4_data *);
690 static int load_boot(struct adapter *, struct t4_bootrom *);
691 static int load_bootcfg(struct adapter *, struct t4_data *);
692 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
693 static void free_offload_policy(struct t4_offload_policy *);
694 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
695 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
696 static int read_i2c(struct adapter *, struct t4_i2c_data *);
698 static int toe_capability(struct vi_info *, int);
700 static int mod_event(module_t, int, void *);
701 static int notify_siblings(device_t, int);
707 {0xa000, "Chelsio Terminator 4 FPGA"},
708 {0x4400, "Chelsio T440-dbg"},
709 {0x4401, "Chelsio T420-CR"},
710 {0x4402, "Chelsio T422-CR"},
711 {0x4403, "Chelsio T440-CR"},
712 {0x4404, "Chelsio T420-BCH"},
713 {0x4405, "Chelsio T440-BCH"},
714 {0x4406, "Chelsio T440-CH"},
715 {0x4407, "Chelsio T420-SO"},
716 {0x4408, "Chelsio T420-CX"},
717 {0x4409, "Chelsio T420-BT"},
718 {0x440a, "Chelsio T404-BT"},
719 {0x440e, "Chelsio T440-LP-CR"},
721 {0xb000, "Chelsio Terminator 5 FPGA"},
722 {0x5400, "Chelsio T580-dbg"},
723 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
724 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
725 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
726 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
727 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
728 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
729 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
730 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
731 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
732 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
733 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
734 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
735 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
736 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
737 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
738 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
739 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
742 {0x5483, "Custom T540-CR"},
743 {0x5484, "Custom T540-BT"},
745 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
746 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
747 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
748 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
749 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
750 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
751 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
752 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
753 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
754 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
755 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
756 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
757 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
758 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
759 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
760 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
763 {0x6480, "Custom T6225-CR"},
764 {0x6481, "Custom T62100-CR"},
765 {0x6482, "Custom T6225-CR"},
766 {0x6483, "Custom T62100-CR"},
767 {0x6484, "Custom T64100-CR"},
768 {0x6485, "Custom T6240-SO"},
769 {0x6486, "Custom T6225-SO-CR"},
770 {0x6487, "Custom T6225-CR"},
775 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
776 * be exactly the same for both rxq and ofld_rxq.
778 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
779 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
781 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
784 t4_probe(device_t dev)
787 uint16_t v = pci_get_vendor(dev);
788 uint16_t d = pci_get_device(dev);
789 uint8_t f = pci_get_function(dev);
791 if (v != PCI_VENDOR_ID_CHELSIO)
794 /* Attach only to PF0 of the FPGA */
795 if (d == 0xa000 && f != 0)
798 for (i = 0; i < nitems(t4_pciids); i++) {
799 if (d == t4_pciids[i].device) {
800 device_set_desc(dev, t4_pciids[i].desc);
801 return (BUS_PROBE_DEFAULT);
809 t5_probe(device_t dev)
812 uint16_t v = pci_get_vendor(dev);
813 uint16_t d = pci_get_device(dev);
814 uint8_t f = pci_get_function(dev);
816 if (v != PCI_VENDOR_ID_CHELSIO)
819 /* Attach only to PF0 of the FPGA */
820 if (d == 0xb000 && f != 0)
823 for (i = 0; i < nitems(t5_pciids); i++) {
824 if (d == t5_pciids[i].device) {
825 device_set_desc(dev, t5_pciids[i].desc);
826 return (BUS_PROBE_DEFAULT);
834 t6_probe(device_t dev)
837 uint16_t v = pci_get_vendor(dev);
838 uint16_t d = pci_get_device(dev);
840 if (v != PCI_VENDOR_ID_CHELSIO)
843 for (i = 0; i < nitems(t6_pciids); i++) {
844 if (d == t6_pciids[i].device) {
845 device_set_desc(dev, t6_pciids[i].desc);
846 return (BUS_PROBE_DEFAULT);
854 t5_attribute_workaround(device_t dev)
860 * The T5 chips do not properly echo the No Snoop and Relaxed
861 * Ordering attributes when replying to a TLP from a Root
862 * Port. As a workaround, find the parent Root Port and
863 * disable No Snoop and Relaxed Ordering. Note that this
864 * affects all devices under this root port.
866 root_port = pci_find_pcie_root_port(dev);
867 if (root_port == NULL) {
868 device_printf(dev, "Unable to find parent root port\n");
872 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
873 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
874 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
876 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
877 device_get_nameunit(root_port));
880 static const struct devnames devnames[] = {
882 .nexus_name = "t4nex",
883 .ifnet_name = "cxgbe",
884 .vi_ifnet_name = "vcxgbe",
885 .pf03_drv_name = "t4iov",
886 .vf_nexus_name = "t4vf",
887 .vf_ifnet_name = "cxgbev"
889 .nexus_name = "t5nex",
891 .vi_ifnet_name = "vcxl",
892 .pf03_drv_name = "t5iov",
893 .vf_nexus_name = "t5vf",
894 .vf_ifnet_name = "cxlv"
896 .nexus_name = "t6nex",
898 .vi_ifnet_name = "vcc",
899 .pf03_drv_name = "t6iov",
900 .vf_nexus_name = "t6vf",
901 .vf_ifnet_name = "ccv"
906 t4_init_devnames(struct adapter *sc)
911 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
912 sc->names = &devnames[id - CHELSIO_T4];
914 device_printf(sc->dev, "chip id %d is not supported.\n", id);
920 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
922 const char *parent, *name;
927 parent = device_get_nameunit(sc->dev);
928 name = sc->names->ifnet_name;
929 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
930 if (resource_long_value(name, unit, "port", &value) == 0 &&
931 value == pi->port_id)
938 t4_attach(device_t dev)
941 int rc = 0, i, j, rqidx, tqidx, nports;
942 struct make_dev_args mda;
943 struct intrs_and_queues iaq;
946 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
953 int nm_rqidx, nm_tqidx;
957 sc = device_get_softc(dev);
959 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
961 if ((pci_get_device(dev) & 0xff00) == 0x5400)
962 t5_attribute_workaround(dev);
963 pci_enable_busmaster(dev);
964 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
967 pci_set_max_read_req(dev, 4096);
968 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
969 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
970 if (pcie_relaxed_ordering == 0 &&
971 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
972 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
973 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
974 } else if (pcie_relaxed_ordering == 1 &&
975 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
976 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
977 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
981 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
982 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
984 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
985 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
986 device_get_nameunit(dev));
988 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
989 device_get_nameunit(dev));
990 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
993 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
994 TAILQ_INIT(&sc->sfl);
995 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
997 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1000 rw_init(&sc->policy_lock, "connection offload policy");
1002 rc = t4_map_bars_0_and_4(sc);
1004 goto done; /* error message displayed already */
1006 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1008 /* Prepare the adapter for operation. */
1009 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1010 rc = -t4_prep_adapter(sc, buf);
1013 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1018 * This is the real PF# to which we're attaching. Works from within PCI
1019 * passthrough environments too, where pci_get_function() could return a
1020 * different PF# depending on the passthrough configuration. We need to
1021 * use the real PF# in all our communication with the firmware.
1023 j = t4_read_reg(sc, A_PL_WHOAMI);
1024 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1027 t4_init_devnames(sc);
1028 if (sc->names == NULL) {
1030 goto done; /* error message displayed already */
1034 * Do this really early, with the memory windows set up even before the
1035 * character device. The userland tool's register i/o and mem read
1036 * will work even in "recovery mode".
1039 if (t4_init_devlog_params(sc, 0) == 0)
1040 fixup_devlog_params(sc);
1041 make_dev_args_init(&mda);
1042 mda.mda_devsw = &t4_cdevsw;
1043 mda.mda_uid = UID_ROOT;
1044 mda.mda_gid = GID_WHEEL;
1045 mda.mda_mode = 0600;
1046 mda.mda_si_drv1 = sc;
1047 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1049 device_printf(dev, "failed to create nexus char device: %d.\n",
1052 /* Go no further if recovery mode has been requested. */
1053 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1054 device_printf(dev, "recovery mode.\n");
1058 #if defined(__i386__)
1059 if ((cpu_feature & CPUID_CX8) == 0) {
1060 device_printf(dev, "64 bit atomics not available.\n");
1066 /* Contact the firmware and try to become the master driver. */
1067 rc = contact_firmware(sc);
1069 goto done; /* error message displayed already */
1070 MPASS(sc->flags & FW_OK);
1072 rc = get_params__pre_init(sc);
1074 goto done; /* error message displayed already */
1076 if (sc->flags & MASTER_PF) {
1077 rc = partition_resources(sc);
1079 goto done; /* error message displayed already */
1083 rc = get_params__post_init(sc);
1085 goto done; /* error message displayed already */
1087 rc = set_params__post_init(sc);
1089 goto done; /* error message displayed already */
1091 rc = t4_map_bar_2(sc);
1093 goto done; /* error message displayed already */
1095 rc = t4_create_dma_tag(sc);
1097 goto done; /* error message displayed already */
1100 * First pass over all the ports - allocate VIs and initialize some
1101 * basic parameters like mac address, port type, etc.
1103 for_each_port(sc, i) {
1104 struct port_info *pi;
1106 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1109 /* These must be set before t4_port_init */
1113 * XXX: vi[0] is special so we can't delay this allocation until
1114 * pi->nvi's final value is known.
1116 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1120 * Allocate the "main" VI and initialize parameters
1123 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1125 device_printf(dev, "unable to initialize port %d: %d\n",
1127 free(pi->vi, M_CXGBE);
1133 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1134 device_get_nameunit(dev), i);
1135 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1136 sc->chan_map[pi->tx_chan] = i;
1138 /* All VIs on this port share this media. */
1139 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1140 cxgbe_media_status);
1143 init_link_config(pi);
1144 fixup_link_config(pi);
1145 build_medialist(pi);
1146 if (fixed_ifmedia(pi))
1147 pi->flags |= FIXED_IFMEDIA;
1150 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1151 t4_ifnet_unit(sc, pi));
1152 if (pi->dev == NULL) {
1154 "failed to add device for port %d.\n", i);
1158 pi->vi[0].dev = pi->dev;
1159 device_set_softc(pi->dev, pi);
1163 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1165 nports = sc->params.nports;
1166 rc = cfg_itype_and_nqueues(sc, &iaq);
1168 goto done; /* error message displayed already */
1170 num_vis = iaq.num_vis;
1171 sc->intr_type = iaq.intr_type;
1172 sc->intr_count = iaq.nirq;
1175 s->nrxq = nports * iaq.nrxq;
1176 s->ntxq = nports * iaq.ntxq;
1178 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1179 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1181 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1182 s->neq += nports; /* ctrl queues: 1 per port */
1183 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1184 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1185 if (is_offload(sc) || is_ethoffload(sc)) {
1186 s->nofldtxq = nports * iaq.nofldtxq;
1188 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1189 s->neq += s->nofldtxq;
1191 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1192 M_CXGBE, M_ZERO | M_WAITOK);
1196 if (is_offload(sc)) {
1197 s->nofldrxq = nports * iaq.nofldrxq;
1199 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1200 s->neq += s->nofldrxq; /* free list */
1201 s->niq += s->nofldrxq;
1203 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1204 M_CXGBE, M_ZERO | M_WAITOK);
1209 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1210 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1212 s->neq += s->nnmtxq + s->nnmrxq;
1213 s->niq += s->nnmrxq;
1215 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1216 M_CXGBE, M_ZERO | M_WAITOK);
1217 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1218 M_CXGBE, M_ZERO | M_WAITOK);
1221 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1223 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1225 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1227 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1229 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1232 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1235 t4_init_l2t(sc, M_WAITOK);
1236 t4_init_smt(sc, M_WAITOK);
1237 t4_init_tx_sched(sc);
1239 t4_init_etid_table(sc);
1242 t4_init_clip_table(sc);
1244 if (sc->vres.key.size != 0)
1245 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1246 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1249 * Second pass over the ports. This time we know the number of rx and
1250 * tx queues that each port should get.
1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1260 nm_rqidx = nm_tqidx = 0;
1262 for_each_port(sc, i) {
1263 struct port_info *pi = sc->port[i];
1270 for_each_vi(pi, j, vi) {
1272 vi->qsize_rxq = t4_qsize_rxq;
1273 vi->qsize_txq = t4_qsize_txq;
1275 vi->first_rxq = rqidx;
1276 vi->first_txq = tqidx;
1277 vi->tmr_idx = t4_tmr_idx;
1278 vi->pktc_idx = t4_pktc_idx;
1279 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1280 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1285 if (j == 0 && vi->ntxq > 1)
1286 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1288 vi->rsrv_noflowq = 0;
1290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1291 vi->first_ofld_txq = ofld_tqidx;
1292 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1293 ofld_tqidx += vi->nofldtxq;
1296 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1297 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1298 vi->first_ofld_rxq = ofld_rqidx;
1299 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1301 ofld_rqidx += vi->nofldrxq;
1305 vi->first_nm_rxq = nm_rqidx;
1306 vi->first_nm_txq = nm_tqidx;
1307 vi->nnmrxq = iaq.nnmrxq_vi;
1308 vi->nnmtxq = iaq.nnmtxq_vi;
1309 nm_rqidx += vi->nnmrxq;
1310 nm_tqidx += vi->nnmtxq;
1316 rc = t4_setup_intr_handlers(sc);
1319 "failed to setup interrupt handlers: %d\n", rc);
1323 rc = bus_generic_probe(dev);
1325 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1330 * Ensure thread-safe mailbox access (in debug builds).
1332 * So far this was the only thread accessing the mailbox but various
1333 * ifnets and sysctls are about to be created and their handlers/ioctls
1334 * will access the mailbox from different threads.
1336 sc->flags |= CHK_MBOX_ACCESS;
1338 rc = bus_generic_attach(dev);
1341 "failed to attach all child ports: %d\n", rc);
1346 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1347 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1348 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1349 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1350 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1354 notify_siblings(dev, 0);
1357 if (rc != 0 && sc->cdev) {
1358 /* cdev was created and so cxgbetool works; recover that way. */
1360 "error during attach, adapter is now in recovery mode.\n");
1365 t4_detach_common(dev);
1373 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1375 struct port_info *pi;
1377 pi = device_get_softc(dev);
1378 snprintf(buf, buflen, "port=%d", pi->port_id);
1383 t4_ready(device_t dev)
1387 sc = device_get_softc(dev);
1388 if (sc->flags & FW_OK)
1394 t4_read_port_device(device_t dev, int port, device_t *child)
1397 struct port_info *pi;
1399 sc = device_get_softc(dev);
1400 if (port < 0 || port >= MAX_NPORTS)
1402 pi = sc->port[port];
1403 if (pi == NULL || pi->dev == NULL)
1410 notify_siblings(device_t dev, int detaching)
1416 for (i = 0; i < PCI_FUNCMAX; i++) {
1417 if (i == pci_get_function(dev))
1419 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1420 pci_get_slot(dev), i);
1421 if (sibling == NULL || !device_is_attached(sibling))
1424 error = T4_DETACH_CHILD(sibling);
1426 (void)T4_ATTACH_CHILD(sibling);
1437 t4_detach(device_t dev)
1442 sc = device_get_softc(dev);
1444 rc = notify_siblings(dev, 1);
1447 "failed to detach sibling devices: %d\n", rc);
1451 return (t4_detach_common(dev));
1455 t4_detach_common(device_t dev)
1458 struct port_info *pi;
1461 sc = device_get_softc(dev);
1464 destroy_dev(sc->cdev);
1468 sc->flags &= ~CHK_MBOX_ACCESS;
1469 if (sc->flags & FULL_INIT_DONE) {
1470 if (!(sc->flags & IS_VF))
1471 t4_intr_disable(sc);
1474 if (device_is_attached(dev)) {
1475 rc = bus_generic_detach(dev);
1478 "failed to detach child devices: %d\n", rc);
1483 for (i = 0; i < sc->intr_count; i++)
1484 t4_free_irq(sc, &sc->irq[i]);
1486 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1487 t4_free_tx_sched(sc);
1489 for (i = 0; i < MAX_NPORTS; i++) {
1492 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1494 device_delete_child(dev, pi->dev);
1496 mtx_destroy(&pi->pi_lock);
1497 free(pi->vi, M_CXGBE);
1502 device_delete_children(dev);
1504 if (sc->flags & FULL_INIT_DONE)
1505 adapter_full_uninit(sc);
1507 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1508 t4_fw_bye(sc, sc->mbox);
1510 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1511 pci_release_msi(dev);
1514 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1518 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1522 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1526 t4_free_l2t(sc->l2t);
1528 t4_free_smt(sc->smt);
1530 t4_free_etid_table(sc);
1533 vmem_destroy(sc->key_map);
1535 t4_destroy_clip_table(sc);
1538 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1539 free(sc->sge.ofld_txq, M_CXGBE);
1542 free(sc->sge.ofld_rxq, M_CXGBE);
1545 free(sc->sge.nm_rxq, M_CXGBE);
1546 free(sc->sge.nm_txq, M_CXGBE);
1548 free(sc->irq, M_CXGBE);
1549 free(sc->sge.rxq, M_CXGBE);
1550 free(sc->sge.txq, M_CXGBE);
1551 free(sc->sge.ctrlq, M_CXGBE);
1552 free(sc->sge.iqmap, M_CXGBE);
1553 free(sc->sge.eqmap, M_CXGBE);
1554 free(sc->tids.ftid_tab, M_CXGBE);
1555 free(sc->tids.hpftid_tab, M_CXGBE);
1556 free_hftid_hash(&sc->tids);
1557 free(sc->tids.atid_tab, M_CXGBE);
1558 free(sc->tids.tid_tab, M_CXGBE);
1559 free(sc->tt.tls_rx_ports, M_CXGBE);
1560 t4_destroy_dma_tag(sc);
1561 if (mtx_initialized(&sc->sc_lock)) {
1562 sx_xlock(&t4_list_lock);
1563 SLIST_REMOVE(&t4_list, sc, adapter, link);
1564 sx_xunlock(&t4_list_lock);
1565 mtx_destroy(&sc->sc_lock);
1568 callout_drain(&sc->sfl_callout);
1569 if (mtx_initialized(&sc->tids.ftid_lock)) {
1570 mtx_destroy(&sc->tids.ftid_lock);
1571 cv_destroy(&sc->tids.ftid_cv);
1573 if (mtx_initialized(&sc->tids.atid_lock))
1574 mtx_destroy(&sc->tids.atid_lock);
1575 if (mtx_initialized(&sc->sfl_lock))
1576 mtx_destroy(&sc->sfl_lock);
1577 if (mtx_initialized(&sc->ifp_lock))
1578 mtx_destroy(&sc->ifp_lock);
1579 if (mtx_initialized(&sc->reg_lock))
1580 mtx_destroy(&sc->reg_lock);
1582 if (rw_initialized(&sc->policy_lock)) {
1583 rw_destroy(&sc->policy_lock);
1585 if (sc->policy != NULL)
1586 free_offload_policy(sc->policy);
1590 for (i = 0; i < NUM_MEMWIN; i++) {
1591 struct memwin *mw = &sc->memwin[i];
1593 if (rw_initialized(&mw->mw_lock))
1594 rw_destroy(&mw->mw_lock);
1597 bzero(sc, sizeof(*sc));
1603 cxgbe_probe(device_t dev)
1606 struct port_info *pi = device_get_softc(dev);
1608 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1609 device_set_desc_copy(dev, buf);
1611 return (BUS_PROBE_DEFAULT);
1614 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1615 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1616 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1618 #define T4_CAP_ENABLE (T4_CAP)
1621 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1626 vi->xact_addr_filt = -1;
1627 callout_init(&vi->tick, 1);
1629 /* Allocate an ifnet and set it up */
1630 ifp = if_alloc(IFT_ETHER);
1632 device_printf(dev, "Cannot allocate ifnet\n");
1638 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1641 ifp->if_init = cxgbe_init;
1642 ifp->if_ioctl = cxgbe_ioctl;
1643 ifp->if_transmit = cxgbe_transmit;
1644 ifp->if_qflush = cxgbe_qflush;
1645 ifp->if_get_counter = cxgbe_get_counter;
1647 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1648 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1649 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1650 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1653 ifp->if_capabilities = T4_CAP;
1654 ifp->if_capenable = T4_CAP_ENABLE;
1656 if (vi->nofldrxq != 0)
1657 ifp->if_capabilities |= IFCAP_TOE;
1660 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1661 ifp->if_capabilities |= IFCAP_TXRTLMT;
1662 ifp->if_capenable |= IFCAP_TXRTLMT;
1665 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1666 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1668 ifp->if_hw_tsomax = IP_MAXPACKET;
1669 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1671 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1672 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1674 ifp->if_hw_tsomaxsegsize = 65536;
1676 ether_ifattach(ifp, vi->hw_addr);
1678 if (vi->nnmrxq != 0)
1679 cxgbe_nm_attach(vi);
1681 sb = sbuf_new_auto();
1682 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1683 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1684 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1686 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1688 case IFCAP_TOE | IFCAP_TXRTLMT:
1689 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1692 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1697 if (ifp->if_capabilities & IFCAP_TOE)
1698 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1701 if (ifp->if_capabilities & IFCAP_NETMAP)
1702 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1703 vi->nnmtxq, vi->nnmrxq);
1706 device_printf(dev, "%s\n", sbuf_data(sb));
1715 cxgbe_attach(device_t dev)
1717 struct port_info *pi = device_get_softc(dev);
1718 struct adapter *sc = pi->adapter;
1722 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1724 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1728 for_each_vi(pi, i, vi) {
1731 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1732 if (vi->dev == NULL) {
1733 device_printf(dev, "failed to add VI %d\n", i);
1736 device_set_softc(vi->dev, vi);
1741 bus_generic_attach(dev);
1747 cxgbe_vi_detach(struct vi_info *vi)
1749 struct ifnet *ifp = vi->ifp;
1751 ether_ifdetach(ifp);
1753 /* Let detach proceed even if these fail. */
1755 if (ifp->if_capabilities & IFCAP_NETMAP)
1756 cxgbe_nm_detach(vi);
1758 cxgbe_uninit_synchronized(vi);
1759 callout_drain(&vi->tick);
1767 cxgbe_detach(device_t dev)
1769 struct port_info *pi = device_get_softc(dev);
1770 struct adapter *sc = pi->adapter;
1773 /* Detach the extra VIs first. */
1774 rc = bus_generic_detach(dev);
1777 device_delete_children(dev);
1779 doom_vi(sc, &pi->vi[0]);
1781 if (pi->flags & HAS_TRACEQ) {
1782 sc->traceq = -1; /* cloner should not create ifnet */
1783 t4_tracer_port_detach(sc);
1786 cxgbe_vi_detach(&pi->vi[0]);
1787 callout_drain(&pi->tick);
1788 ifmedia_removeall(&pi->media);
1790 end_synchronized_op(sc, 0);
1796 cxgbe_init(void *arg)
1798 struct vi_info *vi = arg;
1799 struct adapter *sc = vi->pi->adapter;
1801 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1803 cxgbe_init_synchronized(vi);
1804 end_synchronized_op(sc, 0);
1808 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1810 int rc = 0, mtu, flags;
1811 struct vi_info *vi = ifp->if_softc;
1812 struct port_info *pi = vi->pi;
1813 struct adapter *sc = pi->adapter;
1814 struct ifreq *ifr = (struct ifreq *)data;
1820 if (mtu < ETHERMIN || mtu > MAX_MTU)
1823 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1827 if (vi->flags & VI_INIT_DONE) {
1828 t4_update_fl_bufsize(ifp);
1829 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1830 rc = update_mac_settings(ifp, XGMAC_MTU);
1832 end_synchronized_op(sc, 0);
1836 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1840 if (ifp->if_flags & IFF_UP) {
1841 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1842 flags = vi->if_flags;
1843 if ((ifp->if_flags ^ flags) &
1844 (IFF_PROMISC | IFF_ALLMULTI)) {
1845 rc = update_mac_settings(ifp,
1846 XGMAC_PROMISC | XGMAC_ALLMULTI);
1849 rc = cxgbe_init_synchronized(vi);
1851 vi->if_flags = ifp->if_flags;
1852 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1853 rc = cxgbe_uninit_synchronized(vi);
1855 end_synchronized_op(sc, 0);
1860 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1863 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1864 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1865 end_synchronized_op(sc, 0);
1869 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1873 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1874 if (mask & IFCAP_TXCSUM) {
1875 ifp->if_capenable ^= IFCAP_TXCSUM;
1876 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1878 if (IFCAP_TSO4 & ifp->if_capenable &&
1879 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1880 ifp->if_capenable &= ~IFCAP_TSO4;
1882 "tso4 disabled due to -txcsum.\n");
1885 if (mask & IFCAP_TXCSUM_IPV6) {
1886 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1887 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1889 if (IFCAP_TSO6 & ifp->if_capenable &&
1890 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1891 ifp->if_capenable &= ~IFCAP_TSO6;
1893 "tso6 disabled due to -txcsum6.\n");
1896 if (mask & IFCAP_RXCSUM)
1897 ifp->if_capenable ^= IFCAP_RXCSUM;
1898 if (mask & IFCAP_RXCSUM_IPV6)
1899 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1902 * Note that we leave CSUM_TSO alone (it is always set). The
1903 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1904 * sending a TSO request our way, so it's sufficient to toggle
1907 if (mask & IFCAP_TSO4) {
1908 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1909 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1910 if_printf(ifp, "enable txcsum first.\n");
1914 ifp->if_capenable ^= IFCAP_TSO4;
1916 if (mask & IFCAP_TSO6) {
1917 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1918 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1919 if_printf(ifp, "enable txcsum6 first.\n");
1923 ifp->if_capenable ^= IFCAP_TSO6;
1925 if (mask & IFCAP_LRO) {
1926 #if defined(INET) || defined(INET6)
1928 struct sge_rxq *rxq;
1930 ifp->if_capenable ^= IFCAP_LRO;
1931 for_each_rxq(vi, i, rxq) {
1932 if (ifp->if_capenable & IFCAP_LRO)
1933 rxq->iq.flags |= IQ_LRO_ENABLED;
1935 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1940 if (mask & IFCAP_TOE) {
1941 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1943 rc = toe_capability(vi, enable);
1947 ifp->if_capenable ^= mask;
1950 if (mask & IFCAP_VLAN_HWTAGGING) {
1951 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1952 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1953 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1955 if (mask & IFCAP_VLAN_MTU) {
1956 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1958 /* Need to find out how to disable auto-mtu-inflation */
1960 if (mask & IFCAP_VLAN_HWTSO)
1961 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1962 if (mask & IFCAP_VLAN_HWCSUM)
1963 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1965 if (mask & IFCAP_TXRTLMT)
1966 ifp->if_capenable ^= IFCAP_TXRTLMT;
1968 if (mask & IFCAP_HWRXTSTMP) {
1970 struct sge_rxq *rxq;
1972 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
1973 for_each_rxq(vi, i, rxq) {
1974 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
1975 rxq->iq.flags |= IQ_RX_TIMESTAMP;
1977 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
1981 #ifdef VLAN_CAPABILITIES
1982 VLAN_CAPABILITIES(ifp);
1985 end_synchronized_op(sc, 0);
1991 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1995 struct ifi2creq i2c;
1997 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2000 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2004 if (i2c.len > sizeof(i2c.data)) {
2008 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2011 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2012 i2c.offset, i2c.len, &i2c.data[0]);
2013 end_synchronized_op(sc, 0);
2015 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2020 rc = ether_ioctl(ifp, cmd, data);
2027 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2029 struct vi_info *vi = ifp->if_softc;
2030 struct port_info *pi = vi->pi;
2031 struct adapter *sc = pi->adapter;
2032 struct sge_txq *txq;
2037 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2039 if (__predict_false(pi->link_cfg.link_ok == false)) {
2044 rc = parse_pkt(sc, &m);
2045 if (__predict_false(rc != 0)) {
2046 MPASS(m == NULL); /* was freed already */
2047 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2051 if (m->m_pkthdr.snd_tag != NULL) {
2052 /* EAGAIN tells the stack we are not the correct interface. */
2053 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) {
2058 return (ethofld_transmit(ifp, m));
2063 txq = &sc->sge.txq[vi->first_txq];
2064 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2065 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2069 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2070 if (__predict_false(rc != 0))
2077 cxgbe_qflush(struct ifnet *ifp)
2079 struct vi_info *vi = ifp->if_softc;
2080 struct sge_txq *txq;
2083 /* queues do not exist if !VI_INIT_DONE. */
2084 if (vi->flags & VI_INIT_DONE) {
2085 for_each_txq(vi, i, txq) {
2087 txq->eq.flags |= EQ_QFLUSH;
2089 while (!mp_ring_is_idle(txq->r)) {
2090 mp_ring_check_drainage(txq->r, 0);
2094 txq->eq.flags &= ~EQ_QFLUSH;
2102 vi_get_counter(struct ifnet *ifp, ift_counter c)
2104 struct vi_info *vi = ifp->if_softc;
2105 struct fw_vi_stats_vf *s = &vi->stats;
2107 vi_refresh_stats(vi->pi->adapter, vi);
2110 case IFCOUNTER_IPACKETS:
2111 return (s->rx_bcast_frames + s->rx_mcast_frames +
2112 s->rx_ucast_frames);
2113 case IFCOUNTER_IERRORS:
2114 return (s->rx_err_frames);
2115 case IFCOUNTER_OPACKETS:
2116 return (s->tx_bcast_frames + s->tx_mcast_frames +
2117 s->tx_ucast_frames + s->tx_offload_frames);
2118 case IFCOUNTER_OERRORS:
2119 return (s->tx_drop_frames);
2120 case IFCOUNTER_IBYTES:
2121 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2123 case IFCOUNTER_OBYTES:
2124 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2125 s->tx_ucast_bytes + s->tx_offload_bytes);
2126 case IFCOUNTER_IMCASTS:
2127 return (s->rx_mcast_frames);
2128 case IFCOUNTER_OMCASTS:
2129 return (s->tx_mcast_frames);
2130 case IFCOUNTER_OQDROPS: {
2134 if (vi->flags & VI_INIT_DONE) {
2136 struct sge_txq *txq;
2138 for_each_txq(vi, i, txq)
2139 drops += counter_u64_fetch(txq->r->drops);
2147 return (if_get_counter_default(ifp, c));
2152 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2154 struct vi_info *vi = ifp->if_softc;
2155 struct port_info *pi = vi->pi;
2156 struct adapter *sc = pi->adapter;
2157 struct port_stats *s = &pi->stats;
2159 if (pi->nvi > 1 || sc->flags & IS_VF)
2160 return (vi_get_counter(ifp, c));
2162 cxgbe_refresh_stats(sc, pi);
2165 case IFCOUNTER_IPACKETS:
2166 return (s->rx_frames);
2168 case IFCOUNTER_IERRORS:
2169 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2170 s->rx_fcs_err + s->rx_len_err);
2172 case IFCOUNTER_OPACKETS:
2173 return (s->tx_frames);
2175 case IFCOUNTER_OERRORS:
2176 return (s->tx_error_frames);
2178 case IFCOUNTER_IBYTES:
2179 return (s->rx_octets);
2181 case IFCOUNTER_OBYTES:
2182 return (s->tx_octets);
2184 case IFCOUNTER_IMCASTS:
2185 return (s->rx_mcast_frames);
2187 case IFCOUNTER_OMCASTS:
2188 return (s->tx_mcast_frames);
2190 case IFCOUNTER_IQDROPS:
2191 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2192 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2193 s->rx_trunc3 + pi->tnl_cong_drops);
2195 case IFCOUNTER_OQDROPS: {
2199 if (vi->flags & VI_INIT_DONE) {
2201 struct sge_txq *txq;
2203 for_each_txq(vi, i, txq)
2204 drops += counter_u64_fetch(txq->r->drops);
2212 return (if_get_counter_default(ifp, c));
2217 * The kernel picks a media from the list we had provided but we still validate
2221 cxgbe_media_change(struct ifnet *ifp)
2223 struct vi_info *vi = ifp->if_softc;
2224 struct port_info *pi = vi->pi;
2225 struct ifmedia *ifm = &pi->media;
2226 struct link_config *lc = &pi->link_cfg;
2227 struct adapter *sc = pi->adapter;
2230 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2234 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2235 /* ifconfig .. media autoselect */
2236 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2237 rc = ENOTSUP; /* AN not supported by transceiver */
2240 lc->requested_aneg = AUTONEG_ENABLE;
2241 lc->requested_speed = 0;
2242 lc->requested_fc |= PAUSE_AUTONEG;
2244 lc->requested_aneg = AUTONEG_DISABLE;
2245 lc->requested_speed =
2246 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2247 lc->requested_fc = 0;
2248 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2249 lc->requested_fc |= PAUSE_RX;
2250 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2251 lc->requested_fc |= PAUSE_TX;
2253 if (pi->up_vis > 0) {
2254 fixup_link_config(pi);
2255 rc = apply_link_config(pi);
2259 end_synchronized_op(sc, 0);
2264 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2268 port_mword(struct port_info *pi, uint32_t speed)
2271 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2272 MPASS(powerof2(speed));
2274 switch(pi->port_type) {
2275 case FW_PORT_TYPE_BT_SGMII:
2276 case FW_PORT_TYPE_BT_XFI:
2277 case FW_PORT_TYPE_BT_XAUI:
2280 case FW_PORT_CAP32_SPEED_100M:
2282 case FW_PORT_CAP32_SPEED_1G:
2283 return (IFM_1000_T);
2284 case FW_PORT_CAP32_SPEED_10G:
2288 case FW_PORT_TYPE_KX4:
2289 if (speed == FW_PORT_CAP32_SPEED_10G)
2290 return (IFM_10G_KX4);
2292 case FW_PORT_TYPE_CX4:
2293 if (speed == FW_PORT_CAP32_SPEED_10G)
2294 return (IFM_10G_CX4);
2296 case FW_PORT_TYPE_KX:
2297 if (speed == FW_PORT_CAP32_SPEED_1G)
2298 return (IFM_1000_KX);
2300 case FW_PORT_TYPE_KR:
2301 case FW_PORT_TYPE_BP_AP:
2302 case FW_PORT_TYPE_BP4_AP:
2303 case FW_PORT_TYPE_BP40_BA:
2304 case FW_PORT_TYPE_KR4_100G:
2305 case FW_PORT_TYPE_KR_SFP28:
2306 case FW_PORT_TYPE_KR_XLAUI:
2308 case FW_PORT_CAP32_SPEED_1G:
2309 return (IFM_1000_KX);
2310 case FW_PORT_CAP32_SPEED_10G:
2311 return (IFM_10G_KR);
2312 case FW_PORT_CAP32_SPEED_25G:
2313 return (IFM_25G_KR);
2314 case FW_PORT_CAP32_SPEED_40G:
2315 return (IFM_40G_KR4);
2316 case FW_PORT_CAP32_SPEED_50G:
2317 return (IFM_50G_KR2);
2318 case FW_PORT_CAP32_SPEED_100G:
2319 return (IFM_100G_KR4);
2322 case FW_PORT_TYPE_FIBER_XFI:
2323 case FW_PORT_TYPE_FIBER_XAUI:
2324 case FW_PORT_TYPE_SFP:
2325 case FW_PORT_TYPE_QSFP_10G:
2326 case FW_PORT_TYPE_QSA:
2327 case FW_PORT_TYPE_QSFP:
2328 case FW_PORT_TYPE_CR4_QSFP:
2329 case FW_PORT_TYPE_CR_QSFP:
2330 case FW_PORT_TYPE_CR2_QSFP:
2331 case FW_PORT_TYPE_SFP28:
2332 /* Pluggable transceiver */
2333 switch (pi->mod_type) {
2334 case FW_PORT_MOD_TYPE_LR:
2336 case FW_PORT_CAP32_SPEED_1G:
2337 return (IFM_1000_LX);
2338 case FW_PORT_CAP32_SPEED_10G:
2339 return (IFM_10G_LR);
2340 case FW_PORT_CAP32_SPEED_25G:
2341 return (IFM_25G_LR);
2342 case FW_PORT_CAP32_SPEED_40G:
2343 return (IFM_40G_LR4);
2344 case FW_PORT_CAP32_SPEED_50G:
2345 return (IFM_50G_LR2);
2346 case FW_PORT_CAP32_SPEED_100G:
2347 return (IFM_100G_LR4);
2350 case FW_PORT_MOD_TYPE_SR:
2352 case FW_PORT_CAP32_SPEED_1G:
2353 return (IFM_1000_SX);
2354 case FW_PORT_CAP32_SPEED_10G:
2355 return (IFM_10G_SR);
2356 case FW_PORT_CAP32_SPEED_25G:
2357 return (IFM_25G_SR);
2358 case FW_PORT_CAP32_SPEED_40G:
2359 return (IFM_40G_SR4);
2360 case FW_PORT_CAP32_SPEED_50G:
2361 return (IFM_50G_SR2);
2362 case FW_PORT_CAP32_SPEED_100G:
2363 return (IFM_100G_SR4);
2366 case FW_PORT_MOD_TYPE_ER:
2367 if (speed == FW_PORT_CAP32_SPEED_10G)
2368 return (IFM_10G_ER);
2370 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2371 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2373 case FW_PORT_CAP32_SPEED_1G:
2374 return (IFM_1000_CX);
2375 case FW_PORT_CAP32_SPEED_10G:
2376 return (IFM_10G_TWINAX);
2377 case FW_PORT_CAP32_SPEED_25G:
2378 return (IFM_25G_CR);
2379 case FW_PORT_CAP32_SPEED_40G:
2380 return (IFM_40G_CR4);
2381 case FW_PORT_CAP32_SPEED_50G:
2382 return (IFM_50G_CR2);
2383 case FW_PORT_CAP32_SPEED_100G:
2384 return (IFM_100G_CR4);
2387 case FW_PORT_MOD_TYPE_LRM:
2388 if (speed == FW_PORT_CAP32_SPEED_10G)
2389 return (IFM_10G_LRM);
2391 case FW_PORT_MOD_TYPE_NA:
2392 MPASS(0); /* Not pluggable? */
2394 case FW_PORT_MOD_TYPE_ERROR:
2395 case FW_PORT_MOD_TYPE_UNKNOWN:
2396 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2398 case FW_PORT_MOD_TYPE_NONE:
2402 case FW_PORT_TYPE_NONE:
2406 return (IFM_UNKNOWN);
2410 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2412 struct vi_info *vi = ifp->if_softc;
2413 struct port_info *pi = vi->pi;
2414 struct adapter *sc = pi->adapter;
2415 struct link_config *lc = &pi->link_cfg;
2417 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2421 if (pi->up_vis == 0) {
2423 * If all the interfaces are administratively down the firmware
2424 * does not report transceiver changes. Refresh port info here
2425 * so that ifconfig displays accurate ifmedia at all times.
2426 * This is the only reason we have a synchronized op in this
2427 * function. Just PORT_LOCK would have been enough otherwise.
2429 t4_update_port_info(pi);
2430 build_medialist(pi);
2434 ifmr->ifm_status = IFM_AVALID;
2435 if (lc->link_ok == false)
2437 ifmr->ifm_status |= IFM_ACTIVE;
2440 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2441 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2442 if (lc->fc & PAUSE_RX)
2443 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2444 if (lc->fc & PAUSE_TX)
2445 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2446 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2449 end_synchronized_op(sc, 0);
2453 vcxgbe_probe(device_t dev)
2456 struct vi_info *vi = device_get_softc(dev);
2458 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2460 device_set_desc_copy(dev, buf);
2462 return (BUS_PROBE_DEFAULT);
2466 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2468 int func, index, rc;
2469 uint32_t param, val;
2471 ASSERT_SYNCHRONIZED_OP(sc);
2473 index = vi - pi->vi;
2474 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2475 KASSERT(index < nitems(vi_mac_funcs),
2476 ("%s: VI %s doesn't have a MAC func", __func__,
2477 device_get_nameunit(vi->dev)));
2478 func = vi_mac_funcs[index];
2479 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2480 vi->hw_addr, &vi->rss_size, func, 0);
2482 device_printf(vi->dev, "failed to allocate virtual interface %d"
2483 "for port %d: %d\n", index, pi->port_id, -rc);
2487 if (chip_id(sc) <= CHELSIO_T5)
2488 vi->smt_idx = (rc & 0x7f) << 1;
2490 vi->smt_idx = (rc & 0x7f);
2492 if (vi->rss_size == 1) {
2494 * This VI didn't get a slice of the RSS table. Reduce the
2495 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2496 * configuration file (nvi, rssnvi for this PF) if this is a
2499 device_printf(vi->dev, "RSS table not available.\n");
2500 vi->rss_base = 0xffff;
2505 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2506 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2507 V_FW_PARAMS_PARAM_YZ(vi->viid);
2508 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2510 vi->rss_base = 0xffff;
2512 MPASS((val >> 16) == vi->rss_size);
2513 vi->rss_base = val & 0xffff;
2520 vcxgbe_attach(device_t dev)
2523 struct port_info *pi;
2527 vi = device_get_softc(dev);
2531 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2534 rc = alloc_extra_vi(sc, pi, vi);
2535 end_synchronized_op(sc, 0);
2539 rc = cxgbe_vi_attach(dev, vi);
2541 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2548 vcxgbe_detach(device_t dev)
2553 vi = device_get_softc(dev);
2554 sc = vi->pi->adapter;
2558 cxgbe_vi_detach(vi);
2559 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2561 end_synchronized_op(sc, 0);
2567 t4_fatal_err(struct adapter *sc, bool fw_error)
2570 t4_shutdown_adapter(sc);
2571 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2572 device_get_nameunit(sc->dev));
2573 if (t4_panic_on_fatal_err)
2574 panic("panic requested on fatal error");
2577 ASSERT_SYNCHRONIZED_OP(sc);
2578 sc->flags |= ADAP_ERR;
2581 sc->flags |= ADAP_ERR;
2587 t4_add_adapter(struct adapter *sc)
2589 sx_xlock(&t4_list_lock);
2590 SLIST_INSERT_HEAD(&t4_list, sc, link);
2591 sx_xunlock(&t4_list_lock);
2595 t4_map_bars_0_and_4(struct adapter *sc)
2597 sc->regs_rid = PCIR_BAR(0);
2598 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2599 &sc->regs_rid, RF_ACTIVE);
2600 if (sc->regs_res == NULL) {
2601 device_printf(sc->dev, "cannot map registers.\n");
2604 sc->bt = rman_get_bustag(sc->regs_res);
2605 sc->bh = rman_get_bushandle(sc->regs_res);
2606 sc->mmio_len = rman_get_size(sc->regs_res);
2607 setbit(&sc->doorbells, DOORBELL_KDB);
2609 sc->msix_rid = PCIR_BAR(4);
2610 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2611 &sc->msix_rid, RF_ACTIVE);
2612 if (sc->msix_res == NULL) {
2613 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2621 t4_map_bar_2(struct adapter *sc)
2625 * T4: only iWARP driver uses the userspace doorbells. There is no need
2626 * to map it if RDMA is disabled.
2628 if (is_t4(sc) && sc->rdmacaps == 0)
2631 sc->udbs_rid = PCIR_BAR(2);
2632 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2633 &sc->udbs_rid, RF_ACTIVE);
2634 if (sc->udbs_res == NULL) {
2635 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2638 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2640 if (chip_id(sc) >= CHELSIO_T5) {
2641 setbit(&sc->doorbells, DOORBELL_UDB);
2642 #if defined(__i386__) || defined(__amd64__)
2643 if (t5_write_combine) {
2647 * Enable write combining on BAR2. This is the
2648 * userspace doorbell BAR and is split into 128B
2649 * (UDBS_SEG_SIZE) doorbell regions, each associated
2650 * with an egress queue. The first 64B has the doorbell
2651 * and the second 64B can be used to submit a tx work
2652 * request with an implicit doorbell.
2655 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2656 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2658 clrbit(&sc->doorbells, DOORBELL_UDB);
2659 setbit(&sc->doorbells, DOORBELL_WCWR);
2660 setbit(&sc->doorbells, DOORBELL_UDBWC);
2662 device_printf(sc->dev,
2663 "couldn't enable write combining: %d\n",
2667 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2668 t4_write_reg(sc, A_SGE_STAT_CFG,
2669 V_STATSOURCE_T5(7) | mode);
2673 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2678 struct memwin_init {
2683 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2684 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2685 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2686 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2689 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2690 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2691 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2692 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2696 setup_memwin(struct adapter *sc)
2698 const struct memwin_init *mw_init;
2705 * Read low 32b of bar0 indirectly via the hardware backdoor
2706 * mechanism. Works from within PCI passthrough environments
2707 * too, where rman_get_start() can return a different value. We
2708 * need to program the T4 memory window decoders with the actual
2709 * addresses that will be coming across the PCIe link.
2711 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2712 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2714 mw_init = &t4_memwin[0];
2716 /* T5+ use the relative offset inside the PCIe BAR */
2719 mw_init = &t5_memwin[0];
2722 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2723 rw_init(&mw->mw_lock, "memory window access");
2724 mw->mw_base = mw_init->base;
2725 mw->mw_aperture = mw_init->aperture;
2728 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2729 (mw->mw_base + bar0) | V_BIR(0) |
2730 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2731 rw_wlock(&mw->mw_lock);
2732 position_memwin(sc, i, 0);
2733 rw_wunlock(&mw->mw_lock);
2737 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2741 * Positions the memory window at the given address in the card's address space.
2742 * There are some alignment requirements and the actual position may be at an
2743 * address prior to the requested address. mw->mw_curpos always has the actual
2744 * position of the window.
2747 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2753 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2754 mw = &sc->memwin[idx];
2755 rw_assert(&mw->mw_lock, RA_WLOCKED);
2759 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2761 pf = V_PFNUM(sc->pf);
2762 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2764 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2765 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2766 t4_read_reg(sc, reg); /* flush */
2770 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2776 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2778 /* Memory can only be accessed in naturally aligned 4 byte units */
2779 if (addr & 3 || len & 3 || len <= 0)
2782 mw = &sc->memwin[idx];
2784 rw_rlock(&mw->mw_lock);
2785 mw_end = mw->mw_curpos + mw->mw_aperture;
2786 if (addr >= mw_end || addr < mw->mw_curpos) {
2787 /* Will need to reposition the window */
2788 if (!rw_try_upgrade(&mw->mw_lock)) {
2789 rw_runlock(&mw->mw_lock);
2790 rw_wlock(&mw->mw_lock);
2792 rw_assert(&mw->mw_lock, RA_WLOCKED);
2793 position_memwin(sc, idx, addr);
2794 rw_downgrade(&mw->mw_lock);
2795 mw_end = mw->mw_curpos + mw->mw_aperture;
2797 rw_assert(&mw->mw_lock, RA_RLOCKED);
2798 while (addr < mw_end && len > 0) {
2800 v = t4_read_reg(sc, mw->mw_base + addr -
2802 *val++ = le32toh(v);
2805 t4_write_reg(sc, mw->mw_base + addr -
2806 mw->mw_curpos, htole32(v));
2811 rw_runlock(&mw->mw_lock);
2818 alloc_atid_tab(struct tid_info *t, int flags)
2822 MPASS(t->natids > 0);
2823 MPASS(t->atid_tab == NULL);
2825 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2827 if (t->atid_tab == NULL)
2829 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2830 t->afree = t->atid_tab;
2831 t->atids_in_use = 0;
2832 for (i = 1; i < t->natids; i++)
2833 t->atid_tab[i - 1].next = &t->atid_tab[i];
2834 t->atid_tab[t->natids - 1].next = NULL;
2840 free_atid_tab(struct tid_info *t)
2843 KASSERT(t->atids_in_use == 0,
2844 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2846 if (mtx_initialized(&t->atid_lock))
2847 mtx_destroy(&t->atid_lock);
2848 free(t->atid_tab, M_CXGBE);
2853 alloc_atid(struct adapter *sc, void *ctx)
2855 struct tid_info *t = &sc->tids;
2858 mtx_lock(&t->atid_lock);
2860 union aopen_entry *p = t->afree;
2862 atid = p - t->atid_tab;
2863 MPASS(atid <= M_TID_TID);
2868 mtx_unlock(&t->atid_lock);
2873 lookup_atid(struct adapter *sc, int atid)
2875 struct tid_info *t = &sc->tids;
2877 return (t->atid_tab[atid].data);
2881 free_atid(struct adapter *sc, int atid)
2883 struct tid_info *t = &sc->tids;
2884 union aopen_entry *p = &t->atid_tab[atid];
2886 mtx_lock(&t->atid_lock);
2890 mtx_unlock(&t->atid_lock);
2894 queue_tid_release(struct adapter *sc, int tid)
2897 CXGBE_UNIMPLEMENTED("deferred tid release");
2901 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
2904 struct cpl_tid_release *req;
2906 wr = alloc_wrqe(sizeof(*req), ctrlq);
2908 queue_tid_release(sc, tid); /* defer */
2913 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
2919 t4_range_cmp(const void *a, const void *b)
2921 return ((const struct t4_range *)a)->start -
2922 ((const struct t4_range *)b)->start;
2926 * Verify that the memory range specified by the addr/len pair is valid within
2927 * the card's address space.
2930 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2932 struct t4_range mem_ranges[4], *r, *next;
2933 uint32_t em, addr_len;
2934 int i, n, remaining;
2936 /* Memory can only be accessed in naturally aligned 4 byte units */
2937 if (addr & 3 || len & 3 || len == 0)
2940 /* Enabled memories */
2941 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2945 bzero(r, sizeof(mem_ranges));
2946 if (em & F_EDRAM0_ENABLE) {
2947 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2948 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2950 r->start = G_EDRAM0_BASE(addr_len) << 20;
2951 if (addr >= r->start &&
2952 addr + len <= r->start + r->size)
2958 if (em & F_EDRAM1_ENABLE) {
2959 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2960 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2962 r->start = G_EDRAM1_BASE(addr_len) << 20;
2963 if (addr >= r->start &&
2964 addr + len <= r->start + r->size)
2970 if (em & F_EXT_MEM_ENABLE) {
2971 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2972 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2974 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2975 if (addr >= r->start &&
2976 addr + len <= r->start + r->size)
2982 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2983 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2984 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2986 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2987 if (addr >= r->start &&
2988 addr + len <= r->start + r->size)
2994 MPASS(n <= nitems(mem_ranges));
2997 /* Sort and merge the ranges. */
2998 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3000 /* Start from index 0 and examine the next n - 1 entries. */
3002 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3004 MPASS(r->size > 0); /* r is a valid entry. */
3006 MPASS(next->size > 0); /* and so is the next one. */
3008 while (r->start + r->size >= next->start) {
3009 /* Merge the next one into the current entry. */
3010 r->size = max(r->start + r->size,
3011 next->start + next->size) - r->start;
3012 n--; /* One fewer entry in total. */
3013 if (--remaining == 0)
3014 goto done; /* short circuit */
3017 if (next != r + 1) {
3019 * Some entries were merged into r and next
3020 * points to the first valid entry that couldn't
3023 MPASS(next->size > 0); /* must be valid */
3024 memcpy(r + 1, next, remaining * sizeof(*r));
3027 * This so that the foo->size assertion in the
3028 * next iteration of the loop do the right
3029 * thing for entries that were pulled up and are
3032 MPASS(n < nitems(mem_ranges));
3033 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3034 sizeof(struct t4_range));
3039 /* Done merging the ranges. */
3042 for (i = 0; i < n; i++, r++) {
3043 if (addr >= r->start &&
3044 addr + len <= r->start + r->size)
3053 fwmtype_to_hwmtype(int mtype)
3057 case FW_MEMTYPE_EDC0:
3059 case FW_MEMTYPE_EDC1:
3061 case FW_MEMTYPE_EXTMEM:
3063 case FW_MEMTYPE_EXTMEM1:
3066 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3071 * Verify that the memory range specified by the memtype/offset/len pair is
3072 * valid and lies entirely within the memtype specified. The global address of
3073 * the start of the range is returned in addr.
3076 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3079 uint32_t em, addr_len, maddr;
3081 /* Memory can only be accessed in naturally aligned 4 byte units */
3082 if (off & 3 || len & 3 || len == 0)
3085 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3086 switch (fwmtype_to_hwmtype(mtype)) {
3088 if (!(em & F_EDRAM0_ENABLE))
3090 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3091 maddr = G_EDRAM0_BASE(addr_len) << 20;
3094 if (!(em & F_EDRAM1_ENABLE))
3096 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3097 maddr = G_EDRAM1_BASE(addr_len) << 20;
3100 if (!(em & F_EXT_MEM_ENABLE))
3102 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3103 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3106 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3108 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3109 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3115 *addr = maddr + off; /* global address */
3116 return (validate_mem_range(sc, *addr, len));
3120 fixup_devlog_params(struct adapter *sc)
3122 struct devlog_params *dparams = &sc->params.devlog;
3125 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3126 dparams->size, &dparams->addr);
3132 update_nirq(struct intrs_and_queues *iaq, int nports)
3134 int extra = T4_EXTRA_INTR;
3137 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
3138 iaq->nirq += nports * (iaq->num_vis - 1) *
3139 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3140 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3144 * Adjust requirements to fit the number of interrupts available.
3147 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3151 const int nports = sc->params.nports;
3156 bzero(iaq, sizeof(*iaq));
3157 iaq->intr_type = itype;
3158 iaq->num_vis = t4_num_vis;
3159 iaq->ntxq = t4_ntxq;
3160 iaq->ntxq_vi = t4_ntxq_vi;
3161 iaq->nrxq = t4_nrxq;
3162 iaq->nrxq_vi = t4_nrxq_vi;
3163 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3164 if (is_offload(sc) || is_ethoffload(sc)) {
3165 iaq->nofldtxq = t4_nofldtxq;
3166 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3170 if (is_offload(sc)) {
3171 iaq->nofldrxq = t4_nofldrxq;
3172 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3176 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3177 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3180 update_nirq(iaq, nports);
3181 if (iaq->nirq <= navail &&
3182 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3184 * This is the normal case -- there are enough interrupts for
3191 * If extra VIs have been configured try reducing their count and see if
3194 while (iaq->num_vis > 1) {
3196 update_nirq(iaq, nports);
3197 if (iaq->nirq <= navail &&
3198 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3199 device_printf(sc->dev, "virtual interfaces per port "
3200 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3201 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3202 "itype %d, navail %u, nirq %d.\n",
3203 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3204 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3205 itype, navail, iaq->nirq);
3211 * Extra VIs will not be created. Log a message if they were requested.
3213 MPASS(iaq->num_vis == 1);
3214 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3215 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3216 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3217 if (iaq->num_vis != t4_num_vis) {
3218 device_printf(sc->dev, "extra virtual interfaces disabled. "
3219 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3220 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3221 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3222 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3226 * Keep reducing the number of NIC rx queues to the next lower power of
3227 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3231 if (iaq->nrxq > 1) {
3234 } while (!powerof2(iaq->nrxq));
3236 if (iaq->nofldrxq > 1)
3237 iaq->nofldrxq >>= 1;
3239 old_nirq = iaq->nirq;
3240 update_nirq(iaq, nports);
3241 if (iaq->nirq <= navail &&
3242 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3243 device_printf(sc->dev, "running with reduced number of "
3244 "rx queues because of shortage of interrupts. "
3245 "nrxq=%u, nofldrxq=%u. "
3246 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3247 iaq->nofldrxq, itype, navail, iaq->nirq);
3250 } while (old_nirq != iaq->nirq);
3252 /* One interrupt for everything. Ugh. */
3253 device_printf(sc->dev, "running with minimal number of queues. "
3254 "itype %d, navail %u.\n", itype, navail);
3256 MPASS(iaq->nrxq == 1);
3258 if (iaq->nofldrxq > 1)
3261 MPASS(iaq->num_vis > 0);
3262 if (iaq->num_vis > 1) {
3263 MPASS(iaq->nrxq_vi > 0);
3264 MPASS(iaq->ntxq_vi > 0);
3266 MPASS(iaq->nirq > 0);
3267 MPASS(iaq->nrxq > 0);
3268 MPASS(iaq->ntxq > 0);
3269 if (itype == INTR_MSI) {
3270 MPASS(powerof2(iaq->nirq));
3275 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3277 int rc, itype, navail, nalloc;
3279 for (itype = INTR_MSIX; itype; itype >>= 1) {
3281 if ((itype & t4_intr_types) == 0)
3282 continue; /* not allowed */
3284 if (itype == INTR_MSIX)
3285 navail = pci_msix_count(sc->dev);
3286 else if (itype == INTR_MSI)
3287 navail = pci_msi_count(sc->dev);
3294 calculate_iaq(sc, iaq, itype, navail);
3297 if (itype == INTR_MSIX)
3298 rc = pci_alloc_msix(sc->dev, &nalloc);
3299 else if (itype == INTR_MSI)
3300 rc = pci_alloc_msi(sc->dev, &nalloc);
3302 if (rc == 0 && nalloc > 0) {
3303 if (nalloc == iaq->nirq)
3307 * Didn't get the number requested. Use whatever number
3308 * the kernel is willing to allocate.
3310 device_printf(sc->dev, "fewer vectors than requested, "
3311 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3312 itype, iaq->nirq, nalloc);
3313 pci_release_msi(sc->dev);
3318 device_printf(sc->dev,
3319 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3320 itype, rc, iaq->nirq, nalloc);
3323 device_printf(sc->dev,
3324 "failed to find a usable interrupt type. "
3325 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3326 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3331 #define FW_VERSION(chip) ( \
3332 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3333 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3334 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3335 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3336 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3338 /* Just enough of fw_hdr to cover all version info. */
3344 __be32 tp_microcode_ver;
3349 __u8 intfver_iscsipdu;
3351 __u8 intfver_fcoepdu;
3354 /* Spot check a couple of fields. */
3355 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3356 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3357 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3367 .kld_name = "t4fw_cfg",
3368 .fw_mod_name = "t4fw",
3370 .chip = FW_HDR_CHIP_T4,
3371 .fw_ver = htobe32(FW_VERSION(T4)),
3372 .intfver_nic = FW_INTFVER(T4, NIC),
3373 .intfver_vnic = FW_INTFVER(T4, VNIC),
3374 .intfver_ofld = FW_INTFVER(T4, OFLD),
3375 .intfver_ri = FW_INTFVER(T4, RI),
3376 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3377 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3378 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3379 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3383 .kld_name = "t5fw_cfg",
3384 .fw_mod_name = "t5fw",
3386 .chip = FW_HDR_CHIP_T5,
3387 .fw_ver = htobe32(FW_VERSION(T5)),
3388 .intfver_nic = FW_INTFVER(T5, NIC),
3389 .intfver_vnic = FW_INTFVER(T5, VNIC),
3390 .intfver_ofld = FW_INTFVER(T5, OFLD),
3391 .intfver_ri = FW_INTFVER(T5, RI),
3392 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3393 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3394 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3395 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3399 .kld_name = "t6fw_cfg",
3400 .fw_mod_name = "t6fw",
3402 .chip = FW_HDR_CHIP_T6,
3403 .fw_ver = htobe32(FW_VERSION(T6)),
3404 .intfver_nic = FW_INTFVER(T6, NIC),
3405 .intfver_vnic = FW_INTFVER(T6, VNIC),
3406 .intfver_ofld = FW_INTFVER(T6, OFLD),
3407 .intfver_ri = FW_INTFVER(T6, RI),
3408 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3409 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3410 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3411 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3416 static struct fw_info *
3417 find_fw_info(int chip)
3421 for (i = 0; i < nitems(fw_info); i++) {
3422 if (fw_info[i].chip == chip)
3423 return (&fw_info[i]);
3429 * Is the given firmware API compatible with the one the driver was compiled
3433 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3436 /* short circuit if it's the exact same firmware version */
3437 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3441 * XXX: Is this too conservative? Perhaps I should limit this to the
3442 * features that are supported in the driver.
3444 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3445 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3446 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3447 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3455 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3456 const struct firmware **fw)
3458 struct fw_info *fw_info;
3464 fw_info = find_fw_info(chip_id(sc));
3465 if (fw_info == NULL) {
3466 device_printf(sc->dev,
3467 "unable to look up firmware information for chip %d.\n",
3472 *dcfg = firmware_get(fw_info->kld_name);
3473 if (*dcfg != NULL) {
3475 *fw = firmware_get(fw_info->fw_mod_name);
3483 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3484 const struct firmware *fw)
3488 firmware_put(fw, FIRMWARE_UNLOAD);
3490 firmware_put(dcfg, FIRMWARE_UNLOAD);
3495 * 0 means no firmware install attempted.
3496 * ERESTART means a firmware install was attempted and was successful.
3497 * +ve errno means a firmware install was attempted but failed.
3500 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3501 const struct fw_h *drv_fw, const char *reason, int *already)
3503 const struct firmware *cfg, *fw;
3504 const uint32_t c = be32toh(card_fw->fw_ver);
3507 struct fw_h bundled_fw;
3508 bool load_attempted;
3511 load_attempted = false;
3512 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3517 if ((sc->flags & FW_OK) == 0) {
3519 if (c == 0xffffffff) {
3527 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3528 if (t4_fw_install < 0) {
3529 rc = load_fw_module(sc, &cfg, &fw);
3530 if (rc != 0 || fw == NULL) {
3531 device_printf(sc->dev,
3532 "failed to load firmware module: %d. cfg %p, fw %p;"
3533 " will use compiled-in firmware version for"
3534 "hw.cxgbe.fw_install checks.\n",
3537 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3539 load_attempted = true;
3541 d = be32toh(bundled_fw.fw_ver);
3543 if (!fw_compatible(card_fw, &bundled_fw)) {
3544 reason = "incompatible or unusable";
3549 reason = "older than the version bundled with this driver";
3553 if (fw_install == 2 && d != c) {
3554 reason = "different than the version bundled with this driver";
3558 /* No reason to do anything to the firmware already on the card. */
3567 if (fw_install == 0) {
3568 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3569 "but the driver is prohibited from installing a firmware "
3571 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3572 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3578 * We'll attempt to install a firmware. Load the module first (if it
3579 * hasn't been loaded already).
3581 if (!load_attempted) {
3582 rc = load_fw_module(sc, &cfg, &fw);
3583 if (rc != 0 || fw == NULL) {
3584 device_printf(sc->dev,
3585 "failed to load firmware module: %d. cfg %p, fw %p\n",
3591 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3592 "but the driver cannot take corrective action because it "
3593 "is unable to load the firmware module.\n",
3594 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3595 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3596 rc = sc->flags & FW_OK ? 0 : ENOENT;
3599 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3601 MPASS(t4_fw_install > 0);
3602 device_printf(sc->dev,
3603 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3604 "expecting (%u.%u.%u.%u) and will not be used.\n",
3605 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3606 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3607 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3608 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3609 rc = sc->flags & FW_OK ? 0 : EINVAL;
3613 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3614 "installing firmware %u.%u.%u.%u on card.\n",
3615 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3616 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3617 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3618 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3620 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3622 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3624 /* Installed successfully, update the cached header too. */
3626 memcpy(card_fw, fw->data, sizeof(*card_fw));
3629 unload_fw_module(sc, cfg, fw);
3635 * Establish contact with the firmware and attempt to become the master driver.
3637 * A firmware will be installed to the card if needed (if the driver is allowed
3641 contact_firmware(struct adapter *sc)
3643 int rc, already = 0;
3644 enum dev_state state;
3645 struct fw_info *fw_info;
3646 struct fw_hdr *card_fw; /* fw on the card */
3647 const struct fw_h *drv_fw;
3649 fw_info = find_fw_info(chip_id(sc));
3650 if (fw_info == NULL) {
3651 device_printf(sc->dev,
3652 "unable to look up firmware information for chip %d.\n",
3656 drv_fw = &fw_info->fw_h;
3658 /* Read the header of the firmware on the card */
3659 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3661 rc = -t4_get_fw_hdr(sc, card_fw);
3663 device_printf(sc->dev,
3664 "unable to read firmware header from card's flash: %d\n",
3669 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3676 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3677 if (rc < 0 || state == DEV_STATE_ERR) {
3679 device_printf(sc->dev,
3680 "failed to connect to the firmware: %d, %d. "
3681 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3683 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3684 "not responding properly to HELLO", &already) == ERESTART)
3689 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3690 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3693 sc->flags |= MASTER_PF;
3694 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3700 } else if (state == DEV_STATE_UNINIT) {
3702 * We didn't get to be the master so we definitely won't be
3703 * configuring the chip. It's a bug if someone else hasn't
3704 * configured it already.
3706 device_printf(sc->dev, "couldn't be master(%d), "
3707 "device not already initialized either(%d). "
3708 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3713 * Some other PF is the master and has configured the chip.
3714 * This is allowed but untested.
3716 device_printf(sc->dev, "PF%d is master, device state %d. "
3717 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3718 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3723 if (rc != 0 && sc->flags & FW_OK) {
3724 t4_fw_bye(sc, sc->mbox);
3725 sc->flags &= ~FW_OK;
3727 free(card_fw, M_CXGBE);
3732 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3733 uint32_t mtype, uint32_t moff)
3735 struct fw_info *fw_info;
3736 const struct firmware *dcfg, *rcfg = NULL;
3737 const uint32_t *cfdata;
3738 uint32_t cflen, addr;
3741 load_fw_module(sc, &dcfg, NULL);
3743 /* Card specific interpretation of "default". */
3744 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3745 if (pci_get_device(sc->dev) == 0x440a)
3746 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3748 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3751 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3753 device_printf(sc->dev,
3754 "KLD with default config is not available.\n");
3758 cfdata = dcfg->data;
3759 cflen = dcfg->datasize & ~3;
3763 fw_info = find_fw_info(chip_id(sc));
3764 if (fw_info == NULL) {
3765 device_printf(sc->dev,
3766 "unable to look up firmware information for chip %d.\n",
3771 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
3773 rcfg = firmware_get(s);
3775 device_printf(sc->dev,
3776 "unable to load module \"%s\" for configuration "
3777 "profile \"%s\".\n", s, cfg_file);
3781 cfdata = rcfg->data;
3782 cflen = rcfg->datasize & ~3;
3785 if (cflen > FLASH_CFG_MAX_SIZE) {
3786 device_printf(sc->dev,
3787 "config file too long (%d, max allowed is %d).\n",
3788 cflen, FLASH_CFG_MAX_SIZE);
3793 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3795 device_printf(sc->dev,
3796 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
3797 __func__, mtype, moff, cflen, rc);
3801 write_via_memwin(sc, 2, addr, cfdata, cflen);
3804 firmware_put(rcfg, FIRMWARE_UNLOAD);
3805 unload_fw_module(sc, dcfg, NULL);
3809 struct caps_allowed {
3812 uint16_t switchcaps;
3816 uint16_t cryptocaps;
3821 #define FW_PARAM_DEV(param) \
3822 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3823 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3824 #define FW_PARAM_PFVF(param) \
3825 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3826 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3829 * Provide a configuration profile to the firmware and have it initialize the
3830 * chip accordingly. This may involve uploading a configuration file to the
3834 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
3835 const struct caps_allowed *caps_allowed)
3838 struct fw_caps_config_cmd caps;
3839 uint32_t mtype, moff, finicsum, cfcsum, param, val;
3841 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3843 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3847 bzero(&caps, sizeof(caps));
3848 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3849 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3850 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
3853 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3854 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
3855 mtype = FW_MEMTYPE_FLASH;
3856 moff = t4_flash_cfg_addr(sc);
3857 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3858 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3859 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3863 * Ask the firmware where it wants us to upload the config file.
3865 param = FW_PARAM_DEV(CF);
3866 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3868 /* No support for config file? Shouldn't happen. */
3869 device_printf(sc->dev,
3870 "failed to query config file location: %d.\n", rc);
3873 mtype = G_FW_PARAMS_PARAM_Y(val);
3874 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3875 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3876 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3877 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3880 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
3882 device_printf(sc->dev,
3883 "failed to upload config file to card: %d.\n", rc);
3887 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3889 device_printf(sc->dev, "failed to pre-process config file: %d "
3890 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3894 finicsum = be32toh(caps.finicsum);
3895 cfcsum = be32toh(caps.cfcsum); /* actual */
3896 if (finicsum != cfcsum) {
3897 device_printf(sc->dev,
3898 "WARNING: config file checksum mismatch: %08x %08x\n",
3901 sc->cfcsum = cfcsum;
3902 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
3905 * Let the firmware know what features will (not) be used so it can tune
3906 * things accordingly.
3908 #define LIMIT_CAPS(x) do { \
3909 caps.x##caps &= htobe16(caps_allowed->x##caps); \
3921 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
3923 * TOE and hashfilters are mutually exclusive. It is a config
3924 * file or firmware bug if both are reported as available. Try
3925 * to cope with the situation in non-debug builds by disabling
3928 MPASS(caps.toecaps == 0);
3935 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3936 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3937 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3938 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3940 device_printf(sc->dev,
3941 "failed to process config file: %d.\n", rc);
3945 t4_tweak_chip_settings(sc);
3947 /* get basic stuff going */
3948 rc = -t4_fw_initialize(sc, sc->mbox);
3950 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
3958 * Partition chip resources for use between various PFs, VFs, etc.
3961 partition_resources(struct adapter *sc)
3963 char cfg_file[sizeof(t4_cfg_file)];
3964 struct caps_allowed caps_allowed;
3968 /* Only the master driver gets to configure the chip resources. */
3969 MPASS(sc->flags & MASTER_PF);
3971 #define COPY_CAPS(x) do { \
3972 caps_allowed.x##caps = t4_##x##caps_allowed; \
3974 bzero(&caps_allowed, sizeof(caps_allowed));
3984 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
3985 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
3987 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
3988 if (rc != 0 && fallback) {
3989 device_printf(sc->dev,
3990 "failed (%d) to configure card with \"%s\" profile, "
3991 "will fall back to a basic configuration and retry.\n",
3993 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
3994 bzero(&caps_allowed, sizeof(caps_allowed));
4007 * Retrieve parameters that are needed (or nice to have) very early.
4010 get_params__pre_init(struct adapter *sc)
4013 uint32_t param[2], val[2];
4015 t4_get_version_info(sc);
4017 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4018 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4019 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4020 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4021 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4023 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4024 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4025 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4026 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4027 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4029 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4030 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4031 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4032 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4033 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4035 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4036 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4037 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4038 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4039 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4041 param[0] = FW_PARAM_DEV(PORTVEC);
4042 param[1] = FW_PARAM_DEV(CCLK);
4043 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4045 device_printf(sc->dev,
4046 "failed to query parameters (pre_init): %d.\n", rc);
4050 sc->params.portvec = val[0];
4051 sc->params.nports = bitcount32(val[0]);
4052 sc->params.vpd.cclk = val[1];
4054 /* Read device log parameters. */
4055 rc = -t4_init_devlog_params(sc, 1);
4057 fixup_devlog_params(sc);
4059 device_printf(sc->dev,
4060 "failed to get devlog parameters: %d.\n", rc);
4061 rc = 0; /* devlog isn't critical for device operation */
4068 * Retrieve various parameters that are of interest to the driver. The device
4069 * has been initialized by the firmware at this point.
4072 get_params__post_init(struct adapter *sc)
4075 uint32_t param[7], val[7];
4076 struct fw_caps_config_cmd caps;
4078 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4079 param[1] = FW_PARAM_PFVF(EQ_START);
4080 param[2] = FW_PARAM_PFVF(FILTER_START);
4081 param[3] = FW_PARAM_PFVF(FILTER_END);
4082 param[4] = FW_PARAM_PFVF(L2T_START);
4083 param[5] = FW_PARAM_PFVF(L2T_END);
4084 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4085 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4086 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4087 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4089 device_printf(sc->dev,
4090 "failed to query parameters (post_init): %d.\n", rc);
4094 sc->sge.iq_start = val[0];
4095 sc->sge.eq_start = val[1];
4096 if ((int)val[3] > (int)val[2]) {
4097 sc->tids.ftid_base = val[2];
4098 sc->tids.ftid_end = val[3];
4099 sc->tids.nftids = val[3] - val[2] + 1;
4101 sc->vres.l2t.start = val[4];
4102 sc->vres.l2t.size = val[5] - val[4] + 1;
4103 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4104 ("%s: L2 table size (%u) larger than expected (%u)",
4105 __func__, sc->vres.l2t.size, L2T_SIZE));
4106 sc->params.core_vdd = val[6];
4108 if (chip_id(sc) >= CHELSIO_T6) {
4111 if (sc->params.fw_vers >=
4112 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4113 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) {
4115 * Note that the code to enable the region should run
4116 * before t4_fw_initialize and not here. This is just a
4117 * reminder to add said code.
4119 device_printf(sc->dev,
4120 "hpfilter region not enabled.\n");
4124 sc->tids.tid_base = t4_read_reg(sc,
4125 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4127 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4128 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4129 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4131 device_printf(sc->dev,
4132 "failed to query hpfilter parameters: %d.\n", rc);
4135 if ((int)val[1] > (int)val[0]) {
4136 sc->tids.hpftid_base = val[0];
4137 sc->tids.hpftid_end = val[1];
4138 sc->tids.nhpftids = val[1] - val[0] + 1;
4141 * These should go off if the layout changes and the
4142 * driver needs to catch up.
4144 MPASS(sc->tids.hpftid_base == 0);
4145 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4150 * MPSBGMAP is queried separately because only recent firmwares support
4151 * it as a parameter and we don't want the compound query above to fail
4152 * on older firmwares.
4154 param[0] = FW_PARAM_DEV(MPSBGMAP);
4156 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4158 sc->params.mps_bg_map = val[0];
4160 sc->params.mps_bg_map = 0;
4163 * Determine whether the firmware supports the filter2 work request.
4164 * This is queried separately for the same reason as MPSBGMAP above.
4166 param[0] = FW_PARAM_DEV(FILTER2_WR);
4168 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4170 sc->params.filter2_wr_support = val[0] != 0;
4172 sc->params.filter2_wr_support = 0;
4175 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4176 * This is queried separately for the same reason as other params above.
4178 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4180 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4182 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4184 sc->params.ulptx_memwrite_dsgl = false;
4186 /* get capabilites */
4187 bzero(&caps, sizeof(caps));
4188 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4189 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4190 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4191 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4193 device_printf(sc->dev,
4194 "failed to get card capabilities: %d.\n", rc);
4198 #define READ_CAPS(x) do { \
4199 sc->x = htobe16(caps.x); \
4202 READ_CAPS(linkcaps);
4203 READ_CAPS(switchcaps);
4206 READ_CAPS(rdmacaps);
4207 READ_CAPS(cryptocaps);
4208 READ_CAPS(iscsicaps);
4209 READ_CAPS(fcoecaps);
4211 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4212 MPASS(chip_id(sc) > CHELSIO_T4);
4213 MPASS(sc->toecaps == 0);
4216 param[0] = FW_PARAM_DEV(NTID);
4217 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4219 device_printf(sc->dev,
4220 "failed to query HASHFILTER parameters: %d.\n", rc);
4223 sc->tids.ntids = val[0];
4224 if (sc->params.fw_vers <
4225 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4226 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4227 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4228 sc->tids.ntids -= sc->tids.nhpftids;
4230 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4231 sc->params.hash_filter = 1;
4233 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4234 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4235 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4236 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4237 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4239 device_printf(sc->dev,
4240 "failed to query NIC parameters: %d.\n", rc);
4243 if ((int)val[1] > (int)val[0]) {
4244 sc->tids.etid_base = val[0];
4245 sc->tids.etid_end = val[1];
4246 sc->tids.netids = val[1] - val[0] + 1;
4247 sc->params.eo_wr_cred = val[2];
4248 sc->params.ethoffload = 1;
4252 /* query offload-related parameters */
4253 param[0] = FW_PARAM_DEV(NTID);
4254 param[1] = FW_PARAM_PFVF(SERVER_START);
4255 param[2] = FW_PARAM_PFVF(SERVER_END);
4256 param[3] = FW_PARAM_PFVF(TDDP_START);
4257 param[4] = FW_PARAM_PFVF(TDDP_END);
4258 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4259 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4261 device_printf(sc->dev,
4262 "failed to query TOE parameters: %d.\n", rc);
4265 sc->tids.ntids = val[0];
4266 if (sc->params.fw_vers <
4267 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4268 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4269 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4270 sc->tids.ntids -= sc->tids.nhpftids;
4272 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4273 if ((int)val[2] > (int)val[1]) {
4274 sc->tids.stid_base = val[1];
4275 sc->tids.nstids = val[2] - val[1] + 1;
4277 sc->vres.ddp.start = val[3];
4278 sc->vres.ddp.size = val[4] - val[3] + 1;
4279 sc->params.ofldq_wr_cred = val[5];
4280 sc->params.offload = 1;
4283 * The firmware attempts memfree TOE configuration for -SO cards
4284 * and will report toecaps=0 if it runs out of resources (this
4285 * depends on the config file). It may not report 0 for other
4286 * capabilities dependent on the TOE in this case. Set them to
4287 * 0 here so that the driver doesn't bother tracking resources
4288 * that will never be used.
4294 param[0] = FW_PARAM_PFVF(STAG_START);
4295 param[1] = FW_PARAM_PFVF(STAG_END);
4296 param[2] = FW_PARAM_PFVF(RQ_START);
4297 param[3] = FW_PARAM_PFVF(RQ_END);
4298 param[4] = FW_PARAM_PFVF(PBL_START);
4299 param[5] = FW_PARAM_PFVF(PBL_END);
4300 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4302 device_printf(sc->dev,
4303 "failed to query RDMA parameters(1): %d.\n", rc);
4306 sc->vres.stag.start = val[0];
4307 sc->vres.stag.size = val[1] - val[0] + 1;
4308 sc->vres.rq.start = val[2];
4309 sc->vres.rq.size = val[3] - val[2] + 1;
4310 sc->vres.pbl.start = val[4];
4311 sc->vres.pbl.size = val[5] - val[4] + 1;
4313 param[0] = FW_PARAM_PFVF(SQRQ_START);
4314 param[1] = FW_PARAM_PFVF(SQRQ_END);
4315 param[2] = FW_PARAM_PFVF(CQ_START);
4316 param[3] = FW_PARAM_PFVF(CQ_END);
4317 param[4] = FW_PARAM_PFVF(OCQ_START);
4318 param[5] = FW_PARAM_PFVF(OCQ_END);
4319 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4321 device_printf(sc->dev,
4322 "failed to query RDMA parameters(2): %d.\n", rc);
4325 sc->vres.qp.start = val[0];
4326 sc->vres.qp.size = val[1] - val[0] + 1;
4327 sc->vres.cq.start = val[2];
4328 sc->vres.cq.size = val[3] - val[2] + 1;
4329 sc->vres.ocq.start = val[4];
4330 sc->vres.ocq.size = val[5] - val[4] + 1;
4332 param[0] = FW_PARAM_PFVF(SRQ_START);
4333 param[1] = FW_PARAM_PFVF(SRQ_END);
4334 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4335 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4336 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4338 device_printf(sc->dev,
4339 "failed to query RDMA parameters(3): %d.\n", rc);
4342 sc->vres.srq.start = val[0];
4343 sc->vres.srq.size = val[1] - val[0] + 1;
4344 sc->params.max_ordird_qp = val[2];
4345 sc->params.max_ird_adapter = val[3];
4347 if (sc->iscsicaps) {
4348 param[0] = FW_PARAM_PFVF(ISCSI_START);
4349 param[1] = FW_PARAM_PFVF(ISCSI_END);
4350 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4352 device_printf(sc->dev,
4353 "failed to query iSCSI parameters: %d.\n", rc);
4356 sc->vres.iscsi.start = val[0];
4357 sc->vres.iscsi.size = val[1] - val[0] + 1;
4359 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4360 param[0] = FW_PARAM_PFVF(TLS_START);
4361 param[1] = FW_PARAM_PFVF(TLS_END);
4362 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4364 device_printf(sc->dev,
4365 "failed to query TLS parameters: %d.\n", rc);
4368 sc->vres.key.start = val[0];
4369 sc->vres.key.size = val[1] - val[0] + 1;
4372 t4_init_sge_params(sc);
4375 * We've got the params we wanted to query via the firmware. Now grab
4376 * some others directly from the chip.
4378 rc = t4_read_chip_settings(sc);
4384 set_params__post_init(struct adapter *sc)
4386 uint32_t param, val;
4391 /* ask for encapsulated CPLs */
4392 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4394 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4396 /* Enable 32b port caps if the firmware supports it. */
4397 param = FW_PARAM_PFVF(PORT_CAPS32);
4399 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4400 sc->params.port_caps32 = 1;
4402 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4403 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4404 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4405 V_MASKFILTER(val - 1));
4409 * Override the TOE timers with user provided tunables. This is not the
4410 * recommended way to change the timers (the firmware config file is) so
4411 * these tunables are not documented.
4413 * All the timer tunables are in microseconds.
4415 if (t4_toe_keepalive_idle != 0) {
4416 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4417 v &= M_KEEPALIVEIDLE;
4418 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4419 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4421 if (t4_toe_keepalive_interval != 0) {
4422 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4423 v &= M_KEEPALIVEINTVL;
4424 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4425 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4427 if (t4_toe_keepalive_count != 0) {
4428 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4429 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4430 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4431 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4432 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4434 if (t4_toe_rexmt_min != 0) {
4435 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4437 t4_set_reg_field(sc, A_TP_RXT_MIN,
4438 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4440 if (t4_toe_rexmt_max != 0) {
4441 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4443 t4_set_reg_field(sc, A_TP_RXT_MAX,
4444 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4446 if (t4_toe_rexmt_count != 0) {
4447 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4448 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4449 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4450 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4451 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4453 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4454 if (t4_toe_rexmt_backoff[i] != -1) {
4455 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4456 shift = (i & 3) << 3;
4457 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4458 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4465 #undef FW_PARAM_PFVF
4469 t4_set_desc(struct adapter *sc)
4472 struct adapter_params *p = &sc->params;
4474 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4476 device_set_desc_copy(sc->dev, buf);
4480 ifmedia_add4(struct ifmedia *ifm, int m)
4483 ifmedia_add(ifm, m, 0, NULL);
4484 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4485 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4486 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4490 * This is the selected media, which is not quite the same as the active media.
4491 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4492 * and active are not the same, and "media: Ethernet selected" otherwise.
4495 set_current_media(struct port_info *pi)
4497 struct link_config *lc;
4498 struct ifmedia *ifm;
4502 PORT_LOCK_ASSERT_OWNED(pi);
4504 /* Leave current media alone if it's already set to IFM_NONE. */
4506 if (ifm->ifm_cur != NULL &&
4507 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4511 if (lc->requested_aneg != AUTONEG_DISABLE &&
4512 lc->supported & FW_PORT_CAP32_ANEG) {
4513 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4516 mword = IFM_ETHER | IFM_FDX;
4517 if (lc->requested_fc & PAUSE_TX)
4518 mword |= IFM_ETH_TXPAUSE;
4519 if (lc->requested_fc & PAUSE_RX)
4520 mword |= IFM_ETH_RXPAUSE;
4521 if (lc->requested_speed == 0)
4522 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4524 speed = lc->requested_speed;
4525 mword |= port_mword(pi, speed_to_fwcap(speed));
4526 ifmedia_set(ifm, mword);
4530 * Returns true if the ifmedia list for the port cannot change.
4533 fixed_ifmedia(struct port_info *pi)
4536 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4537 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4538 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4539 pi->port_type == FW_PORT_TYPE_KX4 ||
4540 pi->port_type == FW_PORT_TYPE_KX ||
4541 pi->port_type == FW_PORT_TYPE_KR ||
4542 pi->port_type == FW_PORT_TYPE_BP_AP ||
4543 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4544 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4545 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4546 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4547 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4551 build_medialist(struct port_info *pi)
4554 int unknown, mword, bit;
4555 struct link_config *lc;
4556 struct ifmedia *ifm;
4558 PORT_LOCK_ASSERT_OWNED(pi);
4560 if (pi->flags & FIXED_IFMEDIA)
4564 * Rebuild the ifmedia list.
4567 ifmedia_removeall(ifm);
4569 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4570 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4573 MPASS(LIST_EMPTY(&ifm->ifm_list));
4574 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4575 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4580 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4582 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4584 mword = port_mword(pi, speed);
4585 if (mword == IFM_NONE) {
4587 } else if (mword == IFM_UNKNOWN)
4590 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4593 if (unknown > 0) /* Add one unknown for all unknown media types. */
4594 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4595 if (lc->supported & FW_PORT_CAP32_ANEG)
4596 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4598 set_current_media(pi);
4602 * Initialize the requested fields in the link config based on driver tunables.
4605 init_link_config(struct port_info *pi)
4607 struct link_config *lc = &pi->link_cfg;
4609 PORT_LOCK_ASSERT_OWNED(pi);
4611 lc->requested_speed = 0;
4613 if (t4_autoneg == 0)
4614 lc->requested_aneg = AUTONEG_DISABLE;
4615 else if (t4_autoneg == 1)
4616 lc->requested_aneg = AUTONEG_ENABLE;
4618 lc->requested_aneg = AUTONEG_AUTO;
4620 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4623 if (t4_fec == -1 || t4_fec & FEC_AUTO)
4624 lc->requested_fec = FEC_AUTO;
4626 lc->requested_fec = FEC_NONE;
4627 if (t4_fec & FEC_RS)
4628 lc->requested_fec |= FEC_RS;
4629 if (t4_fec & FEC_BASER_RS)
4630 lc->requested_fec |= FEC_BASER_RS;
4635 * Makes sure that all requested settings comply with what's supported by the
4636 * port. Returns the number of settings that were invalid and had to be fixed.
4639 fixup_link_config(struct port_info *pi)
4642 struct link_config *lc = &pi->link_cfg;
4645 PORT_LOCK_ASSERT_OWNED(pi);
4647 /* Speed (when not autonegotiating) */
4648 if (lc->requested_speed != 0) {
4649 fwspeed = speed_to_fwcap(lc->requested_speed);
4650 if ((fwspeed & lc->supported) == 0) {
4652 lc->requested_speed = 0;
4656 /* Link autonegotiation */
4657 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4658 lc->requested_aneg == AUTONEG_DISABLE ||
4659 lc->requested_aneg == AUTONEG_AUTO);
4660 if (lc->requested_aneg == AUTONEG_ENABLE &&
4661 !(lc->supported & FW_PORT_CAP32_ANEG)) {
4663 lc->requested_aneg = AUTONEG_AUTO;
4667 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4668 if (lc->requested_fc & PAUSE_TX &&
4669 !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4671 lc->requested_fc &= ~PAUSE_TX;
4673 if (lc->requested_fc & PAUSE_RX &&
4674 !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4676 lc->requested_fc &= ~PAUSE_RX;
4678 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4679 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4681 lc->requested_fc |= PAUSE_AUTONEG;
4685 if ((lc->requested_fec & FEC_RS &&
4686 !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4687 (lc->requested_fec & FEC_BASER_RS &&
4688 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4690 lc->requested_fec = FEC_AUTO;
4697 * Apply the requested L1 settings, which are expected to be valid, to the
4701 apply_link_config(struct port_info *pi)
4703 struct adapter *sc = pi->adapter;
4704 struct link_config *lc = &pi->link_cfg;
4708 ASSERT_SYNCHRONIZED_OP(sc);
4709 PORT_LOCK_ASSERT_OWNED(pi);
4711 if (lc->requested_aneg == AUTONEG_ENABLE)
4712 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4713 if (!(lc->requested_fc & PAUSE_AUTONEG))
4714 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4715 if (lc->requested_fc & PAUSE_TX)
4716 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4717 if (lc->requested_fc & PAUSE_RX)
4718 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4719 if (lc->requested_fec & FEC_RS)
4720 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4721 if (lc->requested_fec & FEC_BASER_RS)
4722 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4724 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4726 /* Don't complain if the VF driver gets back an EPERM. */
4727 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
4728 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4731 * An L1_CFG will almost always result in a link-change event if
4732 * the link is up, and the driver will refresh the actual
4733 * fec/fc/etc. when the notification is processed. If the link
4734 * is down then the actual settings are meaningless.
4736 * This takes care of the case where a change in the L1 settings
4737 * may not result in a notification.
4739 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4740 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4745 #define FW_MAC_EXACT_CHUNK 7
4748 * Program the port's XGMAC based on parameters in ifnet. The caller also
4749 * indicates which parameters should be programmed (the rest are left alone).
4752 update_mac_settings(struct ifnet *ifp, int flags)
4755 struct vi_info *vi = ifp->if_softc;
4756 struct port_info *pi = vi->pi;
4757 struct adapter *sc = pi->adapter;
4758 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4760 ASSERT_SYNCHRONIZED_OP(sc);
4761 KASSERT(flags, ("%s: not told what to update.", __func__));
4763 if (flags & XGMAC_MTU)
4766 if (flags & XGMAC_PROMISC)
4767 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4769 if (flags & XGMAC_ALLMULTI)
4770 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4772 if (flags & XGMAC_VLANEX)
4773 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4775 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4776 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4777 allmulti, 1, vlanex, false);
4779 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4785 if (flags & XGMAC_UCADDR) {
4786 uint8_t ucaddr[ETHER_ADDR_LEN];
4788 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4789 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4790 ucaddr, true, true);
4793 if_printf(ifp, "change_mac failed: %d\n", rc);
4796 vi->xact_addr_filt = rc;
4801 if (flags & XGMAC_MCADDRS) {
4802 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4805 struct ifmultiaddr *ifma;
4808 if_maddr_rlock(ifp);
4809 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4810 if (ifma->ifma_addr->sa_family != AF_LINK)
4813 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4814 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4817 if (i == FW_MAC_EXACT_CHUNK) {
4818 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4819 del, i, mcaddr, NULL, &hash, 0);
4822 for (j = 0; j < i; j++) {
4824 "failed to add mc address"
4826 "%02x:%02x:%02x rc=%d\n",
4827 mcaddr[j][0], mcaddr[j][1],
4828 mcaddr[j][2], mcaddr[j][3],
4829 mcaddr[j][4], mcaddr[j][5],
4839 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4840 mcaddr, NULL, &hash, 0);
4843 for (j = 0; j < i; j++) {
4845 "failed to add mc address"
4847 "%02x:%02x:%02x rc=%d\n",
4848 mcaddr[j][0], mcaddr[j][1],
4849 mcaddr[j][2], mcaddr[j][3],
4850 mcaddr[j][4], mcaddr[j][5],
4857 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4859 if_printf(ifp, "failed to set mc address hash: %d", rc);
4861 if_maddr_runlock(ifp);
4868 * {begin|end}_synchronized_op must be called from the same thread.
4871 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4877 /* the caller thinks it's ok to sleep, but is it really? */
4878 if (flags & SLEEP_OK)
4879 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4880 "begin_synchronized_op");
4891 if (vi && IS_DOOMED(vi)) {
4901 if (!(flags & SLEEP_OK)) {
4906 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4912 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4915 sc->last_op = wmesg;
4916 sc->last_op_thr = curthread;
4917 sc->last_op_flags = flags;
4921 if (!(flags & HOLD_LOCK) || rc)
4928 * Tell if_ioctl and if_init that the VI is going away. This is
4929 * special variant of begin_synchronized_op and must be paired with a
4930 * call to end_synchronized_op.
4933 doom_vi(struct adapter *sc, struct vi_info *vi)
4940 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4943 sc->last_op = "t4detach";
4944 sc->last_op_thr = curthread;
4945 sc->last_op_flags = 0;
4951 * {begin|end}_synchronized_op must be called from the same thread.
4954 end_synchronized_op(struct adapter *sc, int flags)
4957 if (flags & LOCK_HELD)
4958 ADAPTER_LOCK_ASSERT_OWNED(sc);
4962 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4969 cxgbe_init_synchronized(struct vi_info *vi)
4971 struct port_info *pi = vi->pi;
4972 struct adapter *sc = pi->adapter;
4973 struct ifnet *ifp = vi->ifp;
4975 struct sge_txq *txq;
4977 ASSERT_SYNCHRONIZED_OP(sc);
4979 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4980 return (0); /* already running */
4982 if (!(sc->flags & FULL_INIT_DONE) &&
4983 ((rc = adapter_full_init(sc)) != 0))
4984 return (rc); /* error message displayed already */
4986 if (!(vi->flags & VI_INIT_DONE) &&
4987 ((rc = vi_full_init(vi)) != 0))
4988 return (rc); /* error message displayed already */
4990 rc = update_mac_settings(ifp, XGMAC_ALL);
4992 goto done; /* error message displayed already */
4995 if (pi->up_vis == 0) {
4996 t4_update_port_info(pi);
4997 fixup_link_config(pi);
4998 build_medialist(pi);
4999 apply_link_config(pi);
5002 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5004 if_printf(ifp, "enable_vi failed: %d\n", rc);
5010 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5014 for_each_txq(vi, i, txq) {
5016 txq->eq.flags |= EQ_ENABLED;
5021 * The first iq of the first port to come up is used for tracing.
5023 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5024 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5025 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5026 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5027 V_QUEUENUMBER(sc->traceq));
5028 pi->flags |= HAS_TRACEQ;
5033 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5035 if (pi->nvi > 1 || sc->flags & IS_VF)
5036 callout_reset(&vi->tick, hz, vi_tick, vi);
5038 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5042 cxgbe_uninit_synchronized(vi);
5051 cxgbe_uninit_synchronized(struct vi_info *vi)
5053 struct port_info *pi = vi->pi;
5054 struct adapter *sc = pi->adapter;
5055 struct ifnet *ifp = vi->ifp;
5057 struct sge_txq *txq;
5059 ASSERT_SYNCHRONIZED_OP(sc);
5061 if (!(vi->flags & VI_INIT_DONE)) {
5062 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5063 KASSERT(0, ("uninited VI is running"));
5064 if_printf(ifp, "uninited VI with running ifnet. "
5065 "vi->flags 0x%016lx, if_flags 0x%08x, "
5066 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5073 * Disable the VI so that all its data in either direction is discarded
5074 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5075 * tick) intact as the TP can deliver negative advice or data that it's
5076 * holding in its RAM (for an offloaded connection) even after the VI is
5079 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5081 if_printf(ifp, "disable_vi failed: %d\n", rc);
5085 for_each_txq(vi, i, txq) {
5087 txq->eq.flags &= ~EQ_ENABLED;
5092 if (pi->nvi > 1 || sc->flags & IS_VF)
5093 callout_stop(&vi->tick);
5095 callout_stop(&pi->tick);
5096 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5100 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5102 if (pi->up_vis > 0) {
5107 pi->link_cfg.link_ok = false;
5108 pi->link_cfg.speed = 0;
5109 pi->link_cfg.link_down_rc = 255;
5110 t4_os_link_changed(pi);
5117 * It is ok for this function to fail midway and return right away. t4_detach
5118 * will walk the entire sc->irq list and clean up whatever is valid.
5121 t4_setup_intr_handlers(struct adapter *sc)
5123 int rc, rid, p, q, v;
5126 struct port_info *pi;
5128 struct sge *sge = &sc->sge;
5129 struct sge_rxq *rxq;
5131 struct sge_ofld_rxq *ofld_rxq;
5134 struct sge_nm_rxq *nm_rxq;
5137 int nbuckets = rss_getnumbuckets();
5144 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5145 if (forwarding_intr_to_fwq(sc))
5146 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5148 /* Multiple interrupts. */
5149 if (sc->flags & IS_VF)
5150 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5151 ("%s: too few intr.", __func__));
5153 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5154 ("%s: too few intr.", __func__));
5156 /* The first one is always error intr on PFs */
5157 if (!(sc->flags & IS_VF)) {
5158 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5165 /* The second one is always the firmware event queue (first on VFs) */
5166 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5172 for_each_port(sc, p) {
5174 for_each_vi(pi, v, vi) {
5175 vi->first_intr = rid - 1;
5177 if (vi->nnmrxq > 0) {
5178 int n = max(vi->nrxq, vi->nnmrxq);
5180 rxq = &sge->rxq[vi->first_rxq];
5182 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5184 for (q = 0; q < n; q++) {
5185 snprintf(s, sizeof(s), "%x%c%x", p,
5191 irq->nm_rxq = nm_rxq++;
5193 if (irq->nm_rxq != NULL &&
5195 /* Netmap rx only */
5196 rc = t4_alloc_irq(sc, irq, rid,
5197 t4_nm_intr, irq->nm_rxq, s);
5199 if (irq->nm_rxq != NULL &&
5201 /* NIC and Netmap rx */
5202 rc = t4_alloc_irq(sc, irq, rid,
5203 t4_vi_intr, irq, s);
5206 if (irq->rxq != NULL &&
5207 irq->nm_rxq == NULL) {
5209 rc = t4_alloc_irq(sc, irq, rid,
5210 t4_intr, irq->rxq, s);
5216 bus_bind_intr(sc->dev, irq->res,
5217 rss_getcpu(q % nbuckets));
5225 for_each_rxq(vi, q, rxq) {
5226 snprintf(s, sizeof(s), "%x%c%x", p,
5228 rc = t4_alloc_irq(sc, irq, rid,
5233 bus_bind_intr(sc->dev, irq->res,
5234 rss_getcpu(q % nbuckets));
5242 for_each_ofld_rxq(vi, q, ofld_rxq) {
5243 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5244 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5255 MPASS(irq == &sc->irq[sc->intr_count]);
5261 adapter_full_init(struct adapter *sc)
5265 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5266 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5269 ASSERT_SYNCHRONIZED_OP(sc);
5270 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5271 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5272 ("%s: FULL_INIT_DONE already", __func__));
5275 * queues that belong to the adapter (not any particular port).
5277 rc = t4_setup_adapter_queues(sc);
5281 for (i = 0; i < nitems(sc->tq); i++) {
5282 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5283 taskqueue_thread_enqueue, &sc->tq[i]);
5284 if (sc->tq[i] == NULL) {
5285 device_printf(sc->dev,
5286 "failed to allocate task queue %d\n", i);
5290 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5291 device_get_nameunit(sc->dev), i);
5294 MPASS(RSS_KEYSIZE == 40);
5295 rss_getkey((void *)&raw_rss_key[0]);
5296 for (i = 0; i < nitems(rss_key); i++) {
5297 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5299 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5302 if (!(sc->flags & IS_VF))
5304 sc->flags |= FULL_INIT_DONE;
5307 adapter_full_uninit(sc);
5313 adapter_full_uninit(struct adapter *sc)
5317 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5319 t4_teardown_adapter_queues(sc);
5321 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5322 taskqueue_free(sc->tq[i]);
5326 sc->flags &= ~FULL_INIT_DONE;
5332 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5333 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5334 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5335 RSS_HASHTYPE_RSS_UDP_IPV6)
5337 /* Translates kernel hash types to hardware. */
5339 hashconfig_to_hashen(int hashconfig)
5343 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5344 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5345 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5346 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5347 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5348 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5349 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5351 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5352 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5353 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5355 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5356 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5357 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5358 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5363 /* Translates hardware hash types to kernel. */
5365 hashen_to_hashconfig(int hashen)
5369 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5371 * If UDP hashing was enabled it must have been enabled for
5372 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5373 * enabling any 4-tuple hash is nonsense configuration.
5375 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5376 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5378 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5379 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5380 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5381 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5383 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5384 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5385 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5386 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5387 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5388 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5389 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5390 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5392 return (hashconfig);
5397 vi_full_init(struct vi_info *vi)
5399 struct adapter *sc = vi->pi->adapter;
5400 struct ifnet *ifp = vi->ifp;
5402 struct sge_rxq *rxq;
5405 int nbuckets = rss_getnumbuckets();
5406 int hashconfig = rss_gethashconfig();
5410 ASSERT_SYNCHRONIZED_OP(sc);
5411 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5412 ("%s: VI_INIT_DONE already", __func__));
5414 sysctl_ctx_init(&vi->ctx);
5415 vi->flags |= VI_SYSCTL_CTX;
5418 * Allocate tx/rx/fl queues for this VI.
5420 rc = t4_setup_vi_queues(vi);
5422 goto done; /* error message displayed already */
5425 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5427 if (vi->nrxq > vi->rss_size) {
5428 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5429 "some queues will never receive traffic.\n", vi->nrxq,
5431 } else if (vi->rss_size % vi->nrxq) {
5432 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5433 "expect uneven traffic distribution.\n", vi->nrxq,
5437 if (vi->nrxq != nbuckets) {
5438 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5439 "performance will be impacted.\n", vi->nrxq, nbuckets);
5442 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5443 for (i = 0; i < vi->rss_size;) {
5445 j = rss_get_indirection_to_bucket(i);
5447 rxq = &sc->sge.rxq[vi->first_rxq + j];
5448 rss[i++] = rxq->iq.abs_id;
5450 for_each_rxq(vi, j, rxq) {
5451 rss[i++] = rxq->iq.abs_id;
5452 if (i == vi->rss_size)
5458 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5462 if_printf(ifp, "rss_config failed: %d\n", rc);
5467 vi->hashen = hashconfig_to_hashen(hashconfig);
5470 * We may have had to enable some hashes even though the global config
5471 * wants them disabled. This is a potential problem that must be
5472 * reported to the user.
5474 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5477 * If we consider only the supported hash types, then the enabled hashes
5478 * are a superset of the requested hashes. In other words, there cannot
5479 * be any supported hash that was requested but not enabled, but there
5480 * can be hashes that were not requested but had to be enabled.
5482 extra &= SUPPORTED_RSS_HASHTYPES;
5483 MPASS((extra & hashconfig) == 0);
5487 "global RSS config (0x%x) cannot be accommodated.\n",
5490 if (extra & RSS_HASHTYPE_RSS_IPV4)
5491 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5492 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5493 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5494 if (extra & RSS_HASHTYPE_RSS_IPV6)
5495 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5496 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5497 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5498 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5499 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5500 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5501 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5503 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5504 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5505 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5506 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5508 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5511 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5516 vi->flags |= VI_INIT_DONE;
5528 vi_full_uninit(struct vi_info *vi)
5530 struct port_info *pi = vi->pi;
5531 struct adapter *sc = pi->adapter;
5533 struct sge_rxq *rxq;
5534 struct sge_txq *txq;
5536 struct sge_ofld_rxq *ofld_rxq;
5538 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5539 struct sge_wrq *ofld_txq;
5542 if (vi->flags & VI_INIT_DONE) {
5544 /* Need to quiesce queues. */
5546 /* XXX: Only for the first VI? */
5547 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5548 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5550 for_each_txq(vi, i, txq) {
5551 quiesce_txq(sc, txq);
5554 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5555 for_each_ofld_txq(vi, i, ofld_txq) {
5556 quiesce_wrq(sc, ofld_txq);
5560 for_each_rxq(vi, i, rxq) {
5561 quiesce_iq(sc, &rxq->iq);
5562 quiesce_fl(sc, &rxq->fl);
5566 for_each_ofld_rxq(vi, i, ofld_rxq) {
5567 quiesce_iq(sc, &ofld_rxq->iq);
5568 quiesce_fl(sc, &ofld_rxq->fl);
5571 free(vi->rss, M_CXGBE);
5572 free(vi->nm_rss, M_CXGBE);
5575 t4_teardown_vi_queues(vi);
5576 vi->flags &= ~VI_INIT_DONE;
5582 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5584 struct sge_eq *eq = &txq->eq;
5585 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5587 (void) sc; /* unused */
5591 MPASS((eq->flags & EQ_ENABLED) == 0);
5595 /* Wait for the mp_ring to empty. */
5596 while (!mp_ring_is_idle(txq->r)) {
5597 mp_ring_check_drainage(txq->r, 0);
5598 pause("rquiesce", 1);
5601 /* Then wait for the hardware to finish. */
5602 while (spg->cidx != htobe16(eq->pidx))
5603 pause("equiesce", 1);
5605 /* Finally, wait for the driver to reclaim all descriptors. */
5606 while (eq->cidx != eq->pidx)
5607 pause("dquiesce", 1);
5611 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5618 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5620 (void) sc; /* unused */
5622 /* Synchronize with the interrupt handler */
5623 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5628 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5630 mtx_lock(&sc->sfl_lock);
5632 fl->flags |= FL_DOOMED;
5634 callout_stop(&sc->sfl_callout);
5635 mtx_unlock(&sc->sfl_lock);
5637 KASSERT((fl->flags & FL_STARVING) == 0,
5638 ("%s: still starving", __func__));
5642 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5643 driver_intr_t *handler, void *arg, char *name)
5648 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5649 RF_SHAREABLE | RF_ACTIVE);
5650 if (irq->res == NULL) {
5651 device_printf(sc->dev,
5652 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5656 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5657 NULL, handler, arg, &irq->tag);
5659 device_printf(sc->dev,
5660 "failed to setup interrupt for rid %d, name %s: %d\n",
5663 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5669 t4_free_irq(struct adapter *sc, struct irq *irq)
5672 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5674 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5676 bzero(irq, sizeof(*irq));
5682 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5685 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5686 t4_get_regs(sc, buf, regs->len);
5689 #define A_PL_INDIR_CMD 0x1f8
5691 #define S_PL_AUTOINC 31
5692 #define M_PL_AUTOINC 0x1U
5693 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5694 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5696 #define S_PL_VFID 20
5697 #define M_PL_VFID 0xffU
5698 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5699 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5702 #define M_PL_ADDR 0xfffffU
5703 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5704 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5706 #define A_PL_INDIR_DATA 0x1fc
5709 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5713 mtx_assert(&sc->reg_lock, MA_OWNED);
5714 if (sc->flags & IS_VF) {
5715 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5716 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5718 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5719 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5720 V_PL_ADDR(VF_MPS_REG(reg)));
5721 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5722 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5724 return (((uint64_t)stats[1]) << 32 | stats[0]);
5728 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5729 struct fw_vi_stats_vf *stats)
5732 #define GET_STAT(name) \
5733 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5735 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5736 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5737 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5738 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5739 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5740 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5741 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5742 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5743 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5744 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5745 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5746 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5747 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5748 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5749 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5750 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5756 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5760 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5761 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5762 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5763 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5764 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5765 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5769 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5772 const struct timeval interval = {0, 250000}; /* 250ms */
5774 if (!(vi->flags & VI_INIT_DONE))
5778 timevalsub(&tv, &interval);
5779 if (timevalcmp(&tv, &vi->last_refreshed, <))
5782 mtx_lock(&sc->reg_lock);
5783 t4_get_vi_stats(sc, vi->viid, &vi->stats);
5784 getmicrotime(&vi->last_refreshed);
5785 mtx_unlock(&sc->reg_lock);
5789 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5791 u_int i, v, tnl_cong_drops, bg_map;
5793 const struct timeval interval = {0, 250000}; /* 250ms */
5796 timevalsub(&tv, &interval);
5797 if (timevalcmp(&tv, &pi->last_refreshed, <))
5801 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5802 bg_map = pi->mps_bg_map;
5804 i = ffs(bg_map) - 1;
5805 mtx_lock(&sc->reg_lock);
5806 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5807 A_TP_MIB_TNL_CNG_DROP_0 + i);
5808 mtx_unlock(&sc->reg_lock);
5809 tnl_cong_drops += v;
5810 bg_map &= ~(1 << i);
5812 pi->tnl_cong_drops = tnl_cong_drops;
5813 getmicrotime(&pi->last_refreshed);
5817 cxgbe_tick(void *arg)
5819 struct port_info *pi = arg;
5820 struct adapter *sc = pi->adapter;
5822 PORT_LOCK_ASSERT_OWNED(pi);
5823 cxgbe_refresh_stats(sc, pi);
5825 callout_schedule(&pi->tick, hz);
5831 struct vi_info *vi = arg;
5832 struct adapter *sc = vi->pi->adapter;
5834 vi_refresh_stats(sc, vi);
5836 callout_schedule(&vi->tick, hz);
5840 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5842 static char *caps_decoder[] = {
5843 "\20\001IPMI\002NCSI", /* 0: NBM */
5844 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5845 "\20\001INGRESS\002EGRESS", /* 2: switch */
5846 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5847 "\006HASHFILTER\007ETHOFLD",
5848 "\20\001TOE", /* 4: TOE */
5849 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5850 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5851 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5852 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5854 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5855 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5856 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5857 "\004PO_INITIATOR\005PO_TARGET",
5861 t4_sysctls(struct adapter *sc)
5863 struct sysctl_ctx_list *ctx;
5864 struct sysctl_oid *oid;
5865 struct sysctl_oid_list *children, *c0;
5866 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5868 ctx = device_get_sysctl_ctx(sc->dev);
5873 oid = device_get_sysctl_tree(sc->dev);
5874 c0 = children = SYSCTL_CHILDREN(oid);
5876 sc->sc_do_rxcopy = 1;
5877 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5878 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5880 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5881 sc->params.nports, "# of ports");
5883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5884 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
5885 sysctl_bitfield_8b, "A", "available doorbells");
5887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5888 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5891 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5892 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5893 "interrupt holdoff timer values (us)");
5895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5896 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5897 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5898 "interrupt holdoff packet counter values");
5900 t4_sge_sysctls(sc, ctx, children);
5902 sc->lro_timeout = 100;
5903 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5904 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5906 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5907 &sc->debug_flags, 0, "flags to enable runtime debugging");
5909 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5910 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5912 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5913 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5915 if (sc->flags & IS_VF)
5918 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5919 NULL, chip_rev(sc), "chip hardware revision");
5921 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5922 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5924 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5925 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5927 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5928 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5930 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5931 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5933 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5934 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5936 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5937 sc->er_version, 0, "expansion ROM version");
5939 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5940 sc->bs_version, 0, "bootstrap firmware version");
5942 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5943 NULL, sc->params.scfg_vers, "serial config version");
5945 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5946 NULL, sc->params.vpd_vers, "VPD version");
5948 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5949 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5951 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5952 sc->cfcsum, "config file checksum");
5954 #define SYSCTL_CAP(name, n, text) \
5955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5956 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
5957 sysctl_bitfield_16b, "A", "available " text " capabilities")
5959 SYSCTL_CAP(nbmcaps, 0, "NBM");
5960 SYSCTL_CAP(linkcaps, 1, "link");
5961 SYSCTL_CAP(switchcaps, 2, "switch");
5962 SYSCTL_CAP(niccaps, 3, "NIC");
5963 SYSCTL_CAP(toecaps, 4, "TCP offload");
5964 SYSCTL_CAP(rdmacaps, 5, "RDMA");
5965 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5966 SYSCTL_CAP(cryptocaps, 7, "crypto");
5967 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5970 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5971 NULL, sc->tids.nftids, "number of filters");
5973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5974 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5975 "chip temperature (in Celsius)");
5977 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5978 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5979 "microprocessor load averages (debug firmwares only)");
5981 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5982 &sc->params.core_vdd, 0, "core Vdd (in mV)");
5984 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
5985 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
5986 sysctl_cpus, "A", "local CPUs");
5988 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
5989 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
5990 sysctl_cpus, "A", "preferred CPUs for interrupts");
5993 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5995 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5996 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5997 "logs and miscellaneous information");
5998 children = SYSCTL_CHILDREN(oid);
6000 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6001 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6002 sysctl_cctrl, "A", "congestion control");
6004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6005 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6006 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6008 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6009 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
6010 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6012 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6013 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
6014 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6016 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6017 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
6018 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6021 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
6022 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6025 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
6026 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6029 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6030 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
6031 "A", "CIM logic analyzer");
6033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6034 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6035 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6037 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6038 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
6039 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6042 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
6043 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6046 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
6047 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6050 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
6051 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6054 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
6055 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6058 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
6059 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6061 if (chip_id(sc) > CHELSIO_T4) {
6062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6063 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
6064 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6067 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
6068 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
6071 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6072 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6073 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6075 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6076 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6077 sysctl_cim_qcfg, "A", "CIM queue configuration");
6079 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6080 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6081 sysctl_cpl_stats, "A", "CPL statistics");
6083 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6084 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6085 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6087 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6088 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6089 sysctl_devlog, "A", "firmware's device log");
6091 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6092 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6093 sysctl_fcoe_stats, "A", "FCoE statistics");
6095 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6096 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6097 sysctl_hw_sched, "A", "hardware scheduler ");
6099 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6100 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6101 sysctl_l2t, "A", "hardware L2 table");
6103 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6104 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6105 sysctl_smt, "A", "hardware source MAC table");
6108 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6109 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6110 sysctl_clip, "A", "active CLIP table entries");
6113 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6114 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6115 sysctl_lb_stats, "A", "loopback statistics");
6117 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6118 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6119 sysctl_meminfo, "A", "memory regions");
6121 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6122 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6123 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6124 "A", "MPS TCAM entries");
6126 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6127 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6128 sysctl_path_mtus, "A", "path MTUs");
6130 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6131 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6132 sysctl_pm_stats, "A", "PM statistics");
6134 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6135 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6136 sysctl_rdma_stats, "A", "RDMA statistics");
6138 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6139 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6140 sysctl_tcp_stats, "A", "TCP statistics");
6142 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6143 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6144 sysctl_tids, "A", "TID information");
6146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6147 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6148 sysctl_tp_err_stats, "A", "TP error statistics");
6150 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6151 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
6152 "TP logic analyzer event capture mask");
6154 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6155 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6156 sysctl_tp_la, "A", "TP logic analyzer");
6158 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6159 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6160 sysctl_tx_rate, "A", "Tx rate");
6162 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6163 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6164 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6166 if (chip_id(sc) >= CHELSIO_T5) {
6167 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6168 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6169 sysctl_wcwr_stats, "A", "write combined work requests");
6173 if (is_offload(sc)) {
6180 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
6181 NULL, "TOE parameters");
6182 children = SYSCTL_CHILDREN(oid);
6184 sc->tt.cong_algorithm = -1;
6185 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6186 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6187 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6190 sc->tt.sndbuf = 256 * 1024;
6191 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6192 &sc->tt.sndbuf, 0, "max hardware send buffer size");
6195 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
6196 &sc->tt.ddp, 0, "DDP allowed");
6198 sc->tt.rx_coalesce = 1;
6199 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6200 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6203 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6204 &sc->tt.tls, 0, "Inline TLS allowed");
6206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6207 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
6208 "I", "TCP ports that use inline TLS+TOE RX");
6210 sc->tt.tx_align = 1;
6211 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6212 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6214 sc->tt.tx_zcopy = 0;
6215 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6216 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6217 "Enable zero-copy aio_write(2)");
6219 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6220 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6221 "cop_managed_offloading", CTLFLAG_RW,
6222 &sc->tt.cop_managed_offloading, 0,
6223 "COP (Connection Offload Policy) controls all TOE offload");
6225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6226 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6227 "TP timer tick (us)");
6229 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6230 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6231 "TCP timestamp tick (us)");
6233 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6234 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6237 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6238 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6239 "IU", "DACK timer (us)");
6241 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6242 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6243 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6245 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6246 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6247 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6250 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6251 sysctl_tp_timer, "LU", "Persist timer min (us)");
6253 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6254 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6255 sysctl_tp_timer, "LU", "Persist timer max (us)");
6257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6258 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6259 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6262 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6263 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6266 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6267 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6270 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6271 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6274 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6275 sysctl_tp_shift_cnt, "IU",
6276 "Number of SYN retransmissions before abort");
6278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6279 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6280 sysctl_tp_shift_cnt, "IU",
6281 "Number of retransmissions before abort");
6283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6284 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6285 sysctl_tp_shift_cnt, "IU",
6286 "Number of keepalive probes before abort");
6288 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6289 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6290 children = SYSCTL_CHILDREN(oid);
6291 for (i = 0; i < 16; i++) {
6292 snprintf(s, sizeof(s), "%u", i);
6293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6294 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6295 "IU", "TOE retransmit backoff");
6302 vi_sysctls(struct vi_info *vi)
6304 struct sysctl_ctx_list *ctx;
6305 struct sysctl_oid *oid;
6306 struct sysctl_oid_list *children;
6308 ctx = device_get_sysctl_ctx(vi->dev);
6311 * dev.v?(cxgbe|cxl).X.
6313 oid = device_get_sysctl_tree(vi->dev);
6314 children = SYSCTL_CHILDREN(oid);
6316 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6317 vi->viid, "VI identifer");
6318 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6319 &vi->nrxq, 0, "# of rx queues");
6320 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6321 &vi->ntxq, 0, "# of tx queues");
6322 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6323 &vi->first_rxq, 0, "index of first rx queue");
6324 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6325 &vi->first_txq, 0, "index of first tx queue");
6326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6327 vi->rss_base, "start of RSS indirection table");
6328 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6329 vi->rss_size, "size of RSS indirection table");
6331 if (IS_MAIN_VI(vi)) {
6332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6333 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6334 "Reserve queue 0 for non-flowid packets");
6338 if (vi->nofldrxq != 0) {
6339 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6341 "# of rx queues for offloaded TCP connections");
6342 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6343 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6344 "index of first TOE rx queue");
6345 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6346 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6347 sysctl_holdoff_tmr_idx_ofld, "I",
6348 "holdoff timer index for TOE queues");
6349 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6350 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6351 sysctl_holdoff_pktc_idx_ofld, "I",
6352 "holdoff packet counter index for TOE queues");
6355 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6356 if (vi->nofldtxq != 0) {
6357 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6359 "# of tx queues for TOE/ETHOFLD");
6360 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6361 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6362 "index of first TOE/ETHOFLD tx queue");
6366 if (vi->nnmrxq != 0) {
6367 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6368 &vi->nnmrxq, 0, "# of netmap rx queues");
6369 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6370 &vi->nnmtxq, 0, "# of netmap tx queues");
6371 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6372 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6373 "index of first netmap rx queue");
6374 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6375 CTLFLAG_RD, &vi->first_nm_txq, 0,
6376 "index of first netmap tx queue");
6380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6381 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6382 "holdoff timer index");
6383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6384 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6385 "holdoff packet counter index");
6387 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6388 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6391 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6396 cxgbe_sysctls(struct port_info *pi)
6398 struct sysctl_ctx_list *ctx;
6399 struct sysctl_oid *oid;
6400 struct sysctl_oid_list *children, *children2;
6401 struct adapter *sc = pi->adapter;
6404 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6406 ctx = device_get_sysctl_ctx(pi->dev);
6411 oid = device_get_sysctl_tree(pi->dev);
6412 children = SYSCTL_CHILDREN(oid);
6414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6415 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6416 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6417 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6418 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6419 "PHY temperature (in Celsius)");
6420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6421 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6422 "PHY firmware version");
6425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6426 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6427 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6429 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6430 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6432 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6433 "autonegotiation (-1 = not supported)");
6435 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6436 port_top_speed(pi), "max speed (in Gbps)");
6437 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6438 pi->mps_bg_map, "MPS buffer group map");
6439 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6440 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6442 if (sc->flags & IS_VF)
6446 * dev.(cxgbe|cxl).X.tc.
6448 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6449 "Tx scheduler traffic classes (cl_rl)");
6450 children2 = SYSCTL_CHILDREN(oid);
6451 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6452 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6453 "pktsize for per-flow cl-rl (0 means up to the driver )");
6454 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6455 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6456 "burstsize for per-flow cl-rl (0 means up to the driver)");
6457 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6458 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6460 snprintf(name, sizeof(name), "%d", i);
6461 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6462 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6464 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6465 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6466 sysctl_bitfield_8b, "A", "flags");
6467 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6468 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6469 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6470 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6471 sysctl_tc_params, "A", "traffic class parameters");
6475 * dev.cxgbe.X.stats.
6477 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6478 NULL, "port statistics");
6479 children = SYSCTL_CHILDREN(oid);
6480 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6481 &pi->tx_parse_error, 0,
6482 "# of tx packets with invalid length or # of segments");
6484 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6485 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6486 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6487 sysctl_handle_t4_reg64, "QU", desc)
6489 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6490 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6491 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6492 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6493 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6494 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6495 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6496 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6497 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6498 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6499 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6500 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6501 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6502 "# of tx frames in this range",
6503 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6504 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6505 "# of tx frames in this range",
6506 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6507 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6508 "# of tx frames in this range",
6509 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6510 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6511 "# of tx frames in this range",
6512 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6513 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6514 "# of tx frames in this range",
6515 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6516 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6517 "# of tx frames in this range",
6518 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6519 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6520 "# of tx frames in this range",
6521 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6522 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6523 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6524 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6525 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6526 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6527 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6528 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6529 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6530 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6531 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6532 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6533 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6534 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6536 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6538 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6540 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6543 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6544 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6545 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6546 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6547 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6548 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6549 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6550 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6551 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6552 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6553 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6554 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6555 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6556 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6557 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6558 "# of frames received with bad FCS",
6559 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6560 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6561 "# of frames received with length error",
6562 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6563 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6564 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6565 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6566 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6567 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6568 "# of rx frames in this range",
6569 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6570 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6571 "# of rx frames in this range",
6572 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6573 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6574 "# of rx frames in this range",
6575 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6576 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6577 "# of rx frames in this range",
6578 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6579 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6580 "# of rx frames in this range",
6581 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6582 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6583 "# of rx frames in this range",
6584 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6585 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6586 "# of rx frames in this range",
6587 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6588 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6590 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6592 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6594 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6596 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6598 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6600 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6601 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6602 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6603 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6604 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6605 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6607 #undef SYSCTL_ADD_T4_REG64
6609 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6610 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6611 &pi->stats.name, desc)
6613 /* We get these from port_stats and they may be stale by up to 1s */
6614 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6615 "# drops due to buffer-group 0 overflows");
6616 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6617 "# drops due to buffer-group 1 overflows");
6618 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6619 "# drops due to buffer-group 2 overflows");
6620 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6621 "# drops due to buffer-group 3 overflows");
6622 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6623 "# of buffer-group 0 truncated packets");
6624 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6625 "# of buffer-group 1 truncated packets");
6626 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6627 "# of buffer-group 2 truncated packets");
6628 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6629 "# of buffer-group 3 truncated packets");
6631 #undef SYSCTL_ADD_T4_PORTSTAT
6633 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6634 CTLFLAG_RD, &pi->tx_tls_records,
6635 "# of TLS records transmitted");
6636 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6637 CTLFLAG_RD, &pi->tx_tls_octets,
6638 "# of payload octets in transmitted TLS records");
6639 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6640 CTLFLAG_RD, &pi->rx_tls_records,
6641 "# of TLS records received");
6642 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6643 CTLFLAG_RD, &pi->rx_tls_octets,
6644 "# of payload octets in received TLS records");
6648 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6650 int rc, *i, space = 0;
6653 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6654 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6656 sbuf_printf(&sb, " ");
6657 sbuf_printf(&sb, "%d", *i);
6660 rc = sbuf_finish(&sb);
6666 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6671 rc = sysctl_wire_old_buffer(req, 0);
6675 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6679 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6680 rc = sbuf_finish(sb);
6687 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6692 rc = sysctl_wire_old_buffer(req, 0);
6696 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6700 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6701 rc = sbuf_finish(sb);
6708 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6710 struct port_info *pi = arg1;
6712 struct adapter *sc = pi->adapter;
6716 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6719 /* XXX: magic numbers */
6720 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6722 end_synchronized_op(sc, 0);
6728 rc = sysctl_handle_int(oidp, &v, 0, req);
6733 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6735 struct vi_info *vi = arg1;
6738 val = vi->rsrv_noflowq;
6739 rc = sysctl_handle_int(oidp, &val, 0, req);
6740 if (rc != 0 || req->newptr == NULL)
6743 if ((val >= 1) && (vi->ntxq > 1))
6744 vi->rsrv_noflowq = 1;
6746 vi->rsrv_noflowq = 0;
6752 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6754 struct vi_info *vi = arg1;
6755 struct adapter *sc = vi->pi->adapter;
6757 struct sge_rxq *rxq;
6762 rc = sysctl_handle_int(oidp, &idx, 0, req);
6763 if (rc != 0 || req->newptr == NULL)
6766 if (idx < 0 || idx >= SGE_NTIMERS)
6769 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6774 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6775 for_each_rxq(vi, i, rxq) {
6776 #ifdef atomic_store_rel_8
6777 atomic_store_rel_8(&rxq->iq.intr_params, v);
6779 rxq->iq.intr_params = v;
6784 end_synchronized_op(sc, LOCK_HELD);
6789 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6791 struct vi_info *vi = arg1;
6792 struct adapter *sc = vi->pi->adapter;
6797 rc = sysctl_handle_int(oidp, &idx, 0, req);
6798 if (rc != 0 || req->newptr == NULL)
6801 if (idx < -1 || idx >= SGE_NCOUNTERS)
6804 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6809 if (vi->flags & VI_INIT_DONE)
6810 rc = EBUSY; /* cannot be changed once the queues are created */
6814 end_synchronized_op(sc, LOCK_HELD);
6819 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6821 struct vi_info *vi = arg1;
6822 struct adapter *sc = vi->pi->adapter;
6825 qsize = vi->qsize_rxq;
6827 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6828 if (rc != 0 || req->newptr == NULL)
6831 if (qsize < 128 || (qsize & 7))
6834 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6839 if (vi->flags & VI_INIT_DONE)
6840 rc = EBUSY; /* cannot be changed once the queues are created */
6842 vi->qsize_rxq = qsize;
6844 end_synchronized_op(sc, LOCK_HELD);
6849 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6851 struct vi_info *vi = arg1;
6852 struct adapter *sc = vi->pi->adapter;
6855 qsize = vi->qsize_txq;
6857 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6858 if (rc != 0 || req->newptr == NULL)
6861 if (qsize < 128 || qsize > 65536)
6864 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6869 if (vi->flags & VI_INIT_DONE)
6870 rc = EBUSY; /* cannot be changed once the queues are created */
6872 vi->qsize_txq = qsize;
6874 end_synchronized_op(sc, LOCK_HELD);
6879 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6881 struct port_info *pi = arg1;
6882 struct adapter *sc = pi->adapter;
6883 struct link_config *lc = &pi->link_cfg;
6886 if (req->newptr == NULL) {
6888 static char *bits = "\20\1RX\2TX\3AUTO";
6890 rc = sysctl_wire_old_buffer(req, 0);
6894 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6899 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6900 (lc->requested_fc & PAUSE_AUTONEG), bits);
6902 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6903 PAUSE_RX | PAUSE_AUTONEG), bits);
6905 rc = sbuf_finish(sb);
6911 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6915 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6921 if (s[0] < '0' || s[0] > '9')
6922 return (EINVAL); /* not a number */
6924 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6925 return (EINVAL); /* some other bit is set too */
6927 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6932 lc->requested_fc = n;
6933 fixup_link_config(pi);
6935 rc = apply_link_config(pi);
6936 set_current_media(pi);
6938 end_synchronized_op(sc, 0);
6945 sysctl_fec(SYSCTL_HANDLER_ARGS)
6947 struct port_info *pi = arg1;
6948 struct adapter *sc = pi->adapter;
6949 struct link_config *lc = &pi->link_cfg;
6953 if (req->newptr == NULL) {
6955 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
6957 rc = sysctl_wire_old_buffer(req, 0);
6961 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6966 * Display the requested_fec when the link is down -- the actual
6967 * FEC makes sense only when the link is up.
6970 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
6971 (lc->requested_fec & FEC_AUTO), bits);
6973 sbuf_printf(sb, "%b", lc->requested_fec, bits);
6975 rc = sbuf_finish(sb);
6981 snprintf(s, sizeof(s), "%d",
6982 lc->requested_fec == FEC_AUTO ? -1 :
6983 lc->requested_fec & M_FW_PORT_CAP32_FEC);
6985 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6989 n = strtol(&s[0], NULL, 0);
6990 if (n < 0 || n & FEC_AUTO)
6993 if (n & ~M_FW_PORT_CAP32_FEC)
6994 return (EINVAL);/* some other bit is set too */
6996 return (EINVAL);/* one bit can be set at most */
6999 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7004 old = lc->requested_fec;
7006 lc->requested_fec = FEC_AUTO;
7008 lc->requested_fec = FEC_NONE;
7010 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
7015 lc->requested_fec = n;
7017 fixup_link_config(pi);
7018 if (pi->up_vis > 0) {
7019 rc = apply_link_config(pi);
7021 lc->requested_fec = old;
7022 if (rc == FW_EPROTO)
7028 end_synchronized_op(sc, 0);
7035 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7037 struct port_info *pi = arg1;
7038 struct adapter *sc = pi->adapter;
7039 struct link_config *lc = &pi->link_cfg;
7042 if (lc->supported & FW_PORT_CAP32_ANEG)
7043 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7046 rc = sysctl_handle_int(oidp, &val, 0, req);
7047 if (rc != 0 || req->newptr == NULL)
7050 val = AUTONEG_DISABLE;
7052 val = AUTONEG_ENABLE;
7056 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7061 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
7065 lc->requested_aneg = val;
7066 fixup_link_config(pi);
7068 rc = apply_link_config(pi);
7069 set_current_media(pi);
7072 end_synchronized_op(sc, 0);
7077 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7079 struct adapter *sc = arg1;
7083 val = t4_read_reg64(sc, reg);
7085 return (sysctl_handle_64(oidp, &val, 0, req));
7089 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7091 struct adapter *sc = arg1;
7093 uint32_t param, val;
7095 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7098 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7099 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7100 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7101 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7102 end_synchronized_op(sc, 0);
7106 /* unknown is returned as 0 but we display -1 in that case */
7107 t = val == 0 ? -1 : val;
7109 rc = sysctl_handle_int(oidp, &t, 0, req);
7114 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7116 struct adapter *sc = arg1;
7119 uint32_t param, val;
7121 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7124 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7125 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7126 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7127 end_synchronized_op(sc, 0);
7131 rc = sysctl_wire_old_buffer(req, 0);
7135 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7139 if (val == 0xffffffff) {
7140 /* Only debug and custom firmwares report load averages. */
7141 sbuf_printf(sb, "not available");
7143 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7144 (val >> 16) & 0xff);
7146 rc = sbuf_finish(sb);
7153 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7155 struct adapter *sc = arg1;
7158 uint16_t incr[NMTUS][NCCTRL_WIN];
7159 static const char *dec_fac[] = {
7160 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7164 rc = sysctl_wire_old_buffer(req, 0);
7168 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7172 t4_read_cong_tbl(sc, incr);
7174 for (i = 0; i < NCCTRL_WIN; ++i) {
7175 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7176 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7177 incr[5][i], incr[6][i], incr[7][i]);
7178 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7179 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7180 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7181 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7184 rc = sbuf_finish(sb);
7190 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7191 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7192 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7193 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7197 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7199 struct adapter *sc = arg1;
7201 int rc, i, n, qid = arg2;
7204 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7206 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7207 ("%s: bad qid %d\n", __func__, qid));
7209 if (qid < CIM_NUM_IBQ) {
7212 n = 4 * CIM_IBQ_SIZE;
7213 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7214 rc = t4_read_cim_ibq(sc, qid, buf, n);
7216 /* outbound queue */
7219 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7220 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7221 rc = t4_read_cim_obq(sc, qid, buf, n);
7228 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7230 rc = sysctl_wire_old_buffer(req, 0);
7234 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7240 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7241 for (i = 0, p = buf; i < n; i += 16, p += 4)
7242 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7245 rc = sbuf_finish(sb);
7253 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7255 struct adapter *sc = arg1;
7261 MPASS(chip_id(sc) <= CHELSIO_T5);
7263 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7267 rc = sysctl_wire_old_buffer(req, 0);
7271 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7275 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7278 rc = -t4_cim_read_la(sc, buf, NULL);
7282 sbuf_printf(sb, "Status Data PC%s",
7283 cfg & F_UPDBGLACAPTPCONLY ? "" :
7284 " LS0Stat LS0Addr LS0Data");
7286 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7287 if (cfg & F_UPDBGLACAPTPCONLY) {
7288 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7290 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7291 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7292 p[4] & 0xff, p[5] >> 8);
7293 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7294 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7295 p[1] & 0xf, p[2] >> 4);
7298 "\n %02x %x%07x %x%07x %08x %08x "
7300 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7301 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7306 rc = sbuf_finish(sb);
7314 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
7316 struct adapter *sc = arg1;
7322 MPASS(chip_id(sc) > CHELSIO_T5);
7324 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7328 rc = sysctl_wire_old_buffer(req, 0);
7332 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7336 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7339 rc = -t4_cim_read_la(sc, buf, NULL);
7343 sbuf_printf(sb, "Status Inst Data PC%s",
7344 cfg & F_UPDBGLACAPTPCONLY ? "" :
7345 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7347 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7348 if (cfg & F_UPDBGLACAPTPCONLY) {
7349 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7350 p[3] & 0xff, p[2], p[1], p[0]);
7351 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7352 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7353 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7354 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7355 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7356 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7359 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7360 "%08x %08x %08x %08x %08x %08x",
7361 (p[9] >> 16) & 0xff,
7362 p[9] & 0xffff, p[8] >> 16,
7363 p[8] & 0xffff, p[7] >> 16,
7364 p[7] & 0xffff, p[6] >> 16,
7365 p[2], p[1], p[0], p[5], p[4], p[3]);
7369 rc = sbuf_finish(sb);
7377 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7379 struct adapter *sc = arg1;
7385 rc = sysctl_wire_old_buffer(req, 0);
7389 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7393 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7396 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7399 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7400 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7404 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7405 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7406 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7407 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7408 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7409 (p[1] >> 2) | ((p[2] & 3) << 30),
7410 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7414 rc = sbuf_finish(sb);
7421 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7423 struct adapter *sc = arg1;
7429 rc = sysctl_wire_old_buffer(req, 0);
7433 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7437 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7440 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7443 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7444 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7445 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7446 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7447 p[4], p[3], p[2], p[1], p[0]);
7450 sbuf_printf(sb, "\n\nCntl ID Data");
7451 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7452 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7453 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7456 rc = sbuf_finish(sb);
7463 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7465 struct adapter *sc = arg1;
7468 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7469 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7470 uint16_t thres[CIM_NUM_IBQ];
7471 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7472 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7473 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7475 cim_num_obq = sc->chip_params->cim_num_obq;
7477 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7478 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7480 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7481 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7483 nq = CIM_NUM_IBQ + cim_num_obq;
7485 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7487 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7491 t4_read_cimq_cfg(sc, base, size, thres);
7493 rc = sysctl_wire_old_buffer(req, 0);
7497 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7502 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7504 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7505 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7506 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7507 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7508 G_QUEREMFLITS(p[2]) * 16);
7509 for ( ; i < nq; i++, p += 4, wr += 2)
7510 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7511 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7512 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7513 G_QUEREMFLITS(p[2]) * 16);
7515 rc = sbuf_finish(sb);
7522 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7524 struct adapter *sc = arg1;
7527 struct tp_cpl_stats stats;
7529 rc = sysctl_wire_old_buffer(req, 0);
7533 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7537 mtx_lock(&sc->reg_lock);
7538 t4_tp_get_cpl_stats(sc, &stats, 0);
7539 mtx_unlock(&sc->reg_lock);
7541 if (sc->chip_params->nchan > 2) {
7542 sbuf_printf(sb, " channel 0 channel 1"
7543 " channel 2 channel 3");
7544 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7545 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7546 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7547 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7549 sbuf_printf(sb, " channel 0 channel 1");
7550 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7551 stats.req[0], stats.req[1]);
7552 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7553 stats.rsp[0], stats.rsp[1]);
7556 rc = sbuf_finish(sb);
7563 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7565 struct adapter *sc = arg1;
7568 struct tp_usm_stats stats;
7570 rc = sysctl_wire_old_buffer(req, 0);
7574 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7578 t4_get_usm_stats(sc, &stats, 1);
7580 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7581 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7582 sbuf_printf(sb, "Drops: %u", stats.drops);
7584 rc = sbuf_finish(sb);
7590 static const char * const devlog_level_strings[] = {
7591 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7592 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7593 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7594 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7595 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7596 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7599 static const char * const devlog_facility_strings[] = {
7600 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7601 [FW_DEVLOG_FACILITY_CF] = "CF",
7602 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7603 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7604 [FW_DEVLOG_FACILITY_RES] = "RES",
7605 [FW_DEVLOG_FACILITY_HW] = "HW",
7606 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7607 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7608 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7609 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7610 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7611 [FW_DEVLOG_FACILITY_VI] = "VI",
7612 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7613 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7614 [FW_DEVLOG_FACILITY_TM] = "TM",
7615 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7616 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7617 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7618 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7619 [FW_DEVLOG_FACILITY_RI] = "RI",
7620 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7621 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7622 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7623 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7624 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7628 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
7630 int i, j, rc, nentries, first = 0;
7631 struct devlog_params *dparams = &sc->params.devlog;
7632 struct fw_devlog_e *buf, *e;
7633 uint64_t ftstamp = UINT64_MAX;
7635 if (dparams->addr == 0)
7638 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7639 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
7643 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7647 nentries = dparams->size / sizeof(struct fw_devlog_e);
7648 for (i = 0; i < nentries; i++) {
7651 if (e->timestamp == 0)
7654 e->timestamp = be64toh(e->timestamp);
7655 e->seqno = be32toh(e->seqno);
7656 for (j = 0; j < 8; j++)
7657 e->params[j] = be32toh(e->params[j]);
7659 if (e->timestamp < ftstamp) {
7660 ftstamp = e->timestamp;
7665 if (buf[first].timestamp == 0)
7666 goto done; /* nothing in the log */
7668 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7669 "Seq#", "Tstamp", "Level", "Facility", "Message");
7674 if (e->timestamp == 0)
7677 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7678 e->seqno, e->timestamp,
7679 (e->level < nitems(devlog_level_strings) ?
7680 devlog_level_strings[e->level] : "UNKNOWN"),
7681 (e->facility < nitems(devlog_facility_strings) ?
7682 devlog_facility_strings[e->facility] : "UNKNOWN"));
7683 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7684 e->params[2], e->params[3], e->params[4],
7685 e->params[5], e->params[6], e->params[7]);
7687 if (++i == nentries)
7689 } while (i != first);
7696 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7698 struct adapter *sc = arg1;
7702 rc = sysctl_wire_old_buffer(req, 0);
7705 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7709 rc = sbuf_devlog(sc, sb, M_WAITOK);
7711 rc = sbuf_finish(sb);
7717 t4_os_dump_devlog(struct adapter *sc)
7722 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7724 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
7726 rc = sbuf_finish(&sb);
7728 log(LOG_DEBUG, "%s: device log follows.\n%s",
7729 device_get_nameunit(sc->dev), sbuf_data(&sb));
7736 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7738 struct adapter *sc = arg1;
7741 struct tp_fcoe_stats stats[MAX_NCHAN];
7742 int i, nchan = sc->chip_params->nchan;
7744 rc = sysctl_wire_old_buffer(req, 0);
7748 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7752 for (i = 0; i < nchan; i++)
7753 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7756 sbuf_printf(sb, " channel 0 channel 1"
7757 " channel 2 channel 3");
7758 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7759 stats[0].octets_ddp, stats[1].octets_ddp,
7760 stats[2].octets_ddp, stats[3].octets_ddp);
7761 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7762 stats[0].frames_ddp, stats[1].frames_ddp,
7763 stats[2].frames_ddp, stats[3].frames_ddp);
7764 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7765 stats[0].frames_drop, stats[1].frames_drop,
7766 stats[2].frames_drop, stats[3].frames_drop);
7768 sbuf_printf(sb, " channel 0 channel 1");
7769 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7770 stats[0].octets_ddp, stats[1].octets_ddp);
7771 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7772 stats[0].frames_ddp, stats[1].frames_ddp);
7773 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7774 stats[0].frames_drop, stats[1].frames_drop);
7777 rc = sbuf_finish(sb);
7784 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7786 struct adapter *sc = arg1;
7789 unsigned int map, kbps, ipg, mode;
7790 unsigned int pace_tab[NTX_SCHED];
7792 rc = sysctl_wire_old_buffer(req, 0);
7796 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7800 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7801 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7802 t4_read_pace_tbl(sc, pace_tab);
7804 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
7805 "Class IPG (0.1 ns) Flow IPG (us)");
7807 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7808 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7809 sbuf_printf(sb, "\n %u %-5s %u ", i,
7810 (mode & (1 << i)) ? "flow" : "class", map & 3);
7812 sbuf_printf(sb, "%9u ", kbps);
7814 sbuf_printf(sb, " disabled ");
7817 sbuf_printf(sb, "%13u ", ipg);
7819 sbuf_printf(sb, " disabled ");
7822 sbuf_printf(sb, "%10u", pace_tab[i]);
7824 sbuf_printf(sb, " disabled");
7827 rc = sbuf_finish(sb);
7834 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7836 struct adapter *sc = arg1;
7840 struct lb_port_stats s[2];
7841 static const char *stat_name[] = {
7842 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7843 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7844 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7845 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7846 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7847 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7848 "BG2FramesTrunc:", "BG3FramesTrunc:"
7851 rc = sysctl_wire_old_buffer(req, 0);
7855 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7859 memset(s, 0, sizeof(s));
7861 for (i = 0; i < sc->chip_params->nchan; i += 2) {
7862 t4_get_lb_stats(sc, i, &s[0]);
7863 t4_get_lb_stats(sc, i + 1, &s[1]);
7867 sbuf_printf(sb, "%s Loopback %u"
7868 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7870 for (j = 0; j < nitems(stat_name); j++)
7871 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7875 rc = sbuf_finish(sb);
7882 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7885 struct port_info *pi = arg1;
7886 struct link_config *lc = &pi->link_cfg;
7889 rc = sysctl_wire_old_buffer(req, 0);
7892 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7896 if (lc->link_ok || lc->link_down_rc == 255)
7897 sbuf_printf(sb, "n/a");
7899 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7901 rc = sbuf_finish(sb);
7914 mem_desc_cmp(const void *a, const void *b)
7916 return ((const struct mem_desc *)a)->base -
7917 ((const struct mem_desc *)b)->base;
7921 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7929 size = to - from + 1;
7933 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7934 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7938 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7940 struct adapter *sc = arg1;
7943 uint32_t lo, hi, used, alloc;
7944 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7945 static const char *region[] = {
7946 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7947 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7948 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7949 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7950 "RQUDP region:", "PBL region:", "TXPBL region:",
7951 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7952 "On-chip queues:", "TLS keys:",
7954 struct mem_desc avail[4];
7955 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
7956 struct mem_desc *md = mem;
7958 rc = sysctl_wire_old_buffer(req, 0);
7962 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7966 for (i = 0; i < nitems(mem); i++) {
7971 /* Find and sort the populated memory ranges */
7973 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7974 if (lo & F_EDRAM0_ENABLE) {
7975 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7976 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7977 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7981 if (lo & F_EDRAM1_ENABLE) {
7982 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7983 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7984 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7988 if (lo & F_EXT_MEM_ENABLE) {
7989 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7990 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7991 avail[i].limit = avail[i].base +
7992 (G_EXT_MEM_SIZE(hi) << 20);
7993 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
7996 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7997 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7998 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7999 avail[i].limit = avail[i].base +
8000 (G_EXT_MEM1_SIZE(hi) << 20);
8004 if (!i) /* no memory available */
8006 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8008 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8009 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8010 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8011 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8012 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8013 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8014 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8015 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8016 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8018 /* the next few have explicit upper bounds */
8019 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8020 md->limit = md->base - 1 +
8021 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8022 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8025 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8026 md->limit = md->base - 1 +
8027 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8028 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8031 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8032 if (chip_id(sc) <= CHELSIO_T5)
8033 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8035 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8039 md->idx = nitems(region); /* hide it */
8043 #define ulp_region(reg) \
8044 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8045 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8047 ulp_region(RX_ISCSI);
8048 ulp_region(RX_TDDP);
8050 ulp_region(RX_STAG);
8052 ulp_region(RX_RQUDP);
8058 md->idx = nitems(region);
8061 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8062 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8065 if (sge_ctrl & F_VFIFO_ENABLE)
8066 size = G_DBVFIFO_SIZE(fifo_size);
8068 size = G_T6_DBVFIFO_SIZE(fifo_size);
8071 md->base = G_BASEADDR(t4_read_reg(sc,
8072 A_SGE_DBVFIFO_BADDR));
8073 md->limit = md->base + (size << 2) - 1;
8078 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8081 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8085 md->base = sc->vres.ocq.start;
8086 if (sc->vres.ocq.size)
8087 md->limit = md->base + sc->vres.ocq.size - 1;
8089 md->idx = nitems(region); /* hide it */
8092 md->base = sc->vres.key.start;
8093 if (sc->vres.key.size)
8094 md->limit = md->base + sc->vres.key.size - 1;
8096 md->idx = nitems(region); /* hide it */
8099 /* add any address-space holes, there can be up to 3 */
8100 for (n = 0; n < i - 1; n++)
8101 if (avail[n].limit < avail[n + 1].base)
8102 (md++)->base = avail[n].limit;
8104 (md++)->base = avail[n].limit;
8107 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8109 for (lo = 0; lo < i; lo++)
8110 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8111 avail[lo].limit - 1);
8113 sbuf_printf(sb, "\n");
8114 for (i = 0; i < n; i++) {
8115 if (mem[i].idx >= nitems(region))
8116 continue; /* skip holes */
8118 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8119 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8123 sbuf_printf(sb, "\n");
8124 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8125 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8126 mem_region_show(sb, "uP RAM:", lo, hi);
8128 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8129 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8130 mem_region_show(sb, "uP Extmem2:", lo, hi);
8132 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8133 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8135 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8136 (lo & F_PMRXNUMCHN) ? 2 : 1);
8138 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8139 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8140 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8142 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8143 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8144 sbuf_printf(sb, "%u p-structs\n",
8145 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8147 for (i = 0; i < 4; i++) {
8148 if (chip_id(sc) > CHELSIO_T5)
8149 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8151 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8153 used = G_T5_USED(lo);
8154 alloc = G_T5_ALLOC(lo);
8157 alloc = G_ALLOC(lo);
8159 /* For T6 these are MAC buffer groups */
8160 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8163 for (i = 0; i < sc->chip_params->nchan; i++) {
8164 if (chip_id(sc) > CHELSIO_T5)
8165 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8167 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8169 used = G_T5_USED(lo);
8170 alloc = G_T5_ALLOC(lo);
8173 alloc = G_ALLOC(lo);
8175 /* For T6 these are MAC buffer groups */
8177 "\nLoopback %d using %u pages out of %u allocated",
8181 rc = sbuf_finish(sb);
8188 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8192 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8196 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8198 struct adapter *sc = arg1;
8202 MPASS(chip_id(sc) <= CHELSIO_T5);
8204 rc = sysctl_wire_old_buffer(req, 0);
8208 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8213 "Idx Ethernet address Mask Vld Ports PF"
8214 " VF Replication P0 P1 P2 P3 ML");
8215 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8216 uint64_t tcamx, tcamy, mask;
8217 uint32_t cls_lo, cls_hi;
8218 uint8_t addr[ETHER_ADDR_LEN];
8220 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8221 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8224 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8225 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8226 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8227 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8228 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8229 addr[3], addr[4], addr[5], (uintmax_t)mask,
8230 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8231 G_PORTMAP(cls_hi), G_PF(cls_lo),
8232 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8234 if (cls_lo & F_REPLICATE) {
8235 struct fw_ldst_cmd ldst_cmd;
8237 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8238 ldst_cmd.op_to_addrspace =
8239 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8240 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8241 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8242 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8243 ldst_cmd.u.mps.rplc.fid_idx =
8244 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8245 V_FW_LDST_CMD_IDX(i));
8247 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8251 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8252 sizeof(ldst_cmd), &ldst_cmd);
8253 end_synchronized_op(sc, 0);
8256 sbuf_printf(sb, "%36d", rc);
8259 sbuf_printf(sb, " %08x %08x %08x %08x",
8260 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8261 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8262 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8263 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8266 sbuf_printf(sb, "%36s", "");
8268 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8269 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8270 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8274 (void) sbuf_finish(sb);
8276 rc = sbuf_finish(sb);
8283 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8285 struct adapter *sc = arg1;
8289 MPASS(chip_id(sc) > CHELSIO_T5);
8291 rc = sysctl_wire_old_buffer(req, 0);
8295 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8299 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8300 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8302 " P0 P1 P2 P3 ML\n");
8304 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8305 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8307 uint64_t tcamx, tcamy, val, mask;
8308 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8309 uint8_t addr[ETHER_ADDR_LEN];
8311 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8313 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8315 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8316 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8317 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8318 tcamy = G_DMACH(val) << 32;
8319 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8320 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8321 lookup_type = G_DATALKPTYPE(data2);
8322 port_num = G_DATAPORTNUM(data2);
8323 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8324 /* Inner header VNI */
8325 vniy = ((data2 & F_DATAVIDH2) << 23) |
8326 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8327 dip_hit = data2 & F_DATADIPHIT;
8332 vlan_vld = data2 & F_DATAVIDH2;
8333 ivlan = G_VIDL(val);
8336 ctl |= V_CTLXYBITSEL(1);
8337 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8338 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8339 tcamx = G_DMACH(val) << 32;
8340 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8341 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8342 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8343 /* Inner header VNI mask */
8344 vnix = ((data2 & F_DATAVIDH2) << 23) |
8345 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8351 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8353 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8354 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8356 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8357 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8358 "%012jx %06x %06x - - %3c"
8359 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8360 addr[1], addr[2], addr[3], addr[4], addr[5],
8361 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8362 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8363 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8364 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8366 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8367 "%012jx - - ", i, addr[0], addr[1],
8368 addr[2], addr[3], addr[4], addr[5],
8372 sbuf_printf(sb, "%4u Y ", ivlan);
8374 sbuf_printf(sb, " - N ");
8376 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8377 lookup_type ? 'I' : 'O', port_num,
8378 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8379 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8380 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8384 if (cls_lo & F_T6_REPLICATE) {
8385 struct fw_ldst_cmd ldst_cmd;
8387 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8388 ldst_cmd.op_to_addrspace =
8389 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8390 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8391 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8392 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8393 ldst_cmd.u.mps.rplc.fid_idx =
8394 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8395 V_FW_LDST_CMD_IDX(i));
8397 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8401 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8402 sizeof(ldst_cmd), &ldst_cmd);
8403 end_synchronized_op(sc, 0);
8406 sbuf_printf(sb, "%72d", rc);
8409 sbuf_printf(sb, " %08x %08x %08x %08x"
8410 " %08x %08x %08x %08x",
8411 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8412 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8413 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8414 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8415 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8416 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8417 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8418 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8421 sbuf_printf(sb, "%72s", "");
8423 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8424 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8425 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8426 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8430 (void) sbuf_finish(sb);
8432 rc = sbuf_finish(sb);
8439 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8441 struct adapter *sc = arg1;
8444 uint16_t mtus[NMTUS];
8446 rc = sysctl_wire_old_buffer(req, 0);
8450 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8454 t4_read_mtu_tbl(sc, mtus, NULL);
8456 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8457 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8458 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8459 mtus[14], mtus[15]);
8461 rc = sbuf_finish(sb);
8468 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8470 struct adapter *sc = arg1;
8473 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8474 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8475 static const char *tx_stats[MAX_PM_NSTATS] = {
8476 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8477 "Tx FIFO wait", NULL, "Tx latency"
8479 static const char *rx_stats[MAX_PM_NSTATS] = {
8480 "Read:", "Write bypass:", "Write mem:", "Flush:",
8481 "Rx FIFO wait", NULL, "Rx latency"
8484 rc = sysctl_wire_old_buffer(req, 0);
8488 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8492 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8493 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8495 sbuf_printf(sb, " Tx pcmds Tx bytes");
8496 for (i = 0; i < 4; i++) {
8497 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8501 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8502 for (i = 0; i < 4; i++) {
8503 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8507 if (chip_id(sc) > CHELSIO_T5) {
8509 "\n Total wait Total occupancy");
8510 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8512 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8516 MPASS(i < nitems(tx_stats));
8519 "\n Reads Total wait");
8520 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8522 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8526 rc = sbuf_finish(sb);
8533 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8535 struct adapter *sc = arg1;
8538 struct tp_rdma_stats stats;
8540 rc = sysctl_wire_old_buffer(req, 0);
8544 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8548 mtx_lock(&sc->reg_lock);
8549 t4_tp_get_rdma_stats(sc, &stats, 0);
8550 mtx_unlock(&sc->reg_lock);
8552 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8553 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8555 rc = sbuf_finish(sb);
8562 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8564 struct adapter *sc = arg1;
8567 struct tp_tcp_stats v4, v6;
8569 rc = sysctl_wire_old_buffer(req, 0);
8573 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8577 mtx_lock(&sc->reg_lock);
8578 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8579 mtx_unlock(&sc->reg_lock);
8583 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8584 v4.tcp_out_rsts, v6.tcp_out_rsts);
8585 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8586 v4.tcp_in_segs, v6.tcp_in_segs);
8587 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8588 v4.tcp_out_segs, v6.tcp_out_segs);
8589 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8590 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8592 rc = sbuf_finish(sb);
8599 sysctl_tids(SYSCTL_HANDLER_ARGS)
8601 struct adapter *sc = arg1;
8604 struct tid_info *t = &sc->tids;
8606 rc = sysctl_wire_old_buffer(req, 0);
8610 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8615 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8620 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
8621 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
8625 sbuf_printf(sb, "TID range: ");
8626 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8629 if (chip_id(sc) <= CHELSIO_T5) {
8630 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8631 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8633 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8634 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8638 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
8639 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8641 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
8642 sbuf_printf(sb, ", in use: %u\n",
8643 atomic_load_acq_int(&t->tids_in_use));
8647 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8648 t->stid_base + t->nstids - 1, t->stids_in_use);
8652 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
8653 t->ftid_end, t->ftids_in_use);
8657 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8658 t->etid_base + t->netids - 1, t->etids_in_use);
8661 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8662 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8663 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8665 rc = sbuf_finish(sb);
8672 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8674 struct adapter *sc = arg1;
8677 struct tp_err_stats stats;
8679 rc = sysctl_wire_old_buffer(req, 0);
8683 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8687 mtx_lock(&sc->reg_lock);
8688 t4_tp_get_err_stats(sc, &stats, 0);
8689 mtx_unlock(&sc->reg_lock);
8691 if (sc->chip_params->nchan > 2) {
8692 sbuf_printf(sb, " channel 0 channel 1"
8693 " channel 2 channel 3\n");
8694 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8695 stats.mac_in_errs[0], stats.mac_in_errs[1],
8696 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8697 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8698 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8699 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8700 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8701 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8702 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8703 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8704 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8705 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8706 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8707 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8708 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8709 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8710 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8711 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8712 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8713 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8714 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8715 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8716 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8717 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8719 sbuf_printf(sb, " channel 0 channel 1\n");
8720 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8721 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8722 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8723 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8724 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8725 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8726 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8727 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8728 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8729 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8730 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8731 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8732 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8733 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8734 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8735 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8738 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8739 stats.ofld_no_neigh, stats.ofld_cong_defer);
8741 rc = sbuf_finish(sb);
8748 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8750 struct adapter *sc = arg1;
8751 struct tp_params *tpp = &sc->params.tp;
8755 mask = tpp->la_mask >> 16;
8756 rc = sysctl_handle_int(oidp, &mask, 0, req);
8757 if (rc != 0 || req->newptr == NULL)
8761 tpp->la_mask = mask << 16;
8762 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8774 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8780 uint64_t mask = (1ULL << f->width) - 1;
8781 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8782 ((uintmax_t)v >> f->start) & mask);
8784 if (line_size + len >= 79) {
8786 sbuf_printf(sb, "\n ");
8788 sbuf_printf(sb, "%s ", buf);
8789 line_size += len + 1;
8792 sbuf_printf(sb, "\n");
8795 static const struct field_desc tp_la0[] = {
8796 { "RcfOpCodeOut", 60, 4 },
8798 { "WcfState", 52, 4 },
8799 { "RcfOpcSrcOut", 50, 2 },
8800 { "CRxError", 49, 1 },
8801 { "ERxError", 48, 1 },
8802 { "SanityFailed", 47, 1 },
8803 { "SpuriousMsg", 46, 1 },
8804 { "FlushInputMsg", 45, 1 },
8805 { "FlushInputCpl", 44, 1 },
8806 { "RssUpBit", 43, 1 },
8807 { "RssFilterHit", 42, 1 },
8809 { "InitTcb", 31, 1 },
8810 { "LineNumber", 24, 7 },
8812 { "EdataOut", 22, 1 },
8814 { "CdataOut", 20, 1 },
8815 { "EreadPdu", 19, 1 },
8816 { "CreadPdu", 18, 1 },
8817 { "TunnelPkt", 17, 1 },
8818 { "RcfPeerFin", 16, 1 },
8819 { "RcfReasonOut", 12, 4 },
8820 { "TxCchannel", 10, 2 },
8821 { "RcfTxChannel", 8, 2 },
8822 { "RxEchannel", 6, 2 },
8823 { "RcfRxChannel", 5, 1 },
8824 { "RcfDataOutSrdy", 4, 1 },
8826 { "RxOoDvld", 2, 1 },
8827 { "RxCongestion", 1, 1 },
8828 { "TxCongestion", 0, 1 },
8832 static const struct field_desc tp_la1[] = {
8833 { "CplCmdIn", 56, 8 },
8834 { "CplCmdOut", 48, 8 },
8835 { "ESynOut", 47, 1 },
8836 { "EAckOut", 46, 1 },
8837 { "EFinOut", 45, 1 },
8838 { "ERstOut", 44, 1 },
8843 { "DataIn", 39, 1 },
8844 { "DataInVld", 38, 1 },
8846 { "RxBufEmpty", 36, 1 },
8848 { "RxFbCongestion", 34, 1 },
8849 { "TxFbCongestion", 33, 1 },
8850 { "TxPktSumSrdy", 32, 1 },
8851 { "RcfUlpType", 28, 4 },
8853 { "Ebypass", 26, 1 },
8855 { "Static0", 24, 1 },
8857 { "Cbypass", 22, 1 },
8859 { "CPktOut", 20, 1 },
8860 { "RxPagePoolFull", 18, 2 },
8861 { "RxLpbkPkt", 17, 1 },
8862 { "TxLpbkPkt", 16, 1 },
8863 { "RxVfValid", 15, 1 },
8864 { "SynLearned", 14, 1 },
8865 { "SetDelEntry", 13, 1 },
8866 { "SetInvEntry", 12, 1 },
8867 { "CpcmdDvld", 11, 1 },
8868 { "CpcmdSave", 10, 1 },
8869 { "RxPstructsFull", 8, 2 },
8870 { "EpcmdDvld", 7, 1 },
8871 { "EpcmdFlush", 6, 1 },
8872 { "EpcmdTrimPrefix", 5, 1 },
8873 { "EpcmdTrimPostfix", 4, 1 },
8874 { "ERssIp4Pkt", 3, 1 },
8875 { "ERssIp6Pkt", 2, 1 },
8876 { "ERssTcpUdpPkt", 1, 1 },
8877 { "ERssFceFipPkt", 0, 1 },
8881 static const struct field_desc tp_la2[] = {
8882 { "CplCmdIn", 56, 8 },
8883 { "MpsVfVld", 55, 1 },
8890 { "DataIn", 39, 1 },
8891 { "DataInVld", 38, 1 },
8893 { "RxBufEmpty", 36, 1 },
8895 { "RxFbCongestion", 34, 1 },
8896 { "TxFbCongestion", 33, 1 },
8897 { "TxPktSumSrdy", 32, 1 },
8898 { "RcfUlpType", 28, 4 },
8900 { "Ebypass", 26, 1 },
8902 { "Static0", 24, 1 },
8904 { "Cbypass", 22, 1 },
8906 { "CPktOut", 20, 1 },
8907 { "RxPagePoolFull", 18, 2 },
8908 { "RxLpbkPkt", 17, 1 },
8909 { "TxLpbkPkt", 16, 1 },
8910 { "RxVfValid", 15, 1 },
8911 { "SynLearned", 14, 1 },
8912 { "SetDelEntry", 13, 1 },
8913 { "SetInvEntry", 12, 1 },
8914 { "CpcmdDvld", 11, 1 },
8915 { "CpcmdSave", 10, 1 },
8916 { "RxPstructsFull", 8, 2 },
8917 { "EpcmdDvld", 7, 1 },
8918 { "EpcmdFlush", 6, 1 },
8919 { "EpcmdTrimPrefix", 5, 1 },
8920 { "EpcmdTrimPostfix", 4, 1 },
8921 { "ERssIp4Pkt", 3, 1 },
8922 { "ERssIp6Pkt", 2, 1 },
8923 { "ERssTcpUdpPkt", 1, 1 },
8924 { "ERssFceFipPkt", 0, 1 },
8929 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8932 field_desc_show(sb, *p, tp_la0);
8936 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8940 sbuf_printf(sb, "\n");
8941 field_desc_show(sb, p[0], tp_la0);
8942 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8943 field_desc_show(sb, p[1], tp_la0);
8947 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8951 sbuf_printf(sb, "\n");
8952 field_desc_show(sb, p[0], tp_la0);
8953 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8954 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8958 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8960 struct adapter *sc = arg1;
8965 void (*show_func)(struct sbuf *, uint64_t *, int);
8967 rc = sysctl_wire_old_buffer(req, 0);
8971 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8975 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8977 t4_tp_read_la(sc, buf, NULL);
8980 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8983 show_func = tp_la_show2;
8987 show_func = tp_la_show3;
8991 show_func = tp_la_show;
8994 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8995 (*show_func)(sb, p, i);
8997 rc = sbuf_finish(sb);
9004 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9006 struct adapter *sc = arg1;
9009 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9011 rc = sysctl_wire_old_buffer(req, 0);
9015 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9019 t4_get_chan_txrate(sc, nrate, orate);
9021 if (sc->chip_params->nchan > 2) {
9022 sbuf_printf(sb, " channel 0 channel 1"
9023 " channel 2 channel 3\n");
9024 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9025 nrate[0], nrate[1], nrate[2], nrate[3]);
9026 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9027 orate[0], orate[1], orate[2], orate[3]);
9029 sbuf_printf(sb, " channel 0 channel 1\n");
9030 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9031 nrate[0], nrate[1]);
9032 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9033 orate[0], orate[1]);
9036 rc = sbuf_finish(sb);
9043 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9045 struct adapter *sc = arg1;
9050 rc = sysctl_wire_old_buffer(req, 0);
9054 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9058 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9061 t4_ulprx_read_la(sc, buf);
9064 sbuf_printf(sb, " Pcmd Type Message"
9066 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9067 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9068 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9071 rc = sbuf_finish(sb);
9078 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9080 struct adapter *sc = arg1;
9084 MPASS(chip_id(sc) >= CHELSIO_T5);
9086 rc = sysctl_wire_old_buffer(req, 0);
9090 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9094 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9095 if (G_STATSOURCE_T5(v) == 7) {
9098 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9100 sbuf_printf(sb, "total %d, incomplete %d",
9101 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9102 t4_read_reg(sc, A_SGE_STAT_MATCH));
9103 } else if (mode == 1) {
9104 sbuf_printf(sb, "total %d, data overflow %d",
9105 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9106 t4_read_reg(sc, A_SGE_STAT_MATCH));
9108 sbuf_printf(sb, "unknown mode %d", mode);
9111 rc = sbuf_finish(sb);
9118 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9120 struct adapter *sc = arg1;
9121 enum cpu_sets op = arg2;
9126 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9129 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9133 rc = sysctl_wire_old_buffer(req, 0);
9137 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9142 sbuf_printf(sb, "%d ", i);
9143 rc = sbuf_finish(sb);
9151 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9153 struct adapter *sc = arg1;
9154 int *old_ports, *new_ports;
9155 int i, new_count, rc;
9157 if (req->newptr == NULL && req->oldptr == NULL)
9158 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9159 sizeof(sc->tt.tls_rx_ports[0])));
9161 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9165 if (sc->tt.num_tls_rx_ports == 0) {
9167 rc = SYSCTL_OUT(req, &i, sizeof(i));
9169 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9170 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9171 if (rc == 0 && req->newptr != NULL) {
9172 new_count = req->newlen / sizeof(new_ports[0]);
9173 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9175 rc = SYSCTL_IN(req, new_ports, new_count *
9176 sizeof(new_ports[0]));
9180 /* Allow setting to a single '-1' to clear the list. */
9181 if (new_count == 1 && new_ports[0] == -1) {
9183 old_ports = sc->tt.tls_rx_ports;
9184 sc->tt.tls_rx_ports = NULL;
9185 sc->tt.num_tls_rx_ports = 0;
9187 free(old_ports, M_CXGBE);
9189 for (i = 0; i < new_count; i++) {
9190 if (new_ports[i] < 1 ||
9191 new_ports[i] > IPPORT_MAX) {
9198 old_ports = sc->tt.tls_rx_ports;
9199 sc->tt.tls_rx_ports = new_ports;
9200 sc->tt.num_tls_rx_ports = new_count;
9202 free(old_ports, M_CXGBE);
9206 free(new_ports, M_CXGBE);
9208 end_synchronized_op(sc, 0);
9213 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9215 u_int rem = val % factor;
9218 snprintf(buf, len, "%u", val / factor);
9220 while (rem % 10 == 0)
9222 snprintf(buf, len, "%u.%u", val / factor, rem);
9227 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9229 struct adapter *sc = arg1;
9232 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9234 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9238 re = G_TIMERRESOLUTION(res);
9241 /* TCP timestamp tick */
9242 re = G_TIMESTAMPRESOLUTION(res);
9246 re = G_DELAYEDACKRESOLUTION(res);
9252 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9254 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9258 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9260 struct adapter *sc = arg1;
9261 u_int res, dack_re, v;
9262 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9264 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9265 dack_re = G_DELAYEDACKRESOLUTION(res);
9266 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9268 return (sysctl_handle_int(oidp, &v, 0, req));
9272 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9274 struct adapter *sc = arg1;
9277 u_long tp_tick_us, v;
9278 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9280 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9281 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9282 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9283 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9285 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9286 tp_tick_us = (cclk_ps << tre) / 1000000;
9288 if (reg == A_TP_INIT_SRTT)
9289 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9291 v = tp_tick_us * t4_read_reg(sc, reg);
9293 return (sysctl_handle_long(oidp, &v, 0, req));
9297 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9298 * passed to this function.
9301 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9303 struct adapter *sc = arg1;
9307 MPASS(idx >= 0 && idx <= 24);
9309 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9311 return (sysctl_handle_int(oidp, &v, 0, req));
9315 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9317 struct adapter *sc = arg1;
9321 MPASS(idx >= 0 && idx < 16);
9323 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9324 shift = (idx & 3) << 3;
9325 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9327 return (sysctl_handle_int(oidp, &v, 0, req));
9331 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9333 struct vi_info *vi = arg1;
9334 struct adapter *sc = vi->pi->adapter;
9336 struct sge_ofld_rxq *ofld_rxq;
9339 idx = vi->ofld_tmr_idx;
9341 rc = sysctl_handle_int(oidp, &idx, 0, req);
9342 if (rc != 0 || req->newptr == NULL)
9345 if (idx < 0 || idx >= SGE_NTIMERS)
9348 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9353 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9354 for_each_ofld_rxq(vi, i, ofld_rxq) {
9355 #ifdef atomic_store_rel_8
9356 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9358 ofld_rxq->iq.intr_params = v;
9361 vi->ofld_tmr_idx = idx;
9363 end_synchronized_op(sc, LOCK_HELD);
9368 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9370 struct vi_info *vi = arg1;
9371 struct adapter *sc = vi->pi->adapter;
9374 idx = vi->ofld_pktc_idx;
9376 rc = sysctl_handle_int(oidp, &idx, 0, req);
9377 if (rc != 0 || req->newptr == NULL)
9380 if (idx < -1 || idx >= SGE_NCOUNTERS)
9383 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9388 if (vi->flags & VI_INIT_DONE)
9389 rc = EBUSY; /* cannot be changed once the queues are created */
9391 vi->ofld_pktc_idx = idx;
9393 end_synchronized_op(sc, LOCK_HELD);
9399 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9403 if (cntxt->cid > M_CTXTQID)
9406 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9407 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9410 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9414 if (sc->flags & FW_OK) {
9415 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9422 * Read via firmware failed or wasn't even attempted. Read directly via
9425 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9427 end_synchronized_op(sc, 0);
9432 load_fw(struct adapter *sc, struct t4_data *fw)
9437 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9442 * The firmware, with the sole exception of the memory parity error
9443 * handler, runs from memory and not flash. It is almost always safe to
9444 * install a new firmware on a running system. Just set bit 1 in
9445 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9447 if (sc->flags & FULL_INIT_DONE &&
9448 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9453 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9454 if (fw_data == NULL) {
9459 rc = copyin(fw->data, fw_data, fw->len);
9461 rc = -t4_load_fw(sc, fw_data, fw->len);
9463 free(fw_data, M_CXGBE);
9465 end_synchronized_op(sc, 0);
9470 load_cfg(struct adapter *sc, struct t4_data *cfg)
9473 uint8_t *cfg_data = NULL;
9475 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9479 if (cfg->len == 0) {
9481 rc = -t4_load_cfg(sc, NULL, 0);
9485 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9486 if (cfg_data == NULL) {
9491 rc = copyin(cfg->data, cfg_data, cfg->len);
9493 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9495 free(cfg_data, M_CXGBE);
9497 end_synchronized_op(sc, 0);
9502 load_boot(struct adapter *sc, struct t4_bootrom *br)
9505 uint8_t *br_data = NULL;
9508 if (br->len > 1024 * 1024)
9511 if (br->pf_offset == 0) {
9513 if (br->pfidx_addr > 7)
9515 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9516 A_PCIE_PF_EXPROM_OFST)));
9517 } else if (br->pf_offset == 1) {
9519 offset = G_OFFSET(br->pfidx_addr);
9524 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9530 rc = -t4_load_boot(sc, NULL, offset, 0);
9534 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9535 if (br_data == NULL) {
9540 rc = copyin(br->data, br_data, br->len);
9542 rc = -t4_load_boot(sc, br_data, offset, br->len);
9544 free(br_data, M_CXGBE);
9546 end_synchronized_op(sc, 0);
9551 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9554 uint8_t *bc_data = NULL;
9556 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9562 rc = -t4_load_bootcfg(sc, NULL, 0);
9566 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9567 if (bc_data == NULL) {
9572 rc = copyin(bc->data, bc_data, bc->len);
9574 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9576 free(bc_data, M_CXGBE);
9578 end_synchronized_op(sc, 0);
9583 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9586 struct cudbg_init *cudbg;
9589 /* buf is large, don't block if no memory is available */
9590 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9594 handle = cudbg_alloc_handle();
9595 if (handle == NULL) {
9600 cudbg = cudbg_get_init(handle);
9602 cudbg->print = (cudbg_print_cb)printf;
9605 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9606 __func__, dump->wr_flash, dump->len, dump->data);
9610 cudbg->use_flash = 1;
9611 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9612 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9614 rc = cudbg_collect(handle, buf, &dump->len);
9618 rc = copyout(buf, dump->data, dump->len);
9620 cudbg_free_handle(handle);
9626 free_offload_policy(struct t4_offload_policy *op)
9628 struct offload_rule *r;
9635 for (i = 0; i < op->nrules; i++, r++) {
9636 free(r->bpf_prog.bf_insns, M_CXGBE);
9638 free(op->rule, M_CXGBE);
9643 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9646 struct t4_offload_policy *op, *old;
9647 struct bpf_program *bf;
9648 const struct offload_settings *s;
9649 struct offload_rule *r;
9652 if (!is_offload(sc))
9655 if (uop->nrules == 0) {
9656 /* Delete installed policies. */
9659 } if (uop->nrules > 256) { /* arbitrary */
9663 /* Copy userspace offload policy to kernel */
9664 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9665 op->nrules = uop->nrules;
9666 len = op->nrules * sizeof(struct offload_rule);
9667 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9668 rc = copyin(uop->rule, op->rule, len);
9670 free(op->rule, M_CXGBE);
9676 for (i = 0; i < op->nrules; i++, r++) {
9678 /* Validate open_type */
9679 if (r->open_type != OPEN_TYPE_LISTEN &&
9680 r->open_type != OPEN_TYPE_ACTIVE &&
9681 r->open_type != OPEN_TYPE_PASSIVE &&
9682 r->open_type != OPEN_TYPE_DONTCARE) {
9685 * Rules 0 to i have malloc'd filters that need to be
9686 * freed. Rules i+1 to nrules have userspace pointers
9687 * and should be left alone.
9690 free_offload_policy(op);
9694 /* Validate settings */
9696 if ((s->offload != 0 && s->offload != 1) ||
9697 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9698 s->sched_class < -1 ||
9699 s->sched_class >= sc->chip_params->nsched_cls) {
9705 u = bf->bf_insns; /* userspace ptr */
9706 bf->bf_insns = NULL;
9707 if (bf->bf_len == 0) {
9708 /* legal, matches everything */
9711 len = bf->bf_len * sizeof(*bf->bf_insns);
9712 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9713 rc = copyin(u, bf->bf_insns, len);
9717 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9723 rw_wlock(&sc->policy_lock);
9726 rw_wunlock(&sc->policy_lock);
9727 free_offload_policy(old);
9732 #define MAX_READ_BUF_SIZE (128 * 1024)
9734 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9736 uint32_t addr, remaining, n;
9741 rc = validate_mem_range(sc, mr->addr, mr->len);
9745 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9747 remaining = mr->len;
9748 dst = (void *)mr->data;
9751 n = min(remaining, MAX_READ_BUF_SIZE);
9752 read_via_memwin(sc, 2, addr, buf, n);
9754 rc = copyout(buf, dst, n);
9766 #undef MAX_READ_BUF_SIZE
9769 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9773 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9776 if (i2cd->len > sizeof(i2cd->data))
9779 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9782 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9783 i2cd->offset, i2cd->len, &i2cd->data[0]);
9784 end_synchronized_op(sc, 0);
9790 t4_os_find_pci_capability(struct adapter *sc, int cap)
9794 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9798 t4_os_pci_save_state(struct adapter *sc)
9801 struct pci_devinfo *dinfo;
9804 dinfo = device_get_ivars(dev);
9806 pci_cfg_save(dev, dinfo, 0);
9811 t4_os_pci_restore_state(struct adapter *sc)
9814 struct pci_devinfo *dinfo;
9817 dinfo = device_get_ivars(dev);
9819 pci_cfg_restore(dev, dinfo);
9824 t4_os_portmod_changed(struct port_info *pi)
9826 struct adapter *sc = pi->adapter;
9829 static const char *mod_str[] = {
9830 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9833 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
9834 ("%s: port_type %u", __func__, pi->port_type));
9837 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9839 build_medialist(pi);
9840 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
9841 fixup_link_config(pi);
9842 apply_link_config(pi);
9845 end_synchronized_op(sc, LOCK_HELD);
9849 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9850 if_printf(ifp, "transceiver unplugged.\n");
9851 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9852 if_printf(ifp, "unknown transceiver inserted.\n");
9853 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9854 if_printf(ifp, "unsupported transceiver inserted.\n");
9855 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9856 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9857 port_top_speed(pi), mod_str[pi->mod_type]);
9859 if_printf(ifp, "transceiver (type %d) inserted.\n",
9865 t4_os_link_changed(struct port_info *pi)
9869 struct link_config *lc;
9872 PORT_LOCK_ASSERT_OWNED(pi);
9874 for_each_vi(pi, v, vi) {
9881 ifp->if_baudrate = IF_Mbps(lc->speed);
9882 if_link_state_change(ifp, LINK_STATE_UP);
9884 if_link_state_change(ifp, LINK_STATE_DOWN);
9890 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9894 sx_slock(&t4_list_lock);
9895 SLIST_FOREACH(sc, &t4_list, link) {
9897 * func should not make any assumptions about what state sc is
9898 * in - the only guarantee is that sc->sc_lock is a valid lock.
9902 sx_sunlock(&t4_list_lock);
9906 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9910 struct adapter *sc = dev->si_drv1;
9912 rc = priv_check(td, PRIV_DRIVER);
9917 case CHELSIO_T4_GETREG: {
9918 struct t4_reg *edata = (struct t4_reg *)data;
9920 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9923 if (edata->size == 4)
9924 edata->val = t4_read_reg(sc, edata->addr);
9925 else if (edata->size == 8)
9926 edata->val = t4_read_reg64(sc, edata->addr);
9932 case CHELSIO_T4_SETREG: {
9933 struct t4_reg *edata = (struct t4_reg *)data;
9935 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9938 if (edata->size == 4) {
9939 if (edata->val & 0xffffffff00000000)
9941 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9942 } else if (edata->size == 8)
9943 t4_write_reg64(sc, edata->addr, edata->val);
9948 case CHELSIO_T4_REGDUMP: {
9949 struct t4_regdump *regs = (struct t4_regdump *)data;
9950 int reglen = t4_get_regs_len(sc);
9953 if (regs->len < reglen) {
9954 regs->len = reglen; /* hint to the caller */
9959 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9960 get_regs(sc, regs, buf);
9961 rc = copyout(buf, regs->data, reglen);
9965 case CHELSIO_T4_GET_FILTER_MODE:
9966 rc = get_filter_mode(sc, (uint32_t *)data);
9968 case CHELSIO_T4_SET_FILTER_MODE:
9969 rc = set_filter_mode(sc, *(uint32_t *)data);
9971 case CHELSIO_T4_GET_FILTER:
9972 rc = get_filter(sc, (struct t4_filter *)data);
9974 case CHELSIO_T4_SET_FILTER:
9975 rc = set_filter(sc, (struct t4_filter *)data);
9977 case CHELSIO_T4_DEL_FILTER:
9978 rc = del_filter(sc, (struct t4_filter *)data);
9980 case CHELSIO_T4_GET_SGE_CONTEXT:
9981 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9983 case CHELSIO_T4_LOAD_FW:
9984 rc = load_fw(sc, (struct t4_data *)data);
9986 case CHELSIO_T4_GET_MEM:
9987 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9989 case CHELSIO_T4_GET_I2C:
9990 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9992 case CHELSIO_T4_CLEAR_STATS: {
9994 u_int port_id = *(uint32_t *)data;
9995 struct port_info *pi;
9998 if (port_id >= sc->params.nports)
10000 pi = sc->port[port_id];
10005 t4_clr_port_stats(sc, pi->tx_chan);
10006 pi->tx_parse_error = 0;
10007 pi->tnl_cong_drops = 0;
10008 mtx_lock(&sc->reg_lock);
10009 for_each_vi(pi, v, vi) {
10010 if (vi->flags & VI_INIT_DONE)
10011 t4_clr_vi_stats(sc, vi->viid);
10013 bg_map = pi->mps_bg_map;
10016 i = ffs(bg_map) - 1;
10017 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10018 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10019 bg_map &= ~(1 << i);
10021 mtx_unlock(&sc->reg_lock);
10024 * Since this command accepts a port, clear stats for
10025 * all VIs on this port.
10027 for_each_vi(pi, v, vi) {
10028 if (vi->flags & VI_INIT_DONE) {
10029 struct sge_rxq *rxq;
10030 struct sge_txq *txq;
10031 struct sge_wrq *wrq;
10033 for_each_rxq(vi, i, rxq) {
10034 #if defined(INET) || defined(INET6)
10035 rxq->lro.lro_queued = 0;
10036 rxq->lro.lro_flushed = 0;
10039 rxq->vlan_extraction = 0;
10042 for_each_txq(vi, i, txq) {
10045 txq->vlan_insertion = 0;
10048 txq->txpkt_wrs = 0;
10049 txq->txpkts0_wrs = 0;
10050 txq->txpkts1_wrs = 0;
10051 txq->txpkts0_pkts = 0;
10052 txq->txpkts1_pkts = 0;
10054 mp_ring_reset_stats(txq->r);
10057 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10058 /* nothing to clear for each ofld_rxq */
10060 for_each_ofld_txq(vi, i, wrq) {
10061 wrq->tx_wrs_direct = 0;
10062 wrq->tx_wrs_copied = 0;
10066 if (IS_MAIN_VI(vi)) {
10067 wrq = &sc->sge.ctrlq[pi->port_id];
10068 wrq->tx_wrs_direct = 0;
10069 wrq->tx_wrs_copied = 0;
10075 case CHELSIO_T4_SCHED_CLASS:
10076 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10078 case CHELSIO_T4_SCHED_QUEUE:
10079 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10081 case CHELSIO_T4_GET_TRACER:
10082 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10084 case CHELSIO_T4_SET_TRACER:
10085 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10087 case CHELSIO_T4_LOAD_CFG:
10088 rc = load_cfg(sc, (struct t4_data *)data);
10090 case CHELSIO_T4_LOAD_BOOT:
10091 rc = load_boot(sc, (struct t4_bootrom *)data);
10093 case CHELSIO_T4_LOAD_BOOTCFG:
10094 rc = load_bootcfg(sc, (struct t4_data *)data);
10096 case CHELSIO_T4_CUDBG_DUMP:
10097 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10099 case CHELSIO_T4_SET_OFLD_POLICY:
10100 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10111 toe_capability(struct vi_info *vi, int enable)
10114 struct port_info *pi = vi->pi;
10115 struct adapter *sc = pi->adapter;
10117 ASSERT_SYNCHRONIZED_OP(sc);
10119 if (!is_offload(sc))
10123 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10124 /* TOE is already enabled. */
10129 * We need the port's queues around so that we're able to send
10130 * and receive CPLs to/from the TOE even if the ifnet for this
10131 * port has never been UP'd administratively.
10133 if (!(vi->flags & VI_INIT_DONE)) {
10134 rc = vi_full_init(vi);
10138 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10139 rc = vi_full_init(&pi->vi[0]);
10144 if (isset(&sc->offload_map, pi->port_id)) {
10145 /* TOE is enabled on another VI of this port. */
10150 if (!uld_active(sc, ULD_TOM)) {
10151 rc = t4_activate_uld(sc, ULD_TOM);
10152 if (rc == EAGAIN) {
10154 "You must kldload t4_tom.ko before trying "
10155 "to enable TOE on a cxgbe interface.\n");
10159 KASSERT(sc->tom_softc != NULL,
10160 ("%s: TOM activated but softc NULL", __func__));
10161 KASSERT(uld_active(sc, ULD_TOM),
10162 ("%s: TOM activated but flag not set", __func__));
10165 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10166 if (!uld_active(sc, ULD_IWARP))
10167 (void) t4_activate_uld(sc, ULD_IWARP);
10168 if (!uld_active(sc, ULD_ISCSI))
10169 (void) t4_activate_uld(sc, ULD_ISCSI);
10172 setbit(&sc->offload_map, pi->port_id);
10176 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10179 KASSERT(uld_active(sc, ULD_TOM),
10180 ("%s: TOM never initialized?", __func__));
10181 clrbit(&sc->offload_map, pi->port_id);
10188 * Add an upper layer driver to the global list.
10191 t4_register_uld(struct uld_info *ui)
10194 struct uld_info *u;
10196 sx_xlock(&t4_uld_list_lock);
10197 SLIST_FOREACH(u, &t4_uld_list, link) {
10198 if (u->uld_id == ui->uld_id) {
10204 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10207 sx_xunlock(&t4_uld_list_lock);
10212 t4_unregister_uld(struct uld_info *ui)
10215 struct uld_info *u;
10217 sx_xlock(&t4_uld_list_lock);
10219 SLIST_FOREACH(u, &t4_uld_list, link) {
10221 if (ui->refcount > 0) {
10226 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10232 sx_xunlock(&t4_uld_list_lock);
10237 t4_activate_uld(struct adapter *sc, int id)
10240 struct uld_info *ui;
10242 ASSERT_SYNCHRONIZED_OP(sc);
10244 if (id < 0 || id > ULD_MAX)
10246 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10248 sx_slock(&t4_uld_list_lock);
10250 SLIST_FOREACH(ui, &t4_uld_list, link) {
10251 if (ui->uld_id == id) {
10252 if (!(sc->flags & FULL_INIT_DONE)) {
10253 rc = adapter_full_init(sc);
10258 rc = ui->activate(sc);
10260 setbit(&sc->active_ulds, id);
10267 sx_sunlock(&t4_uld_list_lock);
10273 t4_deactivate_uld(struct adapter *sc, int id)
10276 struct uld_info *ui;
10278 ASSERT_SYNCHRONIZED_OP(sc);
10280 if (id < 0 || id > ULD_MAX)
10284 sx_slock(&t4_uld_list_lock);
10286 SLIST_FOREACH(ui, &t4_uld_list, link) {
10287 if (ui->uld_id == id) {
10288 rc = ui->deactivate(sc);
10290 clrbit(&sc->active_ulds, id);
10297 sx_sunlock(&t4_uld_list_lock);
10303 uld_active(struct adapter *sc, int uld_id)
10306 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10308 return (isset(&sc->active_ulds, uld_id));
10313 * t = ptr to tunable.
10314 * nc = number of CPUs.
10315 * c = compiled in default for that tunable.
10318 calculate_nqueues(int *t, int nc, const int c)
10324 nq = *t < 0 ? -*t : c;
10329 * Come up with reasonable defaults for some of the tunables, provided they're
10330 * not set by the user (in which case we'll use the values as is).
10333 tweak_tunables(void)
10335 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10339 t4_ntxq = rss_getnumbuckets();
10341 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10345 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10349 t4_nrxq = rss_getnumbuckets();
10351 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10355 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10357 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10358 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10359 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10362 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10363 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10365 if (t4_toecaps_allowed == -1)
10366 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10368 if (t4_rdmacaps_allowed == -1) {
10369 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10370 FW_CAPS_CONFIG_RDMA_RDMAC;
10373 if (t4_iscsicaps_allowed == -1) {
10374 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10375 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10376 FW_CAPS_CONFIG_ISCSI_T10DIF;
10379 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10380 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10382 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10383 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10385 if (t4_toecaps_allowed == -1)
10386 t4_toecaps_allowed = 0;
10388 if (t4_rdmacaps_allowed == -1)
10389 t4_rdmacaps_allowed = 0;
10391 if (t4_iscsicaps_allowed == -1)
10392 t4_iscsicaps_allowed = 0;
10396 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10397 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10400 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10401 t4_tmr_idx = TMR_IDX;
10403 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10404 t4_pktc_idx = PKTC_IDX;
10406 if (t4_qsize_txq < 128)
10407 t4_qsize_txq = 128;
10409 if (t4_qsize_rxq < 128)
10410 t4_qsize_rxq = 128;
10411 while (t4_qsize_rxq & 7)
10414 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10417 * Number of VIs to create per-port. The first VI is the "main" regular
10418 * VI for the port. The rest are additional virtual interfaces on the
10419 * same physical port. Note that the main VI does not have native
10420 * netmap support but the extra VIs do.
10422 * Limit the number of VIs per port to the number of available
10423 * MAC addresses per port.
10425 if (t4_num_vis < 1)
10427 if (t4_num_vis > nitems(vi_mac_funcs)) {
10428 t4_num_vis = nitems(vi_mac_funcs);
10429 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10432 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10433 pcie_relaxed_ordering = 1;
10434 #if defined(__i386__) || defined(__amd64__)
10435 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10436 pcie_relaxed_ordering = 0;
10443 t4_dump_tcb(struct adapter *sc, int tid)
10445 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10447 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10448 save = t4_read_reg(sc, reg);
10449 base = sc->memwin[2].mw_base;
10451 /* Dump TCB for the tid */
10452 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10453 tcb_addr += tid * TCB_SIZE;
10457 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10459 pf = V_PFNUM(sc->pf);
10460 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10462 t4_write_reg(sc, reg, win_pos | pf);
10463 t4_read_reg(sc, reg);
10465 off = tcb_addr - win_pos;
10466 for (i = 0; i < 4; i++) {
10468 for (j = 0; j < 8; j++, off += 4)
10469 buf[j] = htonl(t4_read_reg(sc, base + off));
10471 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10472 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10476 t4_write_reg(sc, reg, save);
10477 t4_read_reg(sc, reg);
10481 t4_dump_devlog(struct adapter *sc)
10483 struct devlog_params *dparams = &sc->params.devlog;
10484 struct fw_devlog_e e;
10485 int i, first, j, m, nentries, rc;
10486 uint64_t ftstamp = UINT64_MAX;
10488 if (dparams->start == 0) {
10489 db_printf("devlog params not valid\n");
10493 nentries = dparams->size / sizeof(struct fw_devlog_e);
10494 m = fwmtype_to_hwmtype(dparams->memtype);
10496 /* Find the first entry. */
10498 for (i = 0; i < nentries && !db_pager_quit; i++) {
10499 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10500 sizeof(e), (void *)&e);
10504 if (e.timestamp == 0)
10507 e.timestamp = be64toh(e.timestamp);
10508 if (e.timestamp < ftstamp) {
10509 ftstamp = e.timestamp;
10519 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10520 sizeof(e), (void *)&e);
10524 if (e.timestamp == 0)
10527 e.timestamp = be64toh(e.timestamp);
10528 e.seqno = be32toh(e.seqno);
10529 for (j = 0; j < 8; j++)
10530 e.params[j] = be32toh(e.params[j]);
10532 db_printf("%10d %15ju %8s %8s ",
10533 e.seqno, e.timestamp,
10534 (e.level < nitems(devlog_level_strings) ?
10535 devlog_level_strings[e.level] : "UNKNOWN"),
10536 (e.facility < nitems(devlog_facility_strings) ?
10537 devlog_facility_strings[e.facility] : "UNKNOWN"));
10538 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10539 e.params[3], e.params[4], e.params[5], e.params[6],
10542 if (++i == nentries)
10544 } while (i != first && !db_pager_quit);
10547 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10548 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10550 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10557 t = db_read_token();
10559 dev = device_lookup_by_name(db_tok_string);
10564 db_printf("usage: show t4 devlog <nexus>\n");
10569 db_printf("device not found\n");
10573 t4_dump_devlog(device_get_softc(dev));
10576 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10585 t = db_read_token();
10587 dev = device_lookup_by_name(db_tok_string);
10588 t = db_read_token();
10589 if (t == tNUMBER) {
10590 tid = db_tok_number;
10597 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10602 db_printf("device not found\n");
10606 db_printf("invalid tid\n");
10610 t4_dump_tcb(device_get_softc(dev), tid);
10615 * Borrowed from cesa_prep_aes_key().
10617 * NB: The crypto engine wants the words in the decryption key in reverse
10621 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10623 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10627 rijndaelKeySetupEnc(ek, enc_key, kbits);
10629 dkey += (kbits / 8) / 4;
10633 for (i = 0; i < 4; i++)
10634 *--dkey = htobe32(ek[4 * 10 + i]);
10637 for (i = 0; i < 2; i++)
10638 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10639 for (i = 0; i < 4; i++)
10640 *--dkey = htobe32(ek[4 * 12 + i]);
10643 for (i = 0; i < 4; i++)
10644 *--dkey = htobe32(ek[4 * 13 + i]);
10645 for (i = 0; i < 4; i++)
10646 *--dkey = htobe32(ek[4 * 14 + i]);
10649 MPASS(dkey == dec_key);
10652 static struct sx mlu; /* mod load unload */
10653 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10656 mod_event(module_t mod, int cmd, void *arg)
10659 static int loaded = 0;
10664 if (loaded++ == 0) {
10666 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10667 t4_filter_rpl, CPL_COOKIE_FILTER);
10668 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10669 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10670 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10671 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10672 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10673 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10674 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10675 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10676 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10677 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10678 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10680 sx_init(&t4_list_lock, "T4/T5 adapters");
10681 SLIST_INIT(&t4_list);
10683 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10684 SLIST_INIT(&t4_uld_list);
10689 t4_tracer_modload();
10697 if (--loaded == 0) {
10700 sx_slock(&t4_list_lock);
10701 if (!SLIST_EMPTY(&t4_list)) {
10703 sx_sunlock(&t4_list_lock);
10707 sx_slock(&t4_uld_list_lock);
10708 if (!SLIST_EMPTY(&t4_uld_list)) {
10710 sx_sunlock(&t4_uld_list_lock);
10711 sx_sunlock(&t4_list_lock);
10716 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10717 uprintf("%ju clusters with custom free routine "
10718 "still is use.\n", t4_sge_extfree_refs());
10719 pause("t4unload", 2 * hz);
10722 sx_sunlock(&t4_uld_list_lock);
10724 sx_sunlock(&t4_list_lock);
10726 if (t4_sge_extfree_refs() == 0) {
10727 t4_tracer_modunload();
10729 t4_clip_modunload();
10732 sx_destroy(&t4_uld_list_lock);
10734 sx_destroy(&t4_list_lock);
10735 t4_sge_modunload();
10739 loaded++; /* undo earlier decrement */
10750 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10751 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10752 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10754 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10755 MODULE_VERSION(t4nex, 1);
10756 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10758 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10759 #endif /* DEV_NETMAP */
10761 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10762 MODULE_VERSION(t5nex, 1);
10763 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10765 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10766 #endif /* DEV_NETMAP */
10768 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10769 MODULE_VERSION(t6nex, 1);
10770 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10772 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10773 #endif /* DEV_NETMAP */
10775 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10776 MODULE_VERSION(cxgbe, 1);
10778 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10779 MODULE_VERSION(cxl, 1);
10781 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10782 MODULE_VERSION(cc, 1);
10784 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10785 MODULE_VERSION(vcxgbe, 1);
10787 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10788 MODULE_VERSION(vcxl, 1);
10790 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10791 MODULE_VERSION(vcc, 1);