2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
74 #include <crypto/rijndael/rijndael.h>
77 #include <ddb/db_lex.h>
80 #include "common/common.h"
81 #include "common/t4_msg.h"
82 #include "common/t4_regs.h"
83 #include "common/t4_regs_values.h"
84 #include "cudbg/cudbg.h"
88 #include "t4_mp_ring.h"
92 /* T4 bus driver interface */
93 static int t4_probe(device_t);
94 static int t4_attach(device_t);
95 static int t4_detach(device_t);
96 static int t4_child_location_str(device_t, device_t, char *, size_t);
97 static int t4_ready(device_t);
98 static int t4_read_port_device(device_t, int, device_t *);
99 static device_method_t t4_methods[] = {
100 DEVMETHOD(device_probe, t4_probe),
101 DEVMETHOD(device_attach, t4_attach),
102 DEVMETHOD(device_detach, t4_detach),
104 DEVMETHOD(bus_child_location_str, t4_child_location_str),
106 DEVMETHOD(t4_is_main_ready, t4_ready),
107 DEVMETHOD(t4_read_port_device, t4_read_port_device),
111 static driver_t t4_driver = {
114 sizeof(struct adapter)
118 /* T4 port (cxgbe) interface */
119 static int cxgbe_probe(device_t);
120 static int cxgbe_attach(device_t);
121 static int cxgbe_detach(device_t);
122 device_method_t cxgbe_methods[] = {
123 DEVMETHOD(device_probe, cxgbe_probe),
124 DEVMETHOD(device_attach, cxgbe_attach),
125 DEVMETHOD(device_detach, cxgbe_detach),
128 static driver_t cxgbe_driver = {
131 sizeof(struct port_info)
134 /* T4 VI (vcxgbe) interface */
135 static int vcxgbe_probe(device_t);
136 static int vcxgbe_attach(device_t);
137 static int vcxgbe_detach(device_t);
138 static device_method_t vcxgbe_methods[] = {
139 DEVMETHOD(device_probe, vcxgbe_probe),
140 DEVMETHOD(device_attach, vcxgbe_attach),
141 DEVMETHOD(device_detach, vcxgbe_detach),
144 static driver_t vcxgbe_driver = {
147 sizeof(struct vi_info)
150 static d_ioctl_t t4_ioctl;
152 static struct cdevsw t4_cdevsw = {
153 .d_version = D_VERSION,
158 /* T5 bus driver interface */
159 static int t5_probe(device_t);
160 static device_method_t t5_methods[] = {
161 DEVMETHOD(device_probe, t5_probe),
162 DEVMETHOD(device_attach, t4_attach),
163 DEVMETHOD(device_detach, t4_detach),
165 DEVMETHOD(bus_child_location_str, t4_child_location_str),
167 DEVMETHOD(t4_is_main_ready, t4_ready),
168 DEVMETHOD(t4_read_port_device, t4_read_port_device),
172 static driver_t t5_driver = {
175 sizeof(struct adapter)
179 /* T5 port (cxl) interface */
180 static driver_t cxl_driver = {
183 sizeof(struct port_info)
186 /* T5 VI (vcxl) interface */
187 static driver_t vcxl_driver = {
190 sizeof(struct vi_info)
193 /* T6 bus driver interface */
194 static int t6_probe(device_t);
195 static device_method_t t6_methods[] = {
196 DEVMETHOD(device_probe, t6_probe),
197 DEVMETHOD(device_attach, t4_attach),
198 DEVMETHOD(device_detach, t4_detach),
200 DEVMETHOD(bus_child_location_str, t4_child_location_str),
202 DEVMETHOD(t4_is_main_ready, t4_ready),
203 DEVMETHOD(t4_read_port_device, t4_read_port_device),
207 static driver_t t6_driver = {
210 sizeof(struct adapter)
214 /* T6 port (cc) interface */
215 static driver_t cc_driver = {
218 sizeof(struct port_info)
221 /* T6 VI (vcc) interface */
222 static driver_t vcc_driver = {
225 sizeof(struct vi_info)
228 /* ifnet interface */
229 static void cxgbe_init(void *);
230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
231 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
232 static void cxgbe_qflush(struct ifnet *);
234 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
235 struct m_snd_tag **);
236 static int cxgbe_snd_tag_modify(struct m_snd_tag *,
237 union if_snd_tag_modify_params *);
238 static int cxgbe_snd_tag_query(struct m_snd_tag *,
239 union if_snd_tag_query_params *);
240 static void cxgbe_snd_tag_free(struct m_snd_tag *);
243 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
246 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
247 * then ADAPTER_LOCK, then t4_uld_list_lock.
249 static struct sx t4_list_lock;
250 SLIST_HEAD(, adapter) t4_list;
252 static struct sx t4_uld_list_lock;
253 SLIST_HEAD(, uld_info) t4_uld_list;
257 * Tunables. See tweak_tunables() too.
259 * Each tunable is set to a default value here if it's known at compile-time.
260 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
261 * provide a reasonable default (upto n) when the driver is loaded.
263 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
264 * T5 are under hw.cxl.
266 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
267 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
268 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
271 * Number of queues for tx and rx, NIC and offload.
275 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
276 "Number of TX queues per port");
277 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
281 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
282 "Number of RX queues per port");
283 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
286 static int t4_ntxq_vi = -NTXQ_VI;
287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
288 "Number of TX queues per VI");
291 static int t4_nrxq_vi = -NRXQ_VI;
292 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
293 "Number of RX queues per VI");
295 static int t4_rsrv_noflowq = 0;
296 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
297 0, "Reserve TX queue 0 of each VI for non-flowid packets");
299 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
301 static int t4_nofldtxq = -NOFLDTXQ;
302 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
303 "Number of offload TX queues per port");
306 static int t4_nofldrxq = -NOFLDRXQ;
307 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
308 "Number of offload RX queues per port");
310 #define NOFLDTXQ_VI 1
311 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
312 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
313 "Number of offload TX queues per VI");
315 #define NOFLDRXQ_VI 1
316 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
317 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
318 "Number of offload RX queues per VI");
320 #define TMR_IDX_OFLD 1
321 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
322 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
323 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
325 #define PKTC_IDX_OFLD (-1)
326 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
327 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
328 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
330 /* 0 means chip/fw default, non-zero number is value in microseconds */
331 static u_long t4_toe_keepalive_idle = 0;
332 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
333 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
335 /* 0 means chip/fw default, non-zero number is value in microseconds */
336 static u_long t4_toe_keepalive_interval = 0;
337 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
338 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
340 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
341 static int t4_toe_keepalive_count = 0;
342 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
343 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
345 /* 0 means chip/fw default, non-zero number is value in microseconds */
346 static u_long t4_toe_rexmt_min = 0;
347 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
348 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
350 /* 0 means chip/fw default, non-zero number is value in microseconds */
351 static u_long t4_toe_rexmt_max = 0;
352 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
353 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
355 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
356 static int t4_toe_rexmt_count = 0;
357 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
358 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
360 /* -1 means chip/fw default, other values are raw backoff values to use */
361 static int t4_toe_rexmt_backoff[16] = {
362 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
364 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
365 "cxgbe(4) TOE retransmit backoff values");
366 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
367 &t4_toe_rexmt_backoff[0], 0, "");
368 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
369 &t4_toe_rexmt_backoff[1], 0, "");
370 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
371 &t4_toe_rexmt_backoff[2], 0, "");
372 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
373 &t4_toe_rexmt_backoff[3], 0, "");
374 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
375 &t4_toe_rexmt_backoff[4], 0, "");
376 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
377 &t4_toe_rexmt_backoff[5], 0, "");
378 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
379 &t4_toe_rexmt_backoff[6], 0, "");
380 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
381 &t4_toe_rexmt_backoff[7], 0, "");
382 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
383 &t4_toe_rexmt_backoff[8], 0, "");
384 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
385 &t4_toe_rexmt_backoff[9], 0, "");
386 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
387 &t4_toe_rexmt_backoff[10], 0, "");
388 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
389 &t4_toe_rexmt_backoff[11], 0, "");
390 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
391 &t4_toe_rexmt_backoff[12], 0, "");
392 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
393 &t4_toe_rexmt_backoff[13], 0, "");
394 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
395 &t4_toe_rexmt_backoff[14], 0, "");
396 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
397 &t4_toe_rexmt_backoff[15], 0, "");
402 static int t4_nnmtxq_vi = -NNMTXQ_VI;
403 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
404 "Number of netmap TX queues per VI");
407 static int t4_nnmrxq_vi = -NNMRXQ_VI;
408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
409 "Number of netmap RX queues per VI");
413 * Holdoff parameters for ports.
416 int t4_tmr_idx = TMR_IDX;
417 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
418 0, "Holdoff timer index");
419 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
421 #define PKTC_IDX (-1)
422 int t4_pktc_idx = PKTC_IDX;
423 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
424 0, "Holdoff packet counter index");
425 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
428 * Size (# of entries) of each tx and rx queue.
430 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
431 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
432 "Number of descriptors in each TX queue");
434 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
435 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
436 "Number of descriptors in each RX queue");
439 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
441 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
442 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
443 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
446 * Configuration file. All the _CF names here are special.
448 #define DEFAULT_CF "default"
449 #define BUILTIN_CF "built-in"
450 #define FLASH_CF "flash"
451 #define UWIRE_CF "uwire"
452 #define FPGA_CF "fpga"
453 static char t4_cfg_file[32] = DEFAULT_CF;
454 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
455 sizeof(t4_cfg_file), "Firmware configuration file");
458 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
459 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
460 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
461 * mark or when signalled to do so, 0 to never emit PAUSE.
462 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
463 * negotiated settings will override rx_pause/tx_pause.
464 * Otherwise rx_pause/tx_pause are applied forcibly.
466 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
467 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
468 &t4_pause_settings, 0,
469 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
472 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
473 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
476 static int t4_fec = -1;
477 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
478 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
481 * Link autonegotiation.
482 * -1 to run with the firmware default.
486 static int t4_autoneg = -1;
487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
488 "Link autonegotiation");
491 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
492 * encouraged respectively). '-n' is the same as 'n' except the firmware
493 * version used in the checks is read from the firmware bundled with the driver.
495 static int t4_fw_install = 1;
496 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
497 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
500 * ASIC features that will be used. Disable the ones you don't want so that the
501 * chip resources aren't wasted on features that will not be used.
503 static int t4_nbmcaps_allowed = 0;
504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
505 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
507 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
508 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
509 &t4_linkcaps_allowed, 0, "Default link capabilities");
511 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
512 FW_CAPS_CONFIG_SWITCH_EGRESS;
513 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
514 &t4_switchcaps_allowed, 0, "Default switch capabilities");
517 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
518 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
520 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
521 FW_CAPS_CONFIG_NIC_HASHFILTER;
523 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
524 &t4_niccaps_allowed, 0, "Default NIC capabilities");
526 static int t4_toecaps_allowed = -1;
527 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
528 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
530 static int t4_rdmacaps_allowed = -1;
531 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
532 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
534 static int t4_cryptocaps_allowed = -1;
535 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
536 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
538 static int t4_iscsicaps_allowed = -1;
539 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
540 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
542 static int t4_fcoecaps_allowed = 0;
543 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
544 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
546 static int t5_write_combine = 0;
547 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
548 0, "Use WC instead of UC for BAR2");
550 static int t4_num_vis = 1;
551 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
552 "Number of VIs per port");
555 * PCIe Relaxed Ordering.
556 * -1: driver should figure out a good value.
561 static int pcie_relaxed_ordering = -1;
562 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
563 &pcie_relaxed_ordering, 0,
564 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
566 static int t4_panic_on_fatal_err = 0;
567 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
568 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
574 static int t4_cop_managed_offloading = 0;
575 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
576 &t4_cop_managed_offloading, 0,
577 "COP (Connection Offload Policy) controls all TOE offload");
580 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
581 static int vi_mac_funcs[] = {
585 FW_VI_FUNC_OPENISCSI,
591 struct intrs_and_queues {
592 uint16_t intr_type; /* INTx, MSI, or MSI-X */
593 uint16_t num_vis; /* number of VIs for each port */
594 uint16_t nirq; /* Total # of vectors */
595 uint16_t ntxq; /* # of NIC txq's for each port */
596 uint16_t nrxq; /* # of NIC rxq's for each port */
597 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
598 uint16_t nofldrxq; /* # of TOE rxq's for each port */
600 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
601 uint16_t ntxq_vi; /* # of NIC txq's */
602 uint16_t nrxq_vi; /* # of NIC rxq's */
603 uint16_t nofldtxq_vi; /* # of TOE txq's */
604 uint16_t nofldrxq_vi; /* # of TOE rxq's */
605 uint16_t nnmtxq_vi; /* # of netmap txq's */
606 uint16_t nnmrxq_vi; /* # of netmap rxq's */
609 static void setup_memwin(struct adapter *);
610 static void position_memwin(struct adapter *, int, uint32_t);
611 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
612 static int fwmtype_to_hwmtype(int);
613 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
615 static int fixup_devlog_params(struct adapter *);
616 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
617 static int contact_firmware(struct adapter *);
618 static int partition_resources(struct adapter *);
619 static int get_params__pre_init(struct adapter *);
620 static int set_params__pre_init(struct adapter *);
621 static int get_params__post_init(struct adapter *);
622 static int set_params__post_init(struct adapter *);
623 static void t4_set_desc(struct adapter *);
624 static bool fixed_ifmedia(struct port_info *);
625 static void build_medialist(struct port_info *);
626 static void init_link_config(struct port_info *);
627 static int fixup_link_config(struct port_info *);
628 static int apply_link_config(struct port_info *);
629 static int cxgbe_init_synchronized(struct vi_info *);
630 static int cxgbe_uninit_synchronized(struct vi_info *);
631 static void quiesce_txq(struct adapter *, struct sge_txq *);
632 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
633 static void quiesce_iq(struct adapter *, struct sge_iq *);
634 static void quiesce_fl(struct adapter *, struct sge_fl *);
635 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
636 driver_intr_t *, void *, char *);
637 static int t4_free_irq(struct adapter *, struct irq *);
638 static void t4_init_atid_table(struct adapter *);
639 static void t4_free_atid_table(struct adapter *);
640 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
641 static void vi_refresh_stats(struct adapter *, struct vi_info *);
642 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
643 static void cxgbe_tick(void *);
644 static void cxgbe_sysctls(struct port_info *);
645 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
646 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
647 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
648 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
649 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
650 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
651 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
652 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
653 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
654 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
655 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
656 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
657 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
658 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
659 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
660 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
661 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
662 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
663 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
664 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
665 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
666 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
667 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
668 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
669 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
670 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
671 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
672 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
673 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
674 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
675 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
676 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
677 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
678 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
679 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
680 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
681 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
682 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
683 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
684 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
685 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
686 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
687 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
688 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
690 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
691 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
692 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
693 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
694 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
695 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
696 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
697 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
699 static int get_sge_context(struct adapter *, struct t4_sge_context *);
700 static int load_fw(struct adapter *, struct t4_data *);
701 static int load_cfg(struct adapter *, struct t4_data *);
702 static int load_boot(struct adapter *, struct t4_bootrom *);
703 static int load_bootcfg(struct adapter *, struct t4_data *);
704 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
705 static void free_offload_policy(struct t4_offload_policy *);
706 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
707 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
708 static int read_i2c(struct adapter *, struct t4_i2c_data *);
709 static int clear_stats(struct adapter *, u_int);
711 static int toe_capability(struct vi_info *, int);
713 static int mod_event(module_t, int, void *);
714 static int notify_siblings(device_t, int);
720 {0xa000, "Chelsio Terminator 4 FPGA"},
721 {0x4400, "Chelsio T440-dbg"},
722 {0x4401, "Chelsio T420-CR"},
723 {0x4402, "Chelsio T422-CR"},
724 {0x4403, "Chelsio T440-CR"},
725 {0x4404, "Chelsio T420-BCH"},
726 {0x4405, "Chelsio T440-BCH"},
727 {0x4406, "Chelsio T440-CH"},
728 {0x4407, "Chelsio T420-SO"},
729 {0x4408, "Chelsio T420-CX"},
730 {0x4409, "Chelsio T420-BT"},
731 {0x440a, "Chelsio T404-BT"},
732 {0x440e, "Chelsio T440-LP-CR"},
734 {0xb000, "Chelsio Terminator 5 FPGA"},
735 {0x5400, "Chelsio T580-dbg"},
736 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
737 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
738 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
739 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
740 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
741 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
742 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
743 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
744 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
745 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
746 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
747 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
748 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
749 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
750 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
751 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
752 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
755 {0x5483, "Custom T540-CR"},
756 {0x5484, "Custom T540-BT"},
758 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
759 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
760 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
761 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
762 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
763 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
764 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
765 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
766 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
767 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
768 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
769 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
770 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
771 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
772 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
773 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
776 {0x6480, "Custom T6225-CR"},
777 {0x6481, "Custom T62100-CR"},
778 {0x6482, "Custom T6225-CR"},
779 {0x6483, "Custom T62100-CR"},
780 {0x6484, "Custom T64100-CR"},
781 {0x6485, "Custom T6240-SO"},
782 {0x6486, "Custom T6225-SO-CR"},
783 {0x6487, "Custom T6225-CR"},
788 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
789 * be exactly the same for both rxq and ofld_rxq.
791 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
792 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
794 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
797 t4_probe(device_t dev)
800 uint16_t v = pci_get_vendor(dev);
801 uint16_t d = pci_get_device(dev);
802 uint8_t f = pci_get_function(dev);
804 if (v != PCI_VENDOR_ID_CHELSIO)
807 /* Attach only to PF0 of the FPGA */
808 if (d == 0xa000 && f != 0)
811 for (i = 0; i < nitems(t4_pciids); i++) {
812 if (d == t4_pciids[i].device) {
813 device_set_desc(dev, t4_pciids[i].desc);
814 return (BUS_PROBE_DEFAULT);
822 t5_probe(device_t dev)
825 uint16_t v = pci_get_vendor(dev);
826 uint16_t d = pci_get_device(dev);
827 uint8_t f = pci_get_function(dev);
829 if (v != PCI_VENDOR_ID_CHELSIO)
832 /* Attach only to PF0 of the FPGA */
833 if (d == 0xb000 && f != 0)
836 for (i = 0; i < nitems(t5_pciids); i++) {
837 if (d == t5_pciids[i].device) {
838 device_set_desc(dev, t5_pciids[i].desc);
839 return (BUS_PROBE_DEFAULT);
847 t6_probe(device_t dev)
850 uint16_t v = pci_get_vendor(dev);
851 uint16_t d = pci_get_device(dev);
853 if (v != PCI_VENDOR_ID_CHELSIO)
856 for (i = 0; i < nitems(t6_pciids); i++) {
857 if (d == t6_pciids[i].device) {
858 device_set_desc(dev, t6_pciids[i].desc);
859 return (BUS_PROBE_DEFAULT);
867 t5_attribute_workaround(device_t dev)
873 * The T5 chips do not properly echo the No Snoop and Relaxed
874 * Ordering attributes when replying to a TLP from a Root
875 * Port. As a workaround, find the parent Root Port and
876 * disable No Snoop and Relaxed Ordering. Note that this
877 * affects all devices under this root port.
879 root_port = pci_find_pcie_root_port(dev);
880 if (root_port == NULL) {
881 device_printf(dev, "Unable to find parent root port\n");
885 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
886 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
887 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
889 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
890 device_get_nameunit(root_port));
893 static const struct devnames devnames[] = {
895 .nexus_name = "t4nex",
896 .ifnet_name = "cxgbe",
897 .vi_ifnet_name = "vcxgbe",
898 .pf03_drv_name = "t4iov",
899 .vf_nexus_name = "t4vf",
900 .vf_ifnet_name = "cxgbev"
902 .nexus_name = "t5nex",
904 .vi_ifnet_name = "vcxl",
905 .pf03_drv_name = "t5iov",
906 .vf_nexus_name = "t5vf",
907 .vf_ifnet_name = "cxlv"
909 .nexus_name = "t6nex",
911 .vi_ifnet_name = "vcc",
912 .pf03_drv_name = "t6iov",
913 .vf_nexus_name = "t6vf",
914 .vf_ifnet_name = "ccv"
919 t4_init_devnames(struct adapter *sc)
924 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
925 sc->names = &devnames[id - CHELSIO_T4];
927 device_printf(sc->dev, "chip id %d is not supported.\n", id);
933 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
935 const char *parent, *name;
940 parent = device_get_nameunit(sc->dev);
941 name = sc->names->ifnet_name;
942 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
943 if (resource_long_value(name, unit, "port", &value) == 0 &&
944 value == pi->port_id)
951 t4_attach(device_t dev)
954 int rc = 0, i, j, rqidx, tqidx, nports;
955 struct make_dev_args mda;
956 struct intrs_and_queues iaq;
959 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
966 int nm_rqidx, nm_tqidx;
970 sc = device_get_softc(dev);
972 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
974 if ((pci_get_device(dev) & 0xff00) == 0x5400)
975 t5_attribute_workaround(dev);
976 pci_enable_busmaster(dev);
977 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
980 pci_set_max_read_req(dev, 4096);
981 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
982 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
983 if (pcie_relaxed_ordering == 0 &&
984 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
985 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
986 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
987 } else if (pcie_relaxed_ordering == 1 &&
988 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
989 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
990 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
994 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
995 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
997 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
998 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
999 device_get_nameunit(dev));
1001 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1002 device_get_nameunit(dev));
1003 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1006 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1007 TAILQ_INIT(&sc->sfl);
1008 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1010 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1013 rw_init(&sc->policy_lock, "connection offload policy");
1015 rc = t4_map_bars_0_and_4(sc);
1017 goto done; /* error message displayed already */
1019 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1021 /* Prepare the adapter for operation. */
1022 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1023 rc = -t4_prep_adapter(sc, buf);
1026 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1031 * This is the real PF# to which we're attaching. Works from within PCI
1032 * passthrough environments too, where pci_get_function() could return a
1033 * different PF# depending on the passthrough configuration. We need to
1034 * use the real PF# in all our communication with the firmware.
1036 j = t4_read_reg(sc, A_PL_WHOAMI);
1037 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1040 t4_init_devnames(sc);
1041 if (sc->names == NULL) {
1043 goto done; /* error message displayed already */
1047 * Do this really early, with the memory windows set up even before the
1048 * character device. The userland tool's register i/o and mem read
1049 * will work even in "recovery mode".
1052 if (t4_init_devlog_params(sc, 0) == 0)
1053 fixup_devlog_params(sc);
1054 make_dev_args_init(&mda);
1055 mda.mda_devsw = &t4_cdevsw;
1056 mda.mda_uid = UID_ROOT;
1057 mda.mda_gid = GID_WHEEL;
1058 mda.mda_mode = 0600;
1059 mda.mda_si_drv1 = sc;
1060 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1062 device_printf(dev, "failed to create nexus char device: %d.\n",
1065 /* Go no further if recovery mode has been requested. */
1066 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1067 device_printf(dev, "recovery mode.\n");
1071 #if defined(__i386__)
1072 if ((cpu_feature & CPUID_CX8) == 0) {
1073 device_printf(dev, "64 bit atomics not available.\n");
1079 /* Contact the firmware and try to become the master driver. */
1080 rc = contact_firmware(sc);
1082 goto done; /* error message displayed already */
1083 MPASS(sc->flags & FW_OK);
1085 rc = get_params__pre_init(sc);
1087 goto done; /* error message displayed already */
1089 if (sc->flags & MASTER_PF) {
1090 rc = partition_resources(sc);
1092 goto done; /* error message displayed already */
1096 rc = get_params__post_init(sc);
1098 goto done; /* error message displayed already */
1100 rc = set_params__post_init(sc);
1102 goto done; /* error message displayed already */
1104 rc = t4_map_bar_2(sc);
1106 goto done; /* error message displayed already */
1108 rc = t4_create_dma_tag(sc);
1110 goto done; /* error message displayed already */
1113 * First pass over all the ports - allocate VIs and initialize some
1114 * basic parameters like mac address, port type, etc.
1116 for_each_port(sc, i) {
1117 struct port_info *pi;
1119 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1122 /* These must be set before t4_port_init */
1126 * XXX: vi[0] is special so we can't delay this allocation until
1127 * pi->nvi's final value is known.
1129 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1133 * Allocate the "main" VI and initialize parameters
1136 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1138 device_printf(dev, "unable to initialize port %d: %d\n",
1140 free(pi->vi, M_CXGBE);
1146 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1147 device_get_nameunit(dev), i);
1148 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1149 sc->chan_map[pi->tx_chan] = i;
1151 /* All VIs on this port share this media. */
1152 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1153 cxgbe_media_status);
1156 init_link_config(pi);
1157 fixup_link_config(pi);
1158 build_medialist(pi);
1159 if (fixed_ifmedia(pi))
1160 pi->flags |= FIXED_IFMEDIA;
1163 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1164 t4_ifnet_unit(sc, pi));
1165 if (pi->dev == NULL) {
1167 "failed to add device for port %d.\n", i);
1171 pi->vi[0].dev = pi->dev;
1172 device_set_softc(pi->dev, pi);
1176 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1178 nports = sc->params.nports;
1179 rc = cfg_itype_and_nqueues(sc, &iaq);
1181 goto done; /* error message displayed already */
1183 num_vis = iaq.num_vis;
1184 sc->intr_type = iaq.intr_type;
1185 sc->intr_count = iaq.nirq;
1188 s->nrxq = nports * iaq.nrxq;
1189 s->ntxq = nports * iaq.ntxq;
1191 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1192 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1194 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1195 s->neq += nports; /* ctrl queues: 1 per port */
1196 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1197 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1198 if (is_offload(sc) || is_ethoffload(sc)) {
1199 s->nofldtxq = nports * iaq.nofldtxq;
1201 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1202 s->neq += s->nofldtxq;
1204 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1205 M_CXGBE, M_ZERO | M_WAITOK);
1209 if (is_offload(sc)) {
1210 s->nofldrxq = nports * iaq.nofldrxq;
1212 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1213 s->neq += s->nofldrxq; /* free list */
1214 s->niq += s->nofldrxq;
1216 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1217 M_CXGBE, M_ZERO | M_WAITOK);
1222 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1223 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1225 s->neq += s->nnmtxq + s->nnmrxq;
1226 s->niq += s->nnmrxq;
1228 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1229 M_CXGBE, M_ZERO | M_WAITOK);
1230 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1231 M_CXGBE, M_ZERO | M_WAITOK);
1234 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1236 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1238 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1240 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1242 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1245 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1248 t4_init_l2t(sc, M_WAITOK);
1249 t4_init_smt(sc, M_WAITOK);
1250 t4_init_tx_sched(sc);
1251 t4_init_atid_table(sc);
1253 t4_init_etid_table(sc);
1256 t4_init_clip_table(sc);
1258 if (sc->vres.key.size != 0)
1259 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1260 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1263 * Second pass over the ports. This time we know the number of rx and
1264 * tx queues that each port should get.
1267 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1274 nm_rqidx = nm_tqidx = 0;
1276 for_each_port(sc, i) {
1277 struct port_info *pi = sc->port[i];
1284 for_each_vi(pi, j, vi) {
1286 vi->qsize_rxq = t4_qsize_rxq;
1287 vi->qsize_txq = t4_qsize_txq;
1289 vi->first_rxq = rqidx;
1290 vi->first_txq = tqidx;
1291 vi->tmr_idx = t4_tmr_idx;
1292 vi->pktc_idx = t4_pktc_idx;
1293 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1294 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1299 if (j == 0 && vi->ntxq > 1)
1300 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1302 vi->rsrv_noflowq = 0;
1304 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1305 vi->first_ofld_txq = ofld_tqidx;
1306 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1307 ofld_tqidx += vi->nofldtxq;
1310 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1311 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1312 vi->first_ofld_rxq = ofld_rqidx;
1313 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1315 ofld_rqidx += vi->nofldrxq;
1319 vi->first_nm_rxq = nm_rqidx;
1320 vi->first_nm_txq = nm_tqidx;
1321 vi->nnmrxq = iaq.nnmrxq_vi;
1322 vi->nnmtxq = iaq.nnmtxq_vi;
1323 nm_rqidx += vi->nnmrxq;
1324 nm_tqidx += vi->nnmtxq;
1330 rc = t4_setup_intr_handlers(sc);
1333 "failed to setup interrupt handlers: %d\n", rc);
1337 rc = bus_generic_probe(dev);
1339 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1344 * Ensure thread-safe mailbox access (in debug builds).
1346 * So far this was the only thread accessing the mailbox but various
1347 * ifnets and sysctls are about to be created and their handlers/ioctls
1348 * will access the mailbox from different threads.
1350 sc->flags |= CHK_MBOX_ACCESS;
1352 rc = bus_generic_attach(dev);
1355 "failed to attach all child ports: %d\n", rc);
1360 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1361 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1362 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1363 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1364 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1368 notify_siblings(dev, 0);
1371 if (rc != 0 && sc->cdev) {
1372 /* cdev was created and so cxgbetool works; recover that way. */
1374 "error during attach, adapter is now in recovery mode.\n");
1379 t4_detach_common(dev);
1387 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1390 struct port_info *pi;
1393 sc = device_get_softc(bus);
1395 for_each_port(sc, i) {
1397 if (pi != NULL && pi->dev == dev) {
1398 snprintf(buf, buflen, "port=%d", pi->port_id);
1406 t4_ready(device_t dev)
1410 sc = device_get_softc(dev);
1411 if (sc->flags & FW_OK)
1417 t4_read_port_device(device_t dev, int port, device_t *child)
1420 struct port_info *pi;
1422 sc = device_get_softc(dev);
1423 if (port < 0 || port >= MAX_NPORTS)
1425 pi = sc->port[port];
1426 if (pi == NULL || pi->dev == NULL)
1433 notify_siblings(device_t dev, int detaching)
1439 for (i = 0; i < PCI_FUNCMAX; i++) {
1440 if (i == pci_get_function(dev))
1442 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1443 pci_get_slot(dev), i);
1444 if (sibling == NULL || !device_is_attached(sibling))
1447 error = T4_DETACH_CHILD(sibling);
1449 (void)T4_ATTACH_CHILD(sibling);
1460 t4_detach(device_t dev)
1465 sc = device_get_softc(dev);
1467 rc = notify_siblings(dev, 1);
1470 "failed to detach sibling devices: %d\n", rc);
1474 return (t4_detach_common(dev));
1478 t4_detach_common(device_t dev)
1481 struct port_info *pi;
1484 sc = device_get_softc(dev);
1487 destroy_dev(sc->cdev);
1491 sx_xlock(&t4_list_lock);
1492 SLIST_REMOVE(&t4_list, sc, adapter, link);
1493 sx_xunlock(&t4_list_lock);
1495 sc->flags &= ~CHK_MBOX_ACCESS;
1496 if (sc->flags & FULL_INIT_DONE) {
1497 if (!(sc->flags & IS_VF))
1498 t4_intr_disable(sc);
1501 if (device_is_attached(dev)) {
1502 rc = bus_generic_detach(dev);
1505 "failed to detach child devices: %d\n", rc);
1510 for (i = 0; i < sc->intr_count; i++)
1511 t4_free_irq(sc, &sc->irq[i]);
1513 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1514 t4_free_tx_sched(sc);
1516 for (i = 0; i < MAX_NPORTS; i++) {
1519 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1521 device_delete_child(dev, pi->dev);
1523 mtx_destroy(&pi->pi_lock);
1524 free(pi->vi, M_CXGBE);
1529 device_delete_children(dev);
1531 if (sc->flags & FULL_INIT_DONE)
1532 adapter_full_uninit(sc);
1534 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1535 t4_fw_bye(sc, sc->mbox);
1537 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1538 pci_release_msi(dev);
1541 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1545 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1549 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1553 t4_free_l2t(sc->l2t);
1555 t4_free_smt(sc->smt);
1556 t4_free_atid_table(sc);
1558 t4_free_etid_table(sc);
1561 vmem_destroy(sc->key_map);
1563 t4_destroy_clip_table(sc);
1566 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1567 free(sc->sge.ofld_txq, M_CXGBE);
1570 free(sc->sge.ofld_rxq, M_CXGBE);
1573 free(sc->sge.nm_rxq, M_CXGBE);
1574 free(sc->sge.nm_txq, M_CXGBE);
1576 free(sc->irq, M_CXGBE);
1577 free(sc->sge.rxq, M_CXGBE);
1578 free(sc->sge.txq, M_CXGBE);
1579 free(sc->sge.ctrlq, M_CXGBE);
1580 free(sc->sge.iqmap, M_CXGBE);
1581 free(sc->sge.eqmap, M_CXGBE);
1582 free(sc->tids.ftid_tab, M_CXGBE);
1583 free(sc->tids.hpftid_tab, M_CXGBE);
1584 free_hftid_hash(&sc->tids);
1585 free(sc->tids.tid_tab, M_CXGBE);
1586 free(sc->tt.tls_rx_ports, M_CXGBE);
1587 t4_destroy_dma_tag(sc);
1589 callout_drain(&sc->sfl_callout);
1590 if (mtx_initialized(&sc->tids.ftid_lock)) {
1591 mtx_destroy(&sc->tids.ftid_lock);
1592 cv_destroy(&sc->tids.ftid_cv);
1594 if (mtx_initialized(&sc->tids.atid_lock))
1595 mtx_destroy(&sc->tids.atid_lock);
1596 if (mtx_initialized(&sc->ifp_lock))
1597 mtx_destroy(&sc->ifp_lock);
1599 if (rw_initialized(&sc->policy_lock)) {
1600 rw_destroy(&sc->policy_lock);
1602 if (sc->policy != NULL)
1603 free_offload_policy(sc->policy);
1607 for (i = 0; i < NUM_MEMWIN; i++) {
1608 struct memwin *mw = &sc->memwin[i];
1610 if (rw_initialized(&mw->mw_lock))
1611 rw_destroy(&mw->mw_lock);
1614 mtx_destroy(&sc->sfl_lock);
1615 mtx_destroy(&sc->reg_lock);
1616 mtx_destroy(&sc->sc_lock);
1618 bzero(sc, sizeof(*sc));
1624 cxgbe_probe(device_t dev)
1627 struct port_info *pi = device_get_softc(dev);
1629 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1630 device_set_desc_copy(dev, buf);
1632 return (BUS_PROBE_DEFAULT);
1635 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1636 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1637 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1638 IFCAP_HWRXTSTMP | IFCAP_NOMAP)
1639 #define T4_CAP_ENABLE (T4_CAP)
1642 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1647 vi->xact_addr_filt = -1;
1648 callout_init(&vi->tick, 1);
1650 /* Allocate an ifnet and set it up */
1651 ifp = if_alloc_dev(IFT_ETHER, dev);
1653 device_printf(dev, "Cannot allocate ifnet\n");
1659 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1660 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1662 ifp->if_init = cxgbe_init;
1663 ifp->if_ioctl = cxgbe_ioctl;
1664 ifp->if_transmit = cxgbe_transmit;
1665 ifp->if_qflush = cxgbe_qflush;
1666 ifp->if_get_counter = cxgbe_get_counter;
1668 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1669 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1670 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1671 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1672 ifp->if_ratelimit_query = cxgbe_ratelimit_query;
1675 ifp->if_capabilities = T4_CAP;
1676 ifp->if_capenable = T4_CAP_ENABLE;
1678 if (vi->nofldrxq != 0)
1679 ifp->if_capabilities |= IFCAP_TOE;
1682 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1683 ifp->if_capabilities |= IFCAP_TXRTLMT;
1684 ifp->if_capenable |= IFCAP_TXRTLMT;
1687 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1688 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1690 ifp->if_hw_tsomax = IP_MAXPACKET;
1691 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1693 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1694 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1696 ifp->if_hw_tsomaxsegsize = 65536;
1698 ether_ifattach(ifp, vi->hw_addr);
1700 if (vi->nnmrxq != 0)
1701 cxgbe_nm_attach(vi);
1703 sb = sbuf_new_auto();
1704 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1705 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1706 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1708 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1710 case IFCAP_TOE | IFCAP_TXRTLMT:
1711 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1714 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1719 if (ifp->if_capabilities & IFCAP_TOE)
1720 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1723 if (ifp->if_capabilities & IFCAP_NETMAP)
1724 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1725 vi->nnmtxq, vi->nnmrxq);
1728 device_printf(dev, "%s\n", sbuf_data(sb));
1737 cxgbe_attach(device_t dev)
1739 struct port_info *pi = device_get_softc(dev);
1740 struct adapter *sc = pi->adapter;
1744 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1746 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1750 for_each_vi(pi, i, vi) {
1753 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1754 if (vi->dev == NULL) {
1755 device_printf(dev, "failed to add VI %d\n", i);
1758 device_set_softc(vi->dev, vi);
1763 bus_generic_attach(dev);
1769 cxgbe_vi_detach(struct vi_info *vi)
1771 struct ifnet *ifp = vi->ifp;
1773 ether_ifdetach(ifp);
1775 /* Let detach proceed even if these fail. */
1777 if (ifp->if_capabilities & IFCAP_NETMAP)
1778 cxgbe_nm_detach(vi);
1780 cxgbe_uninit_synchronized(vi);
1781 callout_drain(&vi->tick);
1789 cxgbe_detach(device_t dev)
1791 struct port_info *pi = device_get_softc(dev);
1792 struct adapter *sc = pi->adapter;
1795 /* Detach the extra VIs first. */
1796 rc = bus_generic_detach(dev);
1799 device_delete_children(dev);
1801 doom_vi(sc, &pi->vi[0]);
1803 if (pi->flags & HAS_TRACEQ) {
1804 sc->traceq = -1; /* cloner should not create ifnet */
1805 t4_tracer_port_detach(sc);
1808 cxgbe_vi_detach(&pi->vi[0]);
1809 callout_drain(&pi->tick);
1810 ifmedia_removeall(&pi->media);
1812 end_synchronized_op(sc, 0);
1818 cxgbe_init(void *arg)
1820 struct vi_info *vi = arg;
1821 struct adapter *sc = vi->pi->adapter;
1823 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1825 cxgbe_init_synchronized(vi);
1826 end_synchronized_op(sc, 0);
1830 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1832 int rc = 0, mtu, flags;
1833 struct vi_info *vi = ifp->if_softc;
1834 struct port_info *pi = vi->pi;
1835 struct adapter *sc = pi->adapter;
1836 struct ifreq *ifr = (struct ifreq *)data;
1842 if (mtu < ETHERMIN || mtu > MAX_MTU)
1845 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1849 if (vi->flags & VI_INIT_DONE) {
1850 t4_update_fl_bufsize(ifp);
1851 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1852 rc = update_mac_settings(ifp, XGMAC_MTU);
1854 end_synchronized_op(sc, 0);
1858 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1862 if (ifp->if_flags & IFF_UP) {
1863 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1864 flags = vi->if_flags;
1865 if ((ifp->if_flags ^ flags) &
1866 (IFF_PROMISC | IFF_ALLMULTI)) {
1867 rc = update_mac_settings(ifp,
1868 XGMAC_PROMISC | XGMAC_ALLMULTI);
1871 rc = cxgbe_init_synchronized(vi);
1873 vi->if_flags = ifp->if_flags;
1874 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1875 rc = cxgbe_uninit_synchronized(vi);
1877 end_synchronized_op(sc, 0);
1882 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1885 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1886 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1887 end_synchronized_op(sc, 0);
1891 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1895 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1896 if (mask & IFCAP_TXCSUM) {
1897 ifp->if_capenable ^= IFCAP_TXCSUM;
1898 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1900 if (IFCAP_TSO4 & ifp->if_capenable &&
1901 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1902 ifp->if_capenable &= ~IFCAP_TSO4;
1904 "tso4 disabled due to -txcsum.\n");
1907 if (mask & IFCAP_TXCSUM_IPV6) {
1908 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1909 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1911 if (IFCAP_TSO6 & ifp->if_capenable &&
1912 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1913 ifp->if_capenable &= ~IFCAP_TSO6;
1915 "tso6 disabled due to -txcsum6.\n");
1918 if (mask & IFCAP_RXCSUM)
1919 ifp->if_capenable ^= IFCAP_RXCSUM;
1920 if (mask & IFCAP_RXCSUM_IPV6)
1921 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1924 * Note that we leave CSUM_TSO alone (it is always set). The
1925 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1926 * sending a TSO request our way, so it's sufficient to toggle
1929 if (mask & IFCAP_TSO4) {
1930 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1931 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1932 if_printf(ifp, "enable txcsum first.\n");
1936 ifp->if_capenable ^= IFCAP_TSO4;
1938 if (mask & IFCAP_TSO6) {
1939 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1940 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1941 if_printf(ifp, "enable txcsum6 first.\n");
1945 ifp->if_capenable ^= IFCAP_TSO6;
1947 if (mask & IFCAP_LRO) {
1948 #if defined(INET) || defined(INET6)
1950 struct sge_rxq *rxq;
1952 ifp->if_capenable ^= IFCAP_LRO;
1953 for_each_rxq(vi, i, rxq) {
1954 if (ifp->if_capenable & IFCAP_LRO)
1955 rxq->iq.flags |= IQ_LRO_ENABLED;
1957 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1962 if (mask & IFCAP_TOE) {
1963 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1965 rc = toe_capability(vi, enable);
1969 ifp->if_capenable ^= mask;
1972 if (mask & IFCAP_VLAN_HWTAGGING) {
1973 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1974 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1975 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1977 if (mask & IFCAP_VLAN_MTU) {
1978 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1980 /* Need to find out how to disable auto-mtu-inflation */
1982 if (mask & IFCAP_VLAN_HWTSO)
1983 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1984 if (mask & IFCAP_VLAN_HWCSUM)
1985 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1987 if (mask & IFCAP_TXRTLMT)
1988 ifp->if_capenable ^= IFCAP_TXRTLMT;
1990 if (mask & IFCAP_HWRXTSTMP) {
1992 struct sge_rxq *rxq;
1994 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
1995 for_each_rxq(vi, i, rxq) {
1996 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
1997 rxq->iq.flags |= IQ_RX_TIMESTAMP;
1999 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
2002 if (mask & IFCAP_NOMAP)
2003 ifp->if_capenable ^= IFCAP_NOMAP;
2005 #ifdef VLAN_CAPABILITIES
2006 VLAN_CAPABILITIES(ifp);
2009 end_synchronized_op(sc, 0);
2015 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
2019 struct ifi2creq i2c;
2021 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2024 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2028 if (i2c.len > sizeof(i2c.data)) {
2032 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2035 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2036 i2c.offset, i2c.len, &i2c.data[0]);
2037 end_synchronized_op(sc, 0);
2039 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2044 rc = ether_ioctl(ifp, cmd, data);
2051 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2053 struct vi_info *vi = ifp->if_softc;
2054 struct port_info *pi = vi->pi;
2055 struct adapter *sc = pi->adapter;
2056 struct sge_txq *txq;
2058 struct cxgbe_snd_tag *cst;
2064 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2066 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
2067 MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
2070 if (__predict_false(pi->link_cfg.link_ok == false)) {
2075 rc = parse_pkt(sc, &m);
2076 if (__predict_false(rc != 0)) {
2077 MPASS(m == NULL); /* was freed already */
2078 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2082 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) {
2083 cst = mst_to_cst(m->m_pkthdr.snd_tag);
2084 if (cst->type == IF_SND_TAG_TYPE_RATE_LIMIT)
2085 return (ethofld_transmit(ifp, m));
2090 txq = &sc->sge.txq[vi->first_txq];
2091 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2092 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2096 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2097 if (__predict_false(rc != 0))
2104 cxgbe_qflush(struct ifnet *ifp)
2106 struct vi_info *vi = ifp->if_softc;
2107 struct sge_txq *txq;
2110 /* queues do not exist if !VI_INIT_DONE. */
2111 if (vi->flags & VI_INIT_DONE) {
2112 for_each_txq(vi, i, txq) {
2114 txq->eq.flags |= EQ_QFLUSH;
2116 while (!mp_ring_is_idle(txq->r)) {
2117 mp_ring_check_drainage(txq->r, 0);
2121 txq->eq.flags &= ~EQ_QFLUSH;
2129 vi_get_counter(struct ifnet *ifp, ift_counter c)
2131 struct vi_info *vi = ifp->if_softc;
2132 struct fw_vi_stats_vf *s = &vi->stats;
2134 vi_refresh_stats(vi->pi->adapter, vi);
2137 case IFCOUNTER_IPACKETS:
2138 return (s->rx_bcast_frames + s->rx_mcast_frames +
2139 s->rx_ucast_frames);
2140 case IFCOUNTER_IERRORS:
2141 return (s->rx_err_frames);
2142 case IFCOUNTER_OPACKETS:
2143 return (s->tx_bcast_frames + s->tx_mcast_frames +
2144 s->tx_ucast_frames + s->tx_offload_frames);
2145 case IFCOUNTER_OERRORS:
2146 return (s->tx_drop_frames);
2147 case IFCOUNTER_IBYTES:
2148 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2150 case IFCOUNTER_OBYTES:
2151 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2152 s->tx_ucast_bytes + s->tx_offload_bytes);
2153 case IFCOUNTER_IMCASTS:
2154 return (s->rx_mcast_frames);
2155 case IFCOUNTER_OMCASTS:
2156 return (s->tx_mcast_frames);
2157 case IFCOUNTER_OQDROPS: {
2161 if (vi->flags & VI_INIT_DONE) {
2163 struct sge_txq *txq;
2165 for_each_txq(vi, i, txq)
2166 drops += counter_u64_fetch(txq->r->drops);
2174 return (if_get_counter_default(ifp, c));
2179 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2181 struct vi_info *vi = ifp->if_softc;
2182 struct port_info *pi = vi->pi;
2183 struct adapter *sc = pi->adapter;
2184 struct port_stats *s = &pi->stats;
2186 if (pi->nvi > 1 || sc->flags & IS_VF)
2187 return (vi_get_counter(ifp, c));
2189 cxgbe_refresh_stats(sc, pi);
2192 case IFCOUNTER_IPACKETS:
2193 return (s->rx_frames);
2195 case IFCOUNTER_IERRORS:
2196 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2197 s->rx_fcs_err + s->rx_len_err);
2199 case IFCOUNTER_OPACKETS:
2200 return (s->tx_frames);
2202 case IFCOUNTER_OERRORS:
2203 return (s->tx_error_frames);
2205 case IFCOUNTER_IBYTES:
2206 return (s->rx_octets);
2208 case IFCOUNTER_OBYTES:
2209 return (s->tx_octets);
2211 case IFCOUNTER_IMCASTS:
2212 return (s->rx_mcast_frames);
2214 case IFCOUNTER_OMCASTS:
2215 return (s->tx_mcast_frames);
2217 case IFCOUNTER_IQDROPS:
2218 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2219 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2220 s->rx_trunc3 + pi->tnl_cong_drops);
2222 case IFCOUNTER_OQDROPS: {
2226 if (vi->flags & VI_INIT_DONE) {
2228 struct sge_txq *txq;
2230 for_each_txq(vi, i, txq)
2231 drops += counter_u64_fetch(txq->r->drops);
2239 return (if_get_counter_default(ifp, c));
2245 cxgbe_snd_tag_init(struct cxgbe_snd_tag *cst, struct ifnet *ifp, int type)
2248 m_snd_tag_init(&cst->com, ifp);
2253 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
2254 struct m_snd_tag **pt)
2258 switch (params->hdr.type) {
2260 case IF_SND_TAG_TYPE_RATE_LIMIT:
2261 error = cxgbe_rate_tag_alloc(ifp, params, pt);
2268 MPASS(mst_to_cst(*pt)->type == params->hdr.type);
2273 cxgbe_snd_tag_modify(struct m_snd_tag *mst,
2274 union if_snd_tag_modify_params *params)
2276 struct cxgbe_snd_tag *cst;
2278 cst = mst_to_cst(mst);
2279 switch (cst->type) {
2281 case IF_SND_TAG_TYPE_RATE_LIMIT:
2282 return (cxgbe_rate_tag_modify(mst, params));
2285 return (EOPNOTSUPP);
2290 cxgbe_snd_tag_query(struct m_snd_tag *mst,
2291 union if_snd_tag_query_params *params)
2293 struct cxgbe_snd_tag *cst;
2295 cst = mst_to_cst(mst);
2296 switch (cst->type) {
2298 case IF_SND_TAG_TYPE_RATE_LIMIT:
2299 return (cxgbe_rate_tag_query(mst, params));
2302 return (EOPNOTSUPP);
2307 cxgbe_snd_tag_free(struct m_snd_tag *mst)
2309 struct cxgbe_snd_tag *cst;
2311 cst = mst_to_cst(mst);
2312 switch (cst->type) {
2314 case IF_SND_TAG_TYPE_RATE_LIMIT:
2315 cxgbe_rate_tag_free(mst);
2319 panic("shouldn't get here");
2325 * The kernel picks a media from the list we had provided but we still validate
2329 cxgbe_media_change(struct ifnet *ifp)
2331 struct vi_info *vi = ifp->if_softc;
2332 struct port_info *pi = vi->pi;
2333 struct ifmedia *ifm = &pi->media;
2334 struct link_config *lc = &pi->link_cfg;
2335 struct adapter *sc = pi->adapter;
2338 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2342 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2343 /* ifconfig .. media autoselect */
2344 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2345 rc = ENOTSUP; /* AN not supported by transceiver */
2348 lc->requested_aneg = AUTONEG_ENABLE;
2349 lc->requested_speed = 0;
2350 lc->requested_fc |= PAUSE_AUTONEG;
2352 lc->requested_aneg = AUTONEG_DISABLE;
2353 lc->requested_speed =
2354 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2355 lc->requested_fc = 0;
2356 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2357 lc->requested_fc |= PAUSE_RX;
2358 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2359 lc->requested_fc |= PAUSE_TX;
2361 if (pi->up_vis > 0) {
2362 fixup_link_config(pi);
2363 rc = apply_link_config(pi);
2367 end_synchronized_op(sc, 0);
2372 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2376 port_mword(struct port_info *pi, uint32_t speed)
2379 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2380 MPASS(powerof2(speed));
2382 switch(pi->port_type) {
2383 case FW_PORT_TYPE_BT_SGMII:
2384 case FW_PORT_TYPE_BT_XFI:
2385 case FW_PORT_TYPE_BT_XAUI:
2388 case FW_PORT_CAP32_SPEED_100M:
2390 case FW_PORT_CAP32_SPEED_1G:
2391 return (IFM_1000_T);
2392 case FW_PORT_CAP32_SPEED_10G:
2396 case FW_PORT_TYPE_KX4:
2397 if (speed == FW_PORT_CAP32_SPEED_10G)
2398 return (IFM_10G_KX4);
2400 case FW_PORT_TYPE_CX4:
2401 if (speed == FW_PORT_CAP32_SPEED_10G)
2402 return (IFM_10G_CX4);
2404 case FW_PORT_TYPE_KX:
2405 if (speed == FW_PORT_CAP32_SPEED_1G)
2406 return (IFM_1000_KX);
2408 case FW_PORT_TYPE_KR:
2409 case FW_PORT_TYPE_BP_AP:
2410 case FW_PORT_TYPE_BP4_AP:
2411 case FW_PORT_TYPE_BP40_BA:
2412 case FW_PORT_TYPE_KR4_100G:
2413 case FW_PORT_TYPE_KR_SFP28:
2414 case FW_PORT_TYPE_KR_XLAUI:
2416 case FW_PORT_CAP32_SPEED_1G:
2417 return (IFM_1000_KX);
2418 case FW_PORT_CAP32_SPEED_10G:
2419 return (IFM_10G_KR);
2420 case FW_PORT_CAP32_SPEED_25G:
2421 return (IFM_25G_KR);
2422 case FW_PORT_CAP32_SPEED_40G:
2423 return (IFM_40G_KR4);
2424 case FW_PORT_CAP32_SPEED_50G:
2425 return (IFM_50G_KR2);
2426 case FW_PORT_CAP32_SPEED_100G:
2427 return (IFM_100G_KR4);
2430 case FW_PORT_TYPE_FIBER_XFI:
2431 case FW_PORT_TYPE_FIBER_XAUI:
2432 case FW_PORT_TYPE_SFP:
2433 case FW_PORT_TYPE_QSFP_10G:
2434 case FW_PORT_TYPE_QSA:
2435 case FW_PORT_TYPE_QSFP:
2436 case FW_PORT_TYPE_CR4_QSFP:
2437 case FW_PORT_TYPE_CR_QSFP:
2438 case FW_PORT_TYPE_CR2_QSFP:
2439 case FW_PORT_TYPE_SFP28:
2440 /* Pluggable transceiver */
2441 switch (pi->mod_type) {
2442 case FW_PORT_MOD_TYPE_LR:
2444 case FW_PORT_CAP32_SPEED_1G:
2445 return (IFM_1000_LX);
2446 case FW_PORT_CAP32_SPEED_10G:
2447 return (IFM_10G_LR);
2448 case FW_PORT_CAP32_SPEED_25G:
2449 return (IFM_25G_LR);
2450 case FW_PORT_CAP32_SPEED_40G:
2451 return (IFM_40G_LR4);
2452 case FW_PORT_CAP32_SPEED_50G:
2453 return (IFM_50G_LR2);
2454 case FW_PORT_CAP32_SPEED_100G:
2455 return (IFM_100G_LR4);
2458 case FW_PORT_MOD_TYPE_SR:
2460 case FW_PORT_CAP32_SPEED_1G:
2461 return (IFM_1000_SX);
2462 case FW_PORT_CAP32_SPEED_10G:
2463 return (IFM_10G_SR);
2464 case FW_PORT_CAP32_SPEED_25G:
2465 return (IFM_25G_SR);
2466 case FW_PORT_CAP32_SPEED_40G:
2467 return (IFM_40G_SR4);
2468 case FW_PORT_CAP32_SPEED_50G:
2469 return (IFM_50G_SR2);
2470 case FW_PORT_CAP32_SPEED_100G:
2471 return (IFM_100G_SR4);
2474 case FW_PORT_MOD_TYPE_ER:
2475 if (speed == FW_PORT_CAP32_SPEED_10G)
2476 return (IFM_10G_ER);
2478 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2479 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2481 case FW_PORT_CAP32_SPEED_1G:
2482 return (IFM_1000_CX);
2483 case FW_PORT_CAP32_SPEED_10G:
2484 return (IFM_10G_TWINAX);
2485 case FW_PORT_CAP32_SPEED_25G:
2486 return (IFM_25G_CR);
2487 case FW_PORT_CAP32_SPEED_40G:
2488 return (IFM_40G_CR4);
2489 case FW_PORT_CAP32_SPEED_50G:
2490 return (IFM_50G_CR2);
2491 case FW_PORT_CAP32_SPEED_100G:
2492 return (IFM_100G_CR4);
2495 case FW_PORT_MOD_TYPE_LRM:
2496 if (speed == FW_PORT_CAP32_SPEED_10G)
2497 return (IFM_10G_LRM);
2499 case FW_PORT_MOD_TYPE_NA:
2500 MPASS(0); /* Not pluggable? */
2502 case FW_PORT_MOD_TYPE_ERROR:
2503 case FW_PORT_MOD_TYPE_UNKNOWN:
2504 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2506 case FW_PORT_MOD_TYPE_NONE:
2510 case FW_PORT_TYPE_NONE:
2514 return (IFM_UNKNOWN);
2518 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2520 struct vi_info *vi = ifp->if_softc;
2521 struct port_info *pi = vi->pi;
2522 struct adapter *sc = pi->adapter;
2523 struct link_config *lc = &pi->link_cfg;
2525 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2529 if (pi->up_vis == 0) {
2531 * If all the interfaces are administratively down the firmware
2532 * does not report transceiver changes. Refresh port info here
2533 * so that ifconfig displays accurate ifmedia at all times.
2534 * This is the only reason we have a synchronized op in this
2535 * function. Just PORT_LOCK would have been enough otherwise.
2537 t4_update_port_info(pi);
2538 build_medialist(pi);
2542 ifmr->ifm_status = IFM_AVALID;
2543 if (lc->link_ok == false)
2545 ifmr->ifm_status |= IFM_ACTIVE;
2548 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2549 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2550 if (lc->fc & PAUSE_RX)
2551 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2552 if (lc->fc & PAUSE_TX)
2553 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2554 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2557 end_synchronized_op(sc, 0);
2561 vcxgbe_probe(device_t dev)
2564 struct vi_info *vi = device_get_softc(dev);
2566 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2568 device_set_desc_copy(dev, buf);
2570 return (BUS_PROBE_DEFAULT);
2574 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2576 int func, index, rc;
2577 uint32_t param, val;
2579 ASSERT_SYNCHRONIZED_OP(sc);
2581 index = vi - pi->vi;
2582 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2583 KASSERT(index < nitems(vi_mac_funcs),
2584 ("%s: VI %s doesn't have a MAC func", __func__,
2585 device_get_nameunit(vi->dev)));
2586 func = vi_mac_funcs[index];
2587 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2588 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
2590 device_printf(vi->dev, "failed to allocate virtual interface %d"
2591 "for port %d: %d\n", index, pi->port_id, -rc);
2596 if (vi->rss_size == 1) {
2598 * This VI didn't get a slice of the RSS table. Reduce the
2599 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2600 * configuration file (nvi, rssnvi for this PF) if this is a
2603 device_printf(vi->dev, "RSS table not available.\n");
2604 vi->rss_base = 0xffff;
2609 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2610 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2611 V_FW_PARAMS_PARAM_YZ(vi->viid);
2612 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2614 vi->rss_base = 0xffff;
2616 MPASS((val >> 16) == vi->rss_size);
2617 vi->rss_base = val & 0xffff;
2624 vcxgbe_attach(device_t dev)
2627 struct port_info *pi;
2631 vi = device_get_softc(dev);
2635 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2638 rc = alloc_extra_vi(sc, pi, vi);
2639 end_synchronized_op(sc, 0);
2643 rc = cxgbe_vi_attach(dev, vi);
2645 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2652 vcxgbe_detach(device_t dev)
2657 vi = device_get_softc(dev);
2658 sc = vi->pi->adapter;
2662 cxgbe_vi_detach(vi);
2663 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2665 end_synchronized_op(sc, 0);
2670 static struct callout fatal_callout;
2673 delayed_panic(void *arg)
2675 struct adapter *sc = arg;
2677 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
2681 t4_fatal_err(struct adapter *sc, bool fw_error)
2684 t4_shutdown_adapter(sc);
2685 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2686 device_get_nameunit(sc->dev));
2688 ASSERT_SYNCHRONIZED_OP(sc);
2689 sc->flags |= ADAP_ERR;
2692 sc->flags |= ADAP_ERR;
2696 if (t4_panic_on_fatal_err) {
2697 log(LOG_ALERT, "%s: panic on fatal error after 30s",
2698 device_get_nameunit(sc->dev));
2699 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
2704 t4_add_adapter(struct adapter *sc)
2706 sx_xlock(&t4_list_lock);
2707 SLIST_INSERT_HEAD(&t4_list, sc, link);
2708 sx_xunlock(&t4_list_lock);
2712 t4_map_bars_0_and_4(struct adapter *sc)
2714 sc->regs_rid = PCIR_BAR(0);
2715 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2716 &sc->regs_rid, RF_ACTIVE);
2717 if (sc->regs_res == NULL) {
2718 device_printf(sc->dev, "cannot map registers.\n");
2721 sc->bt = rman_get_bustag(sc->regs_res);
2722 sc->bh = rman_get_bushandle(sc->regs_res);
2723 sc->mmio_len = rman_get_size(sc->regs_res);
2724 setbit(&sc->doorbells, DOORBELL_KDB);
2726 sc->msix_rid = PCIR_BAR(4);
2727 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2728 &sc->msix_rid, RF_ACTIVE);
2729 if (sc->msix_res == NULL) {
2730 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2738 t4_map_bar_2(struct adapter *sc)
2742 * T4: only iWARP driver uses the userspace doorbells. There is no need
2743 * to map it if RDMA is disabled.
2745 if (is_t4(sc) && sc->rdmacaps == 0)
2748 sc->udbs_rid = PCIR_BAR(2);
2749 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2750 &sc->udbs_rid, RF_ACTIVE);
2751 if (sc->udbs_res == NULL) {
2752 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2755 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2757 if (chip_id(sc) >= CHELSIO_T5) {
2758 setbit(&sc->doorbells, DOORBELL_UDB);
2759 #if defined(__i386__) || defined(__amd64__)
2760 if (t5_write_combine) {
2764 * Enable write combining on BAR2. This is the
2765 * userspace doorbell BAR and is split into 128B
2766 * (UDBS_SEG_SIZE) doorbell regions, each associated
2767 * with an egress queue. The first 64B has the doorbell
2768 * and the second 64B can be used to submit a tx work
2769 * request with an implicit doorbell.
2772 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2773 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2775 clrbit(&sc->doorbells, DOORBELL_UDB);
2776 setbit(&sc->doorbells, DOORBELL_WCWR);
2777 setbit(&sc->doorbells, DOORBELL_UDBWC);
2779 device_printf(sc->dev,
2780 "couldn't enable write combining: %d\n",
2784 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2785 t4_write_reg(sc, A_SGE_STAT_CFG,
2786 V_STATSOURCE_T5(7) | mode);
2790 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2795 struct memwin_init {
2800 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2801 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2802 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2803 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2806 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2807 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2808 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2809 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2813 setup_memwin(struct adapter *sc)
2815 const struct memwin_init *mw_init;
2822 * Read low 32b of bar0 indirectly via the hardware backdoor
2823 * mechanism. Works from within PCI passthrough environments
2824 * too, where rman_get_start() can return a different value. We
2825 * need to program the T4 memory window decoders with the actual
2826 * addresses that will be coming across the PCIe link.
2828 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2829 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2831 mw_init = &t4_memwin[0];
2833 /* T5+ use the relative offset inside the PCIe BAR */
2836 mw_init = &t5_memwin[0];
2839 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2840 rw_init(&mw->mw_lock, "memory window access");
2841 mw->mw_base = mw_init->base;
2842 mw->mw_aperture = mw_init->aperture;
2845 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2846 (mw->mw_base + bar0) | V_BIR(0) |
2847 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2848 rw_wlock(&mw->mw_lock);
2849 position_memwin(sc, i, 0);
2850 rw_wunlock(&mw->mw_lock);
2854 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2858 * Positions the memory window at the given address in the card's address space.
2859 * There are some alignment requirements and the actual position may be at an
2860 * address prior to the requested address. mw->mw_curpos always has the actual
2861 * position of the window.
2864 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2870 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2871 mw = &sc->memwin[idx];
2872 rw_assert(&mw->mw_lock, RA_WLOCKED);
2876 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2878 pf = V_PFNUM(sc->pf);
2879 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2881 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2882 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2883 t4_read_reg(sc, reg); /* flush */
2887 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2893 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2895 /* Memory can only be accessed in naturally aligned 4 byte units */
2896 if (addr & 3 || len & 3 || len <= 0)
2899 mw = &sc->memwin[idx];
2901 rw_rlock(&mw->mw_lock);
2902 mw_end = mw->mw_curpos + mw->mw_aperture;
2903 if (addr >= mw_end || addr < mw->mw_curpos) {
2904 /* Will need to reposition the window */
2905 if (!rw_try_upgrade(&mw->mw_lock)) {
2906 rw_runlock(&mw->mw_lock);
2907 rw_wlock(&mw->mw_lock);
2909 rw_assert(&mw->mw_lock, RA_WLOCKED);
2910 position_memwin(sc, idx, addr);
2911 rw_downgrade(&mw->mw_lock);
2912 mw_end = mw->mw_curpos + mw->mw_aperture;
2914 rw_assert(&mw->mw_lock, RA_RLOCKED);
2915 while (addr < mw_end && len > 0) {
2917 v = t4_read_reg(sc, mw->mw_base + addr -
2919 *val++ = le32toh(v);
2922 t4_write_reg(sc, mw->mw_base + addr -
2923 mw->mw_curpos, htole32(v));
2928 rw_runlock(&mw->mw_lock);
2935 t4_init_atid_table(struct adapter *sc)
2944 MPASS(t->atid_tab == NULL);
2946 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2948 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2949 t->afree = t->atid_tab;
2950 t->atids_in_use = 0;
2951 for (i = 1; i < t->natids; i++)
2952 t->atid_tab[i - 1].next = &t->atid_tab[i];
2953 t->atid_tab[t->natids - 1].next = NULL;
2957 t4_free_atid_table(struct adapter *sc)
2963 KASSERT(t->atids_in_use == 0,
2964 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2966 if (mtx_initialized(&t->atid_lock))
2967 mtx_destroy(&t->atid_lock);
2968 free(t->atid_tab, M_CXGBE);
2973 alloc_atid(struct adapter *sc, void *ctx)
2975 struct tid_info *t = &sc->tids;
2978 mtx_lock(&t->atid_lock);
2980 union aopen_entry *p = t->afree;
2982 atid = p - t->atid_tab;
2983 MPASS(atid <= M_TID_TID);
2988 mtx_unlock(&t->atid_lock);
2993 lookup_atid(struct adapter *sc, int atid)
2995 struct tid_info *t = &sc->tids;
2997 return (t->atid_tab[atid].data);
3001 free_atid(struct adapter *sc, int atid)
3003 struct tid_info *t = &sc->tids;
3004 union aopen_entry *p = &t->atid_tab[atid];
3006 mtx_lock(&t->atid_lock);
3010 mtx_unlock(&t->atid_lock);
3014 queue_tid_release(struct adapter *sc, int tid)
3017 CXGBE_UNIMPLEMENTED("deferred tid release");
3021 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
3024 struct cpl_tid_release *req;
3026 wr = alloc_wrqe(sizeof(*req), ctrlq);
3028 queue_tid_release(sc, tid); /* defer */
3033 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
3039 t4_range_cmp(const void *a, const void *b)
3041 return ((const struct t4_range *)a)->start -
3042 ((const struct t4_range *)b)->start;
3046 * Verify that the memory range specified by the addr/len pair is valid within
3047 * the card's address space.
3050 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
3052 struct t4_range mem_ranges[4], *r, *next;
3053 uint32_t em, addr_len;
3054 int i, n, remaining;
3056 /* Memory can only be accessed in naturally aligned 4 byte units */
3057 if (addr & 3 || len & 3 || len == 0)
3060 /* Enabled memories */
3061 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3065 bzero(r, sizeof(mem_ranges));
3066 if (em & F_EDRAM0_ENABLE) {
3067 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3068 r->size = G_EDRAM0_SIZE(addr_len) << 20;
3070 r->start = G_EDRAM0_BASE(addr_len) << 20;
3071 if (addr >= r->start &&
3072 addr + len <= r->start + r->size)
3078 if (em & F_EDRAM1_ENABLE) {
3079 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3080 r->size = G_EDRAM1_SIZE(addr_len) << 20;
3082 r->start = G_EDRAM1_BASE(addr_len) << 20;
3083 if (addr >= r->start &&
3084 addr + len <= r->start + r->size)
3090 if (em & F_EXT_MEM_ENABLE) {
3091 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3092 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
3094 r->start = G_EXT_MEM_BASE(addr_len) << 20;
3095 if (addr >= r->start &&
3096 addr + len <= r->start + r->size)
3102 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
3103 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3104 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
3106 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
3107 if (addr >= r->start &&
3108 addr + len <= r->start + r->size)
3114 MPASS(n <= nitems(mem_ranges));
3117 /* Sort and merge the ranges. */
3118 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3120 /* Start from index 0 and examine the next n - 1 entries. */
3122 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3124 MPASS(r->size > 0); /* r is a valid entry. */
3126 MPASS(next->size > 0); /* and so is the next one. */
3128 while (r->start + r->size >= next->start) {
3129 /* Merge the next one into the current entry. */
3130 r->size = max(r->start + r->size,
3131 next->start + next->size) - r->start;
3132 n--; /* One fewer entry in total. */
3133 if (--remaining == 0)
3134 goto done; /* short circuit */
3137 if (next != r + 1) {
3139 * Some entries were merged into r and next
3140 * points to the first valid entry that couldn't
3143 MPASS(next->size > 0); /* must be valid */
3144 memcpy(r + 1, next, remaining * sizeof(*r));
3147 * This so that the foo->size assertion in the
3148 * next iteration of the loop do the right
3149 * thing for entries that were pulled up and are
3152 MPASS(n < nitems(mem_ranges));
3153 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3154 sizeof(struct t4_range));
3159 /* Done merging the ranges. */
3162 for (i = 0; i < n; i++, r++) {
3163 if (addr >= r->start &&
3164 addr + len <= r->start + r->size)
3173 fwmtype_to_hwmtype(int mtype)
3177 case FW_MEMTYPE_EDC0:
3179 case FW_MEMTYPE_EDC1:
3181 case FW_MEMTYPE_EXTMEM:
3183 case FW_MEMTYPE_EXTMEM1:
3186 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3191 * Verify that the memory range specified by the memtype/offset/len pair is
3192 * valid and lies entirely within the memtype specified. The global address of
3193 * the start of the range is returned in addr.
3196 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3199 uint32_t em, addr_len, maddr;
3201 /* Memory can only be accessed in naturally aligned 4 byte units */
3202 if (off & 3 || len & 3 || len == 0)
3205 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3206 switch (fwmtype_to_hwmtype(mtype)) {
3208 if (!(em & F_EDRAM0_ENABLE))
3210 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3211 maddr = G_EDRAM0_BASE(addr_len) << 20;
3214 if (!(em & F_EDRAM1_ENABLE))
3216 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3217 maddr = G_EDRAM1_BASE(addr_len) << 20;
3220 if (!(em & F_EXT_MEM_ENABLE))
3222 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3223 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3226 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3228 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3229 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3235 *addr = maddr + off; /* global address */
3236 return (validate_mem_range(sc, *addr, len));
3240 fixup_devlog_params(struct adapter *sc)
3242 struct devlog_params *dparams = &sc->params.devlog;
3245 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3246 dparams->size, &dparams->addr);
3252 update_nirq(struct intrs_and_queues *iaq, int nports)
3254 int extra = T4_EXTRA_INTR;
3257 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
3258 iaq->nirq += nports * (iaq->num_vis - 1) *
3259 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3260 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3264 * Adjust requirements to fit the number of interrupts available.
3267 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3271 const int nports = sc->params.nports;
3276 bzero(iaq, sizeof(*iaq));
3277 iaq->intr_type = itype;
3278 iaq->num_vis = t4_num_vis;
3279 iaq->ntxq = t4_ntxq;
3280 iaq->ntxq_vi = t4_ntxq_vi;
3281 iaq->nrxq = t4_nrxq;
3282 iaq->nrxq_vi = t4_nrxq_vi;
3283 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3284 if (is_offload(sc) || is_ethoffload(sc)) {
3285 iaq->nofldtxq = t4_nofldtxq;
3286 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3290 if (is_offload(sc)) {
3291 iaq->nofldrxq = t4_nofldrxq;
3292 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3296 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3297 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3300 update_nirq(iaq, nports);
3301 if (iaq->nirq <= navail &&
3302 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3304 * This is the normal case -- there are enough interrupts for
3311 * If extra VIs have been configured try reducing their count and see if
3314 while (iaq->num_vis > 1) {
3316 update_nirq(iaq, nports);
3317 if (iaq->nirq <= navail &&
3318 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3319 device_printf(sc->dev, "virtual interfaces per port "
3320 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3321 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3322 "itype %d, navail %u, nirq %d.\n",
3323 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3324 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3325 itype, navail, iaq->nirq);
3331 * Extra VIs will not be created. Log a message if they were requested.
3333 MPASS(iaq->num_vis == 1);
3334 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3335 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3336 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3337 if (iaq->num_vis != t4_num_vis) {
3338 device_printf(sc->dev, "extra virtual interfaces disabled. "
3339 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3340 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3341 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3342 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3346 * Keep reducing the number of NIC rx queues to the next lower power of
3347 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3351 if (iaq->nrxq > 1) {
3354 } while (!powerof2(iaq->nrxq));
3356 if (iaq->nofldrxq > 1)
3357 iaq->nofldrxq >>= 1;
3359 old_nirq = iaq->nirq;
3360 update_nirq(iaq, nports);
3361 if (iaq->nirq <= navail &&
3362 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3363 device_printf(sc->dev, "running with reduced number of "
3364 "rx queues because of shortage of interrupts. "
3365 "nrxq=%u, nofldrxq=%u. "
3366 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3367 iaq->nofldrxq, itype, navail, iaq->nirq);
3370 } while (old_nirq != iaq->nirq);
3372 /* One interrupt for everything. Ugh. */
3373 device_printf(sc->dev, "running with minimal number of queues. "
3374 "itype %d, navail %u.\n", itype, navail);
3376 MPASS(iaq->nrxq == 1);
3378 if (iaq->nofldrxq > 1)
3381 MPASS(iaq->num_vis > 0);
3382 if (iaq->num_vis > 1) {
3383 MPASS(iaq->nrxq_vi > 0);
3384 MPASS(iaq->ntxq_vi > 0);
3386 MPASS(iaq->nirq > 0);
3387 MPASS(iaq->nrxq > 0);
3388 MPASS(iaq->ntxq > 0);
3389 if (itype == INTR_MSI) {
3390 MPASS(powerof2(iaq->nirq));
3395 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3397 int rc, itype, navail, nalloc;
3399 for (itype = INTR_MSIX; itype; itype >>= 1) {
3401 if ((itype & t4_intr_types) == 0)
3402 continue; /* not allowed */
3404 if (itype == INTR_MSIX)
3405 navail = pci_msix_count(sc->dev);
3406 else if (itype == INTR_MSI)
3407 navail = pci_msi_count(sc->dev);
3414 calculate_iaq(sc, iaq, itype, navail);
3417 if (itype == INTR_MSIX)
3418 rc = pci_alloc_msix(sc->dev, &nalloc);
3419 else if (itype == INTR_MSI)
3420 rc = pci_alloc_msi(sc->dev, &nalloc);
3422 if (rc == 0 && nalloc > 0) {
3423 if (nalloc == iaq->nirq)
3427 * Didn't get the number requested. Use whatever number
3428 * the kernel is willing to allocate.
3430 device_printf(sc->dev, "fewer vectors than requested, "
3431 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3432 itype, iaq->nirq, nalloc);
3433 pci_release_msi(sc->dev);
3438 device_printf(sc->dev,
3439 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3440 itype, rc, iaq->nirq, nalloc);
3443 device_printf(sc->dev,
3444 "failed to find a usable interrupt type. "
3445 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3446 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3451 #define FW_VERSION(chip) ( \
3452 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3453 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3454 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3455 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3456 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3458 /* Just enough of fw_hdr to cover all version info. */
3464 __be32 tp_microcode_ver;
3469 __u8 intfver_iscsipdu;
3471 __u8 intfver_fcoepdu;
3474 /* Spot check a couple of fields. */
3475 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3476 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3477 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3487 .kld_name = "t4fw_cfg",
3488 .fw_mod_name = "t4fw",
3490 .chip = FW_HDR_CHIP_T4,
3491 .fw_ver = htobe32(FW_VERSION(T4)),
3492 .intfver_nic = FW_INTFVER(T4, NIC),
3493 .intfver_vnic = FW_INTFVER(T4, VNIC),
3494 .intfver_ofld = FW_INTFVER(T4, OFLD),
3495 .intfver_ri = FW_INTFVER(T4, RI),
3496 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3497 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3498 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3499 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3503 .kld_name = "t5fw_cfg",
3504 .fw_mod_name = "t5fw",
3506 .chip = FW_HDR_CHIP_T5,
3507 .fw_ver = htobe32(FW_VERSION(T5)),
3508 .intfver_nic = FW_INTFVER(T5, NIC),
3509 .intfver_vnic = FW_INTFVER(T5, VNIC),
3510 .intfver_ofld = FW_INTFVER(T5, OFLD),
3511 .intfver_ri = FW_INTFVER(T5, RI),
3512 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3513 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3514 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3515 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3519 .kld_name = "t6fw_cfg",
3520 .fw_mod_name = "t6fw",
3522 .chip = FW_HDR_CHIP_T6,
3523 .fw_ver = htobe32(FW_VERSION(T6)),
3524 .intfver_nic = FW_INTFVER(T6, NIC),
3525 .intfver_vnic = FW_INTFVER(T6, VNIC),
3526 .intfver_ofld = FW_INTFVER(T6, OFLD),
3527 .intfver_ri = FW_INTFVER(T6, RI),
3528 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3529 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3530 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3531 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3536 static struct fw_info *
3537 find_fw_info(int chip)
3541 for (i = 0; i < nitems(fw_info); i++) {
3542 if (fw_info[i].chip == chip)
3543 return (&fw_info[i]);
3549 * Is the given firmware API compatible with the one the driver was compiled
3553 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3556 /* short circuit if it's the exact same firmware version */
3557 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3561 * XXX: Is this too conservative? Perhaps I should limit this to the
3562 * features that are supported in the driver.
3564 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3565 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3566 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3567 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3575 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3576 const struct firmware **fw)
3578 struct fw_info *fw_info;
3584 fw_info = find_fw_info(chip_id(sc));
3585 if (fw_info == NULL) {
3586 device_printf(sc->dev,
3587 "unable to look up firmware information for chip %d.\n",
3592 *dcfg = firmware_get(fw_info->kld_name);
3593 if (*dcfg != NULL) {
3595 *fw = firmware_get(fw_info->fw_mod_name);
3603 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3604 const struct firmware *fw)
3608 firmware_put(fw, FIRMWARE_UNLOAD);
3610 firmware_put(dcfg, FIRMWARE_UNLOAD);
3615 * 0 means no firmware install attempted.
3616 * ERESTART means a firmware install was attempted and was successful.
3617 * +ve errno means a firmware install was attempted but failed.
3620 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3621 const struct fw_h *drv_fw, const char *reason, int *already)
3623 const struct firmware *cfg, *fw;
3624 const uint32_t c = be32toh(card_fw->fw_ver);
3627 struct fw_h bundled_fw;
3628 bool load_attempted;
3631 load_attempted = false;
3632 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3634 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3635 if (t4_fw_install < 0) {
3636 rc = load_fw_module(sc, &cfg, &fw);
3637 if (rc != 0 || fw == NULL) {
3638 device_printf(sc->dev,
3639 "failed to load firmware module: %d. cfg %p, fw %p;"
3640 " will use compiled-in firmware version for"
3641 "hw.cxgbe.fw_install checks.\n",
3644 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3646 load_attempted = true;
3648 d = be32toh(bundled_fw.fw_ver);
3653 if ((sc->flags & FW_OK) == 0) {
3655 if (c == 0xffffffff) {
3664 if (!fw_compatible(card_fw, &bundled_fw)) {
3665 reason = "incompatible or unusable";
3670 reason = "older than the version bundled with this driver";
3674 if (fw_install == 2 && d != c) {
3675 reason = "different than the version bundled with this driver";
3679 /* No reason to do anything to the firmware already on the card. */
3688 if (fw_install == 0) {
3689 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3690 "but the driver is prohibited from installing a firmware "
3692 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3693 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3699 * We'll attempt to install a firmware. Load the module first (if it
3700 * hasn't been loaded already).
3702 if (!load_attempted) {
3703 rc = load_fw_module(sc, &cfg, &fw);
3704 if (rc != 0 || fw == NULL) {
3705 device_printf(sc->dev,
3706 "failed to load firmware module: %d. cfg %p, fw %p\n",
3712 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3713 "but the driver cannot take corrective action because it "
3714 "is unable to load the firmware module.\n",
3715 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3716 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3717 rc = sc->flags & FW_OK ? 0 : ENOENT;
3720 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3722 MPASS(t4_fw_install > 0);
3723 device_printf(sc->dev,
3724 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3725 "expecting (%u.%u.%u.%u) and will not be used.\n",
3726 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3727 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3728 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3729 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3730 rc = sc->flags & FW_OK ? 0 : EINVAL;
3734 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3735 "installing firmware %u.%u.%u.%u on card.\n",
3736 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3737 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3738 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3739 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3741 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3743 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3745 /* Installed successfully, update the cached header too. */
3747 memcpy(card_fw, fw->data, sizeof(*card_fw));
3750 unload_fw_module(sc, cfg, fw);
3756 * Establish contact with the firmware and attempt to become the master driver.
3758 * A firmware will be installed to the card if needed (if the driver is allowed
3762 contact_firmware(struct adapter *sc)
3764 int rc, already = 0;
3765 enum dev_state state;
3766 struct fw_info *fw_info;
3767 struct fw_hdr *card_fw; /* fw on the card */
3768 const struct fw_h *drv_fw;
3770 fw_info = find_fw_info(chip_id(sc));
3771 if (fw_info == NULL) {
3772 device_printf(sc->dev,
3773 "unable to look up firmware information for chip %d.\n",
3777 drv_fw = &fw_info->fw_h;
3779 /* Read the header of the firmware on the card */
3780 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3782 rc = -t4_get_fw_hdr(sc, card_fw);
3784 device_printf(sc->dev,
3785 "unable to read firmware header from card's flash: %d\n",
3790 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3797 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3798 if (rc < 0 || state == DEV_STATE_ERR) {
3800 device_printf(sc->dev,
3801 "failed to connect to the firmware: %d, %d. "
3802 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3804 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3805 "not responding properly to HELLO", &already) == ERESTART)
3810 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3811 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3814 sc->flags |= MASTER_PF;
3815 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3821 } else if (state == DEV_STATE_UNINIT) {
3823 * We didn't get to be the master so we definitely won't be
3824 * configuring the chip. It's a bug if someone else hasn't
3825 * configured it already.
3827 device_printf(sc->dev, "couldn't be master(%d), "
3828 "device not already initialized either(%d). "
3829 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3834 * Some other PF is the master and has configured the chip.
3835 * This is allowed but untested.
3837 device_printf(sc->dev, "PF%d is master, device state %d. "
3838 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3839 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3844 if (rc != 0 && sc->flags & FW_OK) {
3845 t4_fw_bye(sc, sc->mbox);
3846 sc->flags &= ~FW_OK;
3848 free(card_fw, M_CXGBE);
3853 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3854 uint32_t mtype, uint32_t moff)
3856 struct fw_info *fw_info;
3857 const struct firmware *dcfg, *rcfg = NULL;
3858 const uint32_t *cfdata;
3859 uint32_t cflen, addr;
3862 load_fw_module(sc, &dcfg, NULL);
3864 /* Card specific interpretation of "default". */
3865 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3866 if (pci_get_device(sc->dev) == 0x440a)
3867 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3869 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3872 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3874 device_printf(sc->dev,
3875 "KLD with default config is not available.\n");
3879 cfdata = dcfg->data;
3880 cflen = dcfg->datasize & ~3;
3884 fw_info = find_fw_info(chip_id(sc));
3885 if (fw_info == NULL) {
3886 device_printf(sc->dev,
3887 "unable to look up firmware information for chip %d.\n",
3892 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
3894 rcfg = firmware_get(s);
3896 device_printf(sc->dev,
3897 "unable to load module \"%s\" for configuration "
3898 "profile \"%s\".\n", s, cfg_file);
3902 cfdata = rcfg->data;
3903 cflen = rcfg->datasize & ~3;
3906 if (cflen > FLASH_CFG_MAX_SIZE) {
3907 device_printf(sc->dev,
3908 "config file too long (%d, max allowed is %d).\n",
3909 cflen, FLASH_CFG_MAX_SIZE);
3914 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3916 device_printf(sc->dev,
3917 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
3918 __func__, mtype, moff, cflen, rc);
3922 write_via_memwin(sc, 2, addr, cfdata, cflen);
3925 firmware_put(rcfg, FIRMWARE_UNLOAD);
3926 unload_fw_module(sc, dcfg, NULL);
3930 struct caps_allowed {
3933 uint16_t switchcaps;
3937 uint16_t cryptocaps;
3942 #define FW_PARAM_DEV(param) \
3943 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3944 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3945 #define FW_PARAM_PFVF(param) \
3946 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3947 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3950 * Provide a configuration profile to the firmware and have it initialize the
3951 * chip accordingly. This may involve uploading a configuration file to the
3955 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
3956 const struct caps_allowed *caps_allowed)
3959 struct fw_caps_config_cmd caps;
3960 uint32_t mtype, moff, finicsum, cfcsum, param, val;
3962 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3964 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3968 bzero(&caps, sizeof(caps));
3969 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3970 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3971 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
3974 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3975 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
3976 mtype = FW_MEMTYPE_FLASH;
3977 moff = t4_flash_cfg_addr(sc);
3978 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3979 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3980 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3984 * Ask the firmware where it wants us to upload the config file.
3986 param = FW_PARAM_DEV(CF);
3987 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3989 /* No support for config file? Shouldn't happen. */
3990 device_printf(sc->dev,
3991 "failed to query config file location: %d.\n", rc);
3994 mtype = G_FW_PARAMS_PARAM_Y(val);
3995 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3996 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3997 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3998 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4001 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
4003 device_printf(sc->dev,
4004 "failed to upload config file to card: %d.\n", rc);
4008 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4010 device_printf(sc->dev, "failed to pre-process config file: %d "
4011 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
4015 finicsum = be32toh(caps.finicsum);
4016 cfcsum = be32toh(caps.cfcsum); /* actual */
4017 if (finicsum != cfcsum) {
4018 device_printf(sc->dev,
4019 "WARNING: config file checksum mismatch: %08x %08x\n",
4022 sc->cfcsum = cfcsum;
4023 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
4026 * Let the firmware know what features will (not) be used so it can tune
4027 * things accordingly.
4029 #define LIMIT_CAPS(x) do { \
4030 caps.x##caps &= htobe16(caps_allowed->x##caps); \
4042 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4044 * TOE and hashfilters are mutually exclusive. It is a config
4045 * file or firmware bug if both are reported as available. Try
4046 * to cope with the situation in non-debug builds by disabling
4049 MPASS(caps.toecaps == 0);
4056 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4057 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4058 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4059 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
4061 device_printf(sc->dev,
4062 "failed to process config file: %d.\n", rc);
4066 t4_tweak_chip_settings(sc);
4067 set_params__pre_init(sc);
4069 /* get basic stuff going */
4070 rc = -t4_fw_initialize(sc, sc->mbox);
4072 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
4080 * Partition chip resources for use between various PFs, VFs, etc.
4083 partition_resources(struct adapter *sc)
4085 char cfg_file[sizeof(t4_cfg_file)];
4086 struct caps_allowed caps_allowed;
4090 /* Only the master driver gets to configure the chip resources. */
4091 MPASS(sc->flags & MASTER_PF);
4093 #define COPY_CAPS(x) do { \
4094 caps_allowed.x##caps = t4_##x##caps_allowed; \
4096 bzero(&caps_allowed, sizeof(caps_allowed));
4106 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
4107 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
4109 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
4110 if (rc != 0 && fallback) {
4111 device_printf(sc->dev,
4112 "failed (%d) to configure card with \"%s\" profile, "
4113 "will fall back to a basic configuration and retry.\n",
4115 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
4116 bzero(&caps_allowed, sizeof(caps_allowed));
4118 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
4127 * Retrieve parameters that are needed (or nice to have) very early.
4130 get_params__pre_init(struct adapter *sc)
4133 uint32_t param[2], val[2];
4135 t4_get_version_info(sc);
4137 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4138 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4139 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4140 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4141 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4143 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4144 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4145 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4146 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4147 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4149 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4150 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4151 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4152 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4153 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4155 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4156 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4157 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4158 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4159 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4161 param[0] = FW_PARAM_DEV(PORTVEC);
4162 param[1] = FW_PARAM_DEV(CCLK);
4163 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4165 device_printf(sc->dev,
4166 "failed to query parameters (pre_init): %d.\n", rc);
4170 sc->params.portvec = val[0];
4171 sc->params.nports = bitcount32(val[0]);
4172 sc->params.vpd.cclk = val[1];
4174 /* Read device log parameters. */
4175 rc = -t4_init_devlog_params(sc, 1);
4177 fixup_devlog_params(sc);
4179 device_printf(sc->dev,
4180 "failed to get devlog parameters: %d.\n", rc);
4181 rc = 0; /* devlog isn't critical for device operation */
4188 * Any params that need to be set before FW_INITIALIZE.
4191 set_params__pre_init(struct adapter *sc)
4194 uint32_t param, val;
4196 if (chip_id(sc) >= CHELSIO_T6) {
4197 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
4199 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4200 /* firmwares < 1.20.1.0 do not have this param. */
4201 if (rc == FW_EINVAL && sc->params.fw_vers <
4202 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4203 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) {
4207 device_printf(sc->dev,
4208 "failed to enable high priority filters :%d.\n",
4213 /* Enable opaque VIIDs with firmwares that support it. */
4214 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4216 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4217 if (rc == 0 && val == 1)
4218 sc->params.viid_smt_extn_support = true;
4220 sc->params.viid_smt_extn_support = false;
4226 * Retrieve various parameters that are of interest to the driver. The device
4227 * has been initialized by the firmware at this point.
4230 get_params__post_init(struct adapter *sc)
4233 uint32_t param[7], val[7];
4234 struct fw_caps_config_cmd caps;
4236 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4237 param[1] = FW_PARAM_PFVF(EQ_START);
4238 param[2] = FW_PARAM_PFVF(FILTER_START);
4239 param[3] = FW_PARAM_PFVF(FILTER_END);
4240 param[4] = FW_PARAM_PFVF(L2T_START);
4241 param[5] = FW_PARAM_PFVF(L2T_END);
4242 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4243 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4244 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4245 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4247 device_printf(sc->dev,
4248 "failed to query parameters (post_init): %d.\n", rc);
4252 sc->sge.iq_start = val[0];
4253 sc->sge.eq_start = val[1];
4254 if ((int)val[3] > (int)val[2]) {
4255 sc->tids.ftid_base = val[2];
4256 sc->tids.ftid_end = val[3];
4257 sc->tids.nftids = val[3] - val[2] + 1;
4259 sc->vres.l2t.start = val[4];
4260 sc->vres.l2t.size = val[5] - val[4] + 1;
4261 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4262 ("%s: L2 table size (%u) larger than expected (%u)",
4263 __func__, sc->vres.l2t.size, L2T_SIZE));
4264 sc->params.core_vdd = val[6];
4266 if (chip_id(sc) >= CHELSIO_T6) {
4268 sc->tids.tid_base = t4_read_reg(sc,
4269 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4271 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4272 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4273 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4275 device_printf(sc->dev,
4276 "failed to query hpfilter parameters: %d.\n", rc);
4279 if ((int)val[1] > (int)val[0]) {
4280 sc->tids.hpftid_base = val[0];
4281 sc->tids.hpftid_end = val[1];
4282 sc->tids.nhpftids = val[1] - val[0] + 1;
4285 * These should go off if the layout changes and the
4286 * driver needs to catch up.
4288 MPASS(sc->tids.hpftid_base == 0);
4289 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4294 * MPSBGMAP is queried separately because only recent firmwares support
4295 * it as a parameter and we don't want the compound query above to fail
4296 * on older firmwares.
4298 param[0] = FW_PARAM_DEV(MPSBGMAP);
4300 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4302 sc->params.mps_bg_map = val[0];
4304 sc->params.mps_bg_map = 0;
4307 * Determine whether the firmware supports the filter2 work request.
4308 * This is queried separately for the same reason as MPSBGMAP above.
4310 param[0] = FW_PARAM_DEV(FILTER2_WR);
4312 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4314 sc->params.filter2_wr_support = val[0] != 0;
4316 sc->params.filter2_wr_support = 0;
4319 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4320 * This is queried separately for the same reason as other params above.
4322 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4324 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4326 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4328 sc->params.ulptx_memwrite_dsgl = false;
4330 /* get capabilites */
4331 bzero(&caps, sizeof(caps));
4332 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4333 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4334 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4335 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4337 device_printf(sc->dev,
4338 "failed to get card capabilities: %d.\n", rc);
4342 #define READ_CAPS(x) do { \
4343 sc->x = htobe16(caps.x); \
4346 READ_CAPS(linkcaps);
4347 READ_CAPS(switchcaps);
4350 READ_CAPS(rdmacaps);
4351 READ_CAPS(cryptocaps);
4352 READ_CAPS(iscsicaps);
4353 READ_CAPS(fcoecaps);
4355 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4356 MPASS(chip_id(sc) > CHELSIO_T4);
4357 MPASS(sc->toecaps == 0);
4360 param[0] = FW_PARAM_DEV(NTID);
4361 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4363 device_printf(sc->dev,
4364 "failed to query HASHFILTER parameters: %d.\n", rc);
4367 sc->tids.ntids = val[0];
4368 if (sc->params.fw_vers <
4369 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4370 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4371 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4372 sc->tids.ntids -= sc->tids.nhpftids;
4374 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4375 sc->params.hash_filter = 1;
4377 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4378 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4379 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4380 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4381 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4383 device_printf(sc->dev,
4384 "failed to query NIC parameters: %d.\n", rc);
4387 if ((int)val[1] > (int)val[0]) {
4388 sc->tids.etid_base = val[0];
4389 sc->tids.etid_end = val[1];
4390 sc->tids.netids = val[1] - val[0] + 1;
4391 sc->params.eo_wr_cred = val[2];
4392 sc->params.ethoffload = 1;
4396 /* query offload-related parameters */
4397 param[0] = FW_PARAM_DEV(NTID);
4398 param[1] = FW_PARAM_PFVF(SERVER_START);
4399 param[2] = FW_PARAM_PFVF(SERVER_END);
4400 param[3] = FW_PARAM_PFVF(TDDP_START);
4401 param[4] = FW_PARAM_PFVF(TDDP_END);
4402 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4403 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4405 device_printf(sc->dev,
4406 "failed to query TOE parameters: %d.\n", rc);
4409 sc->tids.ntids = val[0];
4410 if (sc->params.fw_vers <
4411 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4412 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4413 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4414 sc->tids.ntids -= sc->tids.nhpftids;
4416 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4417 if ((int)val[2] > (int)val[1]) {
4418 sc->tids.stid_base = val[1];
4419 sc->tids.nstids = val[2] - val[1] + 1;
4421 sc->vres.ddp.start = val[3];
4422 sc->vres.ddp.size = val[4] - val[3] + 1;
4423 sc->params.ofldq_wr_cred = val[5];
4424 sc->params.offload = 1;
4427 * The firmware attempts memfree TOE configuration for -SO cards
4428 * and will report toecaps=0 if it runs out of resources (this
4429 * depends on the config file). It may not report 0 for other
4430 * capabilities dependent on the TOE in this case. Set them to
4431 * 0 here so that the driver doesn't bother tracking resources
4432 * that will never be used.
4438 param[0] = FW_PARAM_PFVF(STAG_START);
4439 param[1] = FW_PARAM_PFVF(STAG_END);
4440 param[2] = FW_PARAM_PFVF(RQ_START);
4441 param[3] = FW_PARAM_PFVF(RQ_END);
4442 param[4] = FW_PARAM_PFVF(PBL_START);
4443 param[5] = FW_PARAM_PFVF(PBL_END);
4444 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4446 device_printf(sc->dev,
4447 "failed to query RDMA parameters(1): %d.\n", rc);
4450 sc->vres.stag.start = val[0];
4451 sc->vres.stag.size = val[1] - val[0] + 1;
4452 sc->vres.rq.start = val[2];
4453 sc->vres.rq.size = val[3] - val[2] + 1;
4454 sc->vres.pbl.start = val[4];
4455 sc->vres.pbl.size = val[5] - val[4] + 1;
4457 param[0] = FW_PARAM_PFVF(SQRQ_START);
4458 param[1] = FW_PARAM_PFVF(SQRQ_END);
4459 param[2] = FW_PARAM_PFVF(CQ_START);
4460 param[3] = FW_PARAM_PFVF(CQ_END);
4461 param[4] = FW_PARAM_PFVF(OCQ_START);
4462 param[5] = FW_PARAM_PFVF(OCQ_END);
4463 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4465 device_printf(sc->dev,
4466 "failed to query RDMA parameters(2): %d.\n", rc);
4469 sc->vres.qp.start = val[0];
4470 sc->vres.qp.size = val[1] - val[0] + 1;
4471 sc->vres.cq.start = val[2];
4472 sc->vres.cq.size = val[3] - val[2] + 1;
4473 sc->vres.ocq.start = val[4];
4474 sc->vres.ocq.size = val[5] - val[4] + 1;
4476 param[0] = FW_PARAM_PFVF(SRQ_START);
4477 param[1] = FW_PARAM_PFVF(SRQ_END);
4478 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4479 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4480 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4482 device_printf(sc->dev,
4483 "failed to query RDMA parameters(3): %d.\n", rc);
4486 sc->vres.srq.start = val[0];
4487 sc->vres.srq.size = val[1] - val[0] + 1;
4488 sc->params.max_ordird_qp = val[2];
4489 sc->params.max_ird_adapter = val[3];
4491 if (sc->iscsicaps) {
4492 param[0] = FW_PARAM_PFVF(ISCSI_START);
4493 param[1] = FW_PARAM_PFVF(ISCSI_END);
4494 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4496 device_printf(sc->dev,
4497 "failed to query iSCSI parameters: %d.\n", rc);
4500 sc->vres.iscsi.start = val[0];
4501 sc->vres.iscsi.size = val[1] - val[0] + 1;
4503 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4504 param[0] = FW_PARAM_PFVF(TLS_START);
4505 param[1] = FW_PARAM_PFVF(TLS_END);
4506 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4508 device_printf(sc->dev,
4509 "failed to query TLS parameters: %d.\n", rc);
4512 sc->vres.key.start = val[0];
4513 sc->vres.key.size = val[1] - val[0] + 1;
4516 t4_init_sge_params(sc);
4519 * We've got the params we wanted to query via the firmware. Now grab
4520 * some others directly from the chip.
4522 rc = t4_read_chip_settings(sc);
4528 set_params__post_init(struct adapter *sc)
4530 uint32_t param, val;
4535 /* ask for encapsulated CPLs */
4536 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4538 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4540 /* Enable 32b port caps if the firmware supports it. */
4541 param = FW_PARAM_PFVF(PORT_CAPS32);
4543 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4544 sc->params.port_caps32 = 1;
4546 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4547 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4548 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4549 V_MASKFILTER(val - 1));
4553 * Override the TOE timers with user provided tunables. This is not the
4554 * recommended way to change the timers (the firmware config file is) so
4555 * these tunables are not documented.
4557 * All the timer tunables are in microseconds.
4559 if (t4_toe_keepalive_idle != 0) {
4560 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4561 v &= M_KEEPALIVEIDLE;
4562 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4563 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4565 if (t4_toe_keepalive_interval != 0) {
4566 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4567 v &= M_KEEPALIVEINTVL;
4568 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4569 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4571 if (t4_toe_keepalive_count != 0) {
4572 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4573 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4574 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4575 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4576 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4578 if (t4_toe_rexmt_min != 0) {
4579 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4581 t4_set_reg_field(sc, A_TP_RXT_MIN,
4582 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4584 if (t4_toe_rexmt_max != 0) {
4585 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4587 t4_set_reg_field(sc, A_TP_RXT_MAX,
4588 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4590 if (t4_toe_rexmt_count != 0) {
4591 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4592 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4593 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4594 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4595 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4597 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4598 if (t4_toe_rexmt_backoff[i] != -1) {
4599 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4600 shift = (i & 3) << 3;
4601 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4602 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4609 #undef FW_PARAM_PFVF
4613 t4_set_desc(struct adapter *sc)
4616 struct adapter_params *p = &sc->params;
4618 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4620 device_set_desc_copy(sc->dev, buf);
4624 ifmedia_add4(struct ifmedia *ifm, int m)
4627 ifmedia_add(ifm, m, 0, NULL);
4628 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4629 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4630 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4634 * This is the selected media, which is not quite the same as the active media.
4635 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4636 * and active are not the same, and "media: Ethernet selected" otherwise.
4639 set_current_media(struct port_info *pi)
4641 struct link_config *lc;
4642 struct ifmedia *ifm;
4646 PORT_LOCK_ASSERT_OWNED(pi);
4648 /* Leave current media alone if it's already set to IFM_NONE. */
4650 if (ifm->ifm_cur != NULL &&
4651 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4655 if (lc->requested_aneg != AUTONEG_DISABLE &&
4656 lc->supported & FW_PORT_CAP32_ANEG) {
4657 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4660 mword = IFM_ETHER | IFM_FDX;
4661 if (lc->requested_fc & PAUSE_TX)
4662 mword |= IFM_ETH_TXPAUSE;
4663 if (lc->requested_fc & PAUSE_RX)
4664 mword |= IFM_ETH_RXPAUSE;
4665 if (lc->requested_speed == 0)
4666 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4668 speed = lc->requested_speed;
4669 mword |= port_mword(pi, speed_to_fwcap(speed));
4670 ifmedia_set(ifm, mword);
4674 * Returns true if the ifmedia list for the port cannot change.
4677 fixed_ifmedia(struct port_info *pi)
4680 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4681 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4682 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4683 pi->port_type == FW_PORT_TYPE_KX4 ||
4684 pi->port_type == FW_PORT_TYPE_KX ||
4685 pi->port_type == FW_PORT_TYPE_KR ||
4686 pi->port_type == FW_PORT_TYPE_BP_AP ||
4687 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4688 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4689 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4690 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4691 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4695 build_medialist(struct port_info *pi)
4698 int unknown, mword, bit;
4699 struct link_config *lc;
4700 struct ifmedia *ifm;
4702 PORT_LOCK_ASSERT_OWNED(pi);
4704 if (pi->flags & FIXED_IFMEDIA)
4708 * Rebuild the ifmedia list.
4711 ifmedia_removeall(ifm);
4713 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4714 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4717 MPASS(LIST_EMPTY(&ifm->ifm_list));
4718 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4719 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4724 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4726 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4728 mword = port_mword(pi, speed);
4729 if (mword == IFM_NONE) {
4731 } else if (mword == IFM_UNKNOWN)
4734 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4737 if (unknown > 0) /* Add one unknown for all unknown media types. */
4738 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4739 if (lc->supported & FW_PORT_CAP32_ANEG)
4740 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4742 set_current_media(pi);
4746 * Initialize the requested fields in the link config based on driver tunables.
4749 init_link_config(struct port_info *pi)
4751 struct link_config *lc = &pi->link_cfg;
4753 PORT_LOCK_ASSERT_OWNED(pi);
4755 lc->requested_speed = 0;
4757 if (t4_autoneg == 0)
4758 lc->requested_aneg = AUTONEG_DISABLE;
4759 else if (t4_autoneg == 1)
4760 lc->requested_aneg = AUTONEG_ENABLE;
4762 lc->requested_aneg = AUTONEG_AUTO;
4764 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4767 if (t4_fec == -1 || t4_fec & FEC_AUTO)
4768 lc->requested_fec = FEC_AUTO;
4770 lc->requested_fec = FEC_NONE;
4771 if (t4_fec & FEC_RS)
4772 lc->requested_fec |= FEC_RS;
4773 if (t4_fec & FEC_BASER_RS)
4774 lc->requested_fec |= FEC_BASER_RS;
4779 * Makes sure that all requested settings comply with what's supported by the
4780 * port. Returns the number of settings that were invalid and had to be fixed.
4783 fixup_link_config(struct port_info *pi)
4786 struct link_config *lc = &pi->link_cfg;
4789 PORT_LOCK_ASSERT_OWNED(pi);
4791 /* Speed (when not autonegotiating) */
4792 if (lc->requested_speed != 0) {
4793 fwspeed = speed_to_fwcap(lc->requested_speed);
4794 if ((fwspeed & lc->supported) == 0) {
4796 lc->requested_speed = 0;
4800 /* Link autonegotiation */
4801 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4802 lc->requested_aneg == AUTONEG_DISABLE ||
4803 lc->requested_aneg == AUTONEG_AUTO);
4804 if (lc->requested_aneg == AUTONEG_ENABLE &&
4805 !(lc->supported & FW_PORT_CAP32_ANEG)) {
4807 lc->requested_aneg = AUTONEG_AUTO;
4811 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4812 if (lc->requested_fc & PAUSE_TX &&
4813 !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4815 lc->requested_fc &= ~PAUSE_TX;
4817 if (lc->requested_fc & PAUSE_RX &&
4818 !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4820 lc->requested_fc &= ~PAUSE_RX;
4822 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4823 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4825 lc->requested_fc |= PAUSE_AUTONEG;
4829 if ((lc->requested_fec & FEC_RS &&
4830 !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4831 (lc->requested_fec & FEC_BASER_RS &&
4832 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4834 lc->requested_fec = FEC_AUTO;
4841 * Apply the requested L1 settings, which are expected to be valid, to the
4845 apply_link_config(struct port_info *pi)
4847 struct adapter *sc = pi->adapter;
4848 struct link_config *lc = &pi->link_cfg;
4852 ASSERT_SYNCHRONIZED_OP(sc);
4853 PORT_LOCK_ASSERT_OWNED(pi);
4855 if (lc->requested_aneg == AUTONEG_ENABLE)
4856 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4857 if (!(lc->requested_fc & PAUSE_AUTONEG))
4858 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4859 if (lc->requested_fc & PAUSE_TX)
4860 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4861 if (lc->requested_fc & PAUSE_RX)
4862 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4863 if (lc->requested_fec & FEC_RS)
4864 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4865 if (lc->requested_fec & FEC_BASER_RS)
4866 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4868 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4870 /* Don't complain if the VF driver gets back an EPERM. */
4871 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
4872 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4875 * An L1_CFG will almost always result in a link-change event if
4876 * the link is up, and the driver will refresh the actual
4877 * fec/fc/etc. when the notification is processed. If the link
4878 * is down then the actual settings are meaningless.
4880 * This takes care of the case where a change in the L1 settings
4881 * may not result in a notification.
4883 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4884 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4889 #define FW_MAC_EXACT_CHUNK 7
4892 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4900 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
4902 struct mcaddr_ctx *ctx = arg;
4903 struct vi_info *vi = ctx->ifp->if_softc;
4904 struct port_info *pi = vi->pi;
4905 struct adapter *sc = pi->adapter;
4910 ctx->mcaddr[ctx->i] = LLADDR(sdl);
4911 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
4914 if (ctx->i == FW_MAC_EXACT_CHUNK) {
4915 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
4916 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
4920 for (j = 0; j < ctx->i; j++) {
4922 "failed to add mc address"
4924 "%02x:%02x:%02x rc=%d\n",
4925 ctx->mcaddr[j][0], ctx->mcaddr[j][1],
4926 ctx->mcaddr[j][2], ctx->mcaddr[j][3],
4927 ctx->mcaddr[j][4], ctx->mcaddr[j][5],
4940 * Program the port's XGMAC based on parameters in ifnet. The caller also
4941 * indicates which parameters should be programmed (the rest are left alone).
4944 update_mac_settings(struct ifnet *ifp, int flags)
4947 struct vi_info *vi = ifp->if_softc;
4948 struct port_info *pi = vi->pi;
4949 struct adapter *sc = pi->adapter;
4950 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4952 ASSERT_SYNCHRONIZED_OP(sc);
4953 KASSERT(flags, ("%s: not told what to update.", __func__));
4955 if (flags & XGMAC_MTU)
4958 if (flags & XGMAC_PROMISC)
4959 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4961 if (flags & XGMAC_ALLMULTI)
4962 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4964 if (flags & XGMAC_VLANEX)
4965 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4967 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4968 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4969 allmulti, 1, vlanex, false);
4971 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4977 if (flags & XGMAC_UCADDR) {
4978 uint8_t ucaddr[ETHER_ADDR_LEN];
4980 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4981 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4982 ucaddr, true, &vi->smt_idx);
4985 if_printf(ifp, "change_mac failed: %d\n", rc);
4988 vi->xact_addr_filt = rc;
4993 if (flags & XGMAC_MCADDRS) {
4994 struct epoch_tracker et;
4995 struct mcaddr_ctx ctx;
5003 * Unlike other drivers, we accumulate list of pointers into
5004 * interface address lists and we need to keep it safe even
5005 * after if_foreach_llmaddr() returns, thus we must enter the
5008 NET_EPOCH_ENTER(et);
5009 if_foreach_llmaddr(ifp, add_maddr, &ctx);
5016 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
5017 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
5021 for (j = 0; j < ctx.i; j++) {
5023 "failed to add mc address"
5025 "%02x:%02x:%02x rc=%d\n",
5026 ctx.mcaddr[j][0], ctx.mcaddr[j][1],
5027 ctx.mcaddr[j][2], ctx.mcaddr[j][3],
5028 ctx.mcaddr[j][4], ctx.mcaddr[j][5],
5036 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
5038 if_printf(ifp, "failed to set mc address hash: %d", rc);
5045 * {begin|end}_synchronized_op must be called from the same thread.
5048 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
5054 /* the caller thinks it's ok to sleep, but is it really? */
5055 if (flags & SLEEP_OK)
5056 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
5057 "begin_synchronized_op");
5068 if (vi && IS_DOOMED(vi)) {
5078 if (!(flags & SLEEP_OK)) {
5083 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
5089 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
5092 sc->last_op = wmesg;
5093 sc->last_op_thr = curthread;
5094 sc->last_op_flags = flags;
5098 if (!(flags & HOLD_LOCK) || rc)
5105 * Tell if_ioctl and if_init that the VI is going away. This is
5106 * special variant of begin_synchronized_op and must be paired with a
5107 * call to end_synchronized_op.
5110 doom_vi(struct adapter *sc, struct vi_info *vi)
5117 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
5120 sc->last_op = "t4detach";
5121 sc->last_op_thr = curthread;
5122 sc->last_op_flags = 0;
5128 * {begin|end}_synchronized_op must be called from the same thread.
5131 end_synchronized_op(struct adapter *sc, int flags)
5134 if (flags & LOCK_HELD)
5135 ADAPTER_LOCK_ASSERT_OWNED(sc);
5139 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
5146 cxgbe_init_synchronized(struct vi_info *vi)
5148 struct port_info *pi = vi->pi;
5149 struct adapter *sc = pi->adapter;
5150 struct ifnet *ifp = vi->ifp;
5152 struct sge_txq *txq;
5154 ASSERT_SYNCHRONIZED_OP(sc);
5156 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5157 return (0); /* already running */
5159 if (!(sc->flags & FULL_INIT_DONE) &&
5160 ((rc = adapter_full_init(sc)) != 0))
5161 return (rc); /* error message displayed already */
5163 if (!(vi->flags & VI_INIT_DONE) &&
5164 ((rc = vi_full_init(vi)) != 0))
5165 return (rc); /* error message displayed already */
5167 rc = update_mac_settings(ifp, XGMAC_ALL);
5169 goto done; /* error message displayed already */
5172 if (pi->up_vis == 0) {
5173 t4_update_port_info(pi);
5174 fixup_link_config(pi);
5175 build_medialist(pi);
5176 apply_link_config(pi);
5179 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5181 if_printf(ifp, "enable_vi failed: %d\n", rc);
5187 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5191 for_each_txq(vi, i, txq) {
5193 txq->eq.flags |= EQ_ENABLED;
5198 * The first iq of the first port to come up is used for tracing.
5200 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5201 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5202 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5203 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5204 V_QUEUENUMBER(sc->traceq));
5205 pi->flags |= HAS_TRACEQ;
5210 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5212 if (pi->nvi > 1 || sc->flags & IS_VF)
5213 callout_reset(&vi->tick, hz, vi_tick, vi);
5215 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5216 if (pi->link_cfg.link_ok)
5217 t4_os_link_changed(pi);
5221 cxgbe_uninit_synchronized(vi);
5230 cxgbe_uninit_synchronized(struct vi_info *vi)
5232 struct port_info *pi = vi->pi;
5233 struct adapter *sc = pi->adapter;
5234 struct ifnet *ifp = vi->ifp;
5236 struct sge_txq *txq;
5238 ASSERT_SYNCHRONIZED_OP(sc);
5240 if (!(vi->flags & VI_INIT_DONE)) {
5241 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5242 KASSERT(0, ("uninited VI is running"));
5243 if_printf(ifp, "uninited VI with running ifnet. "
5244 "vi->flags 0x%016lx, if_flags 0x%08x, "
5245 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5252 * Disable the VI so that all its data in either direction is discarded
5253 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5254 * tick) intact as the TP can deliver negative advice or data that it's
5255 * holding in its RAM (for an offloaded connection) even after the VI is
5258 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5260 if_printf(ifp, "disable_vi failed: %d\n", rc);
5264 for_each_txq(vi, i, txq) {
5266 txq->eq.flags &= ~EQ_ENABLED;
5271 if (pi->nvi > 1 || sc->flags & IS_VF)
5272 callout_stop(&vi->tick);
5274 callout_stop(&pi->tick);
5275 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5281 if (pi->up_vis > 0) {
5286 pi->link_cfg.link_ok = false;
5287 pi->link_cfg.speed = 0;
5288 pi->link_cfg.link_down_rc = 255;
5289 t4_os_link_changed(pi);
5296 * It is ok for this function to fail midway and return right away. t4_detach
5297 * will walk the entire sc->irq list and clean up whatever is valid.
5300 t4_setup_intr_handlers(struct adapter *sc)
5302 int rc, rid, p, q, v;
5305 struct port_info *pi;
5307 struct sge *sge = &sc->sge;
5308 struct sge_rxq *rxq;
5310 struct sge_ofld_rxq *ofld_rxq;
5313 struct sge_nm_rxq *nm_rxq;
5316 int nbuckets = rss_getnumbuckets();
5323 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5324 if (forwarding_intr_to_fwq(sc))
5325 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5327 /* Multiple interrupts. */
5328 if (sc->flags & IS_VF)
5329 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5330 ("%s: too few intr.", __func__));
5332 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5333 ("%s: too few intr.", __func__));
5335 /* The first one is always error intr on PFs */
5336 if (!(sc->flags & IS_VF)) {
5337 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5344 /* The second one is always the firmware event queue (first on VFs) */
5345 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5351 for_each_port(sc, p) {
5353 for_each_vi(pi, v, vi) {
5354 vi->first_intr = rid - 1;
5356 if (vi->nnmrxq > 0) {
5357 int n = max(vi->nrxq, vi->nnmrxq);
5359 rxq = &sge->rxq[vi->first_rxq];
5361 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5363 for (q = 0; q < n; q++) {
5364 snprintf(s, sizeof(s), "%x%c%x", p,
5370 irq->nm_rxq = nm_rxq++;
5372 if (irq->nm_rxq != NULL &&
5374 /* Netmap rx only */
5375 rc = t4_alloc_irq(sc, irq, rid,
5376 t4_nm_intr, irq->nm_rxq, s);
5378 if (irq->nm_rxq != NULL &&
5380 /* NIC and Netmap rx */
5381 rc = t4_alloc_irq(sc, irq, rid,
5382 t4_vi_intr, irq, s);
5385 if (irq->rxq != NULL &&
5386 irq->nm_rxq == NULL) {
5388 rc = t4_alloc_irq(sc, irq, rid,
5389 t4_intr, irq->rxq, s);
5395 bus_bind_intr(sc->dev, irq->res,
5396 rss_getcpu(q % nbuckets));
5404 for_each_rxq(vi, q, rxq) {
5405 snprintf(s, sizeof(s), "%x%c%x", p,
5407 rc = t4_alloc_irq(sc, irq, rid,
5412 bus_bind_intr(sc->dev, irq->res,
5413 rss_getcpu(q % nbuckets));
5421 for_each_ofld_rxq(vi, q, ofld_rxq) {
5422 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5423 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5434 MPASS(irq == &sc->irq[sc->intr_count]);
5440 adapter_full_init(struct adapter *sc)
5444 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5445 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5448 ASSERT_SYNCHRONIZED_OP(sc);
5449 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5450 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5451 ("%s: FULL_INIT_DONE already", __func__));
5454 * queues that belong to the adapter (not any particular port).
5456 rc = t4_setup_adapter_queues(sc);
5460 for (i = 0; i < nitems(sc->tq); i++) {
5461 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5462 taskqueue_thread_enqueue, &sc->tq[i]);
5463 if (sc->tq[i] == NULL) {
5464 device_printf(sc->dev,
5465 "failed to allocate task queue %d\n", i);
5469 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5470 device_get_nameunit(sc->dev), i);
5473 MPASS(RSS_KEYSIZE == 40);
5474 rss_getkey((void *)&raw_rss_key[0]);
5475 for (i = 0; i < nitems(rss_key); i++) {
5476 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5478 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5481 if (!(sc->flags & IS_VF))
5483 sc->flags |= FULL_INIT_DONE;
5486 adapter_full_uninit(sc);
5492 adapter_full_uninit(struct adapter *sc)
5496 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5498 t4_teardown_adapter_queues(sc);
5500 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5501 taskqueue_free(sc->tq[i]);
5505 sc->flags &= ~FULL_INIT_DONE;
5511 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5512 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5513 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5514 RSS_HASHTYPE_RSS_UDP_IPV6)
5516 /* Translates kernel hash types to hardware. */
5518 hashconfig_to_hashen(int hashconfig)
5522 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5523 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5524 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5525 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5526 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5527 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5528 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5530 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5531 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5532 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5534 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5535 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5536 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5537 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5542 /* Translates hardware hash types to kernel. */
5544 hashen_to_hashconfig(int hashen)
5548 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5550 * If UDP hashing was enabled it must have been enabled for
5551 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5552 * enabling any 4-tuple hash is nonsense configuration.
5554 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5555 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5557 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5558 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5559 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5560 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5562 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5563 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5564 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5565 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5566 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5567 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5568 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5569 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5571 return (hashconfig);
5576 vi_full_init(struct vi_info *vi)
5578 struct adapter *sc = vi->pi->adapter;
5579 struct ifnet *ifp = vi->ifp;
5581 struct sge_rxq *rxq;
5584 int nbuckets = rss_getnumbuckets();
5585 int hashconfig = rss_gethashconfig();
5589 ASSERT_SYNCHRONIZED_OP(sc);
5590 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5591 ("%s: VI_INIT_DONE already", __func__));
5593 sysctl_ctx_init(&vi->ctx);
5594 vi->flags |= VI_SYSCTL_CTX;
5597 * Allocate tx/rx/fl queues for this VI.
5599 rc = t4_setup_vi_queues(vi);
5601 goto done; /* error message displayed already */
5604 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5606 if (vi->nrxq > vi->rss_size) {
5607 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5608 "some queues will never receive traffic.\n", vi->nrxq,
5610 } else if (vi->rss_size % vi->nrxq) {
5611 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5612 "expect uneven traffic distribution.\n", vi->nrxq,
5616 if (vi->nrxq != nbuckets) {
5617 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5618 "performance will be impacted.\n", vi->nrxq, nbuckets);
5621 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5622 for (i = 0; i < vi->rss_size;) {
5624 j = rss_get_indirection_to_bucket(i);
5626 rxq = &sc->sge.rxq[vi->first_rxq + j];
5627 rss[i++] = rxq->iq.abs_id;
5629 for_each_rxq(vi, j, rxq) {
5630 rss[i++] = rxq->iq.abs_id;
5631 if (i == vi->rss_size)
5637 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5641 if_printf(ifp, "rss_config failed: %d\n", rc);
5646 vi->hashen = hashconfig_to_hashen(hashconfig);
5649 * We may have had to enable some hashes even though the global config
5650 * wants them disabled. This is a potential problem that must be
5651 * reported to the user.
5653 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5656 * If we consider only the supported hash types, then the enabled hashes
5657 * are a superset of the requested hashes. In other words, there cannot
5658 * be any supported hash that was requested but not enabled, but there
5659 * can be hashes that were not requested but had to be enabled.
5661 extra &= SUPPORTED_RSS_HASHTYPES;
5662 MPASS((extra & hashconfig) == 0);
5666 "global RSS config (0x%x) cannot be accommodated.\n",
5669 if (extra & RSS_HASHTYPE_RSS_IPV4)
5670 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5671 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5672 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5673 if (extra & RSS_HASHTYPE_RSS_IPV6)
5674 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5675 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5676 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5677 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5678 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5679 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5680 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5682 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5683 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5684 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5685 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5687 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5690 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5695 vi->flags |= VI_INIT_DONE;
5707 vi_full_uninit(struct vi_info *vi)
5709 struct port_info *pi = vi->pi;
5710 struct adapter *sc = pi->adapter;
5712 struct sge_rxq *rxq;
5713 struct sge_txq *txq;
5715 struct sge_ofld_rxq *ofld_rxq;
5717 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5718 struct sge_wrq *ofld_txq;
5721 if (vi->flags & VI_INIT_DONE) {
5723 /* Need to quiesce queues. */
5725 /* XXX: Only for the first VI? */
5726 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5727 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5729 for_each_txq(vi, i, txq) {
5730 quiesce_txq(sc, txq);
5733 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5734 for_each_ofld_txq(vi, i, ofld_txq) {
5735 quiesce_wrq(sc, ofld_txq);
5739 for_each_rxq(vi, i, rxq) {
5740 quiesce_iq(sc, &rxq->iq);
5741 quiesce_fl(sc, &rxq->fl);
5745 for_each_ofld_rxq(vi, i, ofld_rxq) {
5746 quiesce_iq(sc, &ofld_rxq->iq);
5747 quiesce_fl(sc, &ofld_rxq->fl);
5750 free(vi->rss, M_CXGBE);
5751 free(vi->nm_rss, M_CXGBE);
5754 t4_teardown_vi_queues(vi);
5755 vi->flags &= ~VI_INIT_DONE;
5761 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5763 struct sge_eq *eq = &txq->eq;
5764 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5766 (void) sc; /* unused */
5770 MPASS((eq->flags & EQ_ENABLED) == 0);
5774 /* Wait for the mp_ring to empty. */
5775 while (!mp_ring_is_idle(txq->r)) {
5776 mp_ring_check_drainage(txq->r, 0);
5777 pause("rquiesce", 1);
5780 /* Then wait for the hardware to finish. */
5781 while (spg->cidx != htobe16(eq->pidx))
5782 pause("equiesce", 1);
5784 /* Finally, wait for the driver to reclaim all descriptors. */
5785 while (eq->cidx != eq->pidx)
5786 pause("dquiesce", 1);
5790 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5797 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5799 (void) sc; /* unused */
5801 /* Synchronize with the interrupt handler */
5802 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5807 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5809 mtx_lock(&sc->sfl_lock);
5811 fl->flags |= FL_DOOMED;
5813 callout_stop(&sc->sfl_callout);
5814 mtx_unlock(&sc->sfl_lock);
5816 KASSERT((fl->flags & FL_STARVING) == 0,
5817 ("%s: still starving", __func__));
5821 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5822 driver_intr_t *handler, void *arg, char *name)
5827 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5828 RF_SHAREABLE | RF_ACTIVE);
5829 if (irq->res == NULL) {
5830 device_printf(sc->dev,
5831 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5835 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5836 NULL, handler, arg, &irq->tag);
5838 device_printf(sc->dev,
5839 "failed to setup interrupt for rid %d, name %s: %d\n",
5842 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5848 t4_free_irq(struct adapter *sc, struct irq *irq)
5851 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5853 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5855 bzero(irq, sizeof(*irq));
5861 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5864 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5865 t4_get_regs(sc, buf, regs->len);
5868 #define A_PL_INDIR_CMD 0x1f8
5870 #define S_PL_AUTOINC 31
5871 #define M_PL_AUTOINC 0x1U
5872 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5873 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5875 #define S_PL_VFID 20
5876 #define M_PL_VFID 0xffU
5877 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5878 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5881 #define M_PL_ADDR 0xfffffU
5882 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5883 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5885 #define A_PL_INDIR_DATA 0x1fc
5888 read_vf_stat(struct adapter *sc, u_int vin, int reg)
5892 mtx_assert(&sc->reg_lock, MA_OWNED);
5893 if (sc->flags & IS_VF) {
5894 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5895 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5897 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5898 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
5899 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5900 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5902 return (((uint64_t)stats[1]) << 32 | stats[0]);
5906 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
5909 #define GET_STAT(name) \
5910 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
5912 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5913 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5914 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5915 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5916 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5917 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5918 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5919 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5920 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5921 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5922 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5923 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5924 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5925 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5926 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5927 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5933 t4_clr_vi_stats(struct adapter *sc, u_int vin)
5937 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
5938 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5939 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5940 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5941 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5945 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5948 const struct timeval interval = {0, 250000}; /* 250ms */
5950 if (!(vi->flags & VI_INIT_DONE))
5954 timevalsub(&tv, &interval);
5955 if (timevalcmp(&tv, &vi->last_refreshed, <))
5958 mtx_lock(&sc->reg_lock);
5959 t4_get_vi_stats(sc, vi->vin, &vi->stats);
5960 getmicrotime(&vi->last_refreshed);
5961 mtx_unlock(&sc->reg_lock);
5965 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5967 u_int i, v, tnl_cong_drops, bg_map;
5969 const struct timeval interval = {0, 250000}; /* 250ms */
5972 timevalsub(&tv, &interval);
5973 if (timevalcmp(&tv, &pi->last_refreshed, <))
5977 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5978 bg_map = pi->mps_bg_map;
5980 i = ffs(bg_map) - 1;
5981 mtx_lock(&sc->reg_lock);
5982 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5983 A_TP_MIB_TNL_CNG_DROP_0 + i);
5984 mtx_unlock(&sc->reg_lock);
5985 tnl_cong_drops += v;
5986 bg_map &= ~(1 << i);
5988 pi->tnl_cong_drops = tnl_cong_drops;
5989 getmicrotime(&pi->last_refreshed);
5993 cxgbe_tick(void *arg)
5995 struct port_info *pi = arg;
5996 struct adapter *sc = pi->adapter;
5998 PORT_LOCK_ASSERT_OWNED(pi);
5999 cxgbe_refresh_stats(sc, pi);
6001 callout_schedule(&pi->tick, hz);
6007 struct vi_info *vi = arg;
6008 struct adapter *sc = vi->pi->adapter;
6010 vi_refresh_stats(sc, vi);
6012 callout_schedule(&vi->tick, hz);
6016 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
6018 static char *caps_decoder[] = {
6019 "\20\001IPMI\002NCSI", /* 0: NBM */
6020 "\20\001PPP\002QFC\003DCBX", /* 1: link */
6021 "\20\001INGRESS\002EGRESS", /* 2: switch */
6022 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
6023 "\006HASHFILTER\007ETHOFLD",
6024 "\20\001TOE", /* 4: TOE */
6025 "\20\001RDDP\002RDMAC", /* 5: RDMA */
6026 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
6027 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
6028 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
6030 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
6031 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
6032 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
6033 "\004PO_INITIATOR\005PO_TARGET",
6037 t4_sysctls(struct adapter *sc)
6039 struct sysctl_ctx_list *ctx;
6040 struct sysctl_oid *oid;
6041 struct sysctl_oid_list *children, *c0;
6042 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
6044 ctx = device_get_sysctl_ctx(sc->dev);
6049 oid = device_get_sysctl_tree(sc->dev);
6050 c0 = children = SYSCTL_CHILDREN(oid);
6052 sc->sc_do_rxcopy = 1;
6053 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
6054 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
6056 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
6057 sc->params.nports, "# of ports");
6059 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
6060 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
6061 sysctl_bitfield_8b, "A", "available doorbells");
6063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
6064 sc->params.vpd.cclk, "core clock frequency (in KHz)");
6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
6067 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
6068 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
6069 "interrupt holdoff timer values (us)");
6071 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
6072 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
6073 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
6074 "interrupt holdoff packet counter values");
6076 t4_sge_sysctls(sc, ctx, children);
6078 sc->lro_timeout = 100;
6079 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
6080 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
6082 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
6083 &sc->debug_flags, 0, "flags to enable runtime debugging");
6085 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
6086 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
6088 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
6089 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
6091 if (sc->flags & IS_VF)
6094 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
6095 NULL, chip_rev(sc), "chip hardware revision");
6097 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
6098 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
6100 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
6101 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
6103 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
6104 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
6106 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
6107 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
6109 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
6110 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
6112 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
6113 sc->er_version, 0, "expansion ROM version");
6115 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
6116 sc->bs_version, 0, "bootstrap firmware version");
6118 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
6119 NULL, sc->params.scfg_vers, "serial config version");
6121 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
6122 NULL, sc->params.vpd_vers, "VPD version");
6124 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
6125 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
6127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
6128 sc->cfcsum, "config file checksum");
6130 #define SYSCTL_CAP(name, n, text) \
6131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
6132 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
6133 sysctl_bitfield_16b, "A", "available " text " capabilities")
6135 SYSCTL_CAP(nbmcaps, 0, "NBM");
6136 SYSCTL_CAP(linkcaps, 1, "link");
6137 SYSCTL_CAP(switchcaps, 2, "switch");
6138 SYSCTL_CAP(niccaps, 3, "NIC");
6139 SYSCTL_CAP(toecaps, 4, "TCP offload");
6140 SYSCTL_CAP(rdmacaps, 5, "RDMA");
6141 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
6142 SYSCTL_CAP(cryptocaps, 7, "crypto");
6143 SYSCTL_CAP(fcoecaps, 8, "FCoE");
6146 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
6147 NULL, sc->tids.nftids, "number of filters");
6149 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
6150 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
6151 "chip temperature (in Celsius)");
6153 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
6154 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
6155 "microprocessor load averages (debug firmwares only)");
6157 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", CTLTYPE_INT |
6158 CTLFLAG_RD, sc, 0, sysctl_vdd, "I", "core Vdd (in mV)");
6160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
6161 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
6162 sysctl_cpus, "A", "local CPUs");
6164 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
6165 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
6166 sysctl_cpus, "A", "preferred CPUs for interrupts");
6168 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
6169 &sc->swintr, 0, "software triggered interrupts");
6172 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
6174 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
6175 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
6176 "logs and miscellaneous information");
6177 children = SYSCTL_CHILDREN(oid);
6179 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6180 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6181 sysctl_cctrl, "A", "congestion control");
6183 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6184 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6185 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6187 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6188 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
6189 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6191 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6192 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
6193 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6196 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
6197 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6199 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6200 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
6201 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6203 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6204 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
6205 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6207 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6208 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la,
6209 "A", "CIM logic analyzer");
6211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6212 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6213 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6215 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6216 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
6217 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6219 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6220 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
6221 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6223 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6224 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
6225 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6227 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6228 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
6229 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6231 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6232 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
6233 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6235 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6236 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
6237 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6239 if (chip_id(sc) > CHELSIO_T4) {
6240 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6241 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
6242 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
6244 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6245 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
6246 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
6249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6250 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6251 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6253 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6254 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6255 sysctl_cim_qcfg, "A", "CIM queue configuration");
6257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6258 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6259 sysctl_cpl_stats, "A", "CPL statistics");
6261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6262 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6263 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6266 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6267 sysctl_devlog, "A", "firmware's device log");
6269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6270 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6271 sysctl_fcoe_stats, "A", "FCoE statistics");
6273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6274 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6275 sysctl_hw_sched, "A", "hardware scheduler ");
6277 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6278 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6279 sysctl_l2t, "A", "hardware L2 table");
6281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6282 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6283 sysctl_smt, "A", "hardware source MAC table");
6286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6287 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6288 sysctl_clip, "A", "active CLIP table entries");
6291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6292 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6293 sysctl_lb_stats, "A", "loopback statistics");
6295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6296 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6297 sysctl_meminfo, "A", "memory regions");
6299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6300 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6301 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6302 "A", "MPS TCAM entries");
6304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6305 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6306 sysctl_path_mtus, "A", "path MTUs");
6308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6309 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6310 sysctl_pm_stats, "A", "PM statistics");
6312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6313 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6314 sysctl_rdma_stats, "A", "RDMA statistics");
6316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6317 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6318 sysctl_tcp_stats, "A", "TCP statistics");
6320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6321 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6322 sysctl_tids, "A", "TID information");
6324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6325 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6326 sysctl_tp_err_stats, "A", "TP error statistics");
6328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6329 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
6330 "TP logic analyzer event capture mask");
6332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6333 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6334 sysctl_tp_la, "A", "TP logic analyzer");
6336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6337 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6338 sysctl_tx_rate, "A", "Tx rate");
6340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6341 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6342 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6344 if (chip_id(sc) >= CHELSIO_T5) {
6345 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6346 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6347 sysctl_wcwr_stats, "A", "write combined work requests");
6351 if (is_offload(sc)) {
6358 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
6359 NULL, "TOE parameters");
6360 children = SYSCTL_CHILDREN(oid);
6362 sc->tt.cong_algorithm = -1;
6363 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6364 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6365 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6369 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6370 &sc->tt.sndbuf, 0, "hardware send buffer");
6373 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
6374 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
6375 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
6376 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
6378 sc->tt.rx_coalesce = -1;
6379 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6380 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6383 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6384 &sc->tt.tls, 0, "Inline TLS allowed");
6386 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6387 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
6388 "I", "TCP ports that use inline TLS+TOE RX");
6390 sc->tt.tx_align = -1;
6391 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6392 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6394 sc->tt.tx_zcopy = 0;
6395 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6396 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6397 "Enable zero-copy aio_write(2)");
6399 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6400 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6401 "cop_managed_offloading", CTLFLAG_RW,
6402 &sc->tt.cop_managed_offloading, 0,
6403 "COP (Connection Offload Policy) controls all TOE offload");
6405 sc->tt.autorcvbuf_inc = 16 * 1024;
6406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
6407 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
6408 "autorcvbuf increment");
6410 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6411 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6412 "TP timer tick (us)");
6414 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6415 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6416 "TCP timestamp tick (us)");
6418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6419 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6422 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6423 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6424 "IU", "DACK timer (us)");
6426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6427 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6428 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6430 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6431 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6432 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6434 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6435 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6436 sysctl_tp_timer, "LU", "Persist timer min (us)");
6438 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6439 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6440 sysctl_tp_timer, "LU", "Persist timer max (us)");
6442 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6443 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6444 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6447 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6448 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6450 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6451 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6452 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6454 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6455 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6456 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6458 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6459 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6460 sysctl_tp_shift_cnt, "IU",
6461 "Number of SYN retransmissions before abort");
6463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6464 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6465 sysctl_tp_shift_cnt, "IU",
6466 "Number of retransmissions before abort");
6468 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6469 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6470 sysctl_tp_shift_cnt, "IU",
6471 "Number of keepalive probes before abort");
6473 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6474 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6475 children = SYSCTL_CHILDREN(oid);
6476 for (i = 0; i < 16; i++) {
6477 snprintf(s, sizeof(s), "%u", i);
6478 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6479 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6480 "IU", "TOE retransmit backoff");
6487 vi_sysctls(struct vi_info *vi)
6489 struct sysctl_ctx_list *ctx;
6490 struct sysctl_oid *oid;
6491 struct sysctl_oid_list *children;
6493 ctx = device_get_sysctl_ctx(vi->dev);
6496 * dev.v?(cxgbe|cxl).X.
6498 oid = device_get_sysctl_tree(vi->dev);
6499 children = SYSCTL_CHILDREN(oid);
6501 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6502 vi->viid, "VI identifer");
6503 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6504 &vi->nrxq, 0, "# of rx queues");
6505 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6506 &vi->ntxq, 0, "# of tx queues");
6507 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6508 &vi->first_rxq, 0, "index of first rx queue");
6509 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6510 &vi->first_txq, 0, "index of first tx queue");
6511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6512 vi->rss_base, "start of RSS indirection table");
6513 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6514 vi->rss_size, "size of RSS indirection table");
6516 if (IS_MAIN_VI(vi)) {
6517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6518 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6519 "Reserve queue 0 for non-flowid packets");
6523 if (vi->nofldrxq != 0) {
6524 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6526 "# of rx queues for offloaded TCP connections");
6527 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6528 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6529 "index of first TOE rx queue");
6530 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6531 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6532 sysctl_holdoff_tmr_idx_ofld, "I",
6533 "holdoff timer index for TOE queues");
6534 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6535 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6536 sysctl_holdoff_pktc_idx_ofld, "I",
6537 "holdoff packet counter index for TOE queues");
6540 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6541 if (vi->nofldtxq != 0) {
6542 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6544 "# of tx queues for TOE/ETHOFLD");
6545 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6546 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6547 "index of first TOE/ETHOFLD tx queue");
6551 if (vi->nnmrxq != 0) {
6552 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6553 &vi->nnmrxq, 0, "# of netmap rx queues");
6554 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6555 &vi->nnmtxq, 0, "# of netmap tx queues");
6556 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6557 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6558 "index of first netmap rx queue");
6559 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6560 CTLFLAG_RD, &vi->first_nm_txq, 0,
6561 "index of first netmap tx queue");
6565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6566 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6567 "holdoff timer index");
6568 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6569 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6570 "holdoff packet counter index");
6572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6573 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6576 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6581 cxgbe_sysctls(struct port_info *pi)
6583 struct sysctl_ctx_list *ctx;
6584 struct sysctl_oid *oid;
6585 struct sysctl_oid_list *children, *children2;
6586 struct adapter *sc = pi->adapter;
6589 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6591 ctx = device_get_sysctl_ctx(pi->dev);
6596 oid = device_get_sysctl_tree(pi->dev);
6597 children = SYSCTL_CHILDREN(oid);
6599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6600 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6601 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6603 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6604 "PHY temperature (in Celsius)");
6605 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6606 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6607 "PHY firmware version");
6610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6611 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6612 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6614 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6615 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6617 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6618 "autonegotiation (-1 = not supported)");
6620 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6621 port_top_speed(pi), "max speed (in Gbps)");
6622 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6623 pi->mps_bg_map, "MPS buffer group map");
6624 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6625 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6627 if (sc->flags & IS_VF)
6631 * dev.(cxgbe|cxl).X.tc.
6633 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6634 "Tx scheduler traffic classes (cl_rl)");
6635 children2 = SYSCTL_CHILDREN(oid);
6636 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6637 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6638 "pktsize for per-flow cl-rl (0 means up to the driver )");
6639 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6640 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6641 "burstsize for per-flow cl-rl (0 means up to the driver)");
6642 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6643 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6645 snprintf(name, sizeof(name), "%d", i);
6646 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6647 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6649 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6650 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6651 sysctl_bitfield_8b, "A", "flags");
6652 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6653 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6654 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6655 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6656 sysctl_tc_params, "A", "traffic class parameters");
6660 * dev.cxgbe.X.stats.
6662 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6663 NULL, "port statistics");
6664 children = SYSCTL_CHILDREN(oid);
6665 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6666 &pi->tx_parse_error, 0,
6667 "# of tx packets with invalid length or # of segments");
6669 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6670 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6671 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6672 sysctl_handle_t4_reg64, "QU", desc)
6674 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6675 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6676 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6677 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6678 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6679 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6680 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6681 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6682 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6683 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6684 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6685 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6686 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6687 "# of tx frames in this range",
6688 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6689 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6690 "# of tx frames in this range",
6691 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6692 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6693 "# of tx frames in this range",
6694 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6695 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6696 "# of tx frames in this range",
6697 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6698 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6699 "# of tx frames in this range",
6700 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6701 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6702 "# of tx frames in this range",
6703 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6704 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6705 "# of tx frames in this range",
6706 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6707 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6708 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6709 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6710 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6711 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6712 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6713 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6714 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6715 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6716 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6717 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6718 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6719 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6720 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6721 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6722 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6723 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6724 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6725 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6726 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6728 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6729 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6730 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6731 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6732 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6733 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6734 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6735 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6736 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6737 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6738 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6739 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6740 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6741 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6742 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6743 "# of frames received with bad FCS",
6744 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6745 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6746 "# of frames received with length error",
6747 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6748 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6749 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6750 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6751 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6752 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6753 "# of rx frames in this range",
6754 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6755 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6756 "# of rx frames in this range",
6757 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6758 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6759 "# of rx frames in this range",
6760 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6761 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6762 "# of rx frames in this range",
6763 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6764 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6765 "# of rx frames in this range",
6766 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6767 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6768 "# of rx frames in this range",
6769 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6770 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6771 "# of rx frames in this range",
6772 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6773 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6774 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6775 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6776 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6777 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6778 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6779 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6780 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6781 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6782 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6783 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6784 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6785 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6786 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6787 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6788 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6789 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6790 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6792 #undef SYSCTL_ADD_T4_REG64
6794 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6795 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6796 &pi->stats.name, desc)
6798 /* We get these from port_stats and they may be stale by up to 1s */
6799 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6800 "# drops due to buffer-group 0 overflows");
6801 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6802 "# drops due to buffer-group 1 overflows");
6803 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6804 "# drops due to buffer-group 2 overflows");
6805 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6806 "# drops due to buffer-group 3 overflows");
6807 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6808 "# of buffer-group 0 truncated packets");
6809 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6810 "# of buffer-group 1 truncated packets");
6811 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6812 "# of buffer-group 2 truncated packets");
6813 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6814 "# of buffer-group 3 truncated packets");
6816 #undef SYSCTL_ADD_T4_PORTSTAT
6818 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6819 CTLFLAG_RD, &pi->tx_tls_records,
6820 "# of TLS records transmitted");
6821 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6822 CTLFLAG_RD, &pi->tx_tls_octets,
6823 "# of payload octets in transmitted TLS records");
6824 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6825 CTLFLAG_RD, &pi->rx_tls_records,
6826 "# of TLS records received");
6827 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6828 CTLFLAG_RD, &pi->rx_tls_octets,
6829 "# of payload octets in received TLS records");
6833 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6835 int rc, *i, space = 0;
6838 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6839 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6841 sbuf_printf(&sb, " ");
6842 sbuf_printf(&sb, "%d", *i);
6845 rc = sbuf_finish(&sb);
6851 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6856 rc = sysctl_wire_old_buffer(req, 0);
6860 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6864 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6865 rc = sbuf_finish(sb);
6872 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6877 rc = sysctl_wire_old_buffer(req, 0);
6881 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6885 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6886 rc = sbuf_finish(sb);
6893 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6895 struct port_info *pi = arg1;
6897 struct adapter *sc = pi->adapter;
6901 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6904 /* XXX: magic numbers */
6905 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6907 end_synchronized_op(sc, 0);
6913 rc = sysctl_handle_int(oidp, &v, 0, req);
6918 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6920 struct vi_info *vi = arg1;
6923 val = vi->rsrv_noflowq;
6924 rc = sysctl_handle_int(oidp, &val, 0, req);
6925 if (rc != 0 || req->newptr == NULL)
6928 if ((val >= 1) && (vi->ntxq > 1))
6929 vi->rsrv_noflowq = 1;
6931 vi->rsrv_noflowq = 0;
6937 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6939 struct vi_info *vi = arg1;
6940 struct adapter *sc = vi->pi->adapter;
6942 struct sge_rxq *rxq;
6947 rc = sysctl_handle_int(oidp, &idx, 0, req);
6948 if (rc != 0 || req->newptr == NULL)
6951 if (idx < 0 || idx >= SGE_NTIMERS)
6954 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6959 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6960 for_each_rxq(vi, i, rxq) {
6961 #ifdef atomic_store_rel_8
6962 atomic_store_rel_8(&rxq->iq.intr_params, v);
6964 rxq->iq.intr_params = v;
6969 end_synchronized_op(sc, LOCK_HELD);
6974 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6976 struct vi_info *vi = arg1;
6977 struct adapter *sc = vi->pi->adapter;
6982 rc = sysctl_handle_int(oidp, &idx, 0, req);
6983 if (rc != 0 || req->newptr == NULL)
6986 if (idx < -1 || idx >= SGE_NCOUNTERS)
6989 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6994 if (vi->flags & VI_INIT_DONE)
6995 rc = EBUSY; /* cannot be changed once the queues are created */
6999 end_synchronized_op(sc, LOCK_HELD);
7004 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
7006 struct vi_info *vi = arg1;
7007 struct adapter *sc = vi->pi->adapter;
7010 qsize = vi->qsize_rxq;
7012 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7013 if (rc != 0 || req->newptr == NULL)
7016 if (qsize < 128 || (qsize & 7))
7019 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7024 if (vi->flags & VI_INIT_DONE)
7025 rc = EBUSY; /* cannot be changed once the queues are created */
7027 vi->qsize_rxq = qsize;
7029 end_synchronized_op(sc, LOCK_HELD);
7034 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
7036 struct vi_info *vi = arg1;
7037 struct adapter *sc = vi->pi->adapter;
7040 qsize = vi->qsize_txq;
7042 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7043 if (rc != 0 || req->newptr == NULL)
7046 if (qsize < 128 || qsize > 65536)
7049 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7054 if (vi->flags & VI_INIT_DONE)
7055 rc = EBUSY; /* cannot be changed once the queues are created */
7057 vi->qsize_txq = qsize;
7059 end_synchronized_op(sc, LOCK_HELD);
7064 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
7066 struct port_info *pi = arg1;
7067 struct adapter *sc = pi->adapter;
7068 struct link_config *lc = &pi->link_cfg;
7071 if (req->newptr == NULL) {
7073 static char *bits = "\20\1RX\2TX\3AUTO";
7075 rc = sysctl_wire_old_buffer(req, 0);
7079 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7084 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
7085 (lc->requested_fc & PAUSE_AUTONEG), bits);
7087 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
7088 PAUSE_RX | PAUSE_AUTONEG), bits);
7090 rc = sbuf_finish(sb);
7096 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
7100 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7106 if (s[0] < '0' || s[0] > '9')
7107 return (EINVAL); /* not a number */
7109 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
7110 return (EINVAL); /* some other bit is set too */
7112 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7117 lc->requested_fc = n;
7118 fixup_link_config(pi);
7120 rc = apply_link_config(pi);
7121 set_current_media(pi);
7123 end_synchronized_op(sc, 0);
7130 sysctl_fec(SYSCTL_HANDLER_ARGS)
7132 struct port_info *pi = arg1;
7133 struct adapter *sc = pi->adapter;
7134 struct link_config *lc = &pi->link_cfg;
7138 if (req->newptr == NULL) {
7140 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
7142 rc = sysctl_wire_old_buffer(req, 0);
7146 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7151 * Display the requested_fec when the link is down -- the actual
7152 * FEC makes sense only when the link is up.
7155 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
7156 (lc->requested_fec & FEC_AUTO), bits);
7158 sbuf_printf(sb, "%b", lc->requested_fec, bits);
7160 rc = sbuf_finish(sb);
7166 snprintf(s, sizeof(s), "%d",
7167 lc->requested_fec == FEC_AUTO ? -1 :
7168 lc->requested_fec & M_FW_PORT_CAP32_FEC);
7170 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7174 n = strtol(&s[0], NULL, 0);
7175 if (n < 0 || n & FEC_AUTO)
7178 if (n & ~M_FW_PORT_CAP32_FEC)
7179 return (EINVAL);/* some other bit is set too */
7181 return (EINVAL);/* one bit can be set at most */
7184 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7189 old = lc->requested_fec;
7191 lc->requested_fec = FEC_AUTO;
7193 lc->requested_fec = FEC_NONE;
7195 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
7200 lc->requested_fec = n;
7202 fixup_link_config(pi);
7203 if (pi->up_vis > 0) {
7204 rc = apply_link_config(pi);
7206 lc->requested_fec = old;
7207 if (rc == FW_EPROTO)
7213 end_synchronized_op(sc, 0);
7220 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7222 struct port_info *pi = arg1;
7223 struct adapter *sc = pi->adapter;
7224 struct link_config *lc = &pi->link_cfg;
7227 if (lc->supported & FW_PORT_CAP32_ANEG)
7228 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7231 rc = sysctl_handle_int(oidp, &val, 0, req);
7232 if (rc != 0 || req->newptr == NULL)
7235 val = AUTONEG_DISABLE;
7237 val = AUTONEG_ENABLE;
7241 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7246 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
7250 lc->requested_aneg = val;
7251 fixup_link_config(pi);
7253 rc = apply_link_config(pi);
7254 set_current_media(pi);
7257 end_synchronized_op(sc, 0);
7262 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7264 struct adapter *sc = arg1;
7268 val = t4_read_reg64(sc, reg);
7270 return (sysctl_handle_64(oidp, &val, 0, req));
7274 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7276 struct adapter *sc = arg1;
7278 uint32_t param, val;
7280 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7283 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7284 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7285 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7286 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7287 end_synchronized_op(sc, 0);
7291 /* unknown is returned as 0 but we display -1 in that case */
7292 t = val == 0 ? -1 : val;
7294 rc = sysctl_handle_int(oidp, &t, 0, req);
7299 sysctl_vdd(SYSCTL_HANDLER_ARGS)
7301 struct adapter *sc = arg1;
7303 uint32_t param, val;
7305 if (sc->params.core_vdd == 0) {
7306 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7310 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7311 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7312 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
7313 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7314 end_synchronized_op(sc, 0);
7317 sc->params.core_vdd = val;
7320 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
7324 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7326 struct adapter *sc = arg1;
7329 uint32_t param, val;
7331 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7334 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7335 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7336 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7337 end_synchronized_op(sc, 0);
7341 rc = sysctl_wire_old_buffer(req, 0);
7345 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7349 if (val == 0xffffffff) {
7350 /* Only debug and custom firmwares report load averages. */
7351 sbuf_printf(sb, "not available");
7353 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7354 (val >> 16) & 0xff);
7356 rc = sbuf_finish(sb);
7363 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7365 struct adapter *sc = arg1;
7368 uint16_t incr[NMTUS][NCCTRL_WIN];
7369 static const char *dec_fac[] = {
7370 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7374 rc = sysctl_wire_old_buffer(req, 0);
7378 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7382 t4_read_cong_tbl(sc, incr);
7384 for (i = 0; i < NCCTRL_WIN; ++i) {
7385 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7386 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7387 incr[5][i], incr[6][i], incr[7][i]);
7388 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7389 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7390 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7391 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7394 rc = sbuf_finish(sb);
7400 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7401 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7402 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7403 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7407 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7409 struct adapter *sc = arg1;
7411 int rc, i, n, qid = arg2;
7414 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7416 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7417 ("%s: bad qid %d\n", __func__, qid));
7419 if (qid < CIM_NUM_IBQ) {
7422 n = 4 * CIM_IBQ_SIZE;
7423 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7424 rc = t4_read_cim_ibq(sc, qid, buf, n);
7426 /* outbound queue */
7429 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7430 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7431 rc = t4_read_cim_obq(sc, qid, buf, n);
7438 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7440 rc = sysctl_wire_old_buffer(req, 0);
7444 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7450 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7451 for (i = 0, p = buf; i < n; i += 16, p += 4)
7452 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7455 rc = sbuf_finish(sb);
7463 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7467 sbuf_printf(sb, "Status Data PC%s",
7468 cfg & F_UPDBGLACAPTPCONLY ? "" :
7469 " LS0Stat LS0Addr LS0Data");
7471 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7472 if (cfg & F_UPDBGLACAPTPCONLY) {
7473 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7475 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7476 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7477 p[4] & 0xff, p[5] >> 8);
7478 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7479 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7480 p[1] & 0xf, p[2] >> 4);
7483 "\n %02x %x%07x %x%07x %08x %08x "
7485 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7486 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7493 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7497 sbuf_printf(sb, "Status Inst Data PC%s",
7498 cfg & F_UPDBGLACAPTPCONLY ? "" :
7499 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7501 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7502 if (cfg & F_UPDBGLACAPTPCONLY) {
7503 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7504 p[3] & 0xff, p[2], p[1], p[0]);
7505 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7506 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7507 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7508 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7509 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7510 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7513 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7514 "%08x %08x %08x %08x %08x %08x",
7515 (p[9] >> 16) & 0xff,
7516 p[9] & 0xffff, p[8] >> 16,
7517 p[8] & 0xffff, p[7] >> 16,
7518 p[7] & 0xffff, p[6] >> 16,
7519 p[2], p[1], p[0], p[5], p[4], p[3]);
7525 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
7530 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7534 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7535 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7540 rc = -t4_cim_read_la(sc, buf, NULL);
7543 if (chip_id(sc) < CHELSIO_T6)
7544 sbuf_cim_la4(sc, sb, buf, cfg);
7546 sbuf_cim_la6(sc, sb, buf, cfg);
7554 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7556 struct adapter *sc = arg1;
7560 rc = sysctl_wire_old_buffer(req, 0);
7563 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7567 rc = sbuf_cim_la(sc, sb, M_WAITOK);
7569 rc = sbuf_finish(sb);
7575 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose)
7580 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7582 rc = sbuf_cim_la(sc, &sb, M_NOWAIT);
7584 rc = sbuf_finish(&sb);
7586 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s",
7587 device_get_nameunit(sc->dev), sbuf_data(&sb));
7595 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7597 struct adapter *sc = arg1;
7603 rc = sysctl_wire_old_buffer(req, 0);
7607 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7611 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7614 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7617 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7618 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7622 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7623 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7624 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7625 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7626 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7627 (p[1] >> 2) | ((p[2] & 3) << 30),
7628 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7632 rc = sbuf_finish(sb);
7639 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7641 struct adapter *sc = arg1;
7647 rc = sysctl_wire_old_buffer(req, 0);
7651 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7655 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7658 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7661 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7662 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7663 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7664 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7665 p[4], p[3], p[2], p[1], p[0]);
7668 sbuf_printf(sb, "\n\nCntl ID Data");
7669 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7670 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7671 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7674 rc = sbuf_finish(sb);
7681 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7683 struct adapter *sc = arg1;
7686 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7687 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7688 uint16_t thres[CIM_NUM_IBQ];
7689 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7690 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7691 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7693 cim_num_obq = sc->chip_params->cim_num_obq;
7695 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7696 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7698 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7699 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7701 nq = CIM_NUM_IBQ + cim_num_obq;
7703 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7705 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7709 t4_read_cimq_cfg(sc, base, size, thres);
7711 rc = sysctl_wire_old_buffer(req, 0);
7715 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7720 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7722 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7723 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7724 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7725 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7726 G_QUEREMFLITS(p[2]) * 16);
7727 for ( ; i < nq; i++, p += 4, wr += 2)
7728 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7729 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7730 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7731 G_QUEREMFLITS(p[2]) * 16);
7733 rc = sbuf_finish(sb);
7740 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7742 struct adapter *sc = arg1;
7745 struct tp_cpl_stats stats;
7747 rc = sysctl_wire_old_buffer(req, 0);
7751 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7755 mtx_lock(&sc->reg_lock);
7756 t4_tp_get_cpl_stats(sc, &stats, 0);
7757 mtx_unlock(&sc->reg_lock);
7759 if (sc->chip_params->nchan > 2) {
7760 sbuf_printf(sb, " channel 0 channel 1"
7761 " channel 2 channel 3");
7762 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7763 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7764 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7765 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7767 sbuf_printf(sb, " channel 0 channel 1");
7768 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7769 stats.req[0], stats.req[1]);
7770 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7771 stats.rsp[0], stats.rsp[1]);
7774 rc = sbuf_finish(sb);
7781 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7783 struct adapter *sc = arg1;
7786 struct tp_usm_stats stats;
7788 rc = sysctl_wire_old_buffer(req, 0);
7792 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7796 t4_get_usm_stats(sc, &stats, 1);
7798 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7799 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7800 sbuf_printf(sb, "Drops: %u", stats.drops);
7802 rc = sbuf_finish(sb);
7808 static const char * const devlog_level_strings[] = {
7809 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7810 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7811 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7812 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7813 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7814 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7817 static const char * const devlog_facility_strings[] = {
7818 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7819 [FW_DEVLOG_FACILITY_CF] = "CF",
7820 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7821 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7822 [FW_DEVLOG_FACILITY_RES] = "RES",
7823 [FW_DEVLOG_FACILITY_HW] = "HW",
7824 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7825 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7826 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7827 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7828 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7829 [FW_DEVLOG_FACILITY_VI] = "VI",
7830 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7831 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7832 [FW_DEVLOG_FACILITY_TM] = "TM",
7833 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7834 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7835 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7836 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7837 [FW_DEVLOG_FACILITY_RI] = "RI",
7838 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7839 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7840 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7841 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7842 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7846 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
7848 int i, j, rc, nentries, first = 0;
7849 struct devlog_params *dparams = &sc->params.devlog;
7850 struct fw_devlog_e *buf, *e;
7851 uint64_t ftstamp = UINT64_MAX;
7853 if (dparams->addr == 0)
7856 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7857 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
7861 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7865 nentries = dparams->size / sizeof(struct fw_devlog_e);
7866 for (i = 0; i < nentries; i++) {
7869 if (e->timestamp == 0)
7872 e->timestamp = be64toh(e->timestamp);
7873 e->seqno = be32toh(e->seqno);
7874 for (j = 0; j < 8; j++)
7875 e->params[j] = be32toh(e->params[j]);
7877 if (e->timestamp < ftstamp) {
7878 ftstamp = e->timestamp;
7883 if (buf[first].timestamp == 0)
7884 goto done; /* nothing in the log */
7886 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7887 "Seq#", "Tstamp", "Level", "Facility", "Message");
7892 if (e->timestamp == 0)
7895 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7896 e->seqno, e->timestamp,
7897 (e->level < nitems(devlog_level_strings) ?
7898 devlog_level_strings[e->level] : "UNKNOWN"),
7899 (e->facility < nitems(devlog_facility_strings) ?
7900 devlog_facility_strings[e->facility] : "UNKNOWN"));
7901 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7902 e->params[2], e->params[3], e->params[4],
7903 e->params[5], e->params[6], e->params[7]);
7905 if (++i == nentries)
7907 } while (i != first);
7914 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7916 struct adapter *sc = arg1;
7920 rc = sysctl_wire_old_buffer(req, 0);
7923 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7927 rc = sbuf_devlog(sc, sb, M_WAITOK);
7929 rc = sbuf_finish(sb);
7935 t4_os_dump_devlog(struct adapter *sc)
7940 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7942 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
7944 rc = sbuf_finish(&sb);
7946 log(LOG_DEBUG, "%s: device log follows.\n%s",
7947 device_get_nameunit(sc->dev), sbuf_data(&sb));
7954 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7956 struct adapter *sc = arg1;
7959 struct tp_fcoe_stats stats[MAX_NCHAN];
7960 int i, nchan = sc->chip_params->nchan;
7962 rc = sysctl_wire_old_buffer(req, 0);
7966 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7970 for (i = 0; i < nchan; i++)
7971 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7974 sbuf_printf(sb, " channel 0 channel 1"
7975 " channel 2 channel 3");
7976 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7977 stats[0].octets_ddp, stats[1].octets_ddp,
7978 stats[2].octets_ddp, stats[3].octets_ddp);
7979 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7980 stats[0].frames_ddp, stats[1].frames_ddp,
7981 stats[2].frames_ddp, stats[3].frames_ddp);
7982 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7983 stats[0].frames_drop, stats[1].frames_drop,
7984 stats[2].frames_drop, stats[3].frames_drop);
7986 sbuf_printf(sb, " channel 0 channel 1");
7987 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7988 stats[0].octets_ddp, stats[1].octets_ddp);
7989 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7990 stats[0].frames_ddp, stats[1].frames_ddp);
7991 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7992 stats[0].frames_drop, stats[1].frames_drop);
7995 rc = sbuf_finish(sb);
8002 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
8004 struct adapter *sc = arg1;
8007 unsigned int map, kbps, ipg, mode;
8008 unsigned int pace_tab[NTX_SCHED];
8010 rc = sysctl_wire_old_buffer(req, 0);
8014 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8018 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
8019 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
8020 t4_read_pace_tbl(sc, pace_tab);
8022 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
8023 "Class IPG (0.1 ns) Flow IPG (us)");
8025 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
8026 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
8027 sbuf_printf(sb, "\n %u %-5s %u ", i,
8028 (mode & (1 << i)) ? "flow" : "class", map & 3);
8030 sbuf_printf(sb, "%9u ", kbps);
8032 sbuf_printf(sb, " disabled ");
8035 sbuf_printf(sb, "%13u ", ipg);
8037 sbuf_printf(sb, " disabled ");
8040 sbuf_printf(sb, "%10u", pace_tab[i]);
8042 sbuf_printf(sb, " disabled");
8045 rc = sbuf_finish(sb);
8052 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
8054 struct adapter *sc = arg1;
8058 struct lb_port_stats s[2];
8059 static const char *stat_name[] = {
8060 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
8061 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
8062 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
8063 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
8064 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
8065 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
8066 "BG2FramesTrunc:", "BG3FramesTrunc:"
8069 rc = sysctl_wire_old_buffer(req, 0);
8073 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8077 memset(s, 0, sizeof(s));
8079 for (i = 0; i < sc->chip_params->nchan; i += 2) {
8080 t4_get_lb_stats(sc, i, &s[0]);
8081 t4_get_lb_stats(sc, i + 1, &s[1]);
8085 sbuf_printf(sb, "%s Loopback %u"
8086 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
8088 for (j = 0; j < nitems(stat_name); j++)
8089 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
8093 rc = sbuf_finish(sb);
8100 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
8103 struct port_info *pi = arg1;
8104 struct link_config *lc = &pi->link_cfg;
8107 rc = sysctl_wire_old_buffer(req, 0);
8110 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
8114 if (lc->link_ok || lc->link_down_rc == 255)
8115 sbuf_printf(sb, "n/a");
8117 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
8119 rc = sbuf_finish(sb);
8132 mem_desc_cmp(const void *a, const void *b)
8134 return ((const struct mem_desc *)a)->base -
8135 ((const struct mem_desc *)b)->base;
8139 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
8147 size = to - from + 1;
8151 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
8152 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
8156 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
8158 struct adapter *sc = arg1;
8161 uint32_t lo, hi, used, alloc;
8162 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
8163 static const char *region[] = {
8164 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
8165 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
8166 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
8167 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
8168 "RQUDP region:", "PBL region:", "TXPBL region:",
8169 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
8170 "On-chip queues:", "TLS keys:",
8172 struct mem_desc avail[4];
8173 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
8174 struct mem_desc *md = mem;
8176 rc = sysctl_wire_old_buffer(req, 0);
8180 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8184 for (i = 0; i < nitems(mem); i++) {
8189 /* Find and sort the populated memory ranges */
8191 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
8192 if (lo & F_EDRAM0_ENABLE) {
8193 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
8194 avail[i].base = G_EDRAM0_BASE(hi) << 20;
8195 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
8199 if (lo & F_EDRAM1_ENABLE) {
8200 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
8201 avail[i].base = G_EDRAM1_BASE(hi) << 20;
8202 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
8206 if (lo & F_EXT_MEM_ENABLE) {
8207 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
8208 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
8209 avail[i].limit = avail[i].base +
8210 (G_EXT_MEM_SIZE(hi) << 20);
8211 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
8214 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
8215 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
8216 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
8217 avail[i].limit = avail[i].base +
8218 (G_EXT_MEM1_SIZE(hi) << 20);
8222 if (!i) /* no memory available */
8224 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8226 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8227 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8228 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8229 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8230 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8231 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8232 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8233 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8234 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8236 /* the next few have explicit upper bounds */
8237 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8238 md->limit = md->base - 1 +
8239 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8240 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8243 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8244 md->limit = md->base - 1 +
8245 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8246 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8249 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8250 if (chip_id(sc) <= CHELSIO_T5)
8251 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8253 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8257 md->idx = nitems(region); /* hide it */
8261 #define ulp_region(reg) \
8262 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8263 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8265 ulp_region(RX_ISCSI);
8266 ulp_region(RX_TDDP);
8268 ulp_region(RX_STAG);
8270 ulp_region(RX_RQUDP);
8276 md->idx = nitems(region);
8279 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8280 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8283 if (sge_ctrl & F_VFIFO_ENABLE)
8284 size = G_DBVFIFO_SIZE(fifo_size);
8286 size = G_T6_DBVFIFO_SIZE(fifo_size);
8289 md->base = G_BASEADDR(t4_read_reg(sc,
8290 A_SGE_DBVFIFO_BADDR));
8291 md->limit = md->base + (size << 2) - 1;
8296 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8299 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8303 md->base = sc->vres.ocq.start;
8304 if (sc->vres.ocq.size)
8305 md->limit = md->base + sc->vres.ocq.size - 1;
8307 md->idx = nitems(region); /* hide it */
8310 md->base = sc->vres.key.start;
8311 if (sc->vres.key.size)
8312 md->limit = md->base + sc->vres.key.size - 1;
8314 md->idx = nitems(region); /* hide it */
8317 /* add any address-space holes, there can be up to 3 */
8318 for (n = 0; n < i - 1; n++)
8319 if (avail[n].limit < avail[n + 1].base)
8320 (md++)->base = avail[n].limit;
8322 (md++)->base = avail[n].limit;
8325 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8327 for (lo = 0; lo < i; lo++)
8328 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8329 avail[lo].limit - 1);
8331 sbuf_printf(sb, "\n");
8332 for (i = 0; i < n; i++) {
8333 if (mem[i].idx >= nitems(region))
8334 continue; /* skip holes */
8336 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8337 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8341 sbuf_printf(sb, "\n");
8342 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8343 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8344 mem_region_show(sb, "uP RAM:", lo, hi);
8346 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8347 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8348 mem_region_show(sb, "uP Extmem2:", lo, hi);
8350 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8351 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8353 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8354 (lo & F_PMRXNUMCHN) ? 2 : 1);
8356 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8357 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8358 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8360 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8361 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8362 sbuf_printf(sb, "%u p-structs\n",
8363 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8365 for (i = 0; i < 4; i++) {
8366 if (chip_id(sc) > CHELSIO_T5)
8367 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8369 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8371 used = G_T5_USED(lo);
8372 alloc = G_T5_ALLOC(lo);
8375 alloc = G_ALLOC(lo);
8377 /* For T6 these are MAC buffer groups */
8378 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8381 for (i = 0; i < sc->chip_params->nchan; i++) {
8382 if (chip_id(sc) > CHELSIO_T5)
8383 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8385 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8387 used = G_T5_USED(lo);
8388 alloc = G_T5_ALLOC(lo);
8391 alloc = G_ALLOC(lo);
8393 /* For T6 these are MAC buffer groups */
8395 "\nLoopback %d using %u pages out of %u allocated",
8399 rc = sbuf_finish(sb);
8406 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8410 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8414 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8416 struct adapter *sc = arg1;
8420 MPASS(chip_id(sc) <= CHELSIO_T5);
8422 rc = sysctl_wire_old_buffer(req, 0);
8426 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8431 "Idx Ethernet address Mask Vld Ports PF"
8432 " VF Replication P0 P1 P2 P3 ML");
8433 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8434 uint64_t tcamx, tcamy, mask;
8435 uint32_t cls_lo, cls_hi;
8436 uint8_t addr[ETHER_ADDR_LEN];
8438 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8439 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8442 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8443 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8444 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8445 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8446 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8447 addr[3], addr[4], addr[5], (uintmax_t)mask,
8448 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8449 G_PORTMAP(cls_hi), G_PF(cls_lo),
8450 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8452 if (cls_lo & F_REPLICATE) {
8453 struct fw_ldst_cmd ldst_cmd;
8455 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8456 ldst_cmd.op_to_addrspace =
8457 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8458 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8459 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8460 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8461 ldst_cmd.u.mps.rplc.fid_idx =
8462 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8463 V_FW_LDST_CMD_IDX(i));
8465 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8469 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8470 sizeof(ldst_cmd), &ldst_cmd);
8471 end_synchronized_op(sc, 0);
8474 sbuf_printf(sb, "%36d", rc);
8477 sbuf_printf(sb, " %08x %08x %08x %08x",
8478 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8479 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8480 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8481 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8484 sbuf_printf(sb, "%36s", "");
8486 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8487 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8488 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8492 (void) sbuf_finish(sb);
8494 rc = sbuf_finish(sb);
8501 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8503 struct adapter *sc = arg1;
8507 MPASS(chip_id(sc) > CHELSIO_T5);
8509 rc = sysctl_wire_old_buffer(req, 0);
8513 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8517 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8518 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8520 " P0 P1 P2 P3 ML\n");
8522 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8523 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8525 uint64_t tcamx, tcamy, val, mask;
8526 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8527 uint8_t addr[ETHER_ADDR_LEN];
8529 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8531 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8533 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8534 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8535 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8536 tcamy = G_DMACH(val) << 32;
8537 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8538 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8539 lookup_type = G_DATALKPTYPE(data2);
8540 port_num = G_DATAPORTNUM(data2);
8541 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8542 /* Inner header VNI */
8543 vniy = ((data2 & F_DATAVIDH2) << 23) |
8544 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8545 dip_hit = data2 & F_DATADIPHIT;
8550 vlan_vld = data2 & F_DATAVIDH2;
8551 ivlan = G_VIDL(val);
8554 ctl |= V_CTLXYBITSEL(1);
8555 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8556 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8557 tcamx = G_DMACH(val) << 32;
8558 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8559 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8560 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8561 /* Inner header VNI mask */
8562 vnix = ((data2 & F_DATAVIDH2) << 23) |
8563 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8569 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8571 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8572 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8574 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8575 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8576 "%012jx %06x %06x - - %3c"
8577 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8578 addr[1], addr[2], addr[3], addr[4], addr[5],
8579 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8580 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8581 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8582 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8584 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8585 "%012jx - - ", i, addr[0], addr[1],
8586 addr[2], addr[3], addr[4], addr[5],
8590 sbuf_printf(sb, "%4u Y ", ivlan);
8592 sbuf_printf(sb, " - N ");
8594 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8595 lookup_type ? 'I' : 'O', port_num,
8596 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8597 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8598 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8602 if (cls_lo & F_T6_REPLICATE) {
8603 struct fw_ldst_cmd ldst_cmd;
8605 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8606 ldst_cmd.op_to_addrspace =
8607 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8608 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8609 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8610 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8611 ldst_cmd.u.mps.rplc.fid_idx =
8612 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8613 V_FW_LDST_CMD_IDX(i));
8615 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8619 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8620 sizeof(ldst_cmd), &ldst_cmd);
8621 end_synchronized_op(sc, 0);
8624 sbuf_printf(sb, "%72d", rc);
8627 sbuf_printf(sb, " %08x %08x %08x %08x"
8628 " %08x %08x %08x %08x",
8629 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8630 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8631 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8632 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8633 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8634 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8635 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8636 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8639 sbuf_printf(sb, "%72s", "");
8641 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8642 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8643 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8644 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8648 (void) sbuf_finish(sb);
8650 rc = sbuf_finish(sb);
8657 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8659 struct adapter *sc = arg1;
8662 uint16_t mtus[NMTUS];
8664 rc = sysctl_wire_old_buffer(req, 0);
8668 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8672 t4_read_mtu_tbl(sc, mtus, NULL);
8674 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8675 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8676 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8677 mtus[14], mtus[15]);
8679 rc = sbuf_finish(sb);
8686 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8688 struct adapter *sc = arg1;
8691 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8692 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8693 static const char *tx_stats[MAX_PM_NSTATS] = {
8694 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8695 "Tx FIFO wait", NULL, "Tx latency"
8697 static const char *rx_stats[MAX_PM_NSTATS] = {
8698 "Read:", "Write bypass:", "Write mem:", "Flush:",
8699 "Rx FIFO wait", NULL, "Rx latency"
8702 rc = sysctl_wire_old_buffer(req, 0);
8706 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8710 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8711 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8713 sbuf_printf(sb, " Tx pcmds Tx bytes");
8714 for (i = 0; i < 4; i++) {
8715 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8719 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8720 for (i = 0; i < 4; i++) {
8721 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8725 if (chip_id(sc) > CHELSIO_T5) {
8727 "\n Total wait Total occupancy");
8728 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8730 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8734 MPASS(i < nitems(tx_stats));
8737 "\n Reads Total wait");
8738 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8740 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8744 rc = sbuf_finish(sb);
8751 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8753 struct adapter *sc = arg1;
8756 struct tp_rdma_stats stats;
8758 rc = sysctl_wire_old_buffer(req, 0);
8762 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8766 mtx_lock(&sc->reg_lock);
8767 t4_tp_get_rdma_stats(sc, &stats, 0);
8768 mtx_unlock(&sc->reg_lock);
8770 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8771 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8773 rc = sbuf_finish(sb);
8780 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8782 struct adapter *sc = arg1;
8785 struct tp_tcp_stats v4, v6;
8787 rc = sysctl_wire_old_buffer(req, 0);
8791 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8795 mtx_lock(&sc->reg_lock);
8796 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8797 mtx_unlock(&sc->reg_lock);
8801 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8802 v4.tcp_out_rsts, v6.tcp_out_rsts);
8803 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8804 v4.tcp_in_segs, v6.tcp_in_segs);
8805 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8806 v4.tcp_out_segs, v6.tcp_out_segs);
8807 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8808 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8810 rc = sbuf_finish(sb);
8817 sysctl_tids(SYSCTL_HANDLER_ARGS)
8819 struct adapter *sc = arg1;
8822 struct tid_info *t = &sc->tids;
8824 rc = sysctl_wire_old_buffer(req, 0);
8828 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8833 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8838 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
8839 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
8843 sbuf_printf(sb, "TID range: ");
8844 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8847 if (chip_id(sc) <= CHELSIO_T5) {
8848 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8849 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8851 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8852 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8856 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
8857 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8859 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
8860 sbuf_printf(sb, ", in use: %u\n",
8861 atomic_load_acq_int(&t->tids_in_use));
8865 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8866 t->stid_base + t->nstids - 1, t->stids_in_use);
8870 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
8871 t->ftid_end, t->ftids_in_use);
8875 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8876 t->etid_base + t->netids - 1, t->etids_in_use);
8879 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8880 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8881 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8883 rc = sbuf_finish(sb);
8890 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8892 struct adapter *sc = arg1;
8895 struct tp_err_stats stats;
8897 rc = sysctl_wire_old_buffer(req, 0);
8901 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8905 mtx_lock(&sc->reg_lock);
8906 t4_tp_get_err_stats(sc, &stats, 0);
8907 mtx_unlock(&sc->reg_lock);
8909 if (sc->chip_params->nchan > 2) {
8910 sbuf_printf(sb, " channel 0 channel 1"
8911 " channel 2 channel 3\n");
8912 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8913 stats.mac_in_errs[0], stats.mac_in_errs[1],
8914 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8915 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8916 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8917 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8918 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8919 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8920 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8921 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8922 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8923 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8924 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8925 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8926 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8927 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8928 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8929 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8930 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8931 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8932 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8933 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8934 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8935 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8937 sbuf_printf(sb, " channel 0 channel 1\n");
8938 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8939 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8940 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8941 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8942 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8943 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8944 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8945 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8946 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8947 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8948 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8949 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8950 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8951 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8952 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8953 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8956 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8957 stats.ofld_no_neigh, stats.ofld_cong_defer);
8959 rc = sbuf_finish(sb);
8966 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8968 struct adapter *sc = arg1;
8969 struct tp_params *tpp = &sc->params.tp;
8973 mask = tpp->la_mask >> 16;
8974 rc = sysctl_handle_int(oidp, &mask, 0, req);
8975 if (rc != 0 || req->newptr == NULL)
8979 tpp->la_mask = mask << 16;
8980 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8992 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8998 uint64_t mask = (1ULL << f->width) - 1;
8999 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
9000 ((uintmax_t)v >> f->start) & mask);
9002 if (line_size + len >= 79) {
9004 sbuf_printf(sb, "\n ");
9006 sbuf_printf(sb, "%s ", buf);
9007 line_size += len + 1;
9010 sbuf_printf(sb, "\n");
9013 static const struct field_desc tp_la0[] = {
9014 { "RcfOpCodeOut", 60, 4 },
9016 { "WcfState", 52, 4 },
9017 { "RcfOpcSrcOut", 50, 2 },
9018 { "CRxError", 49, 1 },
9019 { "ERxError", 48, 1 },
9020 { "SanityFailed", 47, 1 },
9021 { "SpuriousMsg", 46, 1 },
9022 { "FlushInputMsg", 45, 1 },
9023 { "FlushInputCpl", 44, 1 },
9024 { "RssUpBit", 43, 1 },
9025 { "RssFilterHit", 42, 1 },
9027 { "InitTcb", 31, 1 },
9028 { "LineNumber", 24, 7 },
9030 { "EdataOut", 22, 1 },
9032 { "CdataOut", 20, 1 },
9033 { "EreadPdu", 19, 1 },
9034 { "CreadPdu", 18, 1 },
9035 { "TunnelPkt", 17, 1 },
9036 { "RcfPeerFin", 16, 1 },
9037 { "RcfReasonOut", 12, 4 },
9038 { "TxCchannel", 10, 2 },
9039 { "RcfTxChannel", 8, 2 },
9040 { "RxEchannel", 6, 2 },
9041 { "RcfRxChannel", 5, 1 },
9042 { "RcfDataOutSrdy", 4, 1 },
9044 { "RxOoDvld", 2, 1 },
9045 { "RxCongestion", 1, 1 },
9046 { "TxCongestion", 0, 1 },
9050 static const struct field_desc tp_la1[] = {
9051 { "CplCmdIn", 56, 8 },
9052 { "CplCmdOut", 48, 8 },
9053 { "ESynOut", 47, 1 },
9054 { "EAckOut", 46, 1 },
9055 { "EFinOut", 45, 1 },
9056 { "ERstOut", 44, 1 },
9061 { "DataIn", 39, 1 },
9062 { "DataInVld", 38, 1 },
9064 { "RxBufEmpty", 36, 1 },
9066 { "RxFbCongestion", 34, 1 },
9067 { "TxFbCongestion", 33, 1 },
9068 { "TxPktSumSrdy", 32, 1 },
9069 { "RcfUlpType", 28, 4 },
9071 { "Ebypass", 26, 1 },
9073 { "Static0", 24, 1 },
9075 { "Cbypass", 22, 1 },
9077 { "CPktOut", 20, 1 },
9078 { "RxPagePoolFull", 18, 2 },
9079 { "RxLpbkPkt", 17, 1 },
9080 { "TxLpbkPkt", 16, 1 },
9081 { "RxVfValid", 15, 1 },
9082 { "SynLearned", 14, 1 },
9083 { "SetDelEntry", 13, 1 },
9084 { "SetInvEntry", 12, 1 },
9085 { "CpcmdDvld", 11, 1 },
9086 { "CpcmdSave", 10, 1 },
9087 { "RxPstructsFull", 8, 2 },
9088 { "EpcmdDvld", 7, 1 },
9089 { "EpcmdFlush", 6, 1 },
9090 { "EpcmdTrimPrefix", 5, 1 },
9091 { "EpcmdTrimPostfix", 4, 1 },
9092 { "ERssIp4Pkt", 3, 1 },
9093 { "ERssIp6Pkt", 2, 1 },
9094 { "ERssTcpUdpPkt", 1, 1 },
9095 { "ERssFceFipPkt", 0, 1 },
9099 static const struct field_desc tp_la2[] = {
9100 { "CplCmdIn", 56, 8 },
9101 { "MpsVfVld", 55, 1 },
9108 { "DataIn", 39, 1 },
9109 { "DataInVld", 38, 1 },
9111 { "RxBufEmpty", 36, 1 },
9113 { "RxFbCongestion", 34, 1 },
9114 { "TxFbCongestion", 33, 1 },
9115 { "TxPktSumSrdy", 32, 1 },
9116 { "RcfUlpType", 28, 4 },
9118 { "Ebypass", 26, 1 },
9120 { "Static0", 24, 1 },
9122 { "Cbypass", 22, 1 },
9124 { "CPktOut", 20, 1 },
9125 { "RxPagePoolFull", 18, 2 },
9126 { "RxLpbkPkt", 17, 1 },
9127 { "TxLpbkPkt", 16, 1 },
9128 { "RxVfValid", 15, 1 },
9129 { "SynLearned", 14, 1 },
9130 { "SetDelEntry", 13, 1 },
9131 { "SetInvEntry", 12, 1 },
9132 { "CpcmdDvld", 11, 1 },
9133 { "CpcmdSave", 10, 1 },
9134 { "RxPstructsFull", 8, 2 },
9135 { "EpcmdDvld", 7, 1 },
9136 { "EpcmdFlush", 6, 1 },
9137 { "EpcmdTrimPrefix", 5, 1 },
9138 { "EpcmdTrimPostfix", 4, 1 },
9139 { "ERssIp4Pkt", 3, 1 },
9140 { "ERssIp6Pkt", 2, 1 },
9141 { "ERssTcpUdpPkt", 1, 1 },
9142 { "ERssFceFipPkt", 0, 1 },
9147 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
9150 field_desc_show(sb, *p, tp_la0);
9154 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
9158 sbuf_printf(sb, "\n");
9159 field_desc_show(sb, p[0], tp_la0);
9160 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9161 field_desc_show(sb, p[1], tp_la0);
9165 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
9169 sbuf_printf(sb, "\n");
9170 field_desc_show(sb, p[0], tp_la0);
9171 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9172 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
9176 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
9178 struct adapter *sc = arg1;
9183 void (*show_func)(struct sbuf *, uint64_t *, int);
9185 rc = sysctl_wire_old_buffer(req, 0);
9189 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9193 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
9195 t4_tp_read_la(sc, buf, NULL);
9198 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
9201 show_func = tp_la_show2;
9205 show_func = tp_la_show3;
9209 show_func = tp_la_show;
9212 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
9213 (*show_func)(sb, p, i);
9215 rc = sbuf_finish(sb);
9222 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9224 struct adapter *sc = arg1;
9227 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9229 rc = sysctl_wire_old_buffer(req, 0);
9233 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9237 t4_get_chan_txrate(sc, nrate, orate);
9239 if (sc->chip_params->nchan > 2) {
9240 sbuf_printf(sb, " channel 0 channel 1"
9241 " channel 2 channel 3\n");
9242 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9243 nrate[0], nrate[1], nrate[2], nrate[3]);
9244 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9245 orate[0], orate[1], orate[2], orate[3]);
9247 sbuf_printf(sb, " channel 0 channel 1\n");
9248 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9249 nrate[0], nrate[1]);
9250 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9251 orate[0], orate[1]);
9254 rc = sbuf_finish(sb);
9261 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9263 struct adapter *sc = arg1;
9268 rc = sysctl_wire_old_buffer(req, 0);
9272 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9276 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9279 t4_ulprx_read_la(sc, buf);
9282 sbuf_printf(sb, " Pcmd Type Message"
9284 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9285 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9286 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9289 rc = sbuf_finish(sb);
9296 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9298 struct adapter *sc = arg1;
9302 MPASS(chip_id(sc) >= CHELSIO_T5);
9304 rc = sysctl_wire_old_buffer(req, 0);
9308 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9312 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9313 if (G_STATSOURCE_T5(v) == 7) {
9316 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9318 sbuf_printf(sb, "total %d, incomplete %d",
9319 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9320 t4_read_reg(sc, A_SGE_STAT_MATCH));
9321 } else if (mode == 1) {
9322 sbuf_printf(sb, "total %d, data overflow %d",
9323 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9324 t4_read_reg(sc, A_SGE_STAT_MATCH));
9326 sbuf_printf(sb, "unknown mode %d", mode);
9329 rc = sbuf_finish(sb);
9336 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9338 struct adapter *sc = arg1;
9339 enum cpu_sets op = arg2;
9344 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9347 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9351 rc = sysctl_wire_old_buffer(req, 0);
9355 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9360 sbuf_printf(sb, "%d ", i);
9361 rc = sbuf_finish(sb);
9369 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9371 struct adapter *sc = arg1;
9372 int *old_ports, *new_ports;
9373 int i, new_count, rc;
9375 if (req->newptr == NULL && req->oldptr == NULL)
9376 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9377 sizeof(sc->tt.tls_rx_ports[0])));
9379 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9383 if (sc->tt.num_tls_rx_ports == 0) {
9385 rc = SYSCTL_OUT(req, &i, sizeof(i));
9387 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9388 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9389 if (rc == 0 && req->newptr != NULL) {
9390 new_count = req->newlen / sizeof(new_ports[0]);
9391 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9393 rc = SYSCTL_IN(req, new_ports, new_count *
9394 sizeof(new_ports[0]));
9398 /* Allow setting to a single '-1' to clear the list. */
9399 if (new_count == 1 && new_ports[0] == -1) {
9401 old_ports = sc->tt.tls_rx_ports;
9402 sc->tt.tls_rx_ports = NULL;
9403 sc->tt.num_tls_rx_ports = 0;
9405 free(old_ports, M_CXGBE);
9407 for (i = 0; i < new_count; i++) {
9408 if (new_ports[i] < 1 ||
9409 new_ports[i] > IPPORT_MAX) {
9416 old_ports = sc->tt.tls_rx_ports;
9417 sc->tt.tls_rx_ports = new_ports;
9418 sc->tt.num_tls_rx_ports = new_count;
9420 free(old_ports, M_CXGBE);
9424 free(new_ports, M_CXGBE);
9426 end_synchronized_op(sc, 0);
9431 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9433 u_int rem = val % factor;
9436 snprintf(buf, len, "%u", val / factor);
9438 while (rem % 10 == 0)
9440 snprintf(buf, len, "%u.%u", val / factor, rem);
9445 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9447 struct adapter *sc = arg1;
9450 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9452 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9456 re = G_TIMERRESOLUTION(res);
9459 /* TCP timestamp tick */
9460 re = G_TIMESTAMPRESOLUTION(res);
9464 re = G_DELAYEDACKRESOLUTION(res);
9470 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9472 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9476 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9478 struct adapter *sc = arg1;
9479 u_int res, dack_re, v;
9480 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9482 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9483 dack_re = G_DELAYEDACKRESOLUTION(res);
9484 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9486 return (sysctl_handle_int(oidp, &v, 0, req));
9490 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9492 struct adapter *sc = arg1;
9495 u_long tp_tick_us, v;
9496 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9498 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9499 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9500 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9501 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9503 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9504 tp_tick_us = (cclk_ps << tre) / 1000000;
9506 if (reg == A_TP_INIT_SRTT)
9507 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9509 v = tp_tick_us * t4_read_reg(sc, reg);
9511 return (sysctl_handle_long(oidp, &v, 0, req));
9515 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9516 * passed to this function.
9519 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9521 struct adapter *sc = arg1;
9525 MPASS(idx >= 0 && idx <= 24);
9527 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9529 return (sysctl_handle_int(oidp, &v, 0, req));
9533 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9535 struct adapter *sc = arg1;
9539 MPASS(idx >= 0 && idx < 16);
9541 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9542 shift = (idx & 3) << 3;
9543 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9545 return (sysctl_handle_int(oidp, &v, 0, req));
9549 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9551 struct vi_info *vi = arg1;
9552 struct adapter *sc = vi->pi->adapter;
9554 struct sge_ofld_rxq *ofld_rxq;
9557 idx = vi->ofld_tmr_idx;
9559 rc = sysctl_handle_int(oidp, &idx, 0, req);
9560 if (rc != 0 || req->newptr == NULL)
9563 if (idx < 0 || idx >= SGE_NTIMERS)
9566 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9571 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9572 for_each_ofld_rxq(vi, i, ofld_rxq) {
9573 #ifdef atomic_store_rel_8
9574 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9576 ofld_rxq->iq.intr_params = v;
9579 vi->ofld_tmr_idx = idx;
9581 end_synchronized_op(sc, LOCK_HELD);
9586 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9588 struct vi_info *vi = arg1;
9589 struct adapter *sc = vi->pi->adapter;
9592 idx = vi->ofld_pktc_idx;
9594 rc = sysctl_handle_int(oidp, &idx, 0, req);
9595 if (rc != 0 || req->newptr == NULL)
9598 if (idx < -1 || idx >= SGE_NCOUNTERS)
9601 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9606 if (vi->flags & VI_INIT_DONE)
9607 rc = EBUSY; /* cannot be changed once the queues are created */
9609 vi->ofld_pktc_idx = idx;
9611 end_synchronized_op(sc, LOCK_HELD);
9617 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9621 if (cntxt->cid > M_CTXTQID)
9624 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9625 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9628 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9632 if (sc->flags & FW_OK) {
9633 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9640 * Read via firmware failed or wasn't even attempted. Read directly via
9643 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9645 end_synchronized_op(sc, 0);
9650 load_fw(struct adapter *sc, struct t4_data *fw)
9655 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9660 * The firmware, with the sole exception of the memory parity error
9661 * handler, runs from memory and not flash. It is almost always safe to
9662 * install a new firmware on a running system. Just set bit 1 in
9663 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9665 if (sc->flags & FULL_INIT_DONE &&
9666 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9671 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9672 if (fw_data == NULL) {
9677 rc = copyin(fw->data, fw_data, fw->len);
9679 rc = -t4_load_fw(sc, fw_data, fw->len);
9681 free(fw_data, M_CXGBE);
9683 end_synchronized_op(sc, 0);
9688 load_cfg(struct adapter *sc, struct t4_data *cfg)
9691 uint8_t *cfg_data = NULL;
9693 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9697 if (cfg->len == 0) {
9699 rc = -t4_load_cfg(sc, NULL, 0);
9703 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9704 if (cfg_data == NULL) {
9709 rc = copyin(cfg->data, cfg_data, cfg->len);
9711 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9713 free(cfg_data, M_CXGBE);
9715 end_synchronized_op(sc, 0);
9720 load_boot(struct adapter *sc, struct t4_bootrom *br)
9723 uint8_t *br_data = NULL;
9726 if (br->len > 1024 * 1024)
9729 if (br->pf_offset == 0) {
9731 if (br->pfidx_addr > 7)
9733 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9734 A_PCIE_PF_EXPROM_OFST)));
9735 } else if (br->pf_offset == 1) {
9737 offset = G_OFFSET(br->pfidx_addr);
9742 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9748 rc = -t4_load_boot(sc, NULL, offset, 0);
9752 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9753 if (br_data == NULL) {
9758 rc = copyin(br->data, br_data, br->len);
9760 rc = -t4_load_boot(sc, br_data, offset, br->len);
9762 free(br_data, M_CXGBE);
9764 end_synchronized_op(sc, 0);
9769 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9772 uint8_t *bc_data = NULL;
9774 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9780 rc = -t4_load_bootcfg(sc, NULL, 0);
9784 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9785 if (bc_data == NULL) {
9790 rc = copyin(bc->data, bc_data, bc->len);
9792 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9794 free(bc_data, M_CXGBE);
9796 end_synchronized_op(sc, 0);
9801 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9804 struct cudbg_init *cudbg;
9807 /* buf is large, don't block if no memory is available */
9808 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9812 handle = cudbg_alloc_handle();
9813 if (handle == NULL) {
9818 cudbg = cudbg_get_init(handle);
9820 cudbg->print = (cudbg_print_cb)printf;
9823 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9824 __func__, dump->wr_flash, dump->len, dump->data);
9828 cudbg->use_flash = 1;
9829 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9830 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9832 rc = cudbg_collect(handle, buf, &dump->len);
9836 rc = copyout(buf, dump->data, dump->len);
9838 cudbg_free_handle(handle);
9844 free_offload_policy(struct t4_offload_policy *op)
9846 struct offload_rule *r;
9853 for (i = 0; i < op->nrules; i++, r++) {
9854 free(r->bpf_prog.bf_insns, M_CXGBE);
9856 free(op->rule, M_CXGBE);
9861 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9864 struct t4_offload_policy *op, *old;
9865 struct bpf_program *bf;
9866 const struct offload_settings *s;
9867 struct offload_rule *r;
9870 if (!is_offload(sc))
9873 if (uop->nrules == 0) {
9874 /* Delete installed policies. */
9877 } else if (uop->nrules > 256) { /* arbitrary */
9881 /* Copy userspace offload policy to kernel */
9882 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9883 op->nrules = uop->nrules;
9884 len = op->nrules * sizeof(struct offload_rule);
9885 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9886 rc = copyin(uop->rule, op->rule, len);
9888 free(op->rule, M_CXGBE);
9894 for (i = 0; i < op->nrules; i++, r++) {
9896 /* Validate open_type */
9897 if (r->open_type != OPEN_TYPE_LISTEN &&
9898 r->open_type != OPEN_TYPE_ACTIVE &&
9899 r->open_type != OPEN_TYPE_PASSIVE &&
9900 r->open_type != OPEN_TYPE_DONTCARE) {
9903 * Rules 0 to i have malloc'd filters that need to be
9904 * freed. Rules i+1 to nrules have userspace pointers
9905 * and should be left alone.
9908 free_offload_policy(op);
9912 /* Validate settings */
9914 if ((s->offload != 0 && s->offload != 1) ||
9915 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9916 s->sched_class < -1 ||
9917 s->sched_class >= sc->chip_params->nsched_cls) {
9923 u = bf->bf_insns; /* userspace ptr */
9924 bf->bf_insns = NULL;
9925 if (bf->bf_len == 0) {
9926 /* legal, matches everything */
9929 len = bf->bf_len * sizeof(*bf->bf_insns);
9930 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9931 rc = copyin(u, bf->bf_insns, len);
9935 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9941 rw_wlock(&sc->policy_lock);
9944 rw_wunlock(&sc->policy_lock);
9945 free_offload_policy(old);
9950 #define MAX_READ_BUF_SIZE (128 * 1024)
9952 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9954 uint32_t addr, remaining, n;
9959 rc = validate_mem_range(sc, mr->addr, mr->len);
9963 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9965 remaining = mr->len;
9966 dst = (void *)mr->data;
9969 n = min(remaining, MAX_READ_BUF_SIZE);
9970 read_via_memwin(sc, 2, addr, buf, n);
9972 rc = copyout(buf, dst, n);
9984 #undef MAX_READ_BUF_SIZE
9987 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9991 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9994 if (i2cd->len > sizeof(i2cd->data))
9997 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
10000 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
10001 i2cd->offset, i2cd->len, &i2cd->data[0]);
10002 end_synchronized_op(sc, 0);
10008 clear_stats(struct adapter *sc, u_int port_id)
10011 struct port_info *pi;
10012 struct vi_info *vi;
10013 struct sge_rxq *rxq;
10014 struct sge_txq *txq;
10015 struct sge_wrq *wrq;
10017 struct sge_ofld_rxq *ofld_rxq;
10020 if (port_id >= sc->params.nports)
10022 pi = sc->port[port_id];
10027 t4_clr_port_stats(sc, pi->tx_chan);
10028 pi->tx_parse_error = 0;
10029 pi->tnl_cong_drops = 0;
10030 mtx_lock(&sc->reg_lock);
10031 for_each_vi(pi, v, vi) {
10032 if (vi->flags & VI_INIT_DONE)
10033 t4_clr_vi_stats(sc, vi->vin);
10035 bg_map = pi->mps_bg_map;
10038 i = ffs(bg_map) - 1;
10039 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10040 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10041 bg_map &= ~(1 << i);
10043 mtx_unlock(&sc->reg_lock);
10046 * Since this command accepts a port, clear stats for
10047 * all VIs on this port.
10049 for_each_vi(pi, v, vi) {
10050 if (vi->flags & VI_INIT_DONE) {
10052 for_each_rxq(vi, i, rxq) {
10053 #if defined(INET) || defined(INET6)
10054 rxq->lro.lro_queued = 0;
10055 rxq->lro.lro_flushed = 0;
10058 rxq->vlan_extraction = 0;
10060 rxq->fl.mbuf_allocated = 0;
10061 rxq->fl.mbuf_inlined = 0;
10062 rxq->fl.cl_allocated = 0;
10063 rxq->fl.cl_recycled = 0;
10064 rxq->fl.cl_fast_recycled = 0;
10067 for_each_txq(vi, i, txq) {
10070 txq->vlan_insertion = 0;
10073 txq->txpkt_wrs = 0;
10074 txq->txpkts0_wrs = 0;
10075 txq->txpkts1_wrs = 0;
10076 txq->txpkts0_pkts = 0;
10077 txq->txpkts1_pkts = 0;
10079 mp_ring_reset_stats(txq->r);
10082 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10083 for_each_ofld_txq(vi, i, wrq) {
10084 wrq->tx_wrs_direct = 0;
10085 wrq->tx_wrs_copied = 0;
10089 for_each_ofld_rxq(vi, i, ofld_rxq) {
10090 ofld_rxq->fl.mbuf_allocated = 0;
10091 ofld_rxq->fl.mbuf_inlined = 0;
10092 ofld_rxq->fl.cl_allocated = 0;
10093 ofld_rxq->fl.cl_recycled = 0;
10094 ofld_rxq->fl.cl_fast_recycled = 0;
10098 if (IS_MAIN_VI(vi)) {
10099 wrq = &sc->sge.ctrlq[pi->port_id];
10100 wrq->tx_wrs_direct = 0;
10101 wrq->tx_wrs_copied = 0;
10110 t4_os_find_pci_capability(struct adapter *sc, int cap)
10114 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
10118 t4_os_pci_save_state(struct adapter *sc)
10121 struct pci_devinfo *dinfo;
10124 dinfo = device_get_ivars(dev);
10126 pci_cfg_save(dev, dinfo, 0);
10131 t4_os_pci_restore_state(struct adapter *sc)
10134 struct pci_devinfo *dinfo;
10137 dinfo = device_get_ivars(dev);
10139 pci_cfg_restore(dev, dinfo);
10144 t4_os_portmod_changed(struct port_info *pi)
10146 struct adapter *sc = pi->adapter;
10147 struct vi_info *vi;
10149 static const char *mod_str[] = {
10150 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
10153 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
10154 ("%s: port_type %u", __func__, pi->port_type));
10157 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
10159 build_medialist(pi);
10160 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
10161 fixup_link_config(pi);
10162 apply_link_config(pi);
10165 end_synchronized_op(sc, LOCK_HELD);
10169 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
10170 if_printf(ifp, "transceiver unplugged.\n");
10171 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
10172 if_printf(ifp, "unknown transceiver inserted.\n");
10173 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
10174 if_printf(ifp, "unsupported transceiver inserted.\n");
10175 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
10176 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
10177 port_top_speed(pi), mod_str[pi->mod_type]);
10179 if_printf(ifp, "transceiver (type %d) inserted.\n",
10185 t4_os_link_changed(struct port_info *pi)
10187 struct vi_info *vi;
10189 struct link_config *lc;
10192 PORT_LOCK_ASSERT_OWNED(pi);
10194 for_each_vi(pi, v, vi) {
10199 lc = &pi->link_cfg;
10201 ifp->if_baudrate = IF_Mbps(lc->speed);
10202 if_link_state_change(ifp, LINK_STATE_UP);
10204 if_link_state_change(ifp, LINK_STATE_DOWN);
10210 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
10212 struct adapter *sc;
10214 sx_slock(&t4_list_lock);
10215 SLIST_FOREACH(sc, &t4_list, link) {
10217 * func should not make any assumptions about what state sc is
10218 * in - the only guarantee is that sc->sc_lock is a valid lock.
10222 sx_sunlock(&t4_list_lock);
10226 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
10230 struct adapter *sc = dev->si_drv1;
10232 rc = priv_check(td, PRIV_DRIVER);
10237 case CHELSIO_T4_GETREG: {
10238 struct t4_reg *edata = (struct t4_reg *)data;
10240 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10243 if (edata->size == 4)
10244 edata->val = t4_read_reg(sc, edata->addr);
10245 else if (edata->size == 8)
10246 edata->val = t4_read_reg64(sc, edata->addr);
10252 case CHELSIO_T4_SETREG: {
10253 struct t4_reg *edata = (struct t4_reg *)data;
10255 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10258 if (edata->size == 4) {
10259 if (edata->val & 0xffffffff00000000)
10261 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
10262 } else if (edata->size == 8)
10263 t4_write_reg64(sc, edata->addr, edata->val);
10268 case CHELSIO_T4_REGDUMP: {
10269 struct t4_regdump *regs = (struct t4_regdump *)data;
10270 int reglen = t4_get_regs_len(sc);
10273 if (regs->len < reglen) {
10274 regs->len = reglen; /* hint to the caller */
10278 regs->len = reglen;
10279 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
10280 get_regs(sc, regs, buf);
10281 rc = copyout(buf, regs->data, reglen);
10282 free(buf, M_CXGBE);
10285 case CHELSIO_T4_GET_FILTER_MODE:
10286 rc = get_filter_mode(sc, (uint32_t *)data);
10288 case CHELSIO_T4_SET_FILTER_MODE:
10289 rc = set_filter_mode(sc, *(uint32_t *)data);
10291 case CHELSIO_T4_GET_FILTER:
10292 rc = get_filter(sc, (struct t4_filter *)data);
10294 case CHELSIO_T4_SET_FILTER:
10295 rc = set_filter(sc, (struct t4_filter *)data);
10297 case CHELSIO_T4_DEL_FILTER:
10298 rc = del_filter(sc, (struct t4_filter *)data);
10300 case CHELSIO_T4_GET_SGE_CONTEXT:
10301 rc = get_sge_context(sc, (struct t4_sge_context *)data);
10303 case CHELSIO_T4_LOAD_FW:
10304 rc = load_fw(sc, (struct t4_data *)data);
10306 case CHELSIO_T4_GET_MEM:
10307 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
10309 case CHELSIO_T4_GET_I2C:
10310 rc = read_i2c(sc, (struct t4_i2c_data *)data);
10312 case CHELSIO_T4_CLEAR_STATS:
10313 rc = clear_stats(sc, *(uint32_t *)data);
10315 case CHELSIO_T4_SCHED_CLASS:
10316 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10318 case CHELSIO_T4_SCHED_QUEUE:
10319 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10321 case CHELSIO_T4_GET_TRACER:
10322 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10324 case CHELSIO_T4_SET_TRACER:
10325 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10327 case CHELSIO_T4_LOAD_CFG:
10328 rc = load_cfg(sc, (struct t4_data *)data);
10330 case CHELSIO_T4_LOAD_BOOT:
10331 rc = load_boot(sc, (struct t4_bootrom *)data);
10333 case CHELSIO_T4_LOAD_BOOTCFG:
10334 rc = load_bootcfg(sc, (struct t4_data *)data);
10336 case CHELSIO_T4_CUDBG_DUMP:
10337 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10339 case CHELSIO_T4_SET_OFLD_POLICY:
10340 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10351 toe_capability(struct vi_info *vi, int enable)
10354 struct port_info *pi = vi->pi;
10355 struct adapter *sc = pi->adapter;
10357 ASSERT_SYNCHRONIZED_OP(sc);
10359 if (!is_offload(sc))
10363 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10364 /* TOE is already enabled. */
10369 * We need the port's queues around so that we're able to send
10370 * and receive CPLs to/from the TOE even if the ifnet for this
10371 * port has never been UP'd administratively.
10373 if (!(vi->flags & VI_INIT_DONE)) {
10374 rc = vi_full_init(vi);
10378 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10379 rc = vi_full_init(&pi->vi[0]);
10384 if (isset(&sc->offload_map, pi->port_id)) {
10385 /* TOE is enabled on another VI of this port. */
10390 if (!uld_active(sc, ULD_TOM)) {
10391 rc = t4_activate_uld(sc, ULD_TOM);
10392 if (rc == EAGAIN) {
10394 "You must kldload t4_tom.ko before trying "
10395 "to enable TOE on a cxgbe interface.\n");
10399 KASSERT(sc->tom_softc != NULL,
10400 ("%s: TOM activated but softc NULL", __func__));
10401 KASSERT(uld_active(sc, ULD_TOM),
10402 ("%s: TOM activated but flag not set", __func__));
10405 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10406 if (!uld_active(sc, ULD_IWARP))
10407 (void) t4_activate_uld(sc, ULD_IWARP);
10408 if (!uld_active(sc, ULD_ISCSI))
10409 (void) t4_activate_uld(sc, ULD_ISCSI);
10412 setbit(&sc->offload_map, pi->port_id);
10416 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10419 KASSERT(uld_active(sc, ULD_TOM),
10420 ("%s: TOM never initialized?", __func__));
10421 clrbit(&sc->offload_map, pi->port_id);
10428 * Add an upper layer driver to the global list.
10431 t4_register_uld(struct uld_info *ui)
10434 struct uld_info *u;
10436 sx_xlock(&t4_uld_list_lock);
10437 SLIST_FOREACH(u, &t4_uld_list, link) {
10438 if (u->uld_id == ui->uld_id) {
10444 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10447 sx_xunlock(&t4_uld_list_lock);
10452 t4_unregister_uld(struct uld_info *ui)
10455 struct uld_info *u;
10457 sx_xlock(&t4_uld_list_lock);
10459 SLIST_FOREACH(u, &t4_uld_list, link) {
10461 if (ui->refcount > 0) {
10466 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10472 sx_xunlock(&t4_uld_list_lock);
10477 t4_activate_uld(struct adapter *sc, int id)
10480 struct uld_info *ui;
10482 ASSERT_SYNCHRONIZED_OP(sc);
10484 if (id < 0 || id > ULD_MAX)
10486 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10488 sx_slock(&t4_uld_list_lock);
10490 SLIST_FOREACH(ui, &t4_uld_list, link) {
10491 if (ui->uld_id == id) {
10492 if (!(sc->flags & FULL_INIT_DONE)) {
10493 rc = adapter_full_init(sc);
10498 rc = ui->activate(sc);
10500 setbit(&sc->active_ulds, id);
10507 sx_sunlock(&t4_uld_list_lock);
10513 t4_deactivate_uld(struct adapter *sc, int id)
10516 struct uld_info *ui;
10518 ASSERT_SYNCHRONIZED_OP(sc);
10520 if (id < 0 || id > ULD_MAX)
10524 sx_slock(&t4_uld_list_lock);
10526 SLIST_FOREACH(ui, &t4_uld_list, link) {
10527 if (ui->uld_id == id) {
10528 rc = ui->deactivate(sc);
10530 clrbit(&sc->active_ulds, id);
10537 sx_sunlock(&t4_uld_list_lock);
10543 uld_active(struct adapter *sc, int uld_id)
10546 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10548 return (isset(&sc->active_ulds, uld_id));
10553 * t = ptr to tunable.
10554 * nc = number of CPUs.
10555 * c = compiled in default for that tunable.
10558 calculate_nqueues(int *t, int nc, const int c)
10564 nq = *t < 0 ? -*t : c;
10569 * Come up with reasonable defaults for some of the tunables, provided they're
10570 * not set by the user (in which case we'll use the values as is).
10573 tweak_tunables(void)
10575 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10579 t4_ntxq = rss_getnumbuckets();
10581 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10585 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10589 t4_nrxq = rss_getnumbuckets();
10591 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10595 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10597 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10598 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10599 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10602 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10603 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10605 if (t4_toecaps_allowed == -1)
10606 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10608 if (t4_rdmacaps_allowed == -1) {
10609 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10610 FW_CAPS_CONFIG_RDMA_RDMAC;
10613 if (t4_iscsicaps_allowed == -1) {
10614 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10615 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10616 FW_CAPS_CONFIG_ISCSI_T10DIF;
10619 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10620 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10622 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10623 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10625 if (t4_toecaps_allowed == -1)
10626 t4_toecaps_allowed = 0;
10628 if (t4_rdmacaps_allowed == -1)
10629 t4_rdmacaps_allowed = 0;
10631 if (t4_iscsicaps_allowed == -1)
10632 t4_iscsicaps_allowed = 0;
10636 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10637 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10640 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10641 t4_tmr_idx = TMR_IDX;
10643 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10644 t4_pktc_idx = PKTC_IDX;
10646 if (t4_qsize_txq < 128)
10647 t4_qsize_txq = 128;
10649 if (t4_qsize_rxq < 128)
10650 t4_qsize_rxq = 128;
10651 while (t4_qsize_rxq & 7)
10654 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10657 * Number of VIs to create per-port. The first VI is the "main" regular
10658 * VI for the port. The rest are additional virtual interfaces on the
10659 * same physical port. Note that the main VI does not have native
10660 * netmap support but the extra VIs do.
10662 * Limit the number of VIs per port to the number of available
10663 * MAC addresses per port.
10665 if (t4_num_vis < 1)
10667 if (t4_num_vis > nitems(vi_mac_funcs)) {
10668 t4_num_vis = nitems(vi_mac_funcs);
10669 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10672 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10673 pcie_relaxed_ordering = 1;
10674 #if defined(__i386__) || defined(__amd64__)
10675 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10676 pcie_relaxed_ordering = 0;
10683 t4_dump_tcb(struct adapter *sc, int tid)
10685 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10687 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10688 save = t4_read_reg(sc, reg);
10689 base = sc->memwin[2].mw_base;
10691 /* Dump TCB for the tid */
10692 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10693 tcb_addr += tid * TCB_SIZE;
10697 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10699 pf = V_PFNUM(sc->pf);
10700 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10702 t4_write_reg(sc, reg, win_pos | pf);
10703 t4_read_reg(sc, reg);
10705 off = tcb_addr - win_pos;
10706 for (i = 0; i < 4; i++) {
10708 for (j = 0; j < 8; j++, off += 4)
10709 buf[j] = htonl(t4_read_reg(sc, base + off));
10711 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10712 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10716 t4_write_reg(sc, reg, save);
10717 t4_read_reg(sc, reg);
10721 t4_dump_devlog(struct adapter *sc)
10723 struct devlog_params *dparams = &sc->params.devlog;
10724 struct fw_devlog_e e;
10725 int i, first, j, m, nentries, rc;
10726 uint64_t ftstamp = UINT64_MAX;
10728 if (dparams->start == 0) {
10729 db_printf("devlog params not valid\n");
10733 nentries = dparams->size / sizeof(struct fw_devlog_e);
10734 m = fwmtype_to_hwmtype(dparams->memtype);
10736 /* Find the first entry. */
10738 for (i = 0; i < nentries && !db_pager_quit; i++) {
10739 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10740 sizeof(e), (void *)&e);
10744 if (e.timestamp == 0)
10747 e.timestamp = be64toh(e.timestamp);
10748 if (e.timestamp < ftstamp) {
10749 ftstamp = e.timestamp;
10759 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10760 sizeof(e), (void *)&e);
10764 if (e.timestamp == 0)
10767 e.timestamp = be64toh(e.timestamp);
10768 e.seqno = be32toh(e.seqno);
10769 for (j = 0; j < 8; j++)
10770 e.params[j] = be32toh(e.params[j]);
10772 db_printf("%10d %15ju %8s %8s ",
10773 e.seqno, e.timestamp,
10774 (e.level < nitems(devlog_level_strings) ?
10775 devlog_level_strings[e.level] : "UNKNOWN"),
10776 (e.facility < nitems(devlog_facility_strings) ?
10777 devlog_facility_strings[e.facility] : "UNKNOWN"));
10778 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10779 e.params[3], e.params[4], e.params[5], e.params[6],
10782 if (++i == nentries)
10784 } while (i != first && !db_pager_quit);
10787 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10788 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10790 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10797 t = db_read_token();
10799 dev = device_lookup_by_name(db_tok_string);
10804 db_printf("usage: show t4 devlog <nexus>\n");
10809 db_printf("device not found\n");
10813 t4_dump_devlog(device_get_softc(dev));
10816 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10825 t = db_read_token();
10827 dev = device_lookup_by_name(db_tok_string);
10828 t = db_read_token();
10829 if (t == tNUMBER) {
10830 tid = db_tok_number;
10837 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10842 db_printf("device not found\n");
10846 db_printf("invalid tid\n");
10850 t4_dump_tcb(device_get_softc(dev), tid);
10855 * Borrowed from cesa_prep_aes_key().
10857 * NB: The crypto engine wants the words in the decryption key in reverse
10861 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10863 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10867 rijndaelKeySetupEnc(ek, enc_key, kbits);
10869 dkey += (kbits / 8) / 4;
10873 for (i = 0; i < 4; i++)
10874 *--dkey = htobe32(ek[4 * 10 + i]);
10877 for (i = 0; i < 2; i++)
10878 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10879 for (i = 0; i < 4; i++)
10880 *--dkey = htobe32(ek[4 * 12 + i]);
10883 for (i = 0; i < 4; i++)
10884 *--dkey = htobe32(ek[4 * 13 + i]);
10885 for (i = 0; i < 4; i++)
10886 *--dkey = htobe32(ek[4 * 14 + i]);
10889 MPASS(dkey == dec_key);
10892 static struct sx mlu; /* mod load unload */
10893 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10896 mod_event(module_t mod, int cmd, void *arg)
10899 static int loaded = 0;
10904 if (loaded++ == 0) {
10906 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10907 t4_filter_rpl, CPL_COOKIE_FILTER);
10908 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10909 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10910 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10911 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10912 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10913 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10914 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10915 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10916 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10917 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10918 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10920 sx_init(&t4_list_lock, "T4/T5 adapters");
10921 SLIST_INIT(&t4_list);
10922 callout_init(&fatal_callout, 1);
10924 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10925 SLIST_INIT(&t4_uld_list);
10930 t4_tracer_modload();
10938 if (--loaded == 0) {
10941 sx_slock(&t4_list_lock);
10942 if (!SLIST_EMPTY(&t4_list)) {
10944 sx_sunlock(&t4_list_lock);
10948 sx_slock(&t4_uld_list_lock);
10949 if (!SLIST_EMPTY(&t4_uld_list)) {
10951 sx_sunlock(&t4_uld_list_lock);
10952 sx_sunlock(&t4_list_lock);
10957 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10958 uprintf("%ju clusters with custom free routine "
10959 "still is use.\n", t4_sge_extfree_refs());
10960 pause("t4unload", 2 * hz);
10963 sx_sunlock(&t4_uld_list_lock);
10965 sx_sunlock(&t4_list_lock);
10967 if (t4_sge_extfree_refs() == 0) {
10968 t4_tracer_modunload();
10970 t4_clip_modunload();
10973 sx_destroy(&t4_uld_list_lock);
10975 sx_destroy(&t4_list_lock);
10976 t4_sge_modunload();
10980 loaded++; /* undo earlier decrement */
10991 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10992 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10993 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10995 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10996 MODULE_VERSION(t4nex, 1);
10997 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10999 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
11000 #endif /* DEV_NETMAP */
11002 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
11003 MODULE_VERSION(t5nex, 1);
11004 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
11006 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
11007 #endif /* DEV_NETMAP */
11009 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
11010 MODULE_VERSION(t6nex, 1);
11011 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
11013 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
11014 #endif /* DEV_NETMAP */
11016 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
11017 MODULE_VERSION(cxgbe, 1);
11019 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
11020 MODULE_VERSION(cxl, 1);
11022 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
11023 MODULE_VERSION(cc, 1);
11025 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
11026 MODULE_VERSION(vcxgbe, 1);
11028 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
11029 MODULE_VERSION(vcxl, 1);
11031 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
11032 MODULE_VERSION(vcc, 1);