2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_kern_tls.h"
37 #include "opt_ratelimit.h"
40 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
47 #include <sys/queue.h>
48 #include <sys/taskqueue.h>
49 #include <sys/pciio.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pci_private.h>
53 #include <sys/firmware.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
58 #include <sys/sysctl.h>
59 #include <net/ethernet.h>
61 #include <net/if_types.h>
62 #include <net/if_dl.h>
63 #include <net/if_vlan_var.h>
65 #include <net/rss_config.h>
67 #include <netinet/in.h>
68 #include <netinet/ip.h>
70 #include <netinet/tcp_seq.h>
72 #if defined(__i386__) || defined(__amd64__)
73 #include <machine/md_var.h>
74 #include <machine/cputypes.h>
80 #include <ddb/db_lex.h>
83 #include "common/common.h"
84 #include "common/t4_msg.h"
85 #include "common/t4_regs.h"
86 #include "common/t4_regs_values.h"
87 #include "cudbg/cudbg.h"
91 #include "t4_mp_ring.h"
95 /* T4 bus driver interface */
96 static int t4_probe(device_t);
97 static int t4_attach(device_t);
98 static int t4_detach(device_t);
99 static int t4_child_location_str(device_t, device_t, char *, size_t);
100 static int t4_ready(device_t);
101 static int t4_read_port_device(device_t, int, device_t *);
102 static device_method_t t4_methods[] = {
103 DEVMETHOD(device_probe, t4_probe),
104 DEVMETHOD(device_attach, t4_attach),
105 DEVMETHOD(device_detach, t4_detach),
107 DEVMETHOD(bus_child_location_str, t4_child_location_str),
109 DEVMETHOD(t4_is_main_ready, t4_ready),
110 DEVMETHOD(t4_read_port_device, t4_read_port_device),
114 static driver_t t4_driver = {
117 sizeof(struct adapter)
121 /* T4 port (cxgbe) interface */
122 static int cxgbe_probe(device_t);
123 static int cxgbe_attach(device_t);
124 static int cxgbe_detach(device_t);
125 device_method_t cxgbe_methods[] = {
126 DEVMETHOD(device_probe, cxgbe_probe),
127 DEVMETHOD(device_attach, cxgbe_attach),
128 DEVMETHOD(device_detach, cxgbe_detach),
131 static driver_t cxgbe_driver = {
134 sizeof(struct port_info)
137 /* T4 VI (vcxgbe) interface */
138 static int vcxgbe_probe(device_t);
139 static int vcxgbe_attach(device_t);
140 static int vcxgbe_detach(device_t);
141 static device_method_t vcxgbe_methods[] = {
142 DEVMETHOD(device_probe, vcxgbe_probe),
143 DEVMETHOD(device_attach, vcxgbe_attach),
144 DEVMETHOD(device_detach, vcxgbe_detach),
147 static driver_t vcxgbe_driver = {
150 sizeof(struct vi_info)
153 static d_ioctl_t t4_ioctl;
155 static struct cdevsw t4_cdevsw = {
156 .d_version = D_VERSION,
161 /* T5 bus driver interface */
162 static int t5_probe(device_t);
163 static device_method_t t5_methods[] = {
164 DEVMETHOD(device_probe, t5_probe),
165 DEVMETHOD(device_attach, t4_attach),
166 DEVMETHOD(device_detach, t4_detach),
168 DEVMETHOD(bus_child_location_str, t4_child_location_str),
170 DEVMETHOD(t4_is_main_ready, t4_ready),
171 DEVMETHOD(t4_read_port_device, t4_read_port_device),
175 static driver_t t5_driver = {
178 sizeof(struct adapter)
182 /* T5 port (cxl) interface */
183 static driver_t cxl_driver = {
186 sizeof(struct port_info)
189 /* T5 VI (vcxl) interface */
190 static driver_t vcxl_driver = {
193 sizeof(struct vi_info)
196 /* T6 bus driver interface */
197 static int t6_probe(device_t);
198 static device_method_t t6_methods[] = {
199 DEVMETHOD(device_probe, t6_probe),
200 DEVMETHOD(device_attach, t4_attach),
201 DEVMETHOD(device_detach, t4_detach),
203 DEVMETHOD(bus_child_location_str, t4_child_location_str),
205 DEVMETHOD(t4_is_main_ready, t4_ready),
206 DEVMETHOD(t4_read_port_device, t4_read_port_device),
210 static driver_t t6_driver = {
213 sizeof(struct adapter)
217 /* T6 port (cc) interface */
218 static driver_t cc_driver = {
221 sizeof(struct port_info)
224 /* T6 VI (vcc) interface */
225 static driver_t vcc_driver = {
228 sizeof(struct vi_info)
231 /* ifnet interface */
232 static void cxgbe_init(void *);
233 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
234 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
235 static void cxgbe_qflush(struct ifnet *);
236 #if defined(KERN_TLS) || defined(RATELIMIT)
237 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
238 struct m_snd_tag **);
239 static int cxgbe_snd_tag_modify(struct m_snd_tag *,
240 union if_snd_tag_modify_params *);
241 static int cxgbe_snd_tag_query(struct m_snd_tag *,
242 union if_snd_tag_query_params *);
243 static void cxgbe_snd_tag_free(struct m_snd_tag *);
246 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
249 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
250 * then ADAPTER_LOCK, then t4_uld_list_lock.
252 static struct sx t4_list_lock;
253 SLIST_HEAD(, adapter) t4_list;
255 static struct sx t4_uld_list_lock;
256 SLIST_HEAD(, uld_info) t4_uld_list;
260 * Tunables. See tweak_tunables() too.
262 * Each tunable is set to a default value here if it's known at compile-time.
263 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
264 * provide a reasonable default (upto n) when the driver is loaded.
266 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
267 * T5 are under hw.cxl.
269 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
270 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
271 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
274 * Number of queues for tx and rx, NIC and offload.
278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
279 "Number of TX queues per port");
280 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
284 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
285 "Number of RX queues per port");
286 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
289 static int t4_ntxq_vi = -NTXQ_VI;
290 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
291 "Number of TX queues per VI");
294 static int t4_nrxq_vi = -NRXQ_VI;
295 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
296 "Number of RX queues per VI");
298 static int t4_rsrv_noflowq = 0;
299 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
300 0, "Reserve TX queue 0 of each VI for non-flowid packets");
302 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
304 static int t4_nofldtxq = -NOFLDTXQ;
305 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
306 "Number of offload TX queues per port");
309 static int t4_nofldrxq = -NOFLDRXQ;
310 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
311 "Number of offload RX queues per port");
313 #define NOFLDTXQ_VI 1
314 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
315 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
316 "Number of offload TX queues per VI");
318 #define NOFLDRXQ_VI 1
319 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
320 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
321 "Number of offload RX queues per VI");
323 #define TMR_IDX_OFLD 1
324 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
325 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
326 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
328 #define PKTC_IDX_OFLD (-1)
329 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
330 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
331 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
333 /* 0 means chip/fw default, non-zero number is value in microseconds */
334 static u_long t4_toe_keepalive_idle = 0;
335 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
336 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
338 /* 0 means chip/fw default, non-zero number is value in microseconds */
339 static u_long t4_toe_keepalive_interval = 0;
340 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
341 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
343 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
344 static int t4_toe_keepalive_count = 0;
345 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
346 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
348 /* 0 means chip/fw default, non-zero number is value in microseconds */
349 static u_long t4_toe_rexmt_min = 0;
350 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
351 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
353 /* 0 means chip/fw default, non-zero number is value in microseconds */
354 static u_long t4_toe_rexmt_max = 0;
355 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
356 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
358 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
359 static int t4_toe_rexmt_count = 0;
360 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
361 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
363 /* -1 means chip/fw default, other values are raw backoff values to use */
364 static int t4_toe_rexmt_backoff[16] = {
365 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
367 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
368 "cxgbe(4) TOE retransmit backoff values");
369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
370 &t4_toe_rexmt_backoff[0], 0, "");
371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
372 &t4_toe_rexmt_backoff[1], 0, "");
373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_backoff[2], 0, "");
375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_backoff[3], 0, "");
377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
378 &t4_toe_rexmt_backoff[4], 0, "");
379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
380 &t4_toe_rexmt_backoff[5], 0, "");
381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
382 &t4_toe_rexmt_backoff[6], 0, "");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[7], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[8], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[9], 0, "");
389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
390 &t4_toe_rexmt_backoff[10], 0, "");
391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
392 &t4_toe_rexmt_backoff[11], 0, "");
393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
394 &t4_toe_rexmt_backoff[12], 0, "");
395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
396 &t4_toe_rexmt_backoff[13], 0, "");
397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
398 &t4_toe_rexmt_backoff[14], 0, "");
399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
400 &t4_toe_rexmt_backoff[15], 0, "");
404 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */
405 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */
406 static int t4_native_netmap = NN_EXTRA_VI;
407 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
408 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs");
411 static int t4_nnmtxq = -NNMTXQ;
412 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
413 "Number of netmap TX queues");
416 static int t4_nnmrxq = -NNMRXQ;
417 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
418 "Number of netmap RX queues");
421 static int t4_nnmtxq_vi = -NNMTXQ_VI;
422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
423 "Number of netmap TX queues per VI");
426 static int t4_nnmrxq_vi = -NNMRXQ_VI;
427 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
428 "Number of netmap RX queues per VI");
432 * Holdoff parameters for ports.
435 int t4_tmr_idx = TMR_IDX;
436 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
437 0, "Holdoff timer index");
438 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
440 #define PKTC_IDX (-1)
441 int t4_pktc_idx = PKTC_IDX;
442 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
443 0, "Holdoff packet counter index");
444 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
447 * Size (# of entries) of each tx and rx queue.
449 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
450 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
451 "Number of descriptors in each TX queue");
453 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
454 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
455 "Number of descriptors in each RX queue");
458 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
460 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
461 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
462 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
465 * Configuration file. All the _CF names here are special.
467 #define DEFAULT_CF "default"
468 #define BUILTIN_CF "built-in"
469 #define FLASH_CF "flash"
470 #define UWIRE_CF "uwire"
471 #define FPGA_CF "fpga"
472 static char t4_cfg_file[32] = DEFAULT_CF;
473 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
474 sizeof(t4_cfg_file), "Firmware configuration file");
477 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
478 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
479 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
480 * mark or when signalled to do so, 0 to never emit PAUSE.
481 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
482 * negotiated settings will override rx_pause/tx_pause.
483 * Otherwise rx_pause/tx_pause are applied forcibly.
485 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
486 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
487 &t4_pause_settings, 0,
488 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
491 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
492 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
495 static int t4_fec = -1;
496 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
497 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
500 * Link autonegotiation.
501 * -1 to run with the firmware default.
505 static int t4_autoneg = -1;
506 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
507 "Link autonegotiation");
510 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
511 * encouraged respectively). '-n' is the same as 'n' except the firmware
512 * version used in the checks is read from the firmware bundled with the driver.
514 static int t4_fw_install = 1;
515 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
516 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
519 * ASIC features that will be used. Disable the ones you don't want so that the
520 * chip resources aren't wasted on features that will not be used.
522 static int t4_nbmcaps_allowed = 0;
523 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
524 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
526 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
527 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
528 &t4_linkcaps_allowed, 0, "Default link capabilities");
530 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
531 FW_CAPS_CONFIG_SWITCH_EGRESS;
532 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
533 &t4_switchcaps_allowed, 0, "Default switch capabilities");
536 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
537 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
539 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
540 FW_CAPS_CONFIG_NIC_HASHFILTER;
542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
543 &t4_niccaps_allowed, 0, "Default NIC capabilities");
545 static int t4_toecaps_allowed = -1;
546 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
547 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
549 static int t4_rdmacaps_allowed = -1;
550 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
551 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
553 static int t4_cryptocaps_allowed = -1;
554 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
555 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
557 static int t4_iscsicaps_allowed = -1;
558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
559 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
561 static int t4_fcoecaps_allowed = 0;
562 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
563 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
565 static int t5_write_combine = 0;
566 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
567 0, "Use WC instead of UC for BAR2");
569 static int t4_num_vis = 1;
570 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
571 "Number of VIs per port");
574 * PCIe Relaxed Ordering.
575 * -1: driver should figure out a good value.
580 static int pcie_relaxed_ordering = -1;
581 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
582 &pcie_relaxed_ordering, 0,
583 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
585 static int t4_panic_on_fatal_err = 0;
586 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
587 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
593 static int t4_cop_managed_offloading = 0;
594 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
595 &t4_cop_managed_offloading, 0,
596 "COP (Connection Offload Policy) controls all TOE offload");
601 * This enables KERN_TLS for all adapters if set.
603 static int t4_kern_tls = 0;
604 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
605 "Enable KERN_TLS mode for all supported adapters");
607 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD, 0,
608 "cxgbe(4) KERN_TLS parameters");
610 static int t4_tls_inline_keys = 0;
611 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
612 &t4_tls_inline_keys, 0,
613 "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
616 static int t4_tls_combo_wrs = 0;
617 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
618 0, "Attempt to combine TCB field updates with TLS record work requests.");
621 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
622 static int vi_mac_funcs[] = {
626 FW_VI_FUNC_OPENISCSI,
632 struct intrs_and_queues {
633 uint16_t intr_type; /* INTx, MSI, or MSI-X */
634 uint16_t num_vis; /* number of VIs for each port */
635 uint16_t nirq; /* Total # of vectors */
636 uint16_t ntxq; /* # of NIC txq's for each port */
637 uint16_t nrxq; /* # of NIC rxq's for each port */
638 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
639 uint16_t nofldrxq; /* # of TOE rxq's for each port */
640 uint16_t nnmtxq; /* # of netmap txq's */
641 uint16_t nnmrxq; /* # of netmap rxq's */
643 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
644 uint16_t ntxq_vi; /* # of NIC txq's */
645 uint16_t nrxq_vi; /* # of NIC rxq's */
646 uint16_t nofldtxq_vi; /* # of TOE txq's */
647 uint16_t nofldrxq_vi; /* # of TOE rxq's */
648 uint16_t nnmtxq_vi; /* # of netmap txq's */
649 uint16_t nnmrxq_vi; /* # of netmap rxq's */
652 static void setup_memwin(struct adapter *);
653 static void position_memwin(struct adapter *, int, uint32_t);
654 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
655 static int fwmtype_to_hwmtype(int);
656 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
658 static int fixup_devlog_params(struct adapter *);
659 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
660 static int contact_firmware(struct adapter *);
661 static int partition_resources(struct adapter *);
662 static int get_params__pre_init(struct adapter *);
663 static int set_params__pre_init(struct adapter *);
664 static int get_params__post_init(struct adapter *);
665 static int set_params__post_init(struct adapter *);
666 static void t4_set_desc(struct adapter *);
667 static bool fixed_ifmedia(struct port_info *);
668 static void build_medialist(struct port_info *);
669 static void init_link_config(struct port_info *);
670 static int fixup_link_config(struct port_info *);
671 static int apply_link_config(struct port_info *);
672 static int cxgbe_init_synchronized(struct vi_info *);
673 static int cxgbe_uninit_synchronized(struct vi_info *);
674 static void quiesce_txq(struct adapter *, struct sge_txq *);
675 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
676 static void quiesce_iq(struct adapter *, struct sge_iq *);
677 static void quiesce_fl(struct adapter *, struct sge_fl *);
678 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
679 driver_intr_t *, void *, char *);
680 static int t4_free_irq(struct adapter *, struct irq *);
681 static void t4_init_atid_table(struct adapter *);
682 static void t4_free_atid_table(struct adapter *);
683 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
684 static void vi_refresh_stats(struct adapter *, struct vi_info *);
685 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
686 static void cxgbe_tick(void *);
687 static void cxgbe_sysctls(struct port_info *);
688 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
689 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
690 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
691 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
692 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
693 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
694 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
695 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
696 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
697 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
698 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
699 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
700 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
701 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
702 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
703 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
704 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
705 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
706 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
707 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
708 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
709 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
710 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
711 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
712 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
713 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
714 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
715 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
716 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
717 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
718 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
719 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
720 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
721 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
722 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
723 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
724 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
725 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
726 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
727 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
728 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
729 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
730 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
731 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
732 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
733 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
735 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
736 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
737 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
738 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
739 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
740 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
741 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
742 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
744 static int get_sge_context(struct adapter *, struct t4_sge_context *);
745 static int load_fw(struct adapter *, struct t4_data *);
746 static int load_cfg(struct adapter *, struct t4_data *);
747 static int load_boot(struct adapter *, struct t4_bootrom *);
748 static int load_bootcfg(struct adapter *, struct t4_data *);
749 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
750 static void free_offload_policy(struct t4_offload_policy *);
751 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
752 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
753 static int read_i2c(struct adapter *, struct t4_i2c_data *);
754 static int clear_stats(struct adapter *, u_int);
756 static int toe_capability(struct vi_info *, int);
758 static int mod_event(module_t, int, void *);
759 static int notify_siblings(device_t, int);
765 {0xa000, "Chelsio Terminator 4 FPGA"},
766 {0x4400, "Chelsio T440-dbg"},
767 {0x4401, "Chelsio T420-CR"},
768 {0x4402, "Chelsio T422-CR"},
769 {0x4403, "Chelsio T440-CR"},
770 {0x4404, "Chelsio T420-BCH"},
771 {0x4405, "Chelsio T440-BCH"},
772 {0x4406, "Chelsio T440-CH"},
773 {0x4407, "Chelsio T420-SO"},
774 {0x4408, "Chelsio T420-CX"},
775 {0x4409, "Chelsio T420-BT"},
776 {0x440a, "Chelsio T404-BT"},
777 {0x440e, "Chelsio T440-LP-CR"},
779 {0xb000, "Chelsio Terminator 5 FPGA"},
780 {0x5400, "Chelsio T580-dbg"},
781 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
782 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
783 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
784 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
785 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
786 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
787 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
788 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
789 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
790 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
791 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
792 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
793 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
794 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
795 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
796 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
797 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
800 {0x5483, "Custom T540-CR"},
801 {0x5484, "Custom T540-BT"},
803 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
804 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
805 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
806 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
807 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
808 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
809 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
810 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
811 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
812 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
813 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
814 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
815 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
816 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
817 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
818 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
821 {0x6480, "Custom T6225-CR"},
822 {0x6481, "Custom T62100-CR"},
823 {0x6482, "Custom T6225-CR"},
824 {0x6483, "Custom T62100-CR"},
825 {0x6484, "Custom T64100-CR"},
826 {0x6485, "Custom T6240-SO"},
827 {0x6486, "Custom T6225-SO-CR"},
828 {0x6487, "Custom T6225-CR"},
833 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
834 * be exactly the same for both rxq and ofld_rxq.
836 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
837 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
839 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
842 t4_probe(device_t dev)
845 uint16_t v = pci_get_vendor(dev);
846 uint16_t d = pci_get_device(dev);
847 uint8_t f = pci_get_function(dev);
849 if (v != PCI_VENDOR_ID_CHELSIO)
852 /* Attach only to PF0 of the FPGA */
853 if (d == 0xa000 && f != 0)
856 for (i = 0; i < nitems(t4_pciids); i++) {
857 if (d == t4_pciids[i].device) {
858 device_set_desc(dev, t4_pciids[i].desc);
859 return (BUS_PROBE_DEFAULT);
867 t5_probe(device_t dev)
870 uint16_t v = pci_get_vendor(dev);
871 uint16_t d = pci_get_device(dev);
872 uint8_t f = pci_get_function(dev);
874 if (v != PCI_VENDOR_ID_CHELSIO)
877 /* Attach only to PF0 of the FPGA */
878 if (d == 0xb000 && f != 0)
881 for (i = 0; i < nitems(t5_pciids); i++) {
882 if (d == t5_pciids[i].device) {
883 device_set_desc(dev, t5_pciids[i].desc);
884 return (BUS_PROBE_DEFAULT);
892 t6_probe(device_t dev)
895 uint16_t v = pci_get_vendor(dev);
896 uint16_t d = pci_get_device(dev);
898 if (v != PCI_VENDOR_ID_CHELSIO)
901 for (i = 0; i < nitems(t6_pciids); i++) {
902 if (d == t6_pciids[i].device) {
903 device_set_desc(dev, t6_pciids[i].desc);
904 return (BUS_PROBE_DEFAULT);
912 t5_attribute_workaround(device_t dev)
918 * The T5 chips do not properly echo the No Snoop and Relaxed
919 * Ordering attributes when replying to a TLP from a Root
920 * Port. As a workaround, find the parent Root Port and
921 * disable No Snoop and Relaxed Ordering. Note that this
922 * affects all devices under this root port.
924 root_port = pci_find_pcie_root_port(dev);
925 if (root_port == NULL) {
926 device_printf(dev, "Unable to find parent root port\n");
930 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
931 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
932 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
934 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
935 device_get_nameunit(root_port));
938 static const struct devnames devnames[] = {
940 .nexus_name = "t4nex",
941 .ifnet_name = "cxgbe",
942 .vi_ifnet_name = "vcxgbe",
943 .pf03_drv_name = "t4iov",
944 .vf_nexus_name = "t4vf",
945 .vf_ifnet_name = "cxgbev"
947 .nexus_name = "t5nex",
949 .vi_ifnet_name = "vcxl",
950 .pf03_drv_name = "t5iov",
951 .vf_nexus_name = "t5vf",
952 .vf_ifnet_name = "cxlv"
954 .nexus_name = "t6nex",
956 .vi_ifnet_name = "vcc",
957 .pf03_drv_name = "t6iov",
958 .vf_nexus_name = "t6vf",
959 .vf_ifnet_name = "ccv"
964 t4_init_devnames(struct adapter *sc)
969 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
970 sc->names = &devnames[id - CHELSIO_T4];
972 device_printf(sc->dev, "chip id %d is not supported.\n", id);
978 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
980 const char *parent, *name;
985 parent = device_get_nameunit(sc->dev);
986 name = sc->names->ifnet_name;
987 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
988 if (resource_long_value(name, unit, "port", &value) == 0 &&
989 value == pi->port_id)
996 t4_attach(device_t dev)
999 int rc = 0, i, j, rqidx, tqidx, nports;
1000 struct make_dev_args mda;
1001 struct intrs_and_queues iaq;
1004 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1011 int nm_rqidx, nm_tqidx;
1015 sc = device_get_softc(dev);
1017 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1019 if ((pci_get_device(dev) & 0xff00) == 0x5400)
1020 t5_attribute_workaround(dev);
1021 pci_enable_busmaster(dev);
1022 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1025 pci_set_max_read_req(dev, 4096);
1026 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1027 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1028 if (pcie_relaxed_ordering == 0 &&
1029 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1030 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1031 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1032 } else if (pcie_relaxed_ordering == 1 &&
1033 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1034 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1035 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1039 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1040 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1042 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1043 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1044 device_get_nameunit(dev));
1046 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1047 device_get_nameunit(dev));
1048 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1051 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1052 TAILQ_INIT(&sc->sfl);
1053 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1055 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1058 rw_init(&sc->policy_lock, "connection offload policy");
1060 callout_init(&sc->ktls_tick, 1);
1062 rc = t4_map_bars_0_and_4(sc);
1064 goto done; /* error message displayed already */
1066 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1068 /* Prepare the adapter for operation. */
1069 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1070 rc = -t4_prep_adapter(sc, buf);
1073 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1078 * This is the real PF# to which we're attaching. Works from within PCI
1079 * passthrough environments too, where pci_get_function() could return a
1080 * different PF# depending on the passthrough configuration. We need to
1081 * use the real PF# in all our communication with the firmware.
1083 j = t4_read_reg(sc, A_PL_WHOAMI);
1084 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1087 t4_init_devnames(sc);
1088 if (sc->names == NULL) {
1090 goto done; /* error message displayed already */
1094 * Do this really early, with the memory windows set up even before the
1095 * character device. The userland tool's register i/o and mem read
1096 * will work even in "recovery mode".
1099 if (t4_init_devlog_params(sc, 0) == 0)
1100 fixup_devlog_params(sc);
1101 make_dev_args_init(&mda);
1102 mda.mda_devsw = &t4_cdevsw;
1103 mda.mda_uid = UID_ROOT;
1104 mda.mda_gid = GID_WHEEL;
1105 mda.mda_mode = 0600;
1106 mda.mda_si_drv1 = sc;
1107 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1109 device_printf(dev, "failed to create nexus char device: %d.\n",
1112 /* Go no further if recovery mode has been requested. */
1113 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1114 device_printf(dev, "recovery mode.\n");
1118 #if defined(__i386__)
1119 if ((cpu_feature & CPUID_CX8) == 0) {
1120 device_printf(dev, "64 bit atomics not available.\n");
1126 /* Contact the firmware and try to become the master driver. */
1127 rc = contact_firmware(sc);
1129 goto done; /* error message displayed already */
1130 MPASS(sc->flags & FW_OK);
1132 rc = get_params__pre_init(sc);
1134 goto done; /* error message displayed already */
1136 if (sc->flags & MASTER_PF) {
1137 rc = partition_resources(sc);
1139 goto done; /* error message displayed already */
1143 rc = get_params__post_init(sc);
1145 goto done; /* error message displayed already */
1147 rc = set_params__post_init(sc);
1149 goto done; /* error message displayed already */
1151 rc = t4_map_bar_2(sc);
1153 goto done; /* error message displayed already */
1155 rc = t4_create_dma_tag(sc);
1157 goto done; /* error message displayed already */
1160 * First pass over all the ports - allocate VIs and initialize some
1161 * basic parameters like mac address, port type, etc.
1163 for_each_port(sc, i) {
1164 struct port_info *pi;
1166 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1169 /* These must be set before t4_port_init */
1173 * XXX: vi[0] is special so we can't delay this allocation until
1174 * pi->nvi's final value is known.
1176 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1180 * Allocate the "main" VI and initialize parameters
1183 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1185 device_printf(dev, "unable to initialize port %d: %d\n",
1187 free(pi->vi, M_CXGBE);
1193 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1194 device_get_nameunit(dev), i);
1195 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1196 sc->chan_map[pi->tx_chan] = i;
1198 /* All VIs on this port share this media. */
1199 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1200 cxgbe_media_status);
1203 init_link_config(pi);
1204 fixup_link_config(pi);
1205 build_medialist(pi);
1206 if (fixed_ifmedia(pi))
1207 pi->flags |= FIXED_IFMEDIA;
1210 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1211 t4_ifnet_unit(sc, pi));
1212 if (pi->dev == NULL) {
1214 "failed to add device for port %d.\n", i);
1218 pi->vi[0].dev = pi->dev;
1219 device_set_softc(pi->dev, pi);
1223 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1225 nports = sc->params.nports;
1226 rc = cfg_itype_and_nqueues(sc, &iaq);
1228 goto done; /* error message displayed already */
1230 num_vis = iaq.num_vis;
1231 sc->intr_type = iaq.intr_type;
1232 sc->intr_count = iaq.nirq;
1235 s->nrxq = nports * iaq.nrxq;
1236 s->ntxq = nports * iaq.ntxq;
1238 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1239 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1241 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1242 s->neq += nports; /* ctrl queues: 1 per port */
1243 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1244 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1245 if (is_offload(sc) || is_ethoffload(sc)) {
1246 s->nofldtxq = nports * iaq.nofldtxq;
1248 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1249 s->neq += s->nofldtxq;
1251 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1252 M_CXGBE, M_ZERO | M_WAITOK);
1256 if (is_offload(sc)) {
1257 s->nofldrxq = nports * iaq.nofldrxq;
1259 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1260 s->neq += s->nofldrxq; /* free list */
1261 s->niq += s->nofldrxq;
1263 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1264 M_CXGBE, M_ZERO | M_WAITOK);
1270 if (t4_native_netmap & NN_MAIN_VI) {
1271 s->nnmrxq += nports * iaq.nnmrxq;
1272 s->nnmtxq += nports * iaq.nnmtxq;
1274 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1275 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1276 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1278 s->neq += s->nnmtxq + s->nnmrxq;
1279 s->niq += s->nnmrxq;
1281 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1282 M_CXGBE, M_ZERO | M_WAITOK);
1283 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1284 M_CXGBE, M_ZERO | M_WAITOK);
1287 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1289 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1291 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1293 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1295 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1298 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1301 t4_init_l2t(sc, M_WAITOK);
1302 t4_init_smt(sc, M_WAITOK);
1303 t4_init_tx_sched(sc);
1304 t4_init_atid_table(sc);
1306 t4_init_etid_table(sc);
1309 t4_init_clip_table(sc);
1311 if (sc->vres.key.size != 0)
1312 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1313 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1316 * Second pass over the ports. This time we know the number of rx and
1317 * tx queues that each port should get.
1320 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1327 nm_rqidx = nm_tqidx = 0;
1329 for_each_port(sc, i) {
1330 struct port_info *pi = sc->port[i];
1337 for_each_vi(pi, j, vi) {
1339 vi->qsize_rxq = t4_qsize_rxq;
1340 vi->qsize_txq = t4_qsize_txq;
1342 vi->first_rxq = rqidx;
1343 vi->first_txq = tqidx;
1344 vi->tmr_idx = t4_tmr_idx;
1345 vi->pktc_idx = t4_pktc_idx;
1346 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1347 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1352 if (j == 0 && vi->ntxq > 1)
1353 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1355 vi->rsrv_noflowq = 0;
1357 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1358 vi->first_ofld_txq = ofld_tqidx;
1359 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1360 ofld_tqidx += vi->nofldtxq;
1363 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1364 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1365 vi->first_ofld_rxq = ofld_rqidx;
1366 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1368 ofld_rqidx += vi->nofldrxq;
1371 vi->first_nm_rxq = nm_rqidx;
1372 vi->first_nm_txq = nm_tqidx;
1374 vi->nnmrxq = iaq.nnmrxq;
1375 vi->nnmtxq = iaq.nnmtxq;
1377 vi->nnmrxq = iaq.nnmrxq_vi;
1378 vi->nnmtxq = iaq.nnmtxq_vi;
1380 nm_rqidx += vi->nnmrxq;
1381 nm_tqidx += vi->nnmtxq;
1386 rc = t4_setup_intr_handlers(sc);
1389 "failed to setup interrupt handlers: %d\n", rc);
1393 rc = bus_generic_probe(dev);
1395 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1400 * Ensure thread-safe mailbox access (in debug builds).
1402 * So far this was the only thread accessing the mailbox but various
1403 * ifnets and sysctls are about to be created and their handlers/ioctls
1404 * will access the mailbox from different threads.
1406 sc->flags |= CHK_MBOX_ACCESS;
1408 rc = bus_generic_attach(dev);
1411 "failed to attach all child ports: %d\n", rc);
1416 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1417 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1418 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1419 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1420 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1424 notify_siblings(dev, 0);
1427 if (rc != 0 && sc->cdev) {
1428 /* cdev was created and so cxgbetool works; recover that way. */
1430 "error during attach, adapter is now in recovery mode.\n");
1435 t4_detach_common(dev);
1443 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1446 struct port_info *pi;
1449 sc = device_get_softc(bus);
1451 for_each_port(sc, i) {
1453 if (pi != NULL && pi->dev == dev) {
1454 snprintf(buf, buflen, "port=%d", pi->port_id);
1462 t4_ready(device_t dev)
1466 sc = device_get_softc(dev);
1467 if (sc->flags & FW_OK)
1473 t4_read_port_device(device_t dev, int port, device_t *child)
1476 struct port_info *pi;
1478 sc = device_get_softc(dev);
1479 if (port < 0 || port >= MAX_NPORTS)
1481 pi = sc->port[port];
1482 if (pi == NULL || pi->dev == NULL)
1489 notify_siblings(device_t dev, int detaching)
1495 for (i = 0; i < PCI_FUNCMAX; i++) {
1496 if (i == pci_get_function(dev))
1498 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1499 pci_get_slot(dev), i);
1500 if (sibling == NULL || !device_is_attached(sibling))
1503 error = T4_DETACH_CHILD(sibling);
1505 (void)T4_ATTACH_CHILD(sibling);
1516 t4_detach(device_t dev)
1521 sc = device_get_softc(dev);
1523 rc = notify_siblings(dev, 1);
1526 "failed to detach sibling devices: %d\n", rc);
1530 return (t4_detach_common(dev));
1534 t4_detach_common(device_t dev)
1537 struct port_info *pi;
1540 sc = device_get_softc(dev);
1543 destroy_dev(sc->cdev);
1547 sx_xlock(&t4_list_lock);
1548 SLIST_REMOVE(&t4_list, sc, adapter, link);
1549 sx_xunlock(&t4_list_lock);
1551 sc->flags &= ~CHK_MBOX_ACCESS;
1552 if (sc->flags & FULL_INIT_DONE) {
1553 if (!(sc->flags & IS_VF))
1554 t4_intr_disable(sc);
1557 if (device_is_attached(dev)) {
1558 rc = bus_generic_detach(dev);
1561 "failed to detach child devices: %d\n", rc);
1566 for (i = 0; i < sc->intr_count; i++)
1567 t4_free_irq(sc, &sc->irq[i]);
1569 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1570 t4_free_tx_sched(sc);
1572 for (i = 0; i < MAX_NPORTS; i++) {
1575 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1577 device_delete_child(dev, pi->dev);
1579 mtx_destroy(&pi->pi_lock);
1580 free(pi->vi, M_CXGBE);
1585 device_delete_children(dev);
1587 if (sc->flags & FULL_INIT_DONE)
1588 adapter_full_uninit(sc);
1590 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1591 t4_fw_bye(sc, sc->mbox);
1593 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1594 pci_release_msi(dev);
1597 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1601 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1605 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1609 t4_free_l2t(sc->l2t);
1611 t4_free_smt(sc->smt);
1612 t4_free_atid_table(sc);
1614 t4_free_etid_table(sc);
1617 vmem_destroy(sc->key_map);
1619 t4_destroy_clip_table(sc);
1622 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1623 free(sc->sge.ofld_txq, M_CXGBE);
1626 free(sc->sge.ofld_rxq, M_CXGBE);
1629 free(sc->sge.nm_rxq, M_CXGBE);
1630 free(sc->sge.nm_txq, M_CXGBE);
1632 free(sc->irq, M_CXGBE);
1633 free(sc->sge.rxq, M_CXGBE);
1634 free(sc->sge.txq, M_CXGBE);
1635 free(sc->sge.ctrlq, M_CXGBE);
1636 free(sc->sge.iqmap, M_CXGBE);
1637 free(sc->sge.eqmap, M_CXGBE);
1638 free(sc->tids.ftid_tab, M_CXGBE);
1639 free(sc->tids.hpftid_tab, M_CXGBE);
1640 free_hftid_hash(&sc->tids);
1641 free(sc->tids.tid_tab, M_CXGBE);
1642 free(sc->tt.tls_rx_ports, M_CXGBE);
1643 t4_destroy_dma_tag(sc);
1645 callout_drain(&sc->ktls_tick);
1646 callout_drain(&sc->sfl_callout);
1647 if (mtx_initialized(&sc->tids.ftid_lock)) {
1648 mtx_destroy(&sc->tids.ftid_lock);
1649 cv_destroy(&sc->tids.ftid_cv);
1651 if (mtx_initialized(&sc->tids.atid_lock))
1652 mtx_destroy(&sc->tids.atid_lock);
1653 if (mtx_initialized(&sc->ifp_lock))
1654 mtx_destroy(&sc->ifp_lock);
1656 if (rw_initialized(&sc->policy_lock)) {
1657 rw_destroy(&sc->policy_lock);
1659 if (sc->policy != NULL)
1660 free_offload_policy(sc->policy);
1664 for (i = 0; i < NUM_MEMWIN; i++) {
1665 struct memwin *mw = &sc->memwin[i];
1667 if (rw_initialized(&mw->mw_lock))
1668 rw_destroy(&mw->mw_lock);
1671 mtx_destroy(&sc->sfl_lock);
1672 mtx_destroy(&sc->reg_lock);
1673 mtx_destroy(&sc->sc_lock);
1675 bzero(sc, sizeof(*sc));
1681 cxgbe_probe(device_t dev)
1684 struct port_info *pi = device_get_softc(dev);
1686 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1687 device_set_desc_copy(dev, buf);
1689 return (BUS_PROBE_DEFAULT);
1692 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1693 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1694 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1695 IFCAP_HWRXTSTMP | IFCAP_NOMAP)
1696 #define T4_CAP_ENABLE (T4_CAP)
1699 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1703 struct pfil_head_args pa;
1705 vi->xact_addr_filt = -1;
1706 callout_init(&vi->tick, 1);
1708 /* Allocate an ifnet and set it up */
1709 ifp = if_alloc_dev(IFT_ETHER, dev);
1711 device_printf(dev, "Cannot allocate ifnet\n");
1717 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1718 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1720 ifp->if_init = cxgbe_init;
1721 ifp->if_ioctl = cxgbe_ioctl;
1722 ifp->if_transmit = cxgbe_transmit;
1723 ifp->if_qflush = cxgbe_qflush;
1724 ifp->if_get_counter = cxgbe_get_counter;
1725 #if defined(KERN_TLS) || defined(RATELIMIT)
1726 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1727 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1728 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1729 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1732 ifp->if_ratelimit_query = cxgbe_ratelimit_query;
1735 ifp->if_capabilities = T4_CAP;
1736 ifp->if_capenable = T4_CAP_ENABLE;
1738 if (vi->nofldrxq != 0 && (vi->pi->adapter->flags & KERN_TLS_OK) == 0)
1739 ifp->if_capabilities |= IFCAP_TOE;
1742 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1743 ifp->if_capabilities |= IFCAP_TXRTLMT;
1744 ifp->if_capenable |= IFCAP_TXRTLMT;
1747 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1748 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1750 ifp->if_hw_tsomax = IP_MAXPACKET;
1751 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1753 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1754 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1756 ifp->if_hw_tsomaxsegsize = 65536;
1758 if (vi->pi->adapter->flags & KERN_TLS_OK) {
1759 ifp->if_capabilities |= IFCAP_TXTLS;
1760 ifp->if_capenable |= IFCAP_TXTLS;
1764 ether_ifattach(ifp, vi->hw_addr);
1766 if (vi->nnmrxq != 0)
1767 cxgbe_nm_attach(vi);
1769 sb = sbuf_new_auto();
1770 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1771 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1772 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1774 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1776 case IFCAP_TOE | IFCAP_TXRTLMT:
1777 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1780 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1785 if (ifp->if_capabilities & IFCAP_TOE)
1786 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1789 if (ifp->if_capabilities & IFCAP_NETMAP)
1790 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1791 vi->nnmtxq, vi->nnmrxq);
1794 device_printf(dev, "%s\n", sbuf_data(sb));
1799 pa.pa_version = PFIL_VERSION;
1800 pa.pa_flags = PFIL_IN;
1801 pa.pa_type = PFIL_TYPE_ETHERNET;
1802 pa.pa_headname = ifp->if_xname;
1803 vi->pfil = pfil_head_register(&pa);
1809 cxgbe_attach(device_t dev)
1811 struct port_info *pi = device_get_softc(dev);
1812 struct adapter *sc = pi->adapter;
1816 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1818 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1822 for_each_vi(pi, i, vi) {
1825 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1826 if (vi->dev == NULL) {
1827 device_printf(dev, "failed to add VI %d\n", i);
1830 device_set_softc(vi->dev, vi);
1835 bus_generic_attach(dev);
1841 cxgbe_vi_detach(struct vi_info *vi)
1843 struct ifnet *ifp = vi->ifp;
1845 if (vi->pfil != NULL) {
1846 pfil_head_unregister(vi->pfil);
1850 ether_ifdetach(ifp);
1852 /* Let detach proceed even if these fail. */
1854 if (ifp->if_capabilities & IFCAP_NETMAP)
1855 cxgbe_nm_detach(vi);
1857 cxgbe_uninit_synchronized(vi);
1858 callout_drain(&vi->tick);
1866 cxgbe_detach(device_t dev)
1868 struct port_info *pi = device_get_softc(dev);
1869 struct adapter *sc = pi->adapter;
1872 /* Detach the extra VIs first. */
1873 rc = bus_generic_detach(dev);
1876 device_delete_children(dev);
1878 doom_vi(sc, &pi->vi[0]);
1880 if (pi->flags & HAS_TRACEQ) {
1881 sc->traceq = -1; /* cloner should not create ifnet */
1882 t4_tracer_port_detach(sc);
1885 cxgbe_vi_detach(&pi->vi[0]);
1886 callout_drain(&pi->tick);
1887 ifmedia_removeall(&pi->media);
1889 end_synchronized_op(sc, 0);
1895 cxgbe_init(void *arg)
1897 struct vi_info *vi = arg;
1898 struct adapter *sc = vi->pi->adapter;
1900 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1902 cxgbe_init_synchronized(vi);
1903 end_synchronized_op(sc, 0);
1907 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1909 int rc = 0, mtu, flags;
1910 struct vi_info *vi = ifp->if_softc;
1911 struct port_info *pi = vi->pi;
1912 struct adapter *sc = pi->adapter;
1913 struct ifreq *ifr = (struct ifreq *)data;
1919 if (mtu < ETHERMIN || mtu > MAX_MTU)
1922 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1926 if (vi->flags & VI_INIT_DONE) {
1927 t4_update_fl_bufsize(ifp);
1928 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1929 rc = update_mac_settings(ifp, XGMAC_MTU);
1931 end_synchronized_op(sc, 0);
1935 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1939 if (ifp->if_flags & IFF_UP) {
1940 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1941 flags = vi->if_flags;
1942 if ((ifp->if_flags ^ flags) &
1943 (IFF_PROMISC | IFF_ALLMULTI)) {
1944 rc = update_mac_settings(ifp,
1945 XGMAC_PROMISC | XGMAC_ALLMULTI);
1948 rc = cxgbe_init_synchronized(vi);
1950 vi->if_flags = ifp->if_flags;
1951 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1952 rc = cxgbe_uninit_synchronized(vi);
1954 end_synchronized_op(sc, 0);
1959 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1962 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1963 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1964 end_synchronized_op(sc, 0);
1968 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1972 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1973 if (mask & IFCAP_TXCSUM) {
1974 ifp->if_capenable ^= IFCAP_TXCSUM;
1975 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1977 if (IFCAP_TSO4 & ifp->if_capenable &&
1978 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1979 ifp->if_capenable &= ~IFCAP_TSO4;
1981 "tso4 disabled due to -txcsum.\n");
1984 if (mask & IFCAP_TXCSUM_IPV6) {
1985 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1986 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1988 if (IFCAP_TSO6 & ifp->if_capenable &&
1989 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1990 ifp->if_capenable &= ~IFCAP_TSO6;
1992 "tso6 disabled due to -txcsum6.\n");
1995 if (mask & IFCAP_RXCSUM)
1996 ifp->if_capenable ^= IFCAP_RXCSUM;
1997 if (mask & IFCAP_RXCSUM_IPV6)
1998 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2001 * Note that we leave CSUM_TSO alone (it is always set). The
2002 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
2003 * sending a TSO request our way, so it's sufficient to toggle
2006 if (mask & IFCAP_TSO4) {
2007 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2008 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2009 if_printf(ifp, "enable txcsum first.\n");
2013 ifp->if_capenable ^= IFCAP_TSO4;
2015 if (mask & IFCAP_TSO6) {
2016 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2017 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2018 if_printf(ifp, "enable txcsum6 first.\n");
2022 ifp->if_capenable ^= IFCAP_TSO6;
2024 if (mask & IFCAP_LRO) {
2025 #if defined(INET) || defined(INET6)
2027 struct sge_rxq *rxq;
2029 ifp->if_capenable ^= IFCAP_LRO;
2030 for_each_rxq(vi, i, rxq) {
2031 if (ifp->if_capenable & IFCAP_LRO)
2032 rxq->iq.flags |= IQ_LRO_ENABLED;
2034 rxq->iq.flags &= ~IQ_LRO_ENABLED;
2039 if (mask & IFCAP_TOE) {
2040 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
2042 rc = toe_capability(vi, enable);
2046 ifp->if_capenable ^= mask;
2049 if (mask & IFCAP_VLAN_HWTAGGING) {
2050 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2051 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2052 rc = update_mac_settings(ifp, XGMAC_VLANEX);
2054 if (mask & IFCAP_VLAN_MTU) {
2055 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2057 /* Need to find out how to disable auto-mtu-inflation */
2059 if (mask & IFCAP_VLAN_HWTSO)
2060 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2061 if (mask & IFCAP_VLAN_HWCSUM)
2062 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2064 if (mask & IFCAP_TXRTLMT)
2065 ifp->if_capenable ^= IFCAP_TXRTLMT;
2067 if (mask & IFCAP_HWRXTSTMP) {
2069 struct sge_rxq *rxq;
2071 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2072 for_each_rxq(vi, i, rxq) {
2073 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
2074 rxq->iq.flags |= IQ_RX_TIMESTAMP;
2076 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
2079 if (mask & IFCAP_NOMAP)
2080 ifp->if_capenable ^= IFCAP_NOMAP;
2083 if (mask & IFCAP_TXTLS)
2084 ifp->if_capenable ^= (mask & IFCAP_TXTLS);
2087 #ifdef VLAN_CAPABILITIES
2088 VLAN_CAPABILITIES(ifp);
2091 end_synchronized_op(sc, 0);
2097 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
2101 struct ifi2creq i2c;
2103 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2106 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2110 if (i2c.len > sizeof(i2c.data)) {
2114 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2117 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2118 i2c.offset, i2c.len, &i2c.data[0]);
2119 end_synchronized_op(sc, 0);
2121 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2126 rc = ether_ioctl(ifp, cmd, data);
2133 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2135 struct vi_info *vi = ifp->if_softc;
2136 struct port_info *pi = vi->pi;
2137 struct adapter *sc = pi->adapter;
2138 struct sge_txq *txq;
2140 struct cxgbe_snd_tag *cst;
2146 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2147 #if defined(KERN_TLS) || defined(RATELIMIT)
2148 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
2149 MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
2152 if (__predict_false(pi->link_cfg.link_ok == false)) {
2157 rc = parse_pkt(sc, &m);
2158 if (__predict_false(rc != 0)) {
2159 MPASS(m == NULL); /* was freed already */
2160 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2164 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) {
2165 cst = mst_to_cst(m->m_pkthdr.snd_tag);
2166 if (cst->type == IF_SND_TAG_TYPE_RATE_LIMIT)
2167 return (ethofld_transmit(ifp, m));
2172 txq = &sc->sge.txq[vi->first_txq];
2173 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2174 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2178 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2179 if (__predict_false(rc != 0))
2186 cxgbe_qflush(struct ifnet *ifp)
2188 struct vi_info *vi = ifp->if_softc;
2189 struct sge_txq *txq;
2192 /* queues do not exist if !VI_INIT_DONE. */
2193 if (vi->flags & VI_INIT_DONE) {
2194 for_each_txq(vi, i, txq) {
2196 txq->eq.flags |= EQ_QFLUSH;
2198 while (!mp_ring_is_idle(txq->r)) {
2199 mp_ring_check_drainage(txq->r, 0);
2203 txq->eq.flags &= ~EQ_QFLUSH;
2211 vi_get_counter(struct ifnet *ifp, ift_counter c)
2213 struct vi_info *vi = ifp->if_softc;
2214 struct fw_vi_stats_vf *s = &vi->stats;
2216 vi_refresh_stats(vi->pi->adapter, vi);
2219 case IFCOUNTER_IPACKETS:
2220 return (s->rx_bcast_frames + s->rx_mcast_frames +
2221 s->rx_ucast_frames);
2222 case IFCOUNTER_IERRORS:
2223 return (s->rx_err_frames);
2224 case IFCOUNTER_OPACKETS:
2225 return (s->tx_bcast_frames + s->tx_mcast_frames +
2226 s->tx_ucast_frames + s->tx_offload_frames);
2227 case IFCOUNTER_OERRORS:
2228 return (s->tx_drop_frames);
2229 case IFCOUNTER_IBYTES:
2230 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2232 case IFCOUNTER_OBYTES:
2233 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2234 s->tx_ucast_bytes + s->tx_offload_bytes);
2235 case IFCOUNTER_IMCASTS:
2236 return (s->rx_mcast_frames);
2237 case IFCOUNTER_OMCASTS:
2238 return (s->tx_mcast_frames);
2239 case IFCOUNTER_OQDROPS: {
2243 if (vi->flags & VI_INIT_DONE) {
2245 struct sge_txq *txq;
2247 for_each_txq(vi, i, txq)
2248 drops += counter_u64_fetch(txq->r->drops);
2256 return (if_get_counter_default(ifp, c));
2261 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2263 struct vi_info *vi = ifp->if_softc;
2264 struct port_info *pi = vi->pi;
2265 struct adapter *sc = pi->adapter;
2266 struct port_stats *s = &pi->stats;
2268 if (pi->nvi > 1 || sc->flags & IS_VF)
2269 return (vi_get_counter(ifp, c));
2271 cxgbe_refresh_stats(sc, pi);
2274 case IFCOUNTER_IPACKETS:
2275 return (s->rx_frames);
2277 case IFCOUNTER_IERRORS:
2278 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2279 s->rx_fcs_err + s->rx_len_err);
2281 case IFCOUNTER_OPACKETS:
2282 return (s->tx_frames);
2284 case IFCOUNTER_OERRORS:
2285 return (s->tx_error_frames);
2287 case IFCOUNTER_IBYTES:
2288 return (s->rx_octets);
2290 case IFCOUNTER_OBYTES:
2291 return (s->tx_octets);
2293 case IFCOUNTER_IMCASTS:
2294 return (s->rx_mcast_frames);
2296 case IFCOUNTER_OMCASTS:
2297 return (s->tx_mcast_frames);
2299 case IFCOUNTER_IQDROPS:
2300 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2301 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2302 s->rx_trunc3 + pi->tnl_cong_drops);
2304 case IFCOUNTER_OQDROPS: {
2308 if (vi->flags & VI_INIT_DONE) {
2310 struct sge_txq *txq;
2312 for_each_txq(vi, i, txq)
2313 drops += counter_u64_fetch(txq->r->drops);
2321 return (if_get_counter_default(ifp, c));
2325 #if defined(KERN_TLS) || defined(RATELIMIT)
2327 cxgbe_snd_tag_init(struct cxgbe_snd_tag *cst, struct ifnet *ifp, int type)
2330 m_snd_tag_init(&cst->com, ifp);
2335 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
2336 struct m_snd_tag **pt)
2340 switch (params->hdr.type) {
2342 case IF_SND_TAG_TYPE_RATE_LIMIT:
2343 error = cxgbe_rate_tag_alloc(ifp, params, pt);
2347 case IF_SND_TAG_TYPE_TLS:
2348 error = cxgbe_tls_tag_alloc(ifp, params, pt);
2355 MPASS(mst_to_cst(*pt)->type == params->hdr.type);
2360 cxgbe_snd_tag_modify(struct m_snd_tag *mst,
2361 union if_snd_tag_modify_params *params)
2363 struct cxgbe_snd_tag *cst;
2365 cst = mst_to_cst(mst);
2366 switch (cst->type) {
2368 case IF_SND_TAG_TYPE_RATE_LIMIT:
2369 return (cxgbe_rate_tag_modify(mst, params));
2372 return (EOPNOTSUPP);
2377 cxgbe_snd_tag_query(struct m_snd_tag *mst,
2378 union if_snd_tag_query_params *params)
2380 struct cxgbe_snd_tag *cst;
2382 cst = mst_to_cst(mst);
2383 switch (cst->type) {
2385 case IF_SND_TAG_TYPE_RATE_LIMIT:
2386 return (cxgbe_rate_tag_query(mst, params));
2389 return (EOPNOTSUPP);
2394 cxgbe_snd_tag_free(struct m_snd_tag *mst)
2396 struct cxgbe_snd_tag *cst;
2398 cst = mst_to_cst(mst);
2399 switch (cst->type) {
2401 case IF_SND_TAG_TYPE_RATE_LIMIT:
2402 cxgbe_rate_tag_free(mst);
2406 case IF_SND_TAG_TYPE_TLS:
2407 cxgbe_tls_tag_free(mst);
2411 panic("shouldn't get here");
2417 * The kernel picks a media from the list we had provided but we still validate
2421 cxgbe_media_change(struct ifnet *ifp)
2423 struct vi_info *vi = ifp->if_softc;
2424 struct port_info *pi = vi->pi;
2425 struct ifmedia *ifm = &pi->media;
2426 struct link_config *lc = &pi->link_cfg;
2427 struct adapter *sc = pi->adapter;
2430 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2434 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2435 /* ifconfig .. media autoselect */
2436 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2437 rc = ENOTSUP; /* AN not supported by transceiver */
2440 lc->requested_aneg = AUTONEG_ENABLE;
2441 lc->requested_speed = 0;
2442 lc->requested_fc |= PAUSE_AUTONEG;
2444 lc->requested_aneg = AUTONEG_DISABLE;
2445 lc->requested_speed =
2446 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2447 lc->requested_fc = 0;
2448 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2449 lc->requested_fc |= PAUSE_RX;
2450 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2451 lc->requested_fc |= PAUSE_TX;
2453 if (pi->up_vis > 0) {
2454 fixup_link_config(pi);
2455 rc = apply_link_config(pi);
2459 end_synchronized_op(sc, 0);
2464 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2468 port_mword(struct port_info *pi, uint32_t speed)
2471 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2472 MPASS(powerof2(speed));
2474 switch(pi->port_type) {
2475 case FW_PORT_TYPE_BT_SGMII:
2476 case FW_PORT_TYPE_BT_XFI:
2477 case FW_PORT_TYPE_BT_XAUI:
2480 case FW_PORT_CAP32_SPEED_100M:
2482 case FW_PORT_CAP32_SPEED_1G:
2483 return (IFM_1000_T);
2484 case FW_PORT_CAP32_SPEED_10G:
2488 case FW_PORT_TYPE_KX4:
2489 if (speed == FW_PORT_CAP32_SPEED_10G)
2490 return (IFM_10G_KX4);
2492 case FW_PORT_TYPE_CX4:
2493 if (speed == FW_PORT_CAP32_SPEED_10G)
2494 return (IFM_10G_CX4);
2496 case FW_PORT_TYPE_KX:
2497 if (speed == FW_PORT_CAP32_SPEED_1G)
2498 return (IFM_1000_KX);
2500 case FW_PORT_TYPE_KR:
2501 case FW_PORT_TYPE_BP_AP:
2502 case FW_PORT_TYPE_BP4_AP:
2503 case FW_PORT_TYPE_BP40_BA:
2504 case FW_PORT_TYPE_KR4_100G:
2505 case FW_PORT_TYPE_KR_SFP28:
2506 case FW_PORT_TYPE_KR_XLAUI:
2508 case FW_PORT_CAP32_SPEED_1G:
2509 return (IFM_1000_KX);
2510 case FW_PORT_CAP32_SPEED_10G:
2511 return (IFM_10G_KR);
2512 case FW_PORT_CAP32_SPEED_25G:
2513 return (IFM_25G_KR);
2514 case FW_PORT_CAP32_SPEED_40G:
2515 return (IFM_40G_KR4);
2516 case FW_PORT_CAP32_SPEED_50G:
2517 return (IFM_50G_KR2);
2518 case FW_PORT_CAP32_SPEED_100G:
2519 return (IFM_100G_KR4);
2522 case FW_PORT_TYPE_FIBER_XFI:
2523 case FW_PORT_TYPE_FIBER_XAUI:
2524 case FW_PORT_TYPE_SFP:
2525 case FW_PORT_TYPE_QSFP_10G:
2526 case FW_PORT_TYPE_QSA:
2527 case FW_PORT_TYPE_QSFP:
2528 case FW_PORT_TYPE_CR4_QSFP:
2529 case FW_PORT_TYPE_CR_QSFP:
2530 case FW_PORT_TYPE_CR2_QSFP:
2531 case FW_PORT_TYPE_SFP28:
2532 /* Pluggable transceiver */
2533 switch (pi->mod_type) {
2534 case FW_PORT_MOD_TYPE_LR:
2536 case FW_PORT_CAP32_SPEED_1G:
2537 return (IFM_1000_LX);
2538 case FW_PORT_CAP32_SPEED_10G:
2539 return (IFM_10G_LR);
2540 case FW_PORT_CAP32_SPEED_25G:
2541 return (IFM_25G_LR);
2542 case FW_PORT_CAP32_SPEED_40G:
2543 return (IFM_40G_LR4);
2544 case FW_PORT_CAP32_SPEED_50G:
2545 return (IFM_50G_LR2);
2546 case FW_PORT_CAP32_SPEED_100G:
2547 return (IFM_100G_LR4);
2550 case FW_PORT_MOD_TYPE_SR:
2552 case FW_PORT_CAP32_SPEED_1G:
2553 return (IFM_1000_SX);
2554 case FW_PORT_CAP32_SPEED_10G:
2555 return (IFM_10G_SR);
2556 case FW_PORT_CAP32_SPEED_25G:
2557 return (IFM_25G_SR);
2558 case FW_PORT_CAP32_SPEED_40G:
2559 return (IFM_40G_SR4);
2560 case FW_PORT_CAP32_SPEED_50G:
2561 return (IFM_50G_SR2);
2562 case FW_PORT_CAP32_SPEED_100G:
2563 return (IFM_100G_SR4);
2566 case FW_PORT_MOD_TYPE_ER:
2567 if (speed == FW_PORT_CAP32_SPEED_10G)
2568 return (IFM_10G_ER);
2570 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2571 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2573 case FW_PORT_CAP32_SPEED_1G:
2574 return (IFM_1000_CX);
2575 case FW_PORT_CAP32_SPEED_10G:
2576 return (IFM_10G_TWINAX);
2577 case FW_PORT_CAP32_SPEED_25G:
2578 return (IFM_25G_CR);
2579 case FW_PORT_CAP32_SPEED_40G:
2580 return (IFM_40G_CR4);
2581 case FW_PORT_CAP32_SPEED_50G:
2582 return (IFM_50G_CR2);
2583 case FW_PORT_CAP32_SPEED_100G:
2584 return (IFM_100G_CR4);
2587 case FW_PORT_MOD_TYPE_LRM:
2588 if (speed == FW_PORT_CAP32_SPEED_10G)
2589 return (IFM_10G_LRM);
2591 case FW_PORT_MOD_TYPE_NA:
2592 MPASS(0); /* Not pluggable? */
2594 case FW_PORT_MOD_TYPE_ERROR:
2595 case FW_PORT_MOD_TYPE_UNKNOWN:
2596 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2598 case FW_PORT_MOD_TYPE_NONE:
2602 case FW_PORT_TYPE_NONE:
2606 return (IFM_UNKNOWN);
2610 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2612 struct vi_info *vi = ifp->if_softc;
2613 struct port_info *pi = vi->pi;
2614 struct adapter *sc = pi->adapter;
2615 struct link_config *lc = &pi->link_cfg;
2617 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2621 if (pi->up_vis == 0) {
2623 * If all the interfaces are administratively down the firmware
2624 * does not report transceiver changes. Refresh port info here
2625 * so that ifconfig displays accurate ifmedia at all times.
2626 * This is the only reason we have a synchronized op in this
2627 * function. Just PORT_LOCK would have been enough otherwise.
2629 t4_update_port_info(pi);
2630 build_medialist(pi);
2634 ifmr->ifm_status = IFM_AVALID;
2635 if (lc->link_ok == false)
2637 ifmr->ifm_status |= IFM_ACTIVE;
2640 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2641 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2642 if (lc->fc & PAUSE_RX)
2643 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2644 if (lc->fc & PAUSE_TX)
2645 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2646 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2649 end_synchronized_op(sc, 0);
2653 vcxgbe_probe(device_t dev)
2656 struct vi_info *vi = device_get_softc(dev);
2658 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2660 device_set_desc_copy(dev, buf);
2662 return (BUS_PROBE_DEFAULT);
2666 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2668 int func, index, rc;
2669 uint32_t param, val;
2671 ASSERT_SYNCHRONIZED_OP(sc);
2673 index = vi - pi->vi;
2674 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2675 KASSERT(index < nitems(vi_mac_funcs),
2676 ("%s: VI %s doesn't have a MAC func", __func__,
2677 device_get_nameunit(vi->dev)));
2678 func = vi_mac_funcs[index];
2679 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2680 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
2682 device_printf(vi->dev, "failed to allocate virtual interface %d"
2683 "for port %d: %d\n", index, pi->port_id, -rc);
2688 if (vi->rss_size == 1) {
2690 * This VI didn't get a slice of the RSS table. Reduce the
2691 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2692 * configuration file (nvi, rssnvi for this PF) if this is a
2695 device_printf(vi->dev, "RSS table not available.\n");
2696 vi->rss_base = 0xffff;
2701 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2702 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2703 V_FW_PARAMS_PARAM_YZ(vi->viid);
2704 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2706 vi->rss_base = 0xffff;
2708 MPASS((val >> 16) == vi->rss_size);
2709 vi->rss_base = val & 0xffff;
2716 vcxgbe_attach(device_t dev)
2719 struct port_info *pi;
2723 vi = device_get_softc(dev);
2727 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2730 rc = alloc_extra_vi(sc, pi, vi);
2731 end_synchronized_op(sc, 0);
2735 rc = cxgbe_vi_attach(dev, vi);
2737 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2744 vcxgbe_detach(device_t dev)
2749 vi = device_get_softc(dev);
2750 sc = vi->pi->adapter;
2754 cxgbe_vi_detach(vi);
2755 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2757 end_synchronized_op(sc, 0);
2762 static struct callout fatal_callout;
2765 delayed_panic(void *arg)
2767 struct adapter *sc = arg;
2769 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
2773 t4_fatal_err(struct adapter *sc, bool fw_error)
2776 t4_shutdown_adapter(sc);
2777 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2778 device_get_nameunit(sc->dev));
2780 ASSERT_SYNCHRONIZED_OP(sc);
2781 sc->flags |= ADAP_ERR;
2784 sc->flags |= ADAP_ERR;
2788 if (t4_panic_on_fatal_err) {
2789 log(LOG_ALERT, "%s: panic on fatal error after 30s",
2790 device_get_nameunit(sc->dev));
2791 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
2796 t4_add_adapter(struct adapter *sc)
2798 sx_xlock(&t4_list_lock);
2799 SLIST_INSERT_HEAD(&t4_list, sc, link);
2800 sx_xunlock(&t4_list_lock);
2804 t4_map_bars_0_and_4(struct adapter *sc)
2806 sc->regs_rid = PCIR_BAR(0);
2807 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2808 &sc->regs_rid, RF_ACTIVE);
2809 if (sc->regs_res == NULL) {
2810 device_printf(sc->dev, "cannot map registers.\n");
2813 sc->bt = rman_get_bustag(sc->regs_res);
2814 sc->bh = rman_get_bushandle(sc->regs_res);
2815 sc->mmio_len = rman_get_size(sc->regs_res);
2816 setbit(&sc->doorbells, DOORBELL_KDB);
2818 sc->msix_rid = PCIR_BAR(4);
2819 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2820 &sc->msix_rid, RF_ACTIVE);
2821 if (sc->msix_res == NULL) {
2822 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2830 t4_map_bar_2(struct adapter *sc)
2834 * T4: only iWARP driver uses the userspace doorbells. There is no need
2835 * to map it if RDMA is disabled.
2837 if (is_t4(sc) && sc->rdmacaps == 0)
2840 sc->udbs_rid = PCIR_BAR(2);
2841 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2842 &sc->udbs_rid, RF_ACTIVE);
2843 if (sc->udbs_res == NULL) {
2844 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2847 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2849 if (chip_id(sc) >= CHELSIO_T5) {
2850 setbit(&sc->doorbells, DOORBELL_UDB);
2851 #if defined(__i386__) || defined(__amd64__)
2852 if (t5_write_combine) {
2856 * Enable write combining on BAR2. This is the
2857 * userspace doorbell BAR and is split into 128B
2858 * (UDBS_SEG_SIZE) doorbell regions, each associated
2859 * with an egress queue. The first 64B has the doorbell
2860 * and the second 64B can be used to submit a tx work
2861 * request with an implicit doorbell.
2864 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2865 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2867 clrbit(&sc->doorbells, DOORBELL_UDB);
2868 setbit(&sc->doorbells, DOORBELL_WCWR);
2869 setbit(&sc->doorbells, DOORBELL_UDBWC);
2871 device_printf(sc->dev,
2872 "couldn't enable write combining: %d\n",
2876 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2877 t4_write_reg(sc, A_SGE_STAT_CFG,
2878 V_STATSOURCE_T5(7) | mode);
2882 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2887 struct memwin_init {
2892 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2893 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2894 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2895 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2898 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2899 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2900 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2901 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2905 setup_memwin(struct adapter *sc)
2907 const struct memwin_init *mw_init;
2914 * Read low 32b of bar0 indirectly via the hardware backdoor
2915 * mechanism. Works from within PCI passthrough environments
2916 * too, where rman_get_start() can return a different value. We
2917 * need to program the T4 memory window decoders with the actual
2918 * addresses that will be coming across the PCIe link.
2920 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2921 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2923 mw_init = &t4_memwin[0];
2925 /* T5+ use the relative offset inside the PCIe BAR */
2928 mw_init = &t5_memwin[0];
2931 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2932 rw_init(&mw->mw_lock, "memory window access");
2933 mw->mw_base = mw_init->base;
2934 mw->mw_aperture = mw_init->aperture;
2937 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2938 (mw->mw_base + bar0) | V_BIR(0) |
2939 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2940 rw_wlock(&mw->mw_lock);
2941 position_memwin(sc, i, 0);
2942 rw_wunlock(&mw->mw_lock);
2946 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2950 * Positions the memory window at the given address in the card's address space.
2951 * There are some alignment requirements and the actual position may be at an
2952 * address prior to the requested address. mw->mw_curpos always has the actual
2953 * position of the window.
2956 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2962 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2963 mw = &sc->memwin[idx];
2964 rw_assert(&mw->mw_lock, RA_WLOCKED);
2968 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2970 pf = V_PFNUM(sc->pf);
2971 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2973 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2974 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2975 t4_read_reg(sc, reg); /* flush */
2979 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2985 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2987 /* Memory can only be accessed in naturally aligned 4 byte units */
2988 if (addr & 3 || len & 3 || len <= 0)
2991 mw = &sc->memwin[idx];
2993 rw_rlock(&mw->mw_lock);
2994 mw_end = mw->mw_curpos + mw->mw_aperture;
2995 if (addr >= mw_end || addr < mw->mw_curpos) {
2996 /* Will need to reposition the window */
2997 if (!rw_try_upgrade(&mw->mw_lock)) {
2998 rw_runlock(&mw->mw_lock);
2999 rw_wlock(&mw->mw_lock);
3001 rw_assert(&mw->mw_lock, RA_WLOCKED);
3002 position_memwin(sc, idx, addr);
3003 rw_downgrade(&mw->mw_lock);
3004 mw_end = mw->mw_curpos + mw->mw_aperture;
3006 rw_assert(&mw->mw_lock, RA_RLOCKED);
3007 while (addr < mw_end && len > 0) {
3009 v = t4_read_reg(sc, mw->mw_base + addr -
3011 *val++ = le32toh(v);
3014 t4_write_reg(sc, mw->mw_base + addr -
3015 mw->mw_curpos, htole32(v));
3020 rw_runlock(&mw->mw_lock);
3027 t4_init_atid_table(struct adapter *sc)
3036 MPASS(t->atid_tab == NULL);
3038 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
3040 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
3041 t->afree = t->atid_tab;
3042 t->atids_in_use = 0;
3043 for (i = 1; i < t->natids; i++)
3044 t->atid_tab[i - 1].next = &t->atid_tab[i];
3045 t->atid_tab[t->natids - 1].next = NULL;
3049 t4_free_atid_table(struct adapter *sc)
3055 KASSERT(t->atids_in_use == 0,
3056 ("%s: %d atids still in use.", __func__, t->atids_in_use));
3058 if (mtx_initialized(&t->atid_lock))
3059 mtx_destroy(&t->atid_lock);
3060 free(t->atid_tab, M_CXGBE);
3065 alloc_atid(struct adapter *sc, void *ctx)
3067 struct tid_info *t = &sc->tids;
3070 mtx_lock(&t->atid_lock);
3072 union aopen_entry *p = t->afree;
3074 atid = p - t->atid_tab;
3075 MPASS(atid <= M_TID_TID);
3080 mtx_unlock(&t->atid_lock);
3085 lookup_atid(struct adapter *sc, int atid)
3087 struct tid_info *t = &sc->tids;
3089 return (t->atid_tab[atid].data);
3093 free_atid(struct adapter *sc, int atid)
3095 struct tid_info *t = &sc->tids;
3096 union aopen_entry *p = &t->atid_tab[atid];
3098 mtx_lock(&t->atid_lock);
3102 mtx_unlock(&t->atid_lock);
3106 queue_tid_release(struct adapter *sc, int tid)
3109 CXGBE_UNIMPLEMENTED("deferred tid release");
3113 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
3116 struct cpl_tid_release *req;
3118 wr = alloc_wrqe(sizeof(*req), ctrlq);
3120 queue_tid_release(sc, tid); /* defer */
3125 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
3131 t4_range_cmp(const void *a, const void *b)
3133 return ((const struct t4_range *)a)->start -
3134 ((const struct t4_range *)b)->start;
3138 * Verify that the memory range specified by the addr/len pair is valid within
3139 * the card's address space.
3142 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
3144 struct t4_range mem_ranges[4], *r, *next;
3145 uint32_t em, addr_len;
3146 int i, n, remaining;
3148 /* Memory can only be accessed in naturally aligned 4 byte units */
3149 if (addr & 3 || len & 3 || len == 0)
3152 /* Enabled memories */
3153 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3157 bzero(r, sizeof(mem_ranges));
3158 if (em & F_EDRAM0_ENABLE) {
3159 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3160 r->size = G_EDRAM0_SIZE(addr_len) << 20;
3162 r->start = G_EDRAM0_BASE(addr_len) << 20;
3163 if (addr >= r->start &&
3164 addr + len <= r->start + r->size)
3170 if (em & F_EDRAM1_ENABLE) {
3171 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3172 r->size = G_EDRAM1_SIZE(addr_len) << 20;
3174 r->start = G_EDRAM1_BASE(addr_len) << 20;
3175 if (addr >= r->start &&
3176 addr + len <= r->start + r->size)
3182 if (em & F_EXT_MEM_ENABLE) {
3183 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3184 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
3186 r->start = G_EXT_MEM_BASE(addr_len) << 20;
3187 if (addr >= r->start &&
3188 addr + len <= r->start + r->size)
3194 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
3195 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3196 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
3198 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
3199 if (addr >= r->start &&
3200 addr + len <= r->start + r->size)
3206 MPASS(n <= nitems(mem_ranges));
3209 /* Sort and merge the ranges. */
3210 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3212 /* Start from index 0 and examine the next n - 1 entries. */
3214 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3216 MPASS(r->size > 0); /* r is a valid entry. */
3218 MPASS(next->size > 0); /* and so is the next one. */
3220 while (r->start + r->size >= next->start) {
3221 /* Merge the next one into the current entry. */
3222 r->size = max(r->start + r->size,
3223 next->start + next->size) - r->start;
3224 n--; /* One fewer entry in total. */
3225 if (--remaining == 0)
3226 goto done; /* short circuit */
3229 if (next != r + 1) {
3231 * Some entries were merged into r and next
3232 * points to the first valid entry that couldn't
3235 MPASS(next->size > 0); /* must be valid */
3236 memcpy(r + 1, next, remaining * sizeof(*r));
3239 * This so that the foo->size assertion in the
3240 * next iteration of the loop do the right
3241 * thing for entries that were pulled up and are
3244 MPASS(n < nitems(mem_ranges));
3245 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3246 sizeof(struct t4_range));
3251 /* Done merging the ranges. */
3254 for (i = 0; i < n; i++, r++) {
3255 if (addr >= r->start &&
3256 addr + len <= r->start + r->size)
3265 fwmtype_to_hwmtype(int mtype)
3269 case FW_MEMTYPE_EDC0:
3271 case FW_MEMTYPE_EDC1:
3273 case FW_MEMTYPE_EXTMEM:
3275 case FW_MEMTYPE_EXTMEM1:
3278 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3283 * Verify that the memory range specified by the memtype/offset/len pair is
3284 * valid and lies entirely within the memtype specified. The global address of
3285 * the start of the range is returned in addr.
3288 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3291 uint32_t em, addr_len, maddr;
3293 /* Memory can only be accessed in naturally aligned 4 byte units */
3294 if (off & 3 || len & 3 || len == 0)
3297 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3298 switch (fwmtype_to_hwmtype(mtype)) {
3300 if (!(em & F_EDRAM0_ENABLE))
3302 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3303 maddr = G_EDRAM0_BASE(addr_len) << 20;
3306 if (!(em & F_EDRAM1_ENABLE))
3308 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3309 maddr = G_EDRAM1_BASE(addr_len) << 20;
3312 if (!(em & F_EXT_MEM_ENABLE))
3314 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3315 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3318 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3320 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3321 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3327 *addr = maddr + off; /* global address */
3328 return (validate_mem_range(sc, *addr, len));
3332 fixup_devlog_params(struct adapter *sc)
3334 struct devlog_params *dparams = &sc->params.devlog;
3337 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3338 dparams->size, &dparams->addr);
3344 update_nirq(struct intrs_and_queues *iaq, int nports)
3347 iaq->nirq = T4_EXTRA_INTR;
3348 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
3349 iaq->nirq += nports * iaq->nofldrxq;
3350 iaq->nirq += nports * (iaq->num_vis - 1) *
3351 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3352 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3356 * Adjust requirements to fit the number of interrupts available.
3359 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3363 const int nports = sc->params.nports;
3368 bzero(iaq, sizeof(*iaq));
3369 iaq->intr_type = itype;
3370 iaq->num_vis = t4_num_vis;
3371 iaq->ntxq = t4_ntxq;
3372 iaq->ntxq_vi = t4_ntxq_vi;
3373 iaq->nrxq = t4_nrxq;
3374 iaq->nrxq_vi = t4_nrxq_vi;
3375 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3376 if (is_offload(sc) || is_ethoffload(sc)) {
3377 iaq->nofldtxq = t4_nofldtxq;
3378 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3382 if (is_offload(sc)) {
3383 iaq->nofldrxq = t4_nofldrxq;
3384 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3388 if (t4_native_netmap & NN_MAIN_VI) {
3389 iaq->nnmtxq = t4_nnmtxq;
3390 iaq->nnmrxq = t4_nnmrxq;
3392 if (t4_native_netmap & NN_EXTRA_VI) {
3393 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3394 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3398 update_nirq(iaq, nports);
3399 if (iaq->nirq <= navail &&
3400 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3402 * This is the normal case -- there are enough interrupts for
3409 * If extra VIs have been configured try reducing their count and see if
3412 while (iaq->num_vis > 1) {
3414 update_nirq(iaq, nports);
3415 if (iaq->nirq <= navail &&
3416 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3417 device_printf(sc->dev, "virtual interfaces per port "
3418 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3419 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3420 "itype %d, navail %u, nirq %d.\n",
3421 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3422 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3423 itype, navail, iaq->nirq);
3429 * Extra VIs will not be created. Log a message if they were requested.
3431 MPASS(iaq->num_vis == 1);
3432 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3433 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3434 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3435 if (iaq->num_vis != t4_num_vis) {
3436 device_printf(sc->dev, "extra virtual interfaces disabled. "
3437 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3438 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3439 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3440 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3444 * Keep reducing the number of NIC rx queues to the next lower power of
3445 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3449 if (iaq->nrxq > 1) {
3452 } while (!powerof2(iaq->nrxq));
3453 if (iaq->nnmrxq > iaq->nrxq)
3454 iaq->nnmrxq = iaq->nrxq;
3456 if (iaq->nofldrxq > 1)
3457 iaq->nofldrxq >>= 1;
3459 old_nirq = iaq->nirq;
3460 update_nirq(iaq, nports);
3461 if (iaq->nirq <= navail &&
3462 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3463 device_printf(sc->dev, "running with reduced number of "
3464 "rx queues because of shortage of interrupts. "
3465 "nrxq=%u, nofldrxq=%u. "
3466 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3467 iaq->nofldrxq, itype, navail, iaq->nirq);
3470 } while (old_nirq != iaq->nirq);
3472 /* One interrupt for everything. Ugh. */
3473 device_printf(sc->dev, "running with minimal number of queues. "
3474 "itype %d, navail %u.\n", itype, navail);
3478 if (iaq->nofldrxq > 0) {
3485 MPASS(iaq->num_vis > 0);
3486 if (iaq->num_vis > 1) {
3487 MPASS(iaq->nrxq_vi > 0);
3488 MPASS(iaq->ntxq_vi > 0);
3490 MPASS(iaq->nirq > 0);
3491 MPASS(iaq->nrxq > 0);
3492 MPASS(iaq->ntxq > 0);
3493 if (itype == INTR_MSI) {
3494 MPASS(powerof2(iaq->nirq));
3499 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3501 int rc, itype, navail, nalloc;
3503 for (itype = INTR_MSIX; itype; itype >>= 1) {
3505 if ((itype & t4_intr_types) == 0)
3506 continue; /* not allowed */
3508 if (itype == INTR_MSIX)
3509 navail = pci_msix_count(sc->dev);
3510 else if (itype == INTR_MSI)
3511 navail = pci_msi_count(sc->dev);
3518 calculate_iaq(sc, iaq, itype, navail);
3521 if (itype == INTR_MSIX)
3522 rc = pci_alloc_msix(sc->dev, &nalloc);
3523 else if (itype == INTR_MSI)
3524 rc = pci_alloc_msi(sc->dev, &nalloc);
3526 if (rc == 0 && nalloc > 0) {
3527 if (nalloc == iaq->nirq)
3531 * Didn't get the number requested. Use whatever number
3532 * the kernel is willing to allocate.
3534 device_printf(sc->dev, "fewer vectors than requested, "
3535 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3536 itype, iaq->nirq, nalloc);
3537 pci_release_msi(sc->dev);
3542 device_printf(sc->dev,
3543 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3544 itype, rc, iaq->nirq, nalloc);
3547 device_printf(sc->dev,
3548 "failed to find a usable interrupt type. "
3549 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3550 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3555 #define FW_VERSION(chip) ( \
3556 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3557 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3558 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3559 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3560 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3562 /* Just enough of fw_hdr to cover all version info. */
3568 __be32 tp_microcode_ver;
3573 __u8 intfver_iscsipdu;
3575 __u8 intfver_fcoepdu;
3578 /* Spot check a couple of fields. */
3579 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3580 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3581 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3591 .kld_name = "t4fw_cfg",
3592 .fw_mod_name = "t4fw",
3594 .chip = FW_HDR_CHIP_T4,
3595 .fw_ver = htobe32(FW_VERSION(T4)),
3596 .intfver_nic = FW_INTFVER(T4, NIC),
3597 .intfver_vnic = FW_INTFVER(T4, VNIC),
3598 .intfver_ofld = FW_INTFVER(T4, OFLD),
3599 .intfver_ri = FW_INTFVER(T4, RI),
3600 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3601 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3602 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3603 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3607 .kld_name = "t5fw_cfg",
3608 .fw_mod_name = "t5fw",
3610 .chip = FW_HDR_CHIP_T5,
3611 .fw_ver = htobe32(FW_VERSION(T5)),
3612 .intfver_nic = FW_INTFVER(T5, NIC),
3613 .intfver_vnic = FW_INTFVER(T5, VNIC),
3614 .intfver_ofld = FW_INTFVER(T5, OFLD),
3615 .intfver_ri = FW_INTFVER(T5, RI),
3616 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3617 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3618 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3619 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3623 .kld_name = "t6fw_cfg",
3624 .fw_mod_name = "t6fw",
3626 .chip = FW_HDR_CHIP_T6,
3627 .fw_ver = htobe32(FW_VERSION(T6)),
3628 .intfver_nic = FW_INTFVER(T6, NIC),
3629 .intfver_vnic = FW_INTFVER(T6, VNIC),
3630 .intfver_ofld = FW_INTFVER(T6, OFLD),
3631 .intfver_ri = FW_INTFVER(T6, RI),
3632 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3633 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3634 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3635 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3640 static struct fw_info *
3641 find_fw_info(int chip)
3645 for (i = 0; i < nitems(fw_info); i++) {
3646 if (fw_info[i].chip == chip)
3647 return (&fw_info[i]);
3653 * Is the given firmware API compatible with the one the driver was compiled
3657 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3660 /* short circuit if it's the exact same firmware version */
3661 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3665 * XXX: Is this too conservative? Perhaps I should limit this to the
3666 * features that are supported in the driver.
3668 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3669 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3670 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3671 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3679 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3680 const struct firmware **fw)
3682 struct fw_info *fw_info;
3688 fw_info = find_fw_info(chip_id(sc));
3689 if (fw_info == NULL) {
3690 device_printf(sc->dev,
3691 "unable to look up firmware information for chip %d.\n",
3696 *dcfg = firmware_get(fw_info->kld_name);
3697 if (*dcfg != NULL) {
3699 *fw = firmware_get(fw_info->fw_mod_name);
3707 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3708 const struct firmware *fw)
3712 firmware_put(fw, FIRMWARE_UNLOAD);
3714 firmware_put(dcfg, FIRMWARE_UNLOAD);
3719 * 0 means no firmware install attempted.
3720 * ERESTART means a firmware install was attempted and was successful.
3721 * +ve errno means a firmware install was attempted but failed.
3724 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3725 const struct fw_h *drv_fw, const char *reason, int *already)
3727 const struct firmware *cfg, *fw;
3728 const uint32_t c = be32toh(card_fw->fw_ver);
3731 struct fw_h bundled_fw;
3732 bool load_attempted;
3735 load_attempted = false;
3736 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3738 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3739 if (t4_fw_install < 0) {
3740 rc = load_fw_module(sc, &cfg, &fw);
3741 if (rc != 0 || fw == NULL) {
3742 device_printf(sc->dev,
3743 "failed to load firmware module: %d. cfg %p, fw %p;"
3744 " will use compiled-in firmware version for"
3745 "hw.cxgbe.fw_install checks.\n",
3748 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3750 load_attempted = true;
3752 d = be32toh(bundled_fw.fw_ver);
3757 if ((sc->flags & FW_OK) == 0) {
3759 if (c == 0xffffffff) {
3768 if (!fw_compatible(card_fw, &bundled_fw)) {
3769 reason = "incompatible or unusable";
3774 reason = "older than the version bundled with this driver";
3778 if (fw_install == 2 && d != c) {
3779 reason = "different than the version bundled with this driver";
3783 /* No reason to do anything to the firmware already on the card. */
3792 if (fw_install == 0) {
3793 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3794 "but the driver is prohibited from installing a firmware "
3796 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3797 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3803 * We'll attempt to install a firmware. Load the module first (if it
3804 * hasn't been loaded already).
3806 if (!load_attempted) {
3807 rc = load_fw_module(sc, &cfg, &fw);
3808 if (rc != 0 || fw == NULL) {
3809 device_printf(sc->dev,
3810 "failed to load firmware module: %d. cfg %p, fw %p\n",
3816 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3817 "but the driver cannot take corrective action because it "
3818 "is unable to load the firmware module.\n",
3819 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3820 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3821 rc = sc->flags & FW_OK ? 0 : ENOENT;
3824 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3826 MPASS(t4_fw_install > 0);
3827 device_printf(sc->dev,
3828 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3829 "expecting (%u.%u.%u.%u) and will not be used.\n",
3830 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3831 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3832 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3833 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3834 rc = sc->flags & FW_OK ? 0 : EINVAL;
3838 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3839 "installing firmware %u.%u.%u.%u on card.\n",
3840 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3841 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3842 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3843 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3845 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3847 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3849 /* Installed successfully, update the cached header too. */
3851 memcpy(card_fw, fw->data, sizeof(*card_fw));
3854 unload_fw_module(sc, cfg, fw);
3860 * Establish contact with the firmware and attempt to become the master driver.
3862 * A firmware will be installed to the card if needed (if the driver is allowed
3866 contact_firmware(struct adapter *sc)
3868 int rc, already = 0;
3869 enum dev_state state;
3870 struct fw_info *fw_info;
3871 struct fw_hdr *card_fw; /* fw on the card */
3872 const struct fw_h *drv_fw;
3874 fw_info = find_fw_info(chip_id(sc));
3875 if (fw_info == NULL) {
3876 device_printf(sc->dev,
3877 "unable to look up firmware information for chip %d.\n",
3881 drv_fw = &fw_info->fw_h;
3883 /* Read the header of the firmware on the card */
3884 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3886 rc = -t4_get_fw_hdr(sc, card_fw);
3888 device_printf(sc->dev,
3889 "unable to read firmware header from card's flash: %d\n",
3894 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3901 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3902 if (rc < 0 || state == DEV_STATE_ERR) {
3904 device_printf(sc->dev,
3905 "failed to connect to the firmware: %d, %d. "
3906 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3908 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3909 "not responding properly to HELLO", &already) == ERESTART)
3914 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3915 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3918 sc->flags |= MASTER_PF;
3919 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3925 } else if (state == DEV_STATE_UNINIT) {
3927 * We didn't get to be the master so we definitely won't be
3928 * configuring the chip. It's a bug if someone else hasn't
3929 * configured it already.
3931 device_printf(sc->dev, "couldn't be master(%d), "
3932 "device not already initialized either(%d). "
3933 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3938 * Some other PF is the master and has configured the chip.
3939 * This is allowed but untested.
3941 device_printf(sc->dev, "PF%d is master, device state %d. "
3942 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3943 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3948 if (rc != 0 && sc->flags & FW_OK) {
3949 t4_fw_bye(sc, sc->mbox);
3950 sc->flags &= ~FW_OK;
3952 free(card_fw, M_CXGBE);
3957 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3958 uint32_t mtype, uint32_t moff)
3960 struct fw_info *fw_info;
3961 const struct firmware *dcfg, *rcfg = NULL;
3962 const uint32_t *cfdata;
3963 uint32_t cflen, addr;
3966 load_fw_module(sc, &dcfg, NULL);
3968 /* Card specific interpretation of "default". */
3969 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3970 if (pci_get_device(sc->dev) == 0x440a)
3971 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3973 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3976 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3978 device_printf(sc->dev,
3979 "KLD with default config is not available.\n");
3983 cfdata = dcfg->data;
3984 cflen = dcfg->datasize & ~3;
3988 fw_info = find_fw_info(chip_id(sc));
3989 if (fw_info == NULL) {
3990 device_printf(sc->dev,
3991 "unable to look up firmware information for chip %d.\n",
3996 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
3998 rcfg = firmware_get(s);
4000 device_printf(sc->dev,
4001 "unable to load module \"%s\" for configuration "
4002 "profile \"%s\".\n", s, cfg_file);
4006 cfdata = rcfg->data;
4007 cflen = rcfg->datasize & ~3;
4010 if (cflen > FLASH_CFG_MAX_SIZE) {
4011 device_printf(sc->dev,
4012 "config file too long (%d, max allowed is %d).\n",
4013 cflen, FLASH_CFG_MAX_SIZE);
4018 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
4020 device_printf(sc->dev,
4021 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
4022 __func__, mtype, moff, cflen, rc);
4026 write_via_memwin(sc, 2, addr, cfdata, cflen);
4029 firmware_put(rcfg, FIRMWARE_UNLOAD);
4030 unload_fw_module(sc, dcfg, NULL);
4034 struct caps_allowed {
4037 uint16_t switchcaps;
4041 uint16_t cryptocaps;
4046 #define FW_PARAM_DEV(param) \
4047 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4048 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4049 #define FW_PARAM_PFVF(param) \
4050 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4051 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
4054 * Provide a configuration profile to the firmware and have it initialize the
4055 * chip accordingly. This may involve uploading a configuration file to the
4059 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
4060 const struct caps_allowed *caps_allowed)
4063 struct fw_caps_config_cmd caps;
4064 uint32_t mtype, moff, finicsum, cfcsum, param, val;
4066 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
4068 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
4072 bzero(&caps, sizeof(caps));
4073 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4074 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4075 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
4078 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4079 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
4080 mtype = FW_MEMTYPE_FLASH;
4081 moff = t4_flash_cfg_addr(sc);
4082 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4083 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4084 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4088 * Ask the firmware where it wants us to upload the config file.
4090 param = FW_PARAM_DEV(CF);
4091 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4093 /* No support for config file? Shouldn't happen. */
4094 device_printf(sc->dev,
4095 "failed to query config file location: %d.\n", rc);
4098 mtype = G_FW_PARAMS_PARAM_Y(val);
4099 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
4100 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4101 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4102 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4105 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
4107 device_printf(sc->dev,
4108 "failed to upload config file to card: %d.\n", rc);
4112 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4114 device_printf(sc->dev, "failed to pre-process config file: %d "
4115 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
4119 finicsum = be32toh(caps.finicsum);
4120 cfcsum = be32toh(caps.cfcsum); /* actual */
4121 if (finicsum != cfcsum) {
4122 device_printf(sc->dev,
4123 "WARNING: config file checksum mismatch: %08x %08x\n",
4126 sc->cfcsum = cfcsum;
4127 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
4130 * Let the firmware know what features will (not) be used so it can tune
4131 * things accordingly.
4133 #define LIMIT_CAPS(x) do { \
4134 caps.x##caps &= htobe16(caps_allowed->x##caps); \
4146 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4148 * TOE and hashfilters are mutually exclusive. It is a config
4149 * file or firmware bug if both are reported as available. Try
4150 * to cope with the situation in non-debug builds by disabling
4153 MPASS(caps.toecaps == 0);
4160 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4161 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4162 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4163 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
4165 device_printf(sc->dev,
4166 "failed to process config file: %d.\n", rc);
4170 t4_tweak_chip_settings(sc);
4171 set_params__pre_init(sc);
4173 /* get basic stuff going */
4174 rc = -t4_fw_initialize(sc, sc->mbox);
4176 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
4184 * Partition chip resources for use between various PFs, VFs, etc.
4187 partition_resources(struct adapter *sc)
4189 char cfg_file[sizeof(t4_cfg_file)];
4190 struct caps_allowed caps_allowed;
4194 /* Only the master driver gets to configure the chip resources. */
4195 MPASS(sc->flags & MASTER_PF);
4197 #define COPY_CAPS(x) do { \
4198 caps_allowed.x##caps = t4_##x##caps_allowed; \
4200 bzero(&caps_allowed, sizeof(caps_allowed));
4210 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
4211 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
4213 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
4214 if (rc != 0 && fallback) {
4215 device_printf(sc->dev,
4216 "failed (%d) to configure card with \"%s\" profile, "
4217 "will fall back to a basic configuration and retry.\n",
4219 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
4220 bzero(&caps_allowed, sizeof(caps_allowed));
4222 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
4231 * Retrieve parameters that are needed (or nice to have) very early.
4234 get_params__pre_init(struct adapter *sc)
4237 uint32_t param[2], val[2];
4239 t4_get_version_info(sc);
4241 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4242 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4243 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4244 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4245 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4247 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4248 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4249 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4250 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4251 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4253 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4254 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4255 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4256 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4257 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4259 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4260 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4261 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4262 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4263 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4265 param[0] = FW_PARAM_DEV(PORTVEC);
4266 param[1] = FW_PARAM_DEV(CCLK);
4267 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4269 device_printf(sc->dev,
4270 "failed to query parameters (pre_init): %d.\n", rc);
4274 sc->params.portvec = val[0];
4275 sc->params.nports = bitcount32(val[0]);
4276 sc->params.vpd.cclk = val[1];
4278 /* Read device log parameters. */
4279 rc = -t4_init_devlog_params(sc, 1);
4281 fixup_devlog_params(sc);
4283 device_printf(sc->dev,
4284 "failed to get devlog parameters: %d.\n", rc);
4285 rc = 0; /* devlog isn't critical for device operation */
4292 * Any params that need to be set before FW_INITIALIZE.
4295 set_params__pre_init(struct adapter *sc)
4298 uint32_t param, val;
4300 if (chip_id(sc) >= CHELSIO_T6) {
4301 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
4303 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4304 /* firmwares < 1.20.1.0 do not have this param. */
4305 if (rc == FW_EINVAL &&
4306 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
4310 device_printf(sc->dev,
4311 "failed to enable high priority filters :%d.\n",
4316 /* Enable opaque VIIDs with firmwares that support it. */
4317 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4319 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4320 if (rc == 0 && val == 1)
4321 sc->params.viid_smt_extn_support = true;
4323 sc->params.viid_smt_extn_support = false;
4329 * Retrieve various parameters that are of interest to the driver. The device
4330 * has been initialized by the firmware at this point.
4333 get_params__post_init(struct adapter *sc)
4336 uint32_t param[7], val[7];
4337 struct fw_caps_config_cmd caps;
4339 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4340 param[1] = FW_PARAM_PFVF(EQ_START);
4341 param[2] = FW_PARAM_PFVF(FILTER_START);
4342 param[3] = FW_PARAM_PFVF(FILTER_END);
4343 param[4] = FW_PARAM_PFVF(L2T_START);
4344 param[5] = FW_PARAM_PFVF(L2T_END);
4345 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4346 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4347 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4348 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4350 device_printf(sc->dev,
4351 "failed to query parameters (post_init): %d.\n", rc);
4355 sc->sge.iq_start = val[0];
4356 sc->sge.eq_start = val[1];
4357 if ((int)val[3] > (int)val[2]) {
4358 sc->tids.ftid_base = val[2];
4359 sc->tids.ftid_end = val[3];
4360 sc->tids.nftids = val[3] - val[2] + 1;
4362 sc->vres.l2t.start = val[4];
4363 sc->vres.l2t.size = val[5] - val[4] + 1;
4364 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4365 ("%s: L2 table size (%u) larger than expected (%u)",
4366 __func__, sc->vres.l2t.size, L2T_SIZE));
4367 sc->params.core_vdd = val[6];
4369 if (chip_id(sc) >= CHELSIO_T6) {
4371 sc->tids.tid_base = t4_read_reg(sc,
4372 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4374 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4375 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4376 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4378 device_printf(sc->dev,
4379 "failed to query hpfilter parameters: %d.\n", rc);
4382 if ((int)val[1] > (int)val[0]) {
4383 sc->tids.hpftid_base = val[0];
4384 sc->tids.hpftid_end = val[1];
4385 sc->tids.nhpftids = val[1] - val[0] + 1;
4388 * These should go off if the layout changes and the
4389 * driver needs to catch up.
4391 MPASS(sc->tids.hpftid_base == 0);
4392 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4397 * MPSBGMAP is queried separately because only recent firmwares support
4398 * it as a parameter and we don't want the compound query above to fail
4399 * on older firmwares.
4401 param[0] = FW_PARAM_DEV(MPSBGMAP);
4403 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4405 sc->params.mps_bg_map = val[0];
4407 sc->params.mps_bg_map = 0;
4410 * Determine whether the firmware supports the filter2 work request.
4411 * This is queried separately for the same reason as MPSBGMAP above.
4413 param[0] = FW_PARAM_DEV(FILTER2_WR);
4415 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4417 sc->params.filter2_wr_support = val[0] != 0;
4419 sc->params.filter2_wr_support = 0;
4422 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4423 * This is queried separately for the same reason as other params above.
4425 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4427 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4429 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4431 sc->params.ulptx_memwrite_dsgl = false;
4433 /* FW_RI_FR_NSMR_TPTE_WR support */
4434 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4435 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4437 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
4439 sc->params.fr_nsmr_tpte_wr_support = false;
4441 /* get capabilites */
4442 bzero(&caps, sizeof(caps));
4443 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4444 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4445 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4446 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4448 device_printf(sc->dev,
4449 "failed to get card capabilities: %d.\n", rc);
4453 #define READ_CAPS(x) do { \
4454 sc->x = htobe16(caps.x); \
4457 READ_CAPS(linkcaps);
4458 READ_CAPS(switchcaps);
4461 READ_CAPS(rdmacaps);
4462 READ_CAPS(cryptocaps);
4463 READ_CAPS(iscsicaps);
4464 READ_CAPS(fcoecaps);
4466 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4467 MPASS(chip_id(sc) > CHELSIO_T4);
4468 MPASS(sc->toecaps == 0);
4471 param[0] = FW_PARAM_DEV(NTID);
4472 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4474 device_printf(sc->dev,
4475 "failed to query HASHFILTER parameters: %d.\n", rc);
4478 sc->tids.ntids = val[0];
4479 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
4480 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4481 sc->tids.ntids -= sc->tids.nhpftids;
4483 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4484 sc->params.hash_filter = 1;
4486 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4487 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4488 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4489 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4490 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4492 device_printf(sc->dev,
4493 "failed to query NIC parameters: %d.\n", rc);
4496 if ((int)val[1] > (int)val[0]) {
4497 sc->tids.etid_base = val[0];
4498 sc->tids.etid_end = val[1];
4499 sc->tids.netids = val[1] - val[0] + 1;
4500 sc->params.eo_wr_cred = val[2];
4501 sc->params.ethoffload = 1;
4505 /* query offload-related parameters */
4506 param[0] = FW_PARAM_DEV(NTID);
4507 param[1] = FW_PARAM_PFVF(SERVER_START);
4508 param[2] = FW_PARAM_PFVF(SERVER_END);
4509 param[3] = FW_PARAM_PFVF(TDDP_START);
4510 param[4] = FW_PARAM_PFVF(TDDP_END);
4511 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4512 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4514 device_printf(sc->dev,
4515 "failed to query TOE parameters: %d.\n", rc);
4518 sc->tids.ntids = val[0];
4519 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
4520 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4521 sc->tids.ntids -= sc->tids.nhpftids;
4523 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4524 if ((int)val[2] > (int)val[1]) {
4525 sc->tids.stid_base = val[1];
4526 sc->tids.nstids = val[2] - val[1] + 1;
4528 sc->vres.ddp.start = val[3];
4529 sc->vres.ddp.size = val[4] - val[3] + 1;
4530 sc->params.ofldq_wr_cred = val[5];
4531 sc->params.offload = 1;
4534 * The firmware attempts memfree TOE configuration for -SO cards
4535 * and will report toecaps=0 if it runs out of resources (this
4536 * depends on the config file). It may not report 0 for other
4537 * capabilities dependent on the TOE in this case. Set them to
4538 * 0 here so that the driver doesn't bother tracking resources
4539 * that will never be used.
4545 param[0] = FW_PARAM_PFVF(STAG_START);
4546 param[1] = FW_PARAM_PFVF(STAG_END);
4547 param[2] = FW_PARAM_PFVF(RQ_START);
4548 param[3] = FW_PARAM_PFVF(RQ_END);
4549 param[4] = FW_PARAM_PFVF(PBL_START);
4550 param[5] = FW_PARAM_PFVF(PBL_END);
4551 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4553 device_printf(sc->dev,
4554 "failed to query RDMA parameters(1): %d.\n", rc);
4557 sc->vres.stag.start = val[0];
4558 sc->vres.stag.size = val[1] - val[0] + 1;
4559 sc->vres.rq.start = val[2];
4560 sc->vres.rq.size = val[3] - val[2] + 1;
4561 sc->vres.pbl.start = val[4];
4562 sc->vres.pbl.size = val[5] - val[4] + 1;
4564 param[0] = FW_PARAM_PFVF(SQRQ_START);
4565 param[1] = FW_PARAM_PFVF(SQRQ_END);
4566 param[2] = FW_PARAM_PFVF(CQ_START);
4567 param[3] = FW_PARAM_PFVF(CQ_END);
4568 param[4] = FW_PARAM_PFVF(OCQ_START);
4569 param[5] = FW_PARAM_PFVF(OCQ_END);
4570 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4572 device_printf(sc->dev,
4573 "failed to query RDMA parameters(2): %d.\n", rc);
4576 sc->vres.qp.start = val[0];
4577 sc->vres.qp.size = val[1] - val[0] + 1;
4578 sc->vres.cq.start = val[2];
4579 sc->vres.cq.size = val[3] - val[2] + 1;
4580 sc->vres.ocq.start = val[4];
4581 sc->vres.ocq.size = val[5] - val[4] + 1;
4583 param[0] = FW_PARAM_PFVF(SRQ_START);
4584 param[1] = FW_PARAM_PFVF(SRQ_END);
4585 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4586 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4587 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4589 device_printf(sc->dev,
4590 "failed to query RDMA parameters(3): %d.\n", rc);
4593 sc->vres.srq.start = val[0];
4594 sc->vres.srq.size = val[1] - val[0] + 1;
4595 sc->params.max_ordird_qp = val[2];
4596 sc->params.max_ird_adapter = val[3];
4598 if (sc->iscsicaps) {
4599 param[0] = FW_PARAM_PFVF(ISCSI_START);
4600 param[1] = FW_PARAM_PFVF(ISCSI_END);
4601 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4603 device_printf(sc->dev,
4604 "failed to query iSCSI parameters: %d.\n", rc);
4607 sc->vres.iscsi.start = val[0];
4608 sc->vres.iscsi.size = val[1] - val[0] + 1;
4610 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4611 param[0] = FW_PARAM_PFVF(TLS_START);
4612 param[1] = FW_PARAM_PFVF(TLS_END);
4613 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4615 device_printf(sc->dev,
4616 "failed to query TLS parameters: %d.\n", rc);
4619 sc->vres.key.start = val[0];
4620 sc->vres.key.size = val[1] - val[0] + 1;
4623 t4_init_sge_params(sc);
4626 * We've got the params we wanted to query via the firmware. Now grab
4627 * some others directly from the chip.
4629 rc = t4_read_chip_settings(sc);
4636 ktls_tick(void *arg)
4643 tstamp = tcp_ts_getticks();
4644 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
4645 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
4647 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
4651 t4_enable_kern_tls(struct adapter *sc)
4657 t4_set_reg_field(sc, A_TP_PARA_REG6, m, v);
4659 m = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN;
4660 v = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN;
4661 t4_set_reg_field(sc, A_ULP_TX_CONFIG, m, v);
4665 t4_set_reg_field(sc, A_TP_IN_CONFIG, m, v);
4667 m = F_LOOKUPEVERYPKT;
4669 t4_set_reg_field(sc, A_TP_INGRESS_CONFIG, m, v);
4671 m = F_TXDEFERENABLE | F_DISABLEWINDOWPSH | F_DISABLESEPPSHFLAG;
4672 v = F_DISABLEWINDOWPSH;
4673 t4_set_reg_field(sc, A_TP_PC_CONFIG, m, v);
4675 m = V_TIMESTAMPRESOLUTION(M_TIMESTAMPRESOLUTION);
4676 v = V_TIMESTAMPRESOLUTION(0x1f);
4677 t4_set_reg_field(sc, A_TP_TIMER_RESOLUTION, m, v);
4679 sc->flags |= KERN_TLS_OK;
4681 sc->tlst.inline_keys = t4_tls_inline_keys;
4682 sc->tlst.combo_wrs = t4_tls_combo_wrs;
4687 set_params__post_init(struct adapter *sc)
4689 uint32_t param, val;
4694 /* ask for encapsulated CPLs */
4695 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4697 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4699 /* Enable 32b port caps if the firmware supports it. */
4700 param = FW_PARAM_PFVF(PORT_CAPS32);
4702 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4703 sc->params.port_caps32 = 1;
4705 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4706 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4707 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4708 V_MASKFILTER(val - 1));
4712 * Override the TOE timers with user provided tunables. This is not the
4713 * recommended way to change the timers (the firmware config file is) so
4714 * these tunables are not documented.
4716 * All the timer tunables are in microseconds.
4718 if (t4_toe_keepalive_idle != 0) {
4719 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4720 v &= M_KEEPALIVEIDLE;
4721 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4722 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4724 if (t4_toe_keepalive_interval != 0) {
4725 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4726 v &= M_KEEPALIVEINTVL;
4727 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4728 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4730 if (t4_toe_keepalive_count != 0) {
4731 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4732 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4733 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4734 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4735 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4737 if (t4_toe_rexmt_min != 0) {
4738 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4740 t4_set_reg_field(sc, A_TP_RXT_MIN,
4741 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4743 if (t4_toe_rexmt_max != 0) {
4744 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4746 t4_set_reg_field(sc, A_TP_RXT_MAX,
4747 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4749 if (t4_toe_rexmt_count != 0) {
4750 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4751 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4752 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4753 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4754 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4756 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4757 if (t4_toe_rexmt_backoff[i] != -1) {
4758 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4759 shift = (i & 3) << 3;
4760 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4761 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4767 if (t4_kern_tls != 0 && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
4768 sc->toecaps & FW_CAPS_CONFIG_TOE)
4769 t4_enable_kern_tls(sc);
4774 #undef FW_PARAM_PFVF
4778 t4_set_desc(struct adapter *sc)
4781 struct adapter_params *p = &sc->params;
4783 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4785 device_set_desc_copy(sc->dev, buf);
4789 ifmedia_add4(struct ifmedia *ifm, int m)
4792 ifmedia_add(ifm, m, 0, NULL);
4793 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4794 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4795 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4799 * This is the selected media, which is not quite the same as the active media.
4800 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4801 * and active are not the same, and "media: Ethernet selected" otherwise.
4804 set_current_media(struct port_info *pi)
4806 struct link_config *lc;
4807 struct ifmedia *ifm;
4811 PORT_LOCK_ASSERT_OWNED(pi);
4813 /* Leave current media alone if it's already set to IFM_NONE. */
4815 if (ifm->ifm_cur != NULL &&
4816 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4820 if (lc->requested_aneg != AUTONEG_DISABLE &&
4821 lc->pcaps & FW_PORT_CAP32_ANEG) {
4822 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4825 mword = IFM_ETHER | IFM_FDX;
4826 if (lc->requested_fc & PAUSE_TX)
4827 mword |= IFM_ETH_TXPAUSE;
4828 if (lc->requested_fc & PAUSE_RX)
4829 mword |= IFM_ETH_RXPAUSE;
4830 if (lc->requested_speed == 0)
4831 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4833 speed = lc->requested_speed;
4834 mword |= port_mword(pi, speed_to_fwcap(speed));
4835 ifmedia_set(ifm, mword);
4839 * Returns true if the ifmedia list for the port cannot change.
4842 fixed_ifmedia(struct port_info *pi)
4845 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4846 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4847 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4848 pi->port_type == FW_PORT_TYPE_KX4 ||
4849 pi->port_type == FW_PORT_TYPE_KX ||
4850 pi->port_type == FW_PORT_TYPE_KR ||
4851 pi->port_type == FW_PORT_TYPE_BP_AP ||
4852 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4853 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4854 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4855 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4856 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4860 build_medialist(struct port_info *pi)
4863 int unknown, mword, bit;
4864 struct link_config *lc;
4865 struct ifmedia *ifm;
4867 PORT_LOCK_ASSERT_OWNED(pi);
4869 if (pi->flags & FIXED_IFMEDIA)
4873 * Rebuild the ifmedia list.
4876 ifmedia_removeall(ifm);
4878 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
4879 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4882 MPASS(LIST_EMPTY(&ifm->ifm_list));
4883 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4884 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4889 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4891 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4893 mword = port_mword(pi, speed);
4894 if (mword == IFM_NONE) {
4896 } else if (mword == IFM_UNKNOWN)
4899 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4902 if (unknown > 0) /* Add one unknown for all unknown media types. */
4903 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4904 if (lc->pcaps & FW_PORT_CAP32_ANEG)
4905 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4907 set_current_media(pi);
4911 * Initialize the requested fields in the link config based on driver tunables.
4914 init_link_config(struct port_info *pi)
4916 struct link_config *lc = &pi->link_cfg;
4918 PORT_LOCK_ASSERT_OWNED(pi);
4920 lc->requested_speed = 0;
4922 if (t4_autoneg == 0)
4923 lc->requested_aneg = AUTONEG_DISABLE;
4924 else if (t4_autoneg == 1)
4925 lc->requested_aneg = AUTONEG_ENABLE;
4927 lc->requested_aneg = AUTONEG_AUTO;
4929 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4932 if (t4_fec & FEC_AUTO)
4933 lc->requested_fec = FEC_AUTO;
4934 else if (t4_fec == 0)
4935 lc->requested_fec = FEC_NONE;
4937 /* -1 is handled by the FEC_AUTO block above and not here. */
4938 lc->requested_fec = t4_fec &
4939 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
4940 if (lc->requested_fec == 0)
4941 lc->requested_fec = FEC_AUTO;
4946 * Makes sure that all requested settings comply with what's supported by the
4947 * port. Returns the number of settings that were invalid and had to be fixed.
4950 fixup_link_config(struct port_info *pi)
4953 struct link_config *lc = &pi->link_cfg;
4956 PORT_LOCK_ASSERT_OWNED(pi);
4958 /* Speed (when not autonegotiating) */
4959 if (lc->requested_speed != 0) {
4960 fwspeed = speed_to_fwcap(lc->requested_speed);
4961 if ((fwspeed & lc->pcaps) == 0) {
4963 lc->requested_speed = 0;
4967 /* Link autonegotiation */
4968 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4969 lc->requested_aneg == AUTONEG_DISABLE ||
4970 lc->requested_aneg == AUTONEG_AUTO);
4971 if (lc->requested_aneg == AUTONEG_ENABLE &&
4972 !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4974 lc->requested_aneg = AUTONEG_AUTO;
4978 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4979 if (lc->requested_fc & PAUSE_TX &&
4980 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
4982 lc->requested_fc &= ~PAUSE_TX;
4984 if (lc->requested_fc & PAUSE_RX &&
4985 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
4987 lc->requested_fc &= ~PAUSE_RX;
4989 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4990 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
4992 lc->requested_fc |= PAUSE_AUTONEG;
4996 if ((lc->requested_fec & FEC_RS &&
4997 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
4998 (lc->requested_fec & FEC_BASER_RS &&
4999 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
5001 lc->requested_fec = FEC_AUTO;
5008 * Apply the requested L1 settings, which are expected to be valid, to the
5012 apply_link_config(struct port_info *pi)
5014 struct adapter *sc = pi->adapter;
5015 struct link_config *lc = &pi->link_cfg;
5019 ASSERT_SYNCHRONIZED_OP(sc);
5020 PORT_LOCK_ASSERT_OWNED(pi);
5022 if (lc->requested_aneg == AUTONEG_ENABLE)
5023 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
5024 if (!(lc->requested_fc & PAUSE_AUTONEG))
5025 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
5026 if (lc->requested_fc & PAUSE_TX)
5027 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
5028 if (lc->requested_fc & PAUSE_RX)
5029 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
5030 if (lc->requested_fec & FEC_RS)
5031 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
5032 if (lc->requested_fec & FEC_BASER_RS)
5033 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
5035 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5037 /* Don't complain if the VF driver gets back an EPERM. */
5038 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
5039 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
5042 * An L1_CFG will almost always result in a link-change event if
5043 * the link is up, and the driver will refresh the actual
5044 * fec/fc/etc. when the notification is processed. If the link
5045 * is down then the actual settings are meaningless.
5047 * This takes care of the case where a change in the L1 settings
5048 * may not result in a notification.
5050 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
5051 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
5056 #define FW_MAC_EXACT_CHUNK 7
5059 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
5067 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
5069 struct mcaddr_ctx *ctx = arg;
5070 struct vi_info *vi = ctx->ifp->if_softc;
5071 struct port_info *pi = vi->pi;
5072 struct adapter *sc = pi->adapter;
5077 ctx->mcaddr[ctx->i] = LLADDR(sdl);
5078 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
5081 if (ctx->i == FW_MAC_EXACT_CHUNK) {
5082 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
5083 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
5087 for (j = 0; j < ctx->i; j++) {
5089 "failed to add mc address"
5091 "%02x:%02x:%02x rc=%d\n",
5092 ctx->mcaddr[j][0], ctx->mcaddr[j][1],
5093 ctx->mcaddr[j][2], ctx->mcaddr[j][3],
5094 ctx->mcaddr[j][4], ctx->mcaddr[j][5],
5107 * Program the port's XGMAC based on parameters in ifnet. The caller also
5108 * indicates which parameters should be programmed (the rest are left alone).
5111 update_mac_settings(struct ifnet *ifp, int flags)
5114 struct vi_info *vi = ifp->if_softc;
5115 struct port_info *pi = vi->pi;
5116 struct adapter *sc = pi->adapter;
5117 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
5119 ASSERT_SYNCHRONIZED_OP(sc);
5120 KASSERT(flags, ("%s: not told what to update.", __func__));
5122 if (flags & XGMAC_MTU)
5125 if (flags & XGMAC_PROMISC)
5126 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
5128 if (flags & XGMAC_ALLMULTI)
5129 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
5131 if (flags & XGMAC_VLANEX)
5132 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
5134 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
5135 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
5136 allmulti, 1, vlanex, false);
5138 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
5144 if (flags & XGMAC_UCADDR) {
5145 uint8_t ucaddr[ETHER_ADDR_LEN];
5147 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
5148 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
5149 ucaddr, true, &vi->smt_idx);
5152 if_printf(ifp, "change_mac failed: %d\n", rc);
5155 vi->xact_addr_filt = rc;
5160 if (flags & XGMAC_MCADDRS) {
5161 struct epoch_tracker et;
5162 struct mcaddr_ctx ctx;
5171 * Unlike other drivers, we accumulate list of pointers into
5172 * interface address lists and we need to keep it safe even
5173 * after if_foreach_llmaddr() returns, thus we must enter the
5176 NET_EPOCH_ENTER(et);
5177 if_foreach_llmaddr(ifp, add_maddr, &ctx);
5184 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
5185 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
5189 for (j = 0; j < ctx.i; j++) {
5191 "failed to add mc address"
5193 "%02x:%02x:%02x rc=%d\n",
5194 ctx.mcaddr[j][0], ctx.mcaddr[j][1],
5195 ctx.mcaddr[j][2], ctx.mcaddr[j][3],
5196 ctx.mcaddr[j][4], ctx.mcaddr[j][5],
5204 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
5206 if_printf(ifp, "failed to set mc address hash: %d", rc);
5213 * {begin|end}_synchronized_op must be called from the same thread.
5216 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
5222 /* the caller thinks it's ok to sleep, but is it really? */
5223 if (flags & SLEEP_OK)
5224 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
5225 "begin_synchronized_op");
5236 if (vi && IS_DOOMED(vi)) {
5246 if (!(flags & SLEEP_OK)) {
5251 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
5257 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
5260 sc->last_op = wmesg;
5261 sc->last_op_thr = curthread;
5262 sc->last_op_flags = flags;
5266 if (!(flags & HOLD_LOCK) || rc)
5273 * Tell if_ioctl and if_init that the VI is going away. This is
5274 * special variant of begin_synchronized_op and must be paired with a
5275 * call to end_synchronized_op.
5278 doom_vi(struct adapter *sc, struct vi_info *vi)
5285 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
5288 sc->last_op = "t4detach";
5289 sc->last_op_thr = curthread;
5290 sc->last_op_flags = 0;
5296 * {begin|end}_synchronized_op must be called from the same thread.
5299 end_synchronized_op(struct adapter *sc, int flags)
5302 if (flags & LOCK_HELD)
5303 ADAPTER_LOCK_ASSERT_OWNED(sc);
5307 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
5314 cxgbe_init_synchronized(struct vi_info *vi)
5316 struct port_info *pi = vi->pi;
5317 struct adapter *sc = pi->adapter;
5318 struct ifnet *ifp = vi->ifp;
5320 struct sge_txq *txq;
5322 ASSERT_SYNCHRONIZED_OP(sc);
5324 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5325 return (0); /* already running */
5327 if (!(sc->flags & FULL_INIT_DONE) &&
5328 ((rc = adapter_full_init(sc)) != 0))
5329 return (rc); /* error message displayed already */
5331 if (!(vi->flags & VI_INIT_DONE) &&
5332 ((rc = vi_full_init(vi)) != 0))
5333 return (rc); /* error message displayed already */
5335 rc = update_mac_settings(ifp, XGMAC_ALL);
5337 goto done; /* error message displayed already */
5340 if (pi->up_vis == 0) {
5341 t4_update_port_info(pi);
5342 fixup_link_config(pi);
5343 build_medialist(pi);
5344 apply_link_config(pi);
5347 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5349 if_printf(ifp, "enable_vi failed: %d\n", rc);
5355 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5359 for_each_txq(vi, i, txq) {
5361 txq->eq.flags |= EQ_ENABLED;
5366 * The first iq of the first port to come up is used for tracing.
5368 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5369 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5370 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5371 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5372 V_QUEUENUMBER(sc->traceq));
5373 pi->flags |= HAS_TRACEQ;
5378 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5380 if (pi->nvi > 1 || sc->flags & IS_VF)
5381 callout_reset(&vi->tick, hz, vi_tick, vi);
5383 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5384 if (pi->link_cfg.link_ok)
5385 t4_os_link_changed(pi);
5389 cxgbe_uninit_synchronized(vi);
5398 cxgbe_uninit_synchronized(struct vi_info *vi)
5400 struct port_info *pi = vi->pi;
5401 struct adapter *sc = pi->adapter;
5402 struct ifnet *ifp = vi->ifp;
5404 struct sge_txq *txq;
5406 ASSERT_SYNCHRONIZED_OP(sc);
5408 if (!(vi->flags & VI_INIT_DONE)) {
5409 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5410 KASSERT(0, ("uninited VI is running"));
5411 if_printf(ifp, "uninited VI with running ifnet. "
5412 "vi->flags 0x%016lx, if_flags 0x%08x, "
5413 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5420 * Disable the VI so that all its data in either direction is discarded
5421 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5422 * tick) intact as the TP can deliver negative advice or data that it's
5423 * holding in its RAM (for an offloaded connection) even after the VI is
5426 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5428 if_printf(ifp, "disable_vi failed: %d\n", rc);
5432 for_each_txq(vi, i, txq) {
5434 txq->eq.flags &= ~EQ_ENABLED;
5439 if (pi->nvi > 1 || sc->flags & IS_VF)
5440 callout_stop(&vi->tick);
5442 callout_stop(&pi->tick);
5443 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5447 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5449 if (pi->up_vis > 0) {
5454 pi->link_cfg.link_ok = false;
5455 pi->link_cfg.speed = 0;
5456 pi->link_cfg.link_down_rc = 255;
5457 t4_os_link_changed(pi);
5464 * It is ok for this function to fail midway and return right away. t4_detach
5465 * will walk the entire sc->irq list and clean up whatever is valid.
5468 t4_setup_intr_handlers(struct adapter *sc)
5470 int rc, rid, p, q, v;
5473 struct port_info *pi;
5475 struct sge *sge = &sc->sge;
5476 struct sge_rxq *rxq;
5478 struct sge_ofld_rxq *ofld_rxq;
5481 struct sge_nm_rxq *nm_rxq;
5484 int nbuckets = rss_getnumbuckets();
5491 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5492 if (forwarding_intr_to_fwq(sc))
5493 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5495 /* Multiple interrupts. */
5496 if (sc->flags & IS_VF)
5497 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5498 ("%s: too few intr.", __func__));
5500 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5501 ("%s: too few intr.", __func__));
5503 /* The first one is always error intr on PFs */
5504 if (!(sc->flags & IS_VF)) {
5505 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5512 /* The second one is always the firmware event queue (first on VFs) */
5513 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5519 for_each_port(sc, p) {
5521 for_each_vi(pi, v, vi) {
5522 vi->first_intr = rid - 1;
5524 if (vi->nnmrxq > 0) {
5525 int n = max(vi->nrxq, vi->nnmrxq);
5527 rxq = &sge->rxq[vi->first_rxq];
5529 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5531 for (q = 0; q < n; q++) {
5532 snprintf(s, sizeof(s), "%x%c%x", p,
5538 irq->nm_rxq = nm_rxq++;
5540 if (irq->nm_rxq != NULL &&
5542 /* Netmap rx only */
5543 rc = t4_alloc_irq(sc, irq, rid,
5544 t4_nm_intr, irq->nm_rxq, s);
5546 if (irq->nm_rxq != NULL &&
5548 /* NIC and Netmap rx */
5549 rc = t4_alloc_irq(sc, irq, rid,
5550 t4_vi_intr, irq, s);
5553 if (irq->rxq != NULL &&
5554 irq->nm_rxq == NULL) {
5556 rc = t4_alloc_irq(sc, irq, rid,
5557 t4_intr, irq->rxq, s);
5563 bus_bind_intr(sc->dev, irq->res,
5564 rss_getcpu(q % nbuckets));
5572 for_each_rxq(vi, q, rxq) {
5573 snprintf(s, sizeof(s), "%x%c%x", p,
5575 rc = t4_alloc_irq(sc, irq, rid,
5580 bus_bind_intr(sc->dev, irq->res,
5581 rss_getcpu(q % nbuckets));
5589 for_each_ofld_rxq(vi, q, ofld_rxq) {
5590 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5591 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5602 MPASS(irq == &sc->irq[sc->intr_count]);
5608 adapter_full_init(struct adapter *sc)
5612 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5613 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5616 ASSERT_SYNCHRONIZED_OP(sc);
5617 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5618 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5619 ("%s: FULL_INIT_DONE already", __func__));
5622 * queues that belong to the adapter (not any particular port).
5624 rc = t4_setup_adapter_queues(sc);
5628 for (i = 0; i < nitems(sc->tq); i++) {
5629 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5630 taskqueue_thread_enqueue, &sc->tq[i]);
5631 if (sc->tq[i] == NULL) {
5632 device_printf(sc->dev,
5633 "failed to allocate task queue %d\n", i);
5637 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5638 device_get_nameunit(sc->dev), i);
5641 MPASS(RSS_KEYSIZE == 40);
5642 rss_getkey((void *)&raw_rss_key[0]);
5643 for (i = 0; i < nitems(rss_key); i++) {
5644 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5646 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5649 if (!(sc->flags & IS_VF))
5652 if (sc->flags & KERN_TLS_OK)
5653 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
5656 sc->flags |= FULL_INIT_DONE;
5659 adapter_full_uninit(sc);
5665 adapter_full_uninit(struct adapter *sc)
5669 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5671 t4_teardown_adapter_queues(sc);
5673 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5674 taskqueue_free(sc->tq[i]);
5678 sc->flags &= ~FULL_INIT_DONE;
5684 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5685 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5686 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5687 RSS_HASHTYPE_RSS_UDP_IPV6)
5689 /* Translates kernel hash types to hardware. */
5691 hashconfig_to_hashen(int hashconfig)
5695 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5696 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5697 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5698 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5699 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5700 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5701 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5703 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5704 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5705 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5707 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5708 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5709 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5710 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5715 /* Translates hardware hash types to kernel. */
5717 hashen_to_hashconfig(int hashen)
5721 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5723 * If UDP hashing was enabled it must have been enabled for
5724 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5725 * enabling any 4-tuple hash is nonsense configuration.
5727 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5728 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5730 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5731 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5732 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5733 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5735 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5736 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5737 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5738 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5739 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5740 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5741 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5742 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5744 return (hashconfig);
5749 vi_full_init(struct vi_info *vi)
5751 struct adapter *sc = vi->pi->adapter;
5752 struct ifnet *ifp = vi->ifp;
5754 struct sge_rxq *rxq;
5757 int nbuckets = rss_getnumbuckets();
5758 int hashconfig = rss_gethashconfig();
5762 ASSERT_SYNCHRONIZED_OP(sc);
5763 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5764 ("%s: VI_INIT_DONE already", __func__));
5766 sysctl_ctx_init(&vi->ctx);
5767 vi->flags |= VI_SYSCTL_CTX;
5770 * Allocate tx/rx/fl queues for this VI.
5772 rc = t4_setup_vi_queues(vi);
5774 goto done; /* error message displayed already */
5777 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5779 if (vi->nrxq > vi->rss_size) {
5780 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5781 "some queues will never receive traffic.\n", vi->nrxq,
5783 } else if (vi->rss_size % vi->nrxq) {
5784 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5785 "expect uneven traffic distribution.\n", vi->nrxq,
5789 if (vi->nrxq != nbuckets) {
5790 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5791 "performance will be impacted.\n", vi->nrxq, nbuckets);
5794 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5795 for (i = 0; i < vi->rss_size;) {
5797 j = rss_get_indirection_to_bucket(i);
5799 rxq = &sc->sge.rxq[vi->first_rxq + j];
5800 rss[i++] = rxq->iq.abs_id;
5802 for_each_rxq(vi, j, rxq) {
5803 rss[i++] = rxq->iq.abs_id;
5804 if (i == vi->rss_size)
5810 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5814 if_printf(ifp, "rss_config failed: %d\n", rc);
5819 vi->hashen = hashconfig_to_hashen(hashconfig);
5822 * We may have had to enable some hashes even though the global config
5823 * wants them disabled. This is a potential problem that must be
5824 * reported to the user.
5826 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5829 * If we consider only the supported hash types, then the enabled hashes
5830 * are a superset of the requested hashes. In other words, there cannot
5831 * be any supported hash that was requested but not enabled, but there
5832 * can be hashes that were not requested but had to be enabled.
5834 extra &= SUPPORTED_RSS_HASHTYPES;
5835 MPASS((extra & hashconfig) == 0);
5839 "global RSS config (0x%x) cannot be accommodated.\n",
5842 if (extra & RSS_HASHTYPE_RSS_IPV4)
5843 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5844 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5845 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5846 if (extra & RSS_HASHTYPE_RSS_IPV6)
5847 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5848 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5849 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5850 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5851 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5852 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5853 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5855 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5856 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5857 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5858 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5860 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5863 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5868 vi->flags |= VI_INIT_DONE;
5880 vi_full_uninit(struct vi_info *vi)
5882 struct port_info *pi = vi->pi;
5883 struct adapter *sc = pi->adapter;
5885 struct sge_rxq *rxq;
5886 struct sge_txq *txq;
5888 struct sge_ofld_rxq *ofld_rxq;
5890 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5891 struct sge_wrq *ofld_txq;
5894 if (vi->flags & VI_INIT_DONE) {
5896 /* Need to quiesce queues. */
5898 /* XXX: Only for the first VI? */
5899 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5900 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5902 for_each_txq(vi, i, txq) {
5903 quiesce_txq(sc, txq);
5906 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5907 for_each_ofld_txq(vi, i, ofld_txq) {
5908 quiesce_wrq(sc, ofld_txq);
5912 for_each_rxq(vi, i, rxq) {
5913 quiesce_iq(sc, &rxq->iq);
5914 quiesce_fl(sc, &rxq->fl);
5918 for_each_ofld_rxq(vi, i, ofld_rxq) {
5919 quiesce_iq(sc, &ofld_rxq->iq);
5920 quiesce_fl(sc, &ofld_rxq->fl);
5923 free(vi->rss, M_CXGBE);
5924 free(vi->nm_rss, M_CXGBE);
5927 t4_teardown_vi_queues(vi);
5928 vi->flags &= ~VI_INIT_DONE;
5934 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5936 struct sge_eq *eq = &txq->eq;
5937 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5939 (void) sc; /* unused */
5943 MPASS((eq->flags & EQ_ENABLED) == 0);
5947 /* Wait for the mp_ring to empty. */
5948 while (!mp_ring_is_idle(txq->r)) {
5949 mp_ring_check_drainage(txq->r, 0);
5950 pause("rquiesce", 1);
5953 /* Then wait for the hardware to finish. */
5954 while (spg->cidx != htobe16(eq->pidx))
5955 pause("equiesce", 1);
5957 /* Finally, wait for the driver to reclaim all descriptors. */
5958 while (eq->cidx != eq->pidx)
5959 pause("dquiesce", 1);
5963 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5970 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5972 (void) sc; /* unused */
5974 /* Synchronize with the interrupt handler */
5975 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5980 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5982 mtx_lock(&sc->sfl_lock);
5984 fl->flags |= FL_DOOMED;
5986 callout_stop(&sc->sfl_callout);
5987 mtx_unlock(&sc->sfl_lock);
5989 KASSERT((fl->flags & FL_STARVING) == 0,
5990 ("%s: still starving", __func__));
5994 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5995 driver_intr_t *handler, void *arg, char *name)
6000 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
6001 RF_SHAREABLE | RF_ACTIVE);
6002 if (irq->res == NULL) {
6003 device_printf(sc->dev,
6004 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
6008 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
6009 NULL, handler, arg, &irq->tag);
6011 device_printf(sc->dev,
6012 "failed to setup interrupt for rid %d, name %s: %d\n",
6015 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
6021 t4_free_irq(struct adapter *sc, struct irq *irq)
6024 bus_teardown_intr(sc->dev, irq->res, irq->tag);
6026 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
6028 bzero(irq, sizeof(*irq));
6034 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
6037 regs->version = chip_id(sc) | chip_rev(sc) << 10;
6038 t4_get_regs(sc, buf, regs->len);
6041 #define A_PL_INDIR_CMD 0x1f8
6043 #define S_PL_AUTOINC 31
6044 #define M_PL_AUTOINC 0x1U
6045 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
6046 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
6048 #define S_PL_VFID 20
6049 #define M_PL_VFID 0xffU
6050 #define V_PL_VFID(x) ((x) << S_PL_VFID)
6051 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
6054 #define M_PL_ADDR 0xfffffU
6055 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
6056 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
6058 #define A_PL_INDIR_DATA 0x1fc
6061 read_vf_stat(struct adapter *sc, u_int vin, int reg)
6065 mtx_assert(&sc->reg_lock, MA_OWNED);
6066 if (sc->flags & IS_VF) {
6067 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
6068 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
6070 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
6071 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
6072 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
6073 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
6075 return (((uint64_t)stats[1]) << 32 | stats[0]);
6079 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
6082 #define GET_STAT(name) \
6083 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
6085 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
6086 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
6087 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
6088 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
6089 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
6090 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
6091 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
6092 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
6093 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
6094 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
6095 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
6096 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
6097 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
6098 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
6099 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
6100 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
6106 t4_clr_vi_stats(struct adapter *sc, u_int vin)
6110 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
6111 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
6112 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
6113 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
6114 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
6118 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
6121 const struct timeval interval = {0, 250000}; /* 250ms */
6123 if (!(vi->flags & VI_INIT_DONE))
6127 timevalsub(&tv, &interval);
6128 if (timevalcmp(&tv, &vi->last_refreshed, <))
6131 mtx_lock(&sc->reg_lock);
6132 t4_get_vi_stats(sc, vi->vin, &vi->stats);
6133 getmicrotime(&vi->last_refreshed);
6134 mtx_unlock(&sc->reg_lock);
6138 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
6140 u_int i, v, tnl_cong_drops, chan_map;
6142 const struct timeval interval = {0, 250000}; /* 250ms */
6145 timevalsub(&tv, &interval);
6146 if (timevalcmp(&tv, &pi->last_refreshed, <))
6150 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
6151 chan_map = pi->rx_e_chan_map;
6153 i = ffs(chan_map) - 1;
6154 mtx_lock(&sc->reg_lock);
6155 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
6156 A_TP_MIB_TNL_CNG_DROP_0 + i);
6157 mtx_unlock(&sc->reg_lock);
6158 tnl_cong_drops += v;
6159 chan_map &= ~(1 << i);
6161 pi->tnl_cong_drops = tnl_cong_drops;
6162 getmicrotime(&pi->last_refreshed);
6166 cxgbe_tick(void *arg)
6168 struct port_info *pi = arg;
6169 struct adapter *sc = pi->adapter;
6171 PORT_LOCK_ASSERT_OWNED(pi);
6172 cxgbe_refresh_stats(sc, pi);
6174 callout_schedule(&pi->tick, hz);
6180 struct vi_info *vi = arg;
6181 struct adapter *sc = vi->pi->adapter;
6183 vi_refresh_stats(sc, vi);
6185 callout_schedule(&vi->tick, hz);
6189 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
6191 static char *caps_decoder[] = {
6192 "\20\001IPMI\002NCSI", /* 0: NBM */
6193 "\20\001PPP\002QFC\003DCBX", /* 1: link */
6194 "\20\001INGRESS\002EGRESS", /* 2: switch */
6195 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
6196 "\006HASHFILTER\007ETHOFLD",
6197 "\20\001TOE", /* 4: TOE */
6198 "\20\001RDDP\002RDMAC", /* 5: RDMA */
6199 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
6200 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
6201 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
6203 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
6204 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
6205 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
6206 "\004PO_INITIATOR\005PO_TARGET",
6210 t4_sysctls(struct adapter *sc)
6212 struct sysctl_ctx_list *ctx;
6213 struct sysctl_oid *oid;
6214 struct sysctl_oid_list *children, *c0;
6215 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
6217 ctx = device_get_sysctl_ctx(sc->dev);
6222 oid = device_get_sysctl_tree(sc->dev);
6223 c0 = children = SYSCTL_CHILDREN(oid);
6225 sc->sc_do_rxcopy = 1;
6226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
6227 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
6229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
6230 sc->params.nports, "# of ports");
6232 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
6233 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
6234 sysctl_bitfield_8b, "A", "available doorbells");
6236 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
6237 sc->params.vpd.cclk, "core clock frequency (in KHz)");
6239 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
6240 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
6241 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
6242 "interrupt holdoff timer values (us)");
6244 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
6245 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
6246 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
6247 "interrupt holdoff packet counter values");
6249 t4_sge_sysctls(sc, ctx, children);
6251 sc->lro_timeout = 100;
6252 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
6253 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
6255 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
6256 &sc->debug_flags, 0, "flags to enable runtime debugging");
6258 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
6259 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
6261 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
6262 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
6264 if (sc->flags & IS_VF)
6267 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
6268 NULL, chip_rev(sc), "chip hardware revision");
6270 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
6271 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
6273 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
6274 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
6276 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
6277 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
6279 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
6280 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
6282 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
6283 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
6285 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
6286 sc->er_version, 0, "expansion ROM version");
6288 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
6289 sc->bs_version, 0, "bootstrap firmware version");
6291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
6292 NULL, sc->params.scfg_vers, "serial config version");
6294 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
6295 NULL, sc->params.vpd_vers, "VPD version");
6297 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
6298 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
6300 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
6301 sc->cfcsum, "config file checksum");
6303 #define SYSCTL_CAP(name, n, text) \
6304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
6305 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
6306 sysctl_bitfield_16b, "A", "available " text " capabilities")
6308 SYSCTL_CAP(nbmcaps, 0, "NBM");
6309 SYSCTL_CAP(linkcaps, 1, "link");
6310 SYSCTL_CAP(switchcaps, 2, "switch");
6311 SYSCTL_CAP(niccaps, 3, "NIC");
6312 SYSCTL_CAP(toecaps, 4, "TCP offload");
6313 SYSCTL_CAP(rdmacaps, 5, "RDMA");
6314 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
6315 SYSCTL_CAP(cryptocaps, 7, "crypto");
6316 SYSCTL_CAP(fcoecaps, 8, "FCoE");
6319 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
6320 NULL, sc->tids.nftids, "number of filters");
6322 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
6323 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
6324 "chip temperature (in Celsius)");
6325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor", CTLTYPE_INT |
6326 CTLFLAG_RW, sc, 0, sysctl_reset_sensor, "I",
6327 "reset the chip's temperature sensor.");
6329 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
6330 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
6331 "microprocessor load averages (debug firmwares only)");
6333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd", CTLTYPE_INT |
6334 CTLFLAG_RD, sc, 0, sysctl_vdd, "I", "core Vdd (in mV)");
6336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
6337 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
6338 sysctl_cpus, "A", "local CPUs");
6340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
6341 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
6342 sysctl_cpus, "A", "preferred CPUs for interrupts");
6344 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
6345 &sc->swintr, 0, "software triggered interrupts");
6348 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
6350 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
6351 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
6352 "logs and miscellaneous information");
6353 children = SYSCTL_CHILDREN(oid);
6355 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6356 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6357 sysctl_cctrl, "A", "congestion control");
6359 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6360 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6361 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6363 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6364 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
6365 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6367 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6368 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
6369 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6371 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6372 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
6373 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6375 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6376 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
6377 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6379 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6380 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
6381 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6384 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la,
6385 "A", "CIM logic analyzer");
6387 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6388 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6389 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6391 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6392 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
6393 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6395 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6396 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
6397 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6399 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6400 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
6401 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6403 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6404 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
6405 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6407 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6408 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
6409 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6411 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6412 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
6413 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6415 if (chip_id(sc) > CHELSIO_T4) {
6416 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6417 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
6418 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
6420 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6421 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
6422 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
6425 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6426 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6427 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6429 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6430 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6431 sysctl_cim_qcfg, "A", "CIM queue configuration");
6433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6434 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6435 sysctl_cpl_stats, "A", "CPL statistics");
6437 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6438 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6439 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6442 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6443 sysctl_devlog, "A", "firmware's device log");
6445 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6446 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6447 sysctl_fcoe_stats, "A", "FCoE statistics");
6449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6450 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6451 sysctl_hw_sched, "A", "hardware scheduler ");
6453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6454 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6455 sysctl_l2t, "A", "hardware L2 table");
6457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6458 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6459 sysctl_smt, "A", "hardware source MAC table");
6462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6463 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6464 sysctl_clip, "A", "active CLIP table entries");
6467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6468 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6469 sysctl_lb_stats, "A", "loopback statistics");
6471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6472 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6473 sysctl_meminfo, "A", "memory regions");
6475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6476 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6477 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6478 "A", "MPS TCAM entries");
6480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6481 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6482 sysctl_path_mtus, "A", "path MTUs");
6484 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6485 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6486 sysctl_pm_stats, "A", "PM statistics");
6488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6489 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6490 sysctl_rdma_stats, "A", "RDMA statistics");
6492 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6493 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6494 sysctl_tcp_stats, "A", "TCP statistics");
6496 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6497 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6498 sysctl_tids, "A", "TID information");
6500 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6501 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6502 sysctl_tp_err_stats, "A", "TP error statistics");
6504 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6505 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
6506 "TP logic analyzer event capture mask");
6508 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6509 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6510 sysctl_tp_la, "A", "TP logic analyzer");
6512 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6513 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6514 sysctl_tx_rate, "A", "Tx rate");
6516 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6517 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6518 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6520 if (chip_id(sc) >= CHELSIO_T5) {
6521 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6522 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6523 sysctl_wcwr_stats, "A", "write combined work requests");
6527 if (sc->flags & KERN_TLS_OK) {
6531 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls", CTLFLAG_RD,
6532 NULL, "KERN_TLS parameters");
6533 children = SYSCTL_CHILDREN(oid);
6535 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
6536 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
6537 "keys in work requests (1) or attempt to store TLS keys "
6539 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
6540 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to combine "
6541 "TCB field updates with TLS record work requests.");
6546 if (is_offload(sc)) {
6553 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
6554 NULL, "TOE parameters");
6555 children = SYSCTL_CHILDREN(oid);
6557 sc->tt.cong_algorithm = -1;
6558 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6559 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6560 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6564 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6565 &sc->tt.sndbuf, 0, "hardware send buffer");
6568 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
6569 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
6570 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
6571 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
6573 sc->tt.rx_coalesce = -1;
6574 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6575 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6578 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6579 &sc->tt.tls, 0, "Inline TLS allowed");
6581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6582 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
6583 "I", "TCP ports that use inline TLS+TOE RX");
6585 sc->tt.tx_align = -1;
6586 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6587 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6589 sc->tt.tx_zcopy = 0;
6590 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6591 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6592 "Enable zero-copy aio_write(2)");
6594 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6595 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6596 "cop_managed_offloading", CTLFLAG_RW,
6597 &sc->tt.cop_managed_offloading, 0,
6598 "COP (Connection Offload Policy) controls all TOE offload");
6600 sc->tt.autorcvbuf_inc = 16 * 1024;
6601 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
6602 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
6603 "autorcvbuf increment");
6605 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6606 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6607 "TP timer tick (us)");
6609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6610 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6611 "TCP timestamp tick (us)");
6613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6614 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6617 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6618 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6619 "IU", "DACK timer (us)");
6621 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6622 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6623 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6626 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6627 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6629 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6630 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6631 sysctl_tp_timer, "LU", "Persist timer min (us)");
6633 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6634 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6635 sysctl_tp_timer, "LU", "Persist timer max (us)");
6637 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6638 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6639 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6641 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6642 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6643 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6645 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6646 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6647 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6650 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6651 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6654 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6655 sysctl_tp_shift_cnt, "IU",
6656 "Number of SYN retransmissions before abort");
6658 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6659 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6660 sysctl_tp_shift_cnt, "IU",
6661 "Number of retransmissions before abort");
6663 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6664 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6665 sysctl_tp_shift_cnt, "IU",
6666 "Number of keepalive probes before abort");
6668 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6669 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6670 children = SYSCTL_CHILDREN(oid);
6671 for (i = 0; i < 16; i++) {
6672 snprintf(s, sizeof(s), "%u", i);
6673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6674 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6675 "IU", "TOE retransmit backoff");
6682 vi_sysctls(struct vi_info *vi)
6684 struct sysctl_ctx_list *ctx;
6685 struct sysctl_oid *oid;
6686 struct sysctl_oid_list *children;
6688 ctx = device_get_sysctl_ctx(vi->dev);
6691 * dev.v?(cxgbe|cxl).X.
6693 oid = device_get_sysctl_tree(vi->dev);
6694 children = SYSCTL_CHILDREN(oid);
6696 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6697 vi->viid, "VI identifer");
6698 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6699 &vi->nrxq, 0, "# of rx queues");
6700 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6701 &vi->ntxq, 0, "# of tx queues");
6702 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6703 &vi->first_rxq, 0, "index of first rx queue");
6704 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6705 &vi->first_txq, 0, "index of first tx queue");
6706 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6707 vi->rss_base, "start of RSS indirection table");
6708 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6709 vi->rss_size, "size of RSS indirection table");
6711 if (IS_MAIN_VI(vi)) {
6712 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6713 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6714 "Reserve queue 0 for non-flowid packets");
6718 if (vi->nofldrxq != 0) {
6719 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6721 "# of rx queues for offloaded TCP connections");
6722 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6723 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6724 "index of first TOE rx queue");
6725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6726 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6727 sysctl_holdoff_tmr_idx_ofld, "I",
6728 "holdoff timer index for TOE queues");
6729 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6730 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6731 sysctl_holdoff_pktc_idx_ofld, "I",
6732 "holdoff packet counter index for TOE queues");
6735 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6736 if (vi->nofldtxq != 0) {
6737 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6739 "# of tx queues for TOE/ETHOFLD");
6740 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6741 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6742 "index of first TOE/ETHOFLD tx queue");
6746 if (vi->nnmrxq != 0) {
6747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6748 &vi->nnmrxq, 0, "# of netmap rx queues");
6749 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6750 &vi->nnmtxq, 0, "# of netmap tx queues");
6751 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6752 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6753 "index of first netmap rx queue");
6754 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6755 CTLFLAG_RD, &vi->first_nm_txq, 0,
6756 "index of first netmap tx queue");
6760 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6761 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6762 "holdoff timer index");
6763 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6764 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6765 "holdoff packet counter index");
6767 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6768 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6770 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6771 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6776 cxgbe_sysctls(struct port_info *pi)
6778 struct sysctl_ctx_list *ctx;
6779 struct sysctl_oid *oid;
6780 struct sysctl_oid_list *children, *children2;
6781 struct adapter *sc = pi->adapter;
6784 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6786 ctx = device_get_sysctl_ctx(pi->dev);
6791 oid = device_get_sysctl_tree(pi->dev);
6792 children = SYSCTL_CHILDREN(oid);
6794 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6795 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6796 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6797 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6798 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6799 "PHY temperature (in Celsius)");
6800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6801 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6802 "PHY firmware version");
6805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6806 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6807 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6809 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6810 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
6811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
6812 CTLTYPE_STRING, pi, 0, sysctl_module_fec, "A",
6813 "FEC recommended by the cable/transceiver");
6814 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6815 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6816 "autonegotiation (-1 = not supported)");
6818 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
6819 &pi->link_cfg.pcaps, 0, "port capabilities");
6820 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
6821 &pi->link_cfg.acaps, 0, "advertised capabilities");
6822 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
6823 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
6825 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6826 port_top_speed(pi), "max speed (in Gbps)");
6827 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6828 pi->mps_bg_map, "MPS buffer group map");
6829 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6830 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6832 if (sc->flags & IS_VF)
6836 * dev.(cxgbe|cxl).X.tc.
6838 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6839 "Tx scheduler traffic classes (cl_rl)");
6840 children2 = SYSCTL_CHILDREN(oid);
6841 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6842 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6843 "pktsize for per-flow cl-rl (0 means up to the driver )");
6844 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6845 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6846 "burstsize for per-flow cl-rl (0 means up to the driver)");
6847 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6848 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6850 snprintf(name, sizeof(name), "%d", i);
6851 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6852 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6854 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6855 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6856 sysctl_bitfield_8b, "A", "flags");
6857 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6858 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6859 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6860 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6861 sysctl_tc_params, "A", "traffic class parameters");
6865 * dev.cxgbe.X.stats.
6867 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6868 NULL, "port statistics");
6869 children = SYSCTL_CHILDREN(oid);
6870 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6871 &pi->tx_parse_error, 0,
6872 "# of tx packets with invalid length or # of segments");
6874 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6875 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6876 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6877 sysctl_handle_t4_reg64, "QU", desc)
6879 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6880 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6881 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6882 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6883 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6884 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6885 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6886 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6887 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6888 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6889 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6890 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6891 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6892 "# of tx frames in this range",
6893 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6894 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6895 "# of tx frames in this range",
6896 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6897 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6898 "# of tx frames in this range",
6899 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6900 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6901 "# of tx frames in this range",
6902 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6903 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6904 "# of tx frames in this range",
6905 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6906 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6907 "# of tx frames in this range",
6908 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6909 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6910 "# of tx frames in this range",
6911 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6912 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6913 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6914 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6915 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6916 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6917 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6918 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6919 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6920 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6921 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6922 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6923 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6924 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6925 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6926 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6927 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6928 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6929 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6930 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6931 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6933 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6934 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6935 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6936 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6937 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6938 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6939 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6940 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6941 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6942 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6943 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6944 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6945 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6946 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6947 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6948 "# of frames received with bad FCS",
6949 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6950 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6951 "# of frames received with length error",
6952 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6953 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6954 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6955 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6956 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6957 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6958 "# of rx frames in this range",
6959 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6960 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6961 "# of rx frames in this range",
6962 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6963 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6964 "# of rx frames in this range",
6965 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6966 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6967 "# of rx frames in this range",
6968 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6969 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6970 "# of rx frames in this range",
6971 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6972 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6973 "# of rx frames in this range",
6974 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6975 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6976 "# of rx frames in this range",
6977 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6978 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6979 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6980 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6981 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6982 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6983 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6984 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6985 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6986 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6987 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6988 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6989 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6990 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6991 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6992 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6993 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6994 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6995 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6997 #undef SYSCTL_ADD_T4_REG64
6999 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
7000 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
7001 &pi->stats.name, desc)
7003 /* We get these from port_stats and they may be stale by up to 1s */
7004 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
7005 "# drops due to buffer-group 0 overflows");
7006 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
7007 "# drops due to buffer-group 1 overflows");
7008 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
7009 "# drops due to buffer-group 2 overflows");
7010 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
7011 "# drops due to buffer-group 3 overflows");
7012 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
7013 "# of buffer-group 0 truncated packets");
7014 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
7015 "# of buffer-group 1 truncated packets");
7016 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
7017 "# of buffer-group 2 truncated packets");
7018 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
7019 "# of buffer-group 3 truncated packets");
7021 #undef SYSCTL_ADD_T4_PORTSTAT
7023 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
7024 CTLFLAG_RD, &pi->tx_tls_records,
7025 "# of TOE TLS records transmitted");
7026 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
7027 CTLFLAG_RD, &pi->tx_tls_octets,
7028 "# of payload octets in transmitted TOE TLS records");
7029 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
7030 CTLFLAG_RD, &pi->rx_tls_records,
7031 "# of TOE TLS records received");
7032 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
7033 CTLFLAG_RD, &pi->rx_tls_octets,
7034 "# of payload octets in received TOE TLS records");
7038 sysctl_int_array(SYSCTL_HANDLER_ARGS)
7040 int rc, *i, space = 0;
7043 sbuf_new_for_sysctl(&sb, NULL, 64, req);
7044 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
7046 sbuf_printf(&sb, " ");
7047 sbuf_printf(&sb, "%d", *i);
7050 rc = sbuf_finish(&sb);
7056 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
7061 rc = sysctl_wire_old_buffer(req, 0);
7065 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7069 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
7070 rc = sbuf_finish(sb);
7077 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
7082 rc = sysctl_wire_old_buffer(req, 0);
7086 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7090 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
7091 rc = sbuf_finish(sb);
7098 sysctl_btphy(SYSCTL_HANDLER_ARGS)
7100 struct port_info *pi = arg1;
7102 struct adapter *sc = pi->adapter;
7106 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
7109 /* XXX: magic numbers */
7110 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
7112 end_synchronized_op(sc, 0);
7118 rc = sysctl_handle_int(oidp, &v, 0, req);
7123 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
7125 struct vi_info *vi = arg1;
7128 val = vi->rsrv_noflowq;
7129 rc = sysctl_handle_int(oidp, &val, 0, req);
7130 if (rc != 0 || req->newptr == NULL)
7133 if ((val >= 1) && (vi->ntxq > 1))
7134 vi->rsrv_noflowq = 1;
7136 vi->rsrv_noflowq = 0;
7142 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
7144 struct vi_info *vi = arg1;
7145 struct adapter *sc = vi->pi->adapter;
7147 struct sge_rxq *rxq;
7152 rc = sysctl_handle_int(oidp, &idx, 0, req);
7153 if (rc != 0 || req->newptr == NULL)
7156 if (idx < 0 || idx >= SGE_NTIMERS)
7159 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7164 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
7165 for_each_rxq(vi, i, rxq) {
7166 #ifdef atomic_store_rel_8
7167 atomic_store_rel_8(&rxq->iq.intr_params, v);
7169 rxq->iq.intr_params = v;
7174 end_synchronized_op(sc, LOCK_HELD);
7179 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
7181 struct vi_info *vi = arg1;
7182 struct adapter *sc = vi->pi->adapter;
7187 rc = sysctl_handle_int(oidp, &idx, 0, req);
7188 if (rc != 0 || req->newptr == NULL)
7191 if (idx < -1 || idx >= SGE_NCOUNTERS)
7194 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7199 if (vi->flags & VI_INIT_DONE)
7200 rc = EBUSY; /* cannot be changed once the queues are created */
7204 end_synchronized_op(sc, LOCK_HELD);
7209 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
7211 struct vi_info *vi = arg1;
7212 struct adapter *sc = vi->pi->adapter;
7215 qsize = vi->qsize_rxq;
7217 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7218 if (rc != 0 || req->newptr == NULL)
7221 if (qsize < 128 || (qsize & 7))
7224 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7229 if (vi->flags & VI_INIT_DONE)
7230 rc = EBUSY; /* cannot be changed once the queues are created */
7232 vi->qsize_rxq = qsize;
7234 end_synchronized_op(sc, LOCK_HELD);
7239 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
7241 struct vi_info *vi = arg1;
7242 struct adapter *sc = vi->pi->adapter;
7245 qsize = vi->qsize_txq;
7247 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7248 if (rc != 0 || req->newptr == NULL)
7251 if (qsize < 128 || qsize > 65536)
7254 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7259 if (vi->flags & VI_INIT_DONE)
7260 rc = EBUSY; /* cannot be changed once the queues are created */
7262 vi->qsize_txq = qsize;
7264 end_synchronized_op(sc, LOCK_HELD);
7269 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
7271 struct port_info *pi = arg1;
7272 struct adapter *sc = pi->adapter;
7273 struct link_config *lc = &pi->link_cfg;
7276 if (req->newptr == NULL) {
7278 static char *bits = "\20\1RX\2TX\3AUTO";
7280 rc = sysctl_wire_old_buffer(req, 0);
7284 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7289 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
7290 (lc->requested_fc & PAUSE_AUTONEG), bits);
7292 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
7293 PAUSE_RX | PAUSE_AUTONEG), bits);
7295 rc = sbuf_finish(sb);
7301 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
7305 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7311 if (s[0] < '0' || s[0] > '9')
7312 return (EINVAL); /* not a number */
7314 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
7315 return (EINVAL); /* some other bit is set too */
7317 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7322 lc->requested_fc = n;
7323 fixup_link_config(pi);
7325 rc = apply_link_config(pi);
7326 set_current_media(pi);
7328 end_synchronized_op(sc, 0);
7335 sysctl_fec(SYSCTL_HANDLER_ARGS)
7337 struct port_info *pi = arg1;
7338 struct adapter *sc = pi->adapter;
7339 struct link_config *lc = &pi->link_cfg;
7343 if (req->newptr == NULL) {
7345 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2"
7346 "\5RSVD3\6auto\7module";
7348 rc = sysctl_wire_old_buffer(req, 0);
7352 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7357 * Display the requested_fec when the link is down -- the actual
7358 * FEC makes sense only when the link is up.
7361 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
7362 (lc->requested_fec & (FEC_AUTO | FEC_MODULE)),
7365 sbuf_printf(sb, "%b", lc->requested_fec, bits);
7367 rc = sbuf_finish(sb);
7373 snprintf(s, sizeof(s), "%d",
7374 lc->requested_fec == FEC_AUTO ? -1 :
7375 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
7377 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7381 n = strtol(&s[0], NULL, 0);
7382 if (n < 0 || n & FEC_AUTO)
7384 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
7385 return (EINVAL);/* some other bit is set too */
7387 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7392 old = lc->requested_fec;
7394 lc->requested_fec = FEC_AUTO;
7395 else if (n == 0 || n == FEC_NONE)
7396 lc->requested_fec = FEC_NONE;
7399 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
7404 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
7407 fixup_link_config(pi);
7408 if (pi->up_vis > 0) {
7409 rc = apply_link_config(pi);
7411 lc->requested_fec = old;
7412 if (rc == FW_EPROTO)
7418 end_synchronized_op(sc, 0);
7425 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
7427 struct port_info *pi = arg1;
7428 struct adapter *sc = pi->adapter;
7429 struct link_config *lc = &pi->link_cfg;
7433 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3";
7435 rc = sysctl_wire_old_buffer(req, 0);
7439 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7443 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0)
7446 if (pi->up_vis == 0) {
7448 * If all the interfaces are administratively down the firmware
7449 * does not report transceiver changes. Refresh port info here.
7450 * This is the only reason we have a synchronized op in this
7451 * function. Just PORT_LOCK would have been enough otherwise.
7453 t4_update_port_info(pi);
7457 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
7458 !fec_supported(lc->pcaps)) {
7459 sbuf_printf(sb, "n/a");
7463 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits);
7465 rc = sbuf_finish(sb);
7469 end_synchronized_op(sc, 0);
7475 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7477 struct port_info *pi = arg1;
7478 struct adapter *sc = pi->adapter;
7479 struct link_config *lc = &pi->link_cfg;
7482 if (lc->pcaps & FW_PORT_CAP32_ANEG)
7483 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7486 rc = sysctl_handle_int(oidp, &val, 0, req);
7487 if (rc != 0 || req->newptr == NULL)
7490 val = AUTONEG_DISABLE;
7492 val = AUTONEG_ENABLE;
7496 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7501 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
7505 lc->requested_aneg = val;
7506 fixup_link_config(pi);
7508 rc = apply_link_config(pi);
7509 set_current_media(pi);
7512 end_synchronized_op(sc, 0);
7517 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7519 struct adapter *sc = arg1;
7523 val = t4_read_reg64(sc, reg);
7525 return (sysctl_handle_64(oidp, &val, 0, req));
7529 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7531 struct adapter *sc = arg1;
7533 uint32_t param, val;
7535 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7538 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7539 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7540 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7541 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7542 end_synchronized_op(sc, 0);
7546 /* unknown is returned as 0 but we display -1 in that case */
7547 t = val == 0 ? -1 : val;
7549 rc = sysctl_handle_int(oidp, &t, 0, req);
7554 sysctl_vdd(SYSCTL_HANDLER_ARGS)
7556 struct adapter *sc = arg1;
7558 uint32_t param, val;
7560 if (sc->params.core_vdd == 0) {
7561 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7565 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7566 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7567 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
7568 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7569 end_synchronized_op(sc, 0);
7572 sc->params.core_vdd = val;
7575 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
7579 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
7581 struct adapter *sc = arg1;
7583 uint32_t param, val;
7585 v = sc->sensor_resets;
7586 rc = sysctl_handle_int(oidp, &v, 0, req);
7587 if (rc != 0 || req->newptr == NULL || v <= 0)
7590 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
7591 chip_id(sc) < CHELSIO_T5)
7594 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
7597 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7598 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7599 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
7601 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7602 end_synchronized_op(sc, 0);
7604 sc->sensor_resets++;
7609 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7611 struct adapter *sc = arg1;
7614 uint32_t param, val;
7616 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7619 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7620 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7621 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7622 end_synchronized_op(sc, 0);
7626 rc = sysctl_wire_old_buffer(req, 0);
7630 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7634 if (val == 0xffffffff) {
7635 /* Only debug and custom firmwares report load averages. */
7636 sbuf_printf(sb, "not available");
7638 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7639 (val >> 16) & 0xff);
7641 rc = sbuf_finish(sb);
7648 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7650 struct adapter *sc = arg1;
7653 uint16_t incr[NMTUS][NCCTRL_WIN];
7654 static const char *dec_fac[] = {
7655 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7659 rc = sysctl_wire_old_buffer(req, 0);
7663 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7667 t4_read_cong_tbl(sc, incr);
7669 for (i = 0; i < NCCTRL_WIN; ++i) {
7670 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7671 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7672 incr[5][i], incr[6][i], incr[7][i]);
7673 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7674 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7675 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7676 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7679 rc = sbuf_finish(sb);
7685 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7686 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7687 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7688 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7692 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7694 struct adapter *sc = arg1;
7696 int rc, i, n, qid = arg2;
7699 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7701 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7702 ("%s: bad qid %d\n", __func__, qid));
7704 if (qid < CIM_NUM_IBQ) {
7707 n = 4 * CIM_IBQ_SIZE;
7708 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7709 rc = t4_read_cim_ibq(sc, qid, buf, n);
7711 /* outbound queue */
7714 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7715 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7716 rc = t4_read_cim_obq(sc, qid, buf, n);
7723 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7725 rc = sysctl_wire_old_buffer(req, 0);
7729 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7735 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7736 for (i = 0, p = buf; i < n; i += 16, p += 4)
7737 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7740 rc = sbuf_finish(sb);
7748 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7752 sbuf_printf(sb, "Status Data PC%s",
7753 cfg & F_UPDBGLACAPTPCONLY ? "" :
7754 " LS0Stat LS0Addr LS0Data");
7756 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7757 if (cfg & F_UPDBGLACAPTPCONLY) {
7758 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7760 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7761 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7762 p[4] & 0xff, p[5] >> 8);
7763 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7764 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7765 p[1] & 0xf, p[2] >> 4);
7768 "\n %02x %x%07x %x%07x %08x %08x "
7770 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7771 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7778 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7782 sbuf_printf(sb, "Status Inst Data PC%s",
7783 cfg & F_UPDBGLACAPTPCONLY ? "" :
7784 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7786 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7787 if (cfg & F_UPDBGLACAPTPCONLY) {
7788 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7789 p[3] & 0xff, p[2], p[1], p[0]);
7790 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7791 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7792 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7793 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7794 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7795 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7798 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7799 "%08x %08x %08x %08x %08x %08x",
7800 (p[9] >> 16) & 0xff,
7801 p[9] & 0xffff, p[8] >> 16,
7802 p[8] & 0xffff, p[7] >> 16,
7803 p[7] & 0xffff, p[6] >> 16,
7804 p[2], p[1], p[0], p[5], p[4], p[3]);
7810 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
7815 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7819 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7820 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7825 rc = -t4_cim_read_la(sc, buf, NULL);
7828 if (chip_id(sc) < CHELSIO_T6)
7829 sbuf_cim_la4(sc, sb, buf, cfg);
7831 sbuf_cim_la6(sc, sb, buf, cfg);
7839 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7841 struct adapter *sc = arg1;
7845 rc = sysctl_wire_old_buffer(req, 0);
7848 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7852 rc = sbuf_cim_la(sc, sb, M_WAITOK);
7854 rc = sbuf_finish(sb);
7860 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose)
7865 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7867 rc = sbuf_cim_la(sc, &sb, M_NOWAIT);
7869 rc = sbuf_finish(&sb);
7871 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s",
7872 device_get_nameunit(sc->dev), sbuf_data(&sb));
7880 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7882 struct adapter *sc = arg1;
7888 rc = sysctl_wire_old_buffer(req, 0);
7892 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7896 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7899 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7902 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7903 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7907 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7908 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7909 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7910 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7911 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7912 (p[1] >> 2) | ((p[2] & 3) << 30),
7913 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7917 rc = sbuf_finish(sb);
7924 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7926 struct adapter *sc = arg1;
7932 rc = sysctl_wire_old_buffer(req, 0);
7936 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7940 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7943 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7946 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7947 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7948 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7949 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7950 p[4], p[3], p[2], p[1], p[0]);
7953 sbuf_printf(sb, "\n\nCntl ID Data");
7954 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7955 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7956 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7959 rc = sbuf_finish(sb);
7966 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7968 struct adapter *sc = arg1;
7971 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7972 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7973 uint16_t thres[CIM_NUM_IBQ];
7974 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7975 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7976 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7978 cim_num_obq = sc->chip_params->cim_num_obq;
7980 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7981 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7983 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7984 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7986 nq = CIM_NUM_IBQ + cim_num_obq;
7988 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7990 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7994 t4_read_cimq_cfg(sc, base, size, thres);
7996 rc = sysctl_wire_old_buffer(req, 0);
8000 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
8005 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
8007 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
8008 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
8009 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
8010 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
8011 G_QUEREMFLITS(p[2]) * 16);
8012 for ( ; i < nq; i++, p += 4, wr += 2)
8013 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
8014 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
8015 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
8016 G_QUEREMFLITS(p[2]) * 16);
8018 rc = sbuf_finish(sb);
8025 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
8027 struct adapter *sc = arg1;
8030 struct tp_cpl_stats stats;
8032 rc = sysctl_wire_old_buffer(req, 0);
8036 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8040 mtx_lock(&sc->reg_lock);
8041 t4_tp_get_cpl_stats(sc, &stats, 0);
8042 mtx_unlock(&sc->reg_lock);
8044 if (sc->chip_params->nchan > 2) {
8045 sbuf_printf(sb, " channel 0 channel 1"
8046 " channel 2 channel 3");
8047 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
8048 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
8049 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
8050 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
8052 sbuf_printf(sb, " channel 0 channel 1");
8053 sbuf_printf(sb, "\nCPL requests: %10u %10u",
8054 stats.req[0], stats.req[1]);
8055 sbuf_printf(sb, "\nCPL responses: %10u %10u",
8056 stats.rsp[0], stats.rsp[1]);
8059 rc = sbuf_finish(sb);
8066 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
8068 struct adapter *sc = arg1;
8071 struct tp_usm_stats stats;
8073 rc = sysctl_wire_old_buffer(req, 0);
8077 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8081 t4_get_usm_stats(sc, &stats, 1);
8083 sbuf_printf(sb, "Frames: %u\n", stats.frames);
8084 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
8085 sbuf_printf(sb, "Drops: %u", stats.drops);
8087 rc = sbuf_finish(sb);
8093 static const char * const devlog_level_strings[] = {
8094 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
8095 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
8096 [FW_DEVLOG_LEVEL_ERR] = "ERR",
8097 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
8098 [FW_DEVLOG_LEVEL_INFO] = "INFO",
8099 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
8102 static const char * const devlog_facility_strings[] = {
8103 [FW_DEVLOG_FACILITY_CORE] = "CORE",
8104 [FW_DEVLOG_FACILITY_CF] = "CF",
8105 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
8106 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
8107 [FW_DEVLOG_FACILITY_RES] = "RES",
8108 [FW_DEVLOG_FACILITY_HW] = "HW",
8109 [FW_DEVLOG_FACILITY_FLR] = "FLR",
8110 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
8111 [FW_DEVLOG_FACILITY_PHY] = "PHY",
8112 [FW_DEVLOG_FACILITY_MAC] = "MAC",
8113 [FW_DEVLOG_FACILITY_PORT] = "PORT",
8114 [FW_DEVLOG_FACILITY_VI] = "VI",
8115 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
8116 [FW_DEVLOG_FACILITY_ACL] = "ACL",
8117 [FW_DEVLOG_FACILITY_TM] = "TM",
8118 [FW_DEVLOG_FACILITY_QFC] = "QFC",
8119 [FW_DEVLOG_FACILITY_DCB] = "DCB",
8120 [FW_DEVLOG_FACILITY_ETH] = "ETH",
8121 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
8122 [FW_DEVLOG_FACILITY_RI] = "RI",
8123 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
8124 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
8125 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
8126 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
8127 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
8131 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
8133 int i, j, rc, nentries, first = 0;
8134 struct devlog_params *dparams = &sc->params.devlog;
8135 struct fw_devlog_e *buf, *e;
8136 uint64_t ftstamp = UINT64_MAX;
8138 if (dparams->addr == 0)
8141 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
8142 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
8146 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
8150 nentries = dparams->size / sizeof(struct fw_devlog_e);
8151 for (i = 0; i < nentries; i++) {
8154 if (e->timestamp == 0)
8157 e->timestamp = be64toh(e->timestamp);
8158 e->seqno = be32toh(e->seqno);
8159 for (j = 0; j < 8; j++)
8160 e->params[j] = be32toh(e->params[j]);
8162 if (e->timestamp < ftstamp) {
8163 ftstamp = e->timestamp;
8168 if (buf[first].timestamp == 0)
8169 goto done; /* nothing in the log */
8171 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
8172 "Seq#", "Tstamp", "Level", "Facility", "Message");
8177 if (e->timestamp == 0)
8180 sbuf_printf(sb, "%10d %15ju %8s %8s ",
8181 e->seqno, e->timestamp,
8182 (e->level < nitems(devlog_level_strings) ?
8183 devlog_level_strings[e->level] : "UNKNOWN"),
8184 (e->facility < nitems(devlog_facility_strings) ?
8185 devlog_facility_strings[e->facility] : "UNKNOWN"));
8186 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
8187 e->params[2], e->params[3], e->params[4],
8188 e->params[5], e->params[6], e->params[7]);
8190 if (++i == nentries)
8192 } while (i != first);
8199 sysctl_devlog(SYSCTL_HANDLER_ARGS)
8201 struct adapter *sc = arg1;
8205 rc = sysctl_wire_old_buffer(req, 0);
8208 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8212 rc = sbuf_devlog(sc, sb, M_WAITOK);
8214 rc = sbuf_finish(sb);
8220 t4_os_dump_devlog(struct adapter *sc)
8225 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
8227 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
8229 rc = sbuf_finish(&sb);
8231 log(LOG_DEBUG, "%s: device log follows.\n%s",
8232 device_get_nameunit(sc->dev), sbuf_data(&sb));
8239 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
8241 struct adapter *sc = arg1;
8244 struct tp_fcoe_stats stats[MAX_NCHAN];
8245 int i, nchan = sc->chip_params->nchan;
8247 rc = sysctl_wire_old_buffer(req, 0);
8251 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8255 for (i = 0; i < nchan; i++)
8256 t4_get_fcoe_stats(sc, i, &stats[i], 1);
8259 sbuf_printf(sb, " channel 0 channel 1"
8260 " channel 2 channel 3");
8261 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
8262 stats[0].octets_ddp, stats[1].octets_ddp,
8263 stats[2].octets_ddp, stats[3].octets_ddp);
8264 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
8265 stats[0].frames_ddp, stats[1].frames_ddp,
8266 stats[2].frames_ddp, stats[3].frames_ddp);
8267 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
8268 stats[0].frames_drop, stats[1].frames_drop,
8269 stats[2].frames_drop, stats[3].frames_drop);
8271 sbuf_printf(sb, " channel 0 channel 1");
8272 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
8273 stats[0].octets_ddp, stats[1].octets_ddp);
8274 sbuf_printf(sb, "\nframesDDP: %16u %16u",
8275 stats[0].frames_ddp, stats[1].frames_ddp);
8276 sbuf_printf(sb, "\nframesDrop: %16u %16u",
8277 stats[0].frames_drop, stats[1].frames_drop);
8280 rc = sbuf_finish(sb);
8287 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
8289 struct adapter *sc = arg1;
8292 unsigned int map, kbps, ipg, mode;
8293 unsigned int pace_tab[NTX_SCHED];
8295 rc = sysctl_wire_old_buffer(req, 0);
8299 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8303 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
8304 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
8305 t4_read_pace_tbl(sc, pace_tab);
8307 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
8308 "Class IPG (0.1 ns) Flow IPG (us)");
8310 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
8311 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
8312 sbuf_printf(sb, "\n %u %-5s %u ", i,
8313 (mode & (1 << i)) ? "flow" : "class", map & 3);
8315 sbuf_printf(sb, "%9u ", kbps);
8317 sbuf_printf(sb, " disabled ");
8320 sbuf_printf(sb, "%13u ", ipg);
8322 sbuf_printf(sb, " disabled ");
8325 sbuf_printf(sb, "%10u", pace_tab[i]);
8327 sbuf_printf(sb, " disabled");
8330 rc = sbuf_finish(sb);
8337 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
8339 struct adapter *sc = arg1;
8343 struct lb_port_stats s[2];
8344 static const char *stat_name[] = {
8345 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
8346 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
8347 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
8348 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
8349 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
8350 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
8351 "BG2FramesTrunc:", "BG3FramesTrunc:"
8354 rc = sysctl_wire_old_buffer(req, 0);
8358 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8362 memset(s, 0, sizeof(s));
8364 for (i = 0; i < sc->chip_params->nchan; i += 2) {
8365 t4_get_lb_stats(sc, i, &s[0]);
8366 t4_get_lb_stats(sc, i + 1, &s[1]);
8370 sbuf_printf(sb, "%s Loopback %u"
8371 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
8373 for (j = 0; j < nitems(stat_name); j++)
8374 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
8378 rc = sbuf_finish(sb);
8385 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
8388 struct port_info *pi = arg1;
8389 struct link_config *lc = &pi->link_cfg;
8392 rc = sysctl_wire_old_buffer(req, 0);
8395 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
8399 if (lc->link_ok || lc->link_down_rc == 255)
8400 sbuf_printf(sb, "n/a");
8402 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
8404 rc = sbuf_finish(sb);
8417 mem_desc_cmp(const void *a, const void *b)
8419 return ((const struct mem_desc *)a)->base -
8420 ((const struct mem_desc *)b)->base;
8424 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
8432 size = to - from + 1;
8436 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
8437 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
8441 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
8443 struct adapter *sc = arg1;
8446 uint32_t lo, hi, used, alloc;
8447 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
8448 static const char *region[] = {
8449 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
8450 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
8451 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
8452 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
8453 "RQUDP region:", "PBL region:", "TXPBL region:",
8454 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
8455 "On-chip queues:", "TLS keys:",
8457 struct mem_desc avail[4];
8458 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
8459 struct mem_desc *md = mem;
8461 rc = sysctl_wire_old_buffer(req, 0);
8465 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8469 for (i = 0; i < nitems(mem); i++) {
8474 /* Find and sort the populated memory ranges */
8476 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
8477 if (lo & F_EDRAM0_ENABLE) {
8478 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
8479 avail[i].base = G_EDRAM0_BASE(hi) << 20;
8480 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
8484 if (lo & F_EDRAM1_ENABLE) {
8485 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
8486 avail[i].base = G_EDRAM1_BASE(hi) << 20;
8487 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
8491 if (lo & F_EXT_MEM_ENABLE) {
8492 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
8493 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
8494 avail[i].limit = avail[i].base +
8495 (G_EXT_MEM_SIZE(hi) << 20);
8496 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
8499 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
8500 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
8501 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
8502 avail[i].limit = avail[i].base +
8503 (G_EXT_MEM1_SIZE(hi) << 20);
8507 if (!i) /* no memory available */
8509 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8511 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8512 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8513 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8514 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8515 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8516 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8517 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8518 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8519 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8521 /* the next few have explicit upper bounds */
8522 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8523 md->limit = md->base - 1 +
8524 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8525 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8528 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8529 md->limit = md->base - 1 +
8530 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8531 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8534 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8535 if (chip_id(sc) <= CHELSIO_T5)
8536 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8538 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8542 md->idx = nitems(region); /* hide it */
8546 #define ulp_region(reg) \
8547 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8548 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8550 ulp_region(RX_ISCSI);
8551 ulp_region(RX_TDDP);
8553 ulp_region(RX_STAG);
8555 ulp_region(RX_RQUDP);
8561 md->idx = nitems(region);
8564 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8565 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8568 if (sge_ctrl & F_VFIFO_ENABLE)
8569 size = G_DBVFIFO_SIZE(fifo_size);
8571 size = G_T6_DBVFIFO_SIZE(fifo_size);
8574 md->base = G_BASEADDR(t4_read_reg(sc,
8575 A_SGE_DBVFIFO_BADDR));
8576 md->limit = md->base + (size << 2) - 1;
8581 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8584 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8588 md->base = sc->vres.ocq.start;
8589 if (sc->vres.ocq.size)
8590 md->limit = md->base + sc->vres.ocq.size - 1;
8592 md->idx = nitems(region); /* hide it */
8595 md->base = sc->vres.key.start;
8596 if (sc->vres.key.size)
8597 md->limit = md->base + sc->vres.key.size - 1;
8599 md->idx = nitems(region); /* hide it */
8602 /* add any address-space holes, there can be up to 3 */
8603 for (n = 0; n < i - 1; n++)
8604 if (avail[n].limit < avail[n + 1].base)
8605 (md++)->base = avail[n].limit;
8607 (md++)->base = avail[n].limit;
8610 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8612 for (lo = 0; lo < i; lo++)
8613 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8614 avail[lo].limit - 1);
8616 sbuf_printf(sb, "\n");
8617 for (i = 0; i < n; i++) {
8618 if (mem[i].idx >= nitems(region))
8619 continue; /* skip holes */
8621 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8622 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8626 sbuf_printf(sb, "\n");
8627 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8628 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8629 mem_region_show(sb, "uP RAM:", lo, hi);
8631 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8632 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8633 mem_region_show(sb, "uP Extmem2:", lo, hi);
8635 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8636 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8638 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8639 (lo & F_PMRXNUMCHN) ? 2 : 1);
8641 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8642 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8643 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8645 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8646 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8647 sbuf_printf(sb, "%u p-structs\n",
8648 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8650 for (i = 0; i < 4; i++) {
8651 if (chip_id(sc) > CHELSIO_T5)
8652 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8654 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8656 used = G_T5_USED(lo);
8657 alloc = G_T5_ALLOC(lo);
8660 alloc = G_ALLOC(lo);
8662 /* For T6 these are MAC buffer groups */
8663 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8666 for (i = 0; i < sc->chip_params->nchan; i++) {
8667 if (chip_id(sc) > CHELSIO_T5)
8668 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8670 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8672 used = G_T5_USED(lo);
8673 alloc = G_T5_ALLOC(lo);
8676 alloc = G_ALLOC(lo);
8678 /* For T6 these are MAC buffer groups */
8680 "\nLoopback %d using %u pages out of %u allocated",
8684 rc = sbuf_finish(sb);
8691 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8695 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8699 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8701 struct adapter *sc = arg1;
8705 MPASS(chip_id(sc) <= CHELSIO_T5);
8707 rc = sysctl_wire_old_buffer(req, 0);
8711 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8716 "Idx Ethernet address Mask Vld Ports PF"
8717 " VF Replication P0 P1 P2 P3 ML");
8718 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8719 uint64_t tcamx, tcamy, mask;
8720 uint32_t cls_lo, cls_hi;
8721 uint8_t addr[ETHER_ADDR_LEN];
8723 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8724 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8727 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8728 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8729 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8730 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8731 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8732 addr[3], addr[4], addr[5], (uintmax_t)mask,
8733 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8734 G_PORTMAP(cls_hi), G_PF(cls_lo),
8735 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8737 if (cls_lo & F_REPLICATE) {
8738 struct fw_ldst_cmd ldst_cmd;
8740 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8741 ldst_cmd.op_to_addrspace =
8742 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8743 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8744 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8745 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8746 ldst_cmd.u.mps.rplc.fid_idx =
8747 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8748 V_FW_LDST_CMD_IDX(i));
8750 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8754 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8755 sizeof(ldst_cmd), &ldst_cmd);
8756 end_synchronized_op(sc, 0);
8759 sbuf_printf(sb, "%36d", rc);
8762 sbuf_printf(sb, " %08x %08x %08x %08x",
8763 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8764 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8765 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8766 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8769 sbuf_printf(sb, "%36s", "");
8771 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8772 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8773 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8777 (void) sbuf_finish(sb);
8779 rc = sbuf_finish(sb);
8786 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8788 struct adapter *sc = arg1;
8792 MPASS(chip_id(sc) > CHELSIO_T5);
8794 rc = sysctl_wire_old_buffer(req, 0);
8798 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8802 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8803 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8805 " P0 P1 P2 P3 ML\n");
8807 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8808 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8810 uint64_t tcamx, tcamy, val, mask;
8811 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8812 uint8_t addr[ETHER_ADDR_LEN];
8814 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8816 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8818 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8819 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8820 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8821 tcamy = G_DMACH(val) << 32;
8822 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8823 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8824 lookup_type = G_DATALKPTYPE(data2);
8825 port_num = G_DATAPORTNUM(data2);
8826 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8827 /* Inner header VNI */
8828 vniy = ((data2 & F_DATAVIDH2) << 23) |
8829 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8830 dip_hit = data2 & F_DATADIPHIT;
8835 vlan_vld = data2 & F_DATAVIDH2;
8836 ivlan = G_VIDL(val);
8839 ctl |= V_CTLXYBITSEL(1);
8840 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8841 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8842 tcamx = G_DMACH(val) << 32;
8843 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8844 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8845 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8846 /* Inner header VNI mask */
8847 vnix = ((data2 & F_DATAVIDH2) << 23) |
8848 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8854 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8856 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8857 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8859 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8860 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8861 "%012jx %06x %06x - - %3c"
8862 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8863 addr[1], addr[2], addr[3], addr[4], addr[5],
8864 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8865 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8866 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8867 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8869 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8870 "%012jx - - ", i, addr[0], addr[1],
8871 addr[2], addr[3], addr[4], addr[5],
8875 sbuf_printf(sb, "%4u Y ", ivlan);
8877 sbuf_printf(sb, " - N ");
8879 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8880 lookup_type ? 'I' : 'O', port_num,
8881 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8882 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8883 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8887 if (cls_lo & F_T6_REPLICATE) {
8888 struct fw_ldst_cmd ldst_cmd;
8890 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8891 ldst_cmd.op_to_addrspace =
8892 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8893 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8894 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8895 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8896 ldst_cmd.u.mps.rplc.fid_idx =
8897 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8898 V_FW_LDST_CMD_IDX(i));
8900 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8904 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8905 sizeof(ldst_cmd), &ldst_cmd);
8906 end_synchronized_op(sc, 0);
8909 sbuf_printf(sb, "%72d", rc);
8912 sbuf_printf(sb, " %08x %08x %08x %08x"
8913 " %08x %08x %08x %08x",
8914 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8915 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8916 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8917 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8918 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8919 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8920 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8921 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8924 sbuf_printf(sb, "%72s", "");
8926 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8927 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8928 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8929 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8933 (void) sbuf_finish(sb);
8935 rc = sbuf_finish(sb);
8942 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8944 struct adapter *sc = arg1;
8947 uint16_t mtus[NMTUS];
8949 rc = sysctl_wire_old_buffer(req, 0);
8953 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8957 t4_read_mtu_tbl(sc, mtus, NULL);
8959 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8960 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8961 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8962 mtus[14], mtus[15]);
8964 rc = sbuf_finish(sb);
8971 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8973 struct adapter *sc = arg1;
8976 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8977 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8978 static const char *tx_stats[MAX_PM_NSTATS] = {
8979 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8980 "Tx FIFO wait", NULL, "Tx latency"
8982 static const char *rx_stats[MAX_PM_NSTATS] = {
8983 "Read:", "Write bypass:", "Write mem:", "Flush:",
8984 "Rx FIFO wait", NULL, "Rx latency"
8987 rc = sysctl_wire_old_buffer(req, 0);
8991 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8995 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8996 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8998 sbuf_printf(sb, " Tx pcmds Tx bytes");
8999 for (i = 0; i < 4; i++) {
9000 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9004 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
9005 for (i = 0; i < 4; i++) {
9006 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9010 if (chip_id(sc) > CHELSIO_T5) {
9012 "\n Total wait Total occupancy");
9013 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9015 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9019 MPASS(i < nitems(tx_stats));
9022 "\n Reads Total wait");
9023 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9025 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9029 rc = sbuf_finish(sb);
9036 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
9038 struct adapter *sc = arg1;
9041 struct tp_rdma_stats stats;
9043 rc = sysctl_wire_old_buffer(req, 0);
9047 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9051 mtx_lock(&sc->reg_lock);
9052 t4_tp_get_rdma_stats(sc, &stats, 0);
9053 mtx_unlock(&sc->reg_lock);
9055 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
9056 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
9058 rc = sbuf_finish(sb);
9065 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
9067 struct adapter *sc = arg1;
9070 struct tp_tcp_stats v4, v6;
9072 rc = sysctl_wire_old_buffer(req, 0);
9076 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9080 mtx_lock(&sc->reg_lock);
9081 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
9082 mtx_unlock(&sc->reg_lock);
9086 sbuf_printf(sb, "OutRsts: %20u %20u\n",
9087 v4.tcp_out_rsts, v6.tcp_out_rsts);
9088 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
9089 v4.tcp_in_segs, v6.tcp_in_segs);
9090 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
9091 v4.tcp_out_segs, v6.tcp_out_segs);
9092 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
9093 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
9095 rc = sbuf_finish(sb);
9102 sysctl_tids(SYSCTL_HANDLER_ARGS)
9104 struct adapter *sc = arg1;
9107 struct tid_info *t = &sc->tids;
9109 rc = sysctl_wire_old_buffer(req, 0);
9113 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9118 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
9123 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
9124 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
9128 sbuf_printf(sb, "TID range: ");
9129 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
9132 if (chip_id(sc) <= CHELSIO_T5) {
9133 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
9134 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
9136 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
9137 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
9141 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
9142 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
9144 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
9145 sbuf_printf(sb, ", in use: %u\n",
9146 atomic_load_acq_int(&t->tids_in_use));
9150 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
9151 t->stid_base + t->nstids - 1, t->stids_in_use);
9155 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
9156 t->ftid_end, t->ftids_in_use);
9160 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
9161 t->etid_base + t->netids - 1, t->etids_in_use);
9164 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
9165 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
9166 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
9168 rc = sbuf_finish(sb);
9175 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
9177 struct adapter *sc = arg1;
9180 struct tp_err_stats stats;
9182 rc = sysctl_wire_old_buffer(req, 0);
9186 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9190 mtx_lock(&sc->reg_lock);
9191 t4_tp_get_err_stats(sc, &stats, 0);
9192 mtx_unlock(&sc->reg_lock);
9194 if (sc->chip_params->nchan > 2) {
9195 sbuf_printf(sb, " channel 0 channel 1"
9196 " channel 2 channel 3\n");
9197 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
9198 stats.mac_in_errs[0], stats.mac_in_errs[1],
9199 stats.mac_in_errs[2], stats.mac_in_errs[3]);
9200 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
9201 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
9202 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
9203 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
9204 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
9205 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
9206 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
9207 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
9208 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
9209 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
9210 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
9211 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
9212 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
9213 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
9214 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
9215 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
9216 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
9217 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
9218 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
9219 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
9220 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
9222 sbuf_printf(sb, " channel 0 channel 1\n");
9223 sbuf_printf(sb, "macInErrs: %10u %10u\n",
9224 stats.mac_in_errs[0], stats.mac_in_errs[1]);
9225 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
9226 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
9227 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
9228 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
9229 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
9230 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
9231 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
9232 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
9233 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
9234 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
9235 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
9236 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
9237 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
9238 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
9241 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
9242 stats.ofld_no_neigh, stats.ofld_cong_defer);
9244 rc = sbuf_finish(sb);
9251 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
9253 struct adapter *sc = arg1;
9254 struct tp_params *tpp = &sc->params.tp;
9258 mask = tpp->la_mask >> 16;
9259 rc = sysctl_handle_int(oidp, &mask, 0, req);
9260 if (rc != 0 || req->newptr == NULL)
9264 tpp->la_mask = mask << 16;
9265 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
9277 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
9283 uint64_t mask = (1ULL << f->width) - 1;
9284 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
9285 ((uintmax_t)v >> f->start) & mask);
9287 if (line_size + len >= 79) {
9289 sbuf_printf(sb, "\n ");
9291 sbuf_printf(sb, "%s ", buf);
9292 line_size += len + 1;
9295 sbuf_printf(sb, "\n");
9298 static const struct field_desc tp_la0[] = {
9299 { "RcfOpCodeOut", 60, 4 },
9301 { "WcfState", 52, 4 },
9302 { "RcfOpcSrcOut", 50, 2 },
9303 { "CRxError", 49, 1 },
9304 { "ERxError", 48, 1 },
9305 { "SanityFailed", 47, 1 },
9306 { "SpuriousMsg", 46, 1 },
9307 { "FlushInputMsg", 45, 1 },
9308 { "FlushInputCpl", 44, 1 },
9309 { "RssUpBit", 43, 1 },
9310 { "RssFilterHit", 42, 1 },
9312 { "InitTcb", 31, 1 },
9313 { "LineNumber", 24, 7 },
9315 { "EdataOut", 22, 1 },
9317 { "CdataOut", 20, 1 },
9318 { "EreadPdu", 19, 1 },
9319 { "CreadPdu", 18, 1 },
9320 { "TunnelPkt", 17, 1 },
9321 { "RcfPeerFin", 16, 1 },
9322 { "RcfReasonOut", 12, 4 },
9323 { "TxCchannel", 10, 2 },
9324 { "RcfTxChannel", 8, 2 },
9325 { "RxEchannel", 6, 2 },
9326 { "RcfRxChannel", 5, 1 },
9327 { "RcfDataOutSrdy", 4, 1 },
9329 { "RxOoDvld", 2, 1 },
9330 { "RxCongestion", 1, 1 },
9331 { "TxCongestion", 0, 1 },
9335 static const struct field_desc tp_la1[] = {
9336 { "CplCmdIn", 56, 8 },
9337 { "CplCmdOut", 48, 8 },
9338 { "ESynOut", 47, 1 },
9339 { "EAckOut", 46, 1 },
9340 { "EFinOut", 45, 1 },
9341 { "ERstOut", 44, 1 },
9346 { "DataIn", 39, 1 },
9347 { "DataInVld", 38, 1 },
9349 { "RxBufEmpty", 36, 1 },
9351 { "RxFbCongestion", 34, 1 },
9352 { "TxFbCongestion", 33, 1 },
9353 { "TxPktSumSrdy", 32, 1 },
9354 { "RcfUlpType", 28, 4 },
9356 { "Ebypass", 26, 1 },
9358 { "Static0", 24, 1 },
9360 { "Cbypass", 22, 1 },
9362 { "CPktOut", 20, 1 },
9363 { "RxPagePoolFull", 18, 2 },
9364 { "RxLpbkPkt", 17, 1 },
9365 { "TxLpbkPkt", 16, 1 },
9366 { "RxVfValid", 15, 1 },
9367 { "SynLearned", 14, 1 },
9368 { "SetDelEntry", 13, 1 },
9369 { "SetInvEntry", 12, 1 },
9370 { "CpcmdDvld", 11, 1 },
9371 { "CpcmdSave", 10, 1 },
9372 { "RxPstructsFull", 8, 2 },
9373 { "EpcmdDvld", 7, 1 },
9374 { "EpcmdFlush", 6, 1 },
9375 { "EpcmdTrimPrefix", 5, 1 },
9376 { "EpcmdTrimPostfix", 4, 1 },
9377 { "ERssIp4Pkt", 3, 1 },
9378 { "ERssIp6Pkt", 2, 1 },
9379 { "ERssTcpUdpPkt", 1, 1 },
9380 { "ERssFceFipPkt", 0, 1 },
9384 static const struct field_desc tp_la2[] = {
9385 { "CplCmdIn", 56, 8 },
9386 { "MpsVfVld", 55, 1 },
9393 { "DataIn", 39, 1 },
9394 { "DataInVld", 38, 1 },
9396 { "RxBufEmpty", 36, 1 },
9398 { "RxFbCongestion", 34, 1 },
9399 { "TxFbCongestion", 33, 1 },
9400 { "TxPktSumSrdy", 32, 1 },
9401 { "RcfUlpType", 28, 4 },
9403 { "Ebypass", 26, 1 },
9405 { "Static0", 24, 1 },
9407 { "Cbypass", 22, 1 },
9409 { "CPktOut", 20, 1 },
9410 { "RxPagePoolFull", 18, 2 },
9411 { "RxLpbkPkt", 17, 1 },
9412 { "TxLpbkPkt", 16, 1 },
9413 { "RxVfValid", 15, 1 },
9414 { "SynLearned", 14, 1 },
9415 { "SetDelEntry", 13, 1 },
9416 { "SetInvEntry", 12, 1 },
9417 { "CpcmdDvld", 11, 1 },
9418 { "CpcmdSave", 10, 1 },
9419 { "RxPstructsFull", 8, 2 },
9420 { "EpcmdDvld", 7, 1 },
9421 { "EpcmdFlush", 6, 1 },
9422 { "EpcmdTrimPrefix", 5, 1 },
9423 { "EpcmdTrimPostfix", 4, 1 },
9424 { "ERssIp4Pkt", 3, 1 },
9425 { "ERssIp6Pkt", 2, 1 },
9426 { "ERssTcpUdpPkt", 1, 1 },
9427 { "ERssFceFipPkt", 0, 1 },
9432 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
9435 field_desc_show(sb, *p, tp_la0);
9439 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
9443 sbuf_printf(sb, "\n");
9444 field_desc_show(sb, p[0], tp_la0);
9445 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9446 field_desc_show(sb, p[1], tp_la0);
9450 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
9454 sbuf_printf(sb, "\n");
9455 field_desc_show(sb, p[0], tp_la0);
9456 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9457 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
9461 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
9463 struct adapter *sc = arg1;
9468 void (*show_func)(struct sbuf *, uint64_t *, int);
9470 rc = sysctl_wire_old_buffer(req, 0);
9474 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9478 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
9480 t4_tp_read_la(sc, buf, NULL);
9483 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
9486 show_func = tp_la_show2;
9490 show_func = tp_la_show3;
9494 show_func = tp_la_show;
9497 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
9498 (*show_func)(sb, p, i);
9500 rc = sbuf_finish(sb);
9507 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9509 struct adapter *sc = arg1;
9512 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9514 rc = sysctl_wire_old_buffer(req, 0);
9518 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9522 t4_get_chan_txrate(sc, nrate, orate);
9524 if (sc->chip_params->nchan > 2) {
9525 sbuf_printf(sb, " channel 0 channel 1"
9526 " channel 2 channel 3\n");
9527 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9528 nrate[0], nrate[1], nrate[2], nrate[3]);
9529 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9530 orate[0], orate[1], orate[2], orate[3]);
9532 sbuf_printf(sb, " channel 0 channel 1\n");
9533 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9534 nrate[0], nrate[1]);
9535 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9536 orate[0], orate[1]);
9539 rc = sbuf_finish(sb);
9546 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9548 struct adapter *sc = arg1;
9553 rc = sysctl_wire_old_buffer(req, 0);
9557 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9561 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9564 t4_ulprx_read_la(sc, buf);
9567 sbuf_printf(sb, " Pcmd Type Message"
9569 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9570 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9571 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9574 rc = sbuf_finish(sb);
9581 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9583 struct adapter *sc = arg1;
9587 MPASS(chip_id(sc) >= CHELSIO_T5);
9589 rc = sysctl_wire_old_buffer(req, 0);
9593 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9597 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9598 if (G_STATSOURCE_T5(v) == 7) {
9601 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9603 sbuf_printf(sb, "total %d, incomplete %d",
9604 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9605 t4_read_reg(sc, A_SGE_STAT_MATCH));
9606 } else if (mode == 1) {
9607 sbuf_printf(sb, "total %d, data overflow %d",
9608 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9609 t4_read_reg(sc, A_SGE_STAT_MATCH));
9611 sbuf_printf(sb, "unknown mode %d", mode);
9614 rc = sbuf_finish(sb);
9621 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9623 struct adapter *sc = arg1;
9624 enum cpu_sets op = arg2;
9629 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9632 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9636 rc = sysctl_wire_old_buffer(req, 0);
9640 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9645 sbuf_printf(sb, "%d ", i);
9646 rc = sbuf_finish(sb);
9654 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9656 struct adapter *sc = arg1;
9657 int *old_ports, *new_ports;
9658 int i, new_count, rc;
9660 if (req->newptr == NULL && req->oldptr == NULL)
9661 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9662 sizeof(sc->tt.tls_rx_ports[0])));
9664 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9668 if (sc->tt.num_tls_rx_ports == 0) {
9670 rc = SYSCTL_OUT(req, &i, sizeof(i));
9672 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9673 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9674 if (rc == 0 && req->newptr != NULL) {
9675 new_count = req->newlen / sizeof(new_ports[0]);
9676 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9678 rc = SYSCTL_IN(req, new_ports, new_count *
9679 sizeof(new_ports[0]));
9683 /* Allow setting to a single '-1' to clear the list. */
9684 if (new_count == 1 && new_ports[0] == -1) {
9686 old_ports = sc->tt.tls_rx_ports;
9687 sc->tt.tls_rx_ports = NULL;
9688 sc->tt.num_tls_rx_ports = 0;
9690 free(old_ports, M_CXGBE);
9692 for (i = 0; i < new_count; i++) {
9693 if (new_ports[i] < 1 ||
9694 new_ports[i] > IPPORT_MAX) {
9701 old_ports = sc->tt.tls_rx_ports;
9702 sc->tt.tls_rx_ports = new_ports;
9703 sc->tt.num_tls_rx_ports = new_count;
9705 free(old_ports, M_CXGBE);
9709 free(new_ports, M_CXGBE);
9711 end_synchronized_op(sc, 0);
9716 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9718 u_int rem = val % factor;
9721 snprintf(buf, len, "%u", val / factor);
9723 while (rem % 10 == 0)
9725 snprintf(buf, len, "%u.%u", val / factor, rem);
9730 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9732 struct adapter *sc = arg1;
9735 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9737 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9741 re = G_TIMERRESOLUTION(res);
9744 /* TCP timestamp tick */
9745 re = G_TIMESTAMPRESOLUTION(res);
9749 re = G_DELAYEDACKRESOLUTION(res);
9755 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9757 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9761 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9763 struct adapter *sc = arg1;
9764 u_int res, dack_re, v;
9765 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9767 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9768 dack_re = G_DELAYEDACKRESOLUTION(res);
9769 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9771 return (sysctl_handle_int(oidp, &v, 0, req));
9775 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9777 struct adapter *sc = arg1;
9780 u_long tp_tick_us, v;
9781 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9783 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9784 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9785 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9786 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9788 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9789 tp_tick_us = (cclk_ps << tre) / 1000000;
9791 if (reg == A_TP_INIT_SRTT)
9792 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9794 v = tp_tick_us * t4_read_reg(sc, reg);
9796 return (sysctl_handle_long(oidp, &v, 0, req));
9800 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9801 * passed to this function.
9804 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9806 struct adapter *sc = arg1;
9810 MPASS(idx >= 0 && idx <= 24);
9812 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9814 return (sysctl_handle_int(oidp, &v, 0, req));
9818 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9820 struct adapter *sc = arg1;
9824 MPASS(idx >= 0 && idx < 16);
9826 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9827 shift = (idx & 3) << 3;
9828 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9830 return (sysctl_handle_int(oidp, &v, 0, req));
9834 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9836 struct vi_info *vi = arg1;
9837 struct adapter *sc = vi->pi->adapter;
9839 struct sge_ofld_rxq *ofld_rxq;
9842 idx = vi->ofld_tmr_idx;
9844 rc = sysctl_handle_int(oidp, &idx, 0, req);
9845 if (rc != 0 || req->newptr == NULL)
9848 if (idx < 0 || idx >= SGE_NTIMERS)
9851 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9856 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9857 for_each_ofld_rxq(vi, i, ofld_rxq) {
9858 #ifdef atomic_store_rel_8
9859 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9861 ofld_rxq->iq.intr_params = v;
9864 vi->ofld_tmr_idx = idx;
9866 end_synchronized_op(sc, LOCK_HELD);
9871 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9873 struct vi_info *vi = arg1;
9874 struct adapter *sc = vi->pi->adapter;
9877 idx = vi->ofld_pktc_idx;
9879 rc = sysctl_handle_int(oidp, &idx, 0, req);
9880 if (rc != 0 || req->newptr == NULL)
9883 if (idx < -1 || idx >= SGE_NCOUNTERS)
9886 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9891 if (vi->flags & VI_INIT_DONE)
9892 rc = EBUSY; /* cannot be changed once the queues are created */
9894 vi->ofld_pktc_idx = idx;
9896 end_synchronized_op(sc, LOCK_HELD);
9902 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9906 if (cntxt->cid > M_CTXTQID)
9909 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9910 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9913 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9917 if (sc->flags & FW_OK) {
9918 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9925 * Read via firmware failed or wasn't even attempted. Read directly via
9928 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9930 end_synchronized_op(sc, 0);
9935 load_fw(struct adapter *sc, struct t4_data *fw)
9940 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9945 * The firmware, with the sole exception of the memory parity error
9946 * handler, runs from memory and not flash. It is almost always safe to
9947 * install a new firmware on a running system. Just set bit 1 in
9948 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9950 if (sc->flags & FULL_INIT_DONE &&
9951 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9956 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9957 if (fw_data == NULL) {
9962 rc = copyin(fw->data, fw_data, fw->len);
9964 rc = -t4_load_fw(sc, fw_data, fw->len);
9966 free(fw_data, M_CXGBE);
9968 end_synchronized_op(sc, 0);
9973 load_cfg(struct adapter *sc, struct t4_data *cfg)
9976 uint8_t *cfg_data = NULL;
9978 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9982 if (cfg->len == 0) {
9984 rc = -t4_load_cfg(sc, NULL, 0);
9988 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9989 if (cfg_data == NULL) {
9994 rc = copyin(cfg->data, cfg_data, cfg->len);
9996 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9998 free(cfg_data, M_CXGBE);
10000 end_synchronized_op(sc, 0);
10005 load_boot(struct adapter *sc, struct t4_bootrom *br)
10008 uint8_t *br_data = NULL;
10011 if (br->len > 1024 * 1024)
10014 if (br->pf_offset == 0) {
10016 if (br->pfidx_addr > 7)
10018 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
10019 A_PCIE_PF_EXPROM_OFST)));
10020 } else if (br->pf_offset == 1) {
10022 offset = G_OFFSET(br->pfidx_addr);
10027 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
10031 if (br->len == 0) {
10033 rc = -t4_load_boot(sc, NULL, offset, 0);
10037 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
10038 if (br_data == NULL) {
10043 rc = copyin(br->data, br_data, br->len);
10045 rc = -t4_load_boot(sc, br_data, offset, br->len);
10047 free(br_data, M_CXGBE);
10049 end_synchronized_op(sc, 0);
10054 load_bootcfg(struct adapter *sc, struct t4_data *bc)
10057 uint8_t *bc_data = NULL;
10059 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
10063 if (bc->len == 0) {
10065 rc = -t4_load_bootcfg(sc, NULL, 0);
10069 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
10070 if (bc_data == NULL) {
10075 rc = copyin(bc->data, bc_data, bc->len);
10077 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
10079 free(bc_data, M_CXGBE);
10081 end_synchronized_op(sc, 0);
10086 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
10089 struct cudbg_init *cudbg;
10090 void *handle, *buf;
10092 /* buf is large, don't block if no memory is available */
10093 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
10097 handle = cudbg_alloc_handle();
10098 if (handle == NULL) {
10103 cudbg = cudbg_get_init(handle);
10105 cudbg->print = (cudbg_print_cb)printf;
10108 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
10109 __func__, dump->wr_flash, dump->len, dump->data);
10112 if (dump->wr_flash)
10113 cudbg->use_flash = 1;
10114 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
10115 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
10117 rc = cudbg_collect(handle, buf, &dump->len);
10121 rc = copyout(buf, dump->data, dump->len);
10123 cudbg_free_handle(handle);
10124 free(buf, M_CXGBE);
10129 free_offload_policy(struct t4_offload_policy *op)
10131 struct offload_rule *r;
10138 for (i = 0; i < op->nrules; i++, r++) {
10139 free(r->bpf_prog.bf_insns, M_CXGBE);
10141 free(op->rule, M_CXGBE);
10146 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
10149 struct t4_offload_policy *op, *old;
10150 struct bpf_program *bf;
10151 const struct offload_settings *s;
10152 struct offload_rule *r;
10155 if (!is_offload(sc))
10158 if (uop->nrules == 0) {
10159 /* Delete installed policies. */
10162 } else if (uop->nrules > 256) { /* arbitrary */
10166 /* Copy userspace offload policy to kernel */
10167 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
10168 op->nrules = uop->nrules;
10169 len = op->nrules * sizeof(struct offload_rule);
10170 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
10171 rc = copyin(uop->rule, op->rule, len);
10173 free(op->rule, M_CXGBE);
10179 for (i = 0; i < op->nrules; i++, r++) {
10181 /* Validate open_type */
10182 if (r->open_type != OPEN_TYPE_LISTEN &&
10183 r->open_type != OPEN_TYPE_ACTIVE &&
10184 r->open_type != OPEN_TYPE_PASSIVE &&
10185 r->open_type != OPEN_TYPE_DONTCARE) {
10188 * Rules 0 to i have malloc'd filters that need to be
10189 * freed. Rules i+1 to nrules have userspace pointers
10190 * and should be left alone.
10193 free_offload_policy(op);
10197 /* Validate settings */
10199 if ((s->offload != 0 && s->offload != 1) ||
10200 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
10201 s->sched_class < -1 ||
10202 s->sched_class >= sc->chip_params->nsched_cls) {
10208 u = bf->bf_insns; /* userspace ptr */
10209 bf->bf_insns = NULL;
10210 if (bf->bf_len == 0) {
10211 /* legal, matches everything */
10214 len = bf->bf_len * sizeof(*bf->bf_insns);
10215 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
10216 rc = copyin(u, bf->bf_insns, len);
10220 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
10226 rw_wlock(&sc->policy_lock);
10229 rw_wunlock(&sc->policy_lock);
10230 free_offload_policy(old);
10235 #define MAX_READ_BUF_SIZE (128 * 1024)
10237 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
10239 uint32_t addr, remaining, n;
10244 rc = validate_mem_range(sc, mr->addr, mr->len);
10248 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
10250 remaining = mr->len;
10251 dst = (void *)mr->data;
10253 while (remaining) {
10254 n = min(remaining, MAX_READ_BUF_SIZE);
10255 read_via_memwin(sc, 2, addr, buf, n);
10257 rc = copyout(buf, dst, n);
10266 free(buf, M_CXGBE);
10269 #undef MAX_READ_BUF_SIZE
10272 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
10276 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
10279 if (i2cd->len > sizeof(i2cd->data))
10282 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
10285 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
10286 i2cd->offset, i2cd->len, &i2cd->data[0]);
10287 end_synchronized_op(sc, 0);
10293 clear_stats(struct adapter *sc, u_int port_id)
10295 int i, v, chan_map;
10296 struct port_info *pi;
10297 struct vi_info *vi;
10298 struct sge_rxq *rxq;
10299 struct sge_txq *txq;
10300 struct sge_wrq *wrq;
10302 struct sge_ofld_rxq *ofld_rxq;
10305 if (port_id >= sc->params.nports)
10307 pi = sc->port[port_id];
10312 t4_clr_port_stats(sc, pi->tx_chan);
10313 pi->tx_parse_error = 0;
10314 pi->tnl_cong_drops = 0;
10315 mtx_lock(&sc->reg_lock);
10316 for_each_vi(pi, v, vi) {
10317 if (vi->flags & VI_INIT_DONE)
10318 t4_clr_vi_stats(sc, vi->vin);
10320 chan_map = pi->rx_e_chan_map;
10323 i = ffs(chan_map) - 1;
10324 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10325 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10326 chan_map &= ~(1 << i);
10328 mtx_unlock(&sc->reg_lock);
10331 * Since this command accepts a port, clear stats for
10332 * all VIs on this port.
10334 for_each_vi(pi, v, vi) {
10335 if (vi->flags & VI_INIT_DONE) {
10337 for_each_rxq(vi, i, rxq) {
10338 #if defined(INET) || defined(INET6)
10339 rxq->lro.lro_queued = 0;
10340 rxq->lro.lro_flushed = 0;
10343 rxq->vlan_extraction = 0;
10345 rxq->fl.cl_allocated = 0;
10346 rxq->fl.cl_recycled = 0;
10347 rxq->fl.cl_fast_recycled = 0;
10350 for_each_txq(vi, i, txq) {
10353 txq->vlan_insertion = 0;
10356 txq->txpkt_wrs = 0;
10357 txq->txpkts0_wrs = 0;
10358 txq->txpkts1_wrs = 0;
10359 txq->txpkts0_pkts = 0;
10360 txq->txpkts1_pkts = 0;
10362 txq->kern_tls_records = 0;
10363 txq->kern_tls_short = 0;
10364 txq->kern_tls_partial = 0;
10365 txq->kern_tls_full = 0;
10366 txq->kern_tls_octets = 0;
10367 txq->kern_tls_waste = 0;
10368 txq->kern_tls_options = 0;
10369 txq->kern_tls_header = 0;
10370 txq->kern_tls_fin = 0;
10371 txq->kern_tls_fin_short = 0;
10372 txq->kern_tls_cbc = 0;
10373 txq->kern_tls_gcm = 0;
10374 mp_ring_reset_stats(txq->r);
10377 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10378 for_each_ofld_txq(vi, i, wrq) {
10379 wrq->tx_wrs_direct = 0;
10380 wrq->tx_wrs_copied = 0;
10384 for_each_ofld_rxq(vi, i, ofld_rxq) {
10385 ofld_rxq->fl.cl_allocated = 0;
10386 ofld_rxq->fl.cl_recycled = 0;
10387 ofld_rxq->fl.cl_fast_recycled = 0;
10391 if (IS_MAIN_VI(vi)) {
10392 wrq = &sc->sge.ctrlq[pi->port_id];
10393 wrq->tx_wrs_direct = 0;
10394 wrq->tx_wrs_copied = 0;
10403 t4_os_find_pci_capability(struct adapter *sc, int cap)
10407 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
10411 t4_os_pci_save_state(struct adapter *sc)
10414 struct pci_devinfo *dinfo;
10417 dinfo = device_get_ivars(dev);
10419 pci_cfg_save(dev, dinfo, 0);
10424 t4_os_pci_restore_state(struct adapter *sc)
10427 struct pci_devinfo *dinfo;
10430 dinfo = device_get_ivars(dev);
10432 pci_cfg_restore(dev, dinfo);
10437 t4_os_portmod_changed(struct port_info *pi)
10439 struct adapter *sc = pi->adapter;
10440 struct vi_info *vi;
10442 static const char *mod_str[] = {
10443 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
10446 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
10447 ("%s: port_type %u", __func__, pi->port_type));
10450 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
10452 build_medialist(pi);
10453 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
10454 fixup_link_config(pi);
10455 apply_link_config(pi);
10458 end_synchronized_op(sc, LOCK_HELD);
10462 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
10463 if_printf(ifp, "transceiver unplugged.\n");
10464 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
10465 if_printf(ifp, "unknown transceiver inserted.\n");
10466 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
10467 if_printf(ifp, "unsupported transceiver inserted.\n");
10468 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
10469 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
10470 port_top_speed(pi), mod_str[pi->mod_type]);
10472 if_printf(ifp, "transceiver (type %d) inserted.\n",
10478 t4_os_link_changed(struct port_info *pi)
10480 struct vi_info *vi;
10482 struct link_config *lc;
10485 PORT_LOCK_ASSERT_OWNED(pi);
10487 for_each_vi(pi, v, vi) {
10492 lc = &pi->link_cfg;
10494 ifp->if_baudrate = IF_Mbps(lc->speed);
10495 if_link_state_change(ifp, LINK_STATE_UP);
10497 if_link_state_change(ifp, LINK_STATE_DOWN);
10503 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
10505 struct adapter *sc;
10507 sx_slock(&t4_list_lock);
10508 SLIST_FOREACH(sc, &t4_list, link) {
10510 * func should not make any assumptions about what state sc is
10511 * in - the only guarantee is that sc->sc_lock is a valid lock.
10515 sx_sunlock(&t4_list_lock);
10519 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
10523 struct adapter *sc = dev->si_drv1;
10525 rc = priv_check(td, PRIV_DRIVER);
10530 case CHELSIO_T4_GETREG: {
10531 struct t4_reg *edata = (struct t4_reg *)data;
10533 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10536 if (edata->size == 4)
10537 edata->val = t4_read_reg(sc, edata->addr);
10538 else if (edata->size == 8)
10539 edata->val = t4_read_reg64(sc, edata->addr);
10545 case CHELSIO_T4_SETREG: {
10546 struct t4_reg *edata = (struct t4_reg *)data;
10548 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10551 if (edata->size == 4) {
10552 if (edata->val & 0xffffffff00000000)
10554 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
10555 } else if (edata->size == 8)
10556 t4_write_reg64(sc, edata->addr, edata->val);
10561 case CHELSIO_T4_REGDUMP: {
10562 struct t4_regdump *regs = (struct t4_regdump *)data;
10563 int reglen = t4_get_regs_len(sc);
10566 if (regs->len < reglen) {
10567 regs->len = reglen; /* hint to the caller */
10571 regs->len = reglen;
10572 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
10573 get_regs(sc, regs, buf);
10574 rc = copyout(buf, regs->data, reglen);
10575 free(buf, M_CXGBE);
10578 case CHELSIO_T4_GET_FILTER_MODE:
10579 rc = get_filter_mode(sc, (uint32_t *)data);
10581 case CHELSIO_T4_SET_FILTER_MODE:
10582 rc = set_filter_mode(sc, *(uint32_t *)data);
10584 case CHELSIO_T4_GET_FILTER:
10585 rc = get_filter(sc, (struct t4_filter *)data);
10587 case CHELSIO_T4_SET_FILTER:
10588 rc = set_filter(sc, (struct t4_filter *)data);
10590 case CHELSIO_T4_DEL_FILTER:
10591 rc = del_filter(sc, (struct t4_filter *)data);
10593 case CHELSIO_T4_GET_SGE_CONTEXT:
10594 rc = get_sge_context(sc, (struct t4_sge_context *)data);
10596 case CHELSIO_T4_LOAD_FW:
10597 rc = load_fw(sc, (struct t4_data *)data);
10599 case CHELSIO_T4_GET_MEM:
10600 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
10602 case CHELSIO_T4_GET_I2C:
10603 rc = read_i2c(sc, (struct t4_i2c_data *)data);
10605 case CHELSIO_T4_CLEAR_STATS:
10606 rc = clear_stats(sc, *(uint32_t *)data);
10608 case CHELSIO_T4_SCHED_CLASS:
10609 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10611 case CHELSIO_T4_SCHED_QUEUE:
10612 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10614 case CHELSIO_T4_GET_TRACER:
10615 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10617 case CHELSIO_T4_SET_TRACER:
10618 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10620 case CHELSIO_T4_LOAD_CFG:
10621 rc = load_cfg(sc, (struct t4_data *)data);
10623 case CHELSIO_T4_LOAD_BOOT:
10624 rc = load_boot(sc, (struct t4_bootrom *)data);
10626 case CHELSIO_T4_LOAD_BOOTCFG:
10627 rc = load_bootcfg(sc, (struct t4_data *)data);
10629 case CHELSIO_T4_CUDBG_DUMP:
10630 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10632 case CHELSIO_T4_SET_OFLD_POLICY:
10633 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10644 toe_capability(struct vi_info *vi, int enable)
10647 struct port_info *pi = vi->pi;
10648 struct adapter *sc = pi->adapter;
10650 ASSERT_SYNCHRONIZED_OP(sc);
10652 if (!is_offload(sc))
10656 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10657 /* TOE is already enabled. */
10662 * We need the port's queues around so that we're able to send
10663 * and receive CPLs to/from the TOE even if the ifnet for this
10664 * port has never been UP'd administratively.
10666 if (!(vi->flags & VI_INIT_DONE)) {
10667 rc = vi_full_init(vi);
10671 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10672 rc = vi_full_init(&pi->vi[0]);
10677 if (isset(&sc->offload_map, pi->port_id)) {
10678 /* TOE is enabled on another VI of this port. */
10683 if (!uld_active(sc, ULD_TOM)) {
10684 rc = t4_activate_uld(sc, ULD_TOM);
10685 if (rc == EAGAIN) {
10687 "You must kldload t4_tom.ko before trying "
10688 "to enable TOE on a cxgbe interface.\n");
10692 KASSERT(sc->tom_softc != NULL,
10693 ("%s: TOM activated but softc NULL", __func__));
10694 KASSERT(uld_active(sc, ULD_TOM),
10695 ("%s: TOM activated but flag not set", __func__));
10698 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10699 if (!uld_active(sc, ULD_IWARP))
10700 (void) t4_activate_uld(sc, ULD_IWARP);
10701 if (!uld_active(sc, ULD_ISCSI))
10702 (void) t4_activate_uld(sc, ULD_ISCSI);
10705 setbit(&sc->offload_map, pi->port_id);
10709 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10712 KASSERT(uld_active(sc, ULD_TOM),
10713 ("%s: TOM never initialized?", __func__));
10714 clrbit(&sc->offload_map, pi->port_id);
10721 * Add an upper layer driver to the global list.
10724 t4_register_uld(struct uld_info *ui)
10727 struct uld_info *u;
10729 sx_xlock(&t4_uld_list_lock);
10730 SLIST_FOREACH(u, &t4_uld_list, link) {
10731 if (u->uld_id == ui->uld_id) {
10737 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10740 sx_xunlock(&t4_uld_list_lock);
10745 t4_unregister_uld(struct uld_info *ui)
10748 struct uld_info *u;
10750 sx_xlock(&t4_uld_list_lock);
10752 SLIST_FOREACH(u, &t4_uld_list, link) {
10754 if (ui->refcount > 0) {
10759 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10765 sx_xunlock(&t4_uld_list_lock);
10770 t4_activate_uld(struct adapter *sc, int id)
10773 struct uld_info *ui;
10775 ASSERT_SYNCHRONIZED_OP(sc);
10777 if (id < 0 || id > ULD_MAX)
10779 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10781 sx_slock(&t4_uld_list_lock);
10783 SLIST_FOREACH(ui, &t4_uld_list, link) {
10784 if (ui->uld_id == id) {
10785 if (!(sc->flags & FULL_INIT_DONE)) {
10786 rc = adapter_full_init(sc);
10791 rc = ui->activate(sc);
10793 setbit(&sc->active_ulds, id);
10800 sx_sunlock(&t4_uld_list_lock);
10806 t4_deactivate_uld(struct adapter *sc, int id)
10809 struct uld_info *ui;
10811 ASSERT_SYNCHRONIZED_OP(sc);
10813 if (id < 0 || id > ULD_MAX)
10817 sx_slock(&t4_uld_list_lock);
10819 SLIST_FOREACH(ui, &t4_uld_list, link) {
10820 if (ui->uld_id == id) {
10821 rc = ui->deactivate(sc);
10823 clrbit(&sc->active_ulds, id);
10830 sx_sunlock(&t4_uld_list_lock);
10836 uld_active(struct adapter *sc, int uld_id)
10839 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10841 return (isset(&sc->active_ulds, uld_id));
10846 * t = ptr to tunable.
10847 * nc = number of CPUs.
10848 * c = compiled in default for that tunable.
10851 calculate_nqueues(int *t, int nc, const int c)
10857 nq = *t < 0 ? -*t : c;
10862 * Come up with reasonable defaults for some of the tunables, provided they're
10863 * not set by the user (in which case we'll use the values as is).
10866 tweak_tunables(void)
10868 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10872 t4_ntxq = rss_getnumbuckets();
10874 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10878 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10882 t4_nrxq = rss_getnumbuckets();
10884 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10888 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10890 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10891 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10892 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10895 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10896 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10899 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
10900 if (t4_toecaps_allowed == -1)
10901 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10903 if (t4_toecaps_allowed == -1)
10904 t4_toecaps_allowed = 0;
10908 if (t4_rdmacaps_allowed == -1) {
10909 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10910 FW_CAPS_CONFIG_RDMA_RDMAC;
10913 if (t4_iscsicaps_allowed == -1) {
10914 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10915 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10916 FW_CAPS_CONFIG_ISCSI_T10DIF;
10919 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10920 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10922 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10923 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10925 if (t4_rdmacaps_allowed == -1)
10926 t4_rdmacaps_allowed = 0;
10928 if (t4_iscsicaps_allowed == -1)
10929 t4_iscsicaps_allowed = 0;
10933 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
10934 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
10935 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10936 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10939 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10940 t4_tmr_idx = TMR_IDX;
10942 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10943 t4_pktc_idx = PKTC_IDX;
10945 if (t4_qsize_txq < 128)
10946 t4_qsize_txq = 128;
10948 if (t4_qsize_rxq < 128)
10949 t4_qsize_rxq = 128;
10950 while (t4_qsize_rxq & 7)
10953 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10956 * Number of VIs to create per-port. The first VI is the "main" regular
10957 * VI for the port. The rest are additional virtual interfaces on the
10958 * same physical port. Note that the main VI does not have native
10959 * netmap support but the extra VIs do.
10961 * Limit the number of VIs per port to the number of available
10962 * MAC addresses per port.
10964 if (t4_num_vis < 1)
10966 if (t4_num_vis > nitems(vi_mac_funcs)) {
10967 t4_num_vis = nitems(vi_mac_funcs);
10968 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10971 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10972 pcie_relaxed_ordering = 1;
10973 #if defined(__i386__) || defined(__amd64__)
10974 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10975 pcie_relaxed_ordering = 0;
10982 t4_dump_tcb(struct adapter *sc, int tid)
10984 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10986 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10987 save = t4_read_reg(sc, reg);
10988 base = sc->memwin[2].mw_base;
10990 /* Dump TCB for the tid */
10991 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10992 tcb_addr += tid * TCB_SIZE;
10996 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10998 pf = V_PFNUM(sc->pf);
10999 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
11001 t4_write_reg(sc, reg, win_pos | pf);
11002 t4_read_reg(sc, reg);
11004 off = tcb_addr - win_pos;
11005 for (i = 0; i < 4; i++) {
11007 for (j = 0; j < 8; j++, off += 4)
11008 buf[j] = htonl(t4_read_reg(sc, base + off));
11010 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
11011 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
11015 t4_write_reg(sc, reg, save);
11016 t4_read_reg(sc, reg);
11020 t4_dump_devlog(struct adapter *sc)
11022 struct devlog_params *dparams = &sc->params.devlog;
11023 struct fw_devlog_e e;
11024 int i, first, j, m, nentries, rc;
11025 uint64_t ftstamp = UINT64_MAX;
11027 if (dparams->start == 0) {
11028 db_printf("devlog params not valid\n");
11032 nentries = dparams->size / sizeof(struct fw_devlog_e);
11033 m = fwmtype_to_hwmtype(dparams->memtype);
11035 /* Find the first entry. */
11037 for (i = 0; i < nentries && !db_pager_quit; i++) {
11038 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
11039 sizeof(e), (void *)&e);
11043 if (e.timestamp == 0)
11046 e.timestamp = be64toh(e.timestamp);
11047 if (e.timestamp < ftstamp) {
11048 ftstamp = e.timestamp;
11058 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
11059 sizeof(e), (void *)&e);
11063 if (e.timestamp == 0)
11066 e.timestamp = be64toh(e.timestamp);
11067 e.seqno = be32toh(e.seqno);
11068 for (j = 0; j < 8; j++)
11069 e.params[j] = be32toh(e.params[j]);
11071 db_printf("%10d %15ju %8s %8s ",
11072 e.seqno, e.timestamp,
11073 (e.level < nitems(devlog_level_strings) ?
11074 devlog_level_strings[e.level] : "UNKNOWN"),
11075 (e.facility < nitems(devlog_facility_strings) ?
11076 devlog_facility_strings[e.facility] : "UNKNOWN"));
11077 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
11078 e.params[3], e.params[4], e.params[5], e.params[6],
11081 if (++i == nentries)
11083 } while (i != first && !db_pager_quit);
11086 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
11087 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
11089 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
11096 t = db_read_token();
11098 dev = device_lookup_by_name(db_tok_string);
11103 db_printf("usage: show t4 devlog <nexus>\n");
11108 db_printf("device not found\n");
11112 t4_dump_devlog(device_get_softc(dev));
11115 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
11124 t = db_read_token();
11126 dev = device_lookup_by_name(db_tok_string);
11127 t = db_read_token();
11128 if (t == tNUMBER) {
11129 tid = db_tok_number;
11136 db_printf("usage: show t4 tcb <nexus> <tid>\n");
11141 db_printf("device not found\n");
11145 db_printf("invalid tid\n");
11149 t4_dump_tcb(device_get_softc(dev), tid);
11153 static struct sx mlu; /* mod load unload */
11154 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
11157 mod_event(module_t mod, int cmd, void *arg)
11160 static int loaded = 0;
11165 if (loaded++ == 0) {
11167 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
11168 t4_filter_rpl, CPL_COOKIE_FILTER);
11169 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
11170 do_l2t_write_rpl, CPL_COOKIE_FILTER);
11171 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
11172 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
11173 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
11174 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
11175 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
11176 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
11177 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
11178 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
11179 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
11181 sx_init(&t4_list_lock, "T4/T5 adapters");
11182 SLIST_INIT(&t4_list);
11183 callout_init(&fatal_callout, 1);
11185 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
11186 SLIST_INIT(&t4_uld_list);
11194 t4_tracer_modload();
11202 if (--loaded == 0) {
11205 sx_slock(&t4_list_lock);
11206 if (!SLIST_EMPTY(&t4_list)) {
11208 sx_sunlock(&t4_list_lock);
11212 sx_slock(&t4_uld_list_lock);
11213 if (!SLIST_EMPTY(&t4_uld_list)) {
11215 sx_sunlock(&t4_uld_list_lock);
11216 sx_sunlock(&t4_list_lock);
11221 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
11222 uprintf("%ju clusters with custom free routine "
11223 "still is use.\n", t4_sge_extfree_refs());
11224 pause("t4unload", 2 * hz);
11227 sx_sunlock(&t4_uld_list_lock);
11229 sx_sunlock(&t4_list_lock);
11231 if (t4_sge_extfree_refs() == 0) {
11232 t4_tracer_modunload();
11234 t6_ktls_modunload();
11237 t4_clip_modunload();
11240 sx_destroy(&t4_uld_list_lock);
11242 sx_destroy(&t4_list_lock);
11243 t4_sge_modunload();
11247 loaded++; /* undo earlier decrement */
11258 static devclass_t t4_devclass, t5_devclass, t6_devclass;
11259 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
11260 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
11262 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
11263 MODULE_VERSION(t4nex, 1);
11264 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
11266 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
11267 #endif /* DEV_NETMAP */
11269 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
11270 MODULE_VERSION(t5nex, 1);
11271 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
11273 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
11274 #endif /* DEV_NETMAP */
11276 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
11277 MODULE_VERSION(t6nex, 1);
11278 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
11280 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
11281 #endif /* DEV_NETMAP */
11283 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
11284 MODULE_VERSION(cxgbe, 1);
11286 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
11287 MODULE_VERSION(cxl, 1);
11289 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
11290 MODULE_VERSION(cc, 1);
11292 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
11293 MODULE_VERSION(vcxgbe, 1);
11295 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
11296 MODULE_VERSION(vcxl, 1);
11298 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
11299 MODULE_VERSION(vcc, 1);