2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
36 #include <sys/param.h>
39 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pci_private.h>
49 #include <sys/firmware.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
61 #include <net/rss_config.h>
63 #if defined(__i386__) || defined(__amd64__)
69 #include <ddb/db_lex.h>
72 #include "common/common.h"
73 #include "common/t4_msg.h"
74 #include "common/t4_regs.h"
75 #include "common/t4_regs_values.h"
78 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static int t4_ready(device_t);
86 static int t4_read_port_device(device_t, int, device_t *);
87 static device_method_t t4_methods[] = {
88 DEVMETHOD(device_probe, t4_probe),
89 DEVMETHOD(device_attach, t4_attach),
90 DEVMETHOD(device_detach, t4_detach),
92 DEVMETHOD(t4_is_main_ready, t4_ready),
93 DEVMETHOD(t4_read_port_device, t4_read_port_device),
97 static driver_t t4_driver = {
100 sizeof(struct adapter)
104 /* T4 port (cxgbe) interface */
105 static int cxgbe_probe(device_t);
106 static int cxgbe_attach(device_t);
107 static int cxgbe_detach(device_t);
108 static device_method_t cxgbe_methods[] = {
109 DEVMETHOD(device_probe, cxgbe_probe),
110 DEVMETHOD(device_attach, cxgbe_attach),
111 DEVMETHOD(device_detach, cxgbe_detach),
114 static driver_t cxgbe_driver = {
117 sizeof(struct port_info)
120 /* T4 VI (vcxgbe) interface */
121 static int vcxgbe_probe(device_t);
122 static int vcxgbe_attach(device_t);
123 static int vcxgbe_detach(device_t);
124 static device_method_t vcxgbe_methods[] = {
125 DEVMETHOD(device_probe, vcxgbe_probe),
126 DEVMETHOD(device_attach, vcxgbe_attach),
127 DEVMETHOD(device_detach, vcxgbe_detach),
130 static driver_t vcxgbe_driver = {
133 sizeof(struct vi_info)
136 static d_ioctl_t t4_ioctl;
138 static struct cdevsw t4_cdevsw = {
139 .d_version = D_VERSION,
144 /* T5 bus driver interface */
145 static int t5_probe(device_t);
146 static device_method_t t5_methods[] = {
147 DEVMETHOD(device_probe, t5_probe),
148 DEVMETHOD(device_attach, t4_attach),
149 DEVMETHOD(device_detach, t4_detach),
151 DEVMETHOD(t4_is_main_ready, t4_ready),
152 DEVMETHOD(t4_read_port_device, t4_read_port_device),
156 static driver_t t5_driver = {
159 sizeof(struct adapter)
163 /* T5 port (cxl) interface */
164 static driver_t cxl_driver = {
167 sizeof(struct port_info)
170 /* T5 VI (vcxl) interface */
171 static driver_t vcxl_driver = {
174 sizeof(struct vi_info)
177 /* ifnet + media interface */
178 static void cxgbe_init(void *);
179 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
180 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
181 static void cxgbe_qflush(struct ifnet *);
182 static int cxgbe_media_change(struct ifnet *);
183 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
185 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
188 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
189 * then ADAPTER_LOCK, then t4_uld_list_lock.
191 static struct sx t4_list_lock;
192 SLIST_HEAD(, adapter) t4_list;
194 static struct sx t4_uld_list_lock;
195 SLIST_HEAD(, uld_info) t4_uld_list;
199 * Tunables. See tweak_tunables() too.
201 * Each tunable is set to a default value here if it's known at compile-time.
202 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
203 * provide a reasonable default when the driver is loaded.
205 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
206 * T5 are under hw.cxl.
210 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
213 static int t4_ntxq10g = -1;
214 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
217 static int t4_nrxq10g = -1;
218 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
221 static int t4_ntxq1g = -1;
222 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
225 static int t4_nrxq1g = -1;
226 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
229 static int t4_ntxq_vi = -1;
230 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
233 static int t4_nrxq_vi = -1;
234 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
236 static int t4_rsrv_noflowq = 0;
237 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
240 #define NOFLDTXQ_10G 8
241 static int t4_nofldtxq10g = -1;
242 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
244 #define NOFLDRXQ_10G 2
245 static int t4_nofldrxq10g = -1;
246 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
248 #define NOFLDTXQ_1G 2
249 static int t4_nofldtxq1g = -1;
250 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
252 #define NOFLDRXQ_1G 1
253 static int t4_nofldrxq1g = -1;
254 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
256 #define NOFLDTXQ_VI 1
257 static int t4_nofldtxq_vi = -1;
258 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
260 #define NOFLDRXQ_VI 1
261 static int t4_nofldrxq_vi = -1;
262 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
267 static int t4_nnmtxq_vi = -1;
268 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
271 static int t4_nnmrxq_vi = -1;
272 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
276 * Holdoff parameters for 10G and 1G ports.
278 #define TMR_IDX_10G 1
279 static int t4_tmr_idx_10g = TMR_IDX_10G;
280 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
282 #define PKTC_IDX_10G (-1)
283 static int t4_pktc_idx_10g = PKTC_IDX_10G;
284 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
287 static int t4_tmr_idx_1g = TMR_IDX_1G;
288 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
290 #define PKTC_IDX_1G (-1)
291 static int t4_pktc_idx_1g = PKTC_IDX_1G;
292 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
295 * Size (# of entries) of each tx and rx queue.
297 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
298 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
300 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
301 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
304 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
306 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
307 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
310 * Configuration file.
312 #define DEFAULT_CF "default"
313 #define FLASH_CF "flash"
314 #define UWIRE_CF "uwire"
315 #define FPGA_CF "fpga"
316 static char t4_cfg_file[32] = DEFAULT_CF;
317 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
320 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
321 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
322 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
323 * mark or when signalled to do so, 0 to never emit PAUSE.
325 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
326 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
329 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
330 * encouraged respectively).
332 static unsigned int t4_fw_install = 1;
333 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
336 * ASIC features that will be used. Disable the ones you don't want so that the
337 * chip resources aren't wasted on features that will not be used.
339 static int t4_nbmcaps_allowed = 0;
340 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
342 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
343 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
345 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
346 FW_CAPS_CONFIG_SWITCH_EGRESS;
347 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
349 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
350 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
352 static int t4_toecaps_allowed = -1;
353 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
355 static int t4_rdmacaps_allowed = -1;
356 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
358 static int t4_tlscaps_allowed = 0;
359 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
361 static int t4_iscsicaps_allowed = -1;
362 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
364 static int t4_fcoecaps_allowed = 0;
365 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
367 static int t5_write_combine = 0;
368 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
370 static int t4_num_vis = 1;
371 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
373 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
374 static int vi_mac_funcs[] = {
377 FW_VI_FUNC_OPENISCSI,
383 struct intrs_and_queues {
384 uint16_t intr_type; /* INTx, MSI, or MSI-X */
385 uint16_t nirq; /* Total # of vectors */
386 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
387 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
388 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
389 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
390 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
391 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
392 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
393 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
394 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
395 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
396 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
398 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
399 uint16_t ntxq_vi; /* # of NIC txq's */
400 uint16_t nrxq_vi; /* # of NIC rxq's */
401 uint16_t nofldtxq_vi; /* # of TOE txq's */
402 uint16_t nofldrxq_vi; /* # of TOE rxq's */
403 uint16_t nnmtxq_vi; /* # of netmap txq's */
404 uint16_t nnmrxq_vi; /* # of netmap rxq's */
407 struct filter_entry {
408 uint32_t valid:1; /* filter allocated and valid */
409 uint32_t locked:1; /* filter is administratively locked */
410 uint32_t pending:1; /* filter action is pending firmware reply */
411 uint32_t smtidx:8; /* Source MAC Table index for smac */
412 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
414 struct t4_filter_specification fs;
417 static int map_bars_0_and_4(struct adapter *);
418 static int map_bar_2(struct adapter *);
419 static void setup_memwin(struct adapter *);
420 static void position_memwin(struct adapter *, int, uint32_t);
421 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
422 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
424 static inline int write_via_memwin(struct adapter *, int, uint32_t,
425 const uint32_t *, int);
426 static int validate_mem_range(struct adapter *, uint32_t, int);
427 static int fwmtype_to_hwmtype(int);
428 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
430 static int fixup_devlog_params(struct adapter *);
431 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
432 struct intrs_and_queues *);
433 static int prep_firmware(struct adapter *);
434 static int partition_resources(struct adapter *, const struct firmware *,
436 static int get_params__pre_init(struct adapter *);
437 static int get_params__post_init(struct adapter *);
438 static int set_params__post_init(struct adapter *);
439 static void t4_set_desc(struct adapter *);
440 static void build_medialist(struct port_info *, struct ifmedia *);
441 static int cxgbe_init_synchronized(struct vi_info *);
442 static int cxgbe_uninit_synchronized(struct vi_info *);
443 static int setup_intr_handlers(struct adapter *);
444 static void quiesce_txq(struct adapter *, struct sge_txq *);
445 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
446 static void quiesce_iq(struct adapter *, struct sge_iq *);
447 static void quiesce_fl(struct adapter *, struct sge_fl *);
448 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
449 driver_intr_t *, void *, char *);
450 static int t4_free_irq(struct adapter *, struct irq *);
451 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
452 static void vi_refresh_stats(struct adapter *, struct vi_info *);
453 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
454 static void cxgbe_tick(void *);
455 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
456 static void t4_sysctls(struct adapter *);
457 static void cxgbe_sysctls(struct port_info *);
458 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
459 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
460 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
461 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
462 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
463 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
464 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
465 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
466 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
467 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
468 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
470 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
471 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
472 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
473 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
474 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
475 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
476 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
477 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
478 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
479 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
480 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
481 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
482 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
483 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
484 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
485 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
486 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
487 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
488 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
489 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
490 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
491 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
492 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
493 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
494 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
495 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
496 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
497 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
498 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
501 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
502 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
503 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
505 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
506 static uint32_t mode_to_fconf(uint32_t);
507 static uint32_t mode_to_iconf(uint32_t);
508 static int check_fspec_against_fconf_iconf(struct adapter *,
509 struct t4_filter_specification *);
510 static int get_filter_mode(struct adapter *, uint32_t *);
511 static int set_filter_mode(struct adapter *, uint32_t);
512 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
513 static int get_filter(struct adapter *, struct t4_filter *);
514 static int set_filter(struct adapter *, struct t4_filter *);
515 static int del_filter(struct adapter *, struct t4_filter *);
516 static void clear_filter(struct filter_entry *);
517 static int set_filter_wr(struct adapter *, int);
518 static int del_filter_wr(struct adapter *, int);
519 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
521 static int get_sge_context(struct adapter *, struct t4_sge_context *);
522 static int load_fw(struct adapter *, struct t4_data *);
523 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
524 static int read_i2c(struct adapter *, struct t4_i2c_data *);
525 static int set_sched_class(struct adapter *, struct t4_sched_params *);
526 static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
528 static int toe_capability(struct vi_info *, int);
530 static int mod_event(module_t, int, void *);
531 static int notify_siblings(device_t, int);
537 {0xa000, "Chelsio Terminator 4 FPGA"},
538 {0x4400, "Chelsio T440-dbg"},
539 {0x4401, "Chelsio T420-CR"},
540 {0x4402, "Chelsio T422-CR"},
541 {0x4403, "Chelsio T440-CR"},
542 {0x4404, "Chelsio T420-BCH"},
543 {0x4405, "Chelsio T440-BCH"},
544 {0x4406, "Chelsio T440-CH"},
545 {0x4407, "Chelsio T420-SO"},
546 {0x4408, "Chelsio T420-CX"},
547 {0x4409, "Chelsio T420-BT"},
548 {0x440a, "Chelsio T404-BT"},
549 {0x440e, "Chelsio T440-LP-CR"},
551 {0xb000, "Chelsio Terminator 5 FPGA"},
552 {0x5400, "Chelsio T580-dbg"},
553 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
554 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
555 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
556 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
557 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
558 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
559 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
560 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
561 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
562 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
563 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
564 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
565 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
567 {0x5404, "Chelsio T520-BCH"},
568 {0x5405, "Chelsio T540-BCH"},
569 {0x5406, "Chelsio T540-CH"},
570 {0x5408, "Chelsio T520-CX"},
571 {0x540b, "Chelsio B520-SR"},
572 {0x540c, "Chelsio B504-BT"},
573 {0x540f, "Chelsio Amsterdam"},
574 {0x5413, "Chelsio T580-CHR"},
580 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
581 * exactly the same for both rxq and ofld_rxq.
583 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
584 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
586 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
589 t4_probe(device_t dev)
592 uint16_t v = pci_get_vendor(dev);
593 uint16_t d = pci_get_device(dev);
594 uint8_t f = pci_get_function(dev);
596 if (v != PCI_VENDOR_ID_CHELSIO)
599 /* Attach only to PF0 of the FPGA */
600 if (d == 0xa000 && f != 0)
603 for (i = 0; i < nitems(t4_pciids); i++) {
604 if (d == t4_pciids[i].device) {
605 device_set_desc(dev, t4_pciids[i].desc);
606 return (BUS_PROBE_DEFAULT);
614 t5_probe(device_t dev)
617 uint16_t v = pci_get_vendor(dev);
618 uint16_t d = pci_get_device(dev);
619 uint8_t f = pci_get_function(dev);
621 if (v != PCI_VENDOR_ID_CHELSIO)
624 /* Attach only to PF0 of the FPGA */
625 if (d == 0xb000 && f != 0)
628 for (i = 0; i < nitems(t5_pciids); i++) {
629 if (d == t5_pciids[i].device) {
630 device_set_desc(dev, t5_pciids[i].desc);
631 return (BUS_PROBE_DEFAULT);
639 t5_attribute_workaround(device_t dev)
645 * The T5 chips do not properly echo the No Snoop and Relaxed
646 * Ordering attributes when replying to a TLP from a Root
647 * Port. As a workaround, find the parent Root Port and
648 * disable No Snoop and Relaxed Ordering. Note that this
649 * affects all devices under this root port.
651 root_port = pci_find_pcie_root_port(dev);
652 if (root_port == NULL) {
653 device_printf(dev, "Unable to find parent root port\n");
657 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
658 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
659 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
661 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
662 device_get_nameunit(root_port));
666 t4_attach(device_t dev)
669 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
670 struct make_dev_args mda;
671 struct intrs_and_queues iaq;
675 int ofld_rqidx, ofld_tqidx;
678 int nm_rqidx, nm_tqidx;
682 sc = device_get_softc(dev);
684 TUNABLE_INT_FETCH("hw.cxgbe.debug_flags", &sc->debug_flags);
686 if ((pci_get_device(dev) & 0xff00) == 0x5400)
687 t5_attribute_workaround(dev);
688 pci_enable_busmaster(dev);
689 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
692 pci_set_max_read_req(dev, 4096);
693 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
694 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
695 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
697 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
700 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
701 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
703 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
704 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
705 device_get_nameunit(dev));
707 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
708 device_get_nameunit(dev));
709 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
710 sx_xlock(&t4_list_lock);
711 SLIST_INSERT_HEAD(&t4_list, sc, link);
712 sx_xunlock(&t4_list_lock);
714 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
715 TAILQ_INIT(&sc->sfl);
716 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
718 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
720 rc = map_bars_0_and_4(sc);
722 goto done; /* error message displayed already */
725 * This is the real PF# to which we're attaching. Works from within PCI
726 * passthrough environments too, where pci_get_function() could return a
727 * different PF# depending on the passthrough configuration. We need to
728 * use the real PF# in all our communication with the firmware.
730 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
733 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
735 /* Prepare the adapter for operation. */
736 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
737 rc = -t4_prep_adapter(sc, buf);
740 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
745 * Do this really early, with the memory windows set up even before the
746 * character device. The userland tool's register i/o and mem read
747 * will work even in "recovery mode".
750 if (t4_init_devlog_params(sc, 0) == 0)
751 fixup_devlog_params(sc);
752 make_dev_args_init(&mda);
753 mda.mda_devsw = &t4_cdevsw;
754 mda.mda_uid = UID_ROOT;
755 mda.mda_gid = GID_WHEEL;
757 mda.mda_si_drv1 = sc;
758 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
760 device_printf(dev, "failed to create nexus char device: %d.\n",
763 /* Go no further if recovery mode has been requested. */
764 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
765 device_printf(dev, "recovery mode.\n");
769 #if defined(__i386__)
770 if ((cpu_feature & CPUID_CX8) == 0) {
771 device_printf(dev, "64 bit atomics not available.\n");
777 /* Prepare the firmware for operation */
778 rc = prep_firmware(sc);
780 goto done; /* error message displayed already */
782 rc = get_params__post_init(sc);
784 goto done; /* error message displayed already */
786 rc = set_params__post_init(sc);
788 goto done; /* error message displayed already */
792 goto done; /* error message displayed already */
794 rc = t4_create_dma_tag(sc);
796 goto done; /* error message displayed already */
799 * Number of VIs to create per-port. The first VI is the "main" regular
800 * VI for the port. The rest are additional virtual interfaces on the
801 * same physical port. Note that the main VI does not have native
802 * netmap support but the extra VIs do.
804 * Limit the number of VIs per port to the number of available
805 * MAC addresses per port.
808 num_vis = t4_num_vis;
811 if (num_vis > nitems(vi_mac_funcs)) {
812 num_vis = nitems(vi_mac_funcs);
813 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
817 * First pass over all the ports - allocate VIs and initialize some
818 * basic parameters like mac address, port type, etc. We also figure
819 * out whether a port is 10G or 1G and use that information when
820 * calculating how many interrupts to attempt to allocate.
823 for_each_port(sc, i) {
824 struct port_info *pi;
826 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
829 /* These must be set before t4_port_init */
833 * XXX: vi[0] is special so we can't delay this allocation until
834 * pi->nvi's final value is known.
836 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
840 * Allocate the "main" VI and initialize parameters
843 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
845 device_printf(dev, "unable to initialize port %d: %d\n",
847 free(pi->vi, M_CXGBE);
853 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
854 pi->link_cfg.requested_fc |= t4_pause_settings;
855 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
856 pi->link_cfg.fc |= t4_pause_settings;
858 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
860 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
861 free(pi->vi, M_CXGBE);
867 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
868 device_get_nameunit(dev), i);
869 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
870 sc->chan_map[pi->tx_chan] = i;
872 pi->tc = malloc(sizeof(struct tx_sched_class) *
873 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
875 if (is_10G_port(pi) || is_40G_port(pi)) {
883 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
884 if (pi->dev == NULL) {
886 "failed to add device for port %d.\n", i);
890 pi->vi[0].dev = pi->dev;
891 device_set_softc(pi->dev, pi);
895 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
897 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
899 goto done; /* error message displayed already */
900 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
903 sc->intr_type = iaq.intr_type;
904 sc->intr_count = iaq.nirq;
907 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
908 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
910 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
911 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
913 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
914 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
915 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
917 if (is_offload(sc)) {
918 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
919 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
921 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
923 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
926 s->neq += s->nofldtxq + s->nofldrxq;
927 s->niq += s->nofldrxq;
929 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
930 M_CXGBE, M_ZERO | M_WAITOK);
931 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
932 M_CXGBE, M_ZERO | M_WAITOK);
937 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
938 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
940 s->neq += s->nnmtxq + s->nnmrxq;
943 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
944 M_CXGBE, M_ZERO | M_WAITOK);
945 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
946 M_CXGBE, M_ZERO | M_WAITOK);
949 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
951 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
953 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
955 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
957 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
960 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
963 t4_init_l2t(sc, M_WAITOK);
966 * Second pass over the ports. This time we know the number of rx and
967 * tx queues that each port should get.
971 ofld_rqidx = ofld_tqidx = 0;
974 nm_rqidx = nm_tqidx = 0;
976 for_each_port(sc, i) {
977 struct port_info *pi = sc->port[i];
984 for_each_vi(pi, j, vi) {
986 vi->qsize_rxq = t4_qsize_rxq;
987 vi->qsize_txq = t4_qsize_txq;
989 vi->first_rxq = rqidx;
990 vi->first_txq = tqidx;
991 if (is_10G_port(pi) || is_40G_port(pi)) {
992 vi->tmr_idx = t4_tmr_idx_10g;
993 vi->pktc_idx = t4_pktc_idx_10g;
994 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
995 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
996 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
998 vi->tmr_idx = t4_tmr_idx_1g;
999 vi->pktc_idx = t4_pktc_idx_1g;
1000 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1001 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1002 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1007 if (j == 0 && vi->ntxq > 1)
1008 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1010 vi->rsrv_noflowq = 0;
1013 vi->first_ofld_rxq = ofld_rqidx;
1014 vi->first_ofld_txq = ofld_tqidx;
1015 if (is_10G_port(pi) || is_40G_port(pi)) {
1016 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1017 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1019 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1022 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1023 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1025 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1028 ofld_rqidx += vi->nofldrxq;
1029 ofld_tqidx += vi->nofldtxq;
1033 vi->first_nm_rxq = nm_rqidx;
1034 vi->first_nm_txq = nm_tqidx;
1035 vi->nnmrxq = iaq.nnmrxq_vi;
1036 vi->nnmtxq = iaq.nnmtxq_vi;
1037 nm_rqidx += vi->nnmrxq;
1038 nm_tqidx += vi->nnmtxq;
1044 rc = setup_intr_handlers(sc);
1047 "failed to setup interrupt handlers: %d\n", rc);
1051 rc = bus_generic_attach(dev);
1054 "failed to attach all child ports: %d\n", rc);
1059 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1060 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1061 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1062 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1063 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1067 notify_siblings(dev, 0);
1070 if (rc != 0 && sc->cdev) {
1071 /* cdev was created and so cxgbetool works; recover that way. */
1073 "error during attach, adapter is now in recovery mode.\n");
1086 t4_ready(device_t dev)
1090 sc = device_get_softc(dev);
1091 if (sc->flags & FW_OK)
1097 t4_read_port_device(device_t dev, int port, device_t *child)
1100 struct port_info *pi;
1102 sc = device_get_softc(dev);
1103 if (port < 0 || port >= MAX_NPORTS)
1105 pi = sc->port[port];
1106 if (pi == NULL || pi->dev == NULL)
1113 notify_siblings(device_t dev, int detaching)
1119 for (i = 0; i < PCI_FUNCMAX; i++) {
1120 if (i == pci_get_function(dev))
1122 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1123 pci_get_slot(dev), i);
1124 if (sibling == NULL || !device_is_attached(sibling))
1127 error = T4_DETACH_CHILD(sibling);
1129 (void)T4_ATTACH_CHILD(sibling);
1140 t4_detach(device_t dev)
1143 struct port_info *pi;
1146 sc = device_get_softc(dev);
1148 rc = notify_siblings(dev, 1);
1151 "failed to detach sibling devices: %d\n", rc);
1155 if (sc->flags & FULL_INIT_DONE)
1156 t4_intr_disable(sc);
1159 destroy_dev(sc->cdev);
1163 rc = bus_generic_detach(dev);
1166 "failed to detach child devices: %d\n", rc);
1170 for (i = 0; i < sc->intr_count; i++)
1171 t4_free_irq(sc, &sc->irq[i]);
1173 for (i = 0; i < MAX_NPORTS; i++) {
1176 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1178 device_delete_child(dev, pi->dev);
1180 mtx_destroy(&pi->pi_lock);
1181 free(pi->vi, M_CXGBE);
1182 free(pi->tc, M_CXGBE);
1187 if (sc->flags & FULL_INIT_DONE)
1188 adapter_full_uninit(sc);
1190 if (sc->flags & FW_OK)
1191 t4_fw_bye(sc, sc->mbox);
1193 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1194 pci_release_msi(dev);
1197 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1201 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1205 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1209 t4_free_l2t(sc->l2t);
1212 free(sc->sge.ofld_rxq, M_CXGBE);
1213 free(sc->sge.ofld_txq, M_CXGBE);
1216 free(sc->sge.nm_rxq, M_CXGBE);
1217 free(sc->sge.nm_txq, M_CXGBE);
1219 free(sc->irq, M_CXGBE);
1220 free(sc->sge.rxq, M_CXGBE);
1221 free(sc->sge.txq, M_CXGBE);
1222 free(sc->sge.ctrlq, M_CXGBE);
1223 free(sc->sge.iqmap, M_CXGBE);
1224 free(sc->sge.eqmap, M_CXGBE);
1225 free(sc->tids.ftid_tab, M_CXGBE);
1226 t4_destroy_dma_tag(sc);
1227 if (mtx_initialized(&sc->sc_lock)) {
1228 sx_xlock(&t4_list_lock);
1229 SLIST_REMOVE(&t4_list, sc, adapter, link);
1230 sx_xunlock(&t4_list_lock);
1231 mtx_destroy(&sc->sc_lock);
1234 callout_drain(&sc->sfl_callout);
1235 if (mtx_initialized(&sc->tids.ftid_lock))
1236 mtx_destroy(&sc->tids.ftid_lock);
1237 if (mtx_initialized(&sc->sfl_lock))
1238 mtx_destroy(&sc->sfl_lock);
1239 if (mtx_initialized(&sc->ifp_lock))
1240 mtx_destroy(&sc->ifp_lock);
1241 if (mtx_initialized(&sc->reg_lock))
1242 mtx_destroy(&sc->reg_lock);
1244 for (i = 0; i < NUM_MEMWIN; i++) {
1245 struct memwin *mw = &sc->memwin[i];
1247 if (rw_initialized(&mw->mw_lock))
1248 rw_destroy(&mw->mw_lock);
1251 bzero(sc, sizeof(*sc));
1257 cxgbe_probe(device_t dev)
1260 struct port_info *pi = device_get_softc(dev);
1262 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1263 device_set_desc_copy(dev, buf);
1265 return (BUS_PROBE_DEFAULT);
1268 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1269 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1270 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1271 #define T4_CAP_ENABLE (T4_CAP)
1274 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1279 vi->xact_addr_filt = -1;
1280 callout_init(&vi->tick, 1);
1282 /* Allocate an ifnet and set it up */
1283 ifp = if_alloc(IFT_ETHER);
1285 device_printf(dev, "Cannot allocate ifnet\n");
1291 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1294 ifp->if_init = cxgbe_init;
1295 ifp->if_ioctl = cxgbe_ioctl;
1296 ifp->if_transmit = cxgbe_transmit;
1297 ifp->if_qflush = cxgbe_qflush;
1298 ifp->if_get_counter = cxgbe_get_counter;
1300 ifp->if_capabilities = T4_CAP;
1302 if (vi->nofldrxq != 0)
1303 ifp->if_capabilities |= IFCAP_TOE;
1305 ifp->if_capenable = T4_CAP_ENABLE;
1306 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1307 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1309 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1310 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1311 ifp->if_hw_tsomaxsegsize = 65536;
1313 /* Initialize ifmedia for this VI */
1314 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1315 cxgbe_media_status);
1316 build_medialist(vi->pi, &vi->media);
1318 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1319 EVENTHANDLER_PRI_ANY);
1321 ether_ifattach(ifp, vi->hw_addr);
1323 if (vi->nnmrxq != 0)
1324 cxgbe_nm_attach(vi);
1326 sb = sbuf_new_auto();
1327 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1329 if (ifp->if_capabilities & IFCAP_TOE)
1330 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1331 vi->nofldtxq, vi->nofldrxq);
1334 if (ifp->if_capabilities & IFCAP_NETMAP)
1335 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1336 vi->nnmtxq, vi->nnmrxq);
1339 device_printf(dev, "%s\n", sbuf_data(sb));
1348 cxgbe_attach(device_t dev)
1350 struct port_info *pi = device_get_softc(dev);
1354 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1356 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1360 for_each_vi(pi, i, vi) {
1363 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1364 "vcxgbe" : "vcxl", -1);
1365 if (vi->dev == NULL) {
1366 device_printf(dev, "failed to add VI %d\n", i);
1369 device_set_softc(vi->dev, vi);
1374 bus_generic_attach(dev);
1380 cxgbe_vi_detach(struct vi_info *vi)
1382 struct ifnet *ifp = vi->ifp;
1384 ether_ifdetach(ifp);
1387 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1389 /* Let detach proceed even if these fail. */
1391 if (ifp->if_capabilities & IFCAP_NETMAP)
1392 cxgbe_nm_detach(vi);
1394 cxgbe_uninit_synchronized(vi);
1395 callout_drain(&vi->tick);
1398 ifmedia_removeall(&vi->media);
1404 cxgbe_detach(device_t dev)
1406 struct port_info *pi = device_get_softc(dev);
1407 struct adapter *sc = pi->adapter;
1410 /* Detach the extra VIs first. */
1411 rc = bus_generic_detach(dev);
1414 device_delete_children(dev);
1416 doom_vi(sc, &pi->vi[0]);
1418 if (pi->flags & HAS_TRACEQ) {
1419 sc->traceq = -1; /* cloner should not create ifnet */
1420 t4_tracer_port_detach(sc);
1423 cxgbe_vi_detach(&pi->vi[0]);
1424 callout_drain(&pi->tick);
1426 end_synchronized_op(sc, 0);
1432 cxgbe_init(void *arg)
1434 struct vi_info *vi = arg;
1435 struct adapter *sc = vi->pi->adapter;
1437 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1439 cxgbe_init_synchronized(vi);
1440 end_synchronized_op(sc, 0);
1444 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1446 int rc = 0, mtu, flags, can_sleep;
1447 struct vi_info *vi = ifp->if_softc;
1448 struct adapter *sc = vi->pi->adapter;
1449 struct ifreq *ifr = (struct ifreq *)data;
1455 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1458 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1462 if (vi->flags & VI_INIT_DONE) {
1463 t4_update_fl_bufsize(ifp);
1464 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1465 rc = update_mac_settings(ifp, XGMAC_MTU);
1467 end_synchronized_op(sc, 0);
1473 rc = begin_synchronized_op(sc, vi,
1474 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1478 if (ifp->if_flags & IFF_UP) {
1479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1480 flags = vi->if_flags;
1481 if ((ifp->if_flags ^ flags) &
1482 (IFF_PROMISC | IFF_ALLMULTI)) {
1483 if (can_sleep == 1) {
1484 end_synchronized_op(sc, 0);
1488 rc = update_mac_settings(ifp,
1489 XGMAC_PROMISC | XGMAC_ALLMULTI);
1492 if (can_sleep == 0) {
1493 end_synchronized_op(sc, LOCK_HELD);
1497 rc = cxgbe_init_synchronized(vi);
1499 vi->if_flags = ifp->if_flags;
1500 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1501 if (can_sleep == 0) {
1502 end_synchronized_op(sc, LOCK_HELD);
1506 rc = cxgbe_uninit_synchronized(vi);
1508 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1512 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1513 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1516 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1517 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1518 end_synchronized_op(sc, LOCK_HELD);
1522 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1526 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1527 if (mask & IFCAP_TXCSUM) {
1528 ifp->if_capenable ^= IFCAP_TXCSUM;
1529 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1531 if (IFCAP_TSO4 & ifp->if_capenable &&
1532 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1533 ifp->if_capenable &= ~IFCAP_TSO4;
1535 "tso4 disabled due to -txcsum.\n");
1538 if (mask & IFCAP_TXCSUM_IPV6) {
1539 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1540 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1542 if (IFCAP_TSO6 & ifp->if_capenable &&
1543 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1544 ifp->if_capenable &= ~IFCAP_TSO6;
1546 "tso6 disabled due to -txcsum6.\n");
1549 if (mask & IFCAP_RXCSUM)
1550 ifp->if_capenable ^= IFCAP_RXCSUM;
1551 if (mask & IFCAP_RXCSUM_IPV6)
1552 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1555 * Note that we leave CSUM_TSO alone (it is always set). The
1556 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1557 * sending a TSO request our way, so it's sufficient to toggle
1560 if (mask & IFCAP_TSO4) {
1561 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1562 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1563 if_printf(ifp, "enable txcsum first.\n");
1567 ifp->if_capenable ^= IFCAP_TSO4;
1569 if (mask & IFCAP_TSO6) {
1570 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1571 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1572 if_printf(ifp, "enable txcsum6 first.\n");
1576 ifp->if_capenable ^= IFCAP_TSO6;
1578 if (mask & IFCAP_LRO) {
1579 #if defined(INET) || defined(INET6)
1581 struct sge_rxq *rxq;
1583 ifp->if_capenable ^= IFCAP_LRO;
1584 for_each_rxq(vi, i, rxq) {
1585 if (ifp->if_capenable & IFCAP_LRO)
1586 rxq->iq.flags |= IQ_LRO_ENABLED;
1588 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1593 if (mask & IFCAP_TOE) {
1594 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1596 rc = toe_capability(vi, enable);
1600 ifp->if_capenable ^= mask;
1603 if (mask & IFCAP_VLAN_HWTAGGING) {
1604 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1605 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1606 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1608 if (mask & IFCAP_VLAN_MTU) {
1609 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1611 /* Need to find out how to disable auto-mtu-inflation */
1613 if (mask & IFCAP_VLAN_HWTSO)
1614 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1615 if (mask & IFCAP_VLAN_HWCSUM)
1616 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1618 #ifdef VLAN_CAPABILITIES
1619 VLAN_CAPABILITIES(ifp);
1622 end_synchronized_op(sc, 0);
1627 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1631 struct ifi2creq i2c;
1633 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1636 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1640 if (i2c.len > sizeof(i2c.data)) {
1644 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1647 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1648 i2c.offset, i2c.len, &i2c.data[0]);
1649 end_synchronized_op(sc, 0);
1651 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1656 rc = ether_ioctl(ifp, cmd, data);
1663 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1665 struct vi_info *vi = ifp->if_softc;
1666 struct port_info *pi = vi->pi;
1667 struct adapter *sc = pi->adapter;
1668 struct sge_txq *txq;
1673 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1675 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1681 if (__predict_false(rc != 0)) {
1682 MPASS(m == NULL); /* was freed already */
1683 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1688 txq = &sc->sge.txq[vi->first_txq];
1689 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1690 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1694 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1695 if (__predict_false(rc != 0))
1702 cxgbe_qflush(struct ifnet *ifp)
1704 struct vi_info *vi = ifp->if_softc;
1705 struct sge_txq *txq;
1708 /* queues do not exist if !VI_INIT_DONE. */
1709 if (vi->flags & VI_INIT_DONE) {
1710 for_each_txq(vi, i, txq) {
1712 txq->eq.flags &= ~EQ_ENABLED;
1714 while (!mp_ring_is_idle(txq->r)) {
1715 mp_ring_check_drainage(txq->r, 0);
1724 vi_get_counter(struct ifnet *ifp, ift_counter c)
1726 struct vi_info *vi = ifp->if_softc;
1727 struct fw_vi_stats_vf *s = &vi->stats;
1729 vi_refresh_stats(vi->pi->adapter, vi);
1732 case IFCOUNTER_IPACKETS:
1733 return (s->rx_bcast_frames + s->rx_mcast_frames +
1734 s->rx_ucast_frames);
1735 case IFCOUNTER_IERRORS:
1736 return (s->rx_err_frames);
1737 case IFCOUNTER_OPACKETS:
1738 return (s->tx_bcast_frames + s->tx_mcast_frames +
1739 s->tx_ucast_frames + s->tx_offload_frames);
1740 case IFCOUNTER_OERRORS:
1741 return (s->tx_drop_frames);
1742 case IFCOUNTER_IBYTES:
1743 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
1745 case IFCOUNTER_OBYTES:
1746 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
1747 s->tx_ucast_bytes + s->tx_offload_bytes);
1748 case IFCOUNTER_IMCASTS:
1749 return (s->rx_mcast_frames);
1750 case IFCOUNTER_OMCASTS:
1751 return (s->tx_mcast_frames);
1752 case IFCOUNTER_OQDROPS: {
1756 if (vi->flags & VI_INIT_DONE) {
1758 struct sge_txq *txq;
1760 for_each_txq(vi, i, txq)
1761 drops += counter_u64_fetch(txq->r->drops);
1769 return (if_get_counter_default(ifp, c));
1774 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
1776 struct vi_info *vi = ifp->if_softc;
1777 struct port_info *pi = vi->pi;
1778 struct adapter *sc = pi->adapter;
1779 struct port_stats *s = &pi->stats;
1782 return (vi_get_counter(ifp, c));
1784 cxgbe_refresh_stats(sc, pi);
1787 case IFCOUNTER_IPACKETS:
1788 return (s->rx_frames);
1790 case IFCOUNTER_IERRORS:
1791 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
1792 s->rx_fcs_err + s->rx_len_err);
1794 case IFCOUNTER_OPACKETS:
1795 return (s->tx_frames);
1797 case IFCOUNTER_OERRORS:
1798 return (s->tx_error_frames);
1800 case IFCOUNTER_IBYTES:
1801 return (s->rx_octets);
1803 case IFCOUNTER_OBYTES:
1804 return (s->tx_octets);
1806 case IFCOUNTER_IMCASTS:
1807 return (s->rx_mcast_frames);
1809 case IFCOUNTER_OMCASTS:
1810 return (s->tx_mcast_frames);
1812 case IFCOUNTER_IQDROPS:
1813 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
1814 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
1815 s->rx_trunc3 + pi->tnl_cong_drops);
1817 case IFCOUNTER_OQDROPS: {
1821 if (vi->flags & VI_INIT_DONE) {
1823 struct sge_txq *txq;
1825 for_each_txq(vi, i, txq)
1826 drops += counter_u64_fetch(txq->r->drops);
1834 return (if_get_counter_default(ifp, c));
1839 cxgbe_media_change(struct ifnet *ifp)
1841 struct vi_info *vi = ifp->if_softc;
1843 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1845 return (EOPNOTSUPP);
1849 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1851 struct vi_info *vi = ifp->if_softc;
1852 struct port_info *pi = vi->pi;
1853 struct ifmedia_entry *cur;
1854 int speed = pi->link_cfg.speed;
1856 cur = vi->media.ifm_cur;
1858 ifmr->ifm_status = IFM_AVALID;
1859 if (!pi->link_cfg.link_ok)
1862 ifmr->ifm_status |= IFM_ACTIVE;
1864 /* active and current will differ iff current media is autoselect. */
1865 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1868 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1870 ifmr->ifm_active |= IFM_10G_T;
1871 else if (speed == 1000)
1872 ifmr->ifm_active |= IFM_1000_T;
1873 else if (speed == 100)
1874 ifmr->ifm_active |= IFM_100_TX;
1875 else if (speed == 10)
1876 ifmr->ifm_active |= IFM_10_T;
1878 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1883 vcxgbe_probe(device_t dev)
1886 struct vi_info *vi = device_get_softc(dev);
1888 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1890 device_set_desc_copy(dev, buf);
1892 return (BUS_PROBE_DEFAULT);
1896 vcxgbe_attach(device_t dev)
1899 struct port_info *pi;
1901 int func, index, rc;
1904 vi = device_get_softc(dev);
1908 index = vi - pi->vi;
1909 KASSERT(index < nitems(vi_mac_funcs),
1910 ("%s: VI %s doesn't have a MAC func", __func__,
1911 device_get_nameunit(dev)));
1912 func = vi_mac_funcs[index];
1913 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1914 vi->hw_addr, &vi->rss_size, func, 0);
1916 device_printf(dev, "Failed to allocate virtual interface "
1917 "for port %d: %d\n", pi->port_id, -rc);
1922 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1923 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1924 V_FW_PARAMS_PARAM_YZ(vi->viid);
1925 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1927 vi->rss_base = 0xffff;
1929 /* MPASS((val >> 16) == rss_size); */
1930 vi->rss_base = val & 0xffff;
1933 rc = cxgbe_vi_attach(dev, vi);
1935 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1942 vcxgbe_detach(device_t dev)
1947 vi = device_get_softc(dev);
1948 sc = vi->pi->adapter;
1952 cxgbe_vi_detach(vi);
1953 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1955 end_synchronized_op(sc, 0);
1961 t4_fatal_err(struct adapter *sc)
1963 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1964 t4_intr_disable(sc);
1965 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1966 device_get_nameunit(sc->dev));
1970 map_bars_0_and_4(struct adapter *sc)
1972 sc->regs_rid = PCIR_BAR(0);
1973 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1974 &sc->regs_rid, RF_ACTIVE);
1975 if (sc->regs_res == NULL) {
1976 device_printf(sc->dev, "cannot map registers.\n");
1979 sc->bt = rman_get_bustag(sc->regs_res);
1980 sc->bh = rman_get_bushandle(sc->regs_res);
1981 sc->mmio_len = rman_get_size(sc->regs_res);
1982 setbit(&sc->doorbells, DOORBELL_KDB);
1984 sc->msix_rid = PCIR_BAR(4);
1985 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1986 &sc->msix_rid, RF_ACTIVE);
1987 if (sc->msix_res == NULL) {
1988 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1996 map_bar_2(struct adapter *sc)
2000 * T4: only iWARP driver uses the userspace doorbells. There is no need
2001 * to map it if RDMA is disabled.
2003 if (is_t4(sc) && sc->rdmacaps == 0)
2006 sc->udbs_rid = PCIR_BAR(2);
2007 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2008 &sc->udbs_rid, RF_ACTIVE);
2009 if (sc->udbs_res == NULL) {
2010 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2013 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2016 setbit(&sc->doorbells, DOORBELL_UDB);
2017 #if defined(__i386__) || defined(__amd64__)
2018 if (t5_write_combine) {
2022 * Enable write combining on BAR2. This is the
2023 * userspace doorbell BAR and is split into 128B
2024 * (UDBS_SEG_SIZE) doorbell regions, each associated
2025 * with an egress queue. The first 64B has the doorbell
2026 * and the second 64B can be used to submit a tx work
2027 * request with an implicit doorbell.
2030 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2031 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2033 clrbit(&sc->doorbells, DOORBELL_UDB);
2034 setbit(&sc->doorbells, DOORBELL_WCWR);
2035 setbit(&sc->doorbells, DOORBELL_UDBWC);
2037 device_printf(sc->dev,
2038 "couldn't enable write combining: %d\n",
2042 t4_write_reg(sc, A_SGE_STAT_CFG,
2043 V_STATSOURCE_T5(7) | V_STATMODE(0));
2051 struct memwin_init {
2056 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2057 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2058 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2059 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2062 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2063 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2064 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2065 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2069 setup_memwin(struct adapter *sc)
2071 const struct memwin_init *mw_init;
2078 * Read low 32b of bar0 indirectly via the hardware backdoor
2079 * mechanism. Works from within PCI passthrough environments
2080 * too, where rman_get_start() can return a different value. We
2081 * need to program the T4 memory window decoders with the actual
2082 * addresses that will be coming across the PCIe link.
2084 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2085 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2087 mw_init = &t4_memwin[0];
2089 /* T5+ use the relative offset inside the PCIe BAR */
2092 mw_init = &t5_memwin[0];
2095 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2096 rw_init(&mw->mw_lock, "memory window access");
2097 mw->mw_base = mw_init->base;
2098 mw->mw_aperture = mw_init->aperture;
2101 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2102 (mw->mw_base + bar0) | V_BIR(0) |
2103 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2104 rw_wlock(&mw->mw_lock);
2105 position_memwin(sc, i, 0);
2106 rw_wunlock(&mw->mw_lock);
2110 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2114 * Positions the memory window at the given address in the card's address space.
2115 * There are some alignment requirements and the actual position may be at an
2116 * address prior to the requested address. mw->mw_curpos always has the actual
2117 * position of the window.
2120 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2126 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2127 mw = &sc->memwin[idx];
2128 rw_assert(&mw->mw_lock, RA_WLOCKED);
2132 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2134 pf = V_PFNUM(sc->pf);
2135 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2137 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2138 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2139 t4_read_reg(sc, reg); /* flush */
2143 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2149 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2151 /* Memory can only be accessed in naturally aligned 4 byte units */
2152 if (addr & 3 || len & 3 || len <= 0)
2155 mw = &sc->memwin[idx];
2157 rw_rlock(&mw->mw_lock);
2158 mw_end = mw->mw_curpos + mw->mw_aperture;
2159 if (addr >= mw_end || addr < mw->mw_curpos) {
2160 /* Will need to reposition the window */
2161 if (!rw_try_upgrade(&mw->mw_lock)) {
2162 rw_runlock(&mw->mw_lock);
2163 rw_wlock(&mw->mw_lock);
2165 rw_assert(&mw->mw_lock, RA_WLOCKED);
2166 position_memwin(sc, idx, addr);
2167 rw_downgrade(&mw->mw_lock);
2168 mw_end = mw->mw_curpos + mw->mw_aperture;
2170 rw_assert(&mw->mw_lock, RA_RLOCKED);
2171 while (addr < mw_end && len > 0) {
2173 v = t4_read_reg(sc, mw->mw_base + addr -
2175 *val++ = le32toh(v);
2178 t4_write_reg(sc, mw->mw_base + addr -
2179 mw->mw_curpos, htole32(v));
2184 rw_runlock(&mw->mw_lock);
2191 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2195 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2199 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2200 const uint32_t *val, int len)
2203 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2207 t4_range_cmp(const void *a, const void *b)
2209 return ((const struct t4_range *)a)->start -
2210 ((const struct t4_range *)b)->start;
2214 * Verify that the memory range specified by the addr/len pair is valid within
2215 * the card's address space.
2218 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2220 struct t4_range mem_ranges[4], *r, *next;
2221 uint32_t em, addr_len;
2222 int i, n, remaining;
2224 /* Memory can only be accessed in naturally aligned 4 byte units */
2225 if (addr & 3 || len & 3 || len <= 0)
2228 /* Enabled memories */
2229 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2233 bzero(r, sizeof(mem_ranges));
2234 if (em & F_EDRAM0_ENABLE) {
2235 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2236 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2238 r->start = G_EDRAM0_BASE(addr_len) << 20;
2239 if (addr >= r->start &&
2240 addr + len <= r->start + r->size)
2246 if (em & F_EDRAM1_ENABLE) {
2247 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2248 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2250 r->start = G_EDRAM1_BASE(addr_len) << 20;
2251 if (addr >= r->start &&
2252 addr + len <= r->start + r->size)
2258 if (em & F_EXT_MEM_ENABLE) {
2259 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2260 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2262 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2263 if (addr >= r->start &&
2264 addr + len <= r->start + r->size)
2270 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2271 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2272 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2274 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2275 if (addr >= r->start &&
2276 addr + len <= r->start + r->size)
2282 MPASS(n <= nitems(mem_ranges));
2285 /* Sort and merge the ranges. */
2286 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2288 /* Start from index 0 and examine the next n - 1 entries. */
2290 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2292 MPASS(r->size > 0); /* r is a valid entry. */
2294 MPASS(next->size > 0); /* and so is the next one. */
2296 while (r->start + r->size >= next->start) {
2297 /* Merge the next one into the current entry. */
2298 r->size = max(r->start + r->size,
2299 next->start + next->size) - r->start;
2300 n--; /* One fewer entry in total. */
2301 if (--remaining == 0)
2302 goto done; /* short circuit */
2305 if (next != r + 1) {
2307 * Some entries were merged into r and next
2308 * points to the first valid entry that couldn't
2311 MPASS(next->size > 0); /* must be valid */
2312 memcpy(r + 1, next, remaining * sizeof(*r));
2315 * This so that the foo->size assertion in the
2316 * next iteration of the loop do the right
2317 * thing for entries that were pulled up and are
2320 MPASS(n < nitems(mem_ranges));
2321 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2322 sizeof(struct t4_range));
2327 /* Done merging the ranges. */
2330 for (i = 0; i < n; i++, r++) {
2331 if (addr >= r->start &&
2332 addr + len <= r->start + r->size)
2341 fwmtype_to_hwmtype(int mtype)
2345 case FW_MEMTYPE_EDC0:
2347 case FW_MEMTYPE_EDC1:
2349 case FW_MEMTYPE_EXTMEM:
2351 case FW_MEMTYPE_EXTMEM1:
2354 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2359 * Verify that the memory range specified by the memtype/offset/len pair is
2360 * valid and lies entirely within the memtype specified. The global address of
2361 * the start of the range is returned in addr.
2364 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2367 uint32_t em, addr_len, maddr;
2369 /* Memory can only be accessed in naturally aligned 4 byte units */
2370 if (off & 3 || len & 3 || len == 0)
2373 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2374 switch (fwmtype_to_hwmtype(mtype)) {
2376 if (!(em & F_EDRAM0_ENABLE))
2378 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2379 maddr = G_EDRAM0_BASE(addr_len) << 20;
2382 if (!(em & F_EDRAM1_ENABLE))
2384 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2385 maddr = G_EDRAM1_BASE(addr_len) << 20;
2388 if (!(em & F_EXT_MEM_ENABLE))
2390 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2391 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2394 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2396 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2397 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2403 *addr = maddr + off; /* global address */
2404 return (validate_mem_range(sc, *addr, len));
2408 fixup_devlog_params(struct adapter *sc)
2410 struct devlog_params *dparams = &sc->params.devlog;
2413 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2414 dparams->size, &dparams->addr);
2420 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2421 struct intrs_and_queues *iaq)
2423 int rc, itype, navail, nrxq10g, nrxq1g, n;
2424 int nofldrxq10g = 0, nofldrxq1g = 0;
2426 bzero(iaq, sizeof(*iaq));
2428 iaq->ntxq10g = t4_ntxq10g;
2429 iaq->ntxq1g = t4_ntxq1g;
2430 iaq->ntxq_vi = t4_ntxq_vi;
2431 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2432 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2433 iaq->nrxq_vi = t4_nrxq_vi;
2434 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2436 if (is_offload(sc)) {
2437 iaq->nofldtxq10g = t4_nofldtxq10g;
2438 iaq->nofldtxq1g = t4_nofldtxq1g;
2439 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2440 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2441 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2442 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2446 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2447 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2450 for (itype = INTR_MSIX; itype; itype >>= 1) {
2452 if ((itype & t4_intr_types) == 0)
2453 continue; /* not allowed */
2455 if (itype == INTR_MSIX)
2456 navail = pci_msix_count(sc->dev);
2457 else if (itype == INTR_MSI)
2458 navail = pci_msi_count(sc->dev);
2465 iaq->intr_type = itype;
2466 iaq->intr_flags_10g = 0;
2467 iaq->intr_flags_1g = 0;
2470 * Best option: an interrupt vector for errors, one for the
2471 * firmware event queue, and one for every rxq (NIC and TOE) of
2472 * every VI. The VIs that support netmap use the same
2473 * interrupts for the NIC rx queues and the netmap rx queues
2474 * because only one set of queues is active at a time.
2476 iaq->nirq = T4_EXTRA_INTR;
2477 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2478 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2479 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2480 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2481 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2482 if (iaq->nirq <= navail &&
2483 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2484 iaq->intr_flags_10g = INTR_ALL;
2485 iaq->intr_flags_1g = INTR_ALL;
2489 /* Disable the VIs (and netmap) if there aren't enough intrs */
2491 device_printf(sc->dev, "virtual interfaces disabled "
2492 "because num_vis=%u with current settings "
2493 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2494 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2495 "nnmrxq_vi=%u) would need %u interrupts but "
2496 "only %u are available.\n", num_vis, nrxq10g,
2497 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2498 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2501 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2502 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2503 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2508 * Second best option: a vector for errors, one for the firmware
2509 * event queue, and vectors for either all the NIC rx queues or
2510 * all the TOE rx queues. The queues that don't get vectors
2511 * will forward their interrupts to those that do.
2513 iaq->nirq = T4_EXTRA_INTR;
2514 if (nrxq10g >= nofldrxq10g) {
2515 iaq->intr_flags_10g = INTR_RXQ;
2516 iaq->nirq += n10g * nrxq10g;
2518 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2519 iaq->nirq += n10g * nofldrxq10g;
2521 if (nrxq1g >= nofldrxq1g) {
2522 iaq->intr_flags_1g = INTR_RXQ;
2523 iaq->nirq += n1g * nrxq1g;
2525 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2526 iaq->nirq += n1g * nofldrxq1g;
2528 if (iaq->nirq <= navail &&
2529 (itype != INTR_MSI || powerof2(iaq->nirq)))
2533 * Next best option: an interrupt vector for errors, one for the
2534 * firmware event queue, and at least one per main-VI. At this
2535 * point we know we'll have to downsize nrxq and/or nofldrxq to
2536 * fit what's available to us.
2538 iaq->nirq = T4_EXTRA_INTR;
2539 iaq->nirq += n10g + n1g;
2540 if (iaq->nirq <= navail) {
2541 int leftover = navail - iaq->nirq;
2544 int target = max(nrxq10g, nofldrxq10g);
2546 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2547 INTR_RXQ : INTR_OFLD_RXQ;
2550 while (n < target && leftover >= n10g) {
2555 iaq->nrxq10g = min(n, nrxq10g);
2557 iaq->nofldrxq10g = min(n, nofldrxq10g);
2562 int target = max(nrxq1g, nofldrxq1g);
2564 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2565 INTR_RXQ : INTR_OFLD_RXQ;
2568 while (n < target && leftover >= n1g) {
2573 iaq->nrxq1g = min(n, nrxq1g);
2575 iaq->nofldrxq1g = min(n, nofldrxq1g);
2579 if (itype != INTR_MSI || powerof2(iaq->nirq))
2584 * Least desirable option: one interrupt vector for everything.
2586 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2587 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2590 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2595 if (itype == INTR_MSIX)
2596 rc = pci_alloc_msix(sc->dev, &navail);
2597 else if (itype == INTR_MSI)
2598 rc = pci_alloc_msi(sc->dev, &navail);
2601 if (navail == iaq->nirq)
2605 * Didn't get the number requested. Use whatever number
2606 * the kernel is willing to allocate (it's in navail).
2608 device_printf(sc->dev, "fewer vectors than requested, "
2609 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2610 itype, iaq->nirq, navail);
2611 pci_release_msi(sc->dev);
2615 device_printf(sc->dev,
2616 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2617 itype, rc, iaq->nirq, navail);
2620 device_printf(sc->dev,
2621 "failed to find a usable interrupt type. "
2622 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2623 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2628 #define FW_VERSION(chip) ( \
2629 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2630 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2631 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2632 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2633 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2639 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2643 .kld_name = "t4fw_cfg",
2644 .fw_mod_name = "t4fw",
2646 .chip = FW_HDR_CHIP_T4,
2647 .fw_ver = htobe32_const(FW_VERSION(T4)),
2648 .intfver_nic = FW_INTFVER(T4, NIC),
2649 .intfver_vnic = FW_INTFVER(T4, VNIC),
2650 .intfver_ofld = FW_INTFVER(T4, OFLD),
2651 .intfver_ri = FW_INTFVER(T4, RI),
2652 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2653 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2654 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2655 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2659 .kld_name = "t5fw_cfg",
2660 .fw_mod_name = "t5fw",
2662 .chip = FW_HDR_CHIP_T5,
2663 .fw_ver = htobe32_const(FW_VERSION(T5)),
2664 .intfver_nic = FW_INTFVER(T5, NIC),
2665 .intfver_vnic = FW_INTFVER(T5, VNIC),
2666 .intfver_ofld = FW_INTFVER(T5, OFLD),
2667 .intfver_ri = FW_INTFVER(T5, RI),
2668 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2669 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2670 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2671 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2676 static struct fw_info *
2677 find_fw_info(int chip)
2681 for (i = 0; i < nitems(fw_info); i++) {
2682 if (fw_info[i].chip == chip)
2683 return (&fw_info[i]);
2689 * Is the given firmware API compatible with the one the driver was compiled
2693 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2696 /* short circuit if it's the exact same firmware version */
2697 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2701 * XXX: Is this too conservative? Perhaps I should limit this to the
2702 * features that are supported in the driver.
2704 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2705 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2706 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2707 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2715 * The firmware in the KLD is usable, but should it be installed? This routine
2716 * explains itself in detail if it indicates the KLD firmware should be
2720 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2724 if (!card_fw_usable) {
2725 reason = "incompatible or unusable";
2730 reason = "older than the version bundled with this driver";
2734 if (t4_fw_install == 2 && k != c) {
2735 reason = "different than the version bundled with this driver";
2742 if (t4_fw_install == 0) {
2743 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2744 "but the driver is prohibited from installing a different "
2745 "firmware on the card.\n",
2746 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2747 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2752 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2753 "installing firmware %u.%u.%u.%u on card.\n",
2754 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2755 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2756 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2757 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2762 * Establish contact with the firmware and determine if we are the master driver
2763 * or not, and whether we are responsible for chip initialization.
2766 prep_firmware(struct adapter *sc)
2768 const struct firmware *fw = NULL, *default_cfg;
2769 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2770 enum dev_state state;
2771 struct fw_info *fw_info;
2772 struct fw_hdr *card_fw; /* fw on the card */
2773 const struct fw_hdr *kld_fw; /* fw in the KLD */
2774 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2777 /* Contact firmware. */
2778 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2779 if (rc < 0 || state == DEV_STATE_ERR) {
2781 device_printf(sc->dev,
2782 "failed to connect to the firmware: %d, %d.\n", rc, state);
2787 sc->flags |= MASTER_PF;
2788 else if (state == DEV_STATE_UNINIT) {
2790 * We didn't get to be the master so we definitely won't be
2791 * configuring the chip. It's a bug if someone else hasn't
2792 * configured it already.
2794 device_printf(sc->dev, "couldn't be master(%d), "
2795 "device not already initialized either(%d).\n", rc, state);
2799 /* This is the firmware whose headers the driver was compiled against */
2800 fw_info = find_fw_info(chip_id(sc));
2801 if (fw_info == NULL) {
2802 device_printf(sc->dev,
2803 "unable to look up firmware information for chip %d.\n",
2807 drv_fw = &fw_info->fw_hdr;
2810 * The firmware KLD contains many modules. The KLD name is also the
2811 * name of the module that contains the default config file.
2813 default_cfg = firmware_get(fw_info->kld_name);
2815 /* Read the header of the firmware on the card */
2816 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2817 rc = -t4_read_flash(sc, FLASH_FW_START,
2818 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2820 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2822 device_printf(sc->dev,
2823 "Unable to read card's firmware header: %d\n", rc);
2827 /* This is the firmware in the KLD */
2828 fw = firmware_get(fw_info->fw_mod_name);
2830 kld_fw = (const void *)fw->data;
2831 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2837 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2838 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2840 * Common case: the firmware on the card is an exact match and
2841 * the KLD is an exact match too, or the KLD is
2842 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2843 * here -- use cxgbetool loadfw if you want to reinstall the
2844 * same firmware as the one on the card.
2846 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2847 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2848 be32toh(card_fw->fw_ver))) {
2850 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2852 device_printf(sc->dev,
2853 "failed to install firmware: %d\n", rc);
2857 /* Installed successfully, update the cached header too. */
2858 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2860 need_fw_reset = 0; /* already reset as part of load_fw */
2863 if (!card_fw_usable) {
2866 d = ntohl(drv_fw->fw_ver);
2867 c = ntohl(card_fw->fw_ver);
2868 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2870 device_printf(sc->dev, "Cannot find a usable firmware: "
2871 "fw_install %d, chip state %d, "
2872 "driver compiled with %d.%d.%d.%d, "
2873 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2874 t4_fw_install, state,
2875 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2876 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2877 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2878 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2879 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2880 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2886 if (need_fw_reset &&
2887 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2888 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2889 if (rc != ETIMEDOUT && rc != EIO)
2890 t4_fw_bye(sc, sc->mbox);
2895 rc = get_params__pre_init(sc);
2897 goto done; /* error message displayed already */
2899 /* Partition adapter resources as specified in the config file. */
2900 if (state == DEV_STATE_UNINIT) {
2902 KASSERT(sc->flags & MASTER_PF,
2903 ("%s: trying to change chip settings when not master.",
2906 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2908 goto done; /* error message displayed already */
2910 t4_tweak_chip_settings(sc);
2912 /* get basic stuff going */
2913 rc = -t4_fw_initialize(sc, sc->mbox);
2915 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2919 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2924 free(card_fw, M_CXGBE);
2926 firmware_put(fw, FIRMWARE_UNLOAD);
2927 if (default_cfg != NULL)
2928 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2933 #define FW_PARAM_DEV(param) \
2934 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2935 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2936 #define FW_PARAM_PFVF(param) \
2937 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2938 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2941 * Partition chip resources for use between various PFs, VFs, etc.
2944 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2945 const char *name_prefix)
2947 const struct firmware *cfg = NULL;
2949 struct fw_caps_config_cmd caps;
2950 uint32_t mtype, moff, finicsum, cfcsum;
2953 * Figure out what configuration file to use. Pick the default config
2954 * file for the card if the user hasn't specified one explicitly.
2956 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2957 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2958 /* Card specific overrides go here. */
2959 if (pci_get_device(sc->dev) == 0x440a)
2960 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2962 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2966 * We need to load another module if the profile is anything except
2967 * "default" or "flash".
2969 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2970 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2973 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2974 cfg = firmware_get(s);
2976 if (default_cfg != NULL) {
2977 device_printf(sc->dev,
2978 "unable to load module \"%s\" for "
2979 "configuration profile \"%s\", will use "
2980 "the default config file instead.\n",
2982 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2985 device_printf(sc->dev,
2986 "unable to load module \"%s\" for "
2987 "configuration profile \"%s\", will use "
2988 "the config file on the card's flash "
2989 "instead.\n", s, sc->cfg_file);
2990 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2996 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2997 default_cfg == NULL) {
2998 device_printf(sc->dev,
2999 "default config file not available, will use the config "
3000 "file on the card's flash instead.\n");
3001 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3004 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3006 const uint32_t *cfdata;
3007 uint32_t param, val, addr;
3009 KASSERT(cfg != NULL || default_cfg != NULL,
3010 ("%s: no config to upload", __func__));
3013 * Ask the firmware where it wants us to upload the config file.
3015 param = FW_PARAM_DEV(CF);
3016 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3018 /* No support for config file? Shouldn't happen. */
3019 device_printf(sc->dev,
3020 "failed to query config file location: %d.\n", rc);
3023 mtype = G_FW_PARAMS_PARAM_Y(val);
3024 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3027 * XXX: sheer laziness. We deliberately added 4 bytes of
3028 * useless stuffing/comments at the end of the config file so
3029 * it's ok to simply throw away the last remaining bytes when
3030 * the config file is not an exact multiple of 4. This also
3031 * helps with the validate_mt_off_len check.
3034 cflen = cfg->datasize & ~3;
3037 cflen = default_cfg->datasize & ~3;
3038 cfdata = default_cfg->data;
3041 if (cflen > FLASH_CFG_MAX_SIZE) {
3042 device_printf(sc->dev,
3043 "config file too long (%d, max allowed is %d). "
3044 "Will try to use the config on the card, if any.\n",
3045 cflen, FLASH_CFG_MAX_SIZE);
3046 goto use_config_on_flash;
3049 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3051 device_printf(sc->dev,
3052 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3053 "Will try to use the config on the card, if any.\n",
3054 __func__, mtype, moff, cflen, rc);
3055 goto use_config_on_flash;
3057 write_via_memwin(sc, 2, addr, cfdata, cflen);
3059 use_config_on_flash:
3060 mtype = FW_MEMTYPE_FLASH;
3061 moff = t4_flash_cfg_addr(sc);
3064 bzero(&caps, sizeof(caps));
3065 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3066 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3067 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3068 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3069 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3070 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3072 device_printf(sc->dev,
3073 "failed to pre-process config file: %d "
3074 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3078 finicsum = be32toh(caps.finicsum);
3079 cfcsum = be32toh(caps.cfcsum);
3080 if (finicsum != cfcsum) {
3081 device_printf(sc->dev,
3082 "WARNING: config file checksum mismatch: %08x %08x\n",
3085 sc->cfcsum = cfcsum;
3087 #define LIMIT_CAPS(x) do { \
3088 caps.x &= htobe16(t4_##x##_allowed); \
3092 * Let the firmware know what features will (not) be used so it can tune
3093 * things accordingly.
3095 LIMIT_CAPS(nbmcaps);
3096 LIMIT_CAPS(linkcaps);
3097 LIMIT_CAPS(switchcaps);
3098 LIMIT_CAPS(niccaps);
3099 LIMIT_CAPS(toecaps);
3100 LIMIT_CAPS(rdmacaps);
3101 LIMIT_CAPS(tlscaps);
3102 LIMIT_CAPS(iscsicaps);
3103 LIMIT_CAPS(fcoecaps);
3106 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3107 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3108 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3109 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3111 device_printf(sc->dev,
3112 "failed to process config file: %d.\n", rc);
3116 firmware_put(cfg, FIRMWARE_UNLOAD);
3121 * Retrieve parameters that are needed (or nice to have) very early.
3124 get_params__pre_init(struct adapter *sc)
3127 uint32_t param[2], val[2];
3129 t4_get_version_info(sc);
3131 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3132 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3133 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3134 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3135 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3137 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3138 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3139 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3140 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3141 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3143 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3144 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3145 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3146 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3147 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3149 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3150 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3151 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3152 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3153 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3155 param[0] = FW_PARAM_DEV(PORTVEC);
3156 param[1] = FW_PARAM_DEV(CCLK);
3157 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3159 device_printf(sc->dev,
3160 "failed to query parameters (pre_init): %d.\n", rc);
3164 sc->params.portvec = val[0];
3165 sc->params.nports = bitcount32(val[0]);
3166 sc->params.vpd.cclk = val[1];
3168 /* Read device log parameters. */
3169 rc = -t4_init_devlog_params(sc, 1);
3171 fixup_devlog_params(sc);
3173 device_printf(sc->dev,
3174 "failed to get devlog parameters: %d.\n", rc);
3175 rc = 0; /* devlog isn't critical for device operation */
3182 * Retrieve various parameters that are of interest to the driver. The device
3183 * has been initialized by the firmware at this point.
3186 get_params__post_init(struct adapter *sc)
3189 uint32_t param[7], val[7];
3190 struct fw_caps_config_cmd caps;
3192 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3193 param[1] = FW_PARAM_PFVF(EQ_START);
3194 param[2] = FW_PARAM_PFVF(FILTER_START);
3195 param[3] = FW_PARAM_PFVF(FILTER_END);
3196 param[4] = FW_PARAM_PFVF(L2T_START);
3197 param[5] = FW_PARAM_PFVF(L2T_END);
3198 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3200 device_printf(sc->dev,
3201 "failed to query parameters (post_init): %d.\n", rc);
3205 sc->sge.iq_start = val[0];
3206 sc->sge.eq_start = val[1];
3207 sc->tids.ftid_base = val[2];
3208 sc->tids.nftids = val[3] - val[2] + 1;
3209 sc->params.ftid_min = val[2];
3210 sc->params.ftid_max = val[3];
3211 sc->vres.l2t.start = val[4];
3212 sc->vres.l2t.size = val[5] - val[4] + 1;
3213 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3214 ("%s: L2 table size (%u) larger than expected (%u)",
3215 __func__, sc->vres.l2t.size, L2T_SIZE));
3217 /* get capabilites */
3218 bzero(&caps, sizeof(caps));
3219 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3220 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3221 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3222 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3224 device_printf(sc->dev,
3225 "failed to get card capabilities: %d.\n", rc);
3229 #define READ_CAPS(x) do { \
3230 sc->x = htobe16(caps.x); \
3233 READ_CAPS(linkcaps);
3234 READ_CAPS(switchcaps);
3237 READ_CAPS(rdmacaps);
3239 READ_CAPS(iscsicaps);
3240 READ_CAPS(fcoecaps);
3242 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3243 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3244 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3245 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3246 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3248 device_printf(sc->dev,
3249 "failed to query NIC parameters: %d.\n", rc);
3252 sc->tids.etid_base = val[0];
3253 sc->params.etid_min = val[0];
3254 sc->tids.netids = val[1] - val[0] + 1;
3255 sc->params.netids = sc->tids.netids;
3256 sc->params.eo_wr_cred = val[2];
3257 sc->params.ethoffload = 1;
3261 /* query offload-related parameters */
3262 param[0] = FW_PARAM_DEV(NTID);
3263 param[1] = FW_PARAM_PFVF(SERVER_START);
3264 param[2] = FW_PARAM_PFVF(SERVER_END);
3265 param[3] = FW_PARAM_PFVF(TDDP_START);
3266 param[4] = FW_PARAM_PFVF(TDDP_END);
3267 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3268 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3270 device_printf(sc->dev,
3271 "failed to query TOE parameters: %d.\n", rc);
3274 sc->tids.ntids = val[0];
3275 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3276 sc->tids.stid_base = val[1];
3277 sc->tids.nstids = val[2] - val[1] + 1;
3278 sc->vres.ddp.start = val[3];
3279 sc->vres.ddp.size = val[4] - val[3] + 1;
3280 sc->params.ofldq_wr_cred = val[5];
3281 sc->params.offload = 1;
3284 param[0] = FW_PARAM_PFVF(STAG_START);
3285 param[1] = FW_PARAM_PFVF(STAG_END);
3286 param[2] = FW_PARAM_PFVF(RQ_START);
3287 param[3] = FW_PARAM_PFVF(RQ_END);
3288 param[4] = FW_PARAM_PFVF(PBL_START);
3289 param[5] = FW_PARAM_PFVF(PBL_END);
3290 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3292 device_printf(sc->dev,
3293 "failed to query RDMA parameters(1): %d.\n", rc);
3296 sc->vres.stag.start = val[0];
3297 sc->vres.stag.size = val[1] - val[0] + 1;
3298 sc->vres.rq.start = val[2];
3299 sc->vres.rq.size = val[3] - val[2] + 1;
3300 sc->vres.pbl.start = val[4];
3301 sc->vres.pbl.size = val[5] - val[4] + 1;
3303 param[0] = FW_PARAM_PFVF(SQRQ_START);
3304 param[1] = FW_PARAM_PFVF(SQRQ_END);
3305 param[2] = FW_PARAM_PFVF(CQ_START);
3306 param[3] = FW_PARAM_PFVF(CQ_END);
3307 param[4] = FW_PARAM_PFVF(OCQ_START);
3308 param[5] = FW_PARAM_PFVF(OCQ_END);
3309 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3311 device_printf(sc->dev,
3312 "failed to query RDMA parameters(2): %d.\n", rc);
3315 sc->vres.qp.start = val[0];
3316 sc->vres.qp.size = val[1] - val[0] + 1;
3317 sc->vres.cq.start = val[2];
3318 sc->vres.cq.size = val[3] - val[2] + 1;
3319 sc->vres.ocq.start = val[4];
3320 sc->vres.ocq.size = val[5] - val[4] + 1;
3322 if (sc->iscsicaps) {
3323 param[0] = FW_PARAM_PFVF(ISCSI_START);
3324 param[1] = FW_PARAM_PFVF(ISCSI_END);
3325 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3327 device_printf(sc->dev,
3328 "failed to query iSCSI parameters: %d.\n", rc);
3331 sc->vres.iscsi.start = val[0];
3332 sc->vres.iscsi.size = val[1] - val[0] + 1;
3335 t4_init_sge_params(sc);
3338 * We've got the params we wanted to query via the firmware. Now grab
3339 * some others directly from the chip.
3341 rc = t4_read_chip_settings(sc);
3347 set_params__post_init(struct adapter *sc)
3349 uint32_t param, val;
3351 /* ask for encapsulated CPLs */
3352 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3354 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3359 #undef FW_PARAM_PFVF
3363 t4_set_desc(struct adapter *sc)
3366 struct adapter_params *p = &sc->params;
3368 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3370 device_set_desc_copy(sc->dev, buf);
3374 build_medialist(struct port_info *pi, struct ifmedia *media)
3380 ifmedia_removeall(media);
3382 m = IFM_ETHER | IFM_FDX;
3384 switch(pi->port_type) {
3385 case FW_PORT_TYPE_BT_XFI:
3386 case FW_PORT_TYPE_BT_XAUI:
3387 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3390 case FW_PORT_TYPE_BT_SGMII:
3391 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3392 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3393 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3394 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3397 case FW_PORT_TYPE_CX4:
3398 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3399 ifmedia_set(media, m | IFM_10G_CX4);
3402 case FW_PORT_TYPE_QSFP_10G:
3403 case FW_PORT_TYPE_SFP:
3404 case FW_PORT_TYPE_FIBER_XFI:
3405 case FW_PORT_TYPE_FIBER_XAUI:
3406 switch (pi->mod_type) {
3408 case FW_PORT_MOD_TYPE_LR:
3409 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3410 ifmedia_set(media, m | IFM_10G_LR);
3413 case FW_PORT_MOD_TYPE_SR:
3414 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3415 ifmedia_set(media, m | IFM_10G_SR);
3418 case FW_PORT_MOD_TYPE_LRM:
3419 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3420 ifmedia_set(media, m | IFM_10G_LRM);
3423 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3424 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3425 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3426 ifmedia_set(media, m | IFM_10G_TWINAX);
3429 case FW_PORT_MOD_TYPE_NONE:
3431 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3432 ifmedia_set(media, m | IFM_NONE);
3435 case FW_PORT_MOD_TYPE_NA:
3436 case FW_PORT_MOD_TYPE_ER:
3438 device_printf(pi->dev,
3439 "unknown port_type (%d), mod_type (%d)\n",
3440 pi->port_type, pi->mod_type);
3441 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3442 ifmedia_set(media, m | IFM_UNKNOWN);
3447 case FW_PORT_TYPE_QSFP:
3448 switch (pi->mod_type) {
3450 case FW_PORT_MOD_TYPE_LR:
3451 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3452 ifmedia_set(media, m | IFM_40G_LR4);
3455 case FW_PORT_MOD_TYPE_SR:
3456 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3457 ifmedia_set(media, m | IFM_40G_SR4);
3460 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3461 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3462 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3463 ifmedia_set(media, m | IFM_40G_CR4);
3466 case FW_PORT_MOD_TYPE_NONE:
3468 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3469 ifmedia_set(media, m | IFM_NONE);
3473 device_printf(pi->dev,
3474 "unknown port_type (%d), mod_type (%d)\n",
3475 pi->port_type, pi->mod_type);
3476 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3477 ifmedia_set(media, m | IFM_UNKNOWN);
3483 device_printf(pi->dev,
3484 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3486 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3487 ifmedia_set(media, m | IFM_UNKNOWN);
3494 #define FW_MAC_EXACT_CHUNK 7
3497 * Program the port's XGMAC based on parameters in ifnet. The caller also
3498 * indicates which parameters should be programmed (the rest are left alone).
3501 update_mac_settings(struct ifnet *ifp, int flags)
3504 struct vi_info *vi = ifp->if_softc;
3505 struct port_info *pi = vi->pi;
3506 struct adapter *sc = pi->adapter;
3507 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3509 ASSERT_SYNCHRONIZED_OP(sc);
3510 KASSERT(flags, ("%s: not told what to update.", __func__));
3512 if (flags & XGMAC_MTU)
3515 if (flags & XGMAC_PROMISC)
3516 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3518 if (flags & XGMAC_ALLMULTI)
3519 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3521 if (flags & XGMAC_VLANEX)
3522 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3524 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3525 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3526 allmulti, 1, vlanex, false);
3528 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3534 if (flags & XGMAC_UCADDR) {
3535 uint8_t ucaddr[ETHER_ADDR_LEN];
3537 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3538 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3539 ucaddr, true, true);
3542 if_printf(ifp, "change_mac failed: %d\n", rc);
3545 vi->xact_addr_filt = rc;
3550 if (flags & XGMAC_MCADDRS) {
3551 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3554 struct ifmultiaddr *ifma;
3557 if_maddr_rlock(ifp);
3558 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3559 if (ifma->ifma_addr->sa_family != AF_LINK)
3562 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3563 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3566 if (i == FW_MAC_EXACT_CHUNK) {
3567 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3568 del, i, mcaddr, NULL, &hash, 0);
3571 for (j = 0; j < i; j++) {
3573 "failed to add mc address"
3575 "%02x:%02x:%02x rc=%d\n",
3576 mcaddr[j][0], mcaddr[j][1],
3577 mcaddr[j][2], mcaddr[j][3],
3578 mcaddr[j][4], mcaddr[j][5],
3588 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3589 mcaddr, NULL, &hash, 0);
3592 for (j = 0; j < i; j++) {
3594 "failed to add mc address"
3596 "%02x:%02x:%02x rc=%d\n",
3597 mcaddr[j][0], mcaddr[j][1],
3598 mcaddr[j][2], mcaddr[j][3],
3599 mcaddr[j][4], mcaddr[j][5],
3606 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3608 if_printf(ifp, "failed to set mc address hash: %d", rc);
3610 if_maddr_runlock(ifp);
3617 * {begin|end}_synchronized_op must be called from the same thread.
3620 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3626 /* the caller thinks it's ok to sleep, but is it really? */
3627 if (flags & SLEEP_OK)
3628 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3629 "begin_synchronized_op");
3640 if (vi && IS_DOOMED(vi)) {
3650 if (!(flags & SLEEP_OK)) {
3655 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3661 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3664 sc->last_op = wmesg;
3665 sc->last_op_thr = curthread;
3666 sc->last_op_flags = flags;
3670 if (!(flags & HOLD_LOCK) || rc)
3677 * Tell if_ioctl and if_init that the VI is going away. This is
3678 * special variant of begin_synchronized_op and must be paired with a
3679 * call to end_synchronized_op.
3682 doom_vi(struct adapter *sc, struct vi_info *vi)
3689 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3692 sc->last_op = "t4detach";
3693 sc->last_op_thr = curthread;
3694 sc->last_op_flags = 0;
3700 * {begin|end}_synchronized_op must be called from the same thread.
3703 end_synchronized_op(struct adapter *sc, int flags)
3706 if (flags & LOCK_HELD)
3707 ADAPTER_LOCK_ASSERT_OWNED(sc);
3711 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3718 cxgbe_init_synchronized(struct vi_info *vi)
3720 struct port_info *pi = vi->pi;
3721 struct adapter *sc = pi->adapter;
3722 struct ifnet *ifp = vi->ifp;
3724 struct sge_txq *txq;
3726 ASSERT_SYNCHRONIZED_OP(sc);
3728 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3729 return (0); /* already running */
3731 if (!(sc->flags & FULL_INIT_DONE) &&
3732 ((rc = adapter_full_init(sc)) != 0))
3733 return (rc); /* error message displayed already */
3735 if (!(vi->flags & VI_INIT_DONE) &&
3736 ((rc = vi_full_init(vi)) != 0))
3737 return (rc); /* error message displayed already */
3739 rc = update_mac_settings(ifp, XGMAC_ALL);
3741 goto done; /* error message displayed already */
3743 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3745 if_printf(ifp, "enable_vi failed: %d\n", rc);
3750 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3754 for_each_txq(vi, i, txq) {
3756 txq->eq.flags |= EQ_ENABLED;
3761 * The first iq of the first port to come up is used for tracing.
3763 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3764 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3765 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3766 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3767 V_QUEUENUMBER(sc->traceq));
3768 pi->flags |= HAS_TRACEQ;
3773 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3777 callout_reset(&vi->tick, hz, vi_tick, vi);
3779 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3783 cxgbe_uninit_synchronized(vi);
3792 cxgbe_uninit_synchronized(struct vi_info *vi)
3794 struct port_info *pi = vi->pi;
3795 struct adapter *sc = pi->adapter;
3796 struct ifnet *ifp = vi->ifp;
3798 struct sge_txq *txq;
3800 ASSERT_SYNCHRONIZED_OP(sc);
3802 if (!(vi->flags & VI_INIT_DONE)) {
3803 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3804 ("uninited VI is running"));
3809 * Disable the VI so that all its data in either direction is discarded
3810 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3811 * tick) intact as the TP can deliver negative advice or data that it's
3812 * holding in its RAM (for an offloaded connection) even after the VI is
3815 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3817 if_printf(ifp, "disable_vi failed: %d\n", rc);
3821 for_each_txq(vi, i, txq) {
3823 txq->eq.flags &= ~EQ_ENABLED;
3829 callout_stop(&pi->tick);
3831 callout_stop(&vi->tick);
3832 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3836 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3838 if (pi->up_vis > 0) {
3844 pi->link_cfg.link_ok = 0;
3845 pi->link_cfg.speed = 0;
3847 t4_os_link_changed(sc, pi->port_id, 0, -1);
3853 * It is ok for this function to fail midway and return right away. t4_detach
3854 * will walk the entire sc->irq list and clean up whatever is valid.
3857 setup_intr_handlers(struct adapter *sc)
3859 int rc, rid, p, q, v;
3862 struct port_info *pi;
3864 struct sge *sge = &sc->sge;
3865 struct sge_rxq *rxq;
3867 struct sge_ofld_rxq *ofld_rxq;
3870 struct sge_nm_rxq *nm_rxq;
3873 int nbuckets = rss_getnumbuckets();
3880 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3881 if (sc->intr_count == 1)
3882 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3884 /* Multiple interrupts. */
3885 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3886 ("%s: too few intr.", __func__));
3888 /* The first one is always error intr */
3889 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3895 /* The second one is always the firmware event queue */
3896 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3902 for_each_port(sc, p) {
3904 for_each_vi(pi, v, vi) {
3905 vi->first_intr = rid - 1;
3907 if (vi->nnmrxq > 0) {
3908 int n = max(vi->nrxq, vi->nnmrxq);
3910 MPASS(vi->flags & INTR_RXQ);
3912 rxq = &sge->rxq[vi->first_rxq];
3914 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3916 for (q = 0; q < n; q++) {
3917 snprintf(s, sizeof(s), "%x%c%x", p,
3923 irq->nm_rxq = nm_rxq++;
3925 rc = t4_alloc_irq(sc, irq, rid,
3926 t4_vi_intr, irq, s);
3933 } else if (vi->flags & INTR_RXQ) {
3934 for_each_rxq(vi, q, rxq) {
3935 snprintf(s, sizeof(s), "%x%c%x", p,
3937 rc = t4_alloc_irq(sc, irq, rid,
3942 bus_bind_intr(sc->dev, irq->res,
3943 rss_getcpu(q % nbuckets));
3951 if (vi->flags & INTR_OFLD_RXQ) {
3952 for_each_ofld_rxq(vi, q, ofld_rxq) {
3953 snprintf(s, sizeof(s), "%x%c%x", p,
3955 rc = t4_alloc_irq(sc, irq, rid,
3956 t4_intr, ofld_rxq, s);
3967 MPASS(irq == &sc->irq[sc->intr_count]);
3973 adapter_full_init(struct adapter *sc)
3977 ASSERT_SYNCHRONIZED_OP(sc);
3978 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3979 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3980 ("%s: FULL_INIT_DONE already", __func__));
3983 * queues that belong to the adapter (not any particular port).
3985 rc = t4_setup_adapter_queues(sc);
3989 for (i = 0; i < nitems(sc->tq); i++) {
3990 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3991 taskqueue_thread_enqueue, &sc->tq[i]);
3992 if (sc->tq[i] == NULL) {
3993 device_printf(sc->dev,
3994 "failed to allocate task queue %d\n", i);
3998 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3999 device_get_nameunit(sc->dev), i);
4003 sc->flags |= FULL_INIT_DONE;
4006 adapter_full_uninit(sc);
4012 adapter_full_uninit(struct adapter *sc)
4016 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4018 t4_teardown_adapter_queues(sc);
4020 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4021 taskqueue_free(sc->tq[i]);
4025 sc->flags &= ~FULL_INIT_DONE;
4031 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4032 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4033 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4034 RSS_HASHTYPE_RSS_UDP_IPV6)
4036 /* Translates kernel hash types to hardware. */
4038 hashconfig_to_hashen(int hashconfig)
4042 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4043 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4044 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4045 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4046 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4047 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4048 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4050 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4051 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4052 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4054 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4055 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4056 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4057 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4062 /* Translates hardware hash types to kernel. */
4064 hashen_to_hashconfig(int hashen)
4068 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4070 * If UDP hashing was enabled it must have been enabled for
4071 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4072 * enabling any 4-tuple hash is nonsense configuration.
4074 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4075 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4077 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4078 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4079 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4080 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4082 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4083 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4084 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4085 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4086 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4087 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4088 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4089 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4091 return (hashconfig);
4096 vi_full_init(struct vi_info *vi)
4098 struct adapter *sc = vi->pi->adapter;
4099 struct ifnet *ifp = vi->ifp;
4101 struct sge_rxq *rxq;
4102 int rc, i, j, hashen;
4104 int nbuckets = rss_getnumbuckets();
4105 int hashconfig = rss_gethashconfig();
4107 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4108 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4111 ASSERT_SYNCHRONIZED_OP(sc);
4112 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4113 ("%s: VI_INIT_DONE already", __func__));
4115 sysctl_ctx_init(&vi->ctx);
4116 vi->flags |= VI_SYSCTL_CTX;
4119 * Allocate tx/rx/fl queues for this VI.
4121 rc = t4_setup_vi_queues(vi);
4123 goto done; /* error message displayed already */
4126 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4128 if (vi->nrxq > vi->rss_size) {
4129 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4130 "some queues will never receive traffic.\n", vi->nrxq,
4132 } else if (vi->rss_size % vi->nrxq) {
4133 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4134 "expect uneven traffic distribution.\n", vi->nrxq,
4138 MPASS(RSS_KEYSIZE == 40);
4139 if (vi->nrxq != nbuckets) {
4140 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4141 "performance will be impacted.\n", vi->nrxq, nbuckets);
4144 rss_getkey((void *)&raw_rss_key[0]);
4145 for (i = 0; i < nitems(rss_key); i++) {
4146 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4148 t4_write_rss_key(sc, &rss_key[0], -1);
4150 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4151 for (i = 0; i < vi->rss_size;) {
4153 j = rss_get_indirection_to_bucket(i);
4155 rxq = &sc->sge.rxq[vi->first_rxq + j];
4156 rss[i++] = rxq->iq.abs_id;
4158 for_each_rxq(vi, j, rxq) {
4159 rss[i++] = rxq->iq.abs_id;
4160 if (i == vi->rss_size)
4166 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4169 if_printf(ifp, "rss_config failed: %d\n", rc);
4174 hashen = hashconfig_to_hashen(hashconfig);
4177 * We may have had to enable some hashes even though the global config
4178 * wants them disabled. This is a potential problem that must be
4179 * reported to the user.
4181 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4184 * If we consider only the supported hash types, then the enabled hashes
4185 * are a superset of the requested hashes. In other words, there cannot
4186 * be any supported hash that was requested but not enabled, but there
4187 * can be hashes that were not requested but had to be enabled.
4189 extra &= SUPPORTED_RSS_HASHTYPES;
4190 MPASS((extra & hashconfig) == 0);
4194 "global RSS config (0x%x) cannot be accommodated.\n",
4197 if (extra & RSS_HASHTYPE_RSS_IPV4)
4198 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4199 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4200 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4201 if (extra & RSS_HASHTYPE_RSS_IPV6)
4202 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4203 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4204 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4205 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4206 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4207 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4208 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4210 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4211 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4212 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4213 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4215 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4217 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4222 vi->flags |= VI_INIT_DONE;
4234 vi_full_uninit(struct vi_info *vi)
4236 struct port_info *pi = vi->pi;
4237 struct adapter *sc = pi->adapter;
4239 struct sge_rxq *rxq;
4240 struct sge_txq *txq;
4242 struct sge_ofld_rxq *ofld_rxq;
4243 struct sge_wrq *ofld_txq;
4246 if (vi->flags & VI_INIT_DONE) {
4248 /* Need to quiesce queues. */
4250 /* XXX: Only for the first VI? */
4252 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4254 for_each_txq(vi, i, txq) {
4255 quiesce_txq(sc, txq);
4259 for_each_ofld_txq(vi, i, ofld_txq) {
4260 quiesce_wrq(sc, ofld_txq);
4264 for_each_rxq(vi, i, rxq) {
4265 quiesce_iq(sc, &rxq->iq);
4266 quiesce_fl(sc, &rxq->fl);
4270 for_each_ofld_rxq(vi, i, ofld_rxq) {
4271 quiesce_iq(sc, &ofld_rxq->iq);
4272 quiesce_fl(sc, &ofld_rxq->fl);
4275 free(vi->rss, M_CXGBE);
4276 free(vi->nm_rss, M_CXGBE);
4279 t4_teardown_vi_queues(vi);
4280 vi->flags &= ~VI_INIT_DONE;
4286 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4288 struct sge_eq *eq = &txq->eq;
4289 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4291 (void) sc; /* unused */
4295 MPASS((eq->flags & EQ_ENABLED) == 0);
4299 /* Wait for the mp_ring to empty. */
4300 while (!mp_ring_is_idle(txq->r)) {
4301 mp_ring_check_drainage(txq->r, 0);
4302 pause("rquiesce", 1);
4305 /* Then wait for the hardware to finish. */
4306 while (spg->cidx != htobe16(eq->pidx))
4307 pause("equiesce", 1);
4309 /* Finally, wait for the driver to reclaim all descriptors. */
4310 while (eq->cidx != eq->pidx)
4311 pause("dquiesce", 1);
4315 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4322 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4324 (void) sc; /* unused */
4326 /* Synchronize with the interrupt handler */
4327 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4332 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4334 mtx_lock(&sc->sfl_lock);
4336 fl->flags |= FL_DOOMED;
4338 callout_stop(&sc->sfl_callout);
4339 mtx_unlock(&sc->sfl_lock);
4341 KASSERT((fl->flags & FL_STARVING) == 0,
4342 ("%s: still starving", __func__));
4346 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4347 driver_intr_t *handler, void *arg, char *name)
4352 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4353 RF_SHAREABLE | RF_ACTIVE);
4354 if (irq->res == NULL) {
4355 device_printf(sc->dev,
4356 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4360 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4361 NULL, handler, arg, &irq->tag);
4363 device_printf(sc->dev,
4364 "failed to setup interrupt for rid %d, name %s: %d\n",
4367 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
4373 t4_free_irq(struct adapter *sc, struct irq *irq)
4376 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4378 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4380 bzero(irq, sizeof(*irq));
4386 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4389 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4390 t4_get_regs(sc, buf, regs->len);
4393 #define A_PL_INDIR_CMD 0x1f8
4395 #define S_PL_AUTOINC 31
4396 #define M_PL_AUTOINC 0x1U
4397 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4398 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4400 #define S_PL_VFID 20
4401 #define M_PL_VFID 0xffU
4402 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4403 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4406 #define M_PL_ADDR 0xfffffU
4407 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4408 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4410 #define A_PL_INDIR_DATA 0x1fc
4413 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4417 mtx_assert(&sc->reg_lock, MA_OWNED);
4418 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4419 V_PL_VFID(G_FW_VIID_VIN(viid)) | V_PL_ADDR(VF_MPS_REG(reg)));
4420 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4421 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4422 return (((uint64_t)stats[1]) << 32 | stats[0]);
4426 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4427 struct fw_vi_stats_vf *stats)
4430 #define GET_STAT(name) \
4431 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4433 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4434 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4435 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4436 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4437 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4438 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4439 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4440 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4441 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4442 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4443 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4444 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4445 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4446 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4447 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4448 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4454 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4458 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4459 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4460 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4461 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4462 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4463 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4467 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4470 const struct timeval interval = {0, 250000}; /* 250ms */
4472 if (!(vi->flags & VI_INIT_DONE))
4476 timevalsub(&tv, &interval);
4477 if (timevalcmp(&tv, &vi->last_refreshed, <))
4480 mtx_lock(&sc->reg_lock);
4481 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4482 getmicrotime(&vi->last_refreshed);
4483 mtx_unlock(&sc->reg_lock);
4487 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4490 u_int v, tnl_cong_drops;
4492 const struct timeval interval = {0, 250000}; /* 250ms */
4495 timevalsub(&tv, &interval);
4496 if (timevalcmp(&tv, &pi->last_refreshed, <))
4500 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
4501 for (i = 0; i < sc->chip_params->nchan; i++) {
4502 if (pi->rx_chan_map & (1 << i)) {
4503 mtx_lock(&sc->reg_lock);
4504 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4505 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4506 mtx_unlock(&sc->reg_lock);
4507 tnl_cong_drops += v;
4510 pi->tnl_cong_drops = tnl_cong_drops;
4511 getmicrotime(&pi->last_refreshed);
4515 cxgbe_tick(void *arg)
4517 struct port_info *pi = arg;
4518 struct adapter *sc = pi->adapter;
4520 PORT_LOCK_ASSERT_OWNED(pi);
4521 cxgbe_refresh_stats(sc, pi);
4523 callout_schedule(&pi->tick, hz);
4529 struct vi_info *vi = arg;
4530 struct adapter *sc = vi->pi->adapter;
4532 vi_refresh_stats(sc, vi);
4534 callout_schedule(&vi->tick, hz);
4538 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4542 if (arg != ifp || ifp->if_type != IFT_ETHER)
4545 vlan = VLAN_DEVAT(ifp, vid);
4546 VLAN_SETCOOKIE(vlan, ifp);
4550 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4552 static char *caps_decoder[] = {
4553 "\20\001IPMI\002NCSI", /* 0: NBM */
4554 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4555 "\20\001INGRESS\002EGRESS", /* 2: switch */
4556 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4557 "\006HASHFILTER\007ETHOFLD",
4558 "\20\001TOE", /* 4: TOE */
4559 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4560 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4561 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4562 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4564 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4565 "\20\00KEYS", /* 7: TLS */
4566 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4567 "\004PO_INITIATOR\005PO_TARGET",
4571 t4_sysctls(struct adapter *sc)
4573 struct sysctl_ctx_list *ctx;
4574 struct sysctl_oid *oid;
4575 struct sysctl_oid_list *children, *c0;
4576 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4578 ctx = device_get_sysctl_ctx(sc->dev);
4583 oid = device_get_sysctl_tree(sc->dev);
4584 c0 = children = SYSCTL_CHILDREN(oid);
4586 sc->sc_do_rxcopy = 1;
4587 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4588 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4590 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4591 sc->params.nports, "# of ports");
4593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4594 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4595 sysctl_bitfield, "A", "available doorbells");
4597 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4598 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4600 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4601 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4602 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4603 "interrupt holdoff timer values (us)");
4605 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4606 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4607 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4608 "interrupt holdoff packet counter values");
4610 t4_sge_sysctls(sc, ctx, children);
4612 sc->lro_timeout = 100;
4613 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4614 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4616 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "debug_flags", CTLFLAG_RW,
4617 &sc->debug_flags, 0, "flags to enable runtime debugging");
4619 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4620 NULL, chip_rev(sc), "chip hardware revision");
4622 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
4623 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
4625 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
4626 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
4628 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
4629 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
4631 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
4632 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
4634 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4635 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4637 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
4638 sc->er_version, 0, "expansion ROM version");
4640 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4641 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4643 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
4644 sc->bs_version, 0, "bootstrap firmware version");
4646 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
4647 NULL, sc->params.scfg_vers, "serial config version");
4649 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
4650 NULL, sc->params.vpd_vers, "VPD version");
4652 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4653 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4655 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4656 sc->cfcsum, "config file checksum");
4658 #define SYSCTL_CAP(name, n, text) \
4659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4660 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4661 sysctl_bitfield, "A", "available " text " capabilities")
4663 SYSCTL_CAP(nbmcaps, 0, "NBM");
4664 SYSCTL_CAP(linkcaps, 1, "link");
4665 SYSCTL_CAP(switchcaps, 2, "switch");
4666 SYSCTL_CAP(niccaps, 3, "NIC");
4667 SYSCTL_CAP(toecaps, 4, "TCP offload");
4668 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4669 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4670 SYSCTL_CAP(tlscaps, 7, "TLS");
4671 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4674 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4675 NULL, sc->tids.nftids, "number of filters");
4677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4678 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4679 "chip temperature (in Celsius)");
4683 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4685 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4686 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4687 "logs and miscellaneous information");
4688 children = SYSCTL_CHILDREN(oid);
4690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4691 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4692 sysctl_cctrl, "A", "congestion control");
4694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4695 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4696 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4699 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4700 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4703 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4704 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4707 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4708 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4711 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4712 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4715 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4716 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4718 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4719 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4720 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4721 "A", "CIM logic analyzer");
4723 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4724 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4725 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4727 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4728 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4729 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4731 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4732 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4733 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4736 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4737 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4739 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4740 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4741 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4743 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4744 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4745 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4747 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4748 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4749 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4751 if (chip_id(sc) > CHELSIO_T4) {
4752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4753 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4754 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4756 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4757 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4758 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4761 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4762 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4763 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4765 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4766 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4767 sysctl_cim_qcfg, "A", "CIM queue configuration");
4769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4770 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4771 sysctl_cpl_stats, "A", "CPL statistics");
4773 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4774 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4775 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4777 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4778 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4779 sysctl_devlog, "A", "firmware's device log");
4781 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4782 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4783 sysctl_fcoe_stats, "A", "FCoE statistics");
4785 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4786 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4787 sysctl_hw_sched, "A", "hardware scheduler ");
4789 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4790 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4791 sysctl_l2t, "A", "hardware L2 table");
4793 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4794 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4795 sysctl_lb_stats, "A", "loopback statistics");
4797 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4798 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4799 sysctl_meminfo, "A", "memory regions");
4801 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4802 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4803 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4804 "A", "MPS TCAM entries");
4806 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4807 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4808 sysctl_path_mtus, "A", "path MTUs");
4810 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4811 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4812 sysctl_pm_stats, "A", "PM statistics");
4814 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4815 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4816 sysctl_rdma_stats, "A", "RDMA statistics");
4818 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4819 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4820 sysctl_tcp_stats, "A", "TCP statistics");
4822 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4823 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4824 sysctl_tids, "A", "TID information");
4826 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4827 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4828 sysctl_tp_err_stats, "A", "TP error statistics");
4830 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4831 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4832 "TP logic analyzer event capture mask");
4834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4835 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4836 sysctl_tp_la, "A", "TP logic analyzer");
4838 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4839 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4840 sysctl_tx_rate, "A", "Tx rate");
4842 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4843 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4844 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4848 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4849 sysctl_wcwr_stats, "A", "write combined work requests");
4854 if (is_offload(sc)) {
4858 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4859 NULL, "TOE parameters");
4860 children = SYSCTL_CHILDREN(oid);
4862 sc->tt.sndbuf = 256 * 1024;
4863 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4864 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4867 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4868 &sc->tt.ddp, 0, "DDP allowed");
4870 sc->tt.rx_coalesce = 1;
4871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4872 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4874 sc->tt.tx_align = 1;
4875 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4876 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4878 sc->tt.tx_zcopy = 0;
4879 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
4880 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
4881 "Enable zero-copy aio_write(2)");
4883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4884 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4885 "TP timer tick (us)");
4887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4888 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4889 "TCP timestamp tick (us)");
4891 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4892 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4896 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4897 "IU", "DACK timer (us)");
4899 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4900 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4901 sysctl_tp_timer, "LU", "Retransmit min (us)");
4903 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4904 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4905 sysctl_tp_timer, "LU", "Retransmit max (us)");
4907 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4908 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4909 sysctl_tp_timer, "LU", "Persist timer min (us)");
4911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4912 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4913 sysctl_tp_timer, "LU", "Persist timer max (us)");
4915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4916 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
4917 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
4919 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
4920 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
4921 sysctl_tp_timer, "LU", "Keepidle interval (us)");
4923 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
4924 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
4925 sysctl_tp_timer, "LU", "Initial SRTT (us)");
4927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
4928 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
4929 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
4935 vi_sysctls(struct vi_info *vi)
4937 struct sysctl_ctx_list *ctx;
4938 struct sysctl_oid *oid;
4939 struct sysctl_oid_list *children;
4941 ctx = device_get_sysctl_ctx(vi->dev);
4944 * dev.v?(cxgbe|cxl).X.
4946 oid = device_get_sysctl_tree(vi->dev);
4947 children = SYSCTL_CHILDREN(oid);
4949 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4950 vi->viid, "VI identifer");
4951 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4952 &vi->nrxq, 0, "# of rx queues");
4953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4954 &vi->ntxq, 0, "# of tx queues");
4955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4956 &vi->first_rxq, 0, "index of first rx queue");
4957 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4958 &vi->first_txq, 0, "index of first tx queue");
4959 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
4960 vi->rss_size, "size of RSS indirection table");
4962 if (IS_MAIN_VI(vi)) {
4963 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4964 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4965 "Reserve queue 0 for non-flowid packets");
4969 if (vi->nofldrxq != 0) {
4970 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4972 "# of rx queues for offloaded TCP connections");
4973 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4975 "# of tx queues for offloaded TCP connections");
4976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4977 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4978 "index of first TOE rx queue");
4979 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4980 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4981 "index of first TOE tx queue");
4985 if (vi->nnmrxq != 0) {
4986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4987 &vi->nnmrxq, 0, "# of netmap rx queues");
4988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4989 &vi->nnmtxq, 0, "# of netmap tx queues");
4990 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4991 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4992 "index of first netmap rx queue");
4993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4994 CTLFLAG_RD, &vi->first_nm_txq, 0,
4995 "index of first netmap tx queue");
4999 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5000 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5001 "holdoff timer index");
5002 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5003 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5004 "holdoff packet counter index");
5006 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5007 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5009 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5010 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5015 cxgbe_sysctls(struct port_info *pi)
5017 struct sysctl_ctx_list *ctx;
5018 struct sysctl_oid *oid;
5019 struct sysctl_oid_list *children, *children2;
5020 struct adapter *sc = pi->adapter;
5024 ctx = device_get_sysctl_ctx(pi->dev);
5029 oid = device_get_sysctl_tree(pi->dev);
5030 children = SYSCTL_CHILDREN(oid);
5032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5033 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5034 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5036 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5037 "PHY temperature (in Celsius)");
5038 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5039 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5040 "PHY firmware version");
5043 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5044 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
5045 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5047 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5048 port_top_speed(pi), "max speed (in Gbps)");
5051 * dev.(cxgbe|cxl).X.tc.
5053 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5054 "Tx scheduler traffic classes");
5055 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5056 struct tx_sched_class *tc = &pi->tc[i];
5058 snprintf(name, sizeof(name), "%d", i);
5059 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5060 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5062 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5063 &tc->flags, 0, "flags");
5064 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5065 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5067 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5068 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5069 sysctl_tc_params, "A", "traffic class parameters");
5074 * dev.cxgbe.X.stats.
5076 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5077 NULL, "port statistics");
5078 children = SYSCTL_CHILDREN(oid);
5079 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5080 &pi->tx_parse_error, 0,
5081 "# of tx packets with invalid length or # of segments");
5083 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5084 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5085 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5086 sysctl_handle_t4_reg64, "QU", desc)
5088 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5089 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5090 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5091 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5092 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5093 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5094 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5095 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5096 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5097 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5098 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5099 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5100 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5101 "# of tx frames in this range",
5102 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5103 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5104 "# of tx frames in this range",
5105 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5106 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5107 "# of tx frames in this range",
5108 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5109 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5110 "# of tx frames in this range",
5111 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5112 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5113 "# of tx frames in this range",
5114 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5115 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5116 "# of tx frames in this range",
5117 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5118 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5119 "# of tx frames in this range",
5120 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5121 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5122 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5123 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5124 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5125 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5126 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5127 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5128 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5129 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5130 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5131 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5132 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5133 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5134 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5135 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5136 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5137 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5138 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5139 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5140 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5142 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5143 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5144 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5145 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5146 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5147 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5148 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5149 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5150 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5151 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5152 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5153 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5154 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5155 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5156 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5157 "# of frames received with bad FCS",
5158 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5159 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5160 "# of frames received with length error",
5161 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5162 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5163 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5164 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5165 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5166 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5167 "# of rx frames in this range",
5168 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5169 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5170 "# of rx frames in this range",
5171 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5172 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5173 "# of rx frames in this range",
5174 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5175 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5176 "# of rx frames in this range",
5177 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5178 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5179 "# of rx frames in this range",
5180 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5181 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5182 "# of rx frames in this range",
5183 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5184 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5185 "# of rx frames in this range",
5186 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5187 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5188 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5189 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5190 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5191 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5192 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5193 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5194 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5195 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5196 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5197 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5198 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5199 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5200 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5201 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5202 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5203 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5204 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5206 #undef SYSCTL_ADD_T4_REG64
5208 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5209 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5210 &pi->stats.name, desc)
5212 /* We get these from port_stats and they may be stale by up to 1s */
5213 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5214 "# drops due to buffer-group 0 overflows");
5215 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5216 "# drops due to buffer-group 1 overflows");
5217 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5218 "# drops due to buffer-group 2 overflows");
5219 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5220 "# drops due to buffer-group 3 overflows");
5221 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5222 "# of buffer-group 0 truncated packets");
5223 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5224 "# of buffer-group 1 truncated packets");
5225 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5226 "# of buffer-group 2 truncated packets");
5227 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5228 "# of buffer-group 3 truncated packets");
5230 #undef SYSCTL_ADD_T4_PORTSTAT
5234 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5236 int rc, *i, space = 0;
5239 sbuf_new_for_sysctl(&sb, NULL, 64, req);
5240 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5242 sbuf_printf(&sb, " ");
5243 sbuf_printf(&sb, "%d", *i);
5246 rc = sbuf_finish(&sb);
5252 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5257 rc = sysctl_wire_old_buffer(req, 0);
5261 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5265 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5266 rc = sbuf_finish(sb);
5273 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5275 struct port_info *pi = arg1;
5277 struct adapter *sc = pi->adapter;
5281 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5284 /* XXX: magic numbers */
5285 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5287 end_synchronized_op(sc, 0);
5293 rc = sysctl_handle_int(oidp, &v, 0, req);
5298 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5300 struct vi_info *vi = arg1;
5303 val = vi->rsrv_noflowq;
5304 rc = sysctl_handle_int(oidp, &val, 0, req);
5305 if (rc != 0 || req->newptr == NULL)
5308 if ((val >= 1) && (vi->ntxq > 1))
5309 vi->rsrv_noflowq = 1;
5311 vi->rsrv_noflowq = 0;
5317 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5319 struct vi_info *vi = arg1;
5320 struct adapter *sc = vi->pi->adapter;
5322 struct sge_rxq *rxq;
5324 struct sge_ofld_rxq *ofld_rxq;
5330 rc = sysctl_handle_int(oidp, &idx, 0, req);
5331 if (rc != 0 || req->newptr == NULL)
5334 if (idx < 0 || idx >= SGE_NTIMERS)
5337 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5342 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5343 for_each_rxq(vi, i, rxq) {
5344 #ifdef atomic_store_rel_8
5345 atomic_store_rel_8(&rxq->iq.intr_params, v);
5347 rxq->iq.intr_params = v;
5351 for_each_ofld_rxq(vi, i, ofld_rxq) {
5352 #ifdef atomic_store_rel_8
5353 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5355 ofld_rxq->iq.intr_params = v;
5361 end_synchronized_op(sc, LOCK_HELD);
5366 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5368 struct vi_info *vi = arg1;
5369 struct adapter *sc = vi->pi->adapter;
5374 rc = sysctl_handle_int(oidp, &idx, 0, req);
5375 if (rc != 0 || req->newptr == NULL)
5378 if (idx < -1 || idx >= SGE_NCOUNTERS)
5381 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5386 if (vi->flags & VI_INIT_DONE)
5387 rc = EBUSY; /* cannot be changed once the queues are created */
5391 end_synchronized_op(sc, LOCK_HELD);
5396 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5398 struct vi_info *vi = arg1;
5399 struct adapter *sc = vi->pi->adapter;
5402 qsize = vi->qsize_rxq;
5404 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5405 if (rc != 0 || req->newptr == NULL)
5408 if (qsize < 128 || (qsize & 7))
5411 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5416 if (vi->flags & VI_INIT_DONE)
5417 rc = EBUSY; /* cannot be changed once the queues are created */
5419 vi->qsize_rxq = qsize;
5421 end_synchronized_op(sc, LOCK_HELD);
5426 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5428 struct vi_info *vi = arg1;
5429 struct adapter *sc = vi->pi->adapter;
5432 qsize = vi->qsize_txq;
5434 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5435 if (rc != 0 || req->newptr == NULL)
5438 if (qsize < 128 || qsize > 65536)
5441 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5446 if (vi->flags & VI_INIT_DONE)
5447 rc = EBUSY; /* cannot be changed once the queues are created */
5449 vi->qsize_txq = qsize;
5451 end_synchronized_op(sc, LOCK_HELD);
5456 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5458 struct port_info *pi = arg1;
5459 struct adapter *sc = pi->adapter;
5460 struct link_config *lc = &pi->link_cfg;
5463 if (req->newptr == NULL) {
5465 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5467 rc = sysctl_wire_old_buffer(req, 0);
5471 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5475 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5476 rc = sbuf_finish(sb);
5482 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5485 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5491 if (s[0] < '0' || s[0] > '9')
5492 return (EINVAL); /* not a number */
5494 if (n & ~(PAUSE_TX | PAUSE_RX))
5495 return (EINVAL); /* some other bit is set too */
5497 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5501 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5502 int link_ok = lc->link_ok;
5504 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5505 lc->requested_fc |= n;
5506 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5507 lc->link_ok = link_ok; /* restore */
5509 end_synchronized_op(sc, 0);
5516 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5518 struct adapter *sc = arg1;
5522 val = t4_read_reg64(sc, reg);
5524 return (sysctl_handle_64(oidp, &val, 0, req));
5528 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5530 struct adapter *sc = arg1;
5532 uint32_t param, val;
5534 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5537 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5538 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5539 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5540 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5541 end_synchronized_op(sc, 0);
5545 /* unknown is returned as 0 but we display -1 in that case */
5546 t = val == 0 ? -1 : val;
5548 rc = sysctl_handle_int(oidp, &t, 0, req);
5554 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5556 struct adapter *sc = arg1;
5559 uint16_t incr[NMTUS][NCCTRL_WIN];
5560 static const char *dec_fac[] = {
5561 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5565 rc = sysctl_wire_old_buffer(req, 0);
5569 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5573 t4_read_cong_tbl(sc, incr);
5575 for (i = 0; i < NCCTRL_WIN; ++i) {
5576 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5577 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5578 incr[5][i], incr[6][i], incr[7][i]);
5579 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5580 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5581 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5582 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5585 rc = sbuf_finish(sb);
5591 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5592 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5593 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5594 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5598 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5600 struct adapter *sc = arg1;
5602 int rc, i, n, qid = arg2;
5605 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5607 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5608 ("%s: bad qid %d\n", __func__, qid));
5610 if (qid < CIM_NUM_IBQ) {
5613 n = 4 * CIM_IBQ_SIZE;
5614 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5615 rc = t4_read_cim_ibq(sc, qid, buf, n);
5617 /* outbound queue */
5620 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5621 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5622 rc = t4_read_cim_obq(sc, qid, buf, n);
5629 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5631 rc = sysctl_wire_old_buffer(req, 0);
5635 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5641 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5642 for (i = 0, p = buf; i < n; i += 16, p += 4)
5643 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5646 rc = sbuf_finish(sb);
5654 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5656 struct adapter *sc = arg1;
5662 MPASS(chip_id(sc) <= CHELSIO_T5);
5664 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5668 rc = sysctl_wire_old_buffer(req, 0);
5672 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5676 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5679 rc = -t4_cim_read_la(sc, buf, NULL);
5683 sbuf_printf(sb, "Status Data PC%s",
5684 cfg & F_UPDBGLACAPTPCONLY ? "" :
5685 " LS0Stat LS0Addr LS0Data");
5687 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5688 if (cfg & F_UPDBGLACAPTPCONLY) {
5689 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5691 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5692 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5693 p[4] & 0xff, p[5] >> 8);
5694 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5695 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5696 p[1] & 0xf, p[2] >> 4);
5699 "\n %02x %x%07x %x%07x %08x %08x "
5701 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5702 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5707 rc = sbuf_finish(sb);
5715 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5717 struct adapter *sc = arg1;
5723 MPASS(chip_id(sc) > CHELSIO_T5);
5725 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5729 rc = sysctl_wire_old_buffer(req, 0);
5733 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5737 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5740 rc = -t4_cim_read_la(sc, buf, NULL);
5744 sbuf_printf(sb, "Status Inst Data PC%s",
5745 cfg & F_UPDBGLACAPTPCONLY ? "" :
5746 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5748 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5749 if (cfg & F_UPDBGLACAPTPCONLY) {
5750 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5751 p[3] & 0xff, p[2], p[1], p[0]);
5752 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5753 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5754 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5755 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5756 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5757 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5760 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5761 "%08x %08x %08x %08x %08x %08x",
5762 (p[9] >> 16) & 0xff,
5763 p[9] & 0xffff, p[8] >> 16,
5764 p[8] & 0xffff, p[7] >> 16,
5765 p[7] & 0xffff, p[6] >> 16,
5766 p[2], p[1], p[0], p[5], p[4], p[3]);
5770 rc = sbuf_finish(sb);
5778 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5780 struct adapter *sc = arg1;
5786 rc = sysctl_wire_old_buffer(req, 0);
5790 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5794 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5797 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5800 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5801 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5805 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5806 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5807 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5808 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5809 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5810 (p[1] >> 2) | ((p[2] & 3) << 30),
5811 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5815 rc = sbuf_finish(sb);
5822 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5824 struct adapter *sc = arg1;
5830 rc = sysctl_wire_old_buffer(req, 0);
5834 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5838 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5841 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5844 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5845 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5846 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5847 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5848 p[4], p[3], p[2], p[1], p[0]);
5851 sbuf_printf(sb, "\n\nCntl ID Data");
5852 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5853 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5854 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5857 rc = sbuf_finish(sb);
5864 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5866 struct adapter *sc = arg1;
5869 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5870 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5871 uint16_t thres[CIM_NUM_IBQ];
5872 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5873 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5874 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5876 cim_num_obq = sc->chip_params->cim_num_obq;
5878 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5879 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5881 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5882 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5884 nq = CIM_NUM_IBQ + cim_num_obq;
5886 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5888 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5892 t4_read_cimq_cfg(sc, base, size, thres);
5894 rc = sysctl_wire_old_buffer(req, 0);
5898 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5902 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5904 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5905 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5906 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5907 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5908 G_QUEREMFLITS(p[2]) * 16);
5909 for ( ; i < nq; i++, p += 4, wr += 2)
5910 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5911 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5912 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5913 G_QUEREMFLITS(p[2]) * 16);
5915 rc = sbuf_finish(sb);
5922 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5924 struct adapter *sc = arg1;
5927 struct tp_cpl_stats stats;
5929 rc = sysctl_wire_old_buffer(req, 0);
5933 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5937 mtx_lock(&sc->reg_lock);
5938 t4_tp_get_cpl_stats(sc, &stats);
5939 mtx_unlock(&sc->reg_lock);
5941 if (sc->chip_params->nchan > 2) {
5942 sbuf_printf(sb, " channel 0 channel 1"
5943 " channel 2 channel 3");
5944 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5945 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5946 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5947 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5949 sbuf_printf(sb, " channel 0 channel 1");
5950 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5951 stats.req[0], stats.req[1]);
5952 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5953 stats.rsp[0], stats.rsp[1]);
5956 rc = sbuf_finish(sb);
5963 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5965 struct adapter *sc = arg1;
5968 struct tp_usm_stats stats;
5970 rc = sysctl_wire_old_buffer(req, 0);
5974 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5978 t4_get_usm_stats(sc, &stats);
5980 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5981 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5982 sbuf_printf(sb, "Drops: %u", stats.drops);
5984 rc = sbuf_finish(sb);
5990 static const char * const devlog_level_strings[] = {
5991 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5992 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5993 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5994 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5995 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5996 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5999 static const char * const devlog_facility_strings[] = {
6000 [FW_DEVLOG_FACILITY_CORE] = "CORE",
6001 [FW_DEVLOG_FACILITY_CF] = "CF",
6002 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
6003 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
6004 [FW_DEVLOG_FACILITY_RES] = "RES",
6005 [FW_DEVLOG_FACILITY_HW] = "HW",
6006 [FW_DEVLOG_FACILITY_FLR] = "FLR",
6007 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
6008 [FW_DEVLOG_FACILITY_PHY] = "PHY",
6009 [FW_DEVLOG_FACILITY_MAC] = "MAC",
6010 [FW_DEVLOG_FACILITY_PORT] = "PORT",
6011 [FW_DEVLOG_FACILITY_VI] = "VI",
6012 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
6013 [FW_DEVLOG_FACILITY_ACL] = "ACL",
6014 [FW_DEVLOG_FACILITY_TM] = "TM",
6015 [FW_DEVLOG_FACILITY_QFC] = "QFC",
6016 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6017 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6018 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6019 [FW_DEVLOG_FACILITY_RI] = "RI",
6020 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6021 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6022 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6023 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6024 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6028 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6030 struct adapter *sc = arg1;
6031 struct devlog_params *dparams = &sc->params.devlog;
6032 struct fw_devlog_e *buf, *e;
6033 int i, j, rc, nentries, first = 0;
6035 uint64_t ftstamp = UINT64_MAX;
6037 if (dparams->addr == 0)
6040 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6044 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6048 nentries = dparams->size / sizeof(struct fw_devlog_e);
6049 for (i = 0; i < nentries; i++) {
6052 if (e->timestamp == 0)
6055 e->timestamp = be64toh(e->timestamp);
6056 e->seqno = be32toh(e->seqno);
6057 for (j = 0; j < 8; j++)
6058 e->params[j] = be32toh(e->params[j]);
6060 if (e->timestamp < ftstamp) {
6061 ftstamp = e->timestamp;
6066 if (buf[first].timestamp == 0)
6067 goto done; /* nothing in the log */
6069 rc = sysctl_wire_old_buffer(req, 0);
6073 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6078 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6079 "Seq#", "Tstamp", "Level", "Facility", "Message");
6084 if (e->timestamp == 0)
6087 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6088 e->seqno, e->timestamp,
6089 (e->level < nitems(devlog_level_strings) ?
6090 devlog_level_strings[e->level] : "UNKNOWN"),
6091 (e->facility < nitems(devlog_facility_strings) ?
6092 devlog_facility_strings[e->facility] : "UNKNOWN"));
6093 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6094 e->params[2], e->params[3], e->params[4],
6095 e->params[5], e->params[6], e->params[7]);
6097 if (++i == nentries)
6099 } while (i != first);
6101 rc = sbuf_finish(sb);
6109 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6111 struct adapter *sc = arg1;
6114 struct tp_fcoe_stats stats[MAX_NCHAN];
6115 int i, nchan = sc->chip_params->nchan;
6117 rc = sysctl_wire_old_buffer(req, 0);
6121 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6125 for (i = 0; i < nchan; i++)
6126 t4_get_fcoe_stats(sc, i, &stats[i]);
6129 sbuf_printf(sb, " channel 0 channel 1"
6130 " channel 2 channel 3");
6131 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6132 stats[0].octets_ddp, stats[1].octets_ddp,
6133 stats[2].octets_ddp, stats[3].octets_ddp);
6134 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6135 stats[0].frames_ddp, stats[1].frames_ddp,
6136 stats[2].frames_ddp, stats[3].frames_ddp);
6137 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6138 stats[0].frames_drop, stats[1].frames_drop,
6139 stats[2].frames_drop, stats[3].frames_drop);
6141 sbuf_printf(sb, " channel 0 channel 1");
6142 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6143 stats[0].octets_ddp, stats[1].octets_ddp);
6144 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6145 stats[0].frames_ddp, stats[1].frames_ddp);
6146 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6147 stats[0].frames_drop, stats[1].frames_drop);
6150 rc = sbuf_finish(sb);
6157 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6159 struct adapter *sc = arg1;
6162 unsigned int map, kbps, ipg, mode;
6163 unsigned int pace_tab[NTX_SCHED];
6165 rc = sysctl_wire_old_buffer(req, 0);
6169 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6173 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6174 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6175 t4_read_pace_tbl(sc, pace_tab);
6177 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6178 "Class IPG (0.1 ns) Flow IPG (us)");
6180 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6181 t4_get_tx_sched(sc, i, &kbps, &ipg);
6182 sbuf_printf(sb, "\n %u %-5s %u ", i,
6183 (mode & (1 << i)) ? "flow" : "class", map & 3);
6185 sbuf_printf(sb, "%9u ", kbps);
6187 sbuf_printf(sb, " disabled ");
6190 sbuf_printf(sb, "%13u ", ipg);
6192 sbuf_printf(sb, " disabled ");
6195 sbuf_printf(sb, "%10u", pace_tab[i]);
6197 sbuf_printf(sb, " disabled");
6200 rc = sbuf_finish(sb);
6207 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6209 struct adapter *sc = arg1;
6213 struct lb_port_stats s[2];
6214 static const char *stat_name[] = {
6215 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6216 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6217 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6218 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6219 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6220 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6221 "BG2FramesTrunc:", "BG3FramesTrunc:"
6224 rc = sysctl_wire_old_buffer(req, 0);
6228 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6232 memset(s, 0, sizeof(s));
6234 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6235 t4_get_lb_stats(sc, i, &s[0]);
6236 t4_get_lb_stats(sc, i + 1, &s[1]);
6240 sbuf_printf(sb, "%s Loopback %u"
6241 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6243 for (j = 0; j < nitems(stat_name); j++)
6244 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6248 rc = sbuf_finish(sb);
6255 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6258 struct port_info *pi = arg1;
6261 rc = sysctl_wire_old_buffer(req, 0);
6264 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6268 if (pi->linkdnrc < 0)
6269 sbuf_printf(sb, "n/a");
6271 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6273 rc = sbuf_finish(sb);
6286 mem_desc_cmp(const void *a, const void *b)
6288 return ((const struct mem_desc *)a)->base -
6289 ((const struct mem_desc *)b)->base;
6293 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6301 size = to - from + 1;
6305 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6306 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6310 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6312 struct adapter *sc = arg1;
6315 uint32_t lo, hi, used, alloc;
6316 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6317 static const char *region[] = {
6318 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6319 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6320 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6321 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6322 "RQUDP region:", "PBL region:", "TXPBL region:",
6323 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6326 struct mem_desc avail[4];
6327 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6328 struct mem_desc *md = mem;
6330 rc = sysctl_wire_old_buffer(req, 0);
6334 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6338 for (i = 0; i < nitems(mem); i++) {
6343 /* Find and sort the populated memory ranges */
6345 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6346 if (lo & F_EDRAM0_ENABLE) {
6347 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6348 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6349 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6353 if (lo & F_EDRAM1_ENABLE) {
6354 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6355 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6356 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6360 if (lo & F_EXT_MEM_ENABLE) {
6361 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6362 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6363 avail[i].limit = avail[i].base +
6364 (G_EXT_MEM_SIZE(hi) << 20);
6365 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6368 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6369 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6370 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6371 avail[i].limit = avail[i].base +
6372 (G_EXT_MEM1_SIZE(hi) << 20);
6376 if (!i) /* no memory available */
6378 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6380 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6381 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6382 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6383 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6384 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6385 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6386 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6387 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6388 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6390 /* the next few have explicit upper bounds */
6391 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6392 md->limit = md->base - 1 +
6393 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6394 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6397 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6398 md->limit = md->base - 1 +
6399 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6400 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6403 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6404 if (chip_id(sc) <= CHELSIO_T5)
6405 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6407 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6411 md->idx = nitems(region); /* hide it */
6415 #define ulp_region(reg) \
6416 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6417 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6419 ulp_region(RX_ISCSI);
6420 ulp_region(RX_TDDP);
6422 ulp_region(RX_STAG);
6424 ulp_region(RX_RQUDP);
6430 md->idx = nitems(region);
6433 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6434 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6437 if (sge_ctrl & F_VFIFO_ENABLE)
6438 size = G_DBVFIFO_SIZE(fifo_size);
6440 size = G_T6_DBVFIFO_SIZE(fifo_size);
6443 md->base = G_BASEADDR(t4_read_reg(sc,
6444 A_SGE_DBVFIFO_BADDR));
6445 md->limit = md->base + (size << 2) - 1;
6450 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6453 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6457 md->base = sc->vres.ocq.start;
6458 if (sc->vres.ocq.size)
6459 md->limit = md->base + sc->vres.ocq.size - 1;
6461 md->idx = nitems(region); /* hide it */
6464 /* add any address-space holes, there can be up to 3 */
6465 for (n = 0; n < i - 1; n++)
6466 if (avail[n].limit < avail[n + 1].base)
6467 (md++)->base = avail[n].limit;
6469 (md++)->base = avail[n].limit;
6472 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6474 for (lo = 0; lo < i; lo++)
6475 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6476 avail[lo].limit - 1);
6478 sbuf_printf(sb, "\n");
6479 for (i = 0; i < n; i++) {
6480 if (mem[i].idx >= nitems(region))
6481 continue; /* skip holes */
6483 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6484 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6488 sbuf_printf(sb, "\n");
6489 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6490 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6491 mem_region_show(sb, "uP RAM:", lo, hi);
6493 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6494 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6495 mem_region_show(sb, "uP Extmem2:", lo, hi);
6497 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6498 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6500 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6501 (lo & F_PMRXNUMCHN) ? 2 : 1);
6503 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6504 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6505 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6507 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6508 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6509 sbuf_printf(sb, "%u p-structs\n",
6510 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6512 for (i = 0; i < 4; i++) {
6513 if (chip_id(sc) > CHELSIO_T5)
6514 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6516 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6518 used = G_T5_USED(lo);
6519 alloc = G_T5_ALLOC(lo);
6522 alloc = G_ALLOC(lo);
6524 /* For T6 these are MAC buffer groups */
6525 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6528 for (i = 0; i < sc->chip_params->nchan; i++) {
6529 if (chip_id(sc) > CHELSIO_T5)
6530 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6532 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6534 used = G_T5_USED(lo);
6535 alloc = G_T5_ALLOC(lo);
6538 alloc = G_ALLOC(lo);
6540 /* For T6 these are MAC buffer groups */
6542 "\nLoopback %d using %u pages out of %u allocated",
6546 rc = sbuf_finish(sb);
6553 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6557 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6561 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6563 struct adapter *sc = arg1;
6567 MPASS(chip_id(sc) <= CHELSIO_T5);
6569 rc = sysctl_wire_old_buffer(req, 0);
6573 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6578 "Idx Ethernet address Mask Vld Ports PF"
6579 " VF Replication P0 P1 P2 P3 ML");
6580 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6581 uint64_t tcamx, tcamy, mask;
6582 uint32_t cls_lo, cls_hi;
6583 uint8_t addr[ETHER_ADDR_LEN];
6585 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6586 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6589 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6590 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6591 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6592 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6593 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6594 addr[3], addr[4], addr[5], (uintmax_t)mask,
6595 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6596 G_PORTMAP(cls_hi), G_PF(cls_lo),
6597 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6599 if (cls_lo & F_REPLICATE) {
6600 struct fw_ldst_cmd ldst_cmd;
6602 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6603 ldst_cmd.op_to_addrspace =
6604 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6605 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6606 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6607 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6608 ldst_cmd.u.mps.rplc.fid_idx =
6609 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6610 V_FW_LDST_CMD_IDX(i));
6612 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6616 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6617 sizeof(ldst_cmd), &ldst_cmd);
6618 end_synchronized_op(sc, 0);
6621 sbuf_printf(sb, "%36d", rc);
6624 sbuf_printf(sb, " %08x %08x %08x %08x",
6625 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6626 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6627 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6628 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6631 sbuf_printf(sb, "%36s", "");
6633 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6634 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6635 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6639 (void) sbuf_finish(sb);
6641 rc = sbuf_finish(sb);
6648 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6650 struct adapter *sc = arg1;
6654 MPASS(chip_id(sc) > CHELSIO_T5);
6656 rc = sysctl_wire_old_buffer(req, 0);
6660 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6664 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6665 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6667 " P0 P1 P2 P3 ML\n");
6669 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6670 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6672 uint64_t tcamx, tcamy, val, mask;
6673 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6674 uint8_t addr[ETHER_ADDR_LEN];
6676 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6678 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6680 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6681 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6682 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6683 tcamy = G_DMACH(val) << 32;
6684 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6685 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6686 lookup_type = G_DATALKPTYPE(data2);
6687 port_num = G_DATAPORTNUM(data2);
6688 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6689 /* Inner header VNI */
6690 vniy = ((data2 & F_DATAVIDH2) << 23) |
6691 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6692 dip_hit = data2 & F_DATADIPHIT;
6697 vlan_vld = data2 & F_DATAVIDH2;
6698 ivlan = G_VIDL(val);
6701 ctl |= V_CTLXYBITSEL(1);
6702 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6703 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6704 tcamx = G_DMACH(val) << 32;
6705 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6706 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6707 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6708 /* Inner header VNI mask */
6709 vnix = ((data2 & F_DATAVIDH2) << 23) |
6710 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6716 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6718 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6719 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6721 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6722 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6723 "%012jx %06x %06x - - %3c"
6724 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6725 addr[1], addr[2], addr[3], addr[4], addr[5],
6726 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6727 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6728 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6729 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6731 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6732 "%012jx - - ", i, addr[0], addr[1],
6733 addr[2], addr[3], addr[4], addr[5],
6737 sbuf_printf(sb, "%4u Y ", ivlan);
6739 sbuf_printf(sb, " - N ");
6741 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6742 lookup_type ? 'I' : 'O', port_num,
6743 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6744 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6745 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6749 if (cls_lo & F_T6_REPLICATE) {
6750 struct fw_ldst_cmd ldst_cmd;
6752 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6753 ldst_cmd.op_to_addrspace =
6754 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6755 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6756 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6757 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6758 ldst_cmd.u.mps.rplc.fid_idx =
6759 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6760 V_FW_LDST_CMD_IDX(i));
6762 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6766 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6767 sizeof(ldst_cmd), &ldst_cmd);
6768 end_synchronized_op(sc, 0);
6771 sbuf_printf(sb, "%72d", rc);
6774 sbuf_printf(sb, " %08x %08x %08x %08x"
6775 " %08x %08x %08x %08x",
6776 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6777 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6778 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6779 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6780 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6781 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6782 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6783 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6786 sbuf_printf(sb, "%72s", "");
6788 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6789 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6790 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6791 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6795 (void) sbuf_finish(sb);
6797 rc = sbuf_finish(sb);
6804 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6806 struct adapter *sc = arg1;
6809 uint16_t mtus[NMTUS];
6811 rc = sysctl_wire_old_buffer(req, 0);
6815 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6819 t4_read_mtu_tbl(sc, mtus, NULL);
6821 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6822 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6823 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6824 mtus[14], mtus[15]);
6826 rc = sbuf_finish(sb);
6833 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6835 struct adapter *sc = arg1;
6838 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6839 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6840 static const char *tx_stats[MAX_PM_NSTATS] = {
6841 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6842 "Tx FIFO wait", NULL, "Tx latency"
6844 static const char *rx_stats[MAX_PM_NSTATS] = {
6845 "Read:", "Write bypass:", "Write mem:", "Flush:",
6846 " Rx FIFO wait", NULL, "Rx latency"
6849 rc = sysctl_wire_old_buffer(req, 0);
6853 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6857 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6858 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6860 sbuf_printf(sb, " Tx pcmds Tx bytes");
6861 for (i = 0; i < 4; i++) {
6862 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6866 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6867 for (i = 0; i < 4; i++) {
6868 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6872 if (chip_id(sc) > CHELSIO_T5) {
6874 "\n Total wait Total occupancy");
6875 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6877 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6881 MPASS(i < nitems(tx_stats));
6884 "\n Reads Total wait");
6885 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6887 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6891 rc = sbuf_finish(sb);
6898 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6900 struct adapter *sc = arg1;
6903 struct tp_rdma_stats stats;
6905 rc = sysctl_wire_old_buffer(req, 0);
6909 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6913 mtx_lock(&sc->reg_lock);
6914 t4_tp_get_rdma_stats(sc, &stats);
6915 mtx_unlock(&sc->reg_lock);
6917 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6918 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6920 rc = sbuf_finish(sb);
6927 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6929 struct adapter *sc = arg1;
6932 struct tp_tcp_stats v4, v6;
6934 rc = sysctl_wire_old_buffer(req, 0);
6938 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6942 mtx_lock(&sc->reg_lock);
6943 t4_tp_get_tcp_stats(sc, &v4, &v6);
6944 mtx_unlock(&sc->reg_lock);
6948 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6949 v4.tcp_out_rsts, v6.tcp_out_rsts);
6950 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6951 v4.tcp_in_segs, v6.tcp_in_segs);
6952 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6953 v4.tcp_out_segs, v6.tcp_out_segs);
6954 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6955 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6957 rc = sbuf_finish(sb);
6964 sysctl_tids(SYSCTL_HANDLER_ARGS)
6966 struct adapter *sc = arg1;
6969 struct tid_info *t = &sc->tids;
6971 rc = sysctl_wire_old_buffer(req, 0);
6975 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6980 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6985 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6986 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6989 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6990 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6993 sbuf_printf(sb, "TID range: %u-%u",
6994 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6998 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6999 sbuf_printf(sb, ", in use: %u\n",
7000 atomic_load_acq_int(&t->tids_in_use));
7004 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
7005 t->stid_base + t->nstids - 1, t->stids_in_use);
7009 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
7010 t->ftid_base + t->nftids - 1);
7014 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
7015 t->etid_base + t->netids - 1);
7018 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7019 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7020 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7022 rc = sbuf_finish(sb);
7029 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7031 struct adapter *sc = arg1;
7034 struct tp_err_stats stats;
7036 rc = sysctl_wire_old_buffer(req, 0);
7040 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7044 mtx_lock(&sc->reg_lock);
7045 t4_tp_get_err_stats(sc, &stats);
7046 mtx_unlock(&sc->reg_lock);
7048 if (sc->chip_params->nchan > 2) {
7049 sbuf_printf(sb, " channel 0 channel 1"
7050 " channel 2 channel 3\n");
7051 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7052 stats.mac_in_errs[0], stats.mac_in_errs[1],
7053 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7054 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7055 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7056 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7057 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7058 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7059 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7060 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7061 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7062 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7063 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7064 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7065 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7066 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7067 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7068 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7069 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7070 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7071 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7072 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7073 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7074 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7076 sbuf_printf(sb, " channel 0 channel 1\n");
7077 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7078 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7079 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7080 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7081 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7082 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7083 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7084 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7085 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7086 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7087 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7088 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7089 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7090 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7091 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7092 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7095 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7096 stats.ofld_no_neigh, stats.ofld_cong_defer);
7098 rc = sbuf_finish(sb);
7105 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7107 struct adapter *sc = arg1;
7108 struct tp_params *tpp = &sc->params.tp;
7112 mask = tpp->la_mask >> 16;
7113 rc = sysctl_handle_int(oidp, &mask, 0, req);
7114 if (rc != 0 || req->newptr == NULL)
7118 tpp->la_mask = mask << 16;
7119 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7131 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7137 uint64_t mask = (1ULL << f->width) - 1;
7138 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7139 ((uintmax_t)v >> f->start) & mask);
7141 if (line_size + len >= 79) {
7143 sbuf_printf(sb, "\n ");
7145 sbuf_printf(sb, "%s ", buf);
7146 line_size += len + 1;
7149 sbuf_printf(sb, "\n");
7152 static const struct field_desc tp_la0[] = {
7153 { "RcfOpCodeOut", 60, 4 },
7155 { "WcfState", 52, 4 },
7156 { "RcfOpcSrcOut", 50, 2 },
7157 { "CRxError", 49, 1 },
7158 { "ERxError", 48, 1 },
7159 { "SanityFailed", 47, 1 },
7160 { "SpuriousMsg", 46, 1 },
7161 { "FlushInputMsg", 45, 1 },
7162 { "FlushInputCpl", 44, 1 },
7163 { "RssUpBit", 43, 1 },
7164 { "RssFilterHit", 42, 1 },
7166 { "InitTcb", 31, 1 },
7167 { "LineNumber", 24, 7 },
7169 { "EdataOut", 22, 1 },
7171 { "CdataOut", 20, 1 },
7172 { "EreadPdu", 19, 1 },
7173 { "CreadPdu", 18, 1 },
7174 { "TunnelPkt", 17, 1 },
7175 { "RcfPeerFin", 16, 1 },
7176 { "RcfReasonOut", 12, 4 },
7177 { "TxCchannel", 10, 2 },
7178 { "RcfTxChannel", 8, 2 },
7179 { "RxEchannel", 6, 2 },
7180 { "RcfRxChannel", 5, 1 },
7181 { "RcfDataOutSrdy", 4, 1 },
7183 { "RxOoDvld", 2, 1 },
7184 { "RxCongestion", 1, 1 },
7185 { "TxCongestion", 0, 1 },
7189 static const struct field_desc tp_la1[] = {
7190 { "CplCmdIn", 56, 8 },
7191 { "CplCmdOut", 48, 8 },
7192 { "ESynOut", 47, 1 },
7193 { "EAckOut", 46, 1 },
7194 { "EFinOut", 45, 1 },
7195 { "ERstOut", 44, 1 },
7200 { "DataIn", 39, 1 },
7201 { "DataInVld", 38, 1 },
7203 { "RxBufEmpty", 36, 1 },
7205 { "RxFbCongestion", 34, 1 },
7206 { "TxFbCongestion", 33, 1 },
7207 { "TxPktSumSrdy", 32, 1 },
7208 { "RcfUlpType", 28, 4 },
7210 { "Ebypass", 26, 1 },
7212 { "Static0", 24, 1 },
7214 { "Cbypass", 22, 1 },
7216 { "CPktOut", 20, 1 },
7217 { "RxPagePoolFull", 18, 2 },
7218 { "RxLpbkPkt", 17, 1 },
7219 { "TxLpbkPkt", 16, 1 },
7220 { "RxVfValid", 15, 1 },
7221 { "SynLearned", 14, 1 },
7222 { "SetDelEntry", 13, 1 },
7223 { "SetInvEntry", 12, 1 },
7224 { "CpcmdDvld", 11, 1 },
7225 { "CpcmdSave", 10, 1 },
7226 { "RxPstructsFull", 8, 2 },
7227 { "EpcmdDvld", 7, 1 },
7228 { "EpcmdFlush", 6, 1 },
7229 { "EpcmdTrimPrefix", 5, 1 },
7230 { "EpcmdTrimPostfix", 4, 1 },
7231 { "ERssIp4Pkt", 3, 1 },
7232 { "ERssIp6Pkt", 2, 1 },
7233 { "ERssTcpUdpPkt", 1, 1 },
7234 { "ERssFceFipPkt", 0, 1 },
7238 static const struct field_desc tp_la2[] = {
7239 { "CplCmdIn", 56, 8 },
7240 { "MpsVfVld", 55, 1 },
7247 { "DataIn", 39, 1 },
7248 { "DataInVld", 38, 1 },
7250 { "RxBufEmpty", 36, 1 },
7252 { "RxFbCongestion", 34, 1 },
7253 { "TxFbCongestion", 33, 1 },
7254 { "TxPktSumSrdy", 32, 1 },
7255 { "RcfUlpType", 28, 4 },
7257 { "Ebypass", 26, 1 },
7259 { "Static0", 24, 1 },
7261 { "Cbypass", 22, 1 },
7263 { "CPktOut", 20, 1 },
7264 { "RxPagePoolFull", 18, 2 },
7265 { "RxLpbkPkt", 17, 1 },
7266 { "TxLpbkPkt", 16, 1 },
7267 { "RxVfValid", 15, 1 },
7268 { "SynLearned", 14, 1 },
7269 { "SetDelEntry", 13, 1 },
7270 { "SetInvEntry", 12, 1 },
7271 { "CpcmdDvld", 11, 1 },
7272 { "CpcmdSave", 10, 1 },
7273 { "RxPstructsFull", 8, 2 },
7274 { "EpcmdDvld", 7, 1 },
7275 { "EpcmdFlush", 6, 1 },
7276 { "EpcmdTrimPrefix", 5, 1 },
7277 { "EpcmdTrimPostfix", 4, 1 },
7278 { "ERssIp4Pkt", 3, 1 },
7279 { "ERssIp6Pkt", 2, 1 },
7280 { "ERssTcpUdpPkt", 1, 1 },
7281 { "ERssFceFipPkt", 0, 1 },
7286 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7289 field_desc_show(sb, *p, tp_la0);
7293 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7297 sbuf_printf(sb, "\n");
7298 field_desc_show(sb, p[0], tp_la0);
7299 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7300 field_desc_show(sb, p[1], tp_la0);
7304 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7308 sbuf_printf(sb, "\n");
7309 field_desc_show(sb, p[0], tp_la0);
7310 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7311 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7315 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7317 struct adapter *sc = arg1;
7322 void (*show_func)(struct sbuf *, uint64_t *, int);
7324 rc = sysctl_wire_old_buffer(req, 0);
7328 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7332 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7334 t4_tp_read_la(sc, buf, NULL);
7337 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7340 show_func = tp_la_show2;
7344 show_func = tp_la_show3;
7348 show_func = tp_la_show;
7351 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7352 (*show_func)(sb, p, i);
7354 rc = sbuf_finish(sb);
7361 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7363 struct adapter *sc = arg1;
7366 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7368 rc = sysctl_wire_old_buffer(req, 0);
7372 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7376 t4_get_chan_txrate(sc, nrate, orate);
7378 if (sc->chip_params->nchan > 2) {
7379 sbuf_printf(sb, " channel 0 channel 1"
7380 " channel 2 channel 3\n");
7381 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7382 nrate[0], nrate[1], nrate[2], nrate[3]);
7383 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7384 orate[0], orate[1], orate[2], orate[3]);
7386 sbuf_printf(sb, " channel 0 channel 1\n");
7387 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7388 nrate[0], nrate[1]);
7389 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7390 orate[0], orate[1]);
7393 rc = sbuf_finish(sb);
7400 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7402 struct adapter *sc = arg1;
7407 rc = sysctl_wire_old_buffer(req, 0);
7411 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7415 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7418 t4_ulprx_read_la(sc, buf);
7421 sbuf_printf(sb, " Pcmd Type Message"
7423 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7424 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7425 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7428 rc = sbuf_finish(sb);
7435 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7437 struct adapter *sc = arg1;
7441 rc = sysctl_wire_old_buffer(req, 0);
7445 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7449 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7450 if (G_STATSOURCE_T5(v) == 7) {
7451 if (G_STATMODE(v) == 0) {
7452 sbuf_printf(sb, "total %d, incomplete %d",
7453 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7454 t4_read_reg(sc, A_SGE_STAT_MATCH));
7455 } else if (G_STATMODE(v) == 1) {
7456 sbuf_printf(sb, "total %d, data overflow %d",
7457 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7458 t4_read_reg(sc, A_SGE_STAT_MATCH));
7461 rc = sbuf_finish(sb);
7468 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7470 struct adapter *sc = arg1;
7471 struct tx_sched_class *tc;
7472 struct t4_sched_class_params p;
7474 int i, rc, port_id, flags, mbps, gbps;
7476 rc = sysctl_wire_old_buffer(req, 0);
7480 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7484 port_id = arg2 >> 16;
7485 MPASS(port_id < sc->params.nports);
7486 MPASS(sc->port[port_id] != NULL);
7488 MPASS(i < sc->chip_params->nsched_cls);
7489 tc = &sc->port[port_id]->tc[i];
7491 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7497 end_synchronized_op(sc, LOCK_HELD);
7499 if ((flags & TX_SC_OK) == 0) {
7500 sbuf_printf(sb, "none");
7504 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7505 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7507 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7508 sbuf_printf(sb, "cl-rl");
7509 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7510 sbuf_printf(sb, "ch-rl");
7516 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7517 /* XXX: top speed or actual link speed? */
7518 gbps = port_top_speed(sc->port[port_id]);
7519 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7521 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7522 switch (p.rateunit) {
7523 case SCHED_CLASS_RATEUNIT_BITS:
7524 mbps = p.maxrate / 1000;
7525 gbps = p.maxrate / 1000000;
7526 if (p.maxrate == gbps * 1000000)
7527 sbuf_printf(sb, " %uGbps", gbps);
7528 else if (p.maxrate == mbps * 1000)
7529 sbuf_printf(sb, " %uMbps", mbps);
7531 sbuf_printf(sb, " %uKbps", p.maxrate);
7533 case SCHED_CLASS_RATEUNIT_PKTS:
7534 sbuf_printf(sb, " %upps", p.maxrate);
7543 case SCHED_CLASS_MODE_CLASS:
7544 sbuf_printf(sb, " aggregate");
7546 case SCHED_CLASS_MODE_FLOW:
7547 sbuf_printf(sb, " per-flow");
7556 rc = sbuf_finish(sb);
7565 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7567 u_int rem = val % factor;
7570 snprintf(buf, len, "%u", val / factor);
7572 while (rem % 10 == 0)
7574 snprintf(buf, len, "%u.%u", val / factor, rem);
7579 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7581 struct adapter *sc = arg1;
7584 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7586 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7590 re = G_TIMERRESOLUTION(res);
7593 /* TCP timestamp tick */
7594 re = G_TIMESTAMPRESOLUTION(res);
7598 re = G_DELAYEDACKRESOLUTION(res);
7604 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7606 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7610 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7612 struct adapter *sc = arg1;
7613 u_int res, dack_re, v;
7614 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7616 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7617 dack_re = G_DELAYEDACKRESOLUTION(res);
7618 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7620 return (sysctl_handle_int(oidp, &v, 0, req));
7624 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7626 struct adapter *sc = arg1;
7629 u_long tp_tick_us, v;
7630 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7632 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7633 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7634 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7635 reg == A_TP_FINWAIT2_TIMER);
7637 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7638 tp_tick_us = (cclk_ps << tre) / 1000000;
7640 if (reg == A_TP_INIT_SRTT)
7641 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7643 v = tp_tick_us * t4_read_reg(sc, reg);
7645 return (sysctl_handle_long(oidp, &v, 0, req));
7650 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7654 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7655 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7657 if (fconf & F_FRAGMENTATION)
7658 mode |= T4_FILTER_IP_FRAGMENT;
7660 if (fconf & F_MPSHITTYPE)
7661 mode |= T4_FILTER_MPS_HIT_TYPE;
7663 if (fconf & F_MACMATCH)
7664 mode |= T4_FILTER_MAC_IDX;
7666 if (fconf & F_ETHERTYPE)
7667 mode |= T4_FILTER_ETH_TYPE;
7669 if (fconf & F_PROTOCOL)
7670 mode |= T4_FILTER_IP_PROTO;
7673 mode |= T4_FILTER_IP_TOS;
7676 mode |= T4_FILTER_VLAN;
7678 if (fconf & F_VNIC_ID) {
7679 mode |= T4_FILTER_VNIC;
7681 mode |= T4_FILTER_IC_VNIC;
7685 mode |= T4_FILTER_PORT;
7688 mode |= T4_FILTER_FCoE;
7694 mode_to_fconf(uint32_t mode)
7698 if (mode & T4_FILTER_IP_FRAGMENT)
7699 fconf |= F_FRAGMENTATION;
7701 if (mode & T4_FILTER_MPS_HIT_TYPE)
7702 fconf |= F_MPSHITTYPE;
7704 if (mode & T4_FILTER_MAC_IDX)
7705 fconf |= F_MACMATCH;
7707 if (mode & T4_FILTER_ETH_TYPE)
7708 fconf |= F_ETHERTYPE;
7710 if (mode & T4_FILTER_IP_PROTO)
7711 fconf |= F_PROTOCOL;
7713 if (mode & T4_FILTER_IP_TOS)
7716 if (mode & T4_FILTER_VLAN)
7719 if (mode & T4_FILTER_VNIC)
7722 if (mode & T4_FILTER_PORT)
7725 if (mode & T4_FILTER_FCoE)
7732 mode_to_iconf(uint32_t mode)
7735 if (mode & T4_FILTER_IC_VNIC)
7740 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7741 struct t4_filter_specification *fs)
7743 struct tp_params *tpp = &sc->params.tp;
7746 if (fs->val.frag || fs->mask.frag)
7747 fconf |= F_FRAGMENTATION;
7749 if (fs->val.matchtype || fs->mask.matchtype)
7750 fconf |= F_MPSHITTYPE;
7752 if (fs->val.macidx || fs->mask.macidx)
7753 fconf |= F_MACMATCH;
7755 if (fs->val.ethtype || fs->mask.ethtype)
7756 fconf |= F_ETHERTYPE;
7758 if (fs->val.proto || fs->mask.proto)
7759 fconf |= F_PROTOCOL;
7761 if (fs->val.tos || fs->mask.tos)
7764 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7767 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7769 if (tpp->ingress_config & F_VNIC)
7773 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7775 if ((tpp->ingress_config & F_VNIC) == 0)
7779 if (fs->val.iport || fs->mask.iport)
7782 if (fs->val.fcoe || fs->mask.fcoe)
7785 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7792 get_filter_mode(struct adapter *sc, uint32_t *mode)
7794 struct tp_params *tpp = &sc->params.tp;
7797 * We trust the cached values of the relevant TP registers. This means
7798 * things work reliably only if writes to those registers are always via
7799 * t4_set_filter_mode.
7801 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7807 set_filter_mode(struct adapter *sc, uint32_t mode)
7809 struct tp_params *tpp = &sc->params.tp;
7810 uint32_t fconf, iconf;
7813 iconf = mode_to_iconf(mode);
7814 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7816 * For now we just complain if A_TP_INGRESS_CONFIG is not
7817 * already set to the correct value for the requested filter
7818 * mode. It's not clear if it's safe to write to this register
7819 * on the fly. (And we trust the cached value of the register).
7824 fconf = mode_to_fconf(mode);
7826 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7831 if (sc->tids.ftids_in_use > 0) {
7837 if (uld_active(sc, ULD_TOM)) {
7843 rc = -t4_set_filter_mode(sc, fconf);
7845 end_synchronized_op(sc, LOCK_HELD);
7849 static inline uint64_t
7850 get_filter_hits(struct adapter *sc, uint32_t fid)
7854 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7855 (fid + sc->tids.ftid_base) * TCB_SIZE;
7860 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7861 return (be64toh(hits));
7865 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7866 return (be32toh(hits));
7871 get_filter(struct adapter *sc, struct t4_filter *t)
7873 int i, rc, nfilters = sc->tids.nftids;
7874 struct filter_entry *f;
7876 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7881 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7882 t->idx >= nfilters) {
7883 t->idx = 0xffffffff;
7887 f = &sc->tids.ftid_tab[t->idx];
7888 for (i = t->idx; i < nfilters; i++, f++) {
7891 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7892 t->smtidx = f->smtidx;
7894 t->hits = get_filter_hits(sc, t->idx);
7896 t->hits = UINT64_MAX;
7903 t->idx = 0xffffffff;
7905 end_synchronized_op(sc, LOCK_HELD);
7910 set_filter(struct adapter *sc, struct t4_filter *t)
7912 unsigned int nfilters, nports;
7913 struct filter_entry *f;
7916 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7920 nfilters = sc->tids.nftids;
7921 nports = sc->params.nports;
7923 if (nfilters == 0) {
7928 if (t->idx >= nfilters) {
7933 /* Validate against the global filter mode and ingress config */
7934 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7938 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7943 if (t->fs.val.iport >= nports) {
7948 /* Can't specify an iq if not steering to it */
7949 if (!t->fs.dirsteer && t->fs.iq) {
7954 /* IPv6 filter idx must be 4 aligned */
7955 if (t->fs.type == 1 &&
7956 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7961 if (!(sc->flags & FULL_INIT_DONE) &&
7962 ((rc = adapter_full_init(sc)) != 0))
7965 if (sc->tids.ftid_tab == NULL) {
7966 KASSERT(sc->tids.ftids_in_use == 0,
7967 ("%s: no memory allocated but filters_in_use > 0",
7970 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7971 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7972 if (sc->tids.ftid_tab == NULL) {
7976 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7979 for (i = 0; i < 4; i++) {
7980 f = &sc->tids.ftid_tab[t->idx + i];
7982 if (f->pending || f->valid) {
7991 if (t->fs.type == 0)
7995 f = &sc->tids.ftid_tab[t->idx];
7998 rc = set_filter_wr(sc, t->idx);
8000 end_synchronized_op(sc, 0);
8003 mtx_lock(&sc->tids.ftid_lock);
8005 if (f->pending == 0) {
8006 rc = f->valid ? 0 : EIO;
8010 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8011 PCATCH, "t4setfw", 0)) {
8016 mtx_unlock(&sc->tids.ftid_lock);
8022 del_filter(struct adapter *sc, struct t4_filter *t)
8024 unsigned int nfilters;
8025 struct filter_entry *f;
8028 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8032 nfilters = sc->tids.nftids;
8034 if (nfilters == 0) {
8039 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8040 t->idx >= nfilters) {
8045 if (!(sc->flags & FULL_INIT_DONE)) {
8050 f = &sc->tids.ftid_tab[t->idx];
8062 t->fs = f->fs; /* extra info for the caller */
8063 rc = del_filter_wr(sc, t->idx);
8067 end_synchronized_op(sc, 0);
8070 mtx_lock(&sc->tids.ftid_lock);
8072 if (f->pending == 0) {
8073 rc = f->valid ? EIO : 0;
8077 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8078 PCATCH, "t4delfw", 0)) {
8083 mtx_unlock(&sc->tids.ftid_lock);
8090 clear_filter(struct filter_entry *f)
8093 t4_l2t_release(f->l2t);
8095 bzero(f, sizeof (*f));
8099 set_filter_wr(struct adapter *sc, int fidx)
8101 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8102 struct fw_filter_wr *fwr;
8103 unsigned int ftid, vnic_vld, vnic_vld_mask;
8104 struct wrq_cookie cookie;
8106 ASSERT_SYNCHRONIZED_OP(sc);
8108 if (f->fs.newdmac || f->fs.newvlan) {
8109 /* This filter needs an L2T entry; allocate one. */
8110 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8113 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8115 t4_l2t_release(f->l2t);
8121 /* Already validated against fconf, iconf */
8122 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8123 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8124 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8128 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8133 ftid = sc->tids.ftid_base + fidx;
8135 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8138 bzero(fwr, sizeof(*fwr));
8140 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8141 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8143 htobe32(V_FW_FILTER_WR_TID(ftid) |
8144 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8145 V_FW_FILTER_WR_NOREPLY(0) |
8146 V_FW_FILTER_WR_IQ(f->fs.iq));
8147 fwr->del_filter_to_l2tix =
8148 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8149 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8150 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8151 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8152 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8153 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8154 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8155 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8156 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8157 f->fs.newvlan == VLAN_REWRITE) |
8158 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8159 f->fs.newvlan == VLAN_REWRITE) |
8160 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8161 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8162 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8163 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8164 fwr->ethtype = htobe16(f->fs.val.ethtype);
8165 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8166 fwr->frag_to_ovlan_vldm =
8167 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8168 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8169 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8170 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8171 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8172 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8174 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8175 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8176 fwr->maci_to_matchtypem =
8177 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8178 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8179 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8180 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8181 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8182 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8183 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8184 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8185 fwr->ptcl = f->fs.val.proto;
8186 fwr->ptclm = f->fs.mask.proto;
8187 fwr->ttyp = f->fs.val.tos;
8188 fwr->ttypm = f->fs.mask.tos;
8189 fwr->ivlan = htobe16(f->fs.val.vlan);
8190 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8191 fwr->ovlan = htobe16(f->fs.val.vnic);
8192 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8193 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8194 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8195 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8196 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8197 fwr->lp = htobe16(f->fs.val.dport);
8198 fwr->lpm = htobe16(f->fs.mask.dport);
8199 fwr->fp = htobe16(f->fs.val.sport);
8200 fwr->fpm = htobe16(f->fs.mask.sport);
8202 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8205 sc->tids.ftids_in_use++;
8207 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8212 del_filter_wr(struct adapter *sc, int fidx)
8214 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8215 struct fw_filter_wr *fwr;
8217 struct wrq_cookie cookie;
8219 ftid = sc->tids.ftid_base + fidx;
8221 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8224 bzero(fwr, sizeof (*fwr));
8226 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8229 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8234 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8236 struct adapter *sc = iq->adapter;
8237 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8238 unsigned int idx = GET_TID(rpl);
8240 struct filter_entry *f;
8242 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8244 MPASS(iq == &sc->sge.fwq);
8245 MPASS(is_ftid(sc, idx));
8247 idx -= sc->tids.ftid_base;
8248 f = &sc->tids.ftid_tab[idx];
8249 rc = G_COOKIE(rpl->cookie);
8251 mtx_lock(&sc->tids.ftid_lock);
8252 if (rc == FW_FILTER_WR_FLT_ADDED) {
8253 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8255 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8256 f->pending = 0; /* asynchronous setup completed */
8259 if (rc != FW_FILTER_WR_FLT_DELETED) {
8260 /* Add or delete failed, display an error */
8262 "filter %u setup failed with error %u\n",
8267 sc->tids.ftids_in_use--;
8269 wakeup(&sc->tids.ftid_tab);
8270 mtx_unlock(&sc->tids.ftid_lock);
8276 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8279 MPASS(iq->set_tcb_rpl != NULL);
8280 return (iq->set_tcb_rpl(iq, rss, m));
8284 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8287 MPASS(iq->l2t_write_rpl != NULL);
8288 return (iq->l2t_write_rpl(iq, rss, m));
8292 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8296 if (cntxt->cid > M_CTXTQID)
8299 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8300 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8303 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8307 if (sc->flags & FW_OK) {
8308 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8315 * Read via firmware failed or wasn't even attempted. Read directly via
8318 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8320 end_synchronized_op(sc, 0);
8325 load_fw(struct adapter *sc, struct t4_data *fw)
8330 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8334 if (sc->flags & FULL_INIT_DONE) {
8339 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8340 if (fw_data == NULL) {
8345 rc = copyin(fw->data, fw_data, fw->len);
8347 rc = -t4_load_fw(sc, fw_data, fw->len);
8349 free(fw_data, M_CXGBE);
8351 end_synchronized_op(sc, 0);
8355 #define MAX_READ_BUF_SIZE (128 * 1024)
8357 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8359 uint32_t addr, remaining, n;
8364 rc = validate_mem_range(sc, mr->addr, mr->len);
8368 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8370 remaining = mr->len;
8371 dst = (void *)mr->data;
8374 n = min(remaining, MAX_READ_BUF_SIZE);
8375 read_via_memwin(sc, 2, addr, buf, n);
8377 rc = copyout(buf, dst, n);
8389 #undef MAX_READ_BUF_SIZE
8392 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8396 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8399 if (i2cd->len > sizeof(i2cd->data))
8402 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8405 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8406 i2cd->offset, i2cd->len, &i2cd->data[0]);
8407 end_synchronized_op(sc, 0);
8413 in_range(int val, int lo, int hi)
8416 return (val < 0 || (val <= hi && val >= lo));
8420 set_sched_class_config(struct adapter *sc, int minmax)
8427 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8430 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8431 end_synchronized_op(sc, 0);
8437 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8440 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8441 struct port_info *pi;
8442 struct tx_sched_class *tc;
8444 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8445 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8446 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8447 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8448 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8449 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8453 if (p->mode == SCHED_CLASS_MODE_CLASS)
8454 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8455 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8456 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8460 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8461 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8462 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8463 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8467 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8468 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8469 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8470 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8474 /* Vet our parameters ... */
8475 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8478 pi = sc->port[sc->chan_map[p->channel]];
8481 MPASS(pi->tx_chan == p->channel);
8482 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8484 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8485 !in_range(p->minrate, 0, top_speed) ||
8486 !in_range(p->maxrate, 0, top_speed) ||
8487 !in_range(p->weight, 0, 100))
8491 * Translate any unset parameters into the firmware's
8492 * nomenclature and/or fail the call if the parameters
8495 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8500 if (p->maxrate < 0) {
8501 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8502 p->level == SCHED_CLASS_LEVEL_CH_RL)
8507 if (p->weight < 0) {
8508 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8513 if (p->pktsize < 0) {
8514 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8515 p->level == SCHED_CLASS_LEVEL_CH_RL)
8521 rc = begin_synchronized_op(sc, NULL,
8522 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8525 tc = &pi->tc[p->cl];
8527 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8528 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8529 p->weight, p->pktsize, sleep_ok);
8531 tc->flags |= TX_SC_OK;
8534 * Unknown state at this point, see tc->params for what was
8537 tc->flags &= ~TX_SC_OK;
8539 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8545 set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8548 if (p->type != SCHED_CLASS_TYPE_PACKET)
8551 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8552 return (set_sched_class_config(sc, p->u.config.minmax));
8554 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8555 return (set_sched_class_params(sc, &p->u.params, 1));
8561 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8563 struct port_info *pi = NULL;
8565 struct sge_txq *txq;
8566 uint32_t fw_mnem, fw_queue, fw_class;
8569 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8573 if (p->port >= sc->params.nports) {
8578 /* XXX: Only supported for the main VI. */
8579 pi = sc->port[p->port];
8581 if (!(vi->flags & VI_INIT_DONE)) {
8582 /* tx queues not set up yet */
8587 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8588 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8594 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8595 * Scheduling Class in this case).
8597 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8598 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8599 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8602 * If op.queue is non-negative, then we're only changing the scheduling
8603 * on a single specified TX queue.
8605 if (p->queue >= 0) {
8606 txq = &sc->sge.txq[vi->first_txq + p->queue];
8607 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8608 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8614 * Change the scheduling on all the TX queues for the
8617 for_each_txq(vi, i, txq) {
8618 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8619 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8627 end_synchronized_op(sc, 0);
8632 t4_os_find_pci_capability(struct adapter *sc, int cap)
8636 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8640 t4_os_pci_save_state(struct adapter *sc)
8643 struct pci_devinfo *dinfo;
8646 dinfo = device_get_ivars(dev);
8648 pci_cfg_save(dev, dinfo, 0);
8653 t4_os_pci_restore_state(struct adapter *sc)
8656 struct pci_devinfo *dinfo;
8659 dinfo = device_get_ivars(dev);
8661 pci_cfg_restore(dev, dinfo);
8666 t4_os_portmod_changed(const struct adapter *sc, int idx)
8668 struct port_info *pi = sc->port[idx];
8672 static const char *mod_str[] = {
8673 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8676 for_each_vi(pi, v, vi) {
8677 build_medialist(pi, &vi->media);
8680 ifp = pi->vi[0].ifp;
8681 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8682 if_printf(ifp, "transceiver unplugged.\n");
8683 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8684 if_printf(ifp, "unknown transceiver inserted.\n");
8685 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8686 if_printf(ifp, "unsupported transceiver inserted.\n");
8687 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8688 if_printf(ifp, "%s transceiver inserted.\n",
8689 mod_str[pi->mod_type]);
8691 if_printf(ifp, "transceiver (type %d) inserted.\n",
8697 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8699 struct port_info *pi = sc->port[idx];
8708 pi->linkdnrc = reason;
8710 for_each_vi(pi, v, vi) {
8716 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8717 if_link_state_change(ifp, LINK_STATE_UP);
8719 if_link_state_change(ifp, LINK_STATE_DOWN);
8725 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8729 sx_slock(&t4_list_lock);
8730 SLIST_FOREACH(sc, &t4_list, link) {
8732 * func should not make any assumptions about what state sc is
8733 * in - the only guarantee is that sc->sc_lock is a valid lock.
8737 sx_sunlock(&t4_list_lock);
8741 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8745 struct adapter *sc = dev->si_drv1;
8747 rc = priv_check(td, PRIV_DRIVER);
8752 case CHELSIO_T4_GETREG: {
8753 struct t4_reg *edata = (struct t4_reg *)data;
8755 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8758 if (edata->size == 4)
8759 edata->val = t4_read_reg(sc, edata->addr);
8760 else if (edata->size == 8)
8761 edata->val = t4_read_reg64(sc, edata->addr);
8767 case CHELSIO_T4_SETREG: {
8768 struct t4_reg *edata = (struct t4_reg *)data;
8770 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8773 if (edata->size == 4) {
8774 if (edata->val & 0xffffffff00000000)
8776 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8777 } else if (edata->size == 8)
8778 t4_write_reg64(sc, edata->addr, edata->val);
8783 case CHELSIO_T4_REGDUMP: {
8784 struct t4_regdump *regs = (struct t4_regdump *)data;
8785 int reglen = t4_get_regs_len(sc);
8788 if (regs->len < reglen) {
8789 regs->len = reglen; /* hint to the caller */
8794 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8795 get_regs(sc, regs, buf);
8796 rc = copyout(buf, regs->data, reglen);
8800 case CHELSIO_T4_GET_FILTER_MODE:
8801 rc = get_filter_mode(sc, (uint32_t *)data);
8803 case CHELSIO_T4_SET_FILTER_MODE:
8804 rc = set_filter_mode(sc, *(uint32_t *)data);
8806 case CHELSIO_T4_GET_FILTER:
8807 rc = get_filter(sc, (struct t4_filter *)data);
8809 case CHELSIO_T4_SET_FILTER:
8810 rc = set_filter(sc, (struct t4_filter *)data);
8812 case CHELSIO_T4_DEL_FILTER:
8813 rc = del_filter(sc, (struct t4_filter *)data);
8815 case CHELSIO_T4_GET_SGE_CONTEXT:
8816 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8818 case CHELSIO_T4_LOAD_FW:
8819 rc = load_fw(sc, (struct t4_data *)data);
8821 case CHELSIO_T4_GET_MEM:
8822 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8824 case CHELSIO_T4_GET_I2C:
8825 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8827 case CHELSIO_T4_CLEAR_STATS: {
8829 u_int port_id = *(uint32_t *)data;
8830 struct port_info *pi;
8833 if (port_id >= sc->params.nports)
8835 pi = sc->port[port_id];
8838 t4_clr_port_stats(sc, pi->tx_chan);
8839 pi->tx_parse_error = 0;
8840 mtx_lock(&sc->reg_lock);
8841 for_each_vi(pi, v, vi) {
8842 if (vi->flags & VI_INIT_DONE)
8843 t4_clr_vi_stats(sc, vi->viid);
8845 mtx_unlock(&sc->reg_lock);
8848 * Since this command accepts a port, clear stats for
8849 * all VIs on this port.
8851 for_each_vi(pi, v, vi) {
8852 if (vi->flags & VI_INIT_DONE) {
8853 struct sge_rxq *rxq;
8854 struct sge_txq *txq;
8855 struct sge_wrq *wrq;
8857 for_each_rxq(vi, i, rxq) {
8858 #if defined(INET) || defined(INET6)
8859 rxq->lro.lro_queued = 0;
8860 rxq->lro.lro_flushed = 0;
8863 rxq->vlan_extraction = 0;
8866 for_each_txq(vi, i, txq) {
8869 txq->vlan_insertion = 0;
8873 txq->txpkts0_wrs = 0;
8874 txq->txpkts1_wrs = 0;
8875 txq->txpkts0_pkts = 0;
8876 txq->txpkts1_pkts = 0;
8877 mp_ring_reset_stats(txq->r);
8881 /* nothing to clear for each ofld_rxq */
8883 for_each_ofld_txq(vi, i, wrq) {
8884 wrq->tx_wrs_direct = 0;
8885 wrq->tx_wrs_copied = 0;
8889 if (IS_MAIN_VI(vi)) {
8890 wrq = &sc->sge.ctrlq[pi->port_id];
8891 wrq->tx_wrs_direct = 0;
8892 wrq->tx_wrs_copied = 0;
8898 case CHELSIO_T4_SCHED_CLASS:
8899 rc = set_sched_class(sc, (struct t4_sched_params *)data);
8901 case CHELSIO_T4_SCHED_QUEUE:
8902 rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
8904 case CHELSIO_T4_GET_TRACER:
8905 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8907 case CHELSIO_T4_SET_TRACER:
8908 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8918 t4_db_full(struct adapter *sc)
8921 CXGBE_UNIMPLEMENTED(__func__);
8925 t4_db_dropped(struct adapter *sc)
8928 CXGBE_UNIMPLEMENTED(__func__);
8933 toe_capability(struct vi_info *vi, int enable)
8936 struct port_info *pi = vi->pi;
8937 struct adapter *sc = pi->adapter;
8939 ASSERT_SYNCHRONIZED_OP(sc);
8941 if (!is_offload(sc))
8945 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8946 /* TOE is already enabled. */
8951 * We need the port's queues around so that we're able to send
8952 * and receive CPLs to/from the TOE even if the ifnet for this
8953 * port has never been UP'd administratively.
8955 if (!(vi->flags & VI_INIT_DONE)) {
8956 rc = vi_full_init(vi);
8960 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8961 rc = vi_full_init(&pi->vi[0]);
8966 if (isset(&sc->offload_map, pi->port_id)) {
8967 /* TOE is enabled on another VI of this port. */
8972 if (!uld_active(sc, ULD_TOM)) {
8973 rc = t4_activate_uld(sc, ULD_TOM);
8976 "You must kldload t4_tom.ko before trying "
8977 "to enable TOE on a cxgbe interface.\n");
8981 KASSERT(sc->tom_softc != NULL,
8982 ("%s: TOM activated but softc NULL", __func__));
8983 KASSERT(uld_active(sc, ULD_TOM),
8984 ("%s: TOM activated but flag not set", __func__));
8987 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8988 if (!uld_active(sc, ULD_IWARP))
8989 (void) t4_activate_uld(sc, ULD_IWARP);
8990 if (!uld_active(sc, ULD_ISCSI))
8991 (void) t4_activate_uld(sc, ULD_ISCSI);
8994 setbit(&sc->offload_map, pi->port_id);
8998 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9001 KASSERT(uld_active(sc, ULD_TOM),
9002 ("%s: TOM never initialized?", __func__));
9003 clrbit(&sc->offload_map, pi->port_id);
9010 * Add an upper layer driver to the global list.
9013 t4_register_uld(struct uld_info *ui)
9018 sx_xlock(&t4_uld_list_lock);
9019 SLIST_FOREACH(u, &t4_uld_list, link) {
9020 if (u->uld_id == ui->uld_id) {
9026 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9029 sx_xunlock(&t4_uld_list_lock);
9034 t4_unregister_uld(struct uld_info *ui)
9039 sx_xlock(&t4_uld_list_lock);
9041 SLIST_FOREACH(u, &t4_uld_list, link) {
9043 if (ui->refcount > 0) {
9048 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9054 sx_xunlock(&t4_uld_list_lock);
9059 t4_activate_uld(struct adapter *sc, int id)
9062 struct uld_info *ui;
9064 ASSERT_SYNCHRONIZED_OP(sc);
9066 if (id < 0 || id > ULD_MAX)
9068 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9070 sx_slock(&t4_uld_list_lock);
9072 SLIST_FOREACH(ui, &t4_uld_list, link) {
9073 if (ui->uld_id == id) {
9074 if (!(sc->flags & FULL_INIT_DONE)) {
9075 rc = adapter_full_init(sc);
9080 rc = ui->activate(sc);
9082 setbit(&sc->active_ulds, id);
9089 sx_sunlock(&t4_uld_list_lock);
9095 t4_deactivate_uld(struct adapter *sc, int id)
9098 struct uld_info *ui;
9100 ASSERT_SYNCHRONIZED_OP(sc);
9102 if (id < 0 || id > ULD_MAX)
9106 sx_slock(&t4_uld_list_lock);
9108 SLIST_FOREACH(ui, &t4_uld_list, link) {
9109 if (ui->uld_id == id) {
9110 rc = ui->deactivate(sc);
9112 clrbit(&sc->active_ulds, id);
9119 sx_sunlock(&t4_uld_list_lock);
9125 uld_active(struct adapter *sc, int uld_id)
9128 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9130 return (isset(&sc->active_ulds, uld_id));
9135 * Come up with reasonable defaults for some of the tunables, provided they're
9136 * not set by the user (in which case we'll use the values as is).
9139 tweak_tunables(void)
9141 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9143 if (t4_ntxq10g < 1) {
9145 t4_ntxq10g = rss_getnumbuckets();
9147 t4_ntxq10g = min(nc, NTXQ_10G);
9151 if (t4_ntxq1g < 1) {
9153 /* XXX: way too many for 1GbE? */
9154 t4_ntxq1g = rss_getnumbuckets();
9156 t4_ntxq1g = min(nc, NTXQ_1G);
9161 t4_ntxq_vi = min(nc, NTXQ_VI);
9163 if (t4_nrxq10g < 1) {
9165 t4_nrxq10g = rss_getnumbuckets();
9167 t4_nrxq10g = min(nc, NRXQ_10G);
9171 if (t4_nrxq1g < 1) {
9173 /* XXX: way too many for 1GbE? */
9174 t4_nrxq1g = rss_getnumbuckets();
9176 t4_nrxq1g = min(nc, NRXQ_1G);
9181 t4_nrxq_vi = min(nc, NRXQ_VI);
9184 if (t4_nofldtxq10g < 1)
9185 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9187 if (t4_nofldtxq1g < 1)
9188 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9190 if (t4_nofldtxq_vi < 1)
9191 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9193 if (t4_nofldrxq10g < 1)
9194 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9196 if (t4_nofldrxq1g < 1)
9197 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9199 if (t4_nofldrxq_vi < 1)
9200 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9202 if (t4_toecaps_allowed == -1)
9203 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9205 if (t4_rdmacaps_allowed == -1) {
9206 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9207 FW_CAPS_CONFIG_RDMA_RDMAC;
9210 if (t4_iscsicaps_allowed == -1) {
9211 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9212 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9213 FW_CAPS_CONFIG_ISCSI_T10DIF;
9216 if (t4_toecaps_allowed == -1)
9217 t4_toecaps_allowed = 0;
9219 if (t4_rdmacaps_allowed == -1)
9220 t4_rdmacaps_allowed = 0;
9222 if (t4_iscsicaps_allowed == -1)
9223 t4_iscsicaps_allowed = 0;
9227 if (t4_nnmtxq_vi < 1)
9228 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9230 if (t4_nnmrxq_vi < 1)
9231 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9234 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9235 t4_tmr_idx_10g = TMR_IDX_10G;
9237 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9238 t4_pktc_idx_10g = PKTC_IDX_10G;
9240 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9241 t4_tmr_idx_1g = TMR_IDX_1G;
9243 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9244 t4_pktc_idx_1g = PKTC_IDX_1G;
9246 if (t4_qsize_txq < 128)
9249 if (t4_qsize_rxq < 128)
9251 while (t4_qsize_rxq & 7)
9254 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9259 t4_dump_tcb(struct adapter *sc, int tid)
9261 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9263 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9264 save = t4_read_reg(sc, reg);
9265 base = sc->memwin[2].mw_base;
9267 /* Dump TCB for the tid */
9268 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9269 tcb_addr += tid * TCB_SIZE;
9273 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9275 pf = V_PFNUM(sc->pf);
9276 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9278 t4_write_reg(sc, reg, win_pos | pf);
9279 t4_read_reg(sc, reg);
9281 off = tcb_addr - win_pos;
9282 for (i = 0; i < 4; i++) {
9284 for (j = 0; j < 8; j++, off += 4)
9285 buf[j] = htonl(t4_read_reg(sc, base + off));
9287 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9288 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9292 t4_write_reg(sc, reg, save);
9293 t4_read_reg(sc, reg);
9297 t4_dump_devlog(struct adapter *sc)
9299 struct devlog_params *dparams = &sc->params.devlog;
9300 struct fw_devlog_e e;
9301 int i, first, j, m, nentries, rc;
9302 uint64_t ftstamp = UINT64_MAX;
9304 if (dparams->start == 0) {
9305 db_printf("devlog params not valid\n");
9309 nentries = dparams->size / sizeof(struct fw_devlog_e);
9310 m = fwmtype_to_hwmtype(dparams->memtype);
9312 /* Find the first entry. */
9314 for (i = 0; i < nentries && !db_pager_quit; i++) {
9315 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9316 sizeof(e), (void *)&e);
9320 if (e.timestamp == 0)
9323 e.timestamp = be64toh(e.timestamp);
9324 if (e.timestamp < ftstamp) {
9325 ftstamp = e.timestamp;
9335 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9336 sizeof(e), (void *)&e);
9340 if (e.timestamp == 0)
9343 e.timestamp = be64toh(e.timestamp);
9344 e.seqno = be32toh(e.seqno);
9345 for (j = 0; j < 8; j++)
9346 e.params[j] = be32toh(e.params[j]);
9348 db_printf("%10d %15ju %8s %8s ",
9349 e.seqno, e.timestamp,
9350 (e.level < nitems(devlog_level_strings) ?
9351 devlog_level_strings[e.level] : "UNKNOWN"),
9352 (e.facility < nitems(devlog_facility_strings) ?
9353 devlog_facility_strings[e.facility] : "UNKNOWN"));
9354 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9355 e.params[3], e.params[4], e.params[5], e.params[6],
9358 if (++i == nentries)
9360 } while (i != first && !db_pager_quit);
9363 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9364 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9366 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9373 t = db_read_token();
9375 dev = device_lookup_by_name(db_tok_string);
9380 db_printf("usage: show t4 devlog <nexus>\n");
9385 db_printf("device not found\n");
9389 t4_dump_devlog(device_get_softc(dev));
9392 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9401 t = db_read_token();
9403 dev = device_lookup_by_name(db_tok_string);
9404 t = db_read_token();
9406 tid = db_tok_number;
9413 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9418 db_printf("device not found\n");
9422 db_printf("invalid tid\n");
9426 t4_dump_tcb(device_get_softc(dev), tid);
9430 static struct sx mlu; /* mod load unload */
9431 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9434 mod_event(module_t mod, int cmd, void *arg)
9437 static int loaded = 0;
9442 if (loaded++ == 0) {
9444 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9445 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9446 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9447 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9448 sx_init(&t4_list_lock, "T4/T5 adapters");
9449 SLIST_INIT(&t4_list);
9451 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9452 SLIST_INIT(&t4_uld_list);
9454 t4_tracer_modload();
9462 if (--loaded == 0) {
9465 sx_slock(&t4_list_lock);
9466 if (!SLIST_EMPTY(&t4_list)) {
9468 sx_sunlock(&t4_list_lock);
9472 sx_slock(&t4_uld_list_lock);
9473 if (!SLIST_EMPTY(&t4_uld_list)) {
9475 sx_sunlock(&t4_uld_list_lock);
9476 sx_sunlock(&t4_list_lock);
9481 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9482 uprintf("%ju clusters with custom free routine "
9483 "still is use.\n", t4_sge_extfree_refs());
9484 pause("t4unload", 2 * hz);
9487 sx_sunlock(&t4_uld_list_lock);
9489 sx_sunlock(&t4_list_lock);
9491 if (t4_sge_extfree_refs() == 0) {
9492 t4_tracer_modunload();
9494 sx_destroy(&t4_uld_list_lock);
9496 sx_destroy(&t4_list_lock);
9501 loaded++; /* undo earlier decrement */
9512 static devclass_t t4_devclass, t5_devclass;
9513 static devclass_t cxgbe_devclass, cxl_devclass;
9514 static devclass_t vcxgbe_devclass, vcxl_devclass;
9516 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9517 MODULE_VERSION(t4nex, 1);
9518 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9520 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
9521 #endif /* DEV_NETMAP */
9524 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9525 MODULE_VERSION(t5nex, 1);
9526 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9528 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
9529 #endif /* DEV_NETMAP */
9531 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9532 MODULE_VERSION(cxgbe, 1);
9534 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9535 MODULE_VERSION(cxl, 1);
9537 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9538 MODULE_VERSION(vcxgbe, 1);
9540 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9541 MODULE_VERSION(vcxl, 1);