2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #if defined(__i386__) || defined(__amd64__)
67 #include <machine/md_var.h>
68 #include <machine/cputypes.h>
72 #include <crypto/rijndael/rijndael.h>
75 #include <ddb/db_lex.h>
78 #include "common/common.h"
79 #include "common/t4_msg.h"
80 #include "common/t4_regs.h"
81 #include "common/t4_regs_values.h"
82 #include "cudbg/cudbg.h"
85 #include "t4_mp_ring.h"
89 /* T4 bus driver interface */
90 static int t4_probe(device_t);
91 static int t4_attach(device_t);
92 static int t4_detach(device_t);
93 static int t4_ready(device_t);
94 static int t4_read_port_device(device_t, int, device_t *);
95 static device_method_t t4_methods[] = {
96 DEVMETHOD(device_probe, t4_probe),
97 DEVMETHOD(device_attach, t4_attach),
98 DEVMETHOD(device_detach, t4_detach),
100 DEVMETHOD(t4_is_main_ready, t4_ready),
101 DEVMETHOD(t4_read_port_device, t4_read_port_device),
105 static driver_t t4_driver = {
108 sizeof(struct adapter)
112 /* T4 port (cxgbe) interface */
113 static int cxgbe_probe(device_t);
114 static int cxgbe_attach(device_t);
115 static int cxgbe_detach(device_t);
116 device_method_t cxgbe_methods[] = {
117 DEVMETHOD(device_probe, cxgbe_probe),
118 DEVMETHOD(device_attach, cxgbe_attach),
119 DEVMETHOD(device_detach, cxgbe_detach),
122 static driver_t cxgbe_driver = {
125 sizeof(struct port_info)
128 /* T4 VI (vcxgbe) interface */
129 static int vcxgbe_probe(device_t);
130 static int vcxgbe_attach(device_t);
131 static int vcxgbe_detach(device_t);
132 static device_method_t vcxgbe_methods[] = {
133 DEVMETHOD(device_probe, vcxgbe_probe),
134 DEVMETHOD(device_attach, vcxgbe_attach),
135 DEVMETHOD(device_detach, vcxgbe_detach),
138 static driver_t vcxgbe_driver = {
141 sizeof(struct vi_info)
144 static d_ioctl_t t4_ioctl;
146 static struct cdevsw t4_cdevsw = {
147 .d_version = D_VERSION,
152 /* T5 bus driver interface */
153 static int t5_probe(device_t);
154 static device_method_t t5_methods[] = {
155 DEVMETHOD(device_probe, t5_probe),
156 DEVMETHOD(device_attach, t4_attach),
157 DEVMETHOD(device_detach, t4_detach),
159 DEVMETHOD(t4_is_main_ready, t4_ready),
160 DEVMETHOD(t4_read_port_device, t4_read_port_device),
164 static driver_t t5_driver = {
167 sizeof(struct adapter)
171 /* T5 port (cxl) interface */
172 static driver_t cxl_driver = {
175 sizeof(struct port_info)
178 /* T5 VI (vcxl) interface */
179 static driver_t vcxl_driver = {
182 sizeof(struct vi_info)
185 /* T6 bus driver interface */
186 static int t6_probe(device_t);
187 static device_method_t t6_methods[] = {
188 DEVMETHOD(device_probe, t6_probe),
189 DEVMETHOD(device_attach, t4_attach),
190 DEVMETHOD(device_detach, t4_detach),
192 DEVMETHOD(t4_is_main_ready, t4_ready),
193 DEVMETHOD(t4_read_port_device, t4_read_port_device),
197 static driver_t t6_driver = {
200 sizeof(struct adapter)
204 /* T6 port (cc) interface */
205 static driver_t cc_driver = {
208 sizeof(struct port_info)
211 /* T6 VI (vcc) interface */
212 static driver_t vcc_driver = {
215 sizeof(struct vi_info)
218 /* ifnet + media interface */
219 static void cxgbe_init(void *);
220 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
221 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
222 static void cxgbe_qflush(struct ifnet *);
223 static int cxgbe_media_change(struct ifnet *);
224 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
226 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
229 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
230 * then ADAPTER_LOCK, then t4_uld_list_lock.
232 static struct sx t4_list_lock;
233 SLIST_HEAD(, adapter) t4_list;
235 static struct sx t4_uld_list_lock;
236 SLIST_HEAD(, uld_info) t4_uld_list;
240 * Tunables. See tweak_tunables() too.
242 * Each tunable is set to a default value here if it's known at compile-time.
243 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
244 * provide a reasonable default (upto n) when the driver is loaded.
246 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
247 * T5 are under hw.cxl.
251 * Number of queues for tx and rx, NIC and offload.
255 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq);
256 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
260 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq);
261 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
264 static int t4_ntxq_vi = -NTXQ_VI;
265 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
268 static int t4_nrxq_vi = -NRXQ_VI;
269 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
271 static int t4_rsrv_noflowq = 0;
272 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
274 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
276 static int t4_nofldtxq = -NOFLDTXQ;
277 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq);
280 static int t4_nofldrxq = -NOFLDRXQ;
281 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq);
283 #define NOFLDTXQ_VI 1
284 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
285 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
287 #define NOFLDRXQ_VI 1
288 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
289 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
291 #define TMR_IDX_OFLD 1
292 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
293 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld);
295 #define PKTC_IDX_OFLD (-1)
296 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
297 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld);
299 /* 0 means chip/fw default, non-zero number is value in microseconds */
300 static u_long t4_toe_keepalive_idle = 0;
301 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle);
303 /* 0 means chip/fw default, non-zero number is value in microseconds */
304 static u_long t4_toe_keepalive_interval = 0;
305 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval);
307 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
308 static int t4_toe_keepalive_count = 0;
309 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count);
311 /* 0 means chip/fw default, non-zero number is value in microseconds */
312 static u_long t4_toe_rexmt_min = 0;
313 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min);
315 /* 0 means chip/fw default, non-zero number is value in microseconds */
316 static u_long t4_toe_rexmt_max = 0;
317 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max);
319 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
320 static int t4_toe_rexmt_count = 0;
321 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count);
323 /* -1 means chip/fw default, other values are raw backoff values to use */
324 static int t4_toe_rexmt_backoff[16] = {
325 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]);
328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]);
329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]);
330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]);
331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]);
332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]);
333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]);
334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]);
335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]);
336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]);
337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]);
338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]);
339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]);
340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]);
341 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]);
342 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]);
347 static int t4_nnmtxq_vi = -NNMTXQ_VI;
348 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
351 static int t4_nnmrxq_vi = -NNMRXQ_VI;
352 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
356 * Holdoff parameters for ports.
359 int t4_tmr_idx = TMR_IDX;
360 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx);
361 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
363 #define PKTC_IDX (-1)
364 int t4_pktc_idx = PKTC_IDX;
365 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx);
366 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
369 * Size (# of entries) of each tx and rx queue.
371 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
372 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
374 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
375 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
378 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
380 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
381 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
384 * Configuration file. All the _CF names here are special.
386 #define DEFAULT_CF "default"
387 #define BUILTIN_CF "built-in"
388 #define FLASH_CF "flash"
389 #define UWIRE_CF "uwire"
390 #define FPGA_CF "fpga"
391 static char t4_cfg_file[32] = DEFAULT_CF;
392 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
395 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
396 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
397 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
398 * mark or when signalled to do so, 0 to never emit PAUSE.
400 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
401 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
404 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS,
405 * FEC_RESERVED respectively).
406 * -1 to run with the firmware default.
409 static int t4_fec = -1;
410 TUNABLE_INT("hw.cxgbe.fec", &t4_fec);
413 * Link autonegotiation.
414 * -1 to run with the firmware default.
418 static int t4_autoneg = -1;
419 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg);
422 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
423 * encouraged respectively).
425 static unsigned int t4_fw_install = 1;
426 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
429 * ASIC features that will be used. Disable the ones you don't want so that the
430 * chip resources aren't wasted on features that will not be used.
432 static int t4_nbmcaps_allowed = 0;
433 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
435 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
436 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
438 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
439 FW_CAPS_CONFIG_SWITCH_EGRESS;
440 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
442 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
443 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
444 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
446 static int t4_toecaps_allowed = -1;
447 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
449 static int t4_rdmacaps_allowed = -1;
450 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
452 static int t4_cryptocaps_allowed = -1;
453 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
455 static int t4_iscsicaps_allowed = -1;
456 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
458 static int t4_fcoecaps_allowed = 0;
459 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
461 static int t5_write_combine = 0;
462 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
464 static int t4_num_vis = 1;
465 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
467 * PCIe Relaxed Ordering.
468 * -1: driver should figure out a good value.
473 static int pcie_relaxed_ordering = -1;
474 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering);
476 static int t4_panic_on_fatal_err = 0;
477 TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err);
483 static int t4_cop_managed_offloading = 0;
484 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
487 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
488 static int vi_mac_funcs[] = {
492 FW_VI_FUNC_OPENISCSI,
498 struct intrs_and_queues {
499 uint16_t intr_type; /* INTx, MSI, or MSI-X */
500 uint16_t num_vis; /* number of VIs for each port */
501 uint16_t nirq; /* Total # of vectors */
502 uint16_t ntxq; /* # of NIC txq's for each port */
503 uint16_t nrxq; /* # of NIC rxq's for each port */
504 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
505 uint16_t nofldrxq; /* # of TOE rxq's for each port */
507 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
508 uint16_t ntxq_vi; /* # of NIC txq's */
509 uint16_t nrxq_vi; /* # of NIC rxq's */
510 uint16_t nofldtxq_vi; /* # of TOE txq's */
511 uint16_t nofldrxq_vi; /* # of TOE rxq's */
512 uint16_t nnmtxq_vi; /* # of netmap txq's */
513 uint16_t nnmrxq_vi; /* # of netmap rxq's */
516 static void setup_memwin(struct adapter *);
517 static void position_memwin(struct adapter *, int, uint32_t);
518 static int validate_mem_range(struct adapter *, uint32_t, int);
519 static int fwmtype_to_hwmtype(int);
520 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
522 static int fixup_devlog_params(struct adapter *);
523 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
524 static int prep_firmware(struct adapter *);
525 static int partition_resources(struct adapter *, const struct firmware *,
527 static int get_params__pre_init(struct adapter *);
528 static int get_params__post_init(struct adapter *);
529 static int set_params__post_init(struct adapter *);
530 static void t4_set_desc(struct adapter *);
531 static void build_medialist(struct port_info *, struct ifmedia *);
532 static void init_l1cfg(struct port_info *);
533 static int apply_l1cfg(struct port_info *);
534 static int cxgbe_init_synchronized(struct vi_info *);
535 static int cxgbe_uninit_synchronized(struct vi_info *);
536 static void quiesce_txq(struct adapter *, struct sge_txq *);
537 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
538 static void quiesce_iq(struct adapter *, struct sge_iq *);
539 static void quiesce_fl(struct adapter *, struct sge_fl *);
540 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
541 driver_intr_t *, void *, char *);
542 static int t4_free_irq(struct adapter *, struct irq *);
543 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
544 static void vi_refresh_stats(struct adapter *, struct vi_info *);
545 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
546 static void cxgbe_tick(void *);
547 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
548 static void cxgbe_sysctls(struct port_info *);
549 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
550 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
551 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
552 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
553 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
554 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
555 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
556 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
557 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
558 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
559 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
560 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
561 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
562 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
563 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
564 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
565 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
566 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
567 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
568 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
569 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
570 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
571 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
572 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
573 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
574 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
575 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
576 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
577 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
578 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
579 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
580 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
581 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
582 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
583 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
584 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
585 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
586 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
587 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
588 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
589 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
590 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
591 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
592 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
594 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
595 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
596 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
597 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
598 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
599 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
600 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
601 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
603 static int get_sge_context(struct adapter *, struct t4_sge_context *);
604 static int load_fw(struct adapter *, struct t4_data *);
605 static int load_cfg(struct adapter *, struct t4_data *);
606 static int load_boot(struct adapter *, struct t4_bootrom *);
607 static int load_bootcfg(struct adapter *, struct t4_data *);
608 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
609 static void free_offload_policy(struct t4_offload_policy *);
610 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
611 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
612 static int read_i2c(struct adapter *, struct t4_i2c_data *);
614 static int toe_capability(struct vi_info *, int);
616 static int mod_event(module_t, int, void *);
617 static int notify_siblings(device_t, int);
623 {0xa000, "Chelsio Terminator 4 FPGA"},
624 {0x4400, "Chelsio T440-dbg"},
625 {0x4401, "Chelsio T420-CR"},
626 {0x4402, "Chelsio T422-CR"},
627 {0x4403, "Chelsio T440-CR"},
628 {0x4404, "Chelsio T420-BCH"},
629 {0x4405, "Chelsio T440-BCH"},
630 {0x4406, "Chelsio T440-CH"},
631 {0x4407, "Chelsio T420-SO"},
632 {0x4408, "Chelsio T420-CX"},
633 {0x4409, "Chelsio T420-BT"},
634 {0x440a, "Chelsio T404-BT"},
635 {0x440e, "Chelsio T440-LP-CR"},
637 {0xb000, "Chelsio Terminator 5 FPGA"},
638 {0x5400, "Chelsio T580-dbg"},
639 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
640 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
641 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
642 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
643 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
644 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
645 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
646 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
647 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
648 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
649 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
650 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
651 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
652 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
653 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
654 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
655 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
657 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
658 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
659 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
660 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
661 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
662 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
663 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
664 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
665 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
666 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
667 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
668 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
669 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
670 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
671 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
672 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
675 {0x6480, "Custom T6225-CR"},
676 {0x6481, "Custom T62100-CR"},
677 {0x6482, "Custom T6225-CR"},
678 {0x6483, "Custom T62100-CR"},
679 {0x6484, "Custom T64100-CR"},
680 {0x6485, "Custom T6240-SO"},
681 {0x6486, "Custom T6225-SO-CR"},
682 {0x6487, "Custom T6225-CR"},
687 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
688 * exactly the same for both rxq and ofld_rxq.
690 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
691 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
693 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
696 t4_probe(device_t dev)
699 uint16_t v = pci_get_vendor(dev);
700 uint16_t d = pci_get_device(dev);
701 uint8_t f = pci_get_function(dev);
703 if (v != PCI_VENDOR_ID_CHELSIO)
706 /* Attach only to PF0 of the FPGA */
707 if (d == 0xa000 && f != 0)
710 for (i = 0; i < nitems(t4_pciids); i++) {
711 if (d == t4_pciids[i].device) {
712 device_set_desc(dev, t4_pciids[i].desc);
713 return (BUS_PROBE_DEFAULT);
721 t5_probe(device_t dev)
724 uint16_t v = pci_get_vendor(dev);
725 uint16_t d = pci_get_device(dev);
726 uint8_t f = pci_get_function(dev);
728 if (v != PCI_VENDOR_ID_CHELSIO)
731 /* Attach only to PF0 of the FPGA */
732 if (d == 0xb000 && f != 0)
735 for (i = 0; i < nitems(t5_pciids); i++) {
736 if (d == t5_pciids[i].device) {
737 device_set_desc(dev, t5_pciids[i].desc);
738 return (BUS_PROBE_DEFAULT);
746 t6_probe(device_t dev)
749 uint16_t v = pci_get_vendor(dev);
750 uint16_t d = pci_get_device(dev);
752 if (v != PCI_VENDOR_ID_CHELSIO)
755 for (i = 0; i < nitems(t6_pciids); i++) {
756 if (d == t6_pciids[i].device) {
757 device_set_desc(dev, t6_pciids[i].desc);
758 return (BUS_PROBE_DEFAULT);
766 t5_attribute_workaround(device_t dev)
772 * The T5 chips do not properly echo the No Snoop and Relaxed
773 * Ordering attributes when replying to a TLP from a Root
774 * Port. As a workaround, find the parent Root Port and
775 * disable No Snoop and Relaxed Ordering. Note that this
776 * affects all devices under this root port.
778 root_port = pci_find_pcie_root_port(dev);
779 if (root_port == NULL) {
780 device_printf(dev, "Unable to find parent root port\n");
784 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
785 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
786 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
788 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
789 device_get_nameunit(root_port));
792 static const struct devnames devnames[] = {
794 .nexus_name = "t4nex",
795 .ifnet_name = "cxgbe",
796 .vi_ifnet_name = "vcxgbe",
797 .pf03_drv_name = "t4iov",
798 .vf_nexus_name = "t4vf",
799 .vf_ifnet_name = "cxgbev"
801 .nexus_name = "t5nex",
803 .vi_ifnet_name = "vcxl",
804 .pf03_drv_name = "t5iov",
805 .vf_nexus_name = "t5vf",
806 .vf_ifnet_name = "cxlv"
808 .nexus_name = "t6nex",
810 .vi_ifnet_name = "vcc",
811 .pf03_drv_name = "t6iov",
812 .vf_nexus_name = "t6vf",
813 .vf_ifnet_name = "ccv"
818 t4_init_devnames(struct adapter *sc)
823 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
824 sc->names = &devnames[id - CHELSIO_T4];
826 device_printf(sc->dev, "chip id %d is not supported.\n", id);
832 t4_attach(device_t dev)
835 int rc = 0, i, j, rqidx, tqidx, nports;
836 struct make_dev_args mda;
837 struct intrs_and_queues iaq;
840 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
847 int nm_rqidx, nm_tqidx;
851 sc = device_get_softc(dev);
853 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
855 if ((pci_get_device(dev) & 0xff00) == 0x5400)
856 t5_attribute_workaround(dev);
857 pci_enable_busmaster(dev);
858 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
861 pci_set_max_read_req(dev, 4096);
862 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
863 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
864 if (pcie_relaxed_ordering == 0 &&
865 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
866 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
867 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
868 } else if (pcie_relaxed_ordering == 1 &&
869 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
870 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
871 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
875 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
876 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
878 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
879 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
880 device_get_nameunit(dev));
882 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
883 device_get_nameunit(dev));
884 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
887 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
888 TAILQ_INIT(&sc->sfl);
889 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
891 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
894 rw_init(&sc->policy_lock, "connection offload policy");
896 rc = t4_map_bars_0_and_4(sc);
898 goto done; /* error message displayed already */
900 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
902 /* Prepare the adapter for operation. */
903 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
904 rc = -t4_prep_adapter(sc, buf);
907 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
912 * This is the real PF# to which we're attaching. Works from within PCI
913 * passthrough environments too, where pci_get_function() could return a
914 * different PF# depending on the passthrough configuration. We need to
915 * use the real PF# in all our communication with the firmware.
917 j = t4_read_reg(sc, A_PL_WHOAMI);
918 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
921 t4_init_devnames(sc);
922 if (sc->names == NULL) {
924 goto done; /* error message displayed already */
928 * Do this really early, with the memory windows set up even before the
929 * character device. The userland tool's register i/o and mem read
930 * will work even in "recovery mode".
933 if (t4_init_devlog_params(sc, 0) == 0)
934 fixup_devlog_params(sc);
935 make_dev_args_init(&mda);
936 mda.mda_devsw = &t4_cdevsw;
937 mda.mda_uid = UID_ROOT;
938 mda.mda_gid = GID_WHEEL;
940 mda.mda_si_drv1 = sc;
941 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
943 device_printf(dev, "failed to create nexus char device: %d.\n",
946 /* Go no further if recovery mode has been requested. */
947 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
948 device_printf(dev, "recovery mode.\n");
952 #if defined(__i386__)
953 if ((cpu_feature & CPUID_CX8) == 0) {
954 device_printf(dev, "64 bit atomics not available.\n");
960 /* Prepare the firmware for operation */
961 rc = prep_firmware(sc);
963 goto done; /* error message displayed already */
965 rc = get_params__post_init(sc);
967 goto done; /* error message displayed already */
969 rc = set_params__post_init(sc);
971 goto done; /* error message displayed already */
973 rc = t4_map_bar_2(sc);
975 goto done; /* error message displayed already */
977 rc = t4_create_dma_tag(sc);
979 goto done; /* error message displayed already */
982 * First pass over all the ports - allocate VIs and initialize some
983 * basic parameters like mac address, port type, etc.
985 for_each_port(sc, i) {
986 struct port_info *pi;
988 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
991 /* These must be set before t4_port_init */
995 * XXX: vi[0] is special so we can't delay this allocation until
996 * pi->nvi's final value is known.
998 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1002 * Allocate the "main" VI and initialize parameters
1005 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1007 device_printf(dev, "unable to initialize port %d: %d\n",
1009 free(pi->vi, M_CXGBE);
1015 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1016 device_get_nameunit(dev), i);
1017 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1018 sc->chan_map[pi->tx_chan] = i;
1020 /* All VIs on this port share this media. */
1021 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1022 cxgbe_media_status);
1024 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
1025 if (pi->dev == NULL) {
1027 "failed to add device for port %d.\n", i);
1031 pi->vi[0].dev = pi->dev;
1032 device_set_softc(pi->dev, pi);
1036 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1038 nports = sc->params.nports;
1039 rc = cfg_itype_and_nqueues(sc, &iaq);
1041 goto done; /* error message displayed already */
1043 num_vis = iaq.num_vis;
1044 sc->intr_type = iaq.intr_type;
1045 sc->intr_count = iaq.nirq;
1048 s->nrxq = nports * iaq.nrxq;
1049 s->ntxq = nports * iaq.ntxq;
1051 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1052 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1054 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1055 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1056 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1057 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1058 if (is_offload(sc) || is_ethoffload(sc)) {
1059 s->nofldtxq = nports * iaq.nofldtxq;
1061 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1062 s->neq += s->nofldtxq;
1064 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1065 M_CXGBE, M_ZERO | M_WAITOK);
1069 if (is_offload(sc)) {
1070 s->nofldrxq = nports * iaq.nofldrxq;
1072 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1073 s->neq += s->nofldrxq; /* free list */
1074 s->niq += s->nofldrxq;
1076 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1077 M_CXGBE, M_ZERO | M_WAITOK);
1082 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1083 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1085 s->neq += s->nnmtxq + s->nnmrxq;
1086 s->niq += s->nnmrxq;
1088 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1089 M_CXGBE, M_ZERO | M_WAITOK);
1090 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1091 M_CXGBE, M_ZERO | M_WAITOK);
1094 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1096 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1098 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1100 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1102 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1105 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1108 t4_init_l2t(sc, M_WAITOK);
1109 t4_init_smt(sc, M_WAITOK);
1110 t4_init_tx_sched(sc);
1112 t4_init_etid_table(sc);
1116 * Second pass over the ports. This time we know the number of rx and
1117 * tx queues that each port should get.
1120 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1127 nm_rqidx = nm_tqidx = 0;
1129 for_each_port(sc, i) {
1130 struct port_info *pi = sc->port[i];
1137 for_each_vi(pi, j, vi) {
1139 vi->qsize_rxq = t4_qsize_rxq;
1140 vi->qsize_txq = t4_qsize_txq;
1142 vi->first_rxq = rqidx;
1143 vi->first_txq = tqidx;
1144 vi->tmr_idx = t4_tmr_idx;
1145 vi->pktc_idx = t4_pktc_idx;
1146 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1147 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1152 if (j == 0 && vi->ntxq > 1)
1153 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1155 vi->rsrv_noflowq = 0;
1157 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1158 vi->first_ofld_txq = ofld_tqidx;
1159 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1160 ofld_tqidx += vi->nofldtxq;
1163 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1164 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1165 vi->first_ofld_rxq = ofld_rqidx;
1166 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1168 ofld_rqidx += vi->nofldrxq;
1172 vi->first_nm_rxq = nm_rqidx;
1173 vi->first_nm_txq = nm_tqidx;
1174 vi->nnmrxq = iaq.nnmrxq_vi;
1175 vi->nnmtxq = iaq.nnmtxq_vi;
1176 nm_rqidx += vi->nnmrxq;
1177 nm_tqidx += vi->nnmtxq;
1183 rc = t4_setup_intr_handlers(sc);
1186 "failed to setup interrupt handlers: %d\n", rc);
1190 rc = bus_generic_probe(dev);
1192 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1197 * Ensure thread-safe mailbox access (in debug builds).
1199 * So far this was the only thread accessing the mailbox but various
1200 * ifnets and sysctls are about to be created and their handlers/ioctls
1201 * will access the mailbox from different threads.
1203 sc->flags |= CHK_MBOX_ACCESS;
1205 rc = bus_generic_attach(dev);
1208 "failed to attach all child ports: %d\n", rc);
1213 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1214 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1215 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1216 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1217 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1221 notify_siblings(dev, 0);
1224 if (rc != 0 && sc->cdev) {
1225 /* cdev was created and so cxgbetool works; recover that way. */
1227 "error during attach, adapter is now in recovery mode.\n");
1232 t4_detach_common(dev);
1240 t4_ready(device_t dev)
1244 sc = device_get_softc(dev);
1245 if (sc->flags & FW_OK)
1251 t4_read_port_device(device_t dev, int port, device_t *child)
1254 struct port_info *pi;
1256 sc = device_get_softc(dev);
1257 if (port < 0 || port >= MAX_NPORTS)
1259 pi = sc->port[port];
1260 if (pi == NULL || pi->dev == NULL)
1267 notify_siblings(device_t dev, int detaching)
1273 for (i = 0; i < PCI_FUNCMAX; i++) {
1274 if (i == pci_get_function(dev))
1276 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1277 pci_get_slot(dev), i);
1278 if (sibling == NULL || !device_is_attached(sibling))
1281 error = T4_DETACH_CHILD(sibling);
1283 (void)T4_ATTACH_CHILD(sibling);
1294 t4_detach(device_t dev)
1299 sc = device_get_softc(dev);
1301 rc = notify_siblings(dev, 1);
1304 "failed to detach sibling devices: %d\n", rc);
1308 return (t4_detach_common(dev));
1312 t4_detach_common(device_t dev)
1315 struct port_info *pi;
1318 sc = device_get_softc(dev);
1321 destroy_dev(sc->cdev);
1325 sc->flags &= ~CHK_MBOX_ACCESS;
1326 if (sc->flags & FULL_INIT_DONE) {
1327 if (!(sc->flags & IS_VF))
1328 t4_intr_disable(sc);
1331 if (device_is_attached(dev)) {
1332 rc = bus_generic_detach(dev);
1335 "failed to detach child devices: %d\n", rc);
1340 for (i = 0; i < sc->intr_count; i++)
1341 t4_free_irq(sc, &sc->irq[i]);
1343 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1344 t4_free_tx_sched(sc);
1346 for (i = 0; i < MAX_NPORTS; i++) {
1349 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1351 device_delete_child(dev, pi->dev);
1353 mtx_destroy(&pi->pi_lock);
1354 free(pi->vi, M_CXGBE);
1359 device_delete_children(dev);
1361 if (sc->flags & FULL_INIT_DONE)
1362 adapter_full_uninit(sc);
1364 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1365 t4_fw_bye(sc, sc->mbox);
1367 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1368 pci_release_msi(dev);
1371 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1375 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1379 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1383 t4_free_l2t(sc->l2t);
1385 t4_free_smt(sc->smt);
1387 t4_free_etid_table(sc);
1390 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1391 free(sc->sge.ofld_txq, M_CXGBE);
1394 free(sc->sge.ofld_rxq, M_CXGBE);
1397 free(sc->sge.nm_rxq, M_CXGBE);
1398 free(sc->sge.nm_txq, M_CXGBE);
1400 free(sc->irq, M_CXGBE);
1401 free(sc->sge.rxq, M_CXGBE);
1402 free(sc->sge.txq, M_CXGBE);
1403 free(sc->sge.ctrlq, M_CXGBE);
1404 free(sc->sge.iqmap, M_CXGBE);
1405 free(sc->sge.eqmap, M_CXGBE);
1406 free(sc->tids.ftid_tab, M_CXGBE);
1407 if (sc->tids.hftid_tab)
1408 free_hftid_tab(&sc->tids);
1409 free(sc->tids.atid_tab, M_CXGBE);
1410 free(sc->tids.tid_tab, M_CXGBE);
1411 free(sc->tt.tls_rx_ports, M_CXGBE);
1412 t4_destroy_dma_tag(sc);
1413 if (mtx_initialized(&sc->sc_lock)) {
1414 sx_xlock(&t4_list_lock);
1415 SLIST_REMOVE(&t4_list, sc, adapter, link);
1416 sx_xunlock(&t4_list_lock);
1417 mtx_destroy(&sc->sc_lock);
1420 callout_drain(&sc->sfl_callout);
1421 if (mtx_initialized(&sc->tids.ftid_lock)) {
1422 mtx_destroy(&sc->tids.ftid_lock);
1423 cv_destroy(&sc->tids.ftid_cv);
1425 if (mtx_initialized(&sc->tids.atid_lock))
1426 mtx_destroy(&sc->tids.atid_lock);
1427 if (mtx_initialized(&sc->sfl_lock))
1428 mtx_destroy(&sc->sfl_lock);
1429 if (mtx_initialized(&sc->ifp_lock))
1430 mtx_destroy(&sc->ifp_lock);
1431 if (mtx_initialized(&sc->reg_lock))
1432 mtx_destroy(&sc->reg_lock);
1434 if (rw_initialized(&sc->policy_lock)) {
1435 rw_destroy(&sc->policy_lock);
1437 if (sc->policy != NULL)
1438 free_offload_policy(sc->policy);
1442 for (i = 0; i < NUM_MEMWIN; i++) {
1443 struct memwin *mw = &sc->memwin[i];
1445 if (rw_initialized(&mw->mw_lock))
1446 rw_destroy(&mw->mw_lock);
1449 bzero(sc, sizeof(*sc));
1455 cxgbe_probe(device_t dev)
1458 struct port_info *pi = device_get_softc(dev);
1460 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1461 device_set_desc_copy(dev, buf);
1463 return (BUS_PROBE_DEFAULT);
1466 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1467 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1468 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1469 #define T4_CAP_ENABLE (T4_CAP)
1472 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1477 vi->xact_addr_filt = -1;
1478 callout_init(&vi->tick, 1);
1480 /* Allocate an ifnet and set it up */
1481 ifp = if_alloc(IFT_ETHER);
1483 device_printf(dev, "Cannot allocate ifnet\n");
1489 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1490 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1492 ifp->if_init = cxgbe_init;
1493 ifp->if_ioctl = cxgbe_ioctl;
1494 ifp->if_transmit = cxgbe_transmit;
1495 ifp->if_qflush = cxgbe_qflush;
1496 ifp->if_get_counter = cxgbe_get_counter;
1498 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1499 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1500 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1501 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1504 ifp->if_capabilities = T4_CAP;
1506 if (vi->nofldrxq != 0)
1507 ifp->if_capabilities |= IFCAP_TOE;
1510 if (vi->nnmrxq != 0)
1511 ifp->if_capabilities |= IFCAP_NETMAP;
1514 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1515 ifp->if_capabilities |= IFCAP_TXRTLMT;
1517 ifp->if_capenable = T4_CAP_ENABLE;
1518 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1519 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1521 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1522 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1523 ifp->if_hw_tsomaxsegsize = 65536;
1525 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1526 EVENTHANDLER_PRI_ANY);
1528 ether_ifattach(ifp, vi->hw_addr);
1530 if (ifp->if_capabilities & IFCAP_NETMAP)
1531 cxgbe_nm_attach(vi);
1533 sb = sbuf_new_auto();
1534 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1535 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1536 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1538 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1540 case IFCAP_TOE | IFCAP_TXRTLMT:
1541 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1544 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1549 if (ifp->if_capabilities & IFCAP_TOE)
1550 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1553 if (ifp->if_capabilities & IFCAP_NETMAP)
1554 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1555 vi->nnmtxq, vi->nnmrxq);
1558 device_printf(dev, "%s\n", sbuf_data(sb));
1567 cxgbe_attach(device_t dev)
1569 struct port_info *pi = device_get_softc(dev);
1570 struct adapter *sc = pi->adapter;
1574 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1576 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1580 for_each_vi(pi, i, vi) {
1583 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1584 if (vi->dev == NULL) {
1585 device_printf(dev, "failed to add VI %d\n", i);
1588 device_set_softc(vi->dev, vi);
1593 bus_generic_attach(dev);
1599 cxgbe_vi_detach(struct vi_info *vi)
1601 struct ifnet *ifp = vi->ifp;
1603 ether_ifdetach(ifp);
1606 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1608 /* Let detach proceed even if these fail. */
1610 if (ifp->if_capabilities & IFCAP_NETMAP)
1611 cxgbe_nm_detach(vi);
1613 cxgbe_uninit_synchronized(vi);
1614 callout_drain(&vi->tick);
1622 cxgbe_detach(device_t dev)
1624 struct port_info *pi = device_get_softc(dev);
1625 struct adapter *sc = pi->adapter;
1628 /* Detach the extra VIs first. */
1629 rc = bus_generic_detach(dev);
1632 device_delete_children(dev);
1634 doom_vi(sc, &pi->vi[0]);
1636 if (pi->flags & HAS_TRACEQ) {
1637 sc->traceq = -1; /* cloner should not create ifnet */
1638 t4_tracer_port_detach(sc);
1641 cxgbe_vi_detach(&pi->vi[0]);
1642 callout_drain(&pi->tick);
1643 ifmedia_removeall(&pi->media);
1645 end_synchronized_op(sc, 0);
1651 cxgbe_init(void *arg)
1653 struct vi_info *vi = arg;
1654 struct adapter *sc = vi->pi->adapter;
1656 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1658 cxgbe_init_synchronized(vi);
1659 end_synchronized_op(sc, 0);
1663 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1665 int rc = 0, mtu, flags;
1666 struct vi_info *vi = ifp->if_softc;
1667 struct port_info *pi = vi->pi;
1668 struct adapter *sc = pi->adapter;
1669 struct ifreq *ifr = (struct ifreq *)data;
1675 if (mtu < ETHERMIN || mtu > MAX_MTU)
1678 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1682 if (vi->flags & VI_INIT_DONE) {
1683 t4_update_fl_bufsize(ifp);
1684 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1685 rc = update_mac_settings(ifp, XGMAC_MTU);
1687 end_synchronized_op(sc, 0);
1691 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1695 if (ifp->if_flags & IFF_UP) {
1696 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1697 flags = vi->if_flags;
1698 if ((ifp->if_flags ^ flags) &
1699 (IFF_PROMISC | IFF_ALLMULTI)) {
1700 rc = update_mac_settings(ifp,
1701 XGMAC_PROMISC | XGMAC_ALLMULTI);
1704 rc = cxgbe_init_synchronized(vi);
1706 vi->if_flags = ifp->if_flags;
1707 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1708 rc = cxgbe_uninit_synchronized(vi);
1710 end_synchronized_op(sc, 0);
1715 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1718 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1719 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1720 end_synchronized_op(sc, 0);
1724 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1728 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1729 if (mask & IFCAP_TXCSUM) {
1730 ifp->if_capenable ^= IFCAP_TXCSUM;
1731 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1733 if (IFCAP_TSO4 & ifp->if_capenable &&
1734 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1735 ifp->if_capenable &= ~IFCAP_TSO4;
1737 "tso4 disabled due to -txcsum.\n");
1740 if (mask & IFCAP_TXCSUM_IPV6) {
1741 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1742 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1744 if (IFCAP_TSO6 & ifp->if_capenable &&
1745 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1746 ifp->if_capenable &= ~IFCAP_TSO6;
1748 "tso6 disabled due to -txcsum6.\n");
1751 if (mask & IFCAP_RXCSUM)
1752 ifp->if_capenable ^= IFCAP_RXCSUM;
1753 if (mask & IFCAP_RXCSUM_IPV6)
1754 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1757 * Note that we leave CSUM_TSO alone (it is always set). The
1758 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1759 * sending a TSO request our way, so it's sufficient to toggle
1762 if (mask & IFCAP_TSO4) {
1763 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1764 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1765 if_printf(ifp, "enable txcsum first.\n");
1769 ifp->if_capenable ^= IFCAP_TSO4;
1771 if (mask & IFCAP_TSO6) {
1772 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1773 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1774 if_printf(ifp, "enable txcsum6 first.\n");
1778 ifp->if_capenable ^= IFCAP_TSO6;
1780 if (mask & IFCAP_LRO) {
1781 #if defined(INET) || defined(INET6)
1783 struct sge_rxq *rxq;
1785 ifp->if_capenable ^= IFCAP_LRO;
1786 for_each_rxq(vi, i, rxq) {
1787 if (ifp->if_capenable & IFCAP_LRO)
1788 rxq->iq.flags |= IQ_LRO_ENABLED;
1790 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1795 if (mask & IFCAP_TOE) {
1796 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1798 rc = toe_capability(vi, enable);
1802 ifp->if_capenable ^= mask;
1805 if (mask & IFCAP_VLAN_HWTAGGING) {
1806 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1807 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1808 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1810 if (mask & IFCAP_VLAN_MTU) {
1811 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1813 /* Need to find out how to disable auto-mtu-inflation */
1815 if (mask & IFCAP_VLAN_HWTSO)
1816 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1817 if (mask & IFCAP_VLAN_HWCSUM)
1818 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1820 if (mask & IFCAP_TXRTLMT)
1821 ifp->if_capenable ^= IFCAP_TXRTLMT;
1824 #ifdef VLAN_CAPABILITIES
1825 VLAN_CAPABILITIES(ifp);
1828 end_synchronized_op(sc, 0);
1834 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1838 struct ifi2creq i2c;
1840 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
1843 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1847 if (i2c.len > sizeof(i2c.data)) {
1851 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1854 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1855 i2c.offset, i2c.len, &i2c.data[0]);
1856 end_synchronized_op(sc, 0);
1858 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
1863 rc = ether_ioctl(ifp, cmd, data);
1870 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1872 struct vi_info *vi = ifp->if_softc;
1873 struct port_info *pi = vi->pi;
1874 struct adapter *sc = pi->adapter;
1875 struct sge_txq *txq;
1880 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1882 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1887 rc = parse_pkt(sc, &m);
1888 if (__predict_false(rc != 0)) {
1889 MPASS(m == NULL); /* was freed already */
1890 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1894 if (m->m_pkthdr.snd_tag != NULL) {
1895 /* EAGAIN tells the stack we are not the correct interface. */
1896 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) {
1901 return (ethofld_transmit(ifp, m));
1906 txq = &sc->sge.txq[vi->first_txq];
1907 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1908 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1912 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1913 if (__predict_false(rc != 0))
1920 cxgbe_qflush(struct ifnet *ifp)
1922 struct vi_info *vi = ifp->if_softc;
1923 struct sge_txq *txq;
1926 /* queues do not exist if !VI_INIT_DONE. */
1927 if (vi->flags & VI_INIT_DONE) {
1928 for_each_txq(vi, i, txq) {
1930 txq->eq.flags |= EQ_QFLUSH;
1932 while (!mp_ring_is_idle(txq->r)) {
1933 mp_ring_check_drainage(txq->r, 0);
1937 txq->eq.flags &= ~EQ_QFLUSH;
1945 vi_get_counter(struct ifnet *ifp, ift_counter c)
1947 struct vi_info *vi = ifp->if_softc;
1948 struct fw_vi_stats_vf *s = &vi->stats;
1950 vi_refresh_stats(vi->pi->adapter, vi);
1953 case IFCOUNTER_IPACKETS:
1954 return (s->rx_bcast_frames + s->rx_mcast_frames +
1955 s->rx_ucast_frames);
1956 case IFCOUNTER_IERRORS:
1957 return (s->rx_err_frames);
1958 case IFCOUNTER_OPACKETS:
1959 return (s->tx_bcast_frames + s->tx_mcast_frames +
1960 s->tx_ucast_frames + s->tx_offload_frames);
1961 case IFCOUNTER_OERRORS:
1962 return (s->tx_drop_frames);
1963 case IFCOUNTER_IBYTES:
1964 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
1966 case IFCOUNTER_OBYTES:
1967 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
1968 s->tx_ucast_bytes + s->tx_offload_bytes);
1969 case IFCOUNTER_IMCASTS:
1970 return (s->rx_mcast_frames);
1971 case IFCOUNTER_OMCASTS:
1972 return (s->tx_mcast_frames);
1973 case IFCOUNTER_OQDROPS: {
1977 if (vi->flags & VI_INIT_DONE) {
1979 struct sge_txq *txq;
1981 for_each_txq(vi, i, txq)
1982 drops += counter_u64_fetch(txq->r->drops);
1990 return (if_get_counter_default(ifp, c));
1995 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
1997 struct vi_info *vi = ifp->if_softc;
1998 struct port_info *pi = vi->pi;
1999 struct adapter *sc = pi->adapter;
2000 struct port_stats *s = &pi->stats;
2002 if (pi->nvi > 1 || sc->flags & IS_VF)
2003 return (vi_get_counter(ifp, c));
2005 cxgbe_refresh_stats(sc, pi);
2008 case IFCOUNTER_IPACKETS:
2009 return (s->rx_frames);
2011 case IFCOUNTER_IERRORS:
2012 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2013 s->rx_fcs_err + s->rx_len_err);
2015 case IFCOUNTER_OPACKETS:
2016 return (s->tx_frames);
2018 case IFCOUNTER_OERRORS:
2019 return (s->tx_error_frames);
2021 case IFCOUNTER_IBYTES:
2022 return (s->rx_octets);
2024 case IFCOUNTER_OBYTES:
2025 return (s->tx_octets);
2027 case IFCOUNTER_IMCASTS:
2028 return (s->rx_mcast_frames);
2030 case IFCOUNTER_OMCASTS:
2031 return (s->tx_mcast_frames);
2033 case IFCOUNTER_IQDROPS:
2034 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2035 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2036 s->rx_trunc3 + pi->tnl_cong_drops);
2038 case IFCOUNTER_OQDROPS: {
2042 if (vi->flags & VI_INIT_DONE) {
2044 struct sge_txq *txq;
2046 for_each_txq(vi, i, txq)
2047 drops += counter_u64_fetch(txq->r->drops);
2055 return (if_get_counter_default(ifp, c));
2060 * The kernel picks a media from the list we had provided so we do not have to
2061 * validate the request.
2064 cxgbe_media_change(struct ifnet *ifp)
2066 struct vi_info *vi = ifp->if_softc;
2067 struct port_info *pi = vi->pi;
2068 struct ifmedia *ifm = &pi->media;
2069 struct link_config *lc = &pi->link_cfg;
2070 struct adapter *sc = pi->adapter;
2073 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2077 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2078 MPASS(lc->supported & FW_PORT_CAP_ANEG);
2079 lc->requested_aneg = AUTONEG_ENABLE;
2081 lc->requested_aneg = AUTONEG_DISABLE;
2082 lc->requested_speed =
2083 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2084 lc->requested_fc = 0;
2085 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2086 lc->requested_fc |= PAUSE_RX;
2087 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2088 lc->requested_fc |= PAUSE_TX;
2091 rc = apply_l1cfg(pi);
2093 end_synchronized_op(sc, 0);
2098 * Mbps to FW_PORT_CAP_SPEED_* bit.
2101 speed_to_fwspeed(int speed)
2106 return (FW_PORT_CAP_SPEED_100G);
2108 return (FW_PORT_CAP_SPEED_40G);
2110 return (FW_PORT_CAP_SPEED_25G);
2112 return (FW_PORT_CAP_SPEED_10G);
2114 return (FW_PORT_CAP_SPEED_1G);
2116 return (FW_PORT_CAP_SPEED_100M);
2123 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2127 port_mword(struct port_info *pi, uint16_t speed)
2130 MPASS(speed & M_FW_PORT_CAP_SPEED);
2131 MPASS(powerof2(speed));
2133 switch(pi->port_type) {
2134 case FW_PORT_TYPE_BT_SGMII:
2135 case FW_PORT_TYPE_BT_XFI:
2136 case FW_PORT_TYPE_BT_XAUI:
2139 case FW_PORT_CAP_SPEED_100M:
2141 case FW_PORT_CAP_SPEED_1G:
2142 return (IFM_1000_T);
2143 case FW_PORT_CAP_SPEED_10G:
2147 case FW_PORT_TYPE_KX4:
2148 if (speed == FW_PORT_CAP_SPEED_10G)
2149 return (IFM_10G_KX4);
2151 case FW_PORT_TYPE_CX4:
2152 if (speed == FW_PORT_CAP_SPEED_10G)
2153 return (IFM_10G_CX4);
2155 case FW_PORT_TYPE_KX:
2156 if (speed == FW_PORT_CAP_SPEED_1G)
2157 return (IFM_1000_KX);
2159 case FW_PORT_TYPE_KR:
2160 case FW_PORT_TYPE_BP_AP:
2161 case FW_PORT_TYPE_BP4_AP:
2162 case FW_PORT_TYPE_BP40_BA:
2163 case FW_PORT_TYPE_KR4_100G:
2164 case FW_PORT_TYPE_KR_SFP28:
2165 case FW_PORT_TYPE_KR_XLAUI:
2167 case FW_PORT_CAP_SPEED_1G:
2168 return (IFM_1000_KX);
2169 case FW_PORT_CAP_SPEED_10G:
2170 return (IFM_10G_KR);
2171 case FW_PORT_CAP_SPEED_25G:
2172 return (IFM_25G_KR);
2173 case FW_PORT_CAP_SPEED_40G:
2174 return (IFM_40G_KR4);
2175 case FW_PORT_CAP_SPEED_100G:
2176 return (IFM_100G_KR4);
2179 case FW_PORT_TYPE_FIBER_XFI:
2180 case FW_PORT_TYPE_FIBER_XAUI:
2181 case FW_PORT_TYPE_SFP:
2182 case FW_PORT_TYPE_QSFP_10G:
2183 case FW_PORT_TYPE_QSA:
2184 case FW_PORT_TYPE_QSFP:
2185 case FW_PORT_TYPE_CR4_QSFP:
2186 case FW_PORT_TYPE_CR_QSFP:
2187 case FW_PORT_TYPE_CR2_QSFP:
2188 case FW_PORT_TYPE_SFP28:
2189 /* Pluggable transceiver */
2190 switch (pi->mod_type) {
2191 case FW_PORT_MOD_TYPE_LR:
2193 case FW_PORT_CAP_SPEED_1G:
2194 return (IFM_1000_LX);
2195 case FW_PORT_CAP_SPEED_10G:
2196 return (IFM_10G_LR);
2197 case FW_PORT_CAP_SPEED_25G:
2198 return (IFM_25G_LR);
2199 case FW_PORT_CAP_SPEED_40G:
2200 return (IFM_40G_LR4);
2201 case FW_PORT_CAP_SPEED_100G:
2202 return (IFM_100G_LR4);
2205 case FW_PORT_MOD_TYPE_SR:
2207 case FW_PORT_CAP_SPEED_1G:
2208 return (IFM_1000_SX);
2209 case FW_PORT_CAP_SPEED_10G:
2210 return (IFM_10G_SR);
2211 case FW_PORT_CAP_SPEED_25G:
2212 return (IFM_25G_SR);
2213 case FW_PORT_CAP_SPEED_40G:
2214 return (IFM_40G_SR4);
2215 case FW_PORT_CAP_SPEED_100G:
2216 return (IFM_100G_SR4);
2219 case FW_PORT_MOD_TYPE_ER:
2220 if (speed == FW_PORT_CAP_SPEED_10G)
2221 return (IFM_10G_ER);
2223 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2224 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2226 case FW_PORT_CAP_SPEED_1G:
2227 return (IFM_1000_CX);
2228 case FW_PORT_CAP_SPEED_10G:
2229 return (IFM_10G_TWINAX);
2230 case FW_PORT_CAP_SPEED_25G:
2231 return (IFM_25G_CR);
2232 case FW_PORT_CAP_SPEED_40G:
2233 return (IFM_40G_CR4);
2234 case FW_PORT_CAP_SPEED_100G:
2235 return (IFM_100G_CR4);
2238 case FW_PORT_MOD_TYPE_LRM:
2239 if (speed == FW_PORT_CAP_SPEED_10G)
2240 return (IFM_10G_LRM);
2242 case FW_PORT_MOD_TYPE_NA:
2243 MPASS(0); /* Not pluggable? */
2245 case FW_PORT_MOD_TYPE_ERROR:
2246 case FW_PORT_MOD_TYPE_UNKNOWN:
2247 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2249 case FW_PORT_MOD_TYPE_NONE:
2253 case FW_PORT_TYPE_NONE:
2257 return (IFM_UNKNOWN);
2261 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2263 struct vi_info *vi = ifp->if_softc;
2264 struct port_info *pi = vi->pi;
2265 struct adapter *sc = pi->adapter;
2266 struct link_config *lc = &pi->link_cfg;
2268 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2272 if (pi->up_vis == 0) {
2274 * If all the interfaces are administratively down the firmware
2275 * does not report transceiver changes. Refresh port info here
2276 * so that ifconfig displays accurate ifmedia at all times.
2277 * This is the only reason we have a synchronized op in this
2278 * function. Just PORT_LOCK would have been enough otherwise.
2280 t4_update_port_info(pi);
2281 build_medialist(pi, &pi->media);
2285 ifmr->ifm_status = IFM_AVALID;
2286 if (lc->link_ok == 0)
2288 ifmr->ifm_status |= IFM_ACTIVE;
2291 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2292 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2293 if (lc->fc & PAUSE_RX)
2294 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2295 if (lc->fc & PAUSE_TX)
2296 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2297 ifmr->ifm_active |= port_mword(pi, speed_to_fwspeed(lc->speed));
2300 end_synchronized_op(sc, 0);
2304 vcxgbe_probe(device_t dev)
2307 struct vi_info *vi = device_get_softc(dev);
2309 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2311 device_set_desc_copy(dev, buf);
2313 return (BUS_PROBE_DEFAULT);
2317 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2319 int func, index, rc;
2320 uint32_t param, val;
2322 ASSERT_SYNCHRONIZED_OP(sc);
2324 index = vi - pi->vi;
2325 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2326 KASSERT(index < nitems(vi_mac_funcs),
2327 ("%s: VI %s doesn't have a MAC func", __func__,
2328 device_get_nameunit(vi->dev)));
2329 func = vi_mac_funcs[index];
2330 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2331 vi->hw_addr, &vi->rss_size, func, 0);
2333 device_printf(vi->dev, "failed to allocate virtual interface %d"
2334 "for port %d: %d\n", index, pi->port_id, -rc);
2338 if (chip_id(sc) <= CHELSIO_T5)
2339 vi->smt_idx = (rc & 0x7f) << 1;
2341 vi->smt_idx = (rc & 0x7f);
2343 if (vi->rss_size == 1) {
2345 * This VI didn't get a slice of the RSS table. Reduce the
2346 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2347 * configuration file (nvi, rssnvi for this PF) if this is a
2350 device_printf(vi->dev, "RSS table not available.\n");
2351 vi->rss_base = 0xffff;
2356 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2357 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2358 V_FW_PARAMS_PARAM_YZ(vi->viid);
2359 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2361 vi->rss_base = 0xffff;
2363 MPASS((val >> 16) == vi->rss_size);
2364 vi->rss_base = val & 0xffff;
2371 vcxgbe_attach(device_t dev)
2374 struct port_info *pi;
2378 vi = device_get_softc(dev);
2382 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2385 rc = alloc_extra_vi(sc, pi, vi);
2386 end_synchronized_op(sc, 0);
2390 rc = cxgbe_vi_attach(dev, vi);
2392 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2399 vcxgbe_detach(device_t dev)
2404 vi = device_get_softc(dev);
2405 sc = vi->pi->adapter;
2409 cxgbe_vi_detach(vi);
2410 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2412 end_synchronized_op(sc, 0);
2418 t4_fatal_err(struct adapter *sc)
2420 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2421 t4_intr_disable(sc);
2422 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2423 device_get_nameunit(sc->dev));
2424 if (t4_panic_on_fatal_err)
2425 panic("panic requested on fatal error");
2429 t4_add_adapter(struct adapter *sc)
2431 sx_xlock(&t4_list_lock);
2432 SLIST_INSERT_HEAD(&t4_list, sc, link);
2433 sx_xunlock(&t4_list_lock);
2437 t4_map_bars_0_and_4(struct adapter *sc)
2439 sc->regs_rid = PCIR_BAR(0);
2440 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2441 &sc->regs_rid, RF_ACTIVE);
2442 if (sc->regs_res == NULL) {
2443 device_printf(sc->dev, "cannot map registers.\n");
2446 sc->bt = rman_get_bustag(sc->regs_res);
2447 sc->bh = rman_get_bushandle(sc->regs_res);
2448 sc->mmio_len = rman_get_size(sc->regs_res);
2449 setbit(&sc->doorbells, DOORBELL_KDB);
2451 sc->msix_rid = PCIR_BAR(4);
2452 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2453 &sc->msix_rid, RF_ACTIVE);
2454 if (sc->msix_res == NULL) {
2455 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2463 t4_map_bar_2(struct adapter *sc)
2467 * T4: only iWARP driver uses the userspace doorbells. There is no need
2468 * to map it if RDMA is disabled.
2470 if (is_t4(sc) && sc->rdmacaps == 0)
2473 sc->udbs_rid = PCIR_BAR(2);
2474 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2475 &sc->udbs_rid, RF_ACTIVE);
2476 if (sc->udbs_res == NULL) {
2477 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2480 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2482 if (chip_id(sc) >= CHELSIO_T5) {
2483 setbit(&sc->doorbells, DOORBELL_UDB);
2484 #if defined(__i386__) || defined(__amd64__)
2485 if (t5_write_combine) {
2489 * Enable write combining on BAR2. This is the
2490 * userspace doorbell BAR and is split into 128B
2491 * (UDBS_SEG_SIZE) doorbell regions, each associated
2492 * with an egress queue. The first 64B has the doorbell
2493 * and the second 64B can be used to submit a tx work
2494 * request with an implicit doorbell.
2497 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2498 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2500 clrbit(&sc->doorbells, DOORBELL_UDB);
2501 setbit(&sc->doorbells, DOORBELL_WCWR);
2502 setbit(&sc->doorbells, DOORBELL_UDBWC);
2504 device_printf(sc->dev,
2505 "couldn't enable write combining: %d\n",
2509 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2510 t4_write_reg(sc, A_SGE_STAT_CFG,
2511 V_STATSOURCE_T5(7) | mode);
2515 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2520 struct memwin_init {
2525 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2526 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2527 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2528 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2531 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2532 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2533 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2534 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2538 setup_memwin(struct adapter *sc)
2540 const struct memwin_init *mw_init;
2547 * Read low 32b of bar0 indirectly via the hardware backdoor
2548 * mechanism. Works from within PCI passthrough environments
2549 * too, where rman_get_start() can return a different value. We
2550 * need to program the T4 memory window decoders with the actual
2551 * addresses that will be coming across the PCIe link.
2553 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2554 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2556 mw_init = &t4_memwin[0];
2558 /* T5+ use the relative offset inside the PCIe BAR */
2561 mw_init = &t5_memwin[0];
2564 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2565 rw_init(&mw->mw_lock, "memory window access");
2566 mw->mw_base = mw_init->base;
2567 mw->mw_aperture = mw_init->aperture;
2570 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2571 (mw->mw_base + bar0) | V_BIR(0) |
2572 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2573 rw_wlock(&mw->mw_lock);
2574 position_memwin(sc, i, 0);
2575 rw_wunlock(&mw->mw_lock);
2579 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2583 * Positions the memory window at the given address in the card's address space.
2584 * There are some alignment requirements and the actual position may be at an
2585 * address prior to the requested address. mw->mw_curpos always has the actual
2586 * position of the window.
2589 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2595 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2596 mw = &sc->memwin[idx];
2597 rw_assert(&mw->mw_lock, RA_WLOCKED);
2601 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2603 pf = V_PFNUM(sc->pf);
2604 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2606 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2607 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2608 t4_read_reg(sc, reg); /* flush */
2612 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2618 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2620 /* Memory can only be accessed in naturally aligned 4 byte units */
2621 if (addr & 3 || len & 3 || len <= 0)
2624 mw = &sc->memwin[idx];
2626 rw_rlock(&mw->mw_lock);
2627 mw_end = mw->mw_curpos + mw->mw_aperture;
2628 if (addr >= mw_end || addr < mw->mw_curpos) {
2629 /* Will need to reposition the window */
2630 if (!rw_try_upgrade(&mw->mw_lock)) {
2631 rw_runlock(&mw->mw_lock);
2632 rw_wlock(&mw->mw_lock);
2634 rw_assert(&mw->mw_lock, RA_WLOCKED);
2635 position_memwin(sc, idx, addr);
2636 rw_downgrade(&mw->mw_lock);
2637 mw_end = mw->mw_curpos + mw->mw_aperture;
2639 rw_assert(&mw->mw_lock, RA_RLOCKED);
2640 while (addr < mw_end && len > 0) {
2642 v = t4_read_reg(sc, mw->mw_base + addr -
2644 *val++ = le32toh(v);
2647 t4_write_reg(sc, mw->mw_base + addr -
2648 mw->mw_curpos, htole32(v));
2653 rw_runlock(&mw->mw_lock);
2660 alloc_atid_tab(struct tid_info *t, int flags)
2664 MPASS(t->natids > 0);
2665 MPASS(t->atid_tab == NULL);
2667 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2669 if (t->atid_tab == NULL)
2671 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2672 t->afree = t->atid_tab;
2673 t->atids_in_use = 0;
2674 for (i = 1; i < t->natids; i++)
2675 t->atid_tab[i - 1].next = &t->atid_tab[i];
2676 t->atid_tab[t->natids - 1].next = NULL;
2682 free_atid_tab(struct tid_info *t)
2685 KASSERT(t->atids_in_use == 0,
2686 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2688 if (mtx_initialized(&t->atid_lock))
2689 mtx_destroy(&t->atid_lock);
2690 free(t->atid_tab, M_CXGBE);
2695 alloc_atid(struct adapter *sc, void *ctx)
2697 struct tid_info *t = &sc->tids;
2700 mtx_lock(&t->atid_lock);
2702 union aopen_entry *p = t->afree;
2704 atid = p - t->atid_tab;
2705 MPASS(atid <= M_TID_TID);
2710 mtx_unlock(&t->atid_lock);
2715 lookup_atid(struct adapter *sc, int atid)
2717 struct tid_info *t = &sc->tids;
2719 return (t->atid_tab[atid].data);
2723 free_atid(struct adapter *sc, int atid)
2725 struct tid_info *t = &sc->tids;
2726 union aopen_entry *p = &t->atid_tab[atid];
2728 mtx_lock(&t->atid_lock);
2732 mtx_unlock(&t->atid_lock);
2736 queue_tid_release(struct adapter *sc, int tid)
2739 CXGBE_UNIMPLEMENTED("deferred tid release");
2743 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
2746 struct cpl_tid_release *req;
2748 wr = alloc_wrqe(sizeof(*req), ctrlq);
2750 queue_tid_release(sc, tid); /* defer */
2755 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
2761 t4_range_cmp(const void *a, const void *b)
2763 return ((const struct t4_range *)a)->start -
2764 ((const struct t4_range *)b)->start;
2768 * Verify that the memory range specified by the addr/len pair is valid within
2769 * the card's address space.
2772 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2774 struct t4_range mem_ranges[4], *r, *next;
2775 uint32_t em, addr_len;
2776 int i, n, remaining;
2778 /* Memory can only be accessed in naturally aligned 4 byte units */
2779 if (addr & 3 || len & 3 || len <= 0)
2782 /* Enabled memories */
2783 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2787 bzero(r, sizeof(mem_ranges));
2788 if (em & F_EDRAM0_ENABLE) {
2789 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2790 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2792 r->start = G_EDRAM0_BASE(addr_len) << 20;
2793 if (addr >= r->start &&
2794 addr + len <= r->start + r->size)
2800 if (em & F_EDRAM1_ENABLE) {
2801 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2802 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2804 r->start = G_EDRAM1_BASE(addr_len) << 20;
2805 if (addr >= r->start &&
2806 addr + len <= r->start + r->size)
2812 if (em & F_EXT_MEM_ENABLE) {
2813 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2814 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2816 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2817 if (addr >= r->start &&
2818 addr + len <= r->start + r->size)
2824 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2825 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2826 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2828 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2829 if (addr >= r->start &&
2830 addr + len <= r->start + r->size)
2836 MPASS(n <= nitems(mem_ranges));
2839 /* Sort and merge the ranges. */
2840 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2842 /* Start from index 0 and examine the next n - 1 entries. */
2844 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2846 MPASS(r->size > 0); /* r is a valid entry. */
2848 MPASS(next->size > 0); /* and so is the next one. */
2850 while (r->start + r->size >= next->start) {
2851 /* Merge the next one into the current entry. */
2852 r->size = max(r->start + r->size,
2853 next->start + next->size) - r->start;
2854 n--; /* One fewer entry in total. */
2855 if (--remaining == 0)
2856 goto done; /* short circuit */
2859 if (next != r + 1) {
2861 * Some entries were merged into r and next
2862 * points to the first valid entry that couldn't
2865 MPASS(next->size > 0); /* must be valid */
2866 memcpy(r + 1, next, remaining * sizeof(*r));
2869 * This so that the foo->size assertion in the
2870 * next iteration of the loop do the right
2871 * thing for entries that were pulled up and are
2874 MPASS(n < nitems(mem_ranges));
2875 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2876 sizeof(struct t4_range));
2881 /* Done merging the ranges. */
2884 for (i = 0; i < n; i++, r++) {
2885 if (addr >= r->start &&
2886 addr + len <= r->start + r->size)
2895 fwmtype_to_hwmtype(int mtype)
2899 case FW_MEMTYPE_EDC0:
2901 case FW_MEMTYPE_EDC1:
2903 case FW_MEMTYPE_EXTMEM:
2905 case FW_MEMTYPE_EXTMEM1:
2908 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2913 * Verify that the memory range specified by the memtype/offset/len pair is
2914 * valid and lies entirely within the memtype specified. The global address of
2915 * the start of the range is returned in addr.
2918 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2921 uint32_t em, addr_len, maddr;
2923 /* Memory can only be accessed in naturally aligned 4 byte units */
2924 if (off & 3 || len & 3 || len == 0)
2927 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2928 switch (fwmtype_to_hwmtype(mtype)) {
2930 if (!(em & F_EDRAM0_ENABLE))
2932 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2933 maddr = G_EDRAM0_BASE(addr_len) << 20;
2936 if (!(em & F_EDRAM1_ENABLE))
2938 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2939 maddr = G_EDRAM1_BASE(addr_len) << 20;
2942 if (!(em & F_EXT_MEM_ENABLE))
2944 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2945 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2948 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2950 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2951 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2957 *addr = maddr + off; /* global address */
2958 return (validate_mem_range(sc, *addr, len));
2962 fixup_devlog_params(struct adapter *sc)
2964 struct devlog_params *dparams = &sc->params.devlog;
2967 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2968 dparams->size, &dparams->addr);
2974 update_nirq(struct intrs_and_queues *iaq, int nports)
2976 int extra = T4_EXTRA_INTR;
2979 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
2980 iaq->nirq += nports * (iaq->num_vis - 1) *
2981 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
2982 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
2986 * Adjust requirements to fit the number of interrupts available.
2989 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
2993 const int nports = sc->params.nports;
2998 bzero(iaq, sizeof(*iaq));
2999 iaq->intr_type = itype;
3000 iaq->num_vis = t4_num_vis;
3001 iaq->ntxq = t4_ntxq;
3002 iaq->ntxq_vi = t4_ntxq_vi;
3003 iaq->nrxq = t4_nrxq;
3004 iaq->nrxq_vi = t4_nrxq_vi;
3005 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3006 if (is_offload(sc) || is_ethoffload(sc)) {
3007 iaq->nofldtxq = t4_nofldtxq;
3008 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3012 if (is_offload(sc)) {
3013 iaq->nofldrxq = t4_nofldrxq;
3014 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3018 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3019 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3022 update_nirq(iaq, nports);
3023 if (iaq->nirq <= navail &&
3024 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3026 * This is the normal case -- there are enough interrupts for
3033 * If extra VIs have been configured try reducing their count and see if
3036 while (iaq->num_vis > 1) {
3038 update_nirq(iaq, nports);
3039 if (iaq->nirq <= navail &&
3040 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3041 device_printf(sc->dev, "virtual interfaces per port "
3042 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3043 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3044 "itype %d, navail %u, nirq %d.\n",
3045 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3046 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3047 itype, navail, iaq->nirq);
3053 * Extra VIs will not be created. Log a message if they were requested.
3055 MPASS(iaq->num_vis == 1);
3056 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3057 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3058 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3059 if (iaq->num_vis != t4_num_vis) {
3060 device_printf(sc->dev, "extra virtual interfaces disabled. "
3061 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3062 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3063 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3064 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3068 * Keep reducing the number of NIC rx queues to the next lower power of
3069 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3073 if (iaq->nrxq > 1) {
3076 } while (!powerof2(iaq->nrxq));
3078 if (iaq->nofldrxq > 1)
3079 iaq->nofldrxq >>= 1;
3081 old_nirq = iaq->nirq;
3082 update_nirq(iaq, nports);
3083 if (iaq->nirq <= navail &&
3084 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3085 device_printf(sc->dev, "running with reduced number of "
3086 "rx queues because of shortage of interrupts. "
3087 "nrxq=%u, nofldrxq=%u. "
3088 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3089 iaq->nofldrxq, itype, navail, iaq->nirq);
3092 } while (old_nirq != iaq->nirq);
3094 /* One interrupt for everything. Ugh. */
3095 device_printf(sc->dev, "running with minimal number of queues. "
3096 "itype %d, navail %u.\n", itype, navail);
3098 MPASS(iaq->nrxq == 1);
3100 if (iaq->nofldrxq > 1)
3103 MPASS(iaq->num_vis > 0);
3104 if (iaq->num_vis > 1) {
3105 MPASS(iaq->nrxq_vi > 0);
3106 MPASS(iaq->ntxq_vi > 0);
3108 MPASS(iaq->nirq > 0);
3109 MPASS(iaq->nrxq > 0);
3110 MPASS(iaq->ntxq > 0);
3111 if (itype == INTR_MSI) {
3112 MPASS(powerof2(iaq->nirq));
3117 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3119 int rc, itype, navail, nalloc;
3121 for (itype = INTR_MSIX; itype; itype >>= 1) {
3123 if ((itype & t4_intr_types) == 0)
3124 continue; /* not allowed */
3126 if (itype == INTR_MSIX)
3127 navail = pci_msix_count(sc->dev);
3128 else if (itype == INTR_MSI)
3129 navail = pci_msi_count(sc->dev);
3136 calculate_iaq(sc, iaq, itype, navail);
3139 if (itype == INTR_MSIX)
3140 rc = pci_alloc_msix(sc->dev, &nalloc);
3141 else if (itype == INTR_MSI)
3142 rc = pci_alloc_msi(sc->dev, &nalloc);
3144 if (rc == 0 && nalloc > 0) {
3145 if (nalloc == iaq->nirq)
3149 * Didn't get the number requested. Use whatever number
3150 * the kernel is willing to allocate.
3152 device_printf(sc->dev, "fewer vectors than requested, "
3153 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3154 itype, iaq->nirq, nalloc);
3155 pci_release_msi(sc->dev);
3160 device_printf(sc->dev,
3161 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3162 itype, rc, iaq->nirq, nalloc);
3165 device_printf(sc->dev,
3166 "failed to find a usable interrupt type. "
3167 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3168 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3173 #define FW_VERSION(chip) ( \
3174 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3175 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3176 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3177 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3178 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3184 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
3188 .kld_name = "t4fw_cfg",
3189 .fw_mod_name = "t4fw",
3191 .chip = FW_HDR_CHIP_T4,
3192 .fw_ver = htobe32(FW_VERSION(T4)),
3193 .intfver_nic = FW_INTFVER(T4, NIC),
3194 .intfver_vnic = FW_INTFVER(T4, VNIC),
3195 .intfver_ofld = FW_INTFVER(T4, OFLD),
3196 .intfver_ri = FW_INTFVER(T4, RI),
3197 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3198 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3199 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3200 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3204 .kld_name = "t5fw_cfg",
3205 .fw_mod_name = "t5fw",
3207 .chip = FW_HDR_CHIP_T5,
3208 .fw_ver = htobe32(FW_VERSION(T5)),
3209 .intfver_nic = FW_INTFVER(T5, NIC),
3210 .intfver_vnic = FW_INTFVER(T5, VNIC),
3211 .intfver_ofld = FW_INTFVER(T5, OFLD),
3212 .intfver_ri = FW_INTFVER(T5, RI),
3213 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3214 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3215 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3216 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3220 .kld_name = "t6fw_cfg",
3221 .fw_mod_name = "t6fw",
3223 .chip = FW_HDR_CHIP_T6,
3224 .fw_ver = htobe32(FW_VERSION(T6)),
3225 .intfver_nic = FW_INTFVER(T6, NIC),
3226 .intfver_vnic = FW_INTFVER(T6, VNIC),
3227 .intfver_ofld = FW_INTFVER(T6, OFLD),
3228 .intfver_ri = FW_INTFVER(T6, RI),
3229 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3230 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3231 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3232 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3237 static struct fw_info *
3238 find_fw_info(int chip)
3242 for (i = 0; i < nitems(fw_info); i++) {
3243 if (fw_info[i].chip == chip)
3244 return (&fw_info[i]);
3250 * Is the given firmware API compatible with the one the driver was compiled
3254 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3257 /* short circuit if it's the exact same firmware version */
3258 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3262 * XXX: Is this too conservative? Perhaps I should limit this to the
3263 * features that are supported in the driver.
3265 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3266 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3267 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3268 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3276 * The firmware in the KLD is usable, but should it be installed? This routine
3277 * explains itself in detail if it indicates the KLD firmware should be
3281 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
3285 if (!card_fw_usable) {
3286 reason = "incompatible or unusable";
3291 reason = "older than the version bundled with this driver";
3295 if (t4_fw_install == 2 && k != c) {
3296 reason = "different than the version bundled with this driver";
3303 if (t4_fw_install == 0) {
3304 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3305 "but the driver is prohibited from installing a different "
3306 "firmware on the card.\n",
3307 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3308 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3313 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3314 "installing firmware %u.%u.%u.%u on card.\n",
3315 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3316 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3317 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3318 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3324 * Establish contact with the firmware and determine if we are the master driver
3325 * or not, and whether we are responsible for chip initialization.
3328 prep_firmware(struct adapter *sc)
3330 const struct firmware *fw = NULL, *default_cfg;
3331 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
3332 enum dev_state state;
3333 struct fw_info *fw_info;
3334 struct fw_hdr *card_fw; /* fw on the card */
3335 const struct fw_hdr *kld_fw; /* fw in the KLD */
3336 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
3339 /* This is the firmware whose headers the driver was compiled against */
3340 fw_info = find_fw_info(chip_id(sc));
3341 if (fw_info == NULL) {
3342 device_printf(sc->dev,
3343 "unable to look up firmware information for chip %d.\n",
3347 drv_fw = &fw_info->fw_hdr;
3350 * The firmware KLD contains many modules. The KLD name is also the
3351 * name of the module that contains the default config file.
3353 default_cfg = firmware_get(fw_info->kld_name);
3355 /* This is the firmware in the KLD */
3356 fw = firmware_get(fw_info->fw_mod_name);
3358 kld_fw = (const void *)fw->data;
3359 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3365 /* Read the header of the firmware on the card */
3366 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3367 rc = -t4_read_flash(sc, FLASH_FW_START,
3368 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3370 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3371 if (card_fw->fw_ver == be32toh(0xffffffff)) {
3372 uint32_t d = be32toh(kld_fw->fw_ver);
3374 if (!kld_fw_usable) {
3375 device_printf(sc->dev,
3376 "no firmware on the card and no usable "
3377 "firmware bundled with the driver.\n");
3380 } else if (t4_fw_install == 0) {
3381 device_printf(sc->dev,
3382 "no firmware on the card and the driver "
3383 "is prohibited from installing new "
3389 device_printf(sc->dev, "no firmware on the card, "
3390 "installing firmware %d.%d.%d.%d\n",
3391 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3392 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3393 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize);
3396 device_printf(sc->dev,
3397 "firmware install failed: %d.\n", rc);
3400 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3405 device_printf(sc->dev,
3406 "Unable to read card's firmware header: %d\n", rc);
3410 /* Contact firmware. */
3411 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3412 if (rc < 0 || state == DEV_STATE_ERR) {
3414 device_printf(sc->dev,
3415 "failed to connect to the firmware: %d, %d.\n", rc, state);
3420 sc->flags |= MASTER_PF;
3421 else if (state == DEV_STATE_UNINIT) {
3423 * We didn't get to be the master so we definitely won't be
3424 * configuring the chip. It's a bug if someone else hasn't
3425 * configured it already.
3427 device_printf(sc->dev, "couldn't be master(%d), "
3428 "device not already initialized either(%d).\n", rc, state);
3433 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3434 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3436 * Common case: the firmware on the card is an exact match and
3437 * the KLD is an exact match too, or the KLD is
3438 * absent/incompatible. Note that t4_fw_install = 2 is ignored
3439 * here -- use cxgbetool loadfw if you want to reinstall the
3440 * same firmware as the one on the card.
3442 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3443 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3444 be32toh(card_fw->fw_ver))) {
3446 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3448 device_printf(sc->dev,
3449 "failed to install firmware: %d\n", rc);
3453 /* Installed successfully, update the cached header too. */
3454 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3456 need_fw_reset = 0; /* already reset as part of load_fw */
3459 if (!card_fw_usable) {
3462 d = ntohl(drv_fw->fw_ver);
3463 c = ntohl(card_fw->fw_ver);
3464 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3466 device_printf(sc->dev, "Cannot find a usable firmware: "
3467 "fw_install %d, chip state %d, "
3468 "driver compiled with %d.%d.%d.%d, "
3469 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3470 t4_fw_install, state,
3471 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3472 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3473 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3474 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3475 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3476 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3482 if (need_fw_reset &&
3483 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3484 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3485 if (rc != ETIMEDOUT && rc != EIO)
3486 t4_fw_bye(sc, sc->mbox);
3491 rc = get_params__pre_init(sc);
3493 goto done; /* error message displayed already */
3495 /* Partition adapter resources as specified in the config file. */
3496 if (state == DEV_STATE_UNINIT) {
3498 KASSERT(sc->flags & MASTER_PF,
3499 ("%s: trying to change chip settings when not master.",
3502 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3504 goto done; /* error message displayed already */
3506 t4_tweak_chip_settings(sc);
3508 /* get basic stuff going */
3509 rc = -t4_fw_initialize(sc, sc->mbox);
3511 device_printf(sc->dev, "fw init failed: %d.\n", rc);
3515 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3520 free(card_fw, M_CXGBE);
3522 firmware_put(fw, FIRMWARE_UNLOAD);
3523 if (default_cfg != NULL)
3524 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3529 #define FW_PARAM_DEV(param) \
3530 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3531 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3532 #define FW_PARAM_PFVF(param) \
3533 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3534 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3537 * Partition chip resources for use between various PFs, VFs, etc.
3540 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3541 const char *name_prefix)
3543 const struct firmware *cfg = NULL;
3545 struct fw_caps_config_cmd caps;
3546 uint32_t mtype, moff, finicsum, cfcsum;
3549 * Figure out what configuration file to use. Pick the default config
3550 * file for the card if the user hasn't specified one explicitly.
3552 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3553 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3554 /* Card specific overrides go here. */
3555 if (pci_get_device(sc->dev) == 0x440a)
3556 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3558 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3559 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0)
3560 goto use_built_in_config; /* go straight to config. */
3563 * We need to load another module if the profile is anything except
3564 * "default" or "flash".
3566 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3567 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3570 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3571 cfg = firmware_get(s);
3573 if (default_cfg != NULL) {
3574 device_printf(sc->dev,
3575 "unable to load module \"%s\" for "
3576 "configuration profile \"%s\", will use "
3577 "the default config file instead.\n",
3579 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3582 device_printf(sc->dev,
3583 "unable to load module \"%s\" for "
3584 "configuration profile \"%s\", will use "
3585 "the config file on the card's flash "
3586 "instead.\n", s, sc->cfg_file);
3587 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3593 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3594 default_cfg == NULL) {
3595 device_printf(sc->dev,
3596 "default config file not available, will use the config "
3597 "file on the card's flash instead.\n");
3598 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3601 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3603 const uint32_t *cfdata;
3604 uint32_t param, val, addr;
3606 KASSERT(cfg != NULL || default_cfg != NULL,
3607 ("%s: no config to upload", __func__));
3610 * Ask the firmware where it wants us to upload the config file.
3612 param = FW_PARAM_DEV(CF);
3613 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3615 /* No support for config file? Shouldn't happen. */
3616 device_printf(sc->dev,
3617 "failed to query config file location: %d.\n", rc);
3620 mtype = G_FW_PARAMS_PARAM_Y(val);
3621 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3624 * XXX: sheer laziness. We deliberately added 4 bytes of
3625 * useless stuffing/comments at the end of the config file so
3626 * it's ok to simply throw away the last remaining bytes when
3627 * the config file is not an exact multiple of 4. This also
3628 * helps with the validate_mt_off_len check.
3631 cflen = cfg->datasize & ~3;
3634 cflen = default_cfg->datasize & ~3;
3635 cfdata = default_cfg->data;
3638 if (cflen > FLASH_CFG_MAX_SIZE) {
3639 device_printf(sc->dev,
3640 "config file too long (%d, max allowed is %d). "
3641 "Will try to use the config on the card, if any.\n",
3642 cflen, FLASH_CFG_MAX_SIZE);
3643 goto use_config_on_flash;
3646 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3648 device_printf(sc->dev,
3649 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3650 "Will try to use the config on the card, if any.\n",
3651 __func__, mtype, moff, cflen, rc);
3652 goto use_config_on_flash;
3654 write_via_memwin(sc, 2, addr, cfdata, cflen);
3656 use_config_on_flash:
3657 mtype = FW_MEMTYPE_FLASH;
3658 moff = t4_flash_cfg_addr(sc);
3661 bzero(&caps, sizeof(caps));
3662 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3663 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3664 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3665 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3666 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3667 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3669 device_printf(sc->dev,
3670 "failed to pre-process config file: %d "
3671 "(mtype %d, moff 0x%x). Will reset the firmware and retry "
3672 "with the built-in configuration.\n", rc, mtype, moff);
3674 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3676 device_printf(sc->dev,
3677 "firmware reset failed: %d.\n", rc);
3678 if (rc != ETIMEDOUT && rc != EIO) {
3679 t4_fw_bye(sc, sc->mbox);
3680 sc->flags &= ~FW_OK;
3684 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in");
3685 use_built_in_config:
3686 bzero(&caps, sizeof(caps));
3687 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3688 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3689 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3690 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3692 device_printf(sc->dev,
3693 "built-in configuration failed: %d.\n", rc);
3698 finicsum = be32toh(caps.finicsum);
3699 cfcsum = be32toh(caps.cfcsum);
3700 if (finicsum != cfcsum) {
3701 device_printf(sc->dev,
3702 "WARNING: config file checksum mismatch: %08x %08x\n",
3705 sc->cfcsum = cfcsum;
3707 #define LIMIT_CAPS(x) do { \
3708 caps.x &= htobe16(t4_##x##_allowed); \
3712 * Let the firmware know what features will (not) be used so it can tune
3713 * things accordingly.
3715 LIMIT_CAPS(nbmcaps);
3716 LIMIT_CAPS(linkcaps);
3717 LIMIT_CAPS(switchcaps);
3718 LIMIT_CAPS(niccaps);
3719 LIMIT_CAPS(toecaps);
3720 LIMIT_CAPS(rdmacaps);
3721 LIMIT_CAPS(cryptocaps);
3722 LIMIT_CAPS(iscsicaps);
3723 LIMIT_CAPS(fcoecaps);
3726 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
3728 * TOE and hashfilters are mutually exclusive. It is a config
3729 * file or firmware bug if both are reported as available. Try
3730 * to cope with the situation in non-debug builds by disabling
3733 MPASS(caps.toecaps == 0);
3740 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3741 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3742 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3743 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3745 device_printf(sc->dev,
3746 "failed to process config file: %d.\n", rc);
3750 firmware_put(cfg, FIRMWARE_UNLOAD);
3755 * Retrieve parameters that are needed (or nice to have) very early.
3758 get_params__pre_init(struct adapter *sc)
3761 uint32_t param[2], val[2];
3763 t4_get_version_info(sc);
3765 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3766 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3767 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3768 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3769 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3771 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3772 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3773 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3774 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3775 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3777 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3778 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3779 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3780 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3781 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3783 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3784 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3785 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3786 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3787 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3789 param[0] = FW_PARAM_DEV(PORTVEC);
3790 param[1] = FW_PARAM_DEV(CCLK);
3791 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3793 device_printf(sc->dev,
3794 "failed to query parameters (pre_init): %d.\n", rc);
3798 sc->params.portvec = val[0];
3799 sc->params.nports = bitcount32(val[0]);
3800 sc->params.vpd.cclk = val[1];
3802 /* Read device log parameters. */
3803 rc = -t4_init_devlog_params(sc, 1);
3805 fixup_devlog_params(sc);
3807 device_printf(sc->dev,
3808 "failed to get devlog parameters: %d.\n", rc);
3809 rc = 0; /* devlog isn't critical for device operation */
3816 * Retrieve various parameters that are of interest to the driver. The device
3817 * has been initialized by the firmware at this point.
3820 get_params__post_init(struct adapter *sc)
3823 uint32_t param[7], val[7];
3824 struct fw_caps_config_cmd caps;
3826 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3827 param[1] = FW_PARAM_PFVF(EQ_START);
3828 param[2] = FW_PARAM_PFVF(FILTER_START);
3829 param[3] = FW_PARAM_PFVF(FILTER_END);
3830 param[4] = FW_PARAM_PFVF(L2T_START);
3831 param[5] = FW_PARAM_PFVF(L2T_END);
3832 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3833 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
3834 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
3835 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
3837 device_printf(sc->dev,
3838 "failed to query parameters (post_init): %d.\n", rc);
3842 sc->sge.iq_start = val[0];
3843 sc->sge.eq_start = val[1];
3844 if (val[3] > val[2]) {
3845 sc->tids.ftid_base = val[2];
3846 sc->tids.ftid_end = val[3];
3847 sc->tids.nftids = val[3] - val[2] + 1;
3849 sc->vres.l2t.start = val[4];
3850 sc->vres.l2t.size = val[5] - val[4] + 1;
3851 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3852 ("%s: L2 table size (%u) larger than expected (%u)",
3853 __func__, sc->vres.l2t.size, L2T_SIZE));
3854 sc->params.core_vdd = val[6];
3857 * MPSBGMAP is queried separately because only recent firmwares support
3858 * it as a parameter and we don't want the compound query above to fail
3859 * on older firmwares.
3861 param[0] = FW_PARAM_DEV(MPSBGMAP);
3863 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3865 sc->params.mps_bg_map = val[0];
3867 sc->params.mps_bg_map = 0;
3870 * Determine whether the firmware supports the filter2 work request.
3871 * This is queried separately for the same reason as MPSBGMAP above.
3873 param[0] = FW_PARAM_DEV(FILTER2_WR);
3875 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3877 sc->params.filter2_wr_support = val[0] != 0;
3879 sc->params.filter2_wr_support = 0;
3881 /* get capabilites */
3882 bzero(&caps, sizeof(caps));
3883 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3884 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3885 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3886 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3888 device_printf(sc->dev,
3889 "failed to get card capabilities: %d.\n", rc);
3893 #define READ_CAPS(x) do { \
3894 sc->x = htobe16(caps.x); \
3897 READ_CAPS(linkcaps);
3898 READ_CAPS(switchcaps);
3901 READ_CAPS(rdmacaps);
3902 READ_CAPS(cryptocaps);
3903 READ_CAPS(iscsicaps);
3904 READ_CAPS(fcoecaps);
3906 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
3907 MPASS(chip_id(sc) > CHELSIO_T4);
3908 MPASS(sc->toecaps == 0);
3911 param[0] = FW_PARAM_DEV(NTID);
3912 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3914 device_printf(sc->dev,
3915 "failed to query HASHFILTER parameters: %d.\n", rc);
3918 sc->tids.ntids = val[0];
3919 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3920 sc->params.hash_filter = 1;
3922 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3923 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3924 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3925 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3926 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3928 device_printf(sc->dev,
3929 "failed to query NIC parameters: %d.\n", rc);
3932 if (val[1] > val[0]) {
3933 sc->tids.etid_base = val[0];
3934 sc->tids.etid_end = val[1];
3935 sc->tids.netids = val[1] - val[0] + 1;
3936 sc->params.eo_wr_cred = val[2];
3937 sc->params.ethoffload = 1;
3941 /* query offload-related parameters */
3942 param[0] = FW_PARAM_DEV(NTID);
3943 param[1] = FW_PARAM_PFVF(SERVER_START);
3944 param[2] = FW_PARAM_PFVF(SERVER_END);
3945 param[3] = FW_PARAM_PFVF(TDDP_START);
3946 param[4] = FW_PARAM_PFVF(TDDP_END);
3947 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3948 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3950 device_printf(sc->dev,
3951 "failed to query TOE parameters: %d.\n", rc);
3954 sc->tids.ntids = val[0];
3955 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3956 if (val[2] > val[1]) {
3957 sc->tids.stid_base = val[1];
3958 sc->tids.nstids = val[2] - val[1] + 1;
3960 sc->vres.ddp.start = val[3];
3961 sc->vres.ddp.size = val[4] - val[3] + 1;
3962 sc->params.ofldq_wr_cred = val[5];
3963 sc->params.offload = 1;
3966 * The firmware attempts memfree TOE configuration for -SO cards
3967 * and will report toecaps=0 if it runs out of resources (this
3968 * depends on the config file). It may not report 0 for other
3969 * capabilities dependent on the TOE in this case. Set them to
3970 * 0 here so that the driver doesn't bother tracking resources
3971 * that will never be used.
3977 param[0] = FW_PARAM_PFVF(STAG_START);
3978 param[1] = FW_PARAM_PFVF(STAG_END);
3979 param[2] = FW_PARAM_PFVF(RQ_START);
3980 param[3] = FW_PARAM_PFVF(RQ_END);
3981 param[4] = FW_PARAM_PFVF(PBL_START);
3982 param[5] = FW_PARAM_PFVF(PBL_END);
3983 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3985 device_printf(sc->dev,
3986 "failed to query RDMA parameters(1): %d.\n", rc);
3989 sc->vres.stag.start = val[0];
3990 sc->vres.stag.size = val[1] - val[0] + 1;
3991 sc->vres.rq.start = val[2];
3992 sc->vres.rq.size = val[3] - val[2] + 1;
3993 sc->vres.pbl.start = val[4];
3994 sc->vres.pbl.size = val[5] - val[4] + 1;
3996 param[0] = FW_PARAM_PFVF(SQRQ_START);
3997 param[1] = FW_PARAM_PFVF(SQRQ_END);
3998 param[2] = FW_PARAM_PFVF(CQ_START);
3999 param[3] = FW_PARAM_PFVF(CQ_END);
4000 param[4] = FW_PARAM_PFVF(OCQ_START);
4001 param[5] = FW_PARAM_PFVF(OCQ_END);
4002 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4004 device_printf(sc->dev,
4005 "failed to query RDMA parameters(2): %d.\n", rc);
4008 sc->vres.qp.start = val[0];
4009 sc->vres.qp.size = val[1] - val[0] + 1;
4010 sc->vres.cq.start = val[2];
4011 sc->vres.cq.size = val[3] - val[2] + 1;
4012 sc->vres.ocq.start = val[4];
4013 sc->vres.ocq.size = val[5] - val[4] + 1;
4015 param[0] = FW_PARAM_PFVF(SRQ_START);
4016 param[1] = FW_PARAM_PFVF(SRQ_END);
4017 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4018 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4019 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4021 device_printf(sc->dev,
4022 "failed to query RDMA parameters(3): %d.\n", rc);
4025 sc->vres.srq.start = val[0];
4026 sc->vres.srq.size = val[1] - val[0] + 1;
4027 sc->params.max_ordird_qp = val[2];
4028 sc->params.max_ird_adapter = val[3];
4030 if (sc->iscsicaps) {
4031 param[0] = FW_PARAM_PFVF(ISCSI_START);
4032 param[1] = FW_PARAM_PFVF(ISCSI_END);
4033 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4035 device_printf(sc->dev,
4036 "failed to query iSCSI parameters: %d.\n", rc);
4039 sc->vres.iscsi.start = val[0];
4040 sc->vres.iscsi.size = val[1] - val[0] + 1;
4042 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4043 param[0] = FW_PARAM_PFVF(TLS_START);
4044 param[1] = FW_PARAM_PFVF(TLS_END);
4045 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4047 device_printf(sc->dev,
4048 "failed to query TLS parameters: %d.\n", rc);
4051 sc->vres.key.start = val[0];
4052 sc->vres.key.size = val[1] - val[0] + 1;
4055 t4_init_sge_params(sc);
4058 * We've got the params we wanted to query via the firmware. Now grab
4059 * some others directly from the chip.
4061 rc = t4_read_chip_settings(sc);
4067 set_params__post_init(struct adapter *sc)
4069 uint32_t param, val;
4074 /* ask for encapsulated CPLs */
4075 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4077 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4081 * Override the TOE timers with user provided tunables. This is not the
4082 * recommended way to change the timers (the firmware config file is) so
4083 * these tunables are not documented.
4085 * All the timer tunables are in microseconds.
4087 if (t4_toe_keepalive_idle != 0) {
4088 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4089 v &= M_KEEPALIVEIDLE;
4090 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4091 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4093 if (t4_toe_keepalive_interval != 0) {
4094 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4095 v &= M_KEEPALIVEINTVL;
4096 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4097 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4099 if (t4_toe_keepalive_count != 0) {
4100 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4101 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4102 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4103 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4104 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4106 if (t4_toe_rexmt_min != 0) {
4107 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4109 t4_set_reg_field(sc, A_TP_RXT_MIN,
4110 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4112 if (t4_toe_rexmt_max != 0) {
4113 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4115 t4_set_reg_field(sc, A_TP_RXT_MAX,
4116 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4118 if (t4_toe_rexmt_count != 0) {
4119 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4120 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4121 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4122 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4123 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4125 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4126 if (t4_toe_rexmt_backoff[i] != -1) {
4127 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4128 shift = (i & 3) << 3;
4129 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4130 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4137 #undef FW_PARAM_PFVF
4141 t4_set_desc(struct adapter *sc)
4144 struct adapter_params *p = &sc->params;
4146 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4148 device_set_desc_copy(sc->dev, buf);
4152 ifmedia_add4(struct ifmedia *ifm, int m)
4155 ifmedia_add(ifm, m, 0, NULL);
4156 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4157 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4158 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4162 set_current_media(struct port_info *pi, struct ifmedia *ifm)
4164 struct link_config *lc;
4167 PORT_LOCK_ASSERT_OWNED(pi);
4169 /* Leave current media alone if it's already set to IFM_NONE. */
4170 if (ifm->ifm_cur != NULL &&
4171 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4175 if (lc->requested_aneg == AUTONEG_ENABLE &&
4176 lc->supported & FW_PORT_CAP_ANEG) {
4177 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4180 mword = IFM_ETHER | IFM_FDX;
4181 if (lc->requested_fc & PAUSE_TX)
4182 mword |= IFM_ETH_TXPAUSE;
4183 if (lc->requested_fc & PAUSE_RX)
4184 mword |= IFM_ETH_RXPAUSE;
4185 mword |= port_mword(pi, speed_to_fwspeed(lc->requested_speed));
4186 ifmedia_set(ifm, mword);
4190 build_medialist(struct port_info *pi, struct ifmedia *ifm)
4193 int unknown, mword, bit;
4194 struct link_config *lc;
4196 PORT_LOCK_ASSERT_OWNED(pi);
4198 if (pi->flags & FIXED_IFMEDIA)
4202 * First setup all the requested_ fields so that they comply with what's
4203 * supported by the port + transceiver. Note that this clobbers any
4204 * user preferences set via sysctl_pause_settings or sysctl_autoneg.
4209 * Now (re)build the ifmedia list.
4211 ifmedia_removeall(ifm);
4213 ss = G_FW_PORT_CAP_SPEED(lc->supported); /* Supported Speeds */
4214 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4217 MPASS(LIST_EMPTY(&ifm->ifm_list));
4218 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4219 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4224 for (bit = 0; bit < fls(ss); bit++) {
4226 MPASS(speed & M_FW_PORT_CAP_SPEED);
4228 mword = port_mword(pi, speed);
4229 if (mword == IFM_NONE) {
4231 } else if (mword == IFM_UNKNOWN)
4234 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4237 if (unknown > 0) /* Add one unknown for all unknown media types. */
4238 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4239 if (lc->supported & FW_PORT_CAP_ANEG)
4240 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4242 set_current_media(pi, ifm);
4246 * Update all the requested_* fields in the link config to something valid (and
4250 init_l1cfg(struct port_info *pi)
4252 struct link_config *lc = &pi->link_cfg;
4254 PORT_LOCK_ASSERT_OWNED(pi);
4257 lc->requested_speed = port_top_speed(pi) * 1000;
4259 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) {
4260 lc->requested_aneg = AUTONEG_ENABLE;
4262 lc->requested_aneg = AUTONEG_DISABLE;
4265 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX);
4268 if (t4_fec & FEC_RS && lc->supported & FW_PORT_CAP_FEC_RS) {
4269 lc->requested_fec = FEC_RS;
4270 } else if (t4_fec & FEC_BASER_RS &&
4271 lc->supported & FW_PORT_CAP_FEC_BASER_RS) {
4272 lc->requested_fec = FEC_BASER_RS;
4274 lc->requested_fec = 0;
4277 /* Use the suggested value provided by the firmware in acaps */
4278 if (lc->advertising & FW_PORT_CAP_FEC_RS &&
4279 lc->supported & FW_PORT_CAP_FEC_RS) {
4280 lc->requested_fec = FEC_RS;
4281 } else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS &&
4282 lc->supported & FW_PORT_CAP_FEC_BASER_RS) {
4283 lc->requested_fec = FEC_BASER_RS;
4285 lc->requested_fec = 0;
4291 * Apply the settings in requested_* to the hardware. The parameters are
4292 * expected to be sane.
4295 apply_l1cfg(struct port_info *pi)
4297 struct adapter *sc = pi->adapter;
4298 struct link_config *lc = &pi->link_cfg;
4303 ASSERT_SYNCHRONIZED_OP(sc);
4304 PORT_LOCK_ASSERT_OWNED(pi);
4306 if (lc->requested_aneg == AUTONEG_ENABLE)
4307 MPASS(lc->supported & FW_PORT_CAP_ANEG);
4308 if (lc->requested_fc & PAUSE_TX)
4309 MPASS(lc->supported & FW_PORT_CAP_FC_TX);
4310 if (lc->requested_fc & PAUSE_RX)
4311 MPASS(lc->supported & FW_PORT_CAP_FC_RX);
4312 if (lc->requested_fec == FEC_RS)
4313 MPASS(lc->supported & FW_PORT_CAP_FEC_RS);
4314 if (lc->requested_fec == FEC_BASER_RS)
4315 MPASS(lc->supported & FW_PORT_CAP_FEC_BASER_RS);
4316 fwspeed = speed_to_fwspeed(lc->requested_speed);
4317 MPASS(fwspeed != 0);
4318 MPASS(lc->supported & fwspeed);
4320 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4322 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4324 lc->fc = lc->requested_fc;
4325 lc->fec = lc->requested_fec;
4330 #define FW_MAC_EXACT_CHUNK 7
4333 * Program the port's XGMAC based on parameters in ifnet. The caller also
4334 * indicates which parameters should be programmed (the rest are left alone).
4337 update_mac_settings(struct ifnet *ifp, int flags)
4340 struct vi_info *vi = ifp->if_softc;
4341 struct port_info *pi = vi->pi;
4342 struct adapter *sc = pi->adapter;
4343 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4345 ASSERT_SYNCHRONIZED_OP(sc);
4346 KASSERT(flags, ("%s: not told what to update.", __func__));
4348 if (flags & XGMAC_MTU)
4351 if (flags & XGMAC_PROMISC)
4352 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4354 if (flags & XGMAC_ALLMULTI)
4355 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4357 if (flags & XGMAC_VLANEX)
4358 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4360 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4361 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4362 allmulti, 1, vlanex, false);
4364 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4370 if (flags & XGMAC_UCADDR) {
4371 uint8_t ucaddr[ETHER_ADDR_LEN];
4373 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4374 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4375 ucaddr, true, true);
4378 if_printf(ifp, "change_mac failed: %d\n", rc);
4381 vi->xact_addr_filt = rc;
4386 if (flags & XGMAC_MCADDRS) {
4387 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4390 struct ifmultiaddr *ifma;
4393 if_maddr_rlock(ifp);
4394 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4395 if (ifma->ifma_addr->sa_family != AF_LINK)
4398 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4399 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4402 if (i == FW_MAC_EXACT_CHUNK) {
4403 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4404 del, i, mcaddr, NULL, &hash, 0);
4407 for (j = 0; j < i; j++) {
4409 "failed to add mc address"
4411 "%02x:%02x:%02x rc=%d\n",
4412 mcaddr[j][0], mcaddr[j][1],
4413 mcaddr[j][2], mcaddr[j][3],
4414 mcaddr[j][4], mcaddr[j][5],
4424 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4425 mcaddr, NULL, &hash, 0);
4428 for (j = 0; j < i; j++) {
4430 "failed to add mc address"
4432 "%02x:%02x:%02x rc=%d\n",
4433 mcaddr[j][0], mcaddr[j][1],
4434 mcaddr[j][2], mcaddr[j][3],
4435 mcaddr[j][4], mcaddr[j][5],
4442 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4444 if_printf(ifp, "failed to set mc address hash: %d", rc);
4446 if_maddr_runlock(ifp);
4453 * {begin|end}_synchronized_op must be called from the same thread.
4456 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4462 /* the caller thinks it's ok to sleep, but is it really? */
4463 if (flags & SLEEP_OK)
4464 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4465 "begin_synchronized_op");
4476 if (vi && IS_DOOMED(vi)) {
4486 if (!(flags & SLEEP_OK)) {
4491 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4497 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4500 sc->last_op = wmesg;
4501 sc->last_op_thr = curthread;
4502 sc->last_op_flags = flags;
4506 if (!(flags & HOLD_LOCK) || rc)
4513 * Tell if_ioctl and if_init that the VI is going away. This is
4514 * special variant of begin_synchronized_op and must be paired with a
4515 * call to end_synchronized_op.
4518 doom_vi(struct adapter *sc, struct vi_info *vi)
4525 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4528 sc->last_op = "t4detach";
4529 sc->last_op_thr = curthread;
4530 sc->last_op_flags = 0;
4536 * {begin|end}_synchronized_op must be called from the same thread.
4539 end_synchronized_op(struct adapter *sc, int flags)
4542 if (flags & LOCK_HELD)
4543 ADAPTER_LOCK_ASSERT_OWNED(sc);
4547 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4554 cxgbe_init_synchronized(struct vi_info *vi)
4556 struct port_info *pi = vi->pi;
4557 struct adapter *sc = pi->adapter;
4558 struct ifnet *ifp = vi->ifp;
4560 struct sge_txq *txq;
4562 ASSERT_SYNCHRONIZED_OP(sc);
4564 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4565 return (0); /* already running */
4567 if (!(sc->flags & FULL_INIT_DONE) &&
4568 ((rc = adapter_full_init(sc)) != 0))
4569 return (rc); /* error message displayed already */
4571 if (!(vi->flags & VI_INIT_DONE) &&
4572 ((rc = vi_full_init(vi)) != 0))
4573 return (rc); /* error message displayed already */
4575 rc = update_mac_settings(ifp, XGMAC_ALL);
4577 goto done; /* error message displayed already */
4579 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4581 if_printf(ifp, "enable_vi failed: %d\n", rc);
4586 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
4590 for_each_txq(vi, i, txq) {
4592 txq->eq.flags |= EQ_ENABLED;
4597 * The first iq of the first port to come up is used for tracing.
4599 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4600 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4601 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
4602 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4603 V_QUEUENUMBER(sc->traceq));
4604 pi->flags |= HAS_TRACEQ;
4609 if (pi->up_vis++ == 0) {
4610 t4_update_port_info(pi);
4611 build_medialist(pi, &pi->media);
4614 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4616 if (pi->nvi > 1 || sc->flags & IS_VF)
4617 callout_reset(&vi->tick, hz, vi_tick, vi);
4619 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4623 cxgbe_uninit_synchronized(vi);
4632 cxgbe_uninit_synchronized(struct vi_info *vi)
4634 struct port_info *pi = vi->pi;
4635 struct adapter *sc = pi->adapter;
4636 struct ifnet *ifp = vi->ifp;
4638 struct sge_txq *txq;
4640 ASSERT_SYNCHRONIZED_OP(sc);
4642 if (!(vi->flags & VI_INIT_DONE)) {
4643 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4644 KASSERT(0, ("uninited VI is running"));
4645 if_printf(ifp, "uninited VI with running ifnet. "
4646 "vi->flags 0x%016lx, if_flags 0x%08x, "
4647 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
4654 * Disable the VI so that all its data in either direction is discarded
4655 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
4656 * tick) intact as the TP can deliver negative advice or data that it's
4657 * holding in its RAM (for an offloaded connection) even after the VI is
4660 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4662 if_printf(ifp, "disable_vi failed: %d\n", rc);
4666 for_each_txq(vi, i, txq) {
4668 txq->eq.flags &= ~EQ_ENABLED;
4673 if (pi->nvi > 1 || sc->flags & IS_VF)
4674 callout_stop(&vi->tick);
4676 callout_stop(&pi->tick);
4677 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4681 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4683 if (pi->up_vis > 0) {
4688 pi->link_cfg.link_ok = 0;
4689 pi->link_cfg.speed = 0;
4690 pi->link_cfg.link_down_rc = 255;
4691 t4_os_link_changed(pi);
4692 pi->old_link_cfg = pi->link_cfg;
4699 * It is ok for this function to fail midway and return right away. t4_detach
4700 * will walk the entire sc->irq list and clean up whatever is valid.
4703 t4_setup_intr_handlers(struct adapter *sc)
4705 int rc, rid, p, q, v;
4708 struct port_info *pi;
4710 struct sge *sge = &sc->sge;
4711 struct sge_rxq *rxq;
4713 struct sge_ofld_rxq *ofld_rxq;
4716 struct sge_nm_rxq *nm_rxq;
4719 int nbuckets = rss_getnumbuckets();
4726 rid = sc->intr_type == INTR_INTX ? 0 : 1;
4727 if (forwarding_intr_to_fwq(sc))
4728 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4730 /* Multiple interrupts. */
4731 if (sc->flags & IS_VF)
4732 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4733 ("%s: too few intr.", __func__));
4735 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4736 ("%s: too few intr.", __func__));
4738 /* The first one is always error intr on PFs */
4739 if (!(sc->flags & IS_VF)) {
4740 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4747 /* The second one is always the firmware event queue (first on VFs) */
4748 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4754 for_each_port(sc, p) {
4756 for_each_vi(pi, v, vi) {
4757 vi->first_intr = rid - 1;
4759 if (vi->nnmrxq > 0) {
4760 int n = max(vi->nrxq, vi->nnmrxq);
4762 rxq = &sge->rxq[vi->first_rxq];
4764 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4766 for (q = 0; q < n; q++) {
4767 snprintf(s, sizeof(s), "%x%c%x", p,
4773 irq->nm_rxq = nm_rxq++;
4775 rc = t4_alloc_irq(sc, irq, rid,
4776 t4_vi_intr, irq, s);
4781 bus_bind_intr(sc->dev, irq->res,
4782 rss_getcpu(q % nbuckets));
4790 for_each_rxq(vi, q, rxq) {
4791 snprintf(s, sizeof(s), "%x%c%x", p,
4793 rc = t4_alloc_irq(sc, irq, rid,
4798 bus_bind_intr(sc->dev, irq->res,
4799 rss_getcpu(q % nbuckets));
4807 for_each_ofld_rxq(vi, q, ofld_rxq) {
4808 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
4809 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
4820 MPASS(irq == &sc->irq[sc->intr_count]);
4826 adapter_full_init(struct adapter *sc)
4830 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4831 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4834 ASSERT_SYNCHRONIZED_OP(sc);
4835 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4836 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4837 ("%s: FULL_INIT_DONE already", __func__));
4840 * queues that belong to the adapter (not any particular port).
4842 rc = t4_setup_adapter_queues(sc);
4846 for (i = 0; i < nitems(sc->tq); i++) {
4847 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4848 taskqueue_thread_enqueue, &sc->tq[i]);
4849 if (sc->tq[i] == NULL) {
4850 device_printf(sc->dev,
4851 "failed to allocate task queue %d\n", i);
4855 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4856 device_get_nameunit(sc->dev), i);
4859 MPASS(RSS_KEYSIZE == 40);
4860 rss_getkey((void *)&raw_rss_key[0]);
4861 for (i = 0; i < nitems(rss_key); i++) {
4862 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4864 t4_write_rss_key(sc, &rss_key[0], -1, 1);
4867 if (!(sc->flags & IS_VF))
4869 sc->flags |= FULL_INIT_DONE;
4872 adapter_full_uninit(sc);
4878 adapter_full_uninit(struct adapter *sc)
4882 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4884 t4_teardown_adapter_queues(sc);
4886 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4887 taskqueue_free(sc->tq[i]);
4891 sc->flags &= ~FULL_INIT_DONE;
4897 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4898 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4899 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4900 RSS_HASHTYPE_RSS_UDP_IPV6)
4902 /* Translates kernel hash types to hardware. */
4904 hashconfig_to_hashen(int hashconfig)
4908 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4909 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4910 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4911 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4912 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4913 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4914 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4916 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4917 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4918 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4920 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4921 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4922 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4923 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4928 /* Translates hardware hash types to kernel. */
4930 hashen_to_hashconfig(int hashen)
4934 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4936 * If UDP hashing was enabled it must have been enabled for
4937 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4938 * enabling any 4-tuple hash is nonsense configuration.
4940 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4941 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4943 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4944 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4945 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4946 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4948 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4949 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4950 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4951 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4952 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4953 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4954 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4955 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4957 return (hashconfig);
4962 vi_full_init(struct vi_info *vi)
4964 struct adapter *sc = vi->pi->adapter;
4965 struct ifnet *ifp = vi->ifp;
4967 struct sge_rxq *rxq;
4968 int rc, i, j, hashen;
4970 int nbuckets = rss_getnumbuckets();
4971 int hashconfig = rss_gethashconfig();
4975 ASSERT_SYNCHRONIZED_OP(sc);
4976 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4977 ("%s: VI_INIT_DONE already", __func__));
4979 sysctl_ctx_init(&vi->ctx);
4980 vi->flags |= VI_SYSCTL_CTX;
4983 * Allocate tx/rx/fl queues for this VI.
4985 rc = t4_setup_vi_queues(vi);
4987 goto done; /* error message displayed already */
4990 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4992 if (vi->nrxq > vi->rss_size) {
4993 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4994 "some queues will never receive traffic.\n", vi->nrxq,
4996 } else if (vi->rss_size % vi->nrxq) {
4997 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4998 "expect uneven traffic distribution.\n", vi->nrxq,
5002 if (vi->nrxq != nbuckets) {
5003 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5004 "performance will be impacted.\n", vi->nrxq, nbuckets);
5007 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5008 for (i = 0; i < vi->rss_size;) {
5010 j = rss_get_indirection_to_bucket(i);
5012 rxq = &sc->sge.rxq[vi->first_rxq + j];
5013 rss[i++] = rxq->iq.abs_id;
5015 for_each_rxq(vi, j, rxq) {
5016 rss[i++] = rxq->iq.abs_id;
5017 if (i == vi->rss_size)
5023 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5026 if_printf(ifp, "rss_config failed: %d\n", rc);
5031 hashen = hashconfig_to_hashen(hashconfig);
5034 * We may have had to enable some hashes even though the global config
5035 * wants them disabled. This is a potential problem that must be
5036 * reported to the user.
5038 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
5041 * If we consider only the supported hash types, then the enabled hashes
5042 * are a superset of the requested hashes. In other words, there cannot
5043 * be any supported hash that was requested but not enabled, but there
5044 * can be hashes that were not requested but had to be enabled.
5046 extra &= SUPPORTED_RSS_HASHTYPES;
5047 MPASS((extra & hashconfig) == 0);
5051 "global RSS config (0x%x) cannot be accommodated.\n",
5054 if (extra & RSS_HASHTYPE_RSS_IPV4)
5055 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5056 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5057 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5058 if (extra & RSS_HASHTYPE_RSS_IPV6)
5059 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5060 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5061 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5062 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5063 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5064 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5065 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5067 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5068 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5069 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5070 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5072 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
5074 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5079 vi->flags |= VI_INIT_DONE;
5091 vi_full_uninit(struct vi_info *vi)
5093 struct port_info *pi = vi->pi;
5094 struct adapter *sc = pi->adapter;
5096 struct sge_rxq *rxq;
5097 struct sge_txq *txq;
5099 struct sge_ofld_rxq *ofld_rxq;
5100 struct sge_wrq *ofld_txq;
5103 if (vi->flags & VI_INIT_DONE) {
5105 /* Need to quiesce queues. */
5107 /* XXX: Only for the first VI? */
5108 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5109 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5111 for_each_txq(vi, i, txq) {
5112 quiesce_txq(sc, txq);
5116 for_each_ofld_txq(vi, i, ofld_txq) {
5117 quiesce_wrq(sc, ofld_txq);
5121 for_each_rxq(vi, i, rxq) {
5122 quiesce_iq(sc, &rxq->iq);
5123 quiesce_fl(sc, &rxq->fl);
5127 for_each_ofld_rxq(vi, i, ofld_rxq) {
5128 quiesce_iq(sc, &ofld_rxq->iq);
5129 quiesce_fl(sc, &ofld_rxq->fl);
5132 free(vi->rss, M_CXGBE);
5133 free(vi->nm_rss, M_CXGBE);
5136 t4_teardown_vi_queues(vi);
5137 vi->flags &= ~VI_INIT_DONE;
5143 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5145 struct sge_eq *eq = &txq->eq;
5146 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5148 (void) sc; /* unused */
5152 MPASS((eq->flags & EQ_ENABLED) == 0);
5156 /* Wait for the mp_ring to empty. */
5157 while (!mp_ring_is_idle(txq->r)) {
5158 mp_ring_check_drainage(txq->r, 0);
5159 pause("rquiesce", 1);
5162 /* Then wait for the hardware to finish. */
5163 while (spg->cidx != htobe16(eq->pidx))
5164 pause("equiesce", 1);
5166 /* Finally, wait for the driver to reclaim all descriptors. */
5167 while (eq->cidx != eq->pidx)
5168 pause("dquiesce", 1);
5172 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5179 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5181 (void) sc; /* unused */
5183 /* Synchronize with the interrupt handler */
5184 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5189 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5191 mtx_lock(&sc->sfl_lock);
5193 fl->flags |= FL_DOOMED;
5195 callout_stop(&sc->sfl_callout);
5196 mtx_unlock(&sc->sfl_lock);
5198 KASSERT((fl->flags & FL_STARVING) == 0,
5199 ("%s: still starving", __func__));
5203 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5204 driver_intr_t *handler, void *arg, char *name)
5209 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5210 RF_SHAREABLE | RF_ACTIVE);
5211 if (irq->res == NULL) {
5212 device_printf(sc->dev,
5213 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5217 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5218 NULL, handler, arg, &irq->tag);
5220 device_printf(sc->dev,
5221 "failed to setup interrupt for rid %d, name %s: %d\n",
5224 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5230 t4_free_irq(struct adapter *sc, struct irq *irq)
5233 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5235 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5237 bzero(irq, sizeof(*irq));
5243 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5246 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5247 t4_get_regs(sc, buf, regs->len);
5250 #define A_PL_INDIR_CMD 0x1f8
5252 #define S_PL_AUTOINC 31
5253 #define M_PL_AUTOINC 0x1U
5254 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5255 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5257 #define S_PL_VFID 20
5258 #define M_PL_VFID 0xffU
5259 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5260 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5263 #define M_PL_ADDR 0xfffffU
5264 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5265 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5267 #define A_PL_INDIR_DATA 0x1fc
5270 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5274 mtx_assert(&sc->reg_lock, MA_OWNED);
5275 if (sc->flags & IS_VF) {
5276 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5277 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5279 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5280 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5281 V_PL_ADDR(VF_MPS_REG(reg)));
5282 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5283 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5285 return (((uint64_t)stats[1]) << 32 | stats[0]);
5289 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5290 struct fw_vi_stats_vf *stats)
5293 #define GET_STAT(name) \
5294 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5296 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5297 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5298 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5299 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5300 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5301 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5302 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5303 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5304 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5305 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5306 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5307 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5308 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5309 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5310 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5311 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5317 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5321 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5322 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5323 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5324 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5325 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5326 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5330 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5333 const struct timeval interval = {0, 250000}; /* 250ms */
5335 if (!(vi->flags & VI_INIT_DONE))
5339 timevalsub(&tv, &interval);
5340 if (timevalcmp(&tv, &vi->last_refreshed, <))
5343 mtx_lock(&sc->reg_lock);
5344 t4_get_vi_stats(sc, vi->viid, &vi->stats);
5345 getmicrotime(&vi->last_refreshed);
5346 mtx_unlock(&sc->reg_lock);
5350 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5352 u_int i, v, tnl_cong_drops, bg_map;
5354 const struct timeval interval = {0, 250000}; /* 250ms */
5357 timevalsub(&tv, &interval);
5358 if (timevalcmp(&tv, &pi->last_refreshed, <))
5362 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5363 bg_map = pi->mps_bg_map;
5365 i = ffs(bg_map) - 1;
5366 mtx_lock(&sc->reg_lock);
5367 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5368 A_TP_MIB_TNL_CNG_DROP_0 + i);
5369 mtx_unlock(&sc->reg_lock);
5370 tnl_cong_drops += v;
5371 bg_map &= ~(1 << i);
5373 pi->tnl_cong_drops = tnl_cong_drops;
5374 getmicrotime(&pi->last_refreshed);
5378 cxgbe_tick(void *arg)
5380 struct port_info *pi = arg;
5381 struct adapter *sc = pi->adapter;
5383 PORT_LOCK_ASSERT_OWNED(pi);
5384 cxgbe_refresh_stats(sc, pi);
5386 callout_schedule(&pi->tick, hz);
5392 struct vi_info *vi = arg;
5393 struct adapter *sc = vi->pi->adapter;
5395 vi_refresh_stats(sc, vi);
5397 callout_schedule(&vi->tick, hz);
5401 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
5405 if (arg != ifp || ifp->if_type != IFT_ETHER)
5408 vlan = VLAN_DEVAT(ifp, vid);
5409 VLAN_SETCOOKIE(vlan, ifp);
5413 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5415 static char *caps_decoder[] = {
5416 "\20\001IPMI\002NCSI", /* 0: NBM */
5417 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5418 "\20\001INGRESS\002EGRESS", /* 2: switch */
5419 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5420 "\006HASHFILTER\007ETHOFLD",
5421 "\20\001TOE", /* 4: TOE */
5422 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5423 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5424 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5425 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5427 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5428 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5429 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5430 "\004PO_INITIATOR\005PO_TARGET",
5434 t4_sysctls(struct adapter *sc)
5436 struct sysctl_ctx_list *ctx;
5437 struct sysctl_oid *oid;
5438 struct sysctl_oid_list *children, *c0;
5439 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5441 ctx = device_get_sysctl_ctx(sc->dev);
5446 oid = device_get_sysctl_tree(sc->dev);
5447 c0 = children = SYSCTL_CHILDREN(oid);
5449 sc->sc_do_rxcopy = 1;
5450 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5451 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5453 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5454 sc->params.nports, "# of ports");
5456 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5457 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
5458 sysctl_bitfield_8b, "A", "available doorbells");
5460 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5461 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5464 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5465 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5466 "interrupt holdoff timer values (us)");
5468 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5469 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5470 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5471 "interrupt holdoff packet counter values");
5473 t4_sge_sysctls(sc, ctx, children);
5475 sc->lro_timeout = 100;
5476 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5477 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5479 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5480 &sc->debug_flags, 0, "flags to enable runtime debugging");
5482 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5483 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5485 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5486 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5488 if (sc->flags & IS_VF)
5491 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5492 NULL, chip_rev(sc), "chip hardware revision");
5494 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5495 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5497 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5498 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5500 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5501 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5503 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5504 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5506 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5507 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5509 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5510 sc->er_version, 0, "expansion ROM version");
5512 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5513 sc->bs_version, 0, "bootstrap firmware version");
5515 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5516 NULL, sc->params.scfg_vers, "serial config version");
5518 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5519 NULL, sc->params.vpd_vers, "VPD version");
5521 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5522 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5524 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5525 sc->cfcsum, "config file checksum");
5527 #define SYSCTL_CAP(name, n, text) \
5528 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5529 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
5530 sysctl_bitfield_16b, "A", "available " text " capabilities")
5532 SYSCTL_CAP(nbmcaps, 0, "NBM");
5533 SYSCTL_CAP(linkcaps, 1, "link");
5534 SYSCTL_CAP(switchcaps, 2, "switch");
5535 SYSCTL_CAP(niccaps, 3, "NIC");
5536 SYSCTL_CAP(toecaps, 4, "TCP offload");
5537 SYSCTL_CAP(rdmacaps, 5, "RDMA");
5538 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5539 SYSCTL_CAP(cryptocaps, 7, "crypto");
5540 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5543 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5544 NULL, sc->tids.nftids, "number of filters");
5546 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5547 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5548 "chip temperature (in Celsius)");
5550 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5551 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5552 "microprocessor load averages (debug firmwares only)");
5554 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5555 &sc->params.core_vdd, 0, "core Vdd (in mV)");
5557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
5558 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
5559 sysctl_cpus, "A", "local CPUs");
5561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
5562 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
5563 sysctl_cpus, "A", "preferred CPUs for interrupts");
5566 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5568 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5569 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5570 "logs and miscellaneous information");
5571 children = SYSCTL_CHILDREN(oid);
5573 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5574 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5575 sysctl_cctrl, "A", "congestion control");
5577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5578 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5579 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5582 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5583 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5586 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5587 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5589 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5590 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5591 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5594 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5595 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5598 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5599 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5601 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5602 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5603 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5604 "A", "CIM logic analyzer");
5606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5607 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5608 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5611 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5612 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5615 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5616 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5619 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5620 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5623 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5624 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5626 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5627 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5628 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5630 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5631 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5632 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5634 if (chip_id(sc) > CHELSIO_T4) {
5635 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5636 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5637 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5639 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5640 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5641 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5645 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5646 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5649 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5650 sysctl_cim_qcfg, "A", "CIM queue configuration");
5652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5653 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5654 sysctl_cpl_stats, "A", "CPL statistics");
5656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5657 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5658 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5660 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5661 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5662 sysctl_devlog, "A", "firmware's device log");
5664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5665 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5666 sysctl_fcoe_stats, "A", "FCoE statistics");
5668 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5669 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5670 sysctl_hw_sched, "A", "hardware scheduler ");
5672 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5673 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5674 sysctl_l2t, "A", "hardware L2 table");
5676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
5677 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5678 sysctl_smt, "A", "hardware source MAC table");
5680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5681 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5682 sysctl_lb_stats, "A", "loopback statistics");
5684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5685 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5686 sysctl_meminfo, "A", "memory regions");
5688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5689 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5690 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5691 "A", "MPS TCAM entries");
5693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5694 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5695 sysctl_path_mtus, "A", "path MTUs");
5697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5698 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5699 sysctl_pm_stats, "A", "PM statistics");
5701 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5702 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5703 sysctl_rdma_stats, "A", "RDMA statistics");
5705 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5706 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5707 sysctl_tcp_stats, "A", "TCP statistics");
5709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5710 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5711 sysctl_tids, "A", "TID information");
5713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5714 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5715 sysctl_tp_err_stats, "A", "TP error statistics");
5717 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5718 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5719 "TP logic analyzer event capture mask");
5721 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5722 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5723 sysctl_tp_la, "A", "TP logic analyzer");
5725 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5726 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5727 sysctl_tx_rate, "A", "Tx rate");
5729 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5730 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5731 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5733 if (chip_id(sc) >= CHELSIO_T5) {
5734 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5735 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5736 sysctl_wcwr_stats, "A", "write combined work requests");
5740 if (is_offload(sc)) {
5747 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5748 NULL, "TOE parameters");
5749 children = SYSCTL_CHILDREN(oid);
5751 sc->tt.cong_algorithm = -1;
5752 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
5753 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
5754 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
5757 sc->tt.sndbuf = 256 * 1024;
5758 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5759 &sc->tt.sndbuf, 0, "max hardware send buffer size");
5762 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5763 &sc->tt.ddp, 0, "DDP allowed");
5765 sc->tt.rx_coalesce = 1;
5766 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5767 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
5771 &sc->tt.tls, 0, "Inline TLS allowed");
5773 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
5774 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
5775 "I", "TCP ports that use inline TLS+TOE RX");
5777 sc->tt.tx_align = 1;
5778 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
5779 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
5781 sc->tt.tx_zcopy = 0;
5782 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
5783 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
5784 "Enable zero-copy aio_write(2)");
5786 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
5787 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5788 "cop_managed_offloading", CTLFLAG_RW,
5789 &sc->tt.cop_managed_offloading, 0,
5790 "COP (Connection Offload Policy) controls all TOE offload");
5792 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
5793 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
5794 "TP timer tick (us)");
5796 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
5797 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
5798 "TCP timestamp tick (us)");
5800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5801 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5804 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5805 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5806 "IU", "DACK timer (us)");
5808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5809 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5810 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
5812 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5813 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5814 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
5816 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5817 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5818 sysctl_tp_timer, "LU", "Persist timer min (us)");
5820 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5821 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5822 sysctl_tp_timer, "LU", "Persist timer max (us)");
5824 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5825 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5826 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
5828 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
5829 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5830 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
5832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5833 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5834 sysctl_tp_timer, "LU", "Initial SRTT (us)");
5836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5837 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5838 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
5841 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
5842 sysctl_tp_shift_cnt, "IU",
5843 "Number of SYN retransmissions before abort");
5845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
5846 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
5847 sysctl_tp_shift_cnt, "IU",
5848 "Number of retransmissions before abort");
5850 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
5851 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
5852 sysctl_tp_shift_cnt, "IU",
5853 "Number of keepalive probes before abort");
5855 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
5856 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
5857 children = SYSCTL_CHILDREN(oid);
5858 for (i = 0; i < 16; i++) {
5859 snprintf(s, sizeof(s), "%u", i);
5860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
5861 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
5862 "IU", "TOE retransmit backoff");
5869 vi_sysctls(struct vi_info *vi)
5871 struct sysctl_ctx_list *ctx;
5872 struct sysctl_oid *oid;
5873 struct sysctl_oid_list *children;
5875 ctx = device_get_sysctl_ctx(vi->dev);
5878 * dev.v?(cxgbe|cxl).X.
5880 oid = device_get_sysctl_tree(vi->dev);
5881 children = SYSCTL_CHILDREN(oid);
5883 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5884 vi->viid, "VI identifer");
5885 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5886 &vi->nrxq, 0, "# of rx queues");
5887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5888 &vi->ntxq, 0, "# of tx queues");
5889 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5890 &vi->first_rxq, 0, "index of first rx queue");
5891 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5892 &vi->first_txq, 0, "index of first tx queue");
5893 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5894 vi->rss_size, "size of RSS indirection table");
5896 if (IS_MAIN_VI(vi)) {
5897 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5898 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5899 "Reserve queue 0 for non-flowid packets");
5903 if (vi->nofldrxq != 0) {
5904 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5906 "# of rx queues for offloaded TCP connections");
5907 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5909 "# of tx queues for offloaded TCP connections");
5910 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5911 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5912 "index of first TOE rx queue");
5913 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5914 CTLFLAG_RD, &vi->first_ofld_txq, 0,
5915 "index of first TOE tx queue");
5916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
5917 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5918 sysctl_holdoff_tmr_idx_ofld, "I",
5919 "holdoff timer index for TOE queues");
5920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
5921 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5922 sysctl_holdoff_pktc_idx_ofld, "I",
5923 "holdoff packet counter index for TOE queues");
5927 if (vi->nnmrxq != 0) {
5928 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5929 &vi->nnmrxq, 0, "# of netmap rx queues");
5930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5931 &vi->nnmtxq, 0, "# of netmap tx queues");
5932 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5933 CTLFLAG_RD, &vi->first_nm_rxq, 0,
5934 "index of first netmap rx queue");
5935 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5936 CTLFLAG_RD, &vi->first_nm_txq, 0,
5937 "index of first netmap tx queue");
5941 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5942 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5943 "holdoff timer index");
5944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5945 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5946 "holdoff packet counter index");
5948 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5949 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5952 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5957 cxgbe_sysctls(struct port_info *pi)
5959 struct sysctl_ctx_list *ctx;
5960 struct sysctl_oid *oid;
5961 struct sysctl_oid_list *children, *children2;
5962 struct adapter *sc = pi->adapter;
5965 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
5967 ctx = device_get_sysctl_ctx(pi->dev);
5972 oid = device_get_sysctl_tree(pi->dev);
5973 children = SYSCTL_CHILDREN(oid);
5975 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5976 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5977 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5978 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5979 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5980 "PHY temperature (in Celsius)");
5981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5982 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5983 "PHY firmware version");
5986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5987 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
5988 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
5990 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
5991 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
5992 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
5993 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
5994 "autonegotiation (-1 = not supported)");
5996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5997 port_top_speed(pi), "max speed (in Gbps)");
5998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
5999 pi->mps_bg_map, "MPS buffer group map");
6000 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6001 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6003 if (sc->flags & IS_VF)
6007 * dev.(cxgbe|cxl).X.tc.
6009 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6010 "Tx scheduler traffic classes (cl_rl)");
6011 children2 = SYSCTL_CHILDREN(oid);
6012 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6013 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6014 "pktsize for per-flow cl-rl (0 means up to the driver )");
6015 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6016 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6017 "burstsize for per-flow cl-rl (0 means up to the driver)");
6018 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6019 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6021 snprintf(name, sizeof(name), "%d", i);
6022 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6023 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6025 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6026 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6027 sysctl_bitfield_8b, "A", "flags");
6028 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6029 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6030 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6031 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6032 sysctl_tc_params, "A", "traffic class parameters");
6036 * dev.cxgbe.X.stats.
6038 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6039 NULL, "port statistics");
6040 children = SYSCTL_CHILDREN(oid);
6041 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6042 &pi->tx_parse_error, 0,
6043 "# of tx packets with invalid length or # of segments");
6045 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6046 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6047 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6048 sysctl_handle_t4_reg64, "QU", desc)
6050 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6051 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6052 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6053 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6054 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6055 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6056 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6057 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6058 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6059 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6060 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6061 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6062 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6063 "# of tx frames in this range",
6064 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6065 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6066 "# of tx frames in this range",
6067 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6068 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6069 "# of tx frames in this range",
6070 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6071 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6072 "# of tx frames in this range",
6073 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6074 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6075 "# of tx frames in this range",
6076 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6077 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6078 "# of tx frames in this range",
6079 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6080 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6081 "# of tx frames in this range",
6082 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6083 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6084 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6085 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6086 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6087 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6088 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6089 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6090 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6091 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6092 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6093 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6094 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6095 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6096 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6097 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6098 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6099 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6100 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6101 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6102 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6104 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6105 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6106 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6107 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6108 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6109 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6110 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6111 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6112 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6113 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6114 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6115 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6116 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6117 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6118 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6119 "# of frames received with bad FCS",
6120 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6121 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6122 "# of frames received with length error",
6123 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6124 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6125 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6126 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6127 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6128 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6129 "# of rx frames in this range",
6130 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6131 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6132 "# of rx frames in this range",
6133 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6134 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6135 "# of rx frames in this range",
6136 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6137 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6138 "# of rx frames in this range",
6139 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6140 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6141 "# of rx frames in this range",
6142 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6143 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6144 "# of rx frames in this range",
6145 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6146 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6147 "# of rx frames in this range",
6148 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6149 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6150 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6151 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6152 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6153 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6154 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6155 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6156 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6157 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6158 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6159 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6160 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6161 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6162 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6163 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6164 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6165 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6166 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6168 #undef SYSCTL_ADD_T4_REG64
6170 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6171 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6172 &pi->stats.name, desc)
6174 /* We get these from port_stats and they may be stale by up to 1s */
6175 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6176 "# drops due to buffer-group 0 overflows");
6177 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6178 "# drops due to buffer-group 1 overflows");
6179 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6180 "# drops due to buffer-group 2 overflows");
6181 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6182 "# drops due to buffer-group 3 overflows");
6183 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6184 "# of buffer-group 0 truncated packets");
6185 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6186 "# of buffer-group 1 truncated packets");
6187 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6188 "# of buffer-group 2 truncated packets");
6189 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6190 "# of buffer-group 3 truncated packets");
6192 #undef SYSCTL_ADD_T4_PORTSTAT
6194 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6195 CTLFLAG_RD, &pi->tx_tls_records,
6196 "# of TLS records transmitted");
6197 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6198 CTLFLAG_RD, &pi->tx_tls_octets,
6199 "# of payload octets in transmitted TLS records");
6200 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6201 CTLFLAG_RD, &pi->rx_tls_records,
6202 "# of TLS records received");
6203 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6204 CTLFLAG_RD, &pi->rx_tls_octets,
6205 "# of payload octets in received TLS records");
6209 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6211 int rc, *i, space = 0;
6214 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6215 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6217 sbuf_printf(&sb, " ");
6218 sbuf_printf(&sb, "%d", *i);
6221 rc = sbuf_finish(&sb);
6227 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6232 rc = sysctl_wire_old_buffer(req, 0);
6236 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6240 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6241 rc = sbuf_finish(sb);
6248 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6253 rc = sysctl_wire_old_buffer(req, 0);
6257 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6261 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6262 rc = sbuf_finish(sb);
6269 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6271 struct port_info *pi = arg1;
6273 struct adapter *sc = pi->adapter;
6277 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6280 /* XXX: magic numbers */
6281 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6283 end_synchronized_op(sc, 0);
6289 rc = sysctl_handle_int(oidp, &v, 0, req);
6294 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6296 struct vi_info *vi = arg1;
6299 val = vi->rsrv_noflowq;
6300 rc = sysctl_handle_int(oidp, &val, 0, req);
6301 if (rc != 0 || req->newptr == NULL)
6304 if ((val >= 1) && (vi->ntxq > 1))
6305 vi->rsrv_noflowq = 1;
6307 vi->rsrv_noflowq = 0;
6313 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6315 struct vi_info *vi = arg1;
6316 struct adapter *sc = vi->pi->adapter;
6318 struct sge_rxq *rxq;
6323 rc = sysctl_handle_int(oidp, &idx, 0, req);
6324 if (rc != 0 || req->newptr == NULL)
6327 if (idx < 0 || idx >= SGE_NTIMERS)
6330 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6335 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6336 for_each_rxq(vi, i, rxq) {
6337 #ifdef atomic_store_rel_8
6338 atomic_store_rel_8(&rxq->iq.intr_params, v);
6340 rxq->iq.intr_params = v;
6345 end_synchronized_op(sc, LOCK_HELD);
6350 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6352 struct vi_info *vi = arg1;
6353 struct adapter *sc = vi->pi->adapter;
6358 rc = sysctl_handle_int(oidp, &idx, 0, req);
6359 if (rc != 0 || req->newptr == NULL)
6362 if (idx < -1 || idx >= SGE_NCOUNTERS)
6365 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6370 if (vi->flags & VI_INIT_DONE)
6371 rc = EBUSY; /* cannot be changed once the queues are created */
6375 end_synchronized_op(sc, LOCK_HELD);
6380 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6382 struct vi_info *vi = arg1;
6383 struct adapter *sc = vi->pi->adapter;
6386 qsize = vi->qsize_rxq;
6388 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6389 if (rc != 0 || req->newptr == NULL)
6392 if (qsize < 128 || (qsize & 7))
6395 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6400 if (vi->flags & VI_INIT_DONE)
6401 rc = EBUSY; /* cannot be changed once the queues are created */
6403 vi->qsize_rxq = qsize;
6405 end_synchronized_op(sc, LOCK_HELD);
6410 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6412 struct vi_info *vi = arg1;
6413 struct adapter *sc = vi->pi->adapter;
6416 qsize = vi->qsize_txq;
6418 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6419 if (rc != 0 || req->newptr == NULL)
6422 if (qsize < 128 || qsize > 65536)
6425 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6430 if (vi->flags & VI_INIT_DONE)
6431 rc = EBUSY; /* cannot be changed once the queues are created */
6433 vi->qsize_txq = qsize;
6435 end_synchronized_op(sc, LOCK_HELD);
6440 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6442 struct port_info *pi = arg1;
6443 struct adapter *sc = pi->adapter;
6444 struct link_config *lc = &pi->link_cfg;
6447 if (req->newptr == NULL) {
6449 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
6451 rc = sysctl_wire_old_buffer(req, 0);
6455 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6459 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
6460 rc = sbuf_finish(sb);
6466 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
6469 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6475 if (s[0] < '0' || s[0] > '9')
6476 return (EINVAL); /* not a number */
6478 if (n & ~(PAUSE_TX | PAUSE_RX))
6479 return (EINVAL); /* some other bit is set too */
6481 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6486 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
6487 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
6488 lc->requested_fc |= n;
6489 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6491 lc->fc = lc->requested_fc;
6492 set_current_media(pi, &pi->media);
6496 end_synchronized_op(sc, 0);
6503 sysctl_fec(SYSCTL_HANDLER_ARGS)
6505 struct port_info *pi = arg1;
6506 struct adapter *sc = pi->adapter;
6507 struct link_config *lc = &pi->link_cfg;
6510 if (req->newptr == NULL) {
6512 static char *bits = "\20\1RS\2BASER_RS\3RESERVED";
6514 rc = sysctl_wire_old_buffer(req, 0);
6518 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6522 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits);
6523 rc = sbuf_finish(sb);
6529 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC);
6532 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6538 if (s[0] < '0' || s[0] > '9')
6539 return (EINVAL); /* not a number */
6541 if (n & ~M_FW_PORT_CAP_FEC)
6542 return (EINVAL); /* some other bit is set too */
6544 return (EINVAL); /* one bit can be set at most */
6546 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6551 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) {
6552 lc->requested_fec = n &
6553 G_FW_PORT_CAP_FEC(lc->supported);
6554 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6556 lc->fec = lc->requested_fec;
6560 end_synchronized_op(sc, 0);
6567 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
6569 struct port_info *pi = arg1;
6570 struct adapter *sc = pi->adapter;
6571 struct link_config *lc = &pi->link_cfg;
6574 if (lc->supported & FW_PORT_CAP_ANEG)
6575 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0;
6578 rc = sysctl_handle_int(oidp, &val, 0, req);
6579 if (rc != 0 || req->newptr == NULL)
6582 val = AUTONEG_DISABLE;
6584 val = AUTONEG_ENABLE;
6588 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6593 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) {
6597 if (lc->requested_aneg == val) {
6598 rc = 0; /* no change, do nothing. */
6601 old = lc->requested_aneg;
6602 lc->requested_aneg = val;
6603 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6605 lc->requested_aneg = old;
6607 set_current_media(pi, &pi->media);
6610 end_synchronized_op(sc, 0);
6615 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
6617 struct adapter *sc = arg1;
6621 val = t4_read_reg64(sc, reg);
6623 return (sysctl_handle_64(oidp, &val, 0, req));
6627 sysctl_temperature(SYSCTL_HANDLER_ARGS)
6629 struct adapter *sc = arg1;
6631 uint32_t param, val;
6633 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
6636 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6637 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
6638 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
6639 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6640 end_synchronized_op(sc, 0);
6644 /* unknown is returned as 0 but we display -1 in that case */
6645 t = val == 0 ? -1 : val;
6647 rc = sysctl_handle_int(oidp, &t, 0, req);
6652 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
6654 struct adapter *sc = arg1;
6657 uint32_t param, val;
6659 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
6662 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6663 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
6664 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6665 end_synchronized_op(sc, 0);
6669 rc = sysctl_wire_old_buffer(req, 0);
6673 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6677 if (val == 0xffffffff) {
6678 /* Only debug and custom firmwares report load averages. */
6679 sbuf_printf(sb, "not available");
6681 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
6682 (val >> 16) & 0xff);
6684 rc = sbuf_finish(sb);
6691 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6693 struct adapter *sc = arg1;
6696 uint16_t incr[NMTUS][NCCTRL_WIN];
6697 static const char *dec_fac[] = {
6698 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6702 rc = sysctl_wire_old_buffer(req, 0);
6706 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6710 t4_read_cong_tbl(sc, incr);
6712 for (i = 0; i < NCCTRL_WIN; ++i) {
6713 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6714 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6715 incr[5][i], incr[6][i], incr[7][i]);
6716 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6717 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6718 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6719 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6722 rc = sbuf_finish(sb);
6728 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6729 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
6730 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6731 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
6735 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6737 struct adapter *sc = arg1;
6739 int rc, i, n, qid = arg2;
6742 u_int cim_num_obq = sc->chip_params->cim_num_obq;
6744 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6745 ("%s: bad qid %d\n", __func__, qid));
6747 if (qid < CIM_NUM_IBQ) {
6750 n = 4 * CIM_IBQ_SIZE;
6751 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6752 rc = t4_read_cim_ibq(sc, qid, buf, n);
6754 /* outbound queue */
6757 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
6758 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6759 rc = t4_read_cim_obq(sc, qid, buf, n);
6766 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
6768 rc = sysctl_wire_old_buffer(req, 0);
6772 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6778 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
6779 for (i = 0, p = buf; i < n; i += 16, p += 4)
6780 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
6783 rc = sbuf_finish(sb);
6791 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
6793 struct adapter *sc = arg1;
6799 MPASS(chip_id(sc) <= CHELSIO_T5);
6801 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6805 rc = sysctl_wire_old_buffer(req, 0);
6809 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6813 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6816 rc = -t4_cim_read_la(sc, buf, NULL);
6820 sbuf_printf(sb, "Status Data PC%s",
6821 cfg & F_UPDBGLACAPTPCONLY ? "" :
6822 " LS0Stat LS0Addr LS0Data");
6824 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
6825 if (cfg & F_UPDBGLACAPTPCONLY) {
6826 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
6828 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
6829 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
6830 p[4] & 0xff, p[5] >> 8);
6831 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
6832 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6833 p[1] & 0xf, p[2] >> 4);
6836 "\n %02x %x%07x %x%07x %08x %08x "
6838 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6839 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
6844 rc = sbuf_finish(sb);
6852 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
6854 struct adapter *sc = arg1;
6860 MPASS(chip_id(sc) > CHELSIO_T5);
6862 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6866 rc = sysctl_wire_old_buffer(req, 0);
6870 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6874 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6877 rc = -t4_cim_read_la(sc, buf, NULL);
6881 sbuf_printf(sb, "Status Inst Data PC%s",
6882 cfg & F_UPDBGLACAPTPCONLY ? "" :
6883 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
6885 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
6886 if (cfg & F_UPDBGLACAPTPCONLY) {
6887 sbuf_printf(sb, "\n %02x %08x %08x %08x",
6888 p[3] & 0xff, p[2], p[1], p[0]);
6889 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
6890 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
6891 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
6892 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
6893 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
6894 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
6897 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
6898 "%08x %08x %08x %08x %08x %08x",
6899 (p[9] >> 16) & 0xff,
6900 p[9] & 0xffff, p[8] >> 16,
6901 p[8] & 0xffff, p[7] >> 16,
6902 p[7] & 0xffff, p[6] >> 16,
6903 p[2], p[1], p[0], p[5], p[4], p[3]);
6907 rc = sbuf_finish(sb);
6915 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
6917 struct adapter *sc = arg1;
6923 rc = sysctl_wire_old_buffer(req, 0);
6927 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6931 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6934 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6937 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6938 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6942 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
6943 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6944 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
6945 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6946 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6947 (p[1] >> 2) | ((p[2] & 3) << 30),
6948 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
6952 rc = sbuf_finish(sb);
6959 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
6961 struct adapter *sc = arg1;
6967 rc = sysctl_wire_old_buffer(req, 0);
6971 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6975 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
6978 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
6981 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
6982 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6983 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
6984 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
6985 p[4], p[3], p[2], p[1], p[0]);
6988 sbuf_printf(sb, "\n\nCntl ID Data");
6989 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6990 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
6991 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
6994 rc = sbuf_finish(sb);
7001 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7003 struct adapter *sc = arg1;
7006 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7007 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7008 uint16_t thres[CIM_NUM_IBQ];
7009 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7010 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7011 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7013 cim_num_obq = sc->chip_params->cim_num_obq;
7015 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7016 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7018 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7019 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7021 nq = CIM_NUM_IBQ + cim_num_obq;
7023 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7025 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7029 t4_read_cimq_cfg(sc, base, size, thres);
7031 rc = sysctl_wire_old_buffer(req, 0);
7035 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7040 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7042 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7043 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7044 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7045 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7046 G_QUEREMFLITS(p[2]) * 16);
7047 for ( ; i < nq; i++, p += 4, wr += 2)
7048 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7049 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7050 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7051 G_QUEREMFLITS(p[2]) * 16);
7053 rc = sbuf_finish(sb);
7060 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7062 struct adapter *sc = arg1;
7065 struct tp_cpl_stats stats;
7067 rc = sysctl_wire_old_buffer(req, 0);
7071 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7075 mtx_lock(&sc->reg_lock);
7076 t4_tp_get_cpl_stats(sc, &stats, 0);
7077 mtx_unlock(&sc->reg_lock);
7079 if (sc->chip_params->nchan > 2) {
7080 sbuf_printf(sb, " channel 0 channel 1"
7081 " channel 2 channel 3");
7082 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7083 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7084 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7085 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7087 sbuf_printf(sb, " channel 0 channel 1");
7088 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7089 stats.req[0], stats.req[1]);
7090 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7091 stats.rsp[0], stats.rsp[1]);
7094 rc = sbuf_finish(sb);
7101 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7103 struct adapter *sc = arg1;
7106 struct tp_usm_stats stats;
7108 rc = sysctl_wire_old_buffer(req, 0);
7112 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7116 t4_get_usm_stats(sc, &stats, 1);
7118 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7119 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7120 sbuf_printf(sb, "Drops: %u", stats.drops);
7122 rc = sbuf_finish(sb);
7128 static const char * const devlog_level_strings[] = {
7129 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7130 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7131 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7132 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7133 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7134 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7137 static const char * const devlog_facility_strings[] = {
7138 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7139 [FW_DEVLOG_FACILITY_CF] = "CF",
7140 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7141 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7142 [FW_DEVLOG_FACILITY_RES] = "RES",
7143 [FW_DEVLOG_FACILITY_HW] = "HW",
7144 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7145 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7146 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7147 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7148 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7149 [FW_DEVLOG_FACILITY_VI] = "VI",
7150 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7151 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7152 [FW_DEVLOG_FACILITY_TM] = "TM",
7153 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7154 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7155 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7156 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7157 [FW_DEVLOG_FACILITY_RI] = "RI",
7158 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7159 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7160 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7161 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7162 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7166 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7168 struct adapter *sc = arg1;
7169 struct devlog_params *dparams = &sc->params.devlog;
7170 struct fw_devlog_e *buf, *e;
7171 int i, j, rc, nentries, first = 0;
7173 uint64_t ftstamp = UINT64_MAX;
7175 if (dparams->addr == 0)
7178 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
7182 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7186 nentries = dparams->size / sizeof(struct fw_devlog_e);
7187 for (i = 0; i < nentries; i++) {
7190 if (e->timestamp == 0)
7193 e->timestamp = be64toh(e->timestamp);
7194 e->seqno = be32toh(e->seqno);
7195 for (j = 0; j < 8; j++)
7196 e->params[j] = be32toh(e->params[j]);
7198 if (e->timestamp < ftstamp) {
7199 ftstamp = e->timestamp;
7204 if (buf[first].timestamp == 0)
7205 goto done; /* nothing in the log */
7207 rc = sysctl_wire_old_buffer(req, 0);
7211 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7216 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7217 "Seq#", "Tstamp", "Level", "Facility", "Message");
7222 if (e->timestamp == 0)
7225 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7226 e->seqno, e->timestamp,
7227 (e->level < nitems(devlog_level_strings) ?
7228 devlog_level_strings[e->level] : "UNKNOWN"),
7229 (e->facility < nitems(devlog_facility_strings) ?
7230 devlog_facility_strings[e->facility] : "UNKNOWN"));
7231 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7232 e->params[2], e->params[3], e->params[4],
7233 e->params[5], e->params[6], e->params[7]);
7235 if (++i == nentries)
7237 } while (i != first);
7239 rc = sbuf_finish(sb);
7247 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7249 struct adapter *sc = arg1;
7252 struct tp_fcoe_stats stats[MAX_NCHAN];
7253 int i, nchan = sc->chip_params->nchan;
7255 rc = sysctl_wire_old_buffer(req, 0);
7259 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7263 for (i = 0; i < nchan; i++)
7264 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7267 sbuf_printf(sb, " channel 0 channel 1"
7268 " channel 2 channel 3");
7269 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7270 stats[0].octets_ddp, stats[1].octets_ddp,
7271 stats[2].octets_ddp, stats[3].octets_ddp);
7272 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7273 stats[0].frames_ddp, stats[1].frames_ddp,
7274 stats[2].frames_ddp, stats[3].frames_ddp);
7275 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7276 stats[0].frames_drop, stats[1].frames_drop,
7277 stats[2].frames_drop, stats[3].frames_drop);
7279 sbuf_printf(sb, " channel 0 channel 1");
7280 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7281 stats[0].octets_ddp, stats[1].octets_ddp);
7282 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7283 stats[0].frames_ddp, stats[1].frames_ddp);
7284 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7285 stats[0].frames_drop, stats[1].frames_drop);
7288 rc = sbuf_finish(sb);
7295 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7297 struct adapter *sc = arg1;
7300 unsigned int map, kbps, ipg, mode;
7301 unsigned int pace_tab[NTX_SCHED];
7303 rc = sysctl_wire_old_buffer(req, 0);
7307 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7311 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7312 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7313 t4_read_pace_tbl(sc, pace_tab);
7315 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
7316 "Class IPG (0.1 ns) Flow IPG (us)");
7318 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7319 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7320 sbuf_printf(sb, "\n %u %-5s %u ", i,
7321 (mode & (1 << i)) ? "flow" : "class", map & 3);
7323 sbuf_printf(sb, "%9u ", kbps);
7325 sbuf_printf(sb, " disabled ");
7328 sbuf_printf(sb, "%13u ", ipg);
7330 sbuf_printf(sb, " disabled ");
7333 sbuf_printf(sb, "%10u", pace_tab[i]);
7335 sbuf_printf(sb, " disabled");
7338 rc = sbuf_finish(sb);
7345 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7347 struct adapter *sc = arg1;
7351 struct lb_port_stats s[2];
7352 static const char *stat_name[] = {
7353 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7354 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7355 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7356 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7357 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7358 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7359 "BG2FramesTrunc:", "BG3FramesTrunc:"
7362 rc = sysctl_wire_old_buffer(req, 0);
7366 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7370 memset(s, 0, sizeof(s));
7372 for (i = 0; i < sc->chip_params->nchan; i += 2) {
7373 t4_get_lb_stats(sc, i, &s[0]);
7374 t4_get_lb_stats(sc, i + 1, &s[1]);
7378 sbuf_printf(sb, "%s Loopback %u"
7379 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7381 for (j = 0; j < nitems(stat_name); j++)
7382 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7386 rc = sbuf_finish(sb);
7393 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7396 struct port_info *pi = arg1;
7397 struct link_config *lc = &pi->link_cfg;
7400 rc = sysctl_wire_old_buffer(req, 0);
7403 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7407 if (lc->link_ok || lc->link_down_rc == 255)
7408 sbuf_printf(sb, "n/a");
7410 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7412 rc = sbuf_finish(sb);
7425 mem_desc_cmp(const void *a, const void *b)
7427 return ((const struct mem_desc *)a)->base -
7428 ((const struct mem_desc *)b)->base;
7432 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7440 size = to - from + 1;
7444 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7445 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7449 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7451 struct adapter *sc = arg1;
7454 uint32_t lo, hi, used, alloc;
7455 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7456 static const char *region[] = {
7457 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7458 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7459 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7460 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7461 "RQUDP region:", "PBL region:", "TXPBL region:",
7462 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7463 "On-chip queues:", "TLS keys:",
7465 struct mem_desc avail[4];
7466 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
7467 struct mem_desc *md = mem;
7469 rc = sysctl_wire_old_buffer(req, 0);
7473 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7477 for (i = 0; i < nitems(mem); i++) {
7482 /* Find and sort the populated memory ranges */
7484 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7485 if (lo & F_EDRAM0_ENABLE) {
7486 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7487 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7488 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7492 if (lo & F_EDRAM1_ENABLE) {
7493 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7494 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7495 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7499 if (lo & F_EXT_MEM_ENABLE) {
7500 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7501 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7502 avail[i].limit = avail[i].base +
7503 (G_EXT_MEM_SIZE(hi) << 20);
7504 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
7507 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7508 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7509 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7510 avail[i].limit = avail[i].base +
7511 (G_EXT_MEM1_SIZE(hi) << 20);
7515 if (!i) /* no memory available */
7517 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
7519 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
7520 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
7521 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
7522 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7523 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
7524 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
7525 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
7526 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
7527 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
7529 /* the next few have explicit upper bounds */
7530 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
7531 md->limit = md->base - 1 +
7532 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
7533 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
7536 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
7537 md->limit = md->base - 1 +
7538 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
7539 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
7542 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7543 if (chip_id(sc) <= CHELSIO_T5)
7544 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
7546 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
7550 md->idx = nitems(region); /* hide it */
7554 #define ulp_region(reg) \
7555 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
7556 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
7558 ulp_region(RX_ISCSI);
7559 ulp_region(RX_TDDP);
7561 ulp_region(RX_STAG);
7563 ulp_region(RX_RQUDP);
7569 md->idx = nitems(region);
7572 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
7573 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
7576 if (sge_ctrl & F_VFIFO_ENABLE)
7577 size = G_DBVFIFO_SIZE(fifo_size);
7579 size = G_T6_DBVFIFO_SIZE(fifo_size);
7582 md->base = G_BASEADDR(t4_read_reg(sc,
7583 A_SGE_DBVFIFO_BADDR));
7584 md->limit = md->base + (size << 2) - 1;
7589 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
7592 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
7596 md->base = sc->vres.ocq.start;
7597 if (sc->vres.ocq.size)
7598 md->limit = md->base + sc->vres.ocq.size - 1;
7600 md->idx = nitems(region); /* hide it */
7603 md->base = sc->vres.key.start;
7604 if (sc->vres.key.size)
7605 md->limit = md->base + sc->vres.key.size - 1;
7607 md->idx = nitems(region); /* hide it */
7610 /* add any address-space holes, there can be up to 3 */
7611 for (n = 0; n < i - 1; n++)
7612 if (avail[n].limit < avail[n + 1].base)
7613 (md++)->base = avail[n].limit;
7615 (md++)->base = avail[n].limit;
7618 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
7620 for (lo = 0; lo < i; lo++)
7621 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
7622 avail[lo].limit - 1);
7624 sbuf_printf(sb, "\n");
7625 for (i = 0; i < n; i++) {
7626 if (mem[i].idx >= nitems(region))
7627 continue; /* skip holes */
7629 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
7630 mem_region_show(sb, region[mem[i].idx], mem[i].base,
7634 sbuf_printf(sb, "\n");
7635 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
7636 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
7637 mem_region_show(sb, "uP RAM:", lo, hi);
7639 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
7640 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
7641 mem_region_show(sb, "uP Extmem2:", lo, hi);
7643 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
7644 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
7646 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
7647 (lo & F_PMRXNUMCHN) ? 2 : 1);
7649 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
7650 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
7651 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
7653 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
7654 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
7655 sbuf_printf(sb, "%u p-structs\n",
7656 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
7658 for (i = 0; i < 4; i++) {
7659 if (chip_id(sc) > CHELSIO_T5)
7660 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
7662 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
7664 used = G_T5_USED(lo);
7665 alloc = G_T5_ALLOC(lo);
7668 alloc = G_ALLOC(lo);
7670 /* For T6 these are MAC buffer groups */
7671 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
7674 for (i = 0; i < sc->chip_params->nchan; i++) {
7675 if (chip_id(sc) > CHELSIO_T5)
7676 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
7678 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
7680 used = G_T5_USED(lo);
7681 alloc = G_T5_ALLOC(lo);
7684 alloc = G_ALLOC(lo);
7686 /* For T6 these are MAC buffer groups */
7688 "\nLoopback %d using %u pages out of %u allocated",
7692 rc = sbuf_finish(sb);
7699 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7703 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7707 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7709 struct adapter *sc = arg1;
7713 MPASS(chip_id(sc) <= CHELSIO_T5);
7715 rc = sysctl_wire_old_buffer(req, 0);
7719 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7724 "Idx Ethernet address Mask Vld Ports PF"
7725 " VF Replication P0 P1 P2 P3 ML");
7726 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7727 uint64_t tcamx, tcamy, mask;
7728 uint32_t cls_lo, cls_hi;
7729 uint8_t addr[ETHER_ADDR_LEN];
7731 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7732 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7735 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7736 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7737 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7738 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7739 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
7740 addr[3], addr[4], addr[5], (uintmax_t)mask,
7741 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7742 G_PORTMAP(cls_hi), G_PF(cls_lo),
7743 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7745 if (cls_lo & F_REPLICATE) {
7746 struct fw_ldst_cmd ldst_cmd;
7748 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7749 ldst_cmd.op_to_addrspace =
7750 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7751 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7752 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7753 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7754 ldst_cmd.u.mps.rplc.fid_idx =
7755 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7756 V_FW_LDST_CMD_IDX(i));
7758 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7762 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7763 sizeof(ldst_cmd), &ldst_cmd);
7764 end_synchronized_op(sc, 0);
7767 sbuf_printf(sb, "%36d", rc);
7770 sbuf_printf(sb, " %08x %08x %08x %08x",
7771 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7772 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7773 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7774 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7777 sbuf_printf(sb, "%36s", "");
7779 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
7780 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
7781 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
7785 (void) sbuf_finish(sb);
7787 rc = sbuf_finish(sb);
7794 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
7796 struct adapter *sc = arg1;
7800 MPASS(chip_id(sc) > CHELSIO_T5);
7802 rc = sysctl_wire_old_buffer(req, 0);
7806 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7810 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
7811 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
7813 " P0 P1 P2 P3 ML\n");
7815 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7816 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
7818 uint64_t tcamx, tcamy, val, mask;
7819 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
7820 uint8_t addr[ETHER_ADDR_LEN];
7822 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
7824 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
7826 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
7827 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7828 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7829 tcamy = G_DMACH(val) << 32;
7830 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7831 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7832 lookup_type = G_DATALKPTYPE(data2);
7833 port_num = G_DATAPORTNUM(data2);
7834 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7835 /* Inner header VNI */
7836 vniy = ((data2 & F_DATAVIDH2) << 23) |
7837 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7838 dip_hit = data2 & F_DATADIPHIT;
7843 vlan_vld = data2 & F_DATAVIDH2;
7844 ivlan = G_VIDL(val);
7847 ctl |= V_CTLXYBITSEL(1);
7848 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7849 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7850 tcamx = G_DMACH(val) << 32;
7851 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7852 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7853 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7854 /* Inner header VNI mask */
7855 vnix = ((data2 & F_DATAVIDH2) << 23) |
7856 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7862 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7864 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7865 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7867 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7868 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7869 "%012jx %06x %06x - - %3c"
7870 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
7871 addr[1], addr[2], addr[3], addr[4], addr[5],
7872 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
7873 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7874 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7875 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7877 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7878 "%012jx - - ", i, addr[0], addr[1],
7879 addr[2], addr[3], addr[4], addr[5],
7883 sbuf_printf(sb, "%4u Y ", ivlan);
7885 sbuf_printf(sb, " - N ");
7887 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
7888 lookup_type ? 'I' : 'O', port_num,
7889 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7890 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7891 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7895 if (cls_lo & F_T6_REPLICATE) {
7896 struct fw_ldst_cmd ldst_cmd;
7898 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7899 ldst_cmd.op_to_addrspace =
7900 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7901 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7902 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7903 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7904 ldst_cmd.u.mps.rplc.fid_idx =
7905 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7906 V_FW_LDST_CMD_IDX(i));
7908 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7912 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7913 sizeof(ldst_cmd), &ldst_cmd);
7914 end_synchronized_op(sc, 0);
7917 sbuf_printf(sb, "%72d", rc);
7920 sbuf_printf(sb, " %08x %08x %08x %08x"
7921 " %08x %08x %08x %08x",
7922 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
7923 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
7924 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
7925 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
7926 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7927 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7928 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7929 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7932 sbuf_printf(sb, "%72s", "");
7934 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
7935 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
7936 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7937 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7941 (void) sbuf_finish(sb);
7943 rc = sbuf_finish(sb);
7950 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
7952 struct adapter *sc = arg1;
7955 uint16_t mtus[NMTUS];
7957 rc = sysctl_wire_old_buffer(req, 0);
7961 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7965 t4_read_mtu_tbl(sc, mtus, NULL);
7967 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
7968 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
7969 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
7970 mtus[14], mtus[15]);
7972 rc = sbuf_finish(sb);
7979 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
7981 struct adapter *sc = arg1;
7984 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
7985 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
7986 static const char *tx_stats[MAX_PM_NSTATS] = {
7987 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
7988 "Tx FIFO wait", NULL, "Tx latency"
7990 static const char *rx_stats[MAX_PM_NSTATS] = {
7991 "Read:", "Write bypass:", "Write mem:", "Flush:",
7992 "Rx FIFO wait", NULL, "Rx latency"
7995 rc = sysctl_wire_old_buffer(req, 0);
7999 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8003 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8004 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8006 sbuf_printf(sb, " Tx pcmds Tx bytes");
8007 for (i = 0; i < 4; i++) {
8008 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8012 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8013 for (i = 0; i < 4; i++) {
8014 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8018 if (chip_id(sc) > CHELSIO_T5) {
8020 "\n Total wait Total occupancy");
8021 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8023 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8027 MPASS(i < nitems(tx_stats));
8030 "\n Reads Total wait");
8031 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8033 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8037 rc = sbuf_finish(sb);
8044 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8046 struct adapter *sc = arg1;
8049 struct tp_rdma_stats stats;
8051 rc = sysctl_wire_old_buffer(req, 0);
8055 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8059 mtx_lock(&sc->reg_lock);
8060 t4_tp_get_rdma_stats(sc, &stats, 0);
8061 mtx_unlock(&sc->reg_lock);
8063 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8064 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8066 rc = sbuf_finish(sb);
8073 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8075 struct adapter *sc = arg1;
8078 struct tp_tcp_stats v4, v6;
8080 rc = sysctl_wire_old_buffer(req, 0);
8084 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8088 mtx_lock(&sc->reg_lock);
8089 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8090 mtx_unlock(&sc->reg_lock);
8094 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8095 v4.tcp_out_rsts, v6.tcp_out_rsts);
8096 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8097 v4.tcp_in_segs, v6.tcp_in_segs);
8098 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8099 v4.tcp_out_segs, v6.tcp_out_segs);
8100 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8101 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8103 rc = sbuf_finish(sb);
8110 sysctl_tids(SYSCTL_HANDLER_ARGS)
8112 struct adapter *sc = arg1;
8115 struct tid_info *t = &sc->tids;
8117 rc = sysctl_wire_old_buffer(req, 0);
8121 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8126 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8131 sbuf_printf(sb, "TID range: ");
8132 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8135 if (chip_id(sc) <= CHELSIO_T5) {
8136 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8137 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8139 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8140 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8144 sbuf_printf(sb, "0-%u, ", b - 1);
8145 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8147 sbuf_printf(sb, "0-%u", t->ntids - 1);
8148 sbuf_printf(sb, ", in use: %u\n",
8149 atomic_load_acq_int(&t->tids_in_use));
8153 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8154 t->stid_base + t->nstids - 1, t->stids_in_use);
8158 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
8159 t->ftid_base + t->nftids - 1);
8163 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8164 t->etid_base + t->netids - 1, t->etids_in_use);
8167 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8168 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8169 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8171 rc = sbuf_finish(sb);
8178 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8180 struct adapter *sc = arg1;
8183 struct tp_err_stats stats;
8185 rc = sysctl_wire_old_buffer(req, 0);
8189 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8193 mtx_lock(&sc->reg_lock);
8194 t4_tp_get_err_stats(sc, &stats, 0);
8195 mtx_unlock(&sc->reg_lock);
8197 if (sc->chip_params->nchan > 2) {
8198 sbuf_printf(sb, " channel 0 channel 1"
8199 " channel 2 channel 3\n");
8200 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8201 stats.mac_in_errs[0], stats.mac_in_errs[1],
8202 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8203 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8204 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8205 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8206 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8207 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8208 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8209 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8210 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8211 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8212 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8213 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8214 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8215 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8216 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8217 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8218 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8219 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8220 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8221 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8222 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8223 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8225 sbuf_printf(sb, " channel 0 channel 1\n");
8226 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8227 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8228 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8229 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8230 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8231 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8232 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8233 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8234 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8235 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8236 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8237 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8238 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8239 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8240 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8241 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8244 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8245 stats.ofld_no_neigh, stats.ofld_cong_defer);
8247 rc = sbuf_finish(sb);
8254 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8256 struct adapter *sc = arg1;
8257 struct tp_params *tpp = &sc->params.tp;
8261 mask = tpp->la_mask >> 16;
8262 rc = sysctl_handle_int(oidp, &mask, 0, req);
8263 if (rc != 0 || req->newptr == NULL)
8267 tpp->la_mask = mask << 16;
8268 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8280 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8286 uint64_t mask = (1ULL << f->width) - 1;
8287 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8288 ((uintmax_t)v >> f->start) & mask);
8290 if (line_size + len >= 79) {
8292 sbuf_printf(sb, "\n ");
8294 sbuf_printf(sb, "%s ", buf);
8295 line_size += len + 1;
8298 sbuf_printf(sb, "\n");
8301 static const struct field_desc tp_la0[] = {
8302 { "RcfOpCodeOut", 60, 4 },
8304 { "WcfState", 52, 4 },
8305 { "RcfOpcSrcOut", 50, 2 },
8306 { "CRxError", 49, 1 },
8307 { "ERxError", 48, 1 },
8308 { "SanityFailed", 47, 1 },
8309 { "SpuriousMsg", 46, 1 },
8310 { "FlushInputMsg", 45, 1 },
8311 { "FlushInputCpl", 44, 1 },
8312 { "RssUpBit", 43, 1 },
8313 { "RssFilterHit", 42, 1 },
8315 { "InitTcb", 31, 1 },
8316 { "LineNumber", 24, 7 },
8318 { "EdataOut", 22, 1 },
8320 { "CdataOut", 20, 1 },
8321 { "EreadPdu", 19, 1 },
8322 { "CreadPdu", 18, 1 },
8323 { "TunnelPkt", 17, 1 },
8324 { "RcfPeerFin", 16, 1 },
8325 { "RcfReasonOut", 12, 4 },
8326 { "TxCchannel", 10, 2 },
8327 { "RcfTxChannel", 8, 2 },
8328 { "RxEchannel", 6, 2 },
8329 { "RcfRxChannel", 5, 1 },
8330 { "RcfDataOutSrdy", 4, 1 },
8332 { "RxOoDvld", 2, 1 },
8333 { "RxCongestion", 1, 1 },
8334 { "TxCongestion", 0, 1 },
8338 static const struct field_desc tp_la1[] = {
8339 { "CplCmdIn", 56, 8 },
8340 { "CplCmdOut", 48, 8 },
8341 { "ESynOut", 47, 1 },
8342 { "EAckOut", 46, 1 },
8343 { "EFinOut", 45, 1 },
8344 { "ERstOut", 44, 1 },
8349 { "DataIn", 39, 1 },
8350 { "DataInVld", 38, 1 },
8352 { "RxBufEmpty", 36, 1 },
8354 { "RxFbCongestion", 34, 1 },
8355 { "TxFbCongestion", 33, 1 },
8356 { "TxPktSumSrdy", 32, 1 },
8357 { "RcfUlpType", 28, 4 },
8359 { "Ebypass", 26, 1 },
8361 { "Static0", 24, 1 },
8363 { "Cbypass", 22, 1 },
8365 { "CPktOut", 20, 1 },
8366 { "RxPagePoolFull", 18, 2 },
8367 { "RxLpbkPkt", 17, 1 },
8368 { "TxLpbkPkt", 16, 1 },
8369 { "RxVfValid", 15, 1 },
8370 { "SynLearned", 14, 1 },
8371 { "SetDelEntry", 13, 1 },
8372 { "SetInvEntry", 12, 1 },
8373 { "CpcmdDvld", 11, 1 },
8374 { "CpcmdSave", 10, 1 },
8375 { "RxPstructsFull", 8, 2 },
8376 { "EpcmdDvld", 7, 1 },
8377 { "EpcmdFlush", 6, 1 },
8378 { "EpcmdTrimPrefix", 5, 1 },
8379 { "EpcmdTrimPostfix", 4, 1 },
8380 { "ERssIp4Pkt", 3, 1 },
8381 { "ERssIp6Pkt", 2, 1 },
8382 { "ERssTcpUdpPkt", 1, 1 },
8383 { "ERssFceFipPkt", 0, 1 },
8387 static const struct field_desc tp_la2[] = {
8388 { "CplCmdIn", 56, 8 },
8389 { "MpsVfVld", 55, 1 },
8396 { "DataIn", 39, 1 },
8397 { "DataInVld", 38, 1 },
8399 { "RxBufEmpty", 36, 1 },
8401 { "RxFbCongestion", 34, 1 },
8402 { "TxFbCongestion", 33, 1 },
8403 { "TxPktSumSrdy", 32, 1 },
8404 { "RcfUlpType", 28, 4 },
8406 { "Ebypass", 26, 1 },
8408 { "Static0", 24, 1 },
8410 { "Cbypass", 22, 1 },
8412 { "CPktOut", 20, 1 },
8413 { "RxPagePoolFull", 18, 2 },
8414 { "RxLpbkPkt", 17, 1 },
8415 { "TxLpbkPkt", 16, 1 },
8416 { "RxVfValid", 15, 1 },
8417 { "SynLearned", 14, 1 },
8418 { "SetDelEntry", 13, 1 },
8419 { "SetInvEntry", 12, 1 },
8420 { "CpcmdDvld", 11, 1 },
8421 { "CpcmdSave", 10, 1 },
8422 { "RxPstructsFull", 8, 2 },
8423 { "EpcmdDvld", 7, 1 },
8424 { "EpcmdFlush", 6, 1 },
8425 { "EpcmdTrimPrefix", 5, 1 },
8426 { "EpcmdTrimPostfix", 4, 1 },
8427 { "ERssIp4Pkt", 3, 1 },
8428 { "ERssIp6Pkt", 2, 1 },
8429 { "ERssTcpUdpPkt", 1, 1 },
8430 { "ERssFceFipPkt", 0, 1 },
8435 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8438 field_desc_show(sb, *p, tp_la0);
8442 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8446 sbuf_printf(sb, "\n");
8447 field_desc_show(sb, p[0], tp_la0);
8448 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8449 field_desc_show(sb, p[1], tp_la0);
8453 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8457 sbuf_printf(sb, "\n");
8458 field_desc_show(sb, p[0], tp_la0);
8459 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8460 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8464 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8466 struct adapter *sc = arg1;
8471 void (*show_func)(struct sbuf *, uint64_t *, int);
8473 rc = sysctl_wire_old_buffer(req, 0);
8477 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8481 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8483 t4_tp_read_la(sc, buf, NULL);
8486 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8489 show_func = tp_la_show2;
8493 show_func = tp_la_show3;
8497 show_func = tp_la_show;
8500 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8501 (*show_func)(sb, p, i);
8503 rc = sbuf_finish(sb);
8510 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
8512 struct adapter *sc = arg1;
8515 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
8517 rc = sysctl_wire_old_buffer(req, 0);
8521 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8525 t4_get_chan_txrate(sc, nrate, orate);
8527 if (sc->chip_params->nchan > 2) {
8528 sbuf_printf(sb, " channel 0 channel 1"
8529 " channel 2 channel 3\n");
8530 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
8531 nrate[0], nrate[1], nrate[2], nrate[3]);
8532 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
8533 orate[0], orate[1], orate[2], orate[3]);
8535 sbuf_printf(sb, " channel 0 channel 1\n");
8536 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
8537 nrate[0], nrate[1]);
8538 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
8539 orate[0], orate[1]);
8542 rc = sbuf_finish(sb);
8549 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
8551 struct adapter *sc = arg1;
8556 rc = sysctl_wire_old_buffer(req, 0);
8560 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8564 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
8567 t4_ulprx_read_la(sc, buf);
8570 sbuf_printf(sb, " Pcmd Type Message"
8572 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
8573 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
8574 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
8577 rc = sbuf_finish(sb);
8584 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
8586 struct adapter *sc = arg1;
8590 MPASS(chip_id(sc) >= CHELSIO_T5);
8592 rc = sysctl_wire_old_buffer(req, 0);
8596 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8600 v = t4_read_reg(sc, A_SGE_STAT_CFG);
8601 if (G_STATSOURCE_T5(v) == 7) {
8604 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
8606 sbuf_printf(sb, "total %d, incomplete %d",
8607 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8608 t4_read_reg(sc, A_SGE_STAT_MATCH));
8609 } else if (mode == 1) {
8610 sbuf_printf(sb, "total %d, data overflow %d",
8611 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8612 t4_read_reg(sc, A_SGE_STAT_MATCH));
8614 sbuf_printf(sb, "unknown mode %d", mode);
8617 rc = sbuf_finish(sb);
8624 sysctl_cpus(SYSCTL_HANDLER_ARGS)
8626 struct adapter *sc = arg1;
8627 enum cpu_sets op = arg2;
8632 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
8635 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
8639 rc = sysctl_wire_old_buffer(req, 0);
8643 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8648 sbuf_printf(sb, "%d ", i);
8649 rc = sbuf_finish(sb);
8657 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
8659 struct adapter *sc = arg1;
8660 int *old_ports, *new_ports;
8661 int i, new_count, rc;
8663 if (req->newptr == NULL && req->oldptr == NULL)
8664 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
8665 sizeof(sc->tt.tls_rx_ports[0])));
8667 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
8671 if (sc->tt.num_tls_rx_ports == 0) {
8673 rc = SYSCTL_OUT(req, &i, sizeof(i));
8675 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
8676 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
8677 if (rc == 0 && req->newptr != NULL) {
8678 new_count = req->newlen / sizeof(new_ports[0]);
8679 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
8681 rc = SYSCTL_IN(req, new_ports, new_count *
8682 sizeof(new_ports[0]));
8686 /* Allow setting to a single '-1' to clear the list. */
8687 if (new_count == 1 && new_ports[0] == -1) {
8689 old_ports = sc->tt.tls_rx_ports;
8690 sc->tt.tls_rx_ports = NULL;
8691 sc->tt.num_tls_rx_ports = 0;
8693 free(old_ports, M_CXGBE);
8695 for (i = 0; i < new_count; i++) {
8696 if (new_ports[i] < 1 ||
8697 new_ports[i] > IPPORT_MAX) {
8704 old_ports = sc->tt.tls_rx_ports;
8705 sc->tt.tls_rx_ports = new_ports;
8706 sc->tt.num_tls_rx_ports = new_count;
8708 free(old_ports, M_CXGBE);
8712 free(new_ports, M_CXGBE);
8714 end_synchronized_op(sc, 0);
8719 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8721 u_int rem = val % factor;
8724 snprintf(buf, len, "%u", val / factor);
8726 while (rem % 10 == 0)
8728 snprintf(buf, len, "%u.%u", val / factor, rem);
8733 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8735 struct adapter *sc = arg1;
8738 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8740 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8744 re = G_TIMERRESOLUTION(res);
8747 /* TCP timestamp tick */
8748 re = G_TIMESTAMPRESOLUTION(res);
8752 re = G_DELAYEDACKRESOLUTION(res);
8758 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
8760 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
8764 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
8766 struct adapter *sc = arg1;
8767 u_int res, dack_re, v;
8768 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8770 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8771 dack_re = G_DELAYEDACKRESOLUTION(res);
8772 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
8774 return (sysctl_handle_int(oidp, &v, 0, req));
8778 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
8780 struct adapter *sc = arg1;
8783 u_long tp_tick_us, v;
8784 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8786 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
8787 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
8788 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
8789 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
8791 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
8792 tp_tick_us = (cclk_ps << tre) / 1000000;
8794 if (reg == A_TP_INIT_SRTT)
8795 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
8797 v = tp_tick_us * t4_read_reg(sc, reg);
8799 return (sysctl_handle_long(oidp, &v, 0, req));
8803 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
8804 * passed to this function.
8807 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
8809 struct adapter *sc = arg1;
8813 MPASS(idx >= 0 && idx <= 24);
8815 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
8817 return (sysctl_handle_int(oidp, &v, 0, req));
8821 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
8823 struct adapter *sc = arg1;
8827 MPASS(idx >= 0 && idx < 16);
8829 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
8830 shift = (idx & 3) << 3;
8831 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
8833 return (sysctl_handle_int(oidp, &v, 0, req));
8837 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
8839 struct vi_info *vi = arg1;
8840 struct adapter *sc = vi->pi->adapter;
8842 struct sge_ofld_rxq *ofld_rxq;
8845 idx = vi->ofld_tmr_idx;
8847 rc = sysctl_handle_int(oidp, &idx, 0, req);
8848 if (rc != 0 || req->newptr == NULL)
8851 if (idx < 0 || idx >= SGE_NTIMERS)
8854 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8859 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
8860 for_each_ofld_rxq(vi, i, ofld_rxq) {
8861 #ifdef atomic_store_rel_8
8862 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
8864 ofld_rxq->iq.intr_params = v;
8867 vi->ofld_tmr_idx = idx;
8869 end_synchronized_op(sc, LOCK_HELD);
8874 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
8876 struct vi_info *vi = arg1;
8877 struct adapter *sc = vi->pi->adapter;
8880 idx = vi->ofld_pktc_idx;
8882 rc = sysctl_handle_int(oidp, &idx, 0, req);
8883 if (rc != 0 || req->newptr == NULL)
8886 if (idx < -1 || idx >= SGE_NCOUNTERS)
8889 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8894 if (vi->flags & VI_INIT_DONE)
8895 rc = EBUSY; /* cannot be changed once the queues are created */
8897 vi->ofld_pktc_idx = idx;
8899 end_synchronized_op(sc, LOCK_HELD);
8905 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8909 if (cntxt->cid > M_CTXTQID)
8912 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8913 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8916 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8920 if (sc->flags & FW_OK) {
8921 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8928 * Read via firmware failed or wasn't even attempted. Read directly via
8931 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8933 end_synchronized_op(sc, 0);
8938 load_fw(struct adapter *sc, struct t4_data *fw)
8943 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8948 * The firmware, with the sole exception of the memory parity error
8949 * handler, runs from memory and not flash. It is almost always safe to
8950 * install a new firmware on a running system. Just set bit 1 in
8951 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
8953 if (sc->flags & FULL_INIT_DONE &&
8954 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
8959 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8960 if (fw_data == NULL) {
8965 rc = copyin(fw->data, fw_data, fw->len);
8967 rc = -t4_load_fw(sc, fw_data, fw->len);
8969 free(fw_data, M_CXGBE);
8971 end_synchronized_op(sc, 0);
8976 load_cfg(struct adapter *sc, struct t4_data *cfg)
8979 uint8_t *cfg_data = NULL;
8981 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
8985 if (cfg->len == 0) {
8987 rc = -t4_load_cfg(sc, NULL, 0);
8991 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
8992 if (cfg_data == NULL) {
8997 rc = copyin(cfg->data, cfg_data, cfg->len);
8999 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9001 free(cfg_data, M_CXGBE);
9003 end_synchronized_op(sc, 0);
9008 load_boot(struct adapter *sc, struct t4_bootrom *br)
9011 uint8_t *br_data = NULL;
9014 if (br->len > 1024 * 1024)
9017 if (br->pf_offset == 0) {
9019 if (br->pfidx_addr > 7)
9021 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9022 A_PCIE_PF_EXPROM_OFST)));
9023 } else if (br->pf_offset == 1) {
9025 offset = G_OFFSET(br->pfidx_addr);
9030 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9036 rc = -t4_load_boot(sc, NULL, offset, 0);
9040 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9041 if (br_data == NULL) {
9046 rc = copyin(br->data, br_data, br->len);
9048 rc = -t4_load_boot(sc, br_data, offset, br->len);
9050 free(br_data, M_CXGBE);
9052 end_synchronized_op(sc, 0);
9057 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9060 uint8_t *bc_data = NULL;
9062 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9068 rc = -t4_load_bootcfg(sc, NULL, 0);
9072 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9073 if (bc_data == NULL) {
9078 rc = copyin(bc->data, bc_data, bc->len);
9080 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9082 free(bc_data, M_CXGBE);
9084 end_synchronized_op(sc, 0);
9089 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9092 struct cudbg_init *cudbg;
9095 /* buf is large, don't block if no memory is available */
9096 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9100 handle = cudbg_alloc_handle();
9101 if (handle == NULL) {
9106 cudbg = cudbg_get_init(handle);
9108 cudbg->print = (cudbg_print_cb)printf;
9111 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9112 __func__, dump->wr_flash, dump->len, dump->data);
9116 cudbg->use_flash = 1;
9117 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9118 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9120 rc = cudbg_collect(handle, buf, &dump->len);
9124 rc = copyout(buf, dump->data, dump->len);
9126 cudbg_free_handle(handle);
9132 free_offload_policy(struct t4_offload_policy *op)
9134 struct offload_rule *r;
9141 for (i = 0; i < op->nrules; i++, r++) {
9142 free(r->bpf_prog.bf_insns, M_CXGBE);
9144 free(op->rule, M_CXGBE);
9149 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9152 struct t4_offload_policy *op, *old;
9153 struct bpf_program *bf;
9154 const struct offload_settings *s;
9155 struct offload_rule *r;
9158 if (!is_offload(sc))
9161 if (uop->nrules == 0) {
9162 /* Delete installed policies. */
9165 } if (uop->nrules > 256) { /* arbitrary */
9169 /* Copy userspace offload policy to kernel */
9170 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9171 op->nrules = uop->nrules;
9172 len = op->nrules * sizeof(struct offload_rule);
9173 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9174 rc = copyin(uop->rule, op->rule, len);
9176 free(op->rule, M_CXGBE);
9182 for (i = 0; i < op->nrules; i++, r++) {
9184 /* Validate open_type */
9185 if (r->open_type != OPEN_TYPE_LISTEN &&
9186 r->open_type != OPEN_TYPE_ACTIVE &&
9187 r->open_type != OPEN_TYPE_PASSIVE &&
9188 r->open_type != OPEN_TYPE_DONTCARE) {
9191 * Rules 0 to i have malloc'd filters that need to be
9192 * freed. Rules i+1 to nrules have userspace pointers
9193 * and should be left alone.
9196 free_offload_policy(op);
9200 /* Validate settings */
9202 if ((s->offload != 0 && s->offload != 1) ||
9203 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9204 s->sched_class < -1 ||
9205 s->sched_class >= sc->chip_params->nsched_cls) {
9211 u = bf->bf_insns; /* userspace ptr */
9212 bf->bf_insns = NULL;
9213 if (bf->bf_len == 0) {
9214 /* legal, matches everything */
9217 len = bf->bf_len * sizeof(*bf->bf_insns);
9218 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9219 rc = copyin(u, bf->bf_insns, len);
9223 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9229 rw_wlock(&sc->policy_lock);
9232 rw_wunlock(&sc->policy_lock);
9233 free_offload_policy(old);
9238 #define MAX_READ_BUF_SIZE (128 * 1024)
9240 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9242 uint32_t addr, remaining, n;
9247 rc = validate_mem_range(sc, mr->addr, mr->len);
9251 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9253 remaining = mr->len;
9254 dst = (void *)mr->data;
9257 n = min(remaining, MAX_READ_BUF_SIZE);
9258 read_via_memwin(sc, 2, addr, buf, n);
9260 rc = copyout(buf, dst, n);
9272 #undef MAX_READ_BUF_SIZE
9275 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9279 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9282 if (i2cd->len > sizeof(i2cd->data))
9285 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9288 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9289 i2cd->offset, i2cd->len, &i2cd->data[0]);
9290 end_synchronized_op(sc, 0);
9296 t4_os_find_pci_capability(struct adapter *sc, int cap)
9300 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9304 t4_os_pci_save_state(struct adapter *sc)
9307 struct pci_devinfo *dinfo;
9310 dinfo = device_get_ivars(dev);
9312 pci_cfg_save(dev, dinfo, 0);
9317 t4_os_pci_restore_state(struct adapter *sc)
9320 struct pci_devinfo *dinfo;
9323 dinfo = device_get_ivars(dev);
9325 pci_cfg_restore(dev, dinfo);
9330 t4_os_portmod_changed(struct port_info *pi)
9332 struct adapter *sc = pi->adapter;
9335 static const char *mod_str[] = {
9336 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9339 MPASS((pi->flags & FIXED_IFMEDIA) == 0);
9342 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9344 build_medialist(pi, &pi->media);
9347 end_synchronized_op(sc, LOCK_HELD);
9351 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9352 if_printf(ifp, "transceiver unplugged.\n");
9353 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9354 if_printf(ifp, "unknown transceiver inserted.\n");
9355 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9356 if_printf(ifp, "unsupported transceiver inserted.\n");
9357 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9358 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9359 port_top_speed(pi), mod_str[pi->mod_type]);
9361 if_printf(ifp, "transceiver (type %d) inserted.\n",
9367 t4_os_link_changed(struct port_info *pi)
9371 struct link_config *lc;
9374 PORT_LOCK_ASSERT_OWNED(pi);
9376 for_each_vi(pi, v, vi) {
9383 ifp->if_baudrate = IF_Mbps(lc->speed);
9384 if_link_state_change(ifp, LINK_STATE_UP);
9386 if_link_state_change(ifp, LINK_STATE_DOWN);
9392 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9396 sx_slock(&t4_list_lock);
9397 SLIST_FOREACH(sc, &t4_list, link) {
9399 * func should not make any assumptions about what state sc is
9400 * in - the only guarantee is that sc->sc_lock is a valid lock.
9404 sx_sunlock(&t4_list_lock);
9408 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9412 struct adapter *sc = dev->si_drv1;
9414 rc = priv_check(td, PRIV_DRIVER);
9419 case CHELSIO_T4_GETREG: {
9420 struct t4_reg *edata = (struct t4_reg *)data;
9422 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9425 if (edata->size == 4)
9426 edata->val = t4_read_reg(sc, edata->addr);
9427 else if (edata->size == 8)
9428 edata->val = t4_read_reg64(sc, edata->addr);
9434 case CHELSIO_T4_SETREG: {
9435 struct t4_reg *edata = (struct t4_reg *)data;
9437 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9440 if (edata->size == 4) {
9441 if (edata->val & 0xffffffff00000000)
9443 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9444 } else if (edata->size == 8)
9445 t4_write_reg64(sc, edata->addr, edata->val);
9450 case CHELSIO_T4_REGDUMP: {
9451 struct t4_regdump *regs = (struct t4_regdump *)data;
9452 int reglen = t4_get_regs_len(sc);
9455 if (regs->len < reglen) {
9456 regs->len = reglen; /* hint to the caller */
9461 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9462 get_regs(sc, regs, buf);
9463 rc = copyout(buf, regs->data, reglen);
9467 case CHELSIO_T4_GET_FILTER_MODE:
9468 rc = get_filter_mode(sc, (uint32_t *)data);
9470 case CHELSIO_T4_SET_FILTER_MODE:
9471 rc = set_filter_mode(sc, *(uint32_t *)data);
9473 case CHELSIO_T4_GET_FILTER:
9474 rc = get_filter(sc, (struct t4_filter *)data);
9476 case CHELSIO_T4_SET_FILTER:
9477 rc = set_filter(sc, (struct t4_filter *)data);
9479 case CHELSIO_T4_DEL_FILTER:
9480 rc = del_filter(sc, (struct t4_filter *)data);
9482 case CHELSIO_T4_GET_SGE_CONTEXT:
9483 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9485 case CHELSIO_T4_LOAD_FW:
9486 rc = load_fw(sc, (struct t4_data *)data);
9488 case CHELSIO_T4_GET_MEM:
9489 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9491 case CHELSIO_T4_GET_I2C:
9492 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9494 case CHELSIO_T4_CLEAR_STATS: {
9496 u_int port_id = *(uint32_t *)data;
9497 struct port_info *pi;
9500 if (port_id >= sc->params.nports)
9502 pi = sc->port[port_id];
9507 t4_clr_port_stats(sc, pi->tx_chan);
9508 pi->tx_parse_error = 0;
9509 pi->tnl_cong_drops = 0;
9510 mtx_lock(&sc->reg_lock);
9511 for_each_vi(pi, v, vi) {
9512 if (vi->flags & VI_INIT_DONE)
9513 t4_clr_vi_stats(sc, vi->viid);
9515 bg_map = pi->mps_bg_map;
9518 i = ffs(bg_map) - 1;
9519 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
9520 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
9521 bg_map &= ~(1 << i);
9523 mtx_unlock(&sc->reg_lock);
9526 * Since this command accepts a port, clear stats for
9527 * all VIs on this port.
9529 for_each_vi(pi, v, vi) {
9530 if (vi->flags & VI_INIT_DONE) {
9531 struct sge_rxq *rxq;
9532 struct sge_txq *txq;
9533 struct sge_wrq *wrq;
9535 for_each_rxq(vi, i, rxq) {
9536 #if defined(INET) || defined(INET6)
9537 rxq->lro.lro_queued = 0;
9538 rxq->lro.lro_flushed = 0;
9541 rxq->vlan_extraction = 0;
9544 for_each_txq(vi, i, txq) {
9547 txq->vlan_insertion = 0;
9551 txq->txpkts0_wrs = 0;
9552 txq->txpkts1_wrs = 0;
9553 txq->txpkts0_pkts = 0;
9554 txq->txpkts1_pkts = 0;
9555 mp_ring_reset_stats(txq->r);
9559 /* nothing to clear for each ofld_rxq */
9561 for_each_ofld_txq(vi, i, wrq) {
9562 wrq->tx_wrs_direct = 0;
9563 wrq->tx_wrs_copied = 0;
9567 if (IS_MAIN_VI(vi)) {
9568 wrq = &sc->sge.ctrlq[pi->port_id];
9569 wrq->tx_wrs_direct = 0;
9570 wrq->tx_wrs_copied = 0;
9576 case CHELSIO_T4_SCHED_CLASS:
9577 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9579 case CHELSIO_T4_SCHED_QUEUE:
9580 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9582 case CHELSIO_T4_GET_TRACER:
9583 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9585 case CHELSIO_T4_SET_TRACER:
9586 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9588 case CHELSIO_T4_LOAD_CFG:
9589 rc = load_cfg(sc, (struct t4_data *)data);
9591 case CHELSIO_T4_LOAD_BOOT:
9592 rc = load_boot(sc, (struct t4_bootrom *)data);
9594 case CHELSIO_T4_LOAD_BOOTCFG:
9595 rc = load_bootcfg(sc, (struct t4_data *)data);
9597 case CHELSIO_T4_CUDBG_DUMP:
9598 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
9600 case CHELSIO_T4_SET_OFLD_POLICY:
9601 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
9611 t4_db_full(struct adapter *sc)
9614 CXGBE_UNIMPLEMENTED(__func__);
9618 t4_db_dropped(struct adapter *sc)
9621 CXGBE_UNIMPLEMENTED(__func__);
9626 toe_capability(struct vi_info *vi, int enable)
9629 struct port_info *pi = vi->pi;
9630 struct adapter *sc = pi->adapter;
9632 ASSERT_SYNCHRONIZED_OP(sc);
9634 if (!is_offload(sc))
9638 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9639 /* TOE is already enabled. */
9644 * We need the port's queues around so that we're able to send
9645 * and receive CPLs to/from the TOE even if the ifnet for this
9646 * port has never been UP'd administratively.
9648 if (!(vi->flags & VI_INIT_DONE)) {
9649 rc = vi_full_init(vi);
9653 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9654 rc = vi_full_init(&pi->vi[0]);
9659 if (isset(&sc->offload_map, pi->port_id)) {
9660 /* TOE is enabled on another VI of this port. */
9665 if (!uld_active(sc, ULD_TOM)) {
9666 rc = t4_activate_uld(sc, ULD_TOM);
9669 "You must kldload t4_tom.ko before trying "
9670 "to enable TOE on a cxgbe interface.\n");
9674 KASSERT(sc->tom_softc != NULL,
9675 ("%s: TOM activated but softc NULL", __func__));
9676 KASSERT(uld_active(sc, ULD_TOM),
9677 ("%s: TOM activated but flag not set", __func__));
9680 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9681 if (!uld_active(sc, ULD_IWARP))
9682 (void) t4_activate_uld(sc, ULD_IWARP);
9683 if (!uld_active(sc, ULD_ISCSI))
9684 (void) t4_activate_uld(sc, ULD_ISCSI);
9687 setbit(&sc->offload_map, pi->port_id);
9691 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9694 KASSERT(uld_active(sc, ULD_TOM),
9695 ("%s: TOM never initialized?", __func__));
9696 clrbit(&sc->offload_map, pi->port_id);
9703 * Add an upper layer driver to the global list.
9706 t4_register_uld(struct uld_info *ui)
9711 sx_xlock(&t4_uld_list_lock);
9712 SLIST_FOREACH(u, &t4_uld_list, link) {
9713 if (u->uld_id == ui->uld_id) {
9719 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9722 sx_xunlock(&t4_uld_list_lock);
9727 t4_unregister_uld(struct uld_info *ui)
9732 sx_xlock(&t4_uld_list_lock);
9734 SLIST_FOREACH(u, &t4_uld_list, link) {
9736 if (ui->refcount > 0) {
9741 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9747 sx_xunlock(&t4_uld_list_lock);
9752 t4_activate_uld(struct adapter *sc, int id)
9755 struct uld_info *ui;
9757 ASSERT_SYNCHRONIZED_OP(sc);
9759 if (id < 0 || id > ULD_MAX)
9761 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9763 sx_slock(&t4_uld_list_lock);
9765 SLIST_FOREACH(ui, &t4_uld_list, link) {
9766 if (ui->uld_id == id) {
9767 if (!(sc->flags & FULL_INIT_DONE)) {
9768 rc = adapter_full_init(sc);
9773 rc = ui->activate(sc);
9775 setbit(&sc->active_ulds, id);
9782 sx_sunlock(&t4_uld_list_lock);
9788 t4_deactivate_uld(struct adapter *sc, int id)
9791 struct uld_info *ui;
9793 ASSERT_SYNCHRONIZED_OP(sc);
9795 if (id < 0 || id > ULD_MAX)
9799 sx_slock(&t4_uld_list_lock);
9801 SLIST_FOREACH(ui, &t4_uld_list, link) {
9802 if (ui->uld_id == id) {
9803 rc = ui->deactivate(sc);
9805 clrbit(&sc->active_ulds, id);
9812 sx_sunlock(&t4_uld_list_lock);
9818 uld_active(struct adapter *sc, int uld_id)
9821 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9823 return (isset(&sc->active_ulds, uld_id));
9828 * t = ptr to tunable.
9829 * nc = number of CPUs.
9830 * c = compiled in default for that tunable.
9833 calculate_nqueues(int *t, int nc, const int c)
9839 nq = *t < 0 ? -*t : c;
9844 * Come up with reasonable defaults for some of the tunables, provided they're
9845 * not set by the user (in which case we'll use the values as is).
9848 tweak_tunables(void)
9850 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9854 t4_ntxq = rss_getnumbuckets();
9856 calculate_nqueues(&t4_ntxq, nc, NTXQ);
9860 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
9864 t4_nrxq = rss_getnumbuckets();
9866 calculate_nqueues(&t4_nrxq, nc, NRXQ);
9870 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
9872 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
9873 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
9874 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
9877 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
9878 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
9880 if (t4_toecaps_allowed == -1)
9881 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9883 if (t4_rdmacaps_allowed == -1) {
9884 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9885 FW_CAPS_CONFIG_RDMA_RDMAC;
9888 if (t4_iscsicaps_allowed == -1) {
9889 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9890 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9891 FW_CAPS_CONFIG_ISCSI_T10DIF;
9894 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
9895 t4_tmr_idx_ofld = TMR_IDX_OFLD;
9897 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
9898 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
9900 if (t4_toecaps_allowed == -1)
9901 t4_toecaps_allowed = 0;
9903 if (t4_rdmacaps_allowed == -1)
9904 t4_rdmacaps_allowed = 0;
9906 if (t4_iscsicaps_allowed == -1)
9907 t4_iscsicaps_allowed = 0;
9911 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
9912 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
9915 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
9916 t4_tmr_idx = TMR_IDX;
9918 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
9919 t4_pktc_idx = PKTC_IDX;
9921 if (t4_qsize_txq < 128)
9924 if (t4_qsize_rxq < 128)
9926 while (t4_qsize_rxq & 7)
9929 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9932 * Number of VIs to create per-port. The first VI is the "main" regular
9933 * VI for the port. The rest are additional virtual interfaces on the
9934 * same physical port. Note that the main VI does not have native
9935 * netmap support but the extra VIs do.
9937 * Limit the number of VIs per port to the number of available
9938 * MAC addresses per port.
9942 if (t4_num_vis > nitems(vi_mac_funcs)) {
9943 t4_num_vis = nitems(vi_mac_funcs);
9944 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
9947 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
9948 pcie_relaxed_ordering = 1;
9949 #if defined(__i386__) || defined(__amd64__)
9950 if (cpu_vendor_id == CPU_VENDOR_INTEL)
9951 pcie_relaxed_ordering = 0;
9958 t4_dump_tcb(struct adapter *sc, int tid)
9960 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9962 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9963 save = t4_read_reg(sc, reg);
9964 base = sc->memwin[2].mw_base;
9966 /* Dump TCB for the tid */
9967 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9968 tcb_addr += tid * TCB_SIZE;
9972 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9974 pf = V_PFNUM(sc->pf);
9975 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9977 t4_write_reg(sc, reg, win_pos | pf);
9978 t4_read_reg(sc, reg);
9980 off = tcb_addr - win_pos;
9981 for (i = 0; i < 4; i++) {
9983 for (j = 0; j < 8; j++, off += 4)
9984 buf[j] = htonl(t4_read_reg(sc, base + off));
9986 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9987 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9991 t4_write_reg(sc, reg, save);
9992 t4_read_reg(sc, reg);
9996 t4_dump_devlog(struct adapter *sc)
9998 struct devlog_params *dparams = &sc->params.devlog;
9999 struct fw_devlog_e e;
10000 int i, first, j, m, nentries, rc;
10001 uint64_t ftstamp = UINT64_MAX;
10003 if (dparams->start == 0) {
10004 db_printf("devlog params not valid\n");
10008 nentries = dparams->size / sizeof(struct fw_devlog_e);
10009 m = fwmtype_to_hwmtype(dparams->memtype);
10011 /* Find the first entry. */
10013 for (i = 0; i < nentries && !db_pager_quit; i++) {
10014 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10015 sizeof(e), (void *)&e);
10019 if (e.timestamp == 0)
10022 e.timestamp = be64toh(e.timestamp);
10023 if (e.timestamp < ftstamp) {
10024 ftstamp = e.timestamp;
10034 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10035 sizeof(e), (void *)&e);
10039 if (e.timestamp == 0)
10042 e.timestamp = be64toh(e.timestamp);
10043 e.seqno = be32toh(e.seqno);
10044 for (j = 0; j < 8; j++)
10045 e.params[j] = be32toh(e.params[j]);
10047 db_printf("%10d %15ju %8s %8s ",
10048 e.seqno, e.timestamp,
10049 (e.level < nitems(devlog_level_strings) ?
10050 devlog_level_strings[e.level] : "UNKNOWN"),
10051 (e.facility < nitems(devlog_facility_strings) ?
10052 devlog_facility_strings[e.facility] : "UNKNOWN"));
10053 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10054 e.params[3], e.params[4], e.params[5], e.params[6],
10057 if (++i == nentries)
10059 } while (i != first && !db_pager_quit);
10062 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10063 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10065 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10072 t = db_read_token();
10074 dev = device_lookup_by_name(db_tok_string);
10079 db_printf("usage: show t4 devlog <nexus>\n");
10084 db_printf("device not found\n");
10088 t4_dump_devlog(device_get_softc(dev));
10091 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10100 t = db_read_token();
10102 dev = device_lookup_by_name(db_tok_string);
10103 t = db_read_token();
10104 if (t == tNUMBER) {
10105 tid = db_tok_number;
10112 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10117 db_printf("device not found\n");
10121 db_printf("invalid tid\n");
10125 t4_dump_tcb(device_get_softc(dev), tid);
10130 * Borrowed from cesa_prep_aes_key().
10132 * NB: The crypto engine wants the words in the decryption key in reverse
10136 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10138 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10142 rijndaelKeySetupEnc(ek, enc_key, kbits);
10144 dkey += (kbits / 8) / 4;
10148 for (i = 0; i < 4; i++)
10149 *--dkey = htobe32(ek[4 * 10 + i]);
10152 for (i = 0; i < 2; i++)
10153 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10154 for (i = 0; i < 4; i++)
10155 *--dkey = htobe32(ek[4 * 12 + i]);
10158 for (i = 0; i < 4; i++)
10159 *--dkey = htobe32(ek[4 * 13 + i]);
10160 for (i = 0; i < 4; i++)
10161 *--dkey = htobe32(ek[4 * 14 + i]);
10164 MPASS(dkey == dec_key);
10167 static struct sx mlu; /* mod load unload */
10168 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10171 mod_event(module_t mod, int cmd, void *arg)
10174 static int loaded = 0;
10179 if (loaded++ == 0) {
10181 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10182 t4_filter_rpl, CPL_COOKIE_FILTER);
10183 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10184 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10185 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10186 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10187 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10188 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10189 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10190 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10191 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10192 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10193 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10195 sx_init(&t4_list_lock, "T4/T5 adapters");
10196 SLIST_INIT(&t4_list);
10198 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10199 SLIST_INIT(&t4_uld_list);
10201 t4_tracer_modload();
10209 if (--loaded == 0) {
10212 sx_slock(&t4_list_lock);
10213 if (!SLIST_EMPTY(&t4_list)) {
10215 sx_sunlock(&t4_list_lock);
10219 sx_slock(&t4_uld_list_lock);
10220 if (!SLIST_EMPTY(&t4_uld_list)) {
10222 sx_sunlock(&t4_uld_list_lock);
10223 sx_sunlock(&t4_list_lock);
10228 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10229 uprintf("%ju clusters with custom free routine "
10230 "still is use.\n", t4_sge_extfree_refs());
10231 pause("t4unload", 2 * hz);
10234 sx_sunlock(&t4_uld_list_lock);
10236 sx_sunlock(&t4_list_lock);
10238 if (t4_sge_extfree_refs() == 0) {
10239 t4_tracer_modunload();
10241 sx_destroy(&t4_uld_list_lock);
10243 sx_destroy(&t4_list_lock);
10244 t4_sge_modunload();
10248 loaded++; /* undo earlier decrement */
10259 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10260 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10261 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10263 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10264 MODULE_VERSION(t4nex, 1);
10265 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10267 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10268 #endif /* DEV_NETMAP */
10270 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10271 MODULE_VERSION(t5nex, 1);
10272 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10274 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10275 #endif /* DEV_NETMAP */
10277 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10278 MODULE_VERSION(t6nex, 1);
10279 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10281 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10282 #endif /* DEV_NETMAP */
10284 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10285 MODULE_VERSION(cxgbe, 1);
10287 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10288 MODULE_VERSION(cxl, 1);
10290 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10291 MODULE_VERSION(cc, 1);
10293 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10294 MODULE_VERSION(vcxgbe, 1);
10296 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10297 MODULE_VERSION(vcxl, 1);
10299 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10300 MODULE_VERSION(vcc, 1);