2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
74 #include <crypto/rijndael/rijndael.h>
77 #include <ddb/db_lex.h>
80 #include "common/common.h"
81 #include "common/t4_msg.h"
82 #include "common/t4_regs.h"
83 #include "common/t4_regs_values.h"
84 #include "cudbg/cudbg.h"
88 #include "t4_mp_ring.h"
92 /* T4 bus driver interface */
93 static int t4_probe(device_t);
94 static int t4_attach(device_t);
95 static int t4_detach(device_t);
96 static int t4_child_location_str(device_t, device_t, char *, size_t);
97 static int t4_ready(device_t);
98 static int t4_read_port_device(device_t, int, device_t *);
99 static device_method_t t4_methods[] = {
100 DEVMETHOD(device_probe, t4_probe),
101 DEVMETHOD(device_attach, t4_attach),
102 DEVMETHOD(device_detach, t4_detach),
104 DEVMETHOD(bus_child_location_str, t4_child_location_str),
106 DEVMETHOD(t4_is_main_ready, t4_ready),
107 DEVMETHOD(t4_read_port_device, t4_read_port_device),
111 static driver_t t4_driver = {
114 sizeof(struct adapter)
118 /* T4 port (cxgbe) interface */
119 static int cxgbe_probe(device_t);
120 static int cxgbe_attach(device_t);
121 static int cxgbe_detach(device_t);
122 device_method_t cxgbe_methods[] = {
123 DEVMETHOD(device_probe, cxgbe_probe),
124 DEVMETHOD(device_attach, cxgbe_attach),
125 DEVMETHOD(device_detach, cxgbe_detach),
128 static driver_t cxgbe_driver = {
131 sizeof(struct port_info)
134 /* T4 VI (vcxgbe) interface */
135 static int vcxgbe_probe(device_t);
136 static int vcxgbe_attach(device_t);
137 static int vcxgbe_detach(device_t);
138 static device_method_t vcxgbe_methods[] = {
139 DEVMETHOD(device_probe, vcxgbe_probe),
140 DEVMETHOD(device_attach, vcxgbe_attach),
141 DEVMETHOD(device_detach, vcxgbe_detach),
144 static driver_t vcxgbe_driver = {
147 sizeof(struct vi_info)
150 static d_ioctl_t t4_ioctl;
152 static struct cdevsw t4_cdevsw = {
153 .d_version = D_VERSION,
158 /* T5 bus driver interface */
159 static int t5_probe(device_t);
160 static device_method_t t5_methods[] = {
161 DEVMETHOD(device_probe, t5_probe),
162 DEVMETHOD(device_attach, t4_attach),
163 DEVMETHOD(device_detach, t4_detach),
165 DEVMETHOD(bus_child_location_str, t4_child_location_str),
167 DEVMETHOD(t4_is_main_ready, t4_ready),
168 DEVMETHOD(t4_read_port_device, t4_read_port_device),
172 static driver_t t5_driver = {
175 sizeof(struct adapter)
179 /* T5 port (cxl) interface */
180 static driver_t cxl_driver = {
183 sizeof(struct port_info)
186 /* T5 VI (vcxl) interface */
187 static driver_t vcxl_driver = {
190 sizeof(struct vi_info)
193 /* T6 bus driver interface */
194 static int t6_probe(device_t);
195 static device_method_t t6_methods[] = {
196 DEVMETHOD(device_probe, t6_probe),
197 DEVMETHOD(device_attach, t4_attach),
198 DEVMETHOD(device_detach, t4_detach),
200 DEVMETHOD(bus_child_location_str, t4_child_location_str),
202 DEVMETHOD(t4_is_main_ready, t4_ready),
203 DEVMETHOD(t4_read_port_device, t4_read_port_device),
207 static driver_t t6_driver = {
210 sizeof(struct adapter)
214 /* T6 port (cc) interface */
215 static driver_t cc_driver = {
218 sizeof(struct port_info)
221 /* T6 VI (vcc) interface */
222 static driver_t vcc_driver = {
225 sizeof(struct vi_info)
228 /* ifnet interface */
229 static void cxgbe_init(void *);
230 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
231 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
232 static void cxgbe_qflush(struct ifnet *);
234 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
237 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
238 * then ADAPTER_LOCK, then t4_uld_list_lock.
240 static struct sx t4_list_lock;
241 SLIST_HEAD(, adapter) t4_list;
243 static struct sx t4_uld_list_lock;
244 SLIST_HEAD(, uld_info) t4_uld_list;
248 * Tunables. See tweak_tunables() too.
250 * Each tunable is set to a default value here if it's known at compile-time.
251 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
252 * provide a reasonable default (upto n) when the driver is loaded.
254 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
255 * T5 are under hw.cxl.
257 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters");
258 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters");
259 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters");
262 * Number of queues for tx and rx, NIC and offload.
266 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
267 "Number of TX queues per port");
268 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
272 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
273 "Number of RX queues per port");
274 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
277 static int t4_ntxq_vi = -NTXQ_VI;
278 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
279 "Number of TX queues per VI");
282 static int t4_nrxq_vi = -NRXQ_VI;
283 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
284 "Number of RX queues per VI");
286 static int t4_rsrv_noflowq = 0;
287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
288 0, "Reserve TX queue 0 of each VI for non-flowid packets");
290 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
292 static int t4_nofldtxq = -NOFLDTXQ;
293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
294 "Number of offload TX queues per port");
297 static int t4_nofldrxq = -NOFLDRXQ;
298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
299 "Number of offload RX queues per port");
301 #define NOFLDTXQ_VI 1
302 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
303 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
304 "Number of offload TX queues per VI");
306 #define NOFLDRXQ_VI 1
307 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
309 "Number of offload RX queues per VI");
311 #define TMR_IDX_OFLD 1
312 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
314 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
316 #define PKTC_IDX_OFLD (-1)
317 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
319 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
321 /* 0 means chip/fw default, non-zero number is value in microseconds */
322 static u_long t4_toe_keepalive_idle = 0;
323 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
324 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
326 /* 0 means chip/fw default, non-zero number is value in microseconds */
327 static u_long t4_toe_keepalive_interval = 0;
328 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
329 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
331 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
332 static int t4_toe_keepalive_count = 0;
333 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
334 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
336 /* 0 means chip/fw default, non-zero number is value in microseconds */
337 static u_long t4_toe_rexmt_min = 0;
338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
339 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
341 /* 0 means chip/fw default, non-zero number is value in microseconds */
342 static u_long t4_toe_rexmt_max = 0;
343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
344 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
346 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
347 static int t4_toe_rexmt_count = 0;
348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
349 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
351 /* -1 means chip/fw default, other values are raw backoff values to use */
352 static int t4_toe_rexmt_backoff[16] = {
353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
355 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0,
356 "cxgbe(4) TOE retransmit backoff values");
357 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
358 &t4_toe_rexmt_backoff[0], 0, "");
359 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
360 &t4_toe_rexmt_backoff[1], 0, "");
361 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
362 &t4_toe_rexmt_backoff[2], 0, "");
363 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
364 &t4_toe_rexmt_backoff[3], 0, "");
365 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
366 &t4_toe_rexmt_backoff[4], 0, "");
367 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
368 &t4_toe_rexmt_backoff[5], 0, "");
369 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
370 &t4_toe_rexmt_backoff[6], 0, "");
371 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
372 &t4_toe_rexmt_backoff[7], 0, "");
373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_backoff[8], 0, "");
375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_backoff[9], 0, "");
377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
378 &t4_toe_rexmt_backoff[10], 0, "");
379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
380 &t4_toe_rexmt_backoff[11], 0, "");
381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
382 &t4_toe_rexmt_backoff[12], 0, "");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[13], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[14], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[15], 0, "");
393 static int t4_nnmtxq_vi = -NNMTXQ_VI;
394 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
395 "Number of netmap TX queues per VI");
398 static int t4_nnmrxq_vi = -NNMRXQ_VI;
399 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
400 "Number of netmap RX queues per VI");
404 * Holdoff parameters for ports.
407 int t4_tmr_idx = TMR_IDX;
408 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
409 0, "Holdoff timer index");
410 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
412 #define PKTC_IDX (-1)
413 int t4_pktc_idx = PKTC_IDX;
414 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
415 0, "Holdoff packet counter index");
416 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
419 * Size (# of entries) of each tx and rx queue.
421 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
422 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
423 "Number of descriptors in each TX queue");
425 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
427 "Number of descriptors in each RX queue");
430 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
432 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
433 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
434 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
437 * Configuration file. All the _CF names here are special.
439 #define DEFAULT_CF "default"
440 #define BUILTIN_CF "built-in"
441 #define FLASH_CF "flash"
442 #define UWIRE_CF "uwire"
443 #define FPGA_CF "fpga"
444 static char t4_cfg_file[32] = DEFAULT_CF;
445 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
446 sizeof(t4_cfg_file), "Firmware configuration file");
449 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
450 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
451 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
452 * mark or when signalled to do so, 0 to never emit PAUSE.
453 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
454 * negotiated settings will override rx_pause/tx_pause.
455 * Otherwise rx_pause/tx_pause are applied forcibly.
457 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
459 &t4_pause_settings, 0,
460 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
463 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
464 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
467 static int t4_fec = -1;
468 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
469 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
472 * Link autonegotiation.
473 * -1 to run with the firmware default.
477 static int t4_autoneg = -1;
478 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
479 "Link autonegotiation");
482 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
483 * encouraged respectively). '-n' is the same as 'n' except the firmware
484 * version used in the checks is read from the firmware bundled with the driver.
486 static int t4_fw_install = 1;
487 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
488 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
491 * ASIC features that will be used. Disable the ones you don't want so that the
492 * chip resources aren't wasted on features that will not be used.
494 static int t4_nbmcaps_allowed = 0;
495 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
496 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
498 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
499 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
500 &t4_linkcaps_allowed, 0, "Default link capabilities");
502 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
503 FW_CAPS_CONFIG_SWITCH_EGRESS;
504 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
505 &t4_switchcaps_allowed, 0, "Default switch capabilities");
508 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
509 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
511 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
512 FW_CAPS_CONFIG_NIC_HASHFILTER;
514 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
515 &t4_niccaps_allowed, 0, "Default NIC capabilities");
517 static int t4_toecaps_allowed = -1;
518 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
519 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
521 static int t4_rdmacaps_allowed = -1;
522 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
523 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
525 static int t4_cryptocaps_allowed = -1;
526 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
527 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
529 static int t4_iscsicaps_allowed = -1;
530 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
531 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
533 static int t4_fcoecaps_allowed = 0;
534 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
535 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
537 static int t5_write_combine = 0;
538 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
539 0, "Use WC instead of UC for BAR2");
541 static int t4_num_vis = 1;
542 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
543 "Number of VIs per port");
546 * PCIe Relaxed Ordering.
547 * -1: driver should figure out a good value.
552 static int pcie_relaxed_ordering = -1;
553 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
554 &pcie_relaxed_ordering, 0,
555 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
557 static int t4_panic_on_fatal_err = 0;
558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
559 &t4_panic_on_fatal_err, 0, "panic on fatal firmware errors");
565 static int t4_cop_managed_offloading = 0;
566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
567 &t4_cop_managed_offloading, 0,
568 "COP (Connection Offload Policy) controls all TOE offload");
571 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
572 static int vi_mac_funcs[] = {
576 FW_VI_FUNC_OPENISCSI,
582 struct intrs_and_queues {
583 uint16_t intr_type; /* INTx, MSI, or MSI-X */
584 uint16_t num_vis; /* number of VIs for each port */
585 uint16_t nirq; /* Total # of vectors */
586 uint16_t ntxq; /* # of NIC txq's for each port */
587 uint16_t nrxq; /* # of NIC rxq's for each port */
588 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
589 uint16_t nofldrxq; /* # of TOE rxq's for each port */
591 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
592 uint16_t ntxq_vi; /* # of NIC txq's */
593 uint16_t nrxq_vi; /* # of NIC rxq's */
594 uint16_t nofldtxq_vi; /* # of TOE txq's */
595 uint16_t nofldrxq_vi; /* # of TOE rxq's */
596 uint16_t nnmtxq_vi; /* # of netmap txq's */
597 uint16_t nnmrxq_vi; /* # of netmap rxq's */
600 static void setup_memwin(struct adapter *);
601 static void position_memwin(struct adapter *, int, uint32_t);
602 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
603 static int fwmtype_to_hwmtype(int);
604 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
606 static int fixup_devlog_params(struct adapter *);
607 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
608 static int contact_firmware(struct adapter *);
609 static int partition_resources(struct adapter *);
610 static int get_params__pre_init(struct adapter *);
611 static int get_params__post_init(struct adapter *);
612 static int set_params__post_init(struct adapter *);
613 static void t4_set_desc(struct adapter *);
614 static bool fixed_ifmedia(struct port_info *);
615 static void build_medialist(struct port_info *);
616 static void init_link_config(struct port_info *);
617 static int fixup_link_config(struct port_info *);
618 static int apply_link_config(struct port_info *);
619 static int cxgbe_init_synchronized(struct vi_info *);
620 static int cxgbe_uninit_synchronized(struct vi_info *);
621 static void quiesce_txq(struct adapter *, struct sge_txq *);
622 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
623 static void quiesce_iq(struct adapter *, struct sge_iq *);
624 static void quiesce_fl(struct adapter *, struct sge_fl *);
625 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
626 driver_intr_t *, void *, char *);
627 static int t4_free_irq(struct adapter *, struct irq *);
628 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
629 static void vi_refresh_stats(struct adapter *, struct vi_info *);
630 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
631 static void cxgbe_tick(void *);
632 static void cxgbe_sysctls(struct port_info *);
633 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
634 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
635 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
636 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
637 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
638 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
639 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
640 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
641 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
642 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
643 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
644 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
645 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
646 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
647 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
648 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
649 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
650 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
651 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
652 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
653 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
654 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
655 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
656 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
657 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
658 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
659 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
660 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
661 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
662 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
663 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
664 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
665 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
666 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
667 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
668 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
669 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
670 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
671 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
672 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
673 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
674 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
675 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
677 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
678 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
679 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
680 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
681 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
682 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
683 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
684 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
686 static int get_sge_context(struct adapter *, struct t4_sge_context *);
687 static int load_fw(struct adapter *, struct t4_data *);
688 static int load_cfg(struct adapter *, struct t4_data *);
689 static int load_boot(struct adapter *, struct t4_bootrom *);
690 static int load_bootcfg(struct adapter *, struct t4_data *);
691 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
692 static void free_offload_policy(struct t4_offload_policy *);
693 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
694 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
695 static int read_i2c(struct adapter *, struct t4_i2c_data *);
697 static int toe_capability(struct vi_info *, int);
699 static int mod_event(module_t, int, void *);
700 static int notify_siblings(device_t, int);
706 {0xa000, "Chelsio Terminator 4 FPGA"},
707 {0x4400, "Chelsio T440-dbg"},
708 {0x4401, "Chelsio T420-CR"},
709 {0x4402, "Chelsio T422-CR"},
710 {0x4403, "Chelsio T440-CR"},
711 {0x4404, "Chelsio T420-BCH"},
712 {0x4405, "Chelsio T440-BCH"},
713 {0x4406, "Chelsio T440-CH"},
714 {0x4407, "Chelsio T420-SO"},
715 {0x4408, "Chelsio T420-CX"},
716 {0x4409, "Chelsio T420-BT"},
717 {0x440a, "Chelsio T404-BT"},
718 {0x440e, "Chelsio T440-LP-CR"},
720 {0xb000, "Chelsio Terminator 5 FPGA"},
721 {0x5400, "Chelsio T580-dbg"},
722 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
723 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
724 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
725 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
726 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
727 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
728 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
729 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
730 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
731 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
732 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
733 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
734 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
735 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
736 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
737 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
738 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
741 {0x5483, "Custom T540-CR"},
742 {0x5484, "Custom T540-BT"},
744 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
745 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
746 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
747 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
748 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
749 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
750 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
751 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
752 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
753 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
754 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
755 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
756 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
757 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
758 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
759 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
762 {0x6480, "Custom T6225-CR"},
763 {0x6481, "Custom T62100-CR"},
764 {0x6482, "Custom T6225-CR"},
765 {0x6483, "Custom T62100-CR"},
766 {0x6484, "Custom T64100-CR"},
767 {0x6485, "Custom T6240-SO"},
768 {0x6486, "Custom T6225-SO-CR"},
769 {0x6487, "Custom T6225-CR"},
774 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
775 * be exactly the same for both rxq and ofld_rxq.
777 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
778 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
780 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
783 t4_probe(device_t dev)
786 uint16_t v = pci_get_vendor(dev);
787 uint16_t d = pci_get_device(dev);
788 uint8_t f = pci_get_function(dev);
790 if (v != PCI_VENDOR_ID_CHELSIO)
793 /* Attach only to PF0 of the FPGA */
794 if (d == 0xa000 && f != 0)
797 for (i = 0; i < nitems(t4_pciids); i++) {
798 if (d == t4_pciids[i].device) {
799 device_set_desc(dev, t4_pciids[i].desc);
800 return (BUS_PROBE_DEFAULT);
808 t5_probe(device_t dev)
811 uint16_t v = pci_get_vendor(dev);
812 uint16_t d = pci_get_device(dev);
813 uint8_t f = pci_get_function(dev);
815 if (v != PCI_VENDOR_ID_CHELSIO)
818 /* Attach only to PF0 of the FPGA */
819 if (d == 0xb000 && f != 0)
822 for (i = 0; i < nitems(t5_pciids); i++) {
823 if (d == t5_pciids[i].device) {
824 device_set_desc(dev, t5_pciids[i].desc);
825 return (BUS_PROBE_DEFAULT);
833 t6_probe(device_t dev)
836 uint16_t v = pci_get_vendor(dev);
837 uint16_t d = pci_get_device(dev);
839 if (v != PCI_VENDOR_ID_CHELSIO)
842 for (i = 0; i < nitems(t6_pciids); i++) {
843 if (d == t6_pciids[i].device) {
844 device_set_desc(dev, t6_pciids[i].desc);
845 return (BUS_PROBE_DEFAULT);
853 t5_attribute_workaround(device_t dev)
859 * The T5 chips do not properly echo the No Snoop and Relaxed
860 * Ordering attributes when replying to a TLP from a Root
861 * Port. As a workaround, find the parent Root Port and
862 * disable No Snoop and Relaxed Ordering. Note that this
863 * affects all devices under this root port.
865 root_port = pci_find_pcie_root_port(dev);
866 if (root_port == NULL) {
867 device_printf(dev, "Unable to find parent root port\n");
871 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
872 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
873 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
875 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
876 device_get_nameunit(root_port));
879 static const struct devnames devnames[] = {
881 .nexus_name = "t4nex",
882 .ifnet_name = "cxgbe",
883 .vi_ifnet_name = "vcxgbe",
884 .pf03_drv_name = "t4iov",
885 .vf_nexus_name = "t4vf",
886 .vf_ifnet_name = "cxgbev"
888 .nexus_name = "t5nex",
890 .vi_ifnet_name = "vcxl",
891 .pf03_drv_name = "t5iov",
892 .vf_nexus_name = "t5vf",
893 .vf_ifnet_name = "cxlv"
895 .nexus_name = "t6nex",
897 .vi_ifnet_name = "vcc",
898 .pf03_drv_name = "t6iov",
899 .vf_nexus_name = "t6vf",
900 .vf_ifnet_name = "ccv"
905 t4_init_devnames(struct adapter *sc)
910 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
911 sc->names = &devnames[id - CHELSIO_T4];
913 device_printf(sc->dev, "chip id %d is not supported.\n", id);
919 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
921 const char *parent, *name;
926 parent = device_get_nameunit(sc->dev);
927 name = sc->names->ifnet_name;
928 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
929 if (resource_long_value(name, unit, "port", &value) == 0 &&
930 value == pi->port_id)
937 t4_attach(device_t dev)
940 int rc = 0, i, j, rqidx, tqidx, nports;
941 struct make_dev_args mda;
942 struct intrs_and_queues iaq;
945 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
952 int nm_rqidx, nm_tqidx;
956 sc = device_get_softc(dev);
958 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
960 if ((pci_get_device(dev) & 0xff00) == 0x5400)
961 t5_attribute_workaround(dev);
962 pci_enable_busmaster(dev);
963 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
966 pci_set_max_read_req(dev, 4096);
967 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
968 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
969 if (pcie_relaxed_ordering == 0 &&
970 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
971 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
972 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
973 } else if (pcie_relaxed_ordering == 1 &&
974 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
975 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
976 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
980 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
981 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
983 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
984 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
985 device_get_nameunit(dev));
987 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
988 device_get_nameunit(dev));
989 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
992 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
993 TAILQ_INIT(&sc->sfl);
994 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
996 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
999 rw_init(&sc->policy_lock, "connection offload policy");
1001 rc = t4_map_bars_0_and_4(sc);
1003 goto done; /* error message displayed already */
1005 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1007 /* Prepare the adapter for operation. */
1008 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1009 rc = -t4_prep_adapter(sc, buf);
1012 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1017 * This is the real PF# to which we're attaching. Works from within PCI
1018 * passthrough environments too, where pci_get_function() could return a
1019 * different PF# depending on the passthrough configuration. We need to
1020 * use the real PF# in all our communication with the firmware.
1022 j = t4_read_reg(sc, A_PL_WHOAMI);
1023 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1026 t4_init_devnames(sc);
1027 if (sc->names == NULL) {
1029 goto done; /* error message displayed already */
1033 * Do this really early, with the memory windows set up even before the
1034 * character device. The userland tool's register i/o and mem read
1035 * will work even in "recovery mode".
1038 if (t4_init_devlog_params(sc, 0) == 0)
1039 fixup_devlog_params(sc);
1040 make_dev_args_init(&mda);
1041 mda.mda_devsw = &t4_cdevsw;
1042 mda.mda_uid = UID_ROOT;
1043 mda.mda_gid = GID_WHEEL;
1044 mda.mda_mode = 0600;
1045 mda.mda_si_drv1 = sc;
1046 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1048 device_printf(dev, "failed to create nexus char device: %d.\n",
1051 /* Go no further if recovery mode has been requested. */
1052 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1053 device_printf(dev, "recovery mode.\n");
1057 #if defined(__i386__)
1058 if ((cpu_feature & CPUID_CX8) == 0) {
1059 device_printf(dev, "64 bit atomics not available.\n");
1065 /* Contact the firmware and try to become the master driver. */
1066 rc = contact_firmware(sc);
1068 goto done; /* error message displayed already */
1069 MPASS(sc->flags & FW_OK);
1071 rc = get_params__pre_init(sc);
1073 goto done; /* error message displayed already */
1075 if (sc->flags & MASTER_PF) {
1076 rc = partition_resources(sc);
1078 goto done; /* error message displayed already */
1082 rc = get_params__post_init(sc);
1084 goto done; /* error message displayed already */
1086 rc = set_params__post_init(sc);
1088 goto done; /* error message displayed already */
1090 rc = t4_map_bar_2(sc);
1092 goto done; /* error message displayed already */
1094 rc = t4_create_dma_tag(sc);
1096 goto done; /* error message displayed already */
1099 * First pass over all the ports - allocate VIs and initialize some
1100 * basic parameters like mac address, port type, etc.
1102 for_each_port(sc, i) {
1103 struct port_info *pi;
1105 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1108 /* These must be set before t4_port_init */
1112 * XXX: vi[0] is special so we can't delay this allocation until
1113 * pi->nvi's final value is known.
1115 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1119 * Allocate the "main" VI and initialize parameters
1122 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1124 device_printf(dev, "unable to initialize port %d: %d\n",
1126 free(pi->vi, M_CXGBE);
1132 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1133 device_get_nameunit(dev), i);
1134 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1135 sc->chan_map[pi->tx_chan] = i;
1137 /* All VIs on this port share this media. */
1138 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1139 cxgbe_media_status);
1142 init_link_config(pi);
1143 fixup_link_config(pi);
1144 build_medialist(pi);
1145 if (fixed_ifmedia(pi))
1146 pi->flags |= FIXED_IFMEDIA;
1149 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1150 t4_ifnet_unit(sc, pi));
1151 if (pi->dev == NULL) {
1153 "failed to add device for port %d.\n", i);
1157 pi->vi[0].dev = pi->dev;
1158 device_set_softc(pi->dev, pi);
1162 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1164 nports = sc->params.nports;
1165 rc = cfg_itype_and_nqueues(sc, &iaq);
1167 goto done; /* error message displayed already */
1169 num_vis = iaq.num_vis;
1170 sc->intr_type = iaq.intr_type;
1171 sc->intr_count = iaq.nirq;
1174 s->nrxq = nports * iaq.nrxq;
1175 s->ntxq = nports * iaq.ntxq;
1177 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1178 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1180 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1181 s->neq += nports; /* ctrl queues: 1 per port */
1182 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1183 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1184 if (is_offload(sc) || is_ethoffload(sc)) {
1185 s->nofldtxq = nports * iaq.nofldtxq;
1187 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1188 s->neq += s->nofldtxq;
1190 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1191 M_CXGBE, M_ZERO | M_WAITOK);
1195 if (is_offload(sc)) {
1196 s->nofldrxq = nports * iaq.nofldrxq;
1198 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1199 s->neq += s->nofldrxq; /* free list */
1200 s->niq += s->nofldrxq;
1202 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1203 M_CXGBE, M_ZERO | M_WAITOK);
1208 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1209 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1211 s->neq += s->nnmtxq + s->nnmrxq;
1212 s->niq += s->nnmrxq;
1214 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1215 M_CXGBE, M_ZERO | M_WAITOK);
1216 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1217 M_CXGBE, M_ZERO | M_WAITOK);
1220 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1222 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1224 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1226 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1228 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1231 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1234 t4_init_l2t(sc, M_WAITOK);
1235 t4_init_smt(sc, M_WAITOK);
1236 t4_init_tx_sched(sc);
1238 t4_init_etid_table(sc);
1241 t4_init_clip_table(sc);
1243 if (sc->vres.key.size != 0)
1244 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1245 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1248 * Second pass over the ports. This time we know the number of rx and
1249 * tx queues that each port should get.
1252 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1259 nm_rqidx = nm_tqidx = 0;
1261 for_each_port(sc, i) {
1262 struct port_info *pi = sc->port[i];
1269 for_each_vi(pi, j, vi) {
1271 vi->qsize_rxq = t4_qsize_rxq;
1272 vi->qsize_txq = t4_qsize_txq;
1274 vi->first_rxq = rqidx;
1275 vi->first_txq = tqidx;
1276 vi->tmr_idx = t4_tmr_idx;
1277 vi->pktc_idx = t4_pktc_idx;
1278 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1279 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1284 if (j == 0 && vi->ntxq > 1)
1285 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1287 vi->rsrv_noflowq = 0;
1289 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1290 vi->first_ofld_txq = ofld_tqidx;
1291 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1292 ofld_tqidx += vi->nofldtxq;
1295 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1296 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1297 vi->first_ofld_rxq = ofld_rqidx;
1298 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1300 ofld_rqidx += vi->nofldrxq;
1304 vi->first_nm_rxq = nm_rqidx;
1305 vi->first_nm_txq = nm_tqidx;
1306 vi->nnmrxq = iaq.nnmrxq_vi;
1307 vi->nnmtxq = iaq.nnmtxq_vi;
1308 nm_rqidx += vi->nnmrxq;
1309 nm_tqidx += vi->nnmtxq;
1315 rc = t4_setup_intr_handlers(sc);
1318 "failed to setup interrupt handlers: %d\n", rc);
1322 rc = bus_generic_probe(dev);
1324 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1329 * Ensure thread-safe mailbox access (in debug builds).
1331 * So far this was the only thread accessing the mailbox but various
1332 * ifnets and sysctls are about to be created and their handlers/ioctls
1333 * will access the mailbox from different threads.
1335 sc->flags |= CHK_MBOX_ACCESS;
1337 rc = bus_generic_attach(dev);
1340 "failed to attach all child ports: %d\n", rc);
1345 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1346 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1347 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1348 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1349 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1353 notify_siblings(dev, 0);
1356 if (rc != 0 && sc->cdev) {
1357 /* cdev was created and so cxgbetool works; recover that way. */
1359 "error during attach, adapter is now in recovery mode.\n");
1364 t4_detach_common(dev);
1372 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1374 struct port_info *pi;
1376 pi = device_get_softc(dev);
1377 snprintf(buf, buflen, "port=%d", pi->port_id);
1382 t4_ready(device_t dev)
1386 sc = device_get_softc(dev);
1387 if (sc->flags & FW_OK)
1393 t4_read_port_device(device_t dev, int port, device_t *child)
1396 struct port_info *pi;
1398 sc = device_get_softc(dev);
1399 if (port < 0 || port >= MAX_NPORTS)
1401 pi = sc->port[port];
1402 if (pi == NULL || pi->dev == NULL)
1409 notify_siblings(device_t dev, int detaching)
1415 for (i = 0; i < PCI_FUNCMAX; i++) {
1416 if (i == pci_get_function(dev))
1418 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1419 pci_get_slot(dev), i);
1420 if (sibling == NULL || !device_is_attached(sibling))
1423 error = T4_DETACH_CHILD(sibling);
1425 (void)T4_ATTACH_CHILD(sibling);
1436 t4_detach(device_t dev)
1441 sc = device_get_softc(dev);
1443 rc = notify_siblings(dev, 1);
1446 "failed to detach sibling devices: %d\n", rc);
1450 return (t4_detach_common(dev));
1454 t4_detach_common(device_t dev)
1457 struct port_info *pi;
1460 sc = device_get_softc(dev);
1463 destroy_dev(sc->cdev);
1467 sc->flags &= ~CHK_MBOX_ACCESS;
1468 if (sc->flags & FULL_INIT_DONE) {
1469 if (!(sc->flags & IS_VF))
1470 t4_intr_disable(sc);
1473 if (device_is_attached(dev)) {
1474 rc = bus_generic_detach(dev);
1477 "failed to detach child devices: %d\n", rc);
1482 for (i = 0; i < sc->intr_count; i++)
1483 t4_free_irq(sc, &sc->irq[i]);
1485 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1486 t4_free_tx_sched(sc);
1488 for (i = 0; i < MAX_NPORTS; i++) {
1491 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1493 device_delete_child(dev, pi->dev);
1495 mtx_destroy(&pi->pi_lock);
1496 free(pi->vi, M_CXGBE);
1501 device_delete_children(dev);
1503 if (sc->flags & FULL_INIT_DONE)
1504 adapter_full_uninit(sc);
1506 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1507 t4_fw_bye(sc, sc->mbox);
1509 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1510 pci_release_msi(dev);
1513 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1517 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1521 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1525 t4_free_l2t(sc->l2t);
1527 t4_free_smt(sc->smt);
1529 t4_free_etid_table(sc);
1532 vmem_destroy(sc->key_map);
1534 t4_destroy_clip_table(sc);
1537 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1538 free(sc->sge.ofld_txq, M_CXGBE);
1541 free(sc->sge.ofld_rxq, M_CXGBE);
1544 free(sc->sge.nm_rxq, M_CXGBE);
1545 free(sc->sge.nm_txq, M_CXGBE);
1547 free(sc->irq, M_CXGBE);
1548 free(sc->sge.rxq, M_CXGBE);
1549 free(sc->sge.txq, M_CXGBE);
1550 free(sc->sge.ctrlq, M_CXGBE);
1551 free(sc->sge.iqmap, M_CXGBE);
1552 free(sc->sge.eqmap, M_CXGBE);
1553 free(sc->tids.ftid_tab, M_CXGBE);
1554 free(sc->tids.hpftid_tab, M_CXGBE);
1555 free_hftid_hash(&sc->tids);
1556 free(sc->tids.atid_tab, M_CXGBE);
1557 free(sc->tids.tid_tab, M_CXGBE);
1558 free(sc->tt.tls_rx_ports, M_CXGBE);
1559 t4_destroy_dma_tag(sc);
1560 if (mtx_initialized(&sc->sc_lock)) {
1561 sx_xlock(&t4_list_lock);
1562 SLIST_REMOVE(&t4_list, sc, adapter, link);
1563 sx_xunlock(&t4_list_lock);
1564 mtx_destroy(&sc->sc_lock);
1567 callout_drain(&sc->sfl_callout);
1568 if (mtx_initialized(&sc->tids.ftid_lock)) {
1569 mtx_destroy(&sc->tids.ftid_lock);
1570 cv_destroy(&sc->tids.ftid_cv);
1572 if (mtx_initialized(&sc->tids.atid_lock))
1573 mtx_destroy(&sc->tids.atid_lock);
1574 if (mtx_initialized(&sc->sfl_lock))
1575 mtx_destroy(&sc->sfl_lock);
1576 if (mtx_initialized(&sc->ifp_lock))
1577 mtx_destroy(&sc->ifp_lock);
1578 if (mtx_initialized(&sc->reg_lock))
1579 mtx_destroy(&sc->reg_lock);
1581 if (rw_initialized(&sc->policy_lock)) {
1582 rw_destroy(&sc->policy_lock);
1584 if (sc->policy != NULL)
1585 free_offload_policy(sc->policy);
1589 for (i = 0; i < NUM_MEMWIN; i++) {
1590 struct memwin *mw = &sc->memwin[i];
1592 if (rw_initialized(&mw->mw_lock))
1593 rw_destroy(&mw->mw_lock);
1596 bzero(sc, sizeof(*sc));
1602 cxgbe_probe(device_t dev)
1605 struct port_info *pi = device_get_softc(dev);
1607 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1608 device_set_desc_copy(dev, buf);
1610 return (BUS_PROBE_DEFAULT);
1613 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1614 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1615 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1617 #define T4_CAP_ENABLE (T4_CAP)
1620 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1625 vi->xact_addr_filt = -1;
1626 callout_init(&vi->tick, 1);
1628 /* Allocate an ifnet and set it up */
1629 ifp = if_alloc(IFT_ETHER);
1631 device_printf(dev, "Cannot allocate ifnet\n");
1637 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1640 ifp->if_init = cxgbe_init;
1641 ifp->if_ioctl = cxgbe_ioctl;
1642 ifp->if_transmit = cxgbe_transmit;
1643 ifp->if_qflush = cxgbe_qflush;
1644 ifp->if_get_counter = cxgbe_get_counter;
1646 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1647 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1648 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1649 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1652 ifp->if_capabilities = T4_CAP;
1653 ifp->if_capenable = T4_CAP_ENABLE;
1655 if (vi->nofldrxq != 0)
1656 ifp->if_capabilities |= IFCAP_TOE;
1659 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1660 ifp->if_capabilities |= IFCAP_TXRTLMT;
1661 ifp->if_capenable |= IFCAP_TXRTLMT;
1664 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1665 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1667 ifp->if_hw_tsomax = IP_MAXPACKET;
1668 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1670 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1671 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1673 ifp->if_hw_tsomaxsegsize = 65536;
1675 ether_ifattach(ifp, vi->hw_addr);
1677 if (vi->nnmrxq != 0)
1678 cxgbe_nm_attach(vi);
1680 sb = sbuf_new_auto();
1681 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1682 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1683 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1685 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1687 case IFCAP_TOE | IFCAP_TXRTLMT:
1688 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1691 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1696 if (ifp->if_capabilities & IFCAP_TOE)
1697 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1700 if (ifp->if_capabilities & IFCAP_NETMAP)
1701 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1702 vi->nnmtxq, vi->nnmrxq);
1705 device_printf(dev, "%s\n", sbuf_data(sb));
1714 cxgbe_attach(device_t dev)
1716 struct port_info *pi = device_get_softc(dev);
1717 struct adapter *sc = pi->adapter;
1721 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1723 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1727 for_each_vi(pi, i, vi) {
1730 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1731 if (vi->dev == NULL) {
1732 device_printf(dev, "failed to add VI %d\n", i);
1735 device_set_softc(vi->dev, vi);
1740 bus_generic_attach(dev);
1746 cxgbe_vi_detach(struct vi_info *vi)
1748 struct ifnet *ifp = vi->ifp;
1750 ether_ifdetach(ifp);
1752 /* Let detach proceed even if these fail. */
1754 if (ifp->if_capabilities & IFCAP_NETMAP)
1755 cxgbe_nm_detach(vi);
1757 cxgbe_uninit_synchronized(vi);
1758 callout_drain(&vi->tick);
1766 cxgbe_detach(device_t dev)
1768 struct port_info *pi = device_get_softc(dev);
1769 struct adapter *sc = pi->adapter;
1772 /* Detach the extra VIs first. */
1773 rc = bus_generic_detach(dev);
1776 device_delete_children(dev);
1778 doom_vi(sc, &pi->vi[0]);
1780 if (pi->flags & HAS_TRACEQ) {
1781 sc->traceq = -1; /* cloner should not create ifnet */
1782 t4_tracer_port_detach(sc);
1785 cxgbe_vi_detach(&pi->vi[0]);
1786 callout_drain(&pi->tick);
1787 ifmedia_removeall(&pi->media);
1789 end_synchronized_op(sc, 0);
1795 cxgbe_init(void *arg)
1797 struct vi_info *vi = arg;
1798 struct adapter *sc = vi->pi->adapter;
1800 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1802 cxgbe_init_synchronized(vi);
1803 end_synchronized_op(sc, 0);
1807 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1809 int rc = 0, mtu, flags;
1810 struct vi_info *vi = ifp->if_softc;
1811 struct port_info *pi = vi->pi;
1812 struct adapter *sc = pi->adapter;
1813 struct ifreq *ifr = (struct ifreq *)data;
1819 if (mtu < ETHERMIN || mtu > MAX_MTU)
1822 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1826 if (vi->flags & VI_INIT_DONE) {
1827 t4_update_fl_bufsize(ifp);
1828 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1829 rc = update_mac_settings(ifp, XGMAC_MTU);
1831 end_synchronized_op(sc, 0);
1835 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1839 if (ifp->if_flags & IFF_UP) {
1840 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1841 flags = vi->if_flags;
1842 if ((ifp->if_flags ^ flags) &
1843 (IFF_PROMISC | IFF_ALLMULTI)) {
1844 rc = update_mac_settings(ifp,
1845 XGMAC_PROMISC | XGMAC_ALLMULTI);
1848 rc = cxgbe_init_synchronized(vi);
1850 vi->if_flags = ifp->if_flags;
1851 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1852 rc = cxgbe_uninit_synchronized(vi);
1854 end_synchronized_op(sc, 0);
1859 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1862 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1863 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1864 end_synchronized_op(sc, 0);
1868 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1872 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1873 if (mask & IFCAP_TXCSUM) {
1874 ifp->if_capenable ^= IFCAP_TXCSUM;
1875 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1877 if (IFCAP_TSO4 & ifp->if_capenable &&
1878 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1879 ifp->if_capenable &= ~IFCAP_TSO4;
1881 "tso4 disabled due to -txcsum.\n");
1884 if (mask & IFCAP_TXCSUM_IPV6) {
1885 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1886 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1888 if (IFCAP_TSO6 & ifp->if_capenable &&
1889 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1890 ifp->if_capenable &= ~IFCAP_TSO6;
1892 "tso6 disabled due to -txcsum6.\n");
1895 if (mask & IFCAP_RXCSUM)
1896 ifp->if_capenable ^= IFCAP_RXCSUM;
1897 if (mask & IFCAP_RXCSUM_IPV6)
1898 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1901 * Note that we leave CSUM_TSO alone (it is always set). The
1902 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1903 * sending a TSO request our way, so it's sufficient to toggle
1906 if (mask & IFCAP_TSO4) {
1907 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1908 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1909 if_printf(ifp, "enable txcsum first.\n");
1913 ifp->if_capenable ^= IFCAP_TSO4;
1915 if (mask & IFCAP_TSO6) {
1916 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1917 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1918 if_printf(ifp, "enable txcsum6 first.\n");
1922 ifp->if_capenable ^= IFCAP_TSO6;
1924 if (mask & IFCAP_LRO) {
1925 #if defined(INET) || defined(INET6)
1927 struct sge_rxq *rxq;
1929 ifp->if_capenable ^= IFCAP_LRO;
1930 for_each_rxq(vi, i, rxq) {
1931 if (ifp->if_capenable & IFCAP_LRO)
1932 rxq->iq.flags |= IQ_LRO_ENABLED;
1934 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1939 if (mask & IFCAP_TOE) {
1940 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1942 rc = toe_capability(vi, enable);
1946 ifp->if_capenable ^= mask;
1949 if (mask & IFCAP_VLAN_HWTAGGING) {
1950 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1951 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1952 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1954 if (mask & IFCAP_VLAN_MTU) {
1955 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1957 /* Need to find out how to disable auto-mtu-inflation */
1959 if (mask & IFCAP_VLAN_HWTSO)
1960 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1961 if (mask & IFCAP_VLAN_HWCSUM)
1962 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1964 if (mask & IFCAP_TXRTLMT)
1965 ifp->if_capenable ^= IFCAP_TXRTLMT;
1967 if (mask & IFCAP_HWRXTSTMP) {
1969 struct sge_rxq *rxq;
1971 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
1972 for_each_rxq(vi, i, rxq) {
1973 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
1974 rxq->iq.flags |= IQ_RX_TIMESTAMP;
1976 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
1980 #ifdef VLAN_CAPABILITIES
1981 VLAN_CAPABILITIES(ifp);
1984 end_synchronized_op(sc, 0);
1990 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1994 struct ifi2creq i2c;
1996 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
1999 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2003 if (i2c.len > sizeof(i2c.data)) {
2007 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2010 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2011 i2c.offset, i2c.len, &i2c.data[0]);
2012 end_synchronized_op(sc, 0);
2014 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2019 rc = ether_ioctl(ifp, cmd, data);
2026 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2028 struct vi_info *vi = ifp->if_softc;
2029 struct port_info *pi = vi->pi;
2030 struct adapter *sc = pi->adapter;
2031 struct sge_txq *txq;
2036 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2038 if (__predict_false(pi->link_cfg.link_ok == false)) {
2043 rc = parse_pkt(sc, &m);
2044 if (__predict_false(rc != 0)) {
2045 MPASS(m == NULL); /* was freed already */
2046 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2050 if (m->m_pkthdr.snd_tag != NULL) {
2051 /* EAGAIN tells the stack we are not the correct interface. */
2052 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) {
2057 return (ethofld_transmit(ifp, m));
2062 txq = &sc->sge.txq[vi->first_txq];
2063 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2064 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2068 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2069 if (__predict_false(rc != 0))
2076 cxgbe_qflush(struct ifnet *ifp)
2078 struct vi_info *vi = ifp->if_softc;
2079 struct sge_txq *txq;
2082 /* queues do not exist if !VI_INIT_DONE. */
2083 if (vi->flags & VI_INIT_DONE) {
2084 for_each_txq(vi, i, txq) {
2086 txq->eq.flags |= EQ_QFLUSH;
2088 while (!mp_ring_is_idle(txq->r)) {
2089 mp_ring_check_drainage(txq->r, 0);
2093 txq->eq.flags &= ~EQ_QFLUSH;
2101 vi_get_counter(struct ifnet *ifp, ift_counter c)
2103 struct vi_info *vi = ifp->if_softc;
2104 struct fw_vi_stats_vf *s = &vi->stats;
2106 vi_refresh_stats(vi->pi->adapter, vi);
2109 case IFCOUNTER_IPACKETS:
2110 return (s->rx_bcast_frames + s->rx_mcast_frames +
2111 s->rx_ucast_frames);
2112 case IFCOUNTER_IERRORS:
2113 return (s->rx_err_frames);
2114 case IFCOUNTER_OPACKETS:
2115 return (s->tx_bcast_frames + s->tx_mcast_frames +
2116 s->tx_ucast_frames + s->tx_offload_frames);
2117 case IFCOUNTER_OERRORS:
2118 return (s->tx_drop_frames);
2119 case IFCOUNTER_IBYTES:
2120 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2122 case IFCOUNTER_OBYTES:
2123 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2124 s->tx_ucast_bytes + s->tx_offload_bytes);
2125 case IFCOUNTER_IMCASTS:
2126 return (s->rx_mcast_frames);
2127 case IFCOUNTER_OMCASTS:
2128 return (s->tx_mcast_frames);
2129 case IFCOUNTER_OQDROPS: {
2133 if (vi->flags & VI_INIT_DONE) {
2135 struct sge_txq *txq;
2137 for_each_txq(vi, i, txq)
2138 drops += counter_u64_fetch(txq->r->drops);
2146 return (if_get_counter_default(ifp, c));
2151 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2153 struct vi_info *vi = ifp->if_softc;
2154 struct port_info *pi = vi->pi;
2155 struct adapter *sc = pi->adapter;
2156 struct port_stats *s = &pi->stats;
2158 if (pi->nvi > 1 || sc->flags & IS_VF)
2159 return (vi_get_counter(ifp, c));
2161 cxgbe_refresh_stats(sc, pi);
2164 case IFCOUNTER_IPACKETS:
2165 return (s->rx_frames);
2167 case IFCOUNTER_IERRORS:
2168 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2169 s->rx_fcs_err + s->rx_len_err);
2171 case IFCOUNTER_OPACKETS:
2172 return (s->tx_frames);
2174 case IFCOUNTER_OERRORS:
2175 return (s->tx_error_frames);
2177 case IFCOUNTER_IBYTES:
2178 return (s->rx_octets);
2180 case IFCOUNTER_OBYTES:
2181 return (s->tx_octets);
2183 case IFCOUNTER_IMCASTS:
2184 return (s->rx_mcast_frames);
2186 case IFCOUNTER_OMCASTS:
2187 return (s->tx_mcast_frames);
2189 case IFCOUNTER_IQDROPS:
2190 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2191 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2192 s->rx_trunc3 + pi->tnl_cong_drops);
2194 case IFCOUNTER_OQDROPS: {
2198 if (vi->flags & VI_INIT_DONE) {
2200 struct sge_txq *txq;
2202 for_each_txq(vi, i, txq)
2203 drops += counter_u64_fetch(txq->r->drops);
2211 return (if_get_counter_default(ifp, c));
2216 * The kernel picks a media from the list we had provided but we still validate
2220 cxgbe_media_change(struct ifnet *ifp)
2222 struct vi_info *vi = ifp->if_softc;
2223 struct port_info *pi = vi->pi;
2224 struct ifmedia *ifm = &pi->media;
2225 struct link_config *lc = &pi->link_cfg;
2226 struct adapter *sc = pi->adapter;
2229 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2233 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2234 /* ifconfig .. media autoselect */
2235 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2236 rc = ENOTSUP; /* AN not supported by transceiver */
2239 lc->requested_aneg = AUTONEG_ENABLE;
2240 lc->requested_speed = 0;
2241 lc->requested_fc |= PAUSE_AUTONEG;
2243 lc->requested_aneg = AUTONEG_DISABLE;
2244 lc->requested_speed =
2245 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2246 lc->requested_fc = 0;
2247 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2248 lc->requested_fc |= PAUSE_RX;
2249 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2250 lc->requested_fc |= PAUSE_TX;
2252 if (pi->up_vis > 0) {
2253 fixup_link_config(pi);
2254 rc = apply_link_config(pi);
2258 end_synchronized_op(sc, 0);
2263 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2267 port_mword(struct port_info *pi, uint32_t speed)
2270 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2271 MPASS(powerof2(speed));
2273 switch(pi->port_type) {
2274 case FW_PORT_TYPE_BT_SGMII:
2275 case FW_PORT_TYPE_BT_XFI:
2276 case FW_PORT_TYPE_BT_XAUI:
2279 case FW_PORT_CAP32_SPEED_100M:
2281 case FW_PORT_CAP32_SPEED_1G:
2282 return (IFM_1000_T);
2283 case FW_PORT_CAP32_SPEED_10G:
2287 case FW_PORT_TYPE_KX4:
2288 if (speed == FW_PORT_CAP32_SPEED_10G)
2289 return (IFM_10G_KX4);
2291 case FW_PORT_TYPE_CX4:
2292 if (speed == FW_PORT_CAP32_SPEED_10G)
2293 return (IFM_10G_CX4);
2295 case FW_PORT_TYPE_KX:
2296 if (speed == FW_PORT_CAP32_SPEED_1G)
2297 return (IFM_1000_KX);
2299 case FW_PORT_TYPE_KR:
2300 case FW_PORT_TYPE_BP_AP:
2301 case FW_PORT_TYPE_BP4_AP:
2302 case FW_PORT_TYPE_BP40_BA:
2303 case FW_PORT_TYPE_KR4_100G:
2304 case FW_PORT_TYPE_KR_SFP28:
2305 case FW_PORT_TYPE_KR_XLAUI:
2307 case FW_PORT_CAP32_SPEED_1G:
2308 return (IFM_1000_KX);
2309 case FW_PORT_CAP32_SPEED_10G:
2310 return (IFM_10G_KR);
2311 case FW_PORT_CAP32_SPEED_25G:
2312 return (IFM_25G_KR);
2313 case FW_PORT_CAP32_SPEED_40G:
2314 return (IFM_40G_KR4);
2315 case FW_PORT_CAP32_SPEED_50G:
2316 return (IFM_50G_KR2);
2317 case FW_PORT_CAP32_SPEED_100G:
2318 return (IFM_100G_KR4);
2321 case FW_PORT_TYPE_FIBER_XFI:
2322 case FW_PORT_TYPE_FIBER_XAUI:
2323 case FW_PORT_TYPE_SFP:
2324 case FW_PORT_TYPE_QSFP_10G:
2325 case FW_PORT_TYPE_QSA:
2326 case FW_PORT_TYPE_QSFP:
2327 case FW_PORT_TYPE_CR4_QSFP:
2328 case FW_PORT_TYPE_CR_QSFP:
2329 case FW_PORT_TYPE_CR2_QSFP:
2330 case FW_PORT_TYPE_SFP28:
2331 /* Pluggable transceiver */
2332 switch (pi->mod_type) {
2333 case FW_PORT_MOD_TYPE_LR:
2335 case FW_PORT_CAP32_SPEED_1G:
2336 return (IFM_1000_LX);
2337 case FW_PORT_CAP32_SPEED_10G:
2338 return (IFM_10G_LR);
2339 case FW_PORT_CAP32_SPEED_25G:
2340 return (IFM_25G_LR);
2341 case FW_PORT_CAP32_SPEED_40G:
2342 return (IFM_40G_LR4);
2343 case FW_PORT_CAP32_SPEED_50G:
2344 return (IFM_50G_LR2);
2345 case FW_PORT_CAP32_SPEED_100G:
2346 return (IFM_100G_LR4);
2349 case FW_PORT_MOD_TYPE_SR:
2351 case FW_PORT_CAP32_SPEED_1G:
2352 return (IFM_1000_SX);
2353 case FW_PORT_CAP32_SPEED_10G:
2354 return (IFM_10G_SR);
2355 case FW_PORT_CAP32_SPEED_25G:
2356 return (IFM_25G_SR);
2357 case FW_PORT_CAP32_SPEED_40G:
2358 return (IFM_40G_SR4);
2359 case FW_PORT_CAP32_SPEED_50G:
2360 return (IFM_50G_SR2);
2361 case FW_PORT_CAP32_SPEED_100G:
2362 return (IFM_100G_SR4);
2365 case FW_PORT_MOD_TYPE_ER:
2366 if (speed == FW_PORT_CAP32_SPEED_10G)
2367 return (IFM_10G_ER);
2369 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2370 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2372 case FW_PORT_CAP32_SPEED_1G:
2373 return (IFM_1000_CX);
2374 case FW_PORT_CAP32_SPEED_10G:
2375 return (IFM_10G_TWINAX);
2376 case FW_PORT_CAP32_SPEED_25G:
2377 return (IFM_25G_CR);
2378 case FW_PORT_CAP32_SPEED_40G:
2379 return (IFM_40G_CR4);
2380 case FW_PORT_CAP32_SPEED_50G:
2381 return (IFM_50G_CR2);
2382 case FW_PORT_CAP32_SPEED_100G:
2383 return (IFM_100G_CR4);
2386 case FW_PORT_MOD_TYPE_LRM:
2387 if (speed == FW_PORT_CAP32_SPEED_10G)
2388 return (IFM_10G_LRM);
2390 case FW_PORT_MOD_TYPE_NA:
2391 MPASS(0); /* Not pluggable? */
2393 case FW_PORT_MOD_TYPE_ERROR:
2394 case FW_PORT_MOD_TYPE_UNKNOWN:
2395 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2397 case FW_PORT_MOD_TYPE_NONE:
2401 case FW_PORT_TYPE_NONE:
2405 return (IFM_UNKNOWN);
2409 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2411 struct vi_info *vi = ifp->if_softc;
2412 struct port_info *pi = vi->pi;
2413 struct adapter *sc = pi->adapter;
2414 struct link_config *lc = &pi->link_cfg;
2416 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2420 if (pi->up_vis == 0) {
2422 * If all the interfaces are administratively down the firmware
2423 * does not report transceiver changes. Refresh port info here
2424 * so that ifconfig displays accurate ifmedia at all times.
2425 * This is the only reason we have a synchronized op in this
2426 * function. Just PORT_LOCK would have been enough otherwise.
2428 t4_update_port_info(pi);
2429 build_medialist(pi);
2433 ifmr->ifm_status = IFM_AVALID;
2434 if (lc->link_ok == false)
2436 ifmr->ifm_status |= IFM_ACTIVE;
2439 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2440 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2441 if (lc->fc & PAUSE_RX)
2442 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2443 if (lc->fc & PAUSE_TX)
2444 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2445 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2448 end_synchronized_op(sc, 0);
2452 vcxgbe_probe(device_t dev)
2455 struct vi_info *vi = device_get_softc(dev);
2457 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2459 device_set_desc_copy(dev, buf);
2461 return (BUS_PROBE_DEFAULT);
2465 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2467 int func, index, rc;
2468 uint32_t param, val;
2470 ASSERT_SYNCHRONIZED_OP(sc);
2472 index = vi - pi->vi;
2473 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2474 KASSERT(index < nitems(vi_mac_funcs),
2475 ("%s: VI %s doesn't have a MAC func", __func__,
2476 device_get_nameunit(vi->dev)));
2477 func = vi_mac_funcs[index];
2478 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2479 vi->hw_addr, &vi->rss_size, func, 0);
2481 device_printf(vi->dev, "failed to allocate virtual interface %d"
2482 "for port %d: %d\n", index, pi->port_id, -rc);
2486 if (chip_id(sc) <= CHELSIO_T5)
2487 vi->smt_idx = (rc & 0x7f) << 1;
2489 vi->smt_idx = (rc & 0x7f);
2491 if (vi->rss_size == 1) {
2493 * This VI didn't get a slice of the RSS table. Reduce the
2494 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2495 * configuration file (nvi, rssnvi for this PF) if this is a
2498 device_printf(vi->dev, "RSS table not available.\n");
2499 vi->rss_base = 0xffff;
2504 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2505 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2506 V_FW_PARAMS_PARAM_YZ(vi->viid);
2507 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2509 vi->rss_base = 0xffff;
2511 MPASS((val >> 16) == vi->rss_size);
2512 vi->rss_base = val & 0xffff;
2519 vcxgbe_attach(device_t dev)
2522 struct port_info *pi;
2526 vi = device_get_softc(dev);
2530 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2533 rc = alloc_extra_vi(sc, pi, vi);
2534 end_synchronized_op(sc, 0);
2538 rc = cxgbe_vi_attach(dev, vi);
2540 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2547 vcxgbe_detach(device_t dev)
2552 vi = device_get_softc(dev);
2553 sc = vi->pi->adapter;
2557 cxgbe_vi_detach(vi);
2558 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2560 end_synchronized_op(sc, 0);
2566 t4_fatal_err(struct adapter *sc, bool fw_error)
2569 t4_shutdown_adapter(sc);
2570 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2571 device_get_nameunit(sc->dev));
2572 if (t4_panic_on_fatal_err)
2573 panic("panic requested on fatal error");
2576 ASSERT_SYNCHRONIZED_OP(sc);
2577 sc->flags |= ADAP_ERR;
2580 sc->flags |= ADAP_ERR;
2586 t4_add_adapter(struct adapter *sc)
2588 sx_xlock(&t4_list_lock);
2589 SLIST_INSERT_HEAD(&t4_list, sc, link);
2590 sx_xunlock(&t4_list_lock);
2594 t4_map_bars_0_and_4(struct adapter *sc)
2596 sc->regs_rid = PCIR_BAR(0);
2597 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2598 &sc->regs_rid, RF_ACTIVE);
2599 if (sc->regs_res == NULL) {
2600 device_printf(sc->dev, "cannot map registers.\n");
2603 sc->bt = rman_get_bustag(sc->regs_res);
2604 sc->bh = rman_get_bushandle(sc->regs_res);
2605 sc->mmio_len = rman_get_size(sc->regs_res);
2606 setbit(&sc->doorbells, DOORBELL_KDB);
2608 sc->msix_rid = PCIR_BAR(4);
2609 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2610 &sc->msix_rid, RF_ACTIVE);
2611 if (sc->msix_res == NULL) {
2612 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2620 t4_map_bar_2(struct adapter *sc)
2624 * T4: only iWARP driver uses the userspace doorbells. There is no need
2625 * to map it if RDMA is disabled.
2627 if (is_t4(sc) && sc->rdmacaps == 0)
2630 sc->udbs_rid = PCIR_BAR(2);
2631 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2632 &sc->udbs_rid, RF_ACTIVE);
2633 if (sc->udbs_res == NULL) {
2634 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2637 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2639 if (chip_id(sc) >= CHELSIO_T5) {
2640 setbit(&sc->doorbells, DOORBELL_UDB);
2641 #if defined(__i386__) || defined(__amd64__)
2642 if (t5_write_combine) {
2646 * Enable write combining on BAR2. This is the
2647 * userspace doorbell BAR and is split into 128B
2648 * (UDBS_SEG_SIZE) doorbell regions, each associated
2649 * with an egress queue. The first 64B has the doorbell
2650 * and the second 64B can be used to submit a tx work
2651 * request with an implicit doorbell.
2654 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2655 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2657 clrbit(&sc->doorbells, DOORBELL_UDB);
2658 setbit(&sc->doorbells, DOORBELL_WCWR);
2659 setbit(&sc->doorbells, DOORBELL_UDBWC);
2661 device_printf(sc->dev,
2662 "couldn't enable write combining: %d\n",
2666 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2667 t4_write_reg(sc, A_SGE_STAT_CFG,
2668 V_STATSOURCE_T5(7) | mode);
2672 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2677 struct memwin_init {
2682 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2683 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2684 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2685 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2688 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2689 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2690 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2691 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2695 setup_memwin(struct adapter *sc)
2697 const struct memwin_init *mw_init;
2704 * Read low 32b of bar0 indirectly via the hardware backdoor
2705 * mechanism. Works from within PCI passthrough environments
2706 * too, where rman_get_start() can return a different value. We
2707 * need to program the T4 memory window decoders with the actual
2708 * addresses that will be coming across the PCIe link.
2710 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2711 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2713 mw_init = &t4_memwin[0];
2715 /* T5+ use the relative offset inside the PCIe BAR */
2718 mw_init = &t5_memwin[0];
2721 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2722 rw_init(&mw->mw_lock, "memory window access");
2723 mw->mw_base = mw_init->base;
2724 mw->mw_aperture = mw_init->aperture;
2727 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2728 (mw->mw_base + bar0) | V_BIR(0) |
2729 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2730 rw_wlock(&mw->mw_lock);
2731 position_memwin(sc, i, 0);
2732 rw_wunlock(&mw->mw_lock);
2736 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2740 * Positions the memory window at the given address in the card's address space.
2741 * There are some alignment requirements and the actual position may be at an
2742 * address prior to the requested address. mw->mw_curpos always has the actual
2743 * position of the window.
2746 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2752 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2753 mw = &sc->memwin[idx];
2754 rw_assert(&mw->mw_lock, RA_WLOCKED);
2758 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2760 pf = V_PFNUM(sc->pf);
2761 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2763 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2764 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2765 t4_read_reg(sc, reg); /* flush */
2769 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2775 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2777 /* Memory can only be accessed in naturally aligned 4 byte units */
2778 if (addr & 3 || len & 3 || len <= 0)
2781 mw = &sc->memwin[idx];
2783 rw_rlock(&mw->mw_lock);
2784 mw_end = mw->mw_curpos + mw->mw_aperture;
2785 if (addr >= mw_end || addr < mw->mw_curpos) {
2786 /* Will need to reposition the window */
2787 if (!rw_try_upgrade(&mw->mw_lock)) {
2788 rw_runlock(&mw->mw_lock);
2789 rw_wlock(&mw->mw_lock);
2791 rw_assert(&mw->mw_lock, RA_WLOCKED);
2792 position_memwin(sc, idx, addr);
2793 rw_downgrade(&mw->mw_lock);
2794 mw_end = mw->mw_curpos + mw->mw_aperture;
2796 rw_assert(&mw->mw_lock, RA_RLOCKED);
2797 while (addr < mw_end && len > 0) {
2799 v = t4_read_reg(sc, mw->mw_base + addr -
2801 *val++ = le32toh(v);
2804 t4_write_reg(sc, mw->mw_base + addr -
2805 mw->mw_curpos, htole32(v));
2810 rw_runlock(&mw->mw_lock);
2817 alloc_atid_tab(struct tid_info *t, int flags)
2821 MPASS(t->natids > 0);
2822 MPASS(t->atid_tab == NULL);
2824 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2826 if (t->atid_tab == NULL)
2828 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2829 t->afree = t->atid_tab;
2830 t->atids_in_use = 0;
2831 for (i = 1; i < t->natids; i++)
2832 t->atid_tab[i - 1].next = &t->atid_tab[i];
2833 t->atid_tab[t->natids - 1].next = NULL;
2839 free_atid_tab(struct tid_info *t)
2842 KASSERT(t->atids_in_use == 0,
2843 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2845 if (mtx_initialized(&t->atid_lock))
2846 mtx_destroy(&t->atid_lock);
2847 free(t->atid_tab, M_CXGBE);
2852 alloc_atid(struct adapter *sc, void *ctx)
2854 struct tid_info *t = &sc->tids;
2857 mtx_lock(&t->atid_lock);
2859 union aopen_entry *p = t->afree;
2861 atid = p - t->atid_tab;
2862 MPASS(atid <= M_TID_TID);
2867 mtx_unlock(&t->atid_lock);
2872 lookup_atid(struct adapter *sc, int atid)
2874 struct tid_info *t = &sc->tids;
2876 return (t->atid_tab[atid].data);
2880 free_atid(struct adapter *sc, int atid)
2882 struct tid_info *t = &sc->tids;
2883 union aopen_entry *p = &t->atid_tab[atid];
2885 mtx_lock(&t->atid_lock);
2889 mtx_unlock(&t->atid_lock);
2893 queue_tid_release(struct adapter *sc, int tid)
2896 CXGBE_UNIMPLEMENTED("deferred tid release");
2900 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
2903 struct cpl_tid_release *req;
2905 wr = alloc_wrqe(sizeof(*req), ctrlq);
2907 queue_tid_release(sc, tid); /* defer */
2912 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
2918 t4_range_cmp(const void *a, const void *b)
2920 return ((const struct t4_range *)a)->start -
2921 ((const struct t4_range *)b)->start;
2925 * Verify that the memory range specified by the addr/len pair is valid within
2926 * the card's address space.
2929 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2931 struct t4_range mem_ranges[4], *r, *next;
2932 uint32_t em, addr_len;
2933 int i, n, remaining;
2935 /* Memory can only be accessed in naturally aligned 4 byte units */
2936 if (addr & 3 || len & 3 || len == 0)
2939 /* Enabled memories */
2940 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2944 bzero(r, sizeof(mem_ranges));
2945 if (em & F_EDRAM0_ENABLE) {
2946 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2947 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2949 r->start = G_EDRAM0_BASE(addr_len) << 20;
2950 if (addr >= r->start &&
2951 addr + len <= r->start + r->size)
2957 if (em & F_EDRAM1_ENABLE) {
2958 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2959 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2961 r->start = G_EDRAM1_BASE(addr_len) << 20;
2962 if (addr >= r->start &&
2963 addr + len <= r->start + r->size)
2969 if (em & F_EXT_MEM_ENABLE) {
2970 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2971 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2973 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2974 if (addr >= r->start &&
2975 addr + len <= r->start + r->size)
2981 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2982 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2983 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2985 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2986 if (addr >= r->start &&
2987 addr + len <= r->start + r->size)
2993 MPASS(n <= nitems(mem_ranges));
2996 /* Sort and merge the ranges. */
2997 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2999 /* Start from index 0 and examine the next n - 1 entries. */
3001 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3003 MPASS(r->size > 0); /* r is a valid entry. */
3005 MPASS(next->size > 0); /* and so is the next one. */
3007 while (r->start + r->size >= next->start) {
3008 /* Merge the next one into the current entry. */
3009 r->size = max(r->start + r->size,
3010 next->start + next->size) - r->start;
3011 n--; /* One fewer entry in total. */
3012 if (--remaining == 0)
3013 goto done; /* short circuit */
3016 if (next != r + 1) {
3018 * Some entries were merged into r and next
3019 * points to the first valid entry that couldn't
3022 MPASS(next->size > 0); /* must be valid */
3023 memcpy(r + 1, next, remaining * sizeof(*r));
3026 * This so that the foo->size assertion in the
3027 * next iteration of the loop do the right
3028 * thing for entries that were pulled up and are
3031 MPASS(n < nitems(mem_ranges));
3032 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3033 sizeof(struct t4_range));
3038 /* Done merging the ranges. */
3041 for (i = 0; i < n; i++, r++) {
3042 if (addr >= r->start &&
3043 addr + len <= r->start + r->size)
3052 fwmtype_to_hwmtype(int mtype)
3056 case FW_MEMTYPE_EDC0:
3058 case FW_MEMTYPE_EDC1:
3060 case FW_MEMTYPE_EXTMEM:
3062 case FW_MEMTYPE_EXTMEM1:
3065 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3070 * Verify that the memory range specified by the memtype/offset/len pair is
3071 * valid and lies entirely within the memtype specified. The global address of
3072 * the start of the range is returned in addr.
3075 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3078 uint32_t em, addr_len, maddr;
3080 /* Memory can only be accessed in naturally aligned 4 byte units */
3081 if (off & 3 || len & 3 || len == 0)
3084 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3085 switch (fwmtype_to_hwmtype(mtype)) {
3087 if (!(em & F_EDRAM0_ENABLE))
3089 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3090 maddr = G_EDRAM0_BASE(addr_len) << 20;
3093 if (!(em & F_EDRAM1_ENABLE))
3095 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3096 maddr = G_EDRAM1_BASE(addr_len) << 20;
3099 if (!(em & F_EXT_MEM_ENABLE))
3101 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3102 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3105 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3107 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3108 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3114 *addr = maddr + off; /* global address */
3115 return (validate_mem_range(sc, *addr, len));
3119 fixup_devlog_params(struct adapter *sc)
3121 struct devlog_params *dparams = &sc->params.devlog;
3124 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3125 dparams->size, &dparams->addr);
3131 update_nirq(struct intrs_and_queues *iaq, int nports)
3133 int extra = T4_EXTRA_INTR;
3136 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
3137 iaq->nirq += nports * (iaq->num_vis - 1) *
3138 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3139 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3143 * Adjust requirements to fit the number of interrupts available.
3146 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3150 const int nports = sc->params.nports;
3155 bzero(iaq, sizeof(*iaq));
3156 iaq->intr_type = itype;
3157 iaq->num_vis = t4_num_vis;
3158 iaq->ntxq = t4_ntxq;
3159 iaq->ntxq_vi = t4_ntxq_vi;
3160 iaq->nrxq = t4_nrxq;
3161 iaq->nrxq_vi = t4_nrxq_vi;
3162 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3163 if (is_offload(sc) || is_ethoffload(sc)) {
3164 iaq->nofldtxq = t4_nofldtxq;
3165 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3169 if (is_offload(sc)) {
3170 iaq->nofldrxq = t4_nofldrxq;
3171 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3175 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3176 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3179 update_nirq(iaq, nports);
3180 if (iaq->nirq <= navail &&
3181 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3183 * This is the normal case -- there are enough interrupts for
3190 * If extra VIs have been configured try reducing their count and see if
3193 while (iaq->num_vis > 1) {
3195 update_nirq(iaq, nports);
3196 if (iaq->nirq <= navail &&
3197 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3198 device_printf(sc->dev, "virtual interfaces per port "
3199 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3200 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3201 "itype %d, navail %u, nirq %d.\n",
3202 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3203 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3204 itype, navail, iaq->nirq);
3210 * Extra VIs will not be created. Log a message if they were requested.
3212 MPASS(iaq->num_vis == 1);
3213 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3214 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3215 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3216 if (iaq->num_vis != t4_num_vis) {
3217 device_printf(sc->dev, "extra virtual interfaces disabled. "
3218 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3219 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3220 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3221 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3225 * Keep reducing the number of NIC rx queues to the next lower power of
3226 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3230 if (iaq->nrxq > 1) {
3233 } while (!powerof2(iaq->nrxq));
3235 if (iaq->nofldrxq > 1)
3236 iaq->nofldrxq >>= 1;
3238 old_nirq = iaq->nirq;
3239 update_nirq(iaq, nports);
3240 if (iaq->nirq <= navail &&
3241 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3242 device_printf(sc->dev, "running with reduced number of "
3243 "rx queues because of shortage of interrupts. "
3244 "nrxq=%u, nofldrxq=%u. "
3245 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3246 iaq->nofldrxq, itype, navail, iaq->nirq);
3249 } while (old_nirq != iaq->nirq);
3251 /* One interrupt for everything. Ugh. */
3252 device_printf(sc->dev, "running with minimal number of queues. "
3253 "itype %d, navail %u.\n", itype, navail);
3255 MPASS(iaq->nrxq == 1);
3257 if (iaq->nofldrxq > 1)
3260 MPASS(iaq->num_vis > 0);
3261 if (iaq->num_vis > 1) {
3262 MPASS(iaq->nrxq_vi > 0);
3263 MPASS(iaq->ntxq_vi > 0);
3265 MPASS(iaq->nirq > 0);
3266 MPASS(iaq->nrxq > 0);
3267 MPASS(iaq->ntxq > 0);
3268 if (itype == INTR_MSI) {
3269 MPASS(powerof2(iaq->nirq));
3274 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3276 int rc, itype, navail, nalloc;
3278 for (itype = INTR_MSIX; itype; itype >>= 1) {
3280 if ((itype & t4_intr_types) == 0)
3281 continue; /* not allowed */
3283 if (itype == INTR_MSIX)
3284 navail = pci_msix_count(sc->dev);
3285 else if (itype == INTR_MSI)
3286 navail = pci_msi_count(sc->dev);
3293 calculate_iaq(sc, iaq, itype, navail);
3296 if (itype == INTR_MSIX)
3297 rc = pci_alloc_msix(sc->dev, &nalloc);
3298 else if (itype == INTR_MSI)
3299 rc = pci_alloc_msi(sc->dev, &nalloc);
3301 if (rc == 0 && nalloc > 0) {
3302 if (nalloc == iaq->nirq)
3306 * Didn't get the number requested. Use whatever number
3307 * the kernel is willing to allocate.
3309 device_printf(sc->dev, "fewer vectors than requested, "
3310 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3311 itype, iaq->nirq, nalloc);
3312 pci_release_msi(sc->dev);
3317 device_printf(sc->dev,
3318 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3319 itype, rc, iaq->nirq, nalloc);
3322 device_printf(sc->dev,
3323 "failed to find a usable interrupt type. "
3324 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3325 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3330 #define FW_VERSION(chip) ( \
3331 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3332 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3333 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3334 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3335 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3337 /* Just enough of fw_hdr to cover all version info. */
3343 __be32 tp_microcode_ver;
3348 __u8 intfver_iscsipdu;
3350 __u8 intfver_fcoepdu;
3353 /* Spot check a couple of fields. */
3354 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3355 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3356 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3366 .kld_name = "t4fw_cfg",
3367 .fw_mod_name = "t4fw",
3369 .chip = FW_HDR_CHIP_T4,
3370 .fw_ver = htobe32(FW_VERSION(T4)),
3371 .intfver_nic = FW_INTFVER(T4, NIC),
3372 .intfver_vnic = FW_INTFVER(T4, VNIC),
3373 .intfver_ofld = FW_INTFVER(T4, OFLD),
3374 .intfver_ri = FW_INTFVER(T4, RI),
3375 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3376 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3377 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3378 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3382 .kld_name = "t5fw_cfg",
3383 .fw_mod_name = "t5fw",
3385 .chip = FW_HDR_CHIP_T5,
3386 .fw_ver = htobe32(FW_VERSION(T5)),
3387 .intfver_nic = FW_INTFVER(T5, NIC),
3388 .intfver_vnic = FW_INTFVER(T5, VNIC),
3389 .intfver_ofld = FW_INTFVER(T5, OFLD),
3390 .intfver_ri = FW_INTFVER(T5, RI),
3391 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3392 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3393 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3394 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3398 .kld_name = "t6fw_cfg",
3399 .fw_mod_name = "t6fw",
3401 .chip = FW_HDR_CHIP_T6,
3402 .fw_ver = htobe32(FW_VERSION(T6)),
3403 .intfver_nic = FW_INTFVER(T6, NIC),
3404 .intfver_vnic = FW_INTFVER(T6, VNIC),
3405 .intfver_ofld = FW_INTFVER(T6, OFLD),
3406 .intfver_ri = FW_INTFVER(T6, RI),
3407 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3408 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3409 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3410 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3415 static struct fw_info *
3416 find_fw_info(int chip)
3420 for (i = 0; i < nitems(fw_info); i++) {
3421 if (fw_info[i].chip == chip)
3422 return (&fw_info[i]);
3428 * Is the given firmware API compatible with the one the driver was compiled
3432 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3435 /* short circuit if it's the exact same firmware version */
3436 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3440 * XXX: Is this too conservative? Perhaps I should limit this to the
3441 * features that are supported in the driver.
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3444 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3445 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3446 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3454 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3455 const struct firmware **fw)
3457 struct fw_info *fw_info;
3463 fw_info = find_fw_info(chip_id(sc));
3464 if (fw_info == NULL) {
3465 device_printf(sc->dev,
3466 "unable to look up firmware information for chip %d.\n",
3471 *dcfg = firmware_get(fw_info->kld_name);
3472 if (*dcfg != NULL) {
3474 *fw = firmware_get(fw_info->fw_mod_name);
3482 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3483 const struct firmware *fw)
3487 firmware_put(fw, FIRMWARE_UNLOAD);
3489 firmware_put(dcfg, FIRMWARE_UNLOAD);
3494 * 0 means no firmware install attempted.
3495 * ERESTART means a firmware install was attempted and was successful.
3496 * +ve errno means a firmware install was attempted but failed.
3499 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3500 const struct fw_h *drv_fw, const char *reason, int *already)
3502 const struct firmware *cfg, *fw;
3503 const uint32_t c = be32toh(card_fw->fw_ver);
3506 struct fw_h bundled_fw;
3507 bool load_attempted;
3510 load_attempted = false;
3511 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3516 if ((sc->flags & FW_OK) == 0) {
3518 if (c == 0xffffffff) {
3526 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3527 if (t4_fw_install < 0) {
3528 rc = load_fw_module(sc, &cfg, &fw);
3529 if (rc != 0 || fw == NULL) {
3530 device_printf(sc->dev,
3531 "failed to load firmware module: %d. cfg %p, fw %p;"
3532 " will use compiled-in firmware version for"
3533 "hw.cxgbe.fw_install checks.\n",
3536 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3538 load_attempted = true;
3540 d = be32toh(bundled_fw.fw_ver);
3542 if (!fw_compatible(card_fw, &bundled_fw)) {
3543 reason = "incompatible or unusable";
3548 reason = "older than the version bundled with this driver";
3552 if (fw_install == 2 && d != c) {
3553 reason = "different than the version bundled with this driver";
3557 /* No reason to do anything to the firmware already on the card. */
3566 if (fw_install == 0) {
3567 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3568 "but the driver is prohibited from installing a firmware "
3570 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3571 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3577 * We'll attempt to install a firmware. Load the module first (if it
3578 * hasn't been loaded already).
3580 if (!load_attempted) {
3581 rc = load_fw_module(sc, &cfg, &fw);
3582 if (rc != 0 || fw == NULL) {
3583 device_printf(sc->dev,
3584 "failed to load firmware module: %d. cfg %p, fw %p\n",
3590 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3591 "but the driver cannot take corrective action because it "
3592 "is unable to load the firmware module.\n",
3593 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3594 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3595 rc = sc->flags & FW_OK ? 0 : ENOENT;
3598 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3600 MPASS(t4_fw_install > 0);
3601 device_printf(sc->dev,
3602 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3603 "expecting (%u.%u.%u.%u) and will not be used.\n",
3604 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3605 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3606 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3607 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3608 rc = sc->flags & FW_OK ? 0 : EINVAL;
3612 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3613 "installing firmware %u.%u.%u.%u on card.\n",
3614 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3615 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3616 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3617 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3619 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3621 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3623 /* Installed successfully, update the cached header too. */
3625 memcpy(card_fw, fw->data, sizeof(*card_fw));
3628 unload_fw_module(sc, cfg, fw);
3634 * Establish contact with the firmware and attempt to become the master driver.
3636 * A firmware will be installed to the card if needed (if the driver is allowed
3640 contact_firmware(struct adapter *sc)
3642 int rc, already = 0;
3643 enum dev_state state;
3644 struct fw_info *fw_info;
3645 struct fw_hdr *card_fw; /* fw on the card */
3646 const struct fw_h *drv_fw;
3648 fw_info = find_fw_info(chip_id(sc));
3649 if (fw_info == NULL) {
3650 device_printf(sc->dev,
3651 "unable to look up firmware information for chip %d.\n",
3655 drv_fw = &fw_info->fw_h;
3657 /* Read the header of the firmware on the card */
3658 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3660 rc = -t4_get_fw_hdr(sc, card_fw);
3662 device_printf(sc->dev,
3663 "unable to read firmware header from card's flash: %d\n",
3668 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3675 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3676 if (rc < 0 || state == DEV_STATE_ERR) {
3678 device_printf(sc->dev,
3679 "failed to connect to the firmware: %d, %d. "
3680 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3682 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3683 "not responding properly to HELLO", &already) == ERESTART)
3688 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3689 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3692 sc->flags |= MASTER_PF;
3693 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3699 } else if (state == DEV_STATE_UNINIT) {
3701 * We didn't get to be the master so we definitely won't be
3702 * configuring the chip. It's a bug if someone else hasn't
3703 * configured it already.
3705 device_printf(sc->dev, "couldn't be master(%d), "
3706 "device not already initialized either(%d). "
3707 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3712 * Some other PF is the master and has configured the chip.
3713 * This is allowed but untested.
3715 device_printf(sc->dev, "PF%d is master, device state %d. "
3716 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3717 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3722 if (rc != 0 && sc->flags & FW_OK) {
3723 t4_fw_bye(sc, sc->mbox);
3724 sc->flags &= ~FW_OK;
3726 free(card_fw, M_CXGBE);
3731 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3732 uint32_t mtype, uint32_t moff)
3734 struct fw_info *fw_info;
3735 const struct firmware *dcfg, *rcfg = NULL;
3736 const uint32_t *cfdata;
3737 uint32_t cflen, addr;
3740 load_fw_module(sc, &dcfg, NULL);
3742 /* Card specific interpretation of "default". */
3743 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3744 if (pci_get_device(sc->dev) == 0x440a)
3745 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3747 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3750 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3752 device_printf(sc->dev,
3753 "KLD with default config is not available.\n");
3757 cfdata = dcfg->data;
3758 cflen = dcfg->datasize & ~3;
3762 fw_info = find_fw_info(chip_id(sc));
3763 if (fw_info == NULL) {
3764 device_printf(sc->dev,
3765 "unable to look up firmware information for chip %d.\n",
3770 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
3772 rcfg = firmware_get(s);
3774 device_printf(sc->dev,
3775 "unable to load module \"%s\" for configuration "
3776 "profile \"%s\".\n", s, cfg_file);
3780 cfdata = rcfg->data;
3781 cflen = rcfg->datasize & ~3;
3784 if (cflen > FLASH_CFG_MAX_SIZE) {
3785 device_printf(sc->dev,
3786 "config file too long (%d, max allowed is %d).\n",
3787 cflen, FLASH_CFG_MAX_SIZE);
3792 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3794 device_printf(sc->dev,
3795 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
3796 __func__, mtype, moff, cflen, rc);
3800 write_via_memwin(sc, 2, addr, cfdata, cflen);
3803 firmware_put(rcfg, FIRMWARE_UNLOAD);
3804 unload_fw_module(sc, dcfg, NULL);
3808 struct caps_allowed {
3811 uint16_t switchcaps;
3815 uint16_t cryptocaps;
3820 #define FW_PARAM_DEV(param) \
3821 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3822 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3823 #define FW_PARAM_PFVF(param) \
3824 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3825 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3828 * Provide a configuration profile to the firmware and have it initialize the
3829 * chip accordingly. This may involve uploading a configuration file to the
3833 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
3834 const struct caps_allowed *caps_allowed)
3837 struct fw_caps_config_cmd caps;
3838 uint32_t mtype, moff, finicsum, cfcsum, param, val;
3840 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3842 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3846 bzero(&caps, sizeof(caps));
3847 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3848 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3849 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
3852 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3853 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
3854 mtype = FW_MEMTYPE_FLASH;
3855 moff = t4_flash_cfg_addr(sc);
3856 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3857 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3858 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3862 * Ask the firmware where it wants us to upload the config file.
3864 param = FW_PARAM_DEV(CF);
3865 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3867 /* No support for config file? Shouldn't happen. */
3868 device_printf(sc->dev,
3869 "failed to query config file location: %d.\n", rc);
3872 mtype = G_FW_PARAMS_PARAM_Y(val);
3873 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3874 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3875 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3876 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
3879 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
3881 device_printf(sc->dev,
3882 "failed to upload config file to card: %d.\n", rc);
3886 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3888 device_printf(sc->dev, "failed to pre-process config file: %d "
3889 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3893 finicsum = be32toh(caps.finicsum);
3894 cfcsum = be32toh(caps.cfcsum); /* actual */
3895 if (finicsum != cfcsum) {
3896 device_printf(sc->dev,
3897 "WARNING: config file checksum mismatch: %08x %08x\n",
3900 sc->cfcsum = cfcsum;
3901 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
3904 * Let the firmware know what features will (not) be used so it can tune
3905 * things accordingly.
3907 #define LIMIT_CAPS(x) do { \
3908 caps.x##caps &= htobe16(caps_allowed->x##caps); \
3920 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
3922 * TOE and hashfilters are mutually exclusive. It is a config
3923 * file or firmware bug if both are reported as available. Try
3924 * to cope with the situation in non-debug builds by disabling
3927 MPASS(caps.toecaps == 0);
3934 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3935 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3936 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3937 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3939 device_printf(sc->dev,
3940 "failed to process config file: %d.\n", rc);
3944 t4_tweak_chip_settings(sc);
3946 /* get basic stuff going */
3947 rc = -t4_fw_initialize(sc, sc->mbox);
3949 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
3957 * Partition chip resources for use between various PFs, VFs, etc.
3960 partition_resources(struct adapter *sc)
3962 char cfg_file[sizeof(t4_cfg_file)];
3963 struct caps_allowed caps_allowed;
3967 /* Only the master driver gets to configure the chip resources. */
3968 MPASS(sc->flags & MASTER_PF);
3970 #define COPY_CAPS(x) do { \
3971 caps_allowed.x##caps = t4_##x##caps_allowed; \
3973 bzero(&caps_allowed, sizeof(caps_allowed));
3983 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
3984 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
3986 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
3987 if (rc != 0 && fallback) {
3988 device_printf(sc->dev,
3989 "failed (%d) to configure card with \"%s\" profile, "
3990 "will fall back to a basic configuration and retry.\n",
3992 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
3993 bzero(&caps_allowed, sizeof(caps_allowed));
4006 * Retrieve parameters that are needed (or nice to have) very early.
4009 get_params__pre_init(struct adapter *sc)
4012 uint32_t param[2], val[2];
4014 t4_get_version_info(sc);
4016 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4017 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4018 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4019 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4020 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4022 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4023 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4024 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4025 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4026 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4028 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4029 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4030 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4031 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4032 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4034 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4035 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4036 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4037 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4038 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4040 param[0] = FW_PARAM_DEV(PORTVEC);
4041 param[1] = FW_PARAM_DEV(CCLK);
4042 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4044 device_printf(sc->dev,
4045 "failed to query parameters (pre_init): %d.\n", rc);
4049 sc->params.portvec = val[0];
4050 sc->params.nports = bitcount32(val[0]);
4051 sc->params.vpd.cclk = val[1];
4053 /* Read device log parameters. */
4054 rc = -t4_init_devlog_params(sc, 1);
4056 fixup_devlog_params(sc);
4058 device_printf(sc->dev,
4059 "failed to get devlog parameters: %d.\n", rc);
4060 rc = 0; /* devlog isn't critical for device operation */
4067 * Retrieve various parameters that are of interest to the driver. The device
4068 * has been initialized by the firmware at this point.
4071 get_params__post_init(struct adapter *sc)
4074 uint32_t param[7], val[7];
4075 struct fw_caps_config_cmd caps;
4077 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4078 param[1] = FW_PARAM_PFVF(EQ_START);
4079 param[2] = FW_PARAM_PFVF(FILTER_START);
4080 param[3] = FW_PARAM_PFVF(FILTER_END);
4081 param[4] = FW_PARAM_PFVF(L2T_START);
4082 param[5] = FW_PARAM_PFVF(L2T_END);
4083 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4084 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4085 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4086 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4088 device_printf(sc->dev,
4089 "failed to query parameters (post_init): %d.\n", rc);
4093 sc->sge.iq_start = val[0];
4094 sc->sge.eq_start = val[1];
4095 if ((int)val[3] > (int)val[2]) {
4096 sc->tids.ftid_base = val[2];
4097 sc->tids.ftid_end = val[3];
4098 sc->tids.nftids = val[3] - val[2] + 1;
4100 sc->vres.l2t.start = val[4];
4101 sc->vres.l2t.size = val[5] - val[4] + 1;
4102 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4103 ("%s: L2 table size (%u) larger than expected (%u)",
4104 __func__, sc->vres.l2t.size, L2T_SIZE));
4105 sc->params.core_vdd = val[6];
4107 if (chip_id(sc) >= CHELSIO_T6) {
4110 if (sc->params.fw_vers >=
4111 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4112 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) {
4114 * Note that the code to enable the region should run
4115 * before t4_fw_initialize and not here. This is just a
4116 * reminder to add said code.
4118 device_printf(sc->dev,
4119 "hpfilter region not enabled.\n");
4123 sc->tids.tid_base = t4_read_reg(sc,
4124 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4126 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4127 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4128 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4130 device_printf(sc->dev,
4131 "failed to query hpfilter parameters: %d.\n", rc);
4134 if ((int)val[1] > (int)val[0]) {
4135 sc->tids.hpftid_base = val[0];
4136 sc->tids.hpftid_end = val[1];
4137 sc->tids.nhpftids = val[1] - val[0] + 1;
4140 * These should go off if the layout changes and the
4141 * driver needs to catch up.
4143 MPASS(sc->tids.hpftid_base == 0);
4144 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4149 * MPSBGMAP is queried separately because only recent firmwares support
4150 * it as a parameter and we don't want the compound query above to fail
4151 * on older firmwares.
4153 param[0] = FW_PARAM_DEV(MPSBGMAP);
4155 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4157 sc->params.mps_bg_map = val[0];
4159 sc->params.mps_bg_map = 0;
4162 * Determine whether the firmware supports the filter2 work request.
4163 * This is queried separately for the same reason as MPSBGMAP above.
4165 param[0] = FW_PARAM_DEV(FILTER2_WR);
4167 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4169 sc->params.filter2_wr_support = val[0] != 0;
4171 sc->params.filter2_wr_support = 0;
4174 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4175 * This is queried separately for the same reason as other params above.
4177 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4179 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4181 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4183 sc->params.ulptx_memwrite_dsgl = false;
4185 /* get capabilites */
4186 bzero(&caps, sizeof(caps));
4187 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4188 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4189 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4190 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4192 device_printf(sc->dev,
4193 "failed to get card capabilities: %d.\n", rc);
4197 #define READ_CAPS(x) do { \
4198 sc->x = htobe16(caps.x); \
4201 READ_CAPS(linkcaps);
4202 READ_CAPS(switchcaps);
4205 READ_CAPS(rdmacaps);
4206 READ_CAPS(cryptocaps);
4207 READ_CAPS(iscsicaps);
4208 READ_CAPS(fcoecaps);
4210 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4211 MPASS(chip_id(sc) > CHELSIO_T4);
4212 MPASS(sc->toecaps == 0);
4215 param[0] = FW_PARAM_DEV(NTID);
4216 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4218 device_printf(sc->dev,
4219 "failed to query HASHFILTER parameters: %d.\n", rc);
4222 sc->tids.ntids = val[0];
4223 if (sc->params.fw_vers <
4224 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4225 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4226 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4227 sc->tids.ntids -= sc->tids.nhpftids;
4229 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4230 sc->params.hash_filter = 1;
4232 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4233 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4234 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4235 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4236 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4238 device_printf(sc->dev,
4239 "failed to query NIC parameters: %d.\n", rc);
4242 if ((int)val[1] > (int)val[0]) {
4243 sc->tids.etid_base = val[0];
4244 sc->tids.etid_end = val[1];
4245 sc->tids.netids = val[1] - val[0] + 1;
4246 sc->params.eo_wr_cred = val[2];
4247 sc->params.ethoffload = 1;
4251 /* query offload-related parameters */
4252 param[0] = FW_PARAM_DEV(NTID);
4253 param[1] = FW_PARAM_PFVF(SERVER_START);
4254 param[2] = FW_PARAM_PFVF(SERVER_END);
4255 param[3] = FW_PARAM_PFVF(TDDP_START);
4256 param[4] = FW_PARAM_PFVF(TDDP_END);
4257 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4258 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4260 device_printf(sc->dev,
4261 "failed to query TOE parameters: %d.\n", rc);
4264 sc->tids.ntids = val[0];
4265 if (sc->params.fw_vers <
4266 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4267 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4268 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4269 sc->tids.ntids -= sc->tids.nhpftids;
4271 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4272 if ((int)val[2] > (int)val[1]) {
4273 sc->tids.stid_base = val[1];
4274 sc->tids.nstids = val[2] - val[1] + 1;
4276 sc->vres.ddp.start = val[3];
4277 sc->vres.ddp.size = val[4] - val[3] + 1;
4278 sc->params.ofldq_wr_cred = val[5];
4279 sc->params.offload = 1;
4282 * The firmware attempts memfree TOE configuration for -SO cards
4283 * and will report toecaps=0 if it runs out of resources (this
4284 * depends on the config file). It may not report 0 for other
4285 * capabilities dependent on the TOE in this case. Set them to
4286 * 0 here so that the driver doesn't bother tracking resources
4287 * that will never be used.
4293 param[0] = FW_PARAM_PFVF(STAG_START);
4294 param[1] = FW_PARAM_PFVF(STAG_END);
4295 param[2] = FW_PARAM_PFVF(RQ_START);
4296 param[3] = FW_PARAM_PFVF(RQ_END);
4297 param[4] = FW_PARAM_PFVF(PBL_START);
4298 param[5] = FW_PARAM_PFVF(PBL_END);
4299 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4301 device_printf(sc->dev,
4302 "failed to query RDMA parameters(1): %d.\n", rc);
4305 sc->vres.stag.start = val[0];
4306 sc->vres.stag.size = val[1] - val[0] + 1;
4307 sc->vres.rq.start = val[2];
4308 sc->vres.rq.size = val[3] - val[2] + 1;
4309 sc->vres.pbl.start = val[4];
4310 sc->vres.pbl.size = val[5] - val[4] + 1;
4312 param[0] = FW_PARAM_PFVF(SQRQ_START);
4313 param[1] = FW_PARAM_PFVF(SQRQ_END);
4314 param[2] = FW_PARAM_PFVF(CQ_START);
4315 param[3] = FW_PARAM_PFVF(CQ_END);
4316 param[4] = FW_PARAM_PFVF(OCQ_START);
4317 param[5] = FW_PARAM_PFVF(OCQ_END);
4318 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4320 device_printf(sc->dev,
4321 "failed to query RDMA parameters(2): %d.\n", rc);
4324 sc->vres.qp.start = val[0];
4325 sc->vres.qp.size = val[1] - val[0] + 1;
4326 sc->vres.cq.start = val[2];
4327 sc->vres.cq.size = val[3] - val[2] + 1;
4328 sc->vres.ocq.start = val[4];
4329 sc->vres.ocq.size = val[5] - val[4] + 1;
4331 param[0] = FW_PARAM_PFVF(SRQ_START);
4332 param[1] = FW_PARAM_PFVF(SRQ_END);
4333 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4334 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4335 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4337 device_printf(sc->dev,
4338 "failed to query RDMA parameters(3): %d.\n", rc);
4341 sc->vres.srq.start = val[0];
4342 sc->vres.srq.size = val[1] - val[0] + 1;
4343 sc->params.max_ordird_qp = val[2];
4344 sc->params.max_ird_adapter = val[3];
4346 if (sc->iscsicaps) {
4347 param[0] = FW_PARAM_PFVF(ISCSI_START);
4348 param[1] = FW_PARAM_PFVF(ISCSI_END);
4349 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4351 device_printf(sc->dev,
4352 "failed to query iSCSI parameters: %d.\n", rc);
4355 sc->vres.iscsi.start = val[0];
4356 sc->vres.iscsi.size = val[1] - val[0] + 1;
4358 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4359 param[0] = FW_PARAM_PFVF(TLS_START);
4360 param[1] = FW_PARAM_PFVF(TLS_END);
4361 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4363 device_printf(sc->dev,
4364 "failed to query TLS parameters: %d.\n", rc);
4367 sc->vres.key.start = val[0];
4368 sc->vres.key.size = val[1] - val[0] + 1;
4371 t4_init_sge_params(sc);
4374 * We've got the params we wanted to query via the firmware. Now grab
4375 * some others directly from the chip.
4377 rc = t4_read_chip_settings(sc);
4383 set_params__post_init(struct adapter *sc)
4385 uint32_t param, val;
4390 /* ask for encapsulated CPLs */
4391 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4393 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4395 /* Enable 32b port caps if the firmware supports it. */
4396 param = FW_PARAM_PFVF(PORT_CAPS32);
4398 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4399 sc->params.port_caps32 = 1;
4401 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4402 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4403 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4404 V_MASKFILTER(val - 1));
4408 * Override the TOE timers with user provided tunables. This is not the
4409 * recommended way to change the timers (the firmware config file is) so
4410 * these tunables are not documented.
4412 * All the timer tunables are in microseconds.
4414 if (t4_toe_keepalive_idle != 0) {
4415 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4416 v &= M_KEEPALIVEIDLE;
4417 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4418 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4420 if (t4_toe_keepalive_interval != 0) {
4421 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4422 v &= M_KEEPALIVEINTVL;
4423 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4424 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4426 if (t4_toe_keepalive_count != 0) {
4427 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4428 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4429 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4430 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4431 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4433 if (t4_toe_rexmt_min != 0) {
4434 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4436 t4_set_reg_field(sc, A_TP_RXT_MIN,
4437 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4439 if (t4_toe_rexmt_max != 0) {
4440 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4442 t4_set_reg_field(sc, A_TP_RXT_MAX,
4443 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4445 if (t4_toe_rexmt_count != 0) {
4446 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4447 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4448 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4449 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4450 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4452 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4453 if (t4_toe_rexmt_backoff[i] != -1) {
4454 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4455 shift = (i & 3) << 3;
4456 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4457 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4464 #undef FW_PARAM_PFVF
4468 t4_set_desc(struct adapter *sc)
4471 struct adapter_params *p = &sc->params;
4473 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4475 device_set_desc_copy(sc->dev, buf);
4479 ifmedia_add4(struct ifmedia *ifm, int m)
4482 ifmedia_add(ifm, m, 0, NULL);
4483 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4484 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4485 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4489 * This is the selected media, which is not quite the same as the active media.
4490 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4491 * and active are not the same, and "media: Ethernet selected" otherwise.
4494 set_current_media(struct port_info *pi)
4496 struct link_config *lc;
4497 struct ifmedia *ifm;
4501 PORT_LOCK_ASSERT_OWNED(pi);
4503 /* Leave current media alone if it's already set to IFM_NONE. */
4505 if (ifm->ifm_cur != NULL &&
4506 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4510 if (lc->requested_aneg != AUTONEG_DISABLE &&
4511 lc->supported & FW_PORT_CAP32_ANEG) {
4512 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4515 mword = IFM_ETHER | IFM_FDX;
4516 if (lc->requested_fc & PAUSE_TX)
4517 mword |= IFM_ETH_TXPAUSE;
4518 if (lc->requested_fc & PAUSE_RX)
4519 mword |= IFM_ETH_RXPAUSE;
4520 if (lc->requested_speed == 0)
4521 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4523 speed = lc->requested_speed;
4524 mword |= port_mword(pi, speed_to_fwcap(speed));
4525 ifmedia_set(ifm, mword);
4529 * Returns true if the ifmedia list for the port cannot change.
4532 fixed_ifmedia(struct port_info *pi)
4535 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4536 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4537 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4538 pi->port_type == FW_PORT_TYPE_KX4 ||
4539 pi->port_type == FW_PORT_TYPE_KX ||
4540 pi->port_type == FW_PORT_TYPE_KR ||
4541 pi->port_type == FW_PORT_TYPE_BP_AP ||
4542 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4543 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4544 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4545 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4546 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4550 build_medialist(struct port_info *pi)
4553 int unknown, mword, bit;
4554 struct link_config *lc;
4555 struct ifmedia *ifm;
4557 PORT_LOCK_ASSERT_OWNED(pi);
4559 if (pi->flags & FIXED_IFMEDIA)
4563 * Rebuild the ifmedia list.
4566 ifmedia_removeall(ifm);
4568 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4569 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4572 MPASS(LIST_EMPTY(&ifm->ifm_list));
4573 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4574 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4579 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4581 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4583 mword = port_mword(pi, speed);
4584 if (mword == IFM_NONE) {
4586 } else if (mword == IFM_UNKNOWN)
4589 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4592 if (unknown > 0) /* Add one unknown for all unknown media types. */
4593 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4594 if (lc->supported & FW_PORT_CAP32_ANEG)
4595 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4597 set_current_media(pi);
4601 * Initialize the requested fields in the link config based on driver tunables.
4604 init_link_config(struct port_info *pi)
4606 struct link_config *lc = &pi->link_cfg;
4608 PORT_LOCK_ASSERT_OWNED(pi);
4610 lc->requested_speed = 0;
4612 if (t4_autoneg == 0)
4613 lc->requested_aneg = AUTONEG_DISABLE;
4614 else if (t4_autoneg == 1)
4615 lc->requested_aneg = AUTONEG_ENABLE;
4617 lc->requested_aneg = AUTONEG_AUTO;
4619 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4622 if (t4_fec == -1 || t4_fec & FEC_AUTO)
4623 lc->requested_fec = FEC_AUTO;
4625 lc->requested_fec = FEC_NONE;
4626 if (t4_fec & FEC_RS)
4627 lc->requested_fec |= FEC_RS;
4628 if (t4_fec & FEC_BASER_RS)
4629 lc->requested_fec |= FEC_BASER_RS;
4634 * Makes sure that all requested settings comply with what's supported by the
4635 * port. Returns the number of settings that were invalid and had to be fixed.
4638 fixup_link_config(struct port_info *pi)
4641 struct link_config *lc = &pi->link_cfg;
4644 PORT_LOCK_ASSERT_OWNED(pi);
4646 /* Speed (when not autonegotiating) */
4647 if (lc->requested_speed != 0) {
4648 fwspeed = speed_to_fwcap(lc->requested_speed);
4649 if ((fwspeed & lc->supported) == 0) {
4651 lc->requested_speed = 0;
4655 /* Link autonegotiation */
4656 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4657 lc->requested_aneg == AUTONEG_DISABLE ||
4658 lc->requested_aneg == AUTONEG_AUTO);
4659 if (lc->requested_aneg == AUTONEG_ENABLE &&
4660 !(lc->supported & FW_PORT_CAP32_ANEG)) {
4662 lc->requested_aneg = AUTONEG_AUTO;
4666 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4667 if (lc->requested_fc & PAUSE_TX &&
4668 !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4670 lc->requested_fc &= ~PAUSE_TX;
4672 if (lc->requested_fc & PAUSE_RX &&
4673 !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4675 lc->requested_fc &= ~PAUSE_RX;
4677 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4678 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4680 lc->requested_fc |= PAUSE_AUTONEG;
4684 if ((lc->requested_fec & FEC_RS &&
4685 !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4686 (lc->requested_fec & FEC_BASER_RS &&
4687 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4689 lc->requested_fec = FEC_AUTO;
4696 * Apply the requested L1 settings, which are expected to be valid, to the
4700 apply_link_config(struct port_info *pi)
4702 struct adapter *sc = pi->adapter;
4703 struct link_config *lc = &pi->link_cfg;
4707 ASSERT_SYNCHRONIZED_OP(sc);
4708 PORT_LOCK_ASSERT_OWNED(pi);
4710 if (lc->requested_aneg == AUTONEG_ENABLE)
4711 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4712 if (!(lc->requested_fc & PAUSE_AUTONEG))
4713 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4714 if (lc->requested_fc & PAUSE_TX)
4715 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4716 if (lc->requested_fc & PAUSE_RX)
4717 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4718 if (lc->requested_fec & FEC_RS)
4719 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4720 if (lc->requested_fec & FEC_BASER_RS)
4721 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4723 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4725 /* Don't complain if the VF driver gets back an EPERM. */
4726 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
4727 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4730 * An L1_CFG will almost always result in a link-change event if
4731 * the link is up, and the driver will refresh the actual
4732 * fec/fc/etc. when the notification is processed. If the link
4733 * is down then the actual settings are meaningless.
4735 * This takes care of the case where a change in the L1 settings
4736 * may not result in a notification.
4738 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4739 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4744 #define FW_MAC_EXACT_CHUNK 7
4747 * Program the port's XGMAC based on parameters in ifnet. The caller also
4748 * indicates which parameters should be programmed (the rest are left alone).
4751 update_mac_settings(struct ifnet *ifp, int flags)
4754 struct vi_info *vi = ifp->if_softc;
4755 struct port_info *pi = vi->pi;
4756 struct adapter *sc = pi->adapter;
4757 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4759 ASSERT_SYNCHRONIZED_OP(sc);
4760 KASSERT(flags, ("%s: not told what to update.", __func__));
4762 if (flags & XGMAC_MTU)
4765 if (flags & XGMAC_PROMISC)
4766 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4768 if (flags & XGMAC_ALLMULTI)
4769 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4771 if (flags & XGMAC_VLANEX)
4772 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4774 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4775 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4776 allmulti, 1, vlanex, false);
4778 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4784 if (flags & XGMAC_UCADDR) {
4785 uint8_t ucaddr[ETHER_ADDR_LEN];
4787 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4788 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4789 ucaddr, true, true);
4792 if_printf(ifp, "change_mac failed: %d\n", rc);
4795 vi->xact_addr_filt = rc;
4800 if (flags & XGMAC_MCADDRS) {
4801 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4804 struct ifmultiaddr *ifma;
4807 if_maddr_rlock(ifp);
4808 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4809 if (ifma->ifma_addr->sa_family != AF_LINK)
4812 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4813 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4816 if (i == FW_MAC_EXACT_CHUNK) {
4817 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4818 del, i, mcaddr, NULL, &hash, 0);
4821 for (j = 0; j < i; j++) {
4823 "failed to add mc address"
4825 "%02x:%02x:%02x rc=%d\n",
4826 mcaddr[j][0], mcaddr[j][1],
4827 mcaddr[j][2], mcaddr[j][3],
4828 mcaddr[j][4], mcaddr[j][5],
4838 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4839 mcaddr, NULL, &hash, 0);
4842 for (j = 0; j < i; j++) {
4844 "failed to add mc address"
4846 "%02x:%02x:%02x rc=%d\n",
4847 mcaddr[j][0], mcaddr[j][1],
4848 mcaddr[j][2], mcaddr[j][3],
4849 mcaddr[j][4], mcaddr[j][5],
4856 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4858 if_printf(ifp, "failed to set mc address hash: %d", rc);
4860 if_maddr_runlock(ifp);
4867 * {begin|end}_synchronized_op must be called from the same thread.
4870 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4876 /* the caller thinks it's ok to sleep, but is it really? */
4877 if (flags & SLEEP_OK)
4878 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4879 "begin_synchronized_op");
4890 if (vi && IS_DOOMED(vi)) {
4900 if (!(flags & SLEEP_OK)) {
4905 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4911 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4914 sc->last_op = wmesg;
4915 sc->last_op_thr = curthread;
4916 sc->last_op_flags = flags;
4920 if (!(flags & HOLD_LOCK) || rc)
4927 * Tell if_ioctl and if_init that the VI is going away. This is
4928 * special variant of begin_synchronized_op and must be paired with a
4929 * call to end_synchronized_op.
4932 doom_vi(struct adapter *sc, struct vi_info *vi)
4939 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4942 sc->last_op = "t4detach";
4943 sc->last_op_thr = curthread;
4944 sc->last_op_flags = 0;
4950 * {begin|end}_synchronized_op must be called from the same thread.
4953 end_synchronized_op(struct adapter *sc, int flags)
4956 if (flags & LOCK_HELD)
4957 ADAPTER_LOCK_ASSERT_OWNED(sc);
4961 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4968 cxgbe_init_synchronized(struct vi_info *vi)
4970 struct port_info *pi = vi->pi;
4971 struct adapter *sc = pi->adapter;
4972 struct ifnet *ifp = vi->ifp;
4974 struct sge_txq *txq;
4976 ASSERT_SYNCHRONIZED_OP(sc);
4978 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4979 return (0); /* already running */
4981 if (!(sc->flags & FULL_INIT_DONE) &&
4982 ((rc = adapter_full_init(sc)) != 0))
4983 return (rc); /* error message displayed already */
4985 if (!(vi->flags & VI_INIT_DONE) &&
4986 ((rc = vi_full_init(vi)) != 0))
4987 return (rc); /* error message displayed already */
4989 rc = update_mac_settings(ifp, XGMAC_ALL);
4991 goto done; /* error message displayed already */
4994 if (pi->up_vis == 0) {
4995 t4_update_port_info(pi);
4996 fixup_link_config(pi);
4997 build_medialist(pi);
4998 apply_link_config(pi);
5001 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5003 if_printf(ifp, "enable_vi failed: %d\n", rc);
5009 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5013 for_each_txq(vi, i, txq) {
5015 txq->eq.flags |= EQ_ENABLED;
5020 * The first iq of the first port to come up is used for tracing.
5022 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5023 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5024 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5025 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5026 V_QUEUENUMBER(sc->traceq));
5027 pi->flags |= HAS_TRACEQ;
5032 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5034 if (pi->nvi > 1 || sc->flags & IS_VF)
5035 callout_reset(&vi->tick, hz, vi_tick, vi);
5037 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5041 cxgbe_uninit_synchronized(vi);
5050 cxgbe_uninit_synchronized(struct vi_info *vi)
5052 struct port_info *pi = vi->pi;
5053 struct adapter *sc = pi->adapter;
5054 struct ifnet *ifp = vi->ifp;
5056 struct sge_txq *txq;
5058 ASSERT_SYNCHRONIZED_OP(sc);
5060 if (!(vi->flags & VI_INIT_DONE)) {
5061 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5062 KASSERT(0, ("uninited VI is running"));
5063 if_printf(ifp, "uninited VI with running ifnet. "
5064 "vi->flags 0x%016lx, if_flags 0x%08x, "
5065 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5072 * Disable the VI so that all its data in either direction is discarded
5073 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5074 * tick) intact as the TP can deliver negative advice or data that it's
5075 * holding in its RAM (for an offloaded connection) even after the VI is
5078 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5080 if_printf(ifp, "disable_vi failed: %d\n", rc);
5084 for_each_txq(vi, i, txq) {
5086 txq->eq.flags &= ~EQ_ENABLED;
5091 if (pi->nvi > 1 || sc->flags & IS_VF)
5092 callout_stop(&vi->tick);
5094 callout_stop(&pi->tick);
5095 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5099 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5101 if (pi->up_vis > 0) {
5106 pi->link_cfg.link_ok = false;
5107 pi->link_cfg.speed = 0;
5108 pi->link_cfg.link_down_rc = 255;
5109 t4_os_link_changed(pi);
5116 * It is ok for this function to fail midway and return right away. t4_detach
5117 * will walk the entire sc->irq list and clean up whatever is valid.
5120 t4_setup_intr_handlers(struct adapter *sc)
5122 int rc, rid, p, q, v;
5125 struct port_info *pi;
5127 struct sge *sge = &sc->sge;
5128 struct sge_rxq *rxq;
5130 struct sge_ofld_rxq *ofld_rxq;
5133 struct sge_nm_rxq *nm_rxq;
5136 int nbuckets = rss_getnumbuckets();
5143 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5144 if (forwarding_intr_to_fwq(sc))
5145 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5147 /* Multiple interrupts. */
5148 if (sc->flags & IS_VF)
5149 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5150 ("%s: too few intr.", __func__));
5152 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5153 ("%s: too few intr.", __func__));
5155 /* The first one is always error intr on PFs */
5156 if (!(sc->flags & IS_VF)) {
5157 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5164 /* The second one is always the firmware event queue (first on VFs) */
5165 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5171 for_each_port(sc, p) {
5173 for_each_vi(pi, v, vi) {
5174 vi->first_intr = rid - 1;
5176 if (vi->nnmrxq > 0) {
5177 int n = max(vi->nrxq, vi->nnmrxq);
5179 rxq = &sge->rxq[vi->first_rxq];
5181 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5183 for (q = 0; q < n; q++) {
5184 snprintf(s, sizeof(s), "%x%c%x", p,
5190 irq->nm_rxq = nm_rxq++;
5192 if (irq->nm_rxq != NULL &&
5194 /* Netmap rx only */
5195 rc = t4_alloc_irq(sc, irq, rid,
5196 t4_nm_intr, irq->nm_rxq, s);
5198 if (irq->nm_rxq != NULL &&
5200 /* NIC and Netmap rx */
5201 rc = t4_alloc_irq(sc, irq, rid,
5202 t4_vi_intr, irq, s);
5205 if (irq->rxq != NULL &&
5206 irq->nm_rxq == NULL) {
5208 rc = t4_alloc_irq(sc, irq, rid,
5209 t4_intr, irq->rxq, s);
5215 bus_bind_intr(sc->dev, irq->res,
5216 rss_getcpu(q % nbuckets));
5224 for_each_rxq(vi, q, rxq) {
5225 snprintf(s, sizeof(s), "%x%c%x", p,
5227 rc = t4_alloc_irq(sc, irq, rid,
5232 bus_bind_intr(sc->dev, irq->res,
5233 rss_getcpu(q % nbuckets));
5241 for_each_ofld_rxq(vi, q, ofld_rxq) {
5242 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5243 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5254 MPASS(irq == &sc->irq[sc->intr_count]);
5260 adapter_full_init(struct adapter *sc)
5264 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5265 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5268 ASSERT_SYNCHRONIZED_OP(sc);
5269 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5270 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5271 ("%s: FULL_INIT_DONE already", __func__));
5274 * queues that belong to the adapter (not any particular port).
5276 rc = t4_setup_adapter_queues(sc);
5280 for (i = 0; i < nitems(sc->tq); i++) {
5281 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5282 taskqueue_thread_enqueue, &sc->tq[i]);
5283 if (sc->tq[i] == NULL) {
5284 device_printf(sc->dev,
5285 "failed to allocate task queue %d\n", i);
5289 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5290 device_get_nameunit(sc->dev), i);
5293 MPASS(RSS_KEYSIZE == 40);
5294 rss_getkey((void *)&raw_rss_key[0]);
5295 for (i = 0; i < nitems(rss_key); i++) {
5296 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5298 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5301 if (!(sc->flags & IS_VF))
5303 sc->flags |= FULL_INIT_DONE;
5306 adapter_full_uninit(sc);
5312 adapter_full_uninit(struct adapter *sc)
5316 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5318 t4_teardown_adapter_queues(sc);
5320 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5321 taskqueue_free(sc->tq[i]);
5325 sc->flags &= ~FULL_INIT_DONE;
5331 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5332 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5333 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5334 RSS_HASHTYPE_RSS_UDP_IPV6)
5336 /* Translates kernel hash types to hardware. */
5338 hashconfig_to_hashen(int hashconfig)
5342 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5343 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5344 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5345 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5346 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5347 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5348 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5350 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5351 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5352 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5354 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5355 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5356 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5357 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5362 /* Translates hardware hash types to kernel. */
5364 hashen_to_hashconfig(int hashen)
5368 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5370 * If UDP hashing was enabled it must have been enabled for
5371 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5372 * enabling any 4-tuple hash is nonsense configuration.
5374 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5375 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5377 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5378 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5379 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5380 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5382 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5383 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5384 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5385 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5386 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5387 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5388 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5389 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5391 return (hashconfig);
5396 vi_full_init(struct vi_info *vi)
5398 struct adapter *sc = vi->pi->adapter;
5399 struct ifnet *ifp = vi->ifp;
5401 struct sge_rxq *rxq;
5404 int nbuckets = rss_getnumbuckets();
5405 int hashconfig = rss_gethashconfig();
5409 ASSERT_SYNCHRONIZED_OP(sc);
5410 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5411 ("%s: VI_INIT_DONE already", __func__));
5413 sysctl_ctx_init(&vi->ctx);
5414 vi->flags |= VI_SYSCTL_CTX;
5417 * Allocate tx/rx/fl queues for this VI.
5419 rc = t4_setup_vi_queues(vi);
5421 goto done; /* error message displayed already */
5424 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5426 if (vi->nrxq > vi->rss_size) {
5427 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5428 "some queues will never receive traffic.\n", vi->nrxq,
5430 } else if (vi->rss_size % vi->nrxq) {
5431 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5432 "expect uneven traffic distribution.\n", vi->nrxq,
5436 if (vi->nrxq != nbuckets) {
5437 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5438 "performance will be impacted.\n", vi->nrxq, nbuckets);
5441 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5442 for (i = 0; i < vi->rss_size;) {
5444 j = rss_get_indirection_to_bucket(i);
5446 rxq = &sc->sge.rxq[vi->first_rxq + j];
5447 rss[i++] = rxq->iq.abs_id;
5449 for_each_rxq(vi, j, rxq) {
5450 rss[i++] = rxq->iq.abs_id;
5451 if (i == vi->rss_size)
5457 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5461 if_printf(ifp, "rss_config failed: %d\n", rc);
5466 vi->hashen = hashconfig_to_hashen(hashconfig);
5469 * We may have had to enable some hashes even though the global config
5470 * wants them disabled. This is a potential problem that must be
5471 * reported to the user.
5473 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5476 * If we consider only the supported hash types, then the enabled hashes
5477 * are a superset of the requested hashes. In other words, there cannot
5478 * be any supported hash that was requested but not enabled, but there
5479 * can be hashes that were not requested but had to be enabled.
5481 extra &= SUPPORTED_RSS_HASHTYPES;
5482 MPASS((extra & hashconfig) == 0);
5486 "global RSS config (0x%x) cannot be accommodated.\n",
5489 if (extra & RSS_HASHTYPE_RSS_IPV4)
5490 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5491 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5492 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5493 if (extra & RSS_HASHTYPE_RSS_IPV6)
5494 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5495 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5496 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5497 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5498 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5499 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5500 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5502 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5503 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5504 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5505 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5507 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5510 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5515 vi->flags |= VI_INIT_DONE;
5527 vi_full_uninit(struct vi_info *vi)
5529 struct port_info *pi = vi->pi;
5530 struct adapter *sc = pi->adapter;
5532 struct sge_rxq *rxq;
5533 struct sge_txq *txq;
5535 struct sge_ofld_rxq *ofld_rxq;
5537 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5538 struct sge_wrq *ofld_txq;
5541 if (vi->flags & VI_INIT_DONE) {
5543 /* Need to quiesce queues. */
5545 /* XXX: Only for the first VI? */
5546 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5547 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5549 for_each_txq(vi, i, txq) {
5550 quiesce_txq(sc, txq);
5553 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5554 for_each_ofld_txq(vi, i, ofld_txq) {
5555 quiesce_wrq(sc, ofld_txq);
5559 for_each_rxq(vi, i, rxq) {
5560 quiesce_iq(sc, &rxq->iq);
5561 quiesce_fl(sc, &rxq->fl);
5565 for_each_ofld_rxq(vi, i, ofld_rxq) {
5566 quiesce_iq(sc, &ofld_rxq->iq);
5567 quiesce_fl(sc, &ofld_rxq->fl);
5570 free(vi->rss, M_CXGBE);
5571 free(vi->nm_rss, M_CXGBE);
5574 t4_teardown_vi_queues(vi);
5575 vi->flags &= ~VI_INIT_DONE;
5581 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5583 struct sge_eq *eq = &txq->eq;
5584 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5586 (void) sc; /* unused */
5590 MPASS((eq->flags & EQ_ENABLED) == 0);
5594 /* Wait for the mp_ring to empty. */
5595 while (!mp_ring_is_idle(txq->r)) {
5596 mp_ring_check_drainage(txq->r, 0);
5597 pause("rquiesce", 1);
5600 /* Then wait for the hardware to finish. */
5601 while (spg->cidx != htobe16(eq->pidx))
5602 pause("equiesce", 1);
5604 /* Finally, wait for the driver to reclaim all descriptors. */
5605 while (eq->cidx != eq->pidx)
5606 pause("dquiesce", 1);
5610 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5617 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5619 (void) sc; /* unused */
5621 /* Synchronize with the interrupt handler */
5622 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5627 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5629 mtx_lock(&sc->sfl_lock);
5631 fl->flags |= FL_DOOMED;
5633 callout_stop(&sc->sfl_callout);
5634 mtx_unlock(&sc->sfl_lock);
5636 KASSERT((fl->flags & FL_STARVING) == 0,
5637 ("%s: still starving", __func__));
5641 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5642 driver_intr_t *handler, void *arg, char *name)
5647 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5648 RF_SHAREABLE | RF_ACTIVE);
5649 if (irq->res == NULL) {
5650 device_printf(sc->dev,
5651 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5655 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5656 NULL, handler, arg, &irq->tag);
5658 device_printf(sc->dev,
5659 "failed to setup interrupt for rid %d, name %s: %d\n",
5662 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5668 t4_free_irq(struct adapter *sc, struct irq *irq)
5671 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5673 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5675 bzero(irq, sizeof(*irq));
5681 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5684 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5685 t4_get_regs(sc, buf, regs->len);
5688 #define A_PL_INDIR_CMD 0x1f8
5690 #define S_PL_AUTOINC 31
5691 #define M_PL_AUTOINC 0x1U
5692 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5693 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5695 #define S_PL_VFID 20
5696 #define M_PL_VFID 0xffU
5697 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5698 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5701 #define M_PL_ADDR 0xfffffU
5702 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5703 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5705 #define A_PL_INDIR_DATA 0x1fc
5708 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5712 mtx_assert(&sc->reg_lock, MA_OWNED);
5713 if (sc->flags & IS_VF) {
5714 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5715 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5717 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5718 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5719 V_PL_ADDR(VF_MPS_REG(reg)));
5720 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5721 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5723 return (((uint64_t)stats[1]) << 32 | stats[0]);
5727 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5728 struct fw_vi_stats_vf *stats)
5731 #define GET_STAT(name) \
5732 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5734 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5735 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5736 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5737 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5738 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5739 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5740 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5741 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5742 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5743 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5744 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5745 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5746 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5747 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5748 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5749 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5755 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5759 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5760 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5761 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5762 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5763 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5764 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5768 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5771 const struct timeval interval = {0, 250000}; /* 250ms */
5773 if (!(vi->flags & VI_INIT_DONE))
5777 timevalsub(&tv, &interval);
5778 if (timevalcmp(&tv, &vi->last_refreshed, <))
5781 mtx_lock(&sc->reg_lock);
5782 t4_get_vi_stats(sc, vi->viid, &vi->stats);
5783 getmicrotime(&vi->last_refreshed);
5784 mtx_unlock(&sc->reg_lock);
5788 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5790 u_int i, v, tnl_cong_drops, bg_map;
5792 const struct timeval interval = {0, 250000}; /* 250ms */
5795 timevalsub(&tv, &interval);
5796 if (timevalcmp(&tv, &pi->last_refreshed, <))
5800 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5801 bg_map = pi->mps_bg_map;
5803 i = ffs(bg_map) - 1;
5804 mtx_lock(&sc->reg_lock);
5805 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5806 A_TP_MIB_TNL_CNG_DROP_0 + i);
5807 mtx_unlock(&sc->reg_lock);
5808 tnl_cong_drops += v;
5809 bg_map &= ~(1 << i);
5811 pi->tnl_cong_drops = tnl_cong_drops;
5812 getmicrotime(&pi->last_refreshed);
5816 cxgbe_tick(void *arg)
5818 struct port_info *pi = arg;
5819 struct adapter *sc = pi->adapter;
5821 PORT_LOCK_ASSERT_OWNED(pi);
5822 cxgbe_refresh_stats(sc, pi);
5824 callout_schedule(&pi->tick, hz);
5830 struct vi_info *vi = arg;
5831 struct adapter *sc = vi->pi->adapter;
5833 vi_refresh_stats(sc, vi);
5835 callout_schedule(&vi->tick, hz);
5839 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5841 static char *caps_decoder[] = {
5842 "\20\001IPMI\002NCSI", /* 0: NBM */
5843 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5844 "\20\001INGRESS\002EGRESS", /* 2: switch */
5845 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5846 "\006HASHFILTER\007ETHOFLD",
5847 "\20\001TOE", /* 4: TOE */
5848 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5849 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5850 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5851 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5853 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5854 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5855 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5856 "\004PO_INITIATOR\005PO_TARGET",
5860 t4_sysctls(struct adapter *sc)
5862 struct sysctl_ctx_list *ctx;
5863 struct sysctl_oid *oid;
5864 struct sysctl_oid_list *children, *c0;
5865 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5867 ctx = device_get_sysctl_ctx(sc->dev);
5872 oid = device_get_sysctl_tree(sc->dev);
5873 c0 = children = SYSCTL_CHILDREN(oid);
5875 sc->sc_do_rxcopy = 1;
5876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5877 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5879 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5880 sc->params.nports, "# of ports");
5882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5883 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
5884 sysctl_bitfield_8b, "A", "available doorbells");
5886 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5887 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5890 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5891 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5892 "interrupt holdoff timer values (us)");
5894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5895 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5896 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5897 "interrupt holdoff packet counter values");
5899 t4_sge_sysctls(sc, ctx, children);
5901 sc->lro_timeout = 100;
5902 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5903 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5905 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5906 &sc->debug_flags, 0, "flags to enable runtime debugging");
5908 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5909 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5911 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5912 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5914 if (sc->flags & IS_VF)
5917 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5918 NULL, chip_rev(sc), "chip hardware revision");
5920 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5921 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5923 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5924 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5926 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5927 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5929 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5930 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5932 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5933 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5935 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5936 sc->er_version, 0, "expansion ROM version");
5938 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5939 sc->bs_version, 0, "bootstrap firmware version");
5941 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5942 NULL, sc->params.scfg_vers, "serial config version");
5944 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5945 NULL, sc->params.vpd_vers, "VPD version");
5947 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5948 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5950 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5951 sc->cfcsum, "config file checksum");
5953 #define SYSCTL_CAP(name, n, text) \
5954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5955 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
5956 sysctl_bitfield_16b, "A", "available " text " capabilities")
5958 SYSCTL_CAP(nbmcaps, 0, "NBM");
5959 SYSCTL_CAP(linkcaps, 1, "link");
5960 SYSCTL_CAP(switchcaps, 2, "switch");
5961 SYSCTL_CAP(niccaps, 3, "NIC");
5962 SYSCTL_CAP(toecaps, 4, "TCP offload");
5963 SYSCTL_CAP(rdmacaps, 5, "RDMA");
5964 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5965 SYSCTL_CAP(cryptocaps, 7, "crypto");
5966 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5969 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5970 NULL, sc->tids.nftids, "number of filters");
5972 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5973 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5974 "chip temperature (in Celsius)");
5976 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5977 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5978 "microprocessor load averages (debug firmwares only)");
5980 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5981 &sc->params.core_vdd, 0, "core Vdd (in mV)");
5983 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
5984 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
5985 sysctl_cpus, "A", "local CPUs");
5987 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
5988 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
5989 sysctl_cpus, "A", "preferred CPUs for interrupts");
5992 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5994 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5995 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5996 "logs and miscellaneous information");
5997 children = SYSCTL_CHILDREN(oid);
5999 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6000 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6001 sysctl_cctrl, "A", "congestion control");
6003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6004 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6005 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6007 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6008 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
6009 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6011 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6012 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
6013 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6016 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
6017 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6020 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
6021 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6024 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
6025 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6027 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6028 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_cim_la,
6029 "A", "CIM logic analyzer");
6031 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6032 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6033 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6036 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
6037 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6039 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6040 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
6041 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6043 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6044 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
6045 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6047 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6048 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
6049 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6051 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6052 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
6053 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6055 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6056 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
6057 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6059 if (chip_id(sc) > CHELSIO_T4) {
6060 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6061 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
6062 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
6064 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6065 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
6066 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
6069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6070 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6071 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6074 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6075 sysctl_cim_qcfg, "A", "CIM queue configuration");
6077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6078 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6079 sysctl_cpl_stats, "A", "CPL statistics");
6081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6082 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6083 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6086 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6087 sysctl_devlog, "A", "firmware's device log");
6089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6090 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6091 sysctl_fcoe_stats, "A", "FCoE statistics");
6093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6094 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6095 sysctl_hw_sched, "A", "hardware scheduler ");
6097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6098 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6099 sysctl_l2t, "A", "hardware L2 table");
6101 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6102 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6103 sysctl_smt, "A", "hardware source MAC table");
6106 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6107 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6108 sysctl_clip, "A", "active CLIP table entries");
6111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6112 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6113 sysctl_lb_stats, "A", "loopback statistics");
6115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6116 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6117 sysctl_meminfo, "A", "memory regions");
6119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6120 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6121 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6122 "A", "MPS TCAM entries");
6124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6125 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6126 sysctl_path_mtus, "A", "path MTUs");
6128 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6129 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6130 sysctl_pm_stats, "A", "PM statistics");
6132 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6133 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6134 sysctl_rdma_stats, "A", "RDMA statistics");
6136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6137 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6138 sysctl_tcp_stats, "A", "TCP statistics");
6140 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6141 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6142 sysctl_tids, "A", "TID information");
6144 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6145 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6146 sysctl_tp_err_stats, "A", "TP error statistics");
6148 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6149 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
6150 "TP logic analyzer event capture mask");
6152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6153 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6154 sysctl_tp_la, "A", "TP logic analyzer");
6156 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6157 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6158 sysctl_tx_rate, "A", "Tx rate");
6160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6161 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6162 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6164 if (chip_id(sc) >= CHELSIO_T5) {
6165 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6166 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
6167 sysctl_wcwr_stats, "A", "write combined work requests");
6171 if (is_offload(sc)) {
6178 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
6179 NULL, "TOE parameters");
6180 children = SYSCTL_CHILDREN(oid);
6182 sc->tt.cong_algorithm = -1;
6183 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6184 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6185 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6188 sc->tt.sndbuf = 256 * 1024;
6189 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6190 &sc->tt.sndbuf, 0, "max hardware send buffer size");
6193 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
6194 &sc->tt.ddp, 0, "DDP allowed");
6196 sc->tt.rx_coalesce = 1;
6197 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6198 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6201 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6202 &sc->tt.tls, 0, "Inline TLS allowed");
6204 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6205 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
6206 "I", "TCP ports that use inline TLS+TOE RX");
6208 sc->tt.tx_align = 1;
6209 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6210 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6212 sc->tt.tx_zcopy = 0;
6213 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6214 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6215 "Enable zero-copy aio_write(2)");
6217 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6218 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6219 "cop_managed_offloading", CTLFLAG_RW,
6220 &sc->tt.cop_managed_offloading, 0,
6221 "COP (Connection Offload Policy) controls all TOE offload");
6223 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6224 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6225 "TP timer tick (us)");
6227 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6228 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6229 "TCP timestamp tick (us)");
6231 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6232 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6235 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6236 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6237 "IU", "DACK timer (us)");
6239 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6240 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6241 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6243 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6244 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6245 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6248 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6249 sysctl_tp_timer, "LU", "Persist timer min (us)");
6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6252 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6253 sysctl_tp_timer, "LU", "Persist timer max (us)");
6255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6256 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6257 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6260 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6261 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6263 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6264 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6265 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6267 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6268 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6269 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6272 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6273 sysctl_tp_shift_cnt, "IU",
6274 "Number of SYN retransmissions before abort");
6276 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6277 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6278 sysctl_tp_shift_cnt, "IU",
6279 "Number of retransmissions before abort");
6281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6282 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6283 sysctl_tp_shift_cnt, "IU",
6284 "Number of keepalive probes before abort");
6286 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6287 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6288 children = SYSCTL_CHILDREN(oid);
6289 for (i = 0; i < 16; i++) {
6290 snprintf(s, sizeof(s), "%u", i);
6291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6292 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6293 "IU", "TOE retransmit backoff");
6300 vi_sysctls(struct vi_info *vi)
6302 struct sysctl_ctx_list *ctx;
6303 struct sysctl_oid *oid;
6304 struct sysctl_oid_list *children;
6306 ctx = device_get_sysctl_ctx(vi->dev);
6309 * dev.v?(cxgbe|cxl).X.
6311 oid = device_get_sysctl_tree(vi->dev);
6312 children = SYSCTL_CHILDREN(oid);
6314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6315 vi->viid, "VI identifer");
6316 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6317 &vi->nrxq, 0, "# of rx queues");
6318 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6319 &vi->ntxq, 0, "# of tx queues");
6320 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6321 &vi->first_rxq, 0, "index of first rx queue");
6322 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6323 &vi->first_txq, 0, "index of first tx queue");
6324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6325 vi->rss_base, "start of RSS indirection table");
6326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6327 vi->rss_size, "size of RSS indirection table");
6329 if (IS_MAIN_VI(vi)) {
6330 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6331 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6332 "Reserve queue 0 for non-flowid packets");
6336 if (vi->nofldrxq != 0) {
6337 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6339 "# of rx queues for offloaded TCP connections");
6340 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6341 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6342 "index of first TOE rx queue");
6343 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6344 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6345 sysctl_holdoff_tmr_idx_ofld, "I",
6346 "holdoff timer index for TOE queues");
6347 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6348 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6349 sysctl_holdoff_pktc_idx_ofld, "I",
6350 "holdoff packet counter index for TOE queues");
6353 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6354 if (vi->nofldtxq != 0) {
6355 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6357 "# of tx queues for TOE/ETHOFLD");
6358 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6359 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6360 "index of first TOE/ETHOFLD tx queue");
6364 if (vi->nnmrxq != 0) {
6365 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6366 &vi->nnmrxq, 0, "# of netmap rx queues");
6367 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6368 &vi->nnmtxq, 0, "# of netmap tx queues");
6369 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6370 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6371 "index of first netmap rx queue");
6372 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6373 CTLFLAG_RD, &vi->first_nm_txq, 0,
6374 "index of first netmap tx queue");
6378 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6379 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6380 "holdoff timer index");
6381 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6382 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6383 "holdoff packet counter index");
6385 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6386 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6388 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6389 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6394 cxgbe_sysctls(struct port_info *pi)
6396 struct sysctl_ctx_list *ctx;
6397 struct sysctl_oid *oid;
6398 struct sysctl_oid_list *children, *children2;
6399 struct adapter *sc = pi->adapter;
6402 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6404 ctx = device_get_sysctl_ctx(pi->dev);
6409 oid = device_get_sysctl_tree(pi->dev);
6410 children = SYSCTL_CHILDREN(oid);
6412 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6413 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6414 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6415 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6416 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6417 "PHY temperature (in Celsius)");
6418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6419 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6420 "PHY firmware version");
6423 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6424 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6425 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6426 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6427 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6428 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6429 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6430 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6431 "autonegotiation (-1 = not supported)");
6433 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6434 port_top_speed(pi), "max speed (in Gbps)");
6435 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6436 pi->mps_bg_map, "MPS buffer group map");
6437 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6438 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6440 if (sc->flags & IS_VF)
6444 * dev.(cxgbe|cxl).X.tc.
6446 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6447 "Tx scheduler traffic classes (cl_rl)");
6448 children2 = SYSCTL_CHILDREN(oid);
6449 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6450 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6451 "pktsize for per-flow cl-rl (0 means up to the driver )");
6452 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6453 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6454 "burstsize for per-flow cl-rl (0 means up to the driver)");
6455 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6456 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6458 snprintf(name, sizeof(name), "%d", i);
6459 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6460 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6462 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6463 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6464 sysctl_bitfield_8b, "A", "flags");
6465 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6466 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6467 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6468 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6469 sysctl_tc_params, "A", "traffic class parameters");
6473 * dev.cxgbe.X.stats.
6475 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6476 NULL, "port statistics");
6477 children = SYSCTL_CHILDREN(oid);
6478 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6479 &pi->tx_parse_error, 0,
6480 "# of tx packets with invalid length or # of segments");
6482 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6483 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6484 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6485 sysctl_handle_t4_reg64, "QU", desc)
6487 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6488 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6489 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6490 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6491 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6492 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6493 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6494 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6495 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6496 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6497 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6498 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6499 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6500 "# of tx frames in this range",
6501 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6502 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6503 "# of tx frames in this range",
6504 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6505 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6506 "# of tx frames in this range",
6507 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6508 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6509 "# of tx frames in this range",
6510 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6511 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6512 "# of tx frames in this range",
6513 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6514 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6515 "# of tx frames in this range",
6516 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6517 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6518 "# of tx frames in this range",
6519 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6520 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6521 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6522 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6523 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6524 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6525 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6526 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6527 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6528 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6529 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6530 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6531 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6532 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6533 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6534 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6536 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6538 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6541 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6542 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6543 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6544 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6545 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6546 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6547 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6548 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6549 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6550 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6551 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6552 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6553 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6554 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6555 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6556 "# of frames received with bad FCS",
6557 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6558 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6559 "# of frames received with length error",
6560 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6561 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6562 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6563 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6564 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6565 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6566 "# of rx frames in this range",
6567 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6568 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6569 "# of rx frames in this range",
6570 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6571 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6572 "# of rx frames in this range",
6573 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6574 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6575 "# of rx frames in this range",
6576 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6577 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6578 "# of rx frames in this range",
6579 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6580 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6581 "# of rx frames in this range",
6582 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6583 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6584 "# of rx frames in this range",
6585 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6586 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6587 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6588 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6589 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6590 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6591 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6592 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6593 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6594 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6595 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6596 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6597 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6598 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6599 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6600 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6601 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6602 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6603 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6605 #undef SYSCTL_ADD_T4_REG64
6607 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6608 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6609 &pi->stats.name, desc)
6611 /* We get these from port_stats and they may be stale by up to 1s */
6612 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6613 "# drops due to buffer-group 0 overflows");
6614 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6615 "# drops due to buffer-group 1 overflows");
6616 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6617 "# drops due to buffer-group 2 overflows");
6618 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6619 "# drops due to buffer-group 3 overflows");
6620 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6621 "# of buffer-group 0 truncated packets");
6622 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6623 "# of buffer-group 1 truncated packets");
6624 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6625 "# of buffer-group 2 truncated packets");
6626 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6627 "# of buffer-group 3 truncated packets");
6629 #undef SYSCTL_ADD_T4_PORTSTAT
6631 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6632 CTLFLAG_RD, &pi->tx_tls_records,
6633 "# of TLS records transmitted");
6634 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6635 CTLFLAG_RD, &pi->tx_tls_octets,
6636 "# of payload octets in transmitted TLS records");
6637 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6638 CTLFLAG_RD, &pi->rx_tls_records,
6639 "# of TLS records received");
6640 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6641 CTLFLAG_RD, &pi->rx_tls_octets,
6642 "# of payload octets in received TLS records");
6646 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6648 int rc, *i, space = 0;
6651 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6652 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6654 sbuf_printf(&sb, " ");
6655 sbuf_printf(&sb, "%d", *i);
6658 rc = sbuf_finish(&sb);
6664 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6669 rc = sysctl_wire_old_buffer(req, 0);
6673 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6677 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6678 rc = sbuf_finish(sb);
6685 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6690 rc = sysctl_wire_old_buffer(req, 0);
6694 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6698 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6699 rc = sbuf_finish(sb);
6706 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6708 struct port_info *pi = arg1;
6710 struct adapter *sc = pi->adapter;
6714 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6717 /* XXX: magic numbers */
6718 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6720 end_synchronized_op(sc, 0);
6726 rc = sysctl_handle_int(oidp, &v, 0, req);
6731 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6733 struct vi_info *vi = arg1;
6736 val = vi->rsrv_noflowq;
6737 rc = sysctl_handle_int(oidp, &val, 0, req);
6738 if (rc != 0 || req->newptr == NULL)
6741 if ((val >= 1) && (vi->ntxq > 1))
6742 vi->rsrv_noflowq = 1;
6744 vi->rsrv_noflowq = 0;
6750 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6752 struct vi_info *vi = arg1;
6753 struct adapter *sc = vi->pi->adapter;
6755 struct sge_rxq *rxq;
6760 rc = sysctl_handle_int(oidp, &idx, 0, req);
6761 if (rc != 0 || req->newptr == NULL)
6764 if (idx < 0 || idx >= SGE_NTIMERS)
6767 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6772 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6773 for_each_rxq(vi, i, rxq) {
6774 #ifdef atomic_store_rel_8
6775 atomic_store_rel_8(&rxq->iq.intr_params, v);
6777 rxq->iq.intr_params = v;
6782 end_synchronized_op(sc, LOCK_HELD);
6787 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6789 struct vi_info *vi = arg1;
6790 struct adapter *sc = vi->pi->adapter;
6795 rc = sysctl_handle_int(oidp, &idx, 0, req);
6796 if (rc != 0 || req->newptr == NULL)
6799 if (idx < -1 || idx >= SGE_NCOUNTERS)
6802 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6807 if (vi->flags & VI_INIT_DONE)
6808 rc = EBUSY; /* cannot be changed once the queues are created */
6812 end_synchronized_op(sc, LOCK_HELD);
6817 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6819 struct vi_info *vi = arg1;
6820 struct adapter *sc = vi->pi->adapter;
6823 qsize = vi->qsize_rxq;
6825 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6826 if (rc != 0 || req->newptr == NULL)
6829 if (qsize < 128 || (qsize & 7))
6832 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6837 if (vi->flags & VI_INIT_DONE)
6838 rc = EBUSY; /* cannot be changed once the queues are created */
6840 vi->qsize_rxq = qsize;
6842 end_synchronized_op(sc, LOCK_HELD);
6847 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6849 struct vi_info *vi = arg1;
6850 struct adapter *sc = vi->pi->adapter;
6853 qsize = vi->qsize_txq;
6855 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6856 if (rc != 0 || req->newptr == NULL)
6859 if (qsize < 128 || qsize > 65536)
6862 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6867 if (vi->flags & VI_INIT_DONE)
6868 rc = EBUSY; /* cannot be changed once the queues are created */
6870 vi->qsize_txq = qsize;
6872 end_synchronized_op(sc, LOCK_HELD);
6877 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6879 struct port_info *pi = arg1;
6880 struct adapter *sc = pi->adapter;
6881 struct link_config *lc = &pi->link_cfg;
6884 if (req->newptr == NULL) {
6886 static char *bits = "\20\1RX\2TX\3AUTO";
6888 rc = sysctl_wire_old_buffer(req, 0);
6892 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6897 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6898 (lc->requested_fc & PAUSE_AUTONEG), bits);
6900 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6901 PAUSE_RX | PAUSE_AUTONEG), bits);
6903 rc = sbuf_finish(sb);
6909 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6913 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6919 if (s[0] < '0' || s[0] > '9')
6920 return (EINVAL); /* not a number */
6922 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6923 return (EINVAL); /* some other bit is set too */
6925 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6930 lc->requested_fc = n;
6931 fixup_link_config(pi);
6933 rc = apply_link_config(pi);
6934 set_current_media(pi);
6936 end_synchronized_op(sc, 0);
6943 sysctl_fec(SYSCTL_HANDLER_ARGS)
6945 struct port_info *pi = arg1;
6946 struct adapter *sc = pi->adapter;
6947 struct link_config *lc = &pi->link_cfg;
6951 if (req->newptr == NULL) {
6953 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
6955 rc = sysctl_wire_old_buffer(req, 0);
6959 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6964 * Display the requested_fec when the link is down -- the actual
6965 * FEC makes sense only when the link is up.
6968 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
6969 (lc->requested_fec & FEC_AUTO), bits);
6971 sbuf_printf(sb, "%b", lc->requested_fec, bits);
6973 rc = sbuf_finish(sb);
6979 snprintf(s, sizeof(s), "%d",
6980 lc->requested_fec == FEC_AUTO ? -1 :
6981 lc->requested_fec & M_FW_PORT_CAP32_FEC);
6983 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6987 n = strtol(&s[0], NULL, 0);
6988 if (n < 0 || n & FEC_AUTO)
6991 if (n & ~M_FW_PORT_CAP32_FEC)
6992 return (EINVAL);/* some other bit is set too */
6994 return (EINVAL);/* one bit can be set at most */
6997 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7002 old = lc->requested_fec;
7004 lc->requested_fec = FEC_AUTO;
7006 lc->requested_fec = FEC_NONE;
7008 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
7013 lc->requested_fec = n;
7015 fixup_link_config(pi);
7016 if (pi->up_vis > 0) {
7017 rc = apply_link_config(pi);
7019 lc->requested_fec = old;
7020 if (rc == FW_EPROTO)
7026 end_synchronized_op(sc, 0);
7033 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7035 struct port_info *pi = arg1;
7036 struct adapter *sc = pi->adapter;
7037 struct link_config *lc = &pi->link_cfg;
7040 if (lc->supported & FW_PORT_CAP32_ANEG)
7041 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7044 rc = sysctl_handle_int(oidp, &val, 0, req);
7045 if (rc != 0 || req->newptr == NULL)
7048 val = AUTONEG_DISABLE;
7050 val = AUTONEG_ENABLE;
7054 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7059 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
7063 lc->requested_aneg = val;
7064 fixup_link_config(pi);
7066 rc = apply_link_config(pi);
7067 set_current_media(pi);
7070 end_synchronized_op(sc, 0);
7075 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7077 struct adapter *sc = arg1;
7081 val = t4_read_reg64(sc, reg);
7083 return (sysctl_handle_64(oidp, &val, 0, req));
7087 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7089 struct adapter *sc = arg1;
7091 uint32_t param, val;
7093 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7096 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7097 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7098 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7099 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7100 end_synchronized_op(sc, 0);
7104 /* unknown is returned as 0 but we display -1 in that case */
7105 t = val == 0 ? -1 : val;
7107 rc = sysctl_handle_int(oidp, &t, 0, req);
7112 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7114 struct adapter *sc = arg1;
7117 uint32_t param, val;
7119 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7122 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7123 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7124 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7125 end_synchronized_op(sc, 0);
7129 rc = sysctl_wire_old_buffer(req, 0);
7133 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7137 if (val == 0xffffffff) {
7138 /* Only debug and custom firmwares report load averages. */
7139 sbuf_printf(sb, "not available");
7141 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7142 (val >> 16) & 0xff);
7144 rc = sbuf_finish(sb);
7151 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7153 struct adapter *sc = arg1;
7156 uint16_t incr[NMTUS][NCCTRL_WIN];
7157 static const char *dec_fac[] = {
7158 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7162 rc = sysctl_wire_old_buffer(req, 0);
7166 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7170 t4_read_cong_tbl(sc, incr);
7172 for (i = 0; i < NCCTRL_WIN; ++i) {
7173 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7174 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7175 incr[5][i], incr[6][i], incr[7][i]);
7176 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7177 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7178 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7179 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7182 rc = sbuf_finish(sb);
7188 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7189 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7190 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7191 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7195 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7197 struct adapter *sc = arg1;
7199 int rc, i, n, qid = arg2;
7202 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7204 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7205 ("%s: bad qid %d\n", __func__, qid));
7207 if (qid < CIM_NUM_IBQ) {
7210 n = 4 * CIM_IBQ_SIZE;
7211 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7212 rc = t4_read_cim_ibq(sc, qid, buf, n);
7214 /* outbound queue */
7217 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7218 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7219 rc = t4_read_cim_obq(sc, qid, buf, n);
7226 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7228 rc = sysctl_wire_old_buffer(req, 0);
7232 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7238 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7239 for (i = 0, p = buf; i < n; i += 16, p += 4)
7240 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7243 rc = sbuf_finish(sb);
7251 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7255 sbuf_printf(sb, "Status Data PC%s",
7256 cfg & F_UPDBGLACAPTPCONLY ? "" :
7257 " LS0Stat LS0Addr LS0Data");
7259 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7260 if (cfg & F_UPDBGLACAPTPCONLY) {
7261 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7263 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7264 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7265 p[4] & 0xff, p[5] >> 8);
7266 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7267 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7268 p[1] & 0xf, p[2] >> 4);
7271 "\n %02x %x%07x %x%07x %08x %08x "
7273 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7274 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7281 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7285 sbuf_printf(sb, "Status Inst Data PC%s",
7286 cfg & F_UPDBGLACAPTPCONLY ? "" :
7287 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7289 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7290 if (cfg & F_UPDBGLACAPTPCONLY) {
7291 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7292 p[3] & 0xff, p[2], p[1], p[0]);
7293 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7294 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7295 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7296 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7297 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7298 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7301 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7302 "%08x %08x %08x %08x %08x %08x",
7303 (p[9] >> 16) & 0xff,
7304 p[9] & 0xffff, p[8] >> 16,
7305 p[8] & 0xffff, p[7] >> 16,
7306 p[7] & 0xffff, p[6] >> 16,
7307 p[2], p[1], p[0], p[5], p[4], p[3]);
7313 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
7318 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7322 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7323 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7328 rc = -t4_cim_read_la(sc, buf, NULL);
7331 if (chip_id(sc) < CHELSIO_T6)
7332 sbuf_cim_la4(sc, sb, buf, cfg);
7334 sbuf_cim_la6(sc, sb, buf, cfg);
7342 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7344 struct adapter *sc = arg1;
7348 rc = sysctl_wire_old_buffer(req, 0);
7351 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7355 rc = sbuf_cim_la(sc, sb, M_WAITOK);
7357 rc = sbuf_finish(sb);
7363 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose)
7368 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7370 rc = sbuf_cim_la(sc, &sb, M_NOWAIT);
7372 rc = sbuf_finish(&sb);
7374 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s",
7375 device_get_nameunit(sc->dev), sbuf_data(&sb));
7383 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7385 struct adapter *sc = arg1;
7391 rc = sysctl_wire_old_buffer(req, 0);
7395 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7399 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7402 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7405 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7406 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7410 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7411 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7412 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7413 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7414 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7415 (p[1] >> 2) | ((p[2] & 3) << 30),
7416 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7420 rc = sbuf_finish(sb);
7427 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7429 struct adapter *sc = arg1;
7435 rc = sysctl_wire_old_buffer(req, 0);
7439 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7443 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7446 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7449 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7450 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7451 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7452 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7453 p[4], p[3], p[2], p[1], p[0]);
7456 sbuf_printf(sb, "\n\nCntl ID Data");
7457 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7458 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7459 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7462 rc = sbuf_finish(sb);
7469 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7471 struct adapter *sc = arg1;
7474 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7475 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7476 uint16_t thres[CIM_NUM_IBQ];
7477 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7478 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7479 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7481 cim_num_obq = sc->chip_params->cim_num_obq;
7483 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7484 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7486 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7487 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7489 nq = CIM_NUM_IBQ + cim_num_obq;
7491 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7493 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7497 t4_read_cimq_cfg(sc, base, size, thres);
7499 rc = sysctl_wire_old_buffer(req, 0);
7503 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7508 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7510 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7511 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7512 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7513 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7514 G_QUEREMFLITS(p[2]) * 16);
7515 for ( ; i < nq; i++, p += 4, wr += 2)
7516 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7517 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7518 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7519 G_QUEREMFLITS(p[2]) * 16);
7521 rc = sbuf_finish(sb);
7528 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7530 struct adapter *sc = arg1;
7533 struct tp_cpl_stats stats;
7535 rc = sysctl_wire_old_buffer(req, 0);
7539 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7543 mtx_lock(&sc->reg_lock);
7544 t4_tp_get_cpl_stats(sc, &stats, 0);
7545 mtx_unlock(&sc->reg_lock);
7547 if (sc->chip_params->nchan > 2) {
7548 sbuf_printf(sb, " channel 0 channel 1"
7549 " channel 2 channel 3");
7550 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7551 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7552 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7553 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7555 sbuf_printf(sb, " channel 0 channel 1");
7556 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7557 stats.req[0], stats.req[1]);
7558 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7559 stats.rsp[0], stats.rsp[1]);
7562 rc = sbuf_finish(sb);
7569 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7571 struct adapter *sc = arg1;
7574 struct tp_usm_stats stats;
7576 rc = sysctl_wire_old_buffer(req, 0);
7580 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7584 t4_get_usm_stats(sc, &stats, 1);
7586 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7587 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7588 sbuf_printf(sb, "Drops: %u", stats.drops);
7590 rc = sbuf_finish(sb);
7596 static const char * const devlog_level_strings[] = {
7597 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7598 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7599 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7600 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7601 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7602 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7605 static const char * const devlog_facility_strings[] = {
7606 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7607 [FW_DEVLOG_FACILITY_CF] = "CF",
7608 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7609 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7610 [FW_DEVLOG_FACILITY_RES] = "RES",
7611 [FW_DEVLOG_FACILITY_HW] = "HW",
7612 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7613 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7614 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7615 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7616 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7617 [FW_DEVLOG_FACILITY_VI] = "VI",
7618 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7619 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7620 [FW_DEVLOG_FACILITY_TM] = "TM",
7621 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7622 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7623 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7624 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7625 [FW_DEVLOG_FACILITY_RI] = "RI",
7626 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7627 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7628 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7629 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7630 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7634 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
7636 int i, j, rc, nentries, first = 0;
7637 struct devlog_params *dparams = &sc->params.devlog;
7638 struct fw_devlog_e *buf, *e;
7639 uint64_t ftstamp = UINT64_MAX;
7641 if (dparams->addr == 0)
7644 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7645 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
7649 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7653 nentries = dparams->size / sizeof(struct fw_devlog_e);
7654 for (i = 0; i < nentries; i++) {
7657 if (e->timestamp == 0)
7660 e->timestamp = be64toh(e->timestamp);
7661 e->seqno = be32toh(e->seqno);
7662 for (j = 0; j < 8; j++)
7663 e->params[j] = be32toh(e->params[j]);
7665 if (e->timestamp < ftstamp) {
7666 ftstamp = e->timestamp;
7671 if (buf[first].timestamp == 0)
7672 goto done; /* nothing in the log */
7674 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7675 "Seq#", "Tstamp", "Level", "Facility", "Message");
7680 if (e->timestamp == 0)
7683 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7684 e->seqno, e->timestamp,
7685 (e->level < nitems(devlog_level_strings) ?
7686 devlog_level_strings[e->level] : "UNKNOWN"),
7687 (e->facility < nitems(devlog_facility_strings) ?
7688 devlog_facility_strings[e->facility] : "UNKNOWN"));
7689 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7690 e->params[2], e->params[3], e->params[4],
7691 e->params[5], e->params[6], e->params[7]);
7693 if (++i == nentries)
7695 } while (i != first);
7702 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7704 struct adapter *sc = arg1;
7708 rc = sysctl_wire_old_buffer(req, 0);
7711 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7715 rc = sbuf_devlog(sc, sb, M_WAITOK);
7717 rc = sbuf_finish(sb);
7723 t4_os_dump_devlog(struct adapter *sc)
7728 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7730 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
7732 rc = sbuf_finish(&sb);
7734 log(LOG_DEBUG, "%s: device log follows.\n%s",
7735 device_get_nameunit(sc->dev), sbuf_data(&sb));
7742 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7744 struct adapter *sc = arg1;
7747 struct tp_fcoe_stats stats[MAX_NCHAN];
7748 int i, nchan = sc->chip_params->nchan;
7750 rc = sysctl_wire_old_buffer(req, 0);
7754 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7758 for (i = 0; i < nchan; i++)
7759 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7762 sbuf_printf(sb, " channel 0 channel 1"
7763 " channel 2 channel 3");
7764 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7765 stats[0].octets_ddp, stats[1].octets_ddp,
7766 stats[2].octets_ddp, stats[3].octets_ddp);
7767 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7768 stats[0].frames_ddp, stats[1].frames_ddp,
7769 stats[2].frames_ddp, stats[3].frames_ddp);
7770 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7771 stats[0].frames_drop, stats[1].frames_drop,
7772 stats[2].frames_drop, stats[3].frames_drop);
7774 sbuf_printf(sb, " channel 0 channel 1");
7775 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7776 stats[0].octets_ddp, stats[1].octets_ddp);
7777 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7778 stats[0].frames_ddp, stats[1].frames_ddp);
7779 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7780 stats[0].frames_drop, stats[1].frames_drop);
7783 rc = sbuf_finish(sb);
7790 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7792 struct adapter *sc = arg1;
7795 unsigned int map, kbps, ipg, mode;
7796 unsigned int pace_tab[NTX_SCHED];
7798 rc = sysctl_wire_old_buffer(req, 0);
7802 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7806 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7807 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7808 t4_read_pace_tbl(sc, pace_tab);
7810 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
7811 "Class IPG (0.1 ns) Flow IPG (us)");
7813 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7814 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7815 sbuf_printf(sb, "\n %u %-5s %u ", i,
7816 (mode & (1 << i)) ? "flow" : "class", map & 3);
7818 sbuf_printf(sb, "%9u ", kbps);
7820 sbuf_printf(sb, " disabled ");
7823 sbuf_printf(sb, "%13u ", ipg);
7825 sbuf_printf(sb, " disabled ");
7828 sbuf_printf(sb, "%10u", pace_tab[i]);
7830 sbuf_printf(sb, " disabled");
7833 rc = sbuf_finish(sb);
7840 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7842 struct adapter *sc = arg1;
7846 struct lb_port_stats s[2];
7847 static const char *stat_name[] = {
7848 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7849 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7850 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7851 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7852 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7853 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7854 "BG2FramesTrunc:", "BG3FramesTrunc:"
7857 rc = sysctl_wire_old_buffer(req, 0);
7861 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7865 memset(s, 0, sizeof(s));
7867 for (i = 0; i < sc->chip_params->nchan; i += 2) {
7868 t4_get_lb_stats(sc, i, &s[0]);
7869 t4_get_lb_stats(sc, i + 1, &s[1]);
7873 sbuf_printf(sb, "%s Loopback %u"
7874 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7876 for (j = 0; j < nitems(stat_name); j++)
7877 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7881 rc = sbuf_finish(sb);
7888 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7891 struct port_info *pi = arg1;
7892 struct link_config *lc = &pi->link_cfg;
7895 rc = sysctl_wire_old_buffer(req, 0);
7898 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7902 if (lc->link_ok || lc->link_down_rc == 255)
7903 sbuf_printf(sb, "n/a");
7905 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7907 rc = sbuf_finish(sb);
7920 mem_desc_cmp(const void *a, const void *b)
7922 return ((const struct mem_desc *)a)->base -
7923 ((const struct mem_desc *)b)->base;
7927 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7935 size = to - from + 1;
7939 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7940 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7944 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7946 struct adapter *sc = arg1;
7949 uint32_t lo, hi, used, alloc;
7950 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7951 static const char *region[] = {
7952 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7953 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7954 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7955 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7956 "RQUDP region:", "PBL region:", "TXPBL region:",
7957 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7958 "On-chip queues:", "TLS keys:",
7960 struct mem_desc avail[4];
7961 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
7962 struct mem_desc *md = mem;
7964 rc = sysctl_wire_old_buffer(req, 0);
7968 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7972 for (i = 0; i < nitems(mem); i++) {
7977 /* Find and sort the populated memory ranges */
7979 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7980 if (lo & F_EDRAM0_ENABLE) {
7981 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7982 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7983 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7987 if (lo & F_EDRAM1_ENABLE) {
7988 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7989 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7990 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7994 if (lo & F_EXT_MEM_ENABLE) {
7995 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7996 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7997 avail[i].limit = avail[i].base +
7998 (G_EXT_MEM_SIZE(hi) << 20);
7999 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
8002 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
8003 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
8004 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
8005 avail[i].limit = avail[i].base +
8006 (G_EXT_MEM1_SIZE(hi) << 20);
8010 if (!i) /* no memory available */
8012 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8014 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8015 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8016 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8017 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8018 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8019 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8020 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8021 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8022 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8024 /* the next few have explicit upper bounds */
8025 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8026 md->limit = md->base - 1 +
8027 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8028 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8031 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8032 md->limit = md->base - 1 +
8033 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8034 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8037 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8038 if (chip_id(sc) <= CHELSIO_T5)
8039 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8041 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8045 md->idx = nitems(region); /* hide it */
8049 #define ulp_region(reg) \
8050 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8051 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8053 ulp_region(RX_ISCSI);
8054 ulp_region(RX_TDDP);
8056 ulp_region(RX_STAG);
8058 ulp_region(RX_RQUDP);
8064 md->idx = nitems(region);
8067 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8068 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8071 if (sge_ctrl & F_VFIFO_ENABLE)
8072 size = G_DBVFIFO_SIZE(fifo_size);
8074 size = G_T6_DBVFIFO_SIZE(fifo_size);
8077 md->base = G_BASEADDR(t4_read_reg(sc,
8078 A_SGE_DBVFIFO_BADDR));
8079 md->limit = md->base + (size << 2) - 1;
8084 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8087 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8091 md->base = sc->vres.ocq.start;
8092 if (sc->vres.ocq.size)
8093 md->limit = md->base + sc->vres.ocq.size - 1;
8095 md->idx = nitems(region); /* hide it */
8098 md->base = sc->vres.key.start;
8099 if (sc->vres.key.size)
8100 md->limit = md->base + sc->vres.key.size - 1;
8102 md->idx = nitems(region); /* hide it */
8105 /* add any address-space holes, there can be up to 3 */
8106 for (n = 0; n < i - 1; n++)
8107 if (avail[n].limit < avail[n + 1].base)
8108 (md++)->base = avail[n].limit;
8110 (md++)->base = avail[n].limit;
8113 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8115 for (lo = 0; lo < i; lo++)
8116 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8117 avail[lo].limit - 1);
8119 sbuf_printf(sb, "\n");
8120 for (i = 0; i < n; i++) {
8121 if (mem[i].idx >= nitems(region))
8122 continue; /* skip holes */
8124 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8125 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8129 sbuf_printf(sb, "\n");
8130 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8131 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8132 mem_region_show(sb, "uP RAM:", lo, hi);
8134 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8135 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8136 mem_region_show(sb, "uP Extmem2:", lo, hi);
8138 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8139 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8141 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8142 (lo & F_PMRXNUMCHN) ? 2 : 1);
8144 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8145 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8146 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8148 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8149 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8150 sbuf_printf(sb, "%u p-structs\n",
8151 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8153 for (i = 0; i < 4; i++) {
8154 if (chip_id(sc) > CHELSIO_T5)
8155 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8157 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8159 used = G_T5_USED(lo);
8160 alloc = G_T5_ALLOC(lo);
8163 alloc = G_ALLOC(lo);
8165 /* For T6 these are MAC buffer groups */
8166 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8169 for (i = 0; i < sc->chip_params->nchan; i++) {
8170 if (chip_id(sc) > CHELSIO_T5)
8171 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8173 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8175 used = G_T5_USED(lo);
8176 alloc = G_T5_ALLOC(lo);
8179 alloc = G_ALLOC(lo);
8181 /* For T6 these are MAC buffer groups */
8183 "\nLoopback %d using %u pages out of %u allocated",
8187 rc = sbuf_finish(sb);
8194 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8198 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8202 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8204 struct adapter *sc = arg1;
8208 MPASS(chip_id(sc) <= CHELSIO_T5);
8210 rc = sysctl_wire_old_buffer(req, 0);
8214 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8219 "Idx Ethernet address Mask Vld Ports PF"
8220 " VF Replication P0 P1 P2 P3 ML");
8221 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8222 uint64_t tcamx, tcamy, mask;
8223 uint32_t cls_lo, cls_hi;
8224 uint8_t addr[ETHER_ADDR_LEN];
8226 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8227 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8230 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8231 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8232 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8233 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8234 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8235 addr[3], addr[4], addr[5], (uintmax_t)mask,
8236 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8237 G_PORTMAP(cls_hi), G_PF(cls_lo),
8238 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8240 if (cls_lo & F_REPLICATE) {
8241 struct fw_ldst_cmd ldst_cmd;
8243 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8244 ldst_cmd.op_to_addrspace =
8245 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8246 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8247 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8248 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8249 ldst_cmd.u.mps.rplc.fid_idx =
8250 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8251 V_FW_LDST_CMD_IDX(i));
8253 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8257 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8258 sizeof(ldst_cmd), &ldst_cmd);
8259 end_synchronized_op(sc, 0);
8262 sbuf_printf(sb, "%36d", rc);
8265 sbuf_printf(sb, " %08x %08x %08x %08x",
8266 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8267 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8268 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8269 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8272 sbuf_printf(sb, "%36s", "");
8274 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8275 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8276 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8280 (void) sbuf_finish(sb);
8282 rc = sbuf_finish(sb);
8289 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8291 struct adapter *sc = arg1;
8295 MPASS(chip_id(sc) > CHELSIO_T5);
8297 rc = sysctl_wire_old_buffer(req, 0);
8301 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8305 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8306 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8308 " P0 P1 P2 P3 ML\n");
8310 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8311 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8313 uint64_t tcamx, tcamy, val, mask;
8314 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8315 uint8_t addr[ETHER_ADDR_LEN];
8317 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8319 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8321 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8322 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8323 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8324 tcamy = G_DMACH(val) << 32;
8325 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8326 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8327 lookup_type = G_DATALKPTYPE(data2);
8328 port_num = G_DATAPORTNUM(data2);
8329 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8330 /* Inner header VNI */
8331 vniy = ((data2 & F_DATAVIDH2) << 23) |
8332 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8333 dip_hit = data2 & F_DATADIPHIT;
8338 vlan_vld = data2 & F_DATAVIDH2;
8339 ivlan = G_VIDL(val);
8342 ctl |= V_CTLXYBITSEL(1);
8343 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8344 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8345 tcamx = G_DMACH(val) << 32;
8346 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8347 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8348 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8349 /* Inner header VNI mask */
8350 vnix = ((data2 & F_DATAVIDH2) << 23) |
8351 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8357 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8359 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8360 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8362 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8363 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8364 "%012jx %06x %06x - - %3c"
8365 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8366 addr[1], addr[2], addr[3], addr[4], addr[5],
8367 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8368 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8369 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8370 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8372 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8373 "%012jx - - ", i, addr[0], addr[1],
8374 addr[2], addr[3], addr[4], addr[5],
8378 sbuf_printf(sb, "%4u Y ", ivlan);
8380 sbuf_printf(sb, " - N ");
8382 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8383 lookup_type ? 'I' : 'O', port_num,
8384 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8385 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8386 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8390 if (cls_lo & F_T6_REPLICATE) {
8391 struct fw_ldst_cmd ldst_cmd;
8393 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8394 ldst_cmd.op_to_addrspace =
8395 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8396 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8397 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8398 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8399 ldst_cmd.u.mps.rplc.fid_idx =
8400 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8401 V_FW_LDST_CMD_IDX(i));
8403 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8407 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8408 sizeof(ldst_cmd), &ldst_cmd);
8409 end_synchronized_op(sc, 0);
8412 sbuf_printf(sb, "%72d", rc);
8415 sbuf_printf(sb, " %08x %08x %08x %08x"
8416 " %08x %08x %08x %08x",
8417 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8418 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8419 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8420 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8421 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8422 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8423 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8424 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8427 sbuf_printf(sb, "%72s", "");
8429 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8430 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8431 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8432 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8436 (void) sbuf_finish(sb);
8438 rc = sbuf_finish(sb);
8445 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8447 struct adapter *sc = arg1;
8450 uint16_t mtus[NMTUS];
8452 rc = sysctl_wire_old_buffer(req, 0);
8456 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8460 t4_read_mtu_tbl(sc, mtus, NULL);
8462 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8463 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8464 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8465 mtus[14], mtus[15]);
8467 rc = sbuf_finish(sb);
8474 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8476 struct adapter *sc = arg1;
8479 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8480 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8481 static const char *tx_stats[MAX_PM_NSTATS] = {
8482 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8483 "Tx FIFO wait", NULL, "Tx latency"
8485 static const char *rx_stats[MAX_PM_NSTATS] = {
8486 "Read:", "Write bypass:", "Write mem:", "Flush:",
8487 "Rx FIFO wait", NULL, "Rx latency"
8490 rc = sysctl_wire_old_buffer(req, 0);
8494 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8498 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8499 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8501 sbuf_printf(sb, " Tx pcmds Tx bytes");
8502 for (i = 0; i < 4; i++) {
8503 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8507 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8508 for (i = 0; i < 4; i++) {
8509 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8513 if (chip_id(sc) > CHELSIO_T5) {
8515 "\n Total wait Total occupancy");
8516 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8518 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8522 MPASS(i < nitems(tx_stats));
8525 "\n Reads Total wait");
8526 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8528 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8532 rc = sbuf_finish(sb);
8539 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8541 struct adapter *sc = arg1;
8544 struct tp_rdma_stats stats;
8546 rc = sysctl_wire_old_buffer(req, 0);
8550 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8554 mtx_lock(&sc->reg_lock);
8555 t4_tp_get_rdma_stats(sc, &stats, 0);
8556 mtx_unlock(&sc->reg_lock);
8558 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8559 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8561 rc = sbuf_finish(sb);
8568 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8570 struct adapter *sc = arg1;
8573 struct tp_tcp_stats v4, v6;
8575 rc = sysctl_wire_old_buffer(req, 0);
8579 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8583 mtx_lock(&sc->reg_lock);
8584 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8585 mtx_unlock(&sc->reg_lock);
8589 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8590 v4.tcp_out_rsts, v6.tcp_out_rsts);
8591 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8592 v4.tcp_in_segs, v6.tcp_in_segs);
8593 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8594 v4.tcp_out_segs, v6.tcp_out_segs);
8595 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8596 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8598 rc = sbuf_finish(sb);
8605 sysctl_tids(SYSCTL_HANDLER_ARGS)
8607 struct adapter *sc = arg1;
8610 struct tid_info *t = &sc->tids;
8612 rc = sysctl_wire_old_buffer(req, 0);
8616 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8621 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8626 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
8627 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
8631 sbuf_printf(sb, "TID range: ");
8632 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8635 if (chip_id(sc) <= CHELSIO_T5) {
8636 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8637 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8639 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8640 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8644 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
8645 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8647 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
8648 sbuf_printf(sb, ", in use: %u\n",
8649 atomic_load_acq_int(&t->tids_in_use));
8653 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8654 t->stid_base + t->nstids - 1, t->stids_in_use);
8658 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
8659 t->ftid_end, t->ftids_in_use);
8663 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8664 t->etid_base + t->netids - 1, t->etids_in_use);
8667 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8668 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8669 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8671 rc = sbuf_finish(sb);
8678 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8680 struct adapter *sc = arg1;
8683 struct tp_err_stats stats;
8685 rc = sysctl_wire_old_buffer(req, 0);
8689 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8693 mtx_lock(&sc->reg_lock);
8694 t4_tp_get_err_stats(sc, &stats, 0);
8695 mtx_unlock(&sc->reg_lock);
8697 if (sc->chip_params->nchan > 2) {
8698 sbuf_printf(sb, " channel 0 channel 1"
8699 " channel 2 channel 3\n");
8700 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8701 stats.mac_in_errs[0], stats.mac_in_errs[1],
8702 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8703 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8704 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8705 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8706 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8707 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8708 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8709 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8710 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8711 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8712 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8713 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8714 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8715 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8716 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8717 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8718 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8719 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8720 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8721 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8722 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8723 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8725 sbuf_printf(sb, " channel 0 channel 1\n");
8726 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8727 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8728 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8729 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8730 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8731 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8732 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8733 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8734 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8735 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8736 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8737 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8738 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8739 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8740 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8741 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8744 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8745 stats.ofld_no_neigh, stats.ofld_cong_defer);
8747 rc = sbuf_finish(sb);
8754 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8756 struct adapter *sc = arg1;
8757 struct tp_params *tpp = &sc->params.tp;
8761 mask = tpp->la_mask >> 16;
8762 rc = sysctl_handle_int(oidp, &mask, 0, req);
8763 if (rc != 0 || req->newptr == NULL)
8767 tpp->la_mask = mask << 16;
8768 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8780 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8786 uint64_t mask = (1ULL << f->width) - 1;
8787 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8788 ((uintmax_t)v >> f->start) & mask);
8790 if (line_size + len >= 79) {
8792 sbuf_printf(sb, "\n ");
8794 sbuf_printf(sb, "%s ", buf);
8795 line_size += len + 1;
8798 sbuf_printf(sb, "\n");
8801 static const struct field_desc tp_la0[] = {
8802 { "RcfOpCodeOut", 60, 4 },
8804 { "WcfState", 52, 4 },
8805 { "RcfOpcSrcOut", 50, 2 },
8806 { "CRxError", 49, 1 },
8807 { "ERxError", 48, 1 },
8808 { "SanityFailed", 47, 1 },
8809 { "SpuriousMsg", 46, 1 },
8810 { "FlushInputMsg", 45, 1 },
8811 { "FlushInputCpl", 44, 1 },
8812 { "RssUpBit", 43, 1 },
8813 { "RssFilterHit", 42, 1 },
8815 { "InitTcb", 31, 1 },
8816 { "LineNumber", 24, 7 },
8818 { "EdataOut", 22, 1 },
8820 { "CdataOut", 20, 1 },
8821 { "EreadPdu", 19, 1 },
8822 { "CreadPdu", 18, 1 },
8823 { "TunnelPkt", 17, 1 },
8824 { "RcfPeerFin", 16, 1 },
8825 { "RcfReasonOut", 12, 4 },
8826 { "TxCchannel", 10, 2 },
8827 { "RcfTxChannel", 8, 2 },
8828 { "RxEchannel", 6, 2 },
8829 { "RcfRxChannel", 5, 1 },
8830 { "RcfDataOutSrdy", 4, 1 },
8832 { "RxOoDvld", 2, 1 },
8833 { "RxCongestion", 1, 1 },
8834 { "TxCongestion", 0, 1 },
8838 static const struct field_desc tp_la1[] = {
8839 { "CplCmdIn", 56, 8 },
8840 { "CplCmdOut", 48, 8 },
8841 { "ESynOut", 47, 1 },
8842 { "EAckOut", 46, 1 },
8843 { "EFinOut", 45, 1 },
8844 { "ERstOut", 44, 1 },
8849 { "DataIn", 39, 1 },
8850 { "DataInVld", 38, 1 },
8852 { "RxBufEmpty", 36, 1 },
8854 { "RxFbCongestion", 34, 1 },
8855 { "TxFbCongestion", 33, 1 },
8856 { "TxPktSumSrdy", 32, 1 },
8857 { "RcfUlpType", 28, 4 },
8859 { "Ebypass", 26, 1 },
8861 { "Static0", 24, 1 },
8863 { "Cbypass", 22, 1 },
8865 { "CPktOut", 20, 1 },
8866 { "RxPagePoolFull", 18, 2 },
8867 { "RxLpbkPkt", 17, 1 },
8868 { "TxLpbkPkt", 16, 1 },
8869 { "RxVfValid", 15, 1 },
8870 { "SynLearned", 14, 1 },
8871 { "SetDelEntry", 13, 1 },
8872 { "SetInvEntry", 12, 1 },
8873 { "CpcmdDvld", 11, 1 },
8874 { "CpcmdSave", 10, 1 },
8875 { "RxPstructsFull", 8, 2 },
8876 { "EpcmdDvld", 7, 1 },
8877 { "EpcmdFlush", 6, 1 },
8878 { "EpcmdTrimPrefix", 5, 1 },
8879 { "EpcmdTrimPostfix", 4, 1 },
8880 { "ERssIp4Pkt", 3, 1 },
8881 { "ERssIp6Pkt", 2, 1 },
8882 { "ERssTcpUdpPkt", 1, 1 },
8883 { "ERssFceFipPkt", 0, 1 },
8887 static const struct field_desc tp_la2[] = {
8888 { "CplCmdIn", 56, 8 },
8889 { "MpsVfVld", 55, 1 },
8896 { "DataIn", 39, 1 },
8897 { "DataInVld", 38, 1 },
8899 { "RxBufEmpty", 36, 1 },
8901 { "RxFbCongestion", 34, 1 },
8902 { "TxFbCongestion", 33, 1 },
8903 { "TxPktSumSrdy", 32, 1 },
8904 { "RcfUlpType", 28, 4 },
8906 { "Ebypass", 26, 1 },
8908 { "Static0", 24, 1 },
8910 { "Cbypass", 22, 1 },
8912 { "CPktOut", 20, 1 },
8913 { "RxPagePoolFull", 18, 2 },
8914 { "RxLpbkPkt", 17, 1 },
8915 { "TxLpbkPkt", 16, 1 },
8916 { "RxVfValid", 15, 1 },
8917 { "SynLearned", 14, 1 },
8918 { "SetDelEntry", 13, 1 },
8919 { "SetInvEntry", 12, 1 },
8920 { "CpcmdDvld", 11, 1 },
8921 { "CpcmdSave", 10, 1 },
8922 { "RxPstructsFull", 8, 2 },
8923 { "EpcmdDvld", 7, 1 },
8924 { "EpcmdFlush", 6, 1 },
8925 { "EpcmdTrimPrefix", 5, 1 },
8926 { "EpcmdTrimPostfix", 4, 1 },
8927 { "ERssIp4Pkt", 3, 1 },
8928 { "ERssIp6Pkt", 2, 1 },
8929 { "ERssTcpUdpPkt", 1, 1 },
8930 { "ERssFceFipPkt", 0, 1 },
8935 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8938 field_desc_show(sb, *p, tp_la0);
8942 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8946 sbuf_printf(sb, "\n");
8947 field_desc_show(sb, p[0], tp_la0);
8948 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8949 field_desc_show(sb, p[1], tp_la0);
8953 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8957 sbuf_printf(sb, "\n");
8958 field_desc_show(sb, p[0], tp_la0);
8959 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8960 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8964 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8966 struct adapter *sc = arg1;
8971 void (*show_func)(struct sbuf *, uint64_t *, int);
8973 rc = sysctl_wire_old_buffer(req, 0);
8977 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8981 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8983 t4_tp_read_la(sc, buf, NULL);
8986 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8989 show_func = tp_la_show2;
8993 show_func = tp_la_show3;
8997 show_func = tp_la_show;
9000 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
9001 (*show_func)(sb, p, i);
9003 rc = sbuf_finish(sb);
9010 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9012 struct adapter *sc = arg1;
9015 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9017 rc = sysctl_wire_old_buffer(req, 0);
9021 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9025 t4_get_chan_txrate(sc, nrate, orate);
9027 if (sc->chip_params->nchan > 2) {
9028 sbuf_printf(sb, " channel 0 channel 1"
9029 " channel 2 channel 3\n");
9030 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9031 nrate[0], nrate[1], nrate[2], nrate[3]);
9032 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9033 orate[0], orate[1], orate[2], orate[3]);
9035 sbuf_printf(sb, " channel 0 channel 1\n");
9036 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9037 nrate[0], nrate[1]);
9038 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9039 orate[0], orate[1]);
9042 rc = sbuf_finish(sb);
9049 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9051 struct adapter *sc = arg1;
9056 rc = sysctl_wire_old_buffer(req, 0);
9060 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9064 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9067 t4_ulprx_read_la(sc, buf);
9070 sbuf_printf(sb, " Pcmd Type Message"
9072 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9073 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9074 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9077 rc = sbuf_finish(sb);
9084 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9086 struct adapter *sc = arg1;
9090 MPASS(chip_id(sc) >= CHELSIO_T5);
9092 rc = sysctl_wire_old_buffer(req, 0);
9096 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9100 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9101 if (G_STATSOURCE_T5(v) == 7) {
9104 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9106 sbuf_printf(sb, "total %d, incomplete %d",
9107 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9108 t4_read_reg(sc, A_SGE_STAT_MATCH));
9109 } else if (mode == 1) {
9110 sbuf_printf(sb, "total %d, data overflow %d",
9111 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9112 t4_read_reg(sc, A_SGE_STAT_MATCH));
9114 sbuf_printf(sb, "unknown mode %d", mode);
9117 rc = sbuf_finish(sb);
9124 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9126 struct adapter *sc = arg1;
9127 enum cpu_sets op = arg2;
9132 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9135 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9139 rc = sysctl_wire_old_buffer(req, 0);
9143 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9148 sbuf_printf(sb, "%d ", i);
9149 rc = sbuf_finish(sb);
9157 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9159 struct adapter *sc = arg1;
9160 int *old_ports, *new_ports;
9161 int i, new_count, rc;
9163 if (req->newptr == NULL && req->oldptr == NULL)
9164 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9165 sizeof(sc->tt.tls_rx_ports[0])));
9167 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9171 if (sc->tt.num_tls_rx_ports == 0) {
9173 rc = SYSCTL_OUT(req, &i, sizeof(i));
9175 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9176 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9177 if (rc == 0 && req->newptr != NULL) {
9178 new_count = req->newlen / sizeof(new_ports[0]);
9179 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9181 rc = SYSCTL_IN(req, new_ports, new_count *
9182 sizeof(new_ports[0]));
9186 /* Allow setting to a single '-1' to clear the list. */
9187 if (new_count == 1 && new_ports[0] == -1) {
9189 old_ports = sc->tt.tls_rx_ports;
9190 sc->tt.tls_rx_ports = NULL;
9191 sc->tt.num_tls_rx_ports = 0;
9193 free(old_ports, M_CXGBE);
9195 for (i = 0; i < new_count; i++) {
9196 if (new_ports[i] < 1 ||
9197 new_ports[i] > IPPORT_MAX) {
9204 old_ports = sc->tt.tls_rx_ports;
9205 sc->tt.tls_rx_ports = new_ports;
9206 sc->tt.num_tls_rx_ports = new_count;
9208 free(old_ports, M_CXGBE);
9212 free(new_ports, M_CXGBE);
9214 end_synchronized_op(sc, 0);
9219 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9221 u_int rem = val % factor;
9224 snprintf(buf, len, "%u", val / factor);
9226 while (rem % 10 == 0)
9228 snprintf(buf, len, "%u.%u", val / factor, rem);
9233 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9235 struct adapter *sc = arg1;
9238 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9240 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9244 re = G_TIMERRESOLUTION(res);
9247 /* TCP timestamp tick */
9248 re = G_TIMESTAMPRESOLUTION(res);
9252 re = G_DELAYEDACKRESOLUTION(res);
9258 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9260 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9264 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9266 struct adapter *sc = arg1;
9267 u_int res, dack_re, v;
9268 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9270 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9271 dack_re = G_DELAYEDACKRESOLUTION(res);
9272 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9274 return (sysctl_handle_int(oidp, &v, 0, req));
9278 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9280 struct adapter *sc = arg1;
9283 u_long tp_tick_us, v;
9284 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9286 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9287 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9288 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9289 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9291 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9292 tp_tick_us = (cclk_ps << tre) / 1000000;
9294 if (reg == A_TP_INIT_SRTT)
9295 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9297 v = tp_tick_us * t4_read_reg(sc, reg);
9299 return (sysctl_handle_long(oidp, &v, 0, req));
9303 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9304 * passed to this function.
9307 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9309 struct adapter *sc = arg1;
9313 MPASS(idx >= 0 && idx <= 24);
9315 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9317 return (sysctl_handle_int(oidp, &v, 0, req));
9321 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9323 struct adapter *sc = arg1;
9327 MPASS(idx >= 0 && idx < 16);
9329 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9330 shift = (idx & 3) << 3;
9331 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9333 return (sysctl_handle_int(oidp, &v, 0, req));
9337 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9339 struct vi_info *vi = arg1;
9340 struct adapter *sc = vi->pi->adapter;
9342 struct sge_ofld_rxq *ofld_rxq;
9345 idx = vi->ofld_tmr_idx;
9347 rc = sysctl_handle_int(oidp, &idx, 0, req);
9348 if (rc != 0 || req->newptr == NULL)
9351 if (idx < 0 || idx >= SGE_NTIMERS)
9354 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9359 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9360 for_each_ofld_rxq(vi, i, ofld_rxq) {
9361 #ifdef atomic_store_rel_8
9362 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9364 ofld_rxq->iq.intr_params = v;
9367 vi->ofld_tmr_idx = idx;
9369 end_synchronized_op(sc, LOCK_HELD);
9374 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9376 struct vi_info *vi = arg1;
9377 struct adapter *sc = vi->pi->adapter;
9380 idx = vi->ofld_pktc_idx;
9382 rc = sysctl_handle_int(oidp, &idx, 0, req);
9383 if (rc != 0 || req->newptr == NULL)
9386 if (idx < -1 || idx >= SGE_NCOUNTERS)
9389 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9394 if (vi->flags & VI_INIT_DONE)
9395 rc = EBUSY; /* cannot be changed once the queues are created */
9397 vi->ofld_pktc_idx = idx;
9399 end_synchronized_op(sc, LOCK_HELD);
9405 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9409 if (cntxt->cid > M_CTXTQID)
9412 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9413 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9416 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9420 if (sc->flags & FW_OK) {
9421 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9428 * Read via firmware failed or wasn't even attempted. Read directly via
9431 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9433 end_synchronized_op(sc, 0);
9438 load_fw(struct adapter *sc, struct t4_data *fw)
9443 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9448 * The firmware, with the sole exception of the memory parity error
9449 * handler, runs from memory and not flash. It is almost always safe to
9450 * install a new firmware on a running system. Just set bit 1 in
9451 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9453 if (sc->flags & FULL_INIT_DONE &&
9454 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9459 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9460 if (fw_data == NULL) {
9465 rc = copyin(fw->data, fw_data, fw->len);
9467 rc = -t4_load_fw(sc, fw_data, fw->len);
9469 free(fw_data, M_CXGBE);
9471 end_synchronized_op(sc, 0);
9476 load_cfg(struct adapter *sc, struct t4_data *cfg)
9479 uint8_t *cfg_data = NULL;
9481 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9485 if (cfg->len == 0) {
9487 rc = -t4_load_cfg(sc, NULL, 0);
9491 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9492 if (cfg_data == NULL) {
9497 rc = copyin(cfg->data, cfg_data, cfg->len);
9499 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9501 free(cfg_data, M_CXGBE);
9503 end_synchronized_op(sc, 0);
9508 load_boot(struct adapter *sc, struct t4_bootrom *br)
9511 uint8_t *br_data = NULL;
9514 if (br->len > 1024 * 1024)
9517 if (br->pf_offset == 0) {
9519 if (br->pfidx_addr > 7)
9521 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9522 A_PCIE_PF_EXPROM_OFST)));
9523 } else if (br->pf_offset == 1) {
9525 offset = G_OFFSET(br->pfidx_addr);
9530 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9536 rc = -t4_load_boot(sc, NULL, offset, 0);
9540 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9541 if (br_data == NULL) {
9546 rc = copyin(br->data, br_data, br->len);
9548 rc = -t4_load_boot(sc, br_data, offset, br->len);
9550 free(br_data, M_CXGBE);
9552 end_synchronized_op(sc, 0);
9557 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9560 uint8_t *bc_data = NULL;
9562 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9568 rc = -t4_load_bootcfg(sc, NULL, 0);
9572 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9573 if (bc_data == NULL) {
9578 rc = copyin(bc->data, bc_data, bc->len);
9580 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9582 free(bc_data, M_CXGBE);
9584 end_synchronized_op(sc, 0);
9589 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9592 struct cudbg_init *cudbg;
9595 /* buf is large, don't block if no memory is available */
9596 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9600 handle = cudbg_alloc_handle();
9601 if (handle == NULL) {
9606 cudbg = cudbg_get_init(handle);
9608 cudbg->print = (cudbg_print_cb)printf;
9611 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9612 __func__, dump->wr_flash, dump->len, dump->data);
9616 cudbg->use_flash = 1;
9617 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9618 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9620 rc = cudbg_collect(handle, buf, &dump->len);
9624 rc = copyout(buf, dump->data, dump->len);
9626 cudbg_free_handle(handle);
9632 free_offload_policy(struct t4_offload_policy *op)
9634 struct offload_rule *r;
9641 for (i = 0; i < op->nrules; i++, r++) {
9642 free(r->bpf_prog.bf_insns, M_CXGBE);
9644 free(op->rule, M_CXGBE);
9649 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9652 struct t4_offload_policy *op, *old;
9653 struct bpf_program *bf;
9654 const struct offload_settings *s;
9655 struct offload_rule *r;
9658 if (!is_offload(sc))
9661 if (uop->nrules == 0) {
9662 /* Delete installed policies. */
9665 } if (uop->nrules > 256) { /* arbitrary */
9669 /* Copy userspace offload policy to kernel */
9670 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9671 op->nrules = uop->nrules;
9672 len = op->nrules * sizeof(struct offload_rule);
9673 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9674 rc = copyin(uop->rule, op->rule, len);
9676 free(op->rule, M_CXGBE);
9682 for (i = 0; i < op->nrules; i++, r++) {
9684 /* Validate open_type */
9685 if (r->open_type != OPEN_TYPE_LISTEN &&
9686 r->open_type != OPEN_TYPE_ACTIVE &&
9687 r->open_type != OPEN_TYPE_PASSIVE &&
9688 r->open_type != OPEN_TYPE_DONTCARE) {
9691 * Rules 0 to i have malloc'd filters that need to be
9692 * freed. Rules i+1 to nrules have userspace pointers
9693 * and should be left alone.
9696 free_offload_policy(op);
9700 /* Validate settings */
9702 if ((s->offload != 0 && s->offload != 1) ||
9703 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9704 s->sched_class < -1 ||
9705 s->sched_class >= sc->chip_params->nsched_cls) {
9711 u = bf->bf_insns; /* userspace ptr */
9712 bf->bf_insns = NULL;
9713 if (bf->bf_len == 0) {
9714 /* legal, matches everything */
9717 len = bf->bf_len * sizeof(*bf->bf_insns);
9718 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9719 rc = copyin(u, bf->bf_insns, len);
9723 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9729 rw_wlock(&sc->policy_lock);
9732 rw_wunlock(&sc->policy_lock);
9733 free_offload_policy(old);
9738 #define MAX_READ_BUF_SIZE (128 * 1024)
9740 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9742 uint32_t addr, remaining, n;
9747 rc = validate_mem_range(sc, mr->addr, mr->len);
9751 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9753 remaining = mr->len;
9754 dst = (void *)mr->data;
9757 n = min(remaining, MAX_READ_BUF_SIZE);
9758 read_via_memwin(sc, 2, addr, buf, n);
9760 rc = copyout(buf, dst, n);
9772 #undef MAX_READ_BUF_SIZE
9775 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9779 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9782 if (i2cd->len > sizeof(i2cd->data))
9785 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9788 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9789 i2cd->offset, i2cd->len, &i2cd->data[0]);
9790 end_synchronized_op(sc, 0);
9796 t4_os_find_pci_capability(struct adapter *sc, int cap)
9800 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9804 t4_os_pci_save_state(struct adapter *sc)
9807 struct pci_devinfo *dinfo;
9810 dinfo = device_get_ivars(dev);
9812 pci_cfg_save(dev, dinfo, 0);
9817 t4_os_pci_restore_state(struct adapter *sc)
9820 struct pci_devinfo *dinfo;
9823 dinfo = device_get_ivars(dev);
9825 pci_cfg_restore(dev, dinfo);
9830 t4_os_portmod_changed(struct port_info *pi)
9832 struct adapter *sc = pi->adapter;
9835 static const char *mod_str[] = {
9836 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9839 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
9840 ("%s: port_type %u", __func__, pi->port_type));
9843 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9845 build_medialist(pi);
9846 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
9847 fixup_link_config(pi);
9848 apply_link_config(pi);
9851 end_synchronized_op(sc, LOCK_HELD);
9855 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9856 if_printf(ifp, "transceiver unplugged.\n");
9857 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9858 if_printf(ifp, "unknown transceiver inserted.\n");
9859 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9860 if_printf(ifp, "unsupported transceiver inserted.\n");
9861 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9862 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9863 port_top_speed(pi), mod_str[pi->mod_type]);
9865 if_printf(ifp, "transceiver (type %d) inserted.\n",
9871 t4_os_link_changed(struct port_info *pi)
9875 struct link_config *lc;
9878 PORT_LOCK_ASSERT_OWNED(pi);
9880 for_each_vi(pi, v, vi) {
9887 ifp->if_baudrate = IF_Mbps(lc->speed);
9888 if_link_state_change(ifp, LINK_STATE_UP);
9890 if_link_state_change(ifp, LINK_STATE_DOWN);
9896 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9900 sx_slock(&t4_list_lock);
9901 SLIST_FOREACH(sc, &t4_list, link) {
9903 * func should not make any assumptions about what state sc is
9904 * in - the only guarantee is that sc->sc_lock is a valid lock.
9908 sx_sunlock(&t4_list_lock);
9912 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9916 struct adapter *sc = dev->si_drv1;
9918 rc = priv_check(td, PRIV_DRIVER);
9923 case CHELSIO_T4_GETREG: {
9924 struct t4_reg *edata = (struct t4_reg *)data;
9926 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9929 if (edata->size == 4)
9930 edata->val = t4_read_reg(sc, edata->addr);
9931 else if (edata->size == 8)
9932 edata->val = t4_read_reg64(sc, edata->addr);
9938 case CHELSIO_T4_SETREG: {
9939 struct t4_reg *edata = (struct t4_reg *)data;
9941 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9944 if (edata->size == 4) {
9945 if (edata->val & 0xffffffff00000000)
9947 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9948 } else if (edata->size == 8)
9949 t4_write_reg64(sc, edata->addr, edata->val);
9954 case CHELSIO_T4_REGDUMP: {
9955 struct t4_regdump *regs = (struct t4_regdump *)data;
9956 int reglen = t4_get_regs_len(sc);
9959 if (regs->len < reglen) {
9960 regs->len = reglen; /* hint to the caller */
9965 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9966 get_regs(sc, regs, buf);
9967 rc = copyout(buf, regs->data, reglen);
9971 case CHELSIO_T4_GET_FILTER_MODE:
9972 rc = get_filter_mode(sc, (uint32_t *)data);
9974 case CHELSIO_T4_SET_FILTER_MODE:
9975 rc = set_filter_mode(sc, *(uint32_t *)data);
9977 case CHELSIO_T4_GET_FILTER:
9978 rc = get_filter(sc, (struct t4_filter *)data);
9980 case CHELSIO_T4_SET_FILTER:
9981 rc = set_filter(sc, (struct t4_filter *)data);
9983 case CHELSIO_T4_DEL_FILTER:
9984 rc = del_filter(sc, (struct t4_filter *)data);
9986 case CHELSIO_T4_GET_SGE_CONTEXT:
9987 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9989 case CHELSIO_T4_LOAD_FW:
9990 rc = load_fw(sc, (struct t4_data *)data);
9992 case CHELSIO_T4_GET_MEM:
9993 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9995 case CHELSIO_T4_GET_I2C:
9996 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9998 case CHELSIO_T4_CLEAR_STATS: {
10000 u_int port_id = *(uint32_t *)data;
10001 struct port_info *pi;
10002 struct vi_info *vi;
10004 if (port_id >= sc->params.nports)
10006 pi = sc->port[port_id];
10011 t4_clr_port_stats(sc, pi->tx_chan);
10012 pi->tx_parse_error = 0;
10013 pi->tnl_cong_drops = 0;
10014 mtx_lock(&sc->reg_lock);
10015 for_each_vi(pi, v, vi) {
10016 if (vi->flags & VI_INIT_DONE)
10017 t4_clr_vi_stats(sc, vi->viid);
10019 bg_map = pi->mps_bg_map;
10022 i = ffs(bg_map) - 1;
10023 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10024 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10025 bg_map &= ~(1 << i);
10027 mtx_unlock(&sc->reg_lock);
10030 * Since this command accepts a port, clear stats for
10031 * all VIs on this port.
10033 for_each_vi(pi, v, vi) {
10034 if (vi->flags & VI_INIT_DONE) {
10035 struct sge_rxq *rxq;
10036 struct sge_txq *txq;
10037 struct sge_wrq *wrq;
10039 for_each_rxq(vi, i, rxq) {
10040 #if defined(INET) || defined(INET6)
10041 rxq->lro.lro_queued = 0;
10042 rxq->lro.lro_flushed = 0;
10045 rxq->vlan_extraction = 0;
10048 for_each_txq(vi, i, txq) {
10051 txq->vlan_insertion = 0;
10054 txq->txpkt_wrs = 0;
10055 txq->txpkts0_wrs = 0;
10056 txq->txpkts1_wrs = 0;
10057 txq->txpkts0_pkts = 0;
10058 txq->txpkts1_pkts = 0;
10060 mp_ring_reset_stats(txq->r);
10063 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10064 /* nothing to clear for each ofld_rxq */
10066 for_each_ofld_txq(vi, i, wrq) {
10067 wrq->tx_wrs_direct = 0;
10068 wrq->tx_wrs_copied = 0;
10072 if (IS_MAIN_VI(vi)) {
10073 wrq = &sc->sge.ctrlq[pi->port_id];
10074 wrq->tx_wrs_direct = 0;
10075 wrq->tx_wrs_copied = 0;
10081 case CHELSIO_T4_SCHED_CLASS:
10082 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10084 case CHELSIO_T4_SCHED_QUEUE:
10085 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10087 case CHELSIO_T4_GET_TRACER:
10088 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10090 case CHELSIO_T4_SET_TRACER:
10091 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10093 case CHELSIO_T4_LOAD_CFG:
10094 rc = load_cfg(sc, (struct t4_data *)data);
10096 case CHELSIO_T4_LOAD_BOOT:
10097 rc = load_boot(sc, (struct t4_bootrom *)data);
10099 case CHELSIO_T4_LOAD_BOOTCFG:
10100 rc = load_bootcfg(sc, (struct t4_data *)data);
10102 case CHELSIO_T4_CUDBG_DUMP:
10103 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10105 case CHELSIO_T4_SET_OFLD_POLICY:
10106 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10117 toe_capability(struct vi_info *vi, int enable)
10120 struct port_info *pi = vi->pi;
10121 struct adapter *sc = pi->adapter;
10123 ASSERT_SYNCHRONIZED_OP(sc);
10125 if (!is_offload(sc))
10129 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10130 /* TOE is already enabled. */
10135 * We need the port's queues around so that we're able to send
10136 * and receive CPLs to/from the TOE even if the ifnet for this
10137 * port has never been UP'd administratively.
10139 if (!(vi->flags & VI_INIT_DONE)) {
10140 rc = vi_full_init(vi);
10144 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10145 rc = vi_full_init(&pi->vi[0]);
10150 if (isset(&sc->offload_map, pi->port_id)) {
10151 /* TOE is enabled on another VI of this port. */
10156 if (!uld_active(sc, ULD_TOM)) {
10157 rc = t4_activate_uld(sc, ULD_TOM);
10158 if (rc == EAGAIN) {
10160 "You must kldload t4_tom.ko before trying "
10161 "to enable TOE on a cxgbe interface.\n");
10165 KASSERT(sc->tom_softc != NULL,
10166 ("%s: TOM activated but softc NULL", __func__));
10167 KASSERT(uld_active(sc, ULD_TOM),
10168 ("%s: TOM activated but flag not set", __func__));
10171 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10172 if (!uld_active(sc, ULD_IWARP))
10173 (void) t4_activate_uld(sc, ULD_IWARP);
10174 if (!uld_active(sc, ULD_ISCSI))
10175 (void) t4_activate_uld(sc, ULD_ISCSI);
10178 setbit(&sc->offload_map, pi->port_id);
10182 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10185 KASSERT(uld_active(sc, ULD_TOM),
10186 ("%s: TOM never initialized?", __func__));
10187 clrbit(&sc->offload_map, pi->port_id);
10194 * Add an upper layer driver to the global list.
10197 t4_register_uld(struct uld_info *ui)
10200 struct uld_info *u;
10202 sx_xlock(&t4_uld_list_lock);
10203 SLIST_FOREACH(u, &t4_uld_list, link) {
10204 if (u->uld_id == ui->uld_id) {
10210 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10213 sx_xunlock(&t4_uld_list_lock);
10218 t4_unregister_uld(struct uld_info *ui)
10221 struct uld_info *u;
10223 sx_xlock(&t4_uld_list_lock);
10225 SLIST_FOREACH(u, &t4_uld_list, link) {
10227 if (ui->refcount > 0) {
10232 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10238 sx_xunlock(&t4_uld_list_lock);
10243 t4_activate_uld(struct adapter *sc, int id)
10246 struct uld_info *ui;
10248 ASSERT_SYNCHRONIZED_OP(sc);
10250 if (id < 0 || id > ULD_MAX)
10252 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10254 sx_slock(&t4_uld_list_lock);
10256 SLIST_FOREACH(ui, &t4_uld_list, link) {
10257 if (ui->uld_id == id) {
10258 if (!(sc->flags & FULL_INIT_DONE)) {
10259 rc = adapter_full_init(sc);
10264 rc = ui->activate(sc);
10266 setbit(&sc->active_ulds, id);
10273 sx_sunlock(&t4_uld_list_lock);
10279 t4_deactivate_uld(struct adapter *sc, int id)
10282 struct uld_info *ui;
10284 ASSERT_SYNCHRONIZED_OP(sc);
10286 if (id < 0 || id > ULD_MAX)
10290 sx_slock(&t4_uld_list_lock);
10292 SLIST_FOREACH(ui, &t4_uld_list, link) {
10293 if (ui->uld_id == id) {
10294 rc = ui->deactivate(sc);
10296 clrbit(&sc->active_ulds, id);
10303 sx_sunlock(&t4_uld_list_lock);
10309 uld_active(struct adapter *sc, int uld_id)
10312 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10314 return (isset(&sc->active_ulds, uld_id));
10319 * t = ptr to tunable.
10320 * nc = number of CPUs.
10321 * c = compiled in default for that tunable.
10324 calculate_nqueues(int *t, int nc, const int c)
10330 nq = *t < 0 ? -*t : c;
10335 * Come up with reasonable defaults for some of the tunables, provided they're
10336 * not set by the user (in which case we'll use the values as is).
10339 tweak_tunables(void)
10341 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10345 t4_ntxq = rss_getnumbuckets();
10347 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10351 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10355 t4_nrxq = rss_getnumbuckets();
10357 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10361 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10363 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10364 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10365 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10368 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10369 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10371 if (t4_toecaps_allowed == -1)
10372 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10374 if (t4_rdmacaps_allowed == -1) {
10375 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10376 FW_CAPS_CONFIG_RDMA_RDMAC;
10379 if (t4_iscsicaps_allowed == -1) {
10380 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10381 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10382 FW_CAPS_CONFIG_ISCSI_T10DIF;
10385 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10386 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10388 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10389 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10391 if (t4_toecaps_allowed == -1)
10392 t4_toecaps_allowed = 0;
10394 if (t4_rdmacaps_allowed == -1)
10395 t4_rdmacaps_allowed = 0;
10397 if (t4_iscsicaps_allowed == -1)
10398 t4_iscsicaps_allowed = 0;
10402 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10403 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10406 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10407 t4_tmr_idx = TMR_IDX;
10409 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10410 t4_pktc_idx = PKTC_IDX;
10412 if (t4_qsize_txq < 128)
10413 t4_qsize_txq = 128;
10415 if (t4_qsize_rxq < 128)
10416 t4_qsize_rxq = 128;
10417 while (t4_qsize_rxq & 7)
10420 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10423 * Number of VIs to create per-port. The first VI is the "main" regular
10424 * VI for the port. The rest are additional virtual interfaces on the
10425 * same physical port. Note that the main VI does not have native
10426 * netmap support but the extra VIs do.
10428 * Limit the number of VIs per port to the number of available
10429 * MAC addresses per port.
10431 if (t4_num_vis < 1)
10433 if (t4_num_vis > nitems(vi_mac_funcs)) {
10434 t4_num_vis = nitems(vi_mac_funcs);
10435 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10438 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10439 pcie_relaxed_ordering = 1;
10440 #if defined(__i386__) || defined(__amd64__)
10441 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10442 pcie_relaxed_ordering = 0;
10449 t4_dump_tcb(struct adapter *sc, int tid)
10451 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10453 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10454 save = t4_read_reg(sc, reg);
10455 base = sc->memwin[2].mw_base;
10457 /* Dump TCB for the tid */
10458 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10459 tcb_addr += tid * TCB_SIZE;
10463 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10465 pf = V_PFNUM(sc->pf);
10466 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10468 t4_write_reg(sc, reg, win_pos | pf);
10469 t4_read_reg(sc, reg);
10471 off = tcb_addr - win_pos;
10472 for (i = 0; i < 4; i++) {
10474 for (j = 0; j < 8; j++, off += 4)
10475 buf[j] = htonl(t4_read_reg(sc, base + off));
10477 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10478 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10482 t4_write_reg(sc, reg, save);
10483 t4_read_reg(sc, reg);
10487 t4_dump_devlog(struct adapter *sc)
10489 struct devlog_params *dparams = &sc->params.devlog;
10490 struct fw_devlog_e e;
10491 int i, first, j, m, nentries, rc;
10492 uint64_t ftstamp = UINT64_MAX;
10494 if (dparams->start == 0) {
10495 db_printf("devlog params not valid\n");
10499 nentries = dparams->size / sizeof(struct fw_devlog_e);
10500 m = fwmtype_to_hwmtype(dparams->memtype);
10502 /* Find the first entry. */
10504 for (i = 0; i < nentries && !db_pager_quit; i++) {
10505 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10506 sizeof(e), (void *)&e);
10510 if (e.timestamp == 0)
10513 e.timestamp = be64toh(e.timestamp);
10514 if (e.timestamp < ftstamp) {
10515 ftstamp = e.timestamp;
10525 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10526 sizeof(e), (void *)&e);
10530 if (e.timestamp == 0)
10533 e.timestamp = be64toh(e.timestamp);
10534 e.seqno = be32toh(e.seqno);
10535 for (j = 0; j < 8; j++)
10536 e.params[j] = be32toh(e.params[j]);
10538 db_printf("%10d %15ju %8s %8s ",
10539 e.seqno, e.timestamp,
10540 (e.level < nitems(devlog_level_strings) ?
10541 devlog_level_strings[e.level] : "UNKNOWN"),
10542 (e.facility < nitems(devlog_facility_strings) ?
10543 devlog_facility_strings[e.facility] : "UNKNOWN"));
10544 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10545 e.params[3], e.params[4], e.params[5], e.params[6],
10548 if (++i == nentries)
10550 } while (i != first && !db_pager_quit);
10553 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10554 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10556 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10563 t = db_read_token();
10565 dev = device_lookup_by_name(db_tok_string);
10570 db_printf("usage: show t4 devlog <nexus>\n");
10575 db_printf("device not found\n");
10579 t4_dump_devlog(device_get_softc(dev));
10582 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10591 t = db_read_token();
10593 dev = device_lookup_by_name(db_tok_string);
10594 t = db_read_token();
10595 if (t == tNUMBER) {
10596 tid = db_tok_number;
10603 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10608 db_printf("device not found\n");
10612 db_printf("invalid tid\n");
10616 t4_dump_tcb(device_get_softc(dev), tid);
10621 * Borrowed from cesa_prep_aes_key().
10623 * NB: The crypto engine wants the words in the decryption key in reverse
10627 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10629 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10633 rijndaelKeySetupEnc(ek, enc_key, kbits);
10635 dkey += (kbits / 8) / 4;
10639 for (i = 0; i < 4; i++)
10640 *--dkey = htobe32(ek[4 * 10 + i]);
10643 for (i = 0; i < 2; i++)
10644 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10645 for (i = 0; i < 4; i++)
10646 *--dkey = htobe32(ek[4 * 12 + i]);
10649 for (i = 0; i < 4; i++)
10650 *--dkey = htobe32(ek[4 * 13 + i]);
10651 for (i = 0; i < 4; i++)
10652 *--dkey = htobe32(ek[4 * 14 + i]);
10655 MPASS(dkey == dec_key);
10658 static struct sx mlu; /* mod load unload */
10659 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10662 mod_event(module_t mod, int cmd, void *arg)
10665 static int loaded = 0;
10670 if (loaded++ == 0) {
10672 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10673 t4_filter_rpl, CPL_COOKIE_FILTER);
10674 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10675 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10676 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10677 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10678 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10679 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10680 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10681 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10682 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10683 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10684 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10686 sx_init(&t4_list_lock, "T4/T5 adapters");
10687 SLIST_INIT(&t4_list);
10689 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10690 SLIST_INIT(&t4_uld_list);
10695 t4_tracer_modload();
10703 if (--loaded == 0) {
10706 sx_slock(&t4_list_lock);
10707 if (!SLIST_EMPTY(&t4_list)) {
10709 sx_sunlock(&t4_list_lock);
10713 sx_slock(&t4_uld_list_lock);
10714 if (!SLIST_EMPTY(&t4_uld_list)) {
10716 sx_sunlock(&t4_uld_list_lock);
10717 sx_sunlock(&t4_list_lock);
10722 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10723 uprintf("%ju clusters with custom free routine "
10724 "still is use.\n", t4_sge_extfree_refs());
10725 pause("t4unload", 2 * hz);
10728 sx_sunlock(&t4_uld_list_lock);
10730 sx_sunlock(&t4_list_lock);
10732 if (t4_sge_extfree_refs() == 0) {
10733 t4_tracer_modunload();
10735 t4_clip_modunload();
10738 sx_destroy(&t4_uld_list_lock);
10740 sx_destroy(&t4_list_lock);
10741 t4_sge_modunload();
10745 loaded++; /* undo earlier decrement */
10756 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10757 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10758 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10760 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10761 MODULE_VERSION(t4nex, 1);
10762 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10764 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10765 #endif /* DEV_NETMAP */
10767 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10768 MODULE_VERSION(t5nex, 1);
10769 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10771 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10772 #endif /* DEV_NETMAP */
10774 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10775 MODULE_VERSION(t6nex, 1);
10776 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10778 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10779 #endif /* DEV_NETMAP */
10781 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10782 MODULE_VERSION(cxgbe, 1);
10784 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10785 MODULE_VERSION(cxl, 1);
10787 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10788 MODULE_VERSION(cc, 1);
10790 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10791 MODULE_VERSION(vcxgbe, 1);
10793 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10794 MODULE_VERSION(vcxl, 1);
10796 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10797 MODULE_VERSION(vcc, 1);