2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
38 #include <sys/param.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
46 #include <sys/taskqueue.h>
47 #include <sys/pciio.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pci_private.h>
51 #include <sys/firmware.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
56 #include <sys/sysctl.h>
57 #include <net/ethernet.h>
59 #include <net/if_types.h>
60 #include <net/if_dl.h>
61 #include <net/if_vlan_var.h>
63 #include <net/rss_config.h>
65 #if defined(__i386__) || defined(__amd64__)
66 #include <machine/md_var.h>
67 #include <machine/cputypes.h>
73 #include <ddb/db_lex.h>
76 #include "common/common.h"
77 #include "common/t4_msg.h"
78 #include "common/t4_regs.h"
79 #include "common/t4_regs_values.h"
80 #include "cudbg/cudbg.h"
83 #include "t4_mp_ring.h"
86 /* T4 bus driver interface */
87 static int t4_probe(device_t);
88 static int t4_attach(device_t);
89 static int t4_detach(device_t);
90 static int t4_ready(device_t);
91 static int t4_read_port_device(device_t, int, device_t *);
92 static device_method_t t4_methods[] = {
93 DEVMETHOD(device_probe, t4_probe),
94 DEVMETHOD(device_attach, t4_attach),
95 DEVMETHOD(device_detach, t4_detach),
97 DEVMETHOD(t4_is_main_ready, t4_ready),
98 DEVMETHOD(t4_read_port_device, t4_read_port_device),
102 static driver_t t4_driver = {
105 sizeof(struct adapter)
109 /* T4 port (cxgbe) interface */
110 static int cxgbe_probe(device_t);
111 static int cxgbe_attach(device_t);
112 static int cxgbe_detach(device_t);
113 device_method_t cxgbe_methods[] = {
114 DEVMETHOD(device_probe, cxgbe_probe),
115 DEVMETHOD(device_attach, cxgbe_attach),
116 DEVMETHOD(device_detach, cxgbe_detach),
119 static driver_t cxgbe_driver = {
122 sizeof(struct port_info)
125 /* T4 VI (vcxgbe) interface */
126 static int vcxgbe_probe(device_t);
127 static int vcxgbe_attach(device_t);
128 static int vcxgbe_detach(device_t);
129 static device_method_t vcxgbe_methods[] = {
130 DEVMETHOD(device_probe, vcxgbe_probe),
131 DEVMETHOD(device_attach, vcxgbe_attach),
132 DEVMETHOD(device_detach, vcxgbe_detach),
135 static driver_t vcxgbe_driver = {
138 sizeof(struct vi_info)
141 static d_ioctl_t t4_ioctl;
143 static struct cdevsw t4_cdevsw = {
144 .d_version = D_VERSION,
149 /* T5 bus driver interface */
150 static int t5_probe(device_t);
151 static device_method_t t5_methods[] = {
152 DEVMETHOD(device_probe, t5_probe),
153 DEVMETHOD(device_attach, t4_attach),
154 DEVMETHOD(device_detach, t4_detach),
156 DEVMETHOD(t4_is_main_ready, t4_ready),
157 DEVMETHOD(t4_read_port_device, t4_read_port_device),
161 static driver_t t5_driver = {
164 sizeof(struct adapter)
168 /* T5 port (cxl) interface */
169 static driver_t cxl_driver = {
172 sizeof(struct port_info)
175 /* T5 VI (vcxl) interface */
176 static driver_t vcxl_driver = {
179 sizeof(struct vi_info)
182 /* T6 bus driver interface */
183 static int t6_probe(device_t);
184 static device_method_t t6_methods[] = {
185 DEVMETHOD(device_probe, t6_probe),
186 DEVMETHOD(device_attach, t4_attach),
187 DEVMETHOD(device_detach, t4_detach),
189 DEVMETHOD(t4_is_main_ready, t4_ready),
190 DEVMETHOD(t4_read_port_device, t4_read_port_device),
194 static driver_t t6_driver = {
197 sizeof(struct adapter)
201 /* T6 port (cc) interface */
202 static driver_t cc_driver = {
205 sizeof(struct port_info)
208 /* T6 VI (vcc) interface */
209 static driver_t vcc_driver = {
212 sizeof(struct vi_info)
215 /* ifnet + media interface */
216 static void cxgbe_init(void *);
217 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
218 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
219 static void cxgbe_qflush(struct ifnet *);
220 static int cxgbe_media_change(struct ifnet *);
221 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
223 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
226 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
227 * then ADAPTER_LOCK, then t4_uld_list_lock.
229 static struct sx t4_list_lock;
230 SLIST_HEAD(, adapter) t4_list;
232 static struct sx t4_uld_list_lock;
233 SLIST_HEAD(, uld_info) t4_uld_list;
237 * Tunables. See tweak_tunables() too.
239 * Each tunable is set to a default value here if it's known at compile-time.
240 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
241 * provide a reasonable default (upto n) when the driver is loaded.
243 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
244 * T5 are under hw.cxl.
248 * Number of queues for tx and rx, NIC and offload.
252 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq);
253 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
257 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq);
258 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
261 static int t4_ntxq_vi = -NTXQ_VI;
262 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
265 static int t4_nrxq_vi = -NRXQ_VI;
266 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
268 static int t4_rsrv_noflowq = 0;
269 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
273 static int t4_nofldtxq = -NOFLDTXQ;
274 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq);
277 static int t4_nofldrxq = -NOFLDRXQ;
278 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq);
280 #define NOFLDTXQ_VI 1
281 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
282 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
284 #define NOFLDRXQ_VI 1
285 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
286 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
288 #define TMR_IDX_OFLD 1
289 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
290 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld);
292 #define PKTC_IDX_OFLD (-1)
293 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
294 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld);
296 /* 0 means chip/fw default, non-zero number is value in microseconds */
297 static u_long t4_toe_keepalive_idle = 0;
298 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle);
300 /* 0 means chip/fw default, non-zero number is value in microseconds */
301 static u_long t4_toe_keepalive_interval = 0;
302 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval);
304 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
305 static int t4_toe_keepalive_count = 0;
306 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count);
308 /* 0 means chip/fw default, non-zero number is value in microseconds */
309 static u_long t4_toe_rexmt_min = 0;
310 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min);
312 /* 0 means chip/fw default, non-zero number is value in microseconds */
313 static u_long t4_toe_rexmt_max = 0;
314 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max);
316 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
317 static int t4_toe_rexmt_count = 0;
318 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count);
320 /* -1 means chip/fw default, other values are raw backoff values to use */
321 static int t4_toe_rexmt_backoff[16] = {
322 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
324 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]);
325 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]);
326 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]);
327 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]);
328 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]);
329 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]);
330 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]);
331 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]);
332 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]);
333 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]);
334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]);
335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]);
336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]);
337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]);
338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]);
339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]);
344 static int t4_nnmtxq_vi = -NNMTXQ_VI;
345 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
348 static int t4_nnmrxq_vi = -NNMRXQ_VI;
349 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
353 * Holdoff parameters for ports.
356 int t4_tmr_idx = TMR_IDX;
357 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx);
358 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
360 #define PKTC_IDX (-1)
361 int t4_pktc_idx = PKTC_IDX;
362 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx);
363 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
366 * Size (# of entries) of each tx and rx queue.
368 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
369 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
371 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
372 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
375 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
377 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
378 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
381 * Configuration file.
383 #define DEFAULT_CF "default"
384 #define FLASH_CF "flash"
385 #define UWIRE_CF "uwire"
386 #define FPGA_CF "fpga"
387 static char t4_cfg_file[32] = DEFAULT_CF;
388 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
391 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
392 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
393 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
394 * mark or when signalled to do so, 0 to never emit PAUSE.
396 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
397 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
400 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS,
401 * FEC_RESERVED respectively).
402 * -1 to run with the firmware default.
405 static int t4_fec = -1;
406 TUNABLE_INT("hw.cxgbe.fec", &t4_fec);
409 * Link autonegotiation.
410 * -1 to run with the firmware default.
414 static int t4_autoneg = -1;
415 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg);
418 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
419 * encouraged respectively).
421 static unsigned int t4_fw_install = 1;
422 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
425 * ASIC features that will be used. Disable the ones you don't want so that the
426 * chip resources aren't wasted on features that will not be used.
428 static int t4_nbmcaps_allowed = 0;
429 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
431 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
432 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
434 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
435 FW_CAPS_CONFIG_SWITCH_EGRESS;
436 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
438 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
439 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
441 static int t4_toecaps_allowed = -1;
442 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
444 static int t4_rdmacaps_allowed = -1;
445 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
447 static int t4_cryptocaps_allowed = -1;
448 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
450 static int t4_iscsicaps_allowed = -1;
451 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
453 static int t4_fcoecaps_allowed = 0;
454 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
456 static int t5_write_combine = 1;
457 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
459 static int t4_num_vis = 1;
460 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
462 * PCIe Relaxed Ordering.
463 * -1: driver should figure out a good value.
468 static int pcie_relaxed_ordering = -1;
469 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering);
472 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
473 static int vi_mac_funcs[] = {
477 FW_VI_FUNC_OPENISCSI,
483 struct intrs_and_queues {
484 uint16_t intr_type; /* INTx, MSI, or MSI-X */
485 uint16_t num_vis; /* number of VIs for each port */
486 uint16_t nirq; /* Total # of vectors */
487 uint16_t ntxq; /* # of NIC txq's for each port */
488 uint16_t nrxq; /* # of NIC rxq's for each port */
489 uint16_t nofldtxq; /* # of TOE txq's for each port */
490 uint16_t nofldrxq; /* # of TOE rxq's for each port */
492 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
493 uint16_t ntxq_vi; /* # of NIC txq's */
494 uint16_t nrxq_vi; /* # of NIC rxq's */
495 uint16_t nofldtxq_vi; /* # of TOE txq's */
496 uint16_t nofldrxq_vi; /* # of TOE rxq's */
497 uint16_t nnmtxq_vi; /* # of netmap txq's */
498 uint16_t nnmrxq_vi; /* # of netmap rxq's */
501 struct filter_entry {
502 uint32_t valid:1; /* filter allocated and valid */
503 uint32_t locked:1; /* filter is administratively locked */
504 uint32_t pending:1; /* filter action is pending firmware reply */
505 uint32_t smtidx:8; /* Source MAC Table index for smac */
506 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
508 struct t4_filter_specification fs;
511 static void setup_memwin(struct adapter *);
512 static void position_memwin(struct adapter *, int, uint32_t);
513 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
514 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
516 static inline int write_via_memwin(struct adapter *, int, uint32_t,
517 const uint32_t *, int);
518 static int validate_mem_range(struct adapter *, uint32_t, int);
519 static int fwmtype_to_hwmtype(int);
520 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
522 static int fixup_devlog_params(struct adapter *);
523 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
524 static int prep_firmware(struct adapter *);
525 static int partition_resources(struct adapter *, const struct firmware *,
527 static int get_params__pre_init(struct adapter *);
528 static int get_params__post_init(struct adapter *);
529 static int set_params__post_init(struct adapter *);
530 static void t4_set_desc(struct adapter *);
531 static void build_medialist(struct port_info *, struct ifmedia *);
532 static void init_l1cfg(struct port_info *);
533 static int cxgbe_init_synchronized(struct vi_info *);
534 static int cxgbe_uninit_synchronized(struct vi_info *);
535 static void quiesce_txq(struct adapter *, struct sge_txq *);
536 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
537 static void quiesce_iq(struct adapter *, struct sge_iq *);
538 static void quiesce_fl(struct adapter *, struct sge_fl *);
539 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
540 driver_intr_t *, void *, char *);
541 static int t4_free_irq(struct adapter *, struct irq *);
542 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
543 static void vi_refresh_stats(struct adapter *, struct vi_info *);
544 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
545 static void cxgbe_tick(void *);
546 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
547 static void cxgbe_sysctls(struct port_info *);
548 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
549 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
550 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
551 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
552 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
553 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
554 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
555 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
556 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
557 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
558 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
559 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
560 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
562 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
563 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
564 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
565 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
566 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
567 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
568 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
569 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
570 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
571 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
572 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
573 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
574 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
575 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
576 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
577 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
578 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
579 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
580 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
581 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
582 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
583 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
584 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
585 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
586 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
587 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
588 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
589 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
590 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
593 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
594 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
595 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
596 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
597 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
598 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
599 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
601 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
602 static uint32_t mode_to_fconf(uint32_t);
603 static uint32_t mode_to_iconf(uint32_t);
604 static int check_fspec_against_fconf_iconf(struct adapter *,
605 struct t4_filter_specification *);
606 static int get_filter_mode(struct adapter *, uint32_t *);
607 static int set_filter_mode(struct adapter *, uint32_t);
608 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
609 static int get_filter(struct adapter *, struct t4_filter *);
610 static int set_filter(struct adapter *, struct t4_filter *);
611 static int del_filter(struct adapter *, struct t4_filter *);
612 static void clear_filter(struct filter_entry *);
613 static int set_filter_wr(struct adapter *, int);
614 static int del_filter_wr(struct adapter *, int);
615 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
617 static int get_sge_context(struct adapter *, struct t4_sge_context *);
618 static int load_fw(struct adapter *, struct t4_data *);
619 static int load_cfg(struct adapter *, struct t4_data *);
620 static int load_boot(struct adapter *, struct t4_bootrom *);
621 static int load_bootcfg(struct adapter *, struct t4_data *);
622 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
623 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
624 static int read_i2c(struct adapter *, struct t4_i2c_data *);
626 static int toe_capability(struct vi_info *, int);
628 static int mod_event(module_t, int, void *);
629 static int notify_siblings(device_t, int);
635 {0xa000, "Chelsio Terminator 4 FPGA"},
636 {0x4400, "Chelsio T440-dbg"},
637 {0x4401, "Chelsio T420-CR"},
638 {0x4402, "Chelsio T422-CR"},
639 {0x4403, "Chelsio T440-CR"},
640 {0x4404, "Chelsio T420-BCH"},
641 {0x4405, "Chelsio T440-BCH"},
642 {0x4406, "Chelsio T440-CH"},
643 {0x4407, "Chelsio T420-SO"},
644 {0x4408, "Chelsio T420-CX"},
645 {0x4409, "Chelsio T420-BT"},
646 {0x440a, "Chelsio T404-BT"},
647 {0x440e, "Chelsio T440-LP-CR"},
649 {0xb000, "Chelsio Terminator 5 FPGA"},
650 {0x5400, "Chelsio T580-dbg"},
651 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
652 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
653 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
654 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
655 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
656 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
657 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
658 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
659 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
660 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
661 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
662 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
663 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
665 {0x5404, "Chelsio T520-BCH"},
666 {0x5405, "Chelsio T540-BCH"},
667 {0x5406, "Chelsio T540-CH"},
668 {0x5408, "Chelsio T520-CX"},
669 {0x540b, "Chelsio B520-SR"},
670 {0x540c, "Chelsio B504-BT"},
671 {0x540f, "Chelsio Amsterdam"},
672 {0x5413, "Chelsio T580-CHR"},
675 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
676 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
677 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
678 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
679 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
680 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
681 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
682 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
683 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
684 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
685 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
686 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
687 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
688 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
689 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
690 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
693 {0x6480, "Chelsio T6225 80"},
694 {0x6481, "Chelsio T62100 81"},
695 {0x6484, "Chelsio T62100 84"},
700 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
701 * exactly the same for both rxq and ofld_rxq.
703 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
704 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
706 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
709 t4_probe(device_t dev)
712 uint16_t v = pci_get_vendor(dev);
713 uint16_t d = pci_get_device(dev);
714 uint8_t f = pci_get_function(dev);
716 if (v != PCI_VENDOR_ID_CHELSIO)
719 /* Attach only to PF0 of the FPGA */
720 if (d == 0xa000 && f != 0)
723 for (i = 0; i < nitems(t4_pciids); i++) {
724 if (d == t4_pciids[i].device) {
725 device_set_desc(dev, t4_pciids[i].desc);
726 return (BUS_PROBE_DEFAULT);
734 t5_probe(device_t dev)
737 uint16_t v = pci_get_vendor(dev);
738 uint16_t d = pci_get_device(dev);
739 uint8_t f = pci_get_function(dev);
741 if (v != PCI_VENDOR_ID_CHELSIO)
744 /* Attach only to PF0 of the FPGA */
745 if (d == 0xb000 && f != 0)
748 for (i = 0; i < nitems(t5_pciids); i++) {
749 if (d == t5_pciids[i].device) {
750 device_set_desc(dev, t5_pciids[i].desc);
751 return (BUS_PROBE_DEFAULT);
759 t6_probe(device_t dev)
762 uint16_t v = pci_get_vendor(dev);
763 uint16_t d = pci_get_device(dev);
765 if (v != PCI_VENDOR_ID_CHELSIO)
768 for (i = 0; i < nitems(t6_pciids); i++) {
769 if (d == t6_pciids[i].device) {
770 device_set_desc(dev, t6_pciids[i].desc);
771 return (BUS_PROBE_DEFAULT);
779 t5_attribute_workaround(device_t dev)
785 * The T5 chips do not properly echo the No Snoop and Relaxed
786 * Ordering attributes when replying to a TLP from a Root
787 * Port. As a workaround, find the parent Root Port and
788 * disable No Snoop and Relaxed Ordering. Note that this
789 * affects all devices under this root port.
791 root_port = pci_find_pcie_root_port(dev);
792 if (root_port == NULL) {
793 device_printf(dev, "Unable to find parent root port\n");
797 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
798 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
799 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
801 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
802 device_get_nameunit(root_port));
805 static const struct devnames devnames[] = {
807 .nexus_name = "t4nex",
808 .ifnet_name = "cxgbe",
809 .vi_ifnet_name = "vcxgbe",
810 .pf03_drv_name = "t4iov",
811 .vf_nexus_name = "t4vf",
812 .vf_ifnet_name = "cxgbev"
814 .nexus_name = "t5nex",
816 .vi_ifnet_name = "vcxl",
817 .pf03_drv_name = "t5iov",
818 .vf_nexus_name = "t5vf",
819 .vf_ifnet_name = "cxlv"
821 .nexus_name = "t6nex",
823 .vi_ifnet_name = "vcc",
824 .pf03_drv_name = "t6iov",
825 .vf_nexus_name = "t6vf",
826 .vf_ifnet_name = "ccv"
831 t4_init_devnames(struct adapter *sc)
836 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
837 sc->names = &devnames[id - CHELSIO_T4];
839 device_printf(sc->dev, "chip id %d is not supported.\n", id);
845 t4_attach(device_t dev)
848 int rc = 0, i, j, rqidx, tqidx, nports;
849 struct make_dev_args mda;
850 struct intrs_and_queues iaq;
854 int ofld_rqidx, ofld_tqidx;
857 int nm_rqidx, nm_tqidx;
861 sc = device_get_softc(dev);
863 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
865 if ((pci_get_device(dev) & 0xff00) == 0x5400)
866 t5_attribute_workaround(dev);
867 pci_enable_busmaster(dev);
868 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
871 pci_set_max_read_req(dev, 4096);
872 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
873 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
874 if (pcie_relaxed_ordering == 0 &&
875 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
876 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
877 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
878 } else if (pcie_relaxed_ordering == 1 &&
879 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
880 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
881 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
885 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
886 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
888 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
889 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
890 device_get_nameunit(dev));
892 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
893 device_get_nameunit(dev));
894 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
897 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
898 TAILQ_INIT(&sc->sfl);
899 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
901 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
903 rc = t4_map_bars_0_and_4(sc);
905 goto done; /* error message displayed already */
907 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
909 /* Prepare the adapter for operation. */
910 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
911 rc = -t4_prep_adapter(sc, buf);
914 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
919 * This is the real PF# to which we're attaching. Works from within PCI
920 * passthrough environments too, where pci_get_function() could return a
921 * different PF# depending on the passthrough configuration. We need to
922 * use the real PF# in all our communication with the firmware.
924 j = t4_read_reg(sc, A_PL_WHOAMI);
925 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
928 t4_init_devnames(sc);
929 if (sc->names == NULL) {
931 goto done; /* error message displayed already */
935 * Do this really early, with the memory windows set up even before the
936 * character device. The userland tool's register i/o and mem read
937 * will work even in "recovery mode".
940 if (t4_init_devlog_params(sc, 0) == 0)
941 fixup_devlog_params(sc);
942 make_dev_args_init(&mda);
943 mda.mda_devsw = &t4_cdevsw;
944 mda.mda_uid = UID_ROOT;
945 mda.mda_gid = GID_WHEEL;
947 mda.mda_si_drv1 = sc;
948 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
950 device_printf(dev, "failed to create nexus char device: %d.\n",
953 /* Go no further if recovery mode has been requested. */
954 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
955 device_printf(dev, "recovery mode.\n");
959 #if defined(__i386__)
960 if ((cpu_feature & CPUID_CX8) == 0) {
961 device_printf(dev, "64 bit atomics not available.\n");
967 /* Prepare the firmware for operation */
968 rc = prep_firmware(sc);
970 goto done; /* error message displayed already */
972 rc = get_params__post_init(sc);
974 goto done; /* error message displayed already */
976 rc = set_params__post_init(sc);
978 goto done; /* error message displayed already */
980 rc = t4_map_bar_2(sc);
982 goto done; /* error message displayed already */
984 rc = t4_create_dma_tag(sc);
986 goto done; /* error message displayed already */
989 * First pass over all the ports - allocate VIs and initialize some
990 * basic parameters like mac address, port type, etc.
992 for_each_port(sc, i) {
993 struct port_info *pi;
995 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
998 /* These must be set before t4_port_init */
1002 * XXX: vi[0] is special so we can't delay this allocation until
1003 * pi->nvi's final value is known.
1005 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1009 * Allocate the "main" VI and initialize parameters
1012 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1014 device_printf(dev, "unable to initialize port %d: %d\n",
1016 free(pi->vi, M_CXGBE);
1022 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1023 device_get_nameunit(dev), i);
1024 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1025 sc->chan_map[pi->tx_chan] = i;
1027 /* All VIs on this port share this media. */
1028 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1029 cxgbe_media_status);
1031 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
1032 if (pi->dev == NULL) {
1034 "failed to add device for port %d.\n", i);
1038 pi->vi[0].dev = pi->dev;
1039 device_set_softc(pi->dev, pi);
1043 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1045 nports = sc->params.nports;
1046 rc = cfg_itype_and_nqueues(sc, &iaq);
1048 goto done; /* error message displayed already */
1050 num_vis = iaq.num_vis;
1051 sc->intr_type = iaq.intr_type;
1052 sc->intr_count = iaq.nirq;
1055 s->nrxq = nports * iaq.nrxq;
1056 s->ntxq = nports * iaq.ntxq;
1058 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1059 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1061 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1062 s->neq += nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1063 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1065 if (is_offload(sc)) {
1066 s->nofldrxq = nports * iaq.nofldrxq;
1067 s->nofldtxq = nports * iaq.nofldtxq;
1069 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1070 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1072 s->neq += s->nofldtxq + s->nofldrxq;
1073 s->niq += s->nofldrxq;
1075 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1076 M_CXGBE, M_ZERO | M_WAITOK);
1077 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1078 M_CXGBE, M_ZERO | M_WAITOK);
1083 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1084 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1086 s->neq += s->nnmtxq + s->nnmrxq;
1087 s->niq += s->nnmrxq;
1089 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1090 M_CXGBE, M_ZERO | M_WAITOK);
1091 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1092 M_CXGBE, M_ZERO | M_WAITOK);
1095 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1097 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1099 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1101 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1103 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1106 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1109 t4_init_l2t(sc, M_WAITOK);
1110 t4_init_tx_sched(sc);
1113 * Second pass over the ports. This time we know the number of rx and
1114 * tx queues that each port should get.
1118 ofld_rqidx = ofld_tqidx = 0;
1121 nm_rqidx = nm_tqidx = 0;
1123 for_each_port(sc, i) {
1124 struct port_info *pi = sc->port[i];
1131 for_each_vi(pi, j, vi) {
1133 vi->qsize_rxq = t4_qsize_rxq;
1134 vi->qsize_txq = t4_qsize_txq;
1136 vi->first_rxq = rqidx;
1137 vi->first_txq = tqidx;
1138 vi->tmr_idx = t4_tmr_idx;
1139 vi->pktc_idx = t4_pktc_idx;
1140 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1141 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1146 if (j == 0 && vi->ntxq > 1)
1147 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1149 vi->rsrv_noflowq = 0;
1152 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1153 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1154 vi->first_ofld_rxq = ofld_rqidx;
1155 vi->first_ofld_txq = ofld_tqidx;
1156 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1157 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1159 ofld_rqidx += vi->nofldrxq;
1160 ofld_tqidx += vi->nofldtxq;
1164 vi->first_nm_rxq = nm_rqidx;
1165 vi->first_nm_txq = nm_tqidx;
1166 vi->nnmrxq = iaq.nnmrxq_vi;
1167 vi->nnmtxq = iaq.nnmtxq_vi;
1168 nm_rqidx += vi->nnmrxq;
1169 nm_tqidx += vi->nnmtxq;
1175 rc = t4_setup_intr_handlers(sc);
1178 "failed to setup interrupt handlers: %d\n", rc);
1182 rc = bus_generic_probe(dev);
1184 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1189 * Ensure thread-safe mailbox access (in debug builds).
1191 * So far this was the only thread accessing the mailbox but various
1192 * ifnets and sysctls are about to be created and their handlers/ioctls
1193 * will access the mailbox from different threads.
1195 sc->flags |= CHK_MBOX_ACCESS;
1197 rc = bus_generic_attach(dev);
1200 "failed to attach all child ports: %d\n", rc);
1205 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1206 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1207 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1208 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1209 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1213 notify_siblings(dev, 0);
1216 if (rc != 0 && sc->cdev) {
1217 /* cdev was created and so cxgbetool works; recover that way. */
1219 "error during attach, adapter is now in recovery mode.\n");
1224 t4_detach_common(dev);
1232 t4_ready(device_t dev)
1236 sc = device_get_softc(dev);
1237 if (sc->flags & FW_OK)
1243 t4_read_port_device(device_t dev, int port, device_t *child)
1246 struct port_info *pi;
1248 sc = device_get_softc(dev);
1249 if (port < 0 || port >= MAX_NPORTS)
1251 pi = sc->port[port];
1252 if (pi == NULL || pi->dev == NULL)
1259 notify_siblings(device_t dev, int detaching)
1265 for (i = 0; i < PCI_FUNCMAX; i++) {
1266 if (i == pci_get_function(dev))
1268 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1269 pci_get_slot(dev), i);
1270 if (sibling == NULL || !device_is_attached(sibling))
1273 error = T4_DETACH_CHILD(sibling);
1275 (void)T4_ATTACH_CHILD(sibling);
1286 t4_detach(device_t dev)
1291 sc = device_get_softc(dev);
1293 rc = notify_siblings(dev, 1);
1296 "failed to detach sibling devices: %d\n", rc);
1300 return (t4_detach_common(dev));
1304 t4_detach_common(device_t dev)
1307 struct port_info *pi;
1310 sc = device_get_softc(dev);
1312 sc->flags &= ~CHK_MBOX_ACCESS;
1313 if (sc->flags & FULL_INIT_DONE) {
1314 if (!(sc->flags & IS_VF))
1315 t4_intr_disable(sc);
1319 destroy_dev(sc->cdev);
1323 if (device_is_attached(dev)) {
1324 rc = bus_generic_detach(dev);
1327 "failed to detach child devices: %d\n", rc);
1332 for (i = 0; i < sc->intr_count; i++)
1333 t4_free_irq(sc, &sc->irq[i]);
1335 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1336 t4_free_tx_sched(sc);
1338 for (i = 0; i < MAX_NPORTS; i++) {
1341 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1343 device_delete_child(dev, pi->dev);
1345 mtx_destroy(&pi->pi_lock);
1346 free(pi->vi, M_CXGBE);
1351 device_delete_children(dev);
1353 if (sc->flags & FULL_INIT_DONE)
1354 adapter_full_uninit(sc);
1356 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1357 t4_fw_bye(sc, sc->mbox);
1359 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1360 pci_release_msi(dev);
1363 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1367 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1371 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1375 t4_free_l2t(sc->l2t);
1378 free(sc->sge.ofld_rxq, M_CXGBE);
1379 free(sc->sge.ofld_txq, M_CXGBE);
1382 free(sc->sge.nm_rxq, M_CXGBE);
1383 free(sc->sge.nm_txq, M_CXGBE);
1385 free(sc->irq, M_CXGBE);
1386 free(sc->sge.rxq, M_CXGBE);
1387 free(sc->sge.txq, M_CXGBE);
1388 free(sc->sge.ctrlq, M_CXGBE);
1389 free(sc->sge.iqmap, M_CXGBE);
1390 free(sc->sge.eqmap, M_CXGBE);
1391 free(sc->tids.ftid_tab, M_CXGBE);
1392 t4_destroy_dma_tag(sc);
1393 if (mtx_initialized(&sc->sc_lock)) {
1394 sx_xlock(&t4_list_lock);
1395 SLIST_REMOVE(&t4_list, sc, adapter, link);
1396 sx_xunlock(&t4_list_lock);
1397 mtx_destroy(&sc->sc_lock);
1400 callout_drain(&sc->sfl_callout);
1401 if (mtx_initialized(&sc->tids.ftid_lock))
1402 mtx_destroy(&sc->tids.ftid_lock);
1403 if (mtx_initialized(&sc->sfl_lock))
1404 mtx_destroy(&sc->sfl_lock);
1405 if (mtx_initialized(&sc->ifp_lock))
1406 mtx_destroy(&sc->ifp_lock);
1407 if (mtx_initialized(&sc->reg_lock))
1408 mtx_destroy(&sc->reg_lock);
1410 for (i = 0; i < NUM_MEMWIN; i++) {
1411 struct memwin *mw = &sc->memwin[i];
1413 if (rw_initialized(&mw->mw_lock))
1414 rw_destroy(&mw->mw_lock);
1417 bzero(sc, sizeof(*sc));
1423 cxgbe_probe(device_t dev)
1426 struct port_info *pi = device_get_softc(dev);
1428 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1429 device_set_desc_copy(dev, buf);
1431 return (BUS_PROBE_DEFAULT);
1434 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1435 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1436 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1437 #define T4_CAP_ENABLE (T4_CAP)
1440 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1445 vi->xact_addr_filt = -1;
1446 callout_init(&vi->tick, 1);
1448 /* Allocate an ifnet and set it up */
1449 ifp = if_alloc(IFT_ETHER);
1451 device_printf(dev, "Cannot allocate ifnet\n");
1457 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1458 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1460 ifp->if_init = cxgbe_init;
1461 ifp->if_ioctl = cxgbe_ioctl;
1462 ifp->if_transmit = cxgbe_transmit;
1463 ifp->if_qflush = cxgbe_qflush;
1464 ifp->if_get_counter = cxgbe_get_counter;
1466 ifp->if_capabilities = T4_CAP;
1468 if (vi->nofldrxq != 0)
1469 ifp->if_capabilities |= IFCAP_TOE;
1472 if (vi->nnmrxq != 0)
1473 ifp->if_capabilities |= IFCAP_NETMAP;
1475 ifp->if_capenable = T4_CAP_ENABLE;
1476 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1477 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1479 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1480 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1481 ifp->if_hw_tsomaxsegsize = 65536;
1483 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1484 EVENTHANDLER_PRI_ANY);
1486 ether_ifattach(ifp, vi->hw_addr);
1488 if (ifp->if_capabilities & IFCAP_NETMAP)
1489 cxgbe_nm_attach(vi);
1491 sb = sbuf_new_auto();
1492 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1494 if (ifp->if_capabilities & IFCAP_TOE)
1495 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1496 vi->nofldtxq, vi->nofldrxq);
1499 if (ifp->if_capabilities & IFCAP_NETMAP)
1500 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1501 vi->nnmtxq, vi->nnmrxq);
1504 device_printf(dev, "%s\n", sbuf_data(sb));
1513 cxgbe_attach(device_t dev)
1515 struct port_info *pi = device_get_softc(dev);
1516 struct adapter *sc = pi->adapter;
1520 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1522 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1526 for_each_vi(pi, i, vi) {
1529 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1530 if (vi->dev == NULL) {
1531 device_printf(dev, "failed to add VI %d\n", i);
1534 device_set_softc(vi->dev, vi);
1539 bus_generic_attach(dev);
1545 cxgbe_vi_detach(struct vi_info *vi)
1547 struct ifnet *ifp = vi->ifp;
1549 ether_ifdetach(ifp);
1552 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1554 /* Let detach proceed even if these fail. */
1556 if (ifp->if_capabilities & IFCAP_NETMAP)
1557 cxgbe_nm_detach(vi);
1559 cxgbe_uninit_synchronized(vi);
1560 callout_drain(&vi->tick);
1568 cxgbe_detach(device_t dev)
1570 struct port_info *pi = device_get_softc(dev);
1571 struct adapter *sc = pi->adapter;
1574 /* Detach the extra VIs first. */
1575 rc = bus_generic_detach(dev);
1578 device_delete_children(dev);
1580 doom_vi(sc, &pi->vi[0]);
1582 if (pi->flags & HAS_TRACEQ) {
1583 sc->traceq = -1; /* cloner should not create ifnet */
1584 t4_tracer_port_detach(sc);
1587 cxgbe_vi_detach(&pi->vi[0]);
1588 callout_drain(&pi->tick);
1589 ifmedia_removeall(&pi->media);
1591 end_synchronized_op(sc, 0);
1597 cxgbe_init(void *arg)
1599 struct vi_info *vi = arg;
1600 struct adapter *sc = vi->pi->adapter;
1602 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1604 cxgbe_init_synchronized(vi);
1605 end_synchronized_op(sc, 0);
1609 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1611 int rc = 0, mtu, flags, can_sleep;
1612 struct vi_info *vi = ifp->if_softc;
1613 struct port_info *pi = vi->pi;
1614 struct adapter *sc = pi->adapter;
1615 struct ifreq *ifr = (struct ifreq *)data;
1621 if (mtu < ETHERMIN || mtu > MAX_MTU)
1624 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1628 if (vi->flags & VI_INIT_DONE) {
1629 t4_update_fl_bufsize(ifp);
1630 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1631 rc = update_mac_settings(ifp, XGMAC_MTU);
1633 end_synchronized_op(sc, 0);
1639 rc = begin_synchronized_op(sc, vi,
1640 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1644 if (ifp->if_flags & IFF_UP) {
1645 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1646 flags = vi->if_flags;
1647 if ((ifp->if_flags ^ flags) &
1648 (IFF_PROMISC | IFF_ALLMULTI)) {
1649 if (can_sleep == 1) {
1650 end_synchronized_op(sc, 0);
1654 rc = update_mac_settings(ifp,
1655 XGMAC_PROMISC | XGMAC_ALLMULTI);
1658 if (can_sleep == 0) {
1659 end_synchronized_op(sc, LOCK_HELD);
1663 rc = cxgbe_init_synchronized(vi);
1665 vi->if_flags = ifp->if_flags;
1666 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1667 if (can_sleep == 0) {
1668 end_synchronized_op(sc, LOCK_HELD);
1672 rc = cxgbe_uninit_synchronized(vi);
1674 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1678 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1679 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1682 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1683 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1684 end_synchronized_op(sc, LOCK_HELD);
1688 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1692 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1693 if (mask & IFCAP_TXCSUM) {
1694 ifp->if_capenable ^= IFCAP_TXCSUM;
1695 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1697 if (IFCAP_TSO4 & ifp->if_capenable &&
1698 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1699 ifp->if_capenable &= ~IFCAP_TSO4;
1701 "tso4 disabled due to -txcsum.\n");
1704 if (mask & IFCAP_TXCSUM_IPV6) {
1705 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1706 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1708 if (IFCAP_TSO6 & ifp->if_capenable &&
1709 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1710 ifp->if_capenable &= ~IFCAP_TSO6;
1712 "tso6 disabled due to -txcsum6.\n");
1715 if (mask & IFCAP_RXCSUM)
1716 ifp->if_capenable ^= IFCAP_RXCSUM;
1717 if (mask & IFCAP_RXCSUM_IPV6)
1718 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1721 * Note that we leave CSUM_TSO alone (it is always set). The
1722 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1723 * sending a TSO request our way, so it's sufficient to toggle
1726 if (mask & IFCAP_TSO4) {
1727 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1728 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1729 if_printf(ifp, "enable txcsum first.\n");
1733 ifp->if_capenable ^= IFCAP_TSO4;
1735 if (mask & IFCAP_TSO6) {
1736 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1737 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1738 if_printf(ifp, "enable txcsum6 first.\n");
1742 ifp->if_capenable ^= IFCAP_TSO6;
1744 if (mask & IFCAP_LRO) {
1745 #if defined(INET) || defined(INET6)
1747 struct sge_rxq *rxq;
1749 ifp->if_capenable ^= IFCAP_LRO;
1750 for_each_rxq(vi, i, rxq) {
1751 if (ifp->if_capenable & IFCAP_LRO)
1752 rxq->iq.flags |= IQ_LRO_ENABLED;
1754 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1759 if (mask & IFCAP_TOE) {
1760 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1762 rc = toe_capability(vi, enable);
1766 ifp->if_capenable ^= mask;
1769 if (mask & IFCAP_VLAN_HWTAGGING) {
1770 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1771 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1772 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1774 if (mask & IFCAP_VLAN_MTU) {
1775 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1777 /* Need to find out how to disable auto-mtu-inflation */
1779 if (mask & IFCAP_VLAN_HWTSO)
1780 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1781 if (mask & IFCAP_VLAN_HWCSUM)
1782 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1784 #ifdef VLAN_CAPABILITIES
1785 VLAN_CAPABILITIES(ifp);
1788 end_synchronized_op(sc, 0);
1794 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1798 struct ifi2creq i2c;
1800 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1803 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1807 if (i2c.len > sizeof(i2c.data)) {
1811 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1814 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1815 i2c.offset, i2c.len, &i2c.data[0]);
1816 end_synchronized_op(sc, 0);
1818 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1823 rc = ether_ioctl(ifp, cmd, data);
1830 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1832 struct vi_info *vi = ifp->if_softc;
1833 struct port_info *pi = vi->pi;
1834 struct adapter *sc = pi->adapter;
1835 struct sge_txq *txq;
1840 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1842 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1847 rc = parse_pkt(sc, &m);
1848 if (__predict_false(rc != 0)) {
1849 MPASS(m == NULL); /* was freed already */
1850 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1855 txq = &sc->sge.txq[vi->first_txq];
1856 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1857 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1861 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1862 if (__predict_false(rc != 0))
1869 cxgbe_qflush(struct ifnet *ifp)
1871 struct vi_info *vi = ifp->if_softc;
1872 struct sge_txq *txq;
1875 /* queues do not exist if !VI_INIT_DONE. */
1876 if (vi->flags & VI_INIT_DONE) {
1877 for_each_txq(vi, i, txq) {
1879 txq->eq.flags |= EQ_QFLUSH;
1881 while (!mp_ring_is_idle(txq->r)) {
1882 mp_ring_check_drainage(txq->r, 0);
1886 txq->eq.flags &= ~EQ_QFLUSH;
1894 vi_get_counter(struct ifnet *ifp, ift_counter c)
1896 struct vi_info *vi = ifp->if_softc;
1897 struct fw_vi_stats_vf *s = &vi->stats;
1899 vi_refresh_stats(vi->pi->adapter, vi);
1902 case IFCOUNTER_IPACKETS:
1903 return (s->rx_bcast_frames + s->rx_mcast_frames +
1904 s->rx_ucast_frames);
1905 case IFCOUNTER_IERRORS:
1906 return (s->rx_err_frames);
1907 case IFCOUNTER_OPACKETS:
1908 return (s->tx_bcast_frames + s->tx_mcast_frames +
1909 s->tx_ucast_frames + s->tx_offload_frames);
1910 case IFCOUNTER_OERRORS:
1911 return (s->tx_drop_frames);
1912 case IFCOUNTER_IBYTES:
1913 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
1915 case IFCOUNTER_OBYTES:
1916 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
1917 s->tx_ucast_bytes + s->tx_offload_bytes);
1918 case IFCOUNTER_IMCASTS:
1919 return (s->rx_mcast_frames);
1920 case IFCOUNTER_OMCASTS:
1921 return (s->tx_mcast_frames);
1922 case IFCOUNTER_OQDROPS: {
1926 if (vi->flags & VI_INIT_DONE) {
1928 struct sge_txq *txq;
1930 for_each_txq(vi, i, txq)
1931 drops += counter_u64_fetch(txq->r->drops);
1939 return (if_get_counter_default(ifp, c));
1944 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
1946 struct vi_info *vi = ifp->if_softc;
1947 struct port_info *pi = vi->pi;
1948 struct adapter *sc = pi->adapter;
1949 struct port_stats *s = &pi->stats;
1951 if (pi->nvi > 1 || sc->flags & IS_VF)
1952 return (vi_get_counter(ifp, c));
1954 cxgbe_refresh_stats(sc, pi);
1957 case IFCOUNTER_IPACKETS:
1958 return (s->rx_frames);
1960 case IFCOUNTER_IERRORS:
1961 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
1962 s->rx_fcs_err + s->rx_len_err);
1964 case IFCOUNTER_OPACKETS:
1965 return (s->tx_frames);
1967 case IFCOUNTER_OERRORS:
1968 return (s->tx_error_frames);
1970 case IFCOUNTER_IBYTES:
1971 return (s->rx_octets);
1973 case IFCOUNTER_OBYTES:
1974 return (s->tx_octets);
1976 case IFCOUNTER_IMCASTS:
1977 return (s->rx_mcast_frames);
1979 case IFCOUNTER_OMCASTS:
1980 return (s->tx_mcast_frames);
1982 case IFCOUNTER_IQDROPS:
1983 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
1984 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
1985 s->rx_trunc3 + pi->tnl_cong_drops);
1987 case IFCOUNTER_OQDROPS: {
1991 if (vi->flags & VI_INIT_DONE) {
1993 struct sge_txq *txq;
1995 for_each_txq(vi, i, txq)
1996 drops += counter_u64_fetch(txq->r->drops);
2004 return (if_get_counter_default(ifp, c));
2009 cxgbe_media_change(struct ifnet *ifp)
2011 struct vi_info *vi = ifp->if_softc;
2013 device_printf(vi->dev, "%s unimplemented.\n", __func__);
2015 return (EOPNOTSUPP);
2019 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2021 struct vi_info *vi = ifp->if_softc;
2022 struct port_info *pi = vi->pi;
2023 struct ifmedia_entry *cur;
2024 struct link_config *lc = &pi->link_cfg;
2027 * If all the interfaces are administratively down the firmware does not
2028 * report transceiver changes. Refresh port info here so that ifconfig
2029 * displays accurate information at all times.
2031 if (begin_synchronized_op(pi->adapter, NULL, SLEEP_OK | INTR_OK,
2034 if (pi->up_vis == 0) {
2035 t4_update_port_info(pi);
2036 build_medialist(pi, &pi->media);
2039 end_synchronized_op(pi->adapter, 0);
2042 ifmr->ifm_status = IFM_AVALID;
2043 if (lc->link_ok == 0)
2046 ifmr->ifm_status |= IFM_ACTIVE;
2047 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2048 if (lc->fc & PAUSE_RX)
2049 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2050 if (lc->fc & PAUSE_TX)
2051 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2053 /* active and current will differ iff current media is autoselect. */
2054 cur = pi->media.ifm_cur;
2055 if (cur != NULL && IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
2058 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2059 if (lc->fc & PAUSE_RX)
2060 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2061 if (lc->fc & PAUSE_TX)
2062 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2063 switch (lc->speed) {
2065 ifmr->ifm_active |= IFM_10G_T;
2068 ifmr->ifm_active |= IFM_1000_T;
2071 ifmr->ifm_active |= IFM_100_TX;
2074 ifmr->ifm_active |= IFM_10_T;
2077 device_printf(vi->dev, "link up but speed unknown (%u)\n",
2083 vcxgbe_probe(device_t dev)
2086 struct vi_info *vi = device_get_softc(dev);
2088 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2090 device_set_desc_copy(dev, buf);
2092 return (BUS_PROBE_DEFAULT);
2096 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2098 int func, index, rc;
2099 uint32_t param, val;
2101 ASSERT_SYNCHRONIZED_OP(sc);
2103 index = vi - pi->vi;
2104 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2105 KASSERT(index < nitems(vi_mac_funcs),
2106 ("%s: VI %s doesn't have a MAC func", __func__,
2107 device_get_nameunit(vi->dev)));
2108 func = vi_mac_funcs[index];
2109 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2110 vi->hw_addr, &vi->rss_size, func, 0);
2112 device_printf(vi->dev, "failed to allocate virtual interface %d"
2113 "for port %d: %d\n", index, pi->port_id, -rc);
2117 if (chip_id(sc) <= CHELSIO_T5)
2118 vi->smt_idx = (rc & 0x7f) << 1;
2120 vi->smt_idx = (rc & 0x7f);
2122 if (vi->rss_size == 1) {
2124 * This VI didn't get a slice of the RSS table. Reduce the
2125 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2126 * configuration file (nvi, rssnvi for this PF) if this is a
2129 device_printf(vi->dev, "RSS table not available.\n");
2130 vi->rss_base = 0xffff;
2135 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2136 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2137 V_FW_PARAMS_PARAM_YZ(vi->viid);
2138 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2140 vi->rss_base = 0xffff;
2142 MPASS((val >> 16) == vi->rss_size);
2143 vi->rss_base = val & 0xffff;
2150 vcxgbe_attach(device_t dev)
2153 struct port_info *pi;
2157 vi = device_get_softc(dev);
2161 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2164 rc = alloc_extra_vi(sc, pi, vi);
2165 end_synchronized_op(sc, 0);
2169 rc = cxgbe_vi_attach(dev, vi);
2171 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2178 vcxgbe_detach(device_t dev)
2183 vi = device_get_softc(dev);
2184 sc = vi->pi->adapter;
2188 cxgbe_vi_detach(vi);
2189 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2191 end_synchronized_op(sc, 0);
2197 t4_fatal_err(struct adapter *sc)
2199 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2200 t4_intr_disable(sc);
2201 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2202 device_get_nameunit(sc->dev));
2206 t4_add_adapter(struct adapter *sc)
2208 sx_xlock(&t4_list_lock);
2209 SLIST_INSERT_HEAD(&t4_list, sc, link);
2210 sx_xunlock(&t4_list_lock);
2214 t4_map_bars_0_and_4(struct adapter *sc)
2216 sc->regs_rid = PCIR_BAR(0);
2217 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2218 &sc->regs_rid, RF_ACTIVE);
2219 if (sc->regs_res == NULL) {
2220 device_printf(sc->dev, "cannot map registers.\n");
2223 sc->bt = rman_get_bustag(sc->regs_res);
2224 sc->bh = rman_get_bushandle(sc->regs_res);
2225 sc->mmio_len = rman_get_size(sc->regs_res);
2226 setbit(&sc->doorbells, DOORBELL_KDB);
2228 sc->msix_rid = PCIR_BAR(4);
2229 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2230 &sc->msix_rid, RF_ACTIVE);
2231 if (sc->msix_res == NULL) {
2232 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2240 t4_map_bar_2(struct adapter *sc)
2244 * T4: only iWARP driver uses the userspace doorbells. There is no need
2245 * to map it if RDMA is disabled.
2247 if (is_t4(sc) && sc->rdmacaps == 0)
2250 sc->udbs_rid = PCIR_BAR(2);
2251 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2252 &sc->udbs_rid, RF_ACTIVE);
2253 if (sc->udbs_res == NULL) {
2254 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2257 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2259 if (chip_id(sc) >= CHELSIO_T5) {
2260 setbit(&sc->doorbells, DOORBELL_UDB);
2261 #if defined(__i386__) || defined(__amd64__)
2262 if (t5_write_combine) {
2266 * Enable write combining on BAR2. This is the
2267 * userspace doorbell BAR and is split into 128B
2268 * (UDBS_SEG_SIZE) doorbell regions, each associated
2269 * with an egress queue. The first 64B has the doorbell
2270 * and the second 64B can be used to submit a tx work
2271 * request with an implicit doorbell.
2274 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2275 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2277 clrbit(&sc->doorbells, DOORBELL_UDB);
2278 setbit(&sc->doorbells, DOORBELL_WCWR);
2279 setbit(&sc->doorbells, DOORBELL_UDBWC);
2281 t5_write_combine = 0;
2282 device_printf(sc->dev,
2283 "couldn't enable write combining: %d\n",
2287 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2288 t4_write_reg(sc, A_SGE_STAT_CFG,
2289 V_STATSOURCE_T5(7) | mode);
2292 t5_write_combine = 0;
2294 sc->iwt.wc_en = t5_write_combine;
2300 struct memwin_init {
2305 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2306 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2307 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2308 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2311 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2312 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2313 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2314 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2318 setup_memwin(struct adapter *sc)
2320 const struct memwin_init *mw_init;
2327 * Read low 32b of bar0 indirectly via the hardware backdoor
2328 * mechanism. Works from within PCI passthrough environments
2329 * too, where rman_get_start() can return a different value. We
2330 * need to program the T4 memory window decoders with the actual
2331 * addresses that will be coming across the PCIe link.
2333 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2334 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2336 mw_init = &t4_memwin[0];
2338 /* T5+ use the relative offset inside the PCIe BAR */
2341 mw_init = &t5_memwin[0];
2344 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2345 rw_init(&mw->mw_lock, "memory window access");
2346 mw->mw_base = mw_init->base;
2347 mw->mw_aperture = mw_init->aperture;
2350 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2351 (mw->mw_base + bar0) | V_BIR(0) |
2352 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2353 rw_wlock(&mw->mw_lock);
2354 position_memwin(sc, i, 0);
2355 rw_wunlock(&mw->mw_lock);
2359 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2363 * Positions the memory window at the given address in the card's address space.
2364 * There are some alignment requirements and the actual position may be at an
2365 * address prior to the requested address. mw->mw_curpos always has the actual
2366 * position of the window.
2369 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2375 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2376 mw = &sc->memwin[idx];
2377 rw_assert(&mw->mw_lock, RA_WLOCKED);
2381 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2383 pf = V_PFNUM(sc->pf);
2384 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2386 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2387 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2388 t4_read_reg(sc, reg); /* flush */
2392 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2398 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2400 /* Memory can only be accessed in naturally aligned 4 byte units */
2401 if (addr & 3 || len & 3 || len <= 0)
2404 mw = &sc->memwin[idx];
2406 rw_rlock(&mw->mw_lock);
2407 mw_end = mw->mw_curpos + mw->mw_aperture;
2408 if (addr >= mw_end || addr < mw->mw_curpos) {
2409 /* Will need to reposition the window */
2410 if (!rw_try_upgrade(&mw->mw_lock)) {
2411 rw_runlock(&mw->mw_lock);
2412 rw_wlock(&mw->mw_lock);
2414 rw_assert(&mw->mw_lock, RA_WLOCKED);
2415 position_memwin(sc, idx, addr);
2416 rw_downgrade(&mw->mw_lock);
2417 mw_end = mw->mw_curpos + mw->mw_aperture;
2419 rw_assert(&mw->mw_lock, RA_RLOCKED);
2420 while (addr < mw_end && len > 0) {
2422 v = t4_read_reg(sc, mw->mw_base + addr -
2424 *val++ = le32toh(v);
2427 t4_write_reg(sc, mw->mw_base + addr -
2428 mw->mw_curpos, htole32(v));
2433 rw_runlock(&mw->mw_lock);
2440 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2444 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2448 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2449 const uint32_t *val, int len)
2452 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2456 t4_range_cmp(const void *a, const void *b)
2458 return ((const struct t4_range *)a)->start -
2459 ((const struct t4_range *)b)->start;
2463 * Verify that the memory range specified by the addr/len pair is valid within
2464 * the card's address space.
2467 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2469 struct t4_range mem_ranges[4], *r, *next;
2470 uint32_t em, addr_len;
2471 int i, n, remaining;
2473 /* Memory can only be accessed in naturally aligned 4 byte units */
2474 if (addr & 3 || len & 3 || len <= 0)
2477 /* Enabled memories */
2478 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2482 bzero(r, sizeof(mem_ranges));
2483 if (em & F_EDRAM0_ENABLE) {
2484 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2485 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2487 r->start = G_EDRAM0_BASE(addr_len) << 20;
2488 if (addr >= r->start &&
2489 addr + len <= r->start + r->size)
2495 if (em & F_EDRAM1_ENABLE) {
2496 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2497 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2499 r->start = G_EDRAM1_BASE(addr_len) << 20;
2500 if (addr >= r->start &&
2501 addr + len <= r->start + r->size)
2507 if (em & F_EXT_MEM_ENABLE) {
2508 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2509 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2511 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2512 if (addr >= r->start &&
2513 addr + len <= r->start + r->size)
2519 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2520 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2521 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2523 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2524 if (addr >= r->start &&
2525 addr + len <= r->start + r->size)
2531 MPASS(n <= nitems(mem_ranges));
2534 /* Sort and merge the ranges. */
2535 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2537 /* Start from index 0 and examine the next n - 1 entries. */
2539 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2541 MPASS(r->size > 0); /* r is a valid entry. */
2543 MPASS(next->size > 0); /* and so is the next one. */
2545 while (r->start + r->size >= next->start) {
2546 /* Merge the next one into the current entry. */
2547 r->size = max(r->start + r->size,
2548 next->start + next->size) - r->start;
2549 n--; /* One fewer entry in total. */
2550 if (--remaining == 0)
2551 goto done; /* short circuit */
2554 if (next != r + 1) {
2556 * Some entries were merged into r and next
2557 * points to the first valid entry that couldn't
2560 MPASS(next->size > 0); /* must be valid */
2561 memcpy(r + 1, next, remaining * sizeof(*r));
2564 * This so that the foo->size assertion in the
2565 * next iteration of the loop do the right
2566 * thing for entries that were pulled up and are
2569 MPASS(n < nitems(mem_ranges));
2570 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2571 sizeof(struct t4_range));
2576 /* Done merging the ranges. */
2579 for (i = 0; i < n; i++, r++) {
2580 if (addr >= r->start &&
2581 addr + len <= r->start + r->size)
2590 fwmtype_to_hwmtype(int mtype)
2594 case FW_MEMTYPE_EDC0:
2596 case FW_MEMTYPE_EDC1:
2598 case FW_MEMTYPE_EXTMEM:
2600 case FW_MEMTYPE_EXTMEM1:
2603 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2608 * Verify that the memory range specified by the memtype/offset/len pair is
2609 * valid and lies entirely within the memtype specified. The global address of
2610 * the start of the range is returned in addr.
2613 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2616 uint32_t em, addr_len, maddr;
2618 /* Memory can only be accessed in naturally aligned 4 byte units */
2619 if (off & 3 || len & 3 || len == 0)
2622 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2623 switch (fwmtype_to_hwmtype(mtype)) {
2625 if (!(em & F_EDRAM0_ENABLE))
2627 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2628 maddr = G_EDRAM0_BASE(addr_len) << 20;
2631 if (!(em & F_EDRAM1_ENABLE))
2633 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2634 maddr = G_EDRAM1_BASE(addr_len) << 20;
2637 if (!(em & F_EXT_MEM_ENABLE))
2639 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2640 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2643 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2645 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2646 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2652 *addr = maddr + off; /* global address */
2653 return (validate_mem_range(sc, *addr, len));
2657 fixup_devlog_params(struct adapter *sc)
2659 struct devlog_params *dparams = &sc->params.devlog;
2662 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2663 dparams->size, &dparams->addr);
2669 update_nirq(struct intrs_and_queues *iaq, int nports)
2671 int extra = T4_EXTRA_INTR;
2674 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
2675 iaq->nirq += nports * (iaq->num_vis - 1) *
2676 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
2677 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
2681 * Adjust requirements to fit the number of interrupts available.
2684 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
2688 const int nports = sc->params.nports;
2693 bzero(iaq, sizeof(*iaq));
2694 iaq->intr_type = itype;
2695 iaq->num_vis = t4_num_vis;
2696 iaq->ntxq = t4_ntxq;
2697 iaq->ntxq_vi = t4_ntxq_vi;
2698 iaq->nrxq = t4_nrxq;
2699 iaq->nrxq_vi = t4_nrxq_vi;
2701 if (is_offload(sc)) {
2702 iaq->nofldtxq = t4_nofldtxq;
2703 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2704 iaq->nofldrxq = t4_nofldrxq;
2705 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2709 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2710 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2713 update_nirq(iaq, nports);
2714 if (iaq->nirq <= navail &&
2715 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2717 * This is the normal case -- there are enough interrupts for
2724 * If extra VIs have been configured try reducing their count and see if
2727 while (iaq->num_vis > 1) {
2729 update_nirq(iaq, nports);
2730 if (iaq->nirq <= navail &&
2731 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2732 device_printf(sc->dev, "virtual interfaces per port "
2733 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
2734 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
2735 "itype %d, navail %u, nirq %d.\n",
2736 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
2737 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
2738 itype, navail, iaq->nirq);
2744 * Extra VIs will not be created. Log a message if they were requested.
2746 MPASS(iaq->num_vis == 1);
2747 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2748 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2749 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2750 if (iaq->num_vis != t4_num_vis) {
2751 device_printf(sc->dev, "extra virtual interfaces disabled. "
2752 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2753 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
2754 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
2755 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
2759 * Keep reducing the number of NIC rx queues to the next lower power of
2760 * 2 (for even RSS distribution) and halving the TOE rx queues and see
2764 if (iaq->nrxq > 1) {
2767 } while (!powerof2(iaq->nrxq));
2769 if (iaq->nofldrxq > 1)
2770 iaq->nofldrxq >>= 1;
2772 old_nirq = iaq->nirq;
2773 update_nirq(iaq, nports);
2774 if (iaq->nirq <= navail &&
2775 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2776 device_printf(sc->dev, "running with reduced number of "
2777 "rx queues because of shortage of interrupts. "
2778 "nrxq=%u, nofldrxq=%u. "
2779 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
2780 iaq->nofldrxq, itype, navail, iaq->nirq);
2783 } while (old_nirq != iaq->nirq);
2785 /* One interrupt for everything. Ugh. */
2786 device_printf(sc->dev, "running with minimal number of queues. "
2787 "itype %d, navail %u.\n", itype, navail);
2789 MPASS(iaq->nrxq == 1);
2791 if (iaq->nofldrxq > 1)
2794 MPASS(iaq->num_vis > 0);
2795 if (iaq->num_vis > 1) {
2796 MPASS(iaq->nrxq_vi > 0);
2797 MPASS(iaq->ntxq_vi > 0);
2799 MPASS(iaq->nirq > 0);
2800 MPASS(iaq->nrxq > 0);
2801 MPASS(iaq->ntxq > 0);
2802 if (itype == INTR_MSI) {
2803 MPASS(powerof2(iaq->nirq));
2808 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
2810 int rc, itype, navail, nalloc;
2812 for (itype = INTR_MSIX; itype; itype >>= 1) {
2814 if ((itype & t4_intr_types) == 0)
2815 continue; /* not allowed */
2817 if (itype == INTR_MSIX)
2818 navail = pci_msix_count(sc->dev);
2819 else if (itype == INTR_MSI)
2820 navail = pci_msi_count(sc->dev);
2827 calculate_iaq(sc, iaq, itype, navail);
2830 if (itype == INTR_MSIX)
2831 rc = pci_alloc_msix(sc->dev, &nalloc);
2832 else if (itype == INTR_MSI)
2833 rc = pci_alloc_msi(sc->dev, &nalloc);
2835 if (rc == 0 && nalloc > 0) {
2836 if (nalloc == iaq->nirq)
2840 * Didn't get the number requested. Use whatever number
2841 * the kernel is willing to allocate.
2843 device_printf(sc->dev, "fewer vectors than requested, "
2844 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2845 itype, iaq->nirq, nalloc);
2846 pci_release_msi(sc->dev);
2851 device_printf(sc->dev,
2852 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2853 itype, rc, iaq->nirq, nalloc);
2856 device_printf(sc->dev,
2857 "failed to find a usable interrupt type. "
2858 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2859 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2864 #define FW_VERSION(chip) ( \
2865 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2866 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2867 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2868 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2869 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2875 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2879 .kld_name = "t4fw_cfg",
2880 .fw_mod_name = "t4fw",
2882 .chip = FW_HDR_CHIP_T4,
2883 .fw_ver = htobe32_const(FW_VERSION(T4)),
2884 .intfver_nic = FW_INTFVER(T4, NIC),
2885 .intfver_vnic = FW_INTFVER(T4, VNIC),
2886 .intfver_ofld = FW_INTFVER(T4, OFLD),
2887 .intfver_ri = FW_INTFVER(T4, RI),
2888 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2889 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2890 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2891 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2895 .kld_name = "t5fw_cfg",
2896 .fw_mod_name = "t5fw",
2898 .chip = FW_HDR_CHIP_T5,
2899 .fw_ver = htobe32_const(FW_VERSION(T5)),
2900 .intfver_nic = FW_INTFVER(T5, NIC),
2901 .intfver_vnic = FW_INTFVER(T5, VNIC),
2902 .intfver_ofld = FW_INTFVER(T5, OFLD),
2903 .intfver_ri = FW_INTFVER(T5, RI),
2904 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2905 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2906 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2907 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2911 .kld_name = "t6fw_cfg",
2912 .fw_mod_name = "t6fw",
2914 .chip = FW_HDR_CHIP_T6,
2915 .fw_ver = htobe32_const(FW_VERSION(T6)),
2916 .intfver_nic = FW_INTFVER(T6, NIC),
2917 .intfver_vnic = FW_INTFVER(T6, VNIC),
2918 .intfver_ofld = FW_INTFVER(T6, OFLD),
2919 .intfver_ri = FW_INTFVER(T6, RI),
2920 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
2921 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2922 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
2923 .intfver_fcoe = FW_INTFVER(T6, FCOE),
2928 static struct fw_info *
2929 find_fw_info(int chip)
2933 for (i = 0; i < nitems(fw_info); i++) {
2934 if (fw_info[i].chip == chip)
2935 return (&fw_info[i]);
2941 * Is the given firmware API compatible with the one the driver was compiled
2945 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2948 /* short circuit if it's the exact same firmware version */
2949 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2953 * XXX: Is this too conservative? Perhaps I should limit this to the
2954 * features that are supported in the driver.
2956 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2957 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2958 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2959 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2967 * The firmware in the KLD is usable, but should it be installed? This routine
2968 * explains itself in detail if it indicates the KLD firmware should be
2972 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2976 if (!card_fw_usable) {
2977 reason = "incompatible or unusable";
2982 reason = "older than the version bundled with this driver";
2986 if (t4_fw_install == 2 && k != c) {
2987 reason = "different than the version bundled with this driver";
2994 if (t4_fw_install == 0) {
2995 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2996 "but the driver is prohibited from installing a different "
2997 "firmware on the card.\n",
2998 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2999 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3004 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3005 "installing firmware %u.%u.%u.%u on card.\n",
3006 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3007 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3008 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3009 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3015 * Establish contact with the firmware and determine if we are the master driver
3016 * or not, and whether we are responsible for chip initialization.
3019 prep_firmware(struct adapter *sc)
3021 const struct firmware *fw = NULL, *default_cfg;
3022 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
3023 enum dev_state state;
3024 struct fw_info *fw_info;
3025 struct fw_hdr *card_fw; /* fw on the card */
3026 const struct fw_hdr *kld_fw; /* fw in the KLD */
3027 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
3030 /* This is the firmware whose headers the driver was compiled against */
3031 fw_info = find_fw_info(chip_id(sc));
3032 if (fw_info == NULL) {
3033 device_printf(sc->dev,
3034 "unable to look up firmware information for chip %d.\n",
3038 drv_fw = &fw_info->fw_hdr;
3041 * The firmware KLD contains many modules. The KLD name is also the
3042 * name of the module that contains the default config file.
3044 default_cfg = firmware_get(fw_info->kld_name);
3046 /* This is the firmware in the KLD */
3047 fw = firmware_get(fw_info->fw_mod_name);
3049 kld_fw = (const void *)fw->data;
3050 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3056 /* Read the header of the firmware on the card */
3057 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3058 rc = -t4_read_flash(sc, FLASH_FW_START,
3059 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3061 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3062 if (card_fw->fw_ver == be32toh(0xffffffff)) {
3063 uint32_t d = be32toh(kld_fw->fw_ver);
3065 if (!kld_fw_usable) {
3066 device_printf(sc->dev,
3067 "no firmware on the card and no usable "
3068 "firmware bundled with the driver.\n");
3071 } else if (t4_fw_install == 0) {
3072 device_printf(sc->dev,
3073 "no firmware on the card and the driver "
3074 "is prohibited from installing new "
3080 device_printf(sc->dev, "no firmware on the card, "
3081 "installing firmware %d.%d.%d.%d\n",
3082 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3083 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3084 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize);
3087 device_printf(sc->dev,
3088 "firmware install failed: %d.\n", rc);
3091 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3096 device_printf(sc->dev,
3097 "Unable to read card's firmware header: %d\n", rc);
3101 /* Contact firmware. */
3102 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3103 if (rc < 0 || state == DEV_STATE_ERR) {
3105 device_printf(sc->dev,
3106 "failed to connect to the firmware: %d, %d.\n", rc, state);
3111 sc->flags |= MASTER_PF;
3112 else if (state == DEV_STATE_UNINIT) {
3114 * We didn't get to be the master so we definitely won't be
3115 * configuring the chip. It's a bug if someone else hasn't
3116 * configured it already.
3118 device_printf(sc->dev, "couldn't be master(%d), "
3119 "device not already initialized either(%d).\n", rc, state);
3124 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3125 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3127 * Common case: the firmware on the card is an exact match and
3128 * the KLD is an exact match too, or the KLD is
3129 * absent/incompatible. Note that t4_fw_install = 2 is ignored
3130 * here -- use cxgbetool loadfw if you want to reinstall the
3131 * same firmware as the one on the card.
3133 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3134 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3135 be32toh(card_fw->fw_ver))) {
3137 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3139 device_printf(sc->dev,
3140 "failed to install firmware: %d\n", rc);
3144 /* Installed successfully, update the cached header too. */
3145 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3147 need_fw_reset = 0; /* already reset as part of load_fw */
3150 if (!card_fw_usable) {
3153 d = ntohl(drv_fw->fw_ver);
3154 c = ntohl(card_fw->fw_ver);
3155 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3157 device_printf(sc->dev, "Cannot find a usable firmware: "
3158 "fw_install %d, chip state %d, "
3159 "driver compiled with %d.%d.%d.%d, "
3160 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3161 t4_fw_install, state,
3162 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3163 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3164 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3165 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3166 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3167 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3173 if (need_fw_reset &&
3174 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3175 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3176 if (rc != ETIMEDOUT && rc != EIO)
3177 t4_fw_bye(sc, sc->mbox);
3182 rc = get_params__pre_init(sc);
3184 goto done; /* error message displayed already */
3186 /* Partition adapter resources as specified in the config file. */
3187 if (state == DEV_STATE_UNINIT) {
3189 KASSERT(sc->flags & MASTER_PF,
3190 ("%s: trying to change chip settings when not master.",
3193 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3195 goto done; /* error message displayed already */
3197 t4_tweak_chip_settings(sc);
3199 /* get basic stuff going */
3200 rc = -t4_fw_initialize(sc, sc->mbox);
3202 device_printf(sc->dev, "fw init failed: %d.\n", rc);
3206 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3211 free(card_fw, M_CXGBE);
3213 firmware_put(fw, FIRMWARE_UNLOAD);
3214 if (default_cfg != NULL)
3215 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3220 #define FW_PARAM_DEV(param) \
3221 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3222 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3223 #define FW_PARAM_PFVF(param) \
3224 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3225 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3228 * Partition chip resources for use between various PFs, VFs, etc.
3231 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3232 const char *name_prefix)
3234 const struct firmware *cfg = NULL;
3236 struct fw_caps_config_cmd caps;
3237 uint32_t mtype, moff, finicsum, cfcsum;
3240 * Figure out what configuration file to use. Pick the default config
3241 * file for the card if the user hasn't specified one explicitly.
3243 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3244 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3245 /* Card specific overrides go here. */
3246 if (pci_get_device(sc->dev) == 0x440a)
3247 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3249 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3253 * We need to load another module if the profile is anything except
3254 * "default" or "flash".
3256 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3257 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3260 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3261 cfg = firmware_get(s);
3263 if (default_cfg != NULL) {
3264 device_printf(sc->dev,
3265 "unable to load module \"%s\" for "
3266 "configuration profile \"%s\", will use "
3267 "the default config file instead.\n",
3269 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3272 device_printf(sc->dev,
3273 "unable to load module \"%s\" for "
3274 "configuration profile \"%s\", will use "
3275 "the config file on the card's flash "
3276 "instead.\n", s, sc->cfg_file);
3277 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3283 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3284 default_cfg == NULL) {
3285 device_printf(sc->dev,
3286 "default config file not available, will use the config "
3287 "file on the card's flash instead.\n");
3288 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3291 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3293 const uint32_t *cfdata;
3294 uint32_t param, val, addr;
3296 KASSERT(cfg != NULL || default_cfg != NULL,
3297 ("%s: no config to upload", __func__));
3300 * Ask the firmware where it wants us to upload the config file.
3302 param = FW_PARAM_DEV(CF);
3303 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3305 /* No support for config file? Shouldn't happen. */
3306 device_printf(sc->dev,
3307 "failed to query config file location: %d.\n", rc);
3310 mtype = G_FW_PARAMS_PARAM_Y(val);
3311 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3314 * XXX: sheer laziness. We deliberately added 4 bytes of
3315 * useless stuffing/comments at the end of the config file so
3316 * it's ok to simply throw away the last remaining bytes when
3317 * the config file is not an exact multiple of 4. This also
3318 * helps with the validate_mt_off_len check.
3321 cflen = cfg->datasize & ~3;
3324 cflen = default_cfg->datasize & ~3;
3325 cfdata = default_cfg->data;
3328 if (cflen > FLASH_CFG_MAX_SIZE) {
3329 device_printf(sc->dev,
3330 "config file too long (%d, max allowed is %d). "
3331 "Will try to use the config on the card, if any.\n",
3332 cflen, FLASH_CFG_MAX_SIZE);
3333 goto use_config_on_flash;
3336 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3338 device_printf(sc->dev,
3339 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3340 "Will try to use the config on the card, if any.\n",
3341 __func__, mtype, moff, cflen, rc);
3342 goto use_config_on_flash;
3344 write_via_memwin(sc, 2, addr, cfdata, cflen);
3346 use_config_on_flash:
3347 mtype = FW_MEMTYPE_FLASH;
3348 moff = t4_flash_cfg_addr(sc);
3351 bzero(&caps, sizeof(caps));
3352 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3353 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3354 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3355 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3356 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3357 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3359 device_printf(sc->dev,
3360 "failed to pre-process config file: %d "
3361 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3365 finicsum = be32toh(caps.finicsum);
3366 cfcsum = be32toh(caps.cfcsum);
3367 if (finicsum != cfcsum) {
3368 device_printf(sc->dev,
3369 "WARNING: config file checksum mismatch: %08x %08x\n",
3372 sc->cfcsum = cfcsum;
3374 #define LIMIT_CAPS(x) do { \
3375 caps.x &= htobe16(t4_##x##_allowed); \
3379 * Let the firmware know what features will (not) be used so it can tune
3380 * things accordingly.
3382 LIMIT_CAPS(nbmcaps);
3383 LIMIT_CAPS(linkcaps);
3384 LIMIT_CAPS(switchcaps);
3385 LIMIT_CAPS(niccaps);
3386 LIMIT_CAPS(toecaps);
3387 LIMIT_CAPS(rdmacaps);
3388 LIMIT_CAPS(cryptocaps);
3389 LIMIT_CAPS(iscsicaps);
3390 LIMIT_CAPS(fcoecaps);
3393 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3394 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3395 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3396 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3398 device_printf(sc->dev,
3399 "failed to process config file: %d.\n", rc);
3403 firmware_put(cfg, FIRMWARE_UNLOAD);
3408 * Retrieve parameters that are needed (or nice to have) very early.
3411 get_params__pre_init(struct adapter *sc)
3414 uint32_t param[2], val[2];
3416 t4_get_version_info(sc);
3418 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3419 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3420 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3421 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3422 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3424 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3425 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3426 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3427 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3428 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3430 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3431 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3432 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3433 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3434 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3436 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3437 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3438 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3439 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3440 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3442 param[0] = FW_PARAM_DEV(PORTVEC);
3443 param[1] = FW_PARAM_DEV(CCLK);
3444 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3446 device_printf(sc->dev,
3447 "failed to query parameters (pre_init): %d.\n", rc);
3451 sc->params.portvec = val[0];
3452 sc->params.nports = bitcount32(val[0]);
3453 sc->params.vpd.cclk = val[1];
3455 /* Read device log parameters. */
3456 rc = -t4_init_devlog_params(sc, 1);
3458 fixup_devlog_params(sc);
3460 device_printf(sc->dev,
3461 "failed to get devlog parameters: %d.\n", rc);
3462 rc = 0; /* devlog isn't critical for device operation */
3469 * Retrieve various parameters that are of interest to the driver. The device
3470 * has been initialized by the firmware at this point.
3473 get_params__post_init(struct adapter *sc)
3476 uint32_t param[7], val[7];
3477 struct fw_caps_config_cmd caps;
3479 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3480 param[1] = FW_PARAM_PFVF(EQ_START);
3481 param[2] = FW_PARAM_PFVF(FILTER_START);
3482 param[3] = FW_PARAM_PFVF(FILTER_END);
3483 param[4] = FW_PARAM_PFVF(L2T_START);
3484 param[5] = FW_PARAM_PFVF(L2T_END);
3485 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3486 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
3487 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
3488 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
3490 device_printf(sc->dev,
3491 "failed to query parameters (post_init): %d.\n", rc);
3495 sc->sge.iq_start = val[0];
3496 sc->sge.eq_start = val[1];
3497 sc->tids.ftid_base = val[2];
3498 sc->tids.nftids = val[3] - val[2] + 1;
3499 sc->params.ftid_min = val[2];
3500 sc->params.ftid_max = val[3];
3501 sc->vres.l2t.start = val[4];
3502 sc->vres.l2t.size = val[5] - val[4] + 1;
3503 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3504 ("%s: L2 table size (%u) larger than expected (%u)",
3505 __func__, sc->vres.l2t.size, L2T_SIZE));
3506 sc->params.core_vdd = val[6];
3509 * MPSBGMAP is queried separately because only recent firmwares support
3510 * it as a parameter and we don't want the compound query above to fail
3511 * on older firmwares.
3513 param[0] = FW_PARAM_DEV(MPSBGMAP);
3515 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3517 sc->params.mps_bg_map = val[0];
3519 sc->params.mps_bg_map = 0;
3521 /* get capabilites */
3522 bzero(&caps, sizeof(caps));
3523 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3524 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3525 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3526 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3528 device_printf(sc->dev,
3529 "failed to get card capabilities: %d.\n", rc);
3533 #define READ_CAPS(x) do { \
3534 sc->x = htobe16(caps.x); \
3537 READ_CAPS(linkcaps);
3538 READ_CAPS(switchcaps);
3541 READ_CAPS(rdmacaps);
3542 READ_CAPS(cryptocaps);
3543 READ_CAPS(iscsicaps);
3544 READ_CAPS(fcoecaps);
3547 * The firmware attempts memfree TOE configuration for -SO cards and
3548 * will report toecaps=0 if it runs out of resources (this depends on
3549 * the config file). It may not report 0 for other capabilities
3550 * dependent on the TOE in this case. Set them to 0 here so that the
3551 * driver doesn't bother tracking resources that will never be used.
3553 if (sc->toecaps == 0) {
3558 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3559 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3560 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3561 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3562 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3564 device_printf(sc->dev,
3565 "failed to query NIC parameters: %d.\n", rc);
3568 sc->tids.etid_base = val[0];
3569 sc->params.etid_min = val[0];
3570 sc->tids.netids = val[1] - val[0] + 1;
3571 sc->params.netids = sc->tids.netids;
3572 sc->params.eo_wr_cred = val[2];
3573 sc->params.ethoffload = 1;
3577 /* query offload-related parameters */
3578 param[0] = FW_PARAM_DEV(NTID);
3579 param[1] = FW_PARAM_PFVF(SERVER_START);
3580 param[2] = FW_PARAM_PFVF(SERVER_END);
3581 param[3] = FW_PARAM_PFVF(TDDP_START);
3582 param[4] = FW_PARAM_PFVF(TDDP_END);
3583 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3584 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3586 device_printf(sc->dev,
3587 "failed to query TOE parameters: %d.\n", rc);
3590 sc->tids.ntids = val[0];
3591 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3592 sc->tids.stid_base = val[1];
3593 sc->tids.nstids = val[2] - val[1] + 1;
3594 sc->vres.ddp.start = val[3];
3595 sc->vres.ddp.size = val[4] - val[3] + 1;
3596 sc->params.ofldq_wr_cred = val[5];
3597 sc->params.offload = 1;
3600 param[0] = FW_PARAM_PFVF(STAG_START);
3601 param[1] = FW_PARAM_PFVF(STAG_END);
3602 param[2] = FW_PARAM_PFVF(RQ_START);
3603 param[3] = FW_PARAM_PFVF(RQ_END);
3604 param[4] = FW_PARAM_PFVF(PBL_START);
3605 param[5] = FW_PARAM_PFVF(PBL_END);
3606 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3608 device_printf(sc->dev,
3609 "failed to query RDMA parameters(1): %d.\n", rc);
3612 sc->vres.stag.start = val[0];
3613 sc->vres.stag.size = val[1] - val[0] + 1;
3614 sc->vres.rq.start = val[2];
3615 sc->vres.rq.size = val[3] - val[2] + 1;
3616 sc->vres.pbl.start = val[4];
3617 sc->vres.pbl.size = val[5] - val[4] + 1;
3619 param[0] = FW_PARAM_PFVF(SQRQ_START);
3620 param[1] = FW_PARAM_PFVF(SQRQ_END);
3621 param[2] = FW_PARAM_PFVF(CQ_START);
3622 param[3] = FW_PARAM_PFVF(CQ_END);
3623 param[4] = FW_PARAM_PFVF(OCQ_START);
3624 param[5] = FW_PARAM_PFVF(OCQ_END);
3625 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3627 device_printf(sc->dev,
3628 "failed to query RDMA parameters(2): %d.\n", rc);
3631 sc->vres.qp.start = val[0];
3632 sc->vres.qp.size = val[1] - val[0] + 1;
3633 sc->vres.cq.start = val[2];
3634 sc->vres.cq.size = val[3] - val[2] + 1;
3635 sc->vres.ocq.start = val[4];
3636 sc->vres.ocq.size = val[5] - val[4] + 1;
3638 param[0] = FW_PARAM_PFVF(SRQ_START);
3639 param[1] = FW_PARAM_PFVF(SRQ_END);
3640 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
3641 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3642 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
3644 device_printf(sc->dev,
3645 "failed to query RDMA parameters(3): %d.\n", rc);
3648 sc->vres.srq.start = val[0];
3649 sc->vres.srq.size = val[1] - val[0] + 1;
3650 sc->params.max_ordird_qp = val[2];
3651 sc->params.max_ird_adapter = val[3];
3653 if (sc->iscsicaps) {
3654 param[0] = FW_PARAM_PFVF(ISCSI_START);
3655 param[1] = FW_PARAM_PFVF(ISCSI_END);
3656 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3658 device_printf(sc->dev,
3659 "failed to query iSCSI parameters: %d.\n", rc);
3662 sc->vres.iscsi.start = val[0];
3663 sc->vres.iscsi.size = val[1] - val[0] + 1;
3666 t4_init_sge_params(sc);
3669 * We've got the params we wanted to query via the firmware. Now grab
3670 * some others directly from the chip.
3672 rc = t4_read_chip_settings(sc);
3678 set_params__post_init(struct adapter *sc)
3680 uint32_t param, val;
3685 /* ask for encapsulated CPLs */
3686 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3688 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3692 * Override the TOE timers with user provided tunables. This is not the
3693 * recommended way to change the timers (the firmware config file is) so
3694 * these tunables are not documented.
3696 * All the timer tunables are in microseconds.
3698 if (t4_toe_keepalive_idle != 0) {
3699 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
3700 v &= M_KEEPALIVEIDLE;
3701 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
3702 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
3704 if (t4_toe_keepalive_interval != 0) {
3705 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
3706 v &= M_KEEPALIVEINTVL;
3707 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
3708 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
3710 if (t4_toe_keepalive_count != 0) {
3711 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
3712 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
3713 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
3714 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
3715 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
3717 if (t4_toe_rexmt_min != 0) {
3718 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
3720 t4_set_reg_field(sc, A_TP_RXT_MIN,
3721 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
3723 if (t4_toe_rexmt_max != 0) {
3724 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
3726 t4_set_reg_field(sc, A_TP_RXT_MAX,
3727 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
3729 if (t4_toe_rexmt_count != 0) {
3730 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
3731 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
3732 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
3733 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
3734 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
3736 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
3737 if (t4_toe_rexmt_backoff[i] != -1) {
3738 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
3739 shift = (i & 3) << 3;
3740 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
3741 M_TIMERBACKOFFINDEX0 << shift, v << shift);
3748 #undef FW_PARAM_PFVF
3752 t4_set_desc(struct adapter *sc)
3755 struct adapter_params *p = &sc->params;
3757 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3759 device_set_desc_copy(sc->dev, buf);
3763 build_medialist(struct port_info *pi, struct ifmedia *media)
3767 PORT_LOCK_ASSERT_OWNED(pi);
3769 ifmedia_removeall(media);
3772 * XXX: Would it be better to ifmedia_add all 4 combinations of pause
3773 * settings for every speed instead of just txpause|rxpause? ifconfig
3774 * media display looks much better if autoselect is the only case where
3775 * ifm_current is different from ifm_active. If the user picks anything
3776 * except txpause|rxpause the display is ugly.
3778 m = IFM_ETHER | IFM_FDX | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
3780 switch(pi->port_type) {
3781 case FW_PORT_TYPE_BT_XFI:
3782 case FW_PORT_TYPE_BT_XAUI:
3783 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3786 case FW_PORT_TYPE_BT_SGMII:
3787 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3788 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3789 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3790 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3793 case FW_PORT_TYPE_CX4:
3794 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3795 ifmedia_set(media, m | IFM_10G_CX4);
3798 case FW_PORT_TYPE_QSFP_10G:
3799 case FW_PORT_TYPE_SFP:
3800 case FW_PORT_TYPE_FIBER_XFI:
3801 case FW_PORT_TYPE_FIBER_XAUI:
3802 switch (pi->mod_type) {
3804 case FW_PORT_MOD_TYPE_LR:
3805 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3806 ifmedia_set(media, m | IFM_10G_LR);
3809 case FW_PORT_MOD_TYPE_SR:
3810 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3811 ifmedia_set(media, m | IFM_10G_SR);
3814 case FW_PORT_MOD_TYPE_LRM:
3815 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3816 ifmedia_set(media, m | IFM_10G_LRM);
3819 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3820 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3821 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3822 ifmedia_set(media, m | IFM_10G_TWINAX);
3825 case FW_PORT_MOD_TYPE_NONE:
3827 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3828 ifmedia_set(media, m | IFM_NONE);
3831 case FW_PORT_MOD_TYPE_NA:
3832 case FW_PORT_MOD_TYPE_ER:
3834 device_printf(pi->dev,
3835 "unknown port_type (%d), mod_type (%d)\n",
3836 pi->port_type, pi->mod_type);
3837 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3838 ifmedia_set(media, m | IFM_UNKNOWN);
3843 case FW_PORT_TYPE_CR_QSFP:
3844 case FW_PORT_TYPE_SFP28:
3845 case FW_PORT_TYPE_KR_SFP28:
3846 switch (pi->mod_type) {
3848 case FW_PORT_MOD_TYPE_SR:
3849 ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
3850 ifmedia_set(media, m | IFM_25G_SR);
3853 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3854 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3855 ifmedia_add(media, m | IFM_25G_CR, 0, NULL);
3856 ifmedia_set(media, m | IFM_25G_CR);
3859 case FW_PORT_MOD_TYPE_NONE:
3861 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3862 ifmedia_set(media, m | IFM_NONE);
3866 device_printf(pi->dev,
3867 "unknown port_type (%d), mod_type (%d)\n",
3868 pi->port_type, pi->mod_type);
3869 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3870 ifmedia_set(media, m | IFM_UNKNOWN);
3875 case FW_PORT_TYPE_QSFP:
3876 switch (pi->mod_type) {
3878 case FW_PORT_MOD_TYPE_LR:
3879 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3880 ifmedia_set(media, m | IFM_40G_LR4);
3883 case FW_PORT_MOD_TYPE_SR:
3884 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3885 ifmedia_set(media, m | IFM_40G_SR4);
3888 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3889 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3890 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3891 ifmedia_set(media, m | IFM_40G_CR4);
3894 case FW_PORT_MOD_TYPE_NONE:
3896 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3897 ifmedia_set(media, m | IFM_NONE);
3901 device_printf(pi->dev,
3902 "unknown port_type (%d), mod_type (%d)\n",
3903 pi->port_type, pi->mod_type);
3904 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3905 ifmedia_set(media, m | IFM_UNKNOWN);
3910 case FW_PORT_TYPE_KR4_100G:
3911 case FW_PORT_TYPE_CR4_QSFP:
3912 switch (pi->mod_type) {
3914 case FW_PORT_MOD_TYPE_LR:
3915 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL);
3916 ifmedia_set(media, m | IFM_100G_LR4);
3919 case FW_PORT_MOD_TYPE_SR:
3920 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL);
3921 ifmedia_set(media, m | IFM_100G_SR4);
3924 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3925 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3926 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL);
3927 ifmedia_set(media, m | IFM_100G_CR4);
3930 case FW_PORT_MOD_TYPE_NONE:
3932 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3933 ifmedia_set(media, m | IFM_NONE);
3937 device_printf(pi->dev,
3938 "unknown port_type (%d), mod_type (%d)\n",
3939 pi->port_type, pi->mod_type);
3940 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3941 ifmedia_set(media, m | IFM_UNKNOWN);
3947 device_printf(pi->dev,
3948 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3950 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3951 ifmedia_set(media, m | IFM_UNKNOWN);
3957 * Update all the requested_* fields in the link config and then send a mailbox
3958 * command to apply the settings.
3961 init_l1cfg(struct port_info *pi)
3963 struct adapter *sc = pi->adapter;
3964 struct link_config *lc = &pi->link_cfg;
3967 ASSERT_SYNCHRONIZED_OP(sc);
3969 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) {
3970 lc->requested_aneg = AUTONEG_ENABLE;
3971 lc->requested_speed = 0;
3973 lc->requested_aneg = AUTONEG_DISABLE;
3974 lc->requested_speed = port_top_speed(pi); /* in Gbps */
3977 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX);
3980 lc->requested_fec = t4_fec & (FEC_RS | FEC_BASER_RS |
3983 /* Use the suggested value provided by the firmware in acaps */
3984 if (lc->advertising & FW_PORT_CAP_FEC_RS)
3985 lc->requested_fec = FEC_RS;
3986 else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS)
3987 lc->requested_fec = FEC_BASER_RS;
3988 else if (lc->advertising & FW_PORT_CAP_FEC_RESERVED)
3989 lc->requested_fec = FEC_RESERVED;
3991 lc->requested_fec = 0;
3994 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
3996 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
3998 lc->fc = lc->requested_fc;
3999 lc->fec = lc->requested_fec;
4003 #define FW_MAC_EXACT_CHUNK 7
4006 * Program the port's XGMAC based on parameters in ifnet. The caller also
4007 * indicates which parameters should be programmed (the rest are left alone).
4010 update_mac_settings(struct ifnet *ifp, int flags)
4013 struct vi_info *vi = ifp->if_softc;
4014 struct port_info *pi = vi->pi;
4015 struct adapter *sc = pi->adapter;
4016 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4018 ASSERT_SYNCHRONIZED_OP(sc);
4019 KASSERT(flags, ("%s: not told what to update.", __func__));
4021 if (flags & XGMAC_MTU)
4024 if (flags & XGMAC_PROMISC)
4025 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4027 if (flags & XGMAC_ALLMULTI)
4028 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4030 if (flags & XGMAC_VLANEX)
4031 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4033 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4034 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4035 allmulti, 1, vlanex, false);
4037 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4043 if (flags & XGMAC_UCADDR) {
4044 uint8_t ucaddr[ETHER_ADDR_LEN];
4046 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4047 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4048 ucaddr, true, true);
4051 if_printf(ifp, "change_mac failed: %d\n", rc);
4054 vi->xact_addr_filt = rc;
4059 if (flags & XGMAC_MCADDRS) {
4060 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4063 struct ifmultiaddr *ifma;
4066 if_maddr_rlock(ifp);
4067 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4068 if (ifma->ifma_addr->sa_family != AF_LINK)
4071 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4072 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4075 if (i == FW_MAC_EXACT_CHUNK) {
4076 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4077 del, i, mcaddr, NULL, &hash, 0);
4080 for (j = 0; j < i; j++) {
4082 "failed to add mc address"
4084 "%02x:%02x:%02x rc=%d\n",
4085 mcaddr[j][0], mcaddr[j][1],
4086 mcaddr[j][2], mcaddr[j][3],
4087 mcaddr[j][4], mcaddr[j][5],
4097 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4098 mcaddr, NULL, &hash, 0);
4101 for (j = 0; j < i; j++) {
4103 "failed to add mc address"
4105 "%02x:%02x:%02x rc=%d\n",
4106 mcaddr[j][0], mcaddr[j][1],
4107 mcaddr[j][2], mcaddr[j][3],
4108 mcaddr[j][4], mcaddr[j][5],
4115 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4117 if_printf(ifp, "failed to set mc address hash: %d", rc);
4119 if_maddr_runlock(ifp);
4126 * {begin|end}_synchronized_op must be called from the same thread.
4129 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4135 /* the caller thinks it's ok to sleep, but is it really? */
4136 if (flags & SLEEP_OK)
4137 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4138 "begin_synchronized_op");
4149 if (vi && IS_DOOMED(vi)) {
4159 if (!(flags & SLEEP_OK)) {
4164 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4170 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4173 sc->last_op = wmesg;
4174 sc->last_op_thr = curthread;
4175 sc->last_op_flags = flags;
4179 if (!(flags & HOLD_LOCK) || rc)
4186 * Tell if_ioctl and if_init that the VI is going away. This is
4187 * special variant of begin_synchronized_op and must be paired with a
4188 * call to end_synchronized_op.
4191 doom_vi(struct adapter *sc, struct vi_info *vi)
4198 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4201 sc->last_op = "t4detach";
4202 sc->last_op_thr = curthread;
4203 sc->last_op_flags = 0;
4209 * {begin|end}_synchronized_op must be called from the same thread.
4212 end_synchronized_op(struct adapter *sc, int flags)
4215 if (flags & LOCK_HELD)
4216 ADAPTER_LOCK_ASSERT_OWNED(sc);
4220 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4227 cxgbe_init_synchronized(struct vi_info *vi)
4229 struct port_info *pi = vi->pi;
4230 struct adapter *sc = pi->adapter;
4231 struct ifnet *ifp = vi->ifp;
4233 struct sge_txq *txq;
4235 ASSERT_SYNCHRONIZED_OP(sc);
4237 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4238 return (0); /* already running */
4240 if (!(sc->flags & FULL_INIT_DONE) &&
4241 ((rc = adapter_full_init(sc)) != 0))
4242 return (rc); /* error message displayed already */
4244 if (!(vi->flags & VI_INIT_DONE) &&
4245 ((rc = vi_full_init(vi)) != 0))
4246 return (rc); /* error message displayed already */
4248 rc = update_mac_settings(ifp, XGMAC_ALL);
4250 goto done; /* error message displayed already */
4252 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4254 if_printf(ifp, "enable_vi failed: %d\n", rc);
4259 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
4263 for_each_txq(vi, i, txq) {
4265 txq->eq.flags |= EQ_ENABLED;
4270 * The first iq of the first port to come up is used for tracing.
4272 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4273 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4274 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
4275 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4276 V_QUEUENUMBER(sc->traceq));
4277 pi->flags |= HAS_TRACEQ;
4282 if (pi->up_vis++ == 0) {
4283 t4_update_port_info(pi);
4284 build_medialist(pi, &pi->media);
4287 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4289 if (pi->nvi > 1 || sc->flags & IS_VF)
4290 callout_reset(&vi->tick, hz, vi_tick, vi);
4292 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4296 cxgbe_uninit_synchronized(vi);
4305 cxgbe_uninit_synchronized(struct vi_info *vi)
4307 struct port_info *pi = vi->pi;
4308 struct adapter *sc = pi->adapter;
4309 struct ifnet *ifp = vi->ifp;
4311 struct sge_txq *txq;
4313 ASSERT_SYNCHRONIZED_OP(sc);
4315 if (!(vi->flags & VI_INIT_DONE)) {
4316 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
4317 ("uninited VI is running"));
4322 * Disable the VI so that all its data in either direction is discarded
4323 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
4324 * tick) intact as the TP can deliver negative advice or data that it's
4325 * holding in its RAM (for an offloaded connection) even after the VI is
4328 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4330 if_printf(ifp, "disable_vi failed: %d\n", rc);
4334 for_each_txq(vi, i, txq) {
4336 txq->eq.flags &= ~EQ_ENABLED;
4341 if (pi->nvi > 1 || sc->flags & IS_VF)
4342 callout_stop(&vi->tick);
4344 callout_stop(&pi->tick);
4345 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4349 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4351 if (pi->up_vis > 0) {
4357 pi->link_cfg.link_ok = 0;
4358 pi->link_cfg.speed = 0;
4359 pi->link_cfg.link_down_rc = 255;
4360 t4_os_link_changed(pi);
4361 pi->old_link_cfg = pi->link_cfg;
4367 * It is ok for this function to fail midway and return right away. t4_detach
4368 * will walk the entire sc->irq list and clean up whatever is valid.
4371 t4_setup_intr_handlers(struct adapter *sc)
4373 int rc, rid, p, q, v;
4376 struct port_info *pi;
4378 struct sge *sge = &sc->sge;
4379 struct sge_rxq *rxq;
4381 struct sge_ofld_rxq *ofld_rxq;
4384 struct sge_nm_rxq *nm_rxq;
4387 int nbuckets = rss_getnumbuckets();
4394 rid = sc->intr_type == INTR_INTX ? 0 : 1;
4395 if (forwarding_intr_to_fwq(sc))
4396 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4398 /* Multiple interrupts. */
4399 if (sc->flags & IS_VF)
4400 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4401 ("%s: too few intr.", __func__));
4403 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4404 ("%s: too few intr.", __func__));
4406 /* The first one is always error intr on PFs */
4407 if (!(sc->flags & IS_VF)) {
4408 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4415 /* The second one is always the firmware event queue (first on VFs) */
4416 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4422 for_each_port(sc, p) {
4424 for_each_vi(pi, v, vi) {
4425 vi->first_intr = rid - 1;
4427 if (vi->nnmrxq > 0) {
4428 int n = max(vi->nrxq, vi->nnmrxq);
4430 rxq = &sge->rxq[vi->first_rxq];
4432 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4434 for (q = 0; q < n; q++) {
4435 snprintf(s, sizeof(s), "%x%c%x", p,
4441 irq->nm_rxq = nm_rxq++;
4443 rc = t4_alloc_irq(sc, irq, rid,
4444 t4_vi_intr, irq, s);
4449 bus_bind_intr(sc->dev, irq->res,
4450 rss_getcpu(q % nbuckets));
4458 for_each_rxq(vi, q, rxq) {
4459 snprintf(s, sizeof(s), "%x%c%x", p,
4461 rc = t4_alloc_irq(sc, irq, rid,
4466 bus_bind_intr(sc->dev, irq->res,
4467 rss_getcpu(q % nbuckets));
4475 for_each_ofld_rxq(vi, q, ofld_rxq) {
4476 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
4477 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
4488 MPASS(irq == &sc->irq[sc->intr_count]);
4494 adapter_full_init(struct adapter *sc)
4498 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4499 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4502 ASSERT_SYNCHRONIZED_OP(sc);
4503 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4504 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4505 ("%s: FULL_INIT_DONE already", __func__));
4508 * queues that belong to the adapter (not any particular port).
4510 rc = t4_setup_adapter_queues(sc);
4514 for (i = 0; i < nitems(sc->tq); i++) {
4515 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4516 taskqueue_thread_enqueue, &sc->tq[i]);
4517 if (sc->tq[i] == NULL) {
4518 device_printf(sc->dev,
4519 "failed to allocate task queue %d\n", i);
4523 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4524 device_get_nameunit(sc->dev), i);
4527 MPASS(RSS_KEYSIZE == 40);
4528 rss_getkey((void *)&raw_rss_key[0]);
4529 for (i = 0; i < nitems(rss_key); i++) {
4530 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4532 t4_write_rss_key(sc, &rss_key[0], -1, 1);
4535 if (!(sc->flags & IS_VF))
4537 sc->flags |= FULL_INIT_DONE;
4540 adapter_full_uninit(sc);
4546 adapter_full_uninit(struct adapter *sc)
4550 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4552 t4_teardown_adapter_queues(sc);
4554 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4555 taskqueue_free(sc->tq[i]);
4559 sc->flags &= ~FULL_INIT_DONE;
4565 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4566 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4567 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4568 RSS_HASHTYPE_RSS_UDP_IPV6)
4570 /* Translates kernel hash types to hardware. */
4572 hashconfig_to_hashen(int hashconfig)
4576 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4577 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4578 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4579 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4580 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4581 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4582 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4584 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4585 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4586 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4588 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4589 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4590 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4591 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4596 /* Translates hardware hash types to kernel. */
4598 hashen_to_hashconfig(int hashen)
4602 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4604 * If UDP hashing was enabled it must have been enabled for
4605 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4606 * enabling any 4-tuple hash is nonsense configuration.
4608 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4609 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4611 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4612 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4613 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4614 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4616 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4617 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4618 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4619 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4620 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4621 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4622 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4623 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4625 return (hashconfig);
4630 vi_full_init(struct vi_info *vi)
4632 struct adapter *sc = vi->pi->adapter;
4633 struct ifnet *ifp = vi->ifp;
4635 struct sge_rxq *rxq;
4636 int rc, i, j, hashen;
4638 int nbuckets = rss_getnumbuckets();
4639 int hashconfig = rss_gethashconfig();
4643 ASSERT_SYNCHRONIZED_OP(sc);
4644 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4645 ("%s: VI_INIT_DONE already", __func__));
4647 sysctl_ctx_init(&vi->ctx);
4648 vi->flags |= VI_SYSCTL_CTX;
4651 * Allocate tx/rx/fl queues for this VI.
4653 rc = t4_setup_vi_queues(vi);
4655 goto done; /* error message displayed already */
4658 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4660 if (vi->nrxq > vi->rss_size) {
4661 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4662 "some queues will never receive traffic.\n", vi->nrxq,
4664 } else if (vi->rss_size % vi->nrxq) {
4665 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4666 "expect uneven traffic distribution.\n", vi->nrxq,
4670 if (vi->nrxq != nbuckets) {
4671 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4672 "performance will be impacted.\n", vi->nrxq, nbuckets);
4675 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4676 for (i = 0; i < vi->rss_size;) {
4678 j = rss_get_indirection_to_bucket(i);
4680 rxq = &sc->sge.rxq[vi->first_rxq + j];
4681 rss[i++] = rxq->iq.abs_id;
4683 for_each_rxq(vi, j, rxq) {
4684 rss[i++] = rxq->iq.abs_id;
4685 if (i == vi->rss_size)
4691 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4694 if_printf(ifp, "rss_config failed: %d\n", rc);
4699 hashen = hashconfig_to_hashen(hashconfig);
4702 * We may have had to enable some hashes even though the global config
4703 * wants them disabled. This is a potential problem that must be
4704 * reported to the user.
4706 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4709 * If we consider only the supported hash types, then the enabled hashes
4710 * are a superset of the requested hashes. In other words, there cannot
4711 * be any supported hash that was requested but not enabled, but there
4712 * can be hashes that were not requested but had to be enabled.
4714 extra &= SUPPORTED_RSS_HASHTYPES;
4715 MPASS((extra & hashconfig) == 0);
4719 "global RSS config (0x%x) cannot be accommodated.\n",
4722 if (extra & RSS_HASHTYPE_RSS_IPV4)
4723 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4724 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4725 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4726 if (extra & RSS_HASHTYPE_RSS_IPV6)
4727 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4728 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4729 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4730 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4731 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4732 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4733 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4735 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4736 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4737 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4738 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4740 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
4742 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4747 vi->flags |= VI_INIT_DONE;
4759 vi_full_uninit(struct vi_info *vi)
4761 struct port_info *pi = vi->pi;
4762 struct adapter *sc = pi->adapter;
4764 struct sge_rxq *rxq;
4765 struct sge_txq *txq;
4767 struct sge_ofld_rxq *ofld_rxq;
4768 struct sge_wrq *ofld_txq;
4771 if (vi->flags & VI_INIT_DONE) {
4773 /* Need to quiesce queues. */
4775 /* XXX: Only for the first VI? */
4776 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4777 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4779 for_each_txq(vi, i, txq) {
4780 quiesce_txq(sc, txq);
4784 for_each_ofld_txq(vi, i, ofld_txq) {
4785 quiesce_wrq(sc, ofld_txq);
4789 for_each_rxq(vi, i, rxq) {
4790 quiesce_iq(sc, &rxq->iq);
4791 quiesce_fl(sc, &rxq->fl);
4795 for_each_ofld_rxq(vi, i, ofld_rxq) {
4796 quiesce_iq(sc, &ofld_rxq->iq);
4797 quiesce_fl(sc, &ofld_rxq->fl);
4800 free(vi->rss, M_CXGBE);
4801 free(vi->nm_rss, M_CXGBE);
4804 t4_teardown_vi_queues(vi);
4805 vi->flags &= ~VI_INIT_DONE;
4811 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4813 struct sge_eq *eq = &txq->eq;
4814 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4816 (void) sc; /* unused */
4820 MPASS((eq->flags & EQ_ENABLED) == 0);
4824 /* Wait for the mp_ring to empty. */
4825 while (!mp_ring_is_idle(txq->r)) {
4826 mp_ring_check_drainage(txq->r, 0);
4827 pause("rquiesce", 1);
4830 /* Then wait for the hardware to finish. */
4831 while (spg->cidx != htobe16(eq->pidx))
4832 pause("equiesce", 1);
4834 /* Finally, wait for the driver to reclaim all descriptors. */
4835 while (eq->cidx != eq->pidx)
4836 pause("dquiesce", 1);
4840 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4847 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4849 (void) sc; /* unused */
4851 /* Synchronize with the interrupt handler */
4852 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4857 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4859 mtx_lock(&sc->sfl_lock);
4861 fl->flags |= FL_DOOMED;
4863 callout_stop(&sc->sfl_callout);
4864 mtx_unlock(&sc->sfl_lock);
4866 KASSERT((fl->flags & FL_STARVING) == 0,
4867 ("%s: still starving", __func__));
4871 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4872 driver_intr_t *handler, void *arg, char *name)
4877 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4878 RF_SHAREABLE | RF_ACTIVE);
4879 if (irq->res == NULL) {
4880 device_printf(sc->dev,
4881 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4885 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4886 NULL, handler, arg, &irq->tag);
4888 device_printf(sc->dev,
4889 "failed to setup interrupt for rid %d, name %s: %d\n",
4892 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
4898 t4_free_irq(struct adapter *sc, struct irq *irq)
4901 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4903 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4905 bzero(irq, sizeof(*irq));
4911 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4914 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4915 t4_get_regs(sc, buf, regs->len);
4918 #define A_PL_INDIR_CMD 0x1f8
4920 #define S_PL_AUTOINC 31
4921 #define M_PL_AUTOINC 0x1U
4922 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4923 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4925 #define S_PL_VFID 20
4926 #define M_PL_VFID 0xffU
4927 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4928 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4931 #define M_PL_ADDR 0xfffffU
4932 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4933 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4935 #define A_PL_INDIR_DATA 0x1fc
4938 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4942 mtx_assert(&sc->reg_lock, MA_OWNED);
4943 if (sc->flags & IS_VF) {
4944 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4945 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4947 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4948 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4949 V_PL_ADDR(VF_MPS_REG(reg)));
4950 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4951 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4953 return (((uint64_t)stats[1]) << 32 | stats[0]);
4957 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4958 struct fw_vi_stats_vf *stats)
4961 #define GET_STAT(name) \
4962 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4964 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4965 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4966 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4967 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4968 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4969 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4970 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4971 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4972 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4973 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4974 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4975 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4976 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4977 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4978 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4979 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4985 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4989 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4990 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4991 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4992 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4993 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4994 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4998 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5001 const struct timeval interval = {0, 250000}; /* 250ms */
5003 if (!(vi->flags & VI_INIT_DONE))
5007 timevalsub(&tv, &interval);
5008 if (timevalcmp(&tv, &vi->last_refreshed, <))
5011 mtx_lock(&sc->reg_lock);
5012 t4_get_vi_stats(sc, vi->viid, &vi->stats);
5013 getmicrotime(&vi->last_refreshed);
5014 mtx_unlock(&sc->reg_lock);
5018 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5020 u_int i, v, tnl_cong_drops, bg_map;
5022 const struct timeval interval = {0, 250000}; /* 250ms */
5025 timevalsub(&tv, &interval);
5026 if (timevalcmp(&tv, &pi->last_refreshed, <))
5030 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5031 bg_map = pi->mps_bg_map;
5033 i = ffs(bg_map) - 1;
5034 mtx_lock(&sc->reg_lock);
5035 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5036 A_TP_MIB_TNL_CNG_DROP_0 + i);
5037 mtx_unlock(&sc->reg_lock);
5038 tnl_cong_drops += v;
5039 bg_map &= ~(1 << i);
5041 pi->tnl_cong_drops = tnl_cong_drops;
5042 getmicrotime(&pi->last_refreshed);
5046 cxgbe_tick(void *arg)
5048 struct port_info *pi = arg;
5049 struct adapter *sc = pi->adapter;
5051 PORT_LOCK_ASSERT_OWNED(pi);
5052 cxgbe_refresh_stats(sc, pi);
5054 callout_schedule(&pi->tick, hz);
5060 struct vi_info *vi = arg;
5061 struct adapter *sc = vi->pi->adapter;
5063 vi_refresh_stats(sc, vi);
5065 callout_schedule(&vi->tick, hz);
5069 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
5073 if (arg != ifp || ifp->if_type != IFT_ETHER)
5076 vlan = VLAN_DEVAT(ifp, vid);
5077 VLAN_SETCOOKIE(vlan, ifp);
5081 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5083 static char *caps_decoder[] = {
5084 "\20\001IPMI\002NCSI", /* 0: NBM */
5085 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5086 "\20\001INGRESS\002EGRESS", /* 2: switch */
5087 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5088 "\006HASHFILTER\007ETHOFLD",
5089 "\20\001TOE", /* 4: TOE */
5090 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5091 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5092 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5093 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5095 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5096 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5097 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5098 "\004PO_INITIATOR\005PO_TARGET",
5102 t4_sysctls(struct adapter *sc)
5104 struct sysctl_ctx_list *ctx;
5105 struct sysctl_oid *oid;
5106 struct sysctl_oid_list *children, *c0;
5107 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5109 ctx = device_get_sysctl_ctx(sc->dev);
5114 oid = device_get_sysctl_tree(sc->dev);
5115 c0 = children = SYSCTL_CHILDREN(oid);
5117 sc->sc_do_rxcopy = 1;
5118 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5119 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5121 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5122 sc->params.nports, "# of ports");
5124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5125 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
5126 sysctl_bitfield, "A", "available doorbells");
5128 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5129 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5132 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5133 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5134 "interrupt holdoff timer values (us)");
5136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5137 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5138 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5139 "interrupt holdoff packet counter values");
5141 t4_sge_sysctls(sc, ctx, children);
5143 sc->lro_timeout = 100;
5144 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5145 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5147 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5148 &sc->debug_flags, 0, "flags to enable runtime debugging");
5150 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5151 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5153 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5154 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5156 if (sc->flags & IS_VF)
5159 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5160 NULL, chip_rev(sc), "chip hardware revision");
5162 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5163 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5165 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5166 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5168 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5169 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5171 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5172 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5174 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5175 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5177 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5178 sc->er_version, 0, "expansion ROM version");
5180 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5181 sc->bs_version, 0, "bootstrap firmware version");
5183 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5184 NULL, sc->params.scfg_vers, "serial config version");
5186 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5187 NULL, sc->params.vpd_vers, "VPD version");
5189 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5190 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5193 sc->cfcsum, "config file checksum");
5195 #define SYSCTL_CAP(name, n, text) \
5196 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5197 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
5198 sysctl_bitfield, "A", "available " text " capabilities")
5200 SYSCTL_CAP(nbmcaps, 0, "NBM");
5201 SYSCTL_CAP(linkcaps, 1, "link");
5202 SYSCTL_CAP(switchcaps, 2, "switch");
5203 SYSCTL_CAP(niccaps, 3, "NIC");
5204 SYSCTL_CAP(toecaps, 4, "TCP offload");
5205 SYSCTL_CAP(rdmacaps, 5, "RDMA");
5206 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5207 SYSCTL_CAP(cryptocaps, 7, "crypto");
5208 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5211 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5212 NULL, sc->tids.nftids, "number of filters");
5214 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5215 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5216 "chip temperature (in Celsius)");
5218 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5219 &sc->params.core_vdd, 0, "core Vdd (in mV)");
5223 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5225 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5226 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5227 "logs and miscellaneous information");
5228 children = SYSCTL_CHILDREN(oid);
5230 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5231 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5232 sysctl_cctrl, "A", "congestion control");
5234 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5235 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5236 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5238 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5239 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5240 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5242 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5243 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5244 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5246 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5247 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5248 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5250 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5251 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5252 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5254 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5255 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5256 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5258 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5259 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5260 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5261 "A", "CIM logic analyzer");
5263 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5264 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5265 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5267 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5268 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5269 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5272 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5273 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5275 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5276 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5277 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5280 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5281 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5284 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5285 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5288 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5289 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5291 if (chip_id(sc) > CHELSIO_T4) {
5292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5293 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5294 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5297 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5298 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5302 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5303 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5306 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5307 sysctl_cim_qcfg, "A", "CIM queue configuration");
5309 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5310 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5311 sysctl_cpl_stats, "A", "CPL statistics");
5313 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5314 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5315 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5317 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5318 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5319 sysctl_devlog, "A", "firmware's device log");
5321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5322 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5323 sysctl_fcoe_stats, "A", "FCoE statistics");
5325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5326 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5327 sysctl_hw_sched, "A", "hardware scheduler ");
5329 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5330 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5331 sysctl_l2t, "A", "hardware L2 table");
5333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5334 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5335 sysctl_lb_stats, "A", "loopback statistics");
5337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5338 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5339 sysctl_meminfo, "A", "memory regions");
5341 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5342 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5343 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5344 "A", "MPS TCAM entries");
5346 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5347 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5348 sysctl_path_mtus, "A", "path MTUs");
5350 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5351 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5352 sysctl_pm_stats, "A", "PM statistics");
5354 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5355 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5356 sysctl_rdma_stats, "A", "RDMA statistics");
5358 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5359 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5360 sysctl_tcp_stats, "A", "TCP statistics");
5362 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5363 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5364 sysctl_tids, "A", "TID information");
5366 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5367 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5368 sysctl_tp_err_stats, "A", "TP error statistics");
5370 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5371 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5372 "TP logic analyzer event capture mask");
5374 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5375 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5376 sysctl_tp_la, "A", "TP logic analyzer");
5378 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5379 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5380 sysctl_tx_rate, "A", "Tx rate");
5382 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5383 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5384 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5386 if (chip_id(sc) >= CHELSIO_T5) {
5387 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5388 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5389 sysctl_wcwr_stats, "A", "write combined work requests");
5394 if (is_offload(sc)) {
5401 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5402 NULL, "TOE parameters");
5403 children = SYSCTL_CHILDREN(oid);
5405 sc->tt.cong_algorithm = -1;
5406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
5407 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
5408 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
5411 sc->tt.sndbuf = 256 * 1024;
5412 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5413 &sc->tt.sndbuf, 0, "max hardware send buffer size");
5416 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5417 &sc->tt.ddp, 0, "DDP allowed");
5419 sc->tt.rx_coalesce = 1;
5420 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5421 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5423 sc->tt.tx_align = 1;
5424 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
5425 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
5427 sc->tt.tx_zcopy = 0;
5428 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
5429 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
5430 "Enable zero-copy aio_write(2)");
5432 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
5433 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
5434 "TP timer tick (us)");
5436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
5437 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
5438 "TCP timestamp tick (us)");
5440 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5441 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5444 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5445 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5446 "IU", "DACK timer (us)");
5448 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5449 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5450 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
5452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5453 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5454 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
5456 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5457 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5458 sysctl_tp_timer, "LU", "Persist timer min (us)");
5460 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5461 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5462 sysctl_tp_timer, "LU", "Persist timer max (us)");
5464 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5465 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5466 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
5468 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
5469 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5470 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
5472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5473 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5474 sysctl_tp_timer, "LU", "Initial SRTT (us)");
5476 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5477 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5478 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
5481 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
5482 sysctl_tp_shift_cnt, "IU",
5483 "Number of SYN retransmissions before abort");
5485 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
5486 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
5487 sysctl_tp_shift_cnt, "IU",
5488 "Number of retransmissions before abort");
5490 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
5491 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
5492 sysctl_tp_shift_cnt, "IU",
5493 "Number of keepalive probes before abort");
5495 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
5496 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
5497 children = SYSCTL_CHILDREN(oid);
5498 for (i = 0; i < 16; i++) {
5499 snprintf(s, sizeof(s), "%u", i);
5500 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
5501 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
5502 "IU", "TOE retransmit backoff");
5509 vi_sysctls(struct vi_info *vi)
5511 struct sysctl_ctx_list *ctx;
5512 struct sysctl_oid *oid;
5513 struct sysctl_oid_list *children;
5515 ctx = device_get_sysctl_ctx(vi->dev);
5518 * dev.v?(cxgbe|cxl).X.
5520 oid = device_get_sysctl_tree(vi->dev);
5521 children = SYSCTL_CHILDREN(oid);
5523 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5524 vi->viid, "VI identifer");
5525 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5526 &vi->nrxq, 0, "# of rx queues");
5527 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5528 &vi->ntxq, 0, "# of tx queues");
5529 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5530 &vi->first_rxq, 0, "index of first rx queue");
5531 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5532 &vi->first_txq, 0, "index of first tx queue");
5533 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5534 vi->rss_size, "size of RSS indirection table");
5536 if (IS_MAIN_VI(vi)) {
5537 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5538 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5539 "Reserve queue 0 for non-flowid packets");
5543 if (vi->nofldrxq != 0) {
5544 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5546 "# of rx queues for offloaded TCP connections");
5547 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5549 "# of tx queues for offloaded TCP connections");
5550 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5551 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5552 "index of first TOE rx queue");
5553 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5554 CTLFLAG_RD, &vi->first_ofld_txq, 0,
5555 "index of first TOE tx queue");
5556 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
5557 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5558 sysctl_holdoff_tmr_idx_ofld, "I",
5559 "holdoff timer index for TOE queues");
5560 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
5561 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
5562 sysctl_holdoff_pktc_idx_ofld, "I",
5563 "holdoff packet counter index for TOE queues");
5567 if (vi->nnmrxq != 0) {
5568 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5569 &vi->nnmrxq, 0, "# of netmap rx queues");
5570 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5571 &vi->nnmtxq, 0, "# of netmap tx queues");
5572 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5573 CTLFLAG_RD, &vi->first_nm_rxq, 0,
5574 "index of first netmap rx queue");
5575 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5576 CTLFLAG_RD, &vi->first_nm_txq, 0,
5577 "index of first netmap tx queue");
5581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5582 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5583 "holdoff timer index");
5584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5585 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5586 "holdoff packet counter index");
5588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5589 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5592 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5597 cxgbe_sysctls(struct port_info *pi)
5599 struct sysctl_ctx_list *ctx;
5600 struct sysctl_oid *oid;
5601 struct sysctl_oid_list *children, *children2;
5602 struct adapter *sc = pi->adapter;
5606 ctx = device_get_sysctl_ctx(pi->dev);
5611 oid = device_get_sysctl_tree(pi->dev);
5612 children = SYSCTL_CHILDREN(oid);
5614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5615 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5616 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5617 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5618 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5619 "PHY temperature (in Celsius)");
5620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5621 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5622 "PHY firmware version");
5625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5626 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
5627 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
5629 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
5630 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
5631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
5632 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
5633 "autonegotiation (-1 = not supported)");
5635 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5636 port_top_speed(pi), "max speed (in Gbps)");
5637 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
5638 pi->mps_bg_map, "MPS buffer group map");
5639 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
5640 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
5642 if (sc->flags & IS_VF)
5646 * dev.(cxgbe|cxl).X.tc.
5648 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5649 "Tx scheduler traffic classes (cl_rl)");
5650 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5651 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
5653 snprintf(name, sizeof(name), "%d", i);
5654 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5655 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5657 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5658 &tc->flags, 0, "flags");
5659 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5660 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5662 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5663 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5664 sysctl_tc_params, "A", "traffic class parameters");
5669 * dev.cxgbe.X.stats.
5671 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5672 NULL, "port statistics");
5673 children = SYSCTL_CHILDREN(oid);
5674 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5675 &pi->tx_parse_error, 0,
5676 "# of tx packets with invalid length or # of segments");
5678 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5679 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5680 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5681 sysctl_handle_t4_reg64, "QU", desc)
5683 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5684 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5685 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5686 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5687 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5688 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5689 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5690 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5691 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5692 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5693 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5694 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5695 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5696 "# of tx frames in this range",
5697 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5698 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5699 "# of tx frames in this range",
5700 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5701 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5702 "# of tx frames in this range",
5703 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5704 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5705 "# of tx frames in this range",
5706 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5707 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5708 "# of tx frames in this range",
5709 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5710 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5711 "# of tx frames in this range",
5712 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5713 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5714 "# of tx frames in this range",
5715 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5716 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5717 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5718 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5719 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5720 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5721 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5722 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5723 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5724 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5725 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5726 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5727 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5728 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5729 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5730 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5731 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5732 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5733 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5734 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5735 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5737 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5738 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5739 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5740 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5741 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5742 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5743 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5744 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5745 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5746 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5747 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5748 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5749 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5750 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5751 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5752 "# of frames received with bad FCS",
5753 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5754 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5755 "# of frames received with length error",
5756 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5757 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5758 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5759 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5760 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5761 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5762 "# of rx frames in this range",
5763 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5764 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5765 "# of rx frames in this range",
5766 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5767 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5768 "# of rx frames in this range",
5769 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5770 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5771 "# of rx frames in this range",
5772 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5773 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5774 "# of rx frames in this range",
5775 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5776 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5777 "# of rx frames in this range",
5778 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5779 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5780 "# of rx frames in this range",
5781 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5782 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5783 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5784 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5785 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5786 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5787 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5788 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5789 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5790 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5791 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5792 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5793 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5794 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5795 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5796 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5797 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5798 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5799 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5801 #undef SYSCTL_ADD_T4_REG64
5803 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5804 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5805 &pi->stats.name, desc)
5807 /* We get these from port_stats and they may be stale by up to 1s */
5808 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5809 "# drops due to buffer-group 0 overflows");
5810 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5811 "# drops due to buffer-group 1 overflows");
5812 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5813 "# drops due to buffer-group 2 overflows");
5814 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5815 "# drops due to buffer-group 3 overflows");
5816 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5817 "# of buffer-group 0 truncated packets");
5818 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5819 "# of buffer-group 1 truncated packets");
5820 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5821 "# of buffer-group 2 truncated packets");
5822 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5823 "# of buffer-group 3 truncated packets");
5825 #undef SYSCTL_ADD_T4_PORTSTAT
5829 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5831 int rc, *i, space = 0;
5834 sbuf_new_for_sysctl(&sb, NULL, 64, req);
5835 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5837 sbuf_printf(&sb, " ");
5838 sbuf_printf(&sb, "%d", *i);
5841 rc = sbuf_finish(&sb);
5847 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5852 rc = sysctl_wire_old_buffer(req, 0);
5856 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5860 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5861 rc = sbuf_finish(sb);
5868 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5870 struct port_info *pi = arg1;
5872 struct adapter *sc = pi->adapter;
5876 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5879 /* XXX: magic numbers */
5880 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5882 end_synchronized_op(sc, 0);
5888 rc = sysctl_handle_int(oidp, &v, 0, req);
5893 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5895 struct vi_info *vi = arg1;
5898 val = vi->rsrv_noflowq;
5899 rc = sysctl_handle_int(oidp, &val, 0, req);
5900 if (rc != 0 || req->newptr == NULL)
5903 if ((val >= 1) && (vi->ntxq > 1))
5904 vi->rsrv_noflowq = 1;
5906 vi->rsrv_noflowq = 0;
5912 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5914 struct vi_info *vi = arg1;
5915 struct adapter *sc = vi->pi->adapter;
5917 struct sge_rxq *rxq;
5922 rc = sysctl_handle_int(oidp, &idx, 0, req);
5923 if (rc != 0 || req->newptr == NULL)
5926 if (idx < 0 || idx >= SGE_NTIMERS)
5929 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5934 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5935 for_each_rxq(vi, i, rxq) {
5936 #ifdef atomic_store_rel_8
5937 atomic_store_rel_8(&rxq->iq.intr_params, v);
5939 rxq->iq.intr_params = v;
5944 end_synchronized_op(sc, LOCK_HELD);
5949 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5951 struct vi_info *vi = arg1;
5952 struct adapter *sc = vi->pi->adapter;
5957 rc = sysctl_handle_int(oidp, &idx, 0, req);
5958 if (rc != 0 || req->newptr == NULL)
5961 if (idx < -1 || idx >= SGE_NCOUNTERS)
5964 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5969 if (vi->flags & VI_INIT_DONE)
5970 rc = EBUSY; /* cannot be changed once the queues are created */
5974 end_synchronized_op(sc, LOCK_HELD);
5979 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5981 struct vi_info *vi = arg1;
5982 struct adapter *sc = vi->pi->adapter;
5985 qsize = vi->qsize_rxq;
5987 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5988 if (rc != 0 || req->newptr == NULL)
5991 if (qsize < 128 || (qsize & 7))
5994 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5999 if (vi->flags & VI_INIT_DONE)
6000 rc = EBUSY; /* cannot be changed once the queues are created */
6002 vi->qsize_rxq = qsize;
6004 end_synchronized_op(sc, LOCK_HELD);
6009 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6011 struct vi_info *vi = arg1;
6012 struct adapter *sc = vi->pi->adapter;
6015 qsize = vi->qsize_txq;
6017 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6018 if (rc != 0 || req->newptr == NULL)
6021 if (qsize < 128 || qsize > 65536)
6024 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6029 if (vi->flags & VI_INIT_DONE)
6030 rc = EBUSY; /* cannot be changed once the queues are created */
6032 vi->qsize_txq = qsize;
6034 end_synchronized_op(sc, LOCK_HELD);
6039 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6041 struct port_info *pi = arg1;
6042 struct adapter *sc = pi->adapter;
6043 struct link_config *lc = &pi->link_cfg;
6046 if (req->newptr == NULL) {
6048 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
6050 rc = sysctl_wire_old_buffer(req, 0);
6054 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6058 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
6059 rc = sbuf_finish(sb);
6065 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
6068 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6074 if (s[0] < '0' || s[0] > '9')
6075 return (EINVAL); /* not a number */
6077 if (n & ~(PAUSE_TX | PAUSE_RX))
6078 return (EINVAL); /* some other bit is set too */
6080 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6084 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
6085 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
6086 lc->requested_fc |= n;
6087 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6089 lc->fc = lc->requested_fc;
6092 end_synchronized_op(sc, 0);
6099 sysctl_fec(SYSCTL_HANDLER_ARGS)
6101 struct port_info *pi = arg1;
6102 struct adapter *sc = pi->adapter;
6103 struct link_config *lc = &pi->link_cfg;
6106 if (req->newptr == NULL) {
6108 static char *bits = "\20\1RS\2BASER_RS\3RESERVED";
6110 rc = sysctl_wire_old_buffer(req, 0);
6114 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6118 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits);
6119 rc = sbuf_finish(sb);
6125 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC);
6128 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6134 if (s[0] < '0' || s[0] > '9')
6135 return (EINVAL); /* not a number */
6137 if (n & ~M_FW_PORT_CAP_FEC)
6138 return (EINVAL); /* some other bit is set too */
6140 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6144 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) {
6145 lc->requested_fec = n &
6146 G_FW_PORT_CAP_FEC(lc->supported);
6147 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6149 lc->fec = lc->requested_fec;
6152 end_synchronized_op(sc, 0);
6159 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
6161 struct port_info *pi = arg1;
6162 struct adapter *sc = pi->adapter;
6163 struct link_config *lc = &pi->link_cfg;
6166 if (lc->supported & FW_PORT_CAP_ANEG)
6167 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0;
6170 rc = sysctl_handle_int(oidp, &val, 0, req);
6171 if (rc != 0 || req->newptr == NULL)
6173 if ((lc->supported & FW_PORT_CAP_ANEG) == 0)
6177 val = AUTONEG_DISABLE;
6179 val = AUTONEG_ENABLE;
6182 if (lc->requested_aneg == val)
6183 return (0); /* no change */
6185 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6189 old = lc->requested_aneg;
6190 lc->requested_aneg = val;
6191 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
6193 lc->requested_aneg = old;
6194 end_synchronized_op(sc, 0);
6199 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
6201 struct adapter *sc = arg1;
6205 val = t4_read_reg64(sc, reg);
6207 return (sysctl_handle_64(oidp, &val, 0, req));
6211 sysctl_temperature(SYSCTL_HANDLER_ARGS)
6213 struct adapter *sc = arg1;
6215 uint32_t param, val;
6217 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
6220 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6221 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
6222 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
6223 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6224 end_synchronized_op(sc, 0);
6228 /* unknown is returned as 0 but we display -1 in that case */
6229 t = val == 0 ? -1 : val;
6231 rc = sysctl_handle_int(oidp, &t, 0, req);
6237 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6239 struct adapter *sc = arg1;
6242 uint16_t incr[NMTUS][NCCTRL_WIN];
6243 static const char *dec_fac[] = {
6244 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6248 rc = sysctl_wire_old_buffer(req, 0);
6252 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6256 t4_read_cong_tbl(sc, incr);
6258 for (i = 0; i < NCCTRL_WIN; ++i) {
6259 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6260 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6261 incr[5][i], incr[6][i], incr[7][i]);
6262 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6263 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6264 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6265 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6268 rc = sbuf_finish(sb);
6274 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6275 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
6276 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6277 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
6281 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6283 struct adapter *sc = arg1;
6285 int rc, i, n, qid = arg2;
6288 u_int cim_num_obq = sc->chip_params->cim_num_obq;
6290 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6291 ("%s: bad qid %d\n", __func__, qid));
6293 if (qid < CIM_NUM_IBQ) {
6296 n = 4 * CIM_IBQ_SIZE;
6297 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6298 rc = t4_read_cim_ibq(sc, qid, buf, n);
6300 /* outbound queue */
6303 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
6304 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6305 rc = t4_read_cim_obq(sc, qid, buf, n);
6312 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
6314 rc = sysctl_wire_old_buffer(req, 0);
6318 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6324 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
6325 for (i = 0, p = buf; i < n; i += 16, p += 4)
6326 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
6329 rc = sbuf_finish(sb);
6337 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
6339 struct adapter *sc = arg1;
6345 MPASS(chip_id(sc) <= CHELSIO_T5);
6347 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6351 rc = sysctl_wire_old_buffer(req, 0);
6355 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6359 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6362 rc = -t4_cim_read_la(sc, buf, NULL);
6366 sbuf_printf(sb, "Status Data PC%s",
6367 cfg & F_UPDBGLACAPTPCONLY ? "" :
6368 " LS0Stat LS0Addr LS0Data");
6370 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
6371 if (cfg & F_UPDBGLACAPTPCONLY) {
6372 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
6374 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
6375 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
6376 p[4] & 0xff, p[5] >> 8);
6377 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
6378 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6379 p[1] & 0xf, p[2] >> 4);
6382 "\n %02x %x%07x %x%07x %08x %08x "
6384 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6385 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
6390 rc = sbuf_finish(sb);
6398 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
6400 struct adapter *sc = arg1;
6406 MPASS(chip_id(sc) > CHELSIO_T5);
6408 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6412 rc = sysctl_wire_old_buffer(req, 0);
6416 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6420 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6423 rc = -t4_cim_read_la(sc, buf, NULL);
6427 sbuf_printf(sb, "Status Inst Data PC%s",
6428 cfg & F_UPDBGLACAPTPCONLY ? "" :
6429 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
6431 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
6432 if (cfg & F_UPDBGLACAPTPCONLY) {
6433 sbuf_printf(sb, "\n %02x %08x %08x %08x",
6434 p[3] & 0xff, p[2], p[1], p[0]);
6435 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
6436 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
6437 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
6438 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
6439 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
6440 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
6443 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
6444 "%08x %08x %08x %08x %08x %08x",
6445 (p[9] >> 16) & 0xff,
6446 p[9] & 0xffff, p[8] >> 16,
6447 p[8] & 0xffff, p[7] >> 16,
6448 p[7] & 0xffff, p[6] >> 16,
6449 p[2], p[1], p[0], p[5], p[4], p[3]);
6453 rc = sbuf_finish(sb);
6461 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
6463 struct adapter *sc = arg1;
6469 rc = sysctl_wire_old_buffer(req, 0);
6473 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6477 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6480 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6483 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6484 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6488 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
6489 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6490 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
6491 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6492 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6493 (p[1] >> 2) | ((p[2] & 3) << 30),
6494 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
6498 rc = sbuf_finish(sb);
6505 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
6507 struct adapter *sc = arg1;
6513 rc = sysctl_wire_old_buffer(req, 0);
6517 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6521 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
6524 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
6527 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
6528 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6529 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
6530 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
6531 p[4], p[3], p[2], p[1], p[0]);
6534 sbuf_printf(sb, "\n\nCntl ID Data");
6535 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6536 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
6537 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
6540 rc = sbuf_finish(sb);
6547 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
6549 struct adapter *sc = arg1;
6552 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6553 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6554 uint16_t thres[CIM_NUM_IBQ];
6555 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
6556 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
6557 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
6559 cim_num_obq = sc->chip_params->cim_num_obq;
6561 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
6562 obq_rdaddr = A_UP_OBQ_0_REALADDR;
6564 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
6565 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
6567 nq = CIM_NUM_IBQ + cim_num_obq;
6569 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
6571 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
6575 t4_read_cimq_cfg(sc, base, size, thres);
6577 rc = sysctl_wire_old_buffer(req, 0);
6581 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6586 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
6588 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
6589 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
6590 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
6591 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6592 G_QUEREMFLITS(p[2]) * 16);
6593 for ( ; i < nq; i++, p += 4, wr += 2)
6594 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
6595 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
6596 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6597 G_QUEREMFLITS(p[2]) * 16);
6599 rc = sbuf_finish(sb);
6606 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
6608 struct adapter *sc = arg1;
6611 struct tp_cpl_stats stats;
6613 rc = sysctl_wire_old_buffer(req, 0);
6617 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6621 mtx_lock(&sc->reg_lock);
6622 t4_tp_get_cpl_stats(sc, &stats, 0);
6623 mtx_unlock(&sc->reg_lock);
6625 if (sc->chip_params->nchan > 2) {
6626 sbuf_printf(sb, " channel 0 channel 1"
6627 " channel 2 channel 3");
6628 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
6629 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
6630 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
6631 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
6633 sbuf_printf(sb, " channel 0 channel 1");
6634 sbuf_printf(sb, "\nCPL requests: %10u %10u",
6635 stats.req[0], stats.req[1]);
6636 sbuf_printf(sb, "\nCPL responses: %10u %10u",
6637 stats.rsp[0], stats.rsp[1]);
6640 rc = sbuf_finish(sb);
6647 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
6649 struct adapter *sc = arg1;
6652 struct tp_usm_stats stats;
6654 rc = sysctl_wire_old_buffer(req, 0);
6658 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6662 t4_get_usm_stats(sc, &stats, 1);
6664 sbuf_printf(sb, "Frames: %u\n", stats.frames);
6665 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
6666 sbuf_printf(sb, "Drops: %u", stats.drops);
6668 rc = sbuf_finish(sb);
6674 static const char * const devlog_level_strings[] = {
6675 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
6676 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
6677 [FW_DEVLOG_LEVEL_ERR] = "ERR",
6678 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
6679 [FW_DEVLOG_LEVEL_INFO] = "INFO",
6680 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
6683 static const char * const devlog_facility_strings[] = {
6684 [FW_DEVLOG_FACILITY_CORE] = "CORE",
6685 [FW_DEVLOG_FACILITY_CF] = "CF",
6686 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
6687 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
6688 [FW_DEVLOG_FACILITY_RES] = "RES",
6689 [FW_DEVLOG_FACILITY_HW] = "HW",
6690 [FW_DEVLOG_FACILITY_FLR] = "FLR",
6691 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
6692 [FW_DEVLOG_FACILITY_PHY] = "PHY",
6693 [FW_DEVLOG_FACILITY_MAC] = "MAC",
6694 [FW_DEVLOG_FACILITY_PORT] = "PORT",
6695 [FW_DEVLOG_FACILITY_VI] = "VI",
6696 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
6697 [FW_DEVLOG_FACILITY_ACL] = "ACL",
6698 [FW_DEVLOG_FACILITY_TM] = "TM",
6699 [FW_DEVLOG_FACILITY_QFC] = "QFC",
6700 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6701 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6702 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6703 [FW_DEVLOG_FACILITY_RI] = "RI",
6704 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6705 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6706 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6707 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6708 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6712 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6714 struct adapter *sc = arg1;
6715 struct devlog_params *dparams = &sc->params.devlog;
6716 struct fw_devlog_e *buf, *e;
6717 int i, j, rc, nentries, first = 0;
6719 uint64_t ftstamp = UINT64_MAX;
6721 if (dparams->addr == 0)
6724 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6728 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6732 nentries = dparams->size / sizeof(struct fw_devlog_e);
6733 for (i = 0; i < nentries; i++) {
6736 if (e->timestamp == 0)
6739 e->timestamp = be64toh(e->timestamp);
6740 e->seqno = be32toh(e->seqno);
6741 for (j = 0; j < 8; j++)
6742 e->params[j] = be32toh(e->params[j]);
6744 if (e->timestamp < ftstamp) {
6745 ftstamp = e->timestamp;
6750 if (buf[first].timestamp == 0)
6751 goto done; /* nothing in the log */
6753 rc = sysctl_wire_old_buffer(req, 0);
6757 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6762 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6763 "Seq#", "Tstamp", "Level", "Facility", "Message");
6768 if (e->timestamp == 0)
6771 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6772 e->seqno, e->timestamp,
6773 (e->level < nitems(devlog_level_strings) ?
6774 devlog_level_strings[e->level] : "UNKNOWN"),
6775 (e->facility < nitems(devlog_facility_strings) ?
6776 devlog_facility_strings[e->facility] : "UNKNOWN"));
6777 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6778 e->params[2], e->params[3], e->params[4],
6779 e->params[5], e->params[6], e->params[7]);
6781 if (++i == nentries)
6783 } while (i != first);
6785 rc = sbuf_finish(sb);
6793 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6795 struct adapter *sc = arg1;
6798 struct tp_fcoe_stats stats[MAX_NCHAN];
6799 int i, nchan = sc->chip_params->nchan;
6801 rc = sysctl_wire_old_buffer(req, 0);
6805 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6809 for (i = 0; i < nchan; i++)
6810 t4_get_fcoe_stats(sc, i, &stats[i], 1);
6813 sbuf_printf(sb, " channel 0 channel 1"
6814 " channel 2 channel 3");
6815 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6816 stats[0].octets_ddp, stats[1].octets_ddp,
6817 stats[2].octets_ddp, stats[3].octets_ddp);
6818 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6819 stats[0].frames_ddp, stats[1].frames_ddp,
6820 stats[2].frames_ddp, stats[3].frames_ddp);
6821 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6822 stats[0].frames_drop, stats[1].frames_drop,
6823 stats[2].frames_drop, stats[3].frames_drop);
6825 sbuf_printf(sb, " channel 0 channel 1");
6826 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6827 stats[0].octets_ddp, stats[1].octets_ddp);
6828 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6829 stats[0].frames_ddp, stats[1].frames_ddp);
6830 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6831 stats[0].frames_drop, stats[1].frames_drop);
6834 rc = sbuf_finish(sb);
6841 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6843 struct adapter *sc = arg1;
6846 unsigned int map, kbps, ipg, mode;
6847 unsigned int pace_tab[NTX_SCHED];
6849 rc = sysctl_wire_old_buffer(req, 0);
6853 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6857 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6858 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6859 t4_read_pace_tbl(sc, pace_tab);
6861 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6862 "Class IPG (0.1 ns) Flow IPG (us)");
6864 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6865 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
6866 sbuf_printf(sb, "\n %u %-5s %u ", i,
6867 (mode & (1 << i)) ? "flow" : "class", map & 3);
6869 sbuf_printf(sb, "%9u ", kbps);
6871 sbuf_printf(sb, " disabled ");
6874 sbuf_printf(sb, "%13u ", ipg);
6876 sbuf_printf(sb, " disabled ");
6879 sbuf_printf(sb, "%10u", pace_tab[i]);
6881 sbuf_printf(sb, " disabled");
6884 rc = sbuf_finish(sb);
6891 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6893 struct adapter *sc = arg1;
6897 struct lb_port_stats s[2];
6898 static const char *stat_name[] = {
6899 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6900 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6901 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6902 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6903 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6904 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6905 "BG2FramesTrunc:", "BG3FramesTrunc:"
6908 rc = sysctl_wire_old_buffer(req, 0);
6912 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6916 memset(s, 0, sizeof(s));
6918 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6919 t4_get_lb_stats(sc, i, &s[0]);
6920 t4_get_lb_stats(sc, i + 1, &s[1]);
6924 sbuf_printf(sb, "%s Loopback %u"
6925 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6927 for (j = 0; j < nitems(stat_name); j++)
6928 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6932 rc = sbuf_finish(sb);
6939 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6942 struct port_info *pi = arg1;
6943 struct link_config *lc = &pi->link_cfg;
6946 rc = sysctl_wire_old_buffer(req, 0);
6949 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6953 if (lc->link_ok || lc->link_down_rc == 255)
6954 sbuf_printf(sb, "n/a");
6956 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
6958 rc = sbuf_finish(sb);
6971 mem_desc_cmp(const void *a, const void *b)
6973 return ((const struct mem_desc *)a)->base -
6974 ((const struct mem_desc *)b)->base;
6978 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6986 size = to - from + 1;
6990 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6991 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6995 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6997 struct adapter *sc = arg1;
7000 uint32_t lo, hi, used, alloc;
7001 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7002 static const char *region[] = {
7003 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7004 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7005 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7006 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7007 "RQUDP region:", "PBL region:", "TXPBL region:",
7008 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7011 struct mem_desc avail[4];
7012 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
7013 struct mem_desc *md = mem;
7015 rc = sysctl_wire_old_buffer(req, 0);
7019 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7023 for (i = 0; i < nitems(mem); i++) {
7028 /* Find and sort the populated memory ranges */
7030 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7031 if (lo & F_EDRAM0_ENABLE) {
7032 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7033 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7034 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7038 if (lo & F_EDRAM1_ENABLE) {
7039 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7040 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7041 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7045 if (lo & F_EXT_MEM_ENABLE) {
7046 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7047 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7048 avail[i].limit = avail[i].base +
7049 (G_EXT_MEM_SIZE(hi) << 20);
7050 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
7053 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7054 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7055 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7056 avail[i].limit = avail[i].base +
7057 (G_EXT_MEM1_SIZE(hi) << 20);
7061 if (!i) /* no memory available */
7063 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
7065 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
7066 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
7067 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
7068 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7069 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
7070 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
7071 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
7072 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
7073 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
7075 /* the next few have explicit upper bounds */
7076 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
7077 md->limit = md->base - 1 +
7078 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
7079 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
7082 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
7083 md->limit = md->base - 1 +
7084 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
7085 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
7088 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7089 if (chip_id(sc) <= CHELSIO_T5)
7090 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
7092 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
7096 md->idx = nitems(region); /* hide it */
7100 #define ulp_region(reg) \
7101 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
7102 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
7104 ulp_region(RX_ISCSI);
7105 ulp_region(RX_TDDP);
7107 ulp_region(RX_STAG);
7109 ulp_region(RX_RQUDP);
7115 md->idx = nitems(region);
7118 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
7119 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
7122 if (sge_ctrl & F_VFIFO_ENABLE)
7123 size = G_DBVFIFO_SIZE(fifo_size);
7125 size = G_T6_DBVFIFO_SIZE(fifo_size);
7128 md->base = G_BASEADDR(t4_read_reg(sc,
7129 A_SGE_DBVFIFO_BADDR));
7130 md->limit = md->base + (size << 2) - 1;
7135 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
7138 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
7142 md->base = sc->vres.ocq.start;
7143 if (sc->vres.ocq.size)
7144 md->limit = md->base + sc->vres.ocq.size - 1;
7146 md->idx = nitems(region); /* hide it */
7149 /* add any address-space holes, there can be up to 3 */
7150 for (n = 0; n < i - 1; n++)
7151 if (avail[n].limit < avail[n + 1].base)
7152 (md++)->base = avail[n].limit;
7154 (md++)->base = avail[n].limit;
7157 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
7159 for (lo = 0; lo < i; lo++)
7160 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
7161 avail[lo].limit - 1);
7163 sbuf_printf(sb, "\n");
7164 for (i = 0; i < n; i++) {
7165 if (mem[i].idx >= nitems(region))
7166 continue; /* skip holes */
7168 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
7169 mem_region_show(sb, region[mem[i].idx], mem[i].base,
7173 sbuf_printf(sb, "\n");
7174 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
7175 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
7176 mem_region_show(sb, "uP RAM:", lo, hi);
7178 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
7179 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
7180 mem_region_show(sb, "uP Extmem2:", lo, hi);
7182 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
7183 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
7185 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
7186 (lo & F_PMRXNUMCHN) ? 2 : 1);
7188 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
7189 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
7190 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
7192 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
7193 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
7194 sbuf_printf(sb, "%u p-structs\n",
7195 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
7197 for (i = 0; i < 4; i++) {
7198 if (chip_id(sc) > CHELSIO_T5)
7199 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
7201 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
7203 used = G_T5_USED(lo);
7204 alloc = G_T5_ALLOC(lo);
7207 alloc = G_ALLOC(lo);
7209 /* For T6 these are MAC buffer groups */
7210 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
7213 for (i = 0; i < sc->chip_params->nchan; i++) {
7214 if (chip_id(sc) > CHELSIO_T5)
7215 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
7217 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
7219 used = G_T5_USED(lo);
7220 alloc = G_T5_ALLOC(lo);
7223 alloc = G_ALLOC(lo);
7225 /* For T6 these are MAC buffer groups */
7227 "\nLoopback %d using %u pages out of %u allocated",
7231 rc = sbuf_finish(sb);
7238 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7242 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7246 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7248 struct adapter *sc = arg1;
7252 MPASS(chip_id(sc) <= CHELSIO_T5);
7254 rc = sysctl_wire_old_buffer(req, 0);
7258 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7263 "Idx Ethernet address Mask Vld Ports PF"
7264 " VF Replication P0 P1 P2 P3 ML");
7265 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7266 uint64_t tcamx, tcamy, mask;
7267 uint32_t cls_lo, cls_hi;
7268 uint8_t addr[ETHER_ADDR_LEN];
7270 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7271 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7274 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7275 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7276 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7277 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7278 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
7279 addr[3], addr[4], addr[5], (uintmax_t)mask,
7280 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7281 G_PORTMAP(cls_hi), G_PF(cls_lo),
7282 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7284 if (cls_lo & F_REPLICATE) {
7285 struct fw_ldst_cmd ldst_cmd;
7287 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7288 ldst_cmd.op_to_addrspace =
7289 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7290 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7291 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7292 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7293 ldst_cmd.u.mps.rplc.fid_idx =
7294 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7295 V_FW_LDST_CMD_IDX(i));
7297 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7301 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7302 sizeof(ldst_cmd), &ldst_cmd);
7303 end_synchronized_op(sc, 0);
7306 sbuf_printf(sb, "%36d", rc);
7309 sbuf_printf(sb, " %08x %08x %08x %08x",
7310 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7311 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7312 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7313 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7316 sbuf_printf(sb, "%36s", "");
7318 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
7319 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
7320 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
7324 (void) sbuf_finish(sb);
7326 rc = sbuf_finish(sb);
7333 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
7335 struct adapter *sc = arg1;
7339 MPASS(chip_id(sc) > CHELSIO_T5);
7341 rc = sysctl_wire_old_buffer(req, 0);
7345 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7349 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
7350 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
7352 " P0 P1 P2 P3 ML\n");
7354 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7355 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
7357 uint64_t tcamx, tcamy, val, mask;
7358 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
7359 uint8_t addr[ETHER_ADDR_LEN];
7361 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
7363 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
7365 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
7366 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7367 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7368 tcamy = G_DMACH(val) << 32;
7369 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7370 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7371 lookup_type = G_DATALKPTYPE(data2);
7372 port_num = G_DATAPORTNUM(data2);
7373 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7374 /* Inner header VNI */
7375 vniy = ((data2 & F_DATAVIDH2) << 23) |
7376 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7377 dip_hit = data2 & F_DATADIPHIT;
7382 vlan_vld = data2 & F_DATAVIDH2;
7383 ivlan = G_VIDL(val);
7386 ctl |= V_CTLXYBITSEL(1);
7387 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7388 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7389 tcamx = G_DMACH(val) << 32;
7390 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7391 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7392 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7393 /* Inner header VNI mask */
7394 vnix = ((data2 & F_DATAVIDH2) << 23) |
7395 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7401 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7403 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7404 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7406 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7407 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7408 "%012jx %06x %06x - - %3c"
7409 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
7410 addr[1], addr[2], addr[3], addr[4], addr[5],
7411 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
7412 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7413 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7414 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7416 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7417 "%012jx - - ", i, addr[0], addr[1],
7418 addr[2], addr[3], addr[4], addr[5],
7422 sbuf_printf(sb, "%4u Y ", ivlan);
7424 sbuf_printf(sb, " - N ");
7426 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
7427 lookup_type ? 'I' : 'O', port_num,
7428 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7429 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7430 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7434 if (cls_lo & F_T6_REPLICATE) {
7435 struct fw_ldst_cmd ldst_cmd;
7437 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7438 ldst_cmd.op_to_addrspace =
7439 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7440 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7441 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7442 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7443 ldst_cmd.u.mps.rplc.fid_idx =
7444 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7445 V_FW_LDST_CMD_IDX(i));
7447 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7451 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7452 sizeof(ldst_cmd), &ldst_cmd);
7453 end_synchronized_op(sc, 0);
7456 sbuf_printf(sb, "%72d", rc);
7459 sbuf_printf(sb, " %08x %08x %08x %08x"
7460 " %08x %08x %08x %08x",
7461 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
7462 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
7463 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
7464 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
7465 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7466 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7467 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7468 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7471 sbuf_printf(sb, "%72s", "");
7473 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
7474 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
7475 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7476 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7480 (void) sbuf_finish(sb);
7482 rc = sbuf_finish(sb);
7489 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
7491 struct adapter *sc = arg1;
7494 uint16_t mtus[NMTUS];
7496 rc = sysctl_wire_old_buffer(req, 0);
7500 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7504 t4_read_mtu_tbl(sc, mtus, NULL);
7506 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
7507 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
7508 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
7509 mtus[14], mtus[15]);
7511 rc = sbuf_finish(sb);
7518 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
7520 struct adapter *sc = arg1;
7523 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
7524 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
7525 static const char *tx_stats[MAX_PM_NSTATS] = {
7526 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
7527 "Tx FIFO wait", NULL, "Tx latency"
7529 static const char *rx_stats[MAX_PM_NSTATS] = {
7530 "Read:", "Write bypass:", "Write mem:", "Flush:",
7531 "Rx FIFO wait", NULL, "Rx latency"
7534 rc = sysctl_wire_old_buffer(req, 0);
7538 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7542 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
7543 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
7545 sbuf_printf(sb, " Tx pcmds Tx bytes");
7546 for (i = 0; i < 4; i++) {
7547 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7551 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
7552 for (i = 0; i < 4; i++) {
7553 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7557 if (chip_id(sc) > CHELSIO_T5) {
7559 "\n Total wait Total occupancy");
7560 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7562 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7566 MPASS(i < nitems(tx_stats));
7569 "\n Reads Total wait");
7570 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7572 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7576 rc = sbuf_finish(sb);
7583 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
7585 struct adapter *sc = arg1;
7588 struct tp_rdma_stats stats;
7590 rc = sysctl_wire_old_buffer(req, 0);
7594 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7598 mtx_lock(&sc->reg_lock);
7599 t4_tp_get_rdma_stats(sc, &stats, 0);
7600 mtx_unlock(&sc->reg_lock);
7602 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
7603 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
7605 rc = sbuf_finish(sb);
7612 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
7614 struct adapter *sc = arg1;
7617 struct tp_tcp_stats v4, v6;
7619 rc = sysctl_wire_old_buffer(req, 0);
7623 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7627 mtx_lock(&sc->reg_lock);
7628 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
7629 mtx_unlock(&sc->reg_lock);
7633 sbuf_printf(sb, "OutRsts: %20u %20u\n",
7634 v4.tcp_out_rsts, v6.tcp_out_rsts);
7635 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
7636 v4.tcp_in_segs, v6.tcp_in_segs);
7637 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
7638 v4.tcp_out_segs, v6.tcp_out_segs);
7639 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
7640 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
7642 rc = sbuf_finish(sb);
7649 sysctl_tids(SYSCTL_HANDLER_ARGS)
7651 struct adapter *sc = arg1;
7654 struct tid_info *t = &sc->tids;
7656 rc = sysctl_wire_old_buffer(req, 0);
7660 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7665 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7670 sbuf_printf(sb, "TID range: ");
7671 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7674 if (chip_id(sc) <= CHELSIO_T5) {
7675 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7676 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
7678 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
7679 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
7683 sbuf_printf(sb, "0-%u, ", b - 1);
7684 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
7686 sbuf_printf(sb, "0-%u", t->ntids - 1);
7687 sbuf_printf(sb, ", in use: %u\n",
7688 atomic_load_acq_int(&t->tids_in_use));
7692 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
7693 t->stid_base + t->nstids - 1, t->stids_in_use);
7697 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
7698 t->ftid_base + t->nftids - 1);
7702 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
7703 t->etid_base + t->netids - 1);
7706 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7707 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7708 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7710 rc = sbuf_finish(sb);
7717 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7719 struct adapter *sc = arg1;
7722 struct tp_err_stats stats;
7724 rc = sysctl_wire_old_buffer(req, 0);
7728 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7732 mtx_lock(&sc->reg_lock);
7733 t4_tp_get_err_stats(sc, &stats, 0);
7734 mtx_unlock(&sc->reg_lock);
7736 if (sc->chip_params->nchan > 2) {
7737 sbuf_printf(sb, " channel 0 channel 1"
7738 " channel 2 channel 3\n");
7739 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7740 stats.mac_in_errs[0], stats.mac_in_errs[1],
7741 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7742 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7743 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7744 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7745 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7746 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7747 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7748 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7749 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7750 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7751 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7752 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7753 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7754 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7755 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7756 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7757 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7758 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7759 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7760 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7761 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7762 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7764 sbuf_printf(sb, " channel 0 channel 1\n");
7765 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7766 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7767 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7768 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7769 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7770 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7771 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7772 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7773 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7774 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7775 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7776 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7777 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7778 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7779 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7780 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7783 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7784 stats.ofld_no_neigh, stats.ofld_cong_defer);
7786 rc = sbuf_finish(sb);
7793 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7795 struct adapter *sc = arg1;
7796 struct tp_params *tpp = &sc->params.tp;
7800 mask = tpp->la_mask >> 16;
7801 rc = sysctl_handle_int(oidp, &mask, 0, req);
7802 if (rc != 0 || req->newptr == NULL)
7806 tpp->la_mask = mask << 16;
7807 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7819 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7825 uint64_t mask = (1ULL << f->width) - 1;
7826 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7827 ((uintmax_t)v >> f->start) & mask);
7829 if (line_size + len >= 79) {
7831 sbuf_printf(sb, "\n ");
7833 sbuf_printf(sb, "%s ", buf);
7834 line_size += len + 1;
7837 sbuf_printf(sb, "\n");
7840 static const struct field_desc tp_la0[] = {
7841 { "RcfOpCodeOut", 60, 4 },
7843 { "WcfState", 52, 4 },
7844 { "RcfOpcSrcOut", 50, 2 },
7845 { "CRxError", 49, 1 },
7846 { "ERxError", 48, 1 },
7847 { "SanityFailed", 47, 1 },
7848 { "SpuriousMsg", 46, 1 },
7849 { "FlushInputMsg", 45, 1 },
7850 { "FlushInputCpl", 44, 1 },
7851 { "RssUpBit", 43, 1 },
7852 { "RssFilterHit", 42, 1 },
7854 { "InitTcb", 31, 1 },
7855 { "LineNumber", 24, 7 },
7857 { "EdataOut", 22, 1 },
7859 { "CdataOut", 20, 1 },
7860 { "EreadPdu", 19, 1 },
7861 { "CreadPdu", 18, 1 },
7862 { "TunnelPkt", 17, 1 },
7863 { "RcfPeerFin", 16, 1 },
7864 { "RcfReasonOut", 12, 4 },
7865 { "TxCchannel", 10, 2 },
7866 { "RcfTxChannel", 8, 2 },
7867 { "RxEchannel", 6, 2 },
7868 { "RcfRxChannel", 5, 1 },
7869 { "RcfDataOutSrdy", 4, 1 },
7871 { "RxOoDvld", 2, 1 },
7872 { "RxCongestion", 1, 1 },
7873 { "TxCongestion", 0, 1 },
7877 static const struct field_desc tp_la1[] = {
7878 { "CplCmdIn", 56, 8 },
7879 { "CplCmdOut", 48, 8 },
7880 { "ESynOut", 47, 1 },
7881 { "EAckOut", 46, 1 },
7882 { "EFinOut", 45, 1 },
7883 { "ERstOut", 44, 1 },
7888 { "DataIn", 39, 1 },
7889 { "DataInVld", 38, 1 },
7891 { "RxBufEmpty", 36, 1 },
7893 { "RxFbCongestion", 34, 1 },
7894 { "TxFbCongestion", 33, 1 },
7895 { "TxPktSumSrdy", 32, 1 },
7896 { "RcfUlpType", 28, 4 },
7898 { "Ebypass", 26, 1 },
7900 { "Static0", 24, 1 },
7902 { "Cbypass", 22, 1 },
7904 { "CPktOut", 20, 1 },
7905 { "RxPagePoolFull", 18, 2 },
7906 { "RxLpbkPkt", 17, 1 },
7907 { "TxLpbkPkt", 16, 1 },
7908 { "RxVfValid", 15, 1 },
7909 { "SynLearned", 14, 1 },
7910 { "SetDelEntry", 13, 1 },
7911 { "SetInvEntry", 12, 1 },
7912 { "CpcmdDvld", 11, 1 },
7913 { "CpcmdSave", 10, 1 },
7914 { "RxPstructsFull", 8, 2 },
7915 { "EpcmdDvld", 7, 1 },
7916 { "EpcmdFlush", 6, 1 },
7917 { "EpcmdTrimPrefix", 5, 1 },
7918 { "EpcmdTrimPostfix", 4, 1 },
7919 { "ERssIp4Pkt", 3, 1 },
7920 { "ERssIp6Pkt", 2, 1 },
7921 { "ERssTcpUdpPkt", 1, 1 },
7922 { "ERssFceFipPkt", 0, 1 },
7926 static const struct field_desc tp_la2[] = {
7927 { "CplCmdIn", 56, 8 },
7928 { "MpsVfVld", 55, 1 },
7935 { "DataIn", 39, 1 },
7936 { "DataInVld", 38, 1 },
7938 { "RxBufEmpty", 36, 1 },
7940 { "RxFbCongestion", 34, 1 },
7941 { "TxFbCongestion", 33, 1 },
7942 { "TxPktSumSrdy", 32, 1 },
7943 { "RcfUlpType", 28, 4 },
7945 { "Ebypass", 26, 1 },
7947 { "Static0", 24, 1 },
7949 { "Cbypass", 22, 1 },
7951 { "CPktOut", 20, 1 },
7952 { "RxPagePoolFull", 18, 2 },
7953 { "RxLpbkPkt", 17, 1 },
7954 { "TxLpbkPkt", 16, 1 },
7955 { "RxVfValid", 15, 1 },
7956 { "SynLearned", 14, 1 },
7957 { "SetDelEntry", 13, 1 },
7958 { "SetInvEntry", 12, 1 },
7959 { "CpcmdDvld", 11, 1 },
7960 { "CpcmdSave", 10, 1 },
7961 { "RxPstructsFull", 8, 2 },
7962 { "EpcmdDvld", 7, 1 },
7963 { "EpcmdFlush", 6, 1 },
7964 { "EpcmdTrimPrefix", 5, 1 },
7965 { "EpcmdTrimPostfix", 4, 1 },
7966 { "ERssIp4Pkt", 3, 1 },
7967 { "ERssIp6Pkt", 2, 1 },
7968 { "ERssTcpUdpPkt", 1, 1 },
7969 { "ERssFceFipPkt", 0, 1 },
7974 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7977 field_desc_show(sb, *p, tp_la0);
7981 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7985 sbuf_printf(sb, "\n");
7986 field_desc_show(sb, p[0], tp_la0);
7987 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7988 field_desc_show(sb, p[1], tp_la0);
7992 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7996 sbuf_printf(sb, "\n");
7997 field_desc_show(sb, p[0], tp_la0);
7998 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7999 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8003 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8005 struct adapter *sc = arg1;
8010 void (*show_func)(struct sbuf *, uint64_t *, int);
8012 rc = sysctl_wire_old_buffer(req, 0);
8016 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8020 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8022 t4_tp_read_la(sc, buf, NULL);
8025 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8028 show_func = tp_la_show2;
8032 show_func = tp_la_show3;
8036 show_func = tp_la_show;
8039 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8040 (*show_func)(sb, p, i);
8042 rc = sbuf_finish(sb);
8049 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
8051 struct adapter *sc = arg1;
8054 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
8056 rc = sysctl_wire_old_buffer(req, 0);
8060 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8064 t4_get_chan_txrate(sc, nrate, orate);
8066 if (sc->chip_params->nchan > 2) {
8067 sbuf_printf(sb, " channel 0 channel 1"
8068 " channel 2 channel 3\n");
8069 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
8070 nrate[0], nrate[1], nrate[2], nrate[3]);
8071 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
8072 orate[0], orate[1], orate[2], orate[3]);
8074 sbuf_printf(sb, " channel 0 channel 1\n");
8075 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
8076 nrate[0], nrate[1]);
8077 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
8078 orate[0], orate[1]);
8081 rc = sbuf_finish(sb);
8088 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
8090 struct adapter *sc = arg1;
8095 rc = sysctl_wire_old_buffer(req, 0);
8099 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8103 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
8106 t4_ulprx_read_la(sc, buf);
8109 sbuf_printf(sb, " Pcmd Type Message"
8111 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
8112 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
8113 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
8116 rc = sbuf_finish(sb);
8123 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
8125 struct adapter *sc = arg1;
8129 MPASS(chip_id(sc) >= CHELSIO_T5);
8131 rc = sysctl_wire_old_buffer(req, 0);
8135 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8139 v = t4_read_reg(sc, A_SGE_STAT_CFG);
8140 if (G_STATSOURCE_T5(v) == 7) {
8143 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
8145 sbuf_printf(sb, "total %d, incomplete %d",
8146 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8147 t4_read_reg(sc, A_SGE_STAT_MATCH));
8148 } else if (mode == 1) {
8149 sbuf_printf(sb, "total %d, data overflow %d",
8150 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8151 t4_read_reg(sc, A_SGE_STAT_MATCH));
8153 sbuf_printf(sb, "unknown mode %d", mode);
8156 rc = sbuf_finish(sb);
8163 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
8165 struct adapter *sc = arg1;
8166 struct tx_cl_rl_params tc;
8168 int i, rc, port_id, mbps, gbps;
8170 rc = sysctl_wire_old_buffer(req, 0);
8174 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8178 port_id = arg2 >> 16;
8179 MPASS(port_id < sc->params.nports);
8180 MPASS(sc->port[port_id] != NULL);
8182 MPASS(i < sc->chip_params->nsched_cls);
8184 mtx_lock(&sc->tc_lock);
8185 tc = sc->port[port_id]->sched_params->cl_rl[i];
8186 mtx_unlock(&sc->tc_lock);
8188 if (tc.flags & TX_CLRL_ERROR) {
8189 sbuf_printf(sb, "error");
8193 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) {
8194 /* XXX: top speed or actual link speed? */
8195 gbps = port_top_speed(sc->port[port_id]);
8196 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps);
8197 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) {
8198 switch (tc.rateunit) {
8199 case SCHED_CLASS_RATEUNIT_BITS:
8200 mbps = tc.maxrate / 1000;
8201 gbps = tc.maxrate / 1000000;
8202 if (tc.maxrate == gbps * 1000000)
8203 sbuf_printf(sb, " %uGbps", gbps);
8204 else if (tc.maxrate == mbps * 1000)
8205 sbuf_printf(sb, " %uMbps", mbps);
8207 sbuf_printf(sb, " %uKbps", tc.maxrate);
8209 case SCHED_CLASS_RATEUNIT_PKTS:
8210 sbuf_printf(sb, " %upps", tc.maxrate);
8219 case SCHED_CLASS_MODE_CLASS:
8220 sbuf_printf(sb, " aggregate");
8222 case SCHED_CLASS_MODE_FLOW:
8223 sbuf_printf(sb, " per-flow");
8232 rc = sbuf_finish(sb);
8241 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8243 u_int rem = val % factor;
8246 snprintf(buf, len, "%u", val / factor);
8248 while (rem % 10 == 0)
8250 snprintf(buf, len, "%u.%u", val / factor, rem);
8255 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8257 struct adapter *sc = arg1;
8260 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8262 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8266 re = G_TIMERRESOLUTION(res);
8269 /* TCP timestamp tick */
8270 re = G_TIMESTAMPRESOLUTION(res);
8274 re = G_DELAYEDACKRESOLUTION(res);
8280 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
8282 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
8286 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
8288 struct adapter *sc = arg1;
8289 u_int res, dack_re, v;
8290 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8292 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8293 dack_re = G_DELAYEDACKRESOLUTION(res);
8294 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
8296 return (sysctl_handle_int(oidp, &v, 0, req));
8300 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
8302 struct adapter *sc = arg1;
8305 u_long tp_tick_us, v;
8306 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8308 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
8309 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
8310 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
8311 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
8313 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
8314 tp_tick_us = (cclk_ps << tre) / 1000000;
8316 if (reg == A_TP_INIT_SRTT)
8317 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
8319 v = tp_tick_us * t4_read_reg(sc, reg);
8321 return (sysctl_handle_long(oidp, &v, 0, req));
8325 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
8326 * passed to this function.
8329 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
8331 struct adapter *sc = arg1;
8335 MPASS(idx >= 0 && idx <= 24);
8337 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
8339 return (sysctl_handle_int(oidp, &v, 0, req));
8343 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
8345 struct adapter *sc = arg1;
8349 MPASS(idx >= 0 && idx < 16);
8351 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
8352 shift = (idx & 3) << 3;
8353 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
8355 return (sysctl_handle_int(oidp, &v, 0, req));
8359 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
8361 struct vi_info *vi = arg1;
8362 struct adapter *sc = vi->pi->adapter;
8364 struct sge_ofld_rxq *ofld_rxq;
8367 idx = vi->ofld_tmr_idx;
8369 rc = sysctl_handle_int(oidp, &idx, 0, req);
8370 if (rc != 0 || req->newptr == NULL)
8373 if (idx < 0 || idx >= SGE_NTIMERS)
8376 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8381 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
8382 for_each_ofld_rxq(vi, i, ofld_rxq) {
8383 #ifdef atomic_store_rel_8
8384 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
8386 ofld_rxq->iq.intr_params = v;
8389 vi->ofld_tmr_idx = idx;
8391 end_synchronized_op(sc, LOCK_HELD);
8396 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
8398 struct vi_info *vi = arg1;
8399 struct adapter *sc = vi->pi->adapter;
8402 idx = vi->ofld_pktc_idx;
8404 rc = sysctl_handle_int(oidp, &idx, 0, req);
8405 if (rc != 0 || req->newptr == NULL)
8408 if (idx < -1 || idx >= SGE_NCOUNTERS)
8411 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
8416 if (vi->flags & VI_INIT_DONE)
8417 rc = EBUSY; /* cannot be changed once the queues are created */
8419 vi->ofld_pktc_idx = idx;
8421 end_synchronized_op(sc, LOCK_HELD);
8427 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
8431 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
8432 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
8434 if (fconf & F_FRAGMENTATION)
8435 mode |= T4_FILTER_IP_FRAGMENT;
8437 if (fconf & F_MPSHITTYPE)
8438 mode |= T4_FILTER_MPS_HIT_TYPE;
8440 if (fconf & F_MACMATCH)
8441 mode |= T4_FILTER_MAC_IDX;
8443 if (fconf & F_ETHERTYPE)
8444 mode |= T4_FILTER_ETH_TYPE;
8446 if (fconf & F_PROTOCOL)
8447 mode |= T4_FILTER_IP_PROTO;
8450 mode |= T4_FILTER_IP_TOS;
8453 mode |= T4_FILTER_VLAN;
8455 if (fconf & F_VNIC_ID) {
8456 mode |= T4_FILTER_VNIC;
8458 mode |= T4_FILTER_IC_VNIC;
8462 mode |= T4_FILTER_PORT;
8465 mode |= T4_FILTER_FCoE;
8471 mode_to_fconf(uint32_t mode)
8475 if (mode & T4_FILTER_IP_FRAGMENT)
8476 fconf |= F_FRAGMENTATION;
8478 if (mode & T4_FILTER_MPS_HIT_TYPE)
8479 fconf |= F_MPSHITTYPE;
8481 if (mode & T4_FILTER_MAC_IDX)
8482 fconf |= F_MACMATCH;
8484 if (mode & T4_FILTER_ETH_TYPE)
8485 fconf |= F_ETHERTYPE;
8487 if (mode & T4_FILTER_IP_PROTO)
8488 fconf |= F_PROTOCOL;
8490 if (mode & T4_FILTER_IP_TOS)
8493 if (mode & T4_FILTER_VLAN)
8496 if (mode & T4_FILTER_VNIC)
8499 if (mode & T4_FILTER_PORT)
8502 if (mode & T4_FILTER_FCoE)
8509 mode_to_iconf(uint32_t mode)
8512 if (mode & T4_FILTER_IC_VNIC)
8517 static int check_fspec_against_fconf_iconf(struct adapter *sc,
8518 struct t4_filter_specification *fs)
8520 struct tp_params *tpp = &sc->params.tp;
8523 if (fs->val.frag || fs->mask.frag)
8524 fconf |= F_FRAGMENTATION;
8526 if (fs->val.matchtype || fs->mask.matchtype)
8527 fconf |= F_MPSHITTYPE;
8529 if (fs->val.macidx || fs->mask.macidx)
8530 fconf |= F_MACMATCH;
8532 if (fs->val.ethtype || fs->mask.ethtype)
8533 fconf |= F_ETHERTYPE;
8535 if (fs->val.proto || fs->mask.proto)
8536 fconf |= F_PROTOCOL;
8538 if (fs->val.tos || fs->mask.tos)
8541 if (fs->val.vlan_vld || fs->mask.vlan_vld)
8544 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
8546 if (tpp->ingress_config & F_VNIC)
8550 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
8552 if ((tpp->ingress_config & F_VNIC) == 0)
8556 if (fs->val.iport || fs->mask.iport)
8559 if (fs->val.fcoe || fs->mask.fcoe)
8562 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
8569 get_filter_mode(struct adapter *sc, uint32_t *mode)
8571 struct tp_params *tpp = &sc->params.tp;
8574 * We trust the cached values of the relevant TP registers. This means
8575 * things work reliably only if writes to those registers are always via
8576 * t4_set_filter_mode.
8578 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
8584 set_filter_mode(struct adapter *sc, uint32_t mode)
8586 struct tp_params *tpp = &sc->params.tp;
8587 uint32_t fconf, iconf;
8590 iconf = mode_to_iconf(mode);
8591 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
8593 * For now we just complain if A_TP_INGRESS_CONFIG is not
8594 * already set to the correct value for the requested filter
8595 * mode. It's not clear if it's safe to write to this register
8596 * on the fly. (And we trust the cached value of the register).
8601 fconf = mode_to_fconf(mode);
8603 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8608 if (sc->tids.ftids_in_use > 0) {
8614 if (uld_active(sc, ULD_TOM)) {
8620 rc = -t4_set_filter_mode(sc, fconf, true);
8622 end_synchronized_op(sc, LOCK_HELD);
8626 static inline uint64_t
8627 get_filter_hits(struct adapter *sc, uint32_t fid)
8631 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
8632 (fid + sc->tids.ftid_base) * TCB_SIZE;
8637 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
8638 return (be64toh(hits));
8642 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
8643 return (be32toh(hits));
8648 get_filter(struct adapter *sc, struct t4_filter *t)
8650 int i, rc, nfilters = sc->tids.nftids;
8651 struct filter_entry *f;
8653 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8658 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
8659 t->idx >= nfilters) {
8660 t->idx = 0xffffffff;
8664 f = &sc->tids.ftid_tab[t->idx];
8665 for (i = t->idx; i < nfilters; i++, f++) {
8668 t->l2tidx = f->l2t ? f->l2t->idx : 0;
8669 t->smtidx = f->smtidx;
8671 t->hits = get_filter_hits(sc, t->idx);
8673 t->hits = UINT64_MAX;
8680 t->idx = 0xffffffff;
8682 end_synchronized_op(sc, LOCK_HELD);
8687 set_filter(struct adapter *sc, struct t4_filter *t)
8689 unsigned int nfilters, nports;
8690 struct filter_entry *f;
8693 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
8697 nfilters = sc->tids.nftids;
8698 nports = sc->params.nports;
8700 if (nfilters == 0) {
8705 if (t->idx >= nfilters) {
8710 /* Validate against the global filter mode and ingress config */
8711 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
8715 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
8720 if (t->fs.val.iport >= nports) {
8725 /* Can't specify an iq if not steering to it */
8726 if (!t->fs.dirsteer && t->fs.iq) {
8731 /* IPv6 filter idx must be 4 aligned */
8732 if (t->fs.type == 1 &&
8733 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
8738 if (!(sc->flags & FULL_INIT_DONE) &&
8739 ((rc = adapter_full_init(sc)) != 0))
8742 if (sc->tids.ftid_tab == NULL) {
8743 KASSERT(sc->tids.ftids_in_use == 0,
8744 ("%s: no memory allocated but filters_in_use > 0",
8747 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
8748 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
8749 if (sc->tids.ftid_tab == NULL) {
8753 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
8756 for (i = 0; i < 4; i++) {
8757 f = &sc->tids.ftid_tab[t->idx + i];
8759 if (f->pending || f->valid) {
8768 if (t->fs.type == 0)
8772 f = &sc->tids.ftid_tab[t->idx];
8775 rc = set_filter_wr(sc, t->idx);
8777 end_synchronized_op(sc, 0);
8780 mtx_lock(&sc->tids.ftid_lock);
8782 if (f->pending == 0) {
8783 rc = f->valid ? 0 : EIO;
8787 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8788 PCATCH, "t4setfw", 0)) {
8793 mtx_unlock(&sc->tids.ftid_lock);
8799 del_filter(struct adapter *sc, struct t4_filter *t)
8801 unsigned int nfilters;
8802 struct filter_entry *f;
8805 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8809 nfilters = sc->tids.nftids;
8811 if (nfilters == 0) {
8816 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8817 t->idx >= nfilters) {
8822 if (!(sc->flags & FULL_INIT_DONE)) {
8827 f = &sc->tids.ftid_tab[t->idx];
8839 t->fs = f->fs; /* extra info for the caller */
8840 rc = del_filter_wr(sc, t->idx);
8844 end_synchronized_op(sc, 0);
8847 mtx_lock(&sc->tids.ftid_lock);
8849 if (f->pending == 0) {
8850 rc = f->valid ? EIO : 0;
8854 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8855 PCATCH, "t4delfw", 0)) {
8860 mtx_unlock(&sc->tids.ftid_lock);
8867 clear_filter(struct filter_entry *f)
8870 t4_l2t_release(f->l2t);
8872 bzero(f, sizeof (*f));
8876 set_filter_wr(struct adapter *sc, int fidx)
8878 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8879 struct fw_filter_wr *fwr;
8880 unsigned int ftid, vnic_vld, vnic_vld_mask;
8881 struct wrq_cookie cookie;
8883 ASSERT_SYNCHRONIZED_OP(sc);
8885 if (f->fs.newdmac || f->fs.newvlan) {
8886 /* This filter needs an L2T entry; allocate one. */
8887 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8890 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8892 t4_l2t_release(f->l2t);
8898 /* Already validated against fconf, iconf */
8899 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8900 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8901 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8905 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8910 ftid = sc->tids.ftid_base + fidx;
8912 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8915 bzero(fwr, sizeof(*fwr));
8917 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8918 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8920 htobe32(V_FW_FILTER_WR_TID(ftid) |
8921 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8922 V_FW_FILTER_WR_NOREPLY(0) |
8923 V_FW_FILTER_WR_IQ(f->fs.iq));
8924 fwr->del_filter_to_l2tix =
8925 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8926 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8927 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8928 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8929 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8930 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8931 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8932 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8933 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8934 f->fs.newvlan == VLAN_REWRITE) |
8935 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8936 f->fs.newvlan == VLAN_REWRITE) |
8937 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8938 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8939 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8940 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8941 fwr->ethtype = htobe16(f->fs.val.ethtype);
8942 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8943 fwr->frag_to_ovlan_vldm =
8944 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8945 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8946 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8947 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8948 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8949 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8951 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8952 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8953 fwr->maci_to_matchtypem =
8954 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8955 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8956 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8957 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8958 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8959 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8960 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8961 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8962 fwr->ptcl = f->fs.val.proto;
8963 fwr->ptclm = f->fs.mask.proto;
8964 fwr->ttyp = f->fs.val.tos;
8965 fwr->ttypm = f->fs.mask.tos;
8966 fwr->ivlan = htobe16(f->fs.val.vlan);
8967 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8968 fwr->ovlan = htobe16(f->fs.val.vnic);
8969 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8970 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8971 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8972 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8973 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8974 fwr->lp = htobe16(f->fs.val.dport);
8975 fwr->lpm = htobe16(f->fs.mask.dport);
8976 fwr->fp = htobe16(f->fs.val.sport);
8977 fwr->fpm = htobe16(f->fs.mask.sport);
8979 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8982 sc->tids.ftids_in_use++;
8984 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8989 del_filter_wr(struct adapter *sc, int fidx)
8991 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8992 struct fw_filter_wr *fwr;
8994 struct wrq_cookie cookie;
8996 ftid = sc->tids.ftid_base + fidx;
8998 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
9001 bzero(fwr, sizeof (*fwr));
9003 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
9006 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
9011 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9013 struct adapter *sc = iq->adapter;
9014 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
9015 unsigned int idx = GET_TID(rpl);
9017 struct filter_entry *f;
9019 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
9021 MPASS(iq == &sc->sge.fwq);
9022 MPASS(is_ftid(sc, idx));
9024 idx -= sc->tids.ftid_base;
9025 f = &sc->tids.ftid_tab[idx];
9026 rc = G_COOKIE(rpl->cookie);
9028 mtx_lock(&sc->tids.ftid_lock);
9029 if (rc == FW_FILTER_WR_FLT_ADDED) {
9030 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
9032 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
9033 f->pending = 0; /* asynchronous setup completed */
9036 if (rc != FW_FILTER_WR_FLT_DELETED) {
9037 /* Add or delete failed, display an error */
9039 "filter %u setup failed with error %u\n",
9044 sc->tids.ftids_in_use--;
9046 wakeup(&sc->tids.ftid_tab);
9047 mtx_unlock(&sc->tids.ftid_lock);
9053 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9056 MPASS(iq->set_tcb_rpl != NULL);
9057 return (iq->set_tcb_rpl(iq, rss, m));
9061 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
9064 MPASS(iq->l2t_write_rpl != NULL);
9065 return (iq->l2t_write_rpl(iq, rss, m));
9069 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9073 if (cntxt->cid > M_CTXTQID)
9076 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9077 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9080 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9084 if (sc->flags & FW_OK) {
9085 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9092 * Read via firmware failed or wasn't even attempted. Read directly via
9095 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9097 end_synchronized_op(sc, 0);
9102 load_fw(struct adapter *sc, struct t4_data *fw)
9107 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9112 * The firmware, with the sole exception of the memory parity error
9113 * handler, runs from memory and not flash. It is almost always safe to
9114 * install a new firmware on a running system. Just set bit 1 in
9115 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9117 if (sc->flags & FULL_INIT_DONE &&
9118 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9123 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9124 if (fw_data == NULL) {
9129 rc = copyin(fw->data, fw_data, fw->len);
9131 rc = -t4_load_fw(sc, fw_data, fw->len);
9133 free(fw_data, M_CXGBE);
9135 end_synchronized_op(sc, 0);
9140 load_cfg(struct adapter *sc, struct t4_data *cfg)
9143 uint8_t *cfg_data = NULL;
9145 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9149 if (cfg->len == 0) {
9151 rc = -t4_load_cfg(sc, NULL, 0);
9155 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9156 if (cfg_data == NULL) {
9161 rc = copyin(cfg->data, cfg_data, cfg->len);
9163 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9165 free(cfg_data, M_CXGBE);
9167 end_synchronized_op(sc, 0);
9172 load_boot(struct adapter *sc, struct t4_bootrom *br)
9175 uint8_t *br_data = NULL;
9178 if (br->len > 1024 * 1024)
9181 if (br->pf_offset == 0) {
9183 if (br->pfidx_addr > 7)
9185 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9186 A_PCIE_PF_EXPROM_OFST)));
9187 } else if (br->pf_offset == 1) {
9189 offset = G_OFFSET(br->pfidx_addr);
9194 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9200 rc = -t4_load_boot(sc, NULL, offset, 0);
9204 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9205 if (br_data == NULL) {
9210 rc = copyin(br->data, br_data, br->len);
9212 rc = -t4_load_boot(sc, br_data, offset, br->len);
9214 free(br_data, M_CXGBE);
9216 end_synchronized_op(sc, 0);
9221 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9224 uint8_t *bc_data = NULL;
9226 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9232 rc = -t4_load_bootcfg(sc, NULL, 0);
9236 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9237 if (bc_data == NULL) {
9242 rc = copyin(bc->data, bc_data, bc->len);
9244 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9246 free(bc_data, M_CXGBE);
9248 end_synchronized_op(sc, 0);
9253 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9256 struct cudbg_init *cudbg;
9259 /* buf is large, don't block if no memory is available */
9260 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9264 handle = cudbg_alloc_handle();
9265 if (handle == NULL) {
9270 cudbg = cudbg_get_init(handle);
9272 cudbg->print = (cudbg_print_cb)printf;
9275 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9276 __func__, dump->wr_flash, dump->len, dump->data);
9280 cudbg->use_flash = 1;
9281 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9282 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9284 rc = cudbg_collect(handle, buf, &dump->len);
9288 rc = copyout(buf, dump->data, dump->len);
9290 cudbg_free_handle(handle);
9295 #define MAX_READ_BUF_SIZE (128 * 1024)
9297 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9299 uint32_t addr, remaining, n;
9304 rc = validate_mem_range(sc, mr->addr, mr->len);
9308 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9310 remaining = mr->len;
9311 dst = (void *)mr->data;
9314 n = min(remaining, MAX_READ_BUF_SIZE);
9315 read_via_memwin(sc, 2, addr, buf, n);
9317 rc = copyout(buf, dst, n);
9329 #undef MAX_READ_BUF_SIZE
9332 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9336 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9339 if (i2cd->len > sizeof(i2cd->data))
9342 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9345 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9346 i2cd->offset, i2cd->len, &i2cd->data[0]);
9347 end_synchronized_op(sc, 0);
9353 t4_os_find_pci_capability(struct adapter *sc, int cap)
9357 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9361 t4_os_pci_save_state(struct adapter *sc)
9364 struct pci_devinfo *dinfo;
9367 dinfo = device_get_ivars(dev);
9369 pci_cfg_save(dev, dinfo, 0);
9374 t4_os_pci_restore_state(struct adapter *sc)
9377 struct pci_devinfo *dinfo;
9380 dinfo = device_get_ivars(dev);
9382 pci_cfg_restore(dev, dinfo);
9387 t4_os_portmod_changed(struct port_info *pi)
9389 struct adapter *sc = pi->adapter;
9392 static const char *mod_str[] = {
9393 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9397 build_medialist(pi, &pi->media);
9400 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9402 end_synchronized_op(sc, LOCK_HELD);
9406 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9407 if_printf(ifp, "transceiver unplugged.\n");
9408 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9409 if_printf(ifp, "unknown transceiver inserted.\n");
9410 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9411 if_printf(ifp, "unsupported transceiver inserted.\n");
9412 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9413 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9414 port_top_speed(pi), mod_str[pi->mod_type]);
9416 if_printf(ifp, "transceiver (type %d) inserted.\n",
9422 t4_os_link_changed(struct port_info *pi)
9426 struct link_config *lc;
9429 for_each_vi(pi, v, vi) {
9436 ifp->if_baudrate = IF_Mbps(lc->speed);
9437 if_link_state_change(ifp, LINK_STATE_UP);
9439 if_link_state_change(ifp, LINK_STATE_DOWN);
9445 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9449 sx_slock(&t4_list_lock);
9450 SLIST_FOREACH(sc, &t4_list, link) {
9452 * func should not make any assumptions about what state sc is
9453 * in - the only guarantee is that sc->sc_lock is a valid lock.
9457 sx_sunlock(&t4_list_lock);
9461 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9465 struct adapter *sc = dev->si_drv1;
9467 rc = priv_check(td, PRIV_DRIVER);
9472 case CHELSIO_T4_GETREG: {
9473 struct t4_reg *edata = (struct t4_reg *)data;
9475 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9478 if (edata->size == 4)
9479 edata->val = t4_read_reg(sc, edata->addr);
9480 else if (edata->size == 8)
9481 edata->val = t4_read_reg64(sc, edata->addr);
9487 case CHELSIO_T4_SETREG: {
9488 struct t4_reg *edata = (struct t4_reg *)data;
9490 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9493 if (edata->size == 4) {
9494 if (edata->val & 0xffffffff00000000)
9496 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9497 } else if (edata->size == 8)
9498 t4_write_reg64(sc, edata->addr, edata->val);
9503 case CHELSIO_T4_REGDUMP: {
9504 struct t4_regdump *regs = (struct t4_regdump *)data;
9505 int reglen = t4_get_regs_len(sc);
9508 if (regs->len < reglen) {
9509 regs->len = reglen; /* hint to the caller */
9514 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9515 get_regs(sc, regs, buf);
9516 rc = copyout(buf, regs->data, reglen);
9520 case CHELSIO_T4_GET_FILTER_MODE:
9521 rc = get_filter_mode(sc, (uint32_t *)data);
9523 case CHELSIO_T4_SET_FILTER_MODE:
9524 rc = set_filter_mode(sc, *(uint32_t *)data);
9526 case CHELSIO_T4_GET_FILTER:
9527 rc = get_filter(sc, (struct t4_filter *)data);
9529 case CHELSIO_T4_SET_FILTER:
9530 rc = set_filter(sc, (struct t4_filter *)data);
9532 case CHELSIO_T4_DEL_FILTER:
9533 rc = del_filter(sc, (struct t4_filter *)data);
9535 case CHELSIO_T4_GET_SGE_CONTEXT:
9536 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9538 case CHELSIO_T4_LOAD_FW:
9539 rc = load_fw(sc, (struct t4_data *)data);
9541 case CHELSIO_T4_GET_MEM:
9542 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9544 case CHELSIO_T4_GET_I2C:
9545 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9547 case CHELSIO_T4_CLEAR_STATS: {
9549 u_int port_id = *(uint32_t *)data;
9550 struct port_info *pi;
9553 if (port_id >= sc->params.nports)
9555 pi = sc->port[port_id];
9560 t4_clr_port_stats(sc, pi->tx_chan);
9561 pi->tx_parse_error = 0;
9562 mtx_lock(&sc->reg_lock);
9563 for_each_vi(pi, v, vi) {
9564 if (vi->flags & VI_INIT_DONE)
9565 t4_clr_vi_stats(sc, vi->viid);
9567 mtx_unlock(&sc->reg_lock);
9570 * Since this command accepts a port, clear stats for
9571 * all VIs on this port.
9573 for_each_vi(pi, v, vi) {
9574 if (vi->flags & VI_INIT_DONE) {
9575 struct sge_rxq *rxq;
9576 struct sge_txq *txq;
9577 struct sge_wrq *wrq;
9579 for_each_rxq(vi, i, rxq) {
9580 #if defined(INET) || defined(INET6)
9581 rxq->lro.lro_queued = 0;
9582 rxq->lro.lro_flushed = 0;
9585 rxq->vlan_extraction = 0;
9588 for_each_txq(vi, i, txq) {
9591 txq->vlan_insertion = 0;
9595 txq->txpkts0_wrs = 0;
9596 txq->txpkts1_wrs = 0;
9597 txq->txpkts0_pkts = 0;
9598 txq->txpkts1_pkts = 0;
9599 mp_ring_reset_stats(txq->r);
9603 /* nothing to clear for each ofld_rxq */
9605 for_each_ofld_txq(vi, i, wrq) {
9606 wrq->tx_wrs_direct = 0;
9607 wrq->tx_wrs_copied = 0;
9611 if (IS_MAIN_VI(vi)) {
9612 wrq = &sc->sge.ctrlq[pi->port_id];
9613 wrq->tx_wrs_direct = 0;
9614 wrq->tx_wrs_copied = 0;
9620 case CHELSIO_T4_SCHED_CLASS:
9621 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9623 case CHELSIO_T4_SCHED_QUEUE:
9624 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9626 case CHELSIO_T4_GET_TRACER:
9627 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9629 case CHELSIO_T4_SET_TRACER:
9630 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9632 case CHELSIO_T4_LOAD_CFG:
9633 rc = load_cfg(sc, (struct t4_data *)data);
9635 case CHELSIO_T4_LOAD_BOOT:
9636 rc = load_boot(sc, (struct t4_bootrom *)data);
9638 case CHELSIO_T4_LOAD_BOOTCFG:
9639 rc = load_bootcfg(sc, (struct t4_data *)data);
9641 case CHELSIO_T4_CUDBG_DUMP:
9642 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
9652 t4_db_full(struct adapter *sc)
9655 CXGBE_UNIMPLEMENTED(__func__);
9659 t4_db_dropped(struct adapter *sc)
9662 CXGBE_UNIMPLEMENTED(__func__);
9667 toe_capability(struct vi_info *vi, int enable)
9670 struct port_info *pi = vi->pi;
9671 struct adapter *sc = pi->adapter;
9673 ASSERT_SYNCHRONIZED_OP(sc);
9675 if (!is_offload(sc))
9679 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9680 /* TOE is already enabled. */
9685 * We need the port's queues around so that we're able to send
9686 * and receive CPLs to/from the TOE even if the ifnet for this
9687 * port has never been UP'd administratively.
9689 if (!(vi->flags & VI_INIT_DONE)) {
9690 rc = vi_full_init(vi);
9694 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9695 rc = vi_full_init(&pi->vi[0]);
9700 if (isset(&sc->offload_map, pi->port_id)) {
9701 /* TOE is enabled on another VI of this port. */
9706 if (!uld_active(sc, ULD_TOM)) {
9707 rc = t4_activate_uld(sc, ULD_TOM);
9710 "You must kldload t4_tom.ko before trying "
9711 "to enable TOE on a cxgbe interface.\n");
9715 KASSERT(sc->tom_softc != NULL,
9716 ("%s: TOM activated but softc NULL", __func__));
9717 KASSERT(uld_active(sc, ULD_TOM),
9718 ("%s: TOM activated but flag not set", __func__));
9721 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9722 if (!uld_active(sc, ULD_IWARP))
9723 (void) t4_activate_uld(sc, ULD_IWARP);
9724 if (!uld_active(sc, ULD_ISCSI))
9725 (void) t4_activate_uld(sc, ULD_ISCSI);
9728 setbit(&sc->offload_map, pi->port_id);
9732 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9735 KASSERT(uld_active(sc, ULD_TOM),
9736 ("%s: TOM never initialized?", __func__));
9737 clrbit(&sc->offload_map, pi->port_id);
9744 * Add an upper layer driver to the global list.
9747 t4_register_uld(struct uld_info *ui)
9752 sx_xlock(&t4_uld_list_lock);
9753 SLIST_FOREACH(u, &t4_uld_list, link) {
9754 if (u->uld_id == ui->uld_id) {
9760 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9763 sx_xunlock(&t4_uld_list_lock);
9768 t4_unregister_uld(struct uld_info *ui)
9773 sx_xlock(&t4_uld_list_lock);
9775 SLIST_FOREACH(u, &t4_uld_list, link) {
9777 if (ui->refcount > 0) {
9782 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9788 sx_xunlock(&t4_uld_list_lock);
9793 t4_activate_uld(struct adapter *sc, int id)
9796 struct uld_info *ui;
9798 ASSERT_SYNCHRONIZED_OP(sc);
9800 if (id < 0 || id > ULD_MAX)
9802 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9804 sx_slock(&t4_uld_list_lock);
9806 SLIST_FOREACH(ui, &t4_uld_list, link) {
9807 if (ui->uld_id == id) {
9808 if (!(sc->flags & FULL_INIT_DONE)) {
9809 rc = adapter_full_init(sc);
9814 rc = ui->activate(sc);
9816 setbit(&sc->active_ulds, id);
9823 sx_sunlock(&t4_uld_list_lock);
9829 t4_deactivate_uld(struct adapter *sc, int id)
9832 struct uld_info *ui;
9834 ASSERT_SYNCHRONIZED_OP(sc);
9836 if (id < 0 || id > ULD_MAX)
9840 sx_slock(&t4_uld_list_lock);
9842 SLIST_FOREACH(ui, &t4_uld_list, link) {
9843 if (ui->uld_id == id) {
9844 rc = ui->deactivate(sc);
9846 clrbit(&sc->active_ulds, id);
9853 sx_sunlock(&t4_uld_list_lock);
9859 uld_active(struct adapter *sc, int uld_id)
9862 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9864 return (isset(&sc->active_ulds, uld_id));
9869 * t = ptr to tunable.
9870 * nc = number of CPUs.
9871 * c = compiled in default for that tunable.
9874 calculate_nqueues(int *t, int nc, const int c)
9880 nq = *t < 0 ? -*t : c;
9885 * Come up with reasonable defaults for some of the tunables, provided they're
9886 * not set by the user (in which case we'll use the values as is).
9889 tweak_tunables(void)
9891 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9895 t4_ntxq = rss_getnumbuckets();
9897 calculate_nqueues(&t4_ntxq, nc, NTXQ);
9901 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
9905 t4_nrxq = rss_getnumbuckets();
9907 calculate_nqueues(&t4_nrxq, nc, NRXQ);
9911 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
9914 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
9915 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
9916 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
9917 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
9919 if (t4_toecaps_allowed == -1)
9920 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9922 if (t4_rdmacaps_allowed == -1) {
9923 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9924 FW_CAPS_CONFIG_RDMA_RDMAC;
9927 if (t4_iscsicaps_allowed == -1) {
9928 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9929 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9930 FW_CAPS_CONFIG_ISCSI_T10DIF;
9933 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
9934 t4_tmr_idx_ofld = TMR_IDX_OFLD;
9936 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
9937 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
9939 if (t4_toecaps_allowed == -1)
9940 t4_toecaps_allowed = 0;
9942 if (t4_rdmacaps_allowed == -1)
9943 t4_rdmacaps_allowed = 0;
9945 if (t4_iscsicaps_allowed == -1)
9946 t4_iscsicaps_allowed = 0;
9950 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
9951 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
9954 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
9955 t4_tmr_idx = TMR_IDX;
9957 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
9958 t4_pktc_idx = PKTC_IDX;
9960 if (t4_qsize_txq < 128)
9963 if (t4_qsize_rxq < 128)
9965 while (t4_qsize_rxq & 7)
9968 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9971 * Number of VIs to create per-port. The first VI is the "main" regular
9972 * VI for the port. The rest are additional virtual interfaces on the
9973 * same physical port. Note that the main VI does not have native
9974 * netmap support but the extra VIs do.
9976 * Limit the number of VIs per port to the number of available
9977 * MAC addresses per port.
9981 if (t4_num_vis > nitems(vi_mac_funcs)) {
9982 t4_num_vis = nitems(vi_mac_funcs);
9983 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
9986 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
9987 pcie_relaxed_ordering = 1;
9988 #if defined(__i386__) || defined(__amd64__)
9989 if (cpu_vendor_id == CPU_VENDOR_INTEL)
9990 pcie_relaxed_ordering = 0;
9997 t4_dump_tcb(struct adapter *sc, int tid)
9999 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10001 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10002 save = t4_read_reg(sc, reg);
10003 base = sc->memwin[2].mw_base;
10005 /* Dump TCB for the tid */
10006 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10007 tcb_addr += tid * TCB_SIZE;
10011 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10013 pf = V_PFNUM(sc->pf);
10014 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10016 t4_write_reg(sc, reg, win_pos | pf);
10017 t4_read_reg(sc, reg);
10019 off = tcb_addr - win_pos;
10020 for (i = 0; i < 4; i++) {
10022 for (j = 0; j < 8; j++, off += 4)
10023 buf[j] = htonl(t4_read_reg(sc, base + off));
10025 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10026 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10030 t4_write_reg(sc, reg, save);
10031 t4_read_reg(sc, reg);
10035 t4_dump_devlog(struct adapter *sc)
10037 struct devlog_params *dparams = &sc->params.devlog;
10038 struct fw_devlog_e e;
10039 int i, first, j, m, nentries, rc;
10040 uint64_t ftstamp = UINT64_MAX;
10042 if (dparams->start == 0) {
10043 db_printf("devlog params not valid\n");
10047 nentries = dparams->size / sizeof(struct fw_devlog_e);
10048 m = fwmtype_to_hwmtype(dparams->memtype);
10050 /* Find the first entry. */
10052 for (i = 0; i < nentries && !db_pager_quit; i++) {
10053 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10054 sizeof(e), (void *)&e);
10058 if (e.timestamp == 0)
10061 e.timestamp = be64toh(e.timestamp);
10062 if (e.timestamp < ftstamp) {
10063 ftstamp = e.timestamp;
10073 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10074 sizeof(e), (void *)&e);
10078 if (e.timestamp == 0)
10081 e.timestamp = be64toh(e.timestamp);
10082 e.seqno = be32toh(e.seqno);
10083 for (j = 0; j < 8; j++)
10084 e.params[j] = be32toh(e.params[j]);
10086 db_printf("%10d %15ju %8s %8s ",
10087 e.seqno, e.timestamp,
10088 (e.level < nitems(devlog_level_strings) ?
10089 devlog_level_strings[e.level] : "UNKNOWN"),
10090 (e.facility < nitems(devlog_facility_strings) ?
10091 devlog_facility_strings[e.facility] : "UNKNOWN"));
10092 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10093 e.params[3], e.params[4], e.params[5], e.params[6],
10096 if (++i == nentries)
10098 } while (i != first && !db_pager_quit);
10101 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10102 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10104 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10111 t = db_read_token();
10113 dev = device_lookup_by_name(db_tok_string);
10118 db_printf("usage: show t4 devlog <nexus>\n");
10123 db_printf("device not found\n");
10127 t4_dump_devlog(device_get_softc(dev));
10130 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10139 t = db_read_token();
10141 dev = device_lookup_by_name(db_tok_string);
10142 t = db_read_token();
10143 if (t == tNUMBER) {
10144 tid = db_tok_number;
10151 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10156 db_printf("device not found\n");
10160 db_printf("invalid tid\n");
10164 t4_dump_tcb(device_get_softc(dev), tid);
10168 static struct sx mlu; /* mod load unload */
10169 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10172 mod_event(module_t mod, int cmd, void *arg)
10175 static int loaded = 0;
10180 if (loaded++ == 0) {
10182 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
10183 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
10184 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10185 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10186 sx_init(&t4_list_lock, "T4/T5 adapters");
10187 SLIST_INIT(&t4_list);
10189 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10190 SLIST_INIT(&t4_uld_list);
10192 t4_tracer_modload();
10200 if (--loaded == 0) {
10203 sx_slock(&t4_list_lock);
10204 if (!SLIST_EMPTY(&t4_list)) {
10206 sx_sunlock(&t4_list_lock);
10210 sx_slock(&t4_uld_list_lock);
10211 if (!SLIST_EMPTY(&t4_uld_list)) {
10213 sx_sunlock(&t4_uld_list_lock);
10214 sx_sunlock(&t4_list_lock);
10219 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10220 uprintf("%ju clusters with custom free routine "
10221 "still is use.\n", t4_sge_extfree_refs());
10222 pause("t4unload", 2 * hz);
10225 sx_sunlock(&t4_uld_list_lock);
10227 sx_sunlock(&t4_list_lock);
10229 if (t4_sge_extfree_refs() == 0) {
10230 t4_tracer_modunload();
10232 sx_destroy(&t4_uld_list_lock);
10234 sx_destroy(&t4_list_lock);
10235 t4_sge_modunload();
10239 loaded++; /* undo earlier decrement */
10250 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10251 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10252 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10254 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10255 MODULE_VERSION(t4nex, 1);
10256 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10258 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10259 #endif /* DEV_NETMAP */
10261 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10262 MODULE_VERSION(t5nex, 1);
10263 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10265 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10266 #endif /* DEV_NETMAP */
10268 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10269 MODULE_VERSION(t6nex, 1);
10270 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10272 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10273 #endif /* DEV_NETMAP */
10275 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10276 MODULE_VERSION(cxgbe, 1);
10278 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10279 MODULE_VERSION(cxl, 1);
10281 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10282 MODULE_VERSION(cc, 1);
10284 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10285 MODULE_VERSION(vcxgbe, 1);
10287 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10288 MODULE_VERSION(vcxl, 1);
10290 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10291 MODULE_VERSION(vcc, 1);