2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
36 #include <sys/param.h>
39 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pci_private.h>
49 #include <sys/firmware.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
61 #include <net/rss_config.h>
63 #if defined(__i386__) || defined(__amd64__)
69 #include <ddb/db_lex.h>
72 #include "common/common.h"
73 #include "common/t4_msg.h"
74 #include "common/t4_regs.h"
75 #include "common/t4_regs_values.h"
78 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static int t4_ready(device_t);
86 static int t4_read_port_device(device_t, int, device_t *);
87 static device_method_t t4_methods[] = {
88 DEVMETHOD(device_probe, t4_probe),
89 DEVMETHOD(device_attach, t4_attach),
90 DEVMETHOD(device_detach, t4_detach),
92 DEVMETHOD(t4_is_main_ready, t4_ready),
93 DEVMETHOD(t4_read_port_device, t4_read_port_device),
97 static driver_t t4_driver = {
100 sizeof(struct adapter)
104 /* T4 port (cxgbe) interface */
105 static int cxgbe_probe(device_t);
106 static int cxgbe_attach(device_t);
107 static int cxgbe_detach(device_t);
108 static device_method_t cxgbe_methods[] = {
109 DEVMETHOD(device_probe, cxgbe_probe),
110 DEVMETHOD(device_attach, cxgbe_attach),
111 DEVMETHOD(device_detach, cxgbe_detach),
114 static driver_t cxgbe_driver = {
117 sizeof(struct port_info)
120 /* T4 VI (vcxgbe) interface */
121 static int vcxgbe_probe(device_t);
122 static int vcxgbe_attach(device_t);
123 static int vcxgbe_detach(device_t);
124 static device_method_t vcxgbe_methods[] = {
125 DEVMETHOD(device_probe, vcxgbe_probe),
126 DEVMETHOD(device_attach, vcxgbe_attach),
127 DEVMETHOD(device_detach, vcxgbe_detach),
130 static driver_t vcxgbe_driver = {
133 sizeof(struct vi_info)
136 static d_ioctl_t t4_ioctl;
138 static struct cdevsw t4_cdevsw = {
139 .d_version = D_VERSION,
144 /* T5 bus driver interface */
145 static int t5_probe(device_t);
146 static device_method_t t5_methods[] = {
147 DEVMETHOD(device_probe, t5_probe),
148 DEVMETHOD(device_attach, t4_attach),
149 DEVMETHOD(device_detach, t4_detach),
151 DEVMETHOD(t4_is_main_ready, t4_ready),
152 DEVMETHOD(t4_read_port_device, t4_read_port_device),
156 static driver_t t5_driver = {
159 sizeof(struct adapter)
163 /* T5 port (cxl) interface */
164 static driver_t cxl_driver = {
167 sizeof(struct port_info)
170 /* T5 VI (vcxl) interface */
171 static driver_t vcxl_driver = {
174 sizeof(struct vi_info)
177 /* ifnet + media interface */
178 static void cxgbe_init(void *);
179 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
180 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
181 static void cxgbe_qflush(struct ifnet *);
182 static int cxgbe_media_change(struct ifnet *);
183 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
185 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
188 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
189 * then ADAPTER_LOCK, then t4_uld_list_lock.
191 static struct sx t4_list_lock;
192 SLIST_HEAD(, adapter) t4_list;
194 static struct sx t4_uld_list_lock;
195 SLIST_HEAD(, uld_info) t4_uld_list;
199 * Tunables. See tweak_tunables() too.
201 * Each tunable is set to a default value here if it's known at compile-time.
202 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
203 * provide a reasonable default when the driver is loaded.
205 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
206 * T5 are under hw.cxl.
210 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
213 static int t4_ntxq10g = -1;
214 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
217 static int t4_nrxq10g = -1;
218 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
221 static int t4_ntxq1g = -1;
222 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
225 static int t4_nrxq1g = -1;
226 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
229 static int t4_ntxq_vi = -1;
230 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
233 static int t4_nrxq_vi = -1;
234 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
236 static int t4_rsrv_noflowq = 0;
237 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
240 #define NOFLDTXQ_10G 8
241 static int t4_nofldtxq10g = -1;
242 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
244 #define NOFLDRXQ_10G 2
245 static int t4_nofldrxq10g = -1;
246 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
248 #define NOFLDTXQ_1G 2
249 static int t4_nofldtxq1g = -1;
250 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
252 #define NOFLDRXQ_1G 1
253 static int t4_nofldrxq1g = -1;
254 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
256 #define NOFLDTXQ_VI 1
257 static int t4_nofldtxq_vi = -1;
258 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
260 #define NOFLDRXQ_VI 1
261 static int t4_nofldrxq_vi = -1;
262 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
267 static int t4_nnmtxq_vi = -1;
268 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
271 static int t4_nnmrxq_vi = -1;
272 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
276 * Holdoff parameters for 10G and 1G ports.
278 #define TMR_IDX_10G 1
279 static int t4_tmr_idx_10g = TMR_IDX_10G;
280 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
282 #define PKTC_IDX_10G (-1)
283 static int t4_pktc_idx_10g = PKTC_IDX_10G;
284 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
287 static int t4_tmr_idx_1g = TMR_IDX_1G;
288 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
290 #define PKTC_IDX_1G (-1)
291 static int t4_pktc_idx_1g = PKTC_IDX_1G;
292 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
295 * Size (# of entries) of each tx and rx queue.
297 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
298 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
300 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
301 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
304 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
306 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
307 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
310 * Configuration file.
312 #define DEFAULT_CF "default"
313 #define FLASH_CF "flash"
314 #define UWIRE_CF "uwire"
315 #define FPGA_CF "fpga"
316 static char t4_cfg_file[32] = DEFAULT_CF;
317 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
320 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
321 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
322 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
323 * mark or when signalled to do so, 0 to never emit PAUSE.
325 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
326 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
329 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
330 * encouraged respectively).
332 static unsigned int t4_fw_install = 1;
333 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
336 * ASIC features that will be used. Disable the ones you don't want so that the
337 * chip resources aren't wasted on features that will not be used.
339 static int t4_nbmcaps_allowed = 0;
340 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
342 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
343 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
345 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
346 FW_CAPS_CONFIG_SWITCH_EGRESS;
347 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
349 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
350 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
352 static int t4_toecaps_allowed = -1;
353 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
355 static int t4_rdmacaps_allowed = -1;
356 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
358 static int t4_tlscaps_allowed = 0;
359 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
361 static int t4_iscsicaps_allowed = -1;
362 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
364 static int t4_fcoecaps_allowed = 0;
365 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
367 static int t5_write_combine = 0;
368 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
370 static int t4_num_vis = 1;
371 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
373 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
374 static int vi_mac_funcs[] = {
377 FW_VI_FUNC_OPENISCSI,
383 struct intrs_and_queues {
384 uint16_t intr_type; /* INTx, MSI, or MSI-X */
385 uint16_t nirq; /* Total # of vectors */
386 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
387 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
388 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
389 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
390 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
391 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
392 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
393 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
394 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
395 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
396 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
398 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
399 uint16_t ntxq_vi; /* # of NIC txq's */
400 uint16_t nrxq_vi; /* # of NIC rxq's */
401 uint16_t nofldtxq_vi; /* # of TOE txq's */
402 uint16_t nofldrxq_vi; /* # of TOE rxq's */
403 uint16_t nnmtxq_vi; /* # of netmap txq's */
404 uint16_t nnmrxq_vi; /* # of netmap rxq's */
407 struct filter_entry {
408 uint32_t valid:1; /* filter allocated and valid */
409 uint32_t locked:1; /* filter is administratively locked */
410 uint32_t pending:1; /* filter action is pending firmware reply */
411 uint32_t smtidx:8; /* Source MAC Table index for smac */
412 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
414 struct t4_filter_specification fs;
417 static int map_bars_0_and_4(struct adapter *);
418 static int map_bar_2(struct adapter *);
419 static void setup_memwin(struct adapter *);
420 static void position_memwin(struct adapter *, int, uint32_t);
421 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
422 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
424 static inline int write_via_memwin(struct adapter *, int, uint32_t,
425 const uint32_t *, int);
426 static int validate_mem_range(struct adapter *, uint32_t, int);
427 static int fwmtype_to_hwmtype(int);
428 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
430 static int fixup_devlog_params(struct adapter *);
431 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
432 struct intrs_and_queues *);
433 static int prep_firmware(struct adapter *);
434 static int partition_resources(struct adapter *, const struct firmware *,
436 static int get_params__pre_init(struct adapter *);
437 static int get_params__post_init(struct adapter *);
438 static int set_params__post_init(struct adapter *);
439 static void t4_set_desc(struct adapter *);
440 static void build_medialist(struct port_info *, struct ifmedia *);
441 static int cxgbe_init_synchronized(struct vi_info *);
442 static int cxgbe_uninit_synchronized(struct vi_info *);
443 static int setup_intr_handlers(struct adapter *);
444 static void quiesce_txq(struct adapter *, struct sge_txq *);
445 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
446 static void quiesce_iq(struct adapter *, struct sge_iq *);
447 static void quiesce_fl(struct adapter *, struct sge_fl *);
448 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
449 driver_intr_t *, void *, char *);
450 static int t4_free_irq(struct adapter *, struct irq *);
451 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
452 static void vi_refresh_stats(struct adapter *, struct vi_info *);
453 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
454 static void cxgbe_tick(void *);
455 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
456 static void t4_sysctls(struct adapter *);
457 static void cxgbe_sysctls(struct port_info *);
458 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
459 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
460 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
461 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
462 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
463 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
464 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
465 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
466 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
467 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
468 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
470 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
471 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
472 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
473 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
474 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
475 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
476 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
477 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
478 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
479 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
480 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
481 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
482 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
483 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
484 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
485 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
486 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
487 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
488 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
489 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
490 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
491 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
492 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
493 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
494 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
495 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
496 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
497 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
498 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
501 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
502 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
503 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
505 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
506 static uint32_t mode_to_fconf(uint32_t);
507 static uint32_t mode_to_iconf(uint32_t);
508 static int check_fspec_against_fconf_iconf(struct adapter *,
509 struct t4_filter_specification *);
510 static int get_filter_mode(struct adapter *, uint32_t *);
511 static int set_filter_mode(struct adapter *, uint32_t);
512 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
513 static int get_filter(struct adapter *, struct t4_filter *);
514 static int set_filter(struct adapter *, struct t4_filter *);
515 static int del_filter(struct adapter *, struct t4_filter *);
516 static void clear_filter(struct filter_entry *);
517 static int set_filter_wr(struct adapter *, int);
518 static int del_filter_wr(struct adapter *, int);
519 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
521 static int get_sge_context(struct adapter *, struct t4_sge_context *);
522 static int load_fw(struct adapter *, struct t4_data *);
523 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
524 static int read_i2c(struct adapter *, struct t4_i2c_data *);
525 static int set_sched_class(struct adapter *, struct t4_sched_params *);
526 static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
528 static int toe_capability(struct vi_info *, int);
530 static int mod_event(module_t, int, void *);
531 static int notify_siblings(device_t, int);
537 {0xa000, "Chelsio Terminator 4 FPGA"},
538 {0x4400, "Chelsio T440-dbg"},
539 {0x4401, "Chelsio T420-CR"},
540 {0x4402, "Chelsio T422-CR"},
541 {0x4403, "Chelsio T440-CR"},
542 {0x4404, "Chelsio T420-BCH"},
543 {0x4405, "Chelsio T440-BCH"},
544 {0x4406, "Chelsio T440-CH"},
545 {0x4407, "Chelsio T420-SO"},
546 {0x4408, "Chelsio T420-CX"},
547 {0x4409, "Chelsio T420-BT"},
548 {0x440a, "Chelsio T404-BT"},
549 {0x440e, "Chelsio T440-LP-CR"},
551 {0xb000, "Chelsio Terminator 5 FPGA"},
552 {0x5400, "Chelsio T580-dbg"},
553 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
554 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
555 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
556 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
557 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
558 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
559 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
560 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
561 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
562 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
563 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
564 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
565 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
567 {0x5404, "Chelsio T520-BCH"},
568 {0x5405, "Chelsio T540-BCH"},
569 {0x5406, "Chelsio T540-CH"},
570 {0x5408, "Chelsio T520-CX"},
571 {0x540b, "Chelsio B520-SR"},
572 {0x540c, "Chelsio B504-BT"},
573 {0x540f, "Chelsio Amsterdam"},
574 {0x5413, "Chelsio T580-CHR"},
580 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
581 * exactly the same for both rxq and ofld_rxq.
583 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
584 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
586 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
589 t4_probe(device_t dev)
592 uint16_t v = pci_get_vendor(dev);
593 uint16_t d = pci_get_device(dev);
594 uint8_t f = pci_get_function(dev);
596 if (v != PCI_VENDOR_ID_CHELSIO)
599 /* Attach only to PF0 of the FPGA */
600 if (d == 0xa000 && f != 0)
603 for (i = 0; i < nitems(t4_pciids); i++) {
604 if (d == t4_pciids[i].device) {
605 device_set_desc(dev, t4_pciids[i].desc);
606 return (BUS_PROBE_DEFAULT);
614 t5_probe(device_t dev)
617 uint16_t v = pci_get_vendor(dev);
618 uint16_t d = pci_get_device(dev);
619 uint8_t f = pci_get_function(dev);
621 if (v != PCI_VENDOR_ID_CHELSIO)
624 /* Attach only to PF0 of the FPGA */
625 if (d == 0xb000 && f != 0)
628 for (i = 0; i < nitems(t5_pciids); i++) {
629 if (d == t5_pciids[i].device) {
630 device_set_desc(dev, t5_pciids[i].desc);
631 return (BUS_PROBE_DEFAULT);
639 t5_attribute_workaround(device_t dev)
645 * The T5 chips do not properly echo the No Snoop and Relaxed
646 * Ordering attributes when replying to a TLP from a Root
647 * Port. As a workaround, find the parent Root Port and
648 * disable No Snoop and Relaxed Ordering. Note that this
649 * affects all devices under this root port.
651 root_port = pci_find_pcie_root_port(dev);
652 if (root_port == NULL) {
653 device_printf(dev, "Unable to find parent root port\n");
657 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
658 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
659 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
661 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
662 device_get_nameunit(root_port));
666 t4_attach(device_t dev)
669 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
670 struct make_dev_args mda;
671 struct intrs_and_queues iaq;
675 int ofld_rqidx, ofld_tqidx;
678 int nm_rqidx, nm_tqidx;
682 sc = device_get_softc(dev);
684 TUNABLE_INT_FETCH("hw.cxgbe.debug_flags", &sc->debug_flags);
686 if ((pci_get_device(dev) & 0xff00) == 0x5400)
687 t5_attribute_workaround(dev);
688 pci_enable_busmaster(dev);
689 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
692 pci_set_max_read_req(dev, 4096);
693 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
694 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
695 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
697 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
700 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
701 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
703 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
704 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
705 device_get_nameunit(dev));
707 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
708 device_get_nameunit(dev));
709 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
710 sx_xlock(&t4_list_lock);
711 SLIST_INSERT_HEAD(&t4_list, sc, link);
712 sx_xunlock(&t4_list_lock);
714 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
715 TAILQ_INIT(&sc->sfl);
716 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
718 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
720 rc = map_bars_0_and_4(sc);
722 goto done; /* error message displayed already */
725 * This is the real PF# to which we're attaching. Works from within PCI
726 * passthrough environments too, where pci_get_function() could return a
727 * different PF# depending on the passthrough configuration. We need to
728 * use the real PF# in all our communication with the firmware.
730 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
733 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
735 /* Prepare the adapter for operation. */
736 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
737 rc = -t4_prep_adapter(sc, buf);
740 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
745 * Do this really early, with the memory windows set up even before the
746 * character device. The userland tool's register i/o and mem read
747 * will work even in "recovery mode".
750 if (t4_init_devlog_params(sc, 0) == 0)
751 fixup_devlog_params(sc);
752 make_dev_args_init(&mda);
753 mda.mda_devsw = &t4_cdevsw;
754 mda.mda_uid = UID_ROOT;
755 mda.mda_gid = GID_WHEEL;
757 mda.mda_si_drv1 = sc;
758 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
760 device_printf(dev, "failed to create nexus char device: %d.\n",
763 /* Go no further if recovery mode has been requested. */
764 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
765 device_printf(dev, "recovery mode.\n");
769 #if defined(__i386__)
770 if ((cpu_feature & CPUID_CX8) == 0) {
771 device_printf(dev, "64 bit atomics not available.\n");
777 /* Prepare the firmware for operation */
778 rc = prep_firmware(sc);
780 goto done; /* error message displayed already */
782 rc = get_params__post_init(sc);
784 goto done; /* error message displayed already */
786 rc = set_params__post_init(sc);
788 goto done; /* error message displayed already */
792 goto done; /* error message displayed already */
794 rc = t4_create_dma_tag(sc);
796 goto done; /* error message displayed already */
799 * Number of VIs to create per-port. The first VI is the "main" regular
800 * VI for the port. The rest are additional virtual interfaces on the
801 * same physical port. Note that the main VI does not have native
802 * netmap support but the extra VIs do.
804 * Limit the number of VIs per port to the number of available
805 * MAC addresses per port.
808 num_vis = t4_num_vis;
811 if (num_vis > nitems(vi_mac_funcs)) {
812 num_vis = nitems(vi_mac_funcs);
813 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
817 * First pass over all the ports - allocate VIs and initialize some
818 * basic parameters like mac address, port type, etc. We also figure
819 * out whether a port is 10G or 1G and use that information when
820 * calculating how many interrupts to attempt to allocate.
823 for_each_port(sc, i) {
824 struct port_info *pi;
826 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
829 /* These must be set before t4_port_init */
833 * XXX: vi[0] is special so we can't delay this allocation until
834 * pi->nvi's final value is known.
836 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
840 * Allocate the "main" VI and initialize parameters
843 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
845 device_printf(dev, "unable to initialize port %d: %d\n",
847 free(pi->vi, M_CXGBE);
853 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
854 pi->link_cfg.requested_fc |= t4_pause_settings;
855 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
856 pi->link_cfg.fc |= t4_pause_settings;
858 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
860 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
861 free(pi->vi, M_CXGBE);
867 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
868 device_get_nameunit(dev), i);
869 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
870 sc->chan_map[pi->tx_chan] = i;
872 pi->tc = malloc(sizeof(struct tx_sched_class) *
873 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
875 if (is_10G_port(pi) || is_40G_port(pi)) {
883 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
884 if (pi->dev == NULL) {
886 "failed to add device for port %d.\n", i);
890 pi->vi[0].dev = pi->dev;
891 device_set_softc(pi->dev, pi);
895 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
897 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
899 goto done; /* error message displayed already */
900 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
903 sc->intr_type = iaq.intr_type;
904 sc->intr_count = iaq.nirq;
907 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
908 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
910 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
911 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
913 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
914 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
915 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
917 if (is_offload(sc)) {
918 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
919 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
921 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
923 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
926 s->neq += s->nofldtxq + s->nofldrxq;
927 s->niq += s->nofldrxq;
929 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
930 M_CXGBE, M_ZERO | M_WAITOK);
931 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
932 M_CXGBE, M_ZERO | M_WAITOK);
937 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
938 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
940 s->neq += s->nnmtxq + s->nnmrxq;
943 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
944 M_CXGBE, M_ZERO | M_WAITOK);
945 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
946 M_CXGBE, M_ZERO | M_WAITOK);
949 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
951 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
953 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
955 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
957 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
960 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
963 t4_init_l2t(sc, M_WAITOK);
966 * Second pass over the ports. This time we know the number of rx and
967 * tx queues that each port should get.
971 ofld_rqidx = ofld_tqidx = 0;
974 nm_rqidx = nm_tqidx = 0;
976 for_each_port(sc, i) {
977 struct port_info *pi = sc->port[i];
984 for_each_vi(pi, j, vi) {
986 vi->qsize_rxq = t4_qsize_rxq;
987 vi->qsize_txq = t4_qsize_txq;
989 vi->first_rxq = rqidx;
990 vi->first_txq = tqidx;
991 if (is_10G_port(pi) || is_40G_port(pi)) {
992 vi->tmr_idx = t4_tmr_idx_10g;
993 vi->pktc_idx = t4_pktc_idx_10g;
994 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
995 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
996 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
998 vi->tmr_idx = t4_tmr_idx_1g;
999 vi->pktc_idx = t4_pktc_idx_1g;
1000 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1001 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1002 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1007 if (j == 0 && vi->ntxq > 1)
1008 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1010 vi->rsrv_noflowq = 0;
1013 vi->first_ofld_rxq = ofld_rqidx;
1014 vi->first_ofld_txq = ofld_tqidx;
1015 if (is_10G_port(pi) || is_40G_port(pi)) {
1016 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1017 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1019 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1022 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1023 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1025 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1028 ofld_rqidx += vi->nofldrxq;
1029 ofld_tqidx += vi->nofldtxq;
1033 vi->first_nm_rxq = nm_rqidx;
1034 vi->first_nm_txq = nm_tqidx;
1035 vi->nnmrxq = iaq.nnmrxq_vi;
1036 vi->nnmtxq = iaq.nnmtxq_vi;
1037 nm_rqidx += vi->nnmrxq;
1038 nm_tqidx += vi->nnmtxq;
1044 rc = setup_intr_handlers(sc);
1047 "failed to setup interrupt handlers: %d\n", rc);
1051 rc = bus_generic_attach(dev);
1054 "failed to attach all child ports: %d\n", rc);
1059 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1060 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1061 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1062 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1063 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1067 notify_siblings(dev, 0);
1070 if (rc != 0 && sc->cdev) {
1071 /* cdev was created and so cxgbetool works; recover that way. */
1073 "error during attach, adapter is now in recovery mode.\n");
1086 t4_ready(device_t dev)
1090 sc = device_get_softc(dev);
1091 if (sc->flags & FW_OK)
1097 t4_read_port_device(device_t dev, int port, device_t *child)
1100 struct port_info *pi;
1102 sc = device_get_softc(dev);
1103 if (port < 0 || port >= MAX_NPORTS)
1105 pi = sc->port[port];
1106 if (pi == NULL || pi->dev == NULL)
1113 notify_siblings(device_t dev, int detaching)
1119 for (i = 0; i < PCI_FUNCMAX; i++) {
1120 if (i == pci_get_function(dev))
1122 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1123 pci_get_slot(dev), i);
1124 if (sibling == NULL || !device_is_attached(sibling))
1127 error = T4_DETACH_CHILD(sibling);
1129 (void)T4_ATTACH_CHILD(sibling);
1140 t4_detach(device_t dev)
1143 struct port_info *pi;
1146 sc = device_get_softc(dev);
1148 rc = notify_siblings(dev, 1);
1151 "failed to detach sibling devices: %d\n", rc);
1155 if (sc->flags & FULL_INIT_DONE)
1156 t4_intr_disable(sc);
1159 destroy_dev(sc->cdev);
1163 rc = bus_generic_detach(dev);
1166 "failed to detach child devices: %d\n", rc);
1170 for (i = 0; i < sc->intr_count; i++)
1171 t4_free_irq(sc, &sc->irq[i]);
1173 for (i = 0; i < MAX_NPORTS; i++) {
1176 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1178 device_delete_child(dev, pi->dev);
1180 mtx_destroy(&pi->pi_lock);
1181 free(pi->vi, M_CXGBE);
1182 free(pi->tc, M_CXGBE);
1187 if (sc->flags & FULL_INIT_DONE)
1188 adapter_full_uninit(sc);
1190 if (sc->flags & FW_OK)
1191 t4_fw_bye(sc, sc->mbox);
1193 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1194 pci_release_msi(dev);
1197 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1201 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1205 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1209 t4_free_l2t(sc->l2t);
1212 free(sc->sge.ofld_rxq, M_CXGBE);
1213 free(sc->sge.ofld_txq, M_CXGBE);
1216 free(sc->sge.nm_rxq, M_CXGBE);
1217 free(sc->sge.nm_txq, M_CXGBE);
1219 free(sc->irq, M_CXGBE);
1220 free(sc->sge.rxq, M_CXGBE);
1221 free(sc->sge.txq, M_CXGBE);
1222 free(sc->sge.ctrlq, M_CXGBE);
1223 free(sc->sge.iqmap, M_CXGBE);
1224 free(sc->sge.eqmap, M_CXGBE);
1225 free(sc->tids.ftid_tab, M_CXGBE);
1226 t4_destroy_dma_tag(sc);
1227 if (mtx_initialized(&sc->sc_lock)) {
1228 sx_xlock(&t4_list_lock);
1229 SLIST_REMOVE(&t4_list, sc, adapter, link);
1230 sx_xunlock(&t4_list_lock);
1231 mtx_destroy(&sc->sc_lock);
1234 callout_drain(&sc->sfl_callout);
1235 if (mtx_initialized(&sc->tids.ftid_lock))
1236 mtx_destroy(&sc->tids.ftid_lock);
1237 if (mtx_initialized(&sc->sfl_lock))
1238 mtx_destroy(&sc->sfl_lock);
1239 if (mtx_initialized(&sc->ifp_lock))
1240 mtx_destroy(&sc->ifp_lock);
1241 if (mtx_initialized(&sc->reg_lock))
1242 mtx_destroy(&sc->reg_lock);
1244 for (i = 0; i < NUM_MEMWIN; i++) {
1245 struct memwin *mw = &sc->memwin[i];
1247 if (rw_initialized(&mw->mw_lock))
1248 rw_destroy(&mw->mw_lock);
1251 bzero(sc, sizeof(*sc));
1257 cxgbe_probe(device_t dev)
1260 struct port_info *pi = device_get_softc(dev);
1262 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1263 device_set_desc_copy(dev, buf);
1265 return (BUS_PROBE_DEFAULT);
1268 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1269 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1270 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1271 #define T4_CAP_ENABLE (T4_CAP)
1274 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1279 vi->xact_addr_filt = -1;
1280 callout_init(&vi->tick, 1);
1282 /* Allocate an ifnet and set it up */
1283 ifp = if_alloc(IFT_ETHER);
1285 device_printf(dev, "Cannot allocate ifnet\n");
1291 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1294 ifp->if_init = cxgbe_init;
1295 ifp->if_ioctl = cxgbe_ioctl;
1296 ifp->if_transmit = cxgbe_transmit;
1297 ifp->if_qflush = cxgbe_qflush;
1298 ifp->if_get_counter = cxgbe_get_counter;
1300 ifp->if_capabilities = T4_CAP;
1302 if (vi->nofldrxq != 0)
1303 ifp->if_capabilities |= IFCAP_TOE;
1305 ifp->if_capenable = T4_CAP_ENABLE;
1306 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1307 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1309 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1310 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1311 ifp->if_hw_tsomaxsegsize = 65536;
1313 /* Initialize ifmedia for this VI */
1314 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1315 cxgbe_media_status);
1316 build_medialist(vi->pi, &vi->media);
1318 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1319 EVENTHANDLER_PRI_ANY);
1321 ether_ifattach(ifp, vi->hw_addr);
1323 if (vi->nnmrxq != 0)
1324 cxgbe_nm_attach(vi);
1326 sb = sbuf_new_auto();
1327 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1329 if (ifp->if_capabilities & IFCAP_TOE)
1330 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1331 vi->nofldtxq, vi->nofldrxq);
1334 if (ifp->if_capabilities & IFCAP_NETMAP)
1335 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1336 vi->nnmtxq, vi->nnmrxq);
1339 device_printf(dev, "%s\n", sbuf_data(sb));
1348 cxgbe_attach(device_t dev)
1350 struct port_info *pi = device_get_softc(dev);
1354 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1356 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1360 for_each_vi(pi, i, vi) {
1363 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1364 "vcxgbe" : "vcxl", -1);
1365 if (vi->dev == NULL) {
1366 device_printf(dev, "failed to add VI %d\n", i);
1369 device_set_softc(vi->dev, vi);
1374 bus_generic_attach(dev);
1380 cxgbe_vi_detach(struct vi_info *vi)
1382 struct ifnet *ifp = vi->ifp;
1384 ether_ifdetach(ifp);
1387 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1389 /* Let detach proceed even if these fail. */
1391 if (ifp->if_capabilities & IFCAP_NETMAP)
1392 cxgbe_nm_detach(vi);
1394 cxgbe_uninit_synchronized(vi);
1395 callout_drain(&vi->tick);
1398 ifmedia_removeall(&vi->media);
1404 cxgbe_detach(device_t dev)
1406 struct port_info *pi = device_get_softc(dev);
1407 struct adapter *sc = pi->adapter;
1410 /* Detach the extra VIs first. */
1411 rc = bus_generic_detach(dev);
1414 device_delete_children(dev);
1416 doom_vi(sc, &pi->vi[0]);
1418 if (pi->flags & HAS_TRACEQ) {
1419 sc->traceq = -1; /* cloner should not create ifnet */
1420 t4_tracer_port_detach(sc);
1423 cxgbe_vi_detach(&pi->vi[0]);
1424 callout_drain(&pi->tick);
1426 end_synchronized_op(sc, 0);
1432 cxgbe_init(void *arg)
1434 struct vi_info *vi = arg;
1435 struct adapter *sc = vi->pi->adapter;
1437 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1439 cxgbe_init_synchronized(vi);
1440 end_synchronized_op(sc, 0);
1444 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1446 int rc = 0, mtu, flags, can_sleep;
1447 struct vi_info *vi = ifp->if_softc;
1448 struct adapter *sc = vi->pi->adapter;
1449 struct ifreq *ifr = (struct ifreq *)data;
1455 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1458 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1462 if (vi->flags & VI_INIT_DONE) {
1463 t4_update_fl_bufsize(ifp);
1464 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1465 rc = update_mac_settings(ifp, XGMAC_MTU);
1467 end_synchronized_op(sc, 0);
1473 rc = begin_synchronized_op(sc, vi,
1474 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1478 if (ifp->if_flags & IFF_UP) {
1479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1480 flags = vi->if_flags;
1481 if ((ifp->if_flags ^ flags) &
1482 (IFF_PROMISC | IFF_ALLMULTI)) {
1483 if (can_sleep == 1) {
1484 end_synchronized_op(sc, 0);
1488 rc = update_mac_settings(ifp,
1489 XGMAC_PROMISC | XGMAC_ALLMULTI);
1492 if (can_sleep == 0) {
1493 end_synchronized_op(sc, LOCK_HELD);
1497 rc = cxgbe_init_synchronized(vi);
1499 vi->if_flags = ifp->if_flags;
1500 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1501 if (can_sleep == 0) {
1502 end_synchronized_op(sc, LOCK_HELD);
1506 rc = cxgbe_uninit_synchronized(vi);
1508 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1512 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1513 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1516 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1517 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1518 end_synchronized_op(sc, LOCK_HELD);
1522 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1526 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1527 if (mask & IFCAP_TXCSUM) {
1528 ifp->if_capenable ^= IFCAP_TXCSUM;
1529 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1531 if (IFCAP_TSO4 & ifp->if_capenable &&
1532 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1533 ifp->if_capenable &= ~IFCAP_TSO4;
1535 "tso4 disabled due to -txcsum.\n");
1538 if (mask & IFCAP_TXCSUM_IPV6) {
1539 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1540 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1542 if (IFCAP_TSO6 & ifp->if_capenable &&
1543 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1544 ifp->if_capenable &= ~IFCAP_TSO6;
1546 "tso6 disabled due to -txcsum6.\n");
1549 if (mask & IFCAP_RXCSUM)
1550 ifp->if_capenable ^= IFCAP_RXCSUM;
1551 if (mask & IFCAP_RXCSUM_IPV6)
1552 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1555 * Note that we leave CSUM_TSO alone (it is always set). The
1556 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1557 * sending a TSO request our way, so it's sufficient to toggle
1560 if (mask & IFCAP_TSO4) {
1561 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1562 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1563 if_printf(ifp, "enable txcsum first.\n");
1567 ifp->if_capenable ^= IFCAP_TSO4;
1569 if (mask & IFCAP_TSO6) {
1570 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1571 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1572 if_printf(ifp, "enable txcsum6 first.\n");
1576 ifp->if_capenable ^= IFCAP_TSO6;
1578 if (mask & IFCAP_LRO) {
1579 #if defined(INET) || defined(INET6)
1581 struct sge_rxq *rxq;
1583 ifp->if_capenable ^= IFCAP_LRO;
1584 for_each_rxq(vi, i, rxq) {
1585 if (ifp->if_capenable & IFCAP_LRO)
1586 rxq->iq.flags |= IQ_LRO_ENABLED;
1588 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1593 if (mask & IFCAP_TOE) {
1594 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1596 rc = toe_capability(vi, enable);
1600 ifp->if_capenable ^= mask;
1603 if (mask & IFCAP_VLAN_HWTAGGING) {
1604 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1605 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1606 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1608 if (mask & IFCAP_VLAN_MTU) {
1609 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1611 /* Need to find out how to disable auto-mtu-inflation */
1613 if (mask & IFCAP_VLAN_HWTSO)
1614 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1615 if (mask & IFCAP_VLAN_HWCSUM)
1616 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1618 #ifdef VLAN_CAPABILITIES
1619 VLAN_CAPABILITIES(ifp);
1622 end_synchronized_op(sc, 0);
1627 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1631 struct ifi2creq i2c;
1633 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1636 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1640 if (i2c.len > sizeof(i2c.data)) {
1644 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1647 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1648 i2c.offset, i2c.len, &i2c.data[0]);
1649 end_synchronized_op(sc, 0);
1651 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1656 rc = ether_ioctl(ifp, cmd, data);
1663 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1665 struct vi_info *vi = ifp->if_softc;
1666 struct port_info *pi = vi->pi;
1667 struct adapter *sc = pi->adapter;
1668 struct sge_txq *txq;
1673 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1675 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1681 if (__predict_false(rc != 0)) {
1682 MPASS(m == NULL); /* was freed already */
1683 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1688 txq = &sc->sge.txq[vi->first_txq];
1689 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1690 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1694 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1695 if (__predict_false(rc != 0))
1702 cxgbe_qflush(struct ifnet *ifp)
1704 struct vi_info *vi = ifp->if_softc;
1705 struct sge_txq *txq;
1708 /* queues do not exist if !VI_INIT_DONE. */
1709 if (vi->flags & VI_INIT_DONE) {
1710 for_each_txq(vi, i, txq) {
1712 txq->eq.flags &= ~EQ_ENABLED;
1714 while (!mp_ring_is_idle(txq->r)) {
1715 mp_ring_check_drainage(txq->r, 0);
1724 vi_get_counter(struct ifnet *ifp, ift_counter c)
1726 struct vi_info *vi = ifp->if_softc;
1727 struct fw_vi_stats_vf *s = &vi->stats;
1729 vi_refresh_stats(vi->pi->adapter, vi);
1732 case IFCOUNTER_IPACKETS:
1733 return (s->rx_bcast_frames + s->rx_mcast_frames +
1734 s->rx_ucast_frames);
1735 case IFCOUNTER_IERRORS:
1736 return (s->rx_err_frames);
1737 case IFCOUNTER_OPACKETS:
1738 return (s->tx_bcast_frames + s->tx_mcast_frames +
1739 s->tx_ucast_frames + s->tx_offload_frames);
1740 case IFCOUNTER_OERRORS:
1741 return (s->tx_drop_frames);
1742 case IFCOUNTER_IBYTES:
1743 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
1745 case IFCOUNTER_OBYTES:
1746 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
1747 s->tx_ucast_bytes + s->tx_offload_bytes);
1748 case IFCOUNTER_IMCASTS:
1749 return (s->rx_mcast_frames);
1750 case IFCOUNTER_OMCASTS:
1751 return (s->tx_mcast_frames);
1752 case IFCOUNTER_OQDROPS: {
1756 if (vi->flags & VI_INIT_DONE) {
1758 struct sge_txq *txq;
1760 for_each_txq(vi, i, txq)
1761 drops += counter_u64_fetch(txq->r->drops);
1769 return (if_get_counter_default(ifp, c));
1774 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
1776 struct vi_info *vi = ifp->if_softc;
1777 struct port_info *pi = vi->pi;
1778 struct adapter *sc = pi->adapter;
1779 struct port_stats *s = &pi->stats;
1782 return (vi_get_counter(ifp, c));
1784 cxgbe_refresh_stats(sc, pi);
1787 case IFCOUNTER_IPACKETS:
1788 return (s->rx_frames);
1790 case IFCOUNTER_IERRORS:
1791 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
1792 s->rx_fcs_err + s->rx_len_err);
1794 case IFCOUNTER_OPACKETS:
1795 return (s->tx_frames);
1797 case IFCOUNTER_OERRORS:
1798 return (s->tx_error_frames);
1800 case IFCOUNTER_IBYTES:
1801 return (s->rx_octets);
1803 case IFCOUNTER_OBYTES:
1804 return (s->tx_octets);
1806 case IFCOUNTER_IMCASTS:
1807 return (s->rx_mcast_frames);
1809 case IFCOUNTER_OMCASTS:
1810 return (s->tx_mcast_frames);
1812 case IFCOUNTER_IQDROPS:
1813 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
1814 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
1815 s->rx_trunc3 + pi->tnl_cong_drops);
1817 case IFCOUNTER_OQDROPS: {
1821 if (vi->flags & VI_INIT_DONE) {
1823 struct sge_txq *txq;
1825 for_each_txq(vi, i, txq)
1826 drops += counter_u64_fetch(txq->r->drops);
1834 return (if_get_counter_default(ifp, c));
1839 cxgbe_media_change(struct ifnet *ifp)
1841 struct vi_info *vi = ifp->if_softc;
1843 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1845 return (EOPNOTSUPP);
1849 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1851 struct vi_info *vi = ifp->if_softc;
1852 struct port_info *pi = vi->pi;
1853 struct ifmedia_entry *cur;
1854 int speed = pi->link_cfg.speed;
1856 cur = vi->media.ifm_cur;
1858 ifmr->ifm_status = IFM_AVALID;
1859 if (!pi->link_cfg.link_ok)
1862 ifmr->ifm_status |= IFM_ACTIVE;
1864 /* active and current will differ iff current media is autoselect. */
1865 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1868 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1870 ifmr->ifm_active |= IFM_10G_T;
1871 else if (speed == 1000)
1872 ifmr->ifm_active |= IFM_1000_T;
1873 else if (speed == 100)
1874 ifmr->ifm_active |= IFM_100_TX;
1875 else if (speed == 10)
1876 ifmr->ifm_active |= IFM_10_T;
1878 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1883 vcxgbe_probe(device_t dev)
1886 struct vi_info *vi = device_get_softc(dev);
1888 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1890 device_set_desc_copy(dev, buf);
1892 return (BUS_PROBE_DEFAULT);
1896 vcxgbe_attach(device_t dev)
1899 struct port_info *pi;
1901 int func, index, rc;
1904 vi = device_get_softc(dev);
1908 index = vi - pi->vi;
1909 KASSERT(index < nitems(vi_mac_funcs),
1910 ("%s: VI %s doesn't have a MAC func", __func__,
1911 device_get_nameunit(dev)));
1912 func = vi_mac_funcs[index];
1913 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1914 vi->hw_addr, &vi->rss_size, func, 0);
1916 device_printf(dev, "Failed to allocate virtual interface "
1917 "for port %d: %d\n", pi->port_id, -rc);
1922 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1923 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1924 V_FW_PARAMS_PARAM_YZ(vi->viid);
1925 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1927 vi->rss_base = 0xffff;
1929 /* MPASS((val >> 16) == rss_size); */
1930 vi->rss_base = val & 0xffff;
1933 rc = cxgbe_vi_attach(dev, vi);
1935 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1942 vcxgbe_detach(device_t dev)
1947 vi = device_get_softc(dev);
1948 sc = vi->pi->adapter;
1952 cxgbe_vi_detach(vi);
1953 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1955 end_synchronized_op(sc, 0);
1961 t4_fatal_err(struct adapter *sc)
1963 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1964 t4_intr_disable(sc);
1965 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1966 device_get_nameunit(sc->dev));
1970 map_bars_0_and_4(struct adapter *sc)
1972 sc->regs_rid = PCIR_BAR(0);
1973 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1974 &sc->regs_rid, RF_ACTIVE);
1975 if (sc->regs_res == NULL) {
1976 device_printf(sc->dev, "cannot map registers.\n");
1979 sc->bt = rman_get_bustag(sc->regs_res);
1980 sc->bh = rman_get_bushandle(sc->regs_res);
1981 sc->mmio_len = rman_get_size(sc->regs_res);
1982 setbit(&sc->doorbells, DOORBELL_KDB);
1984 sc->msix_rid = PCIR_BAR(4);
1985 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1986 &sc->msix_rid, RF_ACTIVE);
1987 if (sc->msix_res == NULL) {
1988 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1996 map_bar_2(struct adapter *sc)
2000 * T4: only iWARP driver uses the userspace doorbells. There is no need
2001 * to map it if RDMA is disabled.
2003 if (is_t4(sc) && sc->rdmacaps == 0)
2006 sc->udbs_rid = PCIR_BAR(2);
2007 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2008 &sc->udbs_rid, RF_ACTIVE);
2009 if (sc->udbs_res == NULL) {
2010 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2013 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2016 setbit(&sc->doorbells, DOORBELL_UDB);
2017 #if defined(__i386__) || defined(__amd64__)
2018 if (t5_write_combine) {
2022 * Enable write combining on BAR2. This is the
2023 * userspace doorbell BAR and is split into 128B
2024 * (UDBS_SEG_SIZE) doorbell regions, each associated
2025 * with an egress queue. The first 64B has the doorbell
2026 * and the second 64B can be used to submit a tx work
2027 * request with an implicit doorbell.
2030 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2031 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2033 clrbit(&sc->doorbells, DOORBELL_UDB);
2034 setbit(&sc->doorbells, DOORBELL_WCWR);
2035 setbit(&sc->doorbells, DOORBELL_UDBWC);
2037 device_printf(sc->dev,
2038 "couldn't enable write combining: %d\n",
2042 t4_write_reg(sc, A_SGE_STAT_CFG,
2043 V_STATSOURCE_T5(7) | V_STATMODE(0));
2051 struct memwin_init {
2056 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2057 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2058 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2059 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2062 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2063 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2064 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2065 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2069 setup_memwin(struct adapter *sc)
2071 const struct memwin_init *mw_init;
2078 * Read low 32b of bar0 indirectly via the hardware backdoor
2079 * mechanism. Works from within PCI passthrough environments
2080 * too, where rman_get_start() can return a different value. We
2081 * need to program the T4 memory window decoders with the actual
2082 * addresses that will be coming across the PCIe link.
2084 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2085 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2087 mw_init = &t4_memwin[0];
2089 /* T5+ use the relative offset inside the PCIe BAR */
2092 mw_init = &t5_memwin[0];
2095 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2096 rw_init(&mw->mw_lock, "memory window access");
2097 mw->mw_base = mw_init->base;
2098 mw->mw_aperture = mw_init->aperture;
2101 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2102 (mw->mw_base + bar0) | V_BIR(0) |
2103 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2104 rw_wlock(&mw->mw_lock);
2105 position_memwin(sc, i, 0);
2106 rw_wunlock(&mw->mw_lock);
2110 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2114 * Positions the memory window at the given address in the card's address space.
2115 * There are some alignment requirements and the actual position may be at an
2116 * address prior to the requested address. mw->mw_curpos always has the actual
2117 * position of the window.
2120 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2126 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2127 mw = &sc->memwin[idx];
2128 rw_assert(&mw->mw_lock, RA_WLOCKED);
2132 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2134 pf = V_PFNUM(sc->pf);
2135 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2137 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2138 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2139 t4_read_reg(sc, reg); /* flush */
2143 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2149 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2151 /* Memory can only be accessed in naturally aligned 4 byte units */
2152 if (addr & 3 || len & 3 || len <= 0)
2155 mw = &sc->memwin[idx];
2157 rw_rlock(&mw->mw_lock);
2158 mw_end = mw->mw_curpos + mw->mw_aperture;
2159 if (addr >= mw_end || addr < mw->mw_curpos) {
2160 /* Will need to reposition the window */
2161 if (!rw_try_upgrade(&mw->mw_lock)) {
2162 rw_runlock(&mw->mw_lock);
2163 rw_wlock(&mw->mw_lock);
2165 rw_assert(&mw->mw_lock, RA_WLOCKED);
2166 position_memwin(sc, idx, addr);
2167 rw_downgrade(&mw->mw_lock);
2168 mw_end = mw->mw_curpos + mw->mw_aperture;
2170 rw_assert(&mw->mw_lock, RA_RLOCKED);
2171 while (addr < mw_end && len > 0) {
2173 v = t4_read_reg(sc, mw->mw_base + addr -
2175 *val++ = le32toh(v);
2178 t4_write_reg(sc, mw->mw_base + addr -
2179 mw->mw_curpos, htole32(v));
2184 rw_runlock(&mw->mw_lock);
2191 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2195 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2199 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2200 const uint32_t *val, int len)
2203 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2207 t4_range_cmp(const void *a, const void *b)
2209 return ((const struct t4_range *)a)->start -
2210 ((const struct t4_range *)b)->start;
2214 * Verify that the memory range specified by the addr/len pair is valid within
2215 * the card's address space.
2218 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2220 struct t4_range mem_ranges[4], *r, *next;
2221 uint32_t em, addr_len;
2222 int i, n, remaining;
2224 /* Memory can only be accessed in naturally aligned 4 byte units */
2225 if (addr & 3 || len & 3 || len <= 0)
2228 /* Enabled memories */
2229 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2233 bzero(r, sizeof(mem_ranges));
2234 if (em & F_EDRAM0_ENABLE) {
2235 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2236 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2238 r->start = G_EDRAM0_BASE(addr_len) << 20;
2239 if (addr >= r->start &&
2240 addr + len <= r->start + r->size)
2246 if (em & F_EDRAM1_ENABLE) {
2247 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2248 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2250 r->start = G_EDRAM1_BASE(addr_len) << 20;
2251 if (addr >= r->start &&
2252 addr + len <= r->start + r->size)
2258 if (em & F_EXT_MEM_ENABLE) {
2259 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2260 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2262 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2263 if (addr >= r->start &&
2264 addr + len <= r->start + r->size)
2270 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2271 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2272 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2274 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2275 if (addr >= r->start &&
2276 addr + len <= r->start + r->size)
2282 MPASS(n <= nitems(mem_ranges));
2285 /* Sort and merge the ranges. */
2286 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2288 /* Start from index 0 and examine the next n - 1 entries. */
2290 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2292 MPASS(r->size > 0); /* r is a valid entry. */
2294 MPASS(next->size > 0); /* and so is the next one. */
2296 while (r->start + r->size >= next->start) {
2297 /* Merge the next one into the current entry. */
2298 r->size = max(r->start + r->size,
2299 next->start + next->size) - r->start;
2300 n--; /* One fewer entry in total. */
2301 if (--remaining == 0)
2302 goto done; /* short circuit */
2305 if (next != r + 1) {
2307 * Some entries were merged into r and next
2308 * points to the first valid entry that couldn't
2311 MPASS(next->size > 0); /* must be valid */
2312 memcpy(r + 1, next, remaining * sizeof(*r));
2315 * This so that the foo->size assertion in the
2316 * next iteration of the loop do the right
2317 * thing for entries that were pulled up and are
2320 MPASS(n < nitems(mem_ranges));
2321 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2322 sizeof(struct t4_range));
2327 /* Done merging the ranges. */
2330 for (i = 0; i < n; i++, r++) {
2331 if (addr >= r->start &&
2332 addr + len <= r->start + r->size)
2341 fwmtype_to_hwmtype(int mtype)
2345 case FW_MEMTYPE_EDC0:
2347 case FW_MEMTYPE_EDC1:
2349 case FW_MEMTYPE_EXTMEM:
2351 case FW_MEMTYPE_EXTMEM1:
2354 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2359 * Verify that the memory range specified by the memtype/offset/len pair is
2360 * valid and lies entirely within the memtype specified. The global address of
2361 * the start of the range is returned in addr.
2364 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2367 uint32_t em, addr_len, maddr;
2369 /* Memory can only be accessed in naturally aligned 4 byte units */
2370 if (off & 3 || len & 3 || len == 0)
2373 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2374 switch (fwmtype_to_hwmtype(mtype)) {
2376 if (!(em & F_EDRAM0_ENABLE))
2378 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2379 maddr = G_EDRAM0_BASE(addr_len) << 20;
2382 if (!(em & F_EDRAM1_ENABLE))
2384 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2385 maddr = G_EDRAM1_BASE(addr_len) << 20;
2388 if (!(em & F_EXT_MEM_ENABLE))
2390 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2391 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2394 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2396 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2397 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2403 *addr = maddr + off; /* global address */
2404 return (validate_mem_range(sc, *addr, len));
2408 fixup_devlog_params(struct adapter *sc)
2410 struct devlog_params *dparams = &sc->params.devlog;
2413 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2414 dparams->size, &dparams->addr);
2420 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2421 struct intrs_and_queues *iaq)
2423 int rc, itype, navail, nrxq10g, nrxq1g, n;
2424 int nofldrxq10g = 0, nofldrxq1g = 0;
2426 bzero(iaq, sizeof(*iaq));
2428 iaq->ntxq10g = t4_ntxq10g;
2429 iaq->ntxq1g = t4_ntxq1g;
2430 iaq->ntxq_vi = t4_ntxq_vi;
2431 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2432 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2433 iaq->nrxq_vi = t4_nrxq_vi;
2434 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2436 if (is_offload(sc)) {
2437 iaq->nofldtxq10g = t4_nofldtxq10g;
2438 iaq->nofldtxq1g = t4_nofldtxq1g;
2439 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2440 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2441 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2442 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2446 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2447 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2450 for (itype = INTR_MSIX; itype; itype >>= 1) {
2452 if ((itype & t4_intr_types) == 0)
2453 continue; /* not allowed */
2455 if (itype == INTR_MSIX)
2456 navail = pci_msix_count(sc->dev);
2457 else if (itype == INTR_MSI)
2458 navail = pci_msi_count(sc->dev);
2465 iaq->intr_type = itype;
2466 iaq->intr_flags_10g = 0;
2467 iaq->intr_flags_1g = 0;
2470 * Best option: an interrupt vector for errors, one for the
2471 * firmware event queue, and one for every rxq (NIC and TOE) of
2472 * every VI. The VIs that support netmap use the same
2473 * interrupts for the NIC rx queues and the netmap rx queues
2474 * because only one set of queues is active at a time.
2476 iaq->nirq = T4_EXTRA_INTR;
2477 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2478 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2479 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2480 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2481 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2482 if (iaq->nirq <= navail &&
2483 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2484 iaq->intr_flags_10g = INTR_ALL;
2485 iaq->intr_flags_1g = INTR_ALL;
2489 /* Disable the VIs (and netmap) if there aren't enough intrs */
2491 device_printf(sc->dev, "virtual interfaces disabled "
2492 "because num_vis=%u with current settings "
2493 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2494 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2495 "nnmrxq_vi=%u) would need %u interrupts but "
2496 "only %u are available.\n", num_vis, nrxq10g,
2497 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2498 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2501 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2502 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2503 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2508 * Second best option: a vector for errors, one for the firmware
2509 * event queue, and vectors for either all the NIC rx queues or
2510 * all the TOE rx queues. The queues that don't get vectors
2511 * will forward their interrupts to those that do.
2513 iaq->nirq = T4_EXTRA_INTR;
2514 if (nrxq10g >= nofldrxq10g) {
2515 iaq->intr_flags_10g = INTR_RXQ;
2516 iaq->nirq += n10g * nrxq10g;
2518 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2519 iaq->nirq += n10g * nofldrxq10g;
2521 if (nrxq1g >= nofldrxq1g) {
2522 iaq->intr_flags_1g = INTR_RXQ;
2523 iaq->nirq += n1g * nrxq1g;
2525 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2526 iaq->nirq += n1g * nofldrxq1g;
2528 if (iaq->nirq <= navail &&
2529 (itype != INTR_MSI || powerof2(iaq->nirq)))
2533 * Next best option: an interrupt vector for errors, one for the
2534 * firmware event queue, and at least one per main-VI. At this
2535 * point we know we'll have to downsize nrxq and/or nofldrxq to
2536 * fit what's available to us.
2538 iaq->nirq = T4_EXTRA_INTR;
2539 iaq->nirq += n10g + n1g;
2540 if (iaq->nirq <= navail) {
2541 int leftover = navail - iaq->nirq;
2544 int target = max(nrxq10g, nofldrxq10g);
2546 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2547 INTR_RXQ : INTR_OFLD_RXQ;
2550 while (n < target && leftover >= n10g) {
2555 iaq->nrxq10g = min(n, nrxq10g);
2557 iaq->nofldrxq10g = min(n, nofldrxq10g);
2562 int target = max(nrxq1g, nofldrxq1g);
2564 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2565 INTR_RXQ : INTR_OFLD_RXQ;
2568 while (n < target && leftover >= n1g) {
2573 iaq->nrxq1g = min(n, nrxq1g);
2575 iaq->nofldrxq1g = min(n, nofldrxq1g);
2579 if (itype != INTR_MSI || powerof2(iaq->nirq))
2584 * Least desirable option: one interrupt vector for everything.
2586 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2587 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2590 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2595 if (itype == INTR_MSIX)
2596 rc = pci_alloc_msix(sc->dev, &navail);
2597 else if (itype == INTR_MSI)
2598 rc = pci_alloc_msi(sc->dev, &navail);
2601 if (navail == iaq->nirq)
2605 * Didn't get the number requested. Use whatever number
2606 * the kernel is willing to allocate (it's in navail).
2608 device_printf(sc->dev, "fewer vectors than requested, "
2609 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2610 itype, iaq->nirq, navail);
2611 pci_release_msi(sc->dev);
2615 device_printf(sc->dev,
2616 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2617 itype, rc, iaq->nirq, navail);
2620 device_printf(sc->dev,
2621 "failed to find a usable interrupt type. "
2622 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2623 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2628 #define FW_VERSION(chip) ( \
2629 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2630 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2631 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2632 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2633 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2639 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2643 .kld_name = "t4fw_cfg",
2644 .fw_mod_name = "t4fw",
2646 .chip = FW_HDR_CHIP_T4,
2647 .fw_ver = htobe32_const(FW_VERSION(T4)),
2648 .intfver_nic = FW_INTFVER(T4, NIC),
2649 .intfver_vnic = FW_INTFVER(T4, VNIC),
2650 .intfver_ofld = FW_INTFVER(T4, OFLD),
2651 .intfver_ri = FW_INTFVER(T4, RI),
2652 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2653 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2654 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2655 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2659 .kld_name = "t5fw_cfg",
2660 .fw_mod_name = "t5fw",
2662 .chip = FW_HDR_CHIP_T5,
2663 .fw_ver = htobe32_const(FW_VERSION(T5)),
2664 .intfver_nic = FW_INTFVER(T5, NIC),
2665 .intfver_vnic = FW_INTFVER(T5, VNIC),
2666 .intfver_ofld = FW_INTFVER(T5, OFLD),
2667 .intfver_ri = FW_INTFVER(T5, RI),
2668 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2669 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2670 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2671 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2676 static struct fw_info *
2677 find_fw_info(int chip)
2681 for (i = 0; i < nitems(fw_info); i++) {
2682 if (fw_info[i].chip == chip)
2683 return (&fw_info[i]);
2689 * Is the given firmware API compatible with the one the driver was compiled
2693 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2696 /* short circuit if it's the exact same firmware version */
2697 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2701 * XXX: Is this too conservative? Perhaps I should limit this to the
2702 * features that are supported in the driver.
2704 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2705 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2706 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2707 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2715 * The firmware in the KLD is usable, but should it be installed? This routine
2716 * explains itself in detail if it indicates the KLD firmware should be
2720 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2724 if (!card_fw_usable) {
2725 reason = "incompatible or unusable";
2730 reason = "older than the version bundled with this driver";
2734 if (t4_fw_install == 2 && k != c) {
2735 reason = "different than the version bundled with this driver";
2742 if (t4_fw_install == 0) {
2743 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2744 "but the driver is prohibited from installing a different "
2745 "firmware on the card.\n",
2746 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2747 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2752 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2753 "installing firmware %u.%u.%u.%u on card.\n",
2754 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2755 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2756 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2757 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2762 * Establish contact with the firmware and determine if we are the master driver
2763 * or not, and whether we are responsible for chip initialization.
2766 prep_firmware(struct adapter *sc)
2768 const struct firmware *fw = NULL, *default_cfg;
2769 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2770 enum dev_state state;
2771 struct fw_info *fw_info;
2772 struct fw_hdr *card_fw; /* fw on the card */
2773 const struct fw_hdr *kld_fw; /* fw in the KLD */
2774 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2777 /* Contact firmware. */
2778 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2779 if (rc < 0 || state == DEV_STATE_ERR) {
2781 device_printf(sc->dev,
2782 "failed to connect to the firmware: %d, %d.\n", rc, state);
2787 sc->flags |= MASTER_PF;
2788 else if (state == DEV_STATE_UNINIT) {
2790 * We didn't get to be the master so we definitely won't be
2791 * configuring the chip. It's a bug if someone else hasn't
2792 * configured it already.
2794 device_printf(sc->dev, "couldn't be master(%d), "
2795 "device not already initialized either(%d).\n", rc, state);
2799 /* This is the firmware whose headers the driver was compiled against */
2800 fw_info = find_fw_info(chip_id(sc));
2801 if (fw_info == NULL) {
2802 device_printf(sc->dev,
2803 "unable to look up firmware information for chip %d.\n",
2807 drv_fw = &fw_info->fw_hdr;
2810 * The firmware KLD contains many modules. The KLD name is also the
2811 * name of the module that contains the default config file.
2813 default_cfg = firmware_get(fw_info->kld_name);
2815 /* Read the header of the firmware on the card */
2816 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2817 rc = -t4_read_flash(sc, FLASH_FW_START,
2818 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2820 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2822 device_printf(sc->dev,
2823 "Unable to read card's firmware header: %d\n", rc);
2827 /* This is the firmware in the KLD */
2828 fw = firmware_get(fw_info->fw_mod_name);
2830 kld_fw = (const void *)fw->data;
2831 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2837 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2838 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2840 * Common case: the firmware on the card is an exact match and
2841 * the KLD is an exact match too, or the KLD is
2842 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2843 * here -- use cxgbetool loadfw if you want to reinstall the
2844 * same firmware as the one on the card.
2846 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2847 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2848 be32toh(card_fw->fw_ver))) {
2850 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2852 device_printf(sc->dev,
2853 "failed to install firmware: %d\n", rc);
2857 /* Installed successfully, update the cached header too. */
2858 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2860 need_fw_reset = 0; /* already reset as part of load_fw */
2863 if (!card_fw_usable) {
2866 d = ntohl(drv_fw->fw_ver);
2867 c = ntohl(card_fw->fw_ver);
2868 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2870 device_printf(sc->dev, "Cannot find a usable firmware: "
2871 "fw_install %d, chip state %d, "
2872 "driver compiled with %d.%d.%d.%d, "
2873 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2874 t4_fw_install, state,
2875 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2876 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2877 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2878 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2879 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2880 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2885 /* We're using whatever's on the card and it's known to be good. */
2886 sc->params.fw_vers = ntohl(card_fw->fw_ver);
2887 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2888 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2889 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2890 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2891 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2893 t4_get_tp_version(sc, &sc->params.tp_vers);
2894 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
2895 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
2896 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
2897 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
2898 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
2900 if (t4_get_exprom_version(sc, &sc->params.exprom_vers) != 0)
2901 sc->params.exprom_vers = 0;
2903 snprintf(sc->exprom_version, sizeof(sc->exprom_version),
2905 G_FW_HDR_FW_VER_MAJOR(sc->params.exprom_vers),
2906 G_FW_HDR_FW_VER_MINOR(sc->params.exprom_vers),
2907 G_FW_HDR_FW_VER_MICRO(sc->params.exprom_vers),
2908 G_FW_HDR_FW_VER_BUILD(sc->params.exprom_vers));
2912 if (need_fw_reset &&
2913 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2914 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2915 if (rc != ETIMEDOUT && rc != EIO)
2916 t4_fw_bye(sc, sc->mbox);
2921 rc = get_params__pre_init(sc);
2923 goto done; /* error message displayed already */
2925 /* Partition adapter resources as specified in the config file. */
2926 if (state == DEV_STATE_UNINIT) {
2928 KASSERT(sc->flags & MASTER_PF,
2929 ("%s: trying to change chip settings when not master.",
2932 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2934 goto done; /* error message displayed already */
2936 t4_tweak_chip_settings(sc);
2938 /* get basic stuff going */
2939 rc = -t4_fw_initialize(sc, sc->mbox);
2941 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2945 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2950 free(card_fw, M_CXGBE);
2952 firmware_put(fw, FIRMWARE_UNLOAD);
2953 if (default_cfg != NULL)
2954 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2959 #define FW_PARAM_DEV(param) \
2960 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2961 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2962 #define FW_PARAM_PFVF(param) \
2963 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2964 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2967 * Partition chip resources for use between various PFs, VFs, etc.
2970 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2971 const char *name_prefix)
2973 const struct firmware *cfg = NULL;
2975 struct fw_caps_config_cmd caps;
2976 uint32_t mtype, moff, finicsum, cfcsum;
2979 * Figure out what configuration file to use. Pick the default config
2980 * file for the card if the user hasn't specified one explicitly.
2982 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2983 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2984 /* Card specific overrides go here. */
2985 if (pci_get_device(sc->dev) == 0x440a)
2986 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2988 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2992 * We need to load another module if the profile is anything except
2993 * "default" or "flash".
2995 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2996 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2999 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3000 cfg = firmware_get(s);
3002 if (default_cfg != NULL) {
3003 device_printf(sc->dev,
3004 "unable to load module \"%s\" for "
3005 "configuration profile \"%s\", will use "
3006 "the default config file instead.\n",
3008 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3011 device_printf(sc->dev,
3012 "unable to load module \"%s\" for "
3013 "configuration profile \"%s\", will use "
3014 "the config file on the card's flash "
3015 "instead.\n", s, sc->cfg_file);
3016 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3022 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3023 default_cfg == NULL) {
3024 device_printf(sc->dev,
3025 "default config file not available, will use the config "
3026 "file on the card's flash instead.\n");
3027 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3030 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3032 const uint32_t *cfdata;
3033 uint32_t param, val, addr;
3035 KASSERT(cfg != NULL || default_cfg != NULL,
3036 ("%s: no config to upload", __func__));
3039 * Ask the firmware where it wants us to upload the config file.
3041 param = FW_PARAM_DEV(CF);
3042 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3044 /* No support for config file? Shouldn't happen. */
3045 device_printf(sc->dev,
3046 "failed to query config file location: %d.\n", rc);
3049 mtype = G_FW_PARAMS_PARAM_Y(val);
3050 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3053 * XXX: sheer laziness. We deliberately added 4 bytes of
3054 * useless stuffing/comments at the end of the config file so
3055 * it's ok to simply throw away the last remaining bytes when
3056 * the config file is not an exact multiple of 4. This also
3057 * helps with the validate_mt_off_len check.
3060 cflen = cfg->datasize & ~3;
3063 cflen = default_cfg->datasize & ~3;
3064 cfdata = default_cfg->data;
3067 if (cflen > FLASH_CFG_MAX_SIZE) {
3068 device_printf(sc->dev,
3069 "config file too long (%d, max allowed is %d). "
3070 "Will try to use the config on the card, if any.\n",
3071 cflen, FLASH_CFG_MAX_SIZE);
3072 goto use_config_on_flash;
3075 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3077 device_printf(sc->dev,
3078 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3079 "Will try to use the config on the card, if any.\n",
3080 __func__, mtype, moff, cflen, rc);
3081 goto use_config_on_flash;
3083 write_via_memwin(sc, 2, addr, cfdata, cflen);
3085 use_config_on_flash:
3086 mtype = FW_MEMTYPE_FLASH;
3087 moff = t4_flash_cfg_addr(sc);
3090 bzero(&caps, sizeof(caps));
3091 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3092 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3093 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3094 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3095 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3096 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3098 device_printf(sc->dev,
3099 "failed to pre-process config file: %d "
3100 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3104 finicsum = be32toh(caps.finicsum);
3105 cfcsum = be32toh(caps.cfcsum);
3106 if (finicsum != cfcsum) {
3107 device_printf(sc->dev,
3108 "WARNING: config file checksum mismatch: %08x %08x\n",
3111 sc->cfcsum = cfcsum;
3113 #define LIMIT_CAPS(x) do { \
3114 caps.x &= htobe16(t4_##x##_allowed); \
3118 * Let the firmware know what features will (not) be used so it can tune
3119 * things accordingly.
3121 LIMIT_CAPS(nbmcaps);
3122 LIMIT_CAPS(linkcaps);
3123 LIMIT_CAPS(switchcaps);
3124 LIMIT_CAPS(niccaps);
3125 LIMIT_CAPS(toecaps);
3126 LIMIT_CAPS(rdmacaps);
3127 LIMIT_CAPS(tlscaps);
3128 LIMIT_CAPS(iscsicaps);
3129 LIMIT_CAPS(fcoecaps);
3132 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3133 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3134 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3135 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3137 device_printf(sc->dev,
3138 "failed to process config file: %d.\n", rc);
3142 firmware_put(cfg, FIRMWARE_UNLOAD);
3147 * Retrieve parameters that are needed (or nice to have) very early.
3150 get_params__pre_init(struct adapter *sc)
3153 uint32_t param[2], val[2];
3155 param[0] = FW_PARAM_DEV(PORTVEC);
3156 param[1] = FW_PARAM_DEV(CCLK);
3157 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3159 device_printf(sc->dev,
3160 "failed to query parameters (pre_init): %d.\n", rc);
3164 sc->params.portvec = val[0];
3165 sc->params.nports = bitcount32(val[0]);
3166 sc->params.vpd.cclk = val[1];
3168 /* Read device log parameters. */
3169 rc = -t4_init_devlog_params(sc, 1);
3171 fixup_devlog_params(sc);
3173 device_printf(sc->dev,
3174 "failed to get devlog parameters: %d.\n", rc);
3175 rc = 0; /* devlog isn't critical for device operation */
3182 * Retrieve various parameters that are of interest to the driver. The device
3183 * has been initialized by the firmware at this point.
3186 get_params__post_init(struct adapter *sc)
3189 uint32_t param[7], val[7];
3190 struct fw_caps_config_cmd caps;
3192 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3193 param[1] = FW_PARAM_PFVF(EQ_START);
3194 param[2] = FW_PARAM_PFVF(FILTER_START);
3195 param[3] = FW_PARAM_PFVF(FILTER_END);
3196 param[4] = FW_PARAM_PFVF(L2T_START);
3197 param[5] = FW_PARAM_PFVF(L2T_END);
3198 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3200 device_printf(sc->dev,
3201 "failed to query parameters (post_init): %d.\n", rc);
3205 sc->sge.iq_start = val[0];
3206 sc->sge.eq_start = val[1];
3207 sc->tids.ftid_base = val[2];
3208 sc->tids.nftids = val[3] - val[2] + 1;
3209 sc->params.ftid_min = val[2];
3210 sc->params.ftid_max = val[3];
3211 sc->vres.l2t.start = val[4];
3212 sc->vres.l2t.size = val[5] - val[4] + 1;
3213 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3214 ("%s: L2 table size (%u) larger than expected (%u)",
3215 __func__, sc->vres.l2t.size, L2T_SIZE));
3217 /* get capabilites */
3218 bzero(&caps, sizeof(caps));
3219 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3220 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3221 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3222 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3224 device_printf(sc->dev,
3225 "failed to get card capabilities: %d.\n", rc);
3229 #define READ_CAPS(x) do { \
3230 sc->x = htobe16(caps.x); \
3233 READ_CAPS(linkcaps);
3234 READ_CAPS(switchcaps);
3237 READ_CAPS(rdmacaps);
3239 READ_CAPS(iscsicaps);
3240 READ_CAPS(fcoecaps);
3242 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3243 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3244 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3245 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3246 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3248 device_printf(sc->dev,
3249 "failed to query NIC parameters: %d.\n", rc);
3252 sc->tids.etid_base = val[0];
3253 sc->params.etid_min = val[0];
3254 sc->tids.netids = val[1] - val[0] + 1;
3255 sc->params.netids = sc->tids.netids;
3256 sc->params.eo_wr_cred = val[2];
3257 sc->params.ethoffload = 1;
3261 /* query offload-related parameters */
3262 param[0] = FW_PARAM_DEV(NTID);
3263 param[1] = FW_PARAM_PFVF(SERVER_START);
3264 param[2] = FW_PARAM_PFVF(SERVER_END);
3265 param[3] = FW_PARAM_PFVF(TDDP_START);
3266 param[4] = FW_PARAM_PFVF(TDDP_END);
3267 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3268 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3270 device_printf(sc->dev,
3271 "failed to query TOE parameters: %d.\n", rc);
3274 sc->tids.ntids = val[0];
3275 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3276 sc->tids.stid_base = val[1];
3277 sc->tids.nstids = val[2] - val[1] + 1;
3278 sc->vres.ddp.start = val[3];
3279 sc->vres.ddp.size = val[4] - val[3] + 1;
3280 sc->params.ofldq_wr_cred = val[5];
3281 sc->params.offload = 1;
3284 param[0] = FW_PARAM_PFVF(STAG_START);
3285 param[1] = FW_PARAM_PFVF(STAG_END);
3286 param[2] = FW_PARAM_PFVF(RQ_START);
3287 param[3] = FW_PARAM_PFVF(RQ_END);
3288 param[4] = FW_PARAM_PFVF(PBL_START);
3289 param[5] = FW_PARAM_PFVF(PBL_END);
3290 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3292 device_printf(sc->dev,
3293 "failed to query RDMA parameters(1): %d.\n", rc);
3296 sc->vres.stag.start = val[0];
3297 sc->vres.stag.size = val[1] - val[0] + 1;
3298 sc->vres.rq.start = val[2];
3299 sc->vres.rq.size = val[3] - val[2] + 1;
3300 sc->vres.pbl.start = val[4];
3301 sc->vres.pbl.size = val[5] - val[4] + 1;
3303 param[0] = FW_PARAM_PFVF(SQRQ_START);
3304 param[1] = FW_PARAM_PFVF(SQRQ_END);
3305 param[2] = FW_PARAM_PFVF(CQ_START);
3306 param[3] = FW_PARAM_PFVF(CQ_END);
3307 param[4] = FW_PARAM_PFVF(OCQ_START);
3308 param[5] = FW_PARAM_PFVF(OCQ_END);
3309 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3311 device_printf(sc->dev,
3312 "failed to query RDMA parameters(2): %d.\n", rc);
3315 sc->vres.qp.start = val[0];
3316 sc->vres.qp.size = val[1] - val[0] + 1;
3317 sc->vres.cq.start = val[2];
3318 sc->vres.cq.size = val[3] - val[2] + 1;
3319 sc->vres.ocq.start = val[4];
3320 sc->vres.ocq.size = val[5] - val[4] + 1;
3322 if (sc->iscsicaps) {
3323 param[0] = FW_PARAM_PFVF(ISCSI_START);
3324 param[1] = FW_PARAM_PFVF(ISCSI_END);
3325 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3327 device_printf(sc->dev,
3328 "failed to query iSCSI parameters: %d.\n", rc);
3331 sc->vres.iscsi.start = val[0];
3332 sc->vres.iscsi.size = val[1] - val[0] + 1;
3335 t4_init_sge_params(sc);
3338 * We've got the params we wanted to query via the firmware. Now grab
3339 * some others directly from the chip.
3341 rc = t4_read_chip_settings(sc);
3347 set_params__post_init(struct adapter *sc)
3349 uint32_t param, val;
3351 /* ask for encapsulated CPLs */
3352 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3354 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3359 #undef FW_PARAM_PFVF
3363 t4_set_desc(struct adapter *sc)
3366 struct adapter_params *p = &sc->params;
3368 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
3369 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
3370 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
3372 device_set_desc_copy(sc->dev, buf);
3376 build_medialist(struct port_info *pi, struct ifmedia *media)
3382 ifmedia_removeall(media);
3384 m = IFM_ETHER | IFM_FDX;
3386 switch(pi->port_type) {
3387 case FW_PORT_TYPE_BT_XFI:
3388 case FW_PORT_TYPE_BT_XAUI:
3389 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3392 case FW_PORT_TYPE_BT_SGMII:
3393 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3394 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3395 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3396 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3399 case FW_PORT_TYPE_CX4:
3400 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3401 ifmedia_set(media, m | IFM_10G_CX4);
3404 case FW_PORT_TYPE_QSFP_10G:
3405 case FW_PORT_TYPE_SFP:
3406 case FW_PORT_TYPE_FIBER_XFI:
3407 case FW_PORT_TYPE_FIBER_XAUI:
3408 switch (pi->mod_type) {
3410 case FW_PORT_MOD_TYPE_LR:
3411 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3412 ifmedia_set(media, m | IFM_10G_LR);
3415 case FW_PORT_MOD_TYPE_SR:
3416 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3417 ifmedia_set(media, m | IFM_10G_SR);
3420 case FW_PORT_MOD_TYPE_LRM:
3421 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3422 ifmedia_set(media, m | IFM_10G_LRM);
3425 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3426 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3427 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3428 ifmedia_set(media, m | IFM_10G_TWINAX);
3431 case FW_PORT_MOD_TYPE_NONE:
3433 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3434 ifmedia_set(media, m | IFM_NONE);
3437 case FW_PORT_MOD_TYPE_NA:
3438 case FW_PORT_MOD_TYPE_ER:
3440 device_printf(pi->dev,
3441 "unknown port_type (%d), mod_type (%d)\n",
3442 pi->port_type, pi->mod_type);
3443 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3444 ifmedia_set(media, m | IFM_UNKNOWN);
3449 case FW_PORT_TYPE_QSFP:
3450 switch (pi->mod_type) {
3452 case FW_PORT_MOD_TYPE_LR:
3453 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3454 ifmedia_set(media, m | IFM_40G_LR4);
3457 case FW_PORT_MOD_TYPE_SR:
3458 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3459 ifmedia_set(media, m | IFM_40G_SR4);
3462 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3463 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3464 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3465 ifmedia_set(media, m | IFM_40G_CR4);
3468 case FW_PORT_MOD_TYPE_NONE:
3470 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3471 ifmedia_set(media, m | IFM_NONE);
3475 device_printf(pi->dev,
3476 "unknown port_type (%d), mod_type (%d)\n",
3477 pi->port_type, pi->mod_type);
3478 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3479 ifmedia_set(media, m | IFM_UNKNOWN);
3485 device_printf(pi->dev,
3486 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3488 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3489 ifmedia_set(media, m | IFM_UNKNOWN);
3496 #define FW_MAC_EXACT_CHUNK 7
3499 * Program the port's XGMAC based on parameters in ifnet. The caller also
3500 * indicates which parameters should be programmed (the rest are left alone).
3503 update_mac_settings(struct ifnet *ifp, int flags)
3506 struct vi_info *vi = ifp->if_softc;
3507 struct port_info *pi = vi->pi;
3508 struct adapter *sc = pi->adapter;
3509 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3511 ASSERT_SYNCHRONIZED_OP(sc);
3512 KASSERT(flags, ("%s: not told what to update.", __func__));
3514 if (flags & XGMAC_MTU)
3517 if (flags & XGMAC_PROMISC)
3518 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3520 if (flags & XGMAC_ALLMULTI)
3521 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3523 if (flags & XGMAC_VLANEX)
3524 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3526 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3527 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3528 allmulti, 1, vlanex, false);
3530 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3536 if (flags & XGMAC_UCADDR) {
3537 uint8_t ucaddr[ETHER_ADDR_LEN];
3539 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3540 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3541 ucaddr, true, true);
3544 if_printf(ifp, "change_mac failed: %d\n", rc);
3547 vi->xact_addr_filt = rc;
3552 if (flags & XGMAC_MCADDRS) {
3553 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3556 struct ifmultiaddr *ifma;
3559 if_maddr_rlock(ifp);
3560 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3561 if (ifma->ifma_addr->sa_family != AF_LINK)
3564 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3565 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3568 if (i == FW_MAC_EXACT_CHUNK) {
3569 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3570 del, i, mcaddr, NULL, &hash, 0);
3573 for (j = 0; j < i; j++) {
3575 "failed to add mc address"
3577 "%02x:%02x:%02x rc=%d\n",
3578 mcaddr[j][0], mcaddr[j][1],
3579 mcaddr[j][2], mcaddr[j][3],
3580 mcaddr[j][4], mcaddr[j][5],
3590 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3591 mcaddr, NULL, &hash, 0);
3594 for (j = 0; j < i; j++) {
3596 "failed to add mc address"
3598 "%02x:%02x:%02x rc=%d\n",
3599 mcaddr[j][0], mcaddr[j][1],
3600 mcaddr[j][2], mcaddr[j][3],
3601 mcaddr[j][4], mcaddr[j][5],
3608 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3610 if_printf(ifp, "failed to set mc address hash: %d", rc);
3612 if_maddr_runlock(ifp);
3619 * {begin|end}_synchronized_op must be called from the same thread.
3622 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3628 /* the caller thinks it's ok to sleep, but is it really? */
3629 if (flags & SLEEP_OK)
3630 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3631 "begin_synchronized_op");
3642 if (vi && IS_DOOMED(vi)) {
3652 if (!(flags & SLEEP_OK)) {
3657 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3663 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3666 sc->last_op = wmesg;
3667 sc->last_op_thr = curthread;
3668 sc->last_op_flags = flags;
3672 if (!(flags & HOLD_LOCK) || rc)
3679 * Tell if_ioctl and if_init that the VI is going away. This is
3680 * special variant of begin_synchronized_op and must be paired with a
3681 * call to end_synchronized_op.
3684 doom_vi(struct adapter *sc, struct vi_info *vi)
3691 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3694 sc->last_op = "t4detach";
3695 sc->last_op_thr = curthread;
3696 sc->last_op_flags = 0;
3702 * {begin|end}_synchronized_op must be called from the same thread.
3705 end_synchronized_op(struct adapter *sc, int flags)
3708 if (flags & LOCK_HELD)
3709 ADAPTER_LOCK_ASSERT_OWNED(sc);
3713 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3720 cxgbe_init_synchronized(struct vi_info *vi)
3722 struct port_info *pi = vi->pi;
3723 struct adapter *sc = pi->adapter;
3724 struct ifnet *ifp = vi->ifp;
3726 struct sge_txq *txq;
3728 ASSERT_SYNCHRONIZED_OP(sc);
3730 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3731 return (0); /* already running */
3733 if (!(sc->flags & FULL_INIT_DONE) &&
3734 ((rc = adapter_full_init(sc)) != 0))
3735 return (rc); /* error message displayed already */
3737 if (!(vi->flags & VI_INIT_DONE) &&
3738 ((rc = vi_full_init(vi)) != 0))
3739 return (rc); /* error message displayed already */
3741 rc = update_mac_settings(ifp, XGMAC_ALL);
3743 goto done; /* error message displayed already */
3745 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3747 if_printf(ifp, "enable_vi failed: %d\n", rc);
3752 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3756 for_each_txq(vi, i, txq) {
3758 txq->eq.flags |= EQ_ENABLED;
3763 * The first iq of the first port to come up is used for tracing.
3765 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3766 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3767 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3768 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3769 V_QUEUENUMBER(sc->traceq));
3770 pi->flags |= HAS_TRACEQ;
3775 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3779 callout_reset(&vi->tick, hz, vi_tick, vi);
3781 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3785 cxgbe_uninit_synchronized(vi);
3794 cxgbe_uninit_synchronized(struct vi_info *vi)
3796 struct port_info *pi = vi->pi;
3797 struct adapter *sc = pi->adapter;
3798 struct ifnet *ifp = vi->ifp;
3800 struct sge_txq *txq;
3802 ASSERT_SYNCHRONIZED_OP(sc);
3804 if (!(vi->flags & VI_INIT_DONE)) {
3805 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3806 ("uninited VI is running"));
3811 * Disable the VI so that all its data in either direction is discarded
3812 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3813 * tick) intact as the TP can deliver negative advice or data that it's
3814 * holding in its RAM (for an offloaded connection) even after the VI is
3817 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3819 if_printf(ifp, "disable_vi failed: %d\n", rc);
3823 for_each_txq(vi, i, txq) {
3825 txq->eq.flags &= ~EQ_ENABLED;
3831 callout_stop(&pi->tick);
3833 callout_stop(&vi->tick);
3834 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3838 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3840 if (pi->up_vis > 0) {
3846 pi->link_cfg.link_ok = 0;
3847 pi->link_cfg.speed = 0;
3849 t4_os_link_changed(sc, pi->port_id, 0, -1);
3855 * It is ok for this function to fail midway and return right away. t4_detach
3856 * will walk the entire sc->irq list and clean up whatever is valid.
3859 setup_intr_handlers(struct adapter *sc)
3861 int rc, rid, p, q, v;
3864 struct port_info *pi;
3866 struct sge *sge = &sc->sge;
3867 struct sge_rxq *rxq;
3869 struct sge_ofld_rxq *ofld_rxq;
3872 struct sge_nm_rxq *nm_rxq;
3875 int nbuckets = rss_getnumbuckets();
3882 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3883 if (sc->intr_count == 1)
3884 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3886 /* Multiple interrupts. */
3887 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3888 ("%s: too few intr.", __func__));
3890 /* The first one is always error intr */
3891 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3897 /* The second one is always the firmware event queue */
3898 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3904 for_each_port(sc, p) {
3906 for_each_vi(pi, v, vi) {
3907 vi->first_intr = rid - 1;
3909 if (vi->nnmrxq > 0) {
3910 int n = max(vi->nrxq, vi->nnmrxq);
3912 MPASS(vi->flags & INTR_RXQ);
3914 rxq = &sge->rxq[vi->first_rxq];
3916 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3918 for (q = 0; q < n; q++) {
3919 snprintf(s, sizeof(s), "%x%c%x", p,
3925 irq->nm_rxq = nm_rxq++;
3927 rc = t4_alloc_irq(sc, irq, rid,
3928 t4_vi_intr, irq, s);
3935 } else if (vi->flags & INTR_RXQ) {
3936 for_each_rxq(vi, q, rxq) {
3937 snprintf(s, sizeof(s), "%x%c%x", p,
3939 rc = t4_alloc_irq(sc, irq, rid,
3944 bus_bind_intr(sc->dev, irq->res,
3945 rss_getcpu(q % nbuckets));
3953 if (vi->flags & INTR_OFLD_RXQ) {
3954 for_each_ofld_rxq(vi, q, ofld_rxq) {
3955 snprintf(s, sizeof(s), "%x%c%x", p,
3957 rc = t4_alloc_irq(sc, irq, rid,
3958 t4_intr, ofld_rxq, s);
3969 MPASS(irq == &sc->irq[sc->intr_count]);
3975 adapter_full_init(struct adapter *sc)
3979 ASSERT_SYNCHRONIZED_OP(sc);
3980 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3981 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3982 ("%s: FULL_INIT_DONE already", __func__));
3985 * queues that belong to the adapter (not any particular port).
3987 rc = t4_setup_adapter_queues(sc);
3991 for (i = 0; i < nitems(sc->tq); i++) {
3992 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3993 taskqueue_thread_enqueue, &sc->tq[i]);
3994 if (sc->tq[i] == NULL) {
3995 device_printf(sc->dev,
3996 "failed to allocate task queue %d\n", i);
4000 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4001 device_get_nameunit(sc->dev), i);
4005 sc->flags |= FULL_INIT_DONE;
4008 adapter_full_uninit(sc);
4014 adapter_full_uninit(struct adapter *sc)
4018 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4020 t4_teardown_adapter_queues(sc);
4022 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4023 taskqueue_free(sc->tq[i]);
4027 sc->flags &= ~FULL_INIT_DONE;
4033 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4034 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4035 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4036 RSS_HASHTYPE_RSS_UDP_IPV6)
4038 /* Translates kernel hash types to hardware. */
4040 hashconfig_to_hashen(int hashconfig)
4044 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4045 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4046 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4047 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4048 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4049 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4050 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4052 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4053 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4054 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4056 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4057 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4058 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4059 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4064 /* Translates hardware hash types to kernel. */
4066 hashen_to_hashconfig(int hashen)
4070 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4072 * If UDP hashing was enabled it must have been enabled for
4073 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4074 * enabling any 4-tuple hash is nonsense configuration.
4076 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4077 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4079 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4080 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4081 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4082 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4084 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4085 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4086 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4087 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4088 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4089 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4090 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4091 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4093 return (hashconfig);
4098 vi_full_init(struct vi_info *vi)
4100 struct adapter *sc = vi->pi->adapter;
4101 struct ifnet *ifp = vi->ifp;
4103 struct sge_rxq *rxq;
4104 int rc, i, j, hashen;
4106 int nbuckets = rss_getnumbuckets();
4107 int hashconfig = rss_gethashconfig();
4109 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4110 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4113 ASSERT_SYNCHRONIZED_OP(sc);
4114 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4115 ("%s: VI_INIT_DONE already", __func__));
4117 sysctl_ctx_init(&vi->ctx);
4118 vi->flags |= VI_SYSCTL_CTX;
4121 * Allocate tx/rx/fl queues for this VI.
4123 rc = t4_setup_vi_queues(vi);
4125 goto done; /* error message displayed already */
4128 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4130 if (vi->nrxq > vi->rss_size) {
4131 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4132 "some queues will never receive traffic.\n", vi->nrxq,
4134 } else if (vi->rss_size % vi->nrxq) {
4135 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4136 "expect uneven traffic distribution.\n", vi->nrxq,
4140 MPASS(RSS_KEYSIZE == 40);
4141 if (vi->nrxq != nbuckets) {
4142 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4143 "performance will be impacted.\n", vi->nrxq, nbuckets);
4146 rss_getkey((void *)&raw_rss_key[0]);
4147 for (i = 0; i < nitems(rss_key); i++) {
4148 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4150 t4_write_rss_key(sc, &rss_key[0], -1);
4152 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4153 for (i = 0; i < vi->rss_size;) {
4155 j = rss_get_indirection_to_bucket(i);
4157 rxq = &sc->sge.rxq[vi->first_rxq + j];
4158 rss[i++] = rxq->iq.abs_id;
4160 for_each_rxq(vi, j, rxq) {
4161 rss[i++] = rxq->iq.abs_id;
4162 if (i == vi->rss_size)
4168 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4171 if_printf(ifp, "rss_config failed: %d\n", rc);
4176 hashen = hashconfig_to_hashen(hashconfig);
4179 * We may have had to enable some hashes even though the global config
4180 * wants them disabled. This is a potential problem that must be
4181 * reported to the user.
4183 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4186 * If we consider only the supported hash types, then the enabled hashes
4187 * are a superset of the requested hashes. In other words, there cannot
4188 * be any supported hash that was requested but not enabled, but there
4189 * can be hashes that were not requested but had to be enabled.
4191 extra &= SUPPORTED_RSS_HASHTYPES;
4192 MPASS((extra & hashconfig) == 0);
4196 "global RSS config (0x%x) cannot be accommodated.\n",
4199 if (extra & RSS_HASHTYPE_RSS_IPV4)
4200 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4201 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4202 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4203 if (extra & RSS_HASHTYPE_RSS_IPV6)
4204 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4205 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4206 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4207 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4208 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4209 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4210 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4212 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4213 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4214 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4215 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4217 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4219 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4224 vi->flags |= VI_INIT_DONE;
4236 vi_full_uninit(struct vi_info *vi)
4238 struct port_info *pi = vi->pi;
4239 struct adapter *sc = pi->adapter;
4241 struct sge_rxq *rxq;
4242 struct sge_txq *txq;
4244 struct sge_ofld_rxq *ofld_rxq;
4245 struct sge_wrq *ofld_txq;
4248 if (vi->flags & VI_INIT_DONE) {
4250 /* Need to quiesce queues. */
4252 /* XXX: Only for the first VI? */
4254 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4256 for_each_txq(vi, i, txq) {
4257 quiesce_txq(sc, txq);
4261 for_each_ofld_txq(vi, i, ofld_txq) {
4262 quiesce_wrq(sc, ofld_txq);
4266 for_each_rxq(vi, i, rxq) {
4267 quiesce_iq(sc, &rxq->iq);
4268 quiesce_fl(sc, &rxq->fl);
4272 for_each_ofld_rxq(vi, i, ofld_rxq) {
4273 quiesce_iq(sc, &ofld_rxq->iq);
4274 quiesce_fl(sc, &ofld_rxq->fl);
4277 free(vi->rss, M_CXGBE);
4278 free(vi->nm_rss, M_CXGBE);
4281 t4_teardown_vi_queues(vi);
4282 vi->flags &= ~VI_INIT_DONE;
4288 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4290 struct sge_eq *eq = &txq->eq;
4291 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4293 (void) sc; /* unused */
4297 MPASS((eq->flags & EQ_ENABLED) == 0);
4301 /* Wait for the mp_ring to empty. */
4302 while (!mp_ring_is_idle(txq->r)) {
4303 mp_ring_check_drainage(txq->r, 0);
4304 pause("rquiesce", 1);
4307 /* Then wait for the hardware to finish. */
4308 while (spg->cidx != htobe16(eq->pidx))
4309 pause("equiesce", 1);
4311 /* Finally, wait for the driver to reclaim all descriptors. */
4312 while (eq->cidx != eq->pidx)
4313 pause("dquiesce", 1);
4317 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4324 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4326 (void) sc; /* unused */
4328 /* Synchronize with the interrupt handler */
4329 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4334 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4336 mtx_lock(&sc->sfl_lock);
4338 fl->flags |= FL_DOOMED;
4340 callout_stop(&sc->sfl_callout);
4341 mtx_unlock(&sc->sfl_lock);
4343 KASSERT((fl->flags & FL_STARVING) == 0,
4344 ("%s: still starving", __func__));
4348 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4349 driver_intr_t *handler, void *arg, char *name)
4354 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4355 RF_SHAREABLE | RF_ACTIVE);
4356 if (irq->res == NULL) {
4357 device_printf(sc->dev,
4358 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4362 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4363 NULL, handler, arg, &irq->tag);
4365 device_printf(sc->dev,
4366 "failed to setup interrupt for rid %d, name %s: %d\n",
4369 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
4375 t4_free_irq(struct adapter *sc, struct irq *irq)
4378 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4380 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4382 bzero(irq, sizeof(*irq));
4388 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4391 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4392 t4_get_regs(sc, buf, regs->len);
4395 #define A_PL_INDIR_CMD 0x1f8
4397 #define S_PL_AUTOINC 31
4398 #define M_PL_AUTOINC 0x1U
4399 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4400 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4402 #define S_PL_VFID 20
4403 #define M_PL_VFID 0xffU
4404 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4405 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4408 #define M_PL_ADDR 0xfffffU
4409 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4410 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4412 #define A_PL_INDIR_DATA 0x1fc
4415 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4419 mtx_assert(&sc->reg_lock, MA_OWNED);
4420 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4421 V_PL_VFID(G_FW_VIID_VIN(viid)) | V_PL_ADDR(VF_MPS_REG(reg)));
4422 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4423 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4424 return (((uint64_t)stats[1]) << 32 | stats[0]);
4428 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4429 struct fw_vi_stats_vf *stats)
4432 #define GET_STAT(name) \
4433 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4435 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4436 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4437 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4438 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4439 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4440 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4441 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4442 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4443 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4444 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4445 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4446 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4447 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4448 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4449 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4450 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4456 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4460 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4461 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4462 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4463 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4464 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4465 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4469 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4472 const struct timeval interval = {0, 250000}; /* 250ms */
4474 if (!(vi->flags & VI_INIT_DONE))
4478 timevalsub(&tv, &interval);
4479 if (timevalcmp(&tv, &vi->last_refreshed, <))
4482 mtx_lock(&sc->reg_lock);
4483 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4484 getmicrotime(&vi->last_refreshed);
4485 mtx_unlock(&sc->reg_lock);
4489 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4492 u_int v, tnl_cong_drops;
4494 const struct timeval interval = {0, 250000}; /* 250ms */
4497 timevalsub(&tv, &interval);
4498 if (timevalcmp(&tv, &pi->last_refreshed, <))
4502 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
4503 for (i = 0; i < sc->chip_params->nchan; i++) {
4504 if (pi->rx_chan_map & (1 << i)) {
4505 mtx_lock(&sc->reg_lock);
4506 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4507 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4508 mtx_unlock(&sc->reg_lock);
4509 tnl_cong_drops += v;
4512 pi->tnl_cong_drops = tnl_cong_drops;
4513 getmicrotime(&pi->last_refreshed);
4517 cxgbe_tick(void *arg)
4519 struct port_info *pi = arg;
4520 struct adapter *sc = pi->adapter;
4522 PORT_LOCK_ASSERT_OWNED(pi);
4523 cxgbe_refresh_stats(sc, pi);
4525 callout_schedule(&pi->tick, hz);
4531 struct vi_info *vi = arg;
4532 struct adapter *sc = vi->pi->adapter;
4534 vi_refresh_stats(sc, vi);
4536 callout_schedule(&vi->tick, hz);
4540 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4544 if (arg != ifp || ifp->if_type != IFT_ETHER)
4547 vlan = VLAN_DEVAT(ifp, vid);
4548 VLAN_SETCOOKIE(vlan, ifp);
4552 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4554 static char *caps_decoder[] = {
4555 "\20\001IPMI\002NCSI", /* 0: NBM */
4556 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4557 "\20\001INGRESS\002EGRESS", /* 2: switch */
4558 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4559 "\006HASHFILTER\007ETHOFLD",
4560 "\20\001TOE", /* 4: TOE */
4561 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4562 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4563 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4564 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4566 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4567 "\20\00KEYS", /* 7: TLS */
4568 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4569 "\004PO_INITIATOR\005PO_TARGET",
4573 t4_sysctls(struct adapter *sc)
4575 struct sysctl_ctx_list *ctx;
4576 struct sysctl_oid *oid;
4577 struct sysctl_oid_list *children, *c0;
4578 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4580 ctx = device_get_sysctl_ctx(sc->dev);
4585 oid = device_get_sysctl_tree(sc->dev);
4586 c0 = children = SYSCTL_CHILDREN(oid);
4588 sc->sc_do_rxcopy = 1;
4589 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4590 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4592 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4593 sc->params.nports, "# of ports");
4595 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4596 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4597 sysctl_bitfield, "A", "available doorbells");
4599 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4600 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4603 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4604 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4605 "interrupt holdoff timer values (us)");
4607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4608 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4609 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4610 "interrupt holdoff packet counter values");
4612 t4_sge_sysctls(sc, ctx, children);
4614 sc->lro_timeout = 100;
4615 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4616 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4618 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "debug_flags", CTLFLAG_RW,
4619 &sc->debug_flags, 0, "flags to enable runtime debugging");
4621 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4622 NULL, chip_rev(sc), "chip hardware revision");
4624 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4625 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4627 if (sc->params.exprom_vers != 0) {
4628 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "exprom_version",
4629 CTLFLAG_RD, sc->exprom_version, 0, "expansion ROM version");
4632 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4633 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4635 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4636 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4638 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4639 sc->cfcsum, "config file checksum");
4641 #define SYSCTL_CAP(name, n, text) \
4642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4643 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4644 sysctl_bitfield, "A", "available " text "capabilities")
4646 SYSCTL_CAP(nbmcaps, 0, "NBM");
4647 SYSCTL_CAP(linkcaps, 1, "link");
4648 SYSCTL_CAP(switchcaps, 2, "switch");
4649 SYSCTL_CAP(niccaps, 3, "NIC");
4650 SYSCTL_CAP(toecaps, 4, "TCP offload");
4651 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4652 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4653 SYSCTL_CAP(tlscaps, 7, "TLS");
4654 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4657 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4658 NULL, sc->tids.nftids, "number of filters");
4660 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4661 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4662 "chip temperature (in Celsius)");
4666 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4668 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4669 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4670 "logs and miscellaneous information");
4671 children = SYSCTL_CHILDREN(oid);
4673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4674 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4675 sysctl_cctrl, "A", "congestion control");
4677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4678 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4679 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4682 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4683 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4686 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4687 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4690 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4691 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4694 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4695 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4698 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4699 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4701 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4702 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4703 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4704 "A", "CIM logic analyzer");
4706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4707 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4708 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4711 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4712 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4715 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4716 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4718 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4719 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4720 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4722 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4723 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4724 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4727 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4728 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4731 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4732 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4734 if (chip_id(sc) > CHELSIO_T4) {
4735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4736 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4737 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4739 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4740 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4741 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4744 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4745 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4746 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4748 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4749 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4750 sysctl_cim_qcfg, "A", "CIM queue configuration");
4752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4753 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4754 sysctl_cpl_stats, "A", "CPL statistics");
4756 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4757 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4758 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4760 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4761 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4762 sysctl_devlog, "A", "firmware's device log");
4764 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4765 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4766 sysctl_fcoe_stats, "A", "FCoE statistics");
4768 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4769 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4770 sysctl_hw_sched, "A", "hardware scheduler ");
4772 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4773 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4774 sysctl_l2t, "A", "hardware L2 table");
4776 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4777 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4778 sysctl_lb_stats, "A", "loopback statistics");
4780 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4781 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4782 sysctl_meminfo, "A", "memory regions");
4784 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4785 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4786 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4787 "A", "MPS TCAM entries");
4789 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4790 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4791 sysctl_path_mtus, "A", "path MTUs");
4793 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4794 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4795 sysctl_pm_stats, "A", "PM statistics");
4797 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4798 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4799 sysctl_rdma_stats, "A", "RDMA statistics");
4801 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4802 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4803 sysctl_tcp_stats, "A", "TCP statistics");
4805 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4806 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4807 sysctl_tids, "A", "TID information");
4809 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4810 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4811 sysctl_tp_err_stats, "A", "TP error statistics");
4813 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4814 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4815 "TP logic analyzer event capture mask");
4817 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4818 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4819 sysctl_tp_la, "A", "TP logic analyzer");
4821 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4822 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4823 sysctl_tx_rate, "A", "Tx rate");
4825 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4826 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4827 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4830 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4831 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4832 sysctl_wcwr_stats, "A", "write combined work requests");
4837 if (is_offload(sc)) {
4841 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4842 NULL, "TOE parameters");
4843 children = SYSCTL_CHILDREN(oid);
4845 sc->tt.sndbuf = 256 * 1024;
4846 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4847 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4850 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4851 &sc->tt.ddp, 0, "DDP allowed");
4853 sc->tt.rx_coalesce = 1;
4854 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4855 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4857 sc->tt.tx_align = 1;
4858 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4859 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4861 sc->tt.tx_zcopy = 0;
4862 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
4863 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
4864 "Enable zero-copy aio_write(2)");
4866 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4867 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4868 "TP timer tick (us)");
4870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4871 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4872 "TCP timestamp tick (us)");
4874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4875 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4879 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4880 "IU", "DACK timer (us)");
4882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4883 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4884 sysctl_tp_timer, "LU", "Retransmit min (us)");
4886 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4887 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4888 sysctl_tp_timer, "LU", "Retransmit max (us)");
4890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4891 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4892 sysctl_tp_timer, "LU", "Persist timer min (us)");
4894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4895 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4896 sysctl_tp_timer, "LU", "Persist timer max (us)");
4898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4899 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
4900 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
4902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
4903 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
4904 sysctl_tp_timer, "LU", "Keepidle interval (us)");
4906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
4907 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
4908 sysctl_tp_timer, "LU", "Initial SRTT (us)");
4910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
4911 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
4912 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
4918 vi_sysctls(struct vi_info *vi)
4920 struct sysctl_ctx_list *ctx;
4921 struct sysctl_oid *oid;
4922 struct sysctl_oid_list *children;
4924 ctx = device_get_sysctl_ctx(vi->dev);
4927 * dev.v?(cxgbe|cxl).X.
4929 oid = device_get_sysctl_tree(vi->dev);
4930 children = SYSCTL_CHILDREN(oid);
4932 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4933 vi->viid, "VI identifer");
4934 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4935 &vi->nrxq, 0, "# of rx queues");
4936 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4937 &vi->ntxq, 0, "# of tx queues");
4938 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4939 &vi->first_rxq, 0, "index of first rx queue");
4940 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4941 &vi->first_txq, 0, "index of first tx queue");
4942 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
4943 vi->rss_size, "size of RSS indirection table");
4945 if (IS_MAIN_VI(vi)) {
4946 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4947 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4948 "Reserve queue 0 for non-flowid packets");
4952 if (vi->nofldrxq != 0) {
4953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4955 "# of rx queues for offloaded TCP connections");
4956 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4958 "# of tx queues for offloaded TCP connections");
4959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4960 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4961 "index of first TOE rx queue");
4962 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4963 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4964 "index of first TOE tx queue");
4968 if (vi->nnmrxq != 0) {
4969 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4970 &vi->nnmrxq, 0, "# of netmap rx queues");
4971 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4972 &vi->nnmtxq, 0, "# of netmap tx queues");
4973 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4974 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4975 "index of first netmap rx queue");
4976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4977 CTLFLAG_RD, &vi->first_nm_txq, 0,
4978 "index of first netmap tx queue");
4982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4983 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
4984 "holdoff timer index");
4985 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4986 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
4987 "holdoff packet counter index");
4989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4990 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
4992 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4993 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
4998 cxgbe_sysctls(struct port_info *pi)
5000 struct sysctl_ctx_list *ctx;
5001 struct sysctl_oid *oid;
5002 struct sysctl_oid_list *children, *children2;
5003 struct adapter *sc = pi->adapter;
5007 ctx = device_get_sysctl_ctx(pi->dev);
5012 oid = device_get_sysctl_tree(pi->dev);
5013 children = SYSCTL_CHILDREN(oid);
5015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5016 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5017 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5018 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5019 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5020 "PHY temperature (in Celsius)");
5021 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5022 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5023 "PHY firmware version");
5026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5027 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
5028 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5030 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5031 port_top_speed(pi), "max speed (in Gbps)");
5034 * dev.(cxgbe|cxl).X.tc.
5036 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5037 "Tx scheduler traffic classes");
5038 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5039 struct tx_sched_class *tc = &pi->tc[i];
5041 snprintf(name, sizeof(name), "%d", i);
5042 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5043 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5045 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5046 &tc->flags, 0, "flags");
5047 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5048 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5050 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5051 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5052 sysctl_tc_params, "A", "traffic class parameters");
5057 * dev.cxgbe.X.stats.
5059 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5060 NULL, "port statistics");
5061 children = SYSCTL_CHILDREN(oid);
5062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5063 &pi->tx_parse_error, 0,
5064 "# of tx packets with invalid length or # of segments");
5066 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5067 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5068 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5069 sysctl_handle_t4_reg64, "QU", desc)
5071 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5072 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5073 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5074 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5075 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5076 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5077 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5078 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5079 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5080 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5081 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5082 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5083 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5084 "# of tx frames in this range",
5085 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5086 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5087 "# of tx frames in this range",
5088 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5089 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5090 "# of tx frames in this range",
5091 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5092 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5093 "# of tx frames in this range",
5094 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5095 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5096 "# of tx frames in this range",
5097 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5098 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5099 "# of tx frames in this range",
5100 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5101 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5102 "# of tx frames in this range",
5103 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5104 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5105 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5106 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5107 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5108 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5109 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5110 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5111 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5112 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5113 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5114 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5115 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5116 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5117 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5118 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5119 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5120 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5121 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5122 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5123 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5125 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5126 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5127 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5128 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5129 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5130 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5131 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5132 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5133 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5134 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5135 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5136 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5137 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5138 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5139 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5140 "# of frames received with bad FCS",
5141 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5142 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5143 "# of frames received with length error",
5144 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5145 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5146 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5147 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5148 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5149 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5150 "# of rx frames in this range",
5151 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5152 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5153 "# of rx frames in this range",
5154 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5155 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5156 "# of rx frames in this range",
5157 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5158 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5159 "# of rx frames in this range",
5160 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5161 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5162 "# of rx frames in this range",
5163 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5164 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5165 "# of rx frames in this range",
5166 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5167 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5168 "# of rx frames in this range",
5169 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5170 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5171 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5172 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5173 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5174 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5175 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5176 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5177 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5178 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5179 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5180 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5181 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5182 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5183 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5184 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5185 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5186 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5187 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5189 #undef SYSCTL_ADD_T4_REG64
5191 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5192 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5193 &pi->stats.name, desc)
5195 /* We get these from port_stats and they may be stale by up to 1s */
5196 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5197 "# drops due to buffer-group 0 overflows");
5198 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5199 "# drops due to buffer-group 1 overflows");
5200 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5201 "# drops due to buffer-group 2 overflows");
5202 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5203 "# drops due to buffer-group 3 overflows");
5204 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5205 "# of buffer-group 0 truncated packets");
5206 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5207 "# of buffer-group 1 truncated packets");
5208 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5209 "# of buffer-group 2 truncated packets");
5210 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5211 "# of buffer-group 3 truncated packets");
5213 #undef SYSCTL_ADD_T4_PORTSTAT
5217 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5219 int rc, *i, space = 0;
5222 sbuf_new_for_sysctl(&sb, NULL, 64, req);
5223 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5225 sbuf_printf(&sb, " ");
5226 sbuf_printf(&sb, "%d", *i);
5229 rc = sbuf_finish(&sb);
5235 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5240 rc = sysctl_wire_old_buffer(req, 0);
5244 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5248 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5249 rc = sbuf_finish(sb);
5256 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5258 struct port_info *pi = arg1;
5260 struct adapter *sc = pi->adapter;
5264 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5267 /* XXX: magic numbers */
5268 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5270 end_synchronized_op(sc, 0);
5276 rc = sysctl_handle_int(oidp, &v, 0, req);
5281 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5283 struct vi_info *vi = arg1;
5286 val = vi->rsrv_noflowq;
5287 rc = sysctl_handle_int(oidp, &val, 0, req);
5288 if (rc != 0 || req->newptr == NULL)
5291 if ((val >= 1) && (vi->ntxq > 1))
5292 vi->rsrv_noflowq = 1;
5294 vi->rsrv_noflowq = 0;
5300 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5302 struct vi_info *vi = arg1;
5303 struct adapter *sc = vi->pi->adapter;
5305 struct sge_rxq *rxq;
5307 struct sge_ofld_rxq *ofld_rxq;
5313 rc = sysctl_handle_int(oidp, &idx, 0, req);
5314 if (rc != 0 || req->newptr == NULL)
5317 if (idx < 0 || idx >= SGE_NTIMERS)
5320 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5325 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5326 for_each_rxq(vi, i, rxq) {
5327 #ifdef atomic_store_rel_8
5328 atomic_store_rel_8(&rxq->iq.intr_params, v);
5330 rxq->iq.intr_params = v;
5334 for_each_ofld_rxq(vi, i, ofld_rxq) {
5335 #ifdef atomic_store_rel_8
5336 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5338 ofld_rxq->iq.intr_params = v;
5344 end_synchronized_op(sc, LOCK_HELD);
5349 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5351 struct vi_info *vi = arg1;
5352 struct adapter *sc = vi->pi->adapter;
5357 rc = sysctl_handle_int(oidp, &idx, 0, req);
5358 if (rc != 0 || req->newptr == NULL)
5361 if (idx < -1 || idx >= SGE_NCOUNTERS)
5364 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5369 if (vi->flags & VI_INIT_DONE)
5370 rc = EBUSY; /* cannot be changed once the queues are created */
5374 end_synchronized_op(sc, LOCK_HELD);
5379 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5381 struct vi_info *vi = arg1;
5382 struct adapter *sc = vi->pi->adapter;
5385 qsize = vi->qsize_rxq;
5387 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5388 if (rc != 0 || req->newptr == NULL)
5391 if (qsize < 128 || (qsize & 7))
5394 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5399 if (vi->flags & VI_INIT_DONE)
5400 rc = EBUSY; /* cannot be changed once the queues are created */
5402 vi->qsize_rxq = qsize;
5404 end_synchronized_op(sc, LOCK_HELD);
5409 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5411 struct vi_info *vi = arg1;
5412 struct adapter *sc = vi->pi->adapter;
5415 qsize = vi->qsize_txq;
5417 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5418 if (rc != 0 || req->newptr == NULL)
5421 if (qsize < 128 || qsize > 65536)
5424 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5429 if (vi->flags & VI_INIT_DONE)
5430 rc = EBUSY; /* cannot be changed once the queues are created */
5432 vi->qsize_txq = qsize;
5434 end_synchronized_op(sc, LOCK_HELD);
5439 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5441 struct port_info *pi = arg1;
5442 struct adapter *sc = pi->adapter;
5443 struct link_config *lc = &pi->link_cfg;
5446 if (req->newptr == NULL) {
5448 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5450 rc = sysctl_wire_old_buffer(req, 0);
5454 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5458 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5459 rc = sbuf_finish(sb);
5465 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5468 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5474 if (s[0] < '0' || s[0] > '9')
5475 return (EINVAL); /* not a number */
5477 if (n & ~(PAUSE_TX | PAUSE_RX))
5478 return (EINVAL); /* some other bit is set too */
5480 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5484 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5485 int link_ok = lc->link_ok;
5487 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5488 lc->requested_fc |= n;
5489 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5490 lc->link_ok = link_ok; /* restore */
5492 end_synchronized_op(sc, 0);
5499 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5501 struct adapter *sc = arg1;
5505 val = t4_read_reg64(sc, reg);
5507 return (sysctl_handle_64(oidp, &val, 0, req));
5511 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5513 struct adapter *sc = arg1;
5515 uint32_t param, val;
5517 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5520 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5521 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5522 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5523 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5524 end_synchronized_op(sc, 0);
5528 /* unknown is returned as 0 but we display -1 in that case */
5529 t = val == 0 ? -1 : val;
5531 rc = sysctl_handle_int(oidp, &t, 0, req);
5537 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5539 struct adapter *sc = arg1;
5542 uint16_t incr[NMTUS][NCCTRL_WIN];
5543 static const char *dec_fac[] = {
5544 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5548 rc = sysctl_wire_old_buffer(req, 0);
5552 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5556 t4_read_cong_tbl(sc, incr);
5558 for (i = 0; i < NCCTRL_WIN; ++i) {
5559 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5560 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5561 incr[5][i], incr[6][i], incr[7][i]);
5562 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5563 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5564 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5565 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5568 rc = sbuf_finish(sb);
5574 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5575 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5576 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5577 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5581 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5583 struct adapter *sc = arg1;
5585 int rc, i, n, qid = arg2;
5588 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5590 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5591 ("%s: bad qid %d\n", __func__, qid));
5593 if (qid < CIM_NUM_IBQ) {
5596 n = 4 * CIM_IBQ_SIZE;
5597 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5598 rc = t4_read_cim_ibq(sc, qid, buf, n);
5600 /* outbound queue */
5603 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5604 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5605 rc = t4_read_cim_obq(sc, qid, buf, n);
5612 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5614 rc = sysctl_wire_old_buffer(req, 0);
5618 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5624 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5625 for (i = 0, p = buf; i < n; i += 16, p += 4)
5626 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5629 rc = sbuf_finish(sb);
5637 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5639 struct adapter *sc = arg1;
5645 MPASS(chip_id(sc) <= CHELSIO_T5);
5647 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5651 rc = sysctl_wire_old_buffer(req, 0);
5655 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5659 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5662 rc = -t4_cim_read_la(sc, buf, NULL);
5666 sbuf_printf(sb, "Status Data PC%s",
5667 cfg & F_UPDBGLACAPTPCONLY ? "" :
5668 " LS0Stat LS0Addr LS0Data");
5670 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5671 if (cfg & F_UPDBGLACAPTPCONLY) {
5672 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5674 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5675 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5676 p[4] & 0xff, p[5] >> 8);
5677 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5678 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5679 p[1] & 0xf, p[2] >> 4);
5682 "\n %02x %x%07x %x%07x %08x %08x "
5684 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5685 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5690 rc = sbuf_finish(sb);
5698 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5700 struct adapter *sc = arg1;
5706 MPASS(chip_id(sc) > CHELSIO_T5);
5708 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5712 rc = sysctl_wire_old_buffer(req, 0);
5716 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5720 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5723 rc = -t4_cim_read_la(sc, buf, NULL);
5727 sbuf_printf(sb, "Status Inst Data PC%s",
5728 cfg & F_UPDBGLACAPTPCONLY ? "" :
5729 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5731 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5732 if (cfg & F_UPDBGLACAPTPCONLY) {
5733 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5734 p[3] & 0xff, p[2], p[1], p[0]);
5735 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5736 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5737 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5738 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5739 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5740 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5743 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5744 "%08x %08x %08x %08x %08x %08x",
5745 (p[9] >> 16) & 0xff,
5746 p[9] & 0xffff, p[8] >> 16,
5747 p[8] & 0xffff, p[7] >> 16,
5748 p[7] & 0xffff, p[6] >> 16,
5749 p[2], p[1], p[0], p[5], p[4], p[3]);
5753 rc = sbuf_finish(sb);
5761 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5763 struct adapter *sc = arg1;
5769 rc = sysctl_wire_old_buffer(req, 0);
5773 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5777 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5780 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5783 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5784 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5788 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5789 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5790 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5791 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5792 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5793 (p[1] >> 2) | ((p[2] & 3) << 30),
5794 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5798 rc = sbuf_finish(sb);
5805 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5807 struct adapter *sc = arg1;
5813 rc = sysctl_wire_old_buffer(req, 0);
5817 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5821 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5824 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5827 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5828 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5829 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5830 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5831 p[4], p[3], p[2], p[1], p[0]);
5834 sbuf_printf(sb, "\n\nCntl ID Data");
5835 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5836 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5837 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5840 rc = sbuf_finish(sb);
5847 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5849 struct adapter *sc = arg1;
5852 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5853 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5854 uint16_t thres[CIM_NUM_IBQ];
5855 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5856 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5857 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5859 cim_num_obq = sc->chip_params->cim_num_obq;
5861 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5862 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5864 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5865 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5867 nq = CIM_NUM_IBQ + cim_num_obq;
5869 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5871 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5875 t4_read_cimq_cfg(sc, base, size, thres);
5877 rc = sysctl_wire_old_buffer(req, 0);
5881 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5885 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5887 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5888 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5889 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5890 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5891 G_QUEREMFLITS(p[2]) * 16);
5892 for ( ; i < nq; i++, p += 4, wr += 2)
5893 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5894 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5895 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5896 G_QUEREMFLITS(p[2]) * 16);
5898 rc = sbuf_finish(sb);
5905 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5907 struct adapter *sc = arg1;
5910 struct tp_cpl_stats stats;
5912 rc = sysctl_wire_old_buffer(req, 0);
5916 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5920 mtx_lock(&sc->reg_lock);
5921 t4_tp_get_cpl_stats(sc, &stats);
5922 mtx_unlock(&sc->reg_lock);
5924 if (sc->chip_params->nchan > 2) {
5925 sbuf_printf(sb, " channel 0 channel 1"
5926 " channel 2 channel 3");
5927 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5928 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5929 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5930 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5932 sbuf_printf(sb, " channel 0 channel 1");
5933 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5934 stats.req[0], stats.req[1]);
5935 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5936 stats.rsp[0], stats.rsp[1]);
5939 rc = sbuf_finish(sb);
5946 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5948 struct adapter *sc = arg1;
5951 struct tp_usm_stats stats;
5953 rc = sysctl_wire_old_buffer(req, 0);
5957 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5961 t4_get_usm_stats(sc, &stats);
5963 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5964 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5965 sbuf_printf(sb, "Drops: %u", stats.drops);
5967 rc = sbuf_finish(sb);
5973 static const char * const devlog_level_strings[] = {
5974 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5975 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5976 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5977 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5978 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5979 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5982 static const char * const devlog_facility_strings[] = {
5983 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5984 [FW_DEVLOG_FACILITY_CF] = "CF",
5985 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5986 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5987 [FW_DEVLOG_FACILITY_RES] = "RES",
5988 [FW_DEVLOG_FACILITY_HW] = "HW",
5989 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5990 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5991 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5992 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5993 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5994 [FW_DEVLOG_FACILITY_VI] = "VI",
5995 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5996 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5997 [FW_DEVLOG_FACILITY_TM] = "TM",
5998 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5999 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6000 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6001 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6002 [FW_DEVLOG_FACILITY_RI] = "RI",
6003 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6004 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6005 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6006 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6007 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6011 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6013 struct adapter *sc = arg1;
6014 struct devlog_params *dparams = &sc->params.devlog;
6015 struct fw_devlog_e *buf, *e;
6016 int i, j, rc, nentries, first = 0;
6018 uint64_t ftstamp = UINT64_MAX;
6020 if (dparams->addr == 0)
6023 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6027 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6031 nentries = dparams->size / sizeof(struct fw_devlog_e);
6032 for (i = 0; i < nentries; i++) {
6035 if (e->timestamp == 0)
6038 e->timestamp = be64toh(e->timestamp);
6039 e->seqno = be32toh(e->seqno);
6040 for (j = 0; j < 8; j++)
6041 e->params[j] = be32toh(e->params[j]);
6043 if (e->timestamp < ftstamp) {
6044 ftstamp = e->timestamp;
6049 if (buf[first].timestamp == 0)
6050 goto done; /* nothing in the log */
6052 rc = sysctl_wire_old_buffer(req, 0);
6056 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6061 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6062 "Seq#", "Tstamp", "Level", "Facility", "Message");
6067 if (e->timestamp == 0)
6070 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6071 e->seqno, e->timestamp,
6072 (e->level < nitems(devlog_level_strings) ?
6073 devlog_level_strings[e->level] : "UNKNOWN"),
6074 (e->facility < nitems(devlog_facility_strings) ?
6075 devlog_facility_strings[e->facility] : "UNKNOWN"));
6076 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6077 e->params[2], e->params[3], e->params[4],
6078 e->params[5], e->params[6], e->params[7]);
6080 if (++i == nentries)
6082 } while (i != first);
6084 rc = sbuf_finish(sb);
6092 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6094 struct adapter *sc = arg1;
6097 struct tp_fcoe_stats stats[MAX_NCHAN];
6098 int i, nchan = sc->chip_params->nchan;
6100 rc = sysctl_wire_old_buffer(req, 0);
6104 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6108 for (i = 0; i < nchan; i++)
6109 t4_get_fcoe_stats(sc, i, &stats[i]);
6112 sbuf_printf(sb, " channel 0 channel 1"
6113 " channel 2 channel 3");
6114 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6115 stats[0].octets_ddp, stats[1].octets_ddp,
6116 stats[2].octets_ddp, stats[3].octets_ddp);
6117 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6118 stats[0].frames_ddp, stats[1].frames_ddp,
6119 stats[2].frames_ddp, stats[3].frames_ddp);
6120 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6121 stats[0].frames_drop, stats[1].frames_drop,
6122 stats[2].frames_drop, stats[3].frames_drop);
6124 sbuf_printf(sb, " channel 0 channel 1");
6125 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6126 stats[0].octets_ddp, stats[1].octets_ddp);
6127 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6128 stats[0].frames_ddp, stats[1].frames_ddp);
6129 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6130 stats[0].frames_drop, stats[1].frames_drop);
6133 rc = sbuf_finish(sb);
6140 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6142 struct adapter *sc = arg1;
6145 unsigned int map, kbps, ipg, mode;
6146 unsigned int pace_tab[NTX_SCHED];
6148 rc = sysctl_wire_old_buffer(req, 0);
6152 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6156 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6157 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6158 t4_read_pace_tbl(sc, pace_tab);
6160 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6161 "Class IPG (0.1 ns) Flow IPG (us)");
6163 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6164 t4_get_tx_sched(sc, i, &kbps, &ipg);
6165 sbuf_printf(sb, "\n %u %-5s %u ", i,
6166 (mode & (1 << i)) ? "flow" : "class", map & 3);
6168 sbuf_printf(sb, "%9u ", kbps);
6170 sbuf_printf(sb, " disabled ");
6173 sbuf_printf(sb, "%13u ", ipg);
6175 sbuf_printf(sb, " disabled ");
6178 sbuf_printf(sb, "%10u", pace_tab[i]);
6180 sbuf_printf(sb, " disabled");
6183 rc = sbuf_finish(sb);
6190 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6192 struct adapter *sc = arg1;
6196 struct lb_port_stats s[2];
6197 static const char *stat_name[] = {
6198 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6199 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6200 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6201 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6202 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6203 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6204 "BG2FramesTrunc:", "BG3FramesTrunc:"
6207 rc = sysctl_wire_old_buffer(req, 0);
6211 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6215 memset(s, 0, sizeof(s));
6217 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6218 t4_get_lb_stats(sc, i, &s[0]);
6219 t4_get_lb_stats(sc, i + 1, &s[1]);
6223 sbuf_printf(sb, "%s Loopback %u"
6224 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6226 for (j = 0; j < nitems(stat_name); j++)
6227 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6231 rc = sbuf_finish(sb);
6238 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6241 struct port_info *pi = arg1;
6244 rc = sysctl_wire_old_buffer(req, 0);
6247 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6251 if (pi->linkdnrc < 0)
6252 sbuf_printf(sb, "n/a");
6254 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6256 rc = sbuf_finish(sb);
6269 mem_desc_cmp(const void *a, const void *b)
6271 return ((const struct mem_desc *)a)->base -
6272 ((const struct mem_desc *)b)->base;
6276 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6284 size = to - from + 1;
6288 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6289 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6293 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6295 struct adapter *sc = arg1;
6298 uint32_t lo, hi, used, alloc;
6299 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6300 static const char *region[] = {
6301 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6302 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6303 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6304 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6305 "RQUDP region:", "PBL region:", "TXPBL region:",
6306 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6309 struct mem_desc avail[4];
6310 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6311 struct mem_desc *md = mem;
6313 rc = sysctl_wire_old_buffer(req, 0);
6317 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6321 for (i = 0; i < nitems(mem); i++) {
6326 /* Find and sort the populated memory ranges */
6328 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6329 if (lo & F_EDRAM0_ENABLE) {
6330 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6331 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6332 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6336 if (lo & F_EDRAM1_ENABLE) {
6337 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6338 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6339 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6343 if (lo & F_EXT_MEM_ENABLE) {
6344 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6345 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6346 avail[i].limit = avail[i].base +
6347 (G_EXT_MEM_SIZE(hi) << 20);
6348 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6351 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6352 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6353 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6354 avail[i].limit = avail[i].base +
6355 (G_EXT_MEM1_SIZE(hi) << 20);
6359 if (!i) /* no memory available */
6361 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6363 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6364 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6365 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6366 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6367 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6368 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6369 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6370 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6371 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6373 /* the next few have explicit upper bounds */
6374 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6375 md->limit = md->base - 1 +
6376 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6377 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6380 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6381 md->limit = md->base - 1 +
6382 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6383 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6386 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6387 if (chip_id(sc) <= CHELSIO_T5)
6388 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6390 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6394 md->idx = nitems(region); /* hide it */
6398 #define ulp_region(reg) \
6399 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6400 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6402 ulp_region(RX_ISCSI);
6403 ulp_region(RX_TDDP);
6405 ulp_region(RX_STAG);
6407 ulp_region(RX_RQUDP);
6413 md->idx = nitems(region);
6416 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6417 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6420 if (sge_ctrl & F_VFIFO_ENABLE)
6421 size = G_DBVFIFO_SIZE(fifo_size);
6423 size = G_T6_DBVFIFO_SIZE(fifo_size);
6426 md->base = G_BASEADDR(t4_read_reg(sc,
6427 A_SGE_DBVFIFO_BADDR));
6428 md->limit = md->base + (size << 2) - 1;
6433 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6436 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6440 md->base = sc->vres.ocq.start;
6441 if (sc->vres.ocq.size)
6442 md->limit = md->base + sc->vres.ocq.size - 1;
6444 md->idx = nitems(region); /* hide it */
6447 /* add any address-space holes, there can be up to 3 */
6448 for (n = 0; n < i - 1; n++)
6449 if (avail[n].limit < avail[n + 1].base)
6450 (md++)->base = avail[n].limit;
6452 (md++)->base = avail[n].limit;
6455 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6457 for (lo = 0; lo < i; lo++)
6458 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6459 avail[lo].limit - 1);
6461 sbuf_printf(sb, "\n");
6462 for (i = 0; i < n; i++) {
6463 if (mem[i].idx >= nitems(region))
6464 continue; /* skip holes */
6466 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6467 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6471 sbuf_printf(sb, "\n");
6472 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6473 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6474 mem_region_show(sb, "uP RAM:", lo, hi);
6476 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6477 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6478 mem_region_show(sb, "uP Extmem2:", lo, hi);
6480 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6481 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6483 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6484 (lo & F_PMRXNUMCHN) ? 2 : 1);
6486 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6487 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6488 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6490 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6491 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6492 sbuf_printf(sb, "%u p-structs\n",
6493 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6495 for (i = 0; i < 4; i++) {
6496 if (chip_id(sc) > CHELSIO_T5)
6497 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6499 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6501 used = G_T5_USED(lo);
6502 alloc = G_T5_ALLOC(lo);
6505 alloc = G_ALLOC(lo);
6507 /* For T6 these are MAC buffer groups */
6508 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6511 for (i = 0; i < sc->chip_params->nchan; i++) {
6512 if (chip_id(sc) > CHELSIO_T5)
6513 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6515 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6517 used = G_T5_USED(lo);
6518 alloc = G_T5_ALLOC(lo);
6521 alloc = G_ALLOC(lo);
6523 /* For T6 these are MAC buffer groups */
6525 "\nLoopback %d using %u pages out of %u allocated",
6529 rc = sbuf_finish(sb);
6536 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6540 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6544 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6546 struct adapter *sc = arg1;
6550 MPASS(chip_id(sc) <= CHELSIO_T5);
6552 rc = sysctl_wire_old_buffer(req, 0);
6556 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6561 "Idx Ethernet address Mask Vld Ports PF"
6562 " VF Replication P0 P1 P2 P3 ML");
6563 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6564 uint64_t tcamx, tcamy, mask;
6565 uint32_t cls_lo, cls_hi;
6566 uint8_t addr[ETHER_ADDR_LEN];
6568 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6569 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6572 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6573 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6574 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6575 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6576 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6577 addr[3], addr[4], addr[5], (uintmax_t)mask,
6578 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6579 G_PORTMAP(cls_hi), G_PF(cls_lo),
6580 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6582 if (cls_lo & F_REPLICATE) {
6583 struct fw_ldst_cmd ldst_cmd;
6585 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6586 ldst_cmd.op_to_addrspace =
6587 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6588 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6589 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6590 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6591 ldst_cmd.u.mps.rplc.fid_idx =
6592 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6593 V_FW_LDST_CMD_IDX(i));
6595 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6599 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6600 sizeof(ldst_cmd), &ldst_cmd);
6601 end_synchronized_op(sc, 0);
6604 sbuf_printf(sb, "%36d", rc);
6607 sbuf_printf(sb, " %08x %08x %08x %08x",
6608 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6609 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6610 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6611 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6614 sbuf_printf(sb, "%36s", "");
6616 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6617 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6618 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6622 (void) sbuf_finish(sb);
6624 rc = sbuf_finish(sb);
6631 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6633 struct adapter *sc = arg1;
6637 MPASS(chip_id(sc) > CHELSIO_T5);
6639 rc = sysctl_wire_old_buffer(req, 0);
6643 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6647 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6648 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6650 " P0 P1 P2 P3 ML\n");
6652 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6653 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6655 uint64_t tcamx, tcamy, val, mask;
6656 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6657 uint8_t addr[ETHER_ADDR_LEN];
6659 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6661 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6663 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6664 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6665 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6666 tcamy = G_DMACH(val) << 32;
6667 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6668 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6669 lookup_type = G_DATALKPTYPE(data2);
6670 port_num = G_DATAPORTNUM(data2);
6671 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6672 /* Inner header VNI */
6673 vniy = ((data2 & F_DATAVIDH2) << 23) |
6674 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6675 dip_hit = data2 & F_DATADIPHIT;
6680 vlan_vld = data2 & F_DATAVIDH2;
6681 ivlan = G_VIDL(val);
6684 ctl |= V_CTLXYBITSEL(1);
6685 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6686 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6687 tcamx = G_DMACH(val) << 32;
6688 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6689 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6690 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6691 /* Inner header VNI mask */
6692 vnix = ((data2 & F_DATAVIDH2) << 23) |
6693 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6699 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6701 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6702 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6704 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6705 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6706 "%012jx %06x %06x - - %3c"
6707 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6708 addr[1], addr[2], addr[3], addr[4], addr[5],
6709 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6710 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6711 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6712 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6714 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6715 "%012jx - - ", i, addr[0], addr[1],
6716 addr[2], addr[3], addr[4], addr[5],
6720 sbuf_printf(sb, "%4u Y ", ivlan);
6722 sbuf_printf(sb, " - N ");
6724 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6725 lookup_type ? 'I' : 'O', port_num,
6726 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6727 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6728 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6732 if (cls_lo & F_T6_REPLICATE) {
6733 struct fw_ldst_cmd ldst_cmd;
6735 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6736 ldst_cmd.op_to_addrspace =
6737 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6738 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6739 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6740 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6741 ldst_cmd.u.mps.rplc.fid_idx =
6742 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6743 V_FW_LDST_CMD_IDX(i));
6745 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6749 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6750 sizeof(ldst_cmd), &ldst_cmd);
6751 end_synchronized_op(sc, 0);
6754 sbuf_printf(sb, "%72d", rc);
6757 sbuf_printf(sb, " %08x %08x %08x %08x"
6758 " %08x %08x %08x %08x",
6759 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6760 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6761 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6762 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6763 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6764 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6765 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6766 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6769 sbuf_printf(sb, "%72s", "");
6771 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6772 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6773 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6774 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6778 (void) sbuf_finish(sb);
6780 rc = sbuf_finish(sb);
6787 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6789 struct adapter *sc = arg1;
6792 uint16_t mtus[NMTUS];
6794 rc = sysctl_wire_old_buffer(req, 0);
6798 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6802 t4_read_mtu_tbl(sc, mtus, NULL);
6804 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6805 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6806 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6807 mtus[14], mtus[15]);
6809 rc = sbuf_finish(sb);
6816 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6818 struct adapter *sc = arg1;
6821 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6822 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6823 static const char *tx_stats[MAX_PM_NSTATS] = {
6824 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6825 "Tx FIFO wait", NULL, "Tx latency"
6827 static const char *rx_stats[MAX_PM_NSTATS] = {
6828 "Read:", "Write bypass:", "Write mem:", "Flush:",
6829 " Rx FIFO wait", NULL, "Rx latency"
6832 rc = sysctl_wire_old_buffer(req, 0);
6836 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6840 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6841 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6843 sbuf_printf(sb, " Tx pcmds Tx bytes");
6844 for (i = 0; i < 4; i++) {
6845 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6849 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6850 for (i = 0; i < 4; i++) {
6851 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6855 if (chip_id(sc) > CHELSIO_T5) {
6857 "\n Total wait Total occupancy");
6858 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6860 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6864 MPASS(i < nitems(tx_stats));
6867 "\n Reads Total wait");
6868 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6870 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6874 rc = sbuf_finish(sb);
6881 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6883 struct adapter *sc = arg1;
6886 struct tp_rdma_stats stats;
6888 rc = sysctl_wire_old_buffer(req, 0);
6892 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6896 mtx_lock(&sc->reg_lock);
6897 t4_tp_get_rdma_stats(sc, &stats);
6898 mtx_unlock(&sc->reg_lock);
6900 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6901 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6903 rc = sbuf_finish(sb);
6910 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6912 struct adapter *sc = arg1;
6915 struct tp_tcp_stats v4, v6;
6917 rc = sysctl_wire_old_buffer(req, 0);
6921 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6925 mtx_lock(&sc->reg_lock);
6926 t4_tp_get_tcp_stats(sc, &v4, &v6);
6927 mtx_unlock(&sc->reg_lock);
6931 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6932 v4.tcp_out_rsts, v6.tcp_out_rsts);
6933 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6934 v4.tcp_in_segs, v6.tcp_in_segs);
6935 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6936 v4.tcp_out_segs, v6.tcp_out_segs);
6937 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6938 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6940 rc = sbuf_finish(sb);
6947 sysctl_tids(SYSCTL_HANDLER_ARGS)
6949 struct adapter *sc = arg1;
6952 struct tid_info *t = &sc->tids;
6954 rc = sysctl_wire_old_buffer(req, 0);
6958 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6963 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6968 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6969 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6972 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6973 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6976 sbuf_printf(sb, "TID range: %u-%u",
6977 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6981 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6982 sbuf_printf(sb, ", in use: %u\n",
6983 atomic_load_acq_int(&t->tids_in_use));
6987 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6988 t->stid_base + t->nstids - 1, t->stids_in_use);
6992 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6993 t->ftid_base + t->nftids - 1);
6997 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6998 t->etid_base + t->netids - 1);
7001 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7002 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7003 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7005 rc = sbuf_finish(sb);
7012 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7014 struct adapter *sc = arg1;
7017 struct tp_err_stats stats;
7019 rc = sysctl_wire_old_buffer(req, 0);
7023 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7027 mtx_lock(&sc->reg_lock);
7028 t4_tp_get_err_stats(sc, &stats);
7029 mtx_unlock(&sc->reg_lock);
7031 if (sc->chip_params->nchan > 2) {
7032 sbuf_printf(sb, " channel 0 channel 1"
7033 " channel 2 channel 3\n");
7034 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7035 stats.mac_in_errs[0], stats.mac_in_errs[1],
7036 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7037 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7038 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7039 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7040 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7041 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7042 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7043 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7044 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7045 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7046 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7047 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7048 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7049 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7050 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7051 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7052 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7053 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7054 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7055 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7056 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7057 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7059 sbuf_printf(sb, " channel 0 channel 1\n");
7060 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7061 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7062 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7063 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7064 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7065 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7066 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7067 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7068 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7069 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7070 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7071 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7072 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7073 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7074 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7075 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7078 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7079 stats.ofld_no_neigh, stats.ofld_cong_defer);
7081 rc = sbuf_finish(sb);
7088 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7090 struct adapter *sc = arg1;
7091 struct tp_params *tpp = &sc->params.tp;
7095 mask = tpp->la_mask >> 16;
7096 rc = sysctl_handle_int(oidp, &mask, 0, req);
7097 if (rc != 0 || req->newptr == NULL)
7101 tpp->la_mask = mask << 16;
7102 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7114 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7120 uint64_t mask = (1ULL << f->width) - 1;
7121 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7122 ((uintmax_t)v >> f->start) & mask);
7124 if (line_size + len >= 79) {
7126 sbuf_printf(sb, "\n ");
7128 sbuf_printf(sb, "%s ", buf);
7129 line_size += len + 1;
7132 sbuf_printf(sb, "\n");
7135 static const struct field_desc tp_la0[] = {
7136 { "RcfOpCodeOut", 60, 4 },
7138 { "WcfState", 52, 4 },
7139 { "RcfOpcSrcOut", 50, 2 },
7140 { "CRxError", 49, 1 },
7141 { "ERxError", 48, 1 },
7142 { "SanityFailed", 47, 1 },
7143 { "SpuriousMsg", 46, 1 },
7144 { "FlushInputMsg", 45, 1 },
7145 { "FlushInputCpl", 44, 1 },
7146 { "RssUpBit", 43, 1 },
7147 { "RssFilterHit", 42, 1 },
7149 { "InitTcb", 31, 1 },
7150 { "LineNumber", 24, 7 },
7152 { "EdataOut", 22, 1 },
7154 { "CdataOut", 20, 1 },
7155 { "EreadPdu", 19, 1 },
7156 { "CreadPdu", 18, 1 },
7157 { "TunnelPkt", 17, 1 },
7158 { "RcfPeerFin", 16, 1 },
7159 { "RcfReasonOut", 12, 4 },
7160 { "TxCchannel", 10, 2 },
7161 { "RcfTxChannel", 8, 2 },
7162 { "RxEchannel", 6, 2 },
7163 { "RcfRxChannel", 5, 1 },
7164 { "RcfDataOutSrdy", 4, 1 },
7166 { "RxOoDvld", 2, 1 },
7167 { "RxCongestion", 1, 1 },
7168 { "TxCongestion", 0, 1 },
7172 static const struct field_desc tp_la1[] = {
7173 { "CplCmdIn", 56, 8 },
7174 { "CplCmdOut", 48, 8 },
7175 { "ESynOut", 47, 1 },
7176 { "EAckOut", 46, 1 },
7177 { "EFinOut", 45, 1 },
7178 { "ERstOut", 44, 1 },
7183 { "DataIn", 39, 1 },
7184 { "DataInVld", 38, 1 },
7186 { "RxBufEmpty", 36, 1 },
7188 { "RxFbCongestion", 34, 1 },
7189 { "TxFbCongestion", 33, 1 },
7190 { "TxPktSumSrdy", 32, 1 },
7191 { "RcfUlpType", 28, 4 },
7193 { "Ebypass", 26, 1 },
7195 { "Static0", 24, 1 },
7197 { "Cbypass", 22, 1 },
7199 { "CPktOut", 20, 1 },
7200 { "RxPagePoolFull", 18, 2 },
7201 { "RxLpbkPkt", 17, 1 },
7202 { "TxLpbkPkt", 16, 1 },
7203 { "RxVfValid", 15, 1 },
7204 { "SynLearned", 14, 1 },
7205 { "SetDelEntry", 13, 1 },
7206 { "SetInvEntry", 12, 1 },
7207 { "CpcmdDvld", 11, 1 },
7208 { "CpcmdSave", 10, 1 },
7209 { "RxPstructsFull", 8, 2 },
7210 { "EpcmdDvld", 7, 1 },
7211 { "EpcmdFlush", 6, 1 },
7212 { "EpcmdTrimPrefix", 5, 1 },
7213 { "EpcmdTrimPostfix", 4, 1 },
7214 { "ERssIp4Pkt", 3, 1 },
7215 { "ERssIp6Pkt", 2, 1 },
7216 { "ERssTcpUdpPkt", 1, 1 },
7217 { "ERssFceFipPkt", 0, 1 },
7221 static const struct field_desc tp_la2[] = {
7222 { "CplCmdIn", 56, 8 },
7223 { "MpsVfVld", 55, 1 },
7230 { "DataIn", 39, 1 },
7231 { "DataInVld", 38, 1 },
7233 { "RxBufEmpty", 36, 1 },
7235 { "RxFbCongestion", 34, 1 },
7236 { "TxFbCongestion", 33, 1 },
7237 { "TxPktSumSrdy", 32, 1 },
7238 { "RcfUlpType", 28, 4 },
7240 { "Ebypass", 26, 1 },
7242 { "Static0", 24, 1 },
7244 { "Cbypass", 22, 1 },
7246 { "CPktOut", 20, 1 },
7247 { "RxPagePoolFull", 18, 2 },
7248 { "RxLpbkPkt", 17, 1 },
7249 { "TxLpbkPkt", 16, 1 },
7250 { "RxVfValid", 15, 1 },
7251 { "SynLearned", 14, 1 },
7252 { "SetDelEntry", 13, 1 },
7253 { "SetInvEntry", 12, 1 },
7254 { "CpcmdDvld", 11, 1 },
7255 { "CpcmdSave", 10, 1 },
7256 { "RxPstructsFull", 8, 2 },
7257 { "EpcmdDvld", 7, 1 },
7258 { "EpcmdFlush", 6, 1 },
7259 { "EpcmdTrimPrefix", 5, 1 },
7260 { "EpcmdTrimPostfix", 4, 1 },
7261 { "ERssIp4Pkt", 3, 1 },
7262 { "ERssIp6Pkt", 2, 1 },
7263 { "ERssTcpUdpPkt", 1, 1 },
7264 { "ERssFceFipPkt", 0, 1 },
7269 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7272 field_desc_show(sb, *p, tp_la0);
7276 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7280 sbuf_printf(sb, "\n");
7281 field_desc_show(sb, p[0], tp_la0);
7282 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7283 field_desc_show(sb, p[1], tp_la0);
7287 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7291 sbuf_printf(sb, "\n");
7292 field_desc_show(sb, p[0], tp_la0);
7293 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7294 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7298 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7300 struct adapter *sc = arg1;
7305 void (*show_func)(struct sbuf *, uint64_t *, int);
7307 rc = sysctl_wire_old_buffer(req, 0);
7311 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7315 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7317 t4_tp_read_la(sc, buf, NULL);
7320 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7323 show_func = tp_la_show2;
7327 show_func = tp_la_show3;
7331 show_func = tp_la_show;
7334 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7335 (*show_func)(sb, p, i);
7337 rc = sbuf_finish(sb);
7344 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7346 struct adapter *sc = arg1;
7349 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7351 rc = sysctl_wire_old_buffer(req, 0);
7355 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7359 t4_get_chan_txrate(sc, nrate, orate);
7361 if (sc->chip_params->nchan > 2) {
7362 sbuf_printf(sb, " channel 0 channel 1"
7363 " channel 2 channel 3\n");
7364 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7365 nrate[0], nrate[1], nrate[2], nrate[3]);
7366 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7367 orate[0], orate[1], orate[2], orate[3]);
7369 sbuf_printf(sb, " channel 0 channel 1\n");
7370 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7371 nrate[0], nrate[1]);
7372 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7373 orate[0], orate[1]);
7376 rc = sbuf_finish(sb);
7383 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7385 struct adapter *sc = arg1;
7390 rc = sysctl_wire_old_buffer(req, 0);
7394 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7398 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7401 t4_ulprx_read_la(sc, buf);
7404 sbuf_printf(sb, " Pcmd Type Message"
7406 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7407 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7408 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7411 rc = sbuf_finish(sb);
7418 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7420 struct adapter *sc = arg1;
7424 rc = sysctl_wire_old_buffer(req, 0);
7428 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7432 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7433 if (G_STATSOURCE_T5(v) == 7) {
7434 if (G_STATMODE(v) == 0) {
7435 sbuf_printf(sb, "total %d, incomplete %d",
7436 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7437 t4_read_reg(sc, A_SGE_STAT_MATCH));
7438 } else if (G_STATMODE(v) == 1) {
7439 sbuf_printf(sb, "total %d, data overflow %d",
7440 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7441 t4_read_reg(sc, A_SGE_STAT_MATCH));
7444 rc = sbuf_finish(sb);
7451 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7453 struct adapter *sc = arg1;
7454 struct tx_sched_class *tc;
7455 struct t4_sched_class_params p;
7457 int i, rc, port_id, flags, mbps, gbps;
7459 rc = sysctl_wire_old_buffer(req, 0);
7463 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7467 port_id = arg2 >> 16;
7468 MPASS(port_id < sc->params.nports);
7469 MPASS(sc->port[port_id] != NULL);
7471 MPASS(i < sc->chip_params->nsched_cls);
7472 tc = &sc->port[port_id]->tc[i];
7474 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7480 end_synchronized_op(sc, LOCK_HELD);
7482 if ((flags & TX_SC_OK) == 0) {
7483 sbuf_printf(sb, "none");
7487 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7488 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7490 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7491 sbuf_printf(sb, "cl-rl");
7492 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7493 sbuf_printf(sb, "ch-rl");
7499 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7500 /* XXX: top speed or actual link speed? */
7501 gbps = port_top_speed(sc->port[port_id]);
7502 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7504 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7505 switch (p.rateunit) {
7506 case SCHED_CLASS_RATEUNIT_BITS:
7507 mbps = p.maxrate / 1000;
7508 gbps = p.maxrate / 1000000;
7509 if (p.maxrate == gbps * 1000000)
7510 sbuf_printf(sb, " %uGbps", gbps);
7511 else if (p.maxrate == mbps * 1000)
7512 sbuf_printf(sb, " %uMbps", mbps);
7514 sbuf_printf(sb, " %uKbps", p.maxrate);
7516 case SCHED_CLASS_RATEUNIT_PKTS:
7517 sbuf_printf(sb, " %upps", p.maxrate);
7526 case SCHED_CLASS_MODE_CLASS:
7527 sbuf_printf(sb, " aggregate");
7529 case SCHED_CLASS_MODE_FLOW:
7530 sbuf_printf(sb, " per-flow");
7539 rc = sbuf_finish(sb);
7548 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7550 u_int rem = val % factor;
7553 snprintf(buf, len, "%u", val / factor);
7555 while (rem % 10 == 0)
7557 snprintf(buf, len, "%u.%u", val / factor, rem);
7562 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7564 struct adapter *sc = arg1;
7567 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7569 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7573 re = G_TIMERRESOLUTION(res);
7576 /* TCP timestamp tick */
7577 re = G_TIMESTAMPRESOLUTION(res);
7581 re = G_DELAYEDACKRESOLUTION(res);
7587 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7589 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7593 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7595 struct adapter *sc = arg1;
7596 u_int res, dack_re, v;
7597 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7599 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7600 dack_re = G_DELAYEDACKRESOLUTION(res);
7601 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7603 return (sysctl_handle_int(oidp, &v, 0, req));
7607 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7609 struct adapter *sc = arg1;
7612 u_long tp_tick_us, v;
7613 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7615 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7616 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7617 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7618 reg == A_TP_FINWAIT2_TIMER);
7620 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7621 tp_tick_us = (cclk_ps << tre) / 1000000;
7623 if (reg == A_TP_INIT_SRTT)
7624 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7626 v = tp_tick_us * t4_read_reg(sc, reg);
7628 return (sysctl_handle_long(oidp, &v, 0, req));
7633 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7637 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7638 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7640 if (fconf & F_FRAGMENTATION)
7641 mode |= T4_FILTER_IP_FRAGMENT;
7643 if (fconf & F_MPSHITTYPE)
7644 mode |= T4_FILTER_MPS_HIT_TYPE;
7646 if (fconf & F_MACMATCH)
7647 mode |= T4_FILTER_MAC_IDX;
7649 if (fconf & F_ETHERTYPE)
7650 mode |= T4_FILTER_ETH_TYPE;
7652 if (fconf & F_PROTOCOL)
7653 mode |= T4_FILTER_IP_PROTO;
7656 mode |= T4_FILTER_IP_TOS;
7659 mode |= T4_FILTER_VLAN;
7661 if (fconf & F_VNIC_ID) {
7662 mode |= T4_FILTER_VNIC;
7664 mode |= T4_FILTER_IC_VNIC;
7668 mode |= T4_FILTER_PORT;
7671 mode |= T4_FILTER_FCoE;
7677 mode_to_fconf(uint32_t mode)
7681 if (mode & T4_FILTER_IP_FRAGMENT)
7682 fconf |= F_FRAGMENTATION;
7684 if (mode & T4_FILTER_MPS_HIT_TYPE)
7685 fconf |= F_MPSHITTYPE;
7687 if (mode & T4_FILTER_MAC_IDX)
7688 fconf |= F_MACMATCH;
7690 if (mode & T4_FILTER_ETH_TYPE)
7691 fconf |= F_ETHERTYPE;
7693 if (mode & T4_FILTER_IP_PROTO)
7694 fconf |= F_PROTOCOL;
7696 if (mode & T4_FILTER_IP_TOS)
7699 if (mode & T4_FILTER_VLAN)
7702 if (mode & T4_FILTER_VNIC)
7705 if (mode & T4_FILTER_PORT)
7708 if (mode & T4_FILTER_FCoE)
7715 mode_to_iconf(uint32_t mode)
7718 if (mode & T4_FILTER_IC_VNIC)
7723 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7724 struct t4_filter_specification *fs)
7726 struct tp_params *tpp = &sc->params.tp;
7729 if (fs->val.frag || fs->mask.frag)
7730 fconf |= F_FRAGMENTATION;
7732 if (fs->val.matchtype || fs->mask.matchtype)
7733 fconf |= F_MPSHITTYPE;
7735 if (fs->val.macidx || fs->mask.macidx)
7736 fconf |= F_MACMATCH;
7738 if (fs->val.ethtype || fs->mask.ethtype)
7739 fconf |= F_ETHERTYPE;
7741 if (fs->val.proto || fs->mask.proto)
7742 fconf |= F_PROTOCOL;
7744 if (fs->val.tos || fs->mask.tos)
7747 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7750 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7752 if (tpp->ingress_config & F_VNIC)
7756 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7758 if ((tpp->ingress_config & F_VNIC) == 0)
7762 if (fs->val.iport || fs->mask.iport)
7765 if (fs->val.fcoe || fs->mask.fcoe)
7768 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7775 get_filter_mode(struct adapter *sc, uint32_t *mode)
7777 struct tp_params *tpp = &sc->params.tp;
7780 * We trust the cached values of the relevant TP registers. This means
7781 * things work reliably only if writes to those registers are always via
7782 * t4_set_filter_mode.
7784 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7790 set_filter_mode(struct adapter *sc, uint32_t mode)
7792 struct tp_params *tpp = &sc->params.tp;
7793 uint32_t fconf, iconf;
7796 iconf = mode_to_iconf(mode);
7797 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7799 * For now we just complain if A_TP_INGRESS_CONFIG is not
7800 * already set to the correct value for the requested filter
7801 * mode. It's not clear if it's safe to write to this register
7802 * on the fly. (And we trust the cached value of the register).
7807 fconf = mode_to_fconf(mode);
7809 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7814 if (sc->tids.ftids_in_use > 0) {
7820 if (uld_active(sc, ULD_TOM)) {
7826 rc = -t4_set_filter_mode(sc, fconf);
7828 end_synchronized_op(sc, LOCK_HELD);
7832 static inline uint64_t
7833 get_filter_hits(struct adapter *sc, uint32_t fid)
7837 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7838 (fid + sc->tids.ftid_base) * TCB_SIZE;
7843 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7844 return (be64toh(hits));
7848 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7849 return (be32toh(hits));
7854 get_filter(struct adapter *sc, struct t4_filter *t)
7856 int i, rc, nfilters = sc->tids.nftids;
7857 struct filter_entry *f;
7859 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7864 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7865 t->idx >= nfilters) {
7866 t->idx = 0xffffffff;
7870 f = &sc->tids.ftid_tab[t->idx];
7871 for (i = t->idx; i < nfilters; i++, f++) {
7874 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7875 t->smtidx = f->smtidx;
7877 t->hits = get_filter_hits(sc, t->idx);
7879 t->hits = UINT64_MAX;
7886 t->idx = 0xffffffff;
7888 end_synchronized_op(sc, LOCK_HELD);
7893 set_filter(struct adapter *sc, struct t4_filter *t)
7895 unsigned int nfilters, nports;
7896 struct filter_entry *f;
7899 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7903 nfilters = sc->tids.nftids;
7904 nports = sc->params.nports;
7906 if (nfilters == 0) {
7911 if (t->idx >= nfilters) {
7916 /* Validate against the global filter mode and ingress config */
7917 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7921 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7926 if (t->fs.val.iport >= nports) {
7931 /* Can't specify an iq if not steering to it */
7932 if (!t->fs.dirsteer && t->fs.iq) {
7937 /* IPv6 filter idx must be 4 aligned */
7938 if (t->fs.type == 1 &&
7939 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7944 if (!(sc->flags & FULL_INIT_DONE) &&
7945 ((rc = adapter_full_init(sc)) != 0))
7948 if (sc->tids.ftid_tab == NULL) {
7949 KASSERT(sc->tids.ftids_in_use == 0,
7950 ("%s: no memory allocated but filters_in_use > 0",
7953 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7954 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7955 if (sc->tids.ftid_tab == NULL) {
7959 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7962 for (i = 0; i < 4; i++) {
7963 f = &sc->tids.ftid_tab[t->idx + i];
7965 if (f->pending || f->valid) {
7974 if (t->fs.type == 0)
7978 f = &sc->tids.ftid_tab[t->idx];
7981 rc = set_filter_wr(sc, t->idx);
7983 end_synchronized_op(sc, 0);
7986 mtx_lock(&sc->tids.ftid_lock);
7988 if (f->pending == 0) {
7989 rc = f->valid ? 0 : EIO;
7993 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7994 PCATCH, "t4setfw", 0)) {
7999 mtx_unlock(&sc->tids.ftid_lock);
8005 del_filter(struct adapter *sc, struct t4_filter *t)
8007 unsigned int nfilters;
8008 struct filter_entry *f;
8011 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8015 nfilters = sc->tids.nftids;
8017 if (nfilters == 0) {
8022 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8023 t->idx >= nfilters) {
8028 if (!(sc->flags & FULL_INIT_DONE)) {
8033 f = &sc->tids.ftid_tab[t->idx];
8045 t->fs = f->fs; /* extra info for the caller */
8046 rc = del_filter_wr(sc, t->idx);
8050 end_synchronized_op(sc, 0);
8053 mtx_lock(&sc->tids.ftid_lock);
8055 if (f->pending == 0) {
8056 rc = f->valid ? EIO : 0;
8060 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8061 PCATCH, "t4delfw", 0)) {
8066 mtx_unlock(&sc->tids.ftid_lock);
8073 clear_filter(struct filter_entry *f)
8076 t4_l2t_release(f->l2t);
8078 bzero(f, sizeof (*f));
8082 set_filter_wr(struct adapter *sc, int fidx)
8084 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8085 struct fw_filter_wr *fwr;
8086 unsigned int ftid, vnic_vld, vnic_vld_mask;
8087 struct wrq_cookie cookie;
8089 ASSERT_SYNCHRONIZED_OP(sc);
8091 if (f->fs.newdmac || f->fs.newvlan) {
8092 /* This filter needs an L2T entry; allocate one. */
8093 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8096 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8098 t4_l2t_release(f->l2t);
8104 /* Already validated against fconf, iconf */
8105 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8106 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8107 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8111 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8116 ftid = sc->tids.ftid_base + fidx;
8118 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8121 bzero(fwr, sizeof(*fwr));
8123 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8124 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8126 htobe32(V_FW_FILTER_WR_TID(ftid) |
8127 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8128 V_FW_FILTER_WR_NOREPLY(0) |
8129 V_FW_FILTER_WR_IQ(f->fs.iq));
8130 fwr->del_filter_to_l2tix =
8131 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8132 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8133 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8134 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8135 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8136 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8137 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8138 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8139 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8140 f->fs.newvlan == VLAN_REWRITE) |
8141 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8142 f->fs.newvlan == VLAN_REWRITE) |
8143 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8144 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8145 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8146 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8147 fwr->ethtype = htobe16(f->fs.val.ethtype);
8148 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8149 fwr->frag_to_ovlan_vldm =
8150 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8151 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8152 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8153 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8154 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8155 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8157 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8158 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8159 fwr->maci_to_matchtypem =
8160 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8161 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8162 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8163 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8164 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8165 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8166 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8167 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8168 fwr->ptcl = f->fs.val.proto;
8169 fwr->ptclm = f->fs.mask.proto;
8170 fwr->ttyp = f->fs.val.tos;
8171 fwr->ttypm = f->fs.mask.tos;
8172 fwr->ivlan = htobe16(f->fs.val.vlan);
8173 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8174 fwr->ovlan = htobe16(f->fs.val.vnic);
8175 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8176 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8177 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8178 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8179 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8180 fwr->lp = htobe16(f->fs.val.dport);
8181 fwr->lpm = htobe16(f->fs.mask.dport);
8182 fwr->fp = htobe16(f->fs.val.sport);
8183 fwr->fpm = htobe16(f->fs.mask.sport);
8185 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8188 sc->tids.ftids_in_use++;
8190 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8195 del_filter_wr(struct adapter *sc, int fidx)
8197 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8198 struct fw_filter_wr *fwr;
8200 struct wrq_cookie cookie;
8202 ftid = sc->tids.ftid_base + fidx;
8204 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8207 bzero(fwr, sizeof (*fwr));
8209 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8212 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8217 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8219 struct adapter *sc = iq->adapter;
8220 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8221 unsigned int idx = GET_TID(rpl);
8223 struct filter_entry *f;
8225 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8227 MPASS(iq == &sc->sge.fwq);
8228 MPASS(is_ftid(sc, idx));
8230 idx -= sc->tids.ftid_base;
8231 f = &sc->tids.ftid_tab[idx];
8232 rc = G_COOKIE(rpl->cookie);
8234 mtx_lock(&sc->tids.ftid_lock);
8235 if (rc == FW_FILTER_WR_FLT_ADDED) {
8236 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8238 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8239 f->pending = 0; /* asynchronous setup completed */
8242 if (rc != FW_FILTER_WR_FLT_DELETED) {
8243 /* Add or delete failed, display an error */
8245 "filter %u setup failed with error %u\n",
8250 sc->tids.ftids_in_use--;
8252 wakeup(&sc->tids.ftid_tab);
8253 mtx_unlock(&sc->tids.ftid_lock);
8259 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8262 MPASS(iq->set_tcb_rpl != NULL);
8263 return (iq->set_tcb_rpl(iq, rss, m));
8267 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8270 MPASS(iq->l2t_write_rpl != NULL);
8271 return (iq->l2t_write_rpl(iq, rss, m));
8275 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8279 if (cntxt->cid > M_CTXTQID)
8282 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8283 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8286 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8290 if (sc->flags & FW_OK) {
8291 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8298 * Read via firmware failed or wasn't even attempted. Read directly via
8301 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8303 end_synchronized_op(sc, 0);
8308 load_fw(struct adapter *sc, struct t4_data *fw)
8313 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8317 if (sc->flags & FULL_INIT_DONE) {
8322 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8323 if (fw_data == NULL) {
8328 rc = copyin(fw->data, fw_data, fw->len);
8330 rc = -t4_load_fw(sc, fw_data, fw->len);
8332 free(fw_data, M_CXGBE);
8334 end_synchronized_op(sc, 0);
8338 #define MAX_READ_BUF_SIZE (128 * 1024)
8340 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8342 uint32_t addr, remaining, n;
8347 rc = validate_mem_range(sc, mr->addr, mr->len);
8351 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8353 remaining = mr->len;
8354 dst = (void *)mr->data;
8357 n = min(remaining, MAX_READ_BUF_SIZE);
8358 read_via_memwin(sc, 2, addr, buf, n);
8360 rc = copyout(buf, dst, n);
8372 #undef MAX_READ_BUF_SIZE
8375 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8379 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8382 if (i2cd->len > sizeof(i2cd->data))
8385 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8388 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8389 i2cd->offset, i2cd->len, &i2cd->data[0]);
8390 end_synchronized_op(sc, 0);
8396 in_range(int val, int lo, int hi)
8399 return (val < 0 || (val <= hi && val >= lo));
8403 set_sched_class_config(struct adapter *sc, int minmax)
8410 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8413 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8414 end_synchronized_op(sc, 0);
8420 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8423 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8424 struct port_info *pi;
8425 struct tx_sched_class *tc;
8427 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8428 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8429 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8430 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8431 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8432 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8436 if (p->mode == SCHED_CLASS_MODE_CLASS)
8437 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8438 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8439 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8443 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8444 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8445 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8446 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8450 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8451 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8452 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8453 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8457 /* Vet our parameters ... */
8458 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8461 pi = sc->port[sc->chan_map[p->channel]];
8464 MPASS(pi->tx_chan == p->channel);
8465 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8467 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8468 !in_range(p->minrate, 0, top_speed) ||
8469 !in_range(p->maxrate, 0, top_speed) ||
8470 !in_range(p->weight, 0, 100))
8474 * Translate any unset parameters into the firmware's
8475 * nomenclature and/or fail the call if the parameters
8478 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8483 if (p->maxrate < 0) {
8484 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8485 p->level == SCHED_CLASS_LEVEL_CH_RL)
8490 if (p->weight < 0) {
8491 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8496 if (p->pktsize < 0) {
8497 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8498 p->level == SCHED_CLASS_LEVEL_CH_RL)
8504 rc = begin_synchronized_op(sc, NULL,
8505 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8508 tc = &pi->tc[p->cl];
8510 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8511 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8512 p->weight, p->pktsize, sleep_ok);
8514 tc->flags |= TX_SC_OK;
8517 * Unknown state at this point, see tc->params for what was
8520 tc->flags &= ~TX_SC_OK;
8522 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8528 set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8531 if (p->type != SCHED_CLASS_TYPE_PACKET)
8534 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8535 return (set_sched_class_config(sc, p->u.config.minmax));
8537 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8538 return (set_sched_class_params(sc, &p->u.params, 1));
8544 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8546 struct port_info *pi = NULL;
8548 struct sge_txq *txq;
8549 uint32_t fw_mnem, fw_queue, fw_class;
8552 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8556 if (p->port >= sc->params.nports) {
8561 /* XXX: Only supported for the main VI. */
8562 pi = sc->port[p->port];
8564 if (!(vi->flags & VI_INIT_DONE)) {
8565 /* tx queues not set up yet */
8570 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8571 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8577 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8578 * Scheduling Class in this case).
8580 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8581 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8582 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8585 * If op.queue is non-negative, then we're only changing the scheduling
8586 * on a single specified TX queue.
8588 if (p->queue >= 0) {
8589 txq = &sc->sge.txq[vi->first_txq + p->queue];
8590 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8591 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8597 * Change the scheduling on all the TX queues for the
8600 for_each_txq(vi, i, txq) {
8601 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8602 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8610 end_synchronized_op(sc, 0);
8615 t4_os_find_pci_capability(struct adapter *sc, int cap)
8619 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8623 t4_os_pci_save_state(struct adapter *sc)
8626 struct pci_devinfo *dinfo;
8629 dinfo = device_get_ivars(dev);
8631 pci_cfg_save(dev, dinfo, 0);
8636 t4_os_pci_restore_state(struct adapter *sc)
8639 struct pci_devinfo *dinfo;
8642 dinfo = device_get_ivars(dev);
8644 pci_cfg_restore(dev, dinfo);
8649 t4_os_portmod_changed(const struct adapter *sc, int idx)
8651 struct port_info *pi = sc->port[idx];
8655 static const char *mod_str[] = {
8656 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8659 for_each_vi(pi, v, vi) {
8660 build_medialist(pi, &vi->media);
8663 ifp = pi->vi[0].ifp;
8664 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8665 if_printf(ifp, "transceiver unplugged.\n");
8666 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8667 if_printf(ifp, "unknown transceiver inserted.\n");
8668 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8669 if_printf(ifp, "unsupported transceiver inserted.\n");
8670 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8671 if_printf(ifp, "%s transceiver inserted.\n",
8672 mod_str[pi->mod_type]);
8674 if_printf(ifp, "transceiver (type %d) inserted.\n",
8680 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8682 struct port_info *pi = sc->port[idx];
8691 pi->linkdnrc = reason;
8693 for_each_vi(pi, v, vi) {
8699 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8700 if_link_state_change(ifp, LINK_STATE_UP);
8702 if_link_state_change(ifp, LINK_STATE_DOWN);
8708 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8712 sx_slock(&t4_list_lock);
8713 SLIST_FOREACH(sc, &t4_list, link) {
8715 * func should not make any assumptions about what state sc is
8716 * in - the only guarantee is that sc->sc_lock is a valid lock.
8720 sx_sunlock(&t4_list_lock);
8724 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8728 struct adapter *sc = dev->si_drv1;
8730 rc = priv_check(td, PRIV_DRIVER);
8735 case CHELSIO_T4_GETREG: {
8736 struct t4_reg *edata = (struct t4_reg *)data;
8738 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8741 if (edata->size == 4)
8742 edata->val = t4_read_reg(sc, edata->addr);
8743 else if (edata->size == 8)
8744 edata->val = t4_read_reg64(sc, edata->addr);
8750 case CHELSIO_T4_SETREG: {
8751 struct t4_reg *edata = (struct t4_reg *)data;
8753 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8756 if (edata->size == 4) {
8757 if (edata->val & 0xffffffff00000000)
8759 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8760 } else if (edata->size == 8)
8761 t4_write_reg64(sc, edata->addr, edata->val);
8766 case CHELSIO_T4_REGDUMP: {
8767 struct t4_regdump *regs = (struct t4_regdump *)data;
8768 int reglen = t4_get_regs_len(sc);
8771 if (regs->len < reglen) {
8772 regs->len = reglen; /* hint to the caller */
8777 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8778 get_regs(sc, regs, buf);
8779 rc = copyout(buf, regs->data, reglen);
8783 case CHELSIO_T4_GET_FILTER_MODE:
8784 rc = get_filter_mode(sc, (uint32_t *)data);
8786 case CHELSIO_T4_SET_FILTER_MODE:
8787 rc = set_filter_mode(sc, *(uint32_t *)data);
8789 case CHELSIO_T4_GET_FILTER:
8790 rc = get_filter(sc, (struct t4_filter *)data);
8792 case CHELSIO_T4_SET_FILTER:
8793 rc = set_filter(sc, (struct t4_filter *)data);
8795 case CHELSIO_T4_DEL_FILTER:
8796 rc = del_filter(sc, (struct t4_filter *)data);
8798 case CHELSIO_T4_GET_SGE_CONTEXT:
8799 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8801 case CHELSIO_T4_LOAD_FW:
8802 rc = load_fw(sc, (struct t4_data *)data);
8804 case CHELSIO_T4_GET_MEM:
8805 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8807 case CHELSIO_T4_GET_I2C:
8808 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8810 case CHELSIO_T4_CLEAR_STATS: {
8812 u_int port_id = *(uint32_t *)data;
8813 struct port_info *pi;
8816 if (port_id >= sc->params.nports)
8818 pi = sc->port[port_id];
8821 t4_clr_port_stats(sc, pi->tx_chan);
8822 pi->tx_parse_error = 0;
8823 mtx_lock(&sc->reg_lock);
8824 for_each_vi(pi, v, vi) {
8825 if (vi->flags & VI_INIT_DONE)
8826 t4_clr_vi_stats(sc, vi->viid);
8828 mtx_unlock(&sc->reg_lock);
8831 * Since this command accepts a port, clear stats for
8832 * all VIs on this port.
8834 for_each_vi(pi, v, vi) {
8835 if (vi->flags & VI_INIT_DONE) {
8836 struct sge_rxq *rxq;
8837 struct sge_txq *txq;
8838 struct sge_wrq *wrq;
8840 for_each_rxq(vi, i, rxq) {
8841 #if defined(INET) || defined(INET6)
8842 rxq->lro.lro_queued = 0;
8843 rxq->lro.lro_flushed = 0;
8846 rxq->vlan_extraction = 0;
8849 for_each_txq(vi, i, txq) {
8852 txq->vlan_insertion = 0;
8856 txq->txpkts0_wrs = 0;
8857 txq->txpkts1_wrs = 0;
8858 txq->txpkts0_pkts = 0;
8859 txq->txpkts1_pkts = 0;
8860 mp_ring_reset_stats(txq->r);
8864 /* nothing to clear for each ofld_rxq */
8866 for_each_ofld_txq(vi, i, wrq) {
8867 wrq->tx_wrs_direct = 0;
8868 wrq->tx_wrs_copied = 0;
8872 if (IS_MAIN_VI(vi)) {
8873 wrq = &sc->sge.ctrlq[pi->port_id];
8874 wrq->tx_wrs_direct = 0;
8875 wrq->tx_wrs_copied = 0;
8881 case CHELSIO_T4_SCHED_CLASS:
8882 rc = set_sched_class(sc, (struct t4_sched_params *)data);
8884 case CHELSIO_T4_SCHED_QUEUE:
8885 rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
8887 case CHELSIO_T4_GET_TRACER:
8888 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8890 case CHELSIO_T4_SET_TRACER:
8891 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8901 t4_db_full(struct adapter *sc)
8904 CXGBE_UNIMPLEMENTED(__func__);
8908 t4_db_dropped(struct adapter *sc)
8911 CXGBE_UNIMPLEMENTED(__func__);
8916 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
8919 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8920 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8921 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8922 V_HPZ3(pgsz_order[3]));
8926 toe_capability(struct vi_info *vi, int enable)
8929 struct port_info *pi = vi->pi;
8930 struct adapter *sc = pi->adapter;
8932 ASSERT_SYNCHRONIZED_OP(sc);
8934 if (!is_offload(sc))
8938 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8939 /* TOE is already enabled. */
8944 * We need the port's queues around so that we're able to send
8945 * and receive CPLs to/from the TOE even if the ifnet for this
8946 * port has never been UP'd administratively.
8948 if (!(vi->flags & VI_INIT_DONE)) {
8949 rc = vi_full_init(vi);
8953 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8954 rc = vi_full_init(&pi->vi[0]);
8959 if (isset(&sc->offload_map, pi->port_id)) {
8960 /* TOE is enabled on another VI of this port. */
8965 if (!uld_active(sc, ULD_TOM)) {
8966 rc = t4_activate_uld(sc, ULD_TOM);
8969 "You must kldload t4_tom.ko before trying "
8970 "to enable TOE on a cxgbe interface.\n");
8974 KASSERT(sc->tom_softc != NULL,
8975 ("%s: TOM activated but softc NULL", __func__));
8976 KASSERT(uld_active(sc, ULD_TOM),
8977 ("%s: TOM activated but flag not set", __func__));
8980 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8981 if (!uld_active(sc, ULD_IWARP))
8982 (void) t4_activate_uld(sc, ULD_IWARP);
8983 if (!uld_active(sc, ULD_ISCSI))
8984 (void) t4_activate_uld(sc, ULD_ISCSI);
8987 setbit(&sc->offload_map, pi->port_id);
8991 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
8994 KASSERT(uld_active(sc, ULD_TOM),
8995 ("%s: TOM never initialized?", __func__));
8996 clrbit(&sc->offload_map, pi->port_id);
9003 * Add an upper layer driver to the global list.
9006 t4_register_uld(struct uld_info *ui)
9011 sx_xlock(&t4_uld_list_lock);
9012 SLIST_FOREACH(u, &t4_uld_list, link) {
9013 if (u->uld_id == ui->uld_id) {
9019 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9022 sx_xunlock(&t4_uld_list_lock);
9027 t4_unregister_uld(struct uld_info *ui)
9032 sx_xlock(&t4_uld_list_lock);
9034 SLIST_FOREACH(u, &t4_uld_list, link) {
9036 if (ui->refcount > 0) {
9041 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9047 sx_xunlock(&t4_uld_list_lock);
9052 t4_activate_uld(struct adapter *sc, int id)
9055 struct uld_info *ui;
9057 ASSERT_SYNCHRONIZED_OP(sc);
9059 if (id < 0 || id > ULD_MAX)
9061 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9063 sx_slock(&t4_uld_list_lock);
9065 SLIST_FOREACH(ui, &t4_uld_list, link) {
9066 if (ui->uld_id == id) {
9067 if (!(sc->flags & FULL_INIT_DONE)) {
9068 rc = adapter_full_init(sc);
9073 rc = ui->activate(sc);
9075 setbit(&sc->active_ulds, id);
9082 sx_sunlock(&t4_uld_list_lock);
9088 t4_deactivate_uld(struct adapter *sc, int id)
9091 struct uld_info *ui;
9093 ASSERT_SYNCHRONIZED_OP(sc);
9095 if (id < 0 || id > ULD_MAX)
9099 sx_slock(&t4_uld_list_lock);
9101 SLIST_FOREACH(ui, &t4_uld_list, link) {
9102 if (ui->uld_id == id) {
9103 rc = ui->deactivate(sc);
9105 clrbit(&sc->active_ulds, id);
9112 sx_sunlock(&t4_uld_list_lock);
9118 uld_active(struct adapter *sc, int uld_id)
9121 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9123 return (isset(&sc->active_ulds, uld_id));
9128 * Come up with reasonable defaults for some of the tunables, provided they're
9129 * not set by the user (in which case we'll use the values as is).
9132 tweak_tunables(void)
9134 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9136 if (t4_ntxq10g < 1) {
9138 t4_ntxq10g = rss_getnumbuckets();
9140 t4_ntxq10g = min(nc, NTXQ_10G);
9144 if (t4_ntxq1g < 1) {
9146 /* XXX: way too many for 1GbE? */
9147 t4_ntxq1g = rss_getnumbuckets();
9149 t4_ntxq1g = min(nc, NTXQ_1G);
9154 t4_ntxq_vi = min(nc, NTXQ_VI);
9156 if (t4_nrxq10g < 1) {
9158 t4_nrxq10g = rss_getnumbuckets();
9160 t4_nrxq10g = min(nc, NRXQ_10G);
9164 if (t4_nrxq1g < 1) {
9166 /* XXX: way too many for 1GbE? */
9167 t4_nrxq1g = rss_getnumbuckets();
9169 t4_nrxq1g = min(nc, NRXQ_1G);
9174 t4_nrxq_vi = min(nc, NRXQ_VI);
9177 if (t4_nofldtxq10g < 1)
9178 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9180 if (t4_nofldtxq1g < 1)
9181 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9183 if (t4_nofldtxq_vi < 1)
9184 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9186 if (t4_nofldrxq10g < 1)
9187 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9189 if (t4_nofldrxq1g < 1)
9190 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9192 if (t4_nofldrxq_vi < 1)
9193 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9195 if (t4_toecaps_allowed == -1)
9196 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9198 if (t4_rdmacaps_allowed == -1) {
9199 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9200 FW_CAPS_CONFIG_RDMA_RDMAC;
9203 if (t4_iscsicaps_allowed == -1) {
9204 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9205 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9206 FW_CAPS_CONFIG_ISCSI_T10DIF;
9209 if (t4_toecaps_allowed == -1)
9210 t4_toecaps_allowed = 0;
9212 if (t4_rdmacaps_allowed == -1)
9213 t4_rdmacaps_allowed = 0;
9215 if (t4_iscsicaps_allowed == -1)
9216 t4_iscsicaps_allowed = 0;
9220 if (t4_nnmtxq_vi < 1)
9221 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9223 if (t4_nnmrxq_vi < 1)
9224 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9227 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9228 t4_tmr_idx_10g = TMR_IDX_10G;
9230 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9231 t4_pktc_idx_10g = PKTC_IDX_10G;
9233 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9234 t4_tmr_idx_1g = TMR_IDX_1G;
9236 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9237 t4_pktc_idx_1g = PKTC_IDX_1G;
9239 if (t4_qsize_txq < 128)
9242 if (t4_qsize_rxq < 128)
9244 while (t4_qsize_rxq & 7)
9247 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9252 t4_dump_tcb(struct adapter *sc, int tid)
9254 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9256 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9257 save = t4_read_reg(sc, reg);
9258 base = sc->memwin[2].mw_base;
9260 /* Dump TCB for the tid */
9261 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9262 tcb_addr += tid * TCB_SIZE;
9266 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9268 pf = V_PFNUM(sc->pf);
9269 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9271 t4_write_reg(sc, reg, win_pos | pf);
9272 t4_read_reg(sc, reg);
9274 off = tcb_addr - win_pos;
9275 for (i = 0; i < 4; i++) {
9277 for (j = 0; j < 8; j++, off += 4)
9278 buf[j] = htonl(t4_read_reg(sc, base + off));
9280 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9281 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9285 t4_write_reg(sc, reg, save);
9286 t4_read_reg(sc, reg);
9290 t4_dump_devlog(struct adapter *sc)
9292 struct devlog_params *dparams = &sc->params.devlog;
9293 struct fw_devlog_e e;
9294 int i, first, j, m, nentries, rc;
9295 uint64_t ftstamp = UINT64_MAX;
9297 if (dparams->start == 0) {
9298 db_printf("devlog params not valid\n");
9302 nentries = dparams->size / sizeof(struct fw_devlog_e);
9303 m = fwmtype_to_hwmtype(dparams->memtype);
9305 /* Find the first entry. */
9307 for (i = 0; i < nentries && !db_pager_quit; i++) {
9308 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9309 sizeof(e), (void *)&e);
9313 if (e.timestamp == 0)
9316 e.timestamp = be64toh(e.timestamp);
9317 if (e.timestamp < ftstamp) {
9318 ftstamp = e.timestamp;
9328 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9329 sizeof(e), (void *)&e);
9333 if (e.timestamp == 0)
9336 e.timestamp = be64toh(e.timestamp);
9337 e.seqno = be32toh(e.seqno);
9338 for (j = 0; j < 8; j++)
9339 e.params[j] = be32toh(e.params[j]);
9341 db_printf("%10d %15ju %8s %8s ",
9342 e.seqno, e.timestamp,
9343 (e.level < nitems(devlog_level_strings) ?
9344 devlog_level_strings[e.level] : "UNKNOWN"),
9345 (e.facility < nitems(devlog_facility_strings) ?
9346 devlog_facility_strings[e.facility] : "UNKNOWN"));
9347 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9348 e.params[3], e.params[4], e.params[5], e.params[6],
9351 if (++i == nentries)
9353 } while (i != first && !db_pager_quit);
9356 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9357 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9359 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9366 t = db_read_token();
9368 dev = device_lookup_by_name(db_tok_string);
9373 db_printf("usage: show t4 devlog <nexus>\n");
9378 db_printf("device not found\n");
9382 t4_dump_devlog(device_get_softc(dev));
9385 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9394 t = db_read_token();
9396 dev = device_lookup_by_name(db_tok_string);
9397 t = db_read_token();
9399 tid = db_tok_number;
9406 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9411 db_printf("device not found\n");
9415 db_printf("invalid tid\n");
9419 t4_dump_tcb(device_get_softc(dev), tid);
9423 static struct sx mlu; /* mod load unload */
9424 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9427 mod_event(module_t mod, int cmd, void *arg)
9430 static int loaded = 0;
9435 if (loaded++ == 0) {
9437 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9438 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9439 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9440 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9441 sx_init(&t4_list_lock, "T4/T5 adapters");
9442 SLIST_INIT(&t4_list);
9444 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9445 SLIST_INIT(&t4_uld_list);
9447 t4_tracer_modload();
9455 if (--loaded == 0) {
9458 sx_slock(&t4_list_lock);
9459 if (!SLIST_EMPTY(&t4_list)) {
9461 sx_sunlock(&t4_list_lock);
9465 sx_slock(&t4_uld_list_lock);
9466 if (!SLIST_EMPTY(&t4_uld_list)) {
9468 sx_sunlock(&t4_uld_list_lock);
9469 sx_sunlock(&t4_list_lock);
9474 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9475 uprintf("%ju clusters with custom free routine "
9476 "still is use.\n", t4_sge_extfree_refs());
9477 pause("t4unload", 2 * hz);
9480 sx_sunlock(&t4_uld_list_lock);
9482 sx_sunlock(&t4_list_lock);
9484 if (t4_sge_extfree_refs() == 0) {
9485 t4_tracer_modunload();
9487 sx_destroy(&t4_uld_list_lock);
9489 sx_destroy(&t4_list_lock);
9494 loaded++; /* undo earlier decrement */
9505 static devclass_t t4_devclass, t5_devclass;
9506 static devclass_t cxgbe_devclass, cxl_devclass;
9507 static devclass_t vcxgbe_devclass, vcxl_devclass;
9509 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9510 MODULE_VERSION(t4nex, 1);
9511 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9513 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
9514 #endif /* DEV_NETMAP */
9517 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9518 MODULE_VERSION(t5nex, 1);
9519 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9521 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
9522 #endif /* DEV_NETMAP */
9524 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9525 MODULE_VERSION(cxgbe, 1);
9527 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9528 MODULE_VERSION(cxl, 1);
9530 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9531 MODULE_VERSION(vcxgbe, 1);
9533 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9534 MODULE_VERSION(vcxl, 1);