2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_kern_tls.h"
37 #include "opt_ratelimit.h"
40 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
47 #include <sys/queue.h>
48 #include <sys/taskqueue.h>
49 #include <sys/pciio.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pci_private.h>
53 #include <sys/firmware.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
58 #include <sys/sysctl.h>
59 #include <net/ethernet.h>
61 #include <net/if_types.h>
62 #include <net/if_dl.h>
63 #include <net/if_vlan_var.h>
65 #include <net/rss_config.h>
67 #include <netinet/in.h>
68 #include <netinet/ip.h>
70 #include <netinet/tcp_seq.h>
72 #if defined(__i386__) || defined(__amd64__)
73 #include <machine/md_var.h>
74 #include <machine/cputypes.h>
80 #include <ddb/db_lex.h>
83 #include "common/common.h"
84 #include "common/t4_msg.h"
85 #include "common/t4_regs.h"
86 #include "common/t4_regs_values.h"
87 #include "cudbg/cudbg.h"
91 #include "t4_mp_ring.h"
95 /* T4 bus driver interface */
96 static int t4_probe(device_t);
97 static int t4_attach(device_t);
98 static int t4_detach(device_t);
99 static int t4_child_location_str(device_t, device_t, char *, size_t);
100 static int t4_ready(device_t);
101 static int t4_read_port_device(device_t, int, device_t *);
102 static device_method_t t4_methods[] = {
103 DEVMETHOD(device_probe, t4_probe),
104 DEVMETHOD(device_attach, t4_attach),
105 DEVMETHOD(device_detach, t4_detach),
107 DEVMETHOD(bus_child_location_str, t4_child_location_str),
109 DEVMETHOD(t4_is_main_ready, t4_ready),
110 DEVMETHOD(t4_read_port_device, t4_read_port_device),
114 static driver_t t4_driver = {
117 sizeof(struct adapter)
121 /* T4 port (cxgbe) interface */
122 static int cxgbe_probe(device_t);
123 static int cxgbe_attach(device_t);
124 static int cxgbe_detach(device_t);
125 device_method_t cxgbe_methods[] = {
126 DEVMETHOD(device_probe, cxgbe_probe),
127 DEVMETHOD(device_attach, cxgbe_attach),
128 DEVMETHOD(device_detach, cxgbe_detach),
131 static driver_t cxgbe_driver = {
134 sizeof(struct port_info)
137 /* T4 VI (vcxgbe) interface */
138 static int vcxgbe_probe(device_t);
139 static int vcxgbe_attach(device_t);
140 static int vcxgbe_detach(device_t);
141 static device_method_t vcxgbe_methods[] = {
142 DEVMETHOD(device_probe, vcxgbe_probe),
143 DEVMETHOD(device_attach, vcxgbe_attach),
144 DEVMETHOD(device_detach, vcxgbe_detach),
147 static driver_t vcxgbe_driver = {
150 sizeof(struct vi_info)
153 static d_ioctl_t t4_ioctl;
155 static struct cdevsw t4_cdevsw = {
156 .d_version = D_VERSION,
161 /* T5 bus driver interface */
162 static int t5_probe(device_t);
163 static device_method_t t5_methods[] = {
164 DEVMETHOD(device_probe, t5_probe),
165 DEVMETHOD(device_attach, t4_attach),
166 DEVMETHOD(device_detach, t4_detach),
168 DEVMETHOD(bus_child_location_str, t4_child_location_str),
170 DEVMETHOD(t4_is_main_ready, t4_ready),
171 DEVMETHOD(t4_read_port_device, t4_read_port_device),
175 static driver_t t5_driver = {
178 sizeof(struct adapter)
182 /* T5 port (cxl) interface */
183 static driver_t cxl_driver = {
186 sizeof(struct port_info)
189 /* T5 VI (vcxl) interface */
190 static driver_t vcxl_driver = {
193 sizeof(struct vi_info)
196 /* T6 bus driver interface */
197 static int t6_probe(device_t);
198 static device_method_t t6_methods[] = {
199 DEVMETHOD(device_probe, t6_probe),
200 DEVMETHOD(device_attach, t4_attach),
201 DEVMETHOD(device_detach, t4_detach),
203 DEVMETHOD(bus_child_location_str, t4_child_location_str),
205 DEVMETHOD(t4_is_main_ready, t4_ready),
206 DEVMETHOD(t4_read_port_device, t4_read_port_device),
210 static driver_t t6_driver = {
213 sizeof(struct adapter)
217 /* T6 port (cc) interface */
218 static driver_t cc_driver = {
221 sizeof(struct port_info)
224 /* T6 VI (vcc) interface */
225 static driver_t vcc_driver = {
228 sizeof(struct vi_info)
231 /* ifnet interface */
232 static void cxgbe_init(void *);
233 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
234 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
235 static void cxgbe_qflush(struct ifnet *);
236 #if defined(KERN_TLS) || defined(RATELIMIT)
237 static int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
238 struct m_snd_tag **);
239 static int cxgbe_snd_tag_modify(struct m_snd_tag *,
240 union if_snd_tag_modify_params *);
241 static int cxgbe_snd_tag_query(struct m_snd_tag *,
242 union if_snd_tag_query_params *);
243 static void cxgbe_snd_tag_free(struct m_snd_tag *);
246 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
249 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
250 * then ADAPTER_LOCK, then t4_uld_list_lock.
252 static struct sx t4_list_lock;
253 SLIST_HEAD(, adapter) t4_list;
255 static struct sx t4_uld_list_lock;
256 SLIST_HEAD(, uld_info) t4_uld_list;
260 * Tunables. See tweak_tunables() too.
262 * Each tunable is set to a default value here if it's known at compile-time.
263 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
264 * provide a reasonable default (upto n) when the driver is loaded.
266 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
267 * T5 are under hw.cxl.
269 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
270 "cxgbe(4) parameters");
271 SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
272 "cxgbe(4) T5+ parameters");
273 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
274 "cxgbe(4) TOE parameters");
277 * Number of queues for tx and rx, NIC and offload.
281 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0,
282 "Number of TX queues per port");
283 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
287 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0,
288 "Number of RX queues per port");
289 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
292 static int t4_ntxq_vi = -NTXQ_VI;
293 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0,
294 "Number of TX queues per VI");
297 static int t4_nrxq_vi = -NRXQ_VI;
298 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0,
299 "Number of RX queues per VI");
301 static int t4_rsrv_noflowq = 0;
302 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq,
303 0, "Reserve TX queue 0 of each VI for non-flowid packets");
305 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
307 static int t4_nofldtxq = -NOFLDTXQ;
308 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0,
309 "Number of offload TX queues per port");
312 static int t4_nofldrxq = -NOFLDRXQ;
313 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0,
314 "Number of offload RX queues per port");
316 #define NOFLDTXQ_VI 1
317 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
318 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0,
319 "Number of offload TX queues per VI");
321 #define NOFLDRXQ_VI 1
322 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
323 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0,
324 "Number of offload RX queues per VI");
326 #define TMR_IDX_OFLD 1
327 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
328 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN,
329 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues");
331 #define PKTC_IDX_OFLD (-1)
332 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
333 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN,
334 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues");
336 /* 0 means chip/fw default, non-zero number is value in microseconds */
337 static u_long t4_toe_keepalive_idle = 0;
338 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN,
339 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)");
341 /* 0 means chip/fw default, non-zero number is value in microseconds */
342 static u_long t4_toe_keepalive_interval = 0;
343 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN,
344 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)");
346 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
347 static int t4_toe_keepalive_count = 0;
348 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN,
349 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort");
351 /* 0 means chip/fw default, non-zero number is value in microseconds */
352 static u_long t4_toe_rexmt_min = 0;
353 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN,
354 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)");
356 /* 0 means chip/fw default, non-zero number is value in microseconds */
357 static u_long t4_toe_rexmt_max = 0;
358 SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN,
359 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)");
361 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
362 static int t4_toe_rexmt_count = 0;
363 SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN,
364 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort");
366 /* -1 means chip/fw default, other values are raw backoff values to use */
367 static int t4_toe_rexmt_backoff[16] = {
368 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
370 SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff,
371 CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
372 "cxgbe(4) TOE retransmit backoff values");
373 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN,
374 &t4_toe_rexmt_backoff[0], 0, "");
375 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN,
376 &t4_toe_rexmt_backoff[1], 0, "");
377 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN,
378 &t4_toe_rexmt_backoff[2], 0, "");
379 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN,
380 &t4_toe_rexmt_backoff[3], 0, "");
381 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN,
382 &t4_toe_rexmt_backoff[4], 0, "");
383 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN,
384 &t4_toe_rexmt_backoff[5], 0, "");
385 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN,
386 &t4_toe_rexmt_backoff[6], 0, "");
387 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN,
388 &t4_toe_rexmt_backoff[7], 0, "");
389 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN,
390 &t4_toe_rexmt_backoff[8], 0, "");
391 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN,
392 &t4_toe_rexmt_backoff[9], 0, "");
393 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN,
394 &t4_toe_rexmt_backoff[10], 0, "");
395 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN,
396 &t4_toe_rexmt_backoff[11], 0, "");
397 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN,
398 &t4_toe_rexmt_backoff[12], 0, "");
399 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN,
400 &t4_toe_rexmt_backoff[13], 0, "");
401 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN,
402 &t4_toe_rexmt_backoff[14], 0, "");
403 SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN,
404 &t4_toe_rexmt_backoff[15], 0, "");
408 #define NN_MAIN_VI (1 << 0) /* Native netmap on the main VI */
409 #define NN_EXTRA_VI (1 << 1) /* Native netmap on the extra VI(s) */
410 static int t4_native_netmap = NN_EXTRA_VI;
411 SYSCTL_INT(_hw_cxgbe, OID_AUTO, native_netmap, CTLFLAG_RDTUN, &t4_native_netmap,
412 0, "Native netmap support. bit 0 = main VI, bit 1 = extra VIs");
415 static int t4_nnmtxq = -NNMTXQ;
416 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq, CTLFLAG_RDTUN, &t4_nnmtxq, 0,
417 "Number of netmap TX queues");
420 static int t4_nnmrxq = -NNMRXQ;
421 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq, CTLFLAG_RDTUN, &t4_nnmrxq, 0,
422 "Number of netmap RX queues");
425 static int t4_nnmtxq_vi = -NNMTXQ_VI;
426 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0,
427 "Number of netmap TX queues per VI");
430 static int t4_nnmrxq_vi = -NNMRXQ_VI;
431 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0,
432 "Number of netmap RX queues per VI");
436 * Holdoff parameters for ports.
439 int t4_tmr_idx = TMR_IDX;
440 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx,
441 0, "Holdoff timer index");
442 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
444 #define PKTC_IDX (-1)
445 int t4_pktc_idx = PKTC_IDX;
446 SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx,
447 0, "Holdoff packet counter index");
448 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
451 * Size (# of entries) of each tx and rx queue.
453 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
454 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0,
455 "Number of descriptors in each TX queue");
457 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
458 SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0,
459 "Number of descriptors in each RX queue");
462 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
464 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
465 SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types,
466 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)");
469 * Configuration file. All the _CF names here are special.
471 #define DEFAULT_CF "default"
472 #define BUILTIN_CF "built-in"
473 #define FLASH_CF "flash"
474 #define UWIRE_CF "uwire"
475 #define FPGA_CF "fpga"
476 static char t4_cfg_file[32] = DEFAULT_CF;
477 SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file,
478 sizeof(t4_cfg_file), "Firmware configuration file");
481 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
482 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
483 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
484 * mark or when signalled to do so, 0 to never emit PAUSE.
485 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
486 * negotiated settings will override rx_pause/tx_pause.
487 * Otherwise rx_pause/tx_pause are applied forcibly.
489 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
490 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN,
491 &t4_pause_settings, 0,
492 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
495 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
496 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
499 static int t4_fec = -1;
500 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
501 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
504 * Link autonegotiation.
505 * -1 to run with the firmware default.
509 static int t4_autoneg = -1;
510 SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0,
511 "Link autonegotiation");
514 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
515 * encouraged respectively). '-n' is the same as 'n' except the firmware
516 * version used in the checks is read from the firmware bundled with the driver.
518 static int t4_fw_install = 1;
519 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0,
520 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)");
523 * ASIC features that will be used. Disable the ones you don't want so that the
524 * chip resources aren't wasted on features that will not be used.
526 static int t4_nbmcaps_allowed = 0;
527 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN,
528 &t4_nbmcaps_allowed, 0, "Default NBM capabilities");
530 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
531 SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN,
532 &t4_linkcaps_allowed, 0, "Default link capabilities");
534 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
535 FW_CAPS_CONFIG_SWITCH_EGRESS;
536 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
537 &t4_switchcaps_allowed, 0, "Default switch capabilities");
540 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
541 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
543 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
544 FW_CAPS_CONFIG_NIC_HASHFILTER;
546 SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN,
547 &t4_niccaps_allowed, 0, "Default NIC capabilities");
549 static int t4_toecaps_allowed = -1;
550 SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN,
551 &t4_toecaps_allowed, 0, "Default TCP offload capabilities");
553 static int t4_rdmacaps_allowed = -1;
554 SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN,
555 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities");
557 static int t4_cryptocaps_allowed = -1;
558 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN,
559 &t4_cryptocaps_allowed, 0, "Default crypto capabilities");
561 static int t4_iscsicaps_allowed = -1;
562 SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN,
563 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities");
565 static int t4_fcoecaps_allowed = 0;
566 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN,
567 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities");
569 static int t5_write_combine = 0;
570 SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine,
571 0, "Use WC instead of UC for BAR2");
573 static int t4_num_vis = 1;
574 SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0,
575 "Number of VIs per port");
578 * PCIe Relaxed Ordering.
579 * -1: driver should figure out a good value.
584 static int pcie_relaxed_ordering = -1;
585 SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN,
586 &pcie_relaxed_ordering, 0,
587 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone");
589 static int t4_panic_on_fatal_err = 0;
590 SYSCTL_INT(_hw_cxgbe, OID_AUTO, panic_on_fatal_err, CTLFLAG_RDTUN,
591 &t4_panic_on_fatal_err, 0, "panic on fatal errors");
597 static int t4_cop_managed_offloading = 0;
598 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cop_managed_offloading, CTLFLAG_RDTUN,
599 &t4_cop_managed_offloading, 0,
600 "COP (Connection Offload Policy) controls all TOE offload");
605 * This enables KERN_TLS for all adapters if set.
607 static int t4_kern_tls = 0;
608 SYSCTL_INT(_hw_cxgbe, OID_AUTO, kern_tls, CTLFLAG_RDTUN, &t4_kern_tls, 0,
609 "Enable KERN_TLS mode for all supported adapters");
611 SYSCTL_NODE(_hw_cxgbe, OID_AUTO, tls, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
612 "cxgbe(4) KERN_TLS parameters");
614 static int t4_tls_inline_keys = 0;
615 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
616 &t4_tls_inline_keys, 0,
617 "Always pass TLS keys in work requests (1) or attempt to store TLS keys "
620 static int t4_tls_combo_wrs = 0;
621 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
622 0, "Attempt to combine TCB field updates with TLS record work requests.");
625 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
626 static int vi_mac_funcs[] = {
630 FW_VI_FUNC_OPENISCSI,
636 struct intrs_and_queues {
637 uint16_t intr_type; /* INTx, MSI, or MSI-X */
638 uint16_t num_vis; /* number of VIs for each port */
639 uint16_t nirq; /* Total # of vectors */
640 uint16_t ntxq; /* # of NIC txq's for each port */
641 uint16_t nrxq; /* # of NIC rxq's for each port */
642 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
643 uint16_t nofldrxq; /* # of TOE rxq's for each port */
644 uint16_t nnmtxq; /* # of netmap txq's */
645 uint16_t nnmrxq; /* # of netmap rxq's */
647 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
648 uint16_t ntxq_vi; /* # of NIC txq's */
649 uint16_t nrxq_vi; /* # of NIC rxq's */
650 uint16_t nofldtxq_vi; /* # of TOE txq's */
651 uint16_t nofldrxq_vi; /* # of TOE rxq's */
652 uint16_t nnmtxq_vi; /* # of netmap txq's */
653 uint16_t nnmrxq_vi; /* # of netmap rxq's */
656 static void setup_memwin(struct adapter *);
657 static void position_memwin(struct adapter *, int, uint32_t);
658 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
659 static int fwmtype_to_hwmtype(int);
660 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
662 static int fixup_devlog_params(struct adapter *);
663 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
664 static int contact_firmware(struct adapter *);
665 static int partition_resources(struct adapter *);
666 static int get_params__pre_init(struct adapter *);
667 static int set_params__pre_init(struct adapter *);
668 static int get_params__post_init(struct adapter *);
669 static int set_params__post_init(struct adapter *);
670 static void t4_set_desc(struct adapter *);
671 static bool fixed_ifmedia(struct port_info *);
672 static void build_medialist(struct port_info *);
673 static void init_link_config(struct port_info *);
674 static int fixup_link_config(struct port_info *);
675 static int apply_link_config(struct port_info *);
676 static int cxgbe_init_synchronized(struct vi_info *);
677 static int cxgbe_uninit_synchronized(struct vi_info *);
678 static void quiesce_txq(struct adapter *, struct sge_txq *);
679 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
680 static void quiesce_iq(struct adapter *, struct sge_iq *);
681 static void quiesce_fl(struct adapter *, struct sge_fl *);
682 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
683 driver_intr_t *, void *, char *);
684 static int t4_free_irq(struct adapter *, struct irq *);
685 static void t4_init_atid_table(struct adapter *);
686 static void t4_free_atid_table(struct adapter *);
687 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
688 static void vi_refresh_stats(struct adapter *, struct vi_info *);
689 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
690 static void cxgbe_tick(void *);
691 static void cxgbe_sysctls(struct port_info *);
692 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
693 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
694 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
695 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
696 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
697 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
698 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
699 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
700 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
701 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
702 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
703 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
704 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
705 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
706 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
707 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
708 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
709 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
710 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
711 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
712 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
713 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
714 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
715 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
716 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
717 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
718 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
719 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
720 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
721 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
722 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
723 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
724 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
725 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
726 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
727 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
728 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
729 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
730 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
731 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
732 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
733 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
734 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
735 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
736 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
737 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
739 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
740 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
741 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
742 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
743 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
744 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
745 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
746 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
748 static int get_sge_context(struct adapter *, struct t4_sge_context *);
749 static int load_fw(struct adapter *, struct t4_data *);
750 static int load_cfg(struct adapter *, struct t4_data *);
751 static int load_boot(struct adapter *, struct t4_bootrom *);
752 static int load_bootcfg(struct adapter *, struct t4_data *);
753 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
754 static void free_offload_policy(struct t4_offload_policy *);
755 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
756 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
757 static int read_i2c(struct adapter *, struct t4_i2c_data *);
758 static int clear_stats(struct adapter *, u_int);
760 static int toe_capability(struct vi_info *, int);
761 static void t4_async_event(void *, int);
763 static int mod_event(module_t, int, void *);
764 static int notify_siblings(device_t, int);
770 {0xa000, "Chelsio Terminator 4 FPGA"},
771 {0x4400, "Chelsio T440-dbg"},
772 {0x4401, "Chelsio T420-CR"},
773 {0x4402, "Chelsio T422-CR"},
774 {0x4403, "Chelsio T440-CR"},
775 {0x4404, "Chelsio T420-BCH"},
776 {0x4405, "Chelsio T440-BCH"},
777 {0x4406, "Chelsio T440-CH"},
778 {0x4407, "Chelsio T420-SO"},
779 {0x4408, "Chelsio T420-CX"},
780 {0x4409, "Chelsio T420-BT"},
781 {0x440a, "Chelsio T404-BT"},
782 {0x440e, "Chelsio T440-LP-CR"},
784 {0xb000, "Chelsio Terminator 5 FPGA"},
785 {0x5400, "Chelsio T580-dbg"},
786 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
787 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
788 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
789 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
790 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
791 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
792 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
793 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
794 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
795 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
796 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
797 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
798 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
799 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
800 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
801 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
802 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
805 {0x5483, "Custom T540-CR"},
806 {0x5484, "Custom T540-BT"},
808 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
809 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
810 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
811 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
812 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
813 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
814 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
815 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
816 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
817 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
818 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
819 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
820 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
821 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
822 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
823 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
826 {0x6480, "Custom T6225-CR"},
827 {0x6481, "Custom T62100-CR"},
828 {0x6482, "Custom T6225-CR"},
829 {0x6483, "Custom T62100-CR"},
830 {0x6484, "Custom T64100-CR"},
831 {0x6485, "Custom T6240-SO"},
832 {0x6486, "Custom T6225-SO-CR"},
833 {0x6487, "Custom T6225-CR"},
838 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
839 * be exactly the same for both rxq and ofld_rxq.
841 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
842 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
844 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
847 t4_probe(device_t dev)
850 uint16_t v = pci_get_vendor(dev);
851 uint16_t d = pci_get_device(dev);
852 uint8_t f = pci_get_function(dev);
854 if (v != PCI_VENDOR_ID_CHELSIO)
857 /* Attach only to PF0 of the FPGA */
858 if (d == 0xa000 && f != 0)
861 for (i = 0; i < nitems(t4_pciids); i++) {
862 if (d == t4_pciids[i].device) {
863 device_set_desc(dev, t4_pciids[i].desc);
864 return (BUS_PROBE_DEFAULT);
872 t5_probe(device_t dev)
875 uint16_t v = pci_get_vendor(dev);
876 uint16_t d = pci_get_device(dev);
877 uint8_t f = pci_get_function(dev);
879 if (v != PCI_VENDOR_ID_CHELSIO)
882 /* Attach only to PF0 of the FPGA */
883 if (d == 0xb000 && f != 0)
886 for (i = 0; i < nitems(t5_pciids); i++) {
887 if (d == t5_pciids[i].device) {
888 device_set_desc(dev, t5_pciids[i].desc);
889 return (BUS_PROBE_DEFAULT);
897 t6_probe(device_t dev)
900 uint16_t v = pci_get_vendor(dev);
901 uint16_t d = pci_get_device(dev);
903 if (v != PCI_VENDOR_ID_CHELSIO)
906 for (i = 0; i < nitems(t6_pciids); i++) {
907 if (d == t6_pciids[i].device) {
908 device_set_desc(dev, t6_pciids[i].desc);
909 return (BUS_PROBE_DEFAULT);
917 t5_attribute_workaround(device_t dev)
923 * The T5 chips do not properly echo the No Snoop and Relaxed
924 * Ordering attributes when replying to a TLP from a Root
925 * Port. As a workaround, find the parent Root Port and
926 * disable No Snoop and Relaxed Ordering. Note that this
927 * affects all devices under this root port.
929 root_port = pci_find_pcie_root_port(dev);
930 if (root_port == NULL) {
931 device_printf(dev, "Unable to find parent root port\n");
935 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
936 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
937 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
939 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
940 device_get_nameunit(root_port));
943 static const struct devnames devnames[] = {
945 .nexus_name = "t4nex",
946 .ifnet_name = "cxgbe",
947 .vi_ifnet_name = "vcxgbe",
948 .pf03_drv_name = "t4iov",
949 .vf_nexus_name = "t4vf",
950 .vf_ifnet_name = "cxgbev"
952 .nexus_name = "t5nex",
954 .vi_ifnet_name = "vcxl",
955 .pf03_drv_name = "t5iov",
956 .vf_nexus_name = "t5vf",
957 .vf_ifnet_name = "cxlv"
959 .nexus_name = "t6nex",
961 .vi_ifnet_name = "vcc",
962 .pf03_drv_name = "t6iov",
963 .vf_nexus_name = "t6vf",
964 .vf_ifnet_name = "ccv"
969 t4_init_devnames(struct adapter *sc)
974 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
975 sc->names = &devnames[id - CHELSIO_T4];
977 device_printf(sc->dev, "chip id %d is not supported.\n", id);
983 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
985 const char *parent, *name;
990 parent = device_get_nameunit(sc->dev);
991 name = sc->names->ifnet_name;
992 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
993 if (resource_long_value(name, unit, "port", &value) == 0 &&
994 value == pi->port_id)
1001 t4_attach(device_t dev)
1004 int rc = 0, i, j, rqidx, tqidx, nports;
1005 struct make_dev_args mda;
1006 struct intrs_and_queues iaq;
1009 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1016 int nm_rqidx, nm_tqidx;
1020 sc = device_get_softc(dev);
1022 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
1024 if ((pci_get_device(dev) & 0xff00) == 0x5400)
1025 t5_attribute_workaround(dev);
1026 pci_enable_busmaster(dev);
1027 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
1030 pci_set_max_read_req(dev, 4096);
1031 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
1032 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
1033 if (pcie_relaxed_ordering == 0 &&
1034 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
1035 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
1036 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1037 } else if (pcie_relaxed_ordering == 1 &&
1038 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
1039 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
1040 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
1044 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
1045 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
1047 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
1048 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
1049 device_get_nameunit(dev));
1051 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
1052 device_get_nameunit(dev));
1053 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
1056 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
1057 TAILQ_INIT(&sc->sfl);
1058 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
1060 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
1063 rw_init(&sc->policy_lock, "connection offload policy");
1065 callout_init(&sc->ktls_tick, 1);
1068 TASK_INIT(&sc->async_event_task, 0, t4_async_event, sc);
1071 rc = t4_map_bars_0_and_4(sc);
1073 goto done; /* error message displayed already */
1075 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
1077 /* Prepare the adapter for operation. */
1078 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
1079 rc = -t4_prep_adapter(sc, buf);
1082 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
1087 * This is the real PF# to which we're attaching. Works from within PCI
1088 * passthrough environments too, where pci_get_function() could return a
1089 * different PF# depending on the passthrough configuration. We need to
1090 * use the real PF# in all our communication with the firmware.
1092 j = t4_read_reg(sc, A_PL_WHOAMI);
1093 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
1096 t4_init_devnames(sc);
1097 if (sc->names == NULL) {
1099 goto done; /* error message displayed already */
1103 * Do this really early, with the memory windows set up even before the
1104 * character device. The userland tool's register i/o and mem read
1105 * will work even in "recovery mode".
1108 if (t4_init_devlog_params(sc, 0) == 0)
1109 fixup_devlog_params(sc);
1110 make_dev_args_init(&mda);
1111 mda.mda_devsw = &t4_cdevsw;
1112 mda.mda_uid = UID_ROOT;
1113 mda.mda_gid = GID_WHEEL;
1114 mda.mda_mode = 0600;
1115 mda.mda_si_drv1 = sc;
1116 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
1118 device_printf(dev, "failed to create nexus char device: %d.\n",
1121 /* Go no further if recovery mode has been requested. */
1122 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
1123 device_printf(dev, "recovery mode.\n");
1127 #if defined(__i386__)
1128 if ((cpu_feature & CPUID_CX8) == 0) {
1129 device_printf(dev, "64 bit atomics not available.\n");
1135 /* Contact the firmware and try to become the master driver. */
1136 rc = contact_firmware(sc);
1138 goto done; /* error message displayed already */
1139 MPASS(sc->flags & FW_OK);
1141 rc = get_params__pre_init(sc);
1143 goto done; /* error message displayed already */
1145 if (sc->flags & MASTER_PF) {
1146 rc = partition_resources(sc);
1148 goto done; /* error message displayed already */
1152 rc = get_params__post_init(sc);
1154 goto done; /* error message displayed already */
1156 rc = set_params__post_init(sc);
1158 goto done; /* error message displayed already */
1160 rc = t4_map_bar_2(sc);
1162 goto done; /* error message displayed already */
1164 rc = t4_create_dma_tag(sc);
1166 goto done; /* error message displayed already */
1169 * First pass over all the ports - allocate VIs and initialize some
1170 * basic parameters like mac address, port type, etc.
1172 for_each_port(sc, i) {
1173 struct port_info *pi;
1175 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1178 /* These must be set before t4_port_init */
1182 * XXX: vi[0] is special so we can't delay this allocation until
1183 * pi->nvi's final value is known.
1185 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1189 * Allocate the "main" VI and initialize parameters
1192 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1194 device_printf(dev, "unable to initialize port %d: %d\n",
1196 free(pi->vi, M_CXGBE);
1202 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1203 device_get_nameunit(dev), i);
1204 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1205 sc->chan_map[pi->tx_chan] = i;
1207 /* All VIs on this port share this media. */
1208 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1209 cxgbe_media_status);
1212 init_link_config(pi);
1213 fixup_link_config(pi);
1214 build_medialist(pi);
1215 if (fixed_ifmedia(pi))
1216 pi->flags |= FIXED_IFMEDIA;
1219 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1220 t4_ifnet_unit(sc, pi));
1221 if (pi->dev == NULL) {
1223 "failed to add device for port %d.\n", i);
1227 pi->vi[0].dev = pi->dev;
1228 device_set_softc(pi->dev, pi);
1232 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1234 nports = sc->params.nports;
1235 rc = cfg_itype_and_nqueues(sc, &iaq);
1237 goto done; /* error message displayed already */
1239 num_vis = iaq.num_vis;
1240 sc->intr_type = iaq.intr_type;
1241 sc->intr_count = iaq.nirq;
1244 s->nrxq = nports * iaq.nrxq;
1245 s->ntxq = nports * iaq.ntxq;
1247 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1248 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1250 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1251 s->neq += nports; /* ctrl queues: 1 per port */
1252 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1253 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1254 if (is_offload(sc) || is_ethoffload(sc)) {
1255 s->nofldtxq = nports * iaq.nofldtxq;
1257 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1258 s->neq += s->nofldtxq;
1260 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1261 M_CXGBE, M_ZERO | M_WAITOK);
1265 if (is_offload(sc)) {
1266 s->nofldrxq = nports * iaq.nofldrxq;
1268 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1269 s->neq += s->nofldrxq; /* free list */
1270 s->niq += s->nofldrxq;
1272 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1273 M_CXGBE, M_ZERO | M_WAITOK);
1279 if (t4_native_netmap & NN_MAIN_VI) {
1280 s->nnmrxq += nports * iaq.nnmrxq;
1281 s->nnmtxq += nports * iaq.nnmtxq;
1283 if (num_vis > 1 && t4_native_netmap & NN_EXTRA_VI) {
1284 s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1285 s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1287 s->neq += s->nnmtxq + s->nnmrxq;
1288 s->niq += s->nnmrxq;
1290 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1291 M_CXGBE, M_ZERO | M_WAITOK);
1292 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1293 M_CXGBE, M_ZERO | M_WAITOK);
1296 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1298 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1300 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1302 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1304 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1307 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1310 t4_init_l2t(sc, M_WAITOK);
1311 t4_init_smt(sc, M_WAITOK);
1312 t4_init_tx_sched(sc);
1313 t4_init_atid_table(sc);
1315 t4_init_etid_table(sc);
1318 t4_init_clip_table(sc);
1320 if (sc->vres.key.size != 0)
1321 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1322 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1325 * Second pass over the ports. This time we know the number of rx and
1326 * tx queues that each port should get.
1329 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1336 nm_rqidx = nm_tqidx = 0;
1338 for_each_port(sc, i) {
1339 struct port_info *pi = sc->port[i];
1346 for_each_vi(pi, j, vi) {
1348 vi->qsize_rxq = t4_qsize_rxq;
1349 vi->qsize_txq = t4_qsize_txq;
1351 vi->first_rxq = rqidx;
1352 vi->first_txq = tqidx;
1353 vi->tmr_idx = t4_tmr_idx;
1354 vi->pktc_idx = t4_pktc_idx;
1355 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1356 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1361 if (j == 0 && vi->ntxq > 1)
1362 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1364 vi->rsrv_noflowq = 0;
1366 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1367 vi->first_ofld_txq = ofld_tqidx;
1368 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1369 ofld_tqidx += vi->nofldtxq;
1372 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1373 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1374 vi->first_ofld_rxq = ofld_rqidx;
1375 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1377 ofld_rqidx += vi->nofldrxq;
1380 vi->first_nm_rxq = nm_rqidx;
1381 vi->first_nm_txq = nm_tqidx;
1383 vi->nnmrxq = iaq.nnmrxq;
1384 vi->nnmtxq = iaq.nnmtxq;
1386 vi->nnmrxq = iaq.nnmrxq_vi;
1387 vi->nnmtxq = iaq.nnmtxq_vi;
1389 nm_rqidx += vi->nnmrxq;
1390 nm_tqidx += vi->nnmtxq;
1395 rc = t4_setup_intr_handlers(sc);
1398 "failed to setup interrupt handlers: %d\n", rc);
1402 rc = bus_generic_probe(dev);
1404 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1409 * Ensure thread-safe mailbox access (in debug builds).
1411 * So far this was the only thread accessing the mailbox but various
1412 * ifnets and sysctls are about to be created and their handlers/ioctls
1413 * will access the mailbox from different threads.
1415 sc->flags |= CHK_MBOX_ACCESS;
1417 rc = bus_generic_attach(dev);
1420 "failed to attach all child ports: %d\n", rc);
1425 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1426 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1427 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1428 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1429 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1433 notify_siblings(dev, 0);
1436 if (rc != 0 && sc->cdev) {
1437 /* cdev was created and so cxgbetool works; recover that way. */
1439 "error during attach, adapter is now in recovery mode.\n");
1444 t4_detach_common(dev);
1452 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1455 struct port_info *pi;
1458 sc = device_get_softc(bus);
1460 for_each_port(sc, i) {
1462 if (pi != NULL && pi->dev == dev) {
1463 snprintf(buf, buflen, "port=%d", pi->port_id);
1471 t4_ready(device_t dev)
1475 sc = device_get_softc(dev);
1476 if (sc->flags & FW_OK)
1482 t4_read_port_device(device_t dev, int port, device_t *child)
1485 struct port_info *pi;
1487 sc = device_get_softc(dev);
1488 if (port < 0 || port >= MAX_NPORTS)
1490 pi = sc->port[port];
1491 if (pi == NULL || pi->dev == NULL)
1498 notify_siblings(device_t dev, int detaching)
1504 for (i = 0; i < PCI_FUNCMAX; i++) {
1505 if (i == pci_get_function(dev))
1507 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1508 pci_get_slot(dev), i);
1509 if (sibling == NULL || !device_is_attached(sibling))
1512 error = T4_DETACH_CHILD(sibling);
1514 (void)T4_ATTACH_CHILD(sibling);
1525 t4_detach(device_t dev)
1530 sc = device_get_softc(dev);
1532 rc = notify_siblings(dev, 1);
1535 "failed to detach sibling devices: %d\n", rc);
1539 return (t4_detach_common(dev));
1543 t4_detach_common(device_t dev)
1546 struct port_info *pi;
1549 sc = device_get_softc(dev);
1552 destroy_dev(sc->cdev);
1556 sx_xlock(&t4_list_lock);
1557 SLIST_REMOVE(&t4_list, sc, adapter, link);
1558 sx_xunlock(&t4_list_lock);
1560 sc->flags &= ~CHK_MBOX_ACCESS;
1561 if (sc->flags & FULL_INIT_DONE) {
1562 if (!(sc->flags & IS_VF))
1563 t4_intr_disable(sc);
1566 if (device_is_attached(dev)) {
1567 rc = bus_generic_detach(dev);
1570 "failed to detach child devices: %d\n", rc);
1576 taskqueue_drain(taskqueue_thread, &sc->async_event_task);
1579 for (i = 0; i < sc->intr_count; i++)
1580 t4_free_irq(sc, &sc->irq[i]);
1582 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1583 t4_free_tx_sched(sc);
1585 for (i = 0; i < MAX_NPORTS; i++) {
1588 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1590 device_delete_child(dev, pi->dev);
1592 mtx_destroy(&pi->pi_lock);
1593 free(pi->vi, M_CXGBE);
1598 device_delete_children(dev);
1600 if (sc->flags & FULL_INIT_DONE)
1601 adapter_full_uninit(sc);
1603 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1604 t4_fw_bye(sc, sc->mbox);
1606 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1607 pci_release_msi(dev);
1610 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1614 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1618 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1622 t4_free_l2t(sc->l2t);
1624 t4_free_smt(sc->smt);
1625 t4_free_atid_table(sc);
1627 t4_free_etid_table(sc);
1630 vmem_destroy(sc->key_map);
1632 t4_destroy_clip_table(sc);
1635 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1636 free(sc->sge.ofld_txq, M_CXGBE);
1639 free(sc->sge.ofld_rxq, M_CXGBE);
1642 free(sc->sge.nm_rxq, M_CXGBE);
1643 free(sc->sge.nm_txq, M_CXGBE);
1645 free(sc->irq, M_CXGBE);
1646 free(sc->sge.rxq, M_CXGBE);
1647 free(sc->sge.txq, M_CXGBE);
1648 free(sc->sge.ctrlq, M_CXGBE);
1649 free(sc->sge.iqmap, M_CXGBE);
1650 free(sc->sge.eqmap, M_CXGBE);
1651 free(sc->tids.ftid_tab, M_CXGBE);
1652 free(sc->tids.hpftid_tab, M_CXGBE);
1653 free_hftid_hash(&sc->tids);
1654 free(sc->tids.tid_tab, M_CXGBE);
1655 free(sc->tt.tls_rx_ports, M_CXGBE);
1656 t4_destroy_dma_tag(sc);
1658 callout_drain(&sc->ktls_tick);
1659 callout_drain(&sc->sfl_callout);
1660 if (mtx_initialized(&sc->tids.ftid_lock)) {
1661 mtx_destroy(&sc->tids.ftid_lock);
1662 cv_destroy(&sc->tids.ftid_cv);
1664 if (mtx_initialized(&sc->tids.atid_lock))
1665 mtx_destroy(&sc->tids.atid_lock);
1666 if (mtx_initialized(&sc->ifp_lock))
1667 mtx_destroy(&sc->ifp_lock);
1669 if (rw_initialized(&sc->policy_lock)) {
1670 rw_destroy(&sc->policy_lock);
1672 if (sc->policy != NULL)
1673 free_offload_policy(sc->policy);
1677 for (i = 0; i < NUM_MEMWIN; i++) {
1678 struct memwin *mw = &sc->memwin[i];
1680 if (rw_initialized(&mw->mw_lock))
1681 rw_destroy(&mw->mw_lock);
1684 mtx_destroy(&sc->sfl_lock);
1685 mtx_destroy(&sc->reg_lock);
1686 mtx_destroy(&sc->sc_lock);
1688 bzero(sc, sizeof(*sc));
1694 cxgbe_probe(device_t dev)
1697 struct port_info *pi = device_get_softc(dev);
1699 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1700 device_set_desc_copy(dev, buf);
1702 return (BUS_PROBE_DEFAULT);
1705 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1706 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1707 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1708 IFCAP_HWRXTSTMP | IFCAP_NOMAP)
1709 #define T4_CAP_ENABLE (T4_CAP)
1712 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1716 struct pfil_head_args pa;
1718 vi->xact_addr_filt = -1;
1719 callout_init(&vi->tick, 1);
1721 /* Allocate an ifnet and set it up */
1722 ifp = if_alloc_dev(IFT_ETHER, dev);
1724 device_printf(dev, "Cannot allocate ifnet\n");
1730 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1731 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1733 ifp->if_init = cxgbe_init;
1734 ifp->if_ioctl = cxgbe_ioctl;
1735 ifp->if_transmit = cxgbe_transmit;
1736 ifp->if_qflush = cxgbe_qflush;
1737 ifp->if_get_counter = cxgbe_get_counter;
1738 #if defined(KERN_TLS) || defined(RATELIMIT)
1739 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1740 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1741 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1742 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1745 ifp->if_ratelimit_query = cxgbe_ratelimit_query;
1748 ifp->if_capabilities = T4_CAP;
1749 ifp->if_capenable = T4_CAP_ENABLE;
1751 if (vi->nofldrxq != 0 && (vi->pi->adapter->flags & KERN_TLS_OK) == 0)
1752 ifp->if_capabilities |= IFCAP_TOE;
1755 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1756 ifp->if_capabilities |= IFCAP_TXRTLMT;
1757 ifp->if_capenable |= IFCAP_TXRTLMT;
1760 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1761 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1763 ifp->if_hw_tsomax = IP_MAXPACKET;
1764 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1766 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1767 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1769 ifp->if_hw_tsomaxsegsize = 65536;
1771 if (vi->pi->adapter->flags & KERN_TLS_OK) {
1772 ifp->if_capabilities |= IFCAP_TXTLS;
1773 ifp->if_capenable |= IFCAP_TXTLS;
1777 ether_ifattach(ifp, vi->hw_addr);
1779 if (vi->nnmrxq != 0)
1780 cxgbe_nm_attach(vi);
1782 sb = sbuf_new_auto();
1783 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1784 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1785 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1787 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1789 case IFCAP_TOE | IFCAP_TXRTLMT:
1790 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1793 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1798 if (ifp->if_capabilities & IFCAP_TOE)
1799 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1802 if (ifp->if_capabilities & IFCAP_NETMAP)
1803 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1804 vi->nnmtxq, vi->nnmrxq);
1807 device_printf(dev, "%s\n", sbuf_data(sb));
1812 pa.pa_version = PFIL_VERSION;
1813 pa.pa_flags = PFIL_IN;
1814 pa.pa_type = PFIL_TYPE_ETHERNET;
1815 pa.pa_headname = ifp->if_xname;
1816 vi->pfil = pfil_head_register(&pa);
1822 cxgbe_attach(device_t dev)
1824 struct port_info *pi = device_get_softc(dev);
1825 struct adapter *sc = pi->adapter;
1829 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1831 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1835 for_each_vi(pi, i, vi) {
1838 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1839 if (vi->dev == NULL) {
1840 device_printf(dev, "failed to add VI %d\n", i);
1843 device_set_softc(vi->dev, vi);
1848 bus_generic_attach(dev);
1854 cxgbe_vi_detach(struct vi_info *vi)
1856 struct ifnet *ifp = vi->ifp;
1858 if (vi->pfil != NULL) {
1859 pfil_head_unregister(vi->pfil);
1863 ether_ifdetach(ifp);
1865 /* Let detach proceed even if these fail. */
1867 if (ifp->if_capabilities & IFCAP_NETMAP)
1868 cxgbe_nm_detach(vi);
1870 cxgbe_uninit_synchronized(vi);
1871 callout_drain(&vi->tick);
1879 cxgbe_detach(device_t dev)
1881 struct port_info *pi = device_get_softc(dev);
1882 struct adapter *sc = pi->adapter;
1885 /* Detach the extra VIs first. */
1886 rc = bus_generic_detach(dev);
1889 device_delete_children(dev);
1891 doom_vi(sc, &pi->vi[0]);
1893 if (pi->flags & HAS_TRACEQ) {
1894 sc->traceq = -1; /* cloner should not create ifnet */
1895 t4_tracer_port_detach(sc);
1898 cxgbe_vi_detach(&pi->vi[0]);
1899 callout_drain(&pi->tick);
1900 ifmedia_removeall(&pi->media);
1902 end_synchronized_op(sc, 0);
1908 cxgbe_init(void *arg)
1910 struct vi_info *vi = arg;
1911 struct adapter *sc = vi->pi->adapter;
1913 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1915 cxgbe_init_synchronized(vi);
1916 end_synchronized_op(sc, 0);
1920 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1922 int rc = 0, mtu, flags;
1923 struct vi_info *vi = ifp->if_softc;
1924 struct port_info *pi = vi->pi;
1925 struct adapter *sc = pi->adapter;
1926 struct ifreq *ifr = (struct ifreq *)data;
1932 if (mtu < ETHERMIN || mtu > MAX_MTU)
1935 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1939 if (vi->flags & VI_INIT_DONE) {
1940 t4_update_fl_bufsize(ifp);
1941 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1942 rc = update_mac_settings(ifp, XGMAC_MTU);
1944 end_synchronized_op(sc, 0);
1948 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1952 if (ifp->if_flags & IFF_UP) {
1953 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1954 flags = vi->if_flags;
1955 if ((ifp->if_flags ^ flags) &
1956 (IFF_PROMISC | IFF_ALLMULTI)) {
1957 rc = update_mac_settings(ifp,
1958 XGMAC_PROMISC | XGMAC_ALLMULTI);
1961 rc = cxgbe_init_synchronized(vi);
1963 vi->if_flags = ifp->if_flags;
1964 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1965 rc = cxgbe_uninit_synchronized(vi);
1967 end_synchronized_op(sc, 0);
1972 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1975 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1976 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1977 end_synchronized_op(sc, 0);
1981 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1985 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1986 if (mask & IFCAP_TXCSUM) {
1987 ifp->if_capenable ^= IFCAP_TXCSUM;
1988 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1990 if (IFCAP_TSO4 & ifp->if_capenable &&
1991 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1992 ifp->if_capenable &= ~IFCAP_TSO4;
1994 "tso4 disabled due to -txcsum.\n");
1997 if (mask & IFCAP_TXCSUM_IPV6) {
1998 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1999 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2001 if (IFCAP_TSO6 & ifp->if_capenable &&
2002 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2003 ifp->if_capenable &= ~IFCAP_TSO6;
2005 "tso6 disabled due to -txcsum6.\n");
2008 if (mask & IFCAP_RXCSUM)
2009 ifp->if_capenable ^= IFCAP_RXCSUM;
2010 if (mask & IFCAP_RXCSUM_IPV6)
2011 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2014 * Note that we leave CSUM_TSO alone (it is always set). The
2015 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
2016 * sending a TSO request our way, so it's sufficient to toggle
2019 if (mask & IFCAP_TSO4) {
2020 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2021 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2022 if_printf(ifp, "enable txcsum first.\n");
2026 ifp->if_capenable ^= IFCAP_TSO4;
2028 if (mask & IFCAP_TSO6) {
2029 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2030 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2031 if_printf(ifp, "enable txcsum6 first.\n");
2035 ifp->if_capenable ^= IFCAP_TSO6;
2037 if (mask & IFCAP_LRO) {
2038 #if defined(INET) || defined(INET6)
2040 struct sge_rxq *rxq;
2042 ifp->if_capenable ^= IFCAP_LRO;
2043 for_each_rxq(vi, i, rxq) {
2044 if (ifp->if_capenable & IFCAP_LRO)
2045 rxq->iq.flags |= IQ_LRO_ENABLED;
2047 rxq->iq.flags &= ~IQ_LRO_ENABLED;
2052 if (mask & IFCAP_TOE) {
2053 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
2055 rc = toe_capability(vi, enable);
2059 ifp->if_capenable ^= mask;
2062 if (mask & IFCAP_VLAN_HWTAGGING) {
2063 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2064 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2065 rc = update_mac_settings(ifp, XGMAC_VLANEX);
2067 if (mask & IFCAP_VLAN_MTU) {
2068 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2070 /* Need to find out how to disable auto-mtu-inflation */
2072 if (mask & IFCAP_VLAN_HWTSO)
2073 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2074 if (mask & IFCAP_VLAN_HWCSUM)
2075 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2077 if (mask & IFCAP_TXRTLMT)
2078 ifp->if_capenable ^= IFCAP_TXRTLMT;
2080 if (mask & IFCAP_HWRXTSTMP) {
2082 struct sge_rxq *rxq;
2084 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2085 for_each_rxq(vi, i, rxq) {
2086 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
2087 rxq->iq.flags |= IQ_RX_TIMESTAMP;
2089 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
2092 if (mask & IFCAP_NOMAP)
2093 ifp->if_capenable ^= IFCAP_NOMAP;
2096 if (mask & IFCAP_TXTLS)
2097 ifp->if_capenable ^= (mask & IFCAP_TXTLS);
2100 #ifdef VLAN_CAPABILITIES
2101 VLAN_CAPABILITIES(ifp);
2104 end_synchronized_op(sc, 0);
2110 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
2114 struct ifi2creq i2c;
2116 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2119 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
2123 if (i2c.len > sizeof(i2c.data)) {
2127 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
2130 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
2131 i2c.offset, i2c.len, &i2c.data[0]);
2132 end_synchronized_op(sc, 0);
2134 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2139 rc = ether_ioctl(ifp, cmd, data);
2146 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
2148 struct vi_info *vi = ifp->if_softc;
2149 struct port_info *pi = vi->pi;
2150 struct adapter *sc = pi->adapter;
2151 struct sge_txq *txq;
2153 struct cxgbe_snd_tag *cst;
2159 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
2160 #if defined(KERN_TLS) || defined(RATELIMIT)
2161 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG)
2162 MPASS(m->m_pkthdr.snd_tag->ifp == ifp);
2165 if (__predict_false(pi->link_cfg.link_ok == false)) {
2170 rc = parse_pkt(sc, &m);
2171 if (__predict_false(rc != 0)) {
2172 MPASS(m == NULL); /* was freed already */
2173 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
2177 if (m->m_pkthdr.csum_flags & CSUM_SND_TAG) {
2178 cst = mst_to_cst(m->m_pkthdr.snd_tag);
2179 if (cst->type == IF_SND_TAG_TYPE_RATE_LIMIT)
2180 return (ethofld_transmit(ifp, m));
2185 txq = &sc->sge.txq[vi->first_txq];
2186 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2187 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
2191 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
2192 if (__predict_false(rc != 0))
2199 cxgbe_qflush(struct ifnet *ifp)
2201 struct vi_info *vi = ifp->if_softc;
2202 struct sge_txq *txq;
2205 /* queues do not exist if !VI_INIT_DONE. */
2206 if (vi->flags & VI_INIT_DONE) {
2207 for_each_txq(vi, i, txq) {
2209 txq->eq.flags |= EQ_QFLUSH;
2211 while (!mp_ring_is_idle(txq->r)) {
2212 mp_ring_check_drainage(txq->r, 0);
2216 txq->eq.flags &= ~EQ_QFLUSH;
2224 vi_get_counter(struct ifnet *ifp, ift_counter c)
2226 struct vi_info *vi = ifp->if_softc;
2227 struct fw_vi_stats_vf *s = &vi->stats;
2229 vi_refresh_stats(vi->pi->adapter, vi);
2232 case IFCOUNTER_IPACKETS:
2233 return (s->rx_bcast_frames + s->rx_mcast_frames +
2234 s->rx_ucast_frames);
2235 case IFCOUNTER_IERRORS:
2236 return (s->rx_err_frames);
2237 case IFCOUNTER_OPACKETS:
2238 return (s->tx_bcast_frames + s->tx_mcast_frames +
2239 s->tx_ucast_frames + s->tx_offload_frames);
2240 case IFCOUNTER_OERRORS:
2241 return (s->tx_drop_frames);
2242 case IFCOUNTER_IBYTES:
2243 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2245 case IFCOUNTER_OBYTES:
2246 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2247 s->tx_ucast_bytes + s->tx_offload_bytes);
2248 case IFCOUNTER_IMCASTS:
2249 return (s->rx_mcast_frames);
2250 case IFCOUNTER_OMCASTS:
2251 return (s->tx_mcast_frames);
2252 case IFCOUNTER_OQDROPS: {
2256 if (vi->flags & VI_INIT_DONE) {
2258 struct sge_txq *txq;
2260 for_each_txq(vi, i, txq)
2261 drops += counter_u64_fetch(txq->r->drops);
2269 return (if_get_counter_default(ifp, c));
2274 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2276 struct vi_info *vi = ifp->if_softc;
2277 struct port_info *pi = vi->pi;
2278 struct adapter *sc = pi->adapter;
2279 struct port_stats *s = &pi->stats;
2281 if (pi->nvi > 1 || sc->flags & IS_VF)
2282 return (vi_get_counter(ifp, c));
2284 cxgbe_refresh_stats(sc, pi);
2287 case IFCOUNTER_IPACKETS:
2288 return (s->rx_frames);
2290 case IFCOUNTER_IERRORS:
2291 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2292 s->rx_fcs_err + s->rx_len_err);
2294 case IFCOUNTER_OPACKETS:
2295 return (s->tx_frames);
2297 case IFCOUNTER_OERRORS:
2298 return (s->tx_error_frames);
2300 case IFCOUNTER_IBYTES:
2301 return (s->rx_octets);
2303 case IFCOUNTER_OBYTES:
2304 return (s->tx_octets);
2306 case IFCOUNTER_IMCASTS:
2307 return (s->rx_mcast_frames);
2309 case IFCOUNTER_OMCASTS:
2310 return (s->tx_mcast_frames);
2312 case IFCOUNTER_IQDROPS:
2313 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2314 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2315 s->rx_trunc3 + pi->tnl_cong_drops);
2317 case IFCOUNTER_OQDROPS: {
2321 if (vi->flags & VI_INIT_DONE) {
2323 struct sge_txq *txq;
2325 for_each_txq(vi, i, txq)
2326 drops += counter_u64_fetch(txq->r->drops);
2334 return (if_get_counter_default(ifp, c));
2338 #if defined(KERN_TLS) || defined(RATELIMIT)
2340 cxgbe_snd_tag_init(struct cxgbe_snd_tag *cst, struct ifnet *ifp, int type)
2343 m_snd_tag_init(&cst->com, ifp);
2348 cxgbe_snd_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
2349 struct m_snd_tag **pt)
2353 switch (params->hdr.type) {
2355 case IF_SND_TAG_TYPE_RATE_LIMIT:
2356 error = cxgbe_rate_tag_alloc(ifp, params, pt);
2360 case IF_SND_TAG_TYPE_TLS:
2361 error = cxgbe_tls_tag_alloc(ifp, params, pt);
2368 MPASS(mst_to_cst(*pt)->type == params->hdr.type);
2373 cxgbe_snd_tag_modify(struct m_snd_tag *mst,
2374 union if_snd_tag_modify_params *params)
2376 struct cxgbe_snd_tag *cst;
2378 cst = mst_to_cst(mst);
2379 switch (cst->type) {
2381 case IF_SND_TAG_TYPE_RATE_LIMIT:
2382 return (cxgbe_rate_tag_modify(mst, params));
2385 return (EOPNOTSUPP);
2390 cxgbe_snd_tag_query(struct m_snd_tag *mst,
2391 union if_snd_tag_query_params *params)
2393 struct cxgbe_snd_tag *cst;
2395 cst = mst_to_cst(mst);
2396 switch (cst->type) {
2398 case IF_SND_TAG_TYPE_RATE_LIMIT:
2399 return (cxgbe_rate_tag_query(mst, params));
2402 return (EOPNOTSUPP);
2407 cxgbe_snd_tag_free(struct m_snd_tag *mst)
2409 struct cxgbe_snd_tag *cst;
2411 cst = mst_to_cst(mst);
2412 switch (cst->type) {
2414 case IF_SND_TAG_TYPE_RATE_LIMIT:
2415 cxgbe_rate_tag_free(mst);
2419 case IF_SND_TAG_TYPE_TLS:
2420 cxgbe_tls_tag_free(mst);
2424 panic("shouldn't get here");
2430 * The kernel picks a media from the list we had provided but we still validate
2434 cxgbe_media_change(struct ifnet *ifp)
2436 struct vi_info *vi = ifp->if_softc;
2437 struct port_info *pi = vi->pi;
2438 struct ifmedia *ifm = &pi->media;
2439 struct link_config *lc = &pi->link_cfg;
2440 struct adapter *sc = pi->adapter;
2443 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2447 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2448 /* ifconfig .. media autoselect */
2449 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2450 rc = ENOTSUP; /* AN not supported by transceiver */
2453 lc->requested_aneg = AUTONEG_ENABLE;
2454 lc->requested_speed = 0;
2455 lc->requested_fc |= PAUSE_AUTONEG;
2457 lc->requested_aneg = AUTONEG_DISABLE;
2458 lc->requested_speed =
2459 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2460 lc->requested_fc = 0;
2461 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2462 lc->requested_fc |= PAUSE_RX;
2463 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2464 lc->requested_fc |= PAUSE_TX;
2466 if (pi->up_vis > 0) {
2467 fixup_link_config(pi);
2468 rc = apply_link_config(pi);
2472 end_synchronized_op(sc, 0);
2477 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2481 port_mword(struct port_info *pi, uint32_t speed)
2484 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2485 MPASS(powerof2(speed));
2487 switch(pi->port_type) {
2488 case FW_PORT_TYPE_BT_SGMII:
2489 case FW_PORT_TYPE_BT_XFI:
2490 case FW_PORT_TYPE_BT_XAUI:
2493 case FW_PORT_CAP32_SPEED_100M:
2495 case FW_PORT_CAP32_SPEED_1G:
2496 return (IFM_1000_T);
2497 case FW_PORT_CAP32_SPEED_10G:
2501 case FW_PORT_TYPE_KX4:
2502 if (speed == FW_PORT_CAP32_SPEED_10G)
2503 return (IFM_10G_KX4);
2505 case FW_PORT_TYPE_CX4:
2506 if (speed == FW_PORT_CAP32_SPEED_10G)
2507 return (IFM_10G_CX4);
2509 case FW_PORT_TYPE_KX:
2510 if (speed == FW_PORT_CAP32_SPEED_1G)
2511 return (IFM_1000_KX);
2513 case FW_PORT_TYPE_KR:
2514 case FW_PORT_TYPE_BP_AP:
2515 case FW_PORT_TYPE_BP4_AP:
2516 case FW_PORT_TYPE_BP40_BA:
2517 case FW_PORT_TYPE_KR4_100G:
2518 case FW_PORT_TYPE_KR_SFP28:
2519 case FW_PORT_TYPE_KR_XLAUI:
2521 case FW_PORT_CAP32_SPEED_1G:
2522 return (IFM_1000_KX);
2523 case FW_PORT_CAP32_SPEED_10G:
2524 return (IFM_10G_KR);
2525 case FW_PORT_CAP32_SPEED_25G:
2526 return (IFM_25G_KR);
2527 case FW_PORT_CAP32_SPEED_40G:
2528 return (IFM_40G_KR4);
2529 case FW_PORT_CAP32_SPEED_50G:
2530 return (IFM_50G_KR2);
2531 case FW_PORT_CAP32_SPEED_100G:
2532 return (IFM_100G_KR4);
2535 case FW_PORT_TYPE_FIBER_XFI:
2536 case FW_PORT_TYPE_FIBER_XAUI:
2537 case FW_PORT_TYPE_SFP:
2538 case FW_PORT_TYPE_QSFP_10G:
2539 case FW_PORT_TYPE_QSA:
2540 case FW_PORT_TYPE_QSFP:
2541 case FW_PORT_TYPE_CR4_QSFP:
2542 case FW_PORT_TYPE_CR_QSFP:
2543 case FW_PORT_TYPE_CR2_QSFP:
2544 case FW_PORT_TYPE_SFP28:
2545 /* Pluggable transceiver */
2546 switch (pi->mod_type) {
2547 case FW_PORT_MOD_TYPE_LR:
2549 case FW_PORT_CAP32_SPEED_1G:
2550 return (IFM_1000_LX);
2551 case FW_PORT_CAP32_SPEED_10G:
2552 return (IFM_10G_LR);
2553 case FW_PORT_CAP32_SPEED_25G:
2554 return (IFM_25G_LR);
2555 case FW_PORT_CAP32_SPEED_40G:
2556 return (IFM_40G_LR4);
2557 case FW_PORT_CAP32_SPEED_50G:
2558 return (IFM_50G_LR2);
2559 case FW_PORT_CAP32_SPEED_100G:
2560 return (IFM_100G_LR4);
2563 case FW_PORT_MOD_TYPE_SR:
2565 case FW_PORT_CAP32_SPEED_1G:
2566 return (IFM_1000_SX);
2567 case FW_PORT_CAP32_SPEED_10G:
2568 return (IFM_10G_SR);
2569 case FW_PORT_CAP32_SPEED_25G:
2570 return (IFM_25G_SR);
2571 case FW_PORT_CAP32_SPEED_40G:
2572 return (IFM_40G_SR4);
2573 case FW_PORT_CAP32_SPEED_50G:
2574 return (IFM_50G_SR2);
2575 case FW_PORT_CAP32_SPEED_100G:
2576 return (IFM_100G_SR4);
2579 case FW_PORT_MOD_TYPE_ER:
2580 if (speed == FW_PORT_CAP32_SPEED_10G)
2581 return (IFM_10G_ER);
2583 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2584 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2586 case FW_PORT_CAP32_SPEED_1G:
2587 return (IFM_1000_CX);
2588 case FW_PORT_CAP32_SPEED_10G:
2589 return (IFM_10G_TWINAX);
2590 case FW_PORT_CAP32_SPEED_25G:
2591 return (IFM_25G_CR);
2592 case FW_PORT_CAP32_SPEED_40G:
2593 return (IFM_40G_CR4);
2594 case FW_PORT_CAP32_SPEED_50G:
2595 return (IFM_50G_CR2);
2596 case FW_PORT_CAP32_SPEED_100G:
2597 return (IFM_100G_CR4);
2600 case FW_PORT_MOD_TYPE_LRM:
2601 if (speed == FW_PORT_CAP32_SPEED_10G)
2602 return (IFM_10G_LRM);
2604 case FW_PORT_MOD_TYPE_NA:
2605 MPASS(0); /* Not pluggable? */
2607 case FW_PORT_MOD_TYPE_ERROR:
2608 case FW_PORT_MOD_TYPE_UNKNOWN:
2609 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2611 case FW_PORT_MOD_TYPE_NONE:
2615 case FW_PORT_TYPE_NONE:
2619 return (IFM_UNKNOWN);
2623 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2625 struct vi_info *vi = ifp->if_softc;
2626 struct port_info *pi = vi->pi;
2627 struct adapter *sc = pi->adapter;
2628 struct link_config *lc = &pi->link_cfg;
2630 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2634 if (pi->up_vis == 0) {
2636 * If all the interfaces are administratively down the firmware
2637 * does not report transceiver changes. Refresh port info here
2638 * so that ifconfig displays accurate ifmedia at all times.
2639 * This is the only reason we have a synchronized op in this
2640 * function. Just PORT_LOCK would have been enough otherwise.
2642 t4_update_port_info(pi);
2643 build_medialist(pi);
2647 ifmr->ifm_status = IFM_AVALID;
2648 if (lc->link_ok == false)
2650 ifmr->ifm_status |= IFM_ACTIVE;
2653 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2654 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2655 if (lc->fc & PAUSE_RX)
2656 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2657 if (lc->fc & PAUSE_TX)
2658 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2659 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2662 end_synchronized_op(sc, 0);
2666 vcxgbe_probe(device_t dev)
2669 struct vi_info *vi = device_get_softc(dev);
2671 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2673 device_set_desc_copy(dev, buf);
2675 return (BUS_PROBE_DEFAULT);
2679 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2681 int func, index, rc;
2682 uint32_t param, val;
2684 ASSERT_SYNCHRONIZED_OP(sc);
2686 index = vi - pi->vi;
2687 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2688 KASSERT(index < nitems(vi_mac_funcs),
2689 ("%s: VI %s doesn't have a MAC func", __func__,
2690 device_get_nameunit(vi->dev)));
2691 func = vi_mac_funcs[index];
2692 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2693 vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
2695 device_printf(vi->dev, "failed to allocate virtual interface %d"
2696 "for port %d: %d\n", index, pi->port_id, -rc);
2701 if (vi->rss_size == 1) {
2703 * This VI didn't get a slice of the RSS table. Reduce the
2704 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2705 * configuration file (nvi, rssnvi for this PF) if this is a
2708 device_printf(vi->dev, "RSS table not available.\n");
2709 vi->rss_base = 0xffff;
2714 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2715 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2716 V_FW_PARAMS_PARAM_YZ(vi->viid);
2717 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2719 vi->rss_base = 0xffff;
2721 MPASS((val >> 16) == vi->rss_size);
2722 vi->rss_base = val & 0xffff;
2729 vcxgbe_attach(device_t dev)
2732 struct port_info *pi;
2736 vi = device_get_softc(dev);
2740 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2743 rc = alloc_extra_vi(sc, pi, vi);
2744 end_synchronized_op(sc, 0);
2748 rc = cxgbe_vi_attach(dev, vi);
2750 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2757 vcxgbe_detach(device_t dev)
2762 vi = device_get_softc(dev);
2763 sc = vi->pi->adapter;
2767 cxgbe_vi_detach(vi);
2768 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2770 end_synchronized_op(sc, 0);
2775 static struct callout fatal_callout;
2778 delayed_panic(void *arg)
2780 struct adapter *sc = arg;
2782 panic("%s: panic on fatal error", device_get_nameunit(sc->dev));
2786 t4_fatal_err(struct adapter *sc, bool fw_error)
2789 t4_shutdown_adapter(sc);
2790 log(LOG_ALERT, "%s: encountered fatal error, adapter stopped.\n",
2791 device_get_nameunit(sc->dev));
2793 ASSERT_SYNCHRONIZED_OP(sc);
2794 sc->flags |= ADAP_ERR;
2797 sc->flags |= ADAP_ERR;
2801 taskqueue_enqueue(taskqueue_thread, &sc->async_event_task);
2804 if (t4_panic_on_fatal_err) {
2805 log(LOG_ALERT, "%s: panic on fatal error after 30s",
2806 device_get_nameunit(sc->dev));
2807 callout_reset(&fatal_callout, hz * 30, delayed_panic, sc);
2812 t4_add_adapter(struct adapter *sc)
2814 sx_xlock(&t4_list_lock);
2815 SLIST_INSERT_HEAD(&t4_list, sc, link);
2816 sx_xunlock(&t4_list_lock);
2820 t4_map_bars_0_and_4(struct adapter *sc)
2822 sc->regs_rid = PCIR_BAR(0);
2823 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2824 &sc->regs_rid, RF_ACTIVE);
2825 if (sc->regs_res == NULL) {
2826 device_printf(sc->dev, "cannot map registers.\n");
2829 sc->bt = rman_get_bustag(sc->regs_res);
2830 sc->bh = rman_get_bushandle(sc->regs_res);
2831 sc->mmio_len = rman_get_size(sc->regs_res);
2832 setbit(&sc->doorbells, DOORBELL_KDB);
2834 sc->msix_rid = PCIR_BAR(4);
2835 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2836 &sc->msix_rid, RF_ACTIVE);
2837 if (sc->msix_res == NULL) {
2838 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2846 t4_map_bar_2(struct adapter *sc)
2850 * T4: only iWARP driver uses the userspace doorbells. There is no need
2851 * to map it if RDMA is disabled.
2853 if (is_t4(sc) && sc->rdmacaps == 0)
2856 sc->udbs_rid = PCIR_BAR(2);
2857 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2858 &sc->udbs_rid, RF_ACTIVE);
2859 if (sc->udbs_res == NULL) {
2860 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2863 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2865 if (chip_id(sc) >= CHELSIO_T5) {
2866 setbit(&sc->doorbells, DOORBELL_UDB);
2867 #if defined(__i386__) || defined(__amd64__)
2868 if (t5_write_combine) {
2872 * Enable write combining on BAR2. This is the
2873 * userspace doorbell BAR and is split into 128B
2874 * (UDBS_SEG_SIZE) doorbell regions, each associated
2875 * with an egress queue. The first 64B has the doorbell
2876 * and the second 64B can be used to submit a tx work
2877 * request with an implicit doorbell.
2880 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2881 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2883 clrbit(&sc->doorbells, DOORBELL_UDB);
2884 setbit(&sc->doorbells, DOORBELL_WCWR);
2885 setbit(&sc->doorbells, DOORBELL_UDBWC);
2887 device_printf(sc->dev,
2888 "couldn't enable write combining: %d\n",
2892 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2893 t4_write_reg(sc, A_SGE_STAT_CFG,
2894 V_STATSOURCE_T5(7) | mode);
2898 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2903 struct memwin_init {
2908 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2909 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2910 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2911 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2914 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2915 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2916 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2917 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2921 setup_memwin(struct adapter *sc)
2923 const struct memwin_init *mw_init;
2930 * Read low 32b of bar0 indirectly via the hardware backdoor
2931 * mechanism. Works from within PCI passthrough environments
2932 * too, where rman_get_start() can return a different value. We
2933 * need to program the T4 memory window decoders with the actual
2934 * addresses that will be coming across the PCIe link.
2936 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2937 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2939 mw_init = &t4_memwin[0];
2941 /* T5+ use the relative offset inside the PCIe BAR */
2944 mw_init = &t5_memwin[0];
2947 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2948 rw_init(&mw->mw_lock, "memory window access");
2949 mw->mw_base = mw_init->base;
2950 mw->mw_aperture = mw_init->aperture;
2953 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2954 (mw->mw_base + bar0) | V_BIR(0) |
2955 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2956 rw_wlock(&mw->mw_lock);
2957 position_memwin(sc, i, 0);
2958 rw_wunlock(&mw->mw_lock);
2962 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2966 * Positions the memory window at the given address in the card's address space.
2967 * There are some alignment requirements and the actual position may be at an
2968 * address prior to the requested address. mw->mw_curpos always has the actual
2969 * position of the window.
2972 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2978 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2979 mw = &sc->memwin[idx];
2980 rw_assert(&mw->mw_lock, RA_WLOCKED);
2984 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2986 pf = V_PFNUM(sc->pf);
2987 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2989 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2990 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2991 t4_read_reg(sc, reg); /* flush */
2995 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
3001 MPASS(idx >= 0 && idx < NUM_MEMWIN);
3003 /* Memory can only be accessed in naturally aligned 4 byte units */
3004 if (addr & 3 || len & 3 || len <= 0)
3007 mw = &sc->memwin[idx];
3009 rw_rlock(&mw->mw_lock);
3010 mw_end = mw->mw_curpos + mw->mw_aperture;
3011 if (addr >= mw_end || addr < mw->mw_curpos) {
3012 /* Will need to reposition the window */
3013 if (!rw_try_upgrade(&mw->mw_lock)) {
3014 rw_runlock(&mw->mw_lock);
3015 rw_wlock(&mw->mw_lock);
3017 rw_assert(&mw->mw_lock, RA_WLOCKED);
3018 position_memwin(sc, idx, addr);
3019 rw_downgrade(&mw->mw_lock);
3020 mw_end = mw->mw_curpos + mw->mw_aperture;
3022 rw_assert(&mw->mw_lock, RA_RLOCKED);
3023 while (addr < mw_end && len > 0) {
3025 v = t4_read_reg(sc, mw->mw_base + addr -
3027 *val++ = le32toh(v);
3030 t4_write_reg(sc, mw->mw_base + addr -
3031 mw->mw_curpos, htole32(v));
3036 rw_runlock(&mw->mw_lock);
3043 t4_init_atid_table(struct adapter *sc)
3052 MPASS(t->atid_tab == NULL);
3054 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
3056 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
3057 t->afree = t->atid_tab;
3058 t->atids_in_use = 0;
3059 for (i = 1; i < t->natids; i++)
3060 t->atid_tab[i - 1].next = &t->atid_tab[i];
3061 t->atid_tab[t->natids - 1].next = NULL;
3065 t4_free_atid_table(struct adapter *sc)
3071 KASSERT(t->atids_in_use == 0,
3072 ("%s: %d atids still in use.", __func__, t->atids_in_use));
3074 if (mtx_initialized(&t->atid_lock))
3075 mtx_destroy(&t->atid_lock);
3076 free(t->atid_tab, M_CXGBE);
3081 alloc_atid(struct adapter *sc, void *ctx)
3083 struct tid_info *t = &sc->tids;
3086 mtx_lock(&t->atid_lock);
3088 union aopen_entry *p = t->afree;
3090 atid = p - t->atid_tab;
3091 MPASS(atid <= M_TID_TID);
3096 mtx_unlock(&t->atid_lock);
3101 lookup_atid(struct adapter *sc, int atid)
3103 struct tid_info *t = &sc->tids;
3105 return (t->atid_tab[atid].data);
3109 free_atid(struct adapter *sc, int atid)
3111 struct tid_info *t = &sc->tids;
3112 union aopen_entry *p = &t->atid_tab[atid];
3114 mtx_lock(&t->atid_lock);
3118 mtx_unlock(&t->atid_lock);
3122 queue_tid_release(struct adapter *sc, int tid)
3125 CXGBE_UNIMPLEMENTED("deferred tid release");
3129 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
3132 struct cpl_tid_release *req;
3134 wr = alloc_wrqe(sizeof(*req), ctrlq);
3136 queue_tid_release(sc, tid); /* defer */
3141 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
3147 t4_range_cmp(const void *a, const void *b)
3149 return ((const struct t4_range *)a)->start -
3150 ((const struct t4_range *)b)->start;
3154 * Verify that the memory range specified by the addr/len pair is valid within
3155 * the card's address space.
3158 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
3160 struct t4_range mem_ranges[4], *r, *next;
3161 uint32_t em, addr_len;
3162 int i, n, remaining;
3164 /* Memory can only be accessed in naturally aligned 4 byte units */
3165 if (addr & 3 || len & 3 || len == 0)
3168 /* Enabled memories */
3169 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3173 bzero(r, sizeof(mem_ranges));
3174 if (em & F_EDRAM0_ENABLE) {
3175 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3176 r->size = G_EDRAM0_SIZE(addr_len) << 20;
3178 r->start = G_EDRAM0_BASE(addr_len) << 20;
3179 if (addr >= r->start &&
3180 addr + len <= r->start + r->size)
3186 if (em & F_EDRAM1_ENABLE) {
3187 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3188 r->size = G_EDRAM1_SIZE(addr_len) << 20;
3190 r->start = G_EDRAM1_BASE(addr_len) << 20;
3191 if (addr >= r->start &&
3192 addr + len <= r->start + r->size)
3198 if (em & F_EXT_MEM_ENABLE) {
3199 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3200 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
3202 r->start = G_EXT_MEM_BASE(addr_len) << 20;
3203 if (addr >= r->start &&
3204 addr + len <= r->start + r->size)
3210 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
3211 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3212 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
3214 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
3215 if (addr >= r->start &&
3216 addr + len <= r->start + r->size)
3222 MPASS(n <= nitems(mem_ranges));
3225 /* Sort and merge the ranges. */
3226 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
3228 /* Start from index 0 and examine the next n - 1 entries. */
3230 for (remaining = n - 1; remaining > 0; remaining--, r++) {
3232 MPASS(r->size > 0); /* r is a valid entry. */
3234 MPASS(next->size > 0); /* and so is the next one. */
3236 while (r->start + r->size >= next->start) {
3237 /* Merge the next one into the current entry. */
3238 r->size = max(r->start + r->size,
3239 next->start + next->size) - r->start;
3240 n--; /* One fewer entry in total. */
3241 if (--remaining == 0)
3242 goto done; /* short circuit */
3245 if (next != r + 1) {
3247 * Some entries were merged into r and next
3248 * points to the first valid entry that couldn't
3251 MPASS(next->size > 0); /* must be valid */
3252 memcpy(r + 1, next, remaining * sizeof(*r));
3255 * This so that the foo->size assertion in the
3256 * next iteration of the loop do the right
3257 * thing for entries that were pulled up and are
3260 MPASS(n < nitems(mem_ranges));
3261 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
3262 sizeof(struct t4_range));
3267 /* Done merging the ranges. */
3270 for (i = 0; i < n; i++, r++) {
3271 if (addr >= r->start &&
3272 addr + len <= r->start + r->size)
3281 fwmtype_to_hwmtype(int mtype)
3285 case FW_MEMTYPE_EDC0:
3287 case FW_MEMTYPE_EDC1:
3289 case FW_MEMTYPE_EXTMEM:
3291 case FW_MEMTYPE_EXTMEM1:
3294 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
3299 * Verify that the memory range specified by the memtype/offset/len pair is
3300 * valid and lies entirely within the memtype specified. The global address of
3301 * the start of the range is returned in addr.
3304 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
3307 uint32_t em, addr_len, maddr;
3309 /* Memory can only be accessed in naturally aligned 4 byte units */
3310 if (off & 3 || len & 3 || len == 0)
3313 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
3314 switch (fwmtype_to_hwmtype(mtype)) {
3316 if (!(em & F_EDRAM0_ENABLE))
3318 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
3319 maddr = G_EDRAM0_BASE(addr_len) << 20;
3322 if (!(em & F_EDRAM1_ENABLE))
3324 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3325 maddr = G_EDRAM1_BASE(addr_len) << 20;
3328 if (!(em & F_EXT_MEM_ENABLE))
3330 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3331 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3334 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3336 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3337 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3343 *addr = maddr + off; /* global address */
3344 return (validate_mem_range(sc, *addr, len));
3348 fixup_devlog_params(struct adapter *sc)
3350 struct devlog_params *dparams = &sc->params.devlog;
3353 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3354 dparams->size, &dparams->addr);
3360 update_nirq(struct intrs_and_queues *iaq, int nports)
3363 iaq->nirq = T4_EXTRA_INTR;
3364 iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
3365 iaq->nirq += nports * iaq->nofldrxq;
3366 iaq->nirq += nports * (iaq->num_vis - 1) *
3367 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3368 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3372 * Adjust requirements to fit the number of interrupts available.
3375 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3379 const int nports = sc->params.nports;
3384 bzero(iaq, sizeof(*iaq));
3385 iaq->intr_type = itype;
3386 iaq->num_vis = t4_num_vis;
3387 iaq->ntxq = t4_ntxq;
3388 iaq->ntxq_vi = t4_ntxq_vi;
3389 iaq->nrxq = t4_nrxq;
3390 iaq->nrxq_vi = t4_nrxq_vi;
3391 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3392 if (is_offload(sc) || is_ethoffload(sc)) {
3393 iaq->nofldtxq = t4_nofldtxq;
3394 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3398 if (is_offload(sc)) {
3399 iaq->nofldrxq = t4_nofldrxq;
3400 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3404 if (t4_native_netmap & NN_MAIN_VI) {
3405 iaq->nnmtxq = t4_nnmtxq;
3406 iaq->nnmrxq = t4_nnmrxq;
3408 if (t4_native_netmap & NN_EXTRA_VI) {
3409 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3410 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3414 update_nirq(iaq, nports);
3415 if (iaq->nirq <= navail &&
3416 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3418 * This is the normal case -- there are enough interrupts for
3425 * If extra VIs have been configured try reducing their count and see if
3428 while (iaq->num_vis > 1) {
3430 update_nirq(iaq, nports);
3431 if (iaq->nirq <= navail &&
3432 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3433 device_printf(sc->dev, "virtual interfaces per port "
3434 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3435 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3436 "itype %d, navail %u, nirq %d.\n",
3437 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3438 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3439 itype, navail, iaq->nirq);
3445 * Extra VIs will not be created. Log a message if they were requested.
3447 MPASS(iaq->num_vis == 1);
3448 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3449 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3450 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3451 if (iaq->num_vis != t4_num_vis) {
3452 device_printf(sc->dev, "extra virtual interfaces disabled. "
3453 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3454 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3455 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3456 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3460 * Keep reducing the number of NIC rx queues to the next lower power of
3461 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3465 if (iaq->nrxq > 1) {
3468 } while (!powerof2(iaq->nrxq));
3469 if (iaq->nnmrxq > iaq->nrxq)
3470 iaq->nnmrxq = iaq->nrxq;
3472 if (iaq->nofldrxq > 1)
3473 iaq->nofldrxq >>= 1;
3475 old_nirq = iaq->nirq;
3476 update_nirq(iaq, nports);
3477 if (iaq->nirq <= navail &&
3478 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3479 device_printf(sc->dev, "running with reduced number of "
3480 "rx queues because of shortage of interrupts. "
3481 "nrxq=%u, nofldrxq=%u. "
3482 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3483 iaq->nofldrxq, itype, navail, iaq->nirq);
3486 } while (old_nirq != iaq->nirq);
3488 /* One interrupt for everything. Ugh. */
3489 device_printf(sc->dev, "running with minimal number of queues. "
3490 "itype %d, navail %u.\n", itype, navail);
3494 if (iaq->nofldrxq > 0) {
3501 MPASS(iaq->num_vis > 0);
3502 if (iaq->num_vis > 1) {
3503 MPASS(iaq->nrxq_vi > 0);
3504 MPASS(iaq->ntxq_vi > 0);
3506 MPASS(iaq->nirq > 0);
3507 MPASS(iaq->nrxq > 0);
3508 MPASS(iaq->ntxq > 0);
3509 if (itype == INTR_MSI) {
3510 MPASS(powerof2(iaq->nirq));
3515 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3517 int rc, itype, navail, nalloc;
3519 for (itype = INTR_MSIX; itype; itype >>= 1) {
3521 if ((itype & t4_intr_types) == 0)
3522 continue; /* not allowed */
3524 if (itype == INTR_MSIX)
3525 navail = pci_msix_count(sc->dev);
3526 else if (itype == INTR_MSI)
3527 navail = pci_msi_count(sc->dev);
3534 calculate_iaq(sc, iaq, itype, navail);
3537 if (itype == INTR_MSIX)
3538 rc = pci_alloc_msix(sc->dev, &nalloc);
3539 else if (itype == INTR_MSI)
3540 rc = pci_alloc_msi(sc->dev, &nalloc);
3542 if (rc == 0 && nalloc > 0) {
3543 if (nalloc == iaq->nirq)
3547 * Didn't get the number requested. Use whatever number
3548 * the kernel is willing to allocate.
3550 device_printf(sc->dev, "fewer vectors than requested, "
3551 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3552 itype, iaq->nirq, nalloc);
3553 pci_release_msi(sc->dev);
3558 device_printf(sc->dev,
3559 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3560 itype, rc, iaq->nirq, nalloc);
3563 device_printf(sc->dev,
3564 "failed to find a usable interrupt type. "
3565 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3566 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3571 #define FW_VERSION(chip) ( \
3572 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3573 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3574 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3575 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3576 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3578 /* Just enough of fw_hdr to cover all version info. */
3584 __be32 tp_microcode_ver;
3589 __u8 intfver_iscsipdu;
3591 __u8 intfver_fcoepdu;
3594 /* Spot check a couple of fields. */
3595 CTASSERT(offsetof(struct fw_h, fw_ver) == offsetof(struct fw_hdr, fw_ver));
3596 CTASSERT(offsetof(struct fw_h, intfver_nic) == offsetof(struct fw_hdr, intfver_nic));
3597 CTASSERT(offsetof(struct fw_h, intfver_fcoe) == offsetof(struct fw_hdr, intfver_fcoe));
3607 .kld_name = "t4fw_cfg",
3608 .fw_mod_name = "t4fw",
3610 .chip = FW_HDR_CHIP_T4,
3611 .fw_ver = htobe32(FW_VERSION(T4)),
3612 .intfver_nic = FW_INTFVER(T4, NIC),
3613 .intfver_vnic = FW_INTFVER(T4, VNIC),
3614 .intfver_ofld = FW_INTFVER(T4, OFLD),
3615 .intfver_ri = FW_INTFVER(T4, RI),
3616 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3617 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3618 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3619 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3623 .kld_name = "t5fw_cfg",
3624 .fw_mod_name = "t5fw",
3626 .chip = FW_HDR_CHIP_T5,
3627 .fw_ver = htobe32(FW_VERSION(T5)),
3628 .intfver_nic = FW_INTFVER(T5, NIC),
3629 .intfver_vnic = FW_INTFVER(T5, VNIC),
3630 .intfver_ofld = FW_INTFVER(T5, OFLD),
3631 .intfver_ri = FW_INTFVER(T5, RI),
3632 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3633 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3634 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3635 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3639 .kld_name = "t6fw_cfg",
3640 .fw_mod_name = "t6fw",
3642 .chip = FW_HDR_CHIP_T6,
3643 .fw_ver = htobe32(FW_VERSION(T6)),
3644 .intfver_nic = FW_INTFVER(T6, NIC),
3645 .intfver_vnic = FW_INTFVER(T6, VNIC),
3646 .intfver_ofld = FW_INTFVER(T6, OFLD),
3647 .intfver_ri = FW_INTFVER(T6, RI),
3648 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3649 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3650 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3651 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3656 static struct fw_info *
3657 find_fw_info(int chip)
3661 for (i = 0; i < nitems(fw_info); i++) {
3662 if (fw_info[i].chip == chip)
3663 return (&fw_info[i]);
3669 * Is the given firmware API compatible with the one the driver was compiled
3673 fw_compatible(const struct fw_h *hdr1, const struct fw_h *hdr2)
3676 /* short circuit if it's the exact same firmware version */
3677 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3681 * XXX: Is this too conservative? Perhaps I should limit this to the
3682 * features that are supported in the driver.
3684 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3685 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3686 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3687 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3695 load_fw_module(struct adapter *sc, const struct firmware **dcfg,
3696 const struct firmware **fw)
3698 struct fw_info *fw_info;
3704 fw_info = find_fw_info(chip_id(sc));
3705 if (fw_info == NULL) {
3706 device_printf(sc->dev,
3707 "unable to look up firmware information for chip %d.\n",
3712 *dcfg = firmware_get(fw_info->kld_name);
3713 if (*dcfg != NULL) {
3715 *fw = firmware_get(fw_info->fw_mod_name);
3723 unload_fw_module(struct adapter *sc, const struct firmware *dcfg,
3724 const struct firmware *fw)
3728 firmware_put(fw, FIRMWARE_UNLOAD);
3730 firmware_put(dcfg, FIRMWARE_UNLOAD);
3735 * 0 means no firmware install attempted.
3736 * ERESTART means a firmware install was attempted and was successful.
3737 * +ve errno means a firmware install was attempted but failed.
3740 install_kld_firmware(struct adapter *sc, struct fw_h *card_fw,
3741 const struct fw_h *drv_fw, const char *reason, int *already)
3743 const struct firmware *cfg, *fw;
3744 const uint32_t c = be32toh(card_fw->fw_ver);
3747 struct fw_h bundled_fw;
3748 bool load_attempted;
3751 load_attempted = false;
3752 fw_install = t4_fw_install < 0 ? -t4_fw_install : t4_fw_install;
3754 memcpy(&bundled_fw, drv_fw, sizeof(bundled_fw));
3755 if (t4_fw_install < 0) {
3756 rc = load_fw_module(sc, &cfg, &fw);
3757 if (rc != 0 || fw == NULL) {
3758 device_printf(sc->dev,
3759 "failed to load firmware module: %d. cfg %p, fw %p;"
3760 " will use compiled-in firmware version for"
3761 "hw.cxgbe.fw_install checks.\n",
3764 memcpy(&bundled_fw, fw->data, sizeof(bundled_fw));
3766 load_attempted = true;
3768 d = be32toh(bundled_fw.fw_ver);
3773 if ((sc->flags & FW_OK) == 0) {
3775 if (c == 0xffffffff) {
3784 if (!fw_compatible(card_fw, &bundled_fw)) {
3785 reason = "incompatible or unusable";
3790 reason = "older than the version bundled with this driver";
3794 if (fw_install == 2 && d != c) {
3795 reason = "different than the version bundled with this driver";
3799 /* No reason to do anything to the firmware already on the card. */
3808 if (fw_install == 0) {
3809 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3810 "but the driver is prohibited from installing a firmware "
3812 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3813 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3819 * We'll attempt to install a firmware. Load the module first (if it
3820 * hasn't been loaded already).
3822 if (!load_attempted) {
3823 rc = load_fw_module(sc, &cfg, &fw);
3824 if (rc != 0 || fw == NULL) {
3825 device_printf(sc->dev,
3826 "failed to load firmware module: %d. cfg %p, fw %p\n",
3832 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3833 "but the driver cannot take corrective action because it "
3834 "is unable to load the firmware module.\n",
3835 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3836 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3837 rc = sc->flags & FW_OK ? 0 : ENOENT;
3840 k = be32toh(((const struct fw_hdr *)fw->data)->fw_ver);
3842 MPASS(t4_fw_install > 0);
3843 device_printf(sc->dev,
3844 "firmware in KLD (%u.%u.%u.%u) is not what the driver was "
3845 "expecting (%u.%u.%u.%u) and will not be used.\n",
3846 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3847 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k),
3848 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3849 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3850 rc = sc->flags & FW_OK ? 0 : EINVAL;
3854 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3855 "installing firmware %u.%u.%u.%u on card.\n",
3856 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3857 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3858 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3859 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3861 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3863 device_printf(sc->dev, "failed to install firmware: %d\n", rc);
3865 /* Installed successfully, update the cached header too. */
3867 memcpy(card_fw, fw->data, sizeof(*card_fw));
3870 unload_fw_module(sc, cfg, fw);
3876 * Establish contact with the firmware and attempt to become the master driver.
3878 * A firmware will be installed to the card if needed (if the driver is allowed
3882 contact_firmware(struct adapter *sc)
3884 int rc, already = 0;
3885 enum dev_state state;
3886 struct fw_info *fw_info;
3887 struct fw_hdr *card_fw; /* fw on the card */
3888 const struct fw_h *drv_fw;
3890 fw_info = find_fw_info(chip_id(sc));
3891 if (fw_info == NULL) {
3892 device_printf(sc->dev,
3893 "unable to look up firmware information for chip %d.\n",
3897 drv_fw = &fw_info->fw_h;
3899 /* Read the header of the firmware on the card */
3900 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3902 rc = -t4_get_fw_hdr(sc, card_fw);
3904 device_printf(sc->dev,
3905 "unable to read firmware header from card's flash: %d\n",
3910 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw, NULL,
3917 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3918 if (rc < 0 || state == DEV_STATE_ERR) {
3920 device_printf(sc->dev,
3921 "failed to connect to the firmware: %d, %d. "
3922 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3924 if (install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3925 "not responding properly to HELLO", &already) == ERESTART)
3930 MPASS(be32toh(card_fw->flags) & FW_HDR_FLAGS_RESET_HALT);
3931 sc->flags |= FW_OK; /* The firmware responded to the FW_HELLO. */
3934 sc->flags |= MASTER_PF;
3935 rc = install_kld_firmware(sc, (struct fw_h *)card_fw, drv_fw,
3941 } else if (state == DEV_STATE_UNINIT) {
3943 * We didn't get to be the master so we definitely won't be
3944 * configuring the chip. It's a bug if someone else hasn't
3945 * configured it already.
3947 device_printf(sc->dev, "couldn't be master(%d), "
3948 "device not already initialized either(%d). "
3949 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3954 * Some other PF is the master and has configured the chip.
3955 * This is allowed but untested.
3957 device_printf(sc->dev, "PF%d is master, device state %d. "
3958 "PCIE_FW 0x%08x\n", rc, state, t4_read_reg(sc, A_PCIE_FW));
3959 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", rc);
3964 if (rc != 0 && sc->flags & FW_OK) {
3965 t4_fw_bye(sc, sc->mbox);
3966 sc->flags &= ~FW_OK;
3968 free(card_fw, M_CXGBE);
3973 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
3974 uint32_t mtype, uint32_t moff)
3976 struct fw_info *fw_info;
3977 const struct firmware *dcfg, *rcfg = NULL;
3978 const uint32_t *cfdata;
3979 uint32_t cflen, addr;
3982 load_fw_module(sc, &dcfg, NULL);
3984 /* Card specific interpretation of "default". */
3985 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3986 if (pci_get_device(sc->dev) == 0x440a)
3987 snprintf(cfg_file, sizeof(t4_cfg_file), UWIRE_CF);
3989 snprintf(cfg_file, sizeof(t4_cfg_file), FPGA_CF);
3992 if (strncmp(cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3994 device_printf(sc->dev,
3995 "KLD with default config is not available.\n");
3999 cfdata = dcfg->data;
4000 cflen = dcfg->datasize & ~3;
4004 fw_info = find_fw_info(chip_id(sc));
4005 if (fw_info == NULL) {
4006 device_printf(sc->dev,
4007 "unable to look up firmware information for chip %d.\n",
4012 snprintf(s, sizeof(s), "%s_%s", fw_info->kld_name, cfg_file);
4014 rcfg = firmware_get(s);
4016 device_printf(sc->dev,
4017 "unable to load module \"%s\" for configuration "
4018 "profile \"%s\".\n", s, cfg_file);
4022 cfdata = rcfg->data;
4023 cflen = rcfg->datasize & ~3;
4026 if (cflen > FLASH_CFG_MAX_SIZE) {
4027 device_printf(sc->dev,
4028 "config file too long (%d, max allowed is %d).\n",
4029 cflen, FLASH_CFG_MAX_SIZE);
4034 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
4036 device_printf(sc->dev,
4037 "%s: addr (%d/0x%x) or len %d is not valid: %d.\n",
4038 __func__, mtype, moff, cflen, rc);
4042 write_via_memwin(sc, 2, addr, cfdata, cflen);
4045 firmware_put(rcfg, FIRMWARE_UNLOAD);
4046 unload_fw_module(sc, dcfg, NULL);
4050 struct caps_allowed {
4053 uint16_t switchcaps;
4057 uint16_t cryptocaps;
4062 #define FW_PARAM_DEV(param) \
4063 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
4064 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
4065 #define FW_PARAM_PFVF(param) \
4066 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
4067 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
4070 * Provide a configuration profile to the firmware and have it initialize the
4071 * chip accordingly. This may involve uploading a configuration file to the
4075 apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
4076 const struct caps_allowed *caps_allowed)
4079 struct fw_caps_config_cmd caps;
4080 uint32_t mtype, moff, finicsum, cfcsum, param, val;
4082 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
4084 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
4088 bzero(&caps, sizeof(caps));
4089 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4090 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4091 if (strncmp(cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) {
4094 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4095 } else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
4096 mtype = FW_MEMTYPE_FLASH;
4097 moff = t4_flash_cfg_addr(sc);
4098 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4099 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4100 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4104 * Ask the firmware where it wants us to upload the config file.
4106 param = FW_PARAM_DEV(CF);
4107 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4109 /* No support for config file? Shouldn't happen. */
4110 device_printf(sc->dev,
4111 "failed to query config file location: %d.\n", rc);
4114 mtype = G_FW_PARAMS_PARAM_Y(val);
4115 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
4116 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
4117 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
4118 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
4121 rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
4123 device_printf(sc->dev,
4124 "failed to upload config file to card: %d.\n", rc);
4128 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4130 device_printf(sc->dev, "failed to pre-process config file: %d "
4131 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
4135 finicsum = be32toh(caps.finicsum);
4136 cfcsum = be32toh(caps.cfcsum); /* actual */
4137 if (finicsum != cfcsum) {
4138 device_printf(sc->dev,
4139 "WARNING: config file checksum mismatch: %08x %08x\n",
4142 sc->cfcsum = cfcsum;
4143 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", cfg_file);
4146 * Let the firmware know what features will (not) be used so it can tune
4147 * things accordingly.
4149 #define LIMIT_CAPS(x) do { \
4150 caps.x##caps &= htobe16(caps_allowed->x##caps); \
4162 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4164 * TOE and hashfilters are mutually exclusive. It is a config
4165 * file or firmware bug if both are reported as available. Try
4166 * to cope with the situation in non-debug builds by disabling
4169 MPASS(caps.toecaps == 0);
4176 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4177 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4178 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4179 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
4181 device_printf(sc->dev,
4182 "failed to process config file: %d.\n", rc);
4186 t4_tweak_chip_settings(sc);
4187 set_params__pre_init(sc);
4189 /* get basic stuff going */
4190 rc = -t4_fw_initialize(sc, sc->mbox);
4192 device_printf(sc->dev, "fw_initialize failed: %d.\n", rc);
4200 * Partition chip resources for use between various PFs, VFs, etc.
4203 partition_resources(struct adapter *sc)
4205 char cfg_file[sizeof(t4_cfg_file)];
4206 struct caps_allowed caps_allowed;
4210 /* Only the master driver gets to configure the chip resources. */
4211 MPASS(sc->flags & MASTER_PF);
4213 #define COPY_CAPS(x) do { \
4214 caps_allowed.x##caps = t4_##x##caps_allowed; \
4216 bzero(&caps_allowed, sizeof(caps_allowed));
4226 fallback = sc->debug_flags & DF_DISABLE_CFG_RETRY ? false : true;
4227 snprintf(cfg_file, sizeof(cfg_file), "%s", t4_cfg_file);
4229 rc = apply_cfg_and_initialize(sc, cfg_file, &caps_allowed);
4230 if (rc != 0 && fallback) {
4231 device_printf(sc->dev,
4232 "failed (%d) to configure card with \"%s\" profile, "
4233 "will fall back to a basic configuration and retry.\n",
4235 snprintf(cfg_file, sizeof(cfg_file), "%s", BUILTIN_CF);
4236 bzero(&caps_allowed, sizeof(caps_allowed));
4238 caps_allowed.niccaps = FW_CAPS_CONFIG_NIC;
4247 * Retrieve parameters that are needed (or nice to have) very early.
4250 get_params__pre_init(struct adapter *sc)
4253 uint32_t param[2], val[2];
4255 t4_get_version_info(sc);
4257 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
4258 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
4259 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
4260 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
4261 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
4263 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
4264 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
4265 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
4266 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
4267 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
4269 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
4270 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
4271 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
4272 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
4273 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
4275 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
4276 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
4277 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
4278 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
4279 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
4281 param[0] = FW_PARAM_DEV(PORTVEC);
4282 param[1] = FW_PARAM_DEV(CCLK);
4283 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4285 device_printf(sc->dev,
4286 "failed to query parameters (pre_init): %d.\n", rc);
4290 sc->params.portvec = val[0];
4291 sc->params.nports = bitcount32(val[0]);
4292 sc->params.vpd.cclk = val[1];
4294 /* Read device log parameters. */
4295 rc = -t4_init_devlog_params(sc, 1);
4297 fixup_devlog_params(sc);
4299 device_printf(sc->dev,
4300 "failed to get devlog parameters: %d.\n", rc);
4301 rc = 0; /* devlog isn't critical for device operation */
4308 * Any params that need to be set before FW_INITIALIZE.
4311 set_params__pre_init(struct adapter *sc)
4314 uint32_t param, val;
4316 if (chip_id(sc) >= CHELSIO_T6) {
4317 param = FW_PARAM_DEV(HPFILTER_REGION_SUPPORT);
4319 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4320 /* firmwares < 1.20.1.0 do not have this param. */
4321 if (rc == FW_EINVAL &&
4322 sc->params.fw_vers < FW_VERSION32(1, 20, 1, 0)) {
4326 device_printf(sc->dev,
4327 "failed to enable high priority filters :%d.\n",
4332 /* Enable opaque VIIDs with firmwares that support it. */
4333 param = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4335 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4336 if (rc == 0 && val == 1)
4337 sc->params.viid_smt_extn_support = true;
4339 sc->params.viid_smt_extn_support = false;
4345 * Retrieve various parameters that are of interest to the driver. The device
4346 * has been initialized by the firmware at this point.
4349 get_params__post_init(struct adapter *sc)
4352 uint32_t param[7], val[7];
4353 struct fw_caps_config_cmd caps;
4355 param[0] = FW_PARAM_PFVF(IQFLINT_START);
4356 param[1] = FW_PARAM_PFVF(EQ_START);
4357 param[2] = FW_PARAM_PFVF(FILTER_START);
4358 param[3] = FW_PARAM_PFVF(FILTER_END);
4359 param[4] = FW_PARAM_PFVF(L2T_START);
4360 param[5] = FW_PARAM_PFVF(L2T_END);
4361 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
4362 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
4363 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
4364 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
4366 device_printf(sc->dev,
4367 "failed to query parameters (post_init): %d.\n", rc);
4371 sc->sge.iq_start = val[0];
4372 sc->sge.eq_start = val[1];
4373 if ((int)val[3] > (int)val[2]) {
4374 sc->tids.ftid_base = val[2];
4375 sc->tids.ftid_end = val[3];
4376 sc->tids.nftids = val[3] - val[2] + 1;
4378 sc->vres.l2t.start = val[4];
4379 sc->vres.l2t.size = val[5] - val[4] + 1;
4380 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
4381 ("%s: L2 table size (%u) larger than expected (%u)",
4382 __func__, sc->vres.l2t.size, L2T_SIZE));
4383 sc->params.core_vdd = val[6];
4385 if (chip_id(sc) >= CHELSIO_T6) {
4387 sc->tids.tid_base = t4_read_reg(sc,
4388 A_LE_DB_ACTIVE_TABLE_START_INDEX);
4390 param[0] = FW_PARAM_PFVF(HPFILTER_START);
4391 param[1] = FW_PARAM_PFVF(HPFILTER_END);
4392 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4394 device_printf(sc->dev,
4395 "failed to query hpfilter parameters: %d.\n", rc);
4398 if ((int)val[1] > (int)val[0]) {
4399 sc->tids.hpftid_base = val[0];
4400 sc->tids.hpftid_end = val[1];
4401 sc->tids.nhpftids = val[1] - val[0] + 1;
4404 * These should go off if the layout changes and the
4405 * driver needs to catch up.
4407 MPASS(sc->tids.hpftid_base == 0);
4408 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
4413 * MPSBGMAP is queried separately because only recent firmwares support
4414 * it as a parameter and we don't want the compound query above to fail
4415 * on older firmwares.
4417 param[0] = FW_PARAM_DEV(MPSBGMAP);
4419 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4421 sc->params.mps_bg_map = val[0];
4423 sc->params.mps_bg_map = 0;
4426 * Determine whether the firmware supports the filter2 work request.
4427 * This is queried separately for the same reason as MPSBGMAP above.
4429 param[0] = FW_PARAM_DEV(FILTER2_WR);
4431 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4433 sc->params.filter2_wr_support = val[0] != 0;
4435 sc->params.filter2_wr_support = 0;
4438 * Find out whether we're allowed to use the ULPTX MEMWRITE DSGL.
4439 * This is queried separately for the same reason as other params above.
4441 param[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4443 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4445 sc->params.ulptx_memwrite_dsgl = val[0] != 0;
4447 sc->params.ulptx_memwrite_dsgl = false;
4449 /* FW_RI_FR_NSMR_TPTE_WR support */
4450 param[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4451 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4453 sc->params.fr_nsmr_tpte_wr_support = val[0] != 0;
4455 sc->params.fr_nsmr_tpte_wr_support = false;
4457 /* get capabilites */
4458 bzero(&caps, sizeof(caps));
4459 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4460 F_FW_CMD_REQUEST | F_FW_CMD_READ);
4461 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
4462 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
4464 device_printf(sc->dev,
4465 "failed to get card capabilities: %d.\n", rc);
4469 #define READ_CAPS(x) do { \
4470 sc->x = htobe16(caps.x); \
4473 READ_CAPS(linkcaps);
4474 READ_CAPS(switchcaps);
4477 READ_CAPS(rdmacaps);
4478 READ_CAPS(cryptocaps);
4479 READ_CAPS(iscsicaps);
4480 READ_CAPS(fcoecaps);
4482 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4483 MPASS(chip_id(sc) > CHELSIO_T4);
4484 MPASS(sc->toecaps == 0);
4487 param[0] = FW_PARAM_DEV(NTID);
4488 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4490 device_printf(sc->dev,
4491 "failed to query HASHFILTER parameters: %d.\n", rc);
4494 sc->tids.ntids = val[0];
4495 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
4496 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4497 sc->tids.ntids -= sc->tids.nhpftids;
4499 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4500 sc->params.hash_filter = 1;
4502 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4503 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4504 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4505 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4506 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4508 device_printf(sc->dev,
4509 "failed to query NIC parameters: %d.\n", rc);
4512 if ((int)val[1] > (int)val[0]) {
4513 sc->tids.etid_base = val[0];
4514 sc->tids.etid_end = val[1];
4515 sc->tids.netids = val[1] - val[0] + 1;
4516 sc->params.eo_wr_cred = val[2];
4517 sc->params.ethoffload = 1;
4521 /* query offload-related parameters */
4522 param[0] = FW_PARAM_DEV(NTID);
4523 param[1] = FW_PARAM_PFVF(SERVER_START);
4524 param[2] = FW_PARAM_PFVF(SERVER_END);
4525 param[3] = FW_PARAM_PFVF(TDDP_START);
4526 param[4] = FW_PARAM_PFVF(TDDP_END);
4527 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4528 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4530 device_printf(sc->dev,
4531 "failed to query TOE parameters: %d.\n", rc);
4534 sc->tids.ntids = val[0];
4535 if (sc->params.fw_vers < FW_VERSION32(1, 20, 5, 0)) {
4536 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4537 sc->tids.ntids -= sc->tids.nhpftids;
4539 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4540 if ((int)val[2] > (int)val[1]) {
4541 sc->tids.stid_base = val[1];
4542 sc->tids.nstids = val[2] - val[1] + 1;
4544 sc->vres.ddp.start = val[3];
4545 sc->vres.ddp.size = val[4] - val[3] + 1;
4546 sc->params.ofldq_wr_cred = val[5];
4547 sc->params.offload = 1;
4550 * The firmware attempts memfree TOE configuration for -SO cards
4551 * and will report toecaps=0 if it runs out of resources (this
4552 * depends on the config file). It may not report 0 for other
4553 * capabilities dependent on the TOE in this case. Set them to
4554 * 0 here so that the driver doesn't bother tracking resources
4555 * that will never be used.
4561 param[0] = FW_PARAM_PFVF(STAG_START);
4562 param[1] = FW_PARAM_PFVF(STAG_END);
4563 param[2] = FW_PARAM_PFVF(RQ_START);
4564 param[3] = FW_PARAM_PFVF(RQ_END);
4565 param[4] = FW_PARAM_PFVF(PBL_START);
4566 param[5] = FW_PARAM_PFVF(PBL_END);
4567 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4569 device_printf(sc->dev,
4570 "failed to query RDMA parameters(1): %d.\n", rc);
4573 sc->vres.stag.start = val[0];
4574 sc->vres.stag.size = val[1] - val[0] + 1;
4575 sc->vres.rq.start = val[2];
4576 sc->vres.rq.size = val[3] - val[2] + 1;
4577 sc->vres.pbl.start = val[4];
4578 sc->vres.pbl.size = val[5] - val[4] + 1;
4580 param[0] = FW_PARAM_PFVF(SQRQ_START);
4581 param[1] = FW_PARAM_PFVF(SQRQ_END);
4582 param[2] = FW_PARAM_PFVF(CQ_START);
4583 param[3] = FW_PARAM_PFVF(CQ_END);
4584 param[4] = FW_PARAM_PFVF(OCQ_START);
4585 param[5] = FW_PARAM_PFVF(OCQ_END);
4586 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4588 device_printf(sc->dev,
4589 "failed to query RDMA parameters(2): %d.\n", rc);
4592 sc->vres.qp.start = val[0];
4593 sc->vres.qp.size = val[1] - val[0] + 1;
4594 sc->vres.cq.start = val[2];
4595 sc->vres.cq.size = val[3] - val[2] + 1;
4596 sc->vres.ocq.start = val[4];
4597 sc->vres.ocq.size = val[5] - val[4] + 1;
4599 param[0] = FW_PARAM_PFVF(SRQ_START);
4600 param[1] = FW_PARAM_PFVF(SRQ_END);
4601 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4602 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4603 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4605 device_printf(sc->dev,
4606 "failed to query RDMA parameters(3): %d.\n", rc);
4609 sc->vres.srq.start = val[0];
4610 sc->vres.srq.size = val[1] - val[0] + 1;
4611 sc->params.max_ordird_qp = val[2];
4612 sc->params.max_ird_adapter = val[3];
4614 if (sc->iscsicaps) {
4615 param[0] = FW_PARAM_PFVF(ISCSI_START);
4616 param[1] = FW_PARAM_PFVF(ISCSI_END);
4617 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4619 device_printf(sc->dev,
4620 "failed to query iSCSI parameters: %d.\n", rc);
4623 sc->vres.iscsi.start = val[0];
4624 sc->vres.iscsi.size = val[1] - val[0] + 1;
4626 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4627 param[0] = FW_PARAM_PFVF(TLS_START);
4628 param[1] = FW_PARAM_PFVF(TLS_END);
4629 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4631 device_printf(sc->dev,
4632 "failed to query TLS parameters: %d.\n", rc);
4635 sc->vres.key.start = val[0];
4636 sc->vres.key.size = val[1] - val[0] + 1;
4639 t4_init_sge_params(sc);
4642 * We've got the params we wanted to query via the firmware. Now grab
4643 * some others directly from the chip.
4645 rc = t4_read_chip_settings(sc);
4652 ktls_tick(void *arg)
4659 tstamp = tcp_ts_getticks();
4660 t4_write_reg(sc, A_TP_SYNC_TIME_HI, tstamp >> 1);
4661 t4_write_reg(sc, A_TP_SYNC_TIME_LO, tstamp << 31);
4663 callout_schedule_sbt(&sc->ktls_tick, SBT_1MS, 0, C_HARDCLOCK);
4667 t4_enable_kern_tls(struct adapter *sc)
4673 t4_set_reg_field(sc, A_TP_PARA_REG6, m, v);
4675 m = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN;
4676 v = F_CPL_FLAGS_UPDATE_EN | F_SEQ_UPDATE_EN;
4677 t4_set_reg_field(sc, A_ULP_TX_CONFIG, m, v);
4681 t4_set_reg_field(sc, A_TP_IN_CONFIG, m, v);
4683 m = F_LOOKUPEVERYPKT;
4685 t4_set_reg_field(sc, A_TP_INGRESS_CONFIG, m, v);
4687 m = F_TXDEFERENABLE | F_DISABLEWINDOWPSH | F_DISABLESEPPSHFLAG;
4688 v = F_DISABLEWINDOWPSH;
4689 t4_set_reg_field(sc, A_TP_PC_CONFIG, m, v);
4691 m = V_TIMESTAMPRESOLUTION(M_TIMESTAMPRESOLUTION);
4692 v = V_TIMESTAMPRESOLUTION(0x1f);
4693 t4_set_reg_field(sc, A_TP_TIMER_RESOLUTION, m, v);
4695 sc->flags |= KERN_TLS_OK;
4697 sc->tlst.inline_keys = t4_tls_inline_keys;
4698 sc->tlst.combo_wrs = t4_tls_combo_wrs;
4703 set_params__post_init(struct adapter *sc)
4705 uint32_t param, val;
4710 /* ask for encapsulated CPLs */
4711 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4713 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4715 /* Enable 32b port caps if the firmware supports it. */
4716 param = FW_PARAM_PFVF(PORT_CAPS32);
4718 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4719 sc->params.port_caps32 = 1;
4721 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4722 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4723 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4724 V_MASKFILTER(val - 1));
4728 * Override the TOE timers with user provided tunables. This is not the
4729 * recommended way to change the timers (the firmware config file is) so
4730 * these tunables are not documented.
4732 * All the timer tunables are in microseconds.
4734 if (t4_toe_keepalive_idle != 0) {
4735 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4736 v &= M_KEEPALIVEIDLE;
4737 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4738 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4740 if (t4_toe_keepalive_interval != 0) {
4741 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4742 v &= M_KEEPALIVEINTVL;
4743 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4744 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4746 if (t4_toe_keepalive_count != 0) {
4747 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4748 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4749 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4750 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4751 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4753 if (t4_toe_rexmt_min != 0) {
4754 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4756 t4_set_reg_field(sc, A_TP_RXT_MIN,
4757 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4759 if (t4_toe_rexmt_max != 0) {
4760 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4762 t4_set_reg_field(sc, A_TP_RXT_MAX,
4763 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4765 if (t4_toe_rexmt_count != 0) {
4766 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4767 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4768 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4769 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4770 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4772 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4773 if (t4_toe_rexmt_backoff[i] != -1) {
4774 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4775 shift = (i & 3) << 3;
4776 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4777 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4783 if (t4_kern_tls != 0 && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
4784 sc->toecaps & FW_CAPS_CONFIG_TOE)
4785 t4_enable_kern_tls(sc);
4790 #undef FW_PARAM_PFVF
4794 t4_set_desc(struct adapter *sc)
4797 struct adapter_params *p = &sc->params;
4799 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4801 device_set_desc_copy(sc->dev, buf);
4805 ifmedia_add4(struct ifmedia *ifm, int m)
4808 ifmedia_add(ifm, m, 0, NULL);
4809 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4810 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4811 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4815 * This is the selected media, which is not quite the same as the active media.
4816 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4817 * and active are not the same, and "media: Ethernet selected" otherwise.
4820 set_current_media(struct port_info *pi)
4822 struct link_config *lc;
4823 struct ifmedia *ifm;
4827 PORT_LOCK_ASSERT_OWNED(pi);
4829 /* Leave current media alone if it's already set to IFM_NONE. */
4831 if (ifm->ifm_cur != NULL &&
4832 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4836 if (lc->requested_aneg != AUTONEG_DISABLE &&
4837 lc->pcaps & FW_PORT_CAP32_ANEG) {
4838 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4841 mword = IFM_ETHER | IFM_FDX;
4842 if (lc->requested_fc & PAUSE_TX)
4843 mword |= IFM_ETH_TXPAUSE;
4844 if (lc->requested_fc & PAUSE_RX)
4845 mword |= IFM_ETH_RXPAUSE;
4846 if (lc->requested_speed == 0)
4847 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4849 speed = lc->requested_speed;
4850 mword |= port_mword(pi, speed_to_fwcap(speed));
4851 ifmedia_set(ifm, mword);
4855 * Returns true if the ifmedia list for the port cannot change.
4858 fixed_ifmedia(struct port_info *pi)
4861 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4862 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4863 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4864 pi->port_type == FW_PORT_TYPE_KX4 ||
4865 pi->port_type == FW_PORT_TYPE_KX ||
4866 pi->port_type == FW_PORT_TYPE_KR ||
4867 pi->port_type == FW_PORT_TYPE_BP_AP ||
4868 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4869 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4870 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4871 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4872 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4876 build_medialist(struct port_info *pi)
4879 int unknown, mword, bit;
4880 struct link_config *lc;
4881 struct ifmedia *ifm;
4883 PORT_LOCK_ASSERT_OWNED(pi);
4885 if (pi->flags & FIXED_IFMEDIA)
4889 * Rebuild the ifmedia list.
4892 ifmedia_removeall(ifm);
4894 ss = G_FW_PORT_CAP32_SPEED(lc->pcaps); /* Supported Speeds */
4895 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4898 MPASS(LIST_EMPTY(&ifm->ifm_list));
4899 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4900 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4905 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4907 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4909 mword = port_mword(pi, speed);
4910 if (mword == IFM_NONE) {
4912 } else if (mword == IFM_UNKNOWN)
4915 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4918 if (unknown > 0) /* Add one unknown for all unknown media types. */
4919 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4920 if (lc->pcaps & FW_PORT_CAP32_ANEG)
4921 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4923 set_current_media(pi);
4927 * Initialize the requested fields in the link config based on driver tunables.
4930 init_link_config(struct port_info *pi)
4932 struct link_config *lc = &pi->link_cfg;
4934 PORT_LOCK_ASSERT_OWNED(pi);
4936 lc->requested_speed = 0;
4938 if (t4_autoneg == 0)
4939 lc->requested_aneg = AUTONEG_DISABLE;
4940 else if (t4_autoneg == 1)
4941 lc->requested_aneg = AUTONEG_ENABLE;
4943 lc->requested_aneg = AUTONEG_AUTO;
4945 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4948 if (t4_fec & FEC_AUTO)
4949 lc->requested_fec = FEC_AUTO;
4950 else if (t4_fec == 0)
4951 lc->requested_fec = FEC_NONE;
4953 /* -1 is handled by the FEC_AUTO block above and not here. */
4954 lc->requested_fec = t4_fec &
4955 (FEC_RS | FEC_BASER_RS | FEC_NONE | FEC_MODULE);
4956 if (lc->requested_fec == 0)
4957 lc->requested_fec = FEC_AUTO;
4962 * Makes sure that all requested settings comply with what's supported by the
4963 * port. Returns the number of settings that were invalid and had to be fixed.
4966 fixup_link_config(struct port_info *pi)
4969 struct link_config *lc = &pi->link_cfg;
4972 PORT_LOCK_ASSERT_OWNED(pi);
4974 /* Speed (when not autonegotiating) */
4975 if (lc->requested_speed != 0) {
4976 fwspeed = speed_to_fwcap(lc->requested_speed);
4977 if ((fwspeed & lc->pcaps) == 0) {
4979 lc->requested_speed = 0;
4983 /* Link autonegotiation */
4984 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4985 lc->requested_aneg == AUTONEG_DISABLE ||
4986 lc->requested_aneg == AUTONEG_AUTO);
4987 if (lc->requested_aneg == AUTONEG_ENABLE &&
4988 !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4990 lc->requested_aneg = AUTONEG_AUTO;
4994 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4995 if (lc->requested_fc & PAUSE_TX &&
4996 !(lc->pcaps & FW_PORT_CAP32_FC_TX)) {
4998 lc->requested_fc &= ~PAUSE_TX;
5000 if (lc->requested_fc & PAUSE_RX &&
5001 !(lc->pcaps & FW_PORT_CAP32_FC_RX)) {
5003 lc->requested_fc &= ~PAUSE_RX;
5005 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
5006 !(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)) {
5008 lc->requested_fc |= PAUSE_AUTONEG;
5012 if ((lc->requested_fec & FEC_RS &&
5013 !(lc->pcaps & FW_PORT_CAP32_FEC_RS)) ||
5014 (lc->requested_fec & FEC_BASER_RS &&
5015 !(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS))) {
5017 lc->requested_fec = FEC_AUTO;
5024 * Apply the requested L1 settings, which are expected to be valid, to the
5028 apply_link_config(struct port_info *pi)
5030 struct adapter *sc = pi->adapter;
5031 struct link_config *lc = &pi->link_cfg;
5035 ASSERT_SYNCHRONIZED_OP(sc);
5036 PORT_LOCK_ASSERT_OWNED(pi);
5038 if (lc->requested_aneg == AUTONEG_ENABLE)
5039 MPASS(lc->pcaps & FW_PORT_CAP32_ANEG);
5040 if (!(lc->requested_fc & PAUSE_AUTONEG))
5041 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE);
5042 if (lc->requested_fc & PAUSE_TX)
5043 MPASS(lc->pcaps & FW_PORT_CAP32_FC_TX);
5044 if (lc->requested_fc & PAUSE_RX)
5045 MPASS(lc->pcaps & FW_PORT_CAP32_FC_RX);
5046 if (lc->requested_fec & FEC_RS)
5047 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_RS);
5048 if (lc->requested_fec & FEC_BASER_RS)
5049 MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
5051 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5053 /* Don't complain if the VF driver gets back an EPERM. */
5054 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
5055 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
5058 * An L1_CFG will almost always result in a link-change event if
5059 * the link is up, and the driver will refresh the actual
5060 * fec/fc/etc. when the notification is processed. If the link
5061 * is down then the actual settings are meaningless.
5063 * This takes care of the case where a change in the L1 settings
5064 * may not result in a notification.
5066 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
5067 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
5072 #define FW_MAC_EXACT_CHUNK 7
5075 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
5083 add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
5085 struct mcaddr_ctx *ctx = arg;
5086 struct vi_info *vi = ctx->ifp->if_softc;
5087 struct port_info *pi = vi->pi;
5088 struct adapter *sc = pi->adapter;
5093 ctx->mcaddr[ctx->i] = LLADDR(sdl);
5094 MPASS(ETHER_IS_MULTICAST(ctx->mcaddr[ctx->i]));
5097 if (ctx->i == FW_MAC_EXACT_CHUNK) {
5098 ctx->rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, ctx->del,
5099 ctx->i, ctx->mcaddr, NULL, &ctx->hash, 0);
5103 for (j = 0; j < ctx->i; j++) {
5105 "failed to add mc address"
5107 "%02x:%02x:%02x rc=%d\n",
5108 ctx->mcaddr[j][0], ctx->mcaddr[j][1],
5109 ctx->mcaddr[j][2], ctx->mcaddr[j][3],
5110 ctx->mcaddr[j][4], ctx->mcaddr[j][5],
5123 * Program the port's XGMAC based on parameters in ifnet. The caller also
5124 * indicates which parameters should be programmed (the rest are left alone).
5127 update_mac_settings(struct ifnet *ifp, int flags)
5130 struct vi_info *vi = ifp->if_softc;
5131 struct port_info *pi = vi->pi;
5132 struct adapter *sc = pi->adapter;
5133 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
5135 ASSERT_SYNCHRONIZED_OP(sc);
5136 KASSERT(flags, ("%s: not told what to update.", __func__));
5138 if (flags & XGMAC_MTU)
5141 if (flags & XGMAC_PROMISC)
5142 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
5144 if (flags & XGMAC_ALLMULTI)
5145 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
5147 if (flags & XGMAC_VLANEX)
5148 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
5150 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
5151 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
5152 allmulti, 1, vlanex, false);
5154 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
5160 if (flags & XGMAC_UCADDR) {
5161 uint8_t ucaddr[ETHER_ADDR_LEN];
5163 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
5164 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
5165 ucaddr, true, &vi->smt_idx);
5168 if_printf(ifp, "change_mac failed: %d\n", rc);
5171 vi->xact_addr_filt = rc;
5176 if (flags & XGMAC_MCADDRS) {
5177 struct epoch_tracker et;
5178 struct mcaddr_ctx ctx;
5187 * Unlike other drivers, we accumulate list of pointers into
5188 * interface address lists and we need to keep it safe even
5189 * after if_foreach_llmaddr() returns, thus we must enter the
5192 NET_EPOCH_ENTER(et);
5193 if_foreach_llmaddr(ifp, add_maddr, &ctx);
5200 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
5201 ctx.del, ctx.i, ctx.mcaddr, NULL, &ctx.hash, 0);
5205 for (j = 0; j < ctx.i; j++) {
5207 "failed to add mc address"
5209 "%02x:%02x:%02x rc=%d\n",
5210 ctx.mcaddr[j][0], ctx.mcaddr[j][1],
5211 ctx.mcaddr[j][2], ctx.mcaddr[j][3],
5212 ctx.mcaddr[j][4], ctx.mcaddr[j][5],
5220 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, ctx.hash, 0);
5222 if_printf(ifp, "failed to set mc address hash: %d", rc);
5229 * {begin|end}_synchronized_op must be called from the same thread.
5232 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
5238 /* the caller thinks it's ok to sleep, but is it really? */
5239 if (flags & SLEEP_OK)
5240 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
5241 "begin_synchronized_op");
5252 if (vi && IS_DOOMED(vi)) {
5262 if (!(flags & SLEEP_OK)) {
5267 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
5273 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
5276 sc->last_op = wmesg;
5277 sc->last_op_thr = curthread;
5278 sc->last_op_flags = flags;
5282 if (!(flags & HOLD_LOCK) || rc)
5289 * Tell if_ioctl and if_init that the VI is going away. This is
5290 * special variant of begin_synchronized_op and must be paired with a
5291 * call to end_synchronized_op.
5294 doom_vi(struct adapter *sc, struct vi_info *vi)
5301 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
5304 sc->last_op = "t4detach";
5305 sc->last_op_thr = curthread;
5306 sc->last_op_flags = 0;
5312 * {begin|end}_synchronized_op must be called from the same thread.
5315 end_synchronized_op(struct adapter *sc, int flags)
5318 if (flags & LOCK_HELD)
5319 ADAPTER_LOCK_ASSERT_OWNED(sc);
5323 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
5330 cxgbe_init_synchronized(struct vi_info *vi)
5332 struct port_info *pi = vi->pi;
5333 struct adapter *sc = pi->adapter;
5334 struct ifnet *ifp = vi->ifp;
5336 struct sge_txq *txq;
5338 ASSERT_SYNCHRONIZED_OP(sc);
5340 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5341 return (0); /* already running */
5343 if (!(sc->flags & FULL_INIT_DONE) &&
5344 ((rc = adapter_full_init(sc)) != 0))
5345 return (rc); /* error message displayed already */
5347 if (!(vi->flags & VI_INIT_DONE) &&
5348 ((rc = vi_full_init(vi)) != 0))
5349 return (rc); /* error message displayed already */
5351 rc = update_mac_settings(ifp, XGMAC_ALL);
5353 goto done; /* error message displayed already */
5356 if (pi->up_vis == 0) {
5357 t4_update_port_info(pi);
5358 fixup_link_config(pi);
5359 build_medialist(pi);
5360 apply_link_config(pi);
5363 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
5365 if_printf(ifp, "enable_vi failed: %d\n", rc);
5371 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
5375 for_each_txq(vi, i, txq) {
5377 txq->eq.flags |= EQ_ENABLED;
5382 * The first iq of the first port to come up is used for tracing.
5384 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
5385 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
5386 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
5387 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
5388 V_QUEUENUMBER(sc->traceq));
5389 pi->flags |= HAS_TRACEQ;
5394 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5396 if (pi->nvi > 1 || sc->flags & IS_VF)
5397 callout_reset(&vi->tick, hz, vi_tick, vi);
5399 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
5400 if (pi->link_cfg.link_ok)
5401 t4_os_link_changed(pi);
5405 cxgbe_uninit_synchronized(vi);
5414 cxgbe_uninit_synchronized(struct vi_info *vi)
5416 struct port_info *pi = vi->pi;
5417 struct adapter *sc = pi->adapter;
5418 struct ifnet *ifp = vi->ifp;
5420 struct sge_txq *txq;
5422 ASSERT_SYNCHRONIZED_OP(sc);
5424 if (!(vi->flags & VI_INIT_DONE)) {
5425 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5426 KASSERT(0, ("uninited VI is running"));
5427 if_printf(ifp, "uninited VI with running ifnet. "
5428 "vi->flags 0x%016lx, if_flags 0x%08x, "
5429 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
5436 * Disable the VI so that all its data in either direction is discarded
5437 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
5438 * tick) intact as the TP can deliver negative advice or data that it's
5439 * holding in its RAM (for an offloaded connection) even after the VI is
5442 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
5444 if_printf(ifp, "disable_vi failed: %d\n", rc);
5448 for_each_txq(vi, i, txq) {
5450 txq->eq.flags &= ~EQ_ENABLED;
5455 if (pi->nvi > 1 || sc->flags & IS_VF)
5456 callout_stop(&vi->tick);
5458 callout_stop(&pi->tick);
5459 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5463 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5465 if (pi->up_vis > 0) {
5470 pi->link_cfg.link_ok = false;
5471 pi->link_cfg.speed = 0;
5472 pi->link_cfg.link_down_rc = 255;
5473 t4_os_link_changed(pi);
5480 * It is ok for this function to fail midway and return right away. t4_detach
5481 * will walk the entire sc->irq list and clean up whatever is valid.
5484 t4_setup_intr_handlers(struct adapter *sc)
5486 int rc, rid, p, q, v;
5489 struct port_info *pi;
5491 struct sge *sge = &sc->sge;
5492 struct sge_rxq *rxq;
5494 struct sge_ofld_rxq *ofld_rxq;
5497 struct sge_nm_rxq *nm_rxq;
5500 int nbuckets = rss_getnumbuckets();
5507 rid = sc->intr_type == INTR_INTX ? 0 : 1;
5508 if (forwarding_intr_to_fwq(sc))
5509 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
5511 /* Multiple interrupts. */
5512 if (sc->flags & IS_VF)
5513 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
5514 ("%s: too few intr.", __func__));
5516 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
5517 ("%s: too few intr.", __func__));
5519 /* The first one is always error intr on PFs */
5520 if (!(sc->flags & IS_VF)) {
5521 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
5528 /* The second one is always the firmware event queue (first on VFs) */
5529 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
5535 for_each_port(sc, p) {
5537 for_each_vi(pi, v, vi) {
5538 vi->first_intr = rid - 1;
5540 if (vi->nnmrxq > 0) {
5541 int n = max(vi->nrxq, vi->nnmrxq);
5543 rxq = &sge->rxq[vi->first_rxq];
5545 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
5547 for (q = 0; q < n; q++) {
5548 snprintf(s, sizeof(s), "%x%c%x", p,
5554 irq->nm_rxq = nm_rxq++;
5556 if (irq->nm_rxq != NULL &&
5558 /* Netmap rx only */
5559 rc = t4_alloc_irq(sc, irq, rid,
5560 t4_nm_intr, irq->nm_rxq, s);
5562 if (irq->nm_rxq != NULL &&
5564 /* NIC and Netmap rx */
5565 rc = t4_alloc_irq(sc, irq, rid,
5566 t4_vi_intr, irq, s);
5569 if (irq->rxq != NULL &&
5570 irq->nm_rxq == NULL) {
5572 rc = t4_alloc_irq(sc, irq, rid,
5573 t4_intr, irq->rxq, s);
5579 bus_bind_intr(sc->dev, irq->res,
5580 rss_getcpu(q % nbuckets));
5588 for_each_rxq(vi, q, rxq) {
5589 snprintf(s, sizeof(s), "%x%c%x", p,
5591 rc = t4_alloc_irq(sc, irq, rid,
5596 bus_bind_intr(sc->dev, irq->res,
5597 rss_getcpu(q % nbuckets));
5605 for_each_ofld_rxq(vi, q, ofld_rxq) {
5606 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5607 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5618 MPASS(irq == &sc->irq[sc->intr_count]);
5624 adapter_full_init(struct adapter *sc)
5628 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5629 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5632 ASSERT_SYNCHRONIZED_OP(sc);
5633 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5634 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5635 ("%s: FULL_INIT_DONE already", __func__));
5638 * queues that belong to the adapter (not any particular port).
5640 rc = t4_setup_adapter_queues(sc);
5644 for (i = 0; i < nitems(sc->tq); i++) {
5645 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5646 taskqueue_thread_enqueue, &sc->tq[i]);
5647 if (sc->tq[i] == NULL) {
5648 device_printf(sc->dev,
5649 "failed to allocate task queue %d\n", i);
5653 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5654 device_get_nameunit(sc->dev), i);
5657 MPASS(RSS_KEYSIZE == 40);
5658 rss_getkey((void *)&raw_rss_key[0]);
5659 for (i = 0; i < nitems(rss_key); i++) {
5660 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5662 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5665 if (!(sc->flags & IS_VF))
5668 if (sc->flags & KERN_TLS_OK)
5669 callout_reset_sbt(&sc->ktls_tick, SBT_1MS, 0, ktls_tick, sc,
5672 sc->flags |= FULL_INIT_DONE;
5675 adapter_full_uninit(sc);
5681 adapter_full_uninit(struct adapter *sc)
5685 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5687 t4_teardown_adapter_queues(sc);
5689 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5690 taskqueue_free(sc->tq[i]);
5694 sc->flags &= ~FULL_INIT_DONE;
5700 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5701 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5702 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5703 RSS_HASHTYPE_RSS_UDP_IPV6)
5705 /* Translates kernel hash types to hardware. */
5707 hashconfig_to_hashen(int hashconfig)
5711 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5712 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5713 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5714 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5715 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5716 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5717 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5719 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5720 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5721 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5723 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5724 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5725 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5726 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5731 /* Translates hardware hash types to kernel. */
5733 hashen_to_hashconfig(int hashen)
5737 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5739 * If UDP hashing was enabled it must have been enabled for
5740 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5741 * enabling any 4-tuple hash is nonsense configuration.
5743 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5744 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5746 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5747 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5748 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5749 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5751 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5752 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5753 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5754 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5755 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5756 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5757 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5758 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5760 return (hashconfig);
5765 vi_full_init(struct vi_info *vi)
5767 struct adapter *sc = vi->pi->adapter;
5768 struct ifnet *ifp = vi->ifp;
5770 struct sge_rxq *rxq;
5773 int nbuckets = rss_getnumbuckets();
5774 int hashconfig = rss_gethashconfig();
5778 ASSERT_SYNCHRONIZED_OP(sc);
5779 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5780 ("%s: VI_INIT_DONE already", __func__));
5782 sysctl_ctx_init(&vi->ctx);
5783 vi->flags |= VI_SYSCTL_CTX;
5786 * Allocate tx/rx/fl queues for this VI.
5788 rc = t4_setup_vi_queues(vi);
5790 goto done; /* error message displayed already */
5793 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5795 if (vi->nrxq > vi->rss_size) {
5796 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5797 "some queues will never receive traffic.\n", vi->nrxq,
5799 } else if (vi->rss_size % vi->nrxq) {
5800 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5801 "expect uneven traffic distribution.\n", vi->nrxq,
5805 if (vi->nrxq != nbuckets) {
5806 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5807 "performance will be impacted.\n", vi->nrxq, nbuckets);
5810 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5811 for (i = 0; i < vi->rss_size;) {
5813 j = rss_get_indirection_to_bucket(i);
5815 rxq = &sc->sge.rxq[vi->first_rxq + j];
5816 rss[i++] = rxq->iq.abs_id;
5818 for_each_rxq(vi, j, rxq) {
5819 rss[i++] = rxq->iq.abs_id;
5820 if (i == vi->rss_size)
5826 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5830 if_printf(ifp, "rss_config failed: %d\n", rc);
5835 vi->hashen = hashconfig_to_hashen(hashconfig);
5838 * We may have had to enable some hashes even though the global config
5839 * wants them disabled. This is a potential problem that must be
5840 * reported to the user.
5842 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5845 * If we consider only the supported hash types, then the enabled hashes
5846 * are a superset of the requested hashes. In other words, there cannot
5847 * be any supported hash that was requested but not enabled, but there
5848 * can be hashes that were not requested but had to be enabled.
5850 extra &= SUPPORTED_RSS_HASHTYPES;
5851 MPASS((extra & hashconfig) == 0);
5855 "global RSS config (0x%x) cannot be accommodated.\n",
5858 if (extra & RSS_HASHTYPE_RSS_IPV4)
5859 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5860 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5861 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5862 if (extra & RSS_HASHTYPE_RSS_IPV6)
5863 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5864 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5865 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5866 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5867 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5868 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5869 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5871 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5872 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5873 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5874 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5876 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5879 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5884 vi->flags |= VI_INIT_DONE;
5896 vi_full_uninit(struct vi_info *vi)
5898 struct port_info *pi = vi->pi;
5899 struct adapter *sc = pi->adapter;
5901 struct sge_rxq *rxq;
5902 struct sge_txq *txq;
5904 struct sge_ofld_rxq *ofld_rxq;
5906 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5907 struct sge_wrq *ofld_txq;
5910 if (vi->flags & VI_INIT_DONE) {
5912 /* Need to quiesce queues. */
5914 /* XXX: Only for the first VI? */
5915 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5916 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5918 for_each_txq(vi, i, txq) {
5919 quiesce_txq(sc, txq);
5922 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
5923 for_each_ofld_txq(vi, i, ofld_txq) {
5924 quiesce_wrq(sc, ofld_txq);
5928 for_each_rxq(vi, i, rxq) {
5929 quiesce_iq(sc, &rxq->iq);
5930 quiesce_fl(sc, &rxq->fl);
5934 for_each_ofld_rxq(vi, i, ofld_rxq) {
5935 quiesce_iq(sc, &ofld_rxq->iq);
5936 quiesce_fl(sc, &ofld_rxq->fl);
5939 free(vi->rss, M_CXGBE);
5940 free(vi->nm_rss, M_CXGBE);
5943 t4_teardown_vi_queues(vi);
5944 vi->flags &= ~VI_INIT_DONE;
5950 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5952 struct sge_eq *eq = &txq->eq;
5953 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5955 (void) sc; /* unused */
5959 MPASS((eq->flags & EQ_ENABLED) == 0);
5963 /* Wait for the mp_ring to empty. */
5964 while (!mp_ring_is_idle(txq->r)) {
5965 mp_ring_check_drainage(txq->r, 0);
5966 pause("rquiesce", 1);
5969 /* Then wait for the hardware to finish. */
5970 while (spg->cidx != htobe16(eq->pidx))
5971 pause("equiesce", 1);
5973 /* Finally, wait for the driver to reclaim all descriptors. */
5974 while (eq->cidx != eq->pidx)
5975 pause("dquiesce", 1);
5979 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5986 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5988 (void) sc; /* unused */
5990 /* Synchronize with the interrupt handler */
5991 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5996 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5998 mtx_lock(&sc->sfl_lock);
6000 fl->flags |= FL_DOOMED;
6002 callout_stop(&sc->sfl_callout);
6003 mtx_unlock(&sc->sfl_lock);
6005 KASSERT((fl->flags & FL_STARVING) == 0,
6006 ("%s: still starving", __func__));
6010 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
6011 driver_intr_t *handler, void *arg, char *name)
6016 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
6017 RF_SHAREABLE | RF_ACTIVE);
6018 if (irq->res == NULL) {
6019 device_printf(sc->dev,
6020 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
6024 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
6025 NULL, handler, arg, &irq->tag);
6027 device_printf(sc->dev,
6028 "failed to setup interrupt for rid %d, name %s: %d\n",
6031 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
6037 t4_free_irq(struct adapter *sc, struct irq *irq)
6040 bus_teardown_intr(sc->dev, irq->res, irq->tag);
6042 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
6044 bzero(irq, sizeof(*irq));
6050 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
6053 regs->version = chip_id(sc) | chip_rev(sc) << 10;
6054 t4_get_regs(sc, buf, regs->len);
6057 #define A_PL_INDIR_CMD 0x1f8
6059 #define S_PL_AUTOINC 31
6060 #define M_PL_AUTOINC 0x1U
6061 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
6062 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
6064 #define S_PL_VFID 20
6065 #define M_PL_VFID 0xffU
6066 #define V_PL_VFID(x) ((x) << S_PL_VFID)
6067 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
6070 #define M_PL_ADDR 0xfffffU
6071 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
6072 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
6074 #define A_PL_INDIR_DATA 0x1fc
6077 read_vf_stat(struct adapter *sc, u_int vin, int reg)
6081 mtx_assert(&sc->reg_lock, MA_OWNED);
6082 if (sc->flags & IS_VF) {
6083 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
6084 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
6086 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
6087 V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));
6088 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
6089 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
6091 return (((uint64_t)stats[1]) << 32 | stats[0]);
6095 t4_get_vi_stats(struct adapter *sc, u_int vin, struct fw_vi_stats_vf *stats)
6098 #define GET_STAT(name) \
6099 read_vf_stat(sc, vin, A_MPS_VF_STAT_##name##_L)
6101 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
6102 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
6103 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
6104 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
6105 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
6106 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
6107 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
6108 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
6109 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
6110 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
6111 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
6112 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
6113 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
6114 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
6115 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
6116 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
6122 t4_clr_vi_stats(struct adapter *sc, u_int vin)
6126 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | V_PL_VFID(vin) |
6127 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
6128 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
6129 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
6130 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
6134 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
6137 const struct timeval interval = {0, 250000}; /* 250ms */
6139 if (!(vi->flags & VI_INIT_DONE))
6143 timevalsub(&tv, &interval);
6144 if (timevalcmp(&tv, &vi->last_refreshed, <))
6147 mtx_lock(&sc->reg_lock);
6148 t4_get_vi_stats(sc, vi->vin, &vi->stats);
6149 getmicrotime(&vi->last_refreshed);
6150 mtx_unlock(&sc->reg_lock);
6154 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
6156 u_int i, v, tnl_cong_drops, chan_map;
6158 const struct timeval interval = {0, 250000}; /* 250ms */
6161 timevalsub(&tv, &interval);
6162 if (timevalcmp(&tv, &pi->last_refreshed, <))
6166 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
6167 chan_map = pi->rx_e_chan_map;
6169 i = ffs(chan_map) - 1;
6170 mtx_lock(&sc->reg_lock);
6171 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
6172 A_TP_MIB_TNL_CNG_DROP_0 + i);
6173 mtx_unlock(&sc->reg_lock);
6174 tnl_cong_drops += v;
6175 chan_map &= ~(1 << i);
6177 pi->tnl_cong_drops = tnl_cong_drops;
6178 getmicrotime(&pi->last_refreshed);
6182 cxgbe_tick(void *arg)
6184 struct port_info *pi = arg;
6185 struct adapter *sc = pi->adapter;
6187 PORT_LOCK_ASSERT_OWNED(pi);
6188 cxgbe_refresh_stats(sc, pi);
6190 callout_schedule(&pi->tick, hz);
6196 struct vi_info *vi = arg;
6197 struct adapter *sc = vi->pi->adapter;
6199 vi_refresh_stats(sc, vi);
6201 callout_schedule(&vi->tick, hz);
6205 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
6207 static char *caps_decoder[] = {
6208 "\20\001IPMI\002NCSI", /* 0: NBM */
6209 "\20\001PPP\002QFC\003DCBX", /* 1: link */
6210 "\20\001INGRESS\002EGRESS", /* 2: switch */
6211 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
6212 "\006HASHFILTER\007ETHOFLD",
6213 "\20\001TOE", /* 4: TOE */
6214 "\20\001RDDP\002RDMAC", /* 5: RDMA */
6215 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
6216 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
6217 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
6219 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
6220 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
6221 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
6222 "\004PO_INITIATOR\005PO_TARGET",
6226 t4_sysctls(struct adapter *sc)
6228 struct sysctl_ctx_list *ctx;
6229 struct sysctl_oid *oid;
6230 struct sysctl_oid_list *children, *c0;
6231 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
6233 ctx = device_get_sysctl_ctx(sc->dev);
6238 oid = device_get_sysctl_tree(sc->dev);
6239 c0 = children = SYSCTL_CHILDREN(oid);
6241 sc->sc_do_rxcopy = 1;
6242 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
6243 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
6245 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
6246 sc->params.nports, "# of ports");
6248 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
6249 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, doorbells,
6250 (uintptr_t)&sc->doorbells, sysctl_bitfield_8b, "A",
6251 "available doorbells");
6253 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
6254 sc->params.vpd.cclk, "core clock frequency (in KHz)");
6256 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
6257 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6258 sc->params.sge.timer_val, sizeof(sc->params.sge.timer_val),
6259 sysctl_int_array, "A", "interrupt holdoff timer values (us)");
6261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
6262 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6263 sc->params.sge.counter_val, sizeof(sc->params.sge.counter_val),
6264 sysctl_int_array, "A", "interrupt holdoff packet counter values");
6266 t4_sge_sysctls(sc, ctx, children);
6268 sc->lro_timeout = 100;
6269 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
6270 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
6272 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
6273 &sc->debug_flags, 0, "flags to enable runtime debugging");
6275 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
6276 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
6278 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
6279 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
6281 if (sc->flags & IS_VF)
6284 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
6285 NULL, chip_rev(sc), "chip hardware revision");
6287 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
6288 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
6290 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
6291 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
6293 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
6294 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
6296 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
6297 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
6299 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
6300 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
6302 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
6303 sc->er_version, 0, "expansion ROM version");
6305 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
6306 sc->bs_version, 0, "bootstrap firmware version");
6308 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
6309 NULL, sc->params.scfg_vers, "serial config version");
6311 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
6312 NULL, sc->params.vpd_vers, "VPD version");
6314 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
6315 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
6317 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
6318 sc->cfcsum, "config file checksum");
6320 #define SYSCTL_CAP(name, n, text) \
6321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
6322 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, caps_decoder[n], \
6323 (uintptr_t)&sc->name, sysctl_bitfield_16b, "A", \
6324 "available " text " capabilities")
6326 SYSCTL_CAP(nbmcaps, 0, "NBM");
6327 SYSCTL_CAP(linkcaps, 1, "link");
6328 SYSCTL_CAP(switchcaps, 2, "switch");
6329 SYSCTL_CAP(niccaps, 3, "NIC");
6330 SYSCTL_CAP(toecaps, 4, "TCP offload");
6331 SYSCTL_CAP(rdmacaps, 5, "RDMA");
6332 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
6333 SYSCTL_CAP(cryptocaps, 7, "crypto");
6334 SYSCTL_CAP(fcoecaps, 8, "FCoE");
6337 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
6338 NULL, sc->tids.nftids, "number of filters");
6340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6341 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6342 sysctl_temperature, "I", "chip temperature (in Celsius)");
6343 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reset_sensor",
6344 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6345 sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
6347 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg",
6348 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6349 sysctl_loadavg, "A",
6350 "microprocessor load averages (debug firmwares only)");
6352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
6353 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, sysctl_vdd,
6354 "I", "core Vdd (in mV)");
6356 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
6357 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, LOCAL_CPUS,
6358 sysctl_cpus, "A", "local CPUs");
6360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
6361 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, INTR_CPUS,
6362 sysctl_cpus, "A", "preferred CPUs for interrupts");
6364 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "swintr", CTLFLAG_RW,
6365 &sc->swintr, 0, "software triggered interrupts");
6368 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
6370 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
6371 CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_MPSAFE, NULL,
6372 "logs and miscellaneous information");
6373 children = SYSCTL_CHILDREN(oid);
6375 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
6376 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6377 sysctl_cctrl, "A", "congestion control");
6379 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
6380 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6381 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
6383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
6384 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 1,
6385 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
6387 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
6388 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 2,
6389 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
6391 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
6392 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3,
6393 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
6395 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
6396 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4,
6397 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
6399 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
6400 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 5,
6401 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
6403 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
6404 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6405 sysctl_cim_la, "A", "CIM logic analyzer");
6407 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
6408 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6409 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
6411 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
6412 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6413 0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
6415 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
6416 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6417 1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
6419 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
6420 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6421 2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
6423 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
6424 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6425 3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
6427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
6428 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6429 4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
6431 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
6432 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6433 5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
6435 if (chip_id(sc) > CHELSIO_T4) {
6436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
6437 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6438 6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
6439 "CIM OBQ 6 (SGE0-RX)");
6441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
6442 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6443 7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
6444 "CIM OBQ 7 (SGE1-RX)");
6447 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
6448 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6449 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
6451 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
6452 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6453 sysctl_cim_qcfg, "A", "CIM queue configuration");
6455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
6456 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6457 sysctl_cpl_stats, "A", "CPL statistics");
6459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
6460 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6461 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
6463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
6464 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6465 sysctl_devlog, "A", "firmware's device log");
6467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
6468 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6469 sysctl_fcoe_stats, "A", "FCoE statistics");
6471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
6472 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6473 sysctl_hw_sched, "A", "hardware scheduler ");
6475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
6476 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6477 sysctl_l2t, "A", "hardware L2 table");
6479 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
6480 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6481 sysctl_smt, "A", "hardware source MAC table");
6484 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "clip",
6485 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6486 sysctl_clip, "A", "active CLIP table entries");
6489 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
6490 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6491 sysctl_lb_stats, "A", "loopback statistics");
6493 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
6494 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6495 sysctl_meminfo, "A", "memory regions");
6497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
6498 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6499 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
6500 "A", "MPS TCAM entries");
6502 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
6503 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6504 sysctl_path_mtus, "A", "path MTUs");
6506 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
6507 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6508 sysctl_pm_stats, "A", "PM statistics");
6510 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
6511 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6512 sysctl_rdma_stats, "A", "RDMA statistics");
6514 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
6515 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6516 sysctl_tcp_stats, "A", "TCP statistics");
6518 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
6519 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6520 sysctl_tids, "A", "TID information");
6522 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
6523 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6524 sysctl_tp_err_stats, "A", "TP error statistics");
6526 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
6527 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6528 sysctl_tp_la_mask, "I", "TP logic analyzer event capture mask");
6530 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
6531 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6532 sysctl_tp_la, "A", "TP logic analyzer");
6534 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
6535 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6536 sysctl_tx_rate, "A", "Tx rate");
6538 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
6539 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6540 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
6542 if (chip_id(sc) >= CHELSIO_T5) {
6543 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
6544 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6545 sysctl_wcwr_stats, "A", "write combined work requests");
6549 if (sc->flags & KERN_TLS_OK) {
6553 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "tls",
6554 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "KERN_TLS parameters");
6555 children = SYSCTL_CHILDREN(oid);
6557 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "inline_keys",
6558 CTLFLAG_RW, &sc->tlst.inline_keys, 0, "Always pass TLS "
6559 "keys in work requests (1) or attempt to store TLS keys "
6561 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "combo_wrs",
6562 CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to combine "
6563 "TCB field updates with TLS record work requests.");
6568 if (is_offload(sc)) {
6575 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe",
6576 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE parameters");
6577 children = SYSCTL_CHILDREN(oid);
6579 sc->tt.cong_algorithm = -1;
6580 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
6581 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
6582 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
6586 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
6587 &sc->tt.sndbuf, 0, "hardware send buffer");
6590 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp",
6591 CTLFLAG_RW | CTLFLAG_SKIP, &sc->tt.ddp, 0, "");
6592 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_zcopy", CTLFLAG_RW,
6593 &sc->tt.ddp, 0, "Enable zero-copy aio_read(2)");
6595 sc->tt.rx_coalesce = -1;
6596 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
6597 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
6600 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
6601 &sc->tt.tls, 0, "Inline TLS allowed");
6603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
6604 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6605 sysctl_tls_rx_ports, "I",
6606 "TCP ports that use inline TLS+TOE RX");
6608 sc->tt.tx_align = -1;
6609 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6610 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6612 sc->tt.tx_zcopy = 0;
6613 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6614 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6615 "Enable zero-copy aio_write(2)");
6617 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6618 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6619 "cop_managed_offloading", CTLFLAG_RW,
6620 &sc->tt.cop_managed_offloading, 0,
6621 "COP (Connection Offload Policy) controls all TOE offload");
6623 sc->tt.autorcvbuf_inc = 16 * 1024;
6624 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "autorcvbuf_inc",
6625 CTLFLAG_RW, &sc->tt.autorcvbuf_inc, 0,
6626 "autorcvbuf increment");
6628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6629 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6630 sysctl_tp_tick, "A", "TP timer tick (us)");
6632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6633 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 1,
6634 sysctl_tp_tick, "A", "TCP timestamp tick (us)");
6636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6637 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 2,
6638 sysctl_tp_tick, "A", "DACK tick (us)");
6640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6641 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
6642 sysctl_tp_dack_timer, "IU", "DACK timer (us)");
6644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6645 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6646 A_TP_RXT_MIN, sysctl_tp_timer, "LU",
6647 "Minimum retransmit interval (us)");
6649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6650 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6651 A_TP_RXT_MAX, sysctl_tp_timer, "LU",
6652 "Maximum retransmit interval (us)");
6654 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6655 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6656 A_TP_PERS_MIN, sysctl_tp_timer, "LU",
6657 "Persist timer min (us)");
6659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6660 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6661 A_TP_PERS_MAX, sysctl_tp_timer, "LU",
6662 "Persist timer max (us)");
6664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6665 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6666 A_TP_KEEP_IDLE, sysctl_tp_timer, "LU",
6667 "Keepalive idle timer (us)");
6669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6670 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6671 A_TP_KEEP_INTVL, sysctl_tp_timer, "LU",
6672 "Keepalive interval timer (us)");
6674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6675 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6676 A_TP_INIT_SRTT, sysctl_tp_timer, "LU", "Initial SRTT (us)");
6678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6679 CTLTYPE_ULONG | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6680 A_TP_FINWAIT2_TIMER, sysctl_tp_timer, "LU",
6681 "FINWAIT2 timer (us)");
6683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6684 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6685 S_SYNSHIFTMAX, sysctl_tp_shift_cnt, "IU",
6686 "Number of SYN retransmissions before abort");
6688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6689 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6690 S_RXTSHIFTMAXR2, sysctl_tp_shift_cnt, "IU",
6691 "Number of retransmissions before abort");
6693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6694 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6695 S_KEEPALIVEMAXR2, sysctl_tp_shift_cnt, "IU",
6696 "Number of keepalive probes before abort");
6698 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6699 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
6700 "TOE retransmit backoffs");
6701 children = SYSCTL_CHILDREN(oid);
6702 for (i = 0; i < 16; i++) {
6703 snprintf(s, sizeof(s), "%u", i);
6704 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6705 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6706 i, sysctl_tp_backoff, "IU",
6707 "TOE retransmit backoff");
6714 vi_sysctls(struct vi_info *vi)
6716 struct sysctl_ctx_list *ctx;
6717 struct sysctl_oid *oid;
6718 struct sysctl_oid_list *children;
6720 ctx = device_get_sysctl_ctx(vi->dev);
6723 * dev.v?(cxgbe|cxl).X.
6725 oid = device_get_sysctl_tree(vi->dev);
6726 children = SYSCTL_CHILDREN(oid);
6728 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6729 vi->viid, "VI identifer");
6730 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6731 &vi->nrxq, 0, "# of rx queues");
6732 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6733 &vi->ntxq, 0, "# of tx queues");
6734 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6735 &vi->first_rxq, 0, "index of first rx queue");
6736 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6737 &vi->first_txq, 0, "index of first tx queue");
6738 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6739 vi->rss_base, "start of RSS indirection table");
6740 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6741 vi->rss_size, "size of RSS indirection table");
6743 if (IS_MAIN_VI(vi)) {
6744 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6745 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6746 sysctl_noflowq, "IU",
6747 "Reserve queue 0 for non-flowid packets");
6751 if (vi->nofldrxq != 0) {
6752 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6754 "# of rx queues for offloaded TCP connections");
6755 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6756 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6757 "index of first TOE rx queue");
6758 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6759 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6760 sysctl_holdoff_tmr_idx_ofld, "I",
6761 "holdoff timer index for TOE queues");
6762 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6763 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6764 sysctl_holdoff_pktc_idx_ofld, "I",
6765 "holdoff packet counter index for TOE queues");
6768 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
6769 if (vi->nofldtxq != 0) {
6770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6772 "# of tx queues for TOE/ETHOFLD");
6773 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6774 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6775 "index of first TOE/ETHOFLD tx queue");
6779 if (vi->nnmrxq != 0) {
6780 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6781 &vi->nnmrxq, 0, "# of netmap rx queues");
6782 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6783 &vi->nnmtxq, 0, "# of netmap tx queues");
6784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6785 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6786 "index of first netmap rx queue");
6787 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6788 CTLFLAG_RD, &vi->first_nm_txq, 0,
6789 "index of first netmap tx queue");
6793 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6794 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6795 sysctl_holdoff_tmr_idx, "I", "holdoff timer index");
6796 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6797 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6798 sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index");
6800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6801 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6802 sysctl_qsize_rxq, "I", "rx queue size");
6803 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6804 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, 0,
6805 sysctl_qsize_txq, "I", "tx queue size");
6809 cxgbe_sysctls(struct port_info *pi)
6811 struct sysctl_ctx_list *ctx;
6812 struct sysctl_oid *oid;
6813 struct sysctl_oid_list *children, *children2;
6814 struct adapter *sc = pi->adapter;
6817 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6819 ctx = device_get_sysctl_ctx(pi->dev);
6824 oid = device_get_sysctl_tree(pi->dev);
6825 children = SYSCTL_CHILDREN(oid);
6827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc",
6828 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 0,
6829 sysctl_linkdnrc, "A", "reason why link is down");
6830 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6831 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6832 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 0,
6833 sysctl_btphy, "I", "PHY temperature (in Celsius)");
6834 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6835 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, pi, 1,
6836 sysctl_btphy, "I", "PHY firmware version");
6839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6840 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0,
6841 sysctl_pause_settings, "A",
6842 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)");
6843 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6844 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0,
6846 "FECs to use (bit 0 = RS, 1 = FC, 2 = none, 5 = auto, 6 = module)");
6847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "module_fec",
6848 CTLTYPE_STRING | CTLFLAG_NEEDGIANT, pi, 0, sysctl_module_fec, "A",
6849 "FEC recommended by the cable/transceiver");
6850 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6851 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, pi, 0,
6852 sysctl_autoneg, "I",
6853 "autonegotiation (-1 = not supported)");
6855 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcaps", CTLFLAG_RD,
6856 &pi->link_cfg.pcaps, 0, "port capabilities");
6857 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "acaps", CTLFLAG_RD,
6858 &pi->link_cfg.acaps, 0, "advertised capabilities");
6859 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpacaps", CTLFLAG_RD,
6860 &pi->link_cfg.lpacaps, 0, "link partner advertised capabilities");
6862 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6863 port_top_speed(pi), "max speed (in Gbps)");
6864 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6865 pi->mps_bg_map, "MPS buffer group map");
6866 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6867 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6869 if (sc->flags & IS_VF)
6873 * dev.(cxgbe|cxl).X.tc.
6875 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc",
6876 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
6877 "Tx scheduler traffic classes (cl_rl)");
6878 children2 = SYSCTL_CHILDREN(oid);
6879 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6880 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6881 "pktsize for per-flow cl-rl (0 means up to the driver )");
6882 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6883 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6884 "burstsize for per-flow cl-rl (0 means up to the driver)");
6885 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6886 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6888 snprintf(name, sizeof(name), "%d", i);
6889 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6890 SYSCTL_CHILDREN(oid), OID_AUTO, name,
6891 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "traffic class"));
6892 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6893 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, tc_flags,
6894 (uintptr_t)&tc->flags, sysctl_bitfield_8b, "A", "flags");
6895 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6896 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6897 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6898 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
6899 (pi->port_id << 16) | i, sysctl_tc_params, "A",
6900 "traffic class parameters");
6904 * dev.cxgbe.X.stats.
6906 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
6907 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "port statistics");
6908 children = SYSCTL_CHILDREN(oid);
6909 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6910 &pi->tx_parse_error, 0,
6911 "# of tx packets with invalid length or # of segments");
6913 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6914 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6915 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, reg, \
6916 sysctl_handle_t4_reg64, "QU", desc)
6918 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6919 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6920 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6921 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6922 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6923 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6924 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6925 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6926 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6927 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6928 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6929 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6930 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6931 "# of tx frames in this range",
6932 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6933 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6934 "# of tx frames in this range",
6935 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6936 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6937 "# of tx frames in this range",
6938 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6939 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6940 "# of tx frames in this range",
6941 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6942 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6943 "# of tx frames in this range",
6944 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6945 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6946 "# of tx frames in this range",
6947 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6948 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6949 "# of tx frames in this range",
6950 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6951 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6952 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6953 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6954 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6955 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6956 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6957 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6958 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6959 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6960 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6961 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6962 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6963 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6964 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6965 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6966 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6967 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6968 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6969 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6970 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6972 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6973 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6974 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6975 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6976 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6977 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6978 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6979 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6980 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6981 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6982 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6983 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6984 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6985 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6986 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6987 "# of frames received with bad FCS",
6988 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6989 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6990 "# of frames received with length error",
6991 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6992 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6993 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6994 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6995 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6996 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6997 "# of rx frames in this range",
6998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6999 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
7000 "# of rx frames in this range",
7001 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
7002 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
7003 "# of rx frames in this range",
7004 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
7005 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
7006 "# of rx frames in this range",
7007 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
7008 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
7009 "# of rx frames in this range",
7010 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
7011 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
7012 "# of rx frames in this range",
7013 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
7014 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
7015 "# of rx frames in this range",
7016 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
7017 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
7018 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
7019 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
7020 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
7021 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
7022 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
7023 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
7024 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
7025 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
7026 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
7027 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
7028 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
7029 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
7030 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
7031 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
7032 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
7033 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
7034 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
7036 #undef SYSCTL_ADD_T4_REG64
7038 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
7039 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
7040 &pi->stats.name, desc)
7042 /* We get these from port_stats and they may be stale by up to 1s */
7043 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
7044 "# drops due to buffer-group 0 overflows");
7045 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
7046 "# drops due to buffer-group 1 overflows");
7047 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
7048 "# drops due to buffer-group 2 overflows");
7049 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
7050 "# drops due to buffer-group 3 overflows");
7051 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
7052 "# of buffer-group 0 truncated packets");
7053 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
7054 "# of buffer-group 1 truncated packets");
7055 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
7056 "# of buffer-group 2 truncated packets");
7057 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
7058 "# of buffer-group 3 truncated packets");
7060 #undef SYSCTL_ADD_T4_PORTSTAT
7062 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_records",
7063 CTLFLAG_RD, &pi->tx_toe_tls_records,
7064 "# of TOE TLS records transmitted");
7065 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_toe_tls_octets",
7066 CTLFLAG_RD, &pi->tx_toe_tls_octets,
7067 "# of payload octets in transmitted TOE TLS records");
7068 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_records",
7069 CTLFLAG_RD, &pi->rx_toe_tls_records,
7070 "# of TOE TLS records received");
7071 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_toe_tls_octets",
7072 CTLFLAG_RD, &pi->rx_toe_tls_octets,
7073 "# of payload octets in received TOE TLS records");
7077 sysctl_int_array(SYSCTL_HANDLER_ARGS)
7079 int rc, *i, space = 0;
7082 sbuf_new_for_sysctl(&sb, NULL, 64, req);
7083 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
7085 sbuf_printf(&sb, " ");
7086 sbuf_printf(&sb, "%d", *i);
7089 rc = sbuf_finish(&sb);
7095 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
7100 rc = sysctl_wire_old_buffer(req, 0);
7104 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7108 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
7109 rc = sbuf_finish(sb);
7116 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
7121 rc = sysctl_wire_old_buffer(req, 0);
7125 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7129 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
7130 rc = sbuf_finish(sb);
7137 sysctl_btphy(SYSCTL_HANDLER_ARGS)
7139 struct port_info *pi = arg1;
7141 struct adapter *sc = pi->adapter;
7145 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
7148 /* XXX: magic numbers */
7149 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
7151 end_synchronized_op(sc, 0);
7157 rc = sysctl_handle_int(oidp, &v, 0, req);
7162 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
7164 struct vi_info *vi = arg1;
7167 val = vi->rsrv_noflowq;
7168 rc = sysctl_handle_int(oidp, &val, 0, req);
7169 if (rc != 0 || req->newptr == NULL)
7172 if ((val >= 1) && (vi->ntxq > 1))
7173 vi->rsrv_noflowq = 1;
7175 vi->rsrv_noflowq = 0;
7181 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
7183 struct vi_info *vi = arg1;
7184 struct adapter *sc = vi->pi->adapter;
7186 struct sge_rxq *rxq;
7191 rc = sysctl_handle_int(oidp, &idx, 0, req);
7192 if (rc != 0 || req->newptr == NULL)
7195 if (idx < 0 || idx >= SGE_NTIMERS)
7198 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7203 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
7204 for_each_rxq(vi, i, rxq) {
7205 #ifdef atomic_store_rel_8
7206 atomic_store_rel_8(&rxq->iq.intr_params, v);
7208 rxq->iq.intr_params = v;
7213 end_synchronized_op(sc, LOCK_HELD);
7218 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
7220 struct vi_info *vi = arg1;
7221 struct adapter *sc = vi->pi->adapter;
7226 rc = sysctl_handle_int(oidp, &idx, 0, req);
7227 if (rc != 0 || req->newptr == NULL)
7230 if (idx < -1 || idx >= SGE_NCOUNTERS)
7233 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7238 if (vi->flags & VI_INIT_DONE)
7239 rc = EBUSY; /* cannot be changed once the queues are created */
7243 end_synchronized_op(sc, LOCK_HELD);
7248 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
7250 struct vi_info *vi = arg1;
7251 struct adapter *sc = vi->pi->adapter;
7254 qsize = vi->qsize_rxq;
7256 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7257 if (rc != 0 || req->newptr == NULL)
7260 if (qsize < 128 || (qsize & 7))
7263 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7268 if (vi->flags & VI_INIT_DONE)
7269 rc = EBUSY; /* cannot be changed once the queues are created */
7271 vi->qsize_rxq = qsize;
7273 end_synchronized_op(sc, LOCK_HELD);
7278 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
7280 struct vi_info *vi = arg1;
7281 struct adapter *sc = vi->pi->adapter;
7284 qsize = vi->qsize_txq;
7286 rc = sysctl_handle_int(oidp, &qsize, 0, req);
7287 if (rc != 0 || req->newptr == NULL)
7290 if (qsize < 128 || qsize > 65536)
7293 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
7298 if (vi->flags & VI_INIT_DONE)
7299 rc = EBUSY; /* cannot be changed once the queues are created */
7301 vi->qsize_txq = qsize;
7303 end_synchronized_op(sc, LOCK_HELD);
7308 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
7310 struct port_info *pi = arg1;
7311 struct adapter *sc = pi->adapter;
7312 struct link_config *lc = &pi->link_cfg;
7315 if (req->newptr == NULL) {
7317 static char *bits = "\20\1RX\2TX\3AUTO";
7319 rc = sysctl_wire_old_buffer(req, 0);
7323 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7328 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
7329 (lc->requested_fc & PAUSE_AUTONEG), bits);
7331 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
7332 PAUSE_RX | PAUSE_AUTONEG), bits);
7334 rc = sbuf_finish(sb);
7340 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
7344 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7350 if (s[0] < '0' || s[0] > '9')
7351 return (EINVAL); /* not a number */
7353 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
7354 return (EINVAL); /* some other bit is set too */
7356 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7361 lc->requested_fc = n;
7362 fixup_link_config(pi);
7364 rc = apply_link_config(pi);
7365 set_current_media(pi);
7367 end_synchronized_op(sc, 0);
7374 sysctl_fec(SYSCTL_HANDLER_ARGS)
7376 struct port_info *pi = arg1;
7377 struct adapter *sc = pi->adapter;
7378 struct link_config *lc = &pi->link_cfg;
7382 if (req->newptr == NULL) {
7384 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2"
7385 "\5RSVD3\6auto\7module";
7387 rc = sysctl_wire_old_buffer(req, 0);
7391 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7396 * Display the requested_fec when the link is down -- the actual
7397 * FEC makes sense only when the link is up.
7400 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
7401 (lc->requested_fec & (FEC_AUTO | FEC_MODULE)),
7404 sbuf_printf(sb, "%b", lc->requested_fec, bits);
7406 rc = sbuf_finish(sb);
7412 snprintf(s, sizeof(s), "%d",
7413 lc->requested_fec == FEC_AUTO ? -1 :
7414 lc->requested_fec & (M_FW_PORT_CAP32_FEC | FEC_MODULE));
7416 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
7420 n = strtol(&s[0], NULL, 0);
7421 if (n < 0 || n & FEC_AUTO)
7423 else if (n & ~(M_FW_PORT_CAP32_FEC | FEC_MODULE))
7424 return (EINVAL);/* some other bit is set too */
7426 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7431 old = lc->requested_fec;
7433 lc->requested_fec = FEC_AUTO;
7434 else if (n == 0 || n == FEC_NONE)
7435 lc->requested_fec = FEC_NONE;
7438 V_FW_PORT_CAP32_FEC(n & M_FW_PORT_CAP32_FEC)) !=
7443 lc->requested_fec = n & (M_FW_PORT_CAP32_FEC |
7446 fixup_link_config(pi);
7447 if (pi->up_vis > 0) {
7448 rc = apply_link_config(pi);
7450 lc->requested_fec = old;
7451 if (rc == FW_EPROTO)
7457 end_synchronized_op(sc, 0);
7464 sysctl_module_fec(SYSCTL_HANDLER_ARGS)
7466 struct port_info *pi = arg1;
7467 struct adapter *sc = pi->adapter;
7468 struct link_config *lc = &pi->link_cfg;
7472 static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3";
7474 rc = sysctl_wire_old_buffer(req, 0);
7478 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
7482 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mfec") != 0)
7485 if (pi->up_vis == 0) {
7487 * If all the interfaces are administratively down the firmware
7488 * does not report transceiver changes. Refresh port info here.
7489 * This is the only reason we have a synchronized op in this
7490 * function. Just PORT_LOCK would have been enough otherwise.
7492 t4_update_port_info(pi);
7496 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE ||
7497 !fec_supported(lc->pcaps)) {
7498 sbuf_printf(sb, "n/a");
7502 sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits);
7504 rc = sbuf_finish(sb);
7508 end_synchronized_op(sc, 0);
7514 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
7516 struct port_info *pi = arg1;
7517 struct adapter *sc = pi->adapter;
7518 struct link_config *lc = &pi->link_cfg;
7521 if (lc->pcaps & FW_PORT_CAP32_ANEG)
7522 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
7525 rc = sysctl_handle_int(oidp, &val, 0, req);
7526 if (rc != 0 || req->newptr == NULL)
7529 val = AUTONEG_DISABLE;
7531 val = AUTONEG_ENABLE;
7535 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
7540 if (val == AUTONEG_ENABLE && !(lc->pcaps & FW_PORT_CAP32_ANEG)) {
7544 lc->requested_aneg = val;
7545 fixup_link_config(pi);
7547 rc = apply_link_config(pi);
7548 set_current_media(pi);
7551 end_synchronized_op(sc, 0);
7556 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
7558 struct adapter *sc = arg1;
7562 val = t4_read_reg64(sc, reg);
7564 return (sysctl_handle_64(oidp, &val, 0, req));
7568 sysctl_temperature(SYSCTL_HANDLER_ARGS)
7570 struct adapter *sc = arg1;
7572 uint32_t param, val;
7574 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
7577 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7578 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7579 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
7580 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7581 end_synchronized_op(sc, 0);
7585 /* unknown is returned as 0 but we display -1 in that case */
7586 t = val == 0 ? -1 : val;
7588 rc = sysctl_handle_int(oidp, &t, 0, req);
7593 sysctl_vdd(SYSCTL_HANDLER_ARGS)
7595 struct adapter *sc = arg1;
7597 uint32_t param, val;
7599 if (sc->params.core_vdd == 0) {
7600 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7604 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7605 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7606 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
7607 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7608 end_synchronized_op(sc, 0);
7611 sc->params.core_vdd = val;
7614 return (sysctl_handle_int(oidp, &sc->params.core_vdd, 0, req));
7618 sysctl_reset_sensor(SYSCTL_HANDLER_ARGS)
7620 struct adapter *sc = arg1;
7622 uint32_t param, val;
7624 v = sc->sensor_resets;
7625 rc = sysctl_handle_int(oidp, &v, 0, req);
7626 if (rc != 0 || req->newptr == NULL || v <= 0)
7629 if (sc->params.fw_vers < FW_VERSION32(1, 24, 7, 0) ||
7630 chip_id(sc) < CHELSIO_T5)
7633 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4srst");
7636 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7637 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
7638 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR));
7640 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7641 end_synchronized_op(sc, 0);
7643 sc->sensor_resets++;
7648 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
7650 struct adapter *sc = arg1;
7653 uint32_t param, val;
7655 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
7658 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7659 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
7660 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
7661 end_synchronized_op(sc, 0);
7665 rc = sysctl_wire_old_buffer(req, 0);
7669 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7673 if (val == 0xffffffff) {
7674 /* Only debug and custom firmwares report load averages. */
7675 sbuf_printf(sb, "not available");
7677 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
7678 (val >> 16) & 0xff);
7680 rc = sbuf_finish(sb);
7687 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
7689 struct adapter *sc = arg1;
7692 uint16_t incr[NMTUS][NCCTRL_WIN];
7693 static const char *dec_fac[] = {
7694 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
7698 rc = sysctl_wire_old_buffer(req, 0);
7702 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7706 t4_read_cong_tbl(sc, incr);
7708 for (i = 0; i < NCCTRL_WIN; ++i) {
7709 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
7710 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
7711 incr[5][i], incr[6][i], incr[7][i]);
7712 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
7713 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
7714 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
7715 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
7718 rc = sbuf_finish(sb);
7724 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
7725 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
7726 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
7727 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
7731 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
7733 struct adapter *sc = arg1;
7735 int rc, i, n, qid = arg2;
7738 u_int cim_num_obq = sc->chip_params->cim_num_obq;
7740 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
7741 ("%s: bad qid %d\n", __func__, qid));
7743 if (qid < CIM_NUM_IBQ) {
7746 n = 4 * CIM_IBQ_SIZE;
7747 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7748 rc = t4_read_cim_ibq(sc, qid, buf, n);
7750 /* outbound queue */
7753 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7754 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7755 rc = t4_read_cim_obq(sc, qid, buf, n);
7762 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7764 rc = sysctl_wire_old_buffer(req, 0);
7768 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7774 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7775 for (i = 0, p = buf; i < n; i += 16, p += 4)
7776 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7779 rc = sbuf_finish(sb);
7787 sbuf_cim_la4(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7791 sbuf_printf(sb, "Status Data PC%s",
7792 cfg & F_UPDBGLACAPTPCONLY ? "" :
7793 " LS0Stat LS0Addr LS0Data");
7795 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7796 if (cfg & F_UPDBGLACAPTPCONLY) {
7797 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7799 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7800 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7801 p[4] & 0xff, p[5] >> 8);
7802 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7803 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7804 p[1] & 0xf, p[2] >> 4);
7807 "\n %02x %x%07x %x%07x %08x %08x "
7809 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7810 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7817 sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
7821 sbuf_printf(sb, "Status Inst Data PC%s",
7822 cfg & F_UPDBGLACAPTPCONLY ? "" :
7823 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7825 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7826 if (cfg & F_UPDBGLACAPTPCONLY) {
7827 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7828 p[3] & 0xff, p[2], p[1], p[0]);
7829 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7830 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7831 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7832 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7833 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7834 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7837 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7838 "%08x %08x %08x %08x %08x %08x",
7839 (p[9] >> 16) & 0xff,
7840 p[9] & 0xffff, p[8] >> 16,
7841 p[8] & 0xffff, p[7] >> 16,
7842 p[7] & 0xffff, p[6] >> 16,
7843 p[2], p[1], p[0], p[5], p[4], p[3]);
7849 sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
7854 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7858 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
7859 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7864 rc = -t4_cim_read_la(sc, buf, NULL);
7867 if (chip_id(sc) < CHELSIO_T6)
7868 sbuf_cim_la4(sc, sb, buf, cfg);
7870 sbuf_cim_la6(sc, sb, buf, cfg);
7878 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7880 struct adapter *sc = arg1;
7884 rc = sysctl_wire_old_buffer(req, 0);
7887 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7891 rc = sbuf_cim_la(sc, sb, M_WAITOK);
7893 rc = sbuf_finish(sb);
7899 t4_os_dump_cimla(struct adapter *sc, int arg, bool verbose)
7904 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
7906 rc = sbuf_cim_la(sc, &sb, M_NOWAIT);
7908 rc = sbuf_finish(&sb);
7910 log(LOG_DEBUG, "%s: CIM LA dump follows.\n%s",
7911 device_get_nameunit(sc->dev), sbuf_data(&sb));
7919 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7921 struct adapter *sc = arg1;
7927 rc = sysctl_wire_old_buffer(req, 0);
7931 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7935 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7938 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7941 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7942 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7946 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7947 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7948 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7949 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7950 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7951 (p[1] >> 2) | ((p[2] & 3) << 30),
7952 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7956 rc = sbuf_finish(sb);
7963 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7965 struct adapter *sc = arg1;
7971 rc = sysctl_wire_old_buffer(req, 0);
7975 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7979 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7982 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7985 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7986 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7987 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7988 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7989 p[4], p[3], p[2], p[1], p[0]);
7992 sbuf_printf(sb, "\n\nCntl ID Data");
7993 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7994 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7995 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7998 rc = sbuf_finish(sb);
8005 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
8007 struct adapter *sc = arg1;
8010 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
8011 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
8012 uint16_t thres[CIM_NUM_IBQ];
8013 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
8014 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
8015 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
8017 cim_num_obq = sc->chip_params->cim_num_obq;
8019 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
8020 obq_rdaddr = A_UP_OBQ_0_REALADDR;
8022 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
8023 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
8025 nq = CIM_NUM_IBQ + cim_num_obq;
8027 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
8029 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
8033 t4_read_cimq_cfg(sc, base, size, thres);
8035 rc = sysctl_wire_old_buffer(req, 0);
8039 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
8044 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
8046 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
8047 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
8048 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
8049 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
8050 G_QUEREMFLITS(p[2]) * 16);
8051 for ( ; i < nq; i++, p += 4, wr += 2)
8052 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
8053 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
8054 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
8055 G_QUEREMFLITS(p[2]) * 16);
8057 rc = sbuf_finish(sb);
8064 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
8066 struct adapter *sc = arg1;
8069 struct tp_cpl_stats stats;
8071 rc = sysctl_wire_old_buffer(req, 0);
8075 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8079 mtx_lock(&sc->reg_lock);
8080 t4_tp_get_cpl_stats(sc, &stats, 0);
8081 mtx_unlock(&sc->reg_lock);
8083 if (sc->chip_params->nchan > 2) {
8084 sbuf_printf(sb, " channel 0 channel 1"
8085 " channel 2 channel 3");
8086 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
8087 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
8088 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
8089 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
8091 sbuf_printf(sb, " channel 0 channel 1");
8092 sbuf_printf(sb, "\nCPL requests: %10u %10u",
8093 stats.req[0], stats.req[1]);
8094 sbuf_printf(sb, "\nCPL responses: %10u %10u",
8095 stats.rsp[0], stats.rsp[1]);
8098 rc = sbuf_finish(sb);
8105 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
8107 struct adapter *sc = arg1;
8110 struct tp_usm_stats stats;
8112 rc = sysctl_wire_old_buffer(req, 0);
8116 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8120 t4_get_usm_stats(sc, &stats, 1);
8122 sbuf_printf(sb, "Frames: %u\n", stats.frames);
8123 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
8124 sbuf_printf(sb, "Drops: %u", stats.drops);
8126 rc = sbuf_finish(sb);
8132 static const char * const devlog_level_strings[] = {
8133 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
8134 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
8135 [FW_DEVLOG_LEVEL_ERR] = "ERR",
8136 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
8137 [FW_DEVLOG_LEVEL_INFO] = "INFO",
8138 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
8141 static const char * const devlog_facility_strings[] = {
8142 [FW_DEVLOG_FACILITY_CORE] = "CORE",
8143 [FW_DEVLOG_FACILITY_CF] = "CF",
8144 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
8145 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
8146 [FW_DEVLOG_FACILITY_RES] = "RES",
8147 [FW_DEVLOG_FACILITY_HW] = "HW",
8148 [FW_DEVLOG_FACILITY_FLR] = "FLR",
8149 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
8150 [FW_DEVLOG_FACILITY_PHY] = "PHY",
8151 [FW_DEVLOG_FACILITY_MAC] = "MAC",
8152 [FW_DEVLOG_FACILITY_PORT] = "PORT",
8153 [FW_DEVLOG_FACILITY_VI] = "VI",
8154 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
8155 [FW_DEVLOG_FACILITY_ACL] = "ACL",
8156 [FW_DEVLOG_FACILITY_TM] = "TM",
8157 [FW_DEVLOG_FACILITY_QFC] = "QFC",
8158 [FW_DEVLOG_FACILITY_DCB] = "DCB",
8159 [FW_DEVLOG_FACILITY_ETH] = "ETH",
8160 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
8161 [FW_DEVLOG_FACILITY_RI] = "RI",
8162 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
8163 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
8164 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
8165 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
8166 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
8170 sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
8172 int i, j, rc, nentries, first = 0;
8173 struct devlog_params *dparams = &sc->params.devlog;
8174 struct fw_devlog_e *buf, *e;
8175 uint64_t ftstamp = UINT64_MAX;
8177 if (dparams->addr == 0)
8180 MPASS(flags == M_WAITOK || flags == M_NOWAIT);
8181 buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
8185 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
8189 nentries = dparams->size / sizeof(struct fw_devlog_e);
8190 for (i = 0; i < nentries; i++) {
8193 if (e->timestamp == 0)
8196 e->timestamp = be64toh(e->timestamp);
8197 e->seqno = be32toh(e->seqno);
8198 for (j = 0; j < 8; j++)
8199 e->params[j] = be32toh(e->params[j]);
8201 if (e->timestamp < ftstamp) {
8202 ftstamp = e->timestamp;
8207 if (buf[first].timestamp == 0)
8208 goto done; /* nothing in the log */
8210 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
8211 "Seq#", "Tstamp", "Level", "Facility", "Message");
8216 if (e->timestamp == 0)
8219 sbuf_printf(sb, "%10d %15ju %8s %8s ",
8220 e->seqno, e->timestamp,
8221 (e->level < nitems(devlog_level_strings) ?
8222 devlog_level_strings[e->level] : "UNKNOWN"),
8223 (e->facility < nitems(devlog_facility_strings) ?
8224 devlog_facility_strings[e->facility] : "UNKNOWN"));
8225 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
8226 e->params[2], e->params[3], e->params[4],
8227 e->params[5], e->params[6], e->params[7]);
8229 if (++i == nentries)
8231 } while (i != first);
8238 sysctl_devlog(SYSCTL_HANDLER_ARGS)
8240 struct adapter *sc = arg1;
8244 rc = sysctl_wire_old_buffer(req, 0);
8247 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8251 rc = sbuf_devlog(sc, sb, M_WAITOK);
8253 rc = sbuf_finish(sb);
8259 t4_os_dump_devlog(struct adapter *sc)
8264 if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb)
8266 rc = sbuf_devlog(sc, &sb, M_NOWAIT);
8268 rc = sbuf_finish(&sb);
8270 log(LOG_DEBUG, "%s: device log follows.\n%s",
8271 device_get_nameunit(sc->dev), sbuf_data(&sb));
8278 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
8280 struct adapter *sc = arg1;
8283 struct tp_fcoe_stats stats[MAX_NCHAN];
8284 int i, nchan = sc->chip_params->nchan;
8286 rc = sysctl_wire_old_buffer(req, 0);
8290 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8294 for (i = 0; i < nchan; i++)
8295 t4_get_fcoe_stats(sc, i, &stats[i], 1);
8298 sbuf_printf(sb, " channel 0 channel 1"
8299 " channel 2 channel 3");
8300 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
8301 stats[0].octets_ddp, stats[1].octets_ddp,
8302 stats[2].octets_ddp, stats[3].octets_ddp);
8303 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
8304 stats[0].frames_ddp, stats[1].frames_ddp,
8305 stats[2].frames_ddp, stats[3].frames_ddp);
8306 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
8307 stats[0].frames_drop, stats[1].frames_drop,
8308 stats[2].frames_drop, stats[3].frames_drop);
8310 sbuf_printf(sb, " channel 0 channel 1");
8311 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
8312 stats[0].octets_ddp, stats[1].octets_ddp);
8313 sbuf_printf(sb, "\nframesDDP: %16u %16u",
8314 stats[0].frames_ddp, stats[1].frames_ddp);
8315 sbuf_printf(sb, "\nframesDrop: %16u %16u",
8316 stats[0].frames_drop, stats[1].frames_drop);
8319 rc = sbuf_finish(sb);
8326 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
8328 struct adapter *sc = arg1;
8331 unsigned int map, kbps, ipg, mode;
8332 unsigned int pace_tab[NTX_SCHED];
8334 rc = sysctl_wire_old_buffer(req, 0);
8338 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8342 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
8343 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
8344 t4_read_pace_tbl(sc, pace_tab);
8346 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
8347 "Class IPG (0.1 ns) Flow IPG (us)");
8349 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
8350 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
8351 sbuf_printf(sb, "\n %u %-5s %u ", i,
8352 (mode & (1 << i)) ? "flow" : "class", map & 3);
8354 sbuf_printf(sb, "%9u ", kbps);
8356 sbuf_printf(sb, " disabled ");
8359 sbuf_printf(sb, "%13u ", ipg);
8361 sbuf_printf(sb, " disabled ");
8364 sbuf_printf(sb, "%10u", pace_tab[i]);
8366 sbuf_printf(sb, " disabled");
8369 rc = sbuf_finish(sb);
8376 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
8378 struct adapter *sc = arg1;
8382 struct lb_port_stats s[2];
8383 static const char *stat_name[] = {
8384 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
8385 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
8386 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
8387 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
8388 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
8389 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
8390 "BG2FramesTrunc:", "BG3FramesTrunc:"
8393 rc = sysctl_wire_old_buffer(req, 0);
8397 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8401 memset(s, 0, sizeof(s));
8403 for (i = 0; i < sc->chip_params->nchan; i += 2) {
8404 t4_get_lb_stats(sc, i, &s[0]);
8405 t4_get_lb_stats(sc, i + 1, &s[1]);
8409 sbuf_printf(sb, "%s Loopback %u"
8410 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
8412 for (j = 0; j < nitems(stat_name); j++)
8413 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
8417 rc = sbuf_finish(sb);
8424 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
8427 struct port_info *pi = arg1;
8428 struct link_config *lc = &pi->link_cfg;
8431 rc = sysctl_wire_old_buffer(req, 0);
8434 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
8438 if (lc->link_ok || lc->link_down_rc == 255)
8439 sbuf_printf(sb, "n/a");
8441 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
8443 rc = sbuf_finish(sb);
8456 mem_desc_cmp(const void *a, const void *b)
8458 return ((const struct mem_desc *)a)->base -
8459 ((const struct mem_desc *)b)->base;
8463 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
8471 size = to - from + 1;
8475 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
8476 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
8480 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
8482 struct adapter *sc = arg1;
8485 uint32_t lo, hi, used, alloc;
8486 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
8487 static const char *region[] = {
8488 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
8489 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
8490 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
8491 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
8492 "RQUDP region:", "PBL region:", "TXPBL region:",
8493 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
8494 "On-chip queues:", "TLS keys:",
8496 struct mem_desc avail[4];
8497 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
8498 struct mem_desc *md = mem;
8500 rc = sysctl_wire_old_buffer(req, 0);
8504 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8508 for (i = 0; i < nitems(mem); i++) {
8513 /* Find and sort the populated memory ranges */
8515 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
8516 if (lo & F_EDRAM0_ENABLE) {
8517 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
8518 avail[i].base = G_EDRAM0_BASE(hi) << 20;
8519 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
8523 if (lo & F_EDRAM1_ENABLE) {
8524 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
8525 avail[i].base = G_EDRAM1_BASE(hi) << 20;
8526 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
8530 if (lo & F_EXT_MEM_ENABLE) {
8531 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
8532 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
8533 avail[i].limit = avail[i].base +
8534 (G_EXT_MEM_SIZE(hi) << 20);
8535 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
8538 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
8539 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
8540 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
8541 avail[i].limit = avail[i].base +
8542 (G_EXT_MEM1_SIZE(hi) << 20);
8546 if (!i) /* no memory available */
8548 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
8550 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
8551 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
8552 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
8553 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
8554 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
8555 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
8556 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
8557 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
8558 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
8560 /* the next few have explicit upper bounds */
8561 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
8562 md->limit = md->base - 1 +
8563 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
8564 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
8567 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
8568 md->limit = md->base - 1 +
8569 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
8570 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
8573 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8574 if (chip_id(sc) <= CHELSIO_T5)
8575 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
8577 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
8581 md->idx = nitems(region); /* hide it */
8585 #define ulp_region(reg) \
8586 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
8587 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
8589 ulp_region(RX_ISCSI);
8590 ulp_region(RX_TDDP);
8592 ulp_region(RX_STAG);
8594 ulp_region(RX_RQUDP);
8600 md->idx = nitems(region);
8603 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
8604 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
8607 if (sge_ctrl & F_VFIFO_ENABLE)
8608 size = G_DBVFIFO_SIZE(fifo_size);
8610 size = G_T6_DBVFIFO_SIZE(fifo_size);
8613 md->base = G_BASEADDR(t4_read_reg(sc,
8614 A_SGE_DBVFIFO_BADDR));
8615 md->limit = md->base + (size << 2) - 1;
8620 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
8623 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
8627 md->base = sc->vres.ocq.start;
8628 if (sc->vres.ocq.size)
8629 md->limit = md->base + sc->vres.ocq.size - 1;
8631 md->idx = nitems(region); /* hide it */
8634 md->base = sc->vres.key.start;
8635 if (sc->vres.key.size)
8636 md->limit = md->base + sc->vres.key.size - 1;
8638 md->idx = nitems(region); /* hide it */
8641 /* add any address-space holes, there can be up to 3 */
8642 for (n = 0; n < i - 1; n++)
8643 if (avail[n].limit < avail[n + 1].base)
8644 (md++)->base = avail[n].limit;
8646 (md++)->base = avail[n].limit;
8649 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
8651 for (lo = 0; lo < i; lo++)
8652 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
8653 avail[lo].limit - 1);
8655 sbuf_printf(sb, "\n");
8656 for (i = 0; i < n; i++) {
8657 if (mem[i].idx >= nitems(region))
8658 continue; /* skip holes */
8660 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
8661 mem_region_show(sb, region[mem[i].idx], mem[i].base,
8665 sbuf_printf(sb, "\n");
8666 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
8667 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
8668 mem_region_show(sb, "uP RAM:", lo, hi);
8670 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
8671 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
8672 mem_region_show(sb, "uP Extmem2:", lo, hi);
8674 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
8675 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
8677 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
8678 (lo & F_PMRXNUMCHN) ? 2 : 1);
8680 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
8681 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
8682 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
8684 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
8685 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
8686 sbuf_printf(sb, "%u p-structs\n",
8687 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
8689 for (i = 0; i < 4; i++) {
8690 if (chip_id(sc) > CHELSIO_T5)
8691 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
8693 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
8695 used = G_T5_USED(lo);
8696 alloc = G_T5_ALLOC(lo);
8699 alloc = G_ALLOC(lo);
8701 /* For T6 these are MAC buffer groups */
8702 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
8705 for (i = 0; i < sc->chip_params->nchan; i++) {
8706 if (chip_id(sc) > CHELSIO_T5)
8707 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
8709 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
8711 used = G_T5_USED(lo);
8712 alloc = G_T5_ALLOC(lo);
8715 alloc = G_ALLOC(lo);
8717 /* For T6 these are MAC buffer groups */
8719 "\nLoopback %d using %u pages out of %u allocated",
8723 rc = sbuf_finish(sb);
8730 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
8734 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
8738 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
8740 struct adapter *sc = arg1;
8744 MPASS(chip_id(sc) <= CHELSIO_T5);
8746 rc = sysctl_wire_old_buffer(req, 0);
8750 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8755 "Idx Ethernet address Mask Vld Ports PF"
8756 " VF Replication P0 P1 P2 P3 ML");
8757 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8758 uint64_t tcamx, tcamy, mask;
8759 uint32_t cls_lo, cls_hi;
8760 uint8_t addr[ETHER_ADDR_LEN];
8762 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
8763 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
8766 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8767 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8768 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8769 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
8770 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
8771 addr[3], addr[4], addr[5], (uintmax_t)mask,
8772 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
8773 G_PORTMAP(cls_hi), G_PF(cls_lo),
8774 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
8776 if (cls_lo & F_REPLICATE) {
8777 struct fw_ldst_cmd ldst_cmd;
8779 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8780 ldst_cmd.op_to_addrspace =
8781 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8782 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8783 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8784 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8785 ldst_cmd.u.mps.rplc.fid_idx =
8786 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8787 V_FW_LDST_CMD_IDX(i));
8789 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8793 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8794 sizeof(ldst_cmd), &ldst_cmd);
8795 end_synchronized_op(sc, 0);
8798 sbuf_printf(sb, "%36d", rc);
8801 sbuf_printf(sb, " %08x %08x %08x %08x",
8802 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8803 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8804 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8805 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8808 sbuf_printf(sb, "%36s", "");
8810 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8811 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8812 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8816 (void) sbuf_finish(sb);
8818 rc = sbuf_finish(sb);
8825 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8827 struct adapter *sc = arg1;
8831 MPASS(chip_id(sc) > CHELSIO_T5);
8833 rc = sysctl_wire_old_buffer(req, 0);
8837 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8841 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8842 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8844 " P0 P1 P2 P3 ML\n");
8846 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8847 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8849 uint64_t tcamx, tcamy, val, mask;
8850 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8851 uint8_t addr[ETHER_ADDR_LEN];
8853 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8855 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8857 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8858 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8859 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8860 tcamy = G_DMACH(val) << 32;
8861 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8862 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8863 lookup_type = G_DATALKPTYPE(data2);
8864 port_num = G_DATAPORTNUM(data2);
8865 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8866 /* Inner header VNI */
8867 vniy = ((data2 & F_DATAVIDH2) << 23) |
8868 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8869 dip_hit = data2 & F_DATADIPHIT;
8874 vlan_vld = data2 & F_DATAVIDH2;
8875 ivlan = G_VIDL(val);
8878 ctl |= V_CTLXYBITSEL(1);
8879 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8880 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8881 tcamx = G_DMACH(val) << 32;
8882 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8883 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8884 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8885 /* Inner header VNI mask */
8886 vnix = ((data2 & F_DATAVIDH2) << 23) |
8887 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8893 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8895 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8896 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8898 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8899 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8900 "%012jx %06x %06x - - %3c"
8901 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8902 addr[1], addr[2], addr[3], addr[4], addr[5],
8903 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8904 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8905 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8906 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8908 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8909 "%012jx - - ", i, addr[0], addr[1],
8910 addr[2], addr[3], addr[4], addr[5],
8914 sbuf_printf(sb, "%4u Y ", ivlan);
8916 sbuf_printf(sb, " - N ");
8918 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8919 lookup_type ? 'I' : 'O', port_num,
8920 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8921 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8922 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8926 if (cls_lo & F_T6_REPLICATE) {
8927 struct fw_ldst_cmd ldst_cmd;
8929 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8930 ldst_cmd.op_to_addrspace =
8931 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8932 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8933 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8934 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8935 ldst_cmd.u.mps.rplc.fid_idx =
8936 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8937 V_FW_LDST_CMD_IDX(i));
8939 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8943 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8944 sizeof(ldst_cmd), &ldst_cmd);
8945 end_synchronized_op(sc, 0);
8948 sbuf_printf(sb, "%72d", rc);
8951 sbuf_printf(sb, " %08x %08x %08x %08x"
8952 " %08x %08x %08x %08x",
8953 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8954 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8955 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8956 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8957 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8958 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8959 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8960 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8963 sbuf_printf(sb, "%72s", "");
8965 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8966 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8967 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8968 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8972 (void) sbuf_finish(sb);
8974 rc = sbuf_finish(sb);
8981 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8983 struct adapter *sc = arg1;
8986 uint16_t mtus[NMTUS];
8988 rc = sysctl_wire_old_buffer(req, 0);
8992 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8996 t4_read_mtu_tbl(sc, mtus, NULL);
8998 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8999 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
9000 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
9001 mtus[14], mtus[15]);
9003 rc = sbuf_finish(sb);
9010 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
9012 struct adapter *sc = arg1;
9015 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
9016 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
9017 static const char *tx_stats[MAX_PM_NSTATS] = {
9018 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
9019 "Tx FIFO wait", NULL, "Tx latency"
9021 static const char *rx_stats[MAX_PM_NSTATS] = {
9022 "Read:", "Write bypass:", "Write mem:", "Flush:",
9023 "Rx FIFO wait", NULL, "Rx latency"
9026 rc = sysctl_wire_old_buffer(req, 0);
9030 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9034 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
9035 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
9037 sbuf_printf(sb, " Tx pcmds Tx bytes");
9038 for (i = 0; i < 4; i++) {
9039 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9043 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
9044 for (i = 0; i < 4; i++) {
9045 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9049 if (chip_id(sc) > CHELSIO_T5) {
9051 "\n Total wait Total occupancy");
9052 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9054 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9058 MPASS(i < nitems(tx_stats));
9061 "\n Reads Total wait");
9062 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
9064 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
9068 rc = sbuf_finish(sb);
9075 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
9077 struct adapter *sc = arg1;
9080 struct tp_rdma_stats stats;
9082 rc = sysctl_wire_old_buffer(req, 0);
9086 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9090 mtx_lock(&sc->reg_lock);
9091 t4_tp_get_rdma_stats(sc, &stats, 0);
9092 mtx_unlock(&sc->reg_lock);
9094 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
9095 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
9097 rc = sbuf_finish(sb);
9104 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
9106 struct adapter *sc = arg1;
9109 struct tp_tcp_stats v4, v6;
9111 rc = sysctl_wire_old_buffer(req, 0);
9115 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9119 mtx_lock(&sc->reg_lock);
9120 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
9121 mtx_unlock(&sc->reg_lock);
9125 sbuf_printf(sb, "OutRsts: %20u %20u\n",
9126 v4.tcp_out_rsts, v6.tcp_out_rsts);
9127 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
9128 v4.tcp_in_segs, v6.tcp_in_segs);
9129 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
9130 v4.tcp_out_segs, v6.tcp_out_segs);
9131 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
9132 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
9134 rc = sbuf_finish(sb);
9141 sysctl_tids(SYSCTL_HANDLER_ARGS)
9143 struct adapter *sc = arg1;
9146 struct tid_info *t = &sc->tids;
9148 rc = sysctl_wire_old_buffer(req, 0);
9152 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9157 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
9162 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
9163 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
9167 sbuf_printf(sb, "TID range: ");
9168 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
9171 if (chip_id(sc) <= CHELSIO_T5) {
9172 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
9173 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
9175 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
9176 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
9180 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
9181 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
9183 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
9184 sbuf_printf(sb, ", in use: %u\n",
9185 atomic_load_acq_int(&t->tids_in_use));
9189 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
9190 t->stid_base + t->nstids - 1, t->stids_in_use);
9194 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
9195 t->ftid_end, t->ftids_in_use);
9199 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
9200 t->etid_base + t->netids - 1, t->etids_in_use);
9203 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
9204 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
9205 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
9207 rc = sbuf_finish(sb);
9214 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
9216 struct adapter *sc = arg1;
9219 struct tp_err_stats stats;
9221 rc = sysctl_wire_old_buffer(req, 0);
9225 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9229 mtx_lock(&sc->reg_lock);
9230 t4_tp_get_err_stats(sc, &stats, 0);
9231 mtx_unlock(&sc->reg_lock);
9233 if (sc->chip_params->nchan > 2) {
9234 sbuf_printf(sb, " channel 0 channel 1"
9235 " channel 2 channel 3\n");
9236 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
9237 stats.mac_in_errs[0], stats.mac_in_errs[1],
9238 stats.mac_in_errs[2], stats.mac_in_errs[3]);
9239 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
9240 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
9241 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
9242 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
9243 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
9244 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
9245 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
9246 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
9247 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
9248 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
9249 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
9250 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
9251 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
9252 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
9253 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
9254 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
9255 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
9256 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
9257 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
9258 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
9259 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
9261 sbuf_printf(sb, " channel 0 channel 1\n");
9262 sbuf_printf(sb, "macInErrs: %10u %10u\n",
9263 stats.mac_in_errs[0], stats.mac_in_errs[1]);
9264 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
9265 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
9266 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
9267 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
9268 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
9269 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
9270 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
9271 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
9272 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
9273 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
9274 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
9275 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
9276 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
9277 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
9280 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
9281 stats.ofld_no_neigh, stats.ofld_cong_defer);
9283 rc = sbuf_finish(sb);
9290 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
9292 struct adapter *sc = arg1;
9293 struct tp_params *tpp = &sc->params.tp;
9297 mask = tpp->la_mask >> 16;
9298 rc = sysctl_handle_int(oidp, &mask, 0, req);
9299 if (rc != 0 || req->newptr == NULL)
9303 tpp->la_mask = mask << 16;
9304 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
9316 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
9322 uint64_t mask = (1ULL << f->width) - 1;
9323 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
9324 ((uintmax_t)v >> f->start) & mask);
9326 if (line_size + len >= 79) {
9328 sbuf_printf(sb, "\n ");
9330 sbuf_printf(sb, "%s ", buf);
9331 line_size += len + 1;
9334 sbuf_printf(sb, "\n");
9337 static const struct field_desc tp_la0[] = {
9338 { "RcfOpCodeOut", 60, 4 },
9340 { "WcfState", 52, 4 },
9341 { "RcfOpcSrcOut", 50, 2 },
9342 { "CRxError", 49, 1 },
9343 { "ERxError", 48, 1 },
9344 { "SanityFailed", 47, 1 },
9345 { "SpuriousMsg", 46, 1 },
9346 { "FlushInputMsg", 45, 1 },
9347 { "FlushInputCpl", 44, 1 },
9348 { "RssUpBit", 43, 1 },
9349 { "RssFilterHit", 42, 1 },
9351 { "InitTcb", 31, 1 },
9352 { "LineNumber", 24, 7 },
9354 { "EdataOut", 22, 1 },
9356 { "CdataOut", 20, 1 },
9357 { "EreadPdu", 19, 1 },
9358 { "CreadPdu", 18, 1 },
9359 { "TunnelPkt", 17, 1 },
9360 { "RcfPeerFin", 16, 1 },
9361 { "RcfReasonOut", 12, 4 },
9362 { "TxCchannel", 10, 2 },
9363 { "RcfTxChannel", 8, 2 },
9364 { "RxEchannel", 6, 2 },
9365 { "RcfRxChannel", 5, 1 },
9366 { "RcfDataOutSrdy", 4, 1 },
9368 { "RxOoDvld", 2, 1 },
9369 { "RxCongestion", 1, 1 },
9370 { "TxCongestion", 0, 1 },
9374 static const struct field_desc tp_la1[] = {
9375 { "CplCmdIn", 56, 8 },
9376 { "CplCmdOut", 48, 8 },
9377 { "ESynOut", 47, 1 },
9378 { "EAckOut", 46, 1 },
9379 { "EFinOut", 45, 1 },
9380 { "ERstOut", 44, 1 },
9385 { "DataIn", 39, 1 },
9386 { "DataInVld", 38, 1 },
9388 { "RxBufEmpty", 36, 1 },
9390 { "RxFbCongestion", 34, 1 },
9391 { "TxFbCongestion", 33, 1 },
9392 { "TxPktSumSrdy", 32, 1 },
9393 { "RcfUlpType", 28, 4 },
9395 { "Ebypass", 26, 1 },
9397 { "Static0", 24, 1 },
9399 { "Cbypass", 22, 1 },
9401 { "CPktOut", 20, 1 },
9402 { "RxPagePoolFull", 18, 2 },
9403 { "RxLpbkPkt", 17, 1 },
9404 { "TxLpbkPkt", 16, 1 },
9405 { "RxVfValid", 15, 1 },
9406 { "SynLearned", 14, 1 },
9407 { "SetDelEntry", 13, 1 },
9408 { "SetInvEntry", 12, 1 },
9409 { "CpcmdDvld", 11, 1 },
9410 { "CpcmdSave", 10, 1 },
9411 { "RxPstructsFull", 8, 2 },
9412 { "EpcmdDvld", 7, 1 },
9413 { "EpcmdFlush", 6, 1 },
9414 { "EpcmdTrimPrefix", 5, 1 },
9415 { "EpcmdTrimPostfix", 4, 1 },
9416 { "ERssIp4Pkt", 3, 1 },
9417 { "ERssIp6Pkt", 2, 1 },
9418 { "ERssTcpUdpPkt", 1, 1 },
9419 { "ERssFceFipPkt", 0, 1 },
9423 static const struct field_desc tp_la2[] = {
9424 { "CplCmdIn", 56, 8 },
9425 { "MpsVfVld", 55, 1 },
9432 { "DataIn", 39, 1 },
9433 { "DataInVld", 38, 1 },
9435 { "RxBufEmpty", 36, 1 },
9437 { "RxFbCongestion", 34, 1 },
9438 { "TxFbCongestion", 33, 1 },
9439 { "TxPktSumSrdy", 32, 1 },
9440 { "RcfUlpType", 28, 4 },
9442 { "Ebypass", 26, 1 },
9444 { "Static0", 24, 1 },
9446 { "Cbypass", 22, 1 },
9448 { "CPktOut", 20, 1 },
9449 { "RxPagePoolFull", 18, 2 },
9450 { "RxLpbkPkt", 17, 1 },
9451 { "TxLpbkPkt", 16, 1 },
9452 { "RxVfValid", 15, 1 },
9453 { "SynLearned", 14, 1 },
9454 { "SetDelEntry", 13, 1 },
9455 { "SetInvEntry", 12, 1 },
9456 { "CpcmdDvld", 11, 1 },
9457 { "CpcmdSave", 10, 1 },
9458 { "RxPstructsFull", 8, 2 },
9459 { "EpcmdDvld", 7, 1 },
9460 { "EpcmdFlush", 6, 1 },
9461 { "EpcmdTrimPrefix", 5, 1 },
9462 { "EpcmdTrimPostfix", 4, 1 },
9463 { "ERssIp4Pkt", 3, 1 },
9464 { "ERssIp6Pkt", 2, 1 },
9465 { "ERssTcpUdpPkt", 1, 1 },
9466 { "ERssFceFipPkt", 0, 1 },
9471 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
9474 field_desc_show(sb, *p, tp_la0);
9478 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
9482 sbuf_printf(sb, "\n");
9483 field_desc_show(sb, p[0], tp_la0);
9484 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9485 field_desc_show(sb, p[1], tp_la0);
9489 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
9493 sbuf_printf(sb, "\n");
9494 field_desc_show(sb, p[0], tp_la0);
9495 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
9496 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
9500 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
9502 struct adapter *sc = arg1;
9507 void (*show_func)(struct sbuf *, uint64_t *, int);
9509 rc = sysctl_wire_old_buffer(req, 0);
9513 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9517 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
9519 t4_tp_read_la(sc, buf, NULL);
9522 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
9525 show_func = tp_la_show2;
9529 show_func = tp_la_show3;
9533 show_func = tp_la_show;
9536 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
9537 (*show_func)(sb, p, i);
9539 rc = sbuf_finish(sb);
9546 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
9548 struct adapter *sc = arg1;
9551 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
9553 rc = sysctl_wire_old_buffer(req, 0);
9557 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
9561 t4_get_chan_txrate(sc, nrate, orate);
9563 if (sc->chip_params->nchan > 2) {
9564 sbuf_printf(sb, " channel 0 channel 1"
9565 " channel 2 channel 3\n");
9566 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
9567 nrate[0], nrate[1], nrate[2], nrate[3]);
9568 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
9569 orate[0], orate[1], orate[2], orate[3]);
9571 sbuf_printf(sb, " channel 0 channel 1\n");
9572 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
9573 nrate[0], nrate[1]);
9574 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
9575 orate[0], orate[1]);
9578 rc = sbuf_finish(sb);
9585 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
9587 struct adapter *sc = arg1;
9592 rc = sysctl_wire_old_buffer(req, 0);
9596 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9600 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
9603 t4_ulprx_read_la(sc, buf);
9606 sbuf_printf(sb, " Pcmd Type Message"
9608 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
9609 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
9610 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
9613 rc = sbuf_finish(sb);
9620 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
9622 struct adapter *sc = arg1;
9626 MPASS(chip_id(sc) >= CHELSIO_T5);
9628 rc = sysctl_wire_old_buffer(req, 0);
9632 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9636 v = t4_read_reg(sc, A_SGE_STAT_CFG);
9637 if (G_STATSOURCE_T5(v) == 7) {
9640 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
9642 sbuf_printf(sb, "total %d, incomplete %d",
9643 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9644 t4_read_reg(sc, A_SGE_STAT_MATCH));
9645 } else if (mode == 1) {
9646 sbuf_printf(sb, "total %d, data overflow %d",
9647 t4_read_reg(sc, A_SGE_STAT_TOTAL),
9648 t4_read_reg(sc, A_SGE_STAT_MATCH));
9650 sbuf_printf(sb, "unknown mode %d", mode);
9653 rc = sbuf_finish(sb);
9660 sysctl_cpus(SYSCTL_HANDLER_ARGS)
9662 struct adapter *sc = arg1;
9663 enum cpu_sets op = arg2;
9668 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
9671 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
9675 rc = sysctl_wire_old_buffer(req, 0);
9679 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
9684 sbuf_printf(sb, "%d ", i);
9685 rc = sbuf_finish(sb);
9693 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
9695 struct adapter *sc = arg1;
9696 int *old_ports, *new_ports;
9697 int i, new_count, rc;
9699 if (req->newptr == NULL && req->oldptr == NULL)
9700 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
9701 sizeof(sc->tt.tls_rx_ports[0])));
9703 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
9707 if (sc->tt.num_tls_rx_ports == 0) {
9709 rc = SYSCTL_OUT(req, &i, sizeof(i));
9711 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
9712 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
9713 if (rc == 0 && req->newptr != NULL) {
9714 new_count = req->newlen / sizeof(new_ports[0]);
9715 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
9717 rc = SYSCTL_IN(req, new_ports, new_count *
9718 sizeof(new_ports[0]));
9722 /* Allow setting to a single '-1' to clear the list. */
9723 if (new_count == 1 && new_ports[0] == -1) {
9725 old_ports = sc->tt.tls_rx_ports;
9726 sc->tt.tls_rx_ports = NULL;
9727 sc->tt.num_tls_rx_ports = 0;
9729 free(old_ports, M_CXGBE);
9731 for (i = 0; i < new_count; i++) {
9732 if (new_ports[i] < 1 ||
9733 new_ports[i] > IPPORT_MAX) {
9740 old_ports = sc->tt.tls_rx_ports;
9741 sc->tt.tls_rx_ports = new_ports;
9742 sc->tt.num_tls_rx_ports = new_count;
9744 free(old_ports, M_CXGBE);
9748 free(new_ports, M_CXGBE);
9750 end_synchronized_op(sc, 0);
9755 unit_conv(char *buf, size_t len, u_int val, u_int factor)
9757 u_int rem = val % factor;
9760 snprintf(buf, len, "%u", val / factor);
9762 while (rem % 10 == 0)
9764 snprintf(buf, len, "%u.%u", val / factor, rem);
9769 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
9771 struct adapter *sc = arg1;
9774 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9776 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9780 re = G_TIMERRESOLUTION(res);
9783 /* TCP timestamp tick */
9784 re = G_TIMESTAMPRESOLUTION(res);
9788 re = G_DELAYEDACKRESOLUTION(res);
9794 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9796 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9800 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9802 struct adapter *sc = arg1;
9803 u_int res, dack_re, v;
9804 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9806 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9807 dack_re = G_DELAYEDACKRESOLUTION(res);
9808 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9810 return (sysctl_handle_int(oidp, &v, 0, req));
9814 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9816 struct adapter *sc = arg1;
9819 u_long tp_tick_us, v;
9820 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9822 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9823 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9824 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9825 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9827 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9828 tp_tick_us = (cclk_ps << tre) / 1000000;
9830 if (reg == A_TP_INIT_SRTT)
9831 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9833 v = tp_tick_us * t4_read_reg(sc, reg);
9835 return (sysctl_handle_long(oidp, &v, 0, req));
9839 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9840 * passed to this function.
9843 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9845 struct adapter *sc = arg1;
9849 MPASS(idx >= 0 && idx <= 24);
9851 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9853 return (sysctl_handle_int(oidp, &v, 0, req));
9857 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9859 struct adapter *sc = arg1;
9863 MPASS(idx >= 0 && idx < 16);
9865 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9866 shift = (idx & 3) << 3;
9867 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9869 return (sysctl_handle_int(oidp, &v, 0, req));
9873 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9875 struct vi_info *vi = arg1;
9876 struct adapter *sc = vi->pi->adapter;
9878 struct sge_ofld_rxq *ofld_rxq;
9881 idx = vi->ofld_tmr_idx;
9883 rc = sysctl_handle_int(oidp, &idx, 0, req);
9884 if (rc != 0 || req->newptr == NULL)
9887 if (idx < 0 || idx >= SGE_NTIMERS)
9890 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9895 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9896 for_each_ofld_rxq(vi, i, ofld_rxq) {
9897 #ifdef atomic_store_rel_8
9898 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9900 ofld_rxq->iq.intr_params = v;
9903 vi->ofld_tmr_idx = idx;
9905 end_synchronized_op(sc, LOCK_HELD);
9910 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9912 struct vi_info *vi = arg1;
9913 struct adapter *sc = vi->pi->adapter;
9916 idx = vi->ofld_pktc_idx;
9918 rc = sysctl_handle_int(oidp, &idx, 0, req);
9919 if (rc != 0 || req->newptr == NULL)
9922 if (idx < -1 || idx >= SGE_NCOUNTERS)
9925 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9930 if (vi->flags & VI_INIT_DONE)
9931 rc = EBUSY; /* cannot be changed once the queues are created */
9933 vi->ofld_pktc_idx = idx;
9935 end_synchronized_op(sc, LOCK_HELD);
9941 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9945 if (cntxt->cid > M_CTXTQID)
9948 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9949 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9952 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9956 if (sc->flags & FW_OK) {
9957 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9964 * Read via firmware failed or wasn't even attempted. Read directly via
9967 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9969 end_synchronized_op(sc, 0);
9974 load_fw(struct adapter *sc, struct t4_data *fw)
9979 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9984 * The firmware, with the sole exception of the memory parity error
9985 * handler, runs from memory and not flash. It is almost always safe to
9986 * install a new firmware on a running system. Just set bit 1 in
9987 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9989 if (sc->flags & FULL_INIT_DONE &&
9990 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9995 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9996 if (fw_data == NULL) {
10001 rc = copyin(fw->data, fw_data, fw->len);
10003 rc = -t4_load_fw(sc, fw_data, fw->len);
10005 free(fw_data, M_CXGBE);
10007 end_synchronized_op(sc, 0);
10012 load_cfg(struct adapter *sc, struct t4_data *cfg)
10015 uint8_t *cfg_data = NULL;
10017 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
10021 if (cfg->len == 0) {
10023 rc = -t4_load_cfg(sc, NULL, 0);
10027 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
10028 if (cfg_data == NULL) {
10033 rc = copyin(cfg->data, cfg_data, cfg->len);
10035 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
10037 free(cfg_data, M_CXGBE);
10039 end_synchronized_op(sc, 0);
10044 load_boot(struct adapter *sc, struct t4_bootrom *br)
10047 uint8_t *br_data = NULL;
10050 if (br->len > 1024 * 1024)
10053 if (br->pf_offset == 0) {
10055 if (br->pfidx_addr > 7)
10057 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
10058 A_PCIE_PF_EXPROM_OFST)));
10059 } else if (br->pf_offset == 1) {
10061 offset = G_OFFSET(br->pfidx_addr);
10066 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
10070 if (br->len == 0) {
10072 rc = -t4_load_boot(sc, NULL, offset, 0);
10076 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
10077 if (br_data == NULL) {
10082 rc = copyin(br->data, br_data, br->len);
10084 rc = -t4_load_boot(sc, br_data, offset, br->len);
10086 free(br_data, M_CXGBE);
10088 end_synchronized_op(sc, 0);
10093 load_bootcfg(struct adapter *sc, struct t4_data *bc)
10096 uint8_t *bc_data = NULL;
10098 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
10102 if (bc->len == 0) {
10104 rc = -t4_load_bootcfg(sc, NULL, 0);
10108 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
10109 if (bc_data == NULL) {
10114 rc = copyin(bc->data, bc_data, bc->len);
10116 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
10118 free(bc_data, M_CXGBE);
10120 end_synchronized_op(sc, 0);
10125 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
10128 struct cudbg_init *cudbg;
10129 void *handle, *buf;
10131 /* buf is large, don't block if no memory is available */
10132 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
10136 handle = cudbg_alloc_handle();
10137 if (handle == NULL) {
10142 cudbg = cudbg_get_init(handle);
10144 cudbg->print = (cudbg_print_cb)printf;
10147 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
10148 __func__, dump->wr_flash, dump->len, dump->data);
10151 if (dump->wr_flash)
10152 cudbg->use_flash = 1;
10153 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
10154 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
10156 rc = cudbg_collect(handle, buf, &dump->len);
10160 rc = copyout(buf, dump->data, dump->len);
10162 cudbg_free_handle(handle);
10163 free(buf, M_CXGBE);
10168 free_offload_policy(struct t4_offload_policy *op)
10170 struct offload_rule *r;
10177 for (i = 0; i < op->nrules; i++, r++) {
10178 free(r->bpf_prog.bf_insns, M_CXGBE);
10180 free(op->rule, M_CXGBE);
10185 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
10188 struct t4_offload_policy *op, *old;
10189 struct bpf_program *bf;
10190 const struct offload_settings *s;
10191 struct offload_rule *r;
10194 if (!is_offload(sc))
10197 if (uop->nrules == 0) {
10198 /* Delete installed policies. */
10201 } else if (uop->nrules > 256) { /* arbitrary */
10205 /* Copy userspace offload policy to kernel */
10206 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
10207 op->nrules = uop->nrules;
10208 len = op->nrules * sizeof(struct offload_rule);
10209 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
10210 rc = copyin(uop->rule, op->rule, len);
10212 free(op->rule, M_CXGBE);
10218 for (i = 0; i < op->nrules; i++, r++) {
10220 /* Validate open_type */
10221 if (r->open_type != OPEN_TYPE_LISTEN &&
10222 r->open_type != OPEN_TYPE_ACTIVE &&
10223 r->open_type != OPEN_TYPE_PASSIVE &&
10224 r->open_type != OPEN_TYPE_DONTCARE) {
10227 * Rules 0 to i have malloc'd filters that need to be
10228 * freed. Rules i+1 to nrules have userspace pointers
10229 * and should be left alone.
10232 free_offload_policy(op);
10236 /* Validate settings */
10238 if ((s->offload != 0 && s->offload != 1) ||
10239 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
10240 s->sched_class < -1 ||
10241 s->sched_class >= sc->chip_params->nsched_cls) {
10247 u = bf->bf_insns; /* userspace ptr */
10248 bf->bf_insns = NULL;
10249 if (bf->bf_len == 0) {
10250 /* legal, matches everything */
10253 len = bf->bf_len * sizeof(*bf->bf_insns);
10254 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
10255 rc = copyin(u, bf->bf_insns, len);
10259 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
10265 rw_wlock(&sc->policy_lock);
10268 rw_wunlock(&sc->policy_lock);
10269 free_offload_policy(old);
10274 #define MAX_READ_BUF_SIZE (128 * 1024)
10276 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
10278 uint32_t addr, remaining, n;
10283 rc = validate_mem_range(sc, mr->addr, mr->len);
10287 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
10289 remaining = mr->len;
10290 dst = (void *)mr->data;
10292 while (remaining) {
10293 n = min(remaining, MAX_READ_BUF_SIZE);
10294 read_via_memwin(sc, 2, addr, buf, n);
10296 rc = copyout(buf, dst, n);
10305 free(buf, M_CXGBE);
10308 #undef MAX_READ_BUF_SIZE
10311 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
10315 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
10318 if (i2cd->len > sizeof(i2cd->data))
10321 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
10324 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
10325 i2cd->offset, i2cd->len, &i2cd->data[0]);
10326 end_synchronized_op(sc, 0);
10332 clear_stats(struct adapter *sc, u_int port_id)
10334 int i, v, chan_map;
10335 struct port_info *pi;
10336 struct vi_info *vi;
10337 struct sge_rxq *rxq;
10338 struct sge_txq *txq;
10339 struct sge_wrq *wrq;
10341 struct sge_ofld_rxq *ofld_rxq;
10344 if (port_id >= sc->params.nports)
10346 pi = sc->port[port_id];
10351 t4_clr_port_stats(sc, pi->tx_chan);
10352 pi->tx_parse_error = 0;
10353 pi->tnl_cong_drops = 0;
10354 mtx_lock(&sc->reg_lock);
10355 for_each_vi(pi, v, vi) {
10356 if (vi->flags & VI_INIT_DONE)
10357 t4_clr_vi_stats(sc, vi->vin);
10359 chan_map = pi->rx_e_chan_map;
10362 i = ffs(chan_map) - 1;
10363 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
10364 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
10365 chan_map &= ~(1 << i);
10367 mtx_unlock(&sc->reg_lock);
10370 * Since this command accepts a port, clear stats for
10371 * all VIs on this port.
10373 for_each_vi(pi, v, vi) {
10374 if (vi->flags & VI_INIT_DONE) {
10376 for_each_rxq(vi, i, rxq) {
10377 #if defined(INET) || defined(INET6)
10378 rxq->lro.lro_queued = 0;
10379 rxq->lro.lro_flushed = 0;
10382 rxq->vlan_extraction = 0;
10384 rxq->fl.cl_allocated = 0;
10385 rxq->fl.cl_recycled = 0;
10386 rxq->fl.cl_fast_recycled = 0;
10389 for_each_txq(vi, i, txq) {
10392 txq->vlan_insertion = 0;
10395 txq->txpkt_wrs = 0;
10396 txq->txpkts0_wrs = 0;
10397 txq->txpkts1_wrs = 0;
10398 txq->txpkts0_pkts = 0;
10399 txq->txpkts1_pkts = 0;
10401 txq->kern_tls_records = 0;
10402 txq->kern_tls_short = 0;
10403 txq->kern_tls_partial = 0;
10404 txq->kern_tls_full = 0;
10405 txq->kern_tls_octets = 0;
10406 txq->kern_tls_waste = 0;
10407 txq->kern_tls_options = 0;
10408 txq->kern_tls_header = 0;
10409 txq->kern_tls_fin = 0;
10410 txq->kern_tls_fin_short = 0;
10411 txq->kern_tls_cbc = 0;
10412 txq->kern_tls_gcm = 0;
10413 mp_ring_reset_stats(txq->r);
10416 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10417 for_each_ofld_txq(vi, i, wrq) {
10418 wrq->tx_wrs_direct = 0;
10419 wrq->tx_wrs_copied = 0;
10423 for_each_ofld_rxq(vi, i, ofld_rxq) {
10424 ofld_rxq->fl.cl_allocated = 0;
10425 ofld_rxq->fl.cl_recycled = 0;
10426 ofld_rxq->fl.cl_fast_recycled = 0;
10430 if (IS_MAIN_VI(vi)) {
10431 wrq = &sc->sge.ctrlq[pi->port_id];
10432 wrq->tx_wrs_direct = 0;
10433 wrq->tx_wrs_copied = 0;
10442 t4_os_find_pci_capability(struct adapter *sc, int cap)
10446 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
10450 t4_os_pci_save_state(struct adapter *sc)
10453 struct pci_devinfo *dinfo;
10456 dinfo = device_get_ivars(dev);
10458 pci_cfg_save(dev, dinfo, 0);
10463 t4_os_pci_restore_state(struct adapter *sc)
10466 struct pci_devinfo *dinfo;
10469 dinfo = device_get_ivars(dev);
10471 pci_cfg_restore(dev, dinfo);
10476 t4_os_portmod_changed(struct port_info *pi)
10478 struct adapter *sc = pi->adapter;
10479 struct vi_info *vi;
10481 static const char *mod_str[] = {
10482 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
10485 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
10486 ("%s: port_type %u", __func__, pi->port_type));
10489 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
10491 build_medialist(pi);
10492 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
10493 fixup_link_config(pi);
10494 apply_link_config(pi);
10497 end_synchronized_op(sc, LOCK_HELD);
10501 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
10502 if_printf(ifp, "transceiver unplugged.\n");
10503 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
10504 if_printf(ifp, "unknown transceiver inserted.\n");
10505 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
10506 if_printf(ifp, "unsupported transceiver inserted.\n");
10507 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
10508 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
10509 port_top_speed(pi), mod_str[pi->mod_type]);
10511 if_printf(ifp, "transceiver (type %d) inserted.\n",
10517 t4_os_link_changed(struct port_info *pi)
10519 struct vi_info *vi;
10521 struct link_config *lc;
10524 PORT_LOCK_ASSERT_OWNED(pi);
10526 for_each_vi(pi, v, vi) {
10531 lc = &pi->link_cfg;
10533 ifp->if_baudrate = IF_Mbps(lc->speed);
10534 if_link_state_change(ifp, LINK_STATE_UP);
10536 if_link_state_change(ifp, LINK_STATE_DOWN);
10542 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
10544 struct adapter *sc;
10546 sx_slock(&t4_list_lock);
10547 SLIST_FOREACH(sc, &t4_list, link) {
10549 * func should not make any assumptions about what state sc is
10550 * in - the only guarantee is that sc->sc_lock is a valid lock.
10554 sx_sunlock(&t4_list_lock);
10558 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
10562 struct adapter *sc = dev->si_drv1;
10564 rc = priv_check(td, PRIV_DRIVER);
10569 case CHELSIO_T4_GETREG: {
10570 struct t4_reg *edata = (struct t4_reg *)data;
10572 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10575 if (edata->size == 4)
10576 edata->val = t4_read_reg(sc, edata->addr);
10577 else if (edata->size == 8)
10578 edata->val = t4_read_reg64(sc, edata->addr);
10584 case CHELSIO_T4_SETREG: {
10585 struct t4_reg *edata = (struct t4_reg *)data;
10587 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
10590 if (edata->size == 4) {
10591 if (edata->val & 0xffffffff00000000)
10593 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
10594 } else if (edata->size == 8)
10595 t4_write_reg64(sc, edata->addr, edata->val);
10600 case CHELSIO_T4_REGDUMP: {
10601 struct t4_regdump *regs = (struct t4_regdump *)data;
10602 int reglen = t4_get_regs_len(sc);
10605 if (regs->len < reglen) {
10606 regs->len = reglen; /* hint to the caller */
10610 regs->len = reglen;
10611 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
10612 get_regs(sc, regs, buf);
10613 rc = copyout(buf, regs->data, reglen);
10614 free(buf, M_CXGBE);
10617 case CHELSIO_T4_GET_FILTER_MODE:
10618 rc = get_filter_mode(sc, (uint32_t *)data);
10620 case CHELSIO_T4_SET_FILTER_MODE:
10621 rc = set_filter_mode(sc, *(uint32_t *)data);
10623 case CHELSIO_T4_GET_FILTER:
10624 rc = get_filter(sc, (struct t4_filter *)data);
10626 case CHELSIO_T4_SET_FILTER:
10627 rc = set_filter(sc, (struct t4_filter *)data);
10629 case CHELSIO_T4_DEL_FILTER:
10630 rc = del_filter(sc, (struct t4_filter *)data);
10632 case CHELSIO_T4_GET_SGE_CONTEXT:
10633 rc = get_sge_context(sc, (struct t4_sge_context *)data);
10635 case CHELSIO_T4_LOAD_FW:
10636 rc = load_fw(sc, (struct t4_data *)data);
10638 case CHELSIO_T4_GET_MEM:
10639 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
10641 case CHELSIO_T4_GET_I2C:
10642 rc = read_i2c(sc, (struct t4_i2c_data *)data);
10644 case CHELSIO_T4_CLEAR_STATS:
10645 rc = clear_stats(sc, *(uint32_t *)data);
10647 case CHELSIO_T4_SCHED_CLASS:
10648 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
10650 case CHELSIO_T4_SCHED_QUEUE:
10651 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
10653 case CHELSIO_T4_GET_TRACER:
10654 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
10656 case CHELSIO_T4_SET_TRACER:
10657 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
10659 case CHELSIO_T4_LOAD_CFG:
10660 rc = load_cfg(sc, (struct t4_data *)data);
10662 case CHELSIO_T4_LOAD_BOOT:
10663 rc = load_boot(sc, (struct t4_bootrom *)data);
10665 case CHELSIO_T4_LOAD_BOOTCFG:
10666 rc = load_bootcfg(sc, (struct t4_data *)data);
10668 case CHELSIO_T4_CUDBG_DUMP:
10669 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
10671 case CHELSIO_T4_SET_OFLD_POLICY:
10672 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
10683 toe_capability(struct vi_info *vi, int enable)
10686 struct port_info *pi = vi->pi;
10687 struct adapter *sc = pi->adapter;
10689 ASSERT_SYNCHRONIZED_OP(sc);
10691 if (!is_offload(sc))
10695 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
10696 /* TOE is already enabled. */
10701 * We need the port's queues around so that we're able to send
10702 * and receive CPLs to/from the TOE even if the ifnet for this
10703 * port has never been UP'd administratively.
10705 if (!(vi->flags & VI_INIT_DONE)) {
10706 rc = vi_full_init(vi);
10710 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
10711 rc = vi_full_init(&pi->vi[0]);
10716 if (isset(&sc->offload_map, pi->port_id)) {
10717 /* TOE is enabled on another VI of this port. */
10722 if (!uld_active(sc, ULD_TOM)) {
10723 rc = t4_activate_uld(sc, ULD_TOM);
10724 if (rc == EAGAIN) {
10726 "You must kldload t4_tom.ko before trying "
10727 "to enable TOE on a cxgbe interface.\n");
10731 KASSERT(sc->tom_softc != NULL,
10732 ("%s: TOM activated but softc NULL", __func__));
10733 KASSERT(uld_active(sc, ULD_TOM),
10734 ("%s: TOM activated but flag not set", __func__));
10737 /* Activate iWARP and iSCSI too, if the modules are loaded. */
10738 if (!uld_active(sc, ULD_IWARP))
10739 (void) t4_activate_uld(sc, ULD_IWARP);
10740 if (!uld_active(sc, ULD_ISCSI))
10741 (void) t4_activate_uld(sc, ULD_ISCSI);
10744 setbit(&sc->offload_map, pi->port_id);
10748 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
10751 KASSERT(uld_active(sc, ULD_TOM),
10752 ("%s: TOM never initialized?", __func__));
10753 clrbit(&sc->offload_map, pi->port_id);
10760 * Add an upper layer driver to the global list.
10763 t4_register_uld(struct uld_info *ui)
10766 struct uld_info *u;
10768 sx_xlock(&t4_uld_list_lock);
10769 SLIST_FOREACH(u, &t4_uld_list, link) {
10770 if (u->uld_id == ui->uld_id) {
10776 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
10779 sx_xunlock(&t4_uld_list_lock);
10784 t4_unregister_uld(struct uld_info *ui)
10787 struct uld_info *u;
10789 sx_xlock(&t4_uld_list_lock);
10791 SLIST_FOREACH(u, &t4_uld_list, link) {
10793 if (ui->refcount > 0) {
10798 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10804 sx_xunlock(&t4_uld_list_lock);
10809 t4_activate_uld(struct adapter *sc, int id)
10812 struct uld_info *ui;
10814 ASSERT_SYNCHRONIZED_OP(sc);
10816 if (id < 0 || id > ULD_MAX)
10818 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10820 sx_slock(&t4_uld_list_lock);
10822 SLIST_FOREACH(ui, &t4_uld_list, link) {
10823 if (ui->uld_id == id) {
10824 if (!(sc->flags & FULL_INIT_DONE)) {
10825 rc = adapter_full_init(sc);
10830 rc = ui->activate(sc);
10832 setbit(&sc->active_ulds, id);
10839 sx_sunlock(&t4_uld_list_lock);
10845 t4_deactivate_uld(struct adapter *sc, int id)
10848 struct uld_info *ui;
10850 ASSERT_SYNCHRONIZED_OP(sc);
10852 if (id < 0 || id > ULD_MAX)
10856 sx_slock(&t4_uld_list_lock);
10858 SLIST_FOREACH(ui, &t4_uld_list, link) {
10859 if (ui->uld_id == id) {
10860 rc = ui->deactivate(sc);
10862 clrbit(&sc->active_ulds, id);
10869 sx_sunlock(&t4_uld_list_lock);
10875 t4_async_event(void *arg, int n)
10877 struct uld_info *ui;
10878 struct adapter *sc = (struct adapter *)arg;
10880 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4async") != 0)
10882 sx_slock(&t4_uld_list_lock);
10883 SLIST_FOREACH(ui, &t4_uld_list, link) {
10884 if (ui->uld_id == ULD_IWARP) {
10885 ui->async_event(sc);
10889 sx_sunlock(&t4_uld_list_lock);
10890 end_synchronized_op(sc, 0);
10894 uld_active(struct adapter *sc, int uld_id)
10897 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10899 return (isset(&sc->active_ulds, uld_id));
10904 * t = ptr to tunable.
10905 * nc = number of CPUs.
10906 * c = compiled in default for that tunable.
10909 calculate_nqueues(int *t, int nc, const int c)
10915 nq = *t < 0 ? -*t : c;
10920 * Come up with reasonable defaults for some of the tunables, provided they're
10921 * not set by the user (in which case we'll use the values as is).
10924 tweak_tunables(void)
10926 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10930 t4_ntxq = rss_getnumbuckets();
10932 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10936 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10940 t4_nrxq = rss_getnumbuckets();
10942 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10946 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10948 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10949 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10950 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10953 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10954 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10957 #if defined(TCP_OFFLOAD) || defined(KERN_TLS)
10958 if (t4_toecaps_allowed == -1)
10959 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10961 if (t4_toecaps_allowed == -1)
10962 t4_toecaps_allowed = 0;
10966 if (t4_rdmacaps_allowed == -1) {
10967 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10968 FW_CAPS_CONFIG_RDMA_RDMAC;
10971 if (t4_iscsicaps_allowed == -1) {
10972 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10973 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10974 FW_CAPS_CONFIG_ISCSI_T10DIF;
10977 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10978 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10980 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10981 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10983 if (t4_rdmacaps_allowed == -1)
10984 t4_rdmacaps_allowed = 0;
10986 if (t4_iscsicaps_allowed == -1)
10987 t4_iscsicaps_allowed = 0;
10991 calculate_nqueues(&t4_nnmtxq, nc, NNMTXQ);
10992 calculate_nqueues(&t4_nnmrxq, nc, NNMRXQ);
10993 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10994 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10997 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10998 t4_tmr_idx = TMR_IDX;
11000 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
11001 t4_pktc_idx = PKTC_IDX;
11003 if (t4_qsize_txq < 128)
11004 t4_qsize_txq = 128;
11006 if (t4_qsize_rxq < 128)
11007 t4_qsize_rxq = 128;
11008 while (t4_qsize_rxq & 7)
11011 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
11014 * Number of VIs to create per-port. The first VI is the "main" regular
11015 * VI for the port. The rest are additional virtual interfaces on the
11016 * same physical port. Note that the main VI does not have native
11017 * netmap support but the extra VIs do.
11019 * Limit the number of VIs per port to the number of available
11020 * MAC addresses per port.
11022 if (t4_num_vis < 1)
11024 if (t4_num_vis > nitems(vi_mac_funcs)) {
11025 t4_num_vis = nitems(vi_mac_funcs);
11026 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
11029 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
11030 pcie_relaxed_ordering = 1;
11031 #if defined(__i386__) || defined(__amd64__)
11032 if (cpu_vendor_id == CPU_VENDOR_INTEL)
11033 pcie_relaxed_ordering = 0;
11040 t4_dump_tcb(struct adapter *sc, int tid)
11042 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
11044 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
11045 save = t4_read_reg(sc, reg);
11046 base = sc->memwin[2].mw_base;
11048 /* Dump TCB for the tid */
11049 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
11050 tcb_addr += tid * TCB_SIZE;
11054 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
11056 pf = V_PFNUM(sc->pf);
11057 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
11059 t4_write_reg(sc, reg, win_pos | pf);
11060 t4_read_reg(sc, reg);
11062 off = tcb_addr - win_pos;
11063 for (i = 0; i < 4; i++) {
11065 for (j = 0; j < 8; j++, off += 4)
11066 buf[j] = htonl(t4_read_reg(sc, base + off));
11068 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
11069 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
11073 t4_write_reg(sc, reg, save);
11074 t4_read_reg(sc, reg);
11078 t4_dump_devlog(struct adapter *sc)
11080 struct devlog_params *dparams = &sc->params.devlog;
11081 struct fw_devlog_e e;
11082 int i, first, j, m, nentries, rc;
11083 uint64_t ftstamp = UINT64_MAX;
11085 if (dparams->start == 0) {
11086 db_printf("devlog params not valid\n");
11090 nentries = dparams->size / sizeof(struct fw_devlog_e);
11091 m = fwmtype_to_hwmtype(dparams->memtype);
11093 /* Find the first entry. */
11095 for (i = 0; i < nentries && !db_pager_quit; i++) {
11096 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
11097 sizeof(e), (void *)&e);
11101 if (e.timestamp == 0)
11104 e.timestamp = be64toh(e.timestamp);
11105 if (e.timestamp < ftstamp) {
11106 ftstamp = e.timestamp;
11116 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
11117 sizeof(e), (void *)&e);
11121 if (e.timestamp == 0)
11124 e.timestamp = be64toh(e.timestamp);
11125 e.seqno = be32toh(e.seqno);
11126 for (j = 0; j < 8; j++)
11127 e.params[j] = be32toh(e.params[j]);
11129 db_printf("%10d %15ju %8s %8s ",
11130 e.seqno, e.timestamp,
11131 (e.level < nitems(devlog_level_strings) ?
11132 devlog_level_strings[e.level] : "UNKNOWN"),
11133 (e.facility < nitems(devlog_facility_strings) ?
11134 devlog_facility_strings[e.facility] : "UNKNOWN"));
11135 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
11136 e.params[3], e.params[4], e.params[5], e.params[6],
11139 if (++i == nentries)
11141 } while (i != first && !db_pager_quit);
11144 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
11145 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
11147 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
11154 t = db_read_token();
11156 dev = device_lookup_by_name(db_tok_string);
11161 db_printf("usage: show t4 devlog <nexus>\n");
11166 db_printf("device not found\n");
11170 t4_dump_devlog(device_get_softc(dev));
11173 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
11182 t = db_read_token();
11184 dev = device_lookup_by_name(db_tok_string);
11185 t = db_read_token();
11186 if (t == tNUMBER) {
11187 tid = db_tok_number;
11194 db_printf("usage: show t4 tcb <nexus> <tid>\n");
11199 db_printf("device not found\n");
11203 db_printf("invalid tid\n");
11207 t4_dump_tcb(device_get_softc(dev), tid);
11211 static struct sx mlu; /* mod load unload */
11212 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
11215 mod_event(module_t mod, int cmd, void *arg)
11218 static int loaded = 0;
11223 if (loaded++ == 0) {
11225 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
11226 t4_filter_rpl, CPL_COOKIE_FILTER);
11227 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
11228 do_l2t_write_rpl, CPL_COOKIE_FILTER);
11229 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
11230 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
11231 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
11232 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
11233 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
11234 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
11235 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
11236 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
11237 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
11239 sx_init(&t4_list_lock, "T4/T5 adapters");
11240 SLIST_INIT(&t4_list);
11241 callout_init(&fatal_callout, 1);
11243 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
11244 SLIST_INIT(&t4_uld_list);
11252 t4_tracer_modload();
11260 if (--loaded == 0) {
11263 sx_slock(&t4_list_lock);
11264 if (!SLIST_EMPTY(&t4_list)) {
11266 sx_sunlock(&t4_list_lock);
11270 sx_slock(&t4_uld_list_lock);
11271 if (!SLIST_EMPTY(&t4_uld_list)) {
11273 sx_sunlock(&t4_uld_list_lock);
11274 sx_sunlock(&t4_list_lock);
11279 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
11280 uprintf("%ju clusters with custom free routine "
11281 "still is use.\n", t4_sge_extfree_refs());
11282 pause("t4unload", 2 * hz);
11285 sx_sunlock(&t4_uld_list_lock);
11287 sx_sunlock(&t4_list_lock);
11289 if (t4_sge_extfree_refs() == 0) {
11290 t4_tracer_modunload();
11292 t6_ktls_modunload();
11295 t4_clip_modunload();
11298 sx_destroy(&t4_uld_list_lock);
11300 sx_destroy(&t4_list_lock);
11301 t4_sge_modunload();
11305 loaded++; /* undo earlier decrement */
11316 static devclass_t t4_devclass, t5_devclass, t6_devclass;
11317 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
11318 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
11320 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
11321 MODULE_VERSION(t4nex, 1);
11322 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
11324 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
11325 #endif /* DEV_NETMAP */
11327 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
11328 MODULE_VERSION(t5nex, 1);
11329 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
11331 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
11332 #endif /* DEV_NETMAP */
11334 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
11335 MODULE_VERSION(t6nex, 1);
11336 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
11338 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
11339 #endif /* DEV_NETMAP */
11341 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
11342 MODULE_VERSION(cxgbe, 1);
11344 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
11345 MODULE_VERSION(cxl, 1);
11347 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
11348 MODULE_VERSION(cc, 1);
11350 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
11351 MODULE_VERSION(vcxgbe, 1);
11353 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
11354 MODULE_VERSION(vcxl, 1);
11356 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
11357 MODULE_VERSION(vcc, 1);