2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include "opt_inet6.h"
36 #include "opt_ratelimit.h"
39 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
48 #include <sys/pciio.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pci_private.h>
52 #include <sys/firmware.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <net/ethernet.h>
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/if_vlan_var.h>
64 #include <net/rss_config.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #if defined(__i386__) || defined(__amd64__)
69 #include <machine/md_var.h>
70 #include <machine/cputypes.h>
74 #include <crypto/rijndael/rijndael.h>
77 #include <ddb/db_lex.h>
80 #include "common/common.h"
81 #include "common/t4_msg.h"
82 #include "common/t4_regs.h"
83 #include "common/t4_regs_values.h"
84 #include "cudbg/cudbg.h"
87 #include "t4_mp_ring.h"
91 /* T4 bus driver interface */
92 static int t4_probe(device_t);
93 static int t4_attach(device_t);
94 static int t4_detach(device_t);
95 static int t4_child_location_str(device_t, device_t, char *, size_t);
96 static int t4_ready(device_t);
97 static int t4_read_port_device(device_t, int, device_t *);
98 static device_method_t t4_methods[] = {
99 DEVMETHOD(device_probe, t4_probe),
100 DEVMETHOD(device_attach, t4_attach),
101 DEVMETHOD(device_detach, t4_detach),
103 DEVMETHOD(bus_child_location_str, t4_child_location_str),
105 DEVMETHOD(t4_is_main_ready, t4_ready),
106 DEVMETHOD(t4_read_port_device, t4_read_port_device),
110 static driver_t t4_driver = {
113 sizeof(struct adapter)
117 /* T4 port (cxgbe) interface */
118 static int cxgbe_probe(device_t);
119 static int cxgbe_attach(device_t);
120 static int cxgbe_detach(device_t);
121 device_method_t cxgbe_methods[] = {
122 DEVMETHOD(device_probe, cxgbe_probe),
123 DEVMETHOD(device_attach, cxgbe_attach),
124 DEVMETHOD(device_detach, cxgbe_detach),
127 static driver_t cxgbe_driver = {
130 sizeof(struct port_info)
133 /* T4 VI (vcxgbe) interface */
134 static int vcxgbe_probe(device_t);
135 static int vcxgbe_attach(device_t);
136 static int vcxgbe_detach(device_t);
137 static device_method_t vcxgbe_methods[] = {
138 DEVMETHOD(device_probe, vcxgbe_probe),
139 DEVMETHOD(device_attach, vcxgbe_attach),
140 DEVMETHOD(device_detach, vcxgbe_detach),
143 static driver_t vcxgbe_driver = {
146 sizeof(struct vi_info)
149 static d_ioctl_t t4_ioctl;
151 static struct cdevsw t4_cdevsw = {
152 .d_version = D_VERSION,
157 /* T5 bus driver interface */
158 static int t5_probe(device_t);
159 static device_method_t t5_methods[] = {
160 DEVMETHOD(device_probe, t5_probe),
161 DEVMETHOD(device_attach, t4_attach),
162 DEVMETHOD(device_detach, t4_detach),
164 DEVMETHOD(bus_child_location_str, t4_child_location_str),
166 DEVMETHOD(t4_is_main_ready, t4_ready),
167 DEVMETHOD(t4_read_port_device, t4_read_port_device),
171 static driver_t t5_driver = {
174 sizeof(struct adapter)
178 /* T5 port (cxl) interface */
179 static driver_t cxl_driver = {
182 sizeof(struct port_info)
185 /* T5 VI (vcxl) interface */
186 static driver_t vcxl_driver = {
189 sizeof(struct vi_info)
192 /* T6 bus driver interface */
193 static int t6_probe(device_t);
194 static device_method_t t6_methods[] = {
195 DEVMETHOD(device_probe, t6_probe),
196 DEVMETHOD(device_attach, t4_attach),
197 DEVMETHOD(device_detach, t4_detach),
199 DEVMETHOD(bus_child_location_str, t4_child_location_str),
201 DEVMETHOD(t4_is_main_ready, t4_ready),
202 DEVMETHOD(t4_read_port_device, t4_read_port_device),
206 static driver_t t6_driver = {
209 sizeof(struct adapter)
213 /* T6 port (cc) interface */
214 static driver_t cc_driver = {
217 sizeof(struct port_info)
220 /* T6 VI (vcc) interface */
221 static driver_t vcc_driver = {
224 sizeof(struct vi_info)
227 /* ifnet interface */
228 static void cxgbe_init(void *);
229 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
230 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
231 static void cxgbe_qflush(struct ifnet *);
233 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
236 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
237 * then ADAPTER_LOCK, then t4_uld_list_lock.
239 static struct sx t4_list_lock;
240 SLIST_HEAD(, adapter) t4_list;
242 static struct sx t4_uld_list_lock;
243 SLIST_HEAD(, uld_info) t4_uld_list;
247 * Tunables. See tweak_tunables() too.
249 * Each tunable is set to a default value here if it's known at compile-time.
250 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
251 * provide a reasonable default (upto n) when the driver is loaded.
253 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
254 * T5 are under hw.cxl.
258 * Number of queues for tx and rx, NIC and offload.
262 TUNABLE_INT("hw.cxgbe.ntxq", &t4_ntxq);
263 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */
267 TUNABLE_INT("hw.cxgbe.nrxq", &t4_nrxq);
268 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */
271 static int t4_ntxq_vi = -NTXQ_VI;
272 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
275 static int t4_nrxq_vi = -NRXQ_VI;
276 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
278 static int t4_rsrv_noflowq = 0;
279 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
281 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
283 static int t4_nofldtxq = -NOFLDTXQ;
284 TUNABLE_INT("hw.cxgbe.nofldtxq", &t4_nofldtxq);
287 static int t4_nofldrxq = -NOFLDRXQ;
288 TUNABLE_INT("hw.cxgbe.nofldrxq", &t4_nofldrxq);
290 #define NOFLDTXQ_VI 1
291 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
292 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
294 #define NOFLDRXQ_VI 1
295 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
296 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
298 #define TMR_IDX_OFLD 1
299 int t4_tmr_idx_ofld = TMR_IDX_OFLD;
300 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_ofld", &t4_tmr_idx_ofld);
302 #define PKTC_IDX_OFLD (-1)
303 int t4_pktc_idx_ofld = PKTC_IDX_OFLD;
304 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_ofld", &t4_pktc_idx_ofld);
306 /* 0 means chip/fw default, non-zero number is value in microseconds */
307 static u_long t4_toe_keepalive_idle = 0;
308 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_idle", &t4_toe_keepalive_idle);
310 /* 0 means chip/fw default, non-zero number is value in microseconds */
311 static u_long t4_toe_keepalive_interval = 0;
312 TUNABLE_ULONG("hw.cxgbe.toe.keepalive_interval", &t4_toe_keepalive_interval);
314 /* 0 means chip/fw default, non-zero number is # of keepalives before abort */
315 static int t4_toe_keepalive_count = 0;
316 TUNABLE_INT("hw.cxgbe.toe.keepalive_count", &t4_toe_keepalive_count);
318 /* 0 means chip/fw default, non-zero number is value in microseconds */
319 static u_long t4_toe_rexmt_min = 0;
320 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_min", &t4_toe_rexmt_min);
322 /* 0 means chip/fw default, non-zero number is value in microseconds */
323 static u_long t4_toe_rexmt_max = 0;
324 TUNABLE_ULONG("hw.cxgbe.toe.rexmt_max", &t4_toe_rexmt_max);
326 /* 0 means chip/fw default, non-zero number is # of rexmt before abort */
327 static int t4_toe_rexmt_count = 0;
328 TUNABLE_INT("hw.cxgbe.toe.rexmt_count", &t4_toe_rexmt_count);
330 /* -1 means chip/fw default, other values are raw backoff values to use */
331 static int t4_toe_rexmt_backoff[16] = {
332 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
334 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.0", &t4_toe_rexmt_backoff[0]);
335 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.1", &t4_toe_rexmt_backoff[1]);
336 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.2", &t4_toe_rexmt_backoff[2]);
337 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.3", &t4_toe_rexmt_backoff[3]);
338 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.4", &t4_toe_rexmt_backoff[4]);
339 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.5", &t4_toe_rexmt_backoff[5]);
340 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.6", &t4_toe_rexmt_backoff[6]);
341 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.7", &t4_toe_rexmt_backoff[7]);
342 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.8", &t4_toe_rexmt_backoff[8]);
343 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.9", &t4_toe_rexmt_backoff[9]);
344 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.10", &t4_toe_rexmt_backoff[10]);
345 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.11", &t4_toe_rexmt_backoff[11]);
346 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.12", &t4_toe_rexmt_backoff[12]);
347 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.13", &t4_toe_rexmt_backoff[13]);
348 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.14", &t4_toe_rexmt_backoff[14]);
349 TUNABLE_INT("hw.cxgbe.toe.rexmt_backoff.15", &t4_toe_rexmt_backoff[15]);
354 static int t4_nnmtxq_vi = -NNMTXQ_VI;
355 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
358 static int t4_nnmrxq_vi = -NNMRXQ_VI;
359 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
363 * Holdoff parameters for ports.
366 int t4_tmr_idx = TMR_IDX;
367 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx", &t4_tmr_idx);
368 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */
370 #define PKTC_IDX (-1)
371 int t4_pktc_idx = PKTC_IDX;
372 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx", &t4_pktc_idx);
373 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */
376 * Size (# of entries) of each tx and rx queue.
378 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
379 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
381 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
382 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
385 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
387 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
388 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
391 * Configuration file. All the _CF names here are special.
393 #define DEFAULT_CF "default"
394 #define BUILTIN_CF "built-in"
395 #define FLASH_CF "flash"
396 #define UWIRE_CF "uwire"
397 #define FPGA_CF "fpga"
398 static char t4_cfg_file[32] = DEFAULT_CF;
399 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
402 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively).
403 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
404 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
405 * mark or when signalled to do so, 0 to never emit PAUSE.
406 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the
407 * negotiated settings will override rx_pause/tx_pause.
408 * Otherwise rx_pause/tx_pause are applied forcibly.
410 static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG;
411 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
414 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively).
415 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5)
418 static int t4_fec = -1;
419 TUNABLE_INT("hw.cxgbe.fec", &t4_fec);
422 * Link autonegotiation.
423 * -1 to run with the firmware default.
427 static int t4_autoneg = -1;
428 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg);
431 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
432 * encouraged respectively).
434 static unsigned int t4_fw_install = 1;
435 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
438 * ASIC features that will be used. Disable the ones you don't want so that the
439 * chip resources aren't wasted on features that will not be used.
441 static int t4_nbmcaps_allowed = 0;
442 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
444 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
445 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
447 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
448 FW_CAPS_CONFIG_SWITCH_EGRESS;
449 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
452 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
453 FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
455 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
456 FW_CAPS_CONFIG_NIC_HASHFILTER;
458 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
460 static int t4_toecaps_allowed = -1;
461 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
463 static int t4_rdmacaps_allowed = -1;
464 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
466 static int t4_cryptocaps_allowed = -1;
467 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
469 static int t4_iscsicaps_allowed = -1;
470 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
472 static int t4_fcoecaps_allowed = 0;
473 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
475 static int t5_write_combine = 0;
476 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
478 static int t4_num_vis = 1;
479 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
481 * PCIe Relaxed Ordering.
482 * -1: driver should figure out a good value.
487 static int pcie_relaxed_ordering = -1;
488 TUNABLE_INT("hw.cxgbe.pcie_relaxed_ordering", &pcie_relaxed_ordering);
490 static int t4_panic_on_fatal_err = 0;
491 TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err);
497 static int t4_cop_managed_offloading = 0;
498 TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading);
501 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
502 static int vi_mac_funcs[] = {
506 FW_VI_FUNC_OPENISCSI,
512 struct intrs_and_queues {
513 uint16_t intr_type; /* INTx, MSI, or MSI-X */
514 uint16_t num_vis; /* number of VIs for each port */
515 uint16_t nirq; /* Total # of vectors */
516 uint16_t ntxq; /* # of NIC txq's for each port */
517 uint16_t nrxq; /* # of NIC rxq's for each port */
518 uint16_t nofldtxq; /* # of TOE/ETHOFLD txq's for each port */
519 uint16_t nofldrxq; /* # of TOE rxq's for each port */
521 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
522 uint16_t ntxq_vi; /* # of NIC txq's */
523 uint16_t nrxq_vi; /* # of NIC rxq's */
524 uint16_t nofldtxq_vi; /* # of TOE txq's */
525 uint16_t nofldrxq_vi; /* # of TOE rxq's */
526 uint16_t nnmtxq_vi; /* # of netmap txq's */
527 uint16_t nnmrxq_vi; /* # of netmap rxq's */
530 static void setup_memwin(struct adapter *);
531 static void position_memwin(struct adapter *, int, uint32_t);
532 static int validate_mem_range(struct adapter *, uint32_t, uint32_t);
533 static int fwmtype_to_hwmtype(int);
534 static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t,
536 static int fixup_devlog_params(struct adapter *);
537 static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *);
538 static int prep_firmware(struct adapter *);
539 static int partition_resources(struct adapter *, const struct firmware *,
541 static int get_params__pre_init(struct adapter *);
542 static int get_params__post_init(struct adapter *);
543 static int set_params__post_init(struct adapter *);
544 static void t4_set_desc(struct adapter *);
545 static bool fixed_ifmedia(struct port_info *);
546 static void build_medialist(struct port_info *);
547 static void init_link_config(struct port_info *);
548 static int fixup_link_config(struct port_info *);
549 static int apply_link_config(struct port_info *);
550 static int cxgbe_init_synchronized(struct vi_info *);
551 static int cxgbe_uninit_synchronized(struct vi_info *);
552 static void quiesce_txq(struct adapter *, struct sge_txq *);
553 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
554 static void quiesce_iq(struct adapter *, struct sge_iq *);
555 static void quiesce_fl(struct adapter *, struct sge_fl *);
556 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
557 driver_intr_t *, void *, char *);
558 static int t4_free_irq(struct adapter *, struct irq *);
559 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
560 static void vi_refresh_stats(struct adapter *, struct vi_info *);
561 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
562 static void cxgbe_tick(void *);
563 static void cxgbe_sysctls(struct port_info *);
564 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
565 static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS);
566 static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS);
567 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
568 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
569 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
570 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
571 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
572 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
573 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
574 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
575 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
576 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
577 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
578 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
579 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
580 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
581 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
582 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
583 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
584 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
585 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
586 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
587 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
588 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
589 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
590 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
591 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
592 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
593 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
594 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
595 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
596 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
597 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
598 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
599 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
600 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
601 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
602 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
603 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
604 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
605 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
606 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
607 static int sysctl_cpus(SYSCTL_HANDLER_ARGS);
609 static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS);
610 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
611 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
612 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
613 static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS);
614 static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
615 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
616 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
618 static int get_sge_context(struct adapter *, struct t4_sge_context *);
619 static int load_fw(struct adapter *, struct t4_data *);
620 static int load_cfg(struct adapter *, struct t4_data *);
621 static int load_boot(struct adapter *, struct t4_bootrom *);
622 static int load_bootcfg(struct adapter *, struct t4_data *);
623 static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *);
624 static void free_offload_policy(struct t4_offload_policy *);
625 static int set_offload_policy(struct adapter *, struct t4_offload_policy *);
626 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
627 static int read_i2c(struct adapter *, struct t4_i2c_data *);
629 static int toe_capability(struct vi_info *, int);
631 static int mod_event(module_t, int, void *);
632 static int notify_siblings(device_t, int);
638 {0xa000, "Chelsio Terminator 4 FPGA"},
639 {0x4400, "Chelsio T440-dbg"},
640 {0x4401, "Chelsio T420-CR"},
641 {0x4402, "Chelsio T422-CR"},
642 {0x4403, "Chelsio T440-CR"},
643 {0x4404, "Chelsio T420-BCH"},
644 {0x4405, "Chelsio T440-BCH"},
645 {0x4406, "Chelsio T440-CH"},
646 {0x4407, "Chelsio T420-SO"},
647 {0x4408, "Chelsio T420-CX"},
648 {0x4409, "Chelsio T420-BT"},
649 {0x440a, "Chelsio T404-BT"},
650 {0x440e, "Chelsio T440-LP-CR"},
652 {0xb000, "Chelsio Terminator 5 FPGA"},
653 {0x5400, "Chelsio T580-dbg"},
654 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
655 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
656 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
657 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
658 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
659 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
660 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
661 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
662 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
663 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
664 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
665 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
666 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
667 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
668 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
669 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
670 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
672 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
673 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
674 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
675 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
676 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
677 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
678 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
679 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
680 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
681 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
682 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
683 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
684 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
685 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
686 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
687 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
690 {0x6480, "Custom T6225-CR"},
691 {0x6481, "Custom T62100-CR"},
692 {0x6482, "Custom T6225-CR"},
693 {0x6483, "Custom T62100-CR"},
694 {0x6484, "Custom T64100-CR"},
695 {0x6485, "Custom T6240-SO"},
696 {0x6486, "Custom T6225-SO-CR"},
697 {0x6487, "Custom T6225-CR"},
702 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should
703 * be exactly the same for both rxq and ofld_rxq.
705 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
706 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
708 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
711 t4_probe(device_t dev)
714 uint16_t v = pci_get_vendor(dev);
715 uint16_t d = pci_get_device(dev);
716 uint8_t f = pci_get_function(dev);
718 if (v != PCI_VENDOR_ID_CHELSIO)
721 /* Attach only to PF0 of the FPGA */
722 if (d == 0xa000 && f != 0)
725 for (i = 0; i < nitems(t4_pciids); i++) {
726 if (d == t4_pciids[i].device) {
727 device_set_desc(dev, t4_pciids[i].desc);
728 return (BUS_PROBE_DEFAULT);
736 t5_probe(device_t dev)
739 uint16_t v = pci_get_vendor(dev);
740 uint16_t d = pci_get_device(dev);
741 uint8_t f = pci_get_function(dev);
743 if (v != PCI_VENDOR_ID_CHELSIO)
746 /* Attach only to PF0 of the FPGA */
747 if (d == 0xb000 && f != 0)
750 for (i = 0; i < nitems(t5_pciids); i++) {
751 if (d == t5_pciids[i].device) {
752 device_set_desc(dev, t5_pciids[i].desc);
753 return (BUS_PROBE_DEFAULT);
761 t6_probe(device_t dev)
764 uint16_t v = pci_get_vendor(dev);
765 uint16_t d = pci_get_device(dev);
767 if (v != PCI_VENDOR_ID_CHELSIO)
770 for (i = 0; i < nitems(t6_pciids); i++) {
771 if (d == t6_pciids[i].device) {
772 device_set_desc(dev, t6_pciids[i].desc);
773 return (BUS_PROBE_DEFAULT);
781 t5_attribute_workaround(device_t dev)
787 * The T5 chips do not properly echo the No Snoop and Relaxed
788 * Ordering attributes when replying to a TLP from a Root
789 * Port. As a workaround, find the parent Root Port and
790 * disable No Snoop and Relaxed Ordering. Note that this
791 * affects all devices under this root port.
793 root_port = pci_find_pcie_root_port(dev);
794 if (root_port == NULL) {
795 device_printf(dev, "Unable to find parent root port\n");
799 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
800 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
801 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
803 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
804 device_get_nameunit(root_port));
807 static const struct devnames devnames[] = {
809 .nexus_name = "t4nex",
810 .ifnet_name = "cxgbe",
811 .vi_ifnet_name = "vcxgbe",
812 .pf03_drv_name = "t4iov",
813 .vf_nexus_name = "t4vf",
814 .vf_ifnet_name = "cxgbev"
816 .nexus_name = "t5nex",
818 .vi_ifnet_name = "vcxl",
819 .pf03_drv_name = "t5iov",
820 .vf_nexus_name = "t5vf",
821 .vf_ifnet_name = "cxlv"
823 .nexus_name = "t6nex",
825 .vi_ifnet_name = "vcc",
826 .pf03_drv_name = "t6iov",
827 .vf_nexus_name = "t6vf",
828 .vf_ifnet_name = "ccv"
833 t4_init_devnames(struct adapter *sc)
838 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
839 sc->names = &devnames[id - CHELSIO_T4];
841 device_printf(sc->dev, "chip id %d is not supported.\n", id);
847 t4_ifnet_unit(struct adapter *sc, struct port_info *pi)
849 const char *parent, *name;
854 parent = device_get_nameunit(sc->dev);
855 name = sc->names->ifnet_name;
856 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) {
857 if (resource_long_value(name, unit, "port", &value) == 0 &&
858 value == pi->port_id)
865 t4_attach(device_t dev)
868 int rc = 0, i, j, rqidx, tqidx, nports;
869 struct make_dev_args mda;
870 struct intrs_and_queues iaq;
873 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
880 int nm_rqidx, nm_tqidx;
884 sc = device_get_softc(dev);
886 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
888 if ((pci_get_device(dev) & 0xff00) == 0x5400)
889 t5_attribute_workaround(dev);
890 pci_enable_busmaster(dev);
891 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
894 pci_set_max_read_req(dev, 4096);
895 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
896 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
897 if (pcie_relaxed_ordering == 0 &&
898 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
899 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
900 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
901 } else if (pcie_relaxed_ordering == 1 &&
902 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) {
903 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
904 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
908 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
909 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
911 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
912 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
913 device_get_nameunit(dev));
915 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
916 device_get_nameunit(dev));
917 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
920 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
921 TAILQ_INIT(&sc->sfl);
922 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
924 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
927 rw_init(&sc->policy_lock, "connection offload policy");
929 rc = t4_map_bars_0_and_4(sc);
931 goto done; /* error message displayed already */
933 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
935 /* Prepare the adapter for operation. */
936 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
937 rc = -t4_prep_adapter(sc, buf);
940 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
945 * This is the real PF# to which we're attaching. Works from within PCI
946 * passthrough environments too, where pci_get_function() could return a
947 * different PF# depending on the passthrough configuration. We need to
948 * use the real PF# in all our communication with the firmware.
950 j = t4_read_reg(sc, A_PL_WHOAMI);
951 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
954 t4_init_devnames(sc);
955 if (sc->names == NULL) {
957 goto done; /* error message displayed already */
961 * Do this really early, with the memory windows set up even before the
962 * character device. The userland tool's register i/o and mem read
963 * will work even in "recovery mode".
966 if (t4_init_devlog_params(sc, 0) == 0)
967 fixup_devlog_params(sc);
968 make_dev_args_init(&mda);
969 mda.mda_devsw = &t4_cdevsw;
970 mda.mda_uid = UID_ROOT;
971 mda.mda_gid = GID_WHEEL;
973 mda.mda_si_drv1 = sc;
974 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
976 device_printf(dev, "failed to create nexus char device: %d.\n",
979 /* Go no further if recovery mode has been requested. */
980 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
981 device_printf(dev, "recovery mode.\n");
985 #if defined(__i386__)
986 if ((cpu_feature & CPUID_CX8) == 0) {
987 device_printf(dev, "64 bit atomics not available.\n");
993 /* Prepare the firmware for operation */
994 rc = prep_firmware(sc);
996 goto done; /* error message displayed already */
998 rc = get_params__post_init(sc);
1000 goto done; /* error message displayed already */
1002 rc = set_params__post_init(sc);
1004 goto done; /* error message displayed already */
1006 rc = t4_map_bar_2(sc);
1008 goto done; /* error message displayed already */
1010 rc = t4_create_dma_tag(sc);
1012 goto done; /* error message displayed already */
1015 * First pass over all the ports - allocate VIs and initialize some
1016 * basic parameters like mac address, port type, etc.
1018 for_each_port(sc, i) {
1019 struct port_info *pi;
1021 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
1024 /* These must be set before t4_port_init */
1028 * XXX: vi[0] is special so we can't delay this allocation until
1029 * pi->nvi's final value is known.
1031 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE,
1035 * Allocate the "main" VI and initialize parameters
1038 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
1040 device_printf(dev, "unable to initialize port %d: %d\n",
1042 free(pi->vi, M_CXGBE);
1048 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
1049 device_get_nameunit(dev), i);
1050 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
1051 sc->chan_map[pi->tx_chan] = i;
1053 /* All VIs on this port share this media. */
1054 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1055 cxgbe_media_status);
1058 init_link_config(pi);
1059 fixup_link_config(pi);
1060 build_medialist(pi);
1061 if (fixed_ifmedia(pi))
1062 pi->flags |= FIXED_IFMEDIA;
1065 pi->dev = device_add_child(dev, sc->names->ifnet_name,
1066 t4_ifnet_unit(sc, pi));
1067 if (pi->dev == NULL) {
1069 "failed to add device for port %d.\n", i);
1073 pi->vi[0].dev = pi->dev;
1074 device_set_softc(pi->dev, pi);
1078 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1080 nports = sc->params.nports;
1081 rc = cfg_itype_and_nqueues(sc, &iaq);
1083 goto done; /* error message displayed already */
1085 num_vis = iaq.num_vis;
1086 sc->intr_type = iaq.intr_type;
1087 sc->intr_count = iaq.nirq;
1090 s->nrxq = nports * iaq.nrxq;
1091 s->ntxq = nports * iaq.ntxq;
1093 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1094 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1096 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1097 s->neq += nports; /* ctrl queues: 1 per port */
1098 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1099 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1100 if (is_offload(sc) || is_ethoffload(sc)) {
1101 s->nofldtxq = nports * iaq.nofldtxq;
1103 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1104 s->neq += s->nofldtxq;
1106 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1107 M_CXGBE, M_ZERO | M_WAITOK);
1111 if (is_offload(sc)) {
1112 s->nofldrxq = nports * iaq.nofldrxq;
1114 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1115 s->neq += s->nofldrxq; /* free list */
1116 s->niq += s->nofldrxq;
1118 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1119 M_CXGBE, M_ZERO | M_WAITOK);
1124 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi;
1125 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi;
1127 s->neq += s->nnmtxq + s->nnmrxq;
1128 s->niq += s->nnmrxq;
1130 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1131 M_CXGBE, M_ZERO | M_WAITOK);
1132 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1133 M_CXGBE, M_ZERO | M_WAITOK);
1136 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1138 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1140 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1142 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1144 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1147 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1150 t4_init_l2t(sc, M_WAITOK);
1151 t4_init_smt(sc, M_WAITOK);
1152 t4_init_tx_sched(sc);
1154 t4_init_etid_table(sc);
1156 if (sc->vres.key.size != 0)
1157 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
1158 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
1161 * Second pass over the ports. This time we know the number of rx and
1162 * tx queues that each port should get.
1165 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1172 nm_rqidx = nm_tqidx = 0;
1174 for_each_port(sc, i) {
1175 struct port_info *pi = sc->port[i];
1182 for_each_vi(pi, j, vi) {
1184 vi->qsize_rxq = t4_qsize_rxq;
1185 vi->qsize_txq = t4_qsize_txq;
1187 vi->first_rxq = rqidx;
1188 vi->first_txq = tqidx;
1189 vi->tmr_idx = t4_tmr_idx;
1190 vi->pktc_idx = t4_pktc_idx;
1191 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi;
1192 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi;
1197 if (j == 0 && vi->ntxq > 1)
1198 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0;
1200 vi->rsrv_noflowq = 0;
1202 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1203 vi->first_ofld_txq = ofld_tqidx;
1204 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi;
1205 ofld_tqidx += vi->nofldtxq;
1208 vi->ofld_tmr_idx = t4_tmr_idx_ofld;
1209 vi->ofld_pktc_idx = t4_pktc_idx_ofld;
1210 vi->first_ofld_rxq = ofld_rqidx;
1211 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi;
1213 ofld_rqidx += vi->nofldrxq;
1217 vi->first_nm_rxq = nm_rqidx;
1218 vi->first_nm_txq = nm_tqidx;
1219 vi->nnmrxq = iaq.nnmrxq_vi;
1220 vi->nnmtxq = iaq.nnmtxq_vi;
1221 nm_rqidx += vi->nnmrxq;
1222 nm_tqidx += vi->nnmtxq;
1228 rc = t4_setup_intr_handlers(sc);
1231 "failed to setup interrupt handlers: %d\n", rc);
1235 rc = bus_generic_probe(dev);
1237 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1242 * Ensure thread-safe mailbox access (in debug builds).
1244 * So far this was the only thread accessing the mailbox but various
1245 * ifnets and sysctls are about to be created and their handlers/ioctls
1246 * will access the mailbox from different threads.
1248 sc->flags |= CHK_MBOX_ACCESS;
1250 rc = bus_generic_attach(dev);
1253 "failed to attach all child ports: %d\n", rc);
1258 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1259 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1260 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1261 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1262 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1266 notify_siblings(dev, 0);
1269 if (rc != 0 && sc->cdev) {
1270 /* cdev was created and so cxgbetool works; recover that way. */
1272 "error during attach, adapter is now in recovery mode.\n");
1277 t4_detach_common(dev);
1285 t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen)
1287 struct port_info *pi;
1289 pi = device_get_softc(dev);
1290 snprintf(buf, buflen, "port=%d", pi->port_id);
1295 t4_ready(device_t dev)
1299 sc = device_get_softc(dev);
1300 if (sc->flags & FW_OK)
1306 t4_read_port_device(device_t dev, int port, device_t *child)
1309 struct port_info *pi;
1311 sc = device_get_softc(dev);
1312 if (port < 0 || port >= MAX_NPORTS)
1314 pi = sc->port[port];
1315 if (pi == NULL || pi->dev == NULL)
1322 notify_siblings(device_t dev, int detaching)
1328 for (i = 0; i < PCI_FUNCMAX; i++) {
1329 if (i == pci_get_function(dev))
1331 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1332 pci_get_slot(dev), i);
1333 if (sibling == NULL || !device_is_attached(sibling))
1336 error = T4_DETACH_CHILD(sibling);
1338 (void)T4_ATTACH_CHILD(sibling);
1349 t4_detach(device_t dev)
1354 sc = device_get_softc(dev);
1356 rc = notify_siblings(dev, 1);
1359 "failed to detach sibling devices: %d\n", rc);
1363 return (t4_detach_common(dev));
1367 t4_detach_common(device_t dev)
1370 struct port_info *pi;
1373 sc = device_get_softc(dev);
1376 destroy_dev(sc->cdev);
1380 sc->flags &= ~CHK_MBOX_ACCESS;
1381 if (sc->flags & FULL_INIT_DONE) {
1382 if (!(sc->flags & IS_VF))
1383 t4_intr_disable(sc);
1386 if (device_is_attached(dev)) {
1387 rc = bus_generic_detach(dev);
1390 "failed to detach child devices: %d\n", rc);
1395 for (i = 0; i < sc->intr_count; i++)
1396 t4_free_irq(sc, &sc->irq[i]);
1398 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1399 t4_free_tx_sched(sc);
1401 for (i = 0; i < MAX_NPORTS; i++) {
1404 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1406 device_delete_child(dev, pi->dev);
1408 mtx_destroy(&pi->pi_lock);
1409 free(pi->vi, M_CXGBE);
1414 device_delete_children(dev);
1416 if (sc->flags & FULL_INIT_DONE)
1417 adapter_full_uninit(sc);
1419 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1420 t4_fw_bye(sc, sc->mbox);
1422 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1423 pci_release_msi(dev);
1426 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1430 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1434 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1438 t4_free_l2t(sc->l2t);
1440 t4_free_smt(sc->smt);
1442 t4_free_etid_table(sc);
1445 vmem_destroy(sc->key_map);
1447 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1448 free(sc->sge.ofld_txq, M_CXGBE);
1451 free(sc->sge.ofld_rxq, M_CXGBE);
1454 free(sc->sge.nm_rxq, M_CXGBE);
1455 free(sc->sge.nm_txq, M_CXGBE);
1457 free(sc->irq, M_CXGBE);
1458 free(sc->sge.rxq, M_CXGBE);
1459 free(sc->sge.txq, M_CXGBE);
1460 free(sc->sge.ctrlq, M_CXGBE);
1461 free(sc->sge.iqmap, M_CXGBE);
1462 free(sc->sge.eqmap, M_CXGBE);
1463 free(sc->tids.ftid_tab, M_CXGBE);
1464 free(sc->tids.hpftid_tab, M_CXGBE);
1465 free_hftid_hash(&sc->tids);
1466 free(sc->tids.atid_tab, M_CXGBE);
1467 free(sc->tids.tid_tab, M_CXGBE);
1468 free(sc->tt.tls_rx_ports, M_CXGBE);
1469 t4_destroy_dma_tag(sc);
1470 if (mtx_initialized(&sc->sc_lock)) {
1471 sx_xlock(&t4_list_lock);
1472 SLIST_REMOVE(&t4_list, sc, adapter, link);
1473 sx_xunlock(&t4_list_lock);
1474 mtx_destroy(&sc->sc_lock);
1477 callout_drain(&sc->sfl_callout);
1478 if (mtx_initialized(&sc->tids.ftid_lock)) {
1479 mtx_destroy(&sc->tids.ftid_lock);
1480 cv_destroy(&sc->tids.ftid_cv);
1482 if (mtx_initialized(&sc->tids.atid_lock))
1483 mtx_destroy(&sc->tids.atid_lock);
1484 if (mtx_initialized(&sc->sfl_lock))
1485 mtx_destroy(&sc->sfl_lock);
1486 if (mtx_initialized(&sc->ifp_lock))
1487 mtx_destroy(&sc->ifp_lock);
1488 if (mtx_initialized(&sc->reg_lock))
1489 mtx_destroy(&sc->reg_lock);
1491 if (rw_initialized(&sc->policy_lock)) {
1492 rw_destroy(&sc->policy_lock);
1494 if (sc->policy != NULL)
1495 free_offload_policy(sc->policy);
1499 for (i = 0; i < NUM_MEMWIN; i++) {
1500 struct memwin *mw = &sc->memwin[i];
1502 if (rw_initialized(&mw->mw_lock))
1503 rw_destroy(&mw->mw_lock);
1506 bzero(sc, sizeof(*sc));
1512 cxgbe_probe(device_t dev)
1515 struct port_info *pi = device_get_softc(dev);
1517 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1518 device_set_desc_copy(dev, buf);
1520 return (BUS_PROBE_DEFAULT);
1523 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1524 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1525 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS | \
1527 #define T4_CAP_ENABLE (T4_CAP)
1530 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1535 vi->xact_addr_filt = -1;
1536 callout_init(&vi->tick, 1);
1538 /* Allocate an ifnet and set it up */
1539 ifp = if_alloc(IFT_ETHER);
1541 device_printf(dev, "Cannot allocate ifnet\n");
1547 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1548 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1550 ifp->if_init = cxgbe_init;
1551 ifp->if_ioctl = cxgbe_ioctl;
1552 ifp->if_transmit = cxgbe_transmit;
1553 ifp->if_qflush = cxgbe_qflush;
1554 ifp->if_get_counter = cxgbe_get_counter;
1556 ifp->if_snd_tag_alloc = cxgbe_snd_tag_alloc;
1557 ifp->if_snd_tag_modify = cxgbe_snd_tag_modify;
1558 ifp->if_snd_tag_query = cxgbe_snd_tag_query;
1559 ifp->if_snd_tag_free = cxgbe_snd_tag_free;
1562 ifp->if_capabilities = T4_CAP;
1563 ifp->if_capenable = T4_CAP_ENABLE;
1565 if (vi->nofldrxq != 0)
1566 ifp->if_capabilities |= IFCAP_TOE;
1569 if (vi->nnmrxq != 0)
1570 ifp->if_capabilities |= IFCAP_NETMAP;
1573 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0) {
1574 ifp->if_capabilities |= IFCAP_TXRTLMT;
1575 ifp->if_capenable |= IFCAP_TXRTLMT;
1578 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1579 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1581 ifp->if_hw_tsomax = IP_MAXPACKET;
1582 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_TSO;
1584 if (is_ethoffload(vi->pi->adapter) && vi->nofldtxq != 0)
1585 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS_EO_TSO;
1587 ifp->if_hw_tsomaxsegsize = 65536;
1589 ether_ifattach(ifp, vi->hw_addr);
1591 if (ifp->if_capabilities & IFCAP_NETMAP)
1592 cxgbe_nm_attach(vi);
1594 sb = sbuf_new_auto();
1595 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1596 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1597 switch (ifp->if_capabilities & (IFCAP_TOE | IFCAP_TXRTLMT)) {
1599 sbuf_printf(sb, "; %d txq (TOE)", vi->nofldtxq);
1601 case IFCAP_TOE | IFCAP_TXRTLMT:
1602 sbuf_printf(sb, "; %d txq (TOE/ETHOFLD)", vi->nofldtxq);
1605 sbuf_printf(sb, "; %d txq (ETHOFLD)", vi->nofldtxq);
1610 if (ifp->if_capabilities & IFCAP_TOE)
1611 sbuf_printf(sb, ", %d rxq (TOE)", vi->nofldrxq);
1614 if (ifp->if_capabilities & IFCAP_NETMAP)
1615 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1616 vi->nnmtxq, vi->nnmrxq);
1619 device_printf(dev, "%s\n", sbuf_data(sb));
1628 cxgbe_attach(device_t dev)
1630 struct port_info *pi = device_get_softc(dev);
1631 struct adapter *sc = pi->adapter;
1635 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1637 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1641 for_each_vi(pi, i, vi) {
1644 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1645 if (vi->dev == NULL) {
1646 device_printf(dev, "failed to add VI %d\n", i);
1649 device_set_softc(vi->dev, vi);
1654 bus_generic_attach(dev);
1660 cxgbe_vi_detach(struct vi_info *vi)
1662 struct ifnet *ifp = vi->ifp;
1664 ether_ifdetach(ifp);
1666 /* Let detach proceed even if these fail. */
1668 if (ifp->if_capabilities & IFCAP_NETMAP)
1669 cxgbe_nm_detach(vi);
1671 cxgbe_uninit_synchronized(vi);
1672 callout_drain(&vi->tick);
1680 cxgbe_detach(device_t dev)
1682 struct port_info *pi = device_get_softc(dev);
1683 struct adapter *sc = pi->adapter;
1686 /* Detach the extra VIs first. */
1687 rc = bus_generic_detach(dev);
1690 device_delete_children(dev);
1692 doom_vi(sc, &pi->vi[0]);
1694 if (pi->flags & HAS_TRACEQ) {
1695 sc->traceq = -1; /* cloner should not create ifnet */
1696 t4_tracer_port_detach(sc);
1699 cxgbe_vi_detach(&pi->vi[0]);
1700 callout_drain(&pi->tick);
1701 ifmedia_removeall(&pi->media);
1703 end_synchronized_op(sc, 0);
1709 cxgbe_init(void *arg)
1711 struct vi_info *vi = arg;
1712 struct adapter *sc = vi->pi->adapter;
1714 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1716 cxgbe_init_synchronized(vi);
1717 end_synchronized_op(sc, 0);
1721 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1723 int rc = 0, mtu, flags;
1724 struct vi_info *vi = ifp->if_softc;
1725 struct port_info *pi = vi->pi;
1726 struct adapter *sc = pi->adapter;
1727 struct ifreq *ifr = (struct ifreq *)data;
1733 if (mtu < ETHERMIN || mtu > MAX_MTU)
1736 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1740 if (vi->flags & VI_INIT_DONE) {
1741 t4_update_fl_bufsize(ifp);
1742 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1743 rc = update_mac_settings(ifp, XGMAC_MTU);
1745 end_synchronized_op(sc, 0);
1749 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4flg");
1753 if (ifp->if_flags & IFF_UP) {
1754 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1755 flags = vi->if_flags;
1756 if ((ifp->if_flags ^ flags) &
1757 (IFF_PROMISC | IFF_ALLMULTI)) {
1758 rc = update_mac_settings(ifp,
1759 XGMAC_PROMISC | XGMAC_ALLMULTI);
1762 rc = cxgbe_init_synchronized(vi);
1764 vi->if_flags = ifp->if_flags;
1765 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1766 rc = cxgbe_uninit_synchronized(vi);
1768 end_synchronized_op(sc, 0);
1773 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4multi");
1776 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1777 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1778 end_synchronized_op(sc, 0);
1782 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1786 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1787 if (mask & IFCAP_TXCSUM) {
1788 ifp->if_capenable ^= IFCAP_TXCSUM;
1789 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1791 if (IFCAP_TSO4 & ifp->if_capenable &&
1792 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1793 ifp->if_capenable &= ~IFCAP_TSO4;
1795 "tso4 disabled due to -txcsum.\n");
1798 if (mask & IFCAP_TXCSUM_IPV6) {
1799 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1800 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1802 if (IFCAP_TSO6 & ifp->if_capenable &&
1803 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1804 ifp->if_capenable &= ~IFCAP_TSO6;
1806 "tso6 disabled due to -txcsum6.\n");
1809 if (mask & IFCAP_RXCSUM)
1810 ifp->if_capenable ^= IFCAP_RXCSUM;
1811 if (mask & IFCAP_RXCSUM_IPV6)
1812 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1815 * Note that we leave CSUM_TSO alone (it is always set). The
1816 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1817 * sending a TSO request our way, so it's sufficient to toggle
1820 if (mask & IFCAP_TSO4) {
1821 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1822 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1823 if_printf(ifp, "enable txcsum first.\n");
1827 ifp->if_capenable ^= IFCAP_TSO4;
1829 if (mask & IFCAP_TSO6) {
1830 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1831 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1832 if_printf(ifp, "enable txcsum6 first.\n");
1836 ifp->if_capenable ^= IFCAP_TSO6;
1838 if (mask & IFCAP_LRO) {
1839 #if defined(INET) || defined(INET6)
1841 struct sge_rxq *rxq;
1843 ifp->if_capenable ^= IFCAP_LRO;
1844 for_each_rxq(vi, i, rxq) {
1845 if (ifp->if_capenable & IFCAP_LRO)
1846 rxq->iq.flags |= IQ_LRO_ENABLED;
1848 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1853 if (mask & IFCAP_TOE) {
1854 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1856 rc = toe_capability(vi, enable);
1860 ifp->if_capenable ^= mask;
1863 if (mask & IFCAP_VLAN_HWTAGGING) {
1864 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1865 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1866 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1868 if (mask & IFCAP_VLAN_MTU) {
1869 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1871 /* Need to find out how to disable auto-mtu-inflation */
1873 if (mask & IFCAP_VLAN_HWTSO)
1874 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1875 if (mask & IFCAP_VLAN_HWCSUM)
1876 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1878 if (mask & IFCAP_TXRTLMT)
1879 ifp->if_capenable ^= IFCAP_TXRTLMT;
1881 if (mask & IFCAP_HWRXTSTMP) {
1883 struct sge_rxq *rxq;
1885 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
1886 for_each_rxq(vi, i, rxq) {
1887 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
1888 rxq->iq.flags |= IQ_RX_TIMESTAMP;
1890 rxq->iq.flags &= ~IQ_RX_TIMESTAMP;
1894 #ifdef VLAN_CAPABILITIES
1895 VLAN_CAPABILITIES(ifp);
1898 end_synchronized_op(sc, 0);
1904 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1908 struct ifi2creq i2c;
1910 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
1913 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1917 if (i2c.len > sizeof(i2c.data)) {
1921 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1924 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1925 i2c.offset, i2c.len, &i2c.data[0]);
1926 end_synchronized_op(sc, 0);
1928 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
1933 rc = ether_ioctl(ifp, cmd, data);
1940 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1942 struct vi_info *vi = ifp->if_softc;
1943 struct port_info *pi = vi->pi;
1944 struct adapter *sc = pi->adapter;
1945 struct sge_txq *txq;
1950 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1952 if (__predict_false(pi->link_cfg.link_ok == false)) {
1957 rc = parse_pkt(sc, &m);
1958 if (__predict_false(rc != 0)) {
1959 MPASS(m == NULL); /* was freed already */
1960 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1964 if (m->m_pkthdr.snd_tag != NULL) {
1965 /* EAGAIN tells the stack we are not the correct interface. */
1966 if (__predict_false(ifp != m->m_pkthdr.snd_tag->ifp)) {
1971 return (ethofld_transmit(ifp, m));
1976 txq = &sc->sge.txq[vi->first_txq];
1977 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1978 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1982 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1983 if (__predict_false(rc != 0))
1990 cxgbe_qflush(struct ifnet *ifp)
1992 struct vi_info *vi = ifp->if_softc;
1993 struct sge_txq *txq;
1996 /* queues do not exist if !VI_INIT_DONE. */
1997 if (vi->flags & VI_INIT_DONE) {
1998 for_each_txq(vi, i, txq) {
2000 txq->eq.flags |= EQ_QFLUSH;
2002 while (!mp_ring_is_idle(txq->r)) {
2003 mp_ring_check_drainage(txq->r, 0);
2007 txq->eq.flags &= ~EQ_QFLUSH;
2015 vi_get_counter(struct ifnet *ifp, ift_counter c)
2017 struct vi_info *vi = ifp->if_softc;
2018 struct fw_vi_stats_vf *s = &vi->stats;
2020 vi_refresh_stats(vi->pi->adapter, vi);
2023 case IFCOUNTER_IPACKETS:
2024 return (s->rx_bcast_frames + s->rx_mcast_frames +
2025 s->rx_ucast_frames);
2026 case IFCOUNTER_IERRORS:
2027 return (s->rx_err_frames);
2028 case IFCOUNTER_OPACKETS:
2029 return (s->tx_bcast_frames + s->tx_mcast_frames +
2030 s->tx_ucast_frames + s->tx_offload_frames);
2031 case IFCOUNTER_OERRORS:
2032 return (s->tx_drop_frames);
2033 case IFCOUNTER_IBYTES:
2034 return (s->rx_bcast_bytes + s->rx_mcast_bytes +
2036 case IFCOUNTER_OBYTES:
2037 return (s->tx_bcast_bytes + s->tx_mcast_bytes +
2038 s->tx_ucast_bytes + s->tx_offload_bytes);
2039 case IFCOUNTER_IMCASTS:
2040 return (s->rx_mcast_frames);
2041 case IFCOUNTER_OMCASTS:
2042 return (s->tx_mcast_frames);
2043 case IFCOUNTER_OQDROPS: {
2047 if (vi->flags & VI_INIT_DONE) {
2049 struct sge_txq *txq;
2051 for_each_txq(vi, i, txq)
2052 drops += counter_u64_fetch(txq->r->drops);
2060 return (if_get_counter_default(ifp, c));
2065 cxgbe_get_counter(struct ifnet *ifp, ift_counter c)
2067 struct vi_info *vi = ifp->if_softc;
2068 struct port_info *pi = vi->pi;
2069 struct adapter *sc = pi->adapter;
2070 struct port_stats *s = &pi->stats;
2072 if (pi->nvi > 1 || sc->flags & IS_VF)
2073 return (vi_get_counter(ifp, c));
2075 cxgbe_refresh_stats(sc, pi);
2078 case IFCOUNTER_IPACKETS:
2079 return (s->rx_frames);
2081 case IFCOUNTER_IERRORS:
2082 return (s->rx_jabber + s->rx_runt + s->rx_too_long +
2083 s->rx_fcs_err + s->rx_len_err);
2085 case IFCOUNTER_OPACKETS:
2086 return (s->tx_frames);
2088 case IFCOUNTER_OERRORS:
2089 return (s->tx_error_frames);
2091 case IFCOUNTER_IBYTES:
2092 return (s->rx_octets);
2094 case IFCOUNTER_OBYTES:
2095 return (s->tx_octets);
2097 case IFCOUNTER_IMCASTS:
2098 return (s->rx_mcast_frames);
2100 case IFCOUNTER_OMCASTS:
2101 return (s->tx_mcast_frames);
2103 case IFCOUNTER_IQDROPS:
2104 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
2105 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
2106 s->rx_trunc3 + pi->tnl_cong_drops);
2108 case IFCOUNTER_OQDROPS: {
2112 if (vi->flags & VI_INIT_DONE) {
2114 struct sge_txq *txq;
2116 for_each_txq(vi, i, txq)
2117 drops += counter_u64_fetch(txq->r->drops);
2125 return (if_get_counter_default(ifp, c));
2130 * The kernel picks a media from the list we had provided but we still validate
2134 cxgbe_media_change(struct ifnet *ifp)
2136 struct vi_info *vi = ifp->if_softc;
2137 struct port_info *pi = vi->pi;
2138 struct ifmedia *ifm = &pi->media;
2139 struct link_config *lc = &pi->link_cfg;
2140 struct adapter *sc = pi->adapter;
2143 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
2147 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
2148 /* ifconfig .. media autoselect */
2149 if (!(lc->supported & FW_PORT_CAP32_ANEG)) {
2150 rc = ENOTSUP; /* AN not supported by transceiver */
2153 lc->requested_aneg = AUTONEG_ENABLE;
2154 lc->requested_speed = 0;
2155 lc->requested_fc |= PAUSE_AUTONEG;
2157 lc->requested_aneg = AUTONEG_DISABLE;
2158 lc->requested_speed =
2159 ifmedia_baudrate(ifm->ifm_media) / 1000000;
2160 lc->requested_fc = 0;
2161 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
2162 lc->requested_fc |= PAUSE_RX;
2163 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
2164 lc->requested_fc |= PAUSE_TX;
2166 if (pi->up_vis > 0) {
2167 fixup_link_config(pi);
2168 rc = apply_link_config(pi);
2172 end_synchronized_op(sc, 0);
2177 * Base media word (without ETHER, pause, link active, etc.) for the port at the
2181 port_mword(struct port_info *pi, uint32_t speed)
2184 MPASS(speed & M_FW_PORT_CAP32_SPEED);
2185 MPASS(powerof2(speed));
2187 switch(pi->port_type) {
2188 case FW_PORT_TYPE_BT_SGMII:
2189 case FW_PORT_TYPE_BT_XFI:
2190 case FW_PORT_TYPE_BT_XAUI:
2193 case FW_PORT_CAP32_SPEED_100M:
2195 case FW_PORT_CAP32_SPEED_1G:
2196 return (IFM_1000_T);
2197 case FW_PORT_CAP32_SPEED_10G:
2201 case FW_PORT_TYPE_KX4:
2202 if (speed == FW_PORT_CAP32_SPEED_10G)
2203 return (IFM_10G_KX4);
2205 case FW_PORT_TYPE_CX4:
2206 if (speed == FW_PORT_CAP32_SPEED_10G)
2207 return (IFM_10G_CX4);
2209 case FW_PORT_TYPE_KX:
2210 if (speed == FW_PORT_CAP32_SPEED_1G)
2211 return (IFM_1000_KX);
2213 case FW_PORT_TYPE_KR:
2214 case FW_PORT_TYPE_BP_AP:
2215 case FW_PORT_TYPE_BP4_AP:
2216 case FW_PORT_TYPE_BP40_BA:
2217 case FW_PORT_TYPE_KR4_100G:
2218 case FW_PORT_TYPE_KR_SFP28:
2219 case FW_PORT_TYPE_KR_XLAUI:
2221 case FW_PORT_CAP32_SPEED_1G:
2222 return (IFM_1000_KX);
2223 case FW_PORT_CAP32_SPEED_10G:
2224 return (IFM_10G_KR);
2225 case FW_PORT_CAP32_SPEED_25G:
2226 return (IFM_25G_KR);
2227 case FW_PORT_CAP32_SPEED_40G:
2228 return (IFM_40G_KR4);
2229 case FW_PORT_CAP32_SPEED_50G:
2230 return (IFM_50G_KR2);
2231 case FW_PORT_CAP32_SPEED_100G:
2232 return (IFM_100G_KR4);
2235 case FW_PORT_TYPE_FIBER_XFI:
2236 case FW_PORT_TYPE_FIBER_XAUI:
2237 case FW_PORT_TYPE_SFP:
2238 case FW_PORT_TYPE_QSFP_10G:
2239 case FW_PORT_TYPE_QSA:
2240 case FW_PORT_TYPE_QSFP:
2241 case FW_PORT_TYPE_CR4_QSFP:
2242 case FW_PORT_TYPE_CR_QSFP:
2243 case FW_PORT_TYPE_CR2_QSFP:
2244 case FW_PORT_TYPE_SFP28:
2245 /* Pluggable transceiver */
2246 switch (pi->mod_type) {
2247 case FW_PORT_MOD_TYPE_LR:
2249 case FW_PORT_CAP32_SPEED_1G:
2250 return (IFM_1000_LX);
2251 case FW_PORT_CAP32_SPEED_10G:
2252 return (IFM_10G_LR);
2253 case FW_PORT_CAP32_SPEED_25G:
2254 return (IFM_25G_LR);
2255 case FW_PORT_CAP32_SPEED_40G:
2256 return (IFM_40G_LR4);
2257 case FW_PORT_CAP32_SPEED_50G:
2258 return (IFM_50G_LR2);
2259 case FW_PORT_CAP32_SPEED_100G:
2260 return (IFM_100G_LR4);
2263 case FW_PORT_MOD_TYPE_SR:
2265 case FW_PORT_CAP32_SPEED_1G:
2266 return (IFM_1000_SX);
2267 case FW_PORT_CAP32_SPEED_10G:
2268 return (IFM_10G_SR);
2269 case FW_PORT_CAP32_SPEED_25G:
2270 return (IFM_25G_SR);
2271 case FW_PORT_CAP32_SPEED_40G:
2272 return (IFM_40G_SR4);
2273 case FW_PORT_CAP32_SPEED_50G:
2274 return (IFM_50G_SR2);
2275 case FW_PORT_CAP32_SPEED_100G:
2276 return (IFM_100G_SR4);
2279 case FW_PORT_MOD_TYPE_ER:
2280 if (speed == FW_PORT_CAP32_SPEED_10G)
2281 return (IFM_10G_ER);
2283 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2284 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2286 case FW_PORT_CAP32_SPEED_1G:
2287 return (IFM_1000_CX);
2288 case FW_PORT_CAP32_SPEED_10G:
2289 return (IFM_10G_TWINAX);
2290 case FW_PORT_CAP32_SPEED_25G:
2291 return (IFM_25G_CR);
2292 case FW_PORT_CAP32_SPEED_40G:
2293 return (IFM_40G_CR4);
2294 case FW_PORT_CAP32_SPEED_50G:
2295 return (IFM_50G_CR2);
2296 case FW_PORT_CAP32_SPEED_100G:
2297 return (IFM_100G_CR4);
2300 case FW_PORT_MOD_TYPE_LRM:
2301 if (speed == FW_PORT_CAP32_SPEED_10G)
2302 return (IFM_10G_LRM);
2304 case FW_PORT_MOD_TYPE_NA:
2305 MPASS(0); /* Not pluggable? */
2307 case FW_PORT_MOD_TYPE_ERROR:
2308 case FW_PORT_MOD_TYPE_UNKNOWN:
2309 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
2311 case FW_PORT_MOD_TYPE_NONE:
2315 case FW_PORT_TYPE_NONE:
2319 return (IFM_UNKNOWN);
2323 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2325 struct vi_info *vi = ifp->if_softc;
2326 struct port_info *pi = vi->pi;
2327 struct adapter *sc = pi->adapter;
2328 struct link_config *lc = &pi->link_cfg;
2330 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2334 if (pi->up_vis == 0) {
2336 * If all the interfaces are administratively down the firmware
2337 * does not report transceiver changes. Refresh port info here
2338 * so that ifconfig displays accurate ifmedia at all times.
2339 * This is the only reason we have a synchronized op in this
2340 * function. Just PORT_LOCK would have been enough otherwise.
2342 t4_update_port_info(pi);
2343 build_medialist(pi);
2347 ifmr->ifm_status = IFM_AVALID;
2348 if (lc->link_ok == false)
2350 ifmr->ifm_status |= IFM_ACTIVE;
2353 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2354 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2355 if (lc->fc & PAUSE_RX)
2356 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2357 if (lc->fc & PAUSE_TX)
2358 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2359 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed));
2362 end_synchronized_op(sc, 0);
2366 vcxgbe_probe(device_t dev)
2369 struct vi_info *vi = device_get_softc(dev);
2371 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2373 device_set_desc_copy(dev, buf);
2375 return (BUS_PROBE_DEFAULT);
2379 alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
2381 int func, index, rc;
2382 uint32_t param, val;
2384 ASSERT_SYNCHRONIZED_OP(sc);
2386 index = vi - pi->vi;
2387 MPASS(index > 0); /* This function deals with _extra_ VIs only */
2388 KASSERT(index < nitems(vi_mac_funcs),
2389 ("%s: VI %s doesn't have a MAC func", __func__,
2390 device_get_nameunit(vi->dev)));
2391 func = vi_mac_funcs[index];
2392 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2393 vi->hw_addr, &vi->rss_size, func, 0);
2395 device_printf(vi->dev, "failed to allocate virtual interface %d"
2396 "for port %d: %d\n", index, pi->port_id, -rc);
2400 if (chip_id(sc) <= CHELSIO_T5)
2401 vi->smt_idx = (rc & 0x7f) << 1;
2403 vi->smt_idx = (rc & 0x7f);
2405 if (vi->rss_size == 1) {
2407 * This VI didn't get a slice of the RSS table. Reduce the
2408 * number of VIs being created (hw.cxgbe.num_vis) or modify the
2409 * configuration file (nvi, rssnvi for this PF) if this is a
2412 device_printf(vi->dev, "RSS table not available.\n");
2413 vi->rss_base = 0xffff;
2418 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2419 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2420 V_FW_PARAMS_PARAM_YZ(vi->viid);
2421 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2423 vi->rss_base = 0xffff;
2425 MPASS((val >> 16) == vi->rss_size);
2426 vi->rss_base = val & 0xffff;
2433 vcxgbe_attach(device_t dev)
2436 struct port_info *pi;
2440 vi = device_get_softc(dev);
2444 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via");
2447 rc = alloc_extra_vi(sc, pi, vi);
2448 end_synchronized_op(sc, 0);
2452 rc = cxgbe_vi_attach(dev, vi);
2454 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2461 vcxgbe_detach(device_t dev)
2466 vi = device_get_softc(dev);
2467 sc = vi->pi->adapter;
2471 cxgbe_vi_detach(vi);
2472 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2474 end_synchronized_op(sc, 0);
2480 t4_fatal_err(struct adapter *sc)
2482 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2483 t4_intr_disable(sc);
2484 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2485 device_get_nameunit(sc->dev));
2486 if (t4_panic_on_fatal_err)
2487 panic("panic requested on fatal error");
2491 t4_add_adapter(struct adapter *sc)
2493 sx_xlock(&t4_list_lock);
2494 SLIST_INSERT_HEAD(&t4_list, sc, link);
2495 sx_xunlock(&t4_list_lock);
2499 t4_map_bars_0_and_4(struct adapter *sc)
2501 sc->regs_rid = PCIR_BAR(0);
2502 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2503 &sc->regs_rid, RF_ACTIVE);
2504 if (sc->regs_res == NULL) {
2505 device_printf(sc->dev, "cannot map registers.\n");
2508 sc->bt = rman_get_bustag(sc->regs_res);
2509 sc->bh = rman_get_bushandle(sc->regs_res);
2510 sc->mmio_len = rman_get_size(sc->regs_res);
2511 setbit(&sc->doorbells, DOORBELL_KDB);
2513 sc->msix_rid = PCIR_BAR(4);
2514 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2515 &sc->msix_rid, RF_ACTIVE);
2516 if (sc->msix_res == NULL) {
2517 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2525 t4_map_bar_2(struct adapter *sc)
2529 * T4: only iWARP driver uses the userspace doorbells. There is no need
2530 * to map it if RDMA is disabled.
2532 if (is_t4(sc) && sc->rdmacaps == 0)
2535 sc->udbs_rid = PCIR_BAR(2);
2536 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2537 &sc->udbs_rid, RF_ACTIVE);
2538 if (sc->udbs_res == NULL) {
2539 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2542 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2544 if (chip_id(sc) >= CHELSIO_T5) {
2545 setbit(&sc->doorbells, DOORBELL_UDB);
2546 #if defined(__i386__) || defined(__amd64__)
2547 if (t5_write_combine) {
2551 * Enable write combining on BAR2. This is the
2552 * userspace doorbell BAR and is split into 128B
2553 * (UDBS_SEG_SIZE) doorbell regions, each associated
2554 * with an egress queue. The first 64B has the doorbell
2555 * and the second 64B can be used to submit a tx work
2556 * request with an implicit doorbell.
2559 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2560 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2562 clrbit(&sc->doorbells, DOORBELL_UDB);
2563 setbit(&sc->doorbells, DOORBELL_WCWR);
2564 setbit(&sc->doorbells, DOORBELL_UDBWC);
2566 device_printf(sc->dev,
2567 "couldn't enable write combining: %d\n",
2571 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2572 t4_write_reg(sc, A_SGE_STAT_CFG,
2573 V_STATSOURCE_T5(7) | mode);
2577 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0;
2582 struct memwin_init {
2587 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2588 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2589 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2590 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2593 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2594 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2595 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2596 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2600 setup_memwin(struct adapter *sc)
2602 const struct memwin_init *mw_init;
2609 * Read low 32b of bar0 indirectly via the hardware backdoor
2610 * mechanism. Works from within PCI passthrough environments
2611 * too, where rman_get_start() can return a different value. We
2612 * need to program the T4 memory window decoders with the actual
2613 * addresses that will be coming across the PCIe link.
2615 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2616 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2618 mw_init = &t4_memwin[0];
2620 /* T5+ use the relative offset inside the PCIe BAR */
2623 mw_init = &t5_memwin[0];
2626 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2627 rw_init(&mw->mw_lock, "memory window access");
2628 mw->mw_base = mw_init->base;
2629 mw->mw_aperture = mw_init->aperture;
2632 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2633 (mw->mw_base + bar0) | V_BIR(0) |
2634 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2635 rw_wlock(&mw->mw_lock);
2636 position_memwin(sc, i, 0);
2637 rw_wunlock(&mw->mw_lock);
2641 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2645 * Positions the memory window at the given address in the card's address space.
2646 * There are some alignment requirements and the actual position may be at an
2647 * address prior to the requested address. mw->mw_curpos always has the actual
2648 * position of the window.
2651 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2657 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2658 mw = &sc->memwin[idx];
2659 rw_assert(&mw->mw_lock, RA_WLOCKED);
2663 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2665 pf = V_PFNUM(sc->pf);
2666 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2668 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2669 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2670 t4_read_reg(sc, reg); /* flush */
2674 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2680 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2682 /* Memory can only be accessed in naturally aligned 4 byte units */
2683 if (addr & 3 || len & 3 || len <= 0)
2686 mw = &sc->memwin[idx];
2688 rw_rlock(&mw->mw_lock);
2689 mw_end = mw->mw_curpos + mw->mw_aperture;
2690 if (addr >= mw_end || addr < mw->mw_curpos) {
2691 /* Will need to reposition the window */
2692 if (!rw_try_upgrade(&mw->mw_lock)) {
2693 rw_runlock(&mw->mw_lock);
2694 rw_wlock(&mw->mw_lock);
2696 rw_assert(&mw->mw_lock, RA_WLOCKED);
2697 position_memwin(sc, idx, addr);
2698 rw_downgrade(&mw->mw_lock);
2699 mw_end = mw->mw_curpos + mw->mw_aperture;
2701 rw_assert(&mw->mw_lock, RA_RLOCKED);
2702 while (addr < mw_end && len > 0) {
2704 v = t4_read_reg(sc, mw->mw_base + addr -
2706 *val++ = le32toh(v);
2709 t4_write_reg(sc, mw->mw_base + addr -
2710 mw->mw_curpos, htole32(v));
2715 rw_runlock(&mw->mw_lock);
2722 alloc_atid_tab(struct tid_info *t, int flags)
2726 MPASS(t->natids > 0);
2727 MPASS(t->atid_tab == NULL);
2729 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE,
2731 if (t->atid_tab == NULL)
2733 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF);
2734 t->afree = t->atid_tab;
2735 t->atids_in_use = 0;
2736 for (i = 1; i < t->natids; i++)
2737 t->atid_tab[i - 1].next = &t->atid_tab[i];
2738 t->atid_tab[t->natids - 1].next = NULL;
2744 free_atid_tab(struct tid_info *t)
2747 KASSERT(t->atids_in_use == 0,
2748 ("%s: %d atids still in use.", __func__, t->atids_in_use));
2750 if (mtx_initialized(&t->atid_lock))
2751 mtx_destroy(&t->atid_lock);
2752 free(t->atid_tab, M_CXGBE);
2757 alloc_atid(struct adapter *sc, void *ctx)
2759 struct tid_info *t = &sc->tids;
2762 mtx_lock(&t->atid_lock);
2764 union aopen_entry *p = t->afree;
2766 atid = p - t->atid_tab;
2767 MPASS(atid <= M_TID_TID);
2772 mtx_unlock(&t->atid_lock);
2777 lookup_atid(struct adapter *sc, int atid)
2779 struct tid_info *t = &sc->tids;
2781 return (t->atid_tab[atid].data);
2785 free_atid(struct adapter *sc, int atid)
2787 struct tid_info *t = &sc->tids;
2788 union aopen_entry *p = &t->atid_tab[atid];
2790 mtx_lock(&t->atid_lock);
2794 mtx_unlock(&t->atid_lock);
2798 queue_tid_release(struct adapter *sc, int tid)
2801 CXGBE_UNIMPLEMENTED("deferred tid release");
2805 release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq)
2808 struct cpl_tid_release *req;
2810 wr = alloc_wrqe(sizeof(*req), ctrlq);
2812 queue_tid_release(sc, tid); /* defer */
2817 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
2823 t4_range_cmp(const void *a, const void *b)
2825 return ((const struct t4_range *)a)->start -
2826 ((const struct t4_range *)b)->start;
2830 * Verify that the memory range specified by the addr/len pair is valid within
2831 * the card's address space.
2834 validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len)
2836 struct t4_range mem_ranges[4], *r, *next;
2837 uint32_t em, addr_len;
2838 int i, n, remaining;
2840 /* Memory can only be accessed in naturally aligned 4 byte units */
2841 if (addr & 3 || len & 3 || len == 0)
2844 /* Enabled memories */
2845 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2849 bzero(r, sizeof(mem_ranges));
2850 if (em & F_EDRAM0_ENABLE) {
2851 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2852 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2854 r->start = G_EDRAM0_BASE(addr_len) << 20;
2855 if (addr >= r->start &&
2856 addr + len <= r->start + r->size)
2862 if (em & F_EDRAM1_ENABLE) {
2863 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2864 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2866 r->start = G_EDRAM1_BASE(addr_len) << 20;
2867 if (addr >= r->start &&
2868 addr + len <= r->start + r->size)
2874 if (em & F_EXT_MEM_ENABLE) {
2875 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2876 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2878 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2879 if (addr >= r->start &&
2880 addr + len <= r->start + r->size)
2886 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2887 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2888 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2890 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2891 if (addr >= r->start &&
2892 addr + len <= r->start + r->size)
2898 MPASS(n <= nitems(mem_ranges));
2901 /* Sort and merge the ranges. */
2902 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2904 /* Start from index 0 and examine the next n - 1 entries. */
2906 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2908 MPASS(r->size > 0); /* r is a valid entry. */
2910 MPASS(next->size > 0); /* and so is the next one. */
2912 while (r->start + r->size >= next->start) {
2913 /* Merge the next one into the current entry. */
2914 r->size = max(r->start + r->size,
2915 next->start + next->size) - r->start;
2916 n--; /* One fewer entry in total. */
2917 if (--remaining == 0)
2918 goto done; /* short circuit */
2921 if (next != r + 1) {
2923 * Some entries were merged into r and next
2924 * points to the first valid entry that couldn't
2927 MPASS(next->size > 0); /* must be valid */
2928 memcpy(r + 1, next, remaining * sizeof(*r));
2931 * This so that the foo->size assertion in the
2932 * next iteration of the loop do the right
2933 * thing for entries that were pulled up and are
2936 MPASS(n < nitems(mem_ranges));
2937 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2938 sizeof(struct t4_range));
2943 /* Done merging the ranges. */
2946 for (i = 0; i < n; i++, r++) {
2947 if (addr >= r->start &&
2948 addr + len <= r->start + r->size)
2957 fwmtype_to_hwmtype(int mtype)
2961 case FW_MEMTYPE_EDC0:
2963 case FW_MEMTYPE_EDC1:
2965 case FW_MEMTYPE_EXTMEM:
2967 case FW_MEMTYPE_EXTMEM1:
2970 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2975 * Verify that the memory range specified by the memtype/offset/len pair is
2976 * valid and lies entirely within the memtype specified. The global address of
2977 * the start of the range is returned in addr.
2980 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len,
2983 uint32_t em, addr_len, maddr;
2985 /* Memory can only be accessed in naturally aligned 4 byte units */
2986 if (off & 3 || len & 3 || len == 0)
2989 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2990 switch (fwmtype_to_hwmtype(mtype)) {
2992 if (!(em & F_EDRAM0_ENABLE))
2994 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2995 maddr = G_EDRAM0_BASE(addr_len) << 20;
2998 if (!(em & F_EDRAM1_ENABLE))
3000 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
3001 maddr = G_EDRAM1_BASE(addr_len) << 20;
3004 if (!(em & F_EXT_MEM_ENABLE))
3006 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
3007 maddr = G_EXT_MEM_BASE(addr_len) << 20;
3010 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
3012 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
3013 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
3019 *addr = maddr + off; /* global address */
3020 return (validate_mem_range(sc, *addr, len));
3024 fixup_devlog_params(struct adapter *sc)
3026 struct devlog_params *dparams = &sc->params.devlog;
3029 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
3030 dparams->size, &dparams->addr);
3036 update_nirq(struct intrs_and_queues *iaq, int nports)
3038 int extra = T4_EXTRA_INTR;
3041 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq);
3042 iaq->nirq += nports * (iaq->num_vis - 1) *
3043 max(iaq->nrxq_vi, iaq->nnmrxq_vi);
3044 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
3048 * Adjust requirements to fit the number of interrupts available.
3051 calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
3055 const int nports = sc->params.nports;
3060 bzero(iaq, sizeof(*iaq));
3061 iaq->intr_type = itype;
3062 iaq->num_vis = t4_num_vis;
3063 iaq->ntxq = t4_ntxq;
3064 iaq->ntxq_vi = t4_ntxq_vi;
3065 iaq->nrxq = t4_nrxq;
3066 iaq->nrxq_vi = t4_nrxq_vi;
3067 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3068 if (is_offload(sc) || is_ethoffload(sc)) {
3069 iaq->nofldtxq = t4_nofldtxq;
3070 iaq->nofldtxq_vi = t4_nofldtxq_vi;
3074 if (is_offload(sc)) {
3075 iaq->nofldrxq = t4_nofldrxq;
3076 iaq->nofldrxq_vi = t4_nofldrxq_vi;
3080 iaq->nnmtxq_vi = t4_nnmtxq_vi;
3081 iaq->nnmrxq_vi = t4_nnmrxq_vi;
3084 update_nirq(iaq, nports);
3085 if (iaq->nirq <= navail &&
3086 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3088 * This is the normal case -- there are enough interrupts for
3095 * If extra VIs have been configured try reducing their count and see if
3098 while (iaq->num_vis > 1) {
3100 update_nirq(iaq, nports);
3101 if (iaq->nirq <= navail &&
3102 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3103 device_printf(sc->dev, "virtual interfaces per port "
3104 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, "
3105 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. "
3106 "itype %d, navail %u, nirq %d.\n",
3107 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq,
3108 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi,
3109 itype, navail, iaq->nirq);
3115 * Extra VIs will not be created. Log a message if they were requested.
3117 MPASS(iaq->num_vis == 1);
3118 iaq->ntxq_vi = iaq->nrxq_vi = 0;
3119 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
3120 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
3121 if (iaq->num_vis != t4_num_vis) {
3122 device_printf(sc->dev, "extra virtual interfaces disabled. "
3123 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, "
3124 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n",
3125 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi,
3126 iaq->nnmrxq_vi, itype, navail, iaq->nirq);
3130 * Keep reducing the number of NIC rx queues to the next lower power of
3131 * 2 (for even RSS distribution) and halving the TOE rx queues and see
3135 if (iaq->nrxq > 1) {
3138 } while (!powerof2(iaq->nrxq));
3140 if (iaq->nofldrxq > 1)
3141 iaq->nofldrxq >>= 1;
3143 old_nirq = iaq->nirq;
3144 update_nirq(iaq, nports);
3145 if (iaq->nirq <= navail &&
3146 (itype != INTR_MSI || powerof2(iaq->nirq))) {
3147 device_printf(sc->dev, "running with reduced number of "
3148 "rx queues because of shortage of interrupts. "
3149 "nrxq=%u, nofldrxq=%u. "
3150 "itype %d, navail %u, nirq %d.\n", iaq->nrxq,
3151 iaq->nofldrxq, itype, navail, iaq->nirq);
3154 } while (old_nirq != iaq->nirq);
3156 /* One interrupt for everything. Ugh. */
3157 device_printf(sc->dev, "running with minimal number of queues. "
3158 "itype %d, navail %u.\n", itype, navail);
3160 MPASS(iaq->nrxq == 1);
3162 if (iaq->nofldrxq > 1)
3165 MPASS(iaq->num_vis > 0);
3166 if (iaq->num_vis > 1) {
3167 MPASS(iaq->nrxq_vi > 0);
3168 MPASS(iaq->ntxq_vi > 0);
3170 MPASS(iaq->nirq > 0);
3171 MPASS(iaq->nrxq > 0);
3172 MPASS(iaq->ntxq > 0);
3173 if (itype == INTR_MSI) {
3174 MPASS(powerof2(iaq->nirq));
3179 cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
3181 int rc, itype, navail, nalloc;
3183 for (itype = INTR_MSIX; itype; itype >>= 1) {
3185 if ((itype & t4_intr_types) == 0)
3186 continue; /* not allowed */
3188 if (itype == INTR_MSIX)
3189 navail = pci_msix_count(sc->dev);
3190 else if (itype == INTR_MSI)
3191 navail = pci_msi_count(sc->dev);
3198 calculate_iaq(sc, iaq, itype, navail);
3201 if (itype == INTR_MSIX)
3202 rc = pci_alloc_msix(sc->dev, &nalloc);
3203 else if (itype == INTR_MSI)
3204 rc = pci_alloc_msi(sc->dev, &nalloc);
3206 if (rc == 0 && nalloc > 0) {
3207 if (nalloc == iaq->nirq)
3211 * Didn't get the number requested. Use whatever number
3212 * the kernel is willing to allocate.
3214 device_printf(sc->dev, "fewer vectors than requested, "
3215 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
3216 itype, iaq->nirq, nalloc);
3217 pci_release_msi(sc->dev);
3222 device_printf(sc->dev,
3223 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
3224 itype, rc, iaq->nirq, nalloc);
3227 device_printf(sc->dev,
3228 "failed to find a usable interrupt type. "
3229 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
3230 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
3235 #define FW_VERSION(chip) ( \
3236 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
3237 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
3238 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
3239 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
3240 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
3246 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
3250 .kld_name = "t4fw_cfg",
3251 .fw_mod_name = "t4fw",
3253 .chip = FW_HDR_CHIP_T4,
3254 .fw_ver = htobe32(FW_VERSION(T4)),
3255 .intfver_nic = FW_INTFVER(T4, NIC),
3256 .intfver_vnic = FW_INTFVER(T4, VNIC),
3257 .intfver_ofld = FW_INTFVER(T4, OFLD),
3258 .intfver_ri = FW_INTFVER(T4, RI),
3259 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
3260 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3261 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
3262 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3266 .kld_name = "t5fw_cfg",
3267 .fw_mod_name = "t5fw",
3269 .chip = FW_HDR_CHIP_T5,
3270 .fw_ver = htobe32(FW_VERSION(T5)),
3271 .intfver_nic = FW_INTFVER(T5, NIC),
3272 .intfver_vnic = FW_INTFVER(T5, VNIC),
3273 .intfver_ofld = FW_INTFVER(T5, OFLD),
3274 .intfver_ri = FW_INTFVER(T5, RI),
3275 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
3276 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3277 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
3278 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3282 .kld_name = "t6fw_cfg",
3283 .fw_mod_name = "t6fw",
3285 .chip = FW_HDR_CHIP_T6,
3286 .fw_ver = htobe32(FW_VERSION(T6)),
3287 .intfver_nic = FW_INTFVER(T6, NIC),
3288 .intfver_vnic = FW_INTFVER(T6, VNIC),
3289 .intfver_ofld = FW_INTFVER(T6, OFLD),
3290 .intfver_ri = FW_INTFVER(T6, RI),
3291 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3292 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3293 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3294 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3299 static struct fw_info *
3300 find_fw_info(int chip)
3304 for (i = 0; i < nitems(fw_info); i++) {
3305 if (fw_info[i].chip == chip)
3306 return (&fw_info[i]);
3312 * Is the given firmware API compatible with the one the driver was compiled
3316 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3319 /* short circuit if it's the exact same firmware version */
3320 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3324 * XXX: Is this too conservative? Perhaps I should limit this to the
3325 * features that are supported in the driver.
3327 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3328 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3329 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
3330 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
3338 * The firmware in the KLD is usable, but should it be installed? This routine
3339 * explains itself in detail if it indicates the KLD firmware should be
3343 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
3347 if (!card_fw_usable) {
3348 reason = "incompatible or unusable";
3353 reason = "older than the version bundled with this driver";
3357 if (t4_fw_install == 2 && k != c) {
3358 reason = "different than the version bundled with this driver";
3365 if (t4_fw_install == 0) {
3366 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3367 "but the driver is prohibited from installing a different "
3368 "firmware on the card.\n",
3369 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3370 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
3375 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
3376 "installing firmware %u.%u.%u.%u on card.\n",
3377 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3378 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
3379 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3380 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3386 * Establish contact with the firmware and determine if we are the master driver
3387 * or not, and whether we are responsible for chip initialization.
3390 prep_firmware(struct adapter *sc)
3392 const struct firmware *fw = NULL, *default_cfg;
3393 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
3394 enum dev_state state;
3395 struct fw_info *fw_info;
3396 struct fw_hdr *card_fw; /* fw on the card */
3397 const struct fw_hdr *kld_fw; /* fw in the KLD */
3398 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
3401 /* This is the firmware whose headers the driver was compiled against */
3402 fw_info = find_fw_info(chip_id(sc));
3403 if (fw_info == NULL) {
3404 device_printf(sc->dev,
3405 "unable to look up firmware information for chip %d.\n",
3409 drv_fw = &fw_info->fw_hdr;
3412 * The firmware KLD contains many modules. The KLD name is also the
3413 * name of the module that contains the default config file.
3415 default_cfg = firmware_get(fw_info->kld_name);
3417 /* This is the firmware in the KLD */
3418 fw = firmware_get(fw_info->fw_mod_name);
3420 kld_fw = (const void *)fw->data;
3421 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3427 /* Read the header of the firmware on the card */
3428 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3429 rc = -t4_read_flash(sc, FLASH_FW_START,
3430 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3432 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3433 if (card_fw->fw_ver == be32toh(0xffffffff)) {
3434 uint32_t d = be32toh(kld_fw->fw_ver);
3436 if (!kld_fw_usable) {
3437 device_printf(sc->dev,
3438 "no firmware on the card and no usable "
3439 "firmware bundled with the driver.\n");
3442 } else if (t4_fw_install == 0) {
3443 device_printf(sc->dev,
3444 "no firmware on the card and the driver "
3445 "is prohibited from installing new "
3451 device_printf(sc->dev, "no firmware on the card, "
3452 "installing firmware %d.%d.%d.%d\n",
3453 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3454 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d));
3455 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize);
3458 device_printf(sc->dev,
3459 "firmware install failed: %d.\n", rc);
3462 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3467 device_printf(sc->dev,
3468 "Unable to read card's firmware header: %d\n", rc);
3472 /* Contact firmware. */
3473 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
3474 if (rc < 0 || state == DEV_STATE_ERR) {
3476 device_printf(sc->dev,
3477 "failed to connect to the firmware: %d, %d.\n", rc, state);
3482 sc->flags |= MASTER_PF;
3483 else if (state == DEV_STATE_UNINIT) {
3485 * We didn't get to be the master so we definitely won't be
3486 * configuring the chip. It's a bug if someone else hasn't
3487 * configured it already.
3489 device_printf(sc->dev, "couldn't be master(%d), "
3490 "device not already initialized either(%d).\n", rc, state);
3495 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3496 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3498 * Common case: the firmware on the card is an exact match and
3499 * the KLD is an exact match too, or the KLD is
3500 * absent/incompatible. Note that t4_fw_install = 2 is ignored
3501 * here -- use cxgbetool loadfw if you want to reinstall the
3502 * same firmware as the one on the card.
3504 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3505 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3506 be32toh(card_fw->fw_ver))) {
3508 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3510 device_printf(sc->dev,
3511 "failed to install firmware: %d\n", rc);
3515 /* Installed successfully, update the cached header too. */
3516 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3518 need_fw_reset = 0; /* already reset as part of load_fw */
3521 if (!card_fw_usable) {
3524 d = ntohl(drv_fw->fw_ver);
3525 c = ntohl(card_fw->fw_ver);
3526 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3528 device_printf(sc->dev, "Cannot find a usable firmware: "
3529 "fw_install %d, chip state %d, "
3530 "driver compiled with %d.%d.%d.%d, "
3531 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3532 t4_fw_install, state,
3533 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3534 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3535 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3536 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3537 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3538 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3544 if (need_fw_reset &&
3545 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3546 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3547 if (rc != ETIMEDOUT && rc != EIO)
3548 t4_fw_bye(sc, sc->mbox);
3553 rc = get_params__pre_init(sc);
3555 goto done; /* error message displayed already */
3557 /* Partition adapter resources as specified in the config file. */
3558 if (state == DEV_STATE_UNINIT) {
3560 KASSERT(sc->flags & MASTER_PF,
3561 ("%s: trying to change chip settings when not master.",
3564 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3566 goto done; /* error message displayed already */
3568 t4_tweak_chip_settings(sc);
3570 /* get basic stuff going */
3571 rc = -t4_fw_initialize(sc, sc->mbox);
3573 device_printf(sc->dev, "fw init failed: %d.\n", rc);
3577 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3582 free(card_fw, M_CXGBE);
3584 firmware_put(fw, FIRMWARE_UNLOAD);
3585 if (default_cfg != NULL)
3586 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3591 #define FW_PARAM_DEV(param) \
3592 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3593 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3594 #define FW_PARAM_PFVF(param) \
3595 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3596 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3599 * Partition chip resources for use between various PFs, VFs, etc.
3602 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3603 const char *name_prefix)
3605 const struct firmware *cfg = NULL;
3607 struct fw_caps_config_cmd caps;
3608 uint32_t mtype, moff, finicsum, cfcsum;
3611 * Figure out what configuration file to use. Pick the default config
3612 * file for the card if the user hasn't specified one explicitly.
3614 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3615 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3616 /* Card specific overrides go here. */
3617 if (pci_get_device(sc->dev) == 0x440a)
3618 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3620 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3621 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0)
3622 goto use_built_in_config; /* go straight to config. */
3625 * We need to load another module if the profile is anything except
3626 * "default" or "flash".
3628 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3629 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3632 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3633 cfg = firmware_get(s);
3635 if (default_cfg != NULL) {
3636 device_printf(sc->dev,
3637 "unable to load module \"%s\" for "
3638 "configuration profile \"%s\", will use "
3639 "the default config file instead.\n",
3641 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3644 device_printf(sc->dev,
3645 "unable to load module \"%s\" for "
3646 "configuration profile \"%s\", will use "
3647 "the config file on the card's flash "
3648 "instead.\n", s, sc->cfg_file);
3649 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3655 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3656 default_cfg == NULL) {
3657 device_printf(sc->dev,
3658 "default config file not available, will use the config "
3659 "file on the card's flash instead.\n");
3660 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3663 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3665 const uint32_t *cfdata;
3666 uint32_t param, val, addr;
3668 KASSERT(cfg != NULL || default_cfg != NULL,
3669 ("%s: no config to upload", __func__));
3672 * Ask the firmware where it wants us to upload the config file.
3674 param = FW_PARAM_DEV(CF);
3675 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3677 /* No support for config file? Shouldn't happen. */
3678 device_printf(sc->dev,
3679 "failed to query config file location: %d.\n", rc);
3682 mtype = G_FW_PARAMS_PARAM_Y(val);
3683 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3686 * XXX: sheer laziness. We deliberately added 4 bytes of
3687 * useless stuffing/comments at the end of the config file so
3688 * it's ok to simply throw away the last remaining bytes when
3689 * the config file is not an exact multiple of 4. This also
3690 * helps with the validate_mt_off_len check.
3693 cflen = cfg->datasize & ~3;
3696 cflen = default_cfg->datasize & ~3;
3697 cfdata = default_cfg->data;
3700 if (cflen > FLASH_CFG_MAX_SIZE) {
3701 device_printf(sc->dev,
3702 "config file too long (%d, max allowed is %d). "
3703 "Will try to use the config on the card, if any.\n",
3704 cflen, FLASH_CFG_MAX_SIZE);
3705 goto use_config_on_flash;
3708 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3710 device_printf(sc->dev,
3711 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3712 "Will try to use the config on the card, if any.\n",
3713 __func__, mtype, moff, cflen, rc);
3714 goto use_config_on_flash;
3716 write_via_memwin(sc, 2, addr, cfdata, cflen);
3718 use_config_on_flash:
3719 mtype = FW_MEMTYPE_FLASH;
3720 moff = t4_flash_cfg_addr(sc);
3723 bzero(&caps, sizeof(caps));
3724 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3725 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3726 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3727 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3728 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3729 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3731 device_printf(sc->dev,
3732 "failed to pre-process config file: %d "
3733 "(mtype %d, moff 0x%x). Will reset the firmware and retry "
3734 "with the built-in configuration.\n", rc, mtype, moff);
3736 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
3738 device_printf(sc->dev,
3739 "firmware reset failed: %d.\n", rc);
3740 if (rc != ETIMEDOUT && rc != EIO) {
3741 t4_fw_bye(sc, sc->mbox);
3742 sc->flags &= ~FW_OK;
3746 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in");
3747 use_built_in_config:
3748 bzero(&caps, sizeof(caps));
3749 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3750 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3751 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3752 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3754 device_printf(sc->dev,
3755 "built-in configuration failed: %d.\n", rc);
3760 finicsum = be32toh(caps.finicsum);
3761 cfcsum = be32toh(caps.cfcsum);
3762 if (finicsum != cfcsum) {
3763 device_printf(sc->dev,
3764 "WARNING: config file checksum mismatch: %08x %08x\n",
3767 sc->cfcsum = cfcsum;
3769 #define LIMIT_CAPS(x) do { \
3770 caps.x &= htobe16(t4_##x##_allowed); \
3774 * Let the firmware know what features will (not) be used so it can tune
3775 * things accordingly.
3777 LIMIT_CAPS(nbmcaps);
3778 LIMIT_CAPS(linkcaps);
3779 LIMIT_CAPS(switchcaps);
3780 LIMIT_CAPS(niccaps);
3781 LIMIT_CAPS(toecaps);
3782 LIMIT_CAPS(rdmacaps);
3783 LIMIT_CAPS(cryptocaps);
3784 LIMIT_CAPS(iscsicaps);
3785 LIMIT_CAPS(fcoecaps);
3788 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
3790 * TOE and hashfilters are mutually exclusive. It is a config
3791 * file or firmware bug if both are reported as available. Try
3792 * to cope with the situation in non-debug builds by disabling
3795 MPASS(caps.toecaps == 0);
3802 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3803 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3804 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3805 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3807 device_printf(sc->dev,
3808 "failed to process config file: %d.\n", rc);
3812 firmware_put(cfg, FIRMWARE_UNLOAD);
3817 * Retrieve parameters that are needed (or nice to have) very early.
3820 get_params__pre_init(struct adapter *sc)
3823 uint32_t param[2], val[2];
3825 t4_get_version_info(sc);
3827 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3828 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3829 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3830 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3831 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3833 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3834 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3835 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3836 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3837 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3839 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3840 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3841 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3842 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3843 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3845 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3846 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3847 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3848 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3849 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3851 param[0] = FW_PARAM_DEV(PORTVEC);
3852 param[1] = FW_PARAM_DEV(CCLK);
3853 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3855 device_printf(sc->dev,
3856 "failed to query parameters (pre_init): %d.\n", rc);
3860 sc->params.portvec = val[0];
3861 sc->params.nports = bitcount32(val[0]);
3862 sc->params.vpd.cclk = val[1];
3864 /* Read device log parameters. */
3865 rc = -t4_init_devlog_params(sc, 1);
3867 fixup_devlog_params(sc);
3869 device_printf(sc->dev,
3870 "failed to get devlog parameters: %d.\n", rc);
3871 rc = 0; /* devlog isn't critical for device operation */
3878 * Retrieve various parameters that are of interest to the driver. The device
3879 * has been initialized by the firmware at this point.
3882 get_params__post_init(struct adapter *sc)
3885 uint32_t param[7], val[7];
3886 struct fw_caps_config_cmd caps;
3888 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3889 param[1] = FW_PARAM_PFVF(EQ_START);
3890 param[2] = FW_PARAM_PFVF(FILTER_START);
3891 param[3] = FW_PARAM_PFVF(FILTER_END);
3892 param[4] = FW_PARAM_PFVF(L2T_START);
3893 param[5] = FW_PARAM_PFVF(L2T_END);
3894 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3895 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
3896 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD);
3897 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val);
3899 device_printf(sc->dev,
3900 "failed to query parameters (post_init): %d.\n", rc);
3904 sc->sge.iq_start = val[0];
3905 sc->sge.eq_start = val[1];
3906 if ((int)val[3] > (int)val[2]) {
3907 sc->tids.ftid_base = val[2];
3908 sc->tids.ftid_end = val[3];
3909 sc->tids.nftids = val[3] - val[2] + 1;
3911 sc->vres.l2t.start = val[4];
3912 sc->vres.l2t.size = val[5] - val[4] + 1;
3913 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3914 ("%s: L2 table size (%u) larger than expected (%u)",
3915 __func__, sc->vres.l2t.size, L2T_SIZE));
3916 sc->params.core_vdd = val[6];
3918 if (chip_id(sc) >= CHELSIO_T6) {
3921 if (sc->params.fw_vers >=
3922 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
3923 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) {
3925 * Note that the code to enable the region should run
3926 * before t4_fw_initialize and not here. This is just a
3927 * reminder to add said code.
3929 device_printf(sc->dev,
3930 "hpfilter region not enabled.\n");
3934 sc->tids.tid_base = t4_read_reg(sc,
3935 A_LE_DB_ACTIVE_TABLE_START_INDEX);
3937 param[0] = FW_PARAM_PFVF(HPFILTER_START);
3938 param[1] = FW_PARAM_PFVF(HPFILTER_END);
3939 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3941 device_printf(sc->dev,
3942 "failed to query hpfilter parameters: %d.\n", rc);
3945 if ((int)val[1] > (int)val[0]) {
3946 sc->tids.hpftid_base = val[0];
3947 sc->tids.hpftid_end = val[1];
3948 sc->tids.nhpftids = val[1] - val[0] + 1;
3951 * These should go off if the layout changes and the
3952 * driver needs to catch up.
3954 MPASS(sc->tids.hpftid_base == 0);
3955 MPASS(sc->tids.tid_base == sc->tids.nhpftids);
3960 * MPSBGMAP is queried separately because only recent firmwares support
3961 * it as a parameter and we don't want the compound query above to fail
3962 * on older firmwares.
3964 param[0] = FW_PARAM_DEV(MPSBGMAP);
3966 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3968 sc->params.mps_bg_map = val[0];
3970 sc->params.mps_bg_map = 0;
3973 * Determine whether the firmware supports the filter2 work request.
3974 * This is queried separately for the same reason as MPSBGMAP above.
3976 param[0] = FW_PARAM_DEV(FILTER2_WR);
3978 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
3980 sc->params.filter2_wr_support = val[0] != 0;
3982 sc->params.filter2_wr_support = 0;
3984 /* get capabilites */
3985 bzero(&caps, sizeof(caps));
3986 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3987 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3988 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3989 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3991 device_printf(sc->dev,
3992 "failed to get card capabilities: %d.\n", rc);
3996 #define READ_CAPS(x) do { \
3997 sc->x = htobe16(caps.x); \
4000 READ_CAPS(linkcaps);
4001 READ_CAPS(switchcaps);
4004 READ_CAPS(rdmacaps);
4005 READ_CAPS(cryptocaps);
4006 READ_CAPS(iscsicaps);
4007 READ_CAPS(fcoecaps);
4009 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) {
4010 MPASS(chip_id(sc) > CHELSIO_T4);
4011 MPASS(sc->toecaps == 0);
4014 param[0] = FW_PARAM_DEV(NTID);
4015 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
4017 device_printf(sc->dev,
4018 "failed to query HASHFILTER parameters: %d.\n", rc);
4021 sc->tids.ntids = val[0];
4022 if (sc->params.fw_vers <
4023 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4024 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4025 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4026 sc->tids.ntids -= sc->tids.nhpftids;
4028 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4029 sc->params.hash_filter = 1;
4031 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
4032 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
4033 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
4034 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4035 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
4037 device_printf(sc->dev,
4038 "failed to query NIC parameters: %d.\n", rc);
4041 if ((int)val[1] > (int)val[0]) {
4042 sc->tids.etid_base = val[0];
4043 sc->tids.etid_end = val[1];
4044 sc->tids.netids = val[1] - val[0] + 1;
4045 sc->params.eo_wr_cred = val[2];
4046 sc->params.ethoffload = 1;
4050 /* query offload-related parameters */
4051 param[0] = FW_PARAM_DEV(NTID);
4052 param[1] = FW_PARAM_PFVF(SERVER_START);
4053 param[2] = FW_PARAM_PFVF(SERVER_END);
4054 param[3] = FW_PARAM_PFVF(TDDP_START);
4055 param[4] = FW_PARAM_PFVF(TDDP_END);
4056 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4057 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4059 device_printf(sc->dev,
4060 "failed to query TOE parameters: %d.\n", rc);
4063 sc->tids.ntids = val[0];
4064 if (sc->params.fw_vers <
4065 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) |
4066 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) {
4067 MPASS(sc->tids.ntids >= sc->tids.nhpftids);
4068 sc->tids.ntids -= sc->tids.nhpftids;
4070 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
4071 if ((int)val[2] > (int)val[1]) {
4072 sc->tids.stid_base = val[1];
4073 sc->tids.nstids = val[2] - val[1] + 1;
4075 sc->vres.ddp.start = val[3];
4076 sc->vres.ddp.size = val[4] - val[3] + 1;
4077 sc->params.ofldq_wr_cred = val[5];
4078 sc->params.offload = 1;
4081 * The firmware attempts memfree TOE configuration for -SO cards
4082 * and will report toecaps=0 if it runs out of resources (this
4083 * depends on the config file). It may not report 0 for other
4084 * capabilities dependent on the TOE in this case. Set them to
4085 * 0 here so that the driver doesn't bother tracking resources
4086 * that will never be used.
4092 param[0] = FW_PARAM_PFVF(STAG_START);
4093 param[1] = FW_PARAM_PFVF(STAG_END);
4094 param[2] = FW_PARAM_PFVF(RQ_START);
4095 param[3] = FW_PARAM_PFVF(RQ_END);
4096 param[4] = FW_PARAM_PFVF(PBL_START);
4097 param[5] = FW_PARAM_PFVF(PBL_END);
4098 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4100 device_printf(sc->dev,
4101 "failed to query RDMA parameters(1): %d.\n", rc);
4104 sc->vres.stag.start = val[0];
4105 sc->vres.stag.size = val[1] - val[0] + 1;
4106 sc->vres.rq.start = val[2];
4107 sc->vres.rq.size = val[3] - val[2] + 1;
4108 sc->vres.pbl.start = val[4];
4109 sc->vres.pbl.size = val[5] - val[4] + 1;
4111 param[0] = FW_PARAM_PFVF(SQRQ_START);
4112 param[1] = FW_PARAM_PFVF(SQRQ_END);
4113 param[2] = FW_PARAM_PFVF(CQ_START);
4114 param[3] = FW_PARAM_PFVF(CQ_END);
4115 param[4] = FW_PARAM_PFVF(OCQ_START);
4116 param[5] = FW_PARAM_PFVF(OCQ_END);
4117 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
4119 device_printf(sc->dev,
4120 "failed to query RDMA parameters(2): %d.\n", rc);
4123 sc->vres.qp.start = val[0];
4124 sc->vres.qp.size = val[1] - val[0] + 1;
4125 sc->vres.cq.start = val[2];
4126 sc->vres.cq.size = val[3] - val[2] + 1;
4127 sc->vres.ocq.start = val[4];
4128 sc->vres.ocq.size = val[5] - val[4] + 1;
4130 param[0] = FW_PARAM_PFVF(SRQ_START);
4131 param[1] = FW_PARAM_PFVF(SRQ_END);
4132 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
4133 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4134 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
4136 device_printf(sc->dev,
4137 "failed to query RDMA parameters(3): %d.\n", rc);
4140 sc->vres.srq.start = val[0];
4141 sc->vres.srq.size = val[1] - val[0] + 1;
4142 sc->params.max_ordird_qp = val[2];
4143 sc->params.max_ird_adapter = val[3];
4145 if (sc->iscsicaps) {
4146 param[0] = FW_PARAM_PFVF(ISCSI_START);
4147 param[1] = FW_PARAM_PFVF(ISCSI_END);
4148 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4150 device_printf(sc->dev,
4151 "failed to query iSCSI parameters: %d.\n", rc);
4154 sc->vres.iscsi.start = val[0];
4155 sc->vres.iscsi.size = val[1] - val[0] + 1;
4157 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
4158 param[0] = FW_PARAM_PFVF(TLS_START);
4159 param[1] = FW_PARAM_PFVF(TLS_END);
4160 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
4162 device_printf(sc->dev,
4163 "failed to query TLS parameters: %d.\n", rc);
4166 sc->vres.key.start = val[0];
4167 sc->vres.key.size = val[1] - val[0] + 1;
4170 t4_init_sge_params(sc);
4173 * We've got the params we wanted to query via the firmware. Now grab
4174 * some others directly from the chip.
4176 rc = t4_read_chip_settings(sc);
4182 set_params__post_init(struct adapter *sc)
4184 uint32_t param, val;
4189 /* ask for encapsulated CPLs */
4190 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4192 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
4194 /* Enable 32b port caps if the firmware supports it. */
4195 param = FW_PARAM_PFVF(PORT_CAPS32);
4197 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0)
4198 sc->params.port_caps32 = 1;
4200 /* Let filter + maskhash steer to a part of the VI's RSS region. */
4201 val = 1 << (G_MASKSIZE(t4_read_reg(sc, A_TP_RSS_CONFIG_TNL)) - 1);
4202 t4_set_reg_field(sc, A_TP_RSS_CONFIG_TNL, V_MASKFILTER(M_MASKFILTER),
4203 V_MASKFILTER(val - 1));
4207 * Override the TOE timers with user provided tunables. This is not the
4208 * recommended way to change the timers (the firmware config file is) so
4209 * these tunables are not documented.
4211 * All the timer tunables are in microseconds.
4213 if (t4_toe_keepalive_idle != 0) {
4214 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle);
4215 v &= M_KEEPALIVEIDLE;
4216 t4_set_reg_field(sc, A_TP_KEEP_IDLE,
4217 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v));
4219 if (t4_toe_keepalive_interval != 0) {
4220 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval);
4221 v &= M_KEEPALIVEINTVL;
4222 t4_set_reg_field(sc, A_TP_KEEP_INTVL,
4223 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v));
4225 if (t4_toe_keepalive_count != 0) {
4226 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2;
4227 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4228 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) |
4229 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2),
4230 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v));
4232 if (t4_toe_rexmt_min != 0) {
4233 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min);
4235 t4_set_reg_field(sc, A_TP_RXT_MIN,
4236 V_RXTMIN(M_RXTMIN), V_RXTMIN(v));
4238 if (t4_toe_rexmt_max != 0) {
4239 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max);
4241 t4_set_reg_field(sc, A_TP_RXT_MAX,
4242 V_RXTMAX(M_RXTMAX), V_RXTMAX(v));
4244 if (t4_toe_rexmt_count != 0) {
4245 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2;
4246 t4_set_reg_field(sc, A_TP_SHIFT_CNT,
4247 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) |
4248 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2),
4249 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v));
4251 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) {
4252 if (t4_toe_rexmt_backoff[i] != -1) {
4253 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0;
4254 shift = (i & 3) << 3;
4255 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3),
4256 M_TIMERBACKOFFINDEX0 << shift, v << shift);
4263 #undef FW_PARAM_PFVF
4267 t4_set_desc(struct adapter *sc)
4270 struct adapter_params *p = &sc->params;
4272 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
4274 device_set_desc_copy(sc->dev, buf);
4278 ifmedia_add4(struct ifmedia *ifm, int m)
4281 ifmedia_add(ifm, m, 0, NULL);
4282 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
4283 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
4284 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
4288 * This is the selected media, which is not quite the same as the active media.
4289 * The media line in ifconfig is "media: Ethernet selected (active)" if selected
4290 * and active are not the same, and "media: Ethernet selected" otherwise.
4293 set_current_media(struct port_info *pi)
4295 struct link_config *lc;
4296 struct ifmedia *ifm;
4300 PORT_LOCK_ASSERT_OWNED(pi);
4302 /* Leave current media alone if it's already set to IFM_NONE. */
4304 if (ifm->ifm_cur != NULL &&
4305 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
4309 if (lc->requested_aneg != AUTONEG_DISABLE &&
4310 lc->supported & FW_PORT_CAP32_ANEG) {
4311 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
4314 mword = IFM_ETHER | IFM_FDX;
4315 if (lc->requested_fc & PAUSE_TX)
4316 mword |= IFM_ETH_TXPAUSE;
4317 if (lc->requested_fc & PAUSE_RX)
4318 mword |= IFM_ETH_RXPAUSE;
4319 if (lc->requested_speed == 0)
4320 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */
4322 speed = lc->requested_speed;
4323 mword |= port_mword(pi, speed_to_fwcap(speed));
4324 ifmedia_set(ifm, mword);
4328 * Returns true if the ifmedia list for the port cannot change.
4331 fixed_ifmedia(struct port_info *pi)
4334 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
4335 pi->port_type == FW_PORT_TYPE_BT_XFI ||
4336 pi->port_type == FW_PORT_TYPE_BT_XAUI ||
4337 pi->port_type == FW_PORT_TYPE_KX4 ||
4338 pi->port_type == FW_PORT_TYPE_KX ||
4339 pi->port_type == FW_PORT_TYPE_KR ||
4340 pi->port_type == FW_PORT_TYPE_BP_AP ||
4341 pi->port_type == FW_PORT_TYPE_BP4_AP ||
4342 pi->port_type == FW_PORT_TYPE_BP40_BA ||
4343 pi->port_type == FW_PORT_TYPE_KR4_100G ||
4344 pi->port_type == FW_PORT_TYPE_KR_SFP28 ||
4345 pi->port_type == FW_PORT_TYPE_KR_XLAUI);
4349 build_medialist(struct port_info *pi)
4352 int unknown, mword, bit;
4353 struct link_config *lc;
4354 struct ifmedia *ifm;
4356 PORT_LOCK_ASSERT_OWNED(pi);
4358 if (pi->flags & FIXED_IFMEDIA)
4362 * Rebuild the ifmedia list.
4365 ifmedia_removeall(ifm);
4367 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */
4368 if (__predict_false(ss == 0)) { /* not supposed to happen. */
4371 MPASS(LIST_EMPTY(&ifm->ifm_list));
4372 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
4373 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
4378 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) {
4380 MPASS(speed & M_FW_PORT_CAP32_SPEED);
4382 mword = port_mword(pi, speed);
4383 if (mword == IFM_NONE) {
4385 } else if (mword == IFM_UNKNOWN)
4388 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
4391 if (unknown > 0) /* Add one unknown for all unknown media types. */
4392 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
4393 if (lc->supported & FW_PORT_CAP32_ANEG)
4394 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
4396 set_current_media(pi);
4400 * Initialize the requested fields in the link config based on driver tunables.
4403 init_link_config(struct port_info *pi)
4405 struct link_config *lc = &pi->link_cfg;
4407 PORT_LOCK_ASSERT_OWNED(pi);
4409 lc->requested_speed = 0;
4411 if (t4_autoneg == 0)
4412 lc->requested_aneg = AUTONEG_DISABLE;
4413 else if (t4_autoneg == 1)
4414 lc->requested_aneg = AUTONEG_ENABLE;
4416 lc->requested_aneg = AUTONEG_AUTO;
4418 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX |
4421 if (t4_fec == -1 || t4_fec & FEC_AUTO)
4422 lc->requested_fec = FEC_AUTO;
4424 lc->requested_fec = FEC_NONE;
4425 if (t4_fec & FEC_RS)
4426 lc->requested_fec |= FEC_RS;
4427 if (t4_fec & FEC_BASER_RS)
4428 lc->requested_fec |= FEC_BASER_RS;
4433 * Makes sure that all requested settings comply with what's supported by the
4434 * port. Returns the number of settings that were invalid and had to be fixed.
4437 fixup_link_config(struct port_info *pi)
4440 struct link_config *lc = &pi->link_cfg;
4443 PORT_LOCK_ASSERT_OWNED(pi);
4445 /* Speed (when not autonegotiating) */
4446 if (lc->requested_speed != 0) {
4447 fwspeed = speed_to_fwcap(lc->requested_speed);
4448 if ((fwspeed & lc->supported) == 0) {
4450 lc->requested_speed = 0;
4454 /* Link autonegotiation */
4455 MPASS(lc->requested_aneg == AUTONEG_ENABLE ||
4456 lc->requested_aneg == AUTONEG_DISABLE ||
4457 lc->requested_aneg == AUTONEG_AUTO);
4458 if (lc->requested_aneg == AUTONEG_ENABLE &&
4459 !(lc->supported & FW_PORT_CAP32_ANEG)) {
4461 lc->requested_aneg = AUTONEG_AUTO;
4465 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0);
4466 if (lc->requested_fc & PAUSE_TX &&
4467 !(lc->supported & FW_PORT_CAP32_FC_TX)) {
4469 lc->requested_fc &= ~PAUSE_TX;
4471 if (lc->requested_fc & PAUSE_RX &&
4472 !(lc->supported & FW_PORT_CAP32_FC_RX)) {
4474 lc->requested_fc &= ~PAUSE_RX;
4476 if (!(lc->requested_fc & PAUSE_AUTONEG) &&
4477 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) {
4479 lc->requested_fc |= PAUSE_AUTONEG;
4483 if ((lc->requested_fec & FEC_RS &&
4484 !(lc->supported & FW_PORT_CAP32_FEC_RS)) ||
4485 (lc->requested_fec & FEC_BASER_RS &&
4486 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) {
4488 lc->requested_fec = FEC_AUTO;
4495 * Apply the requested L1 settings, which are expected to be valid, to the
4499 apply_link_config(struct port_info *pi)
4501 struct adapter *sc = pi->adapter;
4502 struct link_config *lc = &pi->link_cfg;
4506 ASSERT_SYNCHRONIZED_OP(sc);
4507 PORT_LOCK_ASSERT_OWNED(pi);
4509 if (lc->requested_aneg == AUTONEG_ENABLE)
4510 MPASS(lc->supported & FW_PORT_CAP32_ANEG);
4511 if (!(lc->requested_fc & PAUSE_AUTONEG))
4512 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE);
4513 if (lc->requested_fc & PAUSE_TX)
4514 MPASS(lc->supported & FW_PORT_CAP32_FC_TX);
4515 if (lc->requested_fc & PAUSE_RX)
4516 MPASS(lc->supported & FW_PORT_CAP32_FC_RX);
4517 if (lc->requested_fec & FEC_RS)
4518 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS);
4519 if (lc->requested_fec & FEC_BASER_RS)
4520 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS);
4522 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
4524 /* Don't complain if the VF driver gets back an EPERM. */
4525 if (!(sc->flags & IS_VF) || rc != FW_EPERM)
4526 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
4529 * An L1_CFG will almost always result in a link-change event if
4530 * the link is up, and the driver will refresh the actual
4531 * fec/fc/etc. when the notification is processed. If the link
4532 * is down then the actual settings are meaningless.
4534 * This takes care of the case where a change in the L1 settings
4535 * may not result in a notification.
4537 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG))
4538 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX);
4543 #define FW_MAC_EXACT_CHUNK 7
4546 * Program the port's XGMAC based on parameters in ifnet. The caller also
4547 * indicates which parameters should be programmed (the rest are left alone).
4550 update_mac_settings(struct ifnet *ifp, int flags)
4553 struct vi_info *vi = ifp->if_softc;
4554 struct port_info *pi = vi->pi;
4555 struct adapter *sc = pi->adapter;
4556 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
4558 ASSERT_SYNCHRONIZED_OP(sc);
4559 KASSERT(flags, ("%s: not told what to update.", __func__));
4561 if (flags & XGMAC_MTU)
4564 if (flags & XGMAC_PROMISC)
4565 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
4567 if (flags & XGMAC_ALLMULTI)
4568 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
4570 if (flags & XGMAC_VLANEX)
4571 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
4573 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
4574 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
4575 allmulti, 1, vlanex, false);
4577 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
4583 if (flags & XGMAC_UCADDR) {
4584 uint8_t ucaddr[ETHER_ADDR_LEN];
4586 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
4587 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
4588 ucaddr, true, true);
4591 if_printf(ifp, "change_mac failed: %d\n", rc);
4594 vi->xact_addr_filt = rc;
4599 if (flags & XGMAC_MCADDRS) {
4600 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
4603 struct ifmultiaddr *ifma;
4606 if_maddr_rlock(ifp);
4607 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4608 if (ifma->ifma_addr->sa_family != AF_LINK)
4611 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
4612 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
4615 if (i == FW_MAC_EXACT_CHUNK) {
4616 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
4617 del, i, mcaddr, NULL, &hash, 0);
4620 for (j = 0; j < i; j++) {
4622 "failed to add mc address"
4624 "%02x:%02x:%02x rc=%d\n",
4625 mcaddr[j][0], mcaddr[j][1],
4626 mcaddr[j][2], mcaddr[j][3],
4627 mcaddr[j][4], mcaddr[j][5],
4637 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
4638 mcaddr, NULL, &hash, 0);
4641 for (j = 0; j < i; j++) {
4643 "failed to add mc address"
4645 "%02x:%02x:%02x rc=%d\n",
4646 mcaddr[j][0], mcaddr[j][1],
4647 mcaddr[j][2], mcaddr[j][3],
4648 mcaddr[j][4], mcaddr[j][5],
4655 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
4657 if_printf(ifp, "failed to set mc address hash: %d", rc);
4659 if_maddr_runlock(ifp);
4666 * {begin|end}_synchronized_op must be called from the same thread.
4669 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
4675 /* the caller thinks it's ok to sleep, but is it really? */
4676 if (flags & SLEEP_OK)
4677 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
4678 "begin_synchronized_op");
4689 if (vi && IS_DOOMED(vi)) {
4699 if (!(flags & SLEEP_OK)) {
4704 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
4710 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
4713 sc->last_op = wmesg;
4714 sc->last_op_thr = curthread;
4715 sc->last_op_flags = flags;
4719 if (!(flags & HOLD_LOCK) || rc)
4726 * Tell if_ioctl and if_init that the VI is going away. This is
4727 * special variant of begin_synchronized_op and must be paired with a
4728 * call to end_synchronized_op.
4731 doom_vi(struct adapter *sc, struct vi_info *vi)
4738 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
4741 sc->last_op = "t4detach";
4742 sc->last_op_thr = curthread;
4743 sc->last_op_flags = 0;
4749 * {begin|end}_synchronized_op must be called from the same thread.
4752 end_synchronized_op(struct adapter *sc, int flags)
4755 if (flags & LOCK_HELD)
4756 ADAPTER_LOCK_ASSERT_OWNED(sc);
4760 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
4767 cxgbe_init_synchronized(struct vi_info *vi)
4769 struct port_info *pi = vi->pi;
4770 struct adapter *sc = pi->adapter;
4771 struct ifnet *ifp = vi->ifp;
4773 struct sge_txq *txq;
4775 ASSERT_SYNCHRONIZED_OP(sc);
4777 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4778 return (0); /* already running */
4780 if (!(sc->flags & FULL_INIT_DONE) &&
4781 ((rc = adapter_full_init(sc)) != 0))
4782 return (rc); /* error message displayed already */
4784 if (!(vi->flags & VI_INIT_DONE) &&
4785 ((rc = vi_full_init(vi)) != 0))
4786 return (rc); /* error message displayed already */
4788 rc = update_mac_settings(ifp, XGMAC_ALL);
4790 goto done; /* error message displayed already */
4793 if (pi->up_vis == 0) {
4794 t4_update_port_info(pi);
4795 fixup_link_config(pi);
4796 build_medialist(pi);
4797 apply_link_config(pi);
4800 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4802 if_printf(ifp, "enable_vi failed: %d\n", rc);
4808 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
4812 for_each_txq(vi, i, txq) {
4814 txq->eq.flags |= EQ_ENABLED;
4819 * The first iq of the first port to come up is used for tracing.
4821 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4822 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4823 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
4824 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4825 V_QUEUENUMBER(sc->traceq));
4826 pi->flags |= HAS_TRACEQ;
4831 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4833 if (pi->nvi > 1 || sc->flags & IS_VF)
4834 callout_reset(&vi->tick, hz, vi_tick, vi);
4836 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4840 cxgbe_uninit_synchronized(vi);
4849 cxgbe_uninit_synchronized(struct vi_info *vi)
4851 struct port_info *pi = vi->pi;
4852 struct adapter *sc = pi->adapter;
4853 struct ifnet *ifp = vi->ifp;
4855 struct sge_txq *txq;
4857 ASSERT_SYNCHRONIZED_OP(sc);
4859 if (!(vi->flags & VI_INIT_DONE)) {
4860 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4861 KASSERT(0, ("uninited VI is running"));
4862 if_printf(ifp, "uninited VI with running ifnet. "
4863 "vi->flags 0x%016lx, if_flags 0x%08x, "
4864 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags,
4871 * Disable the VI so that all its data in either direction is discarded
4872 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
4873 * tick) intact as the TP can deliver negative advice or data that it's
4874 * holding in its RAM (for an offloaded connection) even after the VI is
4877 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4879 if_printf(ifp, "disable_vi failed: %d\n", rc);
4883 for_each_txq(vi, i, txq) {
4885 txq->eq.flags &= ~EQ_ENABLED;
4890 if (pi->nvi > 1 || sc->flags & IS_VF)
4891 callout_stop(&vi->tick);
4893 callout_stop(&pi->tick);
4894 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4898 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4900 if (pi->up_vis > 0) {
4905 pi->link_cfg.link_ok = false;
4906 pi->link_cfg.speed = 0;
4907 pi->link_cfg.link_down_rc = 255;
4908 t4_os_link_changed(pi);
4915 * It is ok for this function to fail midway and return right away. t4_detach
4916 * will walk the entire sc->irq list and clean up whatever is valid.
4919 t4_setup_intr_handlers(struct adapter *sc)
4921 int rc, rid, p, q, v;
4924 struct port_info *pi;
4926 struct sge *sge = &sc->sge;
4927 struct sge_rxq *rxq;
4929 struct sge_ofld_rxq *ofld_rxq;
4932 struct sge_nm_rxq *nm_rxq;
4935 int nbuckets = rss_getnumbuckets();
4942 rid = sc->intr_type == INTR_INTX ? 0 : 1;
4943 if (forwarding_intr_to_fwq(sc))
4944 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4946 /* Multiple interrupts. */
4947 if (sc->flags & IS_VF)
4948 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4949 ("%s: too few intr.", __func__));
4951 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4952 ("%s: too few intr.", __func__));
4954 /* The first one is always error intr on PFs */
4955 if (!(sc->flags & IS_VF)) {
4956 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4963 /* The second one is always the firmware event queue (first on VFs) */
4964 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4970 for_each_port(sc, p) {
4972 for_each_vi(pi, v, vi) {
4973 vi->first_intr = rid - 1;
4975 if (vi->nnmrxq > 0) {
4976 int n = max(vi->nrxq, vi->nnmrxq);
4978 rxq = &sge->rxq[vi->first_rxq];
4980 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4982 for (q = 0; q < n; q++) {
4983 snprintf(s, sizeof(s), "%x%c%x", p,
4989 irq->nm_rxq = nm_rxq++;
4991 if (irq->nm_rxq != NULL &&
4993 /* Netmap rx only */
4994 rc = t4_alloc_irq(sc, irq, rid,
4995 t4_nm_intr, irq->nm_rxq, s);
4997 if (irq->nm_rxq != NULL &&
4999 /* NIC and Netmap rx */
5000 rc = t4_alloc_irq(sc, irq, rid,
5001 t4_vi_intr, irq, s);
5004 if (irq->rxq != NULL &&
5005 irq->nm_rxq == NULL) {
5007 rc = t4_alloc_irq(sc, irq, rid,
5008 t4_intr, irq->rxq, s);
5014 bus_bind_intr(sc->dev, irq->res,
5015 rss_getcpu(q % nbuckets));
5023 for_each_rxq(vi, q, rxq) {
5024 snprintf(s, sizeof(s), "%x%c%x", p,
5026 rc = t4_alloc_irq(sc, irq, rid,
5031 bus_bind_intr(sc->dev, irq->res,
5032 rss_getcpu(q % nbuckets));
5040 for_each_ofld_rxq(vi, q, ofld_rxq) {
5041 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q);
5042 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
5053 MPASS(irq == &sc->irq[sc->intr_count]);
5059 adapter_full_init(struct adapter *sc)
5063 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5064 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
5067 ASSERT_SYNCHRONIZED_OP(sc);
5068 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5069 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
5070 ("%s: FULL_INIT_DONE already", __func__));
5073 * queues that belong to the adapter (not any particular port).
5075 rc = t4_setup_adapter_queues(sc);
5079 for (i = 0; i < nitems(sc->tq); i++) {
5080 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
5081 taskqueue_thread_enqueue, &sc->tq[i]);
5082 if (sc->tq[i] == NULL) {
5083 device_printf(sc->dev,
5084 "failed to allocate task queue %d\n", i);
5088 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
5089 device_get_nameunit(sc->dev), i);
5092 MPASS(RSS_KEYSIZE == 40);
5093 rss_getkey((void *)&raw_rss_key[0]);
5094 for (i = 0; i < nitems(rss_key); i++) {
5095 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
5097 t4_write_rss_key(sc, &rss_key[0], -1, 1);
5100 if (!(sc->flags & IS_VF))
5102 sc->flags |= FULL_INIT_DONE;
5105 adapter_full_uninit(sc);
5111 adapter_full_uninit(struct adapter *sc)
5115 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
5117 t4_teardown_adapter_queues(sc);
5119 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
5120 taskqueue_free(sc->tq[i]);
5124 sc->flags &= ~FULL_INIT_DONE;
5130 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
5131 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
5132 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
5133 RSS_HASHTYPE_RSS_UDP_IPV6)
5135 /* Translates kernel hash types to hardware. */
5137 hashconfig_to_hashen(int hashconfig)
5141 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
5142 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
5143 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
5144 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
5145 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
5146 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5147 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5149 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
5150 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
5151 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5153 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
5154 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
5155 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
5156 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
5161 /* Translates hardware hash types to kernel. */
5163 hashen_to_hashconfig(int hashen)
5167 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
5169 * If UDP hashing was enabled it must have been enabled for
5170 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
5171 * enabling any 4-tuple hash is nonsense configuration.
5173 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5174 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
5176 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5177 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
5178 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5179 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
5181 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
5182 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
5183 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
5184 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
5185 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
5186 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
5187 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
5188 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
5190 return (hashconfig);
5195 vi_full_init(struct vi_info *vi)
5197 struct adapter *sc = vi->pi->adapter;
5198 struct ifnet *ifp = vi->ifp;
5200 struct sge_rxq *rxq;
5203 int nbuckets = rss_getnumbuckets();
5204 int hashconfig = rss_gethashconfig();
5208 ASSERT_SYNCHRONIZED_OP(sc);
5209 KASSERT((vi->flags & VI_INIT_DONE) == 0,
5210 ("%s: VI_INIT_DONE already", __func__));
5212 sysctl_ctx_init(&vi->ctx);
5213 vi->flags |= VI_SYSCTL_CTX;
5216 * Allocate tx/rx/fl queues for this VI.
5218 rc = t4_setup_vi_queues(vi);
5220 goto done; /* error message displayed already */
5223 * Setup RSS for this VI. Save a copy of the RSS table for later use.
5225 if (vi->nrxq > vi->rss_size) {
5226 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
5227 "some queues will never receive traffic.\n", vi->nrxq,
5229 } else if (vi->rss_size % vi->nrxq) {
5230 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
5231 "expect uneven traffic distribution.\n", vi->nrxq,
5235 if (vi->nrxq != nbuckets) {
5236 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
5237 "performance will be impacted.\n", vi->nrxq, nbuckets);
5240 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
5241 for (i = 0; i < vi->rss_size;) {
5243 j = rss_get_indirection_to_bucket(i);
5245 rxq = &sc->sge.rxq[vi->first_rxq + j];
5246 rss[i++] = rxq->iq.abs_id;
5248 for_each_rxq(vi, j, rxq) {
5249 rss[i++] = rxq->iq.abs_id;
5250 if (i == vi->rss_size)
5256 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
5260 if_printf(ifp, "rss_config failed: %d\n", rc);
5265 vi->hashen = hashconfig_to_hashen(hashconfig);
5268 * We may have had to enable some hashes even though the global config
5269 * wants them disabled. This is a potential problem that must be
5270 * reported to the user.
5272 extra = hashen_to_hashconfig(vi->hashen) ^ hashconfig;
5275 * If we consider only the supported hash types, then the enabled hashes
5276 * are a superset of the requested hashes. In other words, there cannot
5277 * be any supported hash that was requested but not enabled, but there
5278 * can be hashes that were not requested but had to be enabled.
5280 extra &= SUPPORTED_RSS_HASHTYPES;
5281 MPASS((extra & hashconfig) == 0);
5285 "global RSS config (0x%x) cannot be accommodated.\n",
5288 if (extra & RSS_HASHTYPE_RSS_IPV4)
5289 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
5290 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
5291 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
5292 if (extra & RSS_HASHTYPE_RSS_IPV6)
5293 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
5294 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
5295 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
5296 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
5297 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
5298 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
5299 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
5301 vi->hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
5302 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
5303 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
5304 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
5306 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, rss[0], 0, 0);
5309 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
5314 vi->flags |= VI_INIT_DONE;
5326 vi_full_uninit(struct vi_info *vi)
5328 struct port_info *pi = vi->pi;
5329 struct adapter *sc = pi->adapter;
5331 struct sge_rxq *rxq;
5332 struct sge_txq *txq;
5334 struct sge_ofld_rxq *ofld_rxq;
5335 struct sge_wrq *ofld_txq;
5338 if (vi->flags & VI_INIT_DONE) {
5340 /* Need to quiesce queues. */
5342 /* XXX: Only for the first VI? */
5343 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
5344 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
5346 for_each_txq(vi, i, txq) {
5347 quiesce_txq(sc, txq);
5351 for_each_ofld_txq(vi, i, ofld_txq) {
5352 quiesce_wrq(sc, ofld_txq);
5356 for_each_rxq(vi, i, rxq) {
5357 quiesce_iq(sc, &rxq->iq);
5358 quiesce_fl(sc, &rxq->fl);
5362 for_each_ofld_rxq(vi, i, ofld_rxq) {
5363 quiesce_iq(sc, &ofld_rxq->iq);
5364 quiesce_fl(sc, &ofld_rxq->fl);
5367 free(vi->rss, M_CXGBE);
5368 free(vi->nm_rss, M_CXGBE);
5371 t4_teardown_vi_queues(vi);
5372 vi->flags &= ~VI_INIT_DONE;
5378 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
5380 struct sge_eq *eq = &txq->eq;
5381 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5383 (void) sc; /* unused */
5387 MPASS((eq->flags & EQ_ENABLED) == 0);
5391 /* Wait for the mp_ring to empty. */
5392 while (!mp_ring_is_idle(txq->r)) {
5393 mp_ring_check_drainage(txq->r, 0);
5394 pause("rquiesce", 1);
5397 /* Then wait for the hardware to finish. */
5398 while (spg->cidx != htobe16(eq->pidx))
5399 pause("equiesce", 1);
5401 /* Finally, wait for the driver to reclaim all descriptors. */
5402 while (eq->cidx != eq->pidx)
5403 pause("dquiesce", 1);
5407 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
5414 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
5416 (void) sc; /* unused */
5418 /* Synchronize with the interrupt handler */
5419 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
5424 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
5426 mtx_lock(&sc->sfl_lock);
5428 fl->flags |= FL_DOOMED;
5430 callout_stop(&sc->sfl_callout);
5431 mtx_unlock(&sc->sfl_lock);
5433 KASSERT((fl->flags & FL_STARVING) == 0,
5434 ("%s: still starving", __func__));
5438 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
5439 driver_intr_t *handler, void *arg, char *name)
5444 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
5445 RF_SHAREABLE | RF_ACTIVE);
5446 if (irq->res == NULL) {
5447 device_printf(sc->dev,
5448 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
5452 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
5453 NULL, handler, arg, &irq->tag);
5455 device_printf(sc->dev,
5456 "failed to setup interrupt for rid %d, name %s: %d\n",
5459 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name);
5465 t4_free_irq(struct adapter *sc, struct irq *irq)
5468 bus_teardown_intr(sc->dev, irq->res, irq->tag);
5470 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
5472 bzero(irq, sizeof(*irq));
5478 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
5481 regs->version = chip_id(sc) | chip_rev(sc) << 10;
5482 t4_get_regs(sc, buf, regs->len);
5485 #define A_PL_INDIR_CMD 0x1f8
5487 #define S_PL_AUTOINC 31
5488 #define M_PL_AUTOINC 0x1U
5489 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
5490 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
5492 #define S_PL_VFID 20
5493 #define M_PL_VFID 0xffU
5494 #define V_PL_VFID(x) ((x) << S_PL_VFID)
5495 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
5498 #define M_PL_ADDR 0xfffffU
5499 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
5500 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
5502 #define A_PL_INDIR_DATA 0x1fc
5505 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
5509 mtx_assert(&sc->reg_lock, MA_OWNED);
5510 if (sc->flags & IS_VF) {
5511 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
5512 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
5514 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5515 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5516 V_PL_ADDR(VF_MPS_REG(reg)));
5517 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
5518 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
5520 return (((uint64_t)stats[1]) << 32 | stats[0]);
5524 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
5525 struct fw_vi_stats_vf *stats)
5528 #define GET_STAT(name) \
5529 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
5531 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
5532 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
5533 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
5534 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
5535 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
5536 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
5537 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
5538 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
5539 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
5540 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
5541 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
5542 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
5543 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
5544 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
5545 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
5546 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
5552 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
5556 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
5557 V_PL_VFID(G_FW_VIID_VIN(viid)) |
5558 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
5559 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
5560 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
5561 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
5565 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
5568 const struct timeval interval = {0, 250000}; /* 250ms */
5570 if (!(vi->flags & VI_INIT_DONE))
5574 timevalsub(&tv, &interval);
5575 if (timevalcmp(&tv, &vi->last_refreshed, <))
5578 mtx_lock(&sc->reg_lock);
5579 t4_get_vi_stats(sc, vi->viid, &vi->stats);
5580 getmicrotime(&vi->last_refreshed);
5581 mtx_unlock(&sc->reg_lock);
5585 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
5587 u_int i, v, tnl_cong_drops, bg_map;
5589 const struct timeval interval = {0, 250000}; /* 250ms */
5592 timevalsub(&tv, &interval);
5593 if (timevalcmp(&tv, &pi->last_refreshed, <))
5597 t4_get_port_stats(sc, pi->tx_chan, &pi->stats);
5598 bg_map = pi->mps_bg_map;
5600 i = ffs(bg_map) - 1;
5601 mtx_lock(&sc->reg_lock);
5602 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1,
5603 A_TP_MIB_TNL_CNG_DROP_0 + i);
5604 mtx_unlock(&sc->reg_lock);
5605 tnl_cong_drops += v;
5606 bg_map &= ~(1 << i);
5608 pi->tnl_cong_drops = tnl_cong_drops;
5609 getmicrotime(&pi->last_refreshed);
5613 cxgbe_tick(void *arg)
5615 struct port_info *pi = arg;
5616 struct adapter *sc = pi->adapter;
5618 PORT_LOCK_ASSERT_OWNED(pi);
5619 cxgbe_refresh_stats(sc, pi);
5621 callout_schedule(&pi->tick, hz);
5627 struct vi_info *vi = arg;
5628 struct adapter *sc = vi->pi->adapter;
5630 vi_refresh_stats(sc, vi);
5632 callout_schedule(&vi->tick, hz);
5636 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
5638 static char *caps_decoder[] = {
5639 "\20\001IPMI\002NCSI", /* 0: NBM */
5640 "\20\001PPP\002QFC\003DCBX", /* 1: link */
5641 "\20\001INGRESS\002EGRESS", /* 2: switch */
5642 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
5643 "\006HASHFILTER\007ETHOFLD",
5644 "\20\001TOE", /* 4: TOE */
5645 "\20\001RDDP\002RDMAC", /* 5: RDMA */
5646 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
5647 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
5648 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
5650 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
5651 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
5652 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
5653 "\004PO_INITIATOR\005PO_TARGET",
5657 t4_sysctls(struct adapter *sc)
5659 struct sysctl_ctx_list *ctx;
5660 struct sysctl_oid *oid;
5661 struct sysctl_oid_list *children, *c0;
5662 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
5664 ctx = device_get_sysctl_ctx(sc->dev);
5669 oid = device_get_sysctl_tree(sc->dev);
5670 c0 = children = SYSCTL_CHILDREN(oid);
5672 sc->sc_do_rxcopy = 1;
5673 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
5674 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
5676 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
5677 sc->params.nports, "# of ports");
5679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
5680 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells,
5681 sysctl_bitfield_8b, "A", "available doorbells");
5683 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
5684 sc->params.vpd.cclk, "core clock frequency (in KHz)");
5686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
5687 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
5688 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
5689 "interrupt holdoff timer values (us)");
5691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
5692 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
5693 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
5694 "interrupt holdoff packet counter values");
5696 t4_sge_sysctls(sc, ctx, children);
5698 sc->lro_timeout = 100;
5699 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
5700 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
5702 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
5703 &sc->debug_flags, 0, "flags to enable runtime debugging");
5705 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
5706 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
5708 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
5709 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
5711 if (sc->flags & IS_VF)
5714 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
5715 NULL, chip_rev(sc), "chip hardware revision");
5717 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
5718 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
5720 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
5721 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
5723 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
5724 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
5726 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version",
5727 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version");
5729 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
5730 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
5732 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
5733 sc->er_version, 0, "expansion ROM version");
5735 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
5736 sc->bs_version, 0, "bootstrap firmware version");
5738 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
5739 NULL, sc->params.scfg_vers, "serial config version");
5741 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
5742 NULL, sc->params.vpd_vers, "VPD version");
5744 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
5745 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
5747 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
5748 sc->cfcsum, "config file checksum");
5750 #define SYSCTL_CAP(name, n, text) \
5751 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
5752 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \
5753 sysctl_bitfield_16b, "A", "available " text " capabilities")
5755 SYSCTL_CAP(nbmcaps, 0, "NBM");
5756 SYSCTL_CAP(linkcaps, 1, "link");
5757 SYSCTL_CAP(switchcaps, 2, "switch");
5758 SYSCTL_CAP(niccaps, 3, "NIC");
5759 SYSCTL_CAP(toecaps, 4, "TCP offload");
5760 SYSCTL_CAP(rdmacaps, 5, "RDMA");
5761 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5762 SYSCTL_CAP(cryptocaps, 7, "crypto");
5763 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5766 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5767 NULL, sc->tids.nftids, "number of filters");
5769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5770 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5771 "chip temperature (in Celsius)");
5773 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING |
5774 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A",
5775 "microprocessor load averages (debug firmwares only)");
5777 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD,
5778 &sc->params.core_vdd, 0, "core Vdd (in mV)");
5780 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus",
5781 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS,
5782 sysctl_cpus, "A", "local CPUs");
5784 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus",
5785 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS,
5786 sysctl_cpus, "A", "preferred CPUs for interrupts");
5789 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5791 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5792 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5793 "logs and miscellaneous information");
5794 children = SYSCTL_CHILDREN(oid);
5796 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5797 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5798 sysctl_cctrl, "A", "congestion control");
5800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5801 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5802 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5804 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5805 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5806 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5809 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5810 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5812 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5813 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5814 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5816 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5817 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5818 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5820 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5821 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5822 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5824 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5825 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5826 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5827 "A", "CIM logic analyzer");
5829 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5830 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5831 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5833 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5834 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5835 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5837 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5838 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5839 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5841 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5842 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5843 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5846 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5847 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5850 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5851 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5853 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5854 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5855 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5857 if (chip_id(sc) > CHELSIO_T4) {
5858 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5859 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5860 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5862 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5863 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5864 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5867 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5868 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5869 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5872 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5873 sysctl_cim_qcfg, "A", "CIM queue configuration");
5875 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5876 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5877 sysctl_cpl_stats, "A", "CPL statistics");
5879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5880 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5881 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5884 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5885 sysctl_devlog, "A", "firmware's device log");
5887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5888 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5889 sysctl_fcoe_stats, "A", "FCoE statistics");
5891 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5892 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5893 sysctl_hw_sched, "A", "hardware scheduler ");
5895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5896 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5897 sysctl_l2t, "A", "hardware L2 table");
5899 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt",
5900 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5901 sysctl_smt, "A", "hardware source MAC table");
5903 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5904 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5905 sysctl_lb_stats, "A", "loopback statistics");
5907 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5908 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5909 sysctl_meminfo, "A", "memory regions");
5911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5912 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5913 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5914 "A", "MPS TCAM entries");
5916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5917 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5918 sysctl_path_mtus, "A", "path MTUs");
5920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5921 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5922 sysctl_pm_stats, "A", "PM statistics");
5924 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5925 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5926 sysctl_rdma_stats, "A", "RDMA statistics");
5928 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5929 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5930 sysctl_tcp_stats, "A", "TCP statistics");
5932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5933 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5934 sysctl_tids, "A", "TID information");
5936 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5937 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5938 sysctl_tp_err_stats, "A", "TP error statistics");
5940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5941 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5942 "TP logic analyzer event capture mask");
5944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5945 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5946 sysctl_tp_la, "A", "TP logic analyzer");
5948 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5949 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5950 sysctl_tx_rate, "A", "Tx rate");
5952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5953 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5954 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5956 if (chip_id(sc) >= CHELSIO_T5) {
5957 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5958 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5959 sysctl_wcwr_stats, "A", "write combined work requests");
5963 if (is_offload(sc)) {
5970 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5971 NULL, "TOE parameters");
5972 children = SYSCTL_CHILDREN(oid);
5974 sc->tt.cong_algorithm = -1;
5975 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm",
5976 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control "
5977 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, "
5980 sc->tt.sndbuf = 256 * 1024;
5981 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5982 &sc->tt.sndbuf, 0, "max hardware send buffer size");
5985 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5986 &sc->tt.ddp, 0, "DDP allowed");
5988 sc->tt.rx_coalesce = 1;
5989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5990 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5993 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW,
5994 &sc->tt.tls, 0, "Inline TLS allowed");
5996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports",
5997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports,
5998 "I", "TCP ports that use inline TLS+TOE RX");
6000 sc->tt.tx_align = 1;
6001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
6002 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
6004 sc->tt.tx_zcopy = 0;
6005 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy",
6006 CTLFLAG_RW, &sc->tt.tx_zcopy, 0,
6007 "Enable zero-copy aio_write(2)");
6009 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading;
6010 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6011 "cop_managed_offloading", CTLFLAG_RW,
6012 &sc->tt.cop_managed_offloading, 0,
6013 "COP (Connection Offload Policy) controls all TOE offload");
6015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
6016 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
6017 "TP timer tick (us)");
6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
6020 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
6021 "TCP timestamp tick (us)");
6023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
6024 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
6027 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
6028 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
6029 "IU", "DACK timer (us)");
6031 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
6032 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
6033 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)");
6035 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
6036 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
6037 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)");
6039 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
6040 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
6041 sysctl_tp_timer, "LU", "Persist timer min (us)");
6043 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
6044 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
6045 sysctl_tp_timer, "LU", "Persist timer max (us)");
6047 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
6048 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
6049 sysctl_tp_timer, "LU", "Keepalive idle timer (us)");
6051 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval",
6052 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
6053 sysctl_tp_timer, "LU", "Keepalive interval timer (us)");
6055 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
6056 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
6057 sysctl_tp_timer, "LU", "Initial SRTT (us)");
6059 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
6060 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
6061 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
6063 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count",
6064 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX,
6065 sysctl_tp_shift_cnt, "IU",
6066 "Number of SYN retransmissions before abort");
6068 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count",
6069 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2,
6070 sysctl_tp_shift_cnt, "IU",
6071 "Number of retransmissions before abort");
6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count",
6074 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2,
6075 sysctl_tp_shift_cnt, "IU",
6076 "Number of keepalive probes before abort");
6078 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff",
6079 CTLFLAG_RD, NULL, "TOE retransmit backoffs");
6080 children = SYSCTL_CHILDREN(oid);
6081 for (i = 0; i < 16; i++) {
6082 snprintf(s, sizeof(s), "%u", i);
6083 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s,
6084 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff,
6085 "IU", "TOE retransmit backoff");
6092 vi_sysctls(struct vi_info *vi)
6094 struct sysctl_ctx_list *ctx;
6095 struct sysctl_oid *oid;
6096 struct sysctl_oid_list *children;
6098 ctx = device_get_sysctl_ctx(vi->dev);
6101 * dev.v?(cxgbe|cxl).X.
6103 oid = device_get_sysctl_tree(vi->dev);
6104 children = SYSCTL_CHILDREN(oid);
6106 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
6107 vi->viid, "VI identifer");
6108 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
6109 &vi->nrxq, 0, "# of rx queues");
6110 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
6111 &vi->ntxq, 0, "# of tx queues");
6112 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
6113 &vi->first_rxq, 0, "index of first rx queue");
6114 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
6115 &vi->first_txq, 0, "index of first tx queue");
6116 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_base", CTLFLAG_RD, NULL,
6117 vi->rss_base, "start of RSS indirection table");
6118 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
6119 vi->rss_size, "size of RSS indirection table");
6121 if (IS_MAIN_VI(vi)) {
6122 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
6123 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
6124 "Reserve queue 0 for non-flowid packets");
6128 if (vi->nofldrxq != 0) {
6129 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
6131 "# of rx queues for offloaded TCP connections");
6132 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
6134 "# of tx queues for offloaded TCP connections");
6135 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
6136 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
6137 "index of first TOE rx queue");
6138 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
6139 CTLFLAG_RD, &vi->first_ofld_txq, 0,
6140 "index of first TOE tx queue");
6141 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld",
6142 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6143 sysctl_holdoff_tmr_idx_ofld, "I",
6144 "holdoff timer index for TOE queues");
6145 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld",
6146 CTLTYPE_INT | CTLFLAG_RW, vi, 0,
6147 sysctl_holdoff_pktc_idx_ofld, "I",
6148 "holdoff packet counter index for TOE queues");
6152 if (vi->nnmrxq != 0) {
6153 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
6154 &vi->nnmrxq, 0, "# of netmap rx queues");
6155 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
6156 &vi->nnmtxq, 0, "# of netmap tx queues");
6157 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
6158 CTLFLAG_RD, &vi->first_nm_rxq, 0,
6159 "index of first netmap rx queue");
6160 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
6161 CTLFLAG_RD, &vi->first_nm_txq, 0,
6162 "index of first netmap tx queue");
6166 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
6167 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
6168 "holdoff timer index");
6169 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
6170 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
6171 "holdoff packet counter index");
6173 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
6174 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
6176 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
6177 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
6182 cxgbe_sysctls(struct port_info *pi)
6184 struct sysctl_ctx_list *ctx;
6185 struct sysctl_oid *oid;
6186 struct sysctl_oid_list *children, *children2;
6187 struct adapter *sc = pi->adapter;
6190 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"};
6192 ctx = device_get_sysctl_ctx(pi->dev);
6197 oid = device_get_sysctl_tree(pi->dev);
6198 children = SYSCTL_CHILDREN(oid);
6200 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
6201 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
6202 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
6203 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
6204 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
6205 "PHY temperature (in Celsius)");
6206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
6207 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
6208 "PHY firmware version");
6211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
6212 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
6213 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
6214 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
6215 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
6216 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
6217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
6218 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
6219 "autonegotiation (-1 = not supported)");
6221 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
6222 port_top_speed(pi), "max speed (in Gbps)");
6223 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL,
6224 pi->mps_bg_map, "MPS buffer group map");
6225 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD,
6226 NULL, pi->rx_e_chan_map, "TP rx e-channel map");
6228 if (sc->flags & IS_VF)
6232 * dev.(cxgbe|cxl).X.tc.
6234 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
6235 "Tx scheduler traffic classes (cl_rl)");
6236 children2 = SYSCTL_CHILDREN(oid);
6237 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize",
6238 CTLFLAG_RW, &pi->sched_params->pktsize, 0,
6239 "pktsize for per-flow cl-rl (0 means up to the driver )");
6240 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize",
6241 CTLFLAG_RW, &pi->sched_params->burstsize, 0,
6242 "burstsize for per-flow cl-rl (0 means up to the driver)");
6243 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
6244 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
6246 snprintf(name, sizeof(name), "%d", i);
6247 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
6248 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
6250 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags",
6251 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags,
6252 sysctl_bitfield_8b, "A", "flags");
6253 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
6254 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
6255 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
6256 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
6257 sysctl_tc_params, "A", "traffic class parameters");
6261 * dev.cxgbe.X.stats.
6263 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
6264 NULL, "port statistics");
6265 children = SYSCTL_CHILDREN(oid);
6266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
6267 &pi->tx_parse_error, 0,
6268 "# of tx packets with invalid length or # of segments");
6270 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
6271 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
6272 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
6273 sysctl_handle_t4_reg64, "QU", desc)
6275 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
6276 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
6277 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
6278 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
6279 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
6280 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
6281 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
6282 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
6283 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
6284 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
6285 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
6286 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
6287 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
6288 "# of tx frames in this range",
6289 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
6290 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
6291 "# of tx frames in this range",
6292 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
6293 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
6294 "# of tx frames in this range",
6295 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
6296 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
6297 "# of tx frames in this range",
6298 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
6299 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
6300 "# of tx frames in this range",
6301 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
6302 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
6303 "# of tx frames in this range",
6304 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
6305 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
6306 "# of tx frames in this range",
6307 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
6308 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
6309 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
6310 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
6311 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
6312 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
6313 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
6314 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
6315 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
6316 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
6317 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
6318 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
6319 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
6320 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
6321 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
6322 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
6323 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
6324 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
6325 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
6326 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
6327 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
6329 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
6330 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
6331 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
6332 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
6333 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
6334 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
6335 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
6336 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
6337 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
6338 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
6339 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
6340 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
6341 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
6342 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
6343 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
6344 "# of frames received with bad FCS",
6345 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
6346 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
6347 "# of frames received with length error",
6348 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
6349 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
6350 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
6351 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
6352 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
6353 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
6354 "# of rx frames in this range",
6355 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
6356 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
6357 "# of rx frames in this range",
6358 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
6359 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
6360 "# of rx frames in this range",
6361 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
6362 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
6363 "# of rx frames in this range",
6364 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
6365 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
6366 "# of rx frames in this range",
6367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
6368 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
6369 "# of rx frames in this range",
6370 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
6371 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
6372 "# of rx frames in this range",
6373 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
6374 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
6375 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
6376 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
6377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
6378 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
6379 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
6380 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
6381 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
6382 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
6383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
6384 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
6385 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
6386 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
6387 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
6388 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
6389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
6390 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
6391 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
6393 #undef SYSCTL_ADD_T4_REG64
6395 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
6396 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
6397 &pi->stats.name, desc)
6399 /* We get these from port_stats and they may be stale by up to 1s */
6400 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
6401 "# drops due to buffer-group 0 overflows");
6402 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
6403 "# drops due to buffer-group 1 overflows");
6404 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
6405 "# drops due to buffer-group 2 overflows");
6406 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
6407 "# drops due to buffer-group 3 overflows");
6408 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
6409 "# of buffer-group 0 truncated packets");
6410 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
6411 "# of buffer-group 1 truncated packets");
6412 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
6413 "# of buffer-group 2 truncated packets");
6414 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
6415 "# of buffer-group 3 truncated packets");
6417 #undef SYSCTL_ADD_T4_PORTSTAT
6419 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records",
6420 CTLFLAG_RD, &pi->tx_tls_records,
6421 "# of TLS records transmitted");
6422 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets",
6423 CTLFLAG_RD, &pi->tx_tls_octets,
6424 "# of payload octets in transmitted TLS records");
6425 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records",
6426 CTLFLAG_RD, &pi->rx_tls_records,
6427 "# of TLS records received");
6428 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets",
6429 CTLFLAG_RD, &pi->rx_tls_octets,
6430 "# of payload octets in received TLS records");
6434 sysctl_int_array(SYSCTL_HANDLER_ARGS)
6436 int rc, *i, space = 0;
6439 sbuf_new_for_sysctl(&sb, NULL, 64, req);
6440 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
6442 sbuf_printf(&sb, " ");
6443 sbuf_printf(&sb, "%d", *i);
6446 rc = sbuf_finish(&sb);
6452 sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS)
6457 rc = sysctl_wire_old_buffer(req, 0);
6461 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6465 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1);
6466 rc = sbuf_finish(sb);
6473 sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS)
6478 rc = sysctl_wire_old_buffer(req, 0);
6482 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6486 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1);
6487 rc = sbuf_finish(sb);
6494 sysctl_btphy(SYSCTL_HANDLER_ARGS)
6496 struct port_info *pi = arg1;
6498 struct adapter *sc = pi->adapter;
6502 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
6505 /* XXX: magic numbers */
6506 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
6508 end_synchronized_op(sc, 0);
6514 rc = sysctl_handle_int(oidp, &v, 0, req);
6519 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
6521 struct vi_info *vi = arg1;
6524 val = vi->rsrv_noflowq;
6525 rc = sysctl_handle_int(oidp, &val, 0, req);
6526 if (rc != 0 || req->newptr == NULL)
6529 if ((val >= 1) && (vi->ntxq > 1))
6530 vi->rsrv_noflowq = 1;
6532 vi->rsrv_noflowq = 0;
6538 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
6540 struct vi_info *vi = arg1;
6541 struct adapter *sc = vi->pi->adapter;
6543 struct sge_rxq *rxq;
6548 rc = sysctl_handle_int(oidp, &idx, 0, req);
6549 if (rc != 0 || req->newptr == NULL)
6552 if (idx < 0 || idx >= SGE_NTIMERS)
6555 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6560 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
6561 for_each_rxq(vi, i, rxq) {
6562 #ifdef atomic_store_rel_8
6563 atomic_store_rel_8(&rxq->iq.intr_params, v);
6565 rxq->iq.intr_params = v;
6570 end_synchronized_op(sc, LOCK_HELD);
6575 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
6577 struct vi_info *vi = arg1;
6578 struct adapter *sc = vi->pi->adapter;
6583 rc = sysctl_handle_int(oidp, &idx, 0, req);
6584 if (rc != 0 || req->newptr == NULL)
6587 if (idx < -1 || idx >= SGE_NCOUNTERS)
6590 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6595 if (vi->flags & VI_INIT_DONE)
6596 rc = EBUSY; /* cannot be changed once the queues are created */
6600 end_synchronized_op(sc, LOCK_HELD);
6605 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
6607 struct vi_info *vi = arg1;
6608 struct adapter *sc = vi->pi->adapter;
6611 qsize = vi->qsize_rxq;
6613 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6614 if (rc != 0 || req->newptr == NULL)
6617 if (qsize < 128 || (qsize & 7))
6620 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6625 if (vi->flags & VI_INIT_DONE)
6626 rc = EBUSY; /* cannot be changed once the queues are created */
6628 vi->qsize_rxq = qsize;
6630 end_synchronized_op(sc, LOCK_HELD);
6635 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
6637 struct vi_info *vi = arg1;
6638 struct adapter *sc = vi->pi->adapter;
6641 qsize = vi->qsize_txq;
6643 rc = sysctl_handle_int(oidp, &qsize, 0, req);
6644 if (rc != 0 || req->newptr == NULL)
6647 if (qsize < 128 || qsize > 65536)
6650 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
6655 if (vi->flags & VI_INIT_DONE)
6656 rc = EBUSY; /* cannot be changed once the queues are created */
6658 vi->qsize_txq = qsize;
6660 end_synchronized_op(sc, LOCK_HELD);
6665 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
6667 struct port_info *pi = arg1;
6668 struct adapter *sc = pi->adapter;
6669 struct link_config *lc = &pi->link_cfg;
6672 if (req->newptr == NULL) {
6674 static char *bits = "\20\1RX\2TX\3AUTO";
6676 rc = sysctl_wire_old_buffer(req, 0);
6680 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6685 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) |
6686 (lc->requested_fc & PAUSE_AUTONEG), bits);
6688 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX |
6689 PAUSE_RX | PAUSE_AUTONEG), bits);
6691 rc = sbuf_finish(sb);
6697 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX |
6701 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6707 if (s[0] < '0' || s[0] > '9')
6708 return (EINVAL); /* not a number */
6710 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG))
6711 return (EINVAL); /* some other bit is set too */
6713 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6718 lc->requested_fc = n;
6719 fixup_link_config(pi);
6721 rc = apply_link_config(pi);
6722 set_current_media(pi);
6724 end_synchronized_op(sc, 0);
6731 sysctl_fec(SYSCTL_HANDLER_ARGS)
6733 struct port_info *pi = arg1;
6734 struct adapter *sc = pi->adapter;
6735 struct link_config *lc = &pi->link_cfg;
6739 if (req->newptr == NULL) {
6741 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO";
6743 rc = sysctl_wire_old_buffer(req, 0);
6747 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6752 * Display the requested_fec when the link is down -- the actual
6753 * FEC makes sense only when the link is up.
6756 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) |
6757 (lc->requested_fec & FEC_AUTO), bits);
6759 sbuf_printf(sb, "%b", lc->requested_fec, bits);
6761 rc = sbuf_finish(sb);
6767 snprintf(s, sizeof(s), "%d",
6768 lc->requested_fec == FEC_AUTO ? -1 :
6769 lc->requested_fec & M_FW_PORT_CAP32_FEC);
6771 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
6775 n = strtol(&s[0], NULL, 0);
6776 if (n < 0 || n & FEC_AUTO)
6779 if (n & ~M_FW_PORT_CAP32_FEC)
6780 return (EINVAL);/* some other bit is set too */
6782 return (EINVAL);/* one bit can be set at most */
6785 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6790 old = lc->requested_fec;
6792 lc->requested_fec = FEC_AUTO;
6794 lc->requested_fec = FEC_NONE;
6796 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) !=
6801 lc->requested_fec = n;
6803 fixup_link_config(pi);
6804 if (pi->up_vis > 0) {
6805 rc = apply_link_config(pi);
6807 lc->requested_fec = old;
6808 if (rc == FW_EPROTO)
6814 end_synchronized_op(sc, 0);
6821 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
6823 struct port_info *pi = arg1;
6824 struct adapter *sc = pi->adapter;
6825 struct link_config *lc = &pi->link_cfg;
6828 if (lc->supported & FW_PORT_CAP32_ANEG)
6829 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1;
6832 rc = sysctl_handle_int(oidp, &val, 0, req);
6833 if (rc != 0 || req->newptr == NULL)
6836 val = AUTONEG_DISABLE;
6838 val = AUTONEG_ENABLE;
6842 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
6847 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) {
6851 lc->requested_aneg = val;
6852 fixup_link_config(pi);
6854 rc = apply_link_config(pi);
6855 set_current_media(pi);
6858 end_synchronized_op(sc, 0);
6863 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
6865 struct adapter *sc = arg1;
6869 val = t4_read_reg64(sc, reg);
6871 return (sysctl_handle_64(oidp, &val, 0, req));
6875 sysctl_temperature(SYSCTL_HANDLER_ARGS)
6877 struct adapter *sc = arg1;
6879 uint32_t param, val;
6881 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
6884 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6885 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
6886 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
6887 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6888 end_synchronized_op(sc, 0);
6892 /* unknown is returned as 0 but we display -1 in that case */
6893 t = val == 0 ? -1 : val;
6895 rc = sysctl_handle_int(oidp, &t, 0, req);
6900 sysctl_loadavg(SYSCTL_HANDLER_ARGS)
6902 struct adapter *sc = arg1;
6905 uint32_t param, val;
6907 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
6910 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
6911 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
6912 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6913 end_synchronized_op(sc, 0);
6917 rc = sysctl_wire_old_buffer(req, 0);
6921 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6925 if (val == 0xffffffff) {
6926 /* Only debug and custom firmwares report load averages. */
6927 sbuf_printf(sb, "not available");
6929 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff,
6930 (val >> 16) & 0xff);
6932 rc = sbuf_finish(sb);
6939 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6941 struct adapter *sc = arg1;
6944 uint16_t incr[NMTUS][NCCTRL_WIN];
6945 static const char *dec_fac[] = {
6946 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6950 rc = sysctl_wire_old_buffer(req, 0);
6954 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6958 t4_read_cong_tbl(sc, incr);
6960 for (i = 0; i < NCCTRL_WIN; ++i) {
6961 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6962 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6963 incr[5][i], incr[6][i], incr[7][i]);
6964 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6965 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6966 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6967 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6970 rc = sbuf_finish(sb);
6976 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6977 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
6978 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6979 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
6983 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6985 struct adapter *sc = arg1;
6987 int rc, i, n, qid = arg2;
6990 u_int cim_num_obq = sc->chip_params->cim_num_obq;
6992 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6993 ("%s: bad qid %d\n", __func__, qid));
6995 if (qid < CIM_NUM_IBQ) {
6998 n = 4 * CIM_IBQ_SIZE;
6999 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7000 rc = t4_read_cim_ibq(sc, qid, buf, n);
7002 /* outbound queue */
7005 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
7006 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
7007 rc = t4_read_cim_obq(sc, qid, buf, n);
7014 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
7016 rc = sysctl_wire_old_buffer(req, 0);
7020 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7026 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
7027 for (i = 0, p = buf; i < n; i += 16, p += 4)
7028 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
7031 rc = sbuf_finish(sb);
7039 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
7041 struct adapter *sc = arg1;
7047 MPASS(chip_id(sc) <= CHELSIO_T5);
7049 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7053 rc = sysctl_wire_old_buffer(req, 0);
7057 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7061 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7064 rc = -t4_cim_read_la(sc, buf, NULL);
7068 sbuf_printf(sb, "Status Data PC%s",
7069 cfg & F_UPDBGLACAPTPCONLY ? "" :
7070 " LS0Stat LS0Addr LS0Data");
7072 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
7073 if (cfg & F_UPDBGLACAPTPCONLY) {
7074 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
7076 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
7077 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
7078 p[4] & 0xff, p[5] >> 8);
7079 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
7080 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7081 p[1] & 0xf, p[2] >> 4);
7084 "\n %02x %x%07x %x%07x %08x %08x "
7086 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
7087 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
7092 rc = sbuf_finish(sb);
7100 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
7102 struct adapter *sc = arg1;
7108 MPASS(chip_id(sc) > CHELSIO_T5);
7110 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
7114 rc = sysctl_wire_old_buffer(req, 0);
7118 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7122 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
7125 rc = -t4_cim_read_la(sc, buf, NULL);
7129 sbuf_printf(sb, "Status Inst Data PC%s",
7130 cfg & F_UPDBGLACAPTPCONLY ? "" :
7131 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
7133 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
7134 if (cfg & F_UPDBGLACAPTPCONLY) {
7135 sbuf_printf(sb, "\n %02x %08x %08x %08x",
7136 p[3] & 0xff, p[2], p[1], p[0]);
7137 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
7138 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
7139 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
7140 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
7141 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
7142 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
7145 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
7146 "%08x %08x %08x %08x %08x %08x",
7147 (p[9] >> 16) & 0xff,
7148 p[9] & 0xffff, p[8] >> 16,
7149 p[8] & 0xffff, p[7] >> 16,
7150 p[7] & 0xffff, p[6] >> 16,
7151 p[2], p[1], p[0], p[5], p[4], p[3]);
7155 rc = sbuf_finish(sb);
7163 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
7165 struct adapter *sc = arg1;
7171 rc = sysctl_wire_old_buffer(req, 0);
7175 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7179 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
7182 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
7185 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7186 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
7190 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
7191 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
7192 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
7193 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
7194 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
7195 (p[1] >> 2) | ((p[2] & 3) << 30),
7196 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
7200 rc = sbuf_finish(sb);
7207 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
7209 struct adapter *sc = arg1;
7215 rc = sysctl_wire_old_buffer(req, 0);
7219 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7223 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
7226 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
7229 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
7230 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7231 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
7232 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
7233 p[4], p[3], p[2], p[1], p[0]);
7236 sbuf_printf(sb, "\n\nCntl ID Data");
7237 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
7238 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
7239 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
7242 rc = sbuf_finish(sb);
7249 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
7251 struct adapter *sc = arg1;
7254 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7255 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
7256 uint16_t thres[CIM_NUM_IBQ];
7257 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
7258 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
7259 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
7261 cim_num_obq = sc->chip_params->cim_num_obq;
7263 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
7264 obq_rdaddr = A_UP_OBQ_0_REALADDR;
7266 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
7267 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
7269 nq = CIM_NUM_IBQ + cim_num_obq;
7271 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
7273 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
7277 t4_read_cimq_cfg(sc, base, size, thres);
7279 rc = sysctl_wire_old_buffer(req, 0);
7283 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
7288 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
7290 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
7291 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
7292 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
7293 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7294 G_QUEREMFLITS(p[2]) * 16);
7295 for ( ; i < nq; i++, p += 4, wr += 2)
7296 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
7297 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
7298 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
7299 G_QUEREMFLITS(p[2]) * 16);
7301 rc = sbuf_finish(sb);
7308 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
7310 struct adapter *sc = arg1;
7313 struct tp_cpl_stats stats;
7315 rc = sysctl_wire_old_buffer(req, 0);
7319 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7323 mtx_lock(&sc->reg_lock);
7324 t4_tp_get_cpl_stats(sc, &stats, 0);
7325 mtx_unlock(&sc->reg_lock);
7327 if (sc->chip_params->nchan > 2) {
7328 sbuf_printf(sb, " channel 0 channel 1"
7329 " channel 2 channel 3");
7330 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
7331 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
7332 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
7333 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
7335 sbuf_printf(sb, " channel 0 channel 1");
7336 sbuf_printf(sb, "\nCPL requests: %10u %10u",
7337 stats.req[0], stats.req[1]);
7338 sbuf_printf(sb, "\nCPL responses: %10u %10u",
7339 stats.rsp[0], stats.rsp[1]);
7342 rc = sbuf_finish(sb);
7349 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
7351 struct adapter *sc = arg1;
7354 struct tp_usm_stats stats;
7356 rc = sysctl_wire_old_buffer(req, 0);
7360 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7364 t4_get_usm_stats(sc, &stats, 1);
7366 sbuf_printf(sb, "Frames: %u\n", stats.frames);
7367 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
7368 sbuf_printf(sb, "Drops: %u", stats.drops);
7370 rc = sbuf_finish(sb);
7376 static const char * const devlog_level_strings[] = {
7377 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
7378 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
7379 [FW_DEVLOG_LEVEL_ERR] = "ERR",
7380 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
7381 [FW_DEVLOG_LEVEL_INFO] = "INFO",
7382 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
7385 static const char * const devlog_facility_strings[] = {
7386 [FW_DEVLOG_FACILITY_CORE] = "CORE",
7387 [FW_DEVLOG_FACILITY_CF] = "CF",
7388 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
7389 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
7390 [FW_DEVLOG_FACILITY_RES] = "RES",
7391 [FW_DEVLOG_FACILITY_HW] = "HW",
7392 [FW_DEVLOG_FACILITY_FLR] = "FLR",
7393 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
7394 [FW_DEVLOG_FACILITY_PHY] = "PHY",
7395 [FW_DEVLOG_FACILITY_MAC] = "MAC",
7396 [FW_DEVLOG_FACILITY_PORT] = "PORT",
7397 [FW_DEVLOG_FACILITY_VI] = "VI",
7398 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
7399 [FW_DEVLOG_FACILITY_ACL] = "ACL",
7400 [FW_DEVLOG_FACILITY_TM] = "TM",
7401 [FW_DEVLOG_FACILITY_QFC] = "QFC",
7402 [FW_DEVLOG_FACILITY_DCB] = "DCB",
7403 [FW_DEVLOG_FACILITY_ETH] = "ETH",
7404 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
7405 [FW_DEVLOG_FACILITY_RI] = "RI",
7406 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
7407 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
7408 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
7409 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
7410 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
7414 sysctl_devlog(SYSCTL_HANDLER_ARGS)
7416 struct adapter *sc = arg1;
7417 struct devlog_params *dparams = &sc->params.devlog;
7418 struct fw_devlog_e *buf, *e;
7419 int i, j, rc, nentries, first = 0;
7421 uint64_t ftstamp = UINT64_MAX;
7423 if (dparams->addr == 0)
7426 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
7430 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
7434 nentries = dparams->size / sizeof(struct fw_devlog_e);
7435 for (i = 0; i < nentries; i++) {
7438 if (e->timestamp == 0)
7441 e->timestamp = be64toh(e->timestamp);
7442 e->seqno = be32toh(e->seqno);
7443 for (j = 0; j < 8; j++)
7444 e->params[j] = be32toh(e->params[j]);
7446 if (e->timestamp < ftstamp) {
7447 ftstamp = e->timestamp;
7452 if (buf[first].timestamp == 0)
7453 goto done; /* nothing in the log */
7455 rc = sysctl_wire_old_buffer(req, 0);
7459 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7464 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
7465 "Seq#", "Tstamp", "Level", "Facility", "Message");
7470 if (e->timestamp == 0)
7473 sbuf_printf(sb, "%10d %15ju %8s %8s ",
7474 e->seqno, e->timestamp,
7475 (e->level < nitems(devlog_level_strings) ?
7476 devlog_level_strings[e->level] : "UNKNOWN"),
7477 (e->facility < nitems(devlog_facility_strings) ?
7478 devlog_facility_strings[e->facility] : "UNKNOWN"));
7479 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
7480 e->params[2], e->params[3], e->params[4],
7481 e->params[5], e->params[6], e->params[7]);
7483 if (++i == nentries)
7485 } while (i != first);
7487 rc = sbuf_finish(sb);
7495 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
7497 struct adapter *sc = arg1;
7500 struct tp_fcoe_stats stats[MAX_NCHAN];
7501 int i, nchan = sc->chip_params->nchan;
7503 rc = sysctl_wire_old_buffer(req, 0);
7507 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7511 for (i = 0; i < nchan; i++)
7512 t4_get_fcoe_stats(sc, i, &stats[i], 1);
7515 sbuf_printf(sb, " channel 0 channel 1"
7516 " channel 2 channel 3");
7517 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
7518 stats[0].octets_ddp, stats[1].octets_ddp,
7519 stats[2].octets_ddp, stats[3].octets_ddp);
7520 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
7521 stats[0].frames_ddp, stats[1].frames_ddp,
7522 stats[2].frames_ddp, stats[3].frames_ddp);
7523 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
7524 stats[0].frames_drop, stats[1].frames_drop,
7525 stats[2].frames_drop, stats[3].frames_drop);
7527 sbuf_printf(sb, " channel 0 channel 1");
7528 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
7529 stats[0].octets_ddp, stats[1].octets_ddp);
7530 sbuf_printf(sb, "\nframesDDP: %16u %16u",
7531 stats[0].frames_ddp, stats[1].frames_ddp);
7532 sbuf_printf(sb, "\nframesDrop: %16u %16u",
7533 stats[0].frames_drop, stats[1].frames_drop);
7536 rc = sbuf_finish(sb);
7543 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
7545 struct adapter *sc = arg1;
7548 unsigned int map, kbps, ipg, mode;
7549 unsigned int pace_tab[NTX_SCHED];
7551 rc = sysctl_wire_old_buffer(req, 0);
7555 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7559 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
7560 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
7561 t4_read_pace_tbl(sc, pace_tab);
7563 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
7564 "Class IPG (0.1 ns) Flow IPG (us)");
7566 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
7567 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
7568 sbuf_printf(sb, "\n %u %-5s %u ", i,
7569 (mode & (1 << i)) ? "flow" : "class", map & 3);
7571 sbuf_printf(sb, "%9u ", kbps);
7573 sbuf_printf(sb, " disabled ");
7576 sbuf_printf(sb, "%13u ", ipg);
7578 sbuf_printf(sb, " disabled ");
7581 sbuf_printf(sb, "%10u", pace_tab[i]);
7583 sbuf_printf(sb, " disabled");
7586 rc = sbuf_finish(sb);
7593 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
7595 struct adapter *sc = arg1;
7599 struct lb_port_stats s[2];
7600 static const char *stat_name[] = {
7601 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
7602 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
7603 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
7604 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
7605 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
7606 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
7607 "BG2FramesTrunc:", "BG3FramesTrunc:"
7610 rc = sysctl_wire_old_buffer(req, 0);
7614 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7618 memset(s, 0, sizeof(s));
7620 for (i = 0; i < sc->chip_params->nchan; i += 2) {
7621 t4_get_lb_stats(sc, i, &s[0]);
7622 t4_get_lb_stats(sc, i + 1, &s[1]);
7626 sbuf_printf(sb, "%s Loopback %u"
7627 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
7629 for (j = 0; j < nitems(stat_name); j++)
7630 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
7634 rc = sbuf_finish(sb);
7641 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
7644 struct port_info *pi = arg1;
7645 struct link_config *lc = &pi->link_cfg;
7648 rc = sysctl_wire_old_buffer(req, 0);
7651 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
7655 if (lc->link_ok || lc->link_down_rc == 255)
7656 sbuf_printf(sb, "n/a");
7658 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
7660 rc = sbuf_finish(sb);
7673 mem_desc_cmp(const void *a, const void *b)
7675 return ((const struct mem_desc *)a)->base -
7676 ((const struct mem_desc *)b)->base;
7680 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
7688 size = to - from + 1;
7692 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
7693 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
7697 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
7699 struct adapter *sc = arg1;
7702 uint32_t lo, hi, used, alloc;
7703 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
7704 static const char *region[] = {
7705 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
7706 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
7707 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
7708 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
7709 "RQUDP region:", "PBL region:", "TXPBL region:",
7710 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
7711 "On-chip queues:", "TLS keys:",
7713 struct mem_desc avail[4];
7714 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
7715 struct mem_desc *md = mem;
7717 rc = sysctl_wire_old_buffer(req, 0);
7721 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7725 for (i = 0; i < nitems(mem); i++) {
7730 /* Find and sort the populated memory ranges */
7732 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
7733 if (lo & F_EDRAM0_ENABLE) {
7734 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
7735 avail[i].base = G_EDRAM0_BASE(hi) << 20;
7736 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
7740 if (lo & F_EDRAM1_ENABLE) {
7741 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
7742 avail[i].base = G_EDRAM1_BASE(hi) << 20;
7743 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
7747 if (lo & F_EXT_MEM_ENABLE) {
7748 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
7749 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
7750 avail[i].limit = avail[i].base +
7751 (G_EXT_MEM_SIZE(hi) << 20);
7752 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
7755 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
7756 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
7757 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
7758 avail[i].limit = avail[i].base +
7759 (G_EXT_MEM1_SIZE(hi) << 20);
7763 if (!i) /* no memory available */
7765 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
7767 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
7768 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
7769 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
7770 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7771 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
7772 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
7773 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
7774 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
7775 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
7777 /* the next few have explicit upper bounds */
7778 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
7779 md->limit = md->base - 1 +
7780 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
7781 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
7784 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
7785 md->limit = md->base - 1 +
7786 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
7787 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
7790 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7791 if (chip_id(sc) <= CHELSIO_T5)
7792 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
7794 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
7798 md->idx = nitems(region); /* hide it */
7802 #define ulp_region(reg) \
7803 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
7804 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
7806 ulp_region(RX_ISCSI);
7807 ulp_region(RX_TDDP);
7809 ulp_region(RX_STAG);
7811 ulp_region(RX_RQUDP);
7817 md->idx = nitems(region);
7820 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
7821 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
7824 if (sge_ctrl & F_VFIFO_ENABLE)
7825 size = G_DBVFIFO_SIZE(fifo_size);
7827 size = G_T6_DBVFIFO_SIZE(fifo_size);
7830 md->base = G_BASEADDR(t4_read_reg(sc,
7831 A_SGE_DBVFIFO_BADDR));
7832 md->limit = md->base + (size << 2) - 1;
7837 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
7840 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
7844 md->base = sc->vres.ocq.start;
7845 if (sc->vres.ocq.size)
7846 md->limit = md->base + sc->vres.ocq.size - 1;
7848 md->idx = nitems(region); /* hide it */
7851 md->base = sc->vres.key.start;
7852 if (sc->vres.key.size)
7853 md->limit = md->base + sc->vres.key.size - 1;
7855 md->idx = nitems(region); /* hide it */
7858 /* add any address-space holes, there can be up to 3 */
7859 for (n = 0; n < i - 1; n++)
7860 if (avail[n].limit < avail[n + 1].base)
7861 (md++)->base = avail[n].limit;
7863 (md++)->base = avail[n].limit;
7866 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
7868 for (lo = 0; lo < i; lo++)
7869 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
7870 avail[lo].limit - 1);
7872 sbuf_printf(sb, "\n");
7873 for (i = 0; i < n; i++) {
7874 if (mem[i].idx >= nitems(region))
7875 continue; /* skip holes */
7877 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
7878 mem_region_show(sb, region[mem[i].idx], mem[i].base,
7882 sbuf_printf(sb, "\n");
7883 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
7884 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
7885 mem_region_show(sb, "uP RAM:", lo, hi);
7887 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
7888 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
7889 mem_region_show(sb, "uP Extmem2:", lo, hi);
7891 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
7892 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
7894 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
7895 (lo & F_PMRXNUMCHN) ? 2 : 1);
7897 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
7898 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
7899 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
7901 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
7902 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
7903 sbuf_printf(sb, "%u p-structs\n",
7904 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
7906 for (i = 0; i < 4; i++) {
7907 if (chip_id(sc) > CHELSIO_T5)
7908 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
7910 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
7912 used = G_T5_USED(lo);
7913 alloc = G_T5_ALLOC(lo);
7916 alloc = G_ALLOC(lo);
7918 /* For T6 these are MAC buffer groups */
7919 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
7922 for (i = 0; i < sc->chip_params->nchan; i++) {
7923 if (chip_id(sc) > CHELSIO_T5)
7924 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
7926 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
7928 used = G_T5_USED(lo);
7929 alloc = G_T5_ALLOC(lo);
7932 alloc = G_ALLOC(lo);
7934 /* For T6 these are MAC buffer groups */
7936 "\nLoopback %d using %u pages out of %u allocated",
7940 rc = sbuf_finish(sb);
7947 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7951 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7955 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7957 struct adapter *sc = arg1;
7961 MPASS(chip_id(sc) <= CHELSIO_T5);
7963 rc = sysctl_wire_old_buffer(req, 0);
7967 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7972 "Idx Ethernet address Mask Vld Ports PF"
7973 " VF Replication P0 P1 P2 P3 ML");
7974 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7975 uint64_t tcamx, tcamy, mask;
7976 uint32_t cls_lo, cls_hi;
7977 uint8_t addr[ETHER_ADDR_LEN];
7979 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7980 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7983 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7984 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7985 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7986 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7987 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
7988 addr[3], addr[4], addr[5], (uintmax_t)mask,
7989 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7990 G_PORTMAP(cls_hi), G_PF(cls_lo),
7991 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7993 if (cls_lo & F_REPLICATE) {
7994 struct fw_ldst_cmd ldst_cmd;
7996 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7997 ldst_cmd.op_to_addrspace =
7998 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7999 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8000 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8001 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8002 ldst_cmd.u.mps.rplc.fid_idx =
8003 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8004 V_FW_LDST_CMD_IDX(i));
8006 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8010 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8011 sizeof(ldst_cmd), &ldst_cmd);
8012 end_synchronized_op(sc, 0);
8015 sbuf_printf(sb, "%36d", rc);
8018 sbuf_printf(sb, " %08x %08x %08x %08x",
8019 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8020 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8021 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8022 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8025 sbuf_printf(sb, "%36s", "");
8027 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
8028 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
8029 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
8033 (void) sbuf_finish(sb);
8035 rc = sbuf_finish(sb);
8042 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
8044 struct adapter *sc = arg1;
8048 MPASS(chip_id(sc) > CHELSIO_T5);
8050 rc = sysctl_wire_old_buffer(req, 0);
8054 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8058 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
8059 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
8061 " P0 P1 P2 P3 ML\n");
8063 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
8064 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
8066 uint64_t tcamx, tcamy, val, mask;
8067 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
8068 uint8_t addr[ETHER_ADDR_LEN];
8070 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
8072 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
8074 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
8075 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8076 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8077 tcamy = G_DMACH(val) << 32;
8078 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8079 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8080 lookup_type = G_DATALKPTYPE(data2);
8081 port_num = G_DATAPORTNUM(data2);
8082 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8083 /* Inner header VNI */
8084 vniy = ((data2 & F_DATAVIDH2) << 23) |
8085 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8086 dip_hit = data2 & F_DATADIPHIT;
8091 vlan_vld = data2 & F_DATAVIDH2;
8092 ivlan = G_VIDL(val);
8095 ctl |= V_CTLXYBITSEL(1);
8096 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
8097 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
8098 tcamx = G_DMACH(val) << 32;
8099 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
8100 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
8101 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8102 /* Inner header VNI mask */
8103 vnix = ((data2 & F_DATAVIDH2) << 23) |
8104 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
8110 tcamxy2valmask(tcamx, tcamy, addr, &mask);
8112 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
8113 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
8115 if (lookup_type && lookup_type != M_DATALKPTYPE) {
8116 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8117 "%012jx %06x %06x - - %3c"
8118 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
8119 addr[1], addr[2], addr[3], addr[4], addr[5],
8120 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
8121 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8122 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8123 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8125 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
8126 "%012jx - - ", i, addr[0], addr[1],
8127 addr[2], addr[3], addr[4], addr[5],
8131 sbuf_printf(sb, "%4u Y ", ivlan);
8133 sbuf_printf(sb, " - N ");
8135 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
8136 lookup_type ? 'I' : 'O', port_num,
8137 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
8138 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
8139 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
8143 if (cls_lo & F_T6_REPLICATE) {
8144 struct fw_ldst_cmd ldst_cmd;
8146 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
8147 ldst_cmd.op_to_addrspace =
8148 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
8149 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8150 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
8151 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
8152 ldst_cmd.u.mps.rplc.fid_idx =
8153 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
8154 V_FW_LDST_CMD_IDX(i));
8156 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
8160 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
8161 sizeof(ldst_cmd), &ldst_cmd);
8162 end_synchronized_op(sc, 0);
8165 sbuf_printf(sb, "%72d", rc);
8168 sbuf_printf(sb, " %08x %08x %08x %08x"
8169 " %08x %08x %08x %08x",
8170 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
8171 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
8172 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
8173 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
8174 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
8175 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
8176 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
8177 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
8180 sbuf_printf(sb, "%72s", "");
8182 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
8183 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
8184 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
8185 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
8189 (void) sbuf_finish(sb);
8191 rc = sbuf_finish(sb);
8198 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
8200 struct adapter *sc = arg1;
8203 uint16_t mtus[NMTUS];
8205 rc = sysctl_wire_old_buffer(req, 0);
8209 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8213 t4_read_mtu_tbl(sc, mtus, NULL);
8215 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
8216 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
8217 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
8218 mtus[14], mtus[15]);
8220 rc = sbuf_finish(sb);
8227 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
8229 struct adapter *sc = arg1;
8232 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
8233 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
8234 static const char *tx_stats[MAX_PM_NSTATS] = {
8235 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
8236 "Tx FIFO wait", NULL, "Tx latency"
8238 static const char *rx_stats[MAX_PM_NSTATS] = {
8239 "Read:", "Write bypass:", "Write mem:", "Flush:",
8240 "Rx FIFO wait", NULL, "Rx latency"
8243 rc = sysctl_wire_old_buffer(req, 0);
8247 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8251 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
8252 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
8254 sbuf_printf(sb, " Tx pcmds Tx bytes");
8255 for (i = 0; i < 4; i++) {
8256 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8260 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
8261 for (i = 0; i < 4; i++) {
8262 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8266 if (chip_id(sc) > CHELSIO_T5) {
8268 "\n Total wait Total occupancy");
8269 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8271 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8275 MPASS(i < nitems(tx_stats));
8278 "\n Reads Total wait");
8279 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
8281 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
8285 rc = sbuf_finish(sb);
8292 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
8294 struct adapter *sc = arg1;
8297 struct tp_rdma_stats stats;
8299 rc = sysctl_wire_old_buffer(req, 0);
8303 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8307 mtx_lock(&sc->reg_lock);
8308 t4_tp_get_rdma_stats(sc, &stats, 0);
8309 mtx_unlock(&sc->reg_lock);
8311 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
8312 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
8314 rc = sbuf_finish(sb);
8321 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
8323 struct adapter *sc = arg1;
8326 struct tp_tcp_stats v4, v6;
8328 rc = sysctl_wire_old_buffer(req, 0);
8332 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8336 mtx_lock(&sc->reg_lock);
8337 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
8338 mtx_unlock(&sc->reg_lock);
8342 sbuf_printf(sb, "OutRsts: %20u %20u\n",
8343 v4.tcp_out_rsts, v6.tcp_out_rsts);
8344 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
8345 v4.tcp_in_segs, v6.tcp_in_segs);
8346 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
8347 v4.tcp_out_segs, v6.tcp_out_segs);
8348 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
8349 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
8351 rc = sbuf_finish(sb);
8358 sysctl_tids(SYSCTL_HANDLER_ARGS)
8360 struct adapter *sc = arg1;
8363 struct tid_info *t = &sc->tids;
8365 rc = sysctl_wire_old_buffer(req, 0);
8369 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8374 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
8379 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n",
8380 t->hpftid_base, t->hpftid_end, t->hpftids_in_use);
8384 sbuf_printf(sb, "TID range: ");
8385 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
8388 if (chip_id(sc) <= CHELSIO_T5) {
8389 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
8390 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
8392 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
8393 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
8397 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1);
8398 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
8400 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1);
8401 sbuf_printf(sb, ", in use: %u\n",
8402 atomic_load_acq_int(&t->tids_in_use));
8406 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
8407 t->stid_base + t->nstids - 1, t->stids_in_use);
8411 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base,
8412 t->ftid_end, t->ftids_in_use);
8416 sbuf_printf(sb, "ETID range: %u-%u, in use: %u\n", t->etid_base,
8417 t->etid_base + t->netids - 1, t->etids_in_use);
8420 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
8421 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
8422 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
8424 rc = sbuf_finish(sb);
8431 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
8433 struct adapter *sc = arg1;
8436 struct tp_err_stats stats;
8438 rc = sysctl_wire_old_buffer(req, 0);
8442 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8446 mtx_lock(&sc->reg_lock);
8447 t4_tp_get_err_stats(sc, &stats, 0);
8448 mtx_unlock(&sc->reg_lock);
8450 if (sc->chip_params->nchan > 2) {
8451 sbuf_printf(sb, " channel 0 channel 1"
8452 " channel 2 channel 3\n");
8453 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
8454 stats.mac_in_errs[0], stats.mac_in_errs[1],
8455 stats.mac_in_errs[2], stats.mac_in_errs[3]);
8456 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
8457 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
8458 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
8459 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
8460 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
8461 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
8462 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
8463 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
8464 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
8465 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
8466 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
8467 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
8468 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
8469 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
8470 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
8471 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
8472 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
8473 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
8474 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
8475 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
8476 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
8478 sbuf_printf(sb, " channel 0 channel 1\n");
8479 sbuf_printf(sb, "macInErrs: %10u %10u\n",
8480 stats.mac_in_errs[0], stats.mac_in_errs[1]);
8481 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
8482 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
8483 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
8484 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
8485 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
8486 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
8487 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
8488 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
8489 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
8490 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
8491 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
8492 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
8493 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
8494 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
8497 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
8498 stats.ofld_no_neigh, stats.ofld_cong_defer);
8500 rc = sbuf_finish(sb);
8507 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
8509 struct adapter *sc = arg1;
8510 struct tp_params *tpp = &sc->params.tp;
8514 mask = tpp->la_mask >> 16;
8515 rc = sysctl_handle_int(oidp, &mask, 0, req);
8516 if (rc != 0 || req->newptr == NULL)
8520 tpp->la_mask = mask << 16;
8521 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
8533 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
8539 uint64_t mask = (1ULL << f->width) - 1;
8540 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
8541 ((uintmax_t)v >> f->start) & mask);
8543 if (line_size + len >= 79) {
8545 sbuf_printf(sb, "\n ");
8547 sbuf_printf(sb, "%s ", buf);
8548 line_size += len + 1;
8551 sbuf_printf(sb, "\n");
8554 static const struct field_desc tp_la0[] = {
8555 { "RcfOpCodeOut", 60, 4 },
8557 { "WcfState", 52, 4 },
8558 { "RcfOpcSrcOut", 50, 2 },
8559 { "CRxError", 49, 1 },
8560 { "ERxError", 48, 1 },
8561 { "SanityFailed", 47, 1 },
8562 { "SpuriousMsg", 46, 1 },
8563 { "FlushInputMsg", 45, 1 },
8564 { "FlushInputCpl", 44, 1 },
8565 { "RssUpBit", 43, 1 },
8566 { "RssFilterHit", 42, 1 },
8568 { "InitTcb", 31, 1 },
8569 { "LineNumber", 24, 7 },
8571 { "EdataOut", 22, 1 },
8573 { "CdataOut", 20, 1 },
8574 { "EreadPdu", 19, 1 },
8575 { "CreadPdu", 18, 1 },
8576 { "TunnelPkt", 17, 1 },
8577 { "RcfPeerFin", 16, 1 },
8578 { "RcfReasonOut", 12, 4 },
8579 { "TxCchannel", 10, 2 },
8580 { "RcfTxChannel", 8, 2 },
8581 { "RxEchannel", 6, 2 },
8582 { "RcfRxChannel", 5, 1 },
8583 { "RcfDataOutSrdy", 4, 1 },
8585 { "RxOoDvld", 2, 1 },
8586 { "RxCongestion", 1, 1 },
8587 { "TxCongestion", 0, 1 },
8591 static const struct field_desc tp_la1[] = {
8592 { "CplCmdIn", 56, 8 },
8593 { "CplCmdOut", 48, 8 },
8594 { "ESynOut", 47, 1 },
8595 { "EAckOut", 46, 1 },
8596 { "EFinOut", 45, 1 },
8597 { "ERstOut", 44, 1 },
8602 { "DataIn", 39, 1 },
8603 { "DataInVld", 38, 1 },
8605 { "RxBufEmpty", 36, 1 },
8607 { "RxFbCongestion", 34, 1 },
8608 { "TxFbCongestion", 33, 1 },
8609 { "TxPktSumSrdy", 32, 1 },
8610 { "RcfUlpType", 28, 4 },
8612 { "Ebypass", 26, 1 },
8614 { "Static0", 24, 1 },
8616 { "Cbypass", 22, 1 },
8618 { "CPktOut", 20, 1 },
8619 { "RxPagePoolFull", 18, 2 },
8620 { "RxLpbkPkt", 17, 1 },
8621 { "TxLpbkPkt", 16, 1 },
8622 { "RxVfValid", 15, 1 },
8623 { "SynLearned", 14, 1 },
8624 { "SetDelEntry", 13, 1 },
8625 { "SetInvEntry", 12, 1 },
8626 { "CpcmdDvld", 11, 1 },
8627 { "CpcmdSave", 10, 1 },
8628 { "RxPstructsFull", 8, 2 },
8629 { "EpcmdDvld", 7, 1 },
8630 { "EpcmdFlush", 6, 1 },
8631 { "EpcmdTrimPrefix", 5, 1 },
8632 { "EpcmdTrimPostfix", 4, 1 },
8633 { "ERssIp4Pkt", 3, 1 },
8634 { "ERssIp6Pkt", 2, 1 },
8635 { "ERssTcpUdpPkt", 1, 1 },
8636 { "ERssFceFipPkt", 0, 1 },
8640 static const struct field_desc tp_la2[] = {
8641 { "CplCmdIn", 56, 8 },
8642 { "MpsVfVld", 55, 1 },
8649 { "DataIn", 39, 1 },
8650 { "DataInVld", 38, 1 },
8652 { "RxBufEmpty", 36, 1 },
8654 { "RxFbCongestion", 34, 1 },
8655 { "TxFbCongestion", 33, 1 },
8656 { "TxPktSumSrdy", 32, 1 },
8657 { "RcfUlpType", 28, 4 },
8659 { "Ebypass", 26, 1 },
8661 { "Static0", 24, 1 },
8663 { "Cbypass", 22, 1 },
8665 { "CPktOut", 20, 1 },
8666 { "RxPagePoolFull", 18, 2 },
8667 { "RxLpbkPkt", 17, 1 },
8668 { "TxLpbkPkt", 16, 1 },
8669 { "RxVfValid", 15, 1 },
8670 { "SynLearned", 14, 1 },
8671 { "SetDelEntry", 13, 1 },
8672 { "SetInvEntry", 12, 1 },
8673 { "CpcmdDvld", 11, 1 },
8674 { "CpcmdSave", 10, 1 },
8675 { "RxPstructsFull", 8, 2 },
8676 { "EpcmdDvld", 7, 1 },
8677 { "EpcmdFlush", 6, 1 },
8678 { "EpcmdTrimPrefix", 5, 1 },
8679 { "EpcmdTrimPostfix", 4, 1 },
8680 { "ERssIp4Pkt", 3, 1 },
8681 { "ERssIp6Pkt", 2, 1 },
8682 { "ERssTcpUdpPkt", 1, 1 },
8683 { "ERssFceFipPkt", 0, 1 },
8688 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
8691 field_desc_show(sb, *p, tp_la0);
8695 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
8699 sbuf_printf(sb, "\n");
8700 field_desc_show(sb, p[0], tp_la0);
8701 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8702 field_desc_show(sb, p[1], tp_la0);
8706 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
8710 sbuf_printf(sb, "\n");
8711 field_desc_show(sb, p[0], tp_la0);
8712 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
8713 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
8717 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
8719 struct adapter *sc = arg1;
8724 void (*show_func)(struct sbuf *, uint64_t *, int);
8726 rc = sysctl_wire_old_buffer(req, 0);
8730 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8734 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
8736 t4_tp_read_la(sc, buf, NULL);
8739 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
8742 show_func = tp_la_show2;
8746 show_func = tp_la_show3;
8750 show_func = tp_la_show;
8753 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
8754 (*show_func)(sb, p, i);
8756 rc = sbuf_finish(sb);
8763 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
8765 struct adapter *sc = arg1;
8768 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
8770 rc = sysctl_wire_old_buffer(req, 0);
8774 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
8778 t4_get_chan_txrate(sc, nrate, orate);
8780 if (sc->chip_params->nchan > 2) {
8781 sbuf_printf(sb, " channel 0 channel 1"
8782 " channel 2 channel 3\n");
8783 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
8784 nrate[0], nrate[1], nrate[2], nrate[3]);
8785 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
8786 orate[0], orate[1], orate[2], orate[3]);
8788 sbuf_printf(sb, " channel 0 channel 1\n");
8789 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
8790 nrate[0], nrate[1]);
8791 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
8792 orate[0], orate[1]);
8795 rc = sbuf_finish(sb);
8802 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
8804 struct adapter *sc = arg1;
8809 rc = sysctl_wire_old_buffer(req, 0);
8813 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8817 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
8820 t4_ulprx_read_la(sc, buf);
8823 sbuf_printf(sb, " Pcmd Type Message"
8825 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
8826 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
8827 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
8830 rc = sbuf_finish(sb);
8837 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
8839 struct adapter *sc = arg1;
8843 MPASS(chip_id(sc) >= CHELSIO_T5);
8845 rc = sysctl_wire_old_buffer(req, 0);
8849 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8853 v = t4_read_reg(sc, A_SGE_STAT_CFG);
8854 if (G_STATSOURCE_T5(v) == 7) {
8857 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
8859 sbuf_printf(sb, "total %d, incomplete %d",
8860 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8861 t4_read_reg(sc, A_SGE_STAT_MATCH));
8862 } else if (mode == 1) {
8863 sbuf_printf(sb, "total %d, data overflow %d",
8864 t4_read_reg(sc, A_SGE_STAT_TOTAL),
8865 t4_read_reg(sc, A_SGE_STAT_MATCH));
8867 sbuf_printf(sb, "unknown mode %d", mode);
8870 rc = sbuf_finish(sb);
8877 sysctl_cpus(SYSCTL_HANDLER_ARGS)
8879 struct adapter *sc = arg1;
8880 enum cpu_sets op = arg2;
8885 MPASS(op == LOCAL_CPUS || op == INTR_CPUS);
8888 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset);
8892 rc = sysctl_wire_old_buffer(req, 0);
8896 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
8901 sbuf_printf(sb, "%d ", i);
8902 rc = sbuf_finish(sb);
8910 sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS)
8912 struct adapter *sc = arg1;
8913 int *old_ports, *new_ports;
8914 int i, new_count, rc;
8916 if (req->newptr == NULL && req->oldptr == NULL)
8917 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) *
8918 sizeof(sc->tt.tls_rx_ports[0])));
8920 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx");
8924 if (sc->tt.num_tls_rx_ports == 0) {
8926 rc = SYSCTL_OUT(req, &i, sizeof(i));
8928 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports,
8929 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0]));
8930 if (rc == 0 && req->newptr != NULL) {
8931 new_count = req->newlen / sizeof(new_ports[0]);
8932 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE,
8934 rc = SYSCTL_IN(req, new_ports, new_count *
8935 sizeof(new_ports[0]));
8939 /* Allow setting to a single '-1' to clear the list. */
8940 if (new_count == 1 && new_ports[0] == -1) {
8942 old_ports = sc->tt.tls_rx_ports;
8943 sc->tt.tls_rx_ports = NULL;
8944 sc->tt.num_tls_rx_ports = 0;
8946 free(old_ports, M_CXGBE);
8948 for (i = 0; i < new_count; i++) {
8949 if (new_ports[i] < 1 ||
8950 new_ports[i] > IPPORT_MAX) {
8957 old_ports = sc->tt.tls_rx_ports;
8958 sc->tt.tls_rx_ports = new_ports;
8959 sc->tt.num_tls_rx_ports = new_count;
8961 free(old_ports, M_CXGBE);
8965 free(new_ports, M_CXGBE);
8967 end_synchronized_op(sc, 0);
8972 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8974 u_int rem = val % factor;
8977 snprintf(buf, len, "%u", val / factor);
8979 while (rem % 10 == 0)
8981 snprintf(buf, len, "%u.%u", val / factor, rem);
8986 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8988 struct adapter *sc = arg1;
8991 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8993 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8997 re = G_TIMERRESOLUTION(res);
9000 /* TCP timestamp tick */
9001 re = G_TIMESTAMPRESOLUTION(res);
9005 re = G_DELAYEDACKRESOLUTION(res);
9011 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
9013 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
9017 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
9019 struct adapter *sc = arg1;
9020 u_int res, dack_re, v;
9021 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9023 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
9024 dack_re = G_DELAYEDACKRESOLUTION(res);
9025 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
9027 return (sysctl_handle_int(oidp, &v, 0, req));
9031 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
9033 struct adapter *sc = arg1;
9036 u_long tp_tick_us, v;
9037 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
9039 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
9040 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
9041 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
9042 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
9044 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
9045 tp_tick_us = (cclk_ps << tre) / 1000000;
9047 if (reg == A_TP_INIT_SRTT)
9048 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
9050 v = tp_tick_us * t4_read_reg(sc, reg);
9052 return (sysctl_handle_long(oidp, &v, 0, req));
9056 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is
9057 * passed to this function.
9060 sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS)
9062 struct adapter *sc = arg1;
9066 MPASS(idx >= 0 && idx <= 24);
9068 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf;
9070 return (sysctl_handle_int(oidp, &v, 0, req));
9074 sysctl_tp_backoff(SYSCTL_HANDLER_ARGS)
9076 struct adapter *sc = arg1;
9080 MPASS(idx >= 0 && idx < 16);
9082 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3);
9083 shift = (idx & 3) << 3;
9084 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0;
9086 return (sysctl_handle_int(oidp, &v, 0, req));
9090 sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS)
9092 struct vi_info *vi = arg1;
9093 struct adapter *sc = vi->pi->adapter;
9095 struct sge_ofld_rxq *ofld_rxq;
9098 idx = vi->ofld_tmr_idx;
9100 rc = sysctl_handle_int(oidp, &idx, 0, req);
9101 if (rc != 0 || req->newptr == NULL)
9104 if (idx < 0 || idx >= SGE_NTIMERS)
9107 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9112 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1);
9113 for_each_ofld_rxq(vi, i, ofld_rxq) {
9114 #ifdef atomic_store_rel_8
9115 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
9117 ofld_rxq->iq.intr_params = v;
9120 vi->ofld_tmr_idx = idx;
9122 end_synchronized_op(sc, LOCK_HELD);
9127 sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
9129 struct vi_info *vi = arg1;
9130 struct adapter *sc = vi->pi->adapter;
9133 idx = vi->ofld_pktc_idx;
9135 rc = sysctl_handle_int(oidp, &idx, 0, req);
9136 if (rc != 0 || req->newptr == NULL)
9139 if (idx < -1 || idx >= SGE_NCOUNTERS)
9142 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
9147 if (vi->flags & VI_INIT_DONE)
9148 rc = EBUSY; /* cannot be changed once the queues are created */
9150 vi->ofld_pktc_idx = idx;
9152 end_synchronized_op(sc, LOCK_HELD);
9158 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
9162 if (cntxt->cid > M_CTXTQID)
9165 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
9166 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
9169 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
9173 if (sc->flags & FW_OK) {
9174 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
9181 * Read via firmware failed or wasn't even attempted. Read directly via
9184 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
9186 end_synchronized_op(sc, 0);
9191 load_fw(struct adapter *sc, struct t4_data *fw)
9196 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
9201 * The firmware, with the sole exception of the memory parity error
9202 * handler, runs from memory and not flash. It is almost always safe to
9203 * install a new firmware on a running system. Just set bit 1 in
9204 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first.
9206 if (sc->flags & FULL_INIT_DONE &&
9207 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) {
9212 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
9213 if (fw_data == NULL) {
9218 rc = copyin(fw->data, fw_data, fw->len);
9220 rc = -t4_load_fw(sc, fw_data, fw->len);
9222 free(fw_data, M_CXGBE);
9224 end_synchronized_op(sc, 0);
9229 load_cfg(struct adapter *sc, struct t4_data *cfg)
9232 uint8_t *cfg_data = NULL;
9234 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9238 if (cfg->len == 0) {
9240 rc = -t4_load_cfg(sc, NULL, 0);
9244 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
9245 if (cfg_data == NULL) {
9250 rc = copyin(cfg->data, cfg_data, cfg->len);
9252 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
9254 free(cfg_data, M_CXGBE);
9256 end_synchronized_op(sc, 0);
9261 load_boot(struct adapter *sc, struct t4_bootrom *br)
9264 uint8_t *br_data = NULL;
9267 if (br->len > 1024 * 1024)
9270 if (br->pf_offset == 0) {
9272 if (br->pfidx_addr > 7)
9274 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr,
9275 A_PCIE_PF_EXPROM_OFST)));
9276 } else if (br->pf_offset == 1) {
9278 offset = G_OFFSET(br->pfidx_addr);
9283 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr");
9289 rc = -t4_load_boot(sc, NULL, offset, 0);
9293 br_data = malloc(br->len, M_CXGBE, M_WAITOK);
9294 if (br_data == NULL) {
9299 rc = copyin(br->data, br_data, br->len);
9301 rc = -t4_load_boot(sc, br_data, offset, br->len);
9303 free(br_data, M_CXGBE);
9305 end_synchronized_op(sc, 0);
9310 load_bootcfg(struct adapter *sc, struct t4_data *bc)
9313 uint8_t *bc_data = NULL;
9315 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
9321 rc = -t4_load_bootcfg(sc, NULL, 0);
9325 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK);
9326 if (bc_data == NULL) {
9331 rc = copyin(bc->data, bc_data, bc->len);
9333 rc = -t4_load_bootcfg(sc, bc_data, bc->len);
9335 free(bc_data, M_CXGBE);
9337 end_synchronized_op(sc, 0);
9342 cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump)
9345 struct cudbg_init *cudbg;
9348 /* buf is large, don't block if no memory is available */
9349 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO);
9353 handle = cudbg_alloc_handle();
9354 if (handle == NULL) {
9359 cudbg = cudbg_get_init(handle);
9361 cudbg->print = (cudbg_print_cb)printf;
9364 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n",
9365 __func__, dump->wr_flash, dump->len, dump->data);
9369 cudbg->use_flash = 1;
9370 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap));
9371 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap));
9373 rc = cudbg_collect(handle, buf, &dump->len);
9377 rc = copyout(buf, dump->data, dump->len);
9379 cudbg_free_handle(handle);
9385 free_offload_policy(struct t4_offload_policy *op)
9387 struct offload_rule *r;
9394 for (i = 0; i < op->nrules; i++, r++) {
9395 free(r->bpf_prog.bf_insns, M_CXGBE);
9397 free(op->rule, M_CXGBE);
9402 set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop)
9405 struct t4_offload_policy *op, *old;
9406 struct bpf_program *bf;
9407 const struct offload_settings *s;
9408 struct offload_rule *r;
9411 if (!is_offload(sc))
9414 if (uop->nrules == 0) {
9415 /* Delete installed policies. */
9418 } if (uop->nrules > 256) { /* arbitrary */
9422 /* Copy userspace offload policy to kernel */
9423 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK);
9424 op->nrules = uop->nrules;
9425 len = op->nrules * sizeof(struct offload_rule);
9426 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9427 rc = copyin(uop->rule, op->rule, len);
9429 free(op->rule, M_CXGBE);
9435 for (i = 0; i < op->nrules; i++, r++) {
9437 /* Validate open_type */
9438 if (r->open_type != OPEN_TYPE_LISTEN &&
9439 r->open_type != OPEN_TYPE_ACTIVE &&
9440 r->open_type != OPEN_TYPE_PASSIVE &&
9441 r->open_type != OPEN_TYPE_DONTCARE) {
9444 * Rules 0 to i have malloc'd filters that need to be
9445 * freed. Rules i+1 to nrules have userspace pointers
9446 * and should be left alone.
9449 free_offload_policy(op);
9453 /* Validate settings */
9455 if ((s->offload != 0 && s->offload != 1) ||
9456 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED ||
9457 s->sched_class < -1 ||
9458 s->sched_class >= sc->chip_params->nsched_cls) {
9464 u = bf->bf_insns; /* userspace ptr */
9465 bf->bf_insns = NULL;
9466 if (bf->bf_len == 0) {
9467 /* legal, matches everything */
9470 len = bf->bf_len * sizeof(*bf->bf_insns);
9471 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK);
9472 rc = copyin(u, bf->bf_insns, len);
9476 if (!bpf_validate(bf->bf_insns, bf->bf_len)) {
9482 rw_wlock(&sc->policy_lock);
9485 rw_wunlock(&sc->policy_lock);
9486 free_offload_policy(old);
9491 #define MAX_READ_BUF_SIZE (128 * 1024)
9493 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
9495 uint32_t addr, remaining, n;
9500 rc = validate_mem_range(sc, mr->addr, mr->len);
9504 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
9506 remaining = mr->len;
9507 dst = (void *)mr->data;
9510 n = min(remaining, MAX_READ_BUF_SIZE);
9511 read_via_memwin(sc, 2, addr, buf, n);
9513 rc = copyout(buf, dst, n);
9525 #undef MAX_READ_BUF_SIZE
9528 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
9532 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
9535 if (i2cd->len > sizeof(i2cd->data))
9538 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
9541 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
9542 i2cd->offset, i2cd->len, &i2cd->data[0]);
9543 end_synchronized_op(sc, 0);
9549 t4_os_find_pci_capability(struct adapter *sc, int cap)
9553 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
9557 t4_os_pci_save_state(struct adapter *sc)
9560 struct pci_devinfo *dinfo;
9563 dinfo = device_get_ivars(dev);
9565 pci_cfg_save(dev, dinfo, 0);
9570 t4_os_pci_restore_state(struct adapter *sc)
9573 struct pci_devinfo *dinfo;
9576 dinfo = device_get_ivars(dev);
9578 pci_cfg_restore(dev, dinfo);
9583 t4_os_portmod_changed(struct port_info *pi)
9585 struct adapter *sc = pi->adapter;
9588 static const char *mod_str[] = {
9589 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
9592 KASSERT((pi->flags & FIXED_IFMEDIA) == 0,
9593 ("%s: port_type %u", __func__, pi->port_type));
9596 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
9598 build_medialist(pi);
9599 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
9600 fixup_link_config(pi);
9601 apply_link_config(pi);
9604 end_synchronized_op(sc, LOCK_HELD);
9608 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
9609 if_printf(ifp, "transceiver unplugged.\n");
9610 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
9611 if_printf(ifp, "unknown transceiver inserted.\n");
9612 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
9613 if_printf(ifp, "unsupported transceiver inserted.\n");
9614 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
9615 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
9616 port_top_speed(pi), mod_str[pi->mod_type]);
9618 if_printf(ifp, "transceiver (type %d) inserted.\n",
9624 t4_os_link_changed(struct port_info *pi)
9628 struct link_config *lc;
9631 PORT_LOCK_ASSERT_OWNED(pi);
9633 for_each_vi(pi, v, vi) {
9640 ifp->if_baudrate = IF_Mbps(lc->speed);
9641 if_link_state_change(ifp, LINK_STATE_UP);
9643 if_link_state_change(ifp, LINK_STATE_DOWN);
9649 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
9653 sx_slock(&t4_list_lock);
9654 SLIST_FOREACH(sc, &t4_list, link) {
9656 * func should not make any assumptions about what state sc is
9657 * in - the only guarantee is that sc->sc_lock is a valid lock.
9661 sx_sunlock(&t4_list_lock);
9665 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9669 struct adapter *sc = dev->si_drv1;
9671 rc = priv_check(td, PRIV_DRIVER);
9676 case CHELSIO_T4_GETREG: {
9677 struct t4_reg *edata = (struct t4_reg *)data;
9679 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9682 if (edata->size == 4)
9683 edata->val = t4_read_reg(sc, edata->addr);
9684 else if (edata->size == 8)
9685 edata->val = t4_read_reg64(sc, edata->addr);
9691 case CHELSIO_T4_SETREG: {
9692 struct t4_reg *edata = (struct t4_reg *)data;
9694 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9697 if (edata->size == 4) {
9698 if (edata->val & 0xffffffff00000000)
9700 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9701 } else if (edata->size == 8)
9702 t4_write_reg64(sc, edata->addr, edata->val);
9707 case CHELSIO_T4_REGDUMP: {
9708 struct t4_regdump *regs = (struct t4_regdump *)data;
9709 int reglen = t4_get_regs_len(sc);
9712 if (regs->len < reglen) {
9713 regs->len = reglen; /* hint to the caller */
9718 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9719 get_regs(sc, regs, buf);
9720 rc = copyout(buf, regs->data, reglen);
9724 case CHELSIO_T4_GET_FILTER_MODE:
9725 rc = get_filter_mode(sc, (uint32_t *)data);
9727 case CHELSIO_T4_SET_FILTER_MODE:
9728 rc = set_filter_mode(sc, *(uint32_t *)data);
9730 case CHELSIO_T4_GET_FILTER:
9731 rc = get_filter(sc, (struct t4_filter *)data);
9733 case CHELSIO_T4_SET_FILTER:
9734 rc = set_filter(sc, (struct t4_filter *)data);
9736 case CHELSIO_T4_DEL_FILTER:
9737 rc = del_filter(sc, (struct t4_filter *)data);
9739 case CHELSIO_T4_GET_SGE_CONTEXT:
9740 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9742 case CHELSIO_T4_LOAD_FW:
9743 rc = load_fw(sc, (struct t4_data *)data);
9745 case CHELSIO_T4_GET_MEM:
9746 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9748 case CHELSIO_T4_GET_I2C:
9749 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9751 case CHELSIO_T4_CLEAR_STATS: {
9753 u_int port_id = *(uint32_t *)data;
9754 struct port_info *pi;
9757 if (port_id >= sc->params.nports)
9759 pi = sc->port[port_id];
9764 t4_clr_port_stats(sc, pi->tx_chan);
9765 pi->tx_parse_error = 0;
9766 pi->tnl_cong_drops = 0;
9767 mtx_lock(&sc->reg_lock);
9768 for_each_vi(pi, v, vi) {
9769 if (vi->flags & VI_INIT_DONE)
9770 t4_clr_vi_stats(sc, vi->viid);
9772 bg_map = pi->mps_bg_map;
9775 i = ffs(bg_map) - 1;
9776 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
9777 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
9778 bg_map &= ~(1 << i);
9780 mtx_unlock(&sc->reg_lock);
9783 * Since this command accepts a port, clear stats for
9784 * all VIs on this port.
9786 for_each_vi(pi, v, vi) {
9787 if (vi->flags & VI_INIT_DONE) {
9788 struct sge_rxq *rxq;
9789 struct sge_txq *txq;
9790 struct sge_wrq *wrq;
9792 for_each_rxq(vi, i, rxq) {
9793 #if defined(INET) || defined(INET6)
9794 rxq->lro.lro_queued = 0;
9795 rxq->lro.lro_flushed = 0;
9798 rxq->vlan_extraction = 0;
9801 for_each_txq(vi, i, txq) {
9804 txq->vlan_insertion = 0;
9808 txq->txpkts0_wrs = 0;
9809 txq->txpkts1_wrs = 0;
9810 txq->txpkts0_pkts = 0;
9811 txq->txpkts1_pkts = 0;
9813 mp_ring_reset_stats(txq->r);
9817 /* nothing to clear for each ofld_rxq */
9819 for_each_ofld_txq(vi, i, wrq) {
9820 wrq->tx_wrs_direct = 0;
9821 wrq->tx_wrs_copied = 0;
9825 if (IS_MAIN_VI(vi)) {
9826 wrq = &sc->sge.ctrlq[pi->port_id];
9827 wrq->tx_wrs_direct = 0;
9828 wrq->tx_wrs_copied = 0;
9834 case CHELSIO_T4_SCHED_CLASS:
9835 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9837 case CHELSIO_T4_SCHED_QUEUE:
9838 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9840 case CHELSIO_T4_GET_TRACER:
9841 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9843 case CHELSIO_T4_SET_TRACER:
9844 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9846 case CHELSIO_T4_LOAD_CFG:
9847 rc = load_cfg(sc, (struct t4_data *)data);
9849 case CHELSIO_T4_LOAD_BOOT:
9850 rc = load_boot(sc, (struct t4_bootrom *)data);
9852 case CHELSIO_T4_LOAD_BOOTCFG:
9853 rc = load_bootcfg(sc, (struct t4_data *)data);
9855 case CHELSIO_T4_CUDBG_DUMP:
9856 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data);
9858 case CHELSIO_T4_SET_OFLD_POLICY:
9859 rc = set_offload_policy(sc, (struct t4_offload_policy *)data);
9869 t4_db_full(struct adapter *sc)
9872 CXGBE_UNIMPLEMENTED(__func__);
9876 t4_db_dropped(struct adapter *sc)
9879 CXGBE_UNIMPLEMENTED(__func__);
9884 toe_capability(struct vi_info *vi, int enable)
9887 struct port_info *pi = vi->pi;
9888 struct adapter *sc = pi->adapter;
9890 ASSERT_SYNCHRONIZED_OP(sc);
9892 if (!is_offload(sc))
9896 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9897 /* TOE is already enabled. */
9902 * We need the port's queues around so that we're able to send
9903 * and receive CPLs to/from the TOE even if the ifnet for this
9904 * port has never been UP'd administratively.
9906 if (!(vi->flags & VI_INIT_DONE)) {
9907 rc = vi_full_init(vi);
9911 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9912 rc = vi_full_init(&pi->vi[0]);
9917 if (isset(&sc->offload_map, pi->port_id)) {
9918 /* TOE is enabled on another VI of this port. */
9923 if (!uld_active(sc, ULD_TOM)) {
9924 rc = t4_activate_uld(sc, ULD_TOM);
9927 "You must kldload t4_tom.ko before trying "
9928 "to enable TOE on a cxgbe interface.\n");
9932 KASSERT(sc->tom_softc != NULL,
9933 ("%s: TOM activated but softc NULL", __func__));
9934 KASSERT(uld_active(sc, ULD_TOM),
9935 ("%s: TOM activated but flag not set", __func__));
9938 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9939 if (!uld_active(sc, ULD_IWARP))
9940 (void) t4_activate_uld(sc, ULD_IWARP);
9941 if (!uld_active(sc, ULD_ISCSI))
9942 (void) t4_activate_uld(sc, ULD_ISCSI);
9945 setbit(&sc->offload_map, pi->port_id);
9949 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9952 KASSERT(uld_active(sc, ULD_TOM),
9953 ("%s: TOM never initialized?", __func__));
9954 clrbit(&sc->offload_map, pi->port_id);
9961 * Add an upper layer driver to the global list.
9964 t4_register_uld(struct uld_info *ui)
9969 sx_xlock(&t4_uld_list_lock);
9970 SLIST_FOREACH(u, &t4_uld_list, link) {
9971 if (u->uld_id == ui->uld_id) {
9977 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9980 sx_xunlock(&t4_uld_list_lock);
9985 t4_unregister_uld(struct uld_info *ui)
9990 sx_xlock(&t4_uld_list_lock);
9992 SLIST_FOREACH(u, &t4_uld_list, link) {
9994 if (ui->refcount > 0) {
9999 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
10005 sx_xunlock(&t4_uld_list_lock);
10010 t4_activate_uld(struct adapter *sc, int id)
10013 struct uld_info *ui;
10015 ASSERT_SYNCHRONIZED_OP(sc);
10017 if (id < 0 || id > ULD_MAX)
10019 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
10021 sx_slock(&t4_uld_list_lock);
10023 SLIST_FOREACH(ui, &t4_uld_list, link) {
10024 if (ui->uld_id == id) {
10025 if (!(sc->flags & FULL_INIT_DONE)) {
10026 rc = adapter_full_init(sc);
10031 rc = ui->activate(sc);
10033 setbit(&sc->active_ulds, id);
10040 sx_sunlock(&t4_uld_list_lock);
10046 t4_deactivate_uld(struct adapter *sc, int id)
10049 struct uld_info *ui;
10051 ASSERT_SYNCHRONIZED_OP(sc);
10053 if (id < 0 || id > ULD_MAX)
10057 sx_slock(&t4_uld_list_lock);
10059 SLIST_FOREACH(ui, &t4_uld_list, link) {
10060 if (ui->uld_id == id) {
10061 rc = ui->deactivate(sc);
10063 clrbit(&sc->active_ulds, id);
10070 sx_sunlock(&t4_uld_list_lock);
10076 uld_active(struct adapter *sc, int uld_id)
10079 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
10081 return (isset(&sc->active_ulds, uld_id));
10086 * t = ptr to tunable.
10087 * nc = number of CPUs.
10088 * c = compiled in default for that tunable.
10091 calculate_nqueues(int *t, int nc, const int c)
10097 nq = *t < 0 ? -*t : c;
10102 * Come up with reasonable defaults for some of the tunables, provided they're
10103 * not set by the user (in which case we'll use the values as is).
10106 tweak_tunables(void)
10108 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
10112 t4_ntxq = rss_getnumbuckets();
10114 calculate_nqueues(&t4_ntxq, nc, NTXQ);
10118 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
10122 t4_nrxq = rss_getnumbuckets();
10124 calculate_nqueues(&t4_nrxq, nc, NRXQ);
10128 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
10130 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
10131 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ);
10132 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
10135 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ);
10136 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
10138 if (t4_toecaps_allowed == -1)
10139 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
10141 if (t4_rdmacaps_allowed == -1) {
10142 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
10143 FW_CAPS_CONFIG_RDMA_RDMAC;
10146 if (t4_iscsicaps_allowed == -1) {
10147 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
10148 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
10149 FW_CAPS_CONFIG_ISCSI_T10DIF;
10152 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS)
10153 t4_tmr_idx_ofld = TMR_IDX_OFLD;
10155 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS)
10156 t4_pktc_idx_ofld = PKTC_IDX_OFLD;
10158 if (t4_toecaps_allowed == -1)
10159 t4_toecaps_allowed = 0;
10161 if (t4_rdmacaps_allowed == -1)
10162 t4_rdmacaps_allowed = 0;
10164 if (t4_iscsicaps_allowed == -1)
10165 t4_iscsicaps_allowed = 0;
10169 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
10170 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
10173 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS)
10174 t4_tmr_idx = TMR_IDX;
10176 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS)
10177 t4_pktc_idx = PKTC_IDX;
10179 if (t4_qsize_txq < 128)
10180 t4_qsize_txq = 128;
10182 if (t4_qsize_rxq < 128)
10183 t4_qsize_rxq = 128;
10184 while (t4_qsize_rxq & 7)
10187 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
10190 * Number of VIs to create per-port. The first VI is the "main" regular
10191 * VI for the port. The rest are additional virtual interfaces on the
10192 * same physical port. Note that the main VI does not have native
10193 * netmap support but the extra VIs do.
10195 * Limit the number of VIs per port to the number of available
10196 * MAC addresses per port.
10198 if (t4_num_vis < 1)
10200 if (t4_num_vis > nitems(vi_mac_funcs)) {
10201 t4_num_vis = nitems(vi_mac_funcs);
10202 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis);
10205 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) {
10206 pcie_relaxed_ordering = 1;
10207 #if defined(__i386__) || defined(__amd64__)
10208 if (cpu_vendor_id == CPU_VENDOR_INTEL)
10209 pcie_relaxed_ordering = 0;
10216 t4_dump_tcb(struct adapter *sc, int tid)
10218 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
10220 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
10221 save = t4_read_reg(sc, reg);
10222 base = sc->memwin[2].mw_base;
10224 /* Dump TCB for the tid */
10225 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
10226 tcb_addr += tid * TCB_SIZE;
10230 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
10232 pf = V_PFNUM(sc->pf);
10233 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
10235 t4_write_reg(sc, reg, win_pos | pf);
10236 t4_read_reg(sc, reg);
10238 off = tcb_addr - win_pos;
10239 for (i = 0; i < 4; i++) {
10241 for (j = 0; j < 8; j++, off += 4)
10242 buf[j] = htonl(t4_read_reg(sc, base + off));
10244 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
10245 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
10249 t4_write_reg(sc, reg, save);
10250 t4_read_reg(sc, reg);
10254 t4_dump_devlog(struct adapter *sc)
10256 struct devlog_params *dparams = &sc->params.devlog;
10257 struct fw_devlog_e e;
10258 int i, first, j, m, nentries, rc;
10259 uint64_t ftstamp = UINT64_MAX;
10261 if (dparams->start == 0) {
10262 db_printf("devlog params not valid\n");
10266 nentries = dparams->size / sizeof(struct fw_devlog_e);
10267 m = fwmtype_to_hwmtype(dparams->memtype);
10269 /* Find the first entry. */
10271 for (i = 0; i < nentries && !db_pager_quit; i++) {
10272 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10273 sizeof(e), (void *)&e);
10277 if (e.timestamp == 0)
10280 e.timestamp = be64toh(e.timestamp);
10281 if (e.timestamp < ftstamp) {
10282 ftstamp = e.timestamp;
10292 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
10293 sizeof(e), (void *)&e);
10297 if (e.timestamp == 0)
10300 e.timestamp = be64toh(e.timestamp);
10301 e.seqno = be32toh(e.seqno);
10302 for (j = 0; j < 8; j++)
10303 e.params[j] = be32toh(e.params[j]);
10305 db_printf("%10d %15ju %8s %8s ",
10306 e.seqno, e.timestamp,
10307 (e.level < nitems(devlog_level_strings) ?
10308 devlog_level_strings[e.level] : "UNKNOWN"),
10309 (e.facility < nitems(devlog_facility_strings) ?
10310 devlog_facility_strings[e.facility] : "UNKNOWN"));
10311 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
10312 e.params[3], e.params[4], e.params[5], e.params[6],
10315 if (++i == nentries)
10317 } while (i != first && !db_pager_quit);
10320 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
10321 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
10323 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
10330 t = db_read_token();
10332 dev = device_lookup_by_name(db_tok_string);
10337 db_printf("usage: show t4 devlog <nexus>\n");
10342 db_printf("device not found\n");
10346 t4_dump_devlog(device_get_softc(dev));
10349 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
10358 t = db_read_token();
10360 dev = device_lookup_by_name(db_tok_string);
10361 t = db_read_token();
10362 if (t == tNUMBER) {
10363 tid = db_tok_number;
10370 db_printf("usage: show t4 tcb <nexus> <tid>\n");
10375 db_printf("device not found\n");
10379 db_printf("invalid tid\n");
10383 t4_dump_tcb(device_get_softc(dev), tid);
10388 * Borrowed from cesa_prep_aes_key().
10390 * NB: The crypto engine wants the words in the decryption key in reverse
10394 t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits)
10396 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
10400 rijndaelKeySetupEnc(ek, enc_key, kbits);
10402 dkey += (kbits / 8) / 4;
10406 for (i = 0; i < 4; i++)
10407 *--dkey = htobe32(ek[4 * 10 + i]);
10410 for (i = 0; i < 2; i++)
10411 *--dkey = htobe32(ek[4 * 11 + 2 + i]);
10412 for (i = 0; i < 4; i++)
10413 *--dkey = htobe32(ek[4 * 12 + i]);
10416 for (i = 0; i < 4; i++)
10417 *--dkey = htobe32(ek[4 * 13 + i]);
10418 for (i = 0; i < 4; i++)
10419 *--dkey = htobe32(ek[4 * 14 + i]);
10422 MPASS(dkey == dec_key);
10425 static struct sx mlu; /* mod load unload */
10426 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
10429 mod_event(module_t mod, int cmd, void *arg)
10432 static int loaded = 0;
10437 if (loaded++ == 0) {
10439 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10440 t4_filter_rpl, CPL_COOKIE_FILTER);
10441 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL,
10442 do_l2t_write_rpl, CPL_COOKIE_FILTER);
10443 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL,
10444 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER);
10445 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL,
10446 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER);
10447 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS,
10448 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER);
10449 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
10450 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
10451 t4_register_cpl_handler(CPL_SMT_WRITE_RPL,
10453 sx_init(&t4_list_lock, "T4/T5 adapters");
10454 SLIST_INIT(&t4_list);
10456 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
10457 SLIST_INIT(&t4_uld_list);
10459 t4_tracer_modload();
10467 if (--loaded == 0) {
10470 sx_slock(&t4_list_lock);
10471 if (!SLIST_EMPTY(&t4_list)) {
10473 sx_sunlock(&t4_list_lock);
10477 sx_slock(&t4_uld_list_lock);
10478 if (!SLIST_EMPTY(&t4_uld_list)) {
10480 sx_sunlock(&t4_uld_list_lock);
10481 sx_sunlock(&t4_list_lock);
10486 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
10487 uprintf("%ju clusters with custom free routine "
10488 "still is use.\n", t4_sge_extfree_refs());
10489 pause("t4unload", 2 * hz);
10492 sx_sunlock(&t4_uld_list_lock);
10494 sx_sunlock(&t4_list_lock);
10496 if (t4_sge_extfree_refs() == 0) {
10497 t4_tracer_modunload();
10499 sx_destroy(&t4_uld_list_lock);
10501 sx_destroy(&t4_list_lock);
10502 t4_sge_modunload();
10506 loaded++; /* undo earlier decrement */
10517 static devclass_t t4_devclass, t5_devclass, t6_devclass;
10518 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
10519 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
10521 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
10522 MODULE_VERSION(t4nex, 1);
10523 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
10525 MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
10526 #endif /* DEV_NETMAP */
10528 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
10529 MODULE_VERSION(t5nex, 1);
10530 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
10532 MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
10533 #endif /* DEV_NETMAP */
10535 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
10536 MODULE_VERSION(t6nex, 1);
10537 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
10539 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
10540 #endif /* DEV_NETMAP */
10542 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
10543 MODULE_VERSION(cxgbe, 1);
10545 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
10546 MODULE_VERSION(cxl, 1);
10548 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
10549 MODULE_VERSION(cc, 1);
10551 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
10552 MODULE_VERSION(vcxgbe, 1);
10554 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
10555 MODULE_VERSION(vcxl, 1);
10557 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
10558 MODULE_VERSION(vcc, 1);