2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
37 #include <sys/eventhandler.h>
40 #include <sys/module.h>
41 #include <sys/selinfo.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <machine/bus.h>
45 #include <net/ethernet.h>
47 #include <net/if_media.h>
48 #include <net/if_var.h>
49 #include <net/if_clone.h>
50 #include <net/if_types.h>
51 #include <net/netmap.h>
52 #include <dev/netmap/netmap_kern.h>
54 #include "common/common.h"
55 #include "common/t4_regs.h"
56 #include "common/t4_regs_values.h"
58 extern int fl_pad; /* XXXNM */
61 * 0 = normal netmap rx
63 * 2 = supermassive black hole (buffer packing enabled)
66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
67 "Sink incoming packets.");
70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN,
75 &rx_nframes, 0, "max # of frames received before waking up netmap rx.");
77 int holdoff_tmr_idx = 2;
78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
83 * -1: no congestion feedback (not recommended).
84 * 0: backpressure the channel instead of dropping packets right away.
85 * 1: no backpressure, drop packets for the congested queue immediately.
87 static int nm_cong_drop = 1;
88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RDTUN,
90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop");
93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN,
94 &starve_fl, 0, "Don't ring fl db for netmap rx queues.");
97 * Try to process tx credits in bulk. This may cause a delay in the return of
98 * tx credits and is suitable for bursty or non-stop tx only.
100 int lazy_tx_credit_flush = 1;
101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN,
102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues.");
105 * Split the netmap rx queues into two groups that populate separate halves of
106 * the RSS indirection table. This allows filters with hashmask to steer to a
107 * particular group of queues.
109 static int nm_split_rss = 0;
110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN,
111 &nm_split_rss, 0, "Split the netmap rx queues into two groups.");
114 * netmap(4) says "netmap does not use features such as checksum offloading, TCP
115 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc."
116 * but this knob can be used to get the hardware to checksum all tx traffic
119 static int nm_txcsum = 0;
120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN,
121 &nm_txcsum, 0, "Enable transmit checksum offloading.");
124 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
128 struct adapter *sc = vi->pi->adapter;
129 struct sge_params *sp = &sc->params.sge;
130 struct netmap_adapter *na = NA(vi->ifp);
134 MPASS(nm_rxq->iq_desc != NULL);
135 MPASS(nm_rxq->fl_desc != NULL);
137 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
138 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
140 bzero(&c, sizeof(c));
141 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
142 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
144 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
146 MPASS(!forwarding_intr_to_fwq(sc));
147 KASSERT(nm_rxq->intr_idx < sc->intr_count,
148 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
149 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
150 c.type_to_iqandstindex = htobe32(v |
151 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
152 V_FW_IQ_CMD_VIID(vi->viid) |
153 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
154 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
155 F_FW_IQ_CMD_IQGTSMODE |
156 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
157 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
158 c.iqsize = htobe16(vi->qsize_rxq);
159 c.iqaddr = htobe64(nm_rxq->iq_ba);
161 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
162 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
163 F_FW_IQ_CMD_FL0CONGEN);
165 c.iqns_to_fl0congen |=
166 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
167 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
168 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
169 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
170 c.fl0dcaen_to_fl0cidxfthresh =
171 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
172 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
173 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
174 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
175 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
176 c.fl0addr = htobe64(nm_rxq->fl_ba);
178 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
180 device_printf(sc->dev,
181 "failed to create netmap ingress queue: %d\n", rc);
186 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
187 nm_rxq->iq_gen = F_RSPD_GEN;
188 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
189 nm_rxq->iq_abs_id = be16toh(c.physiqid);
190 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
191 if (cntxt_id >= sc->sge.niq) {
192 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
193 __func__, cntxt_id, sc->sge.niq - 1);
195 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
197 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
198 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
199 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
200 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
201 if (cntxt_id >= sc->sge.neq) {
202 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
203 __func__, cntxt_id, sc->sge.neq - 1);
205 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
207 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
208 sc->chip_params->sge_fl_db;
210 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
213 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
214 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
215 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
216 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
217 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
218 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
223 for (i = 0; i < 4; i++) {
225 val |= 1 << (i << 2);
229 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
231 /* report error but carry on */
232 device_printf(sc->dev,
233 "failed to set congestion manager context for "
234 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
238 t4_write_reg(sc, sc->sge_gts_reg,
239 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
240 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
246 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
248 struct adapter *sc = vi->pi->adapter;
251 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
252 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
254 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
255 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
256 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
261 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
265 struct adapter *sc = vi->pi->adapter;
266 struct netmap_adapter *na = NA(vi->ifp);
267 struct fw_eq_eth_cmd c;
270 MPASS(nm_txq->desc != NULL);
272 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
273 bzero(nm_txq->desc, len);
275 bzero(&c, sizeof(c));
276 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
277 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
278 V_FW_EQ_ETH_CMD_VFN(0));
279 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
280 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
281 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
282 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
284 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
285 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
286 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
288 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
289 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
290 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
291 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
292 c.eqaddr = htobe64(nm_txq->ba);
294 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
296 device_printf(vi->dev,
297 "failed to create netmap egress queue: %d\n", rc);
301 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
302 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
303 if (cntxt_id >= sc->sge.neq)
304 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
305 cntxt_id, sc->sge.neq - 1);
306 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
308 nm_txq->pidx = nm_txq->cidx = 0;
309 MPASS(nm_txq->sidx == na->num_tx_desc);
310 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
312 nm_txq->doorbells = sc->doorbells;
313 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
314 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
315 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
316 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
317 uint32_t mask = (1 << s_qpp) - 1;
318 volatile uint8_t *udb;
320 udb = sc->udbs_base + UDBS_DB_OFFSET;
321 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
322 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
323 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
324 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
326 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
329 nm_txq->udb = (volatile void *)udb;
336 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
338 struct adapter *sc = vi->pi->adapter;
341 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
343 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
344 nm_txq->cntxt_id, rc);
345 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
350 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
351 struct netmap_adapter *na)
353 struct netmap_slot *slot;
354 struct netmap_kring *kring;
355 struct sge_nm_rxq *nm_rxq;
356 struct sge_nm_txq *nm_txq;
357 int rc, i, j, hwidx, defq, nrssq;
358 struct hw_buf_info *hwb;
360 ASSERT_SYNCHRONIZED_OP(sc);
362 if ((vi->flags & VI_INIT_DONE) == 0 ||
363 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
366 hwb = &sc->sge.hw_buf_info[0];
367 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
368 if (hwb->size == NETMAP_BUF_SIZE(na))
371 if (i >= SGE_FLBUF_SIZES) {
372 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
373 NETMAP_BUF_SIZE(na));
378 /* Must set caps before calling netmap_reset */
379 nm_set_native_flags(na);
381 for_each_nm_rxq(vi, i, nm_rxq) {
382 kring = na->rx_rings[nm_rxq->nid];
383 if (!nm_kring_pending_on(kring) ||
384 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
387 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
388 nm_rxq->fl_hwidx = hwidx;
389 slot = netmap_reset(na, NR_RX, i, 0);
390 MPASS(slot != NULL); /* XXXNM: error check, not assert */
392 /* We deal with 8 bufs at a time */
393 MPASS((na->num_rx_desc & 7) == 0);
394 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
395 for (j = 0; j < nm_rxq->fl_sidx; j++) {
398 PNMB(na, &slot[j], &ba);
400 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
402 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
404 j /= 8; /* driver pidx to hardware pidx */
406 t4_write_reg(sc, sc->sge_kdoorbell_reg,
407 nm_rxq->fl_db_val | V_PIDX(j));
409 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
412 for_each_nm_txq(vi, i, nm_txq) {
413 kring = na->tx_rings[nm_txq->nid];
414 if (!nm_kring_pending_on(kring) ||
415 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
418 alloc_nm_txq_hwq(vi, nm_txq);
419 slot = netmap_reset(na, NR_TX, i, 0);
420 MPASS(slot != NULL); /* XXXNM: error check, not assert */
423 if (vi->nm_rss == NULL) {
424 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
428 MPASS(vi->nnmrxq > 0);
429 if (nm_split_rss == 0 || vi->nnmrxq == 1) {
430 for (i = 0; i < vi->rss_size;) {
431 for_each_nm_rxq(vi, j, nm_rxq) {
432 vi->nm_rss[i++] = nm_rxq->iq_abs_id;
433 if (i == vi->rss_size)
437 defq = vi->nm_rss[0];
439 /* We have multiple queues and we want to split the table. */
440 MPASS(nm_split_rss != 0);
441 MPASS(vi->nnmrxq > 1);
443 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq];
445 if (vi->nnmrxq & 1) {
447 * Odd number of queues. The first rxq is designated the
448 * default queue, the rest are split evenly.
450 defq = nm_rxq->iq_abs_id;
455 * Even number of queues split into two halves. The
456 * first rxq in one of the halves is designated the
460 /* First rxq in the first half. */
461 defq = nm_rxq->iq_abs_id;
463 /* First rxq in the second half. */
464 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id;
469 while (i < vi->rss_size / 2) {
470 for (j = 0; j < nrssq / 2; j++) {
471 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
472 if (i == vi->rss_size / 2)
476 while (i < vi->rss_size) {
477 for (j = nrssq / 2; j < nrssq; j++) {
478 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
479 if (i == vi->rss_size)
484 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
485 vi->nm_rss, vi->rss_size);
487 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
489 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
491 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc);
497 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
498 struct netmap_adapter *na)
500 struct netmap_kring *kring;
502 struct sge_nm_txq *nm_txq;
503 struct sge_nm_rxq *nm_rxq;
505 ASSERT_SYNCHRONIZED_OP(sc);
507 if (!nm_netmap_on(na))
510 if ((vi->flags & VI_INIT_DONE) == 0)
513 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
514 vi->rss, vi->rss_size);
516 if_printf(ifp, "failed to restore RSS config: %d\n", rc);
517 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0);
519 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc);
520 nm_clear_native_flags(na);
522 for_each_nm_txq(vi, i, nm_txq) {
523 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
525 kring = na->tx_rings[nm_txq->nid];
526 if (!nm_kring_pending_off(kring) ||
527 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
530 /* Wait for hw pidx to catch up ... */
531 while (be16toh(nm_txq->pidx) != spg->pidx)
534 /* ... and then for the cidx. */
535 while (spg->pidx != spg->cidx)
538 free_nm_txq_hwq(vi, nm_txq);
540 for_each_nm_rxq(vi, i, nm_rxq) {
541 kring = na->rx_rings[nm_rxq->nid];
542 if (!nm_kring_pending_off(kring) ||
543 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
546 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
549 free_nm_rxq_hwq(vi, nm_rxq);
556 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
558 struct ifnet *ifp = na->ifp;
559 struct vi_info *vi = ifp->if_softc;
560 struct adapter *sc = vi->pi->adapter;
563 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
567 rc = cxgbe_netmap_on(sc, vi, ifp, na);
569 rc = cxgbe_netmap_off(sc, vi, ifp, na);
570 end_synchronized_op(sc, 0);
575 /* How many packets can a single type1 WR carry in n descriptors */
577 ndesc_to_npkt(const int n)
580 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
584 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
587 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
591 npkt_to_ndesc(const int n)
594 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
596 return ((n + 2) / 2);
600 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
604 npkt_to_len16(const int n)
607 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
612 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
615 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
618 u_int db = nm_txq->doorbells;
620 MPASS(nm_txq->pidx != nm_txq->dbidx);
622 n = NMIDXDIFF(nm_txq, dbidx);
624 clrbit(&db, DOORBELL_WCWR);
627 switch (ffs(db) - 1) {
629 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
632 case DOORBELL_WCWR: {
633 volatile uint64_t *dst, *src;
636 * Queues whose 128B doorbell segment fits in the page do not
637 * use relative qid (udb_qid is always 0). Only queues with
638 * doorbell segments can do WCWR.
640 KASSERT(nm_txq->udb_qid == 0 && n == 1,
641 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
642 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
644 dst = (volatile void *)((uintptr_t)nm_txq->udb +
645 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
646 src = (void *)&nm_txq->desc[nm_txq->dbidx];
647 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
654 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
659 t4_write_reg(sc, sc->sge_kdoorbell_reg,
660 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
663 nm_txq->dbidx = nm_txq->pidx;
667 * Write work requests to send 'npkt' frames and ring the doorbell to send them
668 * on their way. No need to check for wraparound.
671 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
672 struct netmap_kring *kring, int npkt, int npkt_remaining)
674 struct netmap_ring *ring = kring->ring;
675 struct netmap_slot *slot;
676 const u_int lim = kring->nkr_num_slots - 1;
677 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
680 struct cpl_tx_pkt_core *cpl;
681 struct ulptx_sgl *usgl;
685 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
688 wr = (void *)&nm_txq->desc[nm_txq->pidx];
689 wr->op_pkd = nm_txq->op_pkd;
690 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
694 cpl = (void *)(wr + 1);
696 for (i = 0; i < n; i++) {
697 slot = &ring->slot[kring->nr_hwcur];
698 PNMB(kring->na, slot, &ba);
701 cpl->ctrl0 = nm_txq->cpl_ctrl0;
703 cpl->len = htobe16(slot->len);
704 cpl->ctrl1 = nm_txcsum ? 0 :
705 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
707 usgl = (void *)(cpl + 1);
708 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
710 usgl->len0 = htobe32(slot->len);
711 usgl->addr0 = htobe64(ba);
713 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
714 cpl = (void *)(usgl + 1);
715 MPASS(slot->len + len <= UINT16_MAX);
717 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
719 wr->plen = htobe16(len);
722 nm_txq->pidx += npkt_to_ndesc(n);
723 MPASS(nm_txq->pidx <= nm_txq->sidx);
724 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
726 * This routine doesn't know how to write WRs that wrap
727 * around. Make sure it wasn't asked to.
733 if (npkt == 0 && npkt_remaining == 0) {
735 if (lazy_tx_credit_flush == 0) {
736 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
738 nm_txq->equeqidx = nm_txq->pidx;
739 nm_txq->equiqidx = nm_txq->pidx;
741 ring_nm_txq_db(sc, nm_txq);
745 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
746 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
748 nm_txq->equeqidx = nm_txq->pidx;
749 nm_txq->equiqidx = nm_txq->pidx;
750 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
751 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
752 nm_txq->equeqidx = nm_txq->pidx;
754 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
755 ring_nm_txq_db(sc, nm_txq);
758 /* Will get called again. */
759 MPASS(npkt_remaining);
762 /* How many contiguous free descriptors starting at pidx */
764 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
767 if (nm_txq->cidx > nm_txq->pidx)
768 return (nm_txq->cidx - nm_txq->pidx - 1);
769 else if (nm_txq->cidx > 0)
770 return (nm_txq->sidx - nm_txq->pidx);
772 return (nm_txq->sidx - nm_txq->pidx - 1);
776 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
778 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
779 uint16_t hw_cidx = spg->cidx; /* snapshot */
780 struct fw_eth_tx_pkts_wr *wr;
783 hw_cidx = be16toh(hw_cidx);
785 while (nm_txq->cidx != hw_cidx) {
786 wr = (void *)&nm_txq->desc[nm_txq->cidx];
788 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) ||
789 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)));
790 MPASS(wr->type == 1);
791 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
794 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
797 * We never sent a WR that wrapped around so the credits coming
798 * back, WR by WR, should never cause the cidx to wrap around
801 MPASS(nm_txq->cidx <= nm_txq->sidx);
802 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
810 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
812 struct netmap_adapter *na = kring->na;
813 struct ifnet *ifp = na->ifp;
814 struct vi_info *vi = ifp->if_softc;
815 struct adapter *sc = vi->pi->adapter;
816 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
817 const u_int head = kring->rhead;
819 int n, d, npkt_remaining, ndesc_remaining;
822 * Tx was at kring->nr_hwcur last time around and now we need to advance
823 * to kring->rhead. Note that the driver's pidx moves independent of
824 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
825 * between descriptors and frames isn't 1:1).
828 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
829 kring->nkr_num_slots - kring->nr_hwcur + head;
830 while (npkt_remaining) {
831 reclaimed += reclaim_nm_tx_desc(nm_txq);
832 ndesc_remaining = contiguous_ndesc_available(nm_txq);
833 /* Can't run out of descriptors with packets still remaining */
834 MPASS(ndesc_remaining > 0);
836 /* # of desc needed to tx all remaining packets */
837 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
838 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
839 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
841 if (d <= ndesc_remaining)
844 /* Can't send all, calculate how many can be sent */
845 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
846 MAX_NPKT_IN_TYPE1_WR;
847 if (ndesc_remaining % SGE_MAX_WR_NDESC)
848 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
851 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
853 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining);
855 MPASS(npkt_remaining == 0);
856 MPASS(kring->nr_hwcur == head);
857 MPASS(nm_txq->dbidx == nm_txq->pidx);
860 * Second part: reclaim buffers for completed transmissions.
862 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
863 reclaimed += reclaim_nm_tx_desc(nm_txq);
864 kring->nr_hwtail += reclaimed;
865 if (kring->nr_hwtail >= kring->nkr_num_slots)
866 kring->nr_hwtail -= kring->nkr_num_slots;
873 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
875 struct netmap_adapter *na = kring->na;
876 struct netmap_ring *ring = kring->ring;
877 struct ifnet *ifp = na->ifp;
878 struct vi_info *vi = ifp->if_softc;
879 struct adapter *sc = vi->pi->adapter;
880 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
881 u_int const head = kring->rhead;
883 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
886 return (0); /* No updates ever. */
888 if (netmap_no_pendintr || force_update) {
889 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
890 kring->nr_kflags &= ~NKR_PENDINTR;
893 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
895 t4_write_reg(sc, sc->sge_kdoorbell_reg,
896 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
897 nm_rxq->fl_db_saved = 0;
900 /* Userspace done with buffers from kring->nr_hwcur to head */
901 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
902 kring->nkr_num_slots - kring->nr_hwcur + head;
905 u_int fl_pidx = nm_rxq->fl_pidx;
906 struct netmap_slot *slot = &ring->slot[fl_pidx];
908 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
911 * We always deal with 8 buffers at a time. We must have
912 * stopped at an 8B boundary (fl_pidx) last time around and we
913 * must have a multiple of 8B buffers to give to the freelist.
915 MPASS((fl_pidx & 7) == 0);
918 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
919 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
922 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
925 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
926 slot->flags &= ~NS_BUF_CHANGED;
927 MPASS(fl_pidx <= nm_rxq->fl_sidx);
930 if (fl_pidx == nm_rxq->fl_sidx) {
932 slot = &ring->slot[0];
934 if (++dbinc == 8 && n >= 32) {
937 nm_rxq->fl_db_saved += dbinc;
939 t4_write_reg(sc, sc->sge_kdoorbell_reg,
940 nm_rxq->fl_db_val | V_PIDX(dbinc));
945 MPASS(nm_rxq->fl_pidx == fl_pidx);
950 nm_rxq->fl_db_saved += dbinc;
952 t4_write_reg(sc, sc->sge_kdoorbell_reg,
953 nm_rxq->fl_db_val | V_PIDX(dbinc));
962 cxgbe_nm_attach(struct vi_info *vi)
964 struct port_info *pi;
966 struct netmap_adapter na;
968 MPASS(vi->nnmrxq > 0);
969 MPASS(vi->ifp != NULL);
974 bzero(&na, sizeof(na));
977 na.na_flags = NAF_BDG_MAYSLEEP;
979 /* Netmap doesn't know about the space reserved for the status page. */
980 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
983 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
984 * num_rx_desc is based on the number of buffers that can be held in the
985 * freelist, and not the number of entries in the iq. (These two are
986 * not exactly the same due to the space taken up by the status page).
988 na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
989 na.nm_txsync = cxgbe_netmap_txsync;
990 na.nm_rxsync = cxgbe_netmap_rxsync;
991 na.nm_register = cxgbe_netmap_reg;
992 na.num_tx_rings = vi->nnmtxq;
993 na.num_rx_rings = vi->nnmrxq;
994 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
998 cxgbe_nm_detach(struct vi_info *vi)
1001 MPASS(vi->nnmrxq > 0);
1002 MPASS(vi->ifp != NULL);
1004 netmap_detach(vi->ifp);
1007 static inline const void *
1008 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
1011 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
1013 /* data[0] is RSS header */
1014 return (&cpl->data[1]);
1018 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
1019 const struct cpl_sge_egr_update *egr)
1022 struct sge_nm_txq *nm_txq;
1024 oq = be32toh(egr->opcode_qid);
1025 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1026 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1028 netmap_tx_irq(ifp, nm_txq->nid);
1032 service_nm_rxq(struct sge_nm_rxq *nm_rxq)
1034 struct vi_info *vi = nm_rxq->vi;
1035 struct adapter *sc = vi->pi->adapter;
1036 struct ifnet *ifp = vi->ifp;
1037 struct netmap_adapter *na = NA(ifp);
1038 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
1039 struct netmap_ring *ring = kring->ring;
1040 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1045 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1046 u_int fl_credits = fl_cidx & 7;
1047 u_int ndesc = 0; /* desc processed since last cidx update */
1048 u_int nframes = 0; /* frames processed since last netmap wakeup */
1050 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1054 lq = be32toh(d->rsp.pldbuflen_qid);
1055 opcode = d->rss.opcode;
1058 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1059 case X_RSPD_TYPE_FLBUF:
1063 case X_RSPD_TYPE_CPL:
1064 MPASS(opcode < NUM_CPL_CMDS);
1069 cpl = unwrap_nm_fw6_msg(cpl);
1071 case CPL_SGE_EGR_UPDATE:
1072 handle_nm_sge_egr_update(sc, ifp, cpl);
1075 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1076 sc->params.sge.fl_pktshift;
1077 ring->slot[fl_cidx].flags = 0;
1079 if (!(lq & F_RSPD_NEWBUF)) {
1080 MPASS(black_hole == 2);
1084 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1088 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1089 __func__, opcode, nm_rxq);
1093 case X_RSPD_TYPE_INTR:
1094 /* Not equipped to handle forwarded interrupts. */
1095 panic("%s: netmap queue received interrupt for iq %u\n",
1099 panic("%s: illegal response type %d on nm_rxq %p",
1100 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1104 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1105 nm_rxq->iq_cidx = 0;
1106 d = &nm_rxq->iq_desc[0];
1107 nm_rxq->iq_gen ^= F_RSPD_GEN;
1110 if (__predict_false(++nframes == rx_nframes) && !black_hole) {
1111 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1112 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1116 if (__predict_false(++ndesc == rx_ndesc)) {
1117 if (black_hole && fl_credits >= 8) {
1119 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1121 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1122 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1123 fl_credits = fl_cidx & 7;
1125 t4_write_reg(sc, sc->sge_gts_reg,
1127 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1128 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1133 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1136 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1137 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1138 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1139 } else if (nframes > 0)
1140 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1142 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1143 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1144 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));