sys/dev/cxgbe/t4_netmap.c

   1 /*-
   2  * Copyright (c) 2014 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  * Written by: Navdeep Parhar <np@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_inet.h"
  32 #include "opt_inet6.h"
  33
  34 #ifdef DEV_NETMAP
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/eventhandler.h>
  38 #include <sys/lock.h>
  39 #include <sys/mbuf.h>
  40 #include <sys/module.h>
  41 #include <sys/selinfo.h>
  42 #include <sys/socket.h>
  43 #include <sys/sockio.h>
  44 #include <machine/bus.h>
  45 #include <net/ethernet.h>
  46 #include <net/if.h>
  47 #include <net/if_media.h>
  48 #include <net/if_var.h>
  49 #include <net/if_clone.h>
  50 #include <net/if_types.h>
  51 #include <net/netmap.h>
  52 #include <dev/netmap/netmap_kern.h>
  53
  54 #include "common/common.h"
  55 #include "common/t4_regs.h"
  56 #include "common/t4_regs_values.h"
  57
  58 extern int fl_pad;      /* XXXNM */
  59
  60 /*
  61  * 0 = normal netmap rx
  62  * 1 = black hole
  63  * 2 = supermassive black hole (buffer packing enabled)
  64  */
  65 int black_hole = 0;
  66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0,
  67     "Sink incoming packets.");
  68
  69 int rx_ndesc = 256;
  70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
  71     &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
  72
  73 int rx_nframes = 64;
  74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN,
  75     &rx_nframes, 0, "max # of frames received before waking up netmap rx.");
  76
  77 int holdoff_tmr_idx = 2;
  78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
  79     &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
  80
  81 /*
  82  * Congestion drops.
  83  * -1: no congestion feedback (not recommended).
  84  *  0: backpressure the channel instead of dropping packets right away.
  85  *  1: no backpressure, drop packets for the congested queue immediately.
  86  */
  87 static int nm_cong_drop = 1;
  88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN,
  89     &nm_cong_drop, 0,
  90     "Congestion control for netmap rx queues (0 = backpressure, 1 = drop");
  91
  92 int starve_fl = 0;
  93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN,
  94     &starve_fl, 0, "Don't ring fl db for netmap rx queues.");
  95
  96 /*
  97  * Try to process tx credits in bulk.  This may cause a delay in the return of
  98  * tx credits and is suitable for bursty or non-stop tx only.
  99  */
 100 int lazy_tx_credit_flush = 1;
 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN,
 102     &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues.");
 103
 104 /*
 105  * Split the netmap rx queues into two groups that populate separate halves of
 106  * the RSS indirection table.  This allows filters with hashmask to steer to a
 107  * particular group of queues.
 108  */
 109 static int nm_split_rss = 0;
 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN,
 111     &nm_split_rss, 0, "Split the netmap rx queues into two groups.");
 112
 113 /*
 114  * netmap(4) says "netmap does not use features such as checksum offloading, TCP
 115  * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc."
 116  * but this knob can be used to get the hardware to checksum all tx traffic
 117  * anyway.
 118  */
 119 static int nm_txcsum = 0;
 120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN,
 121     &nm_txcsum, 0, "Enable transmit checksum offloading.");
 122
 123 static int free_nm_rxq_hwq(struct vi_info *, struct sge_nm_rxq *);
 124 static int free_nm_txq_hwq(struct vi_info *, struct sge_nm_txq *);
 125
 126 int
 127 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
 128     int idx)
 129 {
 130         int rc;
 131         struct sysctl_oid *oid;
 132         struct sysctl_oid_list *children;
 133         struct sysctl_ctx_list *ctx;
 134         char name[16];
 135         size_t len;
 136         struct adapter *sc = vi->adapter;
 137         struct netmap_adapter *na = NA(vi->ifp);
 138
 139         MPASS(na != NULL);
 140
 141         len = vi->qsize_rxq * IQ_ESIZE;
 142         rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
 143             &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
 144         if (rc != 0)
 145                 return (rc);
 146
 147         len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
 148         rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
 149             &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
 150         if (rc != 0)
 151                 return (rc);
 152
 153         nm_rxq->vi = vi;
 154         nm_rxq->nid = idx;
 155         nm_rxq->iq_cidx = 0;
 156         nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
 157         nm_rxq->iq_gen = F_RSPD_GEN;
 158         nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
 159         nm_rxq->fl_sidx = na->num_rx_desc;
 160         nm_rxq->fl_sidx2 = nm_rxq->fl_sidx;     /* copy for rxsync cacheline */
 161         nm_rxq->intr_idx = intr_idx;
 162         nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
 163
 164         ctx = &vi->ctx;
 165         children = SYSCTL_CHILDREN(vi->nm_rxq_oid);
 166
 167         snprintf(name, sizeof(name), "%d", idx);
 168         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name,
 169             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
 170         children = SYSCTL_CHILDREN(oid);
 171
 172         SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
 173             &nm_rxq->iq_abs_id, 0, "absolute id of the queue");
 174         SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
 175             &nm_rxq->iq_cntxt_id, 0, "SGE context id of the queue");
 176         SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
 177             &nm_rxq->iq_cidx, 0, "consumer index");
 178
 179         children = SYSCTL_CHILDREN(oid);
 180         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
 181             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
 182         children = SYSCTL_CHILDREN(oid);
 183
 184         SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
 185             &nm_rxq->fl_cntxt_id, 0, "SGE context id of the freelist");
 186         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
 187             &nm_rxq->fl_cidx, 0, "consumer index");
 188         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
 189             &nm_rxq->fl_pidx, 0, "producer index");
 190
 191         return (rc);
 192 }
 193
 194 int
 195 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 196 {
 197         struct adapter *sc = vi->adapter;
 198
 199         if (!(vi->flags & VI_INIT_DONE))
 200                 return (0);
 201
 202         if (nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
 203                 free_nm_rxq_hwq(vi, nm_rxq);
 204         MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
 205
 206         free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
 207             nm_rxq->iq_desc);
 208         free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
 209             nm_rxq->fl_desc);
 210
 211         return (0);
 212 }
 213
 214 int
 215 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx)
 216 {
 217         int rc;
 218         size_t len;
 219         struct port_info *pi = vi->pi;
 220         struct adapter *sc = pi->adapter;
 221         struct netmap_adapter *na = NA(vi->ifp);
 222         char name[16];
 223         struct sysctl_oid *oid;
 224         struct sysctl_oid_list *children = SYSCTL_CHILDREN(vi->nm_txq_oid);
 225
 226         len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
 227         rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
 228             &nm_txq->ba, (void **)&nm_txq->desc);
 229         if (rc)
 230                 return (rc);
 231
 232         nm_txq->pidx = nm_txq->cidx = 0;
 233         nm_txq->sidx = na->num_tx_desc;
 234         nm_txq->nid = idx;
 235         nm_txq->iqidx = iqidx;
 236         nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
 237             V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
 238             V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
 239         if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0))
 240                 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
 241         else
 242                 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
 243         nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
 244
 245         snprintf(name, sizeof(name), "%d", idx);
 246         oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
 247             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queue");
 248         children = SYSCTL_CHILDREN(oid);
 249
 250         SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
 251             &nm_txq->cntxt_id, 0, "SGE context id of the queue");
 252         SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
 253             &nm_txq->cidx, 0, "consumer index");
 254         SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
 255             &nm_txq->pidx, 0, "producer index");
 256
 257         return (rc);
 258 }
 259
 260 int
 261 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 262 {
 263         struct adapter *sc = vi->adapter;
 264
 265         if (!(vi->flags & VI_INIT_DONE))
 266                 return (0);
 267
 268         if (nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
 269                 free_nm_txq_hwq(vi, nm_txq);
 270         MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
 271
 272         free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
 273             nm_txq->desc);
 274
 275         return (0);
 276 }
 277
 278 static int
 279 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
 280 {
 281         int rc, cntxt_id, i;
 282         __be32 v;
 283         struct adapter *sc = vi->adapter;
 284         struct sge_params *sp = &sc->params.sge;
 285         struct netmap_adapter *na = NA(vi->ifp);
 286         struct fw_iq_cmd c;
 287
 288         MPASS(na != NULL);
 289         MPASS(nm_rxq->iq_desc != NULL);
 290         MPASS(nm_rxq->fl_desc != NULL);
 291
 292         bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
 293         bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
 294
 295         bzero(&c, sizeof(c));
 296         c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
 297             F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
 298             V_FW_IQ_CMD_VFN(0));
 299         c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_IQSTART | FW_LEN16(c));
 300         if (nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
 301                 c.alloc_to_len16 |= htobe32(F_FW_IQ_CMD_ALLOC);
 302         else {
 303                 c.iqid = htobe16(nm_rxq->iq_cntxt_id);
 304                 c.fl0id = htobe16(nm_rxq->fl_cntxt_id);
 305                 c.fl1id = htobe16(0xffff);
 306                 c.physiqid = htobe16(nm_rxq->iq_abs_id);
 307         }
 308         MPASS(!forwarding_intr_to_fwq(sc));
 309         KASSERT(nm_rxq->intr_idx < sc->intr_count,
 310             ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
 311         v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
 312         c.type_to_iqandstindex = htobe32(v |
 313             V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
 314             V_FW_IQ_CMD_VIID(vi->viid) |
 315             V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
 316         c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
 317             F_FW_IQ_CMD_IQGTSMODE |
 318             V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
 319             V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
 320         c.iqsize = htobe16(vi->qsize_rxq);
 321         c.iqaddr = htobe64(nm_rxq->iq_ba);
 322         if (cong >= 0) {
 323                 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
 324                     V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
 325                     F_FW_IQ_CMD_FL0CONGEN);
 326         }
 327         c.iqns_to_fl0congen |=
 328             htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
 329                 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
 330                 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
 331                 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
 332         c.fl0dcaen_to_fl0cidxfthresh =
 333             htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
 334                 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
 335                 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
 336                 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
 337         c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
 338         c.fl0addr = htobe64(nm_rxq->fl_ba);
 339
 340         rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 341         if (rc != 0) {
 342                 device_printf(sc->dev,
 343                     "failed to create netmap ingress queue: %d\n", rc);
 344                 return (rc);
 345         }
 346
 347         nm_rxq->iq_cidx = 0;
 348         MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
 349         nm_rxq->iq_gen = F_RSPD_GEN;
 350         nm_rxq->iq_cntxt_id = be16toh(c.iqid);
 351         nm_rxq->iq_abs_id = be16toh(c.physiqid);
 352         cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
 353         if (cntxt_id >= sc->sge.iqmap_sz) {
 354                 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
 355                     __func__, cntxt_id, sc->sge.iqmap_sz - 1);
 356         }
 357         sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
 358
 359         nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
 360         nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
 361         nm_rxq->fl_db_saved = 0;
 362         /* matches the X_FETCHBURSTMAX_512B or X_FETCHBURSTMAX_256B above. */
 363         nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4;
 364         MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
 365         cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
 366         if (cntxt_id >= sc->sge.eqmap_sz) {
 367                 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
 368                     __func__, cntxt_id, sc->sge.eqmap_sz - 1);
 369         }
 370         sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
 371
 372         nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
 373             sc->chip_params->sge_fl_db;
 374
 375         if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
 376                 uint32_t param, val;
 377
 378                 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 379                     V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
 380                     V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
 381                 if (cong == 0)
 382                         val = 1 << 19;
 383                 else {
 384                         val = 2 << 19;
 385                         for (i = 0; i < 4; i++) {
 386                                 if (cong & (1 << i))
 387                                         val |= 1 << (i << 2);
 388                         }
 389                 }
 390
 391                 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 392                 if (rc != 0) {
 393                         /* report error but carry on */
 394                         device_printf(sc->dev,
 395                             "failed to set congestion manager context for "
 396                             "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
 397                 }
 398         }
 399
 400         t4_write_reg(sc, sc->sge_gts_reg,
 401             V_INGRESSQID(nm_rxq->iq_cntxt_id) |
 402             V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
 403
 404         return (rc);
 405 }
 406
 407 static int
 408 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 409 {
 410         struct adapter *sc = vi->adapter;
 411         int rc;
 412
 413         rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
 414             nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
 415         if (rc != 0)
 416                 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
 417                     __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
 418         nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
 419         return (rc);
 420 }
 421
 422 static int
 423 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 424 {
 425         int rc, cntxt_id;
 426         size_t len;
 427         struct adapter *sc = vi->adapter;
 428         struct netmap_adapter *na = NA(vi->ifp);
 429         struct fw_eq_eth_cmd c;
 430
 431         MPASS(na != NULL);
 432         MPASS(nm_txq->desc != NULL);
 433
 434         len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
 435         bzero(nm_txq->desc, len);
 436
 437         bzero(&c, sizeof(c));
 438         c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
 439             F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
 440             V_FW_EQ_ETH_CMD_VFN(0));
 441         c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
 442         if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
 443                 c.alloc_to_len16 |= htobe32(F_FW_EQ_ETH_CMD_ALLOC);
 444         else
 445                 c.eqid_pkd = htobe32(V_FW_EQ_ETH_CMD_EQID(nm_txq->cntxt_id));
 446         c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
 447             F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
 448         c.fetchszm_to_iqid =
 449             htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
 450                 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
 451                 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
 452         c.dcaen_to_eqsize =
 453             htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
 454                 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
 455                 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
 456                 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
 457         c.eqaddr = htobe64(nm_txq->ba);
 458
 459         rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 460         if (rc != 0) {
 461                 device_printf(vi->dev,
 462                     "failed to create netmap egress queue: %d\n", rc);
 463                 return (rc);
 464         }
 465
 466         nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
 467         cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
 468         if (cntxt_id >= sc->sge.eqmap_sz)
 469             panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
 470                 cntxt_id, sc->sge.eqmap_sz - 1);
 471         sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
 472
 473         nm_txq->pidx = nm_txq->cidx = 0;
 474         MPASS(nm_txq->sidx == na->num_tx_desc);
 475         nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
 476
 477         nm_txq->doorbells = sc->doorbells;
 478         if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
 479             isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
 480             isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
 481                 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
 482                 uint32_t mask = (1 << s_qpp) - 1;
 483                 volatile uint8_t *udb;
 484
 485                 udb = sc->udbs_base + UDBS_DB_OFFSET;
 486                 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
 487                 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
 488                 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
 489                         clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
 490                 else {
 491                         udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
 492                         nm_txq->udb_qid = 0;
 493                 }
 494                 nm_txq->udb = (volatile void *)udb;
 495         }
 496
 497         if (sc->params.fw_vers < FW_VERSION32(1, 25, 1, 0)) {
 498                 uint32_t param, val;
 499
 500                 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 501                     V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
 502                     V_FW_PARAMS_PARAM_YZ(nm_txq->cntxt_id);
 503                 val = 0xff;
 504                 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 505                 if (rc != 0) {
 506                         device_printf(vi->dev,
 507                             "failed to bind netmap txq %d to class 0xff: %d\n",
 508                             nm_txq->cntxt_id, rc);
 509                         rc = 0;
 510                 }
 511         }
 512
 513         return (rc);
 514 }
 515
 516 static int
 517 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 518 {
 519         struct adapter *sc = vi->adapter;
 520         int rc;
 521
 522         rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
 523         if (rc != 0)
 524                 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
 525                     nm_txq->cntxt_id, rc);
 526         nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
 527         return (rc);
 528 }
 529
 530 static int
 531 cxgbe_netmap_simple_rss(struct adapter *sc, struct vi_info *vi,
 532     struct ifnet *ifp, struct netmap_adapter *na)
 533 {
 534         struct netmap_kring *kring;
 535         struct sge_nm_rxq *nm_rxq;
 536         int rc, i, j, nm_state, defq;
 537         uint16_t *rss;
 538
 539         /*
 540          * Check if there's at least one active (or about to go active) netmap
 541          * rx queue.
 542          */
 543         defq = -1;
 544         for_each_nm_rxq(vi, j, nm_rxq) {
 545                 nm_state = atomic_load_int(&nm_rxq->nm_state);
 546                 kring = na->rx_rings[nm_rxq->nid];
 547                 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) ||
 548                     (nm_state == NM_OFF && nm_kring_pending_on(kring))) {
 549                         MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
 550                         if (defq == -1) {
 551                                 defq = nm_rxq->iq_abs_id;
 552                                 break;
 553                         }
 554                 }
 555         }
 556
 557         if (defq == -1) {
 558                 /* No active netmap queues.  Switch back to NIC queues. */
 559                 rss = vi->rss;
 560                 defq = vi->rss[0];
 561         } else {
 562                 for (i = 0; i < vi->rss_size;) {
 563                         for_each_nm_rxq(vi, j, nm_rxq) {
 564                                 nm_state = atomic_load_int(&nm_rxq->nm_state);
 565                                 kring = na->rx_rings[nm_rxq->nid];
 566                                 if ((nm_state != NM_OFF &&
 567                                     !nm_kring_pending_off(kring)) ||
 568                                     (nm_state == NM_OFF &&
 569                                     nm_kring_pending_on(kring))) {
 570                                         MPASS(nm_rxq->iq_cntxt_id !=
 571                                             INVALID_NM_RXQ_CNTXT_ID);
 572                                         vi->nm_rss[i++] = nm_rxq->iq_abs_id;
 573                                         if (i == vi->rss_size)
 574                                                 break;
 575                                 }
 576                         }
 577                 }
 578                 rss = vi->nm_rss;
 579         }
 580
 581         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
 582             vi->rss_size);
 583         if (rc != 0)
 584                 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
 585
 586         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
 587         if (rc != 0) {
 588                 if_printf(ifp, "netmap defaultq config failed: %d\n", rc);
 589         }
 590
 591         return (rc);
 592 }
 593
 594 /*
 595  * Odd number of rx queues work best for split RSS mode as the first queue can
 596  * be dedicated for non-RSS traffic and the rest divided into two equal halves.
 597  */
 598 static int
 599 cxgbe_netmap_split_rss(struct adapter *sc, struct vi_info *vi,
 600     struct ifnet *ifp, struct netmap_adapter *na)
 601 {
 602         struct netmap_kring *kring;
 603         struct sge_nm_rxq *nm_rxq;
 604         int rc, i, j, nm_state, defq;
 605         int nactive[2] = {0, 0};
 606         int dq[2] = {-1, -1};
 607         bool dq_norss;          /* default queue should not be in RSS table. */
 608
 609         MPASS(nm_split_rss != 0);
 610         MPASS(vi->nnmrxq > 1);
 611
 612         for_each_nm_rxq(vi, i, nm_rxq) {
 613                 j = i / ((vi->nnmrxq + 1) / 2);
 614                 nm_state = atomic_load_int(&nm_rxq->nm_state);
 615                 kring = na->rx_rings[nm_rxq->nid];
 616                 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) ||
 617                     (nm_state == NM_OFF && nm_kring_pending_on(kring))) {
 618                         MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
 619                         nactive[j]++;
 620                         if (dq[j] == -1) {
 621                                 dq[j] = nm_rxq->iq_abs_id;
 622                                 break;
 623                         }
 624                 }
 625         }
 626
 627         if (nactive[0] == 0 || nactive[1] == 0)
 628                 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na));
 629
 630         MPASS(dq[0] != -1 && dq[1] != -1);
 631         if (nactive[0] > nactive[1]) {
 632                 defq = dq[0];
 633                 dq_norss = true;
 634         } else if (nactive[0] < nactive[1]) {
 635                 defq = dq[1];
 636                 dq_norss = true;
 637         } else {
 638                 defq = dq[0];
 639                 dq_norss = false;
 640         }
 641
 642         i = 0;
 643         nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq];
 644         while (i < vi->rss_size / 2) {
 645                 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) {
 646                         nm_state = atomic_load_int(&nm_rxq[j].nm_state);
 647                         kring = na->rx_rings[nm_rxq[j].nid];
 648                         if ((nm_state == NM_OFF &&
 649                             !nm_kring_pending_on(kring)) ||
 650                             (nm_state == NM_ON &&
 651                             nm_kring_pending_off(kring))) {
 652                                 continue;
 653                         }
 654                         MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
 655                         if (dq_norss && defq == nm_rxq[j].iq_abs_id)
 656                                 continue;
 657                         vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
 658                         if (i == vi->rss_size / 2)
 659                                 break;
 660                 }
 661         }
 662         while (i < vi->rss_size) {
 663                 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) {
 664                         nm_state = atomic_load_int(&nm_rxq[j].nm_state);
 665                         kring = na->rx_rings[nm_rxq[j].nid];
 666                         if ((nm_state == NM_OFF &&
 667                             !nm_kring_pending_on(kring)) ||
 668                             (nm_state == NM_ON &&
 669                             nm_kring_pending_off(kring))) {
 670                                 continue;
 671                         }
 672                         MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
 673                         if (dq_norss && defq == nm_rxq[j].iq_abs_id)
 674                                 continue;
 675                         vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
 676                         if (i == vi->rss_size)
 677                                 break;
 678                 }
 679         }
 680
 681         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
 682             vi->nm_rss, vi->rss_size);
 683         if (rc != 0)
 684                 if_printf(ifp, "netmap split_rss_config failed: %d\n", rc);
 685
 686         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
 687         if (rc != 0)
 688                 if_printf(ifp, "netmap defaultq config failed: %d\n", rc);
 689
 690         return (rc);
 691 }
 692
 693 static inline int
 694 cxgbe_netmap_rss(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
 695     struct netmap_adapter *na)
 696 {
 697
 698         if (nm_split_rss == 0 || vi->nnmrxq == 1)
 699                 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na));
 700         else
 701                 return (cxgbe_netmap_split_rss(sc, vi, ifp, na));
 702 }
 703
 704 static int
 705 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
 706     struct netmap_adapter *na)
 707 {
 708         struct netmap_slot *slot;
 709         struct netmap_kring *kring;
 710         struct sge_nm_rxq *nm_rxq;
 711         struct sge_nm_txq *nm_txq;
 712         int i, j, hwidx;
 713         struct rx_buf_info *rxb;
 714
 715         ASSERT_SYNCHRONIZED_OP(sc);
 716         MPASS(vi->nnmrxq > 0);
 717         MPASS(vi->nnmtxq > 0);
 718
 719         if ((vi->flags & VI_INIT_DONE) == 0 ||
 720             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
 721                 if_printf(ifp, "cannot enable netmap operation because "
 722                     "interface is not UP.\n");
 723                 return (EAGAIN);
 724         }
 725
 726         rxb = &sc->sge.rx_buf_info[0];
 727         for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
 728                 if (rxb->size1 == NETMAP_BUF_SIZE(na)) {
 729                         hwidx = rxb->hwidx1;
 730                         break;
 731                 }
 732                 if (rxb->size2 == NETMAP_BUF_SIZE(na)) {
 733                         hwidx = rxb->hwidx2;
 734                         break;
 735                 }
 736         }
 737         if (i >= SW_ZONE_SIZES) {
 738                 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
 739                     NETMAP_BUF_SIZE(na));
 740                 return (ENXIO);
 741         }
 742
 743         /* Must set caps before calling netmap_reset */
 744         nm_set_native_flags(na);
 745
 746         for_each_nm_rxq(vi, i, nm_rxq) {
 747                 kring = na->rx_rings[nm_rxq->nid];
 748                 if (!nm_kring_pending_on(kring))
 749                         continue;
 750
 751                 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
 752                 nm_rxq->fl_hwidx = hwidx;
 753                 slot = netmap_reset(na, NR_RX, i, 0);
 754                 MPASS(slot != NULL);    /* XXXNM: error check, not assert */
 755
 756                 /* We deal with 8 bufs at a time */
 757                 MPASS((na->num_rx_desc & 7) == 0);
 758                 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
 759                 for (j = 0; j < nm_rxq->fl_sidx; j++) {
 760                         uint64_t ba;
 761
 762                         PNMB(na, &slot[j], &ba);
 763                         MPASS(ba != 0);
 764                         nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
 765                 }
 766                 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
 767                 MPASS((j & 7) == 0);
 768                 j /= 8; /* driver pidx to hardware pidx */
 769                 wmb();
 770                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 771                     nm_rxq->fl_db_val | V_PIDX(j));
 772
 773                 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
 774         }
 775
 776         for_each_nm_txq(vi, i, nm_txq) {
 777                 kring = na->tx_rings[nm_txq->nid];
 778                 if (!nm_kring_pending_on(kring))
 779                         continue;
 780
 781                 alloc_nm_txq_hwq(vi, nm_txq);
 782                 slot = netmap_reset(na, NR_TX, i, 0);
 783                 MPASS(slot != NULL);    /* XXXNM: error check, not assert */
 784         }
 785
 786         if (vi->nm_rss == NULL) {
 787                 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
 788                     M_ZERO | M_WAITOK);
 789         }
 790
 791         return (cxgbe_netmap_rss(sc, vi, ifp, na));
 792 }
 793
 794 static int
 795 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
 796     struct netmap_adapter *na)
 797 {
 798         struct netmap_kring *kring;
 799         int rc, i, nm_state, nactive;
 800         struct sge_nm_txq *nm_txq;
 801         struct sge_nm_rxq *nm_rxq;
 802
 803         ASSERT_SYNCHRONIZED_OP(sc);
 804         MPASS(vi->nnmrxq > 0);
 805         MPASS(vi->nnmtxq > 0);
 806
 807         if (!nm_netmap_on(na))
 808                 return (0);
 809
 810         if ((vi->flags & VI_INIT_DONE) == 0)
 811                 return (0);
 812
 813         /* First remove the queues that are stopping from the RSS table. */
 814         rc = cxgbe_netmap_rss(sc, vi, ifp, na);
 815         if (rc != 0)
 816                 return (rc);    /* error message logged already. */
 817
 818         for_each_nm_txq(vi, i, nm_txq) {
 819                 kring = na->tx_rings[nm_txq->nid];
 820                 if (!nm_kring_pending_off(kring))
 821                         continue;
 822                 MPASS(nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID);
 823
 824                 rc = -t4_eth_eq_stop(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
 825                 if (rc != 0) {
 826                         device_printf(vi->dev,
 827                             "failed to stop nm_txq[%d]: %d.\n", i, rc);
 828                         return (rc);
 829                 }
 830
 831                 /* XXX: netmap, not the driver, should do this. */
 832                 kring->rhead = kring->rcur = kring->nr_hwcur = 0;
 833                 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1;
 834         }
 835         nactive = 0;
 836         for_each_nm_rxq(vi, i, nm_rxq) {
 837                 nm_state = atomic_load_int(&nm_rxq->nm_state);
 838                 kring = na->rx_rings[nm_rxq->nid];
 839                 if (nm_state != NM_OFF && !nm_kring_pending_off(kring))
 840                         nactive++;
 841                 if (!nm_kring_pending_off(kring))
 842                         continue;
 843                 MPASS(nm_state != NM_OFF);
 844                 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
 845
 846                 rc = -t4_iq_stop(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
 847                     nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
 848                 if (rc != 0) {
 849                         device_printf(vi->dev,
 850                             "failed to stop nm_rxq[%d]: %d.\n", i, rc);
 851                         return (rc);
 852                 }
 853
 854                 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
 855                         pause("nmst", 1);
 856
 857                 /* XXX: netmap, not the driver, should do this. */
 858                 kring->rhead = kring->rcur = kring->nr_hwcur = 0;
 859                 kring->rtail = kring->nr_hwtail = 0;
 860         }
 861         netmap_krings_mode_commit(na, 0);
 862         if (nactive == 0)
 863                 nm_clear_native_flags(na);
 864
 865         return (rc);
 866 }
 867
 868 static int
 869 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
 870 {
 871         struct ifnet *ifp = na->ifp;
 872         struct vi_info *vi = ifp->if_softc;
 873         struct adapter *sc = vi->adapter;
 874         int rc;
 875
 876         rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
 877         if (rc != 0)
 878                 return (rc);
 879         if (on)
 880                 rc = cxgbe_netmap_on(sc, vi, ifp, na);
 881         else
 882                 rc = cxgbe_netmap_off(sc, vi, ifp, na);
 883         end_synchronized_op(sc, 0);
 884
 885         return (rc);
 886 }
 887
 888 /* How many packets can a single type1 WR carry in n descriptors */
 889 static inline int
 890 ndesc_to_npkt(const int n)
 891 {
 892
 893         MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
 894
 895         return (n * 2 - 1);
 896 }
 897 #define MAX_NPKT_IN_TYPE1_WR    (ndesc_to_npkt(SGE_MAX_WR_NDESC))
 898
 899 /*
 900  * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
 901  * carries n packets
 902  */
 903 static inline int
 904 npkt_to_ndesc(const int n)
 905 {
 906
 907         MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
 908
 909         return ((n + 2) / 2);
 910 }
 911
 912 /*
 913  * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
 914  * carries n packets
 915  */
 916 static inline int
 917 npkt_to_len16(const int n)
 918 {
 919
 920         MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
 921
 922         return (n * 2 + 1);
 923 }
 924
 925 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
 926
 927 static void
 928 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
 929 {
 930         int n;
 931         u_int db = nm_txq->doorbells;
 932
 933         MPASS(nm_txq->pidx != nm_txq->dbidx);
 934
 935         n = NMIDXDIFF(nm_txq, dbidx);
 936         if (n > 1)
 937                 clrbit(&db, DOORBELL_WCWR);
 938         wmb();
 939
 940         switch (ffs(db) - 1) {
 941         case DOORBELL_UDB:
 942                 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
 943                 break;
 944
 945         case DOORBELL_WCWR: {
 946                 volatile uint64_t *dst, *src;
 947
 948                 /*
 949                  * Queues whose 128B doorbell segment fits in the page do not
 950                  * use relative qid (udb_qid is always 0).  Only queues with
 951                  * doorbell segments can do WCWR.
 952                  */
 953                 KASSERT(nm_txq->udb_qid == 0 && n == 1,
 954                     ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
 955                     __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
 956
 957                 dst = (volatile void *)((uintptr_t)nm_txq->udb +
 958                     UDBS_WR_OFFSET - UDBS_DB_OFFSET);
 959                 src = (void *)&nm_txq->desc[nm_txq->dbidx];
 960                 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
 961                         *dst++ = *src++;
 962                 wmb();
 963                 break;
 964         }
 965
 966         case DOORBELL_UDBWC:
 967                 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
 968                 wmb();
 969                 break;
 970
 971         case DOORBELL_KDB:
 972                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 973                     V_QID(nm_txq->cntxt_id) | V_PIDX(n));
 974                 break;
 975         }
 976         nm_txq->dbidx = nm_txq->pidx;
 977 }
 978
 979 /*
 980  * Write work requests to send 'npkt' frames and ring the doorbell to send them
 981  * on their way.  No need to check for wraparound.
 982  */
 983 static void
 984 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
 985     struct netmap_kring *kring, int npkt, int npkt_remaining)
 986 {
 987         struct netmap_ring *ring = kring->ring;
 988         struct netmap_slot *slot;
 989         const u_int lim = kring->nkr_num_slots - 1;
 990         struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
 991         uint16_t len;
 992         uint64_t ba;
 993         struct cpl_tx_pkt_core *cpl;
 994         struct ulptx_sgl *usgl;
 995         int i, n;
 996
 997         while (npkt) {
 998                 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
 999                 len = 0;
1000
1001                 wr = (void *)&nm_txq->desc[nm_txq->pidx];
1002                 wr->op_pkd = nm_txq->op_pkd;
1003                 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
1004                 wr->npkt = n;
1005                 wr->r3 = 0;
1006                 wr->type = 1;
1007                 cpl = (void *)(wr + 1);
1008
1009                 for (i = 0; i < n; i++) {
1010                         slot = &ring->slot[kring->nr_hwcur];
1011                         PNMB(kring->na, slot, &ba);
1012                         MPASS(ba != 0);
1013
1014                         cpl->ctrl0 = nm_txq->cpl_ctrl0;
1015                         cpl->pack = 0;
1016                         cpl->len = htobe16(slot->len);
1017                         cpl->ctrl1 = nm_txcsum ? 0 :
1018                             htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
1019
1020                         usgl = (void *)(cpl + 1);
1021                         usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
1022                             V_ULPTX_NSGE(1));
1023                         usgl->len0 = htobe32(slot->len);
1024                         usgl->addr0 = htobe64(ba);
1025
1026                         slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1027                         cpl = (void *)(usgl + 1);
1028                         MPASS(slot->len + len <= UINT16_MAX);
1029                         len += slot->len;
1030                         kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
1031                 }
1032                 wr->plen = htobe16(len);
1033
1034                 npkt -= n;
1035                 nm_txq->pidx += npkt_to_ndesc(n);
1036                 MPASS(nm_txq->pidx <= nm_txq->sidx);
1037                 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
1038                         /*
1039                          * This routine doesn't know how to write WRs that wrap
1040                          * around.  Make sure it wasn't asked to.
1041                          */
1042                         MPASS(npkt == 0);
1043                         nm_txq->pidx = 0;
1044                 }
1045
1046                 if (npkt == 0 && npkt_remaining == 0) {
1047                         /* All done. */
1048                         if (lazy_tx_credit_flush == 0) {
1049                                 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
1050                                     F_FW_WR_EQUIQ);
1051                                 nm_txq->equeqidx = nm_txq->pidx;
1052                                 nm_txq->equiqidx = nm_txq->pidx;
1053                         }
1054                         ring_nm_txq_db(sc, nm_txq);
1055                         return;
1056                 }
1057
1058                 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
1059                         wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
1060                             F_FW_WR_EQUIQ);
1061                         nm_txq->equeqidx = nm_txq->pidx;
1062                         nm_txq->equiqidx = nm_txq->pidx;
1063                 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
1064                         wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1065                         nm_txq->equeqidx = nm_txq->pidx;
1066                 }
1067                 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
1068                         ring_nm_txq_db(sc, nm_txq);
1069         }
1070
1071         /* Will get called again. */
1072         MPASS(npkt_remaining);
1073 }
1074
1075 /* How many contiguous free descriptors starting at pidx */
1076 static inline int
1077 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
1078 {
1079
1080         if (nm_txq->cidx > nm_txq->pidx)
1081                 return (nm_txq->cidx - nm_txq->pidx - 1);
1082         else if (nm_txq->cidx > 0)
1083                 return (nm_txq->sidx - nm_txq->pidx);
1084         else
1085                 return (nm_txq->sidx - nm_txq->pidx - 1);
1086 }
1087
1088 static int
1089 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
1090 {
1091         struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
1092         uint16_t hw_cidx = spg->cidx;   /* snapshot */
1093         struct fw_eth_tx_pkts_wr *wr;
1094         int n = 0;
1095
1096         hw_cidx = be16toh(hw_cidx);
1097
1098         while (nm_txq->cidx != hw_cidx) {
1099                 wr = (void *)&nm_txq->desc[nm_txq->cidx];
1100
1101                 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) ||
1102                     wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)));
1103                 MPASS(wr->type == 1);
1104                 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
1105
1106                 n += wr->npkt;
1107                 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
1108
1109                 /*
1110                  * We never sent a WR that wrapped around so the credits coming
1111                  * back, WR by WR, should never cause the cidx to wrap around
1112                  * either.
1113                  */
1114                 MPASS(nm_txq->cidx <= nm_txq->sidx);
1115                 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
1116                         nm_txq->cidx = 0;
1117         }
1118
1119         return (n);
1120 }
1121
1122 static int
1123 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
1124 {
1125         struct netmap_adapter *na = kring->na;
1126         struct ifnet *ifp = na->ifp;
1127         struct vi_info *vi = ifp->if_softc;
1128         struct adapter *sc = vi->adapter;
1129         struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
1130         const u_int head = kring->rhead;
1131         u_int reclaimed = 0;
1132         int n, d, npkt_remaining, ndesc_remaining;
1133
1134         /*
1135          * Tx was at kring->nr_hwcur last time around and now we need to advance
1136          * to kring->rhead.  Note that the driver's pidx moves independent of
1137          * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
1138          * between descriptors and frames isn't 1:1).
1139          */
1140
1141         npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
1142             kring->nkr_num_slots - kring->nr_hwcur + head;
1143         while (npkt_remaining) {
1144                 reclaimed += reclaim_nm_tx_desc(nm_txq);
1145                 ndesc_remaining = contiguous_ndesc_available(nm_txq);
1146                 /* Can't run out of descriptors with packets still remaining */
1147                 MPASS(ndesc_remaining > 0);
1148
1149                 /* # of desc needed to tx all remaining packets */
1150                 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
1151                 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
1152                         d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
1153
1154                 if (d <= ndesc_remaining)
1155                         n = npkt_remaining;
1156                 else {
1157                         /* Can't send all, calculate how many can be sent */
1158                         n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
1159                             MAX_NPKT_IN_TYPE1_WR;
1160                         if (ndesc_remaining % SGE_MAX_WR_NDESC)
1161                                 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
1162                 }
1163
1164                 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
1165                 npkt_remaining -= n;
1166                 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining);
1167         }
1168         MPASS(npkt_remaining == 0);
1169         MPASS(kring->nr_hwcur == head);
1170         MPASS(nm_txq->dbidx == nm_txq->pidx);
1171
1172         /*
1173          * Second part: reclaim buffers for completed transmissions.
1174          */
1175         if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
1176                 reclaimed += reclaim_nm_tx_desc(nm_txq);
1177                 kring->nr_hwtail += reclaimed;
1178                 if (kring->nr_hwtail >= kring->nkr_num_slots)
1179                         kring->nr_hwtail -= kring->nkr_num_slots;
1180         }
1181
1182         return (0);
1183 }
1184
1185 static int
1186 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
1187 {
1188         struct netmap_adapter *na = kring->na;
1189         struct netmap_ring *ring = kring->ring;
1190         struct ifnet *ifp = na->ifp;
1191         struct vi_info *vi = ifp->if_softc;
1192         struct adapter *sc = vi->adapter;
1193         struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
1194         u_int const head = kring->rhead;
1195         u_int n;
1196         int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1197
1198         if (black_hole)
1199                 return (0);     /* No updates ever. */
1200
1201         if (netmap_no_pendintr || force_update) {
1202                 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
1203                 kring->nr_kflags &= ~NKR_PENDINTR;
1204         }
1205
1206         if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
1207                 wmb();
1208                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1209                     nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
1210                 nm_rxq->fl_db_saved = 0;
1211         }
1212
1213         /* Userspace done with buffers from kring->nr_hwcur to head */
1214         n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
1215             kring->nkr_num_slots - kring->nr_hwcur + head;
1216         n &= ~7U;
1217         if (n > 0) {
1218                 u_int fl_pidx = nm_rxq->fl_pidx;
1219                 struct netmap_slot *slot = &ring->slot[fl_pidx];
1220                 uint64_t ba;
1221                 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
1222
1223                 /*
1224                  * We always deal with 8 buffers at a time.  We must have
1225                  * stopped at an 8B boundary (fl_pidx) last time around and we
1226                  * must have a multiple of 8B buffers to give to the freelist.
1227                  */
1228                 MPASS((fl_pidx & 7) == 0);
1229                 MPASS((n & 7) == 0);
1230
1231                 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
1232                 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2);
1233
1234                 while (n > 0) {
1235                         for (i = 0; i < 8; i++, fl_pidx++, slot++) {
1236                                 PNMB(na, slot, &ba);
1237                                 MPASS(ba != 0);
1238                                 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
1239                                 slot->flags &= ~NS_BUF_CHANGED;
1240                                 MPASS(fl_pidx <= nm_rxq->fl_sidx2);
1241                         }
1242                         n -= 8;
1243                         if (fl_pidx == nm_rxq->fl_sidx2) {
1244                                 fl_pidx = 0;
1245                                 slot = &ring->slot[0];
1246                         }
1247                         if (++dbinc == nm_rxq->fl_db_threshold) {
1248                                 wmb();
1249                                 if (starve_fl)
1250                                         nm_rxq->fl_db_saved += dbinc;
1251                                 else {
1252                                         t4_write_reg(sc, sc->sge_kdoorbell_reg,
1253                                             nm_rxq->fl_db_val | V_PIDX(dbinc));
1254                                 }
1255                                 dbinc = 0;
1256                         }
1257                 }
1258                 MPASS(nm_rxq->fl_pidx == fl_pidx);
1259
1260                 if (dbinc > 0) {
1261                         wmb();
1262                         if (starve_fl)
1263                                 nm_rxq->fl_db_saved += dbinc;
1264                         else {
1265                                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1266                                     nm_rxq->fl_db_val | V_PIDX(dbinc));
1267                         }
1268                 }
1269         }
1270
1271         return (0);
1272 }
1273
1274 void
1275 cxgbe_nm_attach(struct vi_info *vi)
1276 {
1277         struct port_info *pi;
1278         struct adapter *sc;
1279         struct netmap_adapter na;
1280
1281         MPASS(vi->nnmrxq > 0);
1282         MPASS(vi->ifp != NULL);
1283
1284         pi = vi->pi;
1285         sc = pi->adapter;
1286
1287         bzero(&na, sizeof(na));
1288
1289         na.ifp = vi->ifp;
1290         na.na_flags = NAF_BDG_MAYSLEEP;
1291
1292         /* Netmap doesn't know about the space reserved for the status page. */
1293         na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
1294
1295         /*
1296          * The freelist's cidx/pidx drives netmap's rx cidx/pidx.  So
1297          * num_rx_desc is based on the number of buffers that can be held in the
1298          * freelist, and not the number of entries in the iq.  (These two are
1299          * not exactly the same due to the space taken up by the status page).
1300          */
1301         na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
1302         na.nm_txsync = cxgbe_netmap_txsync;
1303         na.nm_rxsync = cxgbe_netmap_rxsync;
1304         na.nm_register = cxgbe_netmap_reg;
1305         na.num_tx_rings = vi->nnmtxq;
1306         na.num_rx_rings = vi->nnmrxq;
1307         na.rx_buf_maxsize = MAX_MTU;
1308         netmap_attach(&na);     /* This adds IFCAP_NETMAP to if_capabilities */
1309 }
1310
1311 void
1312 cxgbe_nm_detach(struct vi_info *vi)
1313 {
1314
1315         MPASS(vi->nnmrxq > 0);
1316         MPASS(vi->ifp != NULL);
1317
1318         netmap_detach(vi->ifp);
1319 }
1320
1321 static inline const void *
1322 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
1323 {
1324
1325         MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
1326
1327         /* data[0] is RSS header */
1328         return (&cpl->data[1]);
1329 }
1330
1331 static void
1332 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
1333     const struct cpl_sge_egr_update *egr)
1334 {
1335         uint32_t oq;
1336         struct sge_nm_txq *nm_txq;
1337
1338         oq = be32toh(egr->opcode_qid);
1339         MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1340         nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1341
1342         netmap_tx_irq(ifp, nm_txq->nid);
1343 }
1344
1345 void
1346 service_nm_rxq(struct sge_nm_rxq *nm_rxq)
1347 {
1348         struct vi_info *vi = nm_rxq->vi;
1349         struct adapter *sc = vi->adapter;
1350         struct ifnet *ifp = vi->ifp;
1351         struct netmap_adapter *na = NA(ifp);
1352         struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
1353         struct netmap_ring *ring = kring->ring;
1354         struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1355         const void *cpl;
1356         uint32_t lq;
1357         u_int work = 0;
1358         uint8_t opcode;
1359         uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1360         u_int fl_credits = fl_cidx & 7;
1361         u_int ndesc = 0;        /* desc processed since last cidx update */
1362         u_int nframes = 0;      /* frames processed since last netmap wakeup */
1363
1364         while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1365
1366                 rmb();
1367
1368                 lq = be32toh(d->rsp.pldbuflen_qid);
1369                 opcode = d->rss.opcode;
1370                 cpl = &d->cpl[0];
1371
1372                 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1373                 case X_RSPD_TYPE_FLBUF:
1374
1375                         /* fall through */
1376
1377                 case X_RSPD_TYPE_CPL:
1378                         MPASS(opcode < NUM_CPL_CMDS);
1379
1380                         switch (opcode) {
1381                         case CPL_FW4_MSG:
1382                         case CPL_FW6_MSG:
1383                                 cpl = unwrap_nm_fw6_msg(cpl);
1384                                 /* fall through */
1385                         case CPL_SGE_EGR_UPDATE:
1386                                 handle_nm_sge_egr_update(sc, ifp, cpl);
1387                                 break;
1388                         case CPL_RX_PKT:
1389                                 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1390                                     sc->params.sge.fl_pktshift;
1391                                 ring->slot[fl_cidx].flags = 0;
1392                                 nframes++;
1393                                 if (!(lq & F_RSPD_NEWBUF)) {
1394                                         MPASS(black_hole == 2);
1395                                         break;
1396                                 }
1397                                 fl_credits++;
1398                                 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1399                                         fl_cidx = 0;
1400                                 break;
1401                         default:
1402                                 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1403                                     __func__, opcode, nm_rxq);
1404                         }
1405                         break;
1406
1407                 case X_RSPD_TYPE_INTR:
1408                         /* Not equipped to handle forwarded interrupts. */
1409                         panic("%s: netmap queue received interrupt for iq %u\n",
1410                             __func__, lq);
1411
1412                 default:
1413                         panic("%s: illegal response type %d on nm_rxq %p",
1414                             __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1415                 }
1416
1417                 d++;
1418                 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1419                         nm_rxq->iq_cidx = 0;
1420                         d = &nm_rxq->iq_desc[0];
1421                         nm_rxq->iq_gen ^= F_RSPD_GEN;
1422                 }
1423
1424                 if (__predict_false(++nframes == rx_nframes) && !black_hole) {
1425                         atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1426                         netmap_rx_irq(ifp, nm_rxq->nid, &work);
1427                         nframes = 0;
1428                 }
1429
1430                 if (__predict_false(++ndesc == rx_ndesc)) {
1431                         if (black_hole && fl_credits >= 8) {
1432                                 fl_credits /= 8;
1433                                 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1434                                     nm_rxq->fl_sidx);
1435                                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1436                                     nm_rxq->fl_db_val | V_PIDX(fl_credits));
1437                                 fl_credits = fl_cidx & 7;
1438                         }
1439                         t4_write_reg(sc, sc->sge_gts_reg,
1440                             V_CIDXINC(ndesc) |
1441                             V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1442                             V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1443                         ndesc = 0;
1444                 }
1445         }
1446
1447         atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1448         if (black_hole) {
1449                 fl_credits /= 8;
1450                 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1451                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1452                     nm_rxq->fl_db_val | V_PIDX(fl_credits));
1453         } else if (nframes > 0)
1454                 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1455
1456         t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1457             V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1458             V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
1459 }
1460 #endif