2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
37 #include <sys/eventhandler.h>
40 #include <sys/module.h>
41 #include <sys/selinfo.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <machine/bus.h>
45 #include <net/ethernet.h>
47 #include <net/if_media.h>
48 #include <net/if_var.h>
49 #include <net/if_clone.h>
50 #include <net/if_types.h>
51 #include <net/netmap.h>
52 #include <dev/netmap/netmap_kern.h>
54 #include "common/common.h"
55 #include "common/t4_regs.h"
56 #include "common/t4_regs_values.h"
58 extern int fl_pad; /* XXXNM */
61 * 0 = normal netmap rx
63 * 2 = supermassive black hole (buffer packing enabled)
66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0,
67 "Sink incoming packets.");
70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN,
75 &rx_nframes, 0, "max # of frames received before waking up netmap rx.");
77 int holdoff_tmr_idx = 2;
78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
83 * -1: no congestion feedback (not recommended).
84 * 0: backpressure the channel instead of dropping packets right away.
85 * 1: no backpressure, drop packets for the congested queue immediately.
87 static int nm_cong_drop = 1;
88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN,
90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop");
93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN,
94 &starve_fl, 0, "Don't ring fl db for netmap rx queues.");
97 * Try to process tx credits in bulk. This may cause a delay in the return of
98 * tx credits and is suitable for bursty or non-stop tx only.
100 int lazy_tx_credit_flush = 1;
101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN,
102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues.");
105 * Split the netmap rx queues into two groups that populate separate halves of
106 * the RSS indirection table. This allows filters with hashmask to steer to a
107 * particular group of queues.
109 static int nm_split_rss = 0;
110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN,
111 &nm_split_rss, 0, "Split the netmap rx queues into two groups.");
114 * netmap(4) says "netmap does not use features such as checksum offloading, TCP
115 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc."
116 * but this knob can be used to get the hardware to checksum all tx traffic
119 static int nm_txcsum = 0;
120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN,
121 &nm_txcsum, 0, "Enable transmit checksum offloading.");
124 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
128 struct adapter *sc = vi->pi->adapter;
129 struct sge_params *sp = &sc->params.sge;
130 struct netmap_adapter *na = NA(vi->ifp);
134 MPASS(nm_rxq->iq_desc != NULL);
135 MPASS(nm_rxq->fl_desc != NULL);
137 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
138 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
140 bzero(&c, sizeof(c));
141 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
142 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
144 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
146 MPASS(!forwarding_intr_to_fwq(sc));
147 KASSERT(nm_rxq->intr_idx < sc->intr_count,
148 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
149 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
150 c.type_to_iqandstindex = htobe32(v |
151 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
152 V_FW_IQ_CMD_VIID(vi->viid) |
153 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
154 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
155 F_FW_IQ_CMD_IQGTSMODE |
156 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
157 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
158 c.iqsize = htobe16(vi->qsize_rxq);
159 c.iqaddr = htobe64(nm_rxq->iq_ba);
161 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
162 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
163 F_FW_IQ_CMD_FL0CONGEN);
165 c.iqns_to_fl0congen |=
166 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
167 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
168 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
169 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
170 c.fl0dcaen_to_fl0cidxfthresh =
171 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
172 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
173 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
174 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
175 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
176 c.fl0addr = htobe64(nm_rxq->fl_ba);
178 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
180 device_printf(sc->dev,
181 "failed to create netmap ingress queue: %d\n", rc);
186 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
187 nm_rxq->iq_gen = F_RSPD_GEN;
188 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
189 nm_rxq->iq_abs_id = be16toh(c.physiqid);
190 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
191 if (cntxt_id >= sc->sge.niq) {
192 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
193 __func__, cntxt_id, sc->sge.niq - 1);
195 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
197 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
198 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
199 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
200 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
201 if (cntxt_id >= sc->sge.neq) {
202 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
203 __func__, cntxt_id, sc->sge.neq - 1);
205 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
207 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
208 sc->chip_params->sge_fl_db;
210 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
213 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
214 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
215 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
216 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
217 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
218 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
223 for (i = 0; i < 4; i++) {
225 val |= 1 << (i << 2);
229 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
231 /* report error but carry on */
232 device_printf(sc->dev,
233 "failed to set congestion manager context for "
234 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
238 t4_write_reg(sc, sc->sge_gts_reg,
239 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
240 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
246 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
248 struct adapter *sc = vi->pi->adapter;
251 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
252 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
254 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
255 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
256 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
261 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
265 struct adapter *sc = vi->pi->adapter;
266 struct netmap_adapter *na = NA(vi->ifp);
267 struct fw_eq_eth_cmd c;
270 MPASS(nm_txq->desc != NULL);
272 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
273 bzero(nm_txq->desc, len);
275 bzero(&c, sizeof(c));
276 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
277 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
278 V_FW_EQ_ETH_CMD_VFN(0));
279 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
280 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
281 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
282 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
284 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
285 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
286 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
288 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
289 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
290 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
291 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
292 c.eqaddr = htobe64(nm_txq->ba);
294 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
296 device_printf(vi->dev,
297 "failed to create netmap egress queue: %d\n", rc);
301 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
302 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
303 if (cntxt_id >= sc->sge.neq)
304 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
305 cntxt_id, sc->sge.neq - 1);
306 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
308 nm_txq->pidx = nm_txq->cidx = 0;
309 MPASS(nm_txq->sidx == na->num_tx_desc);
310 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
312 nm_txq->doorbells = sc->doorbells;
313 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
314 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
315 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
316 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
317 uint32_t mask = (1 << s_qpp) - 1;
318 volatile uint8_t *udb;
320 udb = sc->udbs_base + UDBS_DB_OFFSET;
321 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
322 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
323 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
324 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
326 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
329 nm_txq->udb = (volatile void *)udb;
336 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
338 struct adapter *sc = vi->pi->adapter;
341 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
343 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
344 nm_txq->cntxt_id, rc);
345 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
350 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
351 struct netmap_adapter *na)
353 struct netmap_slot *slot;
354 struct netmap_kring *kring;
355 struct sge_nm_rxq *nm_rxq;
356 struct sge_nm_txq *nm_txq;
357 int rc, i, j, hwidx, defq, nrssq;
358 struct rx_buf_info *rxb;
360 ASSERT_SYNCHRONIZED_OP(sc);
362 if ((vi->flags & VI_INIT_DONE) == 0 ||
363 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
366 rxb = &sc->sge.rx_buf_info[0];
367 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
368 if (rxb->size1 == NETMAP_BUF_SIZE(na)) {
372 if (rxb->size2 == NETMAP_BUF_SIZE(na)) {
377 if (i >= SW_ZONE_SIZES) {
378 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
379 NETMAP_BUF_SIZE(na));
383 /* Must set caps before calling netmap_reset */
384 nm_set_native_flags(na);
386 for_each_nm_rxq(vi, i, nm_rxq) {
387 kring = na->rx_rings[nm_rxq->nid];
388 if (!nm_kring_pending_on(kring) ||
389 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
392 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
393 nm_rxq->fl_hwidx = hwidx;
394 slot = netmap_reset(na, NR_RX, i, 0);
395 MPASS(slot != NULL); /* XXXNM: error check, not assert */
397 /* We deal with 8 bufs at a time */
398 MPASS((na->num_rx_desc & 7) == 0);
399 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
400 for (j = 0; j < nm_rxq->fl_sidx; j++) {
403 PNMB(na, &slot[j], &ba);
405 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
407 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
409 j /= 8; /* driver pidx to hardware pidx */
411 t4_write_reg(sc, sc->sge_kdoorbell_reg,
412 nm_rxq->fl_db_val | V_PIDX(j));
414 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
417 for_each_nm_txq(vi, i, nm_txq) {
418 kring = na->tx_rings[nm_txq->nid];
419 if (!nm_kring_pending_on(kring) ||
420 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
423 alloc_nm_txq_hwq(vi, nm_txq);
424 slot = netmap_reset(na, NR_TX, i, 0);
425 MPASS(slot != NULL); /* XXXNM: error check, not assert */
428 if (vi->nm_rss == NULL) {
429 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
433 MPASS(vi->nnmrxq > 0);
434 if (nm_split_rss == 0 || vi->nnmrxq == 1) {
435 for (i = 0; i < vi->rss_size;) {
436 for_each_nm_rxq(vi, j, nm_rxq) {
437 vi->nm_rss[i++] = nm_rxq->iq_abs_id;
438 if (i == vi->rss_size)
442 defq = vi->nm_rss[0];
444 /* We have multiple queues and we want to split the table. */
445 MPASS(nm_split_rss != 0);
446 MPASS(vi->nnmrxq > 1);
448 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq];
450 if (vi->nnmrxq & 1) {
452 * Odd number of queues. The first rxq is designated the
453 * default queue, the rest are split evenly.
455 defq = nm_rxq->iq_abs_id;
460 * Even number of queues split into two halves. The
461 * first rxq in one of the halves is designated the
465 /* First rxq in the first half. */
466 defq = nm_rxq->iq_abs_id;
468 /* First rxq in the second half. */
469 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id;
474 while (i < vi->rss_size / 2) {
475 for (j = 0; j < nrssq / 2; j++) {
476 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
477 if (i == vi->rss_size / 2)
481 while (i < vi->rss_size) {
482 for (j = nrssq / 2; j < nrssq; j++) {
483 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
484 if (i == vi->rss_size)
489 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
490 vi->nm_rss, vi->rss_size);
492 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
494 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
496 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc);
502 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
503 struct netmap_adapter *na)
505 struct netmap_kring *kring;
507 struct sge_nm_txq *nm_txq;
508 struct sge_nm_rxq *nm_rxq;
510 ASSERT_SYNCHRONIZED_OP(sc);
512 if (!nm_netmap_on(na))
515 if ((vi->flags & VI_INIT_DONE) == 0)
518 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
519 vi->rss, vi->rss_size);
521 if_printf(ifp, "failed to restore RSS config: %d\n", rc);
522 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0);
524 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc);
525 nm_clear_native_flags(na);
527 for_each_nm_txq(vi, i, nm_txq) {
528 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
530 kring = na->tx_rings[nm_txq->nid];
531 if (!nm_kring_pending_off(kring) ||
532 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
535 /* Wait for hw pidx to catch up ... */
536 while (be16toh(nm_txq->pidx) != spg->pidx)
539 /* ... and then for the cidx. */
540 while (spg->pidx != spg->cidx)
543 free_nm_txq_hwq(vi, nm_txq);
545 for_each_nm_rxq(vi, i, nm_rxq) {
546 kring = na->rx_rings[nm_rxq->nid];
547 if (!nm_kring_pending_off(kring) ||
548 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
551 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
554 free_nm_rxq_hwq(vi, nm_rxq);
561 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
563 struct ifnet *ifp = na->ifp;
564 struct vi_info *vi = ifp->if_softc;
565 struct adapter *sc = vi->pi->adapter;
568 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
572 rc = cxgbe_netmap_on(sc, vi, ifp, na);
574 rc = cxgbe_netmap_off(sc, vi, ifp, na);
575 end_synchronized_op(sc, 0);
580 /* How many packets can a single type1 WR carry in n descriptors */
582 ndesc_to_npkt(const int n)
585 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
589 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
592 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
596 npkt_to_ndesc(const int n)
599 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
601 return ((n + 2) / 2);
605 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
609 npkt_to_len16(const int n)
612 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
617 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
620 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
623 u_int db = nm_txq->doorbells;
625 MPASS(nm_txq->pidx != nm_txq->dbidx);
627 n = NMIDXDIFF(nm_txq, dbidx);
629 clrbit(&db, DOORBELL_WCWR);
632 switch (ffs(db) - 1) {
634 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
637 case DOORBELL_WCWR: {
638 volatile uint64_t *dst, *src;
641 * Queues whose 128B doorbell segment fits in the page do not
642 * use relative qid (udb_qid is always 0). Only queues with
643 * doorbell segments can do WCWR.
645 KASSERT(nm_txq->udb_qid == 0 && n == 1,
646 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
647 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
649 dst = (volatile void *)((uintptr_t)nm_txq->udb +
650 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
651 src = (void *)&nm_txq->desc[nm_txq->dbidx];
652 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
659 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
664 t4_write_reg(sc, sc->sge_kdoorbell_reg,
665 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
668 nm_txq->dbidx = nm_txq->pidx;
672 * Write work requests to send 'npkt' frames and ring the doorbell to send them
673 * on their way. No need to check for wraparound.
676 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
677 struct netmap_kring *kring, int npkt, int npkt_remaining)
679 struct netmap_ring *ring = kring->ring;
680 struct netmap_slot *slot;
681 const u_int lim = kring->nkr_num_slots - 1;
682 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
685 struct cpl_tx_pkt_core *cpl;
686 struct ulptx_sgl *usgl;
690 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
693 wr = (void *)&nm_txq->desc[nm_txq->pidx];
694 wr->op_pkd = nm_txq->op_pkd;
695 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
699 cpl = (void *)(wr + 1);
701 for (i = 0; i < n; i++) {
702 slot = &ring->slot[kring->nr_hwcur];
703 PNMB(kring->na, slot, &ba);
706 cpl->ctrl0 = nm_txq->cpl_ctrl0;
708 cpl->len = htobe16(slot->len);
709 cpl->ctrl1 = nm_txcsum ? 0 :
710 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
712 usgl = (void *)(cpl + 1);
713 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
715 usgl->len0 = htobe32(slot->len);
716 usgl->addr0 = htobe64(ba);
718 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
719 cpl = (void *)(usgl + 1);
720 MPASS(slot->len + len <= UINT16_MAX);
722 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
724 wr->plen = htobe16(len);
727 nm_txq->pidx += npkt_to_ndesc(n);
728 MPASS(nm_txq->pidx <= nm_txq->sidx);
729 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
731 * This routine doesn't know how to write WRs that wrap
732 * around. Make sure it wasn't asked to.
738 if (npkt == 0 && npkt_remaining == 0) {
740 if (lazy_tx_credit_flush == 0) {
741 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
743 nm_txq->equeqidx = nm_txq->pidx;
744 nm_txq->equiqidx = nm_txq->pidx;
746 ring_nm_txq_db(sc, nm_txq);
750 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
751 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
753 nm_txq->equeqidx = nm_txq->pidx;
754 nm_txq->equiqidx = nm_txq->pidx;
755 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
756 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
757 nm_txq->equeqidx = nm_txq->pidx;
759 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
760 ring_nm_txq_db(sc, nm_txq);
763 /* Will get called again. */
764 MPASS(npkt_remaining);
767 /* How many contiguous free descriptors starting at pidx */
769 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
772 if (nm_txq->cidx > nm_txq->pidx)
773 return (nm_txq->cidx - nm_txq->pidx - 1);
774 else if (nm_txq->cidx > 0)
775 return (nm_txq->sidx - nm_txq->pidx);
777 return (nm_txq->sidx - nm_txq->pidx - 1);
781 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
783 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
784 uint16_t hw_cidx = spg->cidx; /* snapshot */
785 struct fw_eth_tx_pkts_wr *wr;
788 hw_cidx = be16toh(hw_cidx);
790 while (nm_txq->cidx != hw_cidx) {
791 wr = (void *)&nm_txq->desc[nm_txq->cidx];
793 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) ||
794 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)));
795 MPASS(wr->type == 1);
796 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
799 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
802 * We never sent a WR that wrapped around so the credits coming
803 * back, WR by WR, should never cause the cidx to wrap around
806 MPASS(nm_txq->cidx <= nm_txq->sidx);
807 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
815 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
817 struct netmap_adapter *na = kring->na;
818 struct ifnet *ifp = na->ifp;
819 struct vi_info *vi = ifp->if_softc;
820 struct adapter *sc = vi->pi->adapter;
821 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
822 const u_int head = kring->rhead;
824 int n, d, npkt_remaining, ndesc_remaining;
827 * Tx was at kring->nr_hwcur last time around and now we need to advance
828 * to kring->rhead. Note that the driver's pidx moves independent of
829 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
830 * between descriptors and frames isn't 1:1).
833 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
834 kring->nkr_num_slots - kring->nr_hwcur + head;
835 while (npkt_remaining) {
836 reclaimed += reclaim_nm_tx_desc(nm_txq);
837 ndesc_remaining = contiguous_ndesc_available(nm_txq);
838 /* Can't run out of descriptors with packets still remaining */
839 MPASS(ndesc_remaining > 0);
841 /* # of desc needed to tx all remaining packets */
842 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
843 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
844 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
846 if (d <= ndesc_remaining)
849 /* Can't send all, calculate how many can be sent */
850 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
851 MAX_NPKT_IN_TYPE1_WR;
852 if (ndesc_remaining % SGE_MAX_WR_NDESC)
853 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
856 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
858 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining);
860 MPASS(npkt_remaining == 0);
861 MPASS(kring->nr_hwcur == head);
862 MPASS(nm_txq->dbidx == nm_txq->pidx);
865 * Second part: reclaim buffers for completed transmissions.
867 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
868 reclaimed += reclaim_nm_tx_desc(nm_txq);
869 kring->nr_hwtail += reclaimed;
870 if (kring->nr_hwtail >= kring->nkr_num_slots)
871 kring->nr_hwtail -= kring->nkr_num_slots;
878 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
880 struct netmap_adapter *na = kring->na;
881 struct netmap_ring *ring = kring->ring;
882 struct ifnet *ifp = na->ifp;
883 struct vi_info *vi = ifp->if_softc;
884 struct adapter *sc = vi->pi->adapter;
885 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
886 u_int const head = kring->rhead;
888 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
891 return (0); /* No updates ever. */
893 if (netmap_no_pendintr || force_update) {
894 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
895 kring->nr_kflags &= ~NKR_PENDINTR;
898 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
900 t4_write_reg(sc, sc->sge_kdoorbell_reg,
901 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
902 nm_rxq->fl_db_saved = 0;
905 /* Userspace done with buffers from kring->nr_hwcur to head */
906 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
907 kring->nkr_num_slots - kring->nr_hwcur + head;
910 u_int fl_pidx = nm_rxq->fl_pidx;
911 struct netmap_slot *slot = &ring->slot[fl_pidx];
913 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
916 * We always deal with 8 buffers at a time. We must have
917 * stopped at an 8B boundary (fl_pidx) last time around and we
918 * must have a multiple of 8B buffers to give to the freelist.
920 MPASS((fl_pidx & 7) == 0);
923 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
924 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2);
927 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
930 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
931 slot->flags &= ~NS_BUF_CHANGED;
932 MPASS(fl_pidx <= nm_rxq->fl_sidx2);
935 if (fl_pidx == nm_rxq->fl_sidx2) {
937 slot = &ring->slot[0];
939 if (++dbinc == 8 && n >= 32) {
942 nm_rxq->fl_db_saved += dbinc;
944 t4_write_reg(sc, sc->sge_kdoorbell_reg,
945 nm_rxq->fl_db_val | V_PIDX(dbinc));
950 MPASS(nm_rxq->fl_pidx == fl_pidx);
955 nm_rxq->fl_db_saved += dbinc;
957 t4_write_reg(sc, sc->sge_kdoorbell_reg,
958 nm_rxq->fl_db_val | V_PIDX(dbinc));
967 cxgbe_nm_attach(struct vi_info *vi)
969 struct port_info *pi;
971 struct netmap_adapter na;
973 MPASS(vi->nnmrxq > 0);
974 MPASS(vi->ifp != NULL);
979 bzero(&na, sizeof(na));
982 na.na_flags = NAF_BDG_MAYSLEEP;
984 /* Netmap doesn't know about the space reserved for the status page. */
985 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
988 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
989 * num_rx_desc is based on the number of buffers that can be held in the
990 * freelist, and not the number of entries in the iq. (These two are
991 * not exactly the same due to the space taken up by the status page).
993 na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
994 na.nm_txsync = cxgbe_netmap_txsync;
995 na.nm_rxsync = cxgbe_netmap_rxsync;
996 na.nm_register = cxgbe_netmap_reg;
997 na.num_tx_rings = vi->nnmtxq;
998 na.num_rx_rings = vi->nnmrxq;
999 na.rx_buf_maxsize = MAX_MTU;
1000 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
1004 cxgbe_nm_detach(struct vi_info *vi)
1007 MPASS(vi->nnmrxq > 0);
1008 MPASS(vi->ifp != NULL);
1010 netmap_detach(vi->ifp);
1013 static inline const void *
1014 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
1017 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
1019 /* data[0] is RSS header */
1020 return (&cpl->data[1]);
1024 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
1025 const struct cpl_sge_egr_update *egr)
1028 struct sge_nm_txq *nm_txq;
1030 oq = be32toh(egr->opcode_qid);
1031 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1032 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1034 netmap_tx_irq(ifp, nm_txq->nid);
1038 service_nm_rxq(struct sge_nm_rxq *nm_rxq)
1040 struct vi_info *vi = nm_rxq->vi;
1041 struct adapter *sc = vi->pi->adapter;
1042 struct ifnet *ifp = vi->ifp;
1043 struct netmap_adapter *na = NA(ifp);
1044 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
1045 struct netmap_ring *ring = kring->ring;
1046 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1051 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1052 u_int fl_credits = fl_cidx & 7;
1053 u_int ndesc = 0; /* desc processed since last cidx update */
1054 u_int nframes = 0; /* frames processed since last netmap wakeup */
1056 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1060 lq = be32toh(d->rsp.pldbuflen_qid);
1061 opcode = d->rss.opcode;
1064 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1065 case X_RSPD_TYPE_FLBUF:
1069 case X_RSPD_TYPE_CPL:
1070 MPASS(opcode < NUM_CPL_CMDS);
1075 cpl = unwrap_nm_fw6_msg(cpl);
1077 case CPL_SGE_EGR_UPDATE:
1078 handle_nm_sge_egr_update(sc, ifp, cpl);
1081 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1082 sc->params.sge.fl_pktshift;
1083 ring->slot[fl_cidx].flags = 0;
1085 if (!(lq & F_RSPD_NEWBUF)) {
1086 MPASS(black_hole == 2);
1090 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1094 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1095 __func__, opcode, nm_rxq);
1099 case X_RSPD_TYPE_INTR:
1100 /* Not equipped to handle forwarded interrupts. */
1101 panic("%s: netmap queue received interrupt for iq %u\n",
1105 panic("%s: illegal response type %d on nm_rxq %p",
1106 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1110 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1111 nm_rxq->iq_cidx = 0;
1112 d = &nm_rxq->iq_desc[0];
1113 nm_rxq->iq_gen ^= F_RSPD_GEN;
1116 if (__predict_false(++nframes == rx_nframes) && !black_hole) {
1117 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1118 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1122 if (__predict_false(++ndesc == rx_ndesc)) {
1123 if (black_hole && fl_credits >= 8) {
1125 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1127 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1128 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1129 fl_credits = fl_cidx & 7;
1131 t4_write_reg(sc, sc->sge_gts_reg,
1133 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1134 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1139 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1142 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1143 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1144 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1145 } else if (nframes > 0)
1146 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1148 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1149 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1150 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));