2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
37 #include <sys/eventhandler.h>
40 #include <sys/module.h>
41 #include <sys/selinfo.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <machine/bus.h>
45 #include <net/ethernet.h>
47 #include <net/if_media.h>
48 #include <net/if_var.h>
49 #include <net/if_clone.h>
50 #include <net/if_types.h>
51 #include <net/netmap.h>
52 #include <dev/netmap/netmap_kern.h>
54 #include "common/common.h"
55 #include "common/t4_regs.h"
56 #include "common/t4_regs_values.h"
58 extern int fl_pad; /* XXXNM */
60 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters");
63 * 0 = normal netmap rx
65 * 2 = supermassive black hole (buffer packing enabled)
68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
69 "Sink incoming packets.");
72 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
75 int holdoff_tmr_idx = 2;
76 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
77 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
81 * -1: no congestion feedback (not recommended).
82 * 0: backpressure the channel instead of dropping packets right away.
83 * 1: no backpressure, drop packets for the congested queue immediately.
85 static int nm_cong_drop = 1;
86 TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop);
89 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
93 struct adapter *sc = vi->pi->adapter;
94 struct sge_params *sp = &sc->params.sge;
95 struct netmap_adapter *na = NA(vi->ifp);
99 MPASS(nm_rxq->iq_desc != NULL);
100 MPASS(nm_rxq->fl_desc != NULL);
102 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
103 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
105 bzero(&c, sizeof(c));
106 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
107 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
109 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
111 MPASS(!forwarding_intr_to_fwq(sc));
112 KASSERT(nm_rxq->intr_idx < sc->intr_count,
113 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
114 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
115 c.type_to_iqandstindex = htobe32(v |
116 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
117 V_FW_IQ_CMD_VIID(vi->viid) |
118 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
119 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
120 F_FW_IQ_CMD_IQGTSMODE |
121 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
122 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
123 c.iqsize = htobe16(vi->qsize_rxq);
124 c.iqaddr = htobe64(nm_rxq->iq_ba);
126 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
127 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
128 F_FW_IQ_CMD_FL0CONGEN);
130 c.iqns_to_fl0congen |=
131 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
132 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
133 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
134 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
135 c.fl0dcaen_to_fl0cidxfthresh =
136 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
137 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
138 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
139 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
140 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
141 c.fl0addr = htobe64(nm_rxq->fl_ba);
143 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
145 device_printf(sc->dev,
146 "failed to create netmap ingress queue: %d\n", rc);
151 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
152 nm_rxq->iq_gen = F_RSPD_GEN;
153 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
154 nm_rxq->iq_abs_id = be16toh(c.physiqid);
155 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
156 if (cntxt_id >= sc->sge.niq) {
157 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
158 __func__, cntxt_id, sc->sge.niq - 1);
160 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
162 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
163 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
164 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
165 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
166 if (cntxt_id >= sc->sge.neq) {
167 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
168 __func__, cntxt_id, sc->sge.neq - 1);
170 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
172 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
173 sc->chip_params->sge_fl_db;
175 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
178 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
179 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
180 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
181 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
182 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
183 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
188 for (i = 0; i < 4; i++) {
190 val |= 1 << (i << 2);
194 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
196 /* report error but carry on */
197 device_printf(sc->dev,
198 "failed to set congestion manager context for "
199 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
203 t4_write_reg(sc, sc->sge_gts_reg,
204 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
205 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
211 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
213 struct adapter *sc = vi->pi->adapter;
216 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
217 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
219 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
220 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
221 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
226 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
230 struct adapter *sc = vi->pi->adapter;
231 struct netmap_adapter *na = NA(vi->ifp);
232 struct fw_eq_eth_cmd c;
235 MPASS(nm_txq->desc != NULL);
237 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
238 bzero(nm_txq->desc, len);
240 bzero(&c, sizeof(c));
241 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
242 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
243 V_FW_EQ_ETH_CMD_VFN(0));
244 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
245 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
246 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
247 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
249 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
250 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
251 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
252 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
253 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
254 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
255 c.eqaddr = htobe64(nm_txq->ba);
257 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
259 device_printf(vi->dev,
260 "failed to create netmap egress queue: %d\n", rc);
264 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
265 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
266 if (cntxt_id >= sc->sge.neq)
267 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
268 cntxt_id, sc->sge.neq - 1);
269 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
271 nm_txq->pidx = nm_txq->cidx = 0;
272 MPASS(nm_txq->sidx == na->num_tx_desc);
273 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
275 nm_txq->doorbells = sc->doorbells;
276 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
277 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
278 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
279 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
280 uint32_t mask = (1 << s_qpp) - 1;
281 volatile uint8_t *udb;
283 udb = sc->udbs_base + UDBS_DB_OFFSET;
284 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
285 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
286 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
287 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
289 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
292 nm_txq->udb = (volatile void *)udb;
299 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
301 struct adapter *sc = vi->pi->adapter;
304 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
306 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
307 nm_txq->cntxt_id, rc);
308 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
313 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
314 struct netmap_adapter *na)
316 struct netmap_slot *slot;
317 struct netmap_kring *kring;
318 struct sge_nm_rxq *nm_rxq;
319 struct sge_nm_txq *nm_txq;
321 struct hw_buf_info *hwb;
323 ASSERT_SYNCHRONIZED_OP(sc);
325 if ((vi->flags & VI_INIT_DONE) == 0 ||
326 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
329 hwb = &sc->sge.hw_buf_info[0];
330 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
331 if (hwb->size == NETMAP_BUF_SIZE(na))
334 if (i >= SGE_FLBUF_SIZES) {
335 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
336 NETMAP_BUF_SIZE(na));
341 /* Must set caps before calling netmap_reset */
342 nm_set_native_flags(na);
344 for_each_nm_rxq(vi, i, nm_rxq) {
345 struct irq *irq = &sc->irq[vi->first_intr + i];
347 kring = &na->rx_rings[nm_rxq->nid];
348 if (!nm_kring_pending_on(kring) ||
349 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
352 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
353 nm_rxq->fl_hwidx = hwidx;
354 slot = netmap_reset(na, NR_RX, i, 0);
355 MPASS(slot != NULL); /* XXXNM: error check, not assert */
357 /* We deal with 8 bufs at a time */
358 MPASS((na->num_rx_desc & 7) == 0);
359 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
360 for (j = 0; j < nm_rxq->fl_sidx; j++) {
363 PNMB(na, &slot[j], &ba);
365 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
367 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
369 j /= 8; /* driver pidx to hardware pidx */
371 t4_write_reg(sc, sc->sge_kdoorbell_reg,
372 nm_rxq->fl_db_val | V_PIDX(j));
374 atomic_cmpset_int(&irq->nm_state, NM_OFF, NM_ON);
377 for_each_nm_txq(vi, i, nm_txq) {
378 kring = &na->tx_rings[nm_txq->nid];
379 if (!nm_kring_pending_on(kring) ||
380 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
383 alloc_nm_txq_hwq(vi, nm_txq);
384 slot = netmap_reset(na, NR_TX, i, 0);
385 MPASS(slot != NULL); /* XXXNM: error check, not assert */
388 if (vi->nm_rss == NULL) {
389 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
392 for (i = 0; i < vi->rss_size;) {
393 for_each_nm_rxq(vi, j, nm_rxq) {
394 vi->nm_rss[i++] = nm_rxq->iq_abs_id;
395 if (i == vi->rss_size)
399 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
400 vi->nm_rss, vi->rss_size);
402 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
408 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
409 struct netmap_adapter *na)
411 struct netmap_kring *kring;
413 struct sge_nm_txq *nm_txq;
414 struct sge_nm_rxq *nm_rxq;
416 ASSERT_SYNCHRONIZED_OP(sc);
418 if ((vi->flags & VI_INIT_DONE) == 0)
421 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
422 vi->rss, vi->rss_size);
424 if_printf(ifp, "failed to restore RSS config: %d\n", rc);
425 nm_clear_native_flags(na);
427 for_each_nm_txq(vi, i, nm_txq) {
428 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
430 kring = &na->tx_rings[nm_txq->nid];
431 if (!nm_kring_pending_off(kring) ||
432 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
435 /* Wait for hw pidx to catch up ... */
436 while (be16toh(nm_txq->pidx) != spg->pidx)
439 /* ... and then for the cidx. */
440 while (spg->pidx != spg->cidx)
443 free_nm_txq_hwq(vi, nm_txq);
445 for_each_nm_rxq(vi, i, nm_rxq) {
446 struct irq *irq = &sc->irq[vi->first_intr + i];
448 kring = &na->rx_rings[nm_rxq->nid];
449 if (!nm_kring_pending_off(kring) ||
450 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
453 while (!atomic_cmpset_int(&irq->nm_state, NM_ON, NM_OFF))
456 free_nm_rxq_hwq(vi, nm_rxq);
463 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
465 struct ifnet *ifp = na->ifp;
466 struct vi_info *vi = ifp->if_softc;
467 struct adapter *sc = vi->pi->adapter;
470 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
474 rc = cxgbe_netmap_on(sc, vi, ifp, na);
476 rc = cxgbe_netmap_off(sc, vi, ifp, na);
477 end_synchronized_op(sc, 0);
482 /* How many packets can a single type1 WR carry in n descriptors */
484 ndesc_to_npkt(const int n)
487 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
491 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
493 /* Space (in descriptors) needed for a type1 WR that carries n packets */
495 npkt_to_ndesc(const int n)
498 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
500 return ((n + 2) / 2);
503 /* Space (in 16B units) needed for a type1 WR that carries n packets */
505 npkt_to_len16(const int n)
508 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
513 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
516 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
519 u_int db = nm_txq->doorbells;
521 MPASS(nm_txq->pidx != nm_txq->dbidx);
523 n = NMIDXDIFF(nm_txq, dbidx);
525 clrbit(&db, DOORBELL_WCWR);
528 switch (ffs(db) - 1) {
530 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
533 case DOORBELL_WCWR: {
534 volatile uint64_t *dst, *src;
537 * Queues whose 128B doorbell segment fits in the page do not
538 * use relative qid (udb_qid is always 0). Only queues with
539 * doorbell segments can do WCWR.
541 KASSERT(nm_txq->udb_qid == 0 && n == 1,
542 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
543 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
545 dst = (volatile void *)((uintptr_t)nm_txq->udb +
546 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
547 src = (void *)&nm_txq->desc[nm_txq->dbidx];
548 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
555 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
560 t4_write_reg(sc, sc->sge_kdoorbell_reg,
561 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
564 nm_txq->dbidx = nm_txq->pidx;
567 int lazy_tx_credit_flush = 1;
570 * Write work requests to send 'npkt' frames and ring the doorbell to send them
571 * on their way. No need to check for wraparound.
574 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
575 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
577 struct netmap_ring *ring = kring->ring;
578 struct netmap_slot *slot;
579 const u_int lim = kring->nkr_num_slots - 1;
580 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
583 struct cpl_tx_pkt_core *cpl;
584 struct ulptx_sgl *usgl;
588 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
591 wr = (void *)&nm_txq->desc[nm_txq->pidx];
592 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
593 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
597 cpl = (void *)(wr + 1);
599 for (i = 0; i < n; i++) {
600 slot = &ring->slot[kring->nr_hwcur];
601 PNMB(kring->na, slot, &ba);
604 cpl->ctrl0 = nm_txq->cpl_ctrl0;
606 cpl->len = htobe16(slot->len);
608 * netmap(4) says "netmap does not use features such as
609 * checksum offloading, TCP segmentation offloading,
610 * encryption, VLAN encapsulation/decapsulation, etc."
612 * So the ncxl interfaces have tx hardware checksumming
613 * disabled by default. But you can override netmap by
614 * enabling IFCAP_TXCSUM on the interface manully.
616 cpl->ctrl1 = txcsum ? 0 :
617 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
619 usgl = (void *)(cpl + 1);
620 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
622 usgl->len0 = htobe32(slot->len);
623 usgl->addr0 = htobe64(ba);
625 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
626 cpl = (void *)(usgl + 1);
627 MPASS(slot->len + len <= UINT16_MAX);
629 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
631 wr->plen = htobe16(len);
634 nm_txq->pidx += npkt_to_ndesc(n);
635 MPASS(nm_txq->pidx <= nm_txq->sidx);
636 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
638 * This routine doesn't know how to write WRs that wrap
639 * around. Make sure it wasn't asked to.
645 if (npkt == 0 && npkt_remaining == 0) {
647 if (lazy_tx_credit_flush == 0) {
648 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
650 nm_txq->equeqidx = nm_txq->pidx;
651 nm_txq->equiqidx = nm_txq->pidx;
653 ring_nm_txq_db(sc, nm_txq);
657 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
658 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
660 nm_txq->equeqidx = nm_txq->pidx;
661 nm_txq->equiqidx = nm_txq->pidx;
662 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
663 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
664 nm_txq->equeqidx = nm_txq->pidx;
666 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
667 ring_nm_txq_db(sc, nm_txq);
670 /* Will get called again. */
671 MPASS(npkt_remaining);
674 /* How many contiguous free descriptors starting at pidx */
676 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
679 if (nm_txq->cidx > nm_txq->pidx)
680 return (nm_txq->cidx - nm_txq->pidx - 1);
681 else if (nm_txq->cidx > 0)
682 return (nm_txq->sidx - nm_txq->pidx);
684 return (nm_txq->sidx - nm_txq->pidx - 1);
688 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
690 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
691 uint16_t hw_cidx = spg->cidx; /* snapshot */
692 struct fw_eth_tx_pkts_wr *wr;
695 hw_cidx = be16toh(hw_cidx);
697 while (nm_txq->cidx != hw_cidx) {
698 wr = (void *)&nm_txq->desc[nm_txq->cidx];
700 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
701 MPASS(wr->type == 1);
702 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
705 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
708 * We never sent a WR that wrapped around so the credits coming
709 * back, WR by WR, should never cause the cidx to wrap around
712 MPASS(nm_txq->cidx <= nm_txq->sidx);
713 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
721 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
723 struct netmap_adapter *na = kring->na;
724 struct ifnet *ifp = na->ifp;
725 struct vi_info *vi = ifp->if_softc;
726 struct adapter *sc = vi->pi->adapter;
727 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
728 const u_int head = kring->rhead;
730 int n, d, npkt_remaining, ndesc_remaining, txcsum;
733 * Tx was at kring->nr_hwcur last time around and now we need to advance
734 * to kring->rhead. Note that the driver's pidx moves independent of
735 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
736 * between descriptors and frames isn't 1:1).
739 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
740 kring->nkr_num_slots - kring->nr_hwcur + head;
741 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
742 while (npkt_remaining) {
743 reclaimed += reclaim_nm_tx_desc(nm_txq);
744 ndesc_remaining = contiguous_ndesc_available(nm_txq);
745 /* Can't run out of descriptors with packets still remaining */
746 MPASS(ndesc_remaining > 0);
748 /* # of desc needed to tx all remaining packets */
749 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
750 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
751 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
753 if (d <= ndesc_remaining)
756 /* Can't send all, calculate how many can be sent */
757 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
758 MAX_NPKT_IN_TYPE1_WR;
759 if (ndesc_remaining % SGE_MAX_WR_NDESC)
760 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
763 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
765 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
767 MPASS(npkt_remaining == 0);
768 MPASS(kring->nr_hwcur == head);
769 MPASS(nm_txq->dbidx == nm_txq->pidx);
772 * Second part: reclaim buffers for completed transmissions.
774 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
775 reclaimed += reclaim_nm_tx_desc(nm_txq);
776 kring->nr_hwtail += reclaimed;
777 if (kring->nr_hwtail >= kring->nkr_num_slots)
778 kring->nr_hwtail -= kring->nkr_num_slots;
785 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
787 struct netmap_adapter *na = kring->na;
788 struct netmap_ring *ring = kring->ring;
789 struct ifnet *ifp = na->ifp;
790 struct vi_info *vi = ifp->if_softc;
791 struct adapter *sc = vi->pi->adapter;
792 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
793 u_int const head = kring->rhead;
795 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
798 return (0); /* No updates ever. */
800 if (netmap_no_pendintr || force_update) {
801 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
802 kring->nr_kflags &= ~NKR_PENDINTR;
805 /* Userspace done with buffers from kring->nr_hwcur to head */
806 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
807 kring->nkr_num_slots - kring->nr_hwcur + head;
810 u_int fl_pidx = nm_rxq->fl_pidx;
811 struct netmap_slot *slot = &ring->slot[fl_pidx];
813 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
816 * We always deal with 8 buffers at a time. We must have
817 * stopped at an 8B boundary (fl_pidx) last time around and we
818 * must have a multiple of 8B buffers to give to the freelist.
820 MPASS((fl_pidx & 7) == 0);
823 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
824 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
827 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
830 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
831 slot->flags &= ~NS_BUF_CHANGED;
832 MPASS(fl_pidx <= nm_rxq->fl_sidx);
835 if (fl_pidx == nm_rxq->fl_sidx) {
837 slot = &ring->slot[0];
839 if (++dbinc == 8 && n >= 32) {
841 t4_write_reg(sc, sc->sge_kdoorbell_reg,
842 nm_rxq->fl_db_val | V_PIDX(dbinc));
846 MPASS(nm_rxq->fl_pidx == fl_pidx);
850 t4_write_reg(sc, sc->sge_kdoorbell_reg,
851 nm_rxq->fl_db_val | V_PIDX(dbinc));
859 cxgbe_nm_attach(struct vi_info *vi)
861 struct port_info *pi;
863 struct netmap_adapter na;
865 MPASS(vi->nnmrxq > 0);
866 MPASS(vi->ifp != NULL);
871 bzero(&na, sizeof(na));
874 na.na_flags = NAF_BDG_MAYSLEEP;
876 /* Netmap doesn't know about the space reserved for the status page. */
877 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
880 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
881 * num_rx_desc is based on the number of buffers that can be held in the
882 * freelist, and not the number of entries in the iq. (These two are
883 * not exactly the same due to the space taken up by the status page).
885 na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
886 na.nm_txsync = cxgbe_netmap_txsync;
887 na.nm_rxsync = cxgbe_netmap_rxsync;
888 na.nm_register = cxgbe_netmap_reg;
889 na.num_tx_rings = vi->nnmtxq;
890 na.num_rx_rings = vi->nnmrxq;
895 cxgbe_nm_detach(struct vi_info *vi)
898 MPASS(vi->nnmrxq > 0);
899 MPASS(vi->ifp != NULL);
901 netmap_detach(vi->ifp);
904 static inline const void *
905 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
908 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
910 /* data[0] is RSS header */
911 return (&cpl->data[1]);
915 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
916 const struct cpl_sge_egr_update *egr)
919 struct sge_nm_txq *nm_txq;
921 oq = be32toh(egr->opcode_qid);
922 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
923 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
925 netmap_tx_irq(ifp, nm_txq->nid);
929 t4_nm_intr(void *arg)
931 struct sge_nm_rxq *nm_rxq = arg;
932 struct vi_info *vi = nm_rxq->vi;
933 struct adapter *sc = vi->pi->adapter;
934 struct ifnet *ifp = vi->ifp;
935 struct netmap_adapter *na = NA(ifp);
936 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
937 struct netmap_ring *ring = kring->ring;
938 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
941 u_int n = 0, work = 0;
943 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
944 u_int fl_credits = fl_cidx & 7;
946 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
950 lq = be32toh(d->rsp.pldbuflen_qid);
951 opcode = d->rss.opcode;
954 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
955 case X_RSPD_TYPE_FLBUF:
956 if (black_hole != 2) {
957 /* No buffer packing so new buf every time */
958 MPASS(lq & F_RSPD_NEWBUF);
963 case X_RSPD_TYPE_CPL:
964 MPASS(opcode < NUM_CPL_CMDS);
969 cpl = unwrap_nm_fw6_msg(cpl);
971 case CPL_SGE_EGR_UPDATE:
972 handle_nm_sge_egr_update(sc, ifp, cpl);
975 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
976 sc->params.sge.fl_pktshift;
977 ring->slot[fl_cidx].flags = kring->nkr_slot_flags;
978 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0;
979 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0;
980 if (__predict_false(fl_cidx == nm_rxq->fl_sidx))
984 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
985 __func__, opcode, nm_rxq);
989 case X_RSPD_TYPE_INTR:
990 /* Not equipped to handle forwarded interrupts. */
991 panic("%s: netmap queue received interrupt for iq %u\n",
995 panic("%s: illegal response type %d on nm_rxq %p",
996 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1000 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1001 nm_rxq->iq_cidx = 0;
1002 d = &nm_rxq->iq_desc[0];
1003 nm_rxq->iq_gen ^= F_RSPD_GEN;
1006 if (__predict_false(++n == rx_ndesc)) {
1007 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1008 if (black_hole && fl_credits >= 8) {
1010 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1012 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1013 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1014 fl_credits = fl_cidx & 7;
1015 } else if (!black_hole) {
1016 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1019 t4_write_reg(sc, sc->sge_gts_reg,
1020 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1021 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1026 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1029 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1030 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1031 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1033 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1035 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(n) |
1036 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1037 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));