sys/dev/cxgbe/t4_netmap.c

   1 /*-
   2  * Copyright (c) 2014 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  * Written by: Navdeep Parhar <np@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_inet.h"
  32 #include "opt_inet6.h"
  33
  34 #ifdef DEV_NETMAP
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/eventhandler.h>
  38 #include <sys/lock.h>
  39 #include <sys/mbuf.h>
  40 #include <sys/module.h>
  41 #include <sys/selinfo.h>
  42 #include <sys/socket.h>
  43 #include <sys/sockio.h>
  44 #include <machine/bus.h>
  45 #include <net/ethernet.h>
  46 #include <net/if.h>
  47 #include <net/if_media.h>
  48 #include <net/if_var.h>
  49 #include <net/if_clone.h>
  50 #include <net/if_types.h>
  51 #include <net/netmap.h>
  52 #include <dev/netmap/netmap_kern.h>
  53
  54 #include "common/common.h"
  55 #include "common/t4_regs.h"
  56 #include "common/t4_regs_values.h"
  57
  58 extern int fl_pad;      /* XXXNM */
  59
  60 /*
  61  * 0 = normal netmap rx
  62  * 1 = black hole
  63  * 2 = supermassive black hole (buffer packing enabled)
  64  */
  65 int black_hole = 0;
  66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
  67     "Sink incoming packets.");
  68
  69 int rx_ndesc = 256;
  70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
  71     &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
  72
  73 int rx_nframes = 64;
  74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN,
  75     &rx_nframes, 0, "max # of frames received before waking up netmap rx.");
  76
  77 int holdoff_tmr_idx = 2;
  78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
  79     &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
  80
  81 /*
  82  * Congestion drops.
  83  * -1: no congestion feedback (not recommended).
  84  *  0: backpressure the channel instead of dropping packets right away.
  85  *  1: no backpressure, drop packets for the congested queue immediately.
  86  */
  87 static int nm_cong_drop = 1;
  88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RDTUN,
  89     &nm_cong_drop, 0,
  90     "Congestion control for netmap rx queues (0 = backpressure, 1 = drop");
  91
  92 int starve_fl = 0;
  93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN,
  94     &starve_fl, 0, "Don't ring fl db for netmap rx queues.");
  95
  96 /*
  97  * Try to process tx credits in bulk.  This may cause a delay in the return of
  98  * tx credits and is suitable for bursty or non-stop tx only.
  99  */
 100 int lazy_tx_credit_flush = 1;
 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN,
 102     &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues.");
 103
 104 static int
 105 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
 106 {
 107         int rc, cntxt_id, i;
 108         __be32 v;
 109         struct adapter *sc = vi->pi->adapter;
 110         struct sge_params *sp = &sc->params.sge;
 111         struct netmap_adapter *na = NA(vi->ifp);
 112         struct fw_iq_cmd c;
 113
 114         MPASS(na != NULL);
 115         MPASS(nm_rxq->iq_desc != NULL);
 116         MPASS(nm_rxq->fl_desc != NULL);
 117
 118         bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
 119         bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
 120
 121         bzero(&c, sizeof(c));
 122         c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
 123             F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
 124             V_FW_IQ_CMD_VFN(0));
 125         c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
 126             FW_LEN16(c));
 127         MPASS(!forwarding_intr_to_fwq(sc));
 128         KASSERT(nm_rxq->intr_idx < sc->intr_count,
 129             ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
 130         v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
 131         c.type_to_iqandstindex = htobe32(v |
 132             V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
 133             V_FW_IQ_CMD_VIID(vi->viid) |
 134             V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
 135         c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
 136             F_FW_IQ_CMD_IQGTSMODE |
 137             V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
 138             V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
 139         c.iqsize = htobe16(vi->qsize_rxq);
 140         c.iqaddr = htobe64(nm_rxq->iq_ba);
 141         if (cong >= 0) {
 142                 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
 143                     V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
 144                     F_FW_IQ_CMD_FL0CONGEN);
 145         }
 146         c.iqns_to_fl0congen |=
 147             htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
 148                 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
 149                 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
 150                 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
 151         c.fl0dcaen_to_fl0cidxfthresh =
 152             htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
 153                 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
 154                 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
 155                 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
 156         c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
 157         c.fl0addr = htobe64(nm_rxq->fl_ba);
 158
 159         rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 160         if (rc != 0) {
 161                 device_printf(sc->dev,
 162                     "failed to create netmap ingress queue: %d\n", rc);
 163                 return (rc);
 164         }
 165
 166         nm_rxq->iq_cidx = 0;
 167         MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
 168         nm_rxq->iq_gen = F_RSPD_GEN;
 169         nm_rxq->iq_cntxt_id = be16toh(c.iqid);
 170         nm_rxq->iq_abs_id = be16toh(c.physiqid);
 171         cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
 172         if (cntxt_id >= sc->sge.niq) {
 173                 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
 174                     __func__, cntxt_id, sc->sge.niq - 1);
 175         }
 176         sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
 177
 178         nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
 179         nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
 180         MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
 181         cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
 182         if (cntxt_id >= sc->sge.neq) {
 183                 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
 184                     __func__, cntxt_id, sc->sge.neq - 1);
 185         }
 186         sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
 187
 188         nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
 189             sc->chip_params->sge_fl_db;
 190
 191         if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
 192                 uint32_t param, val;
 193
 194                 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 195                     V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
 196                     V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
 197                 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 198                     V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
 199                     V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
 200                 if (cong == 0)
 201                         val = 1 << 19;
 202                 else {
 203                         val = 2 << 19;
 204                         for (i = 0; i < 4; i++) {
 205                                 if (cong & (1 << i))
 206                                         val |= 1 << (i << 2);
 207                         }
 208                 }
 209
 210                 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 211                 if (rc != 0) {
 212                         /* report error but carry on */
 213                         device_printf(sc->dev,
 214                             "failed to set congestion manager context for "
 215                             "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
 216                 }
 217         }
 218
 219         t4_write_reg(sc, sc->sge_gts_reg,
 220             V_INGRESSQID(nm_rxq->iq_cntxt_id) |
 221             V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
 222
 223         return (rc);
 224 }
 225
 226 static int
 227 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 228 {
 229         struct adapter *sc = vi->pi->adapter;
 230         int rc;
 231
 232         rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
 233             nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
 234         if (rc != 0)
 235                 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
 236                     __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
 237         nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
 238         return (rc);
 239 }
 240
 241 static int
 242 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 243 {
 244         int rc, cntxt_id;
 245         size_t len;
 246         struct adapter *sc = vi->pi->adapter;
 247         struct netmap_adapter *na = NA(vi->ifp);
 248         struct fw_eq_eth_cmd c;
 249
 250         MPASS(na != NULL);
 251         MPASS(nm_txq->desc != NULL);
 252
 253         len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
 254         bzero(nm_txq->desc, len);
 255
 256         bzero(&c, sizeof(c));
 257         c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
 258             F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
 259             V_FW_EQ_ETH_CMD_VFN(0));
 260         c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
 261             F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
 262         c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
 263             F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
 264         c.fetchszm_to_iqid =
 265             htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
 266                 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
 267                 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
 268         c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
 269                       V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
 270                       V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
 271         c.eqaddr = htobe64(nm_txq->ba);
 272
 273         rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 274         if (rc != 0) {
 275                 device_printf(vi->dev,
 276                     "failed to create netmap egress queue: %d\n", rc);
 277                 return (rc);
 278         }
 279
 280         nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
 281         cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
 282         if (cntxt_id >= sc->sge.neq)
 283             panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
 284                 cntxt_id, sc->sge.neq - 1);
 285         sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
 286
 287         nm_txq->pidx = nm_txq->cidx = 0;
 288         MPASS(nm_txq->sidx == na->num_tx_desc);
 289         nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
 290
 291         nm_txq->doorbells = sc->doorbells;
 292         if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
 293             isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
 294             isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
 295                 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
 296                 uint32_t mask = (1 << s_qpp) - 1;
 297                 volatile uint8_t *udb;
 298
 299                 udb = sc->udbs_base + UDBS_DB_OFFSET;
 300                 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
 301                 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
 302                 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
 303                         clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
 304                 else {
 305                         udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
 306                         nm_txq->udb_qid = 0;
 307                 }
 308                 nm_txq->udb = (volatile void *)udb;
 309         }
 310
 311         return (rc);
 312 }
 313
 314 static int
 315 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 316 {
 317         struct adapter *sc = vi->pi->adapter;
 318         int rc;
 319
 320         rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
 321         if (rc != 0)
 322                 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
 323                     nm_txq->cntxt_id, rc);
 324         nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
 325         return (rc);
 326 }
 327
 328 static int
 329 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
 330     struct netmap_adapter *na)
 331 {
 332         struct netmap_slot *slot;
 333         struct netmap_kring *kring;
 334         struct sge_nm_rxq *nm_rxq;
 335         struct sge_nm_txq *nm_txq;
 336         int rc, i, j, hwidx;
 337         struct hw_buf_info *hwb;
 338
 339         ASSERT_SYNCHRONIZED_OP(sc);
 340
 341         if ((vi->flags & VI_INIT_DONE) == 0 ||
 342             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 343                 return (EAGAIN);
 344
 345         hwb = &sc->sge.hw_buf_info[0];
 346         for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
 347                 if (hwb->size == NETMAP_BUF_SIZE(na))
 348                         break;
 349         }
 350         if (i >= SGE_FLBUF_SIZES) {
 351                 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
 352                     NETMAP_BUF_SIZE(na));
 353                 return (ENXIO);
 354         }
 355         hwidx = i;
 356
 357         /* Must set caps before calling netmap_reset */
 358         nm_set_native_flags(na);
 359
 360         for_each_nm_rxq(vi, i, nm_rxq) {
 361                 kring = na->rx_rings[nm_rxq->nid];
 362                 if (!nm_kring_pending_on(kring) ||
 363                     nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
 364                         continue;
 365
 366                 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
 367                 nm_rxq->fl_hwidx = hwidx;
 368                 slot = netmap_reset(na, NR_RX, i, 0);
 369                 MPASS(slot != NULL);    /* XXXNM: error check, not assert */
 370
 371                 /* We deal with 8 bufs at a time */
 372                 MPASS((na->num_rx_desc & 7) == 0);
 373                 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
 374                 for (j = 0; j < nm_rxq->fl_sidx; j++) {
 375                         uint64_t ba;
 376
 377                         PNMB(na, &slot[j], &ba);
 378                         MPASS(ba != 0);
 379                         nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
 380                 }
 381                 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
 382                 MPASS((j & 7) == 0);
 383                 j /= 8; /* driver pidx to hardware pidx */
 384                 wmb();
 385                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 386                     nm_rxq->fl_db_val | V_PIDX(j));
 387
 388                 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
 389         }
 390
 391         for_each_nm_txq(vi, i, nm_txq) {
 392                 kring = na->tx_rings[nm_txq->nid];
 393                 if (!nm_kring_pending_on(kring) ||
 394                     nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
 395                         continue;
 396
 397                 alloc_nm_txq_hwq(vi, nm_txq);
 398                 slot = netmap_reset(na, NR_TX, i, 0);
 399                 MPASS(slot != NULL);    /* XXXNM: error check, not assert */
 400         }
 401
 402         if (vi->nm_rss == NULL) {
 403                 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
 404                     M_ZERO | M_WAITOK);
 405         }
 406         for (i = 0; i < vi->rss_size;) {
 407                 for_each_nm_rxq(vi, j, nm_rxq) {
 408                         vi->nm_rss[i++] = nm_rxq->iq_abs_id;
 409                         if (i == vi->rss_size)
 410                                 break;
 411                 }
 412         }
 413         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
 414             vi->nm_rss, vi->rss_size);
 415         if (rc != 0)
 416                 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
 417
 418         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen,
 419             vi->nm_rss[0], 0, 0);
 420         if (rc != 0)
 421                 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc);
 422
 423         return (rc);
 424 }
 425
 426 static int
 427 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
 428     struct netmap_adapter *na)
 429 {
 430         struct netmap_kring *kring;
 431         int rc, i;
 432         struct sge_nm_txq *nm_txq;
 433         struct sge_nm_rxq *nm_rxq;
 434
 435         ASSERT_SYNCHRONIZED_OP(sc);
 436
 437         if ((vi->flags & VI_INIT_DONE) == 0)
 438                 return (0);
 439
 440         rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
 441             vi->rss, vi->rss_size);
 442         if (rc != 0)
 443                 if_printf(ifp, "failed to restore RSS config: %d\n", rc);
 444         rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0);
 445         if (rc != 0)
 446                 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc);
 447         nm_clear_native_flags(na);
 448
 449         for_each_nm_txq(vi, i, nm_txq) {
 450                 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
 451
 452                 kring = na->tx_rings[nm_txq->nid];
 453                 if (!nm_kring_pending_off(kring) ||
 454                     nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
 455                         continue;
 456
 457                 /* Wait for hw pidx to catch up ... */
 458                 while (be16toh(nm_txq->pidx) != spg->pidx)
 459                         pause("nmpidx", 1);
 460
 461                 /* ... and then for the cidx. */
 462                 while (spg->pidx != spg->cidx)
 463                         pause("nmcidx", 1);
 464
 465                 free_nm_txq_hwq(vi, nm_txq);
 466         }
 467         for_each_nm_rxq(vi, i, nm_rxq) {
 468                 kring = na->rx_rings[nm_rxq->nid];
 469                 if (!nm_kring_pending_off(kring) ||
 470                     nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
 471                         continue;
 472
 473                 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
 474                         pause("nmst", 1);
 475
 476                 free_nm_rxq_hwq(vi, nm_rxq);
 477         }
 478
 479         return (rc);
 480 }
 481
 482 static int
 483 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
 484 {
 485         struct ifnet *ifp = na->ifp;
 486         struct vi_info *vi = ifp->if_softc;
 487         struct adapter *sc = vi->pi->adapter;
 488         int rc;
 489
 490         rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
 491         if (rc != 0)
 492                 return (rc);
 493         if (on)
 494                 rc = cxgbe_netmap_on(sc, vi, ifp, na);
 495         else
 496                 rc = cxgbe_netmap_off(sc, vi, ifp, na);
 497         end_synchronized_op(sc, 0);
 498
 499         return (rc);
 500 }
 501
 502 /* How many packets can a single type1 WR carry in n descriptors */
 503 static inline int
 504 ndesc_to_npkt(const int n)
 505 {
 506
 507         MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
 508
 509         return (n * 2 - 1);
 510 }
 511 #define MAX_NPKT_IN_TYPE1_WR    (ndesc_to_npkt(SGE_MAX_WR_NDESC))
 512
 513 /* Space (in descriptors) needed for a type1 WR that carries n packets */
 514 static inline int
 515 npkt_to_ndesc(const int n)
 516 {
 517
 518         MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
 519
 520         return ((n + 2) / 2);
 521 }
 522
 523 /* Space (in 16B units) needed for a type1 WR that carries n packets */
 524 static inline int
 525 npkt_to_len16(const int n)
 526 {
 527
 528         MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
 529
 530         return (n * 2 + 1);
 531 }
 532
 533 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
 534
 535 static void
 536 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
 537 {
 538         int n;
 539         u_int db = nm_txq->doorbells;
 540
 541         MPASS(nm_txq->pidx != nm_txq->dbidx);
 542
 543         n = NMIDXDIFF(nm_txq, dbidx);
 544         if (n > 1)
 545                 clrbit(&db, DOORBELL_WCWR);
 546         wmb();
 547
 548         switch (ffs(db) - 1) {
 549         case DOORBELL_UDB:
 550                 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
 551                 break;
 552
 553         case DOORBELL_WCWR: {
 554                 volatile uint64_t *dst, *src;
 555
 556                 /*
 557                  * Queues whose 128B doorbell segment fits in the page do not
 558                  * use relative qid (udb_qid is always 0).  Only queues with
 559                  * doorbell segments can do WCWR.
 560                  */
 561                 KASSERT(nm_txq->udb_qid == 0 && n == 1,
 562                     ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
 563                     __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
 564
 565                 dst = (volatile void *)((uintptr_t)nm_txq->udb +
 566                     UDBS_WR_OFFSET - UDBS_DB_OFFSET);
 567                 src = (void *)&nm_txq->desc[nm_txq->dbidx];
 568                 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
 569                         *dst++ = *src++;
 570                 wmb();
 571                 break;
 572         }
 573
 574         case DOORBELL_UDBWC:
 575                 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
 576                 wmb();
 577                 break;
 578
 579         case DOORBELL_KDB:
 580                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 581                     V_QID(nm_txq->cntxt_id) | V_PIDX(n));
 582                 break;
 583         }
 584         nm_txq->dbidx = nm_txq->pidx;
 585 }
 586
 587 /*
 588  * Write work requests to send 'npkt' frames and ring the doorbell to send them
 589  * on their way.  No need to check for wraparound.
 590  */
 591 static void
 592 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
 593     struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
 594 {
 595         struct netmap_ring *ring = kring->ring;
 596         struct netmap_slot *slot;
 597         const u_int lim = kring->nkr_num_slots - 1;
 598         struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
 599         uint16_t len;
 600         uint64_t ba;
 601         struct cpl_tx_pkt_core *cpl;
 602         struct ulptx_sgl *usgl;
 603         int i, n;
 604
 605         while (npkt) {
 606                 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
 607                 len = 0;
 608
 609                 wr = (void *)&nm_txq->desc[nm_txq->pidx];
 610                 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
 611                 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
 612                 wr->npkt = n;
 613                 wr->r3 = 0;
 614                 wr->type = 1;
 615                 cpl = (void *)(wr + 1);
 616
 617                 for (i = 0; i < n; i++) {
 618                         slot = &ring->slot[kring->nr_hwcur];
 619                         PNMB(kring->na, slot, &ba);
 620                         MPASS(ba != 0);
 621
 622                         cpl->ctrl0 = nm_txq->cpl_ctrl0;
 623                         cpl->pack = 0;
 624                         cpl->len = htobe16(slot->len);
 625                         /*
 626                          * netmap(4) says "netmap does not use features such as
 627                          * checksum offloading, TCP segmentation offloading,
 628                          * encryption, VLAN encapsulation/decapsulation, etc."
 629                          *
 630                          * So the ncxl interfaces have tx hardware checksumming
 631                          * disabled by default.  But you can override netmap by
 632                          * enabling IFCAP_TXCSUM on the interface manully.
 633                          */
 634                         cpl->ctrl1 = txcsum ? 0 :
 635                             htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
 636
 637                         usgl = (void *)(cpl + 1);
 638                         usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
 639                             V_ULPTX_NSGE(1));
 640                         usgl->len0 = htobe32(slot->len);
 641                         usgl->addr0 = htobe64(ba);
 642
 643                         slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
 644                         cpl = (void *)(usgl + 1);
 645                         MPASS(slot->len + len <= UINT16_MAX);
 646                         len += slot->len;
 647                         kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
 648                 }
 649                 wr->plen = htobe16(len);
 650
 651                 npkt -= n;
 652                 nm_txq->pidx += npkt_to_ndesc(n);
 653                 MPASS(nm_txq->pidx <= nm_txq->sidx);
 654                 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
 655                         /*
 656                          * This routine doesn't know how to write WRs that wrap
 657                          * around.  Make sure it wasn't asked to.
 658                          */
 659                         MPASS(npkt == 0);
 660                         nm_txq->pidx = 0;
 661                 }
 662
 663                 if (npkt == 0 && npkt_remaining == 0) {
 664                         /* All done. */
 665                         if (lazy_tx_credit_flush == 0) {
 666                                 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
 667                                     F_FW_WR_EQUIQ);
 668                                 nm_txq->equeqidx = nm_txq->pidx;
 669                                 nm_txq->equiqidx = nm_txq->pidx;
 670                         }
 671                         ring_nm_txq_db(sc, nm_txq);
 672                         return;
 673                 }
 674
 675                 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
 676                         wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
 677                             F_FW_WR_EQUIQ);
 678                         nm_txq->equeqidx = nm_txq->pidx;
 679                         nm_txq->equiqidx = nm_txq->pidx;
 680                 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
 681                         wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
 682                         nm_txq->equeqidx = nm_txq->pidx;
 683                 }
 684                 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
 685                         ring_nm_txq_db(sc, nm_txq);
 686         }
 687
 688         /* Will get called again. */
 689         MPASS(npkt_remaining);
 690 }
 691
 692 /* How many contiguous free descriptors starting at pidx */
 693 static inline int
 694 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
 695 {
 696
 697         if (nm_txq->cidx > nm_txq->pidx)
 698                 return (nm_txq->cidx - nm_txq->pidx - 1);
 699         else if (nm_txq->cidx > 0)
 700                 return (nm_txq->sidx - nm_txq->pidx);
 701         else
 702                 return (nm_txq->sidx - nm_txq->pidx - 1);
 703 }
 704
 705 static int
 706 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
 707 {
 708         struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
 709         uint16_t hw_cidx = spg->cidx;   /* snapshot */
 710         struct fw_eth_tx_pkts_wr *wr;
 711         int n = 0;
 712
 713         hw_cidx = be16toh(hw_cidx);
 714
 715         while (nm_txq->cidx != hw_cidx) {
 716                 wr = (void *)&nm_txq->desc[nm_txq->cidx];
 717
 718                 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
 719                 MPASS(wr->type == 1);
 720                 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
 721
 722                 n += wr->npkt;
 723                 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
 724
 725                 /*
 726                  * We never sent a WR that wrapped around so the credits coming
 727                  * back, WR by WR, should never cause the cidx to wrap around
 728                  * either.
 729                  */
 730                 MPASS(nm_txq->cidx <= nm_txq->sidx);
 731                 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
 732                         nm_txq->cidx = 0;
 733         }
 734
 735         return (n);
 736 }
 737
 738 static int
 739 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
 740 {
 741         struct netmap_adapter *na = kring->na;
 742         struct ifnet *ifp = na->ifp;
 743         struct vi_info *vi = ifp->if_softc;
 744         struct adapter *sc = vi->pi->adapter;
 745         struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
 746         const u_int head = kring->rhead;
 747         u_int reclaimed = 0;
 748         int n, d, npkt_remaining, ndesc_remaining, txcsum;
 749
 750         /*
 751          * Tx was at kring->nr_hwcur last time around and now we need to advance
 752          * to kring->rhead.  Note that the driver's pidx moves independent of
 753          * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
 754          * between descriptors and frames isn't 1:1).
 755          */
 756
 757         npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
 758             kring->nkr_num_slots - kring->nr_hwcur + head;
 759         txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
 760         while (npkt_remaining) {
 761                 reclaimed += reclaim_nm_tx_desc(nm_txq);
 762                 ndesc_remaining = contiguous_ndesc_available(nm_txq);
 763                 /* Can't run out of descriptors with packets still remaining */
 764                 MPASS(ndesc_remaining > 0);
 765
 766                 /* # of desc needed to tx all remaining packets */
 767                 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
 768                 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
 769                         d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
 770
 771                 if (d <= ndesc_remaining)
 772                         n = npkt_remaining;
 773                 else {
 774                         /* Can't send all, calculate how many can be sent */
 775                         n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
 776                             MAX_NPKT_IN_TYPE1_WR;
 777                         if (ndesc_remaining % SGE_MAX_WR_NDESC)
 778                                 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
 779                 }
 780
 781                 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
 782                 npkt_remaining -= n;
 783                 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
 784         }
 785         MPASS(npkt_remaining == 0);
 786         MPASS(kring->nr_hwcur == head);
 787         MPASS(nm_txq->dbidx == nm_txq->pidx);
 788
 789         /*
 790          * Second part: reclaim buffers for completed transmissions.
 791          */
 792         if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
 793                 reclaimed += reclaim_nm_tx_desc(nm_txq);
 794                 kring->nr_hwtail += reclaimed;
 795                 if (kring->nr_hwtail >= kring->nkr_num_slots)
 796                         kring->nr_hwtail -= kring->nkr_num_slots;
 797         }
 798
 799         return (0);
 800 }
 801
 802 static int
 803 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
 804 {
 805         struct netmap_adapter *na = kring->na;
 806         struct netmap_ring *ring = kring->ring;
 807         struct ifnet *ifp = na->ifp;
 808         struct vi_info *vi = ifp->if_softc;
 809         struct adapter *sc = vi->pi->adapter;
 810         struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
 811         u_int const head = kring->rhead;
 812         u_int n;
 813         int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
 814
 815         if (black_hole)
 816                 return (0);     /* No updates ever. */
 817
 818         if (netmap_no_pendintr || force_update) {
 819                 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
 820                 kring->nr_kflags &= ~NKR_PENDINTR;
 821         }
 822
 823         if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
 824                 wmb();
 825                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 826                     nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
 827                 nm_rxq->fl_db_saved = 0;
 828         }
 829
 830         /* Userspace done with buffers from kring->nr_hwcur to head */
 831         n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
 832             kring->nkr_num_slots - kring->nr_hwcur + head;
 833         n &= ~7U;
 834         if (n > 0) {
 835                 u_int fl_pidx = nm_rxq->fl_pidx;
 836                 struct netmap_slot *slot = &ring->slot[fl_pidx];
 837                 uint64_t ba;
 838                 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
 839
 840                 /*
 841                  * We always deal with 8 buffers at a time.  We must have
 842                  * stopped at an 8B boundary (fl_pidx) last time around and we
 843                  * must have a multiple of 8B buffers to give to the freelist.
 844                  */
 845                 MPASS((fl_pidx & 7) == 0);
 846                 MPASS((n & 7) == 0);
 847
 848                 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
 849                 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
 850
 851                 while (n > 0) {
 852                         for (i = 0; i < 8; i++, fl_pidx++, slot++) {
 853                                 PNMB(na, slot, &ba);
 854                                 MPASS(ba != 0);
 855                                 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
 856                                 slot->flags &= ~NS_BUF_CHANGED;
 857                                 MPASS(fl_pidx <= nm_rxq->fl_sidx);
 858                         }
 859                         n -= 8;
 860                         if (fl_pidx == nm_rxq->fl_sidx) {
 861                                 fl_pidx = 0;
 862                                 slot = &ring->slot[0];
 863                         }
 864                         if (++dbinc == 8 && n >= 32) {
 865                                 wmb();
 866                                 if (starve_fl)
 867                                         nm_rxq->fl_db_saved += dbinc;
 868                                 else {
 869                                         t4_write_reg(sc, sc->sge_kdoorbell_reg,
 870                                             nm_rxq->fl_db_val | V_PIDX(dbinc));
 871                                 }
 872                                 dbinc = 0;
 873                         }
 874                 }
 875                 MPASS(nm_rxq->fl_pidx == fl_pidx);
 876
 877                 if (dbinc > 0) {
 878                         wmb();
 879                         if (starve_fl)
 880                                 nm_rxq->fl_db_saved += dbinc;
 881                         else {
 882                                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
 883                                     nm_rxq->fl_db_val | V_PIDX(dbinc));
 884                         }
 885                 }
 886         }
 887
 888         return (0);
 889 }
 890
 891 void
 892 cxgbe_nm_attach(struct vi_info *vi)
 893 {
 894         struct port_info *pi;
 895         struct adapter *sc;
 896         struct netmap_adapter na;
 897
 898         MPASS(vi->nnmrxq > 0);
 899         MPASS(vi->ifp != NULL);
 900
 901         pi = vi->pi;
 902         sc = pi->adapter;
 903
 904         bzero(&na, sizeof(na));
 905
 906         na.ifp = vi->ifp;
 907         na.na_flags = NAF_BDG_MAYSLEEP;
 908
 909         /* Netmap doesn't know about the space reserved for the status page. */
 910         na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
 911
 912         /*
 913          * The freelist's cidx/pidx drives netmap's rx cidx/pidx.  So
 914          * num_rx_desc is based on the number of buffers that can be held in the
 915          * freelist, and not the number of entries in the iq.  (These two are
 916          * not exactly the same due to the space taken up by the status page).
 917          */
 918         na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
 919         na.nm_txsync = cxgbe_netmap_txsync;
 920         na.nm_rxsync = cxgbe_netmap_rxsync;
 921         na.nm_register = cxgbe_netmap_reg;
 922         na.num_tx_rings = vi->nnmtxq;
 923         na.num_rx_rings = vi->nnmrxq;
 924         netmap_attach(&na);     /* This adds IFCAP_NETMAP to if_capabilities */
 925 }
 926
 927 void
 928 cxgbe_nm_detach(struct vi_info *vi)
 929 {
 930
 931         MPASS(vi->nnmrxq > 0);
 932         MPASS(vi->ifp != NULL);
 933
 934         netmap_detach(vi->ifp);
 935 }
 936
 937 static inline const void *
 938 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
 939 {
 940
 941         MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
 942
 943         /* data[0] is RSS header */
 944         return (&cpl->data[1]);
 945 }
 946
 947 static void
 948 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
 949     const struct cpl_sge_egr_update *egr)
 950 {
 951         uint32_t oq;
 952         struct sge_nm_txq *nm_txq;
 953
 954         oq = be32toh(egr->opcode_qid);
 955         MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
 956         nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
 957
 958         netmap_tx_irq(ifp, nm_txq->nid);
 959 }
 960
 961 void
 962 service_nm_rxq(struct sge_nm_rxq *nm_rxq)
 963 {
 964         struct vi_info *vi = nm_rxq->vi;
 965         struct adapter *sc = vi->pi->adapter;
 966         struct ifnet *ifp = vi->ifp;
 967         struct netmap_adapter *na = NA(ifp);
 968         struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
 969         struct netmap_ring *ring = kring->ring;
 970         struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
 971         const void *cpl;
 972         uint32_t lq;
 973         u_int work = 0;
 974         uint8_t opcode;
 975         uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
 976         u_int fl_credits = fl_cidx & 7;
 977         u_int ndesc = 0;        /* desc processed since last cidx update */
 978         u_int nframes = 0;      /* frames processed since last netmap wakeup */
 979
 980         while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
 981
 982                 rmb();
 983
 984                 lq = be32toh(d->rsp.pldbuflen_qid);
 985                 opcode = d->rss.opcode;
 986                 cpl = &d->cpl[0];
 987
 988                 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
 989                 case X_RSPD_TYPE_FLBUF:
 990
 991                         /* fall through */
 992
 993                 case X_RSPD_TYPE_CPL:
 994                         MPASS(opcode < NUM_CPL_CMDS);
 995
 996                         switch (opcode) {
 997                         case CPL_FW4_MSG:
 998                         case CPL_FW6_MSG:
 999                                 cpl = unwrap_nm_fw6_msg(cpl);
1000                                 /* fall through */
1001                         case CPL_SGE_EGR_UPDATE:
1002                                 handle_nm_sge_egr_update(sc, ifp, cpl);
1003                                 break;
1004                         case CPL_RX_PKT:
1005                                 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1006                                     sc->params.sge.fl_pktshift;
1007                                 ring->slot[fl_cidx].flags = 0;
1008                                 nframes++;
1009                                 if (!(lq & F_RSPD_NEWBUF)) {
1010                                         MPASS(black_hole == 2);
1011                                         break;
1012                                 }
1013                                 fl_credits++;
1014                                 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1015                                         fl_cidx = 0;
1016                                 break;
1017                         default:
1018                                 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1019                                     __func__, opcode, nm_rxq);
1020                         }
1021                         break;
1022
1023                 case X_RSPD_TYPE_INTR:
1024                         /* Not equipped to handle forwarded interrupts. */
1025                         panic("%s: netmap queue received interrupt for iq %u\n",
1026                             __func__, lq);
1027
1028                 default:
1029                         panic("%s: illegal response type %d on nm_rxq %p",
1030                             __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1031                 }
1032
1033                 d++;
1034                 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1035                         nm_rxq->iq_cidx = 0;
1036                         d = &nm_rxq->iq_desc[0];
1037                         nm_rxq->iq_gen ^= F_RSPD_GEN;
1038                 }
1039
1040                 if (__predict_false(++nframes == rx_nframes) && !black_hole) {
1041                         atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1042                         netmap_rx_irq(ifp, nm_rxq->nid, &work);
1043                         nframes = 0;
1044                 }
1045
1046                 if (__predict_false(++ndesc == rx_ndesc)) {
1047                         if (black_hole && fl_credits >= 8) {
1048                                 fl_credits /= 8;
1049                                 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1050                                     nm_rxq->fl_sidx);
1051                                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1052                                     nm_rxq->fl_db_val | V_PIDX(fl_credits));
1053                                 fl_credits = fl_cidx & 7;
1054                         }
1055                         t4_write_reg(sc, sc->sge_gts_reg,
1056                             V_CIDXINC(ndesc) |
1057                             V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1058                             V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1059                         ndesc = 0;
1060                 }
1061         }
1062
1063         atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1064         if (black_hole) {
1065                 fl_credits /= 8;
1066                 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1067                 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1068                     nm_rxq->fl_db_val | V_PIDX(fl_credits));
1069         } else if (nframes > 0)
1070                 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1071
1072         t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1073             V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1074             V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
1075 }
1076 #endif