2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
37 #include <sys/eventhandler.h>
40 #include <sys/module.h>
41 #include <sys/selinfo.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <machine/bus.h>
45 #include <net/ethernet.h>
47 #include <net/if_media.h>
48 #include <net/if_var.h>
49 #include <net/if_clone.h>
50 #include <net/if_types.h>
51 #include <net/netmap.h>
52 #include <dev/netmap/netmap_kern.h>
54 #include "common/common.h"
55 #include "common/t4_regs.h"
56 #include "common/t4_regs_values.h"
58 extern int fl_pad; /* XXXNM */
61 * 0 = normal netmap rx
63 * 2 = supermassive black hole (buffer packing enabled)
66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
67 "Sink incoming packets.");
70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN,
75 &rx_nframes, 0, "max # of frames received before waking up netmap rx.");
77 int holdoff_tmr_idx = 2;
78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
83 * -1: no congestion feedback (not recommended).
84 * 0: backpressure the channel instead of dropping packets right away.
85 * 1: no backpressure, drop packets for the congested queue immediately.
87 static int nm_cong_drop = 1;
88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RDTUN,
90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop");
93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN,
94 &starve_fl, 0, "Don't ring fl db for netmap rx queues.");
97 * Try to process tx credits in bulk. This may cause a delay in the return of
98 * tx credits and is suitable for bursty or non-stop tx only.
100 int lazy_tx_credit_flush = 1;
101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN,
102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues.");
105 * Split the netmap rx queues into two groups that populate separate halves of
106 * the RSS indirection table. This allows filters with hashmask to steer to a
107 * particular group of queues.
109 static int nm_split_rss = 0;
110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN,
111 &nm_split_rss, 0, "Split the netmap rx queues into two groups.");
114 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
118 struct adapter *sc = vi->pi->adapter;
119 struct sge_params *sp = &sc->params.sge;
120 struct netmap_adapter *na = NA(vi->ifp);
124 MPASS(nm_rxq->iq_desc != NULL);
125 MPASS(nm_rxq->fl_desc != NULL);
127 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
128 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
130 bzero(&c, sizeof(c));
131 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
132 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
134 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
136 MPASS(!forwarding_intr_to_fwq(sc));
137 KASSERT(nm_rxq->intr_idx < sc->intr_count,
138 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
139 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
140 c.type_to_iqandstindex = htobe32(v |
141 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
142 V_FW_IQ_CMD_VIID(vi->viid) |
143 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
144 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
145 F_FW_IQ_CMD_IQGTSMODE |
146 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
147 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
148 c.iqsize = htobe16(vi->qsize_rxq);
149 c.iqaddr = htobe64(nm_rxq->iq_ba);
151 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
152 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
153 F_FW_IQ_CMD_FL0CONGEN);
155 c.iqns_to_fl0congen |=
156 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
157 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
158 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
159 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
160 c.fl0dcaen_to_fl0cidxfthresh =
161 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
162 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
163 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
164 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
165 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
166 c.fl0addr = htobe64(nm_rxq->fl_ba);
168 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
170 device_printf(sc->dev,
171 "failed to create netmap ingress queue: %d\n", rc);
176 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
177 nm_rxq->iq_gen = F_RSPD_GEN;
178 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
179 nm_rxq->iq_abs_id = be16toh(c.physiqid);
180 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
181 if (cntxt_id >= sc->sge.niq) {
182 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
183 __func__, cntxt_id, sc->sge.niq - 1);
185 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
187 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
188 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
189 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
190 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
191 if (cntxt_id >= sc->sge.neq) {
192 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
193 __func__, cntxt_id, sc->sge.neq - 1);
195 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
197 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
198 sc->chip_params->sge_fl_db;
200 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
203 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
204 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
205 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
206 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
207 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
208 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
213 for (i = 0; i < 4; i++) {
215 val |= 1 << (i << 2);
219 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
221 /* report error but carry on */
222 device_printf(sc->dev,
223 "failed to set congestion manager context for "
224 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
228 t4_write_reg(sc, sc->sge_gts_reg,
229 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
230 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
236 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
238 struct adapter *sc = vi->pi->adapter;
241 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
242 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
244 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
245 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
246 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
251 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
255 struct adapter *sc = vi->pi->adapter;
256 struct netmap_adapter *na = NA(vi->ifp);
257 struct fw_eq_eth_cmd c;
260 MPASS(nm_txq->desc != NULL);
262 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
263 bzero(nm_txq->desc, len);
265 bzero(&c, sizeof(c));
266 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
267 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
268 V_FW_EQ_ETH_CMD_VFN(0));
269 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
270 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
271 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
272 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
274 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
275 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
276 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
278 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
279 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
280 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
281 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
282 c.eqaddr = htobe64(nm_txq->ba);
284 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
286 device_printf(vi->dev,
287 "failed to create netmap egress queue: %d\n", rc);
291 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
292 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
293 if (cntxt_id >= sc->sge.neq)
294 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
295 cntxt_id, sc->sge.neq - 1);
296 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
298 nm_txq->pidx = nm_txq->cidx = 0;
299 MPASS(nm_txq->sidx == na->num_tx_desc);
300 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
302 nm_txq->doorbells = sc->doorbells;
303 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
304 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
305 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
306 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
307 uint32_t mask = (1 << s_qpp) - 1;
308 volatile uint8_t *udb;
310 udb = sc->udbs_base + UDBS_DB_OFFSET;
311 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
312 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
313 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
314 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
316 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
319 nm_txq->udb = (volatile void *)udb;
326 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
328 struct adapter *sc = vi->pi->adapter;
331 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
333 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
334 nm_txq->cntxt_id, rc);
335 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
340 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
341 struct netmap_adapter *na)
343 struct netmap_slot *slot;
344 struct netmap_kring *kring;
345 struct sge_nm_rxq *nm_rxq;
346 struct sge_nm_txq *nm_txq;
347 int rc, i, j, hwidx, defq, nrssq;
348 struct hw_buf_info *hwb;
350 ASSERT_SYNCHRONIZED_OP(sc);
352 if ((vi->flags & VI_INIT_DONE) == 0 ||
353 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
356 hwb = &sc->sge.hw_buf_info[0];
357 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
358 if (hwb->size == NETMAP_BUF_SIZE(na))
361 if (i >= SGE_FLBUF_SIZES) {
362 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
363 NETMAP_BUF_SIZE(na));
368 /* Must set caps before calling netmap_reset */
369 nm_set_native_flags(na);
371 for_each_nm_rxq(vi, i, nm_rxq) {
372 kring = na->rx_rings[nm_rxq->nid];
373 if (!nm_kring_pending_on(kring) ||
374 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
377 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop));
378 nm_rxq->fl_hwidx = hwidx;
379 slot = netmap_reset(na, NR_RX, i, 0);
380 MPASS(slot != NULL); /* XXXNM: error check, not assert */
382 /* We deal with 8 bufs at a time */
383 MPASS((na->num_rx_desc & 7) == 0);
384 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
385 for (j = 0; j < nm_rxq->fl_sidx; j++) {
388 PNMB(na, &slot[j], &ba);
390 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
392 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
394 j /= 8; /* driver pidx to hardware pidx */
396 t4_write_reg(sc, sc->sge_kdoorbell_reg,
397 nm_rxq->fl_db_val | V_PIDX(j));
399 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
402 for_each_nm_txq(vi, i, nm_txq) {
403 kring = na->tx_rings[nm_txq->nid];
404 if (!nm_kring_pending_on(kring) ||
405 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
408 alloc_nm_txq_hwq(vi, nm_txq);
409 slot = netmap_reset(na, NR_TX, i, 0);
410 MPASS(slot != NULL); /* XXXNM: error check, not assert */
413 if (vi->nm_rss == NULL) {
414 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
418 MPASS(vi->nnmrxq > 0);
419 if (nm_split_rss == 0 || vi->nnmrxq == 1) {
420 for (i = 0; i < vi->rss_size;) {
421 for_each_nm_rxq(vi, j, nm_rxq) {
422 vi->nm_rss[i++] = nm_rxq->iq_abs_id;
423 if (i == vi->rss_size)
427 defq = vi->nm_rss[0];
429 /* We have multiple queues and we want to split the table. */
430 MPASS(nm_split_rss != 0);
431 MPASS(vi->nnmrxq > 1);
433 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq];
435 if (vi->nnmrxq & 1) {
437 * Odd number of queues. The first rxq is designated the
438 * default queue, the rest are split evenly.
440 defq = nm_rxq->iq_abs_id;
445 * Even number of queues split into two halves. The
446 * first rxq in one of the halves is designated the
450 /* First rxq in the first half. */
451 defq = nm_rxq->iq_abs_id;
453 /* First rxq in the second half. */
454 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id;
459 while (i < vi->rss_size / 2) {
460 for (j = 0; j < nrssq / 2; j++) {
461 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
462 if (i == vi->rss_size / 2)
466 while (i < vi->rss_size) {
467 for (j = nrssq / 2; j < nrssq; j++) {
468 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
469 if (i == vi->rss_size)
474 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
475 vi->nm_rss, vi->rss_size);
477 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
479 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
481 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc);
487 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp,
488 struct netmap_adapter *na)
490 struct netmap_kring *kring;
492 struct sge_nm_txq *nm_txq;
493 struct sge_nm_rxq *nm_rxq;
495 ASSERT_SYNCHRONIZED_OP(sc);
497 if (!nm_netmap_on(na))
500 if ((vi->flags & VI_INIT_DONE) == 0)
503 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
504 vi->rss, vi->rss_size);
506 if_printf(ifp, "failed to restore RSS config: %d\n", rc);
507 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0);
509 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc);
510 nm_clear_native_flags(na);
512 for_each_nm_txq(vi, i, nm_txq) {
513 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
515 kring = na->tx_rings[nm_txq->nid];
516 if (!nm_kring_pending_off(kring) ||
517 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
520 /* Wait for hw pidx to catch up ... */
521 while (be16toh(nm_txq->pidx) != spg->pidx)
524 /* ... and then for the cidx. */
525 while (spg->pidx != spg->cidx)
528 free_nm_txq_hwq(vi, nm_txq);
530 for_each_nm_rxq(vi, i, nm_rxq) {
531 kring = na->rx_rings[nm_rxq->nid];
532 if (!nm_kring_pending_off(kring) ||
533 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
536 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
539 free_nm_rxq_hwq(vi, nm_rxq);
546 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
548 struct ifnet *ifp = na->ifp;
549 struct vi_info *vi = ifp->if_softc;
550 struct adapter *sc = vi->pi->adapter;
553 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg");
557 rc = cxgbe_netmap_on(sc, vi, ifp, na);
559 rc = cxgbe_netmap_off(sc, vi, ifp, na);
560 end_synchronized_op(sc, 0);
565 /* How many packets can a single type1 WR carry in n descriptors */
567 ndesc_to_npkt(const int n)
570 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
574 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
576 /* Space (in descriptors) needed for a type1 WR that carries n packets */
578 npkt_to_ndesc(const int n)
581 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
583 return ((n + 2) / 2);
586 /* Space (in 16B units) needed for a type1 WR that carries n packets */
588 npkt_to_len16(const int n)
591 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
596 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
599 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
602 u_int db = nm_txq->doorbells;
604 MPASS(nm_txq->pidx != nm_txq->dbidx);
606 n = NMIDXDIFF(nm_txq, dbidx);
608 clrbit(&db, DOORBELL_WCWR);
611 switch (ffs(db) - 1) {
613 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
616 case DOORBELL_WCWR: {
617 volatile uint64_t *dst, *src;
620 * Queues whose 128B doorbell segment fits in the page do not
621 * use relative qid (udb_qid is always 0). Only queues with
622 * doorbell segments can do WCWR.
624 KASSERT(nm_txq->udb_qid == 0 && n == 1,
625 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
626 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
628 dst = (volatile void *)((uintptr_t)nm_txq->udb +
629 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
630 src = (void *)&nm_txq->desc[nm_txq->dbidx];
631 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
638 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
643 t4_write_reg(sc, sc->sge_kdoorbell_reg,
644 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
647 nm_txq->dbidx = nm_txq->pidx;
651 * Write work requests to send 'npkt' frames and ring the doorbell to send them
652 * on their way. No need to check for wraparound.
655 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
656 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
658 struct netmap_ring *ring = kring->ring;
659 struct netmap_slot *slot;
660 const u_int lim = kring->nkr_num_slots - 1;
661 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
664 struct cpl_tx_pkt_core *cpl;
665 struct ulptx_sgl *usgl;
669 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
672 wr = (void *)&nm_txq->desc[nm_txq->pidx];
673 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
674 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
678 cpl = (void *)(wr + 1);
680 for (i = 0; i < n; i++) {
681 slot = &ring->slot[kring->nr_hwcur];
682 PNMB(kring->na, slot, &ba);
685 cpl->ctrl0 = nm_txq->cpl_ctrl0;
687 cpl->len = htobe16(slot->len);
689 * netmap(4) says "netmap does not use features such as
690 * checksum offloading, TCP segmentation offloading,
691 * encryption, VLAN encapsulation/decapsulation, etc."
693 * So the ncxl interfaces have tx hardware checksumming
694 * disabled by default. But you can override netmap by
695 * enabling IFCAP_TXCSUM on the interface manully.
697 cpl->ctrl1 = txcsum ? 0 :
698 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
700 usgl = (void *)(cpl + 1);
701 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
703 usgl->len0 = htobe32(slot->len);
704 usgl->addr0 = htobe64(ba);
706 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
707 cpl = (void *)(usgl + 1);
708 MPASS(slot->len + len <= UINT16_MAX);
710 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
712 wr->plen = htobe16(len);
715 nm_txq->pidx += npkt_to_ndesc(n);
716 MPASS(nm_txq->pidx <= nm_txq->sidx);
717 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
719 * This routine doesn't know how to write WRs that wrap
720 * around. Make sure it wasn't asked to.
726 if (npkt == 0 && npkt_remaining == 0) {
728 if (lazy_tx_credit_flush == 0) {
729 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
731 nm_txq->equeqidx = nm_txq->pidx;
732 nm_txq->equiqidx = nm_txq->pidx;
734 ring_nm_txq_db(sc, nm_txq);
738 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
739 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
741 nm_txq->equeqidx = nm_txq->pidx;
742 nm_txq->equiqidx = nm_txq->pidx;
743 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
744 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
745 nm_txq->equeqidx = nm_txq->pidx;
747 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
748 ring_nm_txq_db(sc, nm_txq);
751 /* Will get called again. */
752 MPASS(npkt_remaining);
755 /* How many contiguous free descriptors starting at pidx */
757 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
760 if (nm_txq->cidx > nm_txq->pidx)
761 return (nm_txq->cidx - nm_txq->pidx - 1);
762 else if (nm_txq->cidx > 0)
763 return (nm_txq->sidx - nm_txq->pidx);
765 return (nm_txq->sidx - nm_txq->pidx - 1);
769 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
771 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
772 uint16_t hw_cidx = spg->cidx; /* snapshot */
773 struct fw_eth_tx_pkts_wr *wr;
776 hw_cidx = be16toh(hw_cidx);
778 while (nm_txq->cidx != hw_cidx) {
779 wr = (void *)&nm_txq->desc[nm_txq->cidx];
781 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
782 MPASS(wr->type == 1);
783 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
786 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
789 * We never sent a WR that wrapped around so the credits coming
790 * back, WR by WR, should never cause the cidx to wrap around
793 MPASS(nm_txq->cidx <= nm_txq->sidx);
794 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
802 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
804 struct netmap_adapter *na = kring->na;
805 struct ifnet *ifp = na->ifp;
806 struct vi_info *vi = ifp->if_softc;
807 struct adapter *sc = vi->pi->adapter;
808 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
809 const u_int head = kring->rhead;
811 int n, d, npkt_remaining, ndesc_remaining, txcsum;
814 * Tx was at kring->nr_hwcur last time around and now we need to advance
815 * to kring->rhead. Note that the driver's pidx moves independent of
816 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
817 * between descriptors and frames isn't 1:1).
820 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
821 kring->nkr_num_slots - kring->nr_hwcur + head;
822 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
823 while (npkt_remaining) {
824 reclaimed += reclaim_nm_tx_desc(nm_txq);
825 ndesc_remaining = contiguous_ndesc_available(nm_txq);
826 /* Can't run out of descriptors with packets still remaining */
827 MPASS(ndesc_remaining > 0);
829 /* # of desc needed to tx all remaining packets */
830 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
831 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
832 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
834 if (d <= ndesc_remaining)
837 /* Can't send all, calculate how many can be sent */
838 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
839 MAX_NPKT_IN_TYPE1_WR;
840 if (ndesc_remaining % SGE_MAX_WR_NDESC)
841 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
844 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
846 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
848 MPASS(npkt_remaining == 0);
849 MPASS(kring->nr_hwcur == head);
850 MPASS(nm_txq->dbidx == nm_txq->pidx);
853 * Second part: reclaim buffers for completed transmissions.
855 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
856 reclaimed += reclaim_nm_tx_desc(nm_txq);
857 kring->nr_hwtail += reclaimed;
858 if (kring->nr_hwtail >= kring->nkr_num_slots)
859 kring->nr_hwtail -= kring->nkr_num_slots;
866 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
868 struct netmap_adapter *na = kring->na;
869 struct netmap_ring *ring = kring->ring;
870 struct ifnet *ifp = na->ifp;
871 struct vi_info *vi = ifp->if_softc;
872 struct adapter *sc = vi->pi->adapter;
873 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
874 u_int const head = kring->rhead;
876 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
879 return (0); /* No updates ever. */
881 if (netmap_no_pendintr || force_update) {
882 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
883 kring->nr_kflags &= ~NKR_PENDINTR;
886 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
888 t4_write_reg(sc, sc->sge_kdoorbell_reg,
889 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
890 nm_rxq->fl_db_saved = 0;
893 /* Userspace done with buffers from kring->nr_hwcur to head */
894 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
895 kring->nkr_num_slots - kring->nr_hwcur + head;
898 u_int fl_pidx = nm_rxq->fl_pidx;
899 struct netmap_slot *slot = &ring->slot[fl_pidx];
901 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
904 * We always deal with 8 buffers at a time. We must have
905 * stopped at an 8B boundary (fl_pidx) last time around and we
906 * must have a multiple of 8B buffers to give to the freelist.
908 MPASS((fl_pidx & 7) == 0);
911 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
912 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
915 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
918 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
919 slot->flags &= ~NS_BUF_CHANGED;
920 MPASS(fl_pidx <= nm_rxq->fl_sidx);
923 if (fl_pidx == nm_rxq->fl_sidx) {
925 slot = &ring->slot[0];
927 if (++dbinc == 8 && n >= 32) {
930 nm_rxq->fl_db_saved += dbinc;
932 t4_write_reg(sc, sc->sge_kdoorbell_reg,
933 nm_rxq->fl_db_val | V_PIDX(dbinc));
938 MPASS(nm_rxq->fl_pidx == fl_pidx);
943 nm_rxq->fl_db_saved += dbinc;
945 t4_write_reg(sc, sc->sge_kdoorbell_reg,
946 nm_rxq->fl_db_val | V_PIDX(dbinc));
955 cxgbe_nm_attach(struct vi_info *vi)
957 struct port_info *pi;
959 struct netmap_adapter na;
961 MPASS(vi->nnmrxq > 0);
962 MPASS(vi->ifp != NULL);
967 bzero(&na, sizeof(na));
970 na.na_flags = NAF_BDG_MAYSLEEP;
972 /* Netmap doesn't know about the space reserved for the status page. */
973 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
976 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
977 * num_rx_desc is based on the number of buffers that can be held in the
978 * freelist, and not the number of entries in the iq. (These two are
979 * not exactly the same due to the space taken up by the status page).
981 na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
982 na.nm_txsync = cxgbe_netmap_txsync;
983 na.nm_rxsync = cxgbe_netmap_rxsync;
984 na.nm_register = cxgbe_netmap_reg;
985 na.num_tx_rings = vi->nnmtxq;
986 na.num_rx_rings = vi->nnmrxq;
987 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
991 cxgbe_nm_detach(struct vi_info *vi)
994 MPASS(vi->nnmrxq > 0);
995 MPASS(vi->ifp != NULL);
997 netmap_detach(vi->ifp);
1000 static inline const void *
1001 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
1004 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
1006 /* data[0] is RSS header */
1007 return (&cpl->data[1]);
1011 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
1012 const struct cpl_sge_egr_update *egr)
1015 struct sge_nm_txq *nm_txq;
1017 oq = be32toh(egr->opcode_qid);
1018 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1019 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1021 netmap_tx_irq(ifp, nm_txq->nid);
1025 service_nm_rxq(struct sge_nm_rxq *nm_rxq)
1027 struct vi_info *vi = nm_rxq->vi;
1028 struct adapter *sc = vi->pi->adapter;
1029 struct ifnet *ifp = vi->ifp;
1030 struct netmap_adapter *na = NA(ifp);
1031 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
1032 struct netmap_ring *ring = kring->ring;
1033 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1038 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1039 u_int fl_credits = fl_cidx & 7;
1040 u_int ndesc = 0; /* desc processed since last cidx update */
1041 u_int nframes = 0; /* frames processed since last netmap wakeup */
1043 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1047 lq = be32toh(d->rsp.pldbuflen_qid);
1048 opcode = d->rss.opcode;
1051 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1052 case X_RSPD_TYPE_FLBUF:
1056 case X_RSPD_TYPE_CPL:
1057 MPASS(opcode < NUM_CPL_CMDS);
1062 cpl = unwrap_nm_fw6_msg(cpl);
1064 case CPL_SGE_EGR_UPDATE:
1065 handle_nm_sge_egr_update(sc, ifp, cpl);
1068 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1069 sc->params.sge.fl_pktshift;
1070 ring->slot[fl_cidx].flags = 0;
1072 if (!(lq & F_RSPD_NEWBUF)) {
1073 MPASS(black_hole == 2);
1077 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1081 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1082 __func__, opcode, nm_rxq);
1086 case X_RSPD_TYPE_INTR:
1087 /* Not equipped to handle forwarded interrupts. */
1088 panic("%s: netmap queue received interrupt for iq %u\n",
1092 panic("%s: illegal response type %d on nm_rxq %p",
1093 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1097 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1098 nm_rxq->iq_cidx = 0;
1099 d = &nm_rxq->iq_desc[0];
1100 nm_rxq->iq_gen ^= F_RSPD_GEN;
1103 if (__predict_false(++nframes == rx_nframes) && !black_hole) {
1104 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1105 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1109 if (__predict_false(++ndesc == rx_ndesc)) {
1110 if (black_hole && fl_credits >= 8) {
1112 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1114 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1115 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1116 fl_credits = fl_cidx & 7;
1118 t4_write_reg(sc, sc->sge_gts_reg,
1120 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1121 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1126 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1129 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1130 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1131 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1132 } else if (nframes > 0)
1133 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1135 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1136 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1137 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));