2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/eventhandler.h>
38 #include <sys/types.h>
40 #include <sys/selinfo.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <machine/bus.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <net/if_var.h>
48 #include <net/if_clone.h>
49 #include <net/if_types.h>
50 #include <net/netmap.h>
51 #include <dev/netmap/netmap_kern.h>
53 #include "common/common.h"
54 #include "common/t4_regs.h"
55 #include "common/t4_regs_values.h"
57 extern int fl_pad; /* XXXNM */
58 extern int spg_len; /* XXXNM */
59 extern int fl_pktshift; /* XXXNM */
61 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters");
64 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
65 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
67 int holdoff_tmr_idx = 2;
68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
69 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
71 /* netmap ifnet routines */
72 static void cxgbe_nm_init(void *);
73 static int cxgbe_nm_ioctl(struct ifnet *, unsigned long, caddr_t);
74 static int cxgbe_nm_transmit(struct ifnet *, struct mbuf *);
75 static void cxgbe_nm_qflush(struct ifnet *);
77 static int cxgbe_nm_init_synchronized(struct port_info *);
78 static int cxgbe_nm_uninit_synchronized(struct port_info *);
81 cxgbe_nm_init(void *arg)
83 struct port_info *pi = arg;
84 struct adapter *sc = pi->adapter;
86 if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nminit") != 0)
88 cxgbe_nm_init_synchronized(pi);
89 end_synchronized_op(sc, 0);
95 cxgbe_nm_init_synchronized(struct port_info *pi)
97 struct adapter *sc = pi->adapter;
98 struct ifnet *ifp = pi->nm_ifp;
101 ASSERT_SYNCHRONIZED_OP(sc);
103 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
104 return (0); /* already running */
106 if (!(sc->flags & FULL_INIT_DONE) &&
107 ((rc = adapter_full_init(sc)) != 0))
108 return (rc); /* error message displayed already */
110 if (!(pi->flags & PORT_INIT_DONE) &&
111 ((rc = port_full_init(pi)) != 0))
112 return (rc); /* error message displayed already */
114 rc = update_mac_settings(ifp, XGMAC_ALL);
116 return (rc); /* error message displayed already */
118 ifp->if_drv_flags |= IFF_DRV_RUNNING;
124 cxgbe_nm_uninit_synchronized(struct port_info *pi)
127 struct adapter *sc = pi->adapter;
129 struct ifnet *ifp = pi->nm_ifp;
131 ASSERT_SYNCHRONIZED_OP(sc);
133 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
139 cxgbe_nm_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
141 int rc = 0, mtu, flags;
142 struct port_info *pi = ifp->if_softc;
143 struct adapter *sc = pi->adapter;
144 struct ifreq *ifr = (struct ifreq *)data;
147 MPASS(pi->nm_ifp == ifp);
152 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
155 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmtu");
159 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
160 rc = update_mac_settings(ifp, XGMAC_MTU);
161 end_synchronized_op(sc, 0);
165 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nflg");
169 if (ifp->if_flags & IFF_UP) {
170 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
171 flags = pi->nmif_flags;
172 if ((ifp->if_flags ^ flags) &
173 (IFF_PROMISC | IFF_ALLMULTI)) {
174 rc = update_mac_settings(ifp,
175 XGMAC_PROMISC | XGMAC_ALLMULTI);
178 rc = cxgbe_nm_init_synchronized(pi);
179 pi->nmif_flags = ifp->if_flags;
180 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
181 rc = cxgbe_nm_uninit_synchronized(pi);
182 end_synchronized_op(sc, 0);
186 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
187 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4nmulti");
190 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
191 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
192 end_synchronized_op(sc, LOCK_HELD);
196 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
197 if (mask & IFCAP_TXCSUM) {
198 ifp->if_capenable ^= IFCAP_TXCSUM;
199 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
201 if (mask & IFCAP_TXCSUM_IPV6) {
202 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
203 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
205 if (mask & IFCAP_RXCSUM)
206 ifp->if_capenable ^= IFCAP_RXCSUM;
207 if (mask & IFCAP_RXCSUM_IPV6)
208 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
213 ifmedia_ioctl(ifp, ifr, &pi->nm_media, cmd);
217 rc = ether_ioctl(ifp, cmd, data);
224 cxgbe_nm_transmit(struct ifnet *ifp, struct mbuf *m)
232 cxgbe_nm_qflush(struct ifnet *ifp)
239 alloc_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int cong)
243 struct adapter *sc = pi->adapter;
244 struct netmap_adapter *na = NA(pi->nm_ifp);
248 MPASS(nm_rxq->iq_desc != NULL);
249 MPASS(nm_rxq->fl_desc != NULL);
251 bzero(nm_rxq->iq_desc, pi->qsize_rxq * IQ_ESIZE);
252 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + spg_len);
254 bzero(&c, sizeof(c));
255 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
256 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
258 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
260 if (pi->flags & INTR_NM_RXQ) {
261 KASSERT(nm_rxq->intr_idx < sc->intr_count,
262 ("%s: invalid direct intr_idx %d", __func__,
264 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
266 CXGBE_UNIMPLEMENTED(__func__); /* XXXNM: needs review */
267 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx) |
270 c.type_to_iqandstindex = htobe32(v |
271 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
272 V_FW_IQ_CMD_VIID(pi->nm_viid) |
273 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
274 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
275 F_FW_IQ_CMD_IQGTSMODE |
276 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
277 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
278 c.iqsize = htobe16(pi->qsize_rxq);
279 c.iqaddr = htobe64(nm_rxq->iq_ba);
281 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
282 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
283 F_FW_IQ_CMD_FL0CONGEN);
285 c.iqns_to_fl0congen |=
286 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
287 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
288 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0));
289 c.fl0dcaen_to_fl0cidxfthresh =
290 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) |
291 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
292 c.fl0size = htobe16(na->num_rx_desc / 8 + spg_len / EQ_ESIZE);
293 c.fl0addr = htobe64(nm_rxq->fl_ba);
295 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
297 device_printf(sc->dev,
298 "failed to create netmap ingress queue: %d\n", rc);
303 MPASS(nm_rxq->iq_sidx == pi->qsize_rxq - spg_len / IQ_ESIZE);
304 nm_rxq->iq_gen = F_RSPD_GEN;
305 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
306 nm_rxq->iq_abs_id = be16toh(c.physiqid);
307 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
308 if (cntxt_id >= sc->sge.niq) {
309 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
310 __func__, cntxt_id, sc->sge.niq - 1);
312 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
314 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
315 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
316 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
317 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
318 if (cntxt_id >= sc->sge.neq) {
319 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
320 __func__, cntxt_id, sc->sge.neq - 1);
322 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
324 nm_rxq->fl_db_val = F_DBPRIO | V_QID(nm_rxq->fl_cntxt_id) | V_PIDX(0);
326 nm_rxq->fl_db_val |= F_DBTYPE;
328 if (is_t5(sc) && cong >= 0) {
331 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
332 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
333 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
334 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
335 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
336 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
341 for (i = 0; i < 4; i++) {
343 val |= 1 << (i << 2);
347 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
349 /* report error but carry on */
350 device_printf(sc->dev,
351 "failed to set congestion manager context for "
352 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
356 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
357 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
358 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
364 free_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
366 struct adapter *sc = pi->adapter;
369 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
370 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
372 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
373 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
378 alloc_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
382 struct adapter *sc = pi->adapter;
383 struct netmap_adapter *na = NA(pi->nm_ifp);
384 struct fw_eq_eth_cmd c;
387 MPASS(nm_txq->desc != NULL);
389 len = na->num_tx_desc * EQ_ESIZE + spg_len;
390 bzero(nm_txq->desc, len);
392 bzero(&c, sizeof(c));
393 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
394 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
395 V_FW_EQ_ETH_CMD_VFN(0));
396 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
397 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
398 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUEQE |
399 V_FW_EQ_ETH_CMD_VIID(pi->nm_viid));
401 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
402 V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
403 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
404 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
405 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
406 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
407 c.eqaddr = htobe64(nm_txq->ba);
409 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
411 device_printf(pi->dev,
412 "failed to create netmap egress queue: %d\n", rc);
416 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
417 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
418 if (cntxt_id >= sc->sge.neq)
419 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
420 cntxt_id, sc->sge.neq - 1);
421 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
423 nm_txq->pidx = nm_txq->cidx = 0;
424 MPASS(nm_txq->sidx == na->num_tx_desc);
425 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
427 nm_txq->doorbells = sc->doorbells;
428 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
429 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
430 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
431 uint32_t s_qpp = sc->sge.eq_s_qpp;
432 uint32_t mask = (1 << s_qpp) - 1;
433 volatile uint8_t *udb;
435 udb = sc->udbs_base + UDBS_DB_OFFSET;
436 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
437 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
438 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
439 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
441 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
444 nm_txq->udb = (volatile void *)udb;
451 free_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
453 struct adapter *sc = pi->adapter;
456 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
458 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
459 nm_txq->cntxt_id, rc);
464 cxgbe_netmap_on(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
465 struct netmap_adapter *na)
467 struct netmap_slot *slot;
468 struct sge_nm_rxq *nm_rxq;
469 struct sge_nm_txq *nm_txq;
471 struct hw_buf_info *hwb;
474 ASSERT_SYNCHRONIZED_OP(sc);
476 if ((pi->flags & PORT_INIT_DONE) == 0 ||
477 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
480 hwb = &sc->sge.hw_buf_info[0];
481 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
482 if (hwb->size == NETMAP_BUF_SIZE(na))
485 if (i >= SGE_FLBUF_SIZES) {
486 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
487 NETMAP_BUF_SIZE(na));
492 /* Must set caps before calling netmap_reset */
493 nm_set_native_flags(na);
495 for_each_nm_rxq(pi, i, nm_rxq) {
496 alloc_nm_rxq_hwq(pi, nm_rxq, tnl_cong(pi));
497 nm_rxq->fl_hwidx = hwidx;
498 slot = netmap_reset(na, NR_RX, i, 0);
499 MPASS(slot != NULL); /* XXXNM: error check, not assert */
501 /* We deal with 8 bufs at a time */
502 MPASS((na->num_rx_desc & 7) == 0);
503 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
504 for (j = 0; j < nm_rxq->fl_sidx; j++) {
507 PNMB(na, &slot[j], &ba);
509 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
511 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
513 j /= 8; /* driver pidx to hardware pidx */
515 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
516 nm_rxq->fl_db_val | V_PIDX(j));
519 for_each_nm_txq(pi, i, nm_txq) {
520 alloc_nm_txq_hwq(pi, nm_txq);
521 slot = netmap_reset(na, NR_TX, i, 0);
522 MPASS(slot != NULL); /* XXXNM: error check, not assert */
525 rss = malloc(pi->nm_rss_size * sizeof (*rss), M_CXGBE, M_ZERO |
527 for (i = 0; i < pi->nm_rss_size;) {
528 for_each_nm_rxq(pi, j, nm_rxq) {
529 rss[i++] = nm_rxq->iq_abs_id;
530 if (i == pi->nm_rss_size)
534 rc = -t4_config_rss_range(sc, sc->mbox, pi->nm_viid, 0, pi->nm_rss_size,
535 rss, pi->nm_rss_size);
537 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
540 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, true, true);
542 if_printf(ifp, "netmap enable_vi failed: %d\n", rc);
548 cxgbe_netmap_off(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
549 struct netmap_adapter *na)
552 struct sge_nm_txq *nm_txq;
553 struct sge_nm_rxq *nm_rxq;
555 ASSERT_SYNCHRONIZED_OP(sc);
557 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, false, false);
559 if_printf(ifp, "netmap disable_vi failed: %d\n", rc);
560 nm_clear_native_flags(na);
562 for_each_nm_txq(pi, i, nm_txq) {
563 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
565 /* Wait for hw pidx to catch up ... */
566 while (be16toh(nm_txq->pidx) != spg->pidx)
569 /* ... and then for the cidx. */
570 while (spg->pidx != spg->cidx)
573 free_nm_txq_hwq(pi, nm_txq);
575 for_each_nm_rxq(pi, i, nm_rxq) {
576 free_nm_rxq_hwq(pi, nm_rxq);
583 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
585 struct ifnet *ifp = na->ifp;
586 struct port_info *pi = ifp->if_softc;
587 struct adapter *sc = pi->adapter;
590 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmreg");
594 rc = cxgbe_netmap_on(sc, pi, ifp, na);
596 rc = cxgbe_netmap_off(sc, pi, ifp, na);
597 end_synchronized_op(sc, 0);
602 /* How many packets can a single type1 WR carry in n descriptors */
604 ndesc_to_npkt(const int n)
607 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
611 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
613 /* Space (in descriptors) needed for a type1 WR that carries n packets */
615 npkt_to_ndesc(const int n)
618 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
620 return ((n + 2) / 2);
623 /* Space (in 16B units) needed for a type1 WR that carries n packets */
625 npkt_to_len16(const int n)
628 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
633 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
636 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
639 u_int db = nm_txq->doorbells;
641 MPASS(nm_txq->pidx != nm_txq->dbidx);
643 n = NMIDXDIFF(nm_txq, dbidx);
645 clrbit(&db, DOORBELL_WCWR);
648 switch (ffs(db) - 1) {
650 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
653 case DOORBELL_WCWR: {
654 volatile uint64_t *dst, *src;
657 * Queues whose 128B doorbell segment fits in the page do not
658 * use relative qid (udb_qid is always 0). Only queues with
659 * doorbell segments can do WCWR.
661 KASSERT(nm_txq->udb_qid == 0 && n == 1,
662 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
663 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
665 dst = (volatile void *)((uintptr_t)nm_txq->udb +
666 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
667 src = (void *)&nm_txq->desc[nm_txq->dbidx];
668 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
675 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
680 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
681 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
684 nm_txq->dbidx = nm_txq->pidx;
687 int lazy_tx_credit_flush = 1;
690 * Write work requests to send 'npkt' frames and ring the doorbell to send them
691 * on their way. No need to check for wraparound.
694 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
695 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
697 struct netmap_ring *ring = kring->ring;
698 struct netmap_slot *slot;
699 const u_int lim = kring->nkr_num_slots - 1;
700 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
703 struct cpl_tx_pkt_core *cpl;
704 struct ulptx_sgl *usgl;
708 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
711 wr = (void *)&nm_txq->desc[nm_txq->pidx];
712 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
713 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
717 cpl = (void *)(wr + 1);
719 for (i = 0; i < n; i++) {
720 slot = &ring->slot[kring->nr_hwcur];
721 PNMB(kring->na, slot, &ba);
724 cpl->ctrl0 = nm_txq->cpl_ctrl0;
726 cpl->len = htobe16(slot->len);
728 * netmap(4) says "netmap does not use features such as
729 * checksum offloading, TCP segmentation offloading,
730 * encryption, VLAN encapsulation/decapsulation, etc."
732 * So the ncxl interfaces have tx hardware checksumming
733 * disabled by default. But you can override netmap by
734 * enabling IFCAP_TXCSUM on the interface manully.
736 cpl->ctrl1 = txcsum ? 0 :
737 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
739 usgl = (void *)(cpl + 1);
740 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
742 usgl->len0 = htobe32(slot->len);
743 usgl->addr0 = htobe64(ba);
745 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
746 cpl = (void *)(usgl + 1);
747 MPASS(slot->len + len <= UINT16_MAX);
749 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
751 wr->plen = htobe16(len);
754 nm_txq->pidx += npkt_to_ndesc(n);
755 MPASS(nm_txq->pidx <= nm_txq->sidx);
756 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
758 * This routine doesn't know how to write WRs that wrap
759 * around. Make sure it wasn't asked to.
765 if (npkt == 0 && npkt_remaining == 0) {
767 if (lazy_tx_credit_flush == 0) {
768 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
770 nm_txq->equeqidx = nm_txq->pidx;
771 nm_txq->equiqidx = nm_txq->pidx;
773 ring_nm_txq_db(sc, nm_txq);
777 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
778 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
780 nm_txq->equeqidx = nm_txq->pidx;
781 nm_txq->equiqidx = nm_txq->pidx;
782 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
783 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
784 nm_txq->equeqidx = nm_txq->pidx;
786 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
787 ring_nm_txq_db(sc, nm_txq);
790 /* Will get called again. */
791 MPASS(npkt_remaining);
794 /* How many contiguous free descriptors starting at pidx */
796 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
799 if (nm_txq->cidx > nm_txq->pidx)
800 return (nm_txq->cidx - nm_txq->pidx - 1);
801 else if (nm_txq->cidx > 0)
802 return (nm_txq->sidx - nm_txq->pidx);
804 return (nm_txq->sidx - nm_txq->pidx - 1);
808 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
810 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
811 uint16_t hw_cidx = spg->cidx; /* snapshot */
812 struct fw_eth_tx_pkts_wr *wr;
815 hw_cidx = be16toh(hw_cidx);
817 while (nm_txq->cidx != hw_cidx) {
818 wr = (void *)&nm_txq->desc[nm_txq->cidx];
820 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
821 MPASS(wr->type == 1);
822 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
825 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
828 * We never sent a WR that wrapped around so the credits coming
829 * back, WR by WR, should never cause the cidx to wrap around
832 MPASS(nm_txq->cidx <= nm_txq->sidx);
833 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
841 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
843 struct netmap_adapter *na = kring->na;
844 struct ifnet *ifp = na->ifp;
845 struct port_info *pi = ifp->if_softc;
846 struct adapter *sc = pi->adapter;
847 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[pi->first_nm_txq + kring->ring_id];
848 const u_int head = kring->rhead;
850 int n, d, npkt_remaining, ndesc_remaining, txcsum;
853 * Tx was at kring->nr_hwcur last time around and now we need to advance
854 * to kring->rhead. Note that the driver's pidx moves independent of
855 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
856 * between descriptors and frames isn't 1:1).
859 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
860 kring->nkr_num_slots - kring->nr_hwcur + head;
861 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
862 while (npkt_remaining) {
863 reclaimed += reclaim_nm_tx_desc(nm_txq);
864 ndesc_remaining = contiguous_ndesc_available(nm_txq);
865 /* Can't run out of descriptors with packets still remaining */
866 MPASS(ndesc_remaining > 0);
868 /* # of desc needed to tx all remaining packets */
869 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
870 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
871 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
873 if (d <= ndesc_remaining)
876 /* Can't send all, calculate how many can be sent */
877 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
878 MAX_NPKT_IN_TYPE1_WR;
879 if (ndesc_remaining % SGE_MAX_WR_NDESC)
880 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
883 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
885 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
887 MPASS(npkt_remaining == 0);
888 MPASS(kring->nr_hwcur == head);
889 MPASS(nm_txq->dbidx == nm_txq->pidx);
892 * Second part: reclaim buffers for completed transmissions.
894 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
895 reclaimed += reclaim_nm_tx_desc(nm_txq);
896 kring->nr_hwtail += reclaimed;
897 if (kring->nr_hwtail >= kring->nkr_num_slots)
898 kring->nr_hwtail -= kring->nkr_num_slots;
901 nm_txsync_finalize(kring);
907 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
909 struct netmap_adapter *na = kring->na;
910 struct netmap_ring *ring = kring->ring;
911 struct ifnet *ifp = na->ifp;
912 struct port_info *pi = ifp->if_softc;
913 struct adapter *sc = pi->adapter;
914 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[pi->first_nm_rxq + kring->ring_id];
915 u_int const head = nm_rxsync_prologue(kring);
917 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
919 if (netmap_no_pendintr || force_update) {
920 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
921 kring->nr_kflags &= ~NKR_PENDINTR;
924 /* Userspace done with buffers from kring->nr_hwcur to head */
925 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
926 kring->nkr_num_slots - kring->nr_hwcur + head;
929 u_int fl_pidx = nm_rxq->fl_pidx;
930 struct netmap_slot *slot = &ring->slot[fl_pidx];
932 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
935 * We always deal with 8 buffers at a time. We must have
936 * stopped at an 8B boundary (fl_pidx) last time around and we
937 * must have a multiple of 8B buffers to give to the freelist.
939 MPASS((fl_pidx & 7) == 0);
942 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
943 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
946 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
949 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
950 slot->flags &= ~NS_BUF_CHANGED;
951 MPASS(fl_pidx <= nm_rxq->fl_sidx);
954 if (fl_pidx == nm_rxq->fl_sidx) {
956 slot = &ring->slot[0];
958 if (++dbinc == 8 && n >= 32) {
960 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
961 nm_rxq->fl_db_val | V_PIDX(dbinc));
965 MPASS(nm_rxq->fl_pidx == fl_pidx);
969 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
970 nm_rxq->fl_db_val | V_PIDX(dbinc));
974 nm_rxsync_finalize(kring);
980 * Create an ifnet solely for netmap use and register it with the kernel.
983 create_netmap_ifnet(struct port_info *pi)
985 struct adapter *sc = pi->adapter;
986 struct netmap_adapter na;
988 device_t dev = pi->dev;
989 uint8_t mac[ETHER_ADDR_LEN];
992 if (pi->nnmtxq <= 0 || pi->nnmrxq <= 0)
994 MPASS(pi->nm_ifp == NULL);
997 * Allocate a virtual interface exclusively for netmap use. Give it the
998 * MAC address normally reserved for use by a TOE interface. (The TOE
999 * driver on FreeBSD doesn't use it).
1001 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, &mac[0],
1002 &pi->nm_rss_size, FW_VI_FUNC_OFLD, 0);
1004 device_printf(dev, "unable to allocate netmap virtual "
1005 "interface for port %d: %d\n", pi->port_id, -rc);
1009 pi->nm_xact_addr_filt = -1;
1011 ifp = if_alloc(IFT_ETHER);
1013 device_printf(dev, "Cannot allocate netmap ifnet\n");
1019 if_initname(ifp, is_t4(pi->adapter) ? "ncxgbe" : "ncxl",
1020 device_get_unit(dev));
1021 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1023 ifp->if_init = cxgbe_nm_init;
1024 ifp->if_ioctl = cxgbe_nm_ioctl;
1025 ifp->if_transmit = cxgbe_nm_transmit;
1026 ifp->if_qflush = cxgbe_nm_qflush;
1029 * netmap(4) says "netmap does not use features such as checksum
1030 * offloading, TCP segmentation offloading, encryption, VLAN
1031 * encapsulation/decapsulation, etc."
1033 * By default we comply with the statement above. But we do declare the
1034 * ifnet capable of L3/L4 checksumming so that a user can override
1035 * netmap and have the hardware do the L3/L4 checksums.
1037 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_JUMBO_MTU |
1039 ifp->if_capenable = 0;
1040 ifp->if_hwassist = 0;
1042 /* nm_media has already been setup by the caller */
1044 ether_ifattach(ifp, mac);
1047 * Register with netmap in the kernel.
1049 bzero(&na, sizeof(na));
1051 na.ifp = pi->nm_ifp;
1052 na.na_flags = NAF_BDG_MAYSLEEP;
1054 /* Netmap doesn't know about the space reserved for the status page. */
1055 na.num_tx_desc = pi->qsize_txq - spg_len / EQ_ESIZE;
1058 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
1059 * num_rx_desc is based on the number of buffers that can be held in the
1060 * freelist, and not the number of entries in the iq. (These two are
1061 * not exactly the same due to the space taken up by the status page).
1063 na.num_rx_desc = (pi->qsize_rxq / 8) * 8;
1064 na.nm_txsync = cxgbe_netmap_txsync;
1065 na.nm_rxsync = cxgbe_netmap_rxsync;
1066 na.nm_register = cxgbe_netmap_reg;
1067 na.num_tx_rings = pi->nnmtxq;
1068 na.num_rx_rings = pi->nnmrxq;
1069 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
1075 destroy_netmap_ifnet(struct port_info *pi)
1077 struct adapter *sc = pi->adapter;
1079 if (pi->nm_ifp == NULL)
1082 netmap_detach(pi->nm_ifp);
1083 ifmedia_removeall(&pi->nm_media);
1084 ether_ifdetach(pi->nm_ifp);
1085 if_free(pi->nm_ifp);
1086 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->nm_viid);
1092 handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp,
1093 const struct cpl_fw6_msg *cpl)
1095 const struct cpl_sge_egr_update *egr;
1097 struct sge_nm_txq *nm_txq;
1099 if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL)
1100 panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type);
1102 /* data[0] is RSS header */
1103 egr = (const void *)&cpl->data[1];
1104 oq = be32toh(egr->opcode_qid);
1105 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1106 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1108 netmap_tx_irq(ifp, nm_txq->nid);
1112 t4_nm_intr(void *arg)
1114 struct sge_nm_rxq *nm_rxq = arg;
1115 struct port_info *pi = nm_rxq->pi;
1116 struct adapter *sc = pi->adapter;
1117 struct ifnet *ifp = pi->nm_ifp;
1118 struct netmap_adapter *na = NA(ifp);
1119 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
1120 struct netmap_ring *ring = kring->ring;
1121 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1123 u_int n = 0, work = 0;
1125 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1127 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1131 lq = be32toh(d->rsp.pldbuflen_qid);
1132 opcode = d->rss.opcode;
1134 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1135 case X_RSPD_TYPE_FLBUF:
1136 /* No buffer packing so new buf every time */
1137 MPASS(lq & F_RSPD_NEWBUF);
1141 case X_RSPD_TYPE_CPL:
1142 MPASS(opcode < NUM_CPL_CMDS);
1147 handle_nm_fw6_msg(sc, ifp,
1148 (const void *)&d->cpl[0]);
1151 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - fl_pktshift;
1152 ring->slot[fl_cidx].flags = kring->nkr_slot_flags;
1153 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1157 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1158 __func__, opcode, nm_rxq);
1162 case X_RSPD_TYPE_INTR:
1163 /* Not equipped to handle forwarded interrupts. */
1164 panic("%s: netmap queue received interrupt for iq %u\n",
1168 panic("%s: illegal response type %d on nm_rxq %p",
1169 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1173 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1174 nm_rxq->iq_cidx = 0;
1175 d = &nm_rxq->iq_desc[0];
1176 nm_rxq->iq_gen ^= F_RSPD_GEN;
1179 if (__predict_false(++n == rx_ndesc)) {
1180 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1181 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1183 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1184 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1185 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1189 if (fl_cidx != nm_rxq->fl_cidx) {
1190 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1191 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1193 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(n) |
1194 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1195 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));