2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_ratelimit.h"
37 #include <sys/types.h>
38 #include <sys/eventhandler.h>
40 #include <sys/socket.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
47 #include <sys/sglist.h>
48 #include <sys/sysctl.h>
50 #include <sys/counter.h>
52 #include <net/ethernet.h>
54 #include <net/if_vlan_var.h>
55 #include <netinet/in.h>
56 #include <netinet/ip.h>
57 #include <netinet/ip6.h>
58 #include <netinet/tcp.h>
59 #include <netinet/udp.h>
60 #include <machine/in_cksum.h>
61 #include <machine/md_var.h>
65 #include <machine/bus.h>
66 #include <sys/selinfo.h>
67 #include <net/if_var.h>
68 #include <net/netmap.h>
69 #include <dev/netmap/netmap_kern.h>
72 #include "common/common.h"
73 #include "common/t4_regs.h"
74 #include "common/t4_regs_values.h"
75 #include "common/t4_msg.h"
77 #include "t4_mp_ring.h"
79 #ifdef T4_PKT_TIMESTAMP
80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
82 #define RX_COPY_THRESHOLD MINCLSIZE
86 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
87 * 0-7 are valid values.
89 static int fl_pktshift = 0;
90 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
93 * Pad ethernet payload up to this boundary.
94 * -1: driver should figure out a good value.
96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
99 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
102 * Status page length.
103 * -1: driver should figure out a good value.
104 * 64 or 128 are the only other valid values.
106 static int spg_len = -1;
107 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
111 * -1: no congestion feedback (not recommended).
112 * 0: backpressure the channel instead of dropping packets right away.
113 * 1: no backpressure, drop packets for the congested queue immediately.
115 static int cong_drop = 0;
116 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
119 * Deliver multiple frames in the same free list buffer if they fit.
120 * -1: let the driver decide whether to enable buffer packing or not.
121 * 0: disable buffer packing.
122 * 1: enable buffer packing.
124 static int buffer_packing = -1;
125 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
128 * Start next frame in a packed buffer at this boundary.
129 * -1: driver should figure out a good value.
130 * T4: driver will ignore this and use the same value as fl_pad above.
131 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
133 static int fl_pack = -1;
134 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
137 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
138 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
139 * 1: ok to create mbuf(s) within a cluster if there is room.
141 static int allow_mbufs_in_cluster = 1;
142 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
145 * Largest rx cluster size that the driver is allowed to allocate.
147 static int largest_rx_cluster = MJUM16BYTES;
148 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
151 * Size of cluster allocation that's most likely to succeed. The driver will
152 * fall back to this size if it fails to allocate clusters larger than this.
154 static int safest_rx_cluster = PAGE_SIZE;
155 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
159 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
160 * for rewriting. -1 and 0-3 are all valid values.
161 * -1: hardware should leave the TCP timestamps alone.
167 static int tsclk = -1;
168 TUNABLE_INT("hw.cxgbe.tsclk", &tsclk);
170 static int eo_max_backlog = 1024 * 1024;
171 TUNABLE_INT("hw.cxgbe.eo_max_backlog", &eo_max_backlog);
175 * The interrupt holdoff timers are multiplied by this value on T6+.
176 * 1 and 3-17 (both inclusive) are legal values.
178 static int tscale = 1;
179 TUNABLE_INT("hw.cxgbe.tscale", &tscale);
182 * Number of LRO entries in the lro_ctrl structure per rx queue.
184 static int lro_entries = TCP_LRO_ENTRIES;
185 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries);
188 * This enables presorting of frames before they're fed into tcp_lro_rx.
190 static int lro_mbufs = 0;
191 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs);
194 u_int wr_type; /* type 0 or type 1 */
195 u_int npkt; /* # of packets in this work request */
196 u_int plen; /* total payload (sum of all packets) */
197 u_int len16; /* # of 16B pieces used by this work request */
200 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
203 struct sglist_seg seg[TX_SGL_SEGS];
206 static int service_iq(struct sge_iq *, int);
207 static int service_iq_fl(struct sge_iq *, int);
208 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
209 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
210 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
211 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
212 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
214 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
215 bus_addr_t *, void **);
216 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
218 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
220 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
221 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
223 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
224 struct sysctl_oid *, struct sge_fl *);
225 static int alloc_fwq(struct adapter *);
226 static int free_fwq(struct adapter *);
227 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
228 struct sysctl_oid *);
229 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
230 struct sysctl_oid *);
231 static int free_rxq(struct vi_info *, struct sge_rxq *);
233 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
234 struct sysctl_oid *);
235 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
238 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
239 struct sysctl_oid *);
240 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
241 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
242 struct sysctl_oid *);
243 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
245 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
246 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
248 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
250 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
251 static int free_eq(struct adapter *, struct sge_eq *);
252 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
253 struct sysctl_oid *);
254 static int free_wrq(struct adapter *, struct sge_wrq *);
255 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
256 struct sysctl_oid *);
257 static int free_txq(struct vi_info *, struct sge_txq *);
258 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
259 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
260 static int refill_fl(struct adapter *, struct sge_fl *, int);
261 static void refill_sfl(void *);
262 static int alloc_fl_sdesc(struct sge_fl *);
263 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
264 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
265 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
266 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
268 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
269 static inline u_int txpkt_len16(u_int, u_int);
270 static inline u_int txpkt_vm_len16(u_int, u_int);
271 static inline u_int txpkts0_len16(u_int);
272 static inline u_int txpkts1_len16(void);
273 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
274 struct mbuf *, u_int);
275 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
276 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
277 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
278 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
279 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
280 struct mbuf *, const struct txpkts *, u_int);
281 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
282 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
283 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
284 static inline uint16_t read_hw_cidx(struct sge_eq *);
285 static inline u_int reclaimable_tx_desc(struct sge_eq *);
286 static inline u_int total_available_tx_desc(struct sge_eq *);
287 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
288 static void tx_reclaim(void *, int);
289 static __be64 get_flit(struct sglist_seg *, int, int);
290 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
292 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
294 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
295 static void wrq_tx_drain(void *, int);
296 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
298 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
299 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
301 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
302 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
306 static counter_u64_t extfree_refs;
307 static counter_u64_t extfree_rels;
309 an_handler_t t4_an_handler;
310 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
311 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
312 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
313 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
314 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
315 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
316 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
319 t4_register_an_handler(an_handler_t h)
323 MPASS(h == NULL || t4_an_handler == NULL);
325 loc = (uintptr_t *)&t4_an_handler;
326 atomic_store_rel_ptr(loc, (uintptr_t)h);
330 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
334 MPASS(type < nitems(t4_fw_msg_handler));
335 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
337 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
338 * handler dispatch table. Reject any attempt to install a handler for
341 MPASS(type != FW_TYPE_RSSCPL);
342 MPASS(type != FW6_TYPE_RSSCPL);
344 loc = (uintptr_t *)&t4_fw_msg_handler[type];
345 atomic_store_rel_ptr(loc, (uintptr_t)h);
349 t4_register_cpl_handler(int opcode, cpl_handler_t h)
353 MPASS(opcode < nitems(t4_cpl_handler));
354 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
356 loc = (uintptr_t *)&t4_cpl_handler[opcode];
357 atomic_store_rel_ptr(loc, (uintptr_t)h);
361 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
364 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
371 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
373 * The return code for filter-write is put in the CPL cookie so
374 * we have to rely on the hardware tid (is_ftid) to determine
375 * that this is a response to a filter.
377 cookie = CPL_COOKIE_FILTER;
379 cookie = G_COOKIE(cpl->cookie);
381 MPASS(cookie > CPL_COOKIE_RESERVED);
382 MPASS(cookie < nitems(set_tcb_rpl_handlers));
384 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
388 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
391 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
396 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
397 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
401 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
404 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
405 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
408 MPASS(cookie != CPL_COOKIE_RESERVED);
410 return (act_open_rpl_handlers[cookie](iq, rss, m));
414 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
417 struct adapter *sc = iq->adapter;
421 if (is_hashfilter(sc))
422 cookie = CPL_COOKIE_HASHFILTER;
424 cookie = CPL_COOKIE_TOM;
426 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
430 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
432 struct adapter *sc = iq->adapter;
433 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
434 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
438 if (is_etid(sc, tid))
439 cookie = CPL_COOKIE_ETHOFLD;
441 cookie = CPL_COOKIE_TOM;
443 return (fw4_ack_handlers[cookie](iq, rss, m));
447 t4_init_shared_cpl_handlers(void)
450 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
451 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
452 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
453 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
454 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
458 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
462 MPASS(opcode < nitems(t4_cpl_handler));
463 MPASS(cookie > CPL_COOKIE_RESERVED);
464 MPASS(cookie < NUM_CPL_COOKIES);
465 MPASS(t4_cpl_handler[opcode] != NULL);
468 case CPL_SET_TCB_RPL:
469 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
471 case CPL_L2T_WRITE_RPL:
472 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
474 case CPL_ACT_OPEN_RPL:
475 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
477 case CPL_ABORT_RPL_RSS:
478 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
481 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
487 MPASS(h == NULL || *loc == (uintptr_t)NULL);
488 atomic_store_rel_ptr(loc, (uintptr_t)h);
492 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
498 if (fl_pktshift < 0 || fl_pktshift > 7) {
499 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
500 " using 0 instead.\n", fl_pktshift);
504 if (spg_len != 64 && spg_len != 128) {
507 #if defined(__i386__) || defined(__amd64__)
508 len = cpu_clflush_line_size > 64 ? 128 : 64;
513 printf("Invalid hw.cxgbe.spg_len value (%d),"
514 " using %d instead.\n", spg_len, len);
519 if (cong_drop < -1 || cong_drop > 1) {
520 printf("Invalid hw.cxgbe.cong_drop value (%d),"
521 " using 0 instead.\n", cong_drop);
525 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
526 printf("Invalid hw.cxgbe.tscale value (%d),"
527 " using 1 instead.\n", tscale);
531 extfree_refs = counter_u64_alloc(M_WAITOK);
532 extfree_rels = counter_u64_alloc(M_WAITOK);
533 counter_u64_zero(extfree_refs);
534 counter_u64_zero(extfree_rels);
536 t4_init_shared_cpl_handlers();
537 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
538 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
539 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
540 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
542 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
545 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
546 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
550 t4_sge_modunload(void)
553 counter_u64_free(extfree_refs);
554 counter_u64_free(extfree_rels);
558 t4_sge_extfree_refs(void)
562 rels = counter_u64_fetch(extfree_rels);
563 refs = counter_u64_fetch(extfree_refs);
565 return (refs - rels);
569 setup_pad_and_pack_boundaries(struct adapter *sc)
572 int pad, pack, pad_shift;
574 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
575 X_INGPADBOUNDARY_SHIFT;
577 if (fl_pad < (1 << pad_shift) ||
578 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
581 * If there is any chance that we might use buffer packing and
582 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
583 * it to the minimum allowed in all other cases.
585 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
588 * For fl_pad = 0 we'll still write a reasonable value to the
589 * register but all the freelists will opt out of padding.
590 * We'll complain here only if the user tried to set it to a
591 * value greater than 0 that was invalid.
594 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
595 " (%d), using %d instead.\n", fl_pad, pad);
598 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
599 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
600 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
603 if (fl_pack != -1 && fl_pack != pad) {
604 /* Complain but carry on. */
605 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
606 " using %d instead.\n", fl_pack, pad);
612 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
613 !powerof2(fl_pack)) {
614 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
615 MPASS(powerof2(pack));
623 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
624 " (%d), using %d instead.\n", fl_pack, pack);
627 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
629 v = V_INGPACKBOUNDARY(0);
631 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
633 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
634 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
638 * adap->params.vpd.cclk must be set up before this is called.
641 t4_tweak_chip_settings(struct adapter *sc)
645 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
646 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
647 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
648 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
649 static int sge_flbuf_sizes[] = {
651 #if MJUMPAGESIZE != MCLBYTES
653 MJUMPAGESIZE - CL_METADATA_SIZE,
654 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
658 MCLBYTES - MSIZE - CL_METADATA_SIZE,
659 MJUM9BYTES - CL_METADATA_SIZE,
660 MJUM16BYTES - CL_METADATA_SIZE,
663 KASSERT(sc->flags & MASTER_PF,
664 ("%s: trying to change chip settings when not master.", __func__));
666 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
667 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
668 V_EGRSTATUSPAGESIZE(spg_len == 128);
669 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
671 setup_pad_and_pack_boundaries(sc);
673 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
674 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
675 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
676 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
677 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
678 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
679 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
680 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
681 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
683 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
684 ("%s: hw buffer size table too big", __func__));
685 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
686 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
690 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
691 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
692 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
694 KASSERT(intr_timer[0] <= timer_max,
695 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
697 for (i = 1; i < nitems(intr_timer); i++) {
698 KASSERT(intr_timer[i] >= intr_timer[i - 1],
699 ("%s: timers not listed in increasing order (%d)",
702 while (intr_timer[i] > timer_max) {
703 if (i == nitems(intr_timer) - 1) {
704 intr_timer[i] = timer_max;
707 intr_timer[i] += intr_timer[i - 1];
712 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
713 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
714 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
715 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
716 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
717 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
718 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
719 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
720 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
722 if (chip_id(sc) >= CHELSIO_T6) {
723 m = V_TSCALE(M_TSCALE);
727 v = V_TSCALE(tscale - 2);
728 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
730 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
731 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
732 V_WRTHRTHRESH(M_WRTHRTHRESH);
733 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
735 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
737 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
741 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
742 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
743 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
746 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
747 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
748 * may have to deal with is MAXPHYS + 1 page.
750 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
751 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
753 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
754 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
755 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
757 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
759 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
760 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
764 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
765 * padding is in use, the buffer's start and end need to be aligned to the pad
766 * boundary as well. We'll just make sure that the size is a multiple of the
767 * boundary here, it is up to the buffer allocation code to make sure the start
768 * of the buffer is aligned as well.
771 hwsz_ok(struct adapter *sc, int hwsz)
773 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
775 return (hwsz >= 64 && (hwsz & mask) == 0);
779 * XXX: driver really should be able to deal with unexpected settings.
782 t4_read_chip_settings(struct adapter *sc)
784 struct sge *s = &sc->sge;
785 struct sge_params *sp = &sc->params.sge;
788 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
789 static int sw_buf_sizes[] = { /* Sorted by size */
791 #if MJUMPAGESIZE != MCLBYTES
797 struct sw_zone_info *swz, *safe_swz;
798 struct hw_buf_info *hwb;
802 r = sc->params.sge.sge_control;
804 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
809 * If this changes then every single use of PAGE_SHIFT in the driver
810 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
812 if (sp->page_shift != PAGE_SHIFT) {
813 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
817 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
818 hwb = &s->hw_buf_info[0];
819 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
820 r = sc->params.sge.sge_fl_buffer_size[i];
822 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
827 * Create a sorted list in decreasing order of hw buffer sizes (and so
828 * increasing order of spare area) for each software zone.
830 * If padding is enabled then the start and end of the buffer must align
831 * to the pad boundary; if packing is enabled then they must align with
832 * the pack boundary as well. Allocations from the cluster zones are
833 * aligned to min(size, 4K), so the buffer starts at that alignment and
834 * ends at hwb->size alignment. If mbuf inlining is allowed the
835 * starting alignment will be reduced to MSIZE and the driver will
836 * exercise appropriate caution when deciding on the best buffer layout
839 n = 0; /* no usable buffer size to begin with */
840 swz = &s->sw_zone_info[0];
842 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
843 int8_t head = -1, tail = -1;
845 swz->size = sw_buf_sizes[i];
846 swz->zone = m_getzone(swz->size);
847 swz->type = m_gettype(swz->size);
849 if (swz->size < PAGE_SIZE) {
850 MPASS(powerof2(swz->size));
851 if (fl_pad && (swz->size % sp->pad_boundary != 0))
855 if (swz->size == safest_rx_cluster)
858 hwb = &s->hw_buf_info[0];
859 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
860 if (hwb->zidx != -1 || hwb->size > swz->size)
864 MPASS(hwb->size % sp->pad_boundary == 0);
869 else if (hwb->size < s->hw_buf_info[tail].size) {
870 s->hw_buf_info[tail].next = j;
874 struct hw_buf_info *t;
876 for (cur = &head; *cur != -1; cur = &t->next) {
877 t = &s->hw_buf_info[*cur];
878 if (hwb->size == t->size) {
882 if (hwb->size > t->size) {
890 swz->head_hwidx = head;
891 swz->tail_hwidx = tail;
895 if (swz->size - s->hw_buf_info[tail].size >=
897 sc->flags |= BUF_PACKING_OK;
901 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
907 if (safe_swz != NULL) {
908 s->safe_hwidx1 = safe_swz->head_hwidx;
909 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
912 hwb = &s->hw_buf_info[i];
915 MPASS(hwb->size % sp->pad_boundary == 0);
917 spare = safe_swz->size - hwb->size;
918 if (spare >= CL_METADATA_SIZE) {
925 if (sc->flags & IS_VF)
928 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
929 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
931 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
935 m = v = F_TDDPTAGTCB;
936 r = t4_read_reg(sc, A_ULP_RX_CTL);
938 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
942 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
944 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
945 r = t4_read_reg(sc, A_TP_PARA_REG5);
947 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
951 t4_init_tp_params(sc, 1);
953 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
954 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
960 t4_create_dma_tag(struct adapter *sc)
964 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
966 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
969 device_printf(sc->dev,
970 "failed to create main DMA tag: %d\n", rc);
977 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
978 struct sysctl_oid_list *children)
980 struct sge_params *sp = &sc->params.sge;
982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
983 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
984 "freelist buffer sizes");
986 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
987 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
990 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
993 NULL, sp->spg_len, "status page size (bytes)");
995 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
996 NULL, cong_drop, "congestion drop setting");
998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
999 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1003 t4_destroy_dma_tag(struct adapter *sc)
1006 bus_dma_tag_destroy(sc->dmat);
1012 * Allocate and initialize the firmware event queue, control queues, and special
1013 * purpose rx queues owned by the adapter.
1015 * Returns errno on failure. Resources allocated up to that point may still be
1016 * allocated. Caller is responsible for cleanup in case this function fails.
1019 t4_setup_adapter_queues(struct adapter *sc)
1021 struct sysctl_oid *oid;
1022 struct sysctl_oid_list *children;
1025 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1027 sysctl_ctx_init(&sc->ctx);
1028 sc->flags |= ADAP_SYSCTL_CTX;
1031 * Firmware event queue
1038 * That's all for the VF driver.
1040 if (sc->flags & IS_VF)
1043 oid = device_get_sysctl_tree(sc->dev);
1044 children = SYSCTL_CHILDREN(oid);
1047 * XXX: General purpose rx queues, one per port.
1051 * Control queues, one per port.
1053 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1054 CTLFLAG_RD, NULL, "control queues");
1055 for_each_port(sc, i) {
1056 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1058 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1070 t4_teardown_adapter_queues(struct adapter *sc)
1074 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1076 /* Do this before freeing the queue */
1077 if (sc->flags & ADAP_SYSCTL_CTX) {
1078 sysctl_ctx_free(&sc->ctx);
1079 sc->flags &= ~ADAP_SYSCTL_CTX;
1082 for_each_port(sc, i)
1083 free_wrq(sc, &sc->sge.ctrlq[i]);
1089 /* Maximum payload that can be delivered with a single iq descriptor */
1091 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
1097 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
1099 /* Note that COP can set rx_coalesce on/off per connection. */
1100 payload = max(mtu, rxcs);
1103 /* large enough even when hw VLAN extraction is disabled */
1104 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1105 ETHER_VLAN_ENCAP_LEN + mtu;
1114 t4_setup_vi_queues(struct vi_info *vi)
1116 int rc = 0, i, intr_idx, iqidx;
1117 struct sge_rxq *rxq;
1118 struct sge_txq *txq;
1120 struct sge_ofld_rxq *ofld_rxq;
1122 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1123 struct sge_wrq *ofld_txq;
1127 struct sge_nm_rxq *nm_rxq;
1128 struct sge_nm_txq *nm_txq;
1131 struct port_info *pi = vi->pi;
1132 struct adapter *sc = pi->adapter;
1133 struct ifnet *ifp = vi->ifp;
1134 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1135 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1136 int maxp, mtu = ifp->if_mtu;
1138 /* Interrupt vector to start from (when using multiple vectors) */
1139 intr_idx = vi->first_intr;
1142 saved_idx = intr_idx;
1143 if (ifp->if_capabilities & IFCAP_NETMAP) {
1145 /* netmap is supported with direct interrupts only. */
1146 MPASS(!forwarding_intr_to_fwq(sc));
1149 * We don't have buffers to back the netmap rx queues
1150 * right now so we create the queues in a way that
1151 * doesn't set off any congestion signal in the chip.
1153 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1154 CTLFLAG_RD, NULL, "rx queues");
1155 for_each_nm_rxq(vi, i, nm_rxq) {
1156 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1162 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1163 CTLFLAG_RD, NULL, "tx queues");
1164 for_each_nm_txq(vi, i, nm_txq) {
1165 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1166 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1172 /* Normal rx queues and netmap rx queues share the same interrupts. */
1173 intr_idx = saved_idx;
1177 * Allocate rx queues first because a default iqid is required when
1178 * creating a tx queue.
1180 maxp = mtu_to_max_payload(sc, mtu, 0);
1181 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1182 CTLFLAG_RD, NULL, "rx queues");
1183 for_each_rxq(vi, i, rxq) {
1185 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1187 snprintf(name, sizeof(name), "%s rxq%d-fl",
1188 device_get_nameunit(vi->dev), i);
1189 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1191 rc = alloc_rxq(vi, rxq,
1192 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1198 if (ifp->if_capabilities & IFCAP_NETMAP)
1199 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1202 maxp = mtu_to_max_payload(sc, mtu, 1);
1203 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1204 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections");
1205 for_each_ofld_rxq(vi, i, ofld_rxq) {
1207 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1210 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1211 device_get_nameunit(vi->dev), i);
1212 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1214 rc = alloc_ofld_rxq(vi, ofld_rxq,
1215 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1223 * Now the tx queues.
1225 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1227 for_each_txq(vi, i, txq) {
1228 iqidx = vi->first_rxq + (i % vi->nrxq);
1229 snprintf(name, sizeof(name), "%s txq%d",
1230 device_get_nameunit(vi->dev), i);
1231 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1232 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1234 rc = alloc_txq(vi, txq, i, oid);
1238 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1239 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1240 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD");
1241 for_each_ofld_txq(vi, i, ofld_txq) {
1242 struct sysctl_oid *oid2;
1244 snprintf(name, sizeof(name), "%s ofld_txq%d",
1245 device_get_nameunit(vi->dev), i);
1247 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1248 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1249 sc->sge.ofld_rxq[iqidx].iq.cntxt_id, name);
1251 iqidx = vi->first_rxq + (i % vi->nrxq);
1252 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1253 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1256 snprintf(name, sizeof(name), "%d", i);
1257 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1258 name, CTLFLAG_RD, NULL, "offload tx queue");
1260 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1267 t4_teardown_vi_queues(vi);
1276 t4_teardown_vi_queues(struct vi_info *vi)
1279 struct sge_rxq *rxq;
1280 struct sge_txq *txq;
1281 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1282 struct port_info *pi = vi->pi;
1283 struct adapter *sc = pi->adapter;
1284 struct sge_wrq *ofld_txq;
1287 struct sge_ofld_rxq *ofld_rxq;
1290 struct sge_nm_rxq *nm_rxq;
1291 struct sge_nm_txq *nm_txq;
1294 /* Do this before freeing the queues */
1295 if (vi->flags & VI_SYSCTL_CTX) {
1296 sysctl_ctx_free(&vi->ctx);
1297 vi->flags &= ~VI_SYSCTL_CTX;
1301 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1302 for_each_nm_txq(vi, i, nm_txq) {
1303 free_nm_txq(vi, nm_txq);
1306 for_each_nm_rxq(vi, i, nm_rxq) {
1307 free_nm_rxq(vi, nm_rxq);
1313 * Take down all the tx queues first, as they reference the rx queues
1314 * (for egress updates, etc.).
1317 for_each_txq(vi, i, txq) {
1320 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1321 for_each_ofld_txq(vi, i, ofld_txq) {
1322 free_wrq(sc, ofld_txq);
1327 * Then take down the rx queues.
1330 for_each_rxq(vi, i, rxq) {
1334 for_each_ofld_rxq(vi, i, ofld_rxq) {
1335 free_ofld_rxq(vi, ofld_rxq);
1343 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1346 * a) Deals with errors, if any.
1347 * b) Services firmware event queue, which is taking interrupts for all other
1351 t4_intr_all(void *arg)
1353 struct adapter *sc = arg;
1354 struct sge_iq *fwq = &sc->sge.fwq;
1356 MPASS(sc->intr_count == 1);
1363 * Interrupt handler for errors (installed directly when multiple interrupts are
1364 * being used, or called by t4_intr_all).
1367 t4_intr_err(void *arg)
1369 struct adapter *sc = arg;
1371 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1372 t4_slow_intr_handler(sc);
1376 * Interrupt handler for iq-only queues. The firmware event queue is the only
1377 * such queue right now.
1380 t4_intr_evt(void *arg)
1382 struct sge_iq *iq = arg;
1384 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1386 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1391 * Interrupt handler for iq+fl queues.
1396 struct sge_iq *iq = arg;
1398 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1399 service_iq_fl(iq, 0);
1400 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1406 * Interrupt handler for netmap rx queues.
1409 t4_nm_intr(void *arg)
1411 struct sge_nm_rxq *nm_rxq = arg;
1413 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1414 service_nm_rxq(nm_rxq);
1415 atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1420 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1423 t4_vi_intr(void *arg)
1425 struct irq *irq = arg;
1427 MPASS(irq->nm_rxq != NULL);
1428 t4_nm_intr(irq->nm_rxq);
1430 MPASS(irq->rxq != NULL);
1436 * Deals with interrupts on an iq-only (no freelist) queue.
1439 service_iq(struct sge_iq *iq, int budget)
1442 struct adapter *sc = iq->adapter;
1443 struct iq_desc *d = &iq->desc[iq->cidx];
1444 int ndescs = 0, limit;
1447 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1449 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1450 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1451 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1453 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1454 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1456 limit = budget ? budget : iq->qsize / 16;
1459 * We always come back and check the descriptor ring for new indirect
1460 * interrupts and other responses after running a single handler.
1463 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1467 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1468 lq = be32toh(d->rsp.pldbuflen_qid);
1471 case X_RSPD_TYPE_FLBUF:
1472 panic("%s: data for an iq (%p) with no freelist",
1477 case X_RSPD_TYPE_CPL:
1478 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1479 ("%s: bad opcode %02x.", __func__,
1481 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1484 case X_RSPD_TYPE_INTR:
1486 * There are 1K interrupt-capable queues (qids 0
1487 * through 1023). A response type indicating a
1488 * forwarded interrupt with a qid >= 1K is an
1489 * iWARP async notification.
1491 if (__predict_true(lq >= 1024)) {
1492 t4_an_handler(iq, &d->rsp);
1496 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1498 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1500 if (service_iq_fl(q, q->qsize / 16) == 0) {
1501 atomic_cmpset_int(&q->state,
1502 IQS_BUSY, IQS_IDLE);
1504 STAILQ_INSERT_TAIL(&iql, q,
1512 ("%s: illegal response type %d on iq %p",
1513 __func__, rsp_type, iq));
1515 "%s: illegal response type %d on iq %p",
1516 device_get_nameunit(sc->dev), rsp_type, iq);
1521 if (__predict_false(++iq->cidx == iq->sidx)) {
1523 iq->gen ^= F_RSPD_GEN;
1526 if (__predict_false(++ndescs == limit)) {
1527 t4_write_reg(sc, sc->sge_gts_reg,
1529 V_INGRESSQID(iq->cntxt_id) |
1530 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1534 return (EINPROGRESS);
1539 if (STAILQ_EMPTY(&iql))
1543 * Process the head only, and send it to the back of the list if
1544 * it's still not done.
1546 q = STAILQ_FIRST(&iql);
1547 STAILQ_REMOVE_HEAD(&iql, link);
1548 if (service_iq_fl(q, q->qsize / 8) == 0)
1549 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1551 STAILQ_INSERT_TAIL(&iql, q, link);
1554 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1555 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1561 sort_before_lro(struct lro_ctrl *lro)
1564 return (lro->lro_mbuf_max != 0);
1568 * Deals with interrupts on an iq+fl queue.
1571 service_iq_fl(struct sge_iq *iq, int budget)
1573 struct sge_rxq *rxq = iq_to_rxq(iq);
1575 struct adapter *sc = iq->adapter;
1576 struct iq_desc *d = &iq->desc[iq->cidx];
1577 int ndescs = 0, limit;
1578 int rsp_type, refill, starved;
1580 uint16_t fl_hw_cidx;
1582 #if defined(INET) || defined(INET6)
1583 const struct timeval lro_timeout = {0, sc->lro_timeout};
1584 struct lro_ctrl *lro = &rxq->lro;
1587 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1588 MPASS(iq->flags & IQ_HAS_FL);
1590 limit = budget ? budget : iq->qsize / 16;
1592 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1594 #if defined(INET) || defined(INET6)
1595 if (iq->flags & IQ_ADJ_CREDIT) {
1596 MPASS(sort_before_lro(lro));
1597 iq->flags &= ~IQ_ADJ_CREDIT;
1598 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1599 tcp_lro_flush_all(lro);
1600 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1601 V_INGRESSQID((u32)iq->cntxt_id) |
1602 V_SEINTARM(iq->intr_params));
1608 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1611 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1617 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1618 lq = be32toh(d->rsp.pldbuflen_qid);
1621 case X_RSPD_TYPE_FLBUF:
1623 m0 = get_fl_payload(sc, fl, lq);
1624 if (__predict_false(m0 == NULL))
1626 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1627 #ifdef T4_PKT_TIMESTAMP
1629 * 60 bit timestamp for the payload is
1630 * *(uint64_t *)m0->m_pktdat. Note that it is
1631 * in the leading free-space in the mbuf. The
1632 * kernel can clobber it during a pullup,
1633 * m_copymdata, etc. You need to make sure that
1634 * the mbuf reaches you unmolested if you care
1635 * about the timestamp.
1637 *(uint64_t *)m0->m_pktdat =
1638 be64toh(ctrl->u.last_flit) & 0xfffffffffffffff;
1643 case X_RSPD_TYPE_CPL:
1644 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1645 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1646 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1649 case X_RSPD_TYPE_INTR:
1652 * There are 1K interrupt-capable queues (qids 0
1653 * through 1023). A response type indicating a
1654 * forwarded interrupt with a qid >= 1K is an
1655 * iWARP async notification. That is the only
1656 * acceptable indirect interrupt on this queue.
1658 if (__predict_false(lq < 1024)) {
1659 panic("%s: indirect interrupt on iq_fl %p "
1660 "with qid %u", __func__, iq, lq);
1663 t4_an_handler(iq, &d->rsp);
1667 KASSERT(0, ("%s: illegal response type %d on iq %p",
1668 __func__, rsp_type, iq));
1669 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1670 device_get_nameunit(sc->dev), rsp_type, iq);
1675 if (__predict_false(++iq->cidx == iq->sidx)) {
1677 iq->gen ^= F_RSPD_GEN;
1680 if (__predict_false(++ndescs == limit)) {
1681 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1682 V_INGRESSQID(iq->cntxt_id) |
1683 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1686 #if defined(INET) || defined(INET6)
1687 if (iq->flags & IQ_LRO_ENABLED &&
1688 !sort_before_lro(lro) &&
1689 sc->lro_timeout != 0) {
1690 tcp_lro_flush_inactive(lro, &lro_timeout);
1695 refill_fl(sc, fl, 32);
1698 return (EINPROGRESS);
1703 refill_fl(sc, fl, 32);
1705 fl_hw_cidx = fl->hw_cidx;
1709 #if defined(INET) || defined(INET6)
1710 if (iq->flags & IQ_LRO_ENABLED) {
1711 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1712 MPASS(sort_before_lro(lro));
1713 /* hold back one credit and don't flush LRO state */
1714 iq->flags |= IQ_ADJ_CREDIT;
1717 tcp_lro_flush_all(lro);
1722 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1723 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1726 starved = refill_fl(sc, fl, 64);
1728 if (__predict_false(starved != 0))
1729 add_fl_to_sfl(sc, fl);
1735 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1737 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1740 MPASS(cll->region3 >= CL_METADATA_SIZE);
1745 static inline struct cluster_metadata *
1746 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1750 if (cl_has_metadata(fl, cll)) {
1751 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1753 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1759 rxb_free(struct mbuf *m)
1761 uma_zone_t zone = m->m_ext.ext_arg1;
1762 void *cl = m->m_ext.ext_arg2;
1764 uma_zfree(zone, cl);
1765 counter_u64_add(extfree_rels, 1);
1769 * The mbuf returned by this function could be allocated from zone_mbuf or
1770 * constructed in spare room in the cluster.
1772 * The mbuf carries the payload in one of these ways
1773 * a) frame inside the mbuf (mbuf from zone_mbuf)
1774 * b) m_cljset (for clusters without metadata) zone_mbuf
1775 * c) m_extaddref (cluster with metadata) inline mbuf
1776 * d) m_extaddref (cluster with metadata) zone_mbuf
1778 static struct mbuf *
1779 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1783 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1784 struct cluster_layout *cll = &sd->cll;
1785 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1786 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1787 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1791 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1792 len = min(remaining, blen);
1793 payload = sd->cl + cll->region1 + fl->rx_offset;
1794 if (fl->flags & FL_BUF_PACKING) {
1795 const u_int l = fr_offset + len;
1796 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1798 if (fl->rx_offset + len + pad < hwb->size)
1800 MPASS(fl->rx_offset + blen <= hwb->size);
1802 MPASS(fl->rx_offset == 0); /* not packing */
1806 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1809 * Copy payload into a freshly allocated mbuf.
1812 m = fr_offset == 0 ?
1813 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1816 fl->mbuf_allocated++;
1817 #ifdef T4_PKT_TIMESTAMP
1818 /* Leave room for a timestamp */
1821 /* copy data to mbuf */
1822 bcopy(payload, mtod(m, caddr_t), len);
1824 } else if (sd->nmbuf * MSIZE < cll->region1) {
1827 * There's spare room in the cluster for an mbuf. Create one
1828 * and associate it with the payload that's in the cluster.
1832 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1833 /* No bzero required */
1834 if (m_init(m, M_NOWAIT, MT_DATA,
1835 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1838 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1840 if (sd->nmbuf++ == 0)
1841 counter_u64_add(extfree_refs, 1);
1846 * Grab an mbuf from zone_mbuf and associate it with the
1847 * payload in the cluster.
1850 m = fr_offset == 0 ?
1851 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1854 fl->mbuf_allocated++;
1856 m_extaddref(m, payload, blen, &clm->refcount,
1857 rxb_free, swz->zone, sd->cl);
1858 if (sd->nmbuf++ == 0)
1859 counter_u64_add(extfree_refs, 1);
1861 m_cljset(m, sd->cl, swz->type);
1862 sd->cl = NULL; /* consumed, not a recycle candidate */
1866 m->m_pkthdr.len = remaining;
1869 if (fl->flags & FL_BUF_PACKING) {
1870 fl->rx_offset += blen;
1871 MPASS(fl->rx_offset <= hwb->size);
1872 if (fl->rx_offset < hwb->size)
1873 return (m); /* without advancing the cidx */
1876 if (__predict_false(++fl->cidx % 8 == 0)) {
1877 uint16_t cidx = fl->cidx / 8;
1879 if (__predict_false(cidx == fl->sidx))
1880 fl->cidx = cidx = 0;
1888 static struct mbuf *
1889 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1891 struct mbuf *m0, *m, **pnext;
1893 const u_int total = G_RSPD_LEN(len_newbuf);
1895 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1896 M_ASSERTPKTHDR(fl->m0);
1897 MPASS(fl->m0->m_pkthdr.len == total);
1898 MPASS(fl->remaining < total);
1902 remaining = fl->remaining;
1903 fl->flags &= ~FL_BUF_RESUME;
1907 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1909 if (__predict_false(++fl->cidx % 8 == 0)) {
1910 uint16_t cidx = fl->cidx / 8;
1912 if (__predict_false(cidx == fl->sidx))
1913 fl->cidx = cidx = 0;
1919 * Payload starts at rx_offset in the current hw buffer. Its length is
1920 * 'len' and it may span multiple hw buffers.
1923 m0 = get_scatter_segment(sc, fl, 0, total);
1926 remaining = total - m0->m_len;
1927 pnext = &m0->m_next;
1928 while (remaining > 0) {
1930 MPASS(fl->rx_offset == 0);
1931 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1932 if (__predict_false(m == NULL)) {
1935 fl->remaining = remaining;
1936 fl->flags |= FL_BUF_RESUME;
1941 remaining -= m->m_len;
1950 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1952 struct sge_rxq *rxq = iq_to_rxq(iq);
1953 struct ifnet *ifp = rxq->ifp;
1954 struct adapter *sc = iq->adapter;
1955 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1956 #if defined(INET) || defined(INET6)
1957 struct lro_ctrl *lro = &rxq->lro;
1959 static const int sw_hashtype[4][2] = {
1960 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1961 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1962 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1963 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1966 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1969 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1970 m0->m_len -= sc->params.sge.fl_pktshift;
1971 m0->m_data += sc->params.sge.fl_pktshift;
1973 m0->m_pkthdr.rcvif = ifp;
1974 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1975 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1977 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1978 if (ifp->if_capenable & IFCAP_RXCSUM &&
1979 cpl->l2info & htobe32(F_RXF_IP)) {
1980 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1981 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1983 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1984 cpl->l2info & htobe32(F_RXF_IP6)) {
1985 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1990 if (__predict_false(cpl->ip_frag))
1991 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1993 m0->m_pkthdr.csum_data = 0xffff;
1997 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1998 m0->m_flags |= M_VLANTAG;
1999 rxq->vlan_extraction++;
2002 #if defined(INET) || defined(INET6)
2003 if (iq->flags & IQ_LRO_ENABLED) {
2004 if (sort_before_lro(lro)) {
2005 tcp_lro_queue_mbuf(lro, m0);
2006 return (0); /* queued for sort, then LRO */
2008 if (tcp_lro_rx(lro, m0, 0) == 0)
2009 return (0); /* queued for LRO */
2012 ifp->if_input(ifp, m0);
2018 * Must drain the wrq or make sure that someone else will.
2021 wrq_tx_drain(void *arg, int n)
2023 struct sge_wrq *wrq = arg;
2024 struct sge_eq *eq = &wrq->eq;
2027 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2028 drain_wrq_wr_list(wrq->adapter, wrq);
2033 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2035 struct sge_eq *eq = &wrq->eq;
2036 u_int available, dbdiff; /* # of hardware descriptors */
2039 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2041 EQ_LOCK_ASSERT_OWNED(eq);
2042 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2043 wr = STAILQ_FIRST(&wrq->wr_list);
2044 MPASS(wr != NULL); /* Must be called with something useful to do */
2045 MPASS(eq->pidx == eq->dbidx);
2049 eq->cidx = read_hw_cidx(eq);
2050 if (eq->pidx == eq->cidx)
2051 available = eq->sidx - 1;
2053 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2055 MPASS(wr->wrq == wrq);
2056 n = howmany(wr->wr_len, EQ_ESIZE);
2060 dst = (void *)&eq->desc[eq->pidx];
2061 if (__predict_true(eq->sidx - eq->pidx > n)) {
2062 /* Won't wrap, won't end exactly at the status page. */
2063 bcopy(&wr->wr[0], dst, wr->wr_len);
2066 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2068 bcopy(&wr->wr[0], dst, first_portion);
2069 if (wr->wr_len > first_portion) {
2070 bcopy(&wr->wr[first_portion], &eq->desc[0],
2071 wr->wr_len - first_portion);
2073 eq->pidx = n - (eq->sidx - eq->pidx);
2075 wrq->tx_wrs_copied++;
2077 if (available < eq->sidx / 4 &&
2078 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2079 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2081 eq->equeqidx = eq->pidx;
2082 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2083 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2084 eq->equeqidx = eq->pidx;
2089 ring_eq_db(sc, eq, dbdiff);
2093 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2095 MPASS(wrq->nwr_pending > 0);
2097 MPASS(wrq->ndesc_needed >= n);
2098 wrq->ndesc_needed -= n;
2099 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2102 ring_eq_db(sc, eq, dbdiff);
2106 * Doesn't fail. Holds on to work requests it can't send right away.
2109 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2112 struct sge_eq *eq = &wrq->eq;
2115 EQ_LOCK_ASSERT_OWNED(eq);
2117 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2118 MPASS((wr->wr_len & 0x7) == 0);
2120 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2122 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2124 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2125 return; /* commit_wrq_wr will drain wr_list as well. */
2127 drain_wrq_wr_list(sc, wrq);
2129 /* Doorbell must have caught up to the pidx. */
2130 MPASS(eq->pidx == eq->dbidx);
2134 t4_update_fl_bufsize(struct ifnet *ifp)
2136 struct vi_info *vi = ifp->if_softc;
2137 struct adapter *sc = vi->pi->adapter;
2138 struct sge_rxq *rxq;
2140 struct sge_ofld_rxq *ofld_rxq;
2143 int i, maxp, mtu = ifp->if_mtu;
2145 maxp = mtu_to_max_payload(sc, mtu, 0);
2146 for_each_rxq(vi, i, rxq) {
2150 find_best_refill_source(sc, fl, maxp);
2154 maxp = mtu_to_max_payload(sc, mtu, 1);
2155 for_each_ofld_rxq(vi, i, ofld_rxq) {
2159 find_best_refill_source(sc, fl, maxp);
2166 mbuf_nsegs(struct mbuf *m)
2170 KASSERT(m->m_pkthdr.l5hlen > 0,
2171 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2173 return (m->m_pkthdr.l5hlen);
2177 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2181 m->m_pkthdr.l5hlen = nsegs;
2185 mbuf_len16(struct mbuf *m)
2190 n = m->m_pkthdr.PH_loc.eight[0];
2191 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2197 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2201 m->m_pkthdr.PH_loc.eight[0] = len16;
2206 mbuf_eo_nsegs(struct mbuf *m)
2210 return (m->m_pkthdr.PH_loc.eight[1]);
2214 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2218 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2222 mbuf_eo_len16(struct mbuf *m)
2227 n = m->m_pkthdr.PH_loc.eight[2];
2228 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2234 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2238 m->m_pkthdr.PH_loc.eight[2] = len16;
2242 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2246 return (m->m_pkthdr.PH_loc.eight[3]);
2250 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2254 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2258 needs_eo(struct mbuf *m)
2261 return (m->m_pkthdr.snd_tag != NULL);
2266 needs_tso(struct mbuf *m)
2271 return (m->m_pkthdr.csum_flags & CSUM_TSO);
2275 needs_l3_csum(struct mbuf *m)
2280 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO));
2284 needs_l4_csum(struct mbuf *m)
2289 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2290 CSUM_TCP_IPV6 | CSUM_TSO));
2294 needs_tcp_csum(struct mbuf *m)
2298 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO));
2303 needs_udp_csum(struct mbuf *m)
2307 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6));
2312 needs_vlan_insertion(struct mbuf *m)
2317 return (m->m_flags & M_VLANTAG);
2321 m_advance(struct mbuf **pm, int *poffset, int len)
2323 struct mbuf *m = *pm;
2324 int offset = *poffset;
2330 if (offset + len < m->m_len) {
2332 p = mtod(m, uintptr_t) + offset;
2335 len -= m->m_len - offset;
2346 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2347 * must have at least one mbuf that's not empty. It is possible for this
2348 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2351 count_mbuf_nsegs(struct mbuf *m, int skip)
2353 vm_paddr_t lastb, next;
2358 MPASS(m->m_pkthdr.len > 0);
2359 MPASS(m->m_pkthdr.len >= skip);
2363 for (; m; m = m->m_next) {
2366 if (__predict_false(len == 0))
2372 va = mtod(m, vm_offset_t) + skip;
2375 next = pmap_kextract(va);
2376 nsegs += sglist_count((void *)(uintptr_t)va, len);
2377 if (lastb + 1 == next)
2379 lastb = pmap_kextract(va + len - 1);
2386 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2387 * a) caller can assume it's been freed if this function returns with an error.
2388 * b) it may get defragged up if the gather list is too long for the hardware.
2391 parse_pkt(struct adapter *sc, struct mbuf **mp)
2393 struct mbuf *m0 = *mp, *m;
2394 int rc, nsegs, defragged = 0, offset;
2395 struct ether_header *eh;
2397 #if defined(INET) || defined(INET6)
2403 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2412 * First count the number of gather list segments in the payload.
2413 * Defrag the mbuf if nsegs exceeds the hardware limit.
2416 MPASS(m0->m_pkthdr.len > 0);
2417 nsegs = count_mbuf_nsegs(m0, 0);
2418 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2419 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2423 *mp = m0 = m; /* update caller's copy after defrag */
2427 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2428 m0 = m_pullup(m0, m0->m_pkthdr.len);
2430 /* Should have left well enough alone. */
2434 *mp = m0; /* update caller's copy after pullup */
2437 set_mbuf_nsegs(m0, nsegs);
2438 if (sc->flags & IS_VF)
2439 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2441 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2445 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2446 * checksumming is enabled. needs_l4_csum happens to check for all the
2449 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0)))
2450 m0->m_pkthdr.snd_tag = NULL;
2453 if (!needs_tso(m0) &&
2457 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2461 eh = mtod(m, struct ether_header *);
2462 eh_type = ntohs(eh->ether_type);
2463 if (eh_type == ETHERTYPE_VLAN) {
2464 struct ether_vlan_header *evh = (void *)eh;
2466 eh_type = ntohs(evh->evl_proto);
2467 m0->m_pkthdr.l2hlen = sizeof(*evh);
2469 m0->m_pkthdr.l2hlen = sizeof(*eh);
2472 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2476 case ETHERTYPE_IPV6:
2478 struct ip6_hdr *ip6 = l3hdr;
2480 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2482 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2489 struct ip *ip = l3hdr;
2491 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2496 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2497 " with the same INET/INET6 options as the kernel.",
2501 #if defined(INET) || defined(INET6)
2502 if (needs_tcp_csum(m0)) {
2503 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2504 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2506 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2507 set_mbuf_eo_tsclk_tsoff(m0,
2508 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2509 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2511 set_mbuf_eo_tsclk_tsoff(m0, 0);
2512 } else if (needs_udp_csum(m)) {
2513 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2520 /* EO WRs have the headers in the WR and not the GL. */
2521 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2522 m0->m_pkthdr.l4hlen;
2523 nsegs = count_mbuf_nsegs(m0, immhdrs);
2524 set_mbuf_eo_nsegs(m0, nsegs);
2525 set_mbuf_eo_len16(m0,
2526 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2535 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2537 struct sge_eq *eq = &wrq->eq;
2538 struct adapter *sc = wrq->adapter;
2539 int ndesc, available;
2544 ndesc = howmany(len16, EQ_ESIZE / 16);
2545 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2549 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2550 drain_wrq_wr_list(sc, wrq);
2552 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2555 wr = alloc_wrqe(len16 * 16, wrq);
2556 if (__predict_false(wr == NULL))
2559 cookie->ndesc = ndesc;
2563 eq->cidx = read_hw_cidx(eq);
2564 if (eq->pidx == eq->cidx)
2565 available = eq->sidx - 1;
2567 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2568 if (available < ndesc)
2571 cookie->pidx = eq->pidx;
2572 cookie->ndesc = ndesc;
2573 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2575 w = &eq->desc[eq->pidx];
2576 IDXINCR(eq->pidx, ndesc, eq->sidx);
2577 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2579 wrq->ss_pidx = cookie->pidx;
2580 wrq->ss_len = len16 * 16;
2589 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2591 struct sge_eq *eq = &wrq->eq;
2592 struct adapter *sc = wrq->adapter;
2594 struct wrq_cookie *prev, *next;
2596 if (cookie->pidx == -1) {
2597 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2603 if (__predict_false(w == &wrq->ss[0])) {
2604 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2606 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2607 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2608 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2611 wrq->tx_wrs_direct++;
2614 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2615 pidx = cookie->pidx;
2616 MPASS(pidx >= 0 && pidx < eq->sidx);
2617 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2618 next = TAILQ_NEXT(cookie, link);
2620 MPASS(pidx == eq->dbidx);
2621 if (next == NULL || ndesc >= 16) {
2623 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2626 * Note that the WR via which we'll request tx updates
2627 * is at pidx and not eq->pidx, which has moved on
2630 dst = (void *)&eq->desc[pidx];
2631 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2632 if (available < eq->sidx / 4 &&
2633 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2634 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2636 eq->equeqidx = pidx;
2637 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2638 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2639 eq->equeqidx = pidx;
2642 ring_eq_db(wrq->adapter, eq, ndesc);
2644 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2646 next->ndesc += ndesc;
2649 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2650 prev->ndesc += ndesc;
2652 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2654 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2655 drain_wrq_wr_list(sc, wrq);
2658 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2659 /* Doorbell must have caught up to the pidx. */
2660 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2667 can_resume_eth_tx(struct mp_ring *r)
2669 struct sge_eq *eq = r->cookie;
2671 return (total_available_tx_desc(eq) > eq->sidx / 8);
2675 cannot_use_txpkts(struct mbuf *m)
2677 /* maybe put a GL limit too, to avoid silliness? */
2679 return (needs_tso(m));
2683 discard_tx(struct sge_eq *eq)
2686 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2690 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2691 * be consumed. Return the actual number consumed. 0 indicates a stall.
2694 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2696 struct sge_txq *txq = r->cookie;
2697 struct sge_eq *eq = &txq->eq;
2698 struct ifnet *ifp = txq->ifp;
2699 struct vi_info *vi = ifp->if_softc;
2700 struct port_info *pi = vi->pi;
2701 struct adapter *sc = pi->adapter;
2702 u_int total, remaining; /* # of packets */
2703 u_int available, dbdiff; /* # of hardware descriptors */
2705 struct mbuf *m0, *tail;
2707 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2709 remaining = IDXDIFF(pidx, cidx, r->size);
2710 MPASS(remaining > 0); /* Must not be called without work to do. */
2714 if (__predict_false(discard_tx(eq))) {
2715 while (cidx != pidx) {
2716 m0 = r->items[cidx];
2718 if (++cidx == r->size)
2721 reclaim_tx_descs(txq, 2048);
2726 /* How many hardware descriptors do we have readily available. */
2727 if (eq->pidx == eq->cidx)
2728 available = eq->sidx - 1;
2730 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2731 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2733 while (remaining > 0) {
2735 m0 = r->items[cidx];
2737 MPASS(m0->m_nextpkt == NULL);
2739 if (available < SGE_MAX_WR_NDESC) {
2740 available += reclaim_tx_descs(txq, 64);
2741 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2742 break; /* out of descriptors */
2745 next_cidx = cidx + 1;
2746 if (__predict_false(next_cidx == r->size))
2749 wr = (void *)&eq->desc[eq->pidx];
2750 if (sc->flags & IS_VF) {
2753 ETHER_BPF_MTAP(ifp, m0);
2754 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2756 } else if (remaining > 1 &&
2757 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2759 /* pkts at cidx, next_cidx should both be in txp. */
2760 MPASS(txp.npkt == 2);
2761 tail = r->items[next_cidx];
2762 MPASS(tail->m_nextpkt == NULL);
2763 ETHER_BPF_MTAP(ifp, m0);
2764 ETHER_BPF_MTAP(ifp, tail);
2765 m0->m_nextpkt = tail;
2767 if (__predict_false(++next_cidx == r->size))
2770 while (next_cidx != pidx) {
2771 if (add_to_txpkts(r->items[next_cidx], &txp,
2774 tail->m_nextpkt = r->items[next_cidx];
2775 tail = tail->m_nextpkt;
2776 ETHER_BPF_MTAP(ifp, tail);
2777 if (__predict_false(++next_cidx == r->size))
2781 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2783 remaining -= txp.npkt;
2787 ETHER_BPF_MTAP(ifp, m0);
2788 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2790 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2794 IDXINCR(eq->pidx, n, eq->sidx);
2796 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2797 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2798 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2800 eq->equeqidx = eq->pidx;
2801 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2802 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2803 eq->equeqidx = eq->pidx;
2806 if (dbdiff >= 16 && remaining >= 4) {
2807 ring_eq_db(sc, eq, dbdiff);
2808 available += reclaim_tx_descs(txq, 4 * dbdiff);
2815 ring_eq_db(sc, eq, dbdiff);
2816 reclaim_tx_descs(txq, 32);
2825 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2829 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2830 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2831 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2832 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2836 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2837 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2838 if (pktc_idx >= 0) {
2839 iq->intr_params |= F_QINTR_CNT_EN;
2840 iq->intr_pktc_idx = pktc_idx;
2842 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2843 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2847 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2851 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2852 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2853 if (sc->flags & BUF_PACKING_OK &&
2854 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2855 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2856 fl->flags |= FL_BUF_PACKING;
2857 find_best_refill_source(sc, fl, maxp);
2858 find_safe_refill_source(sc, fl);
2862 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2863 uint8_t tx_chan, uint16_t iqid, char *name)
2865 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2867 eq->flags = eqtype & EQ_TYPEMASK;
2868 eq->tx_chan = tx_chan;
2870 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2871 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2875 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2876 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2880 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2881 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2883 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2887 rc = bus_dmamem_alloc(*tag, va,
2888 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2890 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2894 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2896 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2901 free_ring(sc, *tag, *map, *pa, *va);
2907 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2908 bus_addr_t pa, void *va)
2911 bus_dmamap_unload(tag, map);
2913 bus_dmamem_free(tag, va, map);
2915 bus_dma_tag_destroy(tag);
2921 * Allocates the ring for an ingress queue and an optional freelist. If the
2922 * freelist is specified it will be allocated and then associated with the
2925 * Returns errno on failure. Resources allocated up to that point may still be
2926 * allocated. Caller is responsible for cleanup in case this function fails.
2928 * If the ingress queue will take interrupts directly then the intr_idx
2929 * specifies the vector, starting from 0. -1 means the interrupts for this
2930 * queue should be forwarded to the fwq.
2933 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2934 int intr_idx, int cong)
2936 int rc, i, cntxt_id;
2939 struct port_info *pi = vi->pi;
2940 struct adapter *sc = iq->adapter;
2941 struct sge_params *sp = &sc->params.sge;
2944 len = iq->qsize * IQ_ESIZE;
2945 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2946 (void **)&iq->desc);
2950 bzero(&c, sizeof(c));
2951 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2952 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2953 V_FW_IQ_CMD_VFN(0));
2955 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2958 /* Special handling for firmware event queue */
2959 if (iq == &sc->sge.fwq)
2960 v |= F_FW_IQ_CMD_IQASYNCH;
2963 /* Forwarded interrupts, all headed to fwq */
2964 v |= F_FW_IQ_CMD_IQANDST;
2965 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
2967 KASSERT(intr_idx < sc->intr_count,
2968 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2969 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2972 c.type_to_iqandstindex = htobe32(v |
2973 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2974 V_FW_IQ_CMD_VIID(vi->viid) |
2975 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2976 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2977 F_FW_IQ_CMD_IQGTSMODE |
2978 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2979 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2980 c.iqsize = htobe16(iq->qsize);
2981 c.iqaddr = htobe64(iq->ba);
2983 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2986 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2988 len = fl->qsize * EQ_ESIZE;
2989 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2990 &fl->ba, (void **)&fl->desc);
2994 /* Allocate space for one software descriptor per buffer. */
2995 rc = alloc_fl_sdesc(fl);
2997 device_printf(sc->dev,
2998 "failed to setup fl software descriptors: %d\n",
3003 if (fl->flags & FL_BUF_PACKING) {
3004 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3005 fl->buf_boundary = sp->pack_boundary;
3007 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3008 fl->buf_boundary = 16;
3010 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3011 fl->buf_boundary = sp->pad_boundary;
3013 c.iqns_to_fl0congen |=
3014 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3015 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3016 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3017 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3020 c.iqns_to_fl0congen |=
3021 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3022 F_FW_IQ_CMD_FL0CONGCIF |
3023 F_FW_IQ_CMD_FL0CONGEN);
3025 c.fl0dcaen_to_fl0cidxfthresh =
3026 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3027 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
3028 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3029 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3030 c.fl0size = htobe16(fl->qsize);
3031 c.fl0addr = htobe64(fl->ba);
3034 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3036 device_printf(sc->dev,
3037 "failed to create ingress queue: %d\n", rc);
3042 iq->gen = F_RSPD_GEN;
3043 iq->intr_next = iq->intr_params;
3044 iq->cntxt_id = be16toh(c.iqid);
3045 iq->abs_id = be16toh(c.physiqid);
3046 iq->flags |= IQ_ALLOCATED;
3048 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3049 if (cntxt_id >= sc->sge.niq) {
3050 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3051 cntxt_id, sc->sge.niq - 1);
3053 sc->sge.iqmap[cntxt_id] = iq;
3058 iq->flags |= IQ_HAS_FL;
3059 fl->cntxt_id = be16toh(c.fl0id);
3060 fl->pidx = fl->cidx = 0;
3062 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3063 if (cntxt_id >= sc->sge.neq) {
3064 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3065 __func__, cntxt_id, sc->sge.neq - 1);
3067 sc->sge.eqmap[cntxt_id] = (void *)fl;
3070 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3071 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3072 uint32_t mask = (1 << s_qpp) - 1;
3073 volatile uint8_t *udb;
3075 udb = sc->udbs_base + UDBS_DB_OFFSET;
3076 udb += (qid >> s_qpp) << PAGE_SHIFT;
3078 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3079 udb += qid << UDBS_SEG_SHIFT;
3082 fl->udb = (volatile void *)udb;
3084 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3087 /* Enough to make sure the SGE doesn't think it's starved */
3088 refill_fl(sc, fl, fl->lowat);
3092 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3093 uint32_t param, val;
3095 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3096 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3097 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3102 for (i = 0; i < 4; i++) {
3103 if (cong & (1 << i))
3104 val |= 1 << (i << 2);
3108 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3110 /* report error but carry on */
3111 device_printf(sc->dev,
3112 "failed to set congestion manager context for "
3113 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3117 /* Enable IQ interrupts */
3118 atomic_store_rel_int(&iq->state, IQS_IDLE);
3119 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3120 V_INGRESSQID(iq->cntxt_id));
3126 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3129 struct adapter *sc = iq->adapter;
3133 return (0); /* nothing to do */
3135 dev = vi ? vi->dev : sc->dev;
3137 if (iq->flags & IQ_ALLOCATED) {
3138 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3139 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3140 fl ? fl->cntxt_id : 0xffff, 0xffff);
3143 "failed to free queue %p: %d\n", iq, rc);
3146 iq->flags &= ~IQ_ALLOCATED;
3149 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3151 bzero(iq, sizeof(*iq));
3154 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3158 free_fl_sdesc(sc, fl);
3160 if (mtx_initialized(&fl->fl_lock))
3161 mtx_destroy(&fl->fl_lock);
3163 bzero(fl, sizeof(*fl));
3170 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3173 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3175 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3176 "bus address of descriptor ring");
3177 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3178 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3179 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3180 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I",
3181 "absolute id of the queue");
3182 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3183 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I",
3184 "SGE context id of the queue");
3185 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3186 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
3191 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3192 struct sysctl_oid *oid, struct sge_fl *fl)
3194 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3196 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3198 children = SYSCTL_CHILDREN(oid);
3200 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3201 &fl->ba, "bus address of descriptor ring");
3202 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3203 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3204 "desc ring size in bytes");
3205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3206 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
3207 "SGE context id of the freelist");
3208 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3209 fl_pad ? 1 : 0, "padding enabled");
3210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3211 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3213 0, "consumer index");
3214 if (fl->flags & FL_BUF_PACKING) {
3215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3216 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3218 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3219 0, "producer index");
3220 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
3221 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
3222 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
3223 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
3224 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3225 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3226 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3227 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3228 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3229 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3233 alloc_fwq(struct adapter *sc)
3236 struct sge_iq *fwq = &sc->sge.fwq;
3237 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3238 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3240 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3241 if (sc->flags & IS_VF)
3244 intr_idx = sc->intr_count > 1 ? 1 : 0;
3245 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3247 device_printf(sc->dev,
3248 "failed to create firmware event queue: %d\n", rc);
3252 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
3253 NULL, "firmware event queue");
3254 add_iq_sysctls(&sc->ctx, oid, fwq);
3260 free_fwq(struct adapter *sc)
3262 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3266 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3267 struct sysctl_oid *oid)
3271 struct sysctl_oid_list *children;
3273 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3275 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3276 sc->sge.fwq.cntxt_id, name);
3278 children = SYSCTL_CHILDREN(oid);
3279 snprintf(name, sizeof(name), "%d", idx);
3280 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3281 NULL, "ctrl queue");
3282 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3288 tnl_cong(struct port_info *pi, int drop)
3296 return (pi->rx_e_chan_map);
3300 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3301 struct sysctl_oid *oid)
3304 struct adapter *sc = vi->pi->adapter;
3305 struct sysctl_oid_list *children;
3308 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3309 tnl_cong(vi->pi, cong_drop));
3314 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3316 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3317 ("iq_base mismatch"));
3318 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3319 ("PF with non-zero iq_base"));
3322 * The freelist is just barely above the starvation threshold right now,
3323 * fill it up a bit more.
3326 refill_fl(sc, &rxq->fl, 128);
3327 FL_UNLOCK(&rxq->fl);
3329 #if defined(INET) || defined(INET6)
3330 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3333 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3335 if (vi->ifp->if_capenable & IFCAP_LRO)
3336 rxq->iq.flags |= IQ_LRO_ENABLED;
3340 children = SYSCTL_CHILDREN(oid);
3342 snprintf(name, sizeof(name), "%d", idx);
3343 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3345 children = SYSCTL_CHILDREN(oid);
3347 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3348 #if defined(INET) || defined(INET6)
3349 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3350 &rxq->lro.lro_queued, 0, NULL);
3351 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3352 &rxq->lro.lro_flushed, 0, NULL);
3354 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3355 &rxq->rxcsum, "# of times hardware assisted with checksum");
3356 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3357 CTLFLAG_RD, &rxq->vlan_extraction,
3358 "# of times hardware extracted 802.1Q tag");
3360 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3366 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3370 #if defined(INET) || defined(INET6)
3372 tcp_lro_free(&rxq->lro);
3373 rxq->lro.ifp = NULL;
3377 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3379 bzero(rxq, sizeof(*rxq));
3386 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3387 int intr_idx, int idx, struct sysctl_oid *oid)
3389 struct port_info *pi = vi->pi;
3391 struct sysctl_oid_list *children;
3394 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3398 children = SYSCTL_CHILDREN(oid);
3400 snprintf(name, sizeof(name), "%d", idx);
3401 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3403 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3404 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3410 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3414 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3416 bzero(ofld_rxq, sizeof(*ofld_rxq));
3424 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3425 int idx, struct sysctl_oid *oid)
3428 struct sysctl_oid_list *children;
3429 struct sysctl_ctx_list *ctx;
3432 struct adapter *sc = vi->pi->adapter;
3433 struct netmap_adapter *na = NA(vi->ifp);
3437 len = vi->qsize_rxq * IQ_ESIZE;
3438 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3439 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3443 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3444 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3445 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3451 nm_rxq->iq_cidx = 0;
3452 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3453 nm_rxq->iq_gen = F_RSPD_GEN;
3454 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3455 nm_rxq->fl_sidx = na->num_rx_desc;
3456 nm_rxq->intr_idx = intr_idx;
3457 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3460 children = SYSCTL_CHILDREN(oid);
3462 snprintf(name, sizeof(name), "%d", idx);
3463 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3465 children = SYSCTL_CHILDREN(oid);
3467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3468 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3469 "I", "absolute id of the queue");
3470 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3471 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3472 "I", "SGE context id of the queue");
3473 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3474 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3477 children = SYSCTL_CHILDREN(oid);
3478 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3480 children = SYSCTL_CHILDREN(oid);
3482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3483 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3484 "I", "SGE context id of the freelist");
3485 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3486 &nm_rxq->fl_cidx, 0, "consumer index");
3487 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3488 &nm_rxq->fl_pidx, 0, "producer index");
3495 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3497 struct adapter *sc = vi->pi->adapter;
3499 if (vi->flags & VI_INIT_DONE)
3500 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3502 MPASS(nm_rxq->iq_cntxt_id == 0);
3504 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3506 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3513 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3514 struct sysctl_oid *oid)
3518 struct port_info *pi = vi->pi;
3519 struct adapter *sc = pi->adapter;
3520 struct netmap_adapter *na = NA(vi->ifp);
3522 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3524 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3525 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3526 &nm_txq->ba, (void **)&nm_txq->desc);
3530 nm_txq->pidx = nm_txq->cidx = 0;
3531 nm_txq->sidx = na->num_tx_desc;
3533 nm_txq->iqidx = iqidx;
3534 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3535 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3536 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3537 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3538 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3540 snprintf(name, sizeof(name), "%d", idx);
3541 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3542 NULL, "netmap tx queue");
3543 children = SYSCTL_CHILDREN(oid);
3545 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3546 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3547 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3548 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3550 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3551 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3558 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3560 struct adapter *sc = vi->pi->adapter;
3562 if (vi->flags & VI_INIT_DONE)
3563 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3565 MPASS(nm_txq->cntxt_id == 0);
3567 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3575 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3578 struct fw_eq_ctrl_cmd c;
3579 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3581 bzero(&c, sizeof(c));
3583 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3584 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3585 V_FW_EQ_CTRL_CMD_VFN(0));
3586 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3587 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3588 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3589 c.physeqid_pkd = htobe32(0);
3590 c.fetchszm_to_iqid =
3591 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3592 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3593 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3595 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3596 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3597 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
3598 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3599 c.eqaddr = htobe64(eq->ba);
3601 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3603 device_printf(sc->dev,
3604 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3607 eq->flags |= EQ_ALLOCATED;
3609 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3610 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3611 if (cntxt_id >= sc->sge.neq)
3612 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3613 cntxt_id, sc->sge.neq - 1);
3614 sc->sge.eqmap[cntxt_id] = eq;
3620 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3623 struct fw_eq_eth_cmd c;
3624 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3626 bzero(&c, sizeof(c));
3628 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3629 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3630 V_FW_EQ_ETH_CMD_VFN(0));
3631 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3632 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3633 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3634 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3635 c.fetchszm_to_iqid =
3636 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3637 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3638 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3639 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3640 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3641 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3642 c.eqaddr = htobe64(eq->ba);
3644 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3646 device_printf(vi->dev,
3647 "failed to create Ethernet egress queue: %d\n", rc);
3650 eq->flags |= EQ_ALLOCATED;
3652 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3653 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3654 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3655 if (cntxt_id >= sc->sge.neq)
3656 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3657 cntxt_id, sc->sge.neq - 1);
3658 sc->sge.eqmap[cntxt_id] = eq;
3663 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3665 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3668 struct fw_eq_ofld_cmd c;
3669 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3671 bzero(&c, sizeof(c));
3673 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3674 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3675 V_FW_EQ_OFLD_CMD_VFN(0));
3676 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3677 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3678 c.fetchszm_to_iqid =
3679 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3680 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3681 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3683 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3684 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3685 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3686 c.eqaddr = htobe64(eq->ba);
3688 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3690 device_printf(vi->dev,
3691 "failed to create egress queue for TCP offload: %d\n", rc);
3694 eq->flags |= EQ_ALLOCATED;
3696 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3697 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3698 if (cntxt_id >= sc->sge.neq)
3699 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3700 cntxt_id, sc->sge.neq - 1);
3701 sc->sge.eqmap[cntxt_id] = eq;
3708 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3713 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3715 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3716 len = qsize * EQ_ESIZE;
3717 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3718 &eq->ba, (void **)&eq->desc);
3722 eq->pidx = eq->cidx = 0;
3723 eq->equeqidx = eq->dbidx = 0;
3724 eq->doorbells = sc->doorbells;
3726 switch (eq->flags & EQ_TYPEMASK) {
3728 rc = ctrl_eq_alloc(sc, eq);
3732 rc = eth_eq_alloc(sc, vi, eq);
3735 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3737 rc = ofld_eq_alloc(sc, vi, eq);
3742 panic("%s: invalid eq type %d.", __func__,
3743 eq->flags & EQ_TYPEMASK);
3746 device_printf(sc->dev,
3747 "failed to allocate egress queue(%d): %d\n",
3748 eq->flags & EQ_TYPEMASK, rc);
3751 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3752 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3753 isset(&eq->doorbells, DOORBELL_WCWR)) {
3754 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3755 uint32_t mask = (1 << s_qpp) - 1;
3756 volatile uint8_t *udb;
3758 udb = sc->udbs_base + UDBS_DB_OFFSET;
3759 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3760 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3761 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3762 clrbit(&eq->doorbells, DOORBELL_WCWR);
3764 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3767 eq->udb = (volatile void *)udb;
3774 free_eq(struct adapter *sc, struct sge_eq *eq)
3778 if (eq->flags & EQ_ALLOCATED) {
3779 switch (eq->flags & EQ_TYPEMASK) {
3781 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3786 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3790 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3792 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3798 panic("%s: invalid eq type %d.", __func__,
3799 eq->flags & EQ_TYPEMASK);
3802 device_printf(sc->dev,
3803 "failed to free egress queue (%d): %d\n",
3804 eq->flags & EQ_TYPEMASK, rc);
3807 eq->flags &= ~EQ_ALLOCATED;
3810 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3812 if (mtx_initialized(&eq->eq_lock))
3813 mtx_destroy(&eq->eq_lock);
3815 bzero(eq, sizeof(*eq));
3820 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3821 struct sysctl_oid *oid)
3824 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3825 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3827 rc = alloc_eq(sc, vi, &wrq->eq);
3832 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3833 TAILQ_INIT(&wrq->incomplete_wrs);
3834 STAILQ_INIT(&wrq->wr_list);
3835 wrq->nwr_pending = 0;
3836 wrq->ndesc_needed = 0;
3838 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3839 &wrq->eq.ba, "bus address of descriptor ring");
3840 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3841 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3842 "desc ring size in bytes");
3843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3844 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3845 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3846 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3849 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3851 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3852 wrq->eq.sidx, "status page index");
3853 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3854 &wrq->tx_wrs_direct, "# of work requests (direct)");
3855 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3856 &wrq->tx_wrs_copied, "# of work requests (copied)");
3857 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3858 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3864 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3868 rc = free_eq(sc, &wrq->eq);
3872 bzero(wrq, sizeof(*wrq));
3877 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3878 struct sysctl_oid *oid)
3881 struct port_info *pi = vi->pi;
3882 struct adapter *sc = pi->adapter;
3883 struct sge_eq *eq = &txq->eq;
3885 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3887 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3890 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3894 rc = alloc_eq(sc, vi, eq);
3896 mp_ring_free(txq->r);
3901 /* Can't fail after this point. */
3904 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3906 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3907 ("eq_base mismatch"));
3908 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3909 ("PF with non-zero eq_base"));
3911 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3913 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3914 if (sc->flags & IS_VF)
3915 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3916 V_TXPKT_INTF(pi->tx_chan));
3918 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3919 V_TXPKT_INTF(pi->tx_chan) |
3920 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3921 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3922 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3924 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3927 snprintf(name, sizeof(name), "%d", idx);
3928 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3930 children = SYSCTL_CHILDREN(oid);
3932 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3933 &eq->ba, "bus address of descriptor ring");
3934 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3935 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3936 "desc ring size in bytes");
3937 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3938 &eq->abs_id, 0, "absolute id of the queue");
3939 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3940 &eq->cntxt_id, 0, "SGE context id of the queue");
3941 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3942 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3944 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3945 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3947 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3948 eq->sidx, "status page index");
3950 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3951 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3952 "traffic class (-1 means none)");
3954 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3955 &txq->txcsum, "# of times hardware assisted with checksum");
3956 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3957 CTLFLAG_RD, &txq->vlan_insertion,
3958 "# of times hardware inserted 802.1Q tag");
3959 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3960 &txq->tso_wrs, "# of TSO work requests");
3961 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3962 &txq->imm_wrs, "# of work requests with immediate data");
3963 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3964 &txq->sgl_wrs, "# of work requests with direct SGL");
3965 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3966 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3967 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3968 CTLFLAG_RD, &txq->txpkts0_wrs,
3969 "# of txpkts (type 0) work requests");
3970 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3971 CTLFLAG_RD, &txq->txpkts1_wrs,
3972 "# of txpkts (type 1) work requests");
3973 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3974 CTLFLAG_RD, &txq->txpkts0_pkts,
3975 "# of frames tx'd using type0 txpkts work requests");
3976 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3977 CTLFLAG_RD, &txq->txpkts1_pkts,
3978 "# of frames tx'd using type1 txpkts work requests");
3980 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3981 CTLFLAG_RD, &txq->r->enqueues,
3982 "# of enqueues to the mp_ring for this queue");
3983 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3984 CTLFLAG_RD, &txq->r->drops,
3985 "# of drops in the mp_ring for this queue");
3986 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3987 CTLFLAG_RD, &txq->r->starts,
3988 "# of normal consumer starts in the mp_ring for this queue");
3989 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3990 CTLFLAG_RD, &txq->r->stalls,
3991 "# of consumer stalls in the mp_ring for this queue");
3992 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3993 CTLFLAG_RD, &txq->r->restarts,
3994 "# of consumer restarts in the mp_ring for this queue");
3995 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3996 CTLFLAG_RD, &txq->r->abdications,
3997 "# of consumer abdications in the mp_ring for this queue");
4003 free_txq(struct vi_info *vi, struct sge_txq *txq)
4006 struct adapter *sc = vi->pi->adapter;
4007 struct sge_eq *eq = &txq->eq;
4009 rc = free_eq(sc, eq);
4013 sglist_free(txq->gl);
4014 free(txq->sdesc, M_CXGBE);
4015 mp_ring_free(txq->r);
4017 bzero(txq, sizeof(*txq));
4022 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4024 bus_addr_t *ba = arg;
4027 ("%s meant for single segment mappings only.", __func__));
4029 *ba = error ? 0 : segs->ds_addr;
4033 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4037 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
4041 v = fl->dbval | V_PIDX(n);
4043 *fl->udb = htole32(v);
4045 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4046 IDXINCR(fl->dbidx, n, fl->sidx);
4050 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4051 * recycled do not count towards this allocation budget.
4053 * Returns non-zero to indicate that this freelist should be added to the list
4054 * of starving freelists.
4057 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4060 struct fl_sdesc *sd;
4063 struct cluster_layout *cll;
4064 struct sw_zone_info *swz;
4065 struct cluster_metadata *clm;
4067 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4069 FL_LOCK_ASSERT_OWNED(fl);
4072 * We always stop at the beginning of the hardware descriptor that's just
4073 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4074 * which would mean an empty freelist to the chip.
4076 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4077 if (fl->pidx == max_pidx * 8)
4080 d = &fl->desc[fl->pidx];
4081 sd = &fl->sdesc[fl->pidx];
4082 cll = &fl->cll_def; /* default layout */
4083 swz = &sc->sge.sw_zone_info[cll->zidx];
4087 if (sd->cl != NULL) {
4089 if (sd->nmbuf == 0) {
4091 * Fast recycle without involving any atomics on
4092 * the cluster's metadata (if the cluster has
4093 * metadata). This happens when all frames
4094 * received in the cluster were small enough to
4095 * fit within a single mbuf each.
4097 fl->cl_fast_recycled++;
4099 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4101 MPASS(clm->refcount == 1);
4107 * Cluster is guaranteed to have metadata. Clusters
4108 * without metadata always take the fast recycle path
4109 * when they're recycled.
4111 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4114 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4116 counter_u64_add(extfree_rels, 1);
4119 sd->cl = NULL; /* gave up my reference */
4121 MPASS(sd->cl == NULL);
4123 cl = uma_zalloc(swz->zone, M_NOWAIT);
4124 if (__predict_false(cl == NULL)) {
4125 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
4126 fl->cll_def.zidx == fl->cll_alt.zidx)
4129 /* fall back to the safe zone */
4131 swz = &sc->sge.sw_zone_info[cll->zidx];
4137 pa = pmap_kextract((vm_offset_t)cl);
4141 *d = htobe64(pa | cll->hwidx);
4142 clm = cl_metadata(sc, fl, cll, cl);
4154 if (__predict_false(++fl->pidx % 8 == 0)) {
4155 uint16_t pidx = fl->pidx / 8;
4157 if (__predict_false(pidx == fl->sidx)) {
4163 if (pidx == max_pidx)
4166 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4171 if (fl->pidx / 8 != fl->dbidx)
4174 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4178 * Attempt to refill all starving freelists.
4181 refill_sfl(void *arg)
4183 struct adapter *sc = arg;
4184 struct sge_fl *fl, *fl_temp;
4186 mtx_assert(&sc->sfl_lock, MA_OWNED);
4187 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4189 refill_fl(sc, fl, 64);
4190 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4191 TAILQ_REMOVE(&sc->sfl, fl, link);
4192 fl->flags &= ~FL_STARVING;
4197 if (!TAILQ_EMPTY(&sc->sfl))
4198 callout_schedule(&sc->sfl_callout, hz / 5);
4202 alloc_fl_sdesc(struct sge_fl *fl)
4205 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4212 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4214 struct fl_sdesc *sd;
4215 struct cluster_metadata *clm;
4216 struct cluster_layout *cll;
4220 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4225 clm = cl_metadata(sc, fl, cll, sd->cl);
4227 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4228 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4229 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4230 counter_u64_add(extfree_rels, 1);
4235 free(fl->sdesc, M_CXGBE);
4240 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4247 rc = sglist_append_mbuf(gl, m);
4248 if (__predict_false(rc != 0)) {
4249 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4250 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4253 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4254 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4255 mbuf_nsegs(m), gl->sg_nseg));
4256 KASSERT(gl->sg_nseg > 0 &&
4257 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4258 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4259 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4263 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4266 txpkt_len16(u_int nsegs, u_int tso)
4272 nsegs--; /* first segment is part of ulptx_sgl */
4273 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4274 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4276 n += sizeof(struct cpl_tx_pkt_lso_core);
4278 return (howmany(n, 16));
4282 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4286 txpkt_vm_len16(u_int nsegs, u_int tso)
4292 nsegs--; /* first segment is part of ulptx_sgl */
4293 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4294 sizeof(struct cpl_tx_pkt_core) +
4295 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4297 n += sizeof(struct cpl_tx_pkt_lso_core);
4299 return (howmany(n, 16));
4303 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4307 txpkts0_len16(u_int nsegs)
4313 nsegs--; /* first segment is part of ulptx_sgl */
4314 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4315 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4316 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4318 return (howmany(n, 16));
4322 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4330 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4332 return (howmany(n, 16));
4336 imm_payload(u_int ndesc)
4340 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4341 sizeof(struct cpl_tx_pkt_core);
4347 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4348 * software descriptor, and advance the pidx. It is guaranteed that enough
4349 * descriptors are available.
4351 * The return value is the # of hardware descriptors used.
4354 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4355 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4357 struct sge_eq *eq = &txq->eq;
4358 struct tx_sdesc *txsd;
4359 struct cpl_tx_pkt_core *cpl;
4360 uint32_t ctrl; /* used in many unrelated places */
4362 int csum_type, len16, ndesc, pktlen, nsegs;
4365 TXQ_LOCK_ASSERT_OWNED(txq);
4367 MPASS(available > 0 && available < eq->sidx);
4369 len16 = mbuf_len16(m0);
4370 nsegs = mbuf_nsegs(m0);
4371 pktlen = m0->m_pkthdr.len;
4372 ctrl = sizeof(struct cpl_tx_pkt_core);
4374 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4375 ndesc = howmany(len16, EQ_ESIZE / 16);
4376 MPASS(ndesc <= available);
4378 /* Firmware work request header */
4379 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4380 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4381 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4383 ctrl = V_FW_WR_LEN16(len16);
4384 wr->equiq_to_len16 = htobe32(ctrl);
4389 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4390 * vlantci is ignored unless the ethtype is 0x8100, so it's
4391 * simpler to always copy it rather than making it
4392 * conditional. Also, it seems that we do not have to set
4393 * vlantci or fake the ethtype when doing VLAN tag insertion.
4395 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4398 if (needs_tso(m0)) {
4399 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4401 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4402 m0->m_pkthdr.l4hlen > 0,
4403 ("%s: mbuf %p needs TSO but missing header lengths",
4406 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4407 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4408 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4409 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4410 ctrl |= V_LSO_ETHHDR_LEN(1);
4411 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4414 lso->lso_ctrl = htobe32(ctrl);
4415 lso->ipid_ofst = htobe16(0);
4416 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4417 lso->seqno_offset = htobe32(0);
4418 lso->len = htobe32(pktlen);
4420 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4421 csum_type = TX_CSUM_TCPIP6;
4423 csum_type = TX_CSUM_TCPIP;
4425 cpl = (void *)(lso + 1);
4429 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4430 csum_type = TX_CSUM_TCPIP;
4431 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4432 csum_type = TX_CSUM_UDPIP;
4433 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4434 csum_type = TX_CSUM_TCPIP6;
4435 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4436 csum_type = TX_CSUM_UDPIP6;
4438 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4440 * XXX: The firmware appears to stomp on the
4441 * fragment/flags field of the IP header when
4442 * using TX_CSUM_IP. Fall back to doing
4443 * software checksums.
4451 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4452 offsetof(struct ip, ip_sum));
4453 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4454 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4455 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4459 cpl = (void *)(wr + 1);
4462 /* Checksum offload */
4464 if (needs_l3_csum(m0) == 0)
4465 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4466 if (csum_type >= 0) {
4467 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4468 ("%s: mbuf %p needs checksum offload but missing header lengths",
4471 if (chip_id(sc) <= CHELSIO_T5) {
4472 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4475 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4478 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4479 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4481 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4482 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4483 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4484 txq->txcsum++; /* some hardware assistance provided */
4486 /* VLAN tag insertion */
4487 if (needs_vlan_insertion(m0)) {
4488 ctrl1 |= F_TXPKT_VLAN_VLD |
4489 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4490 txq->vlan_insertion++;
4494 cpl->ctrl0 = txq->cpl_ctrl0;
4496 cpl->len = htobe16(pktlen);
4497 cpl->ctrl1 = htobe64(ctrl1);
4500 dst = (void *)(cpl + 1);
4503 * A packet using TSO will use up an entire descriptor for the
4504 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4505 * If this descriptor is the last descriptor in the ring, wrap
4506 * around to the front of the ring explicitly for the start of
4509 if (dst == (void *)&eq->desc[eq->sidx]) {
4510 dst = (void *)&eq->desc[0];
4511 write_gl_to_txd(txq, m0, &dst, 0);
4513 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4518 txsd = &txq->sdesc[eq->pidx];
4520 txsd->desc_used = ndesc;
4526 * Write a txpkt WR for this packet to the hardware descriptors, update the
4527 * software descriptor, and advance the pidx. It is guaranteed that enough
4528 * descriptors are available.
4530 * The return value is the # of hardware descriptors used.
4533 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4534 struct mbuf *m0, u_int available)
4536 struct sge_eq *eq = &txq->eq;
4537 struct tx_sdesc *txsd;
4538 struct cpl_tx_pkt_core *cpl;
4539 uint32_t ctrl; /* used in many unrelated places */
4541 int len16, ndesc, pktlen, nsegs;
4544 TXQ_LOCK_ASSERT_OWNED(txq);
4546 MPASS(available > 0 && available < eq->sidx);
4548 len16 = mbuf_len16(m0);
4549 nsegs = mbuf_nsegs(m0);
4550 pktlen = m0->m_pkthdr.len;
4551 ctrl = sizeof(struct cpl_tx_pkt_core);
4553 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4554 else if (pktlen <= imm_payload(2) && available >= 2) {
4555 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4557 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4558 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4561 ndesc = howmany(len16, EQ_ESIZE / 16);
4562 MPASS(ndesc <= available);
4564 /* Firmware work request header */
4565 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4566 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4567 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4569 ctrl = V_FW_WR_LEN16(len16);
4570 wr->equiq_to_len16 = htobe32(ctrl);
4573 if (needs_tso(m0)) {
4574 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4576 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4577 m0->m_pkthdr.l4hlen > 0,
4578 ("%s: mbuf %p needs TSO but missing header lengths",
4581 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4582 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4583 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4584 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4585 ctrl |= V_LSO_ETHHDR_LEN(1);
4586 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4589 lso->lso_ctrl = htobe32(ctrl);
4590 lso->ipid_ofst = htobe16(0);
4591 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4592 lso->seqno_offset = htobe32(0);
4593 lso->len = htobe32(pktlen);
4595 cpl = (void *)(lso + 1);
4599 cpl = (void *)(wr + 1);
4601 /* Checksum offload */
4603 if (needs_l3_csum(m0) == 0)
4604 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4605 if (needs_l4_csum(m0) == 0)
4606 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4607 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4608 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4609 txq->txcsum++; /* some hardware assistance provided */
4611 /* VLAN tag insertion */
4612 if (needs_vlan_insertion(m0)) {
4613 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4614 txq->vlan_insertion++;
4618 cpl->ctrl0 = txq->cpl_ctrl0;
4620 cpl->len = htobe16(pktlen);
4621 cpl->ctrl1 = htobe64(ctrl1);
4624 dst = (void *)(cpl + 1);
4627 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4632 for (m = m0; m != NULL; m = m->m_next) {
4633 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4639 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4646 txsd = &txq->sdesc[eq->pidx];
4648 txsd->desc_used = ndesc;
4654 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4656 u_int needed, nsegs1, nsegs2, l1, l2;
4658 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4661 nsegs1 = mbuf_nsegs(m);
4662 nsegs2 = mbuf_nsegs(n);
4663 if (nsegs1 + nsegs2 == 2) {
4665 l1 = l2 = txpkts1_len16();
4668 l1 = txpkts0_len16(nsegs1);
4669 l2 = txpkts0_len16(nsegs2);
4671 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4672 needed = howmany(txp->len16, EQ_ESIZE / 16);
4673 if (needed > SGE_MAX_WR_NDESC || needed > available)
4676 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4677 if (txp->plen > 65535)
4681 set_mbuf_len16(m, l1);
4682 set_mbuf_len16(n, l2);
4688 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4690 u_int plen, len16, needed, nsegs;
4692 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4694 nsegs = mbuf_nsegs(m);
4695 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4698 plen = txp->plen + m->m_pkthdr.len;
4702 if (txp->wr_type == 0)
4703 len16 = txpkts0_len16(nsegs);
4705 len16 = txpkts1_len16();
4706 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4707 if (needed > SGE_MAX_WR_NDESC || needed > available)
4712 txp->len16 += len16;
4713 set_mbuf_len16(m, len16);
4719 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4720 * the software descriptor, and advance the pidx. It is guaranteed that enough
4721 * descriptors are available.
4723 * The return value is the # of hardware descriptors used.
4726 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4727 struct mbuf *m0, const struct txpkts *txp, u_int available)
4729 struct sge_eq *eq = &txq->eq;
4730 struct tx_sdesc *txsd;
4731 struct cpl_tx_pkt_core *cpl;
4734 int ndesc, checkwrap;
4738 TXQ_LOCK_ASSERT_OWNED(txq);
4739 MPASS(txp->npkt > 0);
4740 MPASS(txp->plen < 65536);
4742 MPASS(m0->m_nextpkt != NULL);
4743 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4744 MPASS(available > 0 && available < eq->sidx);
4746 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4747 MPASS(ndesc <= available);
4749 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4750 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4751 ctrl = V_FW_WR_LEN16(txp->len16);
4752 wr->equiq_to_len16 = htobe32(ctrl);
4753 wr->plen = htobe16(txp->plen);
4754 wr->npkt = txp->npkt;
4756 wr->type = txp->wr_type;
4760 * At this point we are 16B into a hardware descriptor. If checkwrap is
4761 * set then we know the WR is going to wrap around somewhere. We'll
4762 * check for that at appropriate points.
4764 checkwrap = eq->sidx - ndesc < eq->pidx;
4765 for (m = m0; m != NULL; m = m->m_nextpkt) {
4766 if (txp->wr_type == 0) {
4767 struct ulp_txpkt *ulpmc;
4768 struct ulptx_idata *ulpsc;
4770 /* ULP master command */
4772 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4773 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4774 ulpmc->len = htobe32(mbuf_len16(m));
4776 /* ULP subcommand */
4777 ulpsc = (void *)(ulpmc + 1);
4778 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4780 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4782 cpl = (void *)(ulpsc + 1);
4784 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4785 cpl = (void *)&eq->desc[0];
4790 /* Checksum offload */
4792 if (needs_l3_csum(m) == 0)
4793 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4794 if (needs_l4_csum(m) == 0)
4795 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4796 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4797 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4798 txq->txcsum++; /* some hardware assistance provided */
4800 /* VLAN tag insertion */
4801 if (needs_vlan_insertion(m)) {
4802 ctrl1 |= F_TXPKT_VLAN_VLD |
4803 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4804 txq->vlan_insertion++;
4808 cpl->ctrl0 = txq->cpl_ctrl0;
4810 cpl->len = htobe16(m->m_pkthdr.len);
4811 cpl->ctrl1 = htobe64(ctrl1);
4815 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4816 flitp = (void *)&eq->desc[0];
4818 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4822 if (txp->wr_type == 0) {
4823 txq->txpkts0_pkts += txp->npkt;
4826 txq->txpkts1_pkts += txp->npkt;
4830 txsd = &txq->sdesc[eq->pidx];
4832 txsd->desc_used = ndesc;
4838 * If the SGL ends on an address that is not 16 byte aligned, this function will
4839 * add a 0 filled flit at the end.
4842 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4844 struct sge_eq *eq = &txq->eq;
4845 struct sglist *gl = txq->gl;
4846 struct sglist_seg *seg;
4847 __be64 *flitp, *wrap;
4848 struct ulptx_sgl *usgl;
4849 int i, nflits, nsegs;
4851 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4852 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4853 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4854 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4857 nsegs = gl->sg_nseg;
4860 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4861 flitp = (__be64 *)(*to);
4862 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4863 seg = &gl->sg_segs[0];
4864 usgl = (void *)flitp;
4867 * We start at a 16 byte boundary somewhere inside the tx descriptor
4868 * ring, so we're at least 16 bytes away from the status page. There is
4869 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4872 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4873 V_ULPTX_NSGE(nsegs));
4874 usgl->len0 = htobe32(seg->ss_len);
4875 usgl->addr0 = htobe64(seg->ss_paddr);
4878 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4880 /* Won't wrap around at all */
4882 for (i = 0; i < nsegs - 1; i++, seg++) {
4883 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4884 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4887 usgl->sge[i / 2].len[1] = htobe32(0);
4891 /* Will wrap somewhere in the rest of the SGL */
4893 /* 2 flits already written, write the rest flit by flit */
4894 flitp = (void *)(usgl + 1);
4895 for (i = 0; i < nflits - 2; i++) {
4897 flitp = (void *)eq->desc;
4898 *flitp++ = get_flit(seg, nsegs - 1, i);
4903 MPASS(((uintptr_t)flitp) & 0xf);
4907 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4908 if (__predict_false(flitp == wrap))
4909 *to = (void *)eq->desc;
4911 *to = (void *)flitp;
4915 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4918 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4919 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4921 if (__predict_true((uintptr_t)(*to) + len <=
4922 (uintptr_t)&eq->desc[eq->sidx])) {
4923 bcopy(from, *to, len);
4926 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4928 bcopy(from, *to, portion);
4930 portion = len - portion; /* remaining */
4931 bcopy(from, (void *)eq->desc, portion);
4932 (*to) = (caddr_t)eq->desc + portion;
4937 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4945 clrbit(&db, DOORBELL_WCWR);
4948 switch (ffs(db) - 1) {
4950 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4953 case DOORBELL_WCWR: {
4954 volatile uint64_t *dst, *src;
4958 * Queues whose 128B doorbell segment fits in the page do not
4959 * use relative qid (udb_qid is always 0). Only queues with
4960 * doorbell segments can do WCWR.
4962 KASSERT(eq->udb_qid == 0 && n == 1,
4963 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4964 __func__, eq->doorbells, n, eq->dbidx, eq));
4966 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4969 src = (void *)&eq->desc[i];
4970 while (src != (void *)&eq->desc[i + 1])
4976 case DOORBELL_UDBWC:
4977 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4982 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4983 V_QID(eq->cntxt_id) | V_PIDX(n));
4987 IDXINCR(eq->dbidx, n, eq->sidx);
4991 reclaimable_tx_desc(struct sge_eq *eq)
4995 hw_cidx = read_hw_cidx(eq);
4996 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5000 total_available_tx_desc(struct sge_eq *eq)
5002 uint16_t hw_cidx, pidx;
5004 hw_cidx = read_hw_cidx(eq);
5007 if (pidx == hw_cidx)
5008 return (eq->sidx - 1);
5010 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5013 static inline uint16_t
5014 read_hw_cidx(struct sge_eq *eq)
5016 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5017 uint16_t cidx = spg->cidx; /* stable snapshot */
5019 return (be16toh(cidx));
5023 * Reclaim 'n' descriptors approximately.
5026 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5028 struct tx_sdesc *txsd;
5029 struct sge_eq *eq = &txq->eq;
5030 u_int can_reclaim, reclaimed;
5032 TXQ_LOCK_ASSERT_OWNED(txq);
5036 can_reclaim = reclaimable_tx_desc(eq);
5037 while (can_reclaim && reclaimed < n) {
5039 struct mbuf *m, *nextpkt;
5041 txsd = &txq->sdesc[eq->cidx];
5042 ndesc = txsd->desc_used;
5044 /* Firmware doesn't return "partial" credits. */
5045 KASSERT(can_reclaim >= ndesc,
5046 ("%s: unexpected number of credits: %d, %d",
5047 __func__, can_reclaim, ndesc));
5049 for (m = txsd->m; m != NULL; m = nextpkt) {
5050 nextpkt = m->m_nextpkt;
5051 m->m_nextpkt = NULL;
5055 can_reclaim -= ndesc;
5056 IDXINCR(eq->cidx, ndesc, eq->sidx);
5063 tx_reclaim(void *arg, int n)
5065 struct sge_txq *txq = arg;
5066 struct sge_eq *eq = &txq->eq;
5069 if (TXQ_TRYLOCK(txq) == 0)
5071 n = reclaim_tx_descs(txq, 32);
5072 if (eq->cidx == eq->pidx)
5073 eq->equeqidx = eq->pidx;
5079 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5081 int i = (idx / 3) * 2;
5087 rc = (uint64_t)segs[i].ss_len << 32;
5089 rc |= (uint64_t)(segs[i + 1].ss_len);
5091 return (htobe64(rc));
5094 return (htobe64(segs[i].ss_paddr));
5096 return (htobe64(segs[i + 1].ss_paddr));
5103 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
5105 int8_t zidx, hwidx, idx;
5106 uint16_t region1, region3;
5107 int spare, spare_needed, n;
5108 struct sw_zone_info *swz;
5109 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
5112 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
5113 * large enough for the max payload and cluster metadata. Otherwise
5114 * settle for the largest bufsize that leaves enough room in the cluster
5117 * Without buffer packing: Look for the smallest zone which has a
5118 * bufsize large enough for the max payload. Settle for the largest
5119 * bufsize available if there's nothing big enough for max payload.
5121 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
5122 swz = &sc->sge.sw_zone_info[0];
5124 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
5125 if (swz->size > largest_rx_cluster) {
5126 if (__predict_true(hwidx != -1))
5130 * This is a misconfiguration. largest_rx_cluster is
5131 * preventing us from finding a refill source. See
5132 * dev.t5nex.<n>.buffer_sizes to figure out why.
5134 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
5135 " refill source for fl %p (dma %u). Ignored.\n",
5136 largest_rx_cluster, fl, maxp);
5138 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
5139 hwb = &hwb_list[idx];
5140 spare = swz->size - hwb->size;
5141 if (spare < spare_needed)
5144 hwidx = idx; /* best option so far */
5145 if (hwb->size >= maxp) {
5147 if ((fl->flags & FL_BUF_PACKING) == 0)
5148 goto done; /* stop looking (not packing) */
5150 if (swz->size >= safest_rx_cluster)
5151 goto done; /* stop looking (packing) */
5153 break; /* keep looking, next zone */
5157 /* A usable hwidx has been located. */
5159 hwb = &hwb_list[hwidx];
5161 swz = &sc->sge.sw_zone_info[zidx];
5163 region3 = swz->size - hwb->size;
5166 * Stay within this zone and see if there is a better match when mbuf
5167 * inlining is allowed. Remember that the hwidx's are sorted in
5168 * decreasing order of size (so in increasing order of spare area).
5170 for (idx = hwidx; idx != -1; idx = hwb->next) {
5171 hwb = &hwb_list[idx];
5172 spare = swz->size - hwb->size;
5174 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
5178 * Do not inline mbufs if doing so would violate the pad/pack
5179 * boundary alignment requirement.
5181 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
5183 if (fl->flags & FL_BUF_PACKING &&
5184 (MSIZE % sc->params.sge.pack_boundary) != 0)
5187 if (spare < CL_METADATA_SIZE + MSIZE)
5189 n = (spare - CL_METADATA_SIZE) / MSIZE;
5190 if (n > howmany(hwb->size, maxp))
5194 if (fl->flags & FL_BUF_PACKING) {
5195 region1 = n * MSIZE;
5196 region3 = spare - region1;
5199 region3 = spare - region1;
5204 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
5205 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
5206 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
5207 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
5208 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
5209 sc->sge.sw_zone_info[zidx].size,
5210 ("%s: bad buffer layout for fl %p, maxp %d. "
5211 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5212 sc->sge.sw_zone_info[zidx].size, region1,
5213 sc->sge.hw_buf_info[hwidx].size, region3));
5214 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
5215 KASSERT(region3 >= CL_METADATA_SIZE,
5216 ("%s: no room for metadata. fl %p, maxp %d; "
5217 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5218 sc->sge.sw_zone_info[zidx].size, region1,
5219 sc->sge.hw_buf_info[hwidx].size, region3));
5220 KASSERT(region1 % MSIZE == 0,
5221 ("%s: bad mbuf region for fl %p, maxp %d. "
5222 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5223 sc->sge.sw_zone_info[zidx].size, region1,
5224 sc->sge.hw_buf_info[hwidx].size, region3));
5227 fl->cll_def.zidx = zidx;
5228 fl->cll_def.hwidx = hwidx;
5229 fl->cll_def.region1 = region1;
5230 fl->cll_def.region3 = region3;
5234 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
5236 struct sge *s = &sc->sge;
5237 struct hw_buf_info *hwb;
5238 struct sw_zone_info *swz;
5242 if (fl->flags & FL_BUF_PACKING)
5243 hwidx = s->safe_hwidx2; /* with room for metadata */
5244 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
5245 hwidx = s->safe_hwidx2;
5246 hwb = &s->hw_buf_info[hwidx];
5247 swz = &s->sw_zone_info[hwb->zidx];
5248 spare = swz->size - hwb->size;
5250 /* no good if there isn't room for an mbuf as well */
5251 if (spare < CL_METADATA_SIZE + MSIZE)
5252 hwidx = s->safe_hwidx1;
5254 hwidx = s->safe_hwidx1;
5257 /* No fallback source */
5258 fl->cll_alt.hwidx = -1;
5259 fl->cll_alt.zidx = -1;
5264 hwb = &s->hw_buf_info[hwidx];
5265 swz = &s->sw_zone_info[hwb->zidx];
5266 spare = swz->size - hwb->size;
5267 fl->cll_alt.hwidx = hwidx;
5268 fl->cll_alt.zidx = hwb->zidx;
5269 if (allow_mbufs_in_cluster &&
5270 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5271 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5273 fl->cll_alt.region1 = 0;
5274 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5278 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5280 mtx_lock(&sc->sfl_lock);
5282 if ((fl->flags & FL_DOOMED) == 0) {
5283 fl->flags |= FL_STARVING;
5284 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5285 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5288 mtx_unlock(&sc->sfl_lock);
5292 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5294 struct sge_wrq *wrq = (void *)eq;
5296 atomic_readandclear_int(&eq->equiq);
5297 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5301 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5303 struct sge_txq *txq = (void *)eq;
5305 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5307 atomic_readandclear_int(&eq->equiq);
5308 mp_ring_check_drainage(txq->r, 0);
5309 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5313 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5316 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5317 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5318 struct adapter *sc = iq->adapter;
5319 struct sge *s = &sc->sge;
5321 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5322 &handle_wrq_egr_update, &handle_eth_egr_update,
5323 &handle_wrq_egr_update};
5325 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5328 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5329 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5334 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5335 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5336 offsetof(struct cpl_fw6_msg, data));
5339 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5341 struct adapter *sc = iq->adapter;
5342 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5344 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5347 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5348 const struct rss_header *rss2;
5350 rss2 = (const struct rss_header *)&cpl->data[0];
5351 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5354 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5358 * t4_handle_wrerr_rpl - process a FW work request error message
5359 * @adap: the adapter
5360 * @rpl: start of the FW message
5363 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5365 u8 opcode = *(const u8 *)rpl;
5366 const struct fw_error_cmd *e = (const void *)rpl;
5369 if (opcode != FW_ERROR_CMD) {
5371 "%s: Received WRERR_RPL message with opcode %#x\n",
5372 device_get_nameunit(adap->dev), opcode);
5375 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5376 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5378 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5379 case FW_ERROR_TYPE_EXCEPTION:
5380 log(LOG_ERR, "exception info:\n");
5381 for (i = 0; i < nitems(e->u.exception.info); i++)
5382 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5383 be32toh(e->u.exception.info[i]));
5386 case FW_ERROR_TYPE_HWMODULE:
5387 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5388 be32toh(e->u.hwmodule.regaddr),
5389 be32toh(e->u.hwmodule.regval));
5391 case FW_ERROR_TYPE_WR:
5392 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5393 be16toh(e->u.wr.cidx),
5394 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5395 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5396 be32toh(e->u.wr.eqid));
5397 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5398 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5402 case FW_ERROR_TYPE_ACL:
5403 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5404 be16toh(e->u.acl.cidx),
5405 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5406 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5407 be32toh(e->u.acl.eqid),
5408 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5410 for (i = 0; i < nitems(e->u.acl.val); i++)
5411 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5415 log(LOG_ERR, "type %#x\n",
5416 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5423 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5425 uint16_t *id = arg1;
5428 return sysctl_handle_int(oidp, &i, 0, req);
5432 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5434 struct sge *s = arg1;
5435 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5436 struct sw_zone_info *swz = &s->sw_zone_info[0];
5441 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5442 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5443 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5448 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5452 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5459 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5462 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
5468 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
5469 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
5470 if (__predict_false(nsegs == 0))
5473 nsegs--; /* first segment is part of ulptx_sgl */
5474 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5476 n += sizeof(struct cpl_tx_pkt_lso_core);
5479 return (howmany(n, 16));
5482 #define ETID_FLOWC_NPARAMS 6
5483 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
5484 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
5485 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
5488 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi,
5491 struct wrq_cookie cookie;
5492 u_int pfvf = G_FW_VIID_PFN(vi->viid) << S_FW_VIID_PFN;
5493 struct fw_flowc_wr *flowc;
5495 mtx_assert(&cst->lock, MA_OWNED);
5496 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
5499 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
5500 if (__predict_false(flowc == NULL))
5503 bzero(flowc, ETID_FLOWC_LEN);
5504 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5505 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
5506 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
5507 V_FW_WR_FLOWID(cst->etid));
5508 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
5509 flowc->mnemval[0].val = htobe32(pfvf);
5510 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
5511 flowc->mnemval[1].val = htobe32(pi->tx_chan);
5512 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
5513 flowc->mnemval[2].val = htobe32(pi->tx_chan);
5514 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
5515 flowc->mnemval[3].val = htobe32(cst->iqid);
5516 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
5517 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
5518 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
5519 flowc->mnemval[5].val = htobe32(cst->schedcl);
5521 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5523 cst->flags &= ~EO_FLOWC_PENDING;
5524 cst->flags |= EO_FLOWC_RPL_PENDING;
5525 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
5526 cst->tx_credits -= ETID_FLOWC_LEN16;
5531 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
5534 send_etid_flush_wr(struct cxgbe_snd_tag *cst)
5536 struct fw_flowc_wr *flowc;
5537 struct wrq_cookie cookie;
5539 mtx_assert(&cst->lock, MA_OWNED);
5541 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
5542 if (__predict_false(flowc == NULL))
5543 CXGBE_UNIMPLEMENTED(__func__);
5545 bzero(flowc, ETID_FLUSH_LEN16 * 16);
5546 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5547 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
5548 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
5549 V_FW_WR_FLOWID(cst->etid));
5551 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5553 cst->flags |= EO_FLUSH_RPL_PENDING;
5554 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
5555 cst->tx_credits -= ETID_FLUSH_LEN16;
5560 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr,
5561 struct mbuf *m0, int compl)
5563 struct cpl_tx_pkt_core *cpl;
5565 uint32_t ctrl; /* used in many unrelated places */
5566 int len16, pktlen, nsegs, immhdrs;
5569 struct ulptx_sgl *usgl;
5571 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
5573 mtx_assert(&cst->lock, MA_OWNED);
5575 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5576 m0->m_pkthdr.l4hlen > 0,
5577 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
5579 if (needs_udp_csum(m0)) {
5580 CXGBE_UNIMPLEMENTED("UDP ethofld");
5583 len16 = mbuf_eo_len16(m0);
5584 nsegs = mbuf_eo_nsegs(m0);
5585 pktlen = m0->m_pkthdr.len;
5586 ctrl = sizeof(struct cpl_tx_pkt_core);
5588 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5589 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
5592 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
5593 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
5594 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
5595 V_FW_WR_FLOWID(cst->etid));
5597 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
5598 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
5599 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5600 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
5601 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
5602 wr->u.tcpseg.r4 = 0;
5603 wr->u.tcpseg.r5 = 0;
5604 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
5606 if (needs_tso(m0)) {
5607 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
5609 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
5611 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
5612 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
5613 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5614 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
5615 ctrl |= V_LSO_ETHHDR_LEN(1);
5616 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5618 lso->lso_ctrl = htobe32(ctrl);
5619 lso->ipid_ofst = htobe16(0);
5620 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5621 lso->seqno_offset = htobe32(0);
5622 lso->len = htobe32(pktlen);
5624 cpl = (void *)(lso + 1);
5626 wr->u.tcpseg.mss = htobe16(0xffff);
5627 cpl = (void *)(wr + 1);
5630 /* Checksum offload must be requested for ethofld. */
5632 MPASS(needs_l4_csum(m0));
5634 /* VLAN tag insertion */
5635 if (needs_vlan_insertion(m0)) {
5636 ctrl1 |= F_TXPKT_VLAN_VLD |
5637 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5641 cpl->ctrl0 = cst->ctrl0;
5643 cpl->len = htobe16(pktlen);
5644 cpl->ctrl1 = htobe64(ctrl1);
5646 /* Copy Ethernet, IP & TCP hdrs as immediate data */
5647 p = (uintptr_t)(cpl + 1);
5648 m_copydata(m0, 0, immhdrs, (void *)p);
5651 dst = (void *)(cpl + 1);
5655 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
5657 pad = 16 - (immhdrs & 0xf);
5658 bzero((void *)p, pad);
5660 usgl = (void *)(p + pad);
5661 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5662 V_ULPTX_NSGE(nsegs));
5664 sglist_init(&sg, nitems(segs), segs);
5665 for (; m0 != NULL; m0 = m0->m_next) {
5666 if (__predict_false(m0->m_len == 0))
5668 if (immhdrs >= m0->m_len) {
5669 immhdrs -= m0->m_len;
5673 sglist_append(&sg, mtod(m0, char *) + immhdrs,
5674 m0->m_len - immhdrs);
5677 MPASS(sg.sg_nseg == nsegs);
5680 * Zero pad last 8B in case the WR doesn't end on a 16B
5683 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
5685 usgl->len0 = htobe32(segs[0].ss_len);
5686 usgl->addr0 = htobe64(segs[0].ss_paddr);
5687 for (i = 0; i < nsegs - 1; i++) {
5688 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
5689 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
5692 usgl->sge[i / 2].len[1] = htobe32(0);
5698 ethofld_tx(struct cxgbe_snd_tag *cst)
5701 struct wrq_cookie cookie;
5702 int next_credits, compl;
5703 struct fw_eth_tx_eo_wr *wr;
5705 mtx_assert(&cst->lock, MA_OWNED);
5707 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
5710 /* How many len16 credits do we need to send this mbuf. */
5711 next_credits = mbuf_eo_len16(m);
5712 MPASS(next_credits > 0);
5713 if (next_credits > cst->tx_credits) {
5715 * Tx will make progress eventually because there is at
5716 * least one outstanding fw4_ack that will return
5717 * credits and kick the tx.
5719 MPASS(cst->ncompl > 0);
5722 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
5723 if (__predict_false(wr == NULL)) {
5724 /* XXX: wishful thinking, not a real assertion. */
5725 MPASS(cst->ncompl > 0);
5728 cst->tx_credits -= next_credits;
5729 cst->tx_nocompl += next_credits;
5730 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
5731 ETHER_BPF_MTAP(cst->com.ifp, m);
5732 write_ethofld_wr(cst, wr, m, compl);
5733 commit_wrq_wr(cst->eo_txq, wr, &cookie);
5736 cst->tx_nocompl = 0;
5738 (void) mbufq_dequeue(&cst->pending_tx);
5739 mbufq_enqueue(&cst->pending_fwack, m);
5744 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
5746 struct cxgbe_snd_tag *cst;
5749 MPASS(m0->m_nextpkt == NULL);
5750 MPASS(m0->m_pkthdr.snd_tag != NULL);
5751 cst = mst_to_cst(m0->m_pkthdr.snd_tag);
5753 mtx_lock(&cst->lock);
5754 MPASS(cst->flags & EO_SND_TAG_REF);
5756 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
5757 struct vi_info *vi = ifp->if_softc;
5758 struct port_info *pi = vi->pi;
5759 struct adapter *sc = pi->adapter;
5760 const uint32_t rss_mask = vi->rss_size - 1;
5763 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
5764 if (M_HASHTYPE_ISHASH(m0))
5765 rss_hash = m0->m_pkthdr.flowid;
5767 rss_hash = arc4random();
5768 /* We assume RSS hashing */
5769 cst->iqid = vi->rss[rss_hash & rss_mask];
5770 cst->eo_txq += rss_hash % vi->nofldtxq;
5771 rc = send_etid_flowc_wr(cst, pi, vi);
5776 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
5781 mbufq_enqueue(&cst->pending_tx, m0);
5782 cst->plen += m0->m_pkthdr.len;
5787 mtx_unlock(&cst->lock);
5788 if (__predict_false(rc != 0))
5794 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
5796 struct adapter *sc = iq->adapter;
5797 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
5799 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
5800 struct cxgbe_snd_tag *cst;
5801 uint8_t credits = cpl->credits;
5803 cst = lookup_etid(sc, etid);
5804 mtx_lock(&cst->lock);
5805 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
5806 MPASS(credits >= ETID_FLOWC_LEN16);
5807 credits -= ETID_FLOWC_LEN16;
5808 cst->flags &= ~EO_FLOWC_RPL_PENDING;
5811 KASSERT(cst->ncompl > 0,
5812 ("%s: etid %u (%p) wasn't expecting completion.",
5813 __func__, etid, cst));
5816 while (credits > 0) {
5817 m = mbufq_dequeue(&cst->pending_fwack);
5818 if (__predict_false(m == NULL)) {
5820 * The remaining credits are for the final flush that
5821 * was issued when the tag was freed by the kernel.
5824 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
5825 EO_FLUSH_RPL_PENDING);
5826 MPASS(credits == ETID_FLUSH_LEN16);
5827 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
5828 MPASS(cst->ncompl == 0);
5830 cst->flags &= ~EO_FLUSH_RPL_PENDING;
5831 cst->tx_credits += cpl->credits;
5833 cxgbe_snd_tag_free_locked(cst);
5834 return (0); /* cst is gone. */
5837 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
5839 KASSERT(credits >= mbuf_eo_len16(m),
5840 ("%s: too few credits (%u, %u, %u)", __func__,
5841 cpl->credits, credits, mbuf_eo_len16(m)));
5842 credits -= mbuf_eo_len16(m);
5843 cst->plen -= m->m_pkthdr.len;
5847 cst->tx_credits += cpl->credits;
5848 MPASS(cst->tx_credits <= cst->tx_total);
5850 m = mbufq_first(&cst->pending_tx);
5851 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
5854 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) &&
5856 if (cst->tx_credits == cst->tx_total)
5859 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0);
5860 send_etid_flush_wr(cst);
5864 mtx_unlock(&cst->lock);