2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
49 #include <sys/sglist.h>
50 #include <sys/sysctl.h>
52 #include <sys/socketvar.h>
53 #include <sys/counter.h>
55 #include <net/ethernet.h>
57 #include <net/if_vlan_var.h>
58 #include <net/if_vxlan.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
61 #include <netinet/ip6.h>
62 #include <netinet/tcp.h>
63 #include <netinet/udp.h>
64 #include <machine/in_cksum.h>
65 #include <machine/md_var.h>
69 #include <machine/bus.h>
70 #include <sys/selinfo.h>
71 #include <net/if_var.h>
72 #include <net/netmap.h>
73 #include <dev/netmap/netmap_kern.h>
76 #include "common/common.h"
77 #include "common/t4_regs.h"
78 #include "common/t4_regs_values.h"
79 #include "common/t4_msg.h"
81 #include "t4_mp_ring.h"
83 #ifdef T4_PKT_TIMESTAMP
84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
86 #define RX_COPY_THRESHOLD MINCLSIZE
89 /* Internal mbuf flags stored in PH_loc.eight[1]. */
91 #define MC_RAW_WR 0x02
95 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
96 * 0-7 are valid values.
98 static int fl_pktshift = 0;
99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
100 "payload DMA offset in rx buffer (bytes)");
103 * Pad ethernet payload up to this boundary.
104 * -1: driver should figure out a good value.
105 * 0: disable padding.
106 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
110 "payload pad boundary (bytes)");
113 * Status page length.
114 * -1: driver should figure out a good value.
115 * 64 or 128 are the only other valid values.
117 static int spg_len = -1;
118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
119 "status page size (bytes)");
123 * -1: no congestion feedback (not recommended).
124 * 0: backpressure the channel instead of dropping packets right away.
125 * 1: no backpressure, drop packets for the congested queue immediately.
127 static int cong_drop = 0;
128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
129 "Congestion control for RX queues (0 = backpressure, 1 = drop");
132 * Deliver multiple frames in the same free list buffer if they fit.
133 * -1: let the driver decide whether to enable buffer packing or not.
134 * 0: disable buffer packing.
135 * 1: enable buffer packing.
137 static int buffer_packing = -1;
138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
139 0, "Enable buffer packing");
142 * Start next frame in a packed buffer at this boundary.
143 * -1: driver should figure out a good value.
144 * T4: driver will ignore this and use the same value as fl_pad above.
145 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
147 static int fl_pack = -1;
148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
149 "payload pack boundary (bytes)");
152 * Largest rx cluster size that the driver is allowed to allocate.
154 static int largest_rx_cluster = MJUM16BYTES;
155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
156 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
159 * Size of cluster allocation that's most likely to succeed. The driver will
160 * fall back to this size if it fails to allocate clusters larger than this.
162 static int safest_rx_cluster = PAGE_SIZE;
163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
164 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
168 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
169 * for rewriting. -1 and 0-3 are all valid values.
170 * -1: hardware should leave the TCP timestamps alone.
176 static int tsclk = -1;
177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
178 "Control TCP timestamp rewriting when using pacing");
180 static int eo_max_backlog = 1024 * 1024;
181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
182 0, "Maximum backlog of ratelimited data per flow");
186 * The interrupt holdoff timers are multiplied by this value on T6+.
187 * 1 and 3-17 (both inclusive) are legal values.
189 static int tscale = 1;
190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
191 "Interrupt holdoff timer scale on T6+");
194 * Number of LRO entries in the lro_ctrl structure per rx queue.
196 static int lro_entries = TCP_LRO_ENTRIES;
197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
198 "Number of LRO entries per RX queue");
201 * This enables presorting of frames before they're fed into tcp_lro_rx.
203 static int lro_mbufs = 0;
204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
205 "Enable presorting of LRO frames");
207 static counter_u64_t pullups;
208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
209 "Number of mbuf pullups performed");
211 static counter_u64_t defrags;
212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
213 "Number of mbuf defrags performed");
215 static int t4_tx_coalesce = 1;
216 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
217 "tx coalescing allowed");
220 * The driver will make aggressive attempts at tx coalescing if it sees these
221 * many packets eligible for coalescing in quick succession, with no more than
222 * the specified gap in between the eth_tx calls that delivered the packets.
224 static int t4_tx_coalesce_pkts = 32;
225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
226 &t4_tx_coalesce_pkts, 0,
227 "# of consecutive packets (1 - 255) that will trigger tx coalescing");
228 static int t4_tx_coalesce_gap = 5;
229 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
230 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
232 static int service_iq(struct sge_iq *, int);
233 static int service_iq_fl(struct sge_iq *, int);
234 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
235 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
237 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
239 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
240 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
241 struct sge_iq *, char *);
242 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
243 struct sysctl_ctx_list *, struct sysctl_oid *);
244 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
245 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
247 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
248 struct sysctl_oid *, struct sge_fl *);
249 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *);
250 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *);
251 static int alloc_fwq(struct adapter *);
252 static void free_fwq(struct adapter *);
253 static int alloc_ctrlq(struct adapter *, int);
254 static void free_ctrlq(struct adapter *, int);
255 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int);
256 static void free_rxq(struct vi_info *, struct sge_rxq *);
257 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
260 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
262 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
263 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
264 struct sge_ofld_rxq *);
266 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
267 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
268 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
269 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
271 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
272 struct sysctl_oid *);
273 static void free_eq(struct adapter *, struct sge_eq *);
274 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
275 struct sysctl_oid *, struct sge_eq *);
276 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
277 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
278 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
279 struct sysctl_ctx_list *, struct sysctl_oid *);
280 static void free_wrq(struct adapter *, struct sge_wrq *);
281 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
283 static int alloc_txq(struct vi_info *, struct sge_txq *, int);
284 static void free_txq(struct vi_info *, struct sge_txq *);
285 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *,
286 struct sysctl_oid *, struct sge_txq *);
287 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
288 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int);
289 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *);
290 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
291 struct sge_ofld_txq *);
293 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
294 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
295 static int refill_fl(struct adapter *, struct sge_fl *, int);
296 static void refill_sfl(void *);
297 static int find_refill_source(struct adapter *, int, bool);
298 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
300 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
301 static inline u_int txpkt_len16(u_int, const u_int);
302 static inline u_int txpkt_vm_len16(u_int, const u_int);
303 static inline void calculate_mbuf_len16(struct mbuf *, bool);
304 static inline u_int txpkts0_len16(u_int);
305 static inline u_int txpkts1_len16(void);
306 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
307 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
309 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
311 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
313 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
315 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
316 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
317 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
318 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
319 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
320 static inline uint16_t read_hw_cidx(struct sge_eq *);
321 static inline u_int reclaimable_tx_desc(struct sge_eq *);
322 static inline u_int total_available_tx_desc(struct sge_eq *);
323 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
324 static void tx_reclaim(void *, int);
325 static __be64 get_flit(struct sglist_seg *, int, int);
326 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
328 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
330 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
331 static void wrq_tx_drain(void *, int);
332 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
334 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
336 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
337 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
341 static counter_u64_t extfree_refs;
342 static counter_u64_t extfree_rels;
344 an_handler_t t4_an_handler;
345 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
346 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
347 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
348 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
349 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
350 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
351 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
354 t4_register_an_handler(an_handler_t h)
358 MPASS(h == NULL || t4_an_handler == NULL);
360 loc = (uintptr_t *)&t4_an_handler;
361 atomic_store_rel_ptr(loc, (uintptr_t)h);
365 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
369 MPASS(type < nitems(t4_fw_msg_handler));
370 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
372 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
373 * handler dispatch table. Reject any attempt to install a handler for
376 MPASS(type != FW_TYPE_RSSCPL);
377 MPASS(type != FW6_TYPE_RSSCPL);
379 loc = (uintptr_t *)&t4_fw_msg_handler[type];
380 atomic_store_rel_ptr(loc, (uintptr_t)h);
384 t4_register_cpl_handler(int opcode, cpl_handler_t h)
388 MPASS(opcode < nitems(t4_cpl_handler));
389 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
391 loc = (uintptr_t *)&t4_cpl_handler[opcode];
392 atomic_store_rel_ptr(loc, (uintptr_t)h);
396 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
399 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
406 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
408 * The return code for filter-write is put in the CPL cookie so
409 * we have to rely on the hardware tid (is_ftid) to determine
410 * that this is a response to a filter.
412 cookie = CPL_COOKIE_FILTER;
414 cookie = G_COOKIE(cpl->cookie);
416 MPASS(cookie > CPL_COOKIE_RESERVED);
417 MPASS(cookie < nitems(set_tcb_rpl_handlers));
419 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
423 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
426 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
431 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
432 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
436 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
439 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
440 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
443 MPASS(cookie != CPL_COOKIE_RESERVED);
445 return (act_open_rpl_handlers[cookie](iq, rss, m));
449 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
452 struct adapter *sc = iq->adapter;
456 if (is_hashfilter(sc))
457 cookie = CPL_COOKIE_HASHFILTER;
459 cookie = CPL_COOKIE_TOM;
461 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
465 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
467 struct adapter *sc = iq->adapter;
468 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
469 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
473 if (is_etid(sc, tid))
474 cookie = CPL_COOKIE_ETHOFLD;
476 cookie = CPL_COOKIE_TOM;
478 return (fw4_ack_handlers[cookie](iq, rss, m));
482 t4_init_shared_cpl_handlers(void)
485 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
486 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
487 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
488 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
489 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
493 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
497 MPASS(opcode < nitems(t4_cpl_handler));
498 MPASS(cookie > CPL_COOKIE_RESERVED);
499 MPASS(cookie < NUM_CPL_COOKIES);
500 MPASS(t4_cpl_handler[opcode] != NULL);
503 case CPL_SET_TCB_RPL:
504 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
506 case CPL_L2T_WRITE_RPL:
507 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
509 case CPL_ACT_OPEN_RPL:
510 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
512 case CPL_ABORT_RPL_RSS:
513 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
516 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
522 MPASS(h == NULL || *loc == (uintptr_t)NULL);
523 atomic_store_rel_ptr(loc, (uintptr_t)h);
527 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
533 if (fl_pktshift < 0 || fl_pktshift > 7) {
534 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
535 " using 0 instead.\n", fl_pktshift);
539 if (spg_len != 64 && spg_len != 128) {
542 #if defined(__i386__) || defined(__amd64__)
543 len = cpu_clflush_line_size > 64 ? 128 : 64;
548 printf("Invalid hw.cxgbe.spg_len value (%d),"
549 " using %d instead.\n", spg_len, len);
554 if (cong_drop < -1 || cong_drop > 1) {
555 printf("Invalid hw.cxgbe.cong_drop value (%d),"
556 " using 0 instead.\n", cong_drop);
560 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
561 printf("Invalid hw.cxgbe.tscale value (%d),"
562 " using 1 instead.\n", tscale);
566 if (largest_rx_cluster != MCLBYTES &&
567 #if MJUMPAGESIZE != MCLBYTES
568 largest_rx_cluster != MJUMPAGESIZE &&
570 largest_rx_cluster != MJUM9BYTES &&
571 largest_rx_cluster != MJUM16BYTES) {
572 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
573 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
574 largest_rx_cluster = MJUM16BYTES;
577 if (safest_rx_cluster != MCLBYTES &&
578 #if MJUMPAGESIZE != MCLBYTES
579 safest_rx_cluster != MJUMPAGESIZE &&
581 safest_rx_cluster != MJUM9BYTES &&
582 safest_rx_cluster != MJUM16BYTES) {
583 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
584 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
585 safest_rx_cluster = MJUMPAGESIZE;
588 extfree_refs = counter_u64_alloc(M_WAITOK);
589 extfree_rels = counter_u64_alloc(M_WAITOK);
590 pullups = counter_u64_alloc(M_WAITOK);
591 defrags = counter_u64_alloc(M_WAITOK);
592 counter_u64_zero(extfree_refs);
593 counter_u64_zero(extfree_rels);
594 counter_u64_zero(pullups);
595 counter_u64_zero(defrags);
597 t4_init_shared_cpl_handlers();
598 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
599 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
600 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
602 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
605 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
606 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
610 t4_sge_modunload(void)
613 counter_u64_free(extfree_refs);
614 counter_u64_free(extfree_rels);
615 counter_u64_free(pullups);
616 counter_u64_free(defrags);
620 t4_sge_extfree_refs(void)
624 rels = counter_u64_fetch(extfree_rels);
625 refs = counter_u64_fetch(extfree_refs);
627 return (refs - rels);
631 #define MAX_PACK_BOUNDARY 512
634 setup_pad_and_pack_boundaries(struct adapter *sc)
637 int pad, pack, pad_shift;
639 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
640 X_INGPADBOUNDARY_SHIFT;
642 if (fl_pad < (1 << pad_shift) ||
643 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
646 * If there is any chance that we might use buffer packing and
647 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
648 * it to the minimum allowed in all other cases.
650 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
653 * For fl_pad = 0 we'll still write a reasonable value to the
654 * register but all the freelists will opt out of padding.
655 * We'll complain here only if the user tried to set it to a
656 * value greater than 0 that was invalid.
659 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
660 " (%d), using %d instead.\n", fl_pad, pad);
663 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
664 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
665 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
668 if (fl_pack != -1 && fl_pack != pad) {
669 /* Complain but carry on. */
670 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
671 " using %d instead.\n", fl_pack, pad);
677 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
678 !powerof2(fl_pack)) {
679 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
680 pack = MAX_PACK_BOUNDARY;
682 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
683 MPASS(powerof2(pack));
691 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
692 " (%d), using %d instead.\n", fl_pack, pack);
695 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
697 v = V_INGPACKBOUNDARY(0);
699 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
701 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
702 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
706 * adap->params.vpd.cclk must be set up before this is called.
709 t4_tweak_chip_settings(struct adapter *sc)
713 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
714 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
715 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
716 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
717 static int sw_buf_sizes[] = {
719 #if MJUMPAGESIZE != MCLBYTES
726 KASSERT(sc->flags & MASTER_PF,
727 ("%s: trying to change chip settings when not master.", __func__));
729 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
730 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
731 V_EGRSTATUSPAGESIZE(spg_len == 128);
732 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
734 setup_pad_and_pack_boundaries(sc);
736 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
737 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
738 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
739 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
740 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
741 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
742 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
743 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
744 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
746 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
747 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
748 reg = A_SGE_FL_BUFFER_SIZE2;
749 for (i = 0; i < nitems(sw_buf_sizes); i++) {
750 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
751 t4_write_reg(sc, reg, sw_buf_sizes[i]);
753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
754 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
758 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
759 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
760 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
762 KASSERT(intr_timer[0] <= timer_max,
763 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
765 for (i = 1; i < nitems(intr_timer); i++) {
766 KASSERT(intr_timer[i] >= intr_timer[i - 1],
767 ("%s: timers not listed in increasing order (%d)",
770 while (intr_timer[i] > timer_max) {
771 if (i == nitems(intr_timer) - 1) {
772 intr_timer[i] = timer_max;
775 intr_timer[i] += intr_timer[i - 1];
780 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
781 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
782 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
783 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
784 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
785 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
786 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
787 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
788 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
790 if (chip_id(sc) >= CHELSIO_T6) {
791 m = V_TSCALE(M_TSCALE);
795 v = V_TSCALE(tscale - 2);
796 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
798 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
799 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
800 V_WRTHRTHRESH(M_WRTHRTHRESH);
801 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
803 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
805 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
809 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
810 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
811 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
814 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
815 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
816 * may have to deal with is MAXPHYS + 1 page.
818 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
819 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
821 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
822 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
823 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
825 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
827 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
828 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
832 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its
833 * address mut be 16B aligned. If padding is in use the buffer's start and end
834 * need to be aligned to the pad boundary as well. We'll just make sure that
835 * the size is a multiple of the pad boundary here, it is up to the buffer
836 * allocation code to make sure the start of the buffer is aligned.
839 hwsz_ok(struct adapter *sc, int hwsz)
841 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
843 return (hwsz >= 64 && (hwsz & mask) == 0);
847 * Initialize the rx buffer sizes and figure out which zones the buffers will
851 t4_init_rx_buf_info(struct adapter *sc)
853 struct sge *s = &sc->sge;
854 struct sge_params *sp = &sc->params.sge;
856 static int sw_buf_sizes[] = { /* Sorted by size */
858 #if MJUMPAGESIZE != MCLBYTES
864 struct rx_buf_info *rxb;
867 rxb = &s->rx_buf_info[0];
868 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
869 rxb->size1 = sw_buf_sizes[i];
870 rxb->zone = m_getzone(rxb->size1);
871 rxb->type = m_gettype(rxb->size1);
875 for (j = 0; j < SGE_FLBUF_SIZES; j++) {
876 int hwsize = sp->sge_fl_buffer_size[j];
878 if (!hwsz_ok(sc, hwsize))
881 /* hwidx for size1 */
882 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
885 /* hwidx for size2 (buffer packing) */
886 if (rxb->size1 - CL_METADATA_SIZE < hwsize)
888 n = rxb->size1 - hwsize - CL_METADATA_SIZE;
892 break; /* stop looking */
894 if (rxb->hwidx2 != -1) {
895 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
896 hwsize - CL_METADATA_SIZE) {
900 } else if (n <= 2 * CL_METADATA_SIZE) {
905 if (rxb->hwidx2 != -1)
906 sc->flags |= BUF_PACKING_OK;
907 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
913 * Verify some basic SGE settings for the PF and VF driver, and other
914 * miscellaneous settings for the PF driver.
917 t4_verify_chip_settings(struct adapter *sc)
919 struct sge_params *sp = &sc->params.sge;
922 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
928 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
933 * If this changes then every single use of PAGE_SHIFT in the driver
934 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
936 if (sp->page_shift != PAGE_SHIFT) {
937 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
941 if (sc->flags & IS_VF)
944 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
945 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
947 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
948 if (sc->vres.ddp.size != 0)
952 m = v = F_TDDPTAGTCB;
953 r = t4_read_reg(sc, A_ULP_RX_CTL);
955 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
956 if (sc->vres.ddp.size != 0)
960 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
962 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
963 r = t4_read_reg(sc, A_TP_PARA_REG5);
965 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
966 if (sc->vres.ddp.size != 0)
974 t4_create_dma_tag(struct adapter *sc)
978 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
979 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
980 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
983 device_printf(sc->dev,
984 "failed to create main DMA tag: %d\n", rc);
991 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
992 struct sysctl_oid_list *children)
994 struct sge_params *sp = &sc->params.sge;
996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
997 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
998 sysctl_bufsizes, "A", "freelist buffer sizes");
1000 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1001 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1003 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1004 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1006 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1007 NULL, sp->spg_len, "status page size (bytes)");
1009 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1010 NULL, cong_drop, "congestion drop setting");
1012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1013 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1017 t4_destroy_dma_tag(struct adapter *sc)
1020 bus_dma_tag_destroy(sc->dmat);
1026 * Allocate and initialize the firmware event queue, control queues, and special
1027 * purpose rx queues owned by the adapter.
1029 * Returns errno on failure. Resources allocated up to that point may still be
1030 * allocated. Caller is responsible for cleanup in case this function fails.
1033 t4_setup_adapter_queues(struct adapter *sc)
1037 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1040 * Firmware event queue
1047 * That's all for the VF driver.
1049 if (sc->flags & IS_VF)
1053 * XXX: General purpose rx queues, one per port.
1057 * Control queues, one per port.
1059 for_each_port(sc, i) {
1060 rc = alloc_ctrlq(sc, i);
1072 t4_teardown_adapter_queues(struct adapter *sc)
1076 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1078 if (!(sc->flags & IS_VF)) {
1079 for_each_port(sc, i)
1087 /* Maximum payload that could arrive with a single iq descriptor. */
1089 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld)
1093 /* large enough even when hw VLAN extraction is disabled */
1094 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1095 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu;
1096 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1097 maxp < sc->params.tp.max_rx_pdu)
1098 maxp = sc->params.tp.max_rx_pdu;
1103 t4_setup_vi_queues(struct vi_info *vi)
1105 int rc = 0, i, intr_idx;
1106 struct sge_rxq *rxq;
1107 struct sge_txq *txq;
1109 struct sge_ofld_rxq *ofld_rxq;
1111 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1112 struct sge_ofld_txq *ofld_txq;
1115 int saved_idx, iqidx;
1116 struct sge_nm_rxq *nm_rxq;
1117 struct sge_nm_txq *nm_txq;
1119 struct adapter *sc = vi->adapter;
1120 struct ifnet *ifp = vi->ifp;
1123 /* Interrupt vector to start from (when using multiple vectors) */
1124 intr_idx = vi->first_intr;
1127 saved_idx = intr_idx;
1128 if (ifp->if_capabilities & IFCAP_NETMAP) {
1130 /* netmap is supported with direct interrupts only. */
1131 MPASS(!forwarding_intr_to_fwq(sc));
1132 MPASS(vi->first_intr >= 0);
1135 * We don't have buffers to back the netmap rx queues
1136 * right now so we create the queues in a way that
1137 * doesn't set off any congestion signal in the chip.
1139 for_each_nm_rxq(vi, i, nm_rxq) {
1140 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i);
1146 for_each_nm_txq(vi, i, nm_txq) {
1147 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1148 rc = alloc_nm_txq(vi, nm_txq, iqidx, i);
1154 /* Normal rx queues and netmap rx queues share the same interrupts. */
1155 intr_idx = saved_idx;
1159 * Allocate rx queues first because a default iqid is required when
1160 * creating a tx queue.
1162 maxp = max_rx_payload(sc, ifp, false);
1163 for_each_rxq(vi, i, rxq) {
1164 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp);
1167 if (!forwarding_intr_to_fwq(sc))
1171 if (ifp->if_capabilities & IFCAP_NETMAP)
1172 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1175 maxp = max_rx_payload(sc, ifp, true);
1176 for_each_ofld_rxq(vi, i, ofld_rxq) {
1177 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp);
1180 if (!forwarding_intr_to_fwq(sc))
1186 * Now the tx queues.
1188 for_each_txq(vi, i, txq) {
1189 rc = alloc_txq(vi, txq, i);
1193 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1194 for_each_ofld_txq(vi, i, ofld_txq) {
1195 rc = alloc_ofld_txq(vi, ofld_txq, i);
1202 t4_teardown_vi_queues(vi);
1211 t4_teardown_vi_queues(struct vi_info *vi)
1214 struct sge_rxq *rxq;
1215 struct sge_txq *txq;
1216 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1217 struct sge_ofld_txq *ofld_txq;
1220 struct sge_ofld_rxq *ofld_rxq;
1223 struct sge_nm_rxq *nm_rxq;
1224 struct sge_nm_txq *nm_txq;
1228 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1229 for_each_nm_txq(vi, i, nm_txq) {
1230 free_nm_txq(vi, nm_txq);
1233 for_each_nm_rxq(vi, i, nm_rxq) {
1234 free_nm_rxq(vi, nm_rxq);
1240 * Take down all the tx queues first, as they reference the rx queues
1241 * (for egress updates, etc.).
1244 for_each_txq(vi, i, txq) {
1247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1248 for_each_ofld_txq(vi, i, ofld_txq) {
1249 free_ofld_txq(vi, ofld_txq);
1254 * Then take down the rx queues.
1257 for_each_rxq(vi, i, rxq) {
1261 for_each_ofld_rxq(vi, i, ofld_rxq) {
1262 free_ofld_rxq(vi, ofld_rxq);
1270 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1273 * a) Deals with errors, if any.
1274 * b) Services firmware event queue, which is taking interrupts for all other
1278 t4_intr_all(void *arg)
1280 struct adapter *sc = arg;
1281 struct sge_iq *fwq = &sc->sge.fwq;
1283 MPASS(sc->intr_count == 1);
1285 if (sc->intr_type == INTR_INTX)
1286 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1293 * Interrupt handler for errors (installed directly when multiple interrupts are
1294 * being used, or called by t4_intr_all).
1297 t4_intr_err(void *arg)
1299 struct adapter *sc = arg;
1301 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1303 if (sc->flags & ADAP_ERR)
1306 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1309 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1312 t4_slow_intr_handler(sc, verbose);
1316 * Interrupt handler for iq-only queues. The firmware event queue is the only
1317 * such queue right now.
1320 t4_intr_evt(void *arg)
1322 struct sge_iq *iq = arg;
1324 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1326 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1331 * Interrupt handler for iq+fl queues.
1336 struct sge_iq *iq = arg;
1338 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1339 service_iq_fl(iq, 0);
1340 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1346 * Interrupt handler for netmap rx queues.
1349 t4_nm_intr(void *arg)
1351 struct sge_nm_rxq *nm_rxq = arg;
1353 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1354 service_nm_rxq(nm_rxq);
1355 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1360 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1363 t4_vi_intr(void *arg)
1365 struct irq *irq = arg;
1367 MPASS(irq->nm_rxq != NULL);
1368 t4_nm_intr(irq->nm_rxq);
1370 MPASS(irq->rxq != NULL);
1376 * Deals with interrupts on an iq-only (no freelist) queue.
1379 service_iq(struct sge_iq *iq, int budget)
1382 struct adapter *sc = iq->adapter;
1383 struct iq_desc *d = &iq->desc[iq->cidx];
1384 int ndescs = 0, limit;
1387 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1389 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1390 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1391 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1393 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1394 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1396 limit = budget ? budget : iq->qsize / 16;
1399 * We always come back and check the descriptor ring for new indirect
1400 * interrupts and other responses after running a single handler.
1403 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1407 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1408 lq = be32toh(d->rsp.pldbuflen_qid);
1411 case X_RSPD_TYPE_FLBUF:
1412 panic("%s: data for an iq (%p) with no freelist",
1417 case X_RSPD_TYPE_CPL:
1418 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1419 ("%s: bad opcode %02x.", __func__,
1421 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1424 case X_RSPD_TYPE_INTR:
1426 * There are 1K interrupt-capable queues (qids 0
1427 * through 1023). A response type indicating a
1428 * forwarded interrupt with a qid >= 1K is an
1429 * iWARP async notification.
1431 if (__predict_true(lq >= 1024)) {
1432 t4_an_handler(iq, &d->rsp);
1436 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1438 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1440 if (service_iq_fl(q, q->qsize / 16) == 0) {
1441 (void) atomic_cmpset_int(&q->state,
1442 IQS_BUSY, IQS_IDLE);
1444 STAILQ_INSERT_TAIL(&iql, q,
1452 ("%s: illegal response type %d on iq %p",
1453 __func__, rsp_type, iq));
1455 "%s: illegal response type %d on iq %p",
1456 device_get_nameunit(sc->dev), rsp_type, iq);
1461 if (__predict_false(++iq->cidx == iq->sidx)) {
1463 iq->gen ^= F_RSPD_GEN;
1466 if (__predict_false(++ndescs == limit)) {
1467 t4_write_reg(sc, sc->sge_gts_reg,
1469 V_INGRESSQID(iq->cntxt_id) |
1470 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1474 return (EINPROGRESS);
1479 if (STAILQ_EMPTY(&iql))
1483 * Process the head only, and send it to the back of the list if
1484 * it's still not done.
1486 q = STAILQ_FIRST(&iql);
1487 STAILQ_REMOVE_HEAD(&iql, link);
1488 if (service_iq_fl(q, q->qsize / 8) == 0)
1489 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1491 STAILQ_INSERT_TAIL(&iql, q, link);
1494 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1495 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1501 sort_before_lro(struct lro_ctrl *lro)
1504 return (lro->lro_mbuf_max != 0);
1507 static inline uint64_t
1508 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1510 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1512 if (n > UINT64_MAX / 1000000)
1513 return (n / sc->params.vpd.cclk * 1000000);
1515 return (n * 1000000 / sc->params.vpd.cclk);
1519 move_to_next_rxbuf(struct sge_fl *fl)
1523 if (__predict_false((++fl->cidx & 7) == 0)) {
1524 uint16_t cidx = fl->cidx >> 3;
1526 if (__predict_false(cidx == fl->sidx))
1527 fl->cidx = cidx = 0;
1533 * Deals with interrupts on an iq+fl queue.
1536 service_iq_fl(struct sge_iq *iq, int budget)
1538 struct sge_rxq *rxq = iq_to_rxq(iq);
1540 struct adapter *sc = iq->adapter;
1541 struct iq_desc *d = &iq->desc[iq->cidx];
1543 int rsp_type, starved;
1545 uint16_t fl_hw_cidx;
1547 #if defined(INET) || defined(INET6)
1548 const struct timeval lro_timeout = {0, sc->lro_timeout};
1549 struct lro_ctrl *lro = &rxq->lro;
1552 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1553 MPASS(iq->flags & IQ_HAS_FL);
1556 #if defined(INET) || defined(INET6)
1557 if (iq->flags & IQ_ADJ_CREDIT) {
1558 MPASS(sort_before_lro(lro));
1559 iq->flags &= ~IQ_ADJ_CREDIT;
1560 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1561 tcp_lro_flush_all(lro);
1562 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1563 V_INGRESSQID((u32)iq->cntxt_id) |
1564 V_SEINTARM(iq->intr_params));
1570 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1573 limit = budget ? budget : iq->qsize / 16;
1575 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1576 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1581 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1582 lq = be32toh(d->rsp.pldbuflen_qid);
1585 case X_RSPD_TYPE_FLBUF:
1586 if (lq & F_RSPD_NEWBUF) {
1587 if (fl->rx_offset > 0)
1588 move_to_next_rxbuf(fl);
1589 lq = G_RSPD_LEN(lq);
1591 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1593 refill_fl(sc, fl, 64);
1595 fl_hw_cidx = fl->hw_cidx;
1598 if (d->rss.opcode == CPL_RX_PKT) {
1599 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1603 m0 = get_fl_payload(sc, fl, lq);
1604 if (__predict_false(m0 == NULL))
1609 case X_RSPD_TYPE_CPL:
1610 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1611 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1612 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1615 case X_RSPD_TYPE_INTR:
1618 * There are 1K interrupt-capable queues (qids 0
1619 * through 1023). A response type indicating a
1620 * forwarded interrupt with a qid >= 1K is an
1621 * iWARP async notification. That is the only
1622 * acceptable indirect interrupt on this queue.
1624 if (__predict_false(lq < 1024)) {
1625 panic("%s: indirect interrupt on iq_fl %p "
1626 "with qid %u", __func__, iq, lq);
1629 t4_an_handler(iq, &d->rsp);
1633 KASSERT(0, ("%s: illegal response type %d on iq %p",
1634 __func__, rsp_type, iq));
1635 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1636 device_get_nameunit(sc->dev), rsp_type, iq);
1641 if (__predict_false(++iq->cidx == iq->sidx)) {
1643 iq->gen ^= F_RSPD_GEN;
1646 if (__predict_false(++ndescs == limit)) {
1647 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1648 V_INGRESSQID(iq->cntxt_id) |
1649 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1651 #if defined(INET) || defined(INET6)
1652 if (iq->flags & IQ_LRO_ENABLED &&
1653 !sort_before_lro(lro) &&
1654 sc->lro_timeout != 0) {
1655 tcp_lro_flush_inactive(lro, &lro_timeout);
1659 return (EINPROGRESS);
1664 #if defined(INET) || defined(INET6)
1665 if (iq->flags & IQ_LRO_ENABLED) {
1666 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1667 MPASS(sort_before_lro(lro));
1668 /* hold back one credit and don't flush LRO state */
1669 iq->flags |= IQ_ADJ_CREDIT;
1672 tcp_lro_flush_all(lro);
1677 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1678 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1681 starved = refill_fl(sc, fl, 64);
1683 if (__predict_false(starved != 0))
1684 add_fl_to_sfl(sc, fl);
1689 static inline struct cluster_metadata *
1690 cl_metadata(struct fl_sdesc *sd)
1693 return ((void *)(sd->cl + sd->moff));
1697 rxb_free(struct mbuf *m)
1699 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1701 uma_zfree(clm->zone, clm->cl);
1702 counter_u64_add(extfree_rels, 1);
1706 * The mbuf returned comes from zone_muf and carries the payload in one of these
1708 * a) complete frame inside the mbuf
1709 * b) m_cljset (for clusters without metadata)
1710 * d) m_extaddref (cluster with metadata)
1712 static struct mbuf *
1713 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1717 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1718 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1719 struct cluster_metadata *clm;
1723 if (fl->flags & FL_BUF_PACKING) {
1726 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1727 len = min(remaining, blen);
1728 payload = sd->cl + fl->rx_offset;
1730 l = fr_offset + len;
1731 pad = roundup2(l, fl->buf_boundary) - l;
1732 if (fl->rx_offset + len + pad < rxb->size2)
1734 MPASS(fl->rx_offset + blen <= rxb->size2);
1736 MPASS(fl->rx_offset == 0); /* not packing */
1738 len = min(remaining, blen);
1742 if (fr_offset == 0) {
1743 m = m_gethdr(M_NOWAIT, MT_DATA);
1744 if (__predict_false(m == NULL))
1746 m->m_pkthdr.len = remaining;
1748 m = m_get(M_NOWAIT, MT_DATA);
1749 if (__predict_false(m == NULL))
1754 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1755 /* copy data to mbuf */
1756 bcopy(payload, mtod(m, caddr_t), len);
1757 if (fl->flags & FL_BUF_PACKING) {
1758 fl->rx_offset += blen;
1759 MPASS(fl->rx_offset <= rxb->size2);
1760 if (fl->rx_offset < rxb->size2)
1761 return (m); /* without advancing the cidx */
1763 } else if (fl->flags & FL_BUF_PACKING) {
1764 clm = cl_metadata(sd);
1765 if (sd->nmbuf++ == 0) {
1767 clm->zone = rxb->zone;
1769 counter_u64_add(extfree_refs, 1);
1771 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1774 fl->rx_offset += blen;
1775 MPASS(fl->rx_offset <= rxb->size2);
1776 if (fl->rx_offset < rxb->size2)
1777 return (m); /* without advancing the cidx */
1779 m_cljset(m, sd->cl, rxb->type);
1780 sd->cl = NULL; /* consumed, not a recycle candidate */
1783 move_to_next_rxbuf(fl);
1788 static struct mbuf *
1789 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1791 struct mbuf *m0, *m, **pnext;
1794 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1795 M_ASSERTPKTHDR(fl->m0);
1796 MPASS(fl->m0->m_pkthdr.len == plen);
1797 MPASS(fl->remaining < plen);
1801 remaining = fl->remaining;
1802 fl->flags &= ~FL_BUF_RESUME;
1807 * Payload starts at rx_offset in the current hw buffer. Its length is
1808 * 'len' and it may span multiple hw buffers.
1811 m0 = get_scatter_segment(sc, fl, 0, plen);
1814 remaining = plen - m0->m_len;
1815 pnext = &m0->m_next;
1816 while (remaining > 0) {
1818 MPASS(fl->rx_offset == 0);
1819 m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1820 if (__predict_false(m == NULL)) {
1823 fl->remaining = remaining;
1824 fl->flags |= FL_BUF_RESUME;
1829 remaining -= m->m_len;
1838 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1841 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1842 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1845 if (fl->flags & FL_BUF_PACKING) {
1848 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1849 len = min(remaining, blen);
1851 l = fr_offset + len;
1852 pad = roundup2(l, fl->buf_boundary) - l;
1853 if (fl->rx_offset + len + pad < rxb->size2)
1855 fl->rx_offset += blen;
1856 MPASS(fl->rx_offset <= rxb->size2);
1857 if (fl->rx_offset < rxb->size2)
1858 return (len); /* without advancing the cidx */
1860 MPASS(fl->rx_offset == 0); /* not packing */
1862 len = min(remaining, blen);
1864 move_to_next_rxbuf(fl);
1869 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1871 int remaining, fr_offset, len;
1875 while (remaining > 0) {
1876 len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1883 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1886 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1887 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1889 if (fl->flags & FL_BUF_PACKING)
1890 len = rxb->size2 - fl->rx_offset;
1894 return (min(plen, len));
1898 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1902 struct ifnet *ifp = rxq->ifp;
1903 struct sge_fl *fl = &rxq->fl;
1904 struct vi_info *vi = ifp->if_softc;
1905 const struct cpl_rx_pkt *cpl;
1906 #if defined(INET) || defined(INET6)
1907 struct lro_ctrl *lro = &rxq->lro;
1909 uint16_t err_vec, tnl_type, tnlhdr_len;
1910 static const int sw_hashtype[4][2] = {
1911 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1912 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1913 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1914 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1916 static const int sw_csum_flags[2][2] = {
1920 CSUM_L3_CALC | CSUM_L3_VALID |
1921 CSUM_L4_CALC | CSUM_L4_VALID |
1922 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1923 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1927 CSUM_L3_CALC | CSUM_L3_VALID |
1928 CSUM_L4_CALC | CSUM_L4_VALID |
1929 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1934 CSUM_L4_CALC | CSUM_L4_VALID |
1935 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1936 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1938 /* IP6, inner IP6 */
1940 CSUM_L4_CALC | CSUM_L4_VALID |
1941 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1945 MPASS(plen > sc->params.sge.fl_pktshift);
1946 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1947 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1948 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1952 slen = get_segment_len(sc, fl, plen) -
1953 sc->params.sge.fl_pktshift;
1954 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1955 CURVNET_SET_QUIET(ifp->if_vnet);
1956 rc = pfil_run_hooks(vi->pfil, frame, ifp,
1957 slen | PFIL_MEMPTR | PFIL_IN, NULL);
1959 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1960 skip_fl_payload(sc, fl, plen);
1963 if (rc == PFIL_REALLOCED) {
1964 skip_fl_payload(sc, fl, plen);
1965 m0 = pfil_mem2mbuf(frame);
1970 m0 = get_fl_payload(sc, fl, plen);
1971 if (__predict_false(m0 == NULL))
1974 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1975 m0->m_len -= sc->params.sge.fl_pktshift;
1976 m0->m_data += sc->params.sge.fl_pktshift;
1979 m0->m_pkthdr.rcvif = ifp;
1980 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
1981 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
1983 cpl = (const void *)(&d->rss + 1);
1984 if (sc->params.tp.rx_pkt_encap) {
1985 const uint16_t ev = be16toh(cpl->err_vec);
1987 err_vec = G_T6_COMPR_RXERR_VEC(ev);
1988 tnl_type = G_T6_RX_TNL_TYPE(ev);
1989 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
1991 err_vec = be16toh(cpl->err_vec);
1995 if (cpl->csum_calc && err_vec == 0) {
1996 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
1998 /* checksum(s) calculated and found to be correct. */
2000 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2001 (cpl->l2info & htobe32(F_RXF_IP6)));
2002 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2003 if (tnl_type == 0) {
2004 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) {
2005 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2006 CSUM_L3_VALID | CSUM_L4_CALC |
2008 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) {
2009 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2014 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2016 M_HASHTYPE_SETINNER(m0);
2017 if (__predict_false(cpl->ip_frag)) {
2019 * csum_data is for the inner frame (which is an
2020 * IP fragment) and is not 0xffff. There is no
2021 * way to pass the inner csum_data to the stack.
2022 * We don't want the stack to use the inner
2023 * csum_data to validate the outer frame or it
2024 * will get rejected. So we fix csum_data here
2025 * and let sw do the checksum of inner IP
2028 * XXX: Need 32b for csum_data2 in an rx mbuf.
2029 * Maybe stuff it into rcv_tstmp?
2031 m0->m_pkthdr.csum_data = 0xffff;
2033 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2036 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2037 CSUM_L3_VALID | CSUM_L4_CALC |
2043 MPASS(m0->m_pkthdr.csum_data == 0xffff);
2045 outer_ipv6 = tnlhdr_len >=
2046 sizeof(struct ether_header) +
2047 sizeof(struct ip6_hdr);
2048 m0->m_pkthdr.csum_flags =
2049 sw_csum_flags[outer_ipv6][ipv6];
2051 rxq->vxlan_rxcsum++;
2056 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2057 m0->m_flags |= M_VLANTAG;
2058 rxq->vlan_extraction++;
2061 if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2063 * Fill up rcv_tstmp but do not set M_TSTMP.
2064 * rcv_tstmp is not in the format that the
2065 * kernel expects and we don't want to mislead
2066 * it. For now this is only for custom code
2067 * that knows how to interpret cxgbe's stamp.
2069 m0->m_pkthdr.rcv_tstmp =
2070 last_flit_to_ns(sc, d->rsp.u.last_flit);
2072 m0->m_flags |= M_TSTMP;
2077 m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2079 #if defined(INET) || defined(INET6)
2080 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2081 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2082 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2083 if (sort_before_lro(lro)) {
2084 tcp_lro_queue_mbuf(lro, m0);
2085 return (0); /* queued for sort, then LRO */
2087 if (tcp_lro_rx(lro, m0, 0) == 0)
2088 return (0); /* queued for LRO */
2091 ifp->if_input(ifp, m0);
2097 * Must drain the wrq or make sure that someone else will.
2100 wrq_tx_drain(void *arg, int n)
2102 struct sge_wrq *wrq = arg;
2103 struct sge_eq *eq = &wrq->eq;
2106 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2107 drain_wrq_wr_list(wrq->adapter, wrq);
2112 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2114 struct sge_eq *eq = &wrq->eq;
2115 u_int available, dbdiff; /* # of hardware descriptors */
2118 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2120 EQ_LOCK_ASSERT_OWNED(eq);
2121 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2122 wr = STAILQ_FIRST(&wrq->wr_list);
2123 MPASS(wr != NULL); /* Must be called with something useful to do */
2124 MPASS(eq->pidx == eq->dbidx);
2128 eq->cidx = read_hw_cidx(eq);
2129 if (eq->pidx == eq->cidx)
2130 available = eq->sidx - 1;
2132 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2134 MPASS(wr->wrq == wrq);
2135 n = howmany(wr->wr_len, EQ_ESIZE);
2139 dst = (void *)&eq->desc[eq->pidx];
2140 if (__predict_true(eq->sidx - eq->pidx > n)) {
2141 /* Won't wrap, won't end exactly at the status page. */
2142 bcopy(&wr->wr[0], dst, wr->wr_len);
2145 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2147 bcopy(&wr->wr[0], dst, first_portion);
2148 if (wr->wr_len > first_portion) {
2149 bcopy(&wr->wr[first_portion], &eq->desc[0],
2150 wr->wr_len - first_portion);
2152 eq->pidx = n - (eq->sidx - eq->pidx);
2154 wrq->tx_wrs_copied++;
2156 if (available < eq->sidx / 4 &&
2157 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2159 * XXX: This is not 100% reliable with some
2160 * types of WRs. But this is a very unusual
2161 * situation for an ofld/ctrl queue anyway.
2163 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2169 ring_eq_db(sc, eq, dbdiff);
2173 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2175 MPASS(wrq->nwr_pending > 0);
2177 MPASS(wrq->ndesc_needed >= n);
2178 wrq->ndesc_needed -= n;
2179 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2182 ring_eq_db(sc, eq, dbdiff);
2186 * Doesn't fail. Holds on to work requests it can't send right away.
2189 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2192 struct sge_eq *eq = &wrq->eq;
2195 EQ_LOCK_ASSERT_OWNED(eq);
2197 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2198 MPASS((wr->wr_len & 0x7) == 0);
2200 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2202 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2204 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2205 return; /* commit_wrq_wr will drain wr_list as well. */
2207 drain_wrq_wr_list(sc, wrq);
2209 /* Doorbell must have caught up to the pidx. */
2210 MPASS(eq->pidx == eq->dbidx);
2214 t4_update_fl_bufsize(struct ifnet *ifp)
2216 struct vi_info *vi = ifp->if_softc;
2217 struct adapter *sc = vi->adapter;
2218 struct sge_rxq *rxq;
2220 struct sge_ofld_rxq *ofld_rxq;
2225 maxp = max_rx_payload(sc, ifp, false);
2226 for_each_rxq(vi, i, rxq) {
2230 fl->zidx = find_refill_source(sc, maxp,
2231 fl->flags & FL_BUF_PACKING);
2235 maxp = max_rx_payload(sc, ifp, true);
2236 for_each_ofld_rxq(vi, i, ofld_rxq) {
2240 fl->zidx = find_refill_source(sc, maxp,
2241 fl->flags & FL_BUF_PACKING);
2248 mbuf_nsegs(struct mbuf *m)
2252 KASSERT(m->m_pkthdr.inner_l5hlen > 0,
2253 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2255 return (m->m_pkthdr.inner_l5hlen);
2259 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2263 m->m_pkthdr.inner_l5hlen = nsegs;
2267 mbuf_cflags(struct mbuf *m)
2271 return (m->m_pkthdr.PH_loc.eight[4]);
2275 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2279 m->m_pkthdr.PH_loc.eight[4] = flags;
2283 mbuf_len16(struct mbuf *m)
2288 n = m->m_pkthdr.PH_loc.eight[0];
2289 if (!(mbuf_cflags(m) & MC_TLS))
2290 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2296 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2300 if (!(mbuf_cflags(m) & MC_TLS))
2301 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
2302 m->m_pkthdr.PH_loc.eight[0] = len16;
2307 mbuf_eo_nsegs(struct mbuf *m)
2311 return (m->m_pkthdr.PH_loc.eight[1]);
2315 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2319 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2323 mbuf_eo_len16(struct mbuf *m)
2328 n = m->m_pkthdr.PH_loc.eight[2];
2329 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2335 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2339 m->m_pkthdr.PH_loc.eight[2] = len16;
2343 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2347 return (m->m_pkthdr.PH_loc.eight[3]);
2351 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2355 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2359 needs_eo(struct m_snd_tag *mst)
2362 return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2367 * Try to allocate an mbuf to contain a raw work request. To make it
2368 * easy to construct the work request, don't allocate a chain but a
2372 alloc_wr_mbuf(int len, int how)
2377 m = m_gethdr(how, MT_DATA);
2378 else if (len <= MCLBYTES)
2379 m = m_getcl(how, MT_DATA, M_PKTHDR);
2384 m->m_pkthdr.len = len;
2386 set_mbuf_cflags(m, MC_RAW_WR);
2387 set_mbuf_len16(m, howmany(len, 16));
2392 needs_hwcsum(struct mbuf *m)
2394 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2395 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2396 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2397 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2398 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2402 return (m->m_pkthdr.csum_flags & csum_flags);
2406 needs_tso(struct mbuf *m)
2408 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2409 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2413 return (m->m_pkthdr.csum_flags & csum_flags);
2417 needs_vxlan_csum(struct mbuf *m)
2422 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2426 needs_vxlan_tso(struct mbuf *m)
2428 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2433 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2434 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2438 needs_inner_tcp_csum(struct mbuf *m)
2440 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2444 return (m->m_pkthdr.csum_flags & csum_flags);
2448 needs_l3_csum(struct mbuf *m)
2450 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2455 return (m->m_pkthdr.csum_flags & csum_flags);
2459 needs_outer_tcp_csum(struct mbuf *m)
2461 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2466 return (m->m_pkthdr.csum_flags & csum_flags);
2471 needs_outer_l4_csum(struct mbuf *m)
2473 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2474 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2478 return (m->m_pkthdr.csum_flags & csum_flags);
2482 needs_outer_udp_csum(struct mbuf *m)
2484 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2488 return (m->m_pkthdr.csum_flags & csum_flags);
2493 needs_vlan_insertion(struct mbuf *m)
2498 return (m->m_flags & M_VLANTAG);
2502 m_advance(struct mbuf **pm, int *poffset, int len)
2504 struct mbuf *m = *pm;
2505 int offset = *poffset;
2511 if (offset + len < m->m_len) {
2513 p = mtod(m, uintptr_t) + offset;
2516 len -= m->m_len - offset;
2527 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2530 int i, len, off, pglen, pgoff, seglen, segoff;
2534 off = mtod(m, vm_offset_t);
2539 if (m->m_epg_hdrlen != 0) {
2540 if (off >= m->m_epg_hdrlen) {
2541 off -= m->m_epg_hdrlen;
2543 seglen = m->m_epg_hdrlen - off;
2545 seglen = min(seglen, len);
2548 paddr = pmap_kextract(
2549 (vm_offset_t)&m->m_epg_hdr[segoff]);
2550 if (*nextaddr != paddr)
2552 *nextaddr = paddr + seglen;
2555 pgoff = m->m_epg_1st_off;
2556 for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2557 pglen = m_epg_pagelen(m, i, pgoff);
2563 seglen = pglen - off;
2564 segoff = pgoff + off;
2566 seglen = min(seglen, len);
2568 paddr = m->m_epg_pa[i] + segoff;
2569 if (*nextaddr != paddr)
2571 *nextaddr = paddr + seglen;
2575 seglen = min(len, m->m_epg_trllen - off);
2577 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2578 if (*nextaddr != paddr)
2580 *nextaddr = paddr + seglen;
2588 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2589 * must have at least one mbuf that's not empty. It is possible for this
2590 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2593 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2595 vm_paddr_t nextaddr, paddr;
2600 MPASS(m->m_pkthdr.len > 0);
2601 MPASS(m->m_pkthdr.len >= skip);
2605 for (; m; m = m->m_next) {
2607 if (__predict_false(len == 0))
2613 if ((m->m_flags & M_EXTPG) != 0) {
2614 *cflags |= MC_NOMAP;
2615 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2619 va = mtod(m, vm_offset_t) + skip;
2622 paddr = pmap_kextract(va);
2623 nsegs += sglist_count((void *)(uintptr_t)va, len);
2624 if (paddr == nextaddr)
2626 nextaddr = pmap_kextract(va + len - 1) + 1;
2633 * The maximum number of segments that can fit in a WR.
2636 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2641 return (TX_SGL_SEGS_VM_TSO);
2642 return (TX_SGL_SEGS_VM);
2646 if (needs_vxlan_tso(m))
2647 return (TX_SGL_SEGS_VXLAN_TSO);
2649 return (TX_SGL_SEGS_TSO);
2652 return (TX_SGL_SEGS);
2655 static struct timeval txerr_ratecheck = {0};
2656 static const struct timeval txerr_interval = {3, 0};
2659 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2660 * a) caller can assume it's been freed if this function returns with an error.
2661 * b) it may get defragged up if the gather list is too long for the hardware.
2664 parse_pkt(struct mbuf **mp, bool vm_wr)
2666 struct mbuf *m0 = *mp, *m;
2667 int rc, nsegs, defragged = 0, offset;
2668 struct ether_header *eh;
2670 #if defined(INET) || defined(INET6)
2673 #if defined(KERN_TLS) || defined(RATELIMIT)
2674 struct m_snd_tag *mst;
2681 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2690 * First count the number of gather list segments in the payload.
2691 * Defrag the mbuf if nsegs exceeds the hardware limit.
2694 MPASS(m0->m_pkthdr.len > 0);
2695 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2696 #if defined(KERN_TLS) || defined(RATELIMIT)
2697 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2698 mst = m0->m_pkthdr.snd_tag;
2703 if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) {
2707 set_mbuf_cflags(m0, cflags);
2708 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2711 set_mbuf_nsegs(m0, nsegs);
2712 set_mbuf_len16(m0, len16);
2716 if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2717 if (defragged++ > 0) {
2721 counter_u64_add(defrags, 1);
2722 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2726 *mp = m0 = m; /* update caller's copy after defrag */
2730 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2731 !(cflags & MC_NOMAP))) {
2732 counter_u64_add(pullups, 1);
2733 m0 = m_pullup(m0, m0->m_pkthdr.len);
2735 /* Should have left well enough alone. */
2739 *mp = m0; /* update caller's copy after pullup */
2742 set_mbuf_nsegs(m0, nsegs);
2743 set_mbuf_cflags(m0, cflags);
2744 calculate_mbuf_len16(m0, vm_wr);
2748 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2749 * checksumming is enabled. needs_outer_l4_csum happens to check for
2750 * all the right things.
2752 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2753 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2754 m0->m_pkthdr.snd_tag = NULL;
2755 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2760 if (!needs_hwcsum(m0)
2768 eh = mtod(m, struct ether_header *);
2769 eh_type = ntohs(eh->ether_type);
2770 if (eh_type == ETHERTYPE_VLAN) {
2771 struct ether_vlan_header *evh = (void *)eh;
2773 eh_type = ntohs(evh->evl_proto);
2774 m0->m_pkthdr.l2hlen = sizeof(*evh);
2776 m0->m_pkthdr.l2hlen = sizeof(*eh);
2779 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2783 case ETHERTYPE_IPV6:
2784 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2790 struct ip *ip = l3hdr;
2792 if (needs_vxlan_csum(m0)) {
2793 /* Driver will do the outer IP hdr checksum. */
2795 if (needs_vxlan_tso(m0)) {
2796 const uint16_t ipl = ip->ip_len;
2799 ip->ip_sum = ~in_cksum_hdr(ip);
2802 ip->ip_sum = in_cksum_hdr(ip);
2804 m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2809 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2810 log(LOG_ERR, "%s: ethertype 0x%04x unknown. "
2811 "if_cxgbe must be compiled with the same "
2812 "INET/INET6 options as the kernel.\n", __func__,
2819 if (needs_vxlan_csum(m0)) {
2820 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2821 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2823 /* Inner headers. */
2824 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2825 sizeof(struct udphdr) + sizeof(struct vxlan_header));
2826 eh_type = ntohs(eh->ether_type);
2827 if (eh_type == ETHERTYPE_VLAN) {
2828 struct ether_vlan_header *evh = (void *)eh;
2830 eh_type = ntohs(evh->evl_proto);
2831 m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2833 m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2834 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2838 case ETHERTYPE_IPV6:
2839 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2845 struct ip *ip = l3hdr;
2847 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2852 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2853 log(LOG_ERR, "%s: VXLAN hw offload requested"
2854 "with unknown ethertype 0x%04x. if_cxgbe "
2855 "must be compiled with the same INET/INET6 "
2856 "options as the kernel.\n", __func__,
2862 #if defined(INET) || defined(INET6)
2863 if (needs_inner_tcp_csum(m0)) {
2864 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2865 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2868 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2869 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2870 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2871 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2875 #if defined(INET) || defined(INET6)
2876 if (needs_outer_tcp_csum(m0)) {
2877 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2878 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2880 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2881 set_mbuf_eo_tsclk_tsoff(m0,
2882 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2883 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2885 set_mbuf_eo_tsclk_tsoff(m0, 0);
2886 } else if (needs_outer_udp_csum(m0)) {
2887 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2891 if (needs_eo(mst)) {
2894 /* EO WRs have the headers in the WR and not the GL. */
2895 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2896 m0->m_pkthdr.l4hlen;
2898 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2899 MPASS(cflags == mbuf_cflags(m0));
2900 set_mbuf_eo_nsegs(m0, nsegs);
2901 set_mbuf_eo_len16(m0,
2902 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2911 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2913 struct sge_eq *eq = &wrq->eq;
2914 struct adapter *sc = wrq->adapter;
2915 int ndesc, available;
2920 ndesc = tx_len16_to_desc(len16);
2921 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2925 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2926 drain_wrq_wr_list(sc, wrq);
2928 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2931 wr = alloc_wrqe(len16 * 16, wrq);
2932 if (__predict_false(wr == NULL))
2935 cookie->ndesc = ndesc;
2939 eq->cidx = read_hw_cidx(eq);
2940 if (eq->pidx == eq->cidx)
2941 available = eq->sidx - 1;
2943 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2944 if (available < ndesc)
2947 cookie->pidx = eq->pidx;
2948 cookie->ndesc = ndesc;
2949 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2951 w = &eq->desc[eq->pidx];
2952 IDXINCR(eq->pidx, ndesc, eq->sidx);
2953 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2955 wrq->ss_pidx = cookie->pidx;
2956 wrq->ss_len = len16 * 16;
2965 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2967 struct sge_eq *eq = &wrq->eq;
2968 struct adapter *sc = wrq->adapter;
2970 struct wrq_cookie *prev, *next;
2972 if (cookie->pidx == -1) {
2973 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2979 if (__predict_false(w == &wrq->ss[0])) {
2980 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2982 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2983 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2984 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2987 wrq->tx_wrs_direct++;
2990 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2991 pidx = cookie->pidx;
2992 MPASS(pidx >= 0 && pidx < eq->sidx);
2993 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2994 next = TAILQ_NEXT(cookie, link);
2996 MPASS(pidx == eq->dbidx);
2997 if (next == NULL || ndesc >= 16) {
2999 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
3002 * Note that the WR via which we'll request tx updates
3003 * is at pidx and not eq->pidx, which has moved on
3006 dst = (void *)&eq->desc[pidx];
3007 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3008 if (available < eq->sidx / 4 &&
3009 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3011 * XXX: This is not 100% reliable with some
3012 * types of WRs. But this is a very unusual
3013 * situation for an ofld/ctrl queue anyway.
3015 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3019 ring_eq_db(wrq->adapter, eq, ndesc);
3021 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3023 next->ndesc += ndesc;
3026 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3027 prev->ndesc += ndesc;
3029 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3031 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3032 drain_wrq_wr_list(sc, wrq);
3035 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3036 /* Doorbell must have caught up to the pidx. */
3037 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3044 can_resume_eth_tx(struct mp_ring *r)
3046 struct sge_eq *eq = r->cookie;
3048 return (total_available_tx_desc(eq) > eq->sidx / 8);
3052 cannot_use_txpkts(struct mbuf *m)
3054 /* maybe put a GL limit too, to avoid silliness? */
3056 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3060 discard_tx(struct sge_eq *eq)
3063 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3067 wr_can_update_eq(void *p)
3069 struct fw_eth_tx_pkts_wr *wr = p;
3071 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3073 case FW_ETH_TX_PKT_WR:
3074 case FW_ETH_TX_PKTS_WR:
3075 case FW_ETH_TX_PKTS2_WR:
3076 case FW_ETH_TX_PKT_VM_WR:
3077 case FW_ETH_TX_PKTS_VM_WR:
3085 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3086 struct fw_eth_tx_pkt_wr *wr)
3088 struct sge_eq *eq = &txq->eq;
3089 struct txpkts *txp = &txq->txp;
3091 if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3092 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3093 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3094 eq->equeqidx = eq->pidx;
3095 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3096 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3097 eq->equeqidx = eq->pidx;
3101 #if defined(__i386__) || defined(__amd64__)
3102 extern uint64_t tsc_freq;
3106 record_eth_tx_time(struct sge_txq *txq)
3108 const uint64_t cycles = get_cyclecount();
3109 const uint64_t last_tx = txq->last_tx;
3110 #if defined(__i386__) || defined(__amd64__)
3111 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3113 const uint64_t itg = 0;
3116 MPASS(cycles >= last_tx);
3117 txq->last_tx = cycles;
3118 return (cycles - last_tx < itg);
3122 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3123 * be consumed. Return the actual number consumed. 0 indicates a stall.
3126 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3128 struct sge_txq *txq = r->cookie;
3129 struct ifnet *ifp = txq->ifp;
3130 struct sge_eq *eq = &txq->eq;
3131 struct txpkts *txp = &txq->txp;
3132 struct vi_info *vi = ifp->if_softc;
3133 struct adapter *sc = vi->adapter;
3134 u_int total, remaining; /* # of packets */
3135 u_int n, avail, dbdiff; /* # of hardware descriptors */
3138 bool snd, recent_tx;
3139 void *wr; /* start of the last WR written to the ring */
3141 TXQ_LOCK_ASSERT_OWNED(txq);
3142 recent_tx = record_eth_tx_time(txq);
3144 remaining = IDXDIFF(pidx, cidx, r->size);
3145 if (__predict_false(discard_tx(eq))) {
3146 for (i = 0; i < txp->npkt; i++)
3147 m_freem(txp->mb[i]);
3149 while (cidx != pidx) {
3150 m0 = r->items[cidx];
3152 if (++cidx == r->size)
3155 reclaim_tx_descs(txq, eq->sidx);
3156 *coalescing = false;
3157 return (remaining); /* emptied */
3160 /* How many hardware descriptors do we have readily available. */
3161 if (eq->pidx == eq->cidx)
3162 avail = eq->sidx - 1;
3164 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3167 if (remaining == 0) {
3169 txq->txpkts_flush++;
3174 MPASS(remaining > 0);
3175 while (remaining > 0) {
3176 m0 = r->items[cidx];
3178 MPASS(m0->m_nextpkt == NULL);
3180 if (avail < 2 * SGE_MAX_WR_NDESC)
3181 avail += reclaim_tx_descs(txq, 64);
3183 if (t4_tx_coalesce == 0 && txp->npkt == 0)
3184 goto skip_coalescing;
3185 if (cannot_use_txpkts(m0))
3187 else if (recent_tx) {
3188 if (++txp->score == 0)
3189 txp->score = UINT8_MAX;
3192 if (txp->npkt > 0 || remaining > 1 ||
3193 txp->score >= t4_tx_coalesce_pkts ||
3194 atomic_load_int(&txq->eq.equiq) != 0) {
3195 if (vi->flags & TX_USES_VM_WR)
3196 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3198 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3204 MPASS(txp->npkt > 0);
3205 for (i = 0; i < txp->npkt; i++)
3206 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3207 if (txp->npkt > 1) {
3208 MPASS(avail >= tx_len16_to_desc(txp->len16));
3209 if (vi->flags & TX_USES_VM_WR)
3210 n = write_txpkts_vm_wr(sc, txq);
3212 n = write_txpkts_wr(sc, txq);
3215 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3216 if (vi->flags & TX_USES_VM_WR)
3217 n = write_txpkt_vm_wr(sc, txq,
3220 n = write_txpkt_wr(sc, txq, txp->mb[0],
3223 MPASS(n <= SGE_MAX_WR_NDESC);
3226 wr = &eq->desc[eq->pidx];
3227 IDXINCR(eq->pidx, n, eq->sidx);
3228 txp->npkt = 0; /* emptied */
3231 /* m0 was coalesced into txq->txpkts. */
3236 * m0 is suitable for tx coalescing but could not be
3237 * combined with the existing txq->txpkts, which has now
3238 * been transmitted. Start a new txpkts with m0.
3241 MPASS(txp->npkt == 0);
3245 MPASS(rc != 0 && rc != EAGAIN);
3246 MPASS(txp->npkt == 0);
3248 n = tx_len16_to_desc(mbuf_len16(m0));
3249 if (__predict_false(avail < n)) {
3250 avail += reclaim_tx_descs(txq, min(n, 32));
3252 break; /* out of descriptors */
3255 wr = &eq->desc[eq->pidx];
3256 if (mbuf_cflags(m0) & MC_RAW_WR) {
3257 n = write_raw_wr(txq, wr, m0, avail);
3259 } else if (mbuf_cflags(m0) & MC_TLS) {
3260 ETHER_BPF_MTAP(ifp, m0);
3261 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0),
3265 ETHER_BPF_MTAP(ifp, m0);
3266 if (vi->flags & TX_USES_VM_WR)
3267 n = write_txpkt_vm_wr(sc, txq, m0);
3269 n = write_txpkt_wr(sc, txq, m0, avail);
3271 MPASS(n >= 1 && n <= avail);
3272 if (!(mbuf_cflags(m0) & MC_TLS))
3273 MPASS(n <= SGE_MAX_WR_NDESC);
3277 IDXINCR(eq->pidx, n, eq->sidx);
3279 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */
3280 if (wr_can_update_eq(wr))
3281 set_txupdate_flags(txq, avail, wr);
3282 ring_eq_db(sc, eq, dbdiff);
3283 avail += reclaim_tx_descs(txq, 32);
3289 if (__predict_false(++cidx == r->size))
3293 if (wr_can_update_eq(wr))
3294 set_txupdate_flags(txq, avail, wr);
3295 ring_eq_db(sc, eq, dbdiff);
3296 reclaim_tx_descs(txq, 32);
3297 } else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3298 atomic_load_int(&txq->eq.equiq) == 0) {
3300 * If nothing was submitted to the chip for tx (it was coalesced
3301 * into txpkts instead) and there is no tx update outstanding
3302 * then we need to send txpkts now.
3305 MPASS(txp->npkt > 0);
3306 for (i = 0; i < txp->npkt; i++)
3307 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3308 if (txp->npkt > 1) {
3309 MPASS(avail >= tx_len16_to_desc(txp->len16));
3310 if (vi->flags & TX_USES_VM_WR)
3311 n = write_txpkts_vm_wr(sc, txq);
3313 n = write_txpkts_wr(sc, txq);
3316 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3317 if (vi->flags & TX_USES_VM_WR)
3318 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3320 n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3322 MPASS(n <= SGE_MAX_WR_NDESC);
3323 wr = &eq->desc[eq->pidx];
3324 IDXINCR(eq->pidx, n, eq->sidx);
3325 txp->npkt = 0; /* emptied */
3327 MPASS(wr_can_update_eq(wr));
3328 set_txupdate_flags(txq, avail - n, wr);
3329 ring_eq_db(sc, eq, n);
3330 reclaim_tx_descs(txq, 32);
3332 *coalescing = txp->npkt > 0;
3338 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3339 int qsize, int intr_idx, int cong)
3342 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3343 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3344 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3345 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3346 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count,
3347 ("%s: bad intr_idx %d", __func__, intr_idx));
3350 iq->state = IQS_DISABLED;
3352 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3353 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3354 if (pktc_idx >= 0) {
3355 iq->intr_params |= F_QINTR_CNT_EN;
3356 iq->intr_pktc_idx = pktc_idx;
3358 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3359 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3360 iq->intr_idx = intr_idx;
3365 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3367 struct sge_params *sp = &sc->params.sge;
3370 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3371 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3372 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3373 if (sc->flags & BUF_PACKING_OK &&
3374 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3375 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3376 fl->flags |= FL_BUF_PACKING;
3377 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3378 fl->safe_zidx = sc->sge.safe_zidx;
3379 if (fl->flags & FL_BUF_PACKING) {
3380 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3381 fl->buf_boundary = sp->pack_boundary;
3383 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3384 fl->buf_boundary = 16;
3386 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3387 fl->buf_boundary = sp->pad_boundary;
3391 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3392 uint8_t tx_chan, struct sge_iq *iq, char *name)
3394 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD,
3395 ("%s: bad qtype %d", __func__, eqtype));
3398 eq->tx_chan = tx_chan;
3400 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3401 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3402 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3406 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3407 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3411 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3412 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3414 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc);
3418 rc = bus_dmamem_alloc(*tag, va,
3419 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3421 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc);
3425 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3427 CH_ERR(sc, "cannot load DMA map: %d\n", rc);
3432 free_ring(sc, *tag, *map, *pa, *va);
3438 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3439 bus_addr_t pa, void *va)
3442 bus_dmamap_unload(tag, map);
3444 bus_dmamem_free(tag, va, map);
3446 bus_dma_tag_destroy(tag);
3452 * Allocates the software resources (mainly memory and sysctl nodes) for an
3453 * ingress queue and an optional freelist.
3455 * Sets IQ_SW_ALLOCATED and returns 0 on success.
3458 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3459 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
3463 struct adapter *sc = vi->adapter;
3465 MPASS(!(iq->flags & IQ_SW_ALLOCATED));
3467 len = iq->qsize * IQ_ESIZE;
3468 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3469 (void **)&iq->desc);
3474 len = fl->qsize * EQ_ESIZE;
3475 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3476 &fl->ba, (void **)&fl->desc);
3478 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba,
3483 /* Allocate space for one software descriptor per buffer. */
3484 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc),
3485 M_CXGBE, M_ZERO | M_WAITOK);
3487 add_fl_sysctls(sc, ctx, oid, fl);
3488 iq->flags |= IQ_HAS_FL;
3490 add_iq_sysctls(ctx, oid, iq);
3491 iq->flags |= IQ_SW_ALLOCATED;
3497 * Frees all software resources (memory and locks) associated with an ingress
3498 * queue and an optional freelist.
3501 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3503 MPASS(iq->flags & IQ_SW_ALLOCATED);
3506 MPASS(iq->flags & IQ_HAS_FL);
3507 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc);
3508 free_fl_buffers(sc, fl);
3509 free(fl->sdesc, M_CXGBE);
3510 mtx_destroy(&fl->fl_lock);
3511 bzero(fl, sizeof(*fl));
3513 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3514 bzero(iq, sizeof(*iq));
3518 * Allocates a hardware ingress queue and an optional freelist that will be
3519 * associated with it.
3521 * Returns errno on failure. Resources allocated up to that point may still be
3522 * allocated. Caller is responsible for cleanup in case this function fails.
3525 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3527 int rc, i, cntxt_id;
3529 struct adapter *sc = vi->adapter;
3532 MPASS (!(iq->flags & IQ_HW_ALLOCATED));
3534 bzero(&c, sizeof(c));
3535 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3536 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3537 V_FW_IQ_CMD_VFN(0));
3539 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3542 /* Special handling for firmware event queue */
3543 if (iq == &sc->sge.fwq)
3544 v |= F_FW_IQ_CMD_IQASYNCH;
3546 if (iq->intr_idx < 0) {
3547 /* Forwarded interrupts, all headed to fwq */
3548 v |= F_FW_IQ_CMD_IQANDST;
3549 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3551 KASSERT(iq->intr_idx < sc->intr_count,
3552 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx));
3553 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx);
3556 bzero(iq->desc, iq->qsize * IQ_ESIZE);
3557 c.type_to_iqandstindex = htobe32(v |
3558 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3559 V_FW_IQ_CMD_VIID(vi->viid) |
3560 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3561 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) |
3562 F_FW_IQ_CMD_IQGTSMODE |
3563 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3564 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3565 c.iqsize = htobe16(iq->qsize);
3566 c.iqaddr = htobe64(iq->ba);
3568 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3571 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
3572 c.iqns_to_fl0congen |=
3573 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3574 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3575 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3576 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3578 if (iq->cong >= 0) {
3579 c.iqns_to_fl0congen |=
3580 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(iq->cong) |
3581 F_FW_IQ_CMD_FL0CONGCIF |
3582 F_FW_IQ_CMD_FL0CONGEN);
3584 c.fl0dcaen_to_fl0cidxfthresh =
3585 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3586 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3587 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3588 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3589 c.fl0size = htobe16(fl->qsize);
3590 c.fl0addr = htobe64(fl->ba);
3593 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3595 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc);
3600 iq->gen = F_RSPD_GEN;
3601 iq->cntxt_id = be16toh(c.iqid);
3602 iq->abs_id = be16toh(c.physiqid);
3604 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3605 if (cntxt_id >= sc->sge.iqmap_sz) {
3606 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3607 cntxt_id, sc->sge.iqmap_sz - 1);
3609 sc->sge.iqmap[cntxt_id] = iq;
3614 MPASS(!(fl->flags & FL_BUF_RESUME));
3615 for (i = 0; i < fl->sidx * 8; i++)
3616 MPASS(fl->sdesc[i].cl == NULL);
3618 fl->cntxt_id = be16toh(c.fl0id);
3619 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0;
3621 fl->flags &= ~(FL_STARVING | FL_DOOMED);
3623 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3624 if (cntxt_id >= sc->sge.eqmap_sz) {
3625 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3626 __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3628 sc->sge.eqmap[cntxt_id] = (void *)fl;
3631 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3632 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3633 uint32_t mask = (1 << s_qpp) - 1;
3634 volatile uint8_t *udb;
3636 udb = sc->udbs_base + UDBS_DB_OFFSET;
3637 udb += (qid >> s_qpp) << PAGE_SHIFT;
3639 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3640 udb += qid << UDBS_SEG_SHIFT;
3643 fl->udb = (volatile void *)udb;
3645 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3648 /* Enough to make sure the SGE doesn't think it's starved */
3649 refill_fl(sc, fl, fl->lowat);
3653 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && iq->cong >= 0) {
3654 uint32_t param, val;
3656 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3657 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3658 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3663 for (i = 0; i < 4; i++) {
3664 if (iq->cong & (1 << i))
3665 val |= 1 << (i << 2);
3669 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3671 /* report error but carry on */
3672 CH_ERR(sc, "failed to set congestion manager context "
3673 "for ingress queue %d: %d\n", iq->cntxt_id, rc);
3677 /* Enable IQ interrupts */
3678 atomic_store_rel_int(&iq->state, IQS_IDLE);
3679 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3680 V_INGRESSQID(iq->cntxt_id));
3682 iq->flags |= IQ_HW_ALLOCATED;
3688 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3692 MPASS(iq->flags & IQ_HW_ALLOCATED);
3693 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
3694 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
3696 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc);
3699 iq->flags &= ~IQ_HW_ALLOCATED;
3705 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3708 struct sysctl_oid_list *children;
3710 if (ctx == NULL || oid == NULL)
3713 children = SYSCTL_CHILDREN(oid);
3714 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3715 "bus address of descriptor ring");
3716 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3717 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3718 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3719 &iq->abs_id, 0, "absolute id of the queue");
3720 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3721 &iq->cntxt_id, 0, "SGE context id of the queue");
3722 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3723 0, "consumer index");
3727 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3728 struct sysctl_oid *oid, struct sge_fl *fl)
3730 struct sysctl_oid_list *children;
3732 if (ctx == NULL || oid == NULL)
3735 children = SYSCTL_CHILDREN(oid);
3736 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3737 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3738 children = SYSCTL_CHILDREN(oid);
3740 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3741 &fl->ba, "bus address of descriptor ring");
3742 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3743 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3744 "desc ring size in bytes");
3745 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3746 &fl->cntxt_id, 0, "SGE context id of the freelist");
3747 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3748 fl_pad ? 1 : 0, "padding enabled");
3749 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3750 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3751 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3752 0, "consumer index");
3753 if (fl->flags & FL_BUF_PACKING) {
3754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3755 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3757 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3758 0, "producer index");
3759 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3760 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3761 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3762 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3763 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3764 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3771 alloc_fwq(struct adapter *sc)
3774 struct sge_iq *fwq = &sc->sge.fwq;
3775 struct vi_info *vi = &sc->port[0]->vi[0];
3777 if (!(fwq->flags & IQ_SW_ALLOCATED)) {
3778 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3780 if (sc->flags & IS_VF)
3783 intr_idx = sc->intr_count > 1 ? 1 : 0;
3784 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1);
3785 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid);
3787 CH_ERR(sc, "failed to allocate fwq: %d\n", rc);
3790 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3793 if (!(fwq->flags & IQ_HW_ALLOCATED)) {
3794 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3796 rc = alloc_iq_fl_hwq(vi, fwq, NULL);
3798 CH_ERR(sc, "failed to create hw fwq: %d\n", rc);
3801 MPASS(fwq->flags & IQ_HW_ALLOCATED);
3811 free_fwq(struct adapter *sc)
3813 struct sge_iq *fwq = &sc->sge.fwq;
3815 if (fwq->flags & IQ_HW_ALLOCATED) {
3816 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3817 free_iq_fl_hwq(sc, fwq, NULL);
3818 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3821 if (fwq->flags & IQ_SW_ALLOCATED) {
3822 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3823 free_iq_fl(sc, fwq, NULL);
3824 MPASS(!(fwq->flags & IQ_SW_ALLOCATED));
3832 alloc_ctrlq(struct adapter *sc, int idx)
3836 struct sysctl_oid *oid;
3837 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3839 MPASS(idx < sc->params.nports);
3841 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
3842 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3844 snprintf(name, sizeof(name), "%d", idx);
3845 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid),
3846 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3849 snprintf(name, sizeof(name), "%s ctrlq%d",
3850 device_get_nameunit(sc->dev), idx);
3851 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE,
3852 sc->port[idx]->tx_chan, &sc->sge.fwq, name);
3853 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
3855 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
3856 sysctl_remove_oid(oid, 1, 1);
3859 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3862 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) {
3863 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3865 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
3867 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
3870 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED);
3880 free_ctrlq(struct adapter *sc, int idx)
3882 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3884 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) {
3885 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3886 free_eq_hwq(sc, NULL, &ctrlq->eq);
3887 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3890 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) {
3891 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3892 free_wrq(sc, ctrlq);
3893 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED));
3898 tnl_cong(struct port_info *pi, int drop)
3906 return (pi->rx_e_chan_map);
3913 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
3917 struct adapter *sc = vi->adapter;
3918 struct ifnet *ifp = vi->ifp;
3919 struct sysctl_oid *oid;
3922 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) {
3923 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
3924 #if defined(INET) || defined(INET6)
3925 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs);
3928 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */
3930 if (ifp->if_capenable & IFCAP_LRO)
3931 rxq->iq.flags |= IQ_LRO_ENABLED;
3933 if (ifp->if_capenable & IFCAP_HWRXTSTMP)
3934 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3937 snprintf(name, sizeof(name), "%d", idx);
3938 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid),
3939 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3942 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
3943 intr_idx, tnl_cong(vi->pi, cong_drop));
3944 snprintf(name, sizeof(name), "%s rxq%d-fl",
3945 device_get_nameunit(vi->dev), idx);
3946 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
3947 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid);
3949 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc);
3950 sysctl_remove_oid(oid, 1, 1);
3951 #if defined(INET) || defined(INET6)
3952 tcp_lro_free(&rxq->lro);
3953 rxq->lro.ifp = NULL;
3957 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3958 add_rxq_sysctls(&vi->ctx, oid, rxq);
3961 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) {
3962 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3963 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl);
3965 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc);
3968 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED);
3971 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3973 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3974 ("iq_base mismatch"));
3975 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3976 ("PF with non-zero iq_base"));
3979 * The freelist is just barely above the starvation threshold
3980 * right now, fill it up a bit more.
3983 refill_fl(sc, &rxq->fl, 128);
3984 FL_UNLOCK(&rxq->fl);
3994 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3996 if (rxq->iq.flags & IQ_HW_ALLOCATED) {
3997 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3998 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl);
3999 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4002 if (rxq->iq.flags & IQ_SW_ALLOCATED) {
4003 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4004 #if defined(INET) || defined(INET6)
4005 tcp_lro_free(&rxq->lro);
4007 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl);
4008 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED));
4009 bzero(rxq, sizeof(*rxq));
4014 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4015 struct sge_rxq *rxq)
4017 struct sysctl_oid_list *children;
4019 if (ctx == NULL || oid == NULL)
4022 children = SYSCTL_CHILDREN(oid);
4023 #if defined(INET) || defined(INET6)
4024 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
4025 &rxq->lro.lro_queued, 0, NULL);
4026 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
4027 &rxq->lro.lro_flushed, 0, NULL);
4029 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
4030 &rxq->rxcsum, "# of times hardware assisted with checksum");
4031 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD,
4032 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag");
4033 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD,
4035 "# of times hardware assisted with inner checksum (VXLAN)");
4043 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx,
4044 int intr_idx, int maxp)
4047 struct adapter *sc = vi->adapter;
4048 struct sysctl_oid *oid;
4051 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) {
4052 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4054 snprintf(name, sizeof(name), "%d", idx);
4055 oid = SYSCTL_ADD_NODE(&vi->ctx,
4056 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name,
4057 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue");
4059 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
4060 vi->qsize_rxq, intr_idx, 0);
4061 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
4062 device_get_nameunit(vi->dev), idx);
4063 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
4064 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx,
4067 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx,
4069 sysctl_remove_oid(oid, 1, 1);
4072 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4073 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq);
4076 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) {
4077 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4078 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl);
4080 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx,
4084 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED);
4093 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
4095 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) {
4096 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4097 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4098 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4101 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) {
4102 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4103 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4104 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED));
4105 bzero(ofld_rxq, sizeof(*ofld_rxq));
4110 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4111 struct sge_ofld_rxq *ofld_rxq)
4113 struct sysctl_oid_list *children;
4115 if (ctx == NULL || oid == NULL)
4118 children = SYSCTL_CHILDREN(oid);
4119 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
4120 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records,
4121 "# of TOE TLS records received");
4122 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
4123 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets,
4124 "# of payload octets in received TOE TLS records");
4129 * Returns a reasonable automatic cidx flush threshold for a given queue size.
4132 qsize_to_fthresh(int qsize)
4136 while (!powerof2(qsize))
4138 fthresh = ilog2(qsize);
4139 if (fthresh > X_CIDXFLUSHTHRESH_128)
4140 fthresh = X_CIDXFLUSHTHRESH_128;
4146 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4149 struct fw_eq_ctrl_cmd c;
4150 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4152 bzero(&c, sizeof(c));
4154 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4155 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4156 V_FW_EQ_CTRL_CMD_VFN(0));
4157 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4158 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4159 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4160 c.physeqid_pkd = htobe32(0);
4161 c.fetchszm_to_iqid =
4162 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4163 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4164 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4166 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4167 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4168 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4169 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4170 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4171 c.eqaddr = htobe64(eq->ba);
4173 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4175 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
4180 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4181 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4182 if (cntxt_id >= sc->sge.eqmap_sz)
4183 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4184 cntxt_id, sc->sge.eqmap_sz - 1);
4185 sc->sge.eqmap[cntxt_id] = eq;
4191 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4194 struct fw_eq_eth_cmd c;
4195 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4197 bzero(&c, sizeof(c));
4199 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4200 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4201 V_FW_EQ_ETH_CMD_VFN(0));
4202 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4203 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4204 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4205 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4206 c.fetchszm_to_iqid =
4207 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4208 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4209 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4211 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4212 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4213 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4214 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4215 c.eqaddr = htobe64(eq->ba);
4217 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4219 device_printf(vi->dev,
4220 "failed to create Ethernet egress queue: %d\n", rc);
4224 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4225 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4226 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4227 if (cntxt_id >= sc->sge.eqmap_sz)
4228 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4229 cntxt_id, sc->sge.eqmap_sz - 1);
4230 sc->sge.eqmap[cntxt_id] = eq;
4235 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4237 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4240 struct fw_eq_ofld_cmd c;
4241 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4243 bzero(&c, sizeof(c));
4245 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4246 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4247 V_FW_EQ_OFLD_CMD_VFN(0));
4248 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4249 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4250 c.fetchszm_to_iqid =
4251 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4252 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4253 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4255 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4256 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4257 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4258 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4259 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4260 c.eqaddr = htobe64(eq->ba);
4262 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4264 device_printf(vi->dev,
4265 "failed to create egress queue for TCP offload: %d\n", rc);
4269 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4270 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4271 if (cntxt_id >= sc->sge.eqmap_sz)
4272 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4273 cntxt_id, sc->sge.eqmap_sz - 1);
4274 sc->sge.eqmap[cntxt_id] = eq;
4282 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx,
4283 struct sysctl_oid *oid)
4288 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4290 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4291 len = qsize * EQ_ESIZE;
4292 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba,
4293 (void **)&eq->desc);
4296 if (ctx != NULL && oid != NULL)
4297 add_eq_sysctls(sc, ctx, oid, eq);
4298 eq->flags |= EQ_SW_ALLOCATED;
4305 free_eq(struct adapter *sc, struct sge_eq *eq)
4307 MPASS(eq->flags & EQ_SW_ALLOCATED);
4308 MPASS(eq->pidx == eq->cidx);
4310 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4311 mtx_destroy(&eq->eq_lock);
4312 bzero(eq, sizeof(*eq));
4316 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
4317 struct sysctl_oid *oid, struct sge_eq *eq)
4319 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4321 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba,
4322 "bus address of descriptor ring");
4323 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4324 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4325 "desc ring size in bytes");
4326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4327 &eq->abs_id, 0, "absolute id of the queue");
4328 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4329 &eq->cntxt_id, 0, "SGE context id of the queue");
4330 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx,
4331 0, "consumer index");
4332 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx,
4333 0, "producer index");
4334 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4335 eq->sidx, "status page index");
4339 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4343 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4345 eq->iqid = eq->iq->cntxt_id;
4346 eq->pidx = eq->cidx = eq->dbidx = 0;
4347 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4349 eq->doorbells = sc->doorbells;
4350 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len);
4354 rc = ctrl_eq_alloc(sc, eq);
4358 rc = eth_eq_alloc(sc, vi, eq);
4361 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4363 rc = ofld_eq_alloc(sc, vi, eq);
4368 panic("%s: invalid eq type %d.", __func__, eq->type);
4371 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n",
4376 if (isset(&eq->doorbells, DOORBELL_UDB) ||
4377 isset(&eq->doorbells, DOORBELL_UDBWC) ||
4378 isset(&eq->doorbells, DOORBELL_WCWR)) {
4379 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4380 uint32_t mask = (1 << s_qpp) - 1;
4381 volatile uint8_t *udb;
4383 udb = sc->udbs_base + UDBS_DB_OFFSET;
4384 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
4385 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
4386 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4387 clrbit(&eq->doorbells, DOORBELL_WCWR);
4389 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
4392 eq->udb = (volatile void *)udb;
4395 eq->flags |= EQ_HW_ALLOCATED;
4400 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq)
4404 MPASS(eq->flags & EQ_HW_ALLOCATED);
4408 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4411 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4413 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4415 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4419 panic("%s: invalid eq type %d.", __func__, eq->type);
4422 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc);
4425 eq->flags &= ~EQ_HW_ALLOCATED;
4431 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4432 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
4434 struct sge_eq *eq = &wrq->eq;
4437 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4439 rc = alloc_eq(sc, eq, ctx, oid);
4442 MPASS(eq->flags & EQ_SW_ALLOCATED);
4443 /* Can't fail after this. */
4446 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4447 TAILQ_INIT(&wrq->incomplete_wrs);
4448 STAILQ_INIT(&wrq->wr_list);
4449 wrq->nwr_pending = 0;
4450 wrq->ndesc_needed = 0;
4451 add_wrq_sysctls(ctx, oid, wrq);
4457 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4459 free_eq(sc, &wrq->eq);
4460 MPASS(wrq->nwr_pending == 0);
4461 bzero(wrq, sizeof(*wrq));
4465 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4466 struct sge_wrq *wrq)
4468 struct sysctl_oid_list *children;
4470 if (ctx == NULL || oid == NULL)
4473 children = SYSCTL_CHILDREN(oid);
4474 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4475 &wrq->tx_wrs_direct, "# of work requests (direct)");
4476 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4477 &wrq->tx_wrs_copied, "# of work requests (copied)");
4478 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4479 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4486 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx)
4489 struct port_info *pi = vi->pi;
4490 struct adapter *sc = vi->adapter;
4491 struct sge_eq *eq = &txq->eq;
4494 struct sysctl_oid *oid;
4496 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4497 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4499 snprintf(name, sizeof(name), "%d", idx);
4500 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid),
4501 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4504 iqidx = vi->first_rxq + (idx % vi->nrxq);
4505 snprintf(name, sizeof(name), "%s txq%d",
4506 device_get_nameunit(vi->dev), idx);
4507 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
4508 &sc->sge.rxq[iqidx].iq, name);
4510 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx,
4511 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK);
4513 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n",
4516 sysctl_remove_oid(oid, 1, 1);
4520 rc = alloc_eq(sc, eq, &vi->ctx, oid);
4522 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc);
4523 mp_ring_free(txq->r);
4526 MPASS(eq->flags & EQ_SW_ALLOCATED);
4527 /* Can't fail after this point. */
4529 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4531 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4532 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4535 add_txq_sysctls(vi, &vi->ctx, oid, txq);
4538 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4539 MPASS(eq->flags & EQ_SW_ALLOCATED);
4540 rc = alloc_eq_hwq(sc, vi, eq);
4542 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
4545 MPASS(eq->flags & EQ_HW_ALLOCATED);
4546 /* Can't fail after this point. */
4549 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4551 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4552 ("eq_base mismatch"));
4553 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4554 ("PF with non-zero eq_base"));
4557 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4558 txq->txp.max_npkt = min(nitems(txp->mb),
4559 sc->params.max_pkts_per_eth_tx_pkts_wr);
4560 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4561 txq->txp.max_npkt--;
4563 if (vi->flags & TX_USES_VM_WR)
4564 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4565 V_TXPKT_INTF(pi->tx_chan));
4567 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4568 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4569 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4581 free_txq(struct vi_info *vi, struct sge_txq *txq)
4583 struct adapter *sc = vi->adapter;
4584 struct sge_eq *eq = &txq->eq;
4586 if (eq->flags & EQ_HW_ALLOCATED) {
4587 MPASS(eq->flags & EQ_SW_ALLOCATED);
4588 free_eq_hwq(sc, NULL, eq);
4589 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4592 if (eq->flags & EQ_SW_ALLOCATED) {
4593 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4594 sglist_free(txq->gl);
4595 free(txq->sdesc, M_CXGBE);
4596 mp_ring_free(txq->r);
4598 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4599 bzero(txq, sizeof(*txq));
4604 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
4605 struct sysctl_oid *oid, struct sge_txq *txq)
4608 struct sysctl_oid_list *children;
4610 if (ctx == NULL || oid == NULL)
4614 children = SYSCTL_CHILDREN(oid);
4616 mp_ring_sysctls(txq->r, ctx, children);
4618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc",
4619 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq,
4620 sysctl_tc, "I", "traffic class (-1 means none)");
4622 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4623 &txq->txcsum, "# of times hardware assisted with checksum");
4624 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD,
4625 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag");
4626 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4627 &txq->tso_wrs, "# of TSO work requests");
4628 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4629 &txq->imm_wrs, "# of work requests with immediate data");
4630 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4631 &txq->sgl_wrs, "# of work requests with direct SGL");
4632 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4633 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4634 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD,
4635 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests");
4636 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD,
4637 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests");
4638 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD,
4640 "# of frames tx'd using type0 txpkts work requests");
4641 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD,
4643 "# of frames tx'd using type1 txpkts work requests");
4644 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD,
4646 "# of times txpkts had to be flushed out by an egress-update");
4647 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4648 &txq->raw_wrs, "# of raw work requests (non-packets)");
4649 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD,
4650 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4651 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD,
4653 "# of times hardware assisted with inner checksums (VXLAN)");
4657 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records",
4658 CTLFLAG_RD, &txq->kern_tls_records,
4659 "# of NIC TLS records transmitted");
4660 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short",
4661 CTLFLAG_RD, &txq->kern_tls_short,
4662 "# of short NIC TLS records transmitted");
4663 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial",
4664 CTLFLAG_RD, &txq->kern_tls_partial,
4665 "# of partial NIC TLS records transmitted");
4666 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full",
4667 CTLFLAG_RD, &txq->kern_tls_full,
4668 "# of full NIC TLS records transmitted");
4669 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets",
4670 CTLFLAG_RD, &txq->kern_tls_octets,
4671 "# of payload octets in transmitted NIC TLS records");
4672 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
4673 CTLFLAG_RD, &txq->kern_tls_waste,
4674 "# of octets DMAd but not transmitted in NIC TLS records");
4675 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
4676 CTLFLAG_RD, &txq->kern_tls_options,
4677 "# of NIC TLS options-only packets transmitted");
4678 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
4679 CTLFLAG_RD, &txq->kern_tls_header,
4680 "# of NIC TLS header-only packets transmitted");
4681 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
4682 CTLFLAG_RD, &txq->kern_tls_fin,
4683 "# of NIC TLS FIN-only packets transmitted");
4684 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
4685 CTLFLAG_RD, &txq->kern_tls_fin_short,
4686 "# of NIC TLS padded FIN packets on short TLS records");
4687 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
4688 CTLFLAG_RD, &txq->kern_tls_cbc,
4689 "# of NIC TLS sessions using AES-CBC");
4690 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm",
4691 CTLFLAG_RD, &txq->kern_tls_gcm,
4692 "# of NIC TLS sessions using AES-GCM");
4697 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4702 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
4704 struct sysctl_oid *oid;
4705 struct port_info *pi = vi->pi;
4706 struct adapter *sc = vi->adapter;
4707 struct sge_eq *eq = &ofld_txq->wrq.eq;
4712 MPASS(idx < vi->nofldtxq);
4714 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4715 snprintf(name, sizeof(name), "%d", idx);
4716 oid = SYSCTL_ADD_NODE(&vi->ctx,
4717 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name,
4718 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
4720 snprintf(name, sizeof(name), "%s ofld_txq%d",
4721 device_get_nameunit(vi->dev), idx);
4722 if (vi->nofldrxq > 0) {
4723 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq);
4724 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4725 &sc->sge.ofld_rxq[iqidx].iq, name);
4727 iqidx = vi->first_rxq + (idx % vi->nrxq);
4728 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4729 &sc->sge.rxq[iqidx].iq, name);
4732 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid);
4734 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx,
4736 sysctl_remove_oid(oid, 1, 1);
4739 MPASS(eq->flags & EQ_SW_ALLOCATED);
4740 /* Can't fail after this point. */
4742 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK);
4743 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK);
4744 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK);
4745 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK);
4746 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq);
4749 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4750 rc = alloc_eq_hwq(sc, vi, eq);
4752 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
4756 MPASS(eq->flags & EQ_HW_ALLOCATED);
4766 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq)
4768 struct adapter *sc = vi->adapter;
4769 struct sge_eq *eq = &ofld_txq->wrq.eq;
4771 if (eq->flags & EQ_HW_ALLOCATED) {
4772 MPASS(eq->flags & EQ_SW_ALLOCATED);
4773 free_eq_hwq(sc, NULL, eq);
4774 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4777 if (eq->flags & EQ_SW_ALLOCATED) {
4778 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4779 counter_u64_free(ofld_txq->tx_iscsi_pdus);
4780 counter_u64_free(ofld_txq->tx_iscsi_octets);
4781 counter_u64_free(ofld_txq->tx_toe_tls_records);
4782 counter_u64_free(ofld_txq->tx_toe_tls_octets);
4783 free_wrq(sc, &ofld_txq->wrq);
4784 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4785 bzero(ofld_txq, sizeof(*ofld_txq));
4790 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4791 struct sge_ofld_txq *ofld_txq)
4793 struct sysctl_oid_list *children;
4795 if (ctx == NULL || oid == NULL)
4798 children = SYSCTL_CHILDREN(oid);
4799 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus",
4800 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus,
4801 "# of iSCSI PDUs transmitted");
4802 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets",
4803 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets,
4804 "# of payload octets in transmitted iSCSI PDUs");
4805 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records",
4806 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records,
4807 "# of TOE TLS records transmitted");
4808 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets",
4809 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets,
4810 "# of payload octets in transmitted TOE TLS records");
4815 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4817 bus_addr_t *ba = arg;
4820 ("%s meant for single segment mappings only.", __func__));
4822 *ba = error ? 0 : segs->ds_addr;
4826 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4830 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4834 v = fl->dbval | V_PIDX(n);
4836 *fl->udb = htole32(v);
4838 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4839 IDXINCR(fl->dbidx, n, fl->sidx);
4843 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4844 * recycled do not count towards this allocation budget.
4846 * Returns non-zero to indicate that this freelist should be added to the list
4847 * of starving freelists.
4850 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4853 struct fl_sdesc *sd;
4856 struct rx_buf_info *rxb;
4857 struct cluster_metadata *clm;
4858 uint16_t max_pidx, zidx = fl->zidx;
4859 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4861 FL_LOCK_ASSERT_OWNED(fl);
4864 * We always stop at the beginning of the hardware descriptor that's just
4865 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4866 * which would mean an empty freelist to the chip.
4868 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4869 if (fl->pidx == max_pidx * 8)
4872 d = &fl->desc[fl->pidx];
4873 sd = &fl->sdesc[fl->pidx];
4874 rxb = &sc->sge.rx_buf_info[zidx];
4878 if (sd->cl != NULL) {
4880 if (sd->nmbuf == 0) {
4882 * Fast recycle without involving any atomics on
4883 * the cluster's metadata (if the cluster has
4884 * metadata). This happens when all frames
4885 * received in the cluster were small enough to
4886 * fit within a single mbuf each.
4888 fl->cl_fast_recycled++;
4893 * Cluster is guaranteed to have metadata. Clusters
4894 * without metadata always take the fast recycle path
4895 * when they're recycled.
4897 clm = cl_metadata(sd);
4900 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4902 counter_u64_add(extfree_rels, 1);
4905 sd->cl = NULL; /* gave up my reference */
4907 MPASS(sd->cl == NULL);
4908 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4909 if (__predict_false(cl == NULL)) {
4910 if (zidx != fl->safe_zidx) {
4911 zidx = fl->safe_zidx;
4912 rxb = &sc->sge.rx_buf_info[zidx];
4913 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4921 pa = pmap_kextract((vm_offset_t)cl);
4925 if (fl->flags & FL_BUF_PACKING) {
4926 *d = htobe64(pa | rxb->hwidx2);
4927 sd->moff = rxb->size2;
4929 *d = htobe64(pa | rxb->hwidx1);
4936 if (__predict_false((++fl->pidx & 7) == 0)) {
4937 uint16_t pidx = fl->pidx >> 3;
4939 if (__predict_false(pidx == fl->sidx)) {
4945 if (n < 8 || pidx == max_pidx)
4948 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4953 if ((fl->pidx >> 3) != fl->dbidx)
4956 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4960 * Attempt to refill all starving freelists.
4963 refill_sfl(void *arg)
4965 struct adapter *sc = arg;
4966 struct sge_fl *fl, *fl_temp;
4968 mtx_assert(&sc->sfl_lock, MA_OWNED);
4969 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4971 refill_fl(sc, fl, 64);
4972 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4973 TAILQ_REMOVE(&sc->sfl, fl, link);
4974 fl->flags &= ~FL_STARVING;
4979 if (!TAILQ_EMPTY(&sc->sfl))
4980 callout_schedule(&sc->sfl_callout, hz / 5);
4984 * Release the driver's reference on all buffers in the given freelist. Buffers
4985 * with kernel references cannot be freed and will prevent the driver from being
4989 free_fl_buffers(struct adapter *sc, struct sge_fl *fl)
4991 struct fl_sdesc *sd;
4992 struct cluster_metadata *clm;
4996 for (i = 0; i < fl->sidx * 8; i++, sd++) {
5001 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
5002 else if (fl->flags & FL_BUF_PACKING) {
5003 clm = cl_metadata(sd);
5004 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5005 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
5007 counter_u64_add(extfree_rels, 1);
5013 if (fl->flags & FL_BUF_RESUME) {
5015 fl->flags &= ~FL_BUF_RESUME;
5020 get_pkt_gl(struct mbuf *m, struct sglist *gl)
5027 rc = sglist_append_mbuf(gl, m);
5028 if (__predict_false(rc != 0)) {
5029 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
5030 "with %d.", __func__, m, mbuf_nsegs(m), rc);
5033 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
5034 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
5035 mbuf_nsegs(m), gl->sg_nseg));
5036 #if 0 /* vm_wr not readily available here. */
5037 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
5038 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
5039 gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
5044 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5047 txpkt_len16(u_int nsegs, const u_int extra)
5053 nsegs--; /* first segment is part of ulptx_sgl */
5054 n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
5055 sizeof(struct cpl_tx_pkt_core) +
5056 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5058 return (howmany(n, 16));
5062 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
5066 txpkt_vm_len16(u_int nsegs, const u_int extra)
5072 nsegs--; /* first segment is part of ulptx_sgl */
5073 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
5074 sizeof(struct cpl_tx_pkt_core) +
5075 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5077 return (howmany(n, 16));
5081 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
5083 const int lso = sizeof(struct cpl_tx_pkt_lso_core);
5084 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
5088 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
5090 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
5095 if (needs_vxlan_tso(m))
5096 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
5098 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
5100 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
5104 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
5108 txpkts0_len16(u_int nsegs)
5114 nsegs--; /* first segment is part of ulptx_sgl */
5115 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
5116 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
5117 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5119 return (howmany(n, 16));
5123 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
5131 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
5133 return (howmany(n, 16));
5137 imm_payload(u_int ndesc)
5141 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
5142 sizeof(struct cpl_tx_pkt_core);
5147 static inline uint64_t
5148 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
5151 int csum_type, l2hlen, l3hlen;
5153 static const int csum_types[3][2] = {
5154 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
5155 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
5161 if (!needs_hwcsum(m))
5162 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
5164 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
5165 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
5167 if (needs_vxlan_csum(m)) {
5168 MPASS(m->m_pkthdr.l4hlen > 0);
5169 MPASS(m->m_pkthdr.l5hlen > 0);
5170 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
5171 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
5173 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
5174 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
5175 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
5176 l3hlen = m->m_pkthdr.inner_l3hlen;
5178 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
5179 l3hlen = m->m_pkthdr.l3hlen;
5183 if (!needs_l3_csum(m))
5184 ctrl |= F_TXPKT_IPCSUM_DIS;
5186 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
5187 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
5189 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
5190 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
5195 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
5196 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
5199 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
5200 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
5204 * needs_hwcsum returned true earlier so there must be some kind of
5205 * checksum to calculate.
5207 csum_type = csum_types[x][y];
5208 MPASS(csum_type != 0);
5209 if (csum_type == TX_CSUM_IP)
5210 ctrl |= F_TXPKT_L4CSUM_DIS;
5211 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
5212 if (chip_id(sc) <= CHELSIO_T5)
5213 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
5215 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
5220 static inline void *
5221 write_lso_cpl(void *cpl, struct mbuf *m0)
5223 struct cpl_tx_pkt_lso_core *lso;
5226 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5227 m0->m_pkthdr.l4hlen > 0,
5228 ("%s: mbuf %p needs TSO but missing header lengths",
5231 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5232 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5233 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5234 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5235 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5236 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5240 lso->lso_ctrl = htobe32(ctrl);
5241 lso->ipid_ofst = htobe16(0);
5242 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5243 lso->seqno_offset = htobe32(0);
5244 lso->len = htobe32(m0->m_pkthdr.len);
5250 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
5252 struct cpl_tx_tnl_lso *tnl_lso = cpl;
5255 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
5256 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
5257 m0->m_pkthdr.inner_l5hlen > 0,
5258 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
5260 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5261 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
5262 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
5265 /* Outer headers. */
5266 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
5267 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
5268 V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
5269 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5270 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
5271 F_CPL_TX_TNL_LSO_IPLENSETOUT;
5272 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5273 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
5275 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
5276 F_CPL_TX_TNL_LSO_IPIDINCOUT;
5278 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
5279 tnl_lso->IpIdOffsetOut = 0;
5280 tnl_lso->UdpLenSetOut_to_TnlHdrLen =
5281 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
5282 F_CPL_TX_TNL_LSO_UDPLENSETOUT |
5283 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
5284 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
5285 m0->m_pkthdr.l5hlen) |
5286 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
5289 /* Inner headers. */
5290 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
5291 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
5292 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
5293 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
5294 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
5295 ctrl |= F_CPL_TX_TNL_LSO_IPV6;
5296 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
5297 tnl_lso->IpIdOffset = 0;
5298 tnl_lso->IpIdSplit_to_Mss =
5299 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
5300 tnl_lso->TCPSeqOffset = 0;
5301 tnl_lso->EthLenOffset_Size =
5302 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
5304 return (tnl_lso + 1);
5307 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */
5310 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
5311 * software descriptor, and advance the pidx. It is guaranteed that enough
5312 * descriptors are available.
5314 * The return value is the # of hardware descriptors used.
5317 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
5320 struct fw_eth_tx_pkt_vm_wr *wr;
5321 struct tx_sdesc *txsd;
5322 struct cpl_tx_pkt_core *cpl;
5323 uint32_t ctrl; /* used in many unrelated places */
5325 int len16, ndesc, pktlen, nsegs;
5328 TXQ_LOCK_ASSERT_OWNED(txq);
5331 len16 = mbuf_len16(m0);
5332 nsegs = mbuf_nsegs(m0);
5333 pktlen = m0->m_pkthdr.len;
5334 ctrl = sizeof(struct cpl_tx_pkt_core);
5336 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5337 ndesc = tx_len16_to_desc(len16);
5339 /* Firmware work request header */
5341 wr = (void *)&eq->desc[eq->pidx];
5342 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5343 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5345 ctrl = V_FW_WR_LEN16(len16);
5346 wr->equiq_to_len16 = htobe32(ctrl);
5351 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5352 * vlantci is ignored unless the ethtype is 0x8100, so it's
5353 * simpler to always copy it rather than making it
5354 * conditional. Also, it seems that we do not have to set
5355 * vlantci or fake the ethtype when doing VLAN tag insertion.
5357 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5359 if (needs_tso(m0)) {
5360 cpl = write_lso_cpl(wr + 1, m0);
5363 cpl = (void *)(wr + 1);
5365 /* Checksum offload */
5366 ctrl1 = csum_to_ctrl(sc, m0);
5367 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5368 txq->txcsum++; /* some hardware assistance provided */
5370 /* VLAN tag insertion */
5371 if (needs_vlan_insertion(m0)) {
5372 ctrl1 |= F_TXPKT_VLAN_VLD |
5373 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5374 txq->vlan_insertion++;
5378 cpl->ctrl0 = txq->cpl_ctrl0;
5380 cpl->len = htobe16(pktlen);
5381 cpl->ctrl1 = htobe64(ctrl1);
5384 dst = (void *)(cpl + 1);
5387 * A packet using TSO will use up an entire descriptor for the
5388 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5389 * If this descriptor is the last descriptor in the ring, wrap
5390 * around to the front of the ring explicitly for the start of
5393 if (dst == (void *)&eq->desc[eq->sidx]) {
5394 dst = (void *)&eq->desc[0];
5395 write_gl_to_txd(txq, m0, &dst, 0);
5397 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5401 txsd = &txq->sdesc[eq->pidx];
5403 txsd->desc_used = ndesc;
5409 * Write a raw WR to the hardware descriptors, update the software
5410 * descriptor, and advance the pidx. It is guaranteed that enough
5411 * descriptors are available.
5413 * The return value is the # of hardware descriptors used.
5416 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5418 struct sge_eq *eq = &txq->eq;
5419 struct tx_sdesc *txsd;
5424 len16 = mbuf_len16(m0);
5425 ndesc = tx_len16_to_desc(len16);
5426 MPASS(ndesc <= available);
5429 for (m = m0; m != NULL; m = m->m_next)
5430 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5434 txsd = &txq->sdesc[eq->pidx];
5436 txsd->desc_used = ndesc;
5442 * Write a txpkt WR for this packet to the hardware descriptors, update the
5443 * software descriptor, and advance the pidx. It is guaranteed that enough
5444 * descriptors are available.
5446 * The return value is the # of hardware descriptors used.
5449 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5453 struct fw_eth_tx_pkt_wr *wr;
5454 struct tx_sdesc *txsd;
5455 struct cpl_tx_pkt_core *cpl;
5456 uint32_t ctrl; /* used in many unrelated places */
5458 int len16, ndesc, pktlen, nsegs;
5461 TXQ_LOCK_ASSERT_OWNED(txq);
5464 len16 = mbuf_len16(m0);
5465 nsegs = mbuf_nsegs(m0);
5466 pktlen = m0->m_pkthdr.len;
5467 ctrl = sizeof(struct cpl_tx_pkt_core);
5468 if (needs_tso(m0)) {
5469 if (needs_vxlan_tso(m0))
5470 ctrl += sizeof(struct cpl_tx_tnl_lso);
5472 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5473 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5475 /* Immediate data. Recalculate len16 and set nsegs to 0. */
5477 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5478 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5481 ndesc = tx_len16_to_desc(len16);
5482 MPASS(ndesc <= available);
5484 /* Firmware work request header */
5486 wr = (void *)&eq->desc[eq->pidx];
5487 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5488 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5490 ctrl = V_FW_WR_LEN16(len16);
5491 wr->equiq_to_len16 = htobe32(ctrl);
5494 if (needs_tso(m0)) {
5495 if (needs_vxlan_tso(m0)) {
5496 cpl = write_tnl_lso_cpl(wr + 1, m0);
5497 txq->vxlan_tso_wrs++;
5499 cpl = write_lso_cpl(wr + 1, m0);
5503 cpl = (void *)(wr + 1);
5505 /* Checksum offload */
5506 ctrl1 = csum_to_ctrl(sc, m0);
5507 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5508 /* some hardware assistance provided */
5509 if (needs_vxlan_csum(m0))
5510 txq->vxlan_txcsum++;
5515 /* VLAN tag insertion */
5516 if (needs_vlan_insertion(m0)) {
5517 ctrl1 |= F_TXPKT_VLAN_VLD |
5518 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5519 txq->vlan_insertion++;
5523 cpl->ctrl0 = txq->cpl_ctrl0;
5525 cpl->len = htobe16(pktlen);
5526 cpl->ctrl1 = htobe64(ctrl1);
5529 dst = (void *)(cpl + 1);
5530 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5531 dst = (caddr_t)&eq->desc[0];
5534 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5539 for (m = m0; m != NULL; m = m->m_next) {
5540 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5546 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5553 txsd = &txq->sdesc[eq->pidx];
5555 txsd->desc_used = ndesc;
5561 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5565 MPASS(txp->npkt > 0);
5566 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5568 if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5569 len = VM_TX_L2HDR_LEN;
5571 len = sizeof(struct ether_header);
5573 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5577 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5579 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5581 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5585 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5586 int avail, bool *send)
5588 struct txpkts *txp = &txq->txp;
5590 /* Cannot have TSO and coalesce at the same time. */
5591 if (cannot_use_txpkts(m)) {
5593 *send = txp->npkt > 0;
5597 /* VF allows coalescing of type 1 (1 GL) only */
5598 if (mbuf_nsegs(m) > 1)
5599 goto cannot_coalesce;
5602 if (txp->npkt > 0) {
5603 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5604 MPASS(txp->npkt < txp->max_npkt);
5605 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5607 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5612 if (m->m_pkthdr.len + txp->plen > 65535)
5613 goto retry_after_send;
5614 if (cmp_l2hdr(txp, m))
5615 goto retry_after_send;
5617 txp->len16 += txpkts1_len16();
5618 txp->plen += m->m_pkthdr.len;
5619 txp->mb[txp->npkt++] = m;
5620 if (txp->npkt == txp->max_npkt)
5623 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5625 if (tx_len16_to_desc(txp->len16) > avail)
5626 goto cannot_coalesce;
5629 txp->plen = m->m_pkthdr.len;
5637 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5638 int avail, bool *send)
5640 struct txpkts *txp = &txq->txp;
5643 MPASS(!(sc->flags & IS_VF));
5645 /* Cannot have TSO and coalesce at the same time. */
5646 if (cannot_use_txpkts(m)) {
5648 *send = txp->npkt > 0;
5653 nsegs = mbuf_nsegs(m);
5654 if (txp->npkt == 0) {
5655 if (m->m_pkthdr.len > 65535)
5656 goto cannot_coalesce;
5660 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5661 txpkts0_len16(nsegs);
5665 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5668 if (tx_len16_to_desc(txp->len16) > avail)
5669 goto cannot_coalesce;
5671 txp->plen = m->m_pkthdr.len;
5674 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5675 MPASS(txp->npkt < txp->max_npkt);
5677 if (m->m_pkthdr.len + txp->plen > 65535) {
5683 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5684 if (txp->wr_type == 0) {
5685 if (tx_len16_to_desc(txp->len16 +
5686 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5687 goto retry_after_send;
5688 txp->len16 += txpkts0_len16(nsegs);
5691 goto retry_after_send;
5692 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5694 goto retry_after_send;
5695 txp->len16 += txpkts1_len16();
5698 txp->plen += m->m_pkthdr.len;
5699 txp->mb[txp->npkt++] = m;
5700 if (txp->npkt == txp->max_npkt)
5707 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5708 * the software descriptor, and advance the pidx. It is guaranteed that enough
5709 * descriptors are available.
5711 * The return value is the # of hardware descriptors used.
5714 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5716 const struct txpkts *txp = &txq->txp;
5717 struct sge_eq *eq = &txq->eq;
5718 struct fw_eth_tx_pkts_wr *wr;
5719 struct tx_sdesc *txsd;
5720 struct cpl_tx_pkt_core *cpl;
5722 int ndesc, i, checkwrap;
5723 struct mbuf *m, *last;
5726 TXQ_LOCK_ASSERT_OWNED(txq);
5727 MPASS(txp->npkt > 0);
5728 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5730 wr = (void *)&eq->desc[eq->pidx];
5731 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5732 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5733 wr->plen = htobe16(txp->plen);
5734 wr->npkt = txp->npkt;
5736 wr->type = txp->wr_type;
5740 * At this point we are 16B into a hardware descriptor. If checkwrap is
5741 * set then we know the WR is going to wrap around somewhere. We'll
5742 * check for that at appropriate points.
5744 ndesc = tx_len16_to_desc(txp->len16);
5746 checkwrap = eq->sidx - ndesc < eq->pidx;
5747 for (i = 0; i < txp->npkt; i++) {
5749 if (txp->wr_type == 0) {
5750 struct ulp_txpkt *ulpmc;
5751 struct ulptx_idata *ulpsc;
5753 /* ULP master command */
5755 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5756 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5757 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5759 /* ULP subcommand */
5760 ulpsc = (void *)(ulpmc + 1);
5761 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5763 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5765 cpl = (void *)(ulpsc + 1);
5767 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5768 cpl = (void *)&eq->desc[0];
5773 /* Checksum offload */
5774 ctrl1 = csum_to_ctrl(sc, m);
5775 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5776 /* some hardware assistance provided */
5777 if (needs_vxlan_csum(m))
5778 txq->vxlan_txcsum++;
5783 /* VLAN tag insertion */
5784 if (needs_vlan_insertion(m)) {
5785 ctrl1 |= F_TXPKT_VLAN_VLD |
5786 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5787 txq->vlan_insertion++;
5791 cpl->ctrl0 = txq->cpl_ctrl0;
5793 cpl->len = htobe16(m->m_pkthdr.len);
5794 cpl->ctrl1 = htobe64(ctrl1);
5798 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5799 flitp = (void *)&eq->desc[0];
5801 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5804 last->m_nextpkt = m;
5809 if (txp->wr_type == 0) {
5810 txq->txpkts0_pkts += txp->npkt;
5813 txq->txpkts1_pkts += txp->npkt;
5817 txsd = &txq->sdesc[eq->pidx];
5818 txsd->m = txp->mb[0];
5819 txsd->desc_used = ndesc;
5825 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5827 const struct txpkts *txp = &txq->txp;
5828 struct sge_eq *eq = &txq->eq;
5829 struct fw_eth_tx_pkts_vm_wr *wr;
5830 struct tx_sdesc *txsd;
5831 struct cpl_tx_pkt_core *cpl;
5834 struct mbuf *m, *last;
5837 TXQ_LOCK_ASSERT_OWNED(txq);
5838 MPASS(txp->npkt > 0);
5839 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5840 MPASS(txp->mb[0] != NULL);
5841 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5843 wr = (void *)&eq->desc[eq->pidx];
5844 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5845 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5847 wr->plen = htobe16(txp->plen);
5848 wr->npkt = txp->npkt;
5850 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5854 * At this point we are 32B into a hardware descriptor. Each mbuf in
5855 * the WR will take 32B so we check for the end of the descriptor ring
5856 * before writing odd mbufs (mb[1], 3, 5, ..)
5858 ndesc = tx_len16_to_desc(txp->len16);
5860 for (i = 0; i < txp->npkt; i++) {
5862 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5863 flitp = &eq->desc[0];
5866 /* Checksum offload */
5867 ctrl1 = csum_to_ctrl(sc, m);
5868 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5869 txq->txcsum++; /* some hardware assistance provided */
5871 /* VLAN tag insertion */
5872 if (needs_vlan_insertion(m)) {
5873 ctrl1 |= F_TXPKT_VLAN_VLD |
5874 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5875 txq->vlan_insertion++;
5879 cpl->ctrl0 = txq->cpl_ctrl0;
5881 cpl->len = htobe16(m->m_pkthdr.len);
5882 cpl->ctrl1 = htobe64(ctrl1);
5885 MPASS(mbuf_nsegs(m) == 1);
5886 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
5889 last->m_nextpkt = m;
5894 txq->txpkts1_pkts += txp->npkt;
5897 txsd = &txq->sdesc[eq->pidx];
5898 txsd->m = txp->mb[0];
5899 txsd->desc_used = ndesc;
5905 * If the SGL ends on an address that is not 16 byte aligned, this function will
5906 * add a 0 filled flit at the end.
5909 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5911 struct sge_eq *eq = &txq->eq;
5912 struct sglist *gl = txq->gl;
5913 struct sglist_seg *seg;
5914 __be64 *flitp, *wrap;
5915 struct ulptx_sgl *usgl;
5916 int i, nflits, nsegs;
5918 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5919 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5920 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5921 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5924 nsegs = gl->sg_nseg;
5927 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5928 flitp = (__be64 *)(*to);
5929 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5930 seg = &gl->sg_segs[0];
5931 usgl = (void *)flitp;
5934 * We start at a 16 byte boundary somewhere inside the tx descriptor
5935 * ring, so we're at least 16 bytes away from the status page. There is
5936 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5939 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5940 V_ULPTX_NSGE(nsegs));
5941 usgl->len0 = htobe32(seg->ss_len);
5942 usgl->addr0 = htobe64(seg->ss_paddr);
5945 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5947 /* Won't wrap around at all */
5949 for (i = 0; i < nsegs - 1; i++, seg++) {
5950 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5951 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5954 usgl->sge[i / 2].len[1] = htobe32(0);
5958 /* Will wrap somewhere in the rest of the SGL */
5960 /* 2 flits already written, write the rest flit by flit */
5961 flitp = (void *)(usgl + 1);
5962 for (i = 0; i < nflits - 2; i++) {
5964 flitp = (void *)eq->desc;
5965 *flitp++ = get_flit(seg, nsegs - 1, i);
5970 MPASS(((uintptr_t)flitp) & 0xf);
5974 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5975 if (__predict_false(flitp == wrap))
5976 *to = (void *)eq->desc;
5978 *to = (void *)flitp;
5982 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5985 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5986 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5988 if (__predict_true((uintptr_t)(*to) + len <=
5989 (uintptr_t)&eq->desc[eq->sidx])) {
5990 bcopy(from, *to, len);
5993 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5995 bcopy(from, *to, portion);
5997 portion = len - portion; /* remaining */
5998 bcopy(from, (void *)eq->desc, portion);
5999 (*to) = (caddr_t)eq->desc + portion;
6004 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
6012 clrbit(&db, DOORBELL_WCWR);
6015 switch (ffs(db) - 1) {
6017 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6020 case DOORBELL_WCWR: {
6021 volatile uint64_t *dst, *src;
6025 * Queues whose 128B doorbell segment fits in the page do not
6026 * use relative qid (udb_qid is always 0). Only queues with
6027 * doorbell segments can do WCWR.
6029 KASSERT(eq->udb_qid == 0 && n == 1,
6030 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
6031 __func__, eq->doorbells, n, eq->dbidx, eq));
6033 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
6036 src = (void *)&eq->desc[i];
6037 while (src != (void *)&eq->desc[i + 1])
6043 case DOORBELL_UDBWC:
6044 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6049 t4_write_reg(sc, sc->sge_kdoorbell_reg,
6050 V_QID(eq->cntxt_id) | V_PIDX(n));
6054 IDXINCR(eq->dbidx, n, eq->sidx);
6058 reclaimable_tx_desc(struct sge_eq *eq)
6062 hw_cidx = read_hw_cidx(eq);
6063 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
6067 total_available_tx_desc(struct sge_eq *eq)
6069 uint16_t hw_cidx, pidx;
6071 hw_cidx = read_hw_cidx(eq);
6074 if (pidx == hw_cidx)
6075 return (eq->sidx - 1);
6077 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
6080 static inline uint16_t
6081 read_hw_cidx(struct sge_eq *eq)
6083 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6084 uint16_t cidx = spg->cidx; /* stable snapshot */
6086 return (be16toh(cidx));
6090 * Reclaim 'n' descriptors approximately.
6093 reclaim_tx_descs(struct sge_txq *txq, u_int n)
6095 struct tx_sdesc *txsd;
6096 struct sge_eq *eq = &txq->eq;
6097 u_int can_reclaim, reclaimed;
6099 TXQ_LOCK_ASSERT_OWNED(txq);
6103 can_reclaim = reclaimable_tx_desc(eq);
6104 while (can_reclaim && reclaimed < n) {
6106 struct mbuf *m, *nextpkt;
6108 txsd = &txq->sdesc[eq->cidx];
6109 ndesc = txsd->desc_used;
6111 /* Firmware doesn't return "partial" credits. */
6112 KASSERT(can_reclaim >= ndesc,
6113 ("%s: unexpected number of credits: %d, %d",
6114 __func__, can_reclaim, ndesc));
6116 ("%s: descriptor with no credits: cidx %d",
6117 __func__, eq->cidx));
6119 for (m = txsd->m; m != NULL; m = nextpkt) {
6120 nextpkt = m->m_nextpkt;
6121 m->m_nextpkt = NULL;
6125 can_reclaim -= ndesc;
6126 IDXINCR(eq->cidx, ndesc, eq->sidx);
6133 tx_reclaim(void *arg, int n)
6135 struct sge_txq *txq = arg;
6136 struct sge_eq *eq = &txq->eq;
6139 if (TXQ_TRYLOCK(txq) == 0)
6141 n = reclaim_tx_descs(txq, 32);
6142 if (eq->cidx == eq->pidx)
6143 eq->equeqidx = eq->pidx;
6149 get_flit(struct sglist_seg *segs, int nsegs, int idx)
6151 int i = (idx / 3) * 2;
6157 rc = (uint64_t)segs[i].ss_len << 32;
6159 rc |= (uint64_t)(segs[i + 1].ss_len);
6161 return (htobe64(rc));
6164 return (htobe64(segs[i].ss_paddr));
6166 return (htobe64(segs[i + 1].ss_paddr));
6173 find_refill_source(struct adapter *sc, int maxp, bool packing)
6176 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6179 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6180 if (rxb->hwidx2 == -1)
6182 if (rxb->size1 < PAGE_SIZE &&
6183 rxb->size1 < largest_rx_cluster)
6185 if (rxb->size1 > largest_rx_cluster)
6187 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
6188 if (rxb->size2 >= maxp)
6193 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6194 if (rxb->hwidx1 == -1)
6196 if (rxb->size1 > largest_rx_cluster)
6198 if (rxb->size1 >= maxp)
6208 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
6210 mtx_lock(&sc->sfl_lock);
6212 if ((fl->flags & FL_DOOMED) == 0) {
6213 fl->flags |= FL_STARVING;
6214 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
6215 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
6218 mtx_unlock(&sc->sfl_lock);
6222 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
6224 struct sge_wrq *wrq = (void *)eq;
6226 atomic_readandclear_int(&eq->equiq);
6227 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
6231 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
6233 struct sge_txq *txq = (void *)eq;
6235 MPASS(eq->type == EQ_ETH);
6237 atomic_readandclear_int(&eq->equiq);
6238 if (mp_ring_is_idle(txq->r))
6239 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
6241 mp_ring_check_drainage(txq->r, 64);
6245 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
6248 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
6249 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
6250 struct adapter *sc = iq->adapter;
6251 struct sge *s = &sc->sge;
6253 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
6254 &handle_wrq_egr_update, &handle_eth_egr_update,
6255 &handle_wrq_egr_update};
6257 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6260 eq = s->eqmap[qid - s->eq_start - s->eq_base];
6261 (*h[eq->type])(sc, eq);
6266 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
6267 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
6268 offsetof(struct cpl_fw6_msg, data));
6271 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
6273 struct adapter *sc = iq->adapter;
6274 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
6276 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6279 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
6280 const struct rss_header *rss2;
6282 rss2 = (const struct rss_header *)&cpl->data[0];
6283 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
6286 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
6290 * t4_handle_wrerr_rpl - process a FW work request error message
6291 * @adap: the adapter
6292 * @rpl: start of the FW message
6295 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
6297 u8 opcode = *(const u8 *)rpl;
6298 const struct fw_error_cmd *e = (const void *)rpl;
6301 if (opcode != FW_ERROR_CMD) {
6303 "%s: Received WRERR_RPL message with opcode %#x\n",
6304 device_get_nameunit(adap->dev), opcode);
6307 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
6308 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
6310 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
6311 case FW_ERROR_TYPE_EXCEPTION:
6312 log(LOG_ERR, "exception info:\n");
6313 for (i = 0; i < nitems(e->u.exception.info); i++)
6314 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
6315 be32toh(e->u.exception.info[i]));
6318 case FW_ERROR_TYPE_HWMODULE:
6319 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
6320 be32toh(e->u.hwmodule.regaddr),
6321 be32toh(e->u.hwmodule.regval));
6323 case FW_ERROR_TYPE_WR:
6324 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
6325 be16toh(e->u.wr.cidx),
6326 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6327 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6328 be32toh(e->u.wr.eqid));
6329 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6330 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6334 case FW_ERROR_TYPE_ACL:
6335 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6336 be16toh(e->u.acl.cidx),
6337 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6338 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6339 be32toh(e->u.acl.eqid),
6340 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6342 for (i = 0; i < nitems(e->u.acl.val); i++)
6343 log(LOG_ERR, " %02x", e->u.acl.val[i]);
6347 log(LOG_ERR, "type %#x\n",
6348 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6355 bufidx_used(struct adapter *sc, int idx)
6357 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6360 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6361 if (rxb->size1 > largest_rx_cluster)
6363 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6371 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6373 struct adapter *sc = arg1;
6374 struct sge_params *sp = &sc->params.sge;
6379 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6380 for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6381 if (bufidx_used(sc, i))
6386 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6390 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6397 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
6400 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6406 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6407 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6408 if (__predict_false(nsegs == 0))
6411 nsegs--; /* first segment is part of ulptx_sgl */
6412 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6414 n += sizeof(struct cpl_tx_pkt_lso_core);
6417 return (howmany(n, 16));
6420 #define ETID_FLOWC_NPARAMS 6
6421 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6422 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6423 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6426 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6429 struct wrq_cookie cookie;
6430 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6431 struct fw_flowc_wr *flowc;
6433 mtx_assert(&cst->lock, MA_OWNED);
6434 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6437 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie);
6438 if (__predict_false(flowc == NULL))
6441 bzero(flowc, ETID_FLOWC_LEN);
6442 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6443 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6444 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6445 V_FW_WR_FLOWID(cst->etid));
6446 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6447 flowc->mnemval[0].val = htobe32(pfvf);
6448 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6449 flowc->mnemval[1].val = htobe32(pi->tx_chan);
6450 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6451 flowc->mnemval[2].val = htobe32(pi->tx_chan);
6452 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6453 flowc->mnemval[3].val = htobe32(cst->iqid);
6454 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6455 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6456 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6457 flowc->mnemval[5].val = htobe32(cst->schedcl);
6459 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6461 cst->flags &= ~EO_FLOWC_PENDING;
6462 cst->flags |= EO_FLOWC_RPL_PENDING;
6463 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
6464 cst->tx_credits -= ETID_FLOWC_LEN16;
6469 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6472 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6474 struct fw_flowc_wr *flowc;
6475 struct wrq_cookie cookie;
6477 mtx_assert(&cst->lock, MA_OWNED);
6479 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie);
6480 if (__predict_false(flowc == NULL))
6481 CXGBE_UNIMPLEMENTED(__func__);
6483 bzero(flowc, ETID_FLUSH_LEN16 * 16);
6484 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6485 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6486 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6487 V_FW_WR_FLOWID(cst->etid));
6489 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6491 cst->flags |= EO_FLUSH_RPL_PENDING;
6492 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6493 cst->tx_credits -= ETID_FLUSH_LEN16;
6498 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6499 struct mbuf *m0, int compl)
6501 struct cpl_tx_pkt_core *cpl;
6503 uint32_t ctrl; /* used in many unrelated places */
6504 int len16, pktlen, nsegs, immhdrs;
6507 struct ulptx_sgl *usgl;
6509 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
6511 mtx_assert(&cst->lock, MA_OWNED);
6513 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6514 m0->m_pkthdr.l4hlen > 0,
6515 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6517 len16 = mbuf_eo_len16(m0);
6518 nsegs = mbuf_eo_nsegs(m0);
6519 pktlen = m0->m_pkthdr.len;
6520 ctrl = sizeof(struct cpl_tx_pkt_core);
6522 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6523 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6526 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6527 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6528 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6529 V_FW_WR_FLOWID(cst->etid));
6531 if (needs_outer_udp_csum(m0)) {
6532 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6533 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6534 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6535 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6536 wr->u.udpseg.rtplen = 0;
6537 wr->u.udpseg.r4 = 0;
6538 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6539 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6540 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6541 cpl = (void *)(wr + 1);
6543 MPASS(needs_outer_tcp_csum(m0));
6544 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6545 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6546 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6547 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6548 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6549 wr->u.tcpseg.r4 = 0;
6550 wr->u.tcpseg.r5 = 0;
6551 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6553 if (needs_tso(m0)) {
6554 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6556 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6558 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6559 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6560 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6561 ETHER_HDR_LEN) >> 2) |
6562 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6563 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6564 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6566 lso->lso_ctrl = htobe32(ctrl);
6567 lso->ipid_ofst = htobe16(0);
6568 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6569 lso->seqno_offset = htobe32(0);
6570 lso->len = htobe32(pktlen);
6572 cpl = (void *)(lso + 1);
6574 wr->u.tcpseg.mss = htobe16(0xffff);
6575 cpl = (void *)(wr + 1);
6579 /* Checksum offload must be requested for ethofld. */
6580 MPASS(needs_outer_l4_csum(m0));
6581 ctrl1 = csum_to_ctrl(cst->adapter, m0);
6583 /* VLAN tag insertion */
6584 if (needs_vlan_insertion(m0)) {
6585 ctrl1 |= F_TXPKT_VLAN_VLD |
6586 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6590 cpl->ctrl0 = cst->ctrl0;
6592 cpl->len = htobe16(pktlen);
6593 cpl->ctrl1 = htobe64(ctrl1);
6595 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6596 p = (uintptr_t)(cpl + 1);
6597 m_copydata(m0, 0, immhdrs, (void *)p);
6600 dst = (void *)(cpl + 1);
6604 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6606 pad = 16 - (immhdrs & 0xf);
6607 bzero((void *)p, pad);
6609 usgl = (void *)(p + pad);
6610 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6611 V_ULPTX_NSGE(nsegs));
6613 sglist_init(&sg, nitems(segs), segs);
6614 for (; m0 != NULL; m0 = m0->m_next) {
6615 if (__predict_false(m0->m_len == 0))
6617 if (immhdrs >= m0->m_len) {
6618 immhdrs -= m0->m_len;
6621 if (m0->m_flags & M_EXTPG)
6622 sglist_append_mbuf_epg(&sg, m0,
6623 mtod(m0, vm_offset_t), m0->m_len);
6625 sglist_append(&sg, mtod(m0, char *) + immhdrs,
6626 m0->m_len - immhdrs);
6629 MPASS(sg.sg_nseg == nsegs);
6632 * Zero pad last 8B in case the WR doesn't end on a 16B
6635 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6637 usgl->len0 = htobe32(segs[0].ss_len);
6638 usgl->addr0 = htobe64(segs[0].ss_paddr);
6639 for (i = 0; i < nsegs - 1; i++) {
6640 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6641 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6644 usgl->sge[i / 2].len[1] = htobe32(0);
6650 ethofld_tx(struct cxgbe_rate_tag *cst)
6653 struct wrq_cookie cookie;
6654 int next_credits, compl;
6655 struct fw_eth_tx_eo_wr *wr;
6657 mtx_assert(&cst->lock, MA_OWNED);
6659 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6662 /* How many len16 credits do we need to send this mbuf. */
6663 next_credits = mbuf_eo_len16(m);
6664 MPASS(next_credits > 0);
6665 if (next_credits > cst->tx_credits) {
6667 * Tx will make progress eventually because there is at
6668 * least one outstanding fw4_ack that will return
6669 * credits and kick the tx.
6671 MPASS(cst->ncompl > 0);
6674 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie);
6675 if (__predict_false(wr == NULL)) {
6676 /* XXX: wishful thinking, not a real assertion. */
6677 MPASS(cst->ncompl > 0);
6680 cst->tx_credits -= next_credits;
6681 cst->tx_nocompl += next_credits;
6682 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6683 ETHER_BPF_MTAP(cst->com.ifp, m);
6684 write_ethofld_wr(cst, wr, m, compl);
6685 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie);
6688 cst->tx_nocompl = 0;
6690 (void) mbufq_dequeue(&cst->pending_tx);
6693 * Drop the mbuf's reference on the tag now rather
6694 * than waiting until m_freem(). This ensures that
6695 * cxgbe_rate_tag_free gets called when the inp drops
6696 * its reference on the tag and there are no more
6697 * mbufs in the pending_tx queue and can flush any
6698 * pending requests. Otherwise if the last mbuf
6699 * doesn't request a completion the etid will never be
6702 m->m_pkthdr.snd_tag = NULL;
6703 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6704 m_snd_tag_rele(&cst->com);
6706 mbufq_enqueue(&cst->pending_fwack, m);
6711 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6713 struct cxgbe_rate_tag *cst;
6716 MPASS(m0->m_nextpkt == NULL);
6717 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6718 MPASS(m0->m_pkthdr.snd_tag != NULL);
6719 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6721 mtx_lock(&cst->lock);
6722 MPASS(cst->flags & EO_SND_TAG_REF);
6724 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6725 struct vi_info *vi = ifp->if_softc;
6726 struct port_info *pi = vi->pi;
6727 struct adapter *sc = pi->adapter;
6728 const uint32_t rss_mask = vi->rss_size - 1;
6731 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6732 if (M_HASHTYPE_ISHASH(m0))
6733 rss_hash = m0->m_pkthdr.flowid;
6735 rss_hash = arc4random();
6736 /* We assume RSS hashing */
6737 cst->iqid = vi->rss[rss_hash & rss_mask];
6738 cst->eo_txq += rss_hash % vi->nofldtxq;
6739 rc = send_etid_flowc_wr(cst, pi, vi);
6744 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6749 mbufq_enqueue(&cst->pending_tx, m0);
6750 cst->plen += m0->m_pkthdr.len;
6753 * Hold an extra reference on the tag while generating work
6754 * requests to ensure that we don't try to free the tag during
6755 * ethofld_tx() in case we are sending the final mbuf after
6756 * the inp was freed.
6758 m_snd_tag_ref(&cst->com);
6760 mtx_unlock(&cst->lock);
6761 m_snd_tag_rele(&cst->com);
6765 mtx_unlock(&cst->lock);
6766 if (__predict_false(rc != 0))
6772 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6774 struct adapter *sc = iq->adapter;
6775 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6777 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6778 struct cxgbe_rate_tag *cst;
6779 uint8_t credits = cpl->credits;
6781 cst = lookup_etid(sc, etid);
6782 mtx_lock(&cst->lock);
6783 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6784 MPASS(credits >= ETID_FLOWC_LEN16);
6785 credits -= ETID_FLOWC_LEN16;
6786 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6789 KASSERT(cst->ncompl > 0,
6790 ("%s: etid %u (%p) wasn't expecting completion.",
6791 __func__, etid, cst));
6794 while (credits > 0) {
6795 m = mbufq_dequeue(&cst->pending_fwack);
6796 if (__predict_false(m == NULL)) {
6798 * The remaining credits are for the final flush that
6799 * was issued when the tag was freed by the kernel.
6802 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6803 EO_FLUSH_RPL_PENDING);
6804 MPASS(credits == ETID_FLUSH_LEN16);
6805 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6806 MPASS(cst->ncompl == 0);
6808 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6809 cst->tx_credits += cpl->credits;
6810 cxgbe_rate_tag_free_locked(cst);
6811 return (0); /* cst is gone. */
6814 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6816 KASSERT(credits >= mbuf_eo_len16(m),
6817 ("%s: too few credits (%u, %u, %u)", __func__,
6818 cpl->credits, credits, mbuf_eo_len16(m)));
6819 credits -= mbuf_eo_len16(m);
6820 cst->plen -= m->m_pkthdr.len;
6824 cst->tx_credits += cpl->credits;
6825 MPASS(cst->tx_credits <= cst->tx_total);
6827 if (cst->flags & EO_SND_TAG_REF) {
6829 * As with ethofld_transmit(), hold an extra reference
6830 * so that the tag is stable across ethold_tx().
6832 m_snd_tag_ref(&cst->com);
6833 m = mbufq_first(&cst->pending_tx);
6834 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6836 mtx_unlock(&cst->lock);
6837 m_snd_tag_rele(&cst->com);
6840 * There shouldn't be any pending packets if the tag
6841 * was freed by the kernel since any pending packet
6842 * should hold a reference to the tag.
6844 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6845 mtx_unlock(&cst->lock);