2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
41 #include <sys/taskqueue.h>
43 #include <sys/sysctl.h>
46 #include <net/ethernet.h>
48 #include <net/if_vlan_var.h>
49 #include <netinet/in.h>
50 #include <netinet/ip.h>
51 #include <netinet/ip6.h>
52 #include <netinet/tcp.h>
53 #include <machine/md_var.h>
55 #include "common/common.h"
56 #include "common/t4_regs.h"
57 #include "common/t4_regs_values.h"
58 #include "common/t4_msg.h"
60 #ifdef T4_PKT_TIMESTAMP
61 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
63 #define RX_COPY_THRESHOLD MINCLSIZE
67 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
68 * 0-7 are valid values.
70 static int fl_pktshift = 2;
71 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
74 * Pad ethernet payload up to this boundary.
75 * -1: driver should figure out a good value.
77 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
79 static int fl_pad = -1;
80 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
84 * -1: driver should figure out a good value.
85 * 64 or 128 are the only other valid values.
87 static int spg_len = -1;
88 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
92 * -1: no congestion feedback (not recommended).
93 * 0: backpressure the channel instead of dropping packets right away.
94 * 1: no backpressure, drop packets for the congested queue immediately.
96 static int cong_drop = 0;
97 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
100 * Deliver multiple frames in the same free list buffer if they fit.
101 * -1: let the driver decide whether to enable buffer packing or not.
102 * 0: disable buffer packing.
103 * 1: enable buffer packing.
105 static int buffer_packing = -1;
106 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
109 * Start next frame in a packed buffer at this boundary.
110 * -1: driver should figure out a good value.
114 * value specified here will be overridden by fl_pad.
116 * power of 2 from 32 to 4096 (both inclusive) is a valid value here.
119 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
121 static int fl_pack = -1;
122 static int t4_fl_pack;
123 static int t5_fl_pack;
124 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
126 /* Used to track coalesced tx work request */
128 uint64_t *flitp; /* ptr to flit where next pkt should start */
129 uint8_t npkt; /* # of packets in this work request */
130 uint8_t nflits; /* # of flits used by this work request */
131 uint16_t plen; /* total payload (sum of all packets) */
134 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
136 int nsegs; /* # of segments in the SGL, 0 means imm. tx */
137 int nflits; /* # of flits needed for the SGL */
138 bus_dma_segment_t seg[TX_SGL_SEGS];
141 static int service_iq(struct sge_iq *, int);
142 static struct mbuf *get_fl_payload1(struct adapter *, struct sge_fl *, uint32_t,
144 static struct mbuf *get_fl_payload2(struct adapter *, struct sge_fl *, uint32_t,
146 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
147 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
149 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int,
151 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
153 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
154 bus_addr_t *, void **);
155 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
157 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
159 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
160 static int alloc_fwq(struct adapter *);
161 static int free_fwq(struct adapter *);
162 static int alloc_mgmtq(struct adapter *);
163 static int free_mgmtq(struct adapter *);
164 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
165 struct sysctl_oid *);
166 static int free_rxq(struct port_info *, struct sge_rxq *);
168 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
169 struct sysctl_oid *);
170 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
172 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
173 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
175 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
177 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
178 static int free_eq(struct adapter *, struct sge_eq *);
179 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
180 struct sysctl_oid *);
181 static int free_wrq(struct adapter *, struct sge_wrq *);
182 static int alloc_txq(struct port_info *, struct sge_txq *, int,
183 struct sysctl_oid *);
184 static int free_txq(struct port_info *, struct sge_txq *);
185 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
186 static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **);
187 static inline void iq_next(struct sge_iq *);
188 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
189 static int refill_fl(struct adapter *, struct sge_fl *, int);
190 static void refill_sfl(void *);
191 static int alloc_fl_sdesc(struct sge_fl *);
192 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
193 static void set_fl_tag_idx(struct adapter *, struct sge_fl *, int);
194 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
196 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int);
197 static int free_pkt_sgl(struct sge_txq *, struct sgl *);
198 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *,
200 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *,
201 struct mbuf *, struct sgl *);
202 static void write_txpkts_wr(struct sge_txq *, struct txpkts *);
203 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *,
204 struct txpkts *, struct mbuf *, struct sgl *);
205 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *);
206 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
207 static inline void ring_eq_db(struct adapter *, struct sge_eq *);
208 static inline int reclaimable(struct sge_eq *);
209 static int reclaim_tx_descs(struct sge_txq *, int, int);
210 static void write_eqflush_wr(struct sge_eq *);
211 static __be64 get_flit(bus_dma_segment_t *, int, int);
212 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
214 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
217 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
220 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
227 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */
228 #if defined(__i386__) || defined(__amd64__)
229 pad = max(cpu_clflush_line_size, 16);
231 pad = max(CACHE_LINE_SIZE, 16);
233 pad = min(pad, 4096);
235 if (fl_pktshift < 0 || fl_pktshift > 7) {
236 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
237 " using 2 instead.\n", fl_pktshift);
242 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) {
245 printf("Invalid hw.cxgbe.fl_pad value (%d),"
246 " using %d instead.\n", fl_pad, max(pad, 32));
248 fl_pad = max(pad, 32);
252 * T4 has the same pad and pack boundary. If a pad boundary is set,
253 * pack boundary must be set to the same value. Otherwise take the
254 * specified value or auto-calculate something reasonable.
258 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack))
259 t4_fl_pack = max(pad, 32);
261 t4_fl_pack = fl_pack;
263 /* T5's pack boundary is independent of the pad boundary. */
264 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
266 t5_fl_pack = max(pad, 64);
268 t5_fl_pack = fl_pack;
270 if (spg_len != 64 && spg_len != 128) {
273 #if defined(__i386__) || defined(__amd64__)
274 len = cpu_clflush_line_size > 64 ? 128 : 64;
279 printf("Invalid hw.cxgbe.spg_len value (%d),"
280 " using %d instead.\n", spg_len, len);
285 if (cong_drop < -1 || cong_drop > 1) {
286 printf("Invalid hw.cxgbe.cong_drop value (%d),"
287 " using 0 instead.\n", cong_drop);
293 t4_init_sge_cpl_handlers(struct adapter *sc)
296 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
297 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
298 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
299 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
300 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
304 * adap->params.vpd.cclk must be set up before this is called.
307 t4_tweak_chip_settings(struct adapter *sc)
311 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
312 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
313 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
314 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
315 int sw_flbuf_sizes[] = {
317 #if MJUMPAGESIZE != MCLBYTES
325 KASSERT(sc->flags & MASTER_PF,
326 ("%s: trying to change chip settings when not master.", __func__));
328 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
329 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
330 V_EGRSTATUSPAGESIZE(spg_len == 128);
331 if (is_t4(sc) && (fl_pad || buffer_packing)) {
332 /* t4_fl_pack has the correct value even when fl_pad = 0 */
333 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
334 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
335 } else if (is_t5(sc) && fl_pad) {
336 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
337 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
339 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
341 if (is_t5(sc) && buffer_packing) {
342 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
343 if (t5_fl_pack == 16)
344 v = V_INGPACKBOUNDARY(0);
346 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
347 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
350 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
351 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
352 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
353 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
354 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
355 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
356 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
357 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
358 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
360 for (i = 0; i < min(nitems(sw_flbuf_sizes), 16); i++) {
361 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
365 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
366 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
367 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
369 KASSERT(intr_timer[0] <= timer_max,
370 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
372 for (i = 1; i < nitems(intr_timer); i++) {
373 KASSERT(intr_timer[i] >= intr_timer[i - 1],
374 ("%s: timers not listed in increasing order (%d)",
377 while (intr_timer[i] > timer_max) {
378 if (i == nitems(intr_timer) - 1) {
379 intr_timer[i] = timer_max;
382 intr_timer[i] += intr_timer[i - 1];
387 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
388 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
389 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
390 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
391 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
392 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
393 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
394 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
395 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
397 if (cong_drop == 0) {
398 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
400 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0);
403 /* 4K, 16K, 64K, 256K DDP "page sizes" */
404 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
405 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
407 m = v = F_TDDPTAGTCB;
408 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
410 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
412 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
413 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
417 * XXX: driver really should be able to deal with unexpected settings.
420 t4_read_chip_settings(struct adapter *sc)
422 struct sge *s = &sc->sge;
425 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
426 uint32_t sge_flbuf_sizes[16], sw_flbuf_sizes[] = {
428 #if MJUMPAGESIZE != MCLBYTES
435 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
436 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
437 V_EGRSTATUSPAGESIZE(spg_len == 128);
438 if (is_t4(sc) && (fl_pad || buffer_packing)) {
439 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
440 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
441 } else if (is_t5(sc) && fl_pad) {
442 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
443 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
445 r = t4_read_reg(sc, A_SGE_CONTROL);
447 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
451 if (is_t5(sc) && buffer_packing) {
452 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
453 if (t5_fl_pack == 16)
454 v = V_INGPACKBOUNDARY(0);
456 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
457 r = t4_read_reg(sc, A_SGE_CONTROL2);
459 device_printf(sc->dev,
460 "invalid SGE_CONTROL2(0x%x)\n", r);
465 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
466 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
467 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
468 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
469 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
470 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
471 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
472 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
473 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
475 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
480 * Make a list of SGE FL buffer sizes programmed in the chip and tally
481 * it with the FL buffer sizes that we'd like to use.
484 for (i = 0; i < nitems(sge_flbuf_sizes); i++) {
485 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
486 sge_flbuf_sizes[i] = r;
487 if (r == MJUMPAGESIZE - MSIZE &&
488 (sc->flags & BUF_PACKING_OK) == 0) {
489 sc->flags |= BUF_PACKING_OK;
490 FL_BUF_HWTAG(sc, n) = i;
491 FL_BUF_SIZE(sc, n) = MJUMPAGESIZE - MSIZE;
492 FL_BUF_TYPE(sc, n) = m_gettype(MJUMPAGESIZE);
493 FL_BUF_ZONE(sc, n) = m_getzone(MJUMPAGESIZE);
497 for (i = 0; i < nitems(sw_flbuf_sizes); i++) {
498 for (j = 0; j < nitems(sge_flbuf_sizes); j++) {
499 if (sw_flbuf_sizes[i] != sge_flbuf_sizes[j])
501 FL_BUF_HWTAG(sc, n) = j;
502 FL_BUF_SIZE(sc, n) = sw_flbuf_sizes[i];
503 FL_BUF_TYPE(sc, n) = m_gettype(sw_flbuf_sizes[i]);
504 FL_BUF_ZONE(sc, n) = m_getzone(sw_flbuf_sizes[i]);
510 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
512 } else if (n == 1 && (sc->flags & BUF_PACKING_OK)) {
513 device_printf(sc->dev,
514 "no usable SGE FL buffer size when not packing buffers.\n");
517 FL_BUF_SIZES(sc) = n;
519 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
520 s->counter_val[0] = G_THRESHOLD_0(r);
521 s->counter_val[1] = G_THRESHOLD_1(r);
522 s->counter_val[2] = G_THRESHOLD_2(r);
523 s->counter_val[3] = G_THRESHOLD_3(r);
525 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
526 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc);
527 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc);
528 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
529 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc);
530 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc);
531 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
532 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc);
533 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc);
535 if (cong_drop == 0) {
536 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
538 r = t4_read_reg(sc, A_TP_PARA_REG3);
540 device_printf(sc->dev,
541 "invalid TP_PARA_REG3(0x%x)\n", r);
546 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
547 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
549 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
553 m = v = F_TDDPTAGTCB;
554 r = t4_read_reg(sc, A_ULP_RX_CTL);
556 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
560 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
562 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
563 r = t4_read_reg(sc, A_TP_PARA_REG5);
565 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
569 r = t4_read_reg(sc, A_SGE_CONM_CTRL);
570 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
572 /* egress queues: log2 of # of doorbells per BAR2 page */
573 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
574 r >>= S_QUEUESPERPAGEPF0 +
575 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
576 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
578 /* ingress queues: log2 of # of doorbells per BAR2 page */
579 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
580 r >>= S_QUEUESPERPAGEPF0 +
581 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
582 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
584 t4_init_tp_params(sc);
586 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
587 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
593 t4_create_dma_tag(struct adapter *sc)
597 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
598 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
599 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
602 device_printf(sc->dev,
603 "failed to create main DMA tag: %d\n", rc);
610 enable_buffer_packing(struct adapter *sc)
613 if (sc->flags & BUF_PACKING_OK &&
614 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */
615 (is_t4(sc) && buffer_packing == 1)))
621 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
622 struct sysctl_oid_list *children)
625 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
626 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
628 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
629 NULL, fl_pad, "payload pad boundary (bytes)");
631 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
632 NULL, spg_len, "status page size (bytes)");
634 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
635 NULL, cong_drop, "congestion drop setting");
637 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD,
638 NULL, enable_buffer_packing(sc),
639 "pack multiple frames in one fl buffer");
641 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
642 NULL, is_t5(sc) ? t5_fl_pack : t4_fl_pack,
643 "payload pack boundary (bytes)");
647 t4_destroy_dma_tag(struct adapter *sc)
650 bus_dma_tag_destroy(sc->dmat);
656 * Allocate and initialize the firmware event queue and the management queue.
658 * Returns errno on failure. Resources allocated up to that point may still be
659 * allocated. Caller is responsible for cleanup in case this function fails.
662 t4_setup_adapter_queues(struct adapter *sc)
666 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
668 sysctl_ctx_init(&sc->ctx);
669 sc->flags |= ADAP_SYSCTL_CTX;
672 * Firmware event queue
679 * Management queue. This is just a control queue that uses the fwq as
682 rc = alloc_mgmtq(sc);
691 t4_teardown_adapter_queues(struct adapter *sc)
694 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
696 /* Do this before freeing the queue */
697 if (sc->flags & ADAP_SYSCTL_CTX) {
698 sysctl_ctx_free(&sc->ctx);
699 sc->flags &= ~ADAP_SYSCTL_CTX;
709 first_vector(struct port_info *pi)
711 struct adapter *sc = pi->adapter;
712 int rc = T4_EXTRA_INTR, i;
714 if (sc->intr_count == 1)
717 for_each_port(sc, i) {
718 struct port_info *p = sc->port[i];
720 if (i == pi->port_id)
724 if (sc->flags & INTR_DIRECT)
725 rc += p->nrxq + p->nofldrxq;
727 rc += max(p->nrxq, p->nofldrxq);
730 * Not compiled with offload support and intr_count > 1. Only
731 * NIC queues exist and they'd better be taking direct
734 KASSERT(sc->flags & INTR_DIRECT,
735 ("%s: intr_count %d, !INTR_DIRECT", __func__,
746 * Given an arbitrary "index," come up with an iq that can be used by other
747 * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
748 * The iq returned is guaranteed to be something that takes direct interrupts.
750 static struct sge_iq *
751 port_intr_iq(struct port_info *pi, int idx)
753 struct adapter *sc = pi->adapter;
754 struct sge *s = &sc->sge;
755 struct sge_iq *iq = NULL;
757 if (sc->intr_count == 1)
758 return (&sc->sge.fwq);
761 if (sc->flags & INTR_DIRECT) {
762 idx %= pi->nrxq + pi->nofldrxq;
764 if (idx >= pi->nrxq) {
766 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
768 iq = &s->rxq[pi->first_rxq + idx].iq;
771 idx %= max(pi->nrxq, pi->nofldrxq);
773 if (pi->nrxq >= pi->nofldrxq)
774 iq = &s->rxq[pi->first_rxq + idx].iq;
776 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
780 * Not compiled with offload support and intr_count > 1. Only NIC
781 * queues exist and they'd better be taking direct interrupts.
783 KASSERT(sc->flags & INTR_DIRECT,
784 ("%s: intr_count %d, !INTR_DIRECT", __func__, sc->intr_count));
787 iq = &s->rxq[pi->first_rxq + idx].iq;
790 KASSERT(iq->flags & IQ_INTR, ("%s: EDOOFUS", __func__));
795 mtu_to_bufsize(int mtu)
799 /* large enough for a frame even when VLAN extraction is disabled */
800 bufsize = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + mtu;
801 bufsize = roundup2(bufsize + fl_pktshift, fl_pad);
808 mtu_to_bufsize_toe(struct adapter *sc, int mtu)
811 if (sc->tt.rx_coalesce)
812 return (G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)));
819 t4_setup_port_queues(struct port_info *pi)
821 int rc = 0, i, j, intr_idx, iqid;
824 struct sge_wrq *ctrlq;
826 struct sge_ofld_rxq *ofld_rxq;
827 struct sge_wrq *ofld_txq;
828 struct sysctl_oid *oid2 = NULL;
831 struct adapter *sc = pi->adapter;
832 struct ifnet *ifp = pi->ifp;
833 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
834 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
837 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD,
841 if (is_offload(sc)) {
842 oid2 = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
844 "rx queues for offloaded TCP connections");
848 /* Interrupt vector to start from (when using multiple vectors) */
849 intr_idx = first_vector(pi);
852 * First pass over all rx queues (NIC and TOE):
853 * a) initialize iq and fl
854 * b) allocate queue iff it will take direct interrupts.
856 bufsize = mtu_to_bufsize(ifp->if_mtu);
857 pack = enable_buffer_packing(sc);
858 for_each_rxq(pi, i, rxq) {
860 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq,
863 snprintf(name, sizeof(name), "%s rxq%d-fl",
864 device_get_nameunit(pi->dev), i);
865 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, bufsize, pack, name);
867 if (sc->flags & INTR_DIRECT
869 || (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq)
872 rxq->iq.flags |= IQ_INTR;
873 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
881 bufsize = mtu_to_bufsize_toe(sc, ifp->if_mtu);
882 pack = 0; /* XXX: think about this some more */
883 for_each_ofld_rxq(pi, i, ofld_rxq) {
885 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
886 pi->qsize_rxq, RX_IQ_ESIZE);
888 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
889 device_get_nameunit(pi->dev), i);
890 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, bufsize, pack,
893 if (sc->flags & INTR_DIRECT ||
894 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) {
895 ofld_rxq->iq.flags |= IQ_INTR;
896 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2);
905 * Second pass over all rx queues (NIC and TOE). The queues forwarding
906 * their interrupts are allocated now.
909 for_each_rxq(pi, i, rxq) {
910 if (rxq->iq.flags & IQ_INTR)
913 intr_idx = port_intr_iq(pi, j)->abs_id;
915 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
922 for_each_ofld_rxq(pi, i, ofld_rxq) {
923 if (ofld_rxq->iq.flags & IQ_INTR)
926 intr_idx = port_intr_iq(pi, j)->abs_id;
928 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid2);
936 * Now the tx queues. Only one pass needed.
938 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
941 for_each_txq(pi, i, txq) {
944 iqid = port_intr_iq(pi, j)->cntxt_id;
946 snprintf(name, sizeof(name), "%s txq%d",
947 device_get_nameunit(pi->dev), i);
948 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
951 rc = alloc_txq(pi, txq, i, oid);
958 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
959 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
960 for_each_ofld_txq(pi, i, ofld_txq) {
963 iqid = port_intr_iq(pi, j)->cntxt_id;
965 snprintf(name, sizeof(name), "%s ofld_txq%d",
966 device_get_nameunit(pi->dev), i);
967 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
970 snprintf(name, sizeof(name), "%d", i);
971 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
972 name, CTLFLAG_RD, NULL, "offload tx queue");
974 rc = alloc_wrq(sc, pi, ofld_txq, oid2);
982 * Finally, the control queue.
984 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
986 ctrlq = &sc->sge.ctrlq[pi->port_id];
987 iqid = port_intr_iq(pi, 0)->cntxt_id;
988 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
989 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
990 rc = alloc_wrq(sc, pi, ctrlq, oid);
994 t4_teardown_port_queues(pi);
1003 t4_teardown_port_queues(struct port_info *pi)
1006 struct adapter *sc = pi->adapter;
1007 struct sge_rxq *rxq;
1008 struct sge_txq *txq;
1010 struct sge_ofld_rxq *ofld_rxq;
1011 struct sge_wrq *ofld_txq;
1014 /* Do this before freeing the queues */
1015 if (pi->flags & PORT_SYSCTL_CTX) {
1016 sysctl_ctx_free(&pi->ctx);
1017 pi->flags &= ~PORT_SYSCTL_CTX;
1021 * Take down all the tx queues first, as they reference the rx queues
1022 * (for egress updates, etc.).
1025 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1027 for_each_txq(pi, i, txq) {
1032 for_each_ofld_txq(pi, i, ofld_txq) {
1033 free_wrq(sc, ofld_txq);
1038 * Then take down the rx queues that forward their interrupts, as they
1039 * reference other rx queues.
1042 for_each_rxq(pi, i, rxq) {
1043 if ((rxq->iq.flags & IQ_INTR) == 0)
1048 for_each_ofld_rxq(pi, i, ofld_rxq) {
1049 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1050 free_ofld_rxq(pi, ofld_rxq);
1055 * Then take down the rx queues that take direct interrupts.
1058 for_each_rxq(pi, i, rxq) {
1059 if (rxq->iq.flags & IQ_INTR)
1064 for_each_ofld_rxq(pi, i, ofld_rxq) {
1065 if (ofld_rxq->iq.flags & IQ_INTR)
1066 free_ofld_rxq(pi, ofld_rxq);
1074 * Deals with errors and the firmware event queue. All data rx queues forward
1075 * their interrupt to the firmware event queue.
1078 t4_intr_all(void *arg)
1080 struct adapter *sc = arg;
1081 struct sge_iq *fwq = &sc->sge.fwq;
1084 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1086 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1090 /* Deals with error interrupts */
1092 t4_intr_err(void *arg)
1094 struct adapter *sc = arg;
1096 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1097 t4_slow_intr_handler(sc);
1101 t4_intr_evt(void *arg)
1103 struct sge_iq *iq = arg;
1105 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1107 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1114 struct sge_iq *iq = arg;
1116 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1118 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1123 * Deals with anything and everything on the given ingress queue.
1126 service_iq(struct sge_iq *iq, int budget)
1129 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1130 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */
1131 struct adapter *sc = iq->adapter;
1132 struct rsp_ctrl *ctrl;
1133 const struct rss_header *rss;
1134 int ndescs = 0, limit, fl_bufs_used = 0;
1138 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1139 #if defined(INET) || defined(INET6)
1140 const struct timeval lro_timeout = {0, sc->lro_timeout};
1143 limit = budget ? budget : iq->qsize / 8;
1145 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1148 * We always come back and check the descriptor ring for new indirect
1149 * interrupts and other responses after running a single handler.
1152 while (is_new_response(iq, &ctrl)) {
1157 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen);
1158 lq = be32toh(ctrl->pldbuflen_qid);
1159 rss = (const void *)iq->cdesc;
1162 case X_RSPD_TYPE_FLBUF:
1164 KASSERT(iq->flags & IQ_HAS_FL,
1165 ("%s: data for an iq (%p) with no freelist",
1168 m0 = fl->flags & FL_BUF_PACKING ?
1169 get_fl_payload1(sc, fl, lq, &fl_bufs_used) :
1170 get_fl_payload2(sc, fl, lq, &fl_bufs_used);
1172 if (__predict_false(m0 == NULL))
1174 #ifdef T4_PKT_TIMESTAMP
1176 * 60 bit timestamp for the payload is
1177 * *(uint64_t *)m0->m_pktdat. Note that it is
1178 * in the leading free-space in the mbuf. The
1179 * kernel can clobber it during a pullup,
1180 * m_copymdata, etc. You need to make sure that
1181 * the mbuf reaches you unmolested if you care
1182 * about the timestamp.
1184 *(uint64_t *)m0->m_pktdat =
1185 be64toh(ctrl->u.last_flit) &
1191 case X_RSPD_TYPE_CPL:
1192 KASSERT(rss->opcode < NUM_CPL_CMDS,
1193 ("%s: bad opcode %02x.", __func__,
1195 sc->cpl_handler[rss->opcode](iq, rss, m0);
1198 case X_RSPD_TYPE_INTR:
1201 * Interrupts should be forwarded only to queues
1202 * that are not forwarding their interrupts.
1203 * This means service_iq can recurse but only 1
1206 KASSERT(budget == 0,
1207 ("%s: budget %u, rsp_type %u", __func__,
1211 * There are 1K interrupt-capable queues (qids 0
1212 * through 1023). A response type indicating a
1213 * forwarded interrupt with a qid >= 1K is an
1214 * iWARP async notification.
1217 sc->an_handler(iq, ctrl);
1221 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1222 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1224 if (service_iq(q, q->qsize / 8) == 0) {
1225 atomic_cmpset_int(&q->state,
1226 IQS_BUSY, IQS_IDLE);
1228 STAILQ_INSERT_TAIL(&iql, q,
1236 ("%s: illegal response type %d on iq %p",
1237 __func__, rsp_type, iq));
1239 "%s: illegal response type %d on iq %p",
1240 device_get_nameunit(sc->dev), rsp_type, iq);
1245 if (++ndescs == limit) {
1246 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1248 V_INGRESSQID(iq->cntxt_id) |
1249 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1252 #if defined(INET) || defined(INET6)
1253 if (iq->flags & IQ_LRO_ENABLED &&
1254 sc->lro_timeout != 0) {
1255 tcp_lro_flush_inactive(&rxq->lro,
1260 if (fl_bufs_used > 0) {
1262 fl->needed += fl_bufs_used;
1263 refill_fl(sc, fl, fl->cap / 8);
1269 return (EINPROGRESS);
1274 if (STAILQ_EMPTY(&iql))
1278 * Process the head only, and send it to the back of the list if
1279 * it's still not done.
1281 q = STAILQ_FIRST(&iql);
1282 STAILQ_REMOVE_HEAD(&iql, link);
1283 if (service_iq(q, q->qsize / 8) == 0)
1284 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1286 STAILQ_INSERT_TAIL(&iql, q, link);
1289 #if defined(INET) || defined(INET6)
1290 if (iq->flags & IQ_LRO_ENABLED) {
1291 struct lro_ctrl *lro = &rxq->lro;
1292 struct lro_entry *l;
1294 while (!SLIST_EMPTY(&lro->lro_active)) {
1295 l = SLIST_FIRST(&lro->lro_active);
1296 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1297 tcp_lro_flush(lro, l);
1302 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1303 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1305 if (iq->flags & IQ_HAS_FL) {
1309 fl->needed += fl_bufs_used;
1310 starved = refill_fl(sc, fl, fl->cap / 4);
1312 if (__predict_false(starved != 0))
1313 add_fl_to_sfl(sc, fl);
1320 fill_mbuf_stash(struct sge_fl *fl)
1324 for (i = 0; i < nitems(fl->mstash); i++) {
1325 if (fl->mstash[i] == NULL) {
1327 if ((m = m_get(M_NOWAIT, MT_NOINIT)) == NULL)
1335 static struct mbuf *
1336 get_mbuf_from_stash(struct sge_fl *fl)
1340 for (i = 0; i < nitems(fl->mstash); i++) {
1341 if (fl->mstash[i] != NULL) {
1345 fl->mstash[i] = NULL;
1348 fl->mstash[i] = m_get(M_NOWAIT, MT_NOINIT);
1351 return (m_get(M_NOWAIT, MT_NOINIT));
1355 return_mbuf_to_stash(struct sge_fl *fl, struct mbuf *m)
1362 for (i = 0; i < nitems(fl->mstash); i++) {
1363 if (fl->mstash[i] == NULL) {
1368 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0);
1372 /* buf can be any address within the buffer */
1373 static inline u_int *
1374 find_buf_refcnt(caddr_t buf)
1376 uintptr_t ptr = (uintptr_t)buf;
1378 return ((u_int *)((ptr & ~(MJUMPAGESIZE - 1)) + MSIZE - sizeof(u_int)));
1381 static inline struct mbuf *
1382 find_buf_mbuf(caddr_t buf)
1384 uintptr_t ptr = (uintptr_t)buf;
1386 return ((struct mbuf *)(ptr & ~(MJUMPAGESIZE - 1)));
1390 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1392 uma_zone_t zone = arg1;
1397 refcount = *find_buf_refcnt(cl);
1398 KASSERT(refcount == 0, ("%s: cl %p refcount is %u", __func__,
1399 cl - MSIZE, refcount));
1402 uma_zfree(zone, cl);
1404 return (EXT_FREE_OK);
1407 static struct mbuf *
1408 get_fl_payload1(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf,
1411 struct mbuf *m0, *m;
1412 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1413 unsigned int nbuf, len;
1414 int pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack;
1417 * No assertion for the fl lock because we don't need it. This routine
1418 * is called only from the rx interrupt handler and it only updates
1419 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be
1420 * updated in the rx interrupt handler or the starvation helper routine.
1421 * That's why code that manipulates fl->pidx/fl->needed needs the fl
1422 * lock but this routine does not).
1425 KASSERT(fl->flags & FL_BUF_PACKING,
1426 ("%s: buffer packing disabled for fl %p", __func__, fl));
1428 len = G_RSPD_LEN(len_newbuf);
1430 if ((len_newbuf & F_RSPD_NEWBUF) == 0) {
1431 KASSERT(fl->rx_offset > 0,
1432 ("%s: packed frame but driver at offset=0", __func__));
1434 /* A packed frame is guaranteed to fit entirely in this buf. */
1435 KASSERT(FL_BUF_SIZE(sc, sd->tag_idx) - fl->rx_offset >= len,
1436 ("%s: packing error. bufsz=%u, offset=%u, len=%u",
1437 __func__, FL_BUF_SIZE(sc, sd->tag_idx), fl->rx_offset,
1440 m0 = get_mbuf_from_stash(fl);
1442 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR) != 0) {
1443 return_mbuf_to_stash(fl, m0);
1447 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map,
1448 BUS_DMASYNC_POSTREAD);
1449 if (len < RX_COPY_THRESHOLD) {
1450 #ifdef T4_PKT_TIMESTAMP
1451 /* Leave room for a timestamp */
1454 bcopy(sd->cl + fl->rx_offset, mtod(m0, caddr_t), len);
1455 m0->m_pkthdr.len = len;
1458 m0->m_pkthdr.len = len;
1460 m_extaddref(m0, sd->cl + fl->rx_offset,
1461 roundup2(m0->m_len, fl_pad),
1462 find_buf_refcnt(sd->cl), rxb_free,
1463 FL_BUF_ZONE(sc, sd->tag_idx), sd->cl);
1465 fl->rx_offset += len;
1466 fl->rx_offset = roundup2(fl->rx_offset, fl_pad);
1467 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary);
1468 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) {
1470 (*fl_bufs_used) += 1;
1471 if (__predict_false(++fl->cidx == fl->cap))
1478 KASSERT(len_newbuf & F_RSPD_NEWBUF,
1479 ("%s: only new buffer handled here", __func__));
1484 * Move to the start of the next buffer if we are still in the middle of
1485 * some buffer. This is the case where there was some room left in the
1486 * previous buffer but not enough to fit this frame in its entirety.
1488 if (fl->rx_offset > 0) {
1489 KASSERT(roundup2(len, fl_pad) > FL_BUF_SIZE(sc, sd->tag_idx) -
1490 fl->rx_offset, ("%s: frame (%u bytes) should have fit at "
1491 "cidx %u offset %u bufsize %u", __func__, len, fl->cidx,
1492 fl->rx_offset, FL_BUF_SIZE(sc, sd->tag_idx)));
1496 if (__predict_false(++fl->cidx == fl->cap)) {
1502 m0 = find_buf_mbuf(sd->cl);
1503 if (m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR | M_NOFREE))
1505 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD);
1506 m0->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx));
1507 m_extaddref(m0, sd->cl, roundup2(m0->m_len, fl_pad),
1508 find_buf_refcnt(sd->cl), rxb_free, FL_BUF_ZONE(sc, sd->tag_idx),
1510 m0->m_pkthdr.len = len;
1512 fl->rx_offset = roundup2(m0->m_len, fl_pad);
1513 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary);
1514 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) {
1518 if (__predict_false(++fl->cidx == fl->cap)) {
1528 m->m_next = find_buf_mbuf(sd->cl);
1531 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map,
1532 BUS_DMASYNC_POSTREAD);
1534 /* m_init for !M_PKTHDR can't fail so don't bother */
1535 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, M_NOFREE);
1536 m->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx));
1537 m_extaddref(m, sd->cl, roundup2(m->m_len, fl_pad),
1538 find_buf_refcnt(sd->cl), rxb_free,
1539 FL_BUF_ZONE(sc, sd->tag_idx), sd->cl);
1541 fl->rx_offset = roundup2(m->m_len, fl_pad);
1542 fl->rx_offset = roundup2(fl->rx_offset, pack_boundary);
1543 if (fl->rx_offset >= FL_BUF_SIZE(sc, sd->tag_idx)) {
1547 if (__predict_false(++fl->cidx == fl->cap)) {
1556 (*fl_bufs_used) += nbuf;
1560 static struct mbuf *
1561 get_fl_payload2(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf,
1564 struct mbuf *m0, *m;
1565 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1566 unsigned int nbuf, len;
1569 * No assertion for the fl lock because we don't need it. This routine
1570 * is called only from the rx interrupt handler and it only updates
1571 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be
1572 * updated in the rx interrupt handler or the starvation helper routine.
1573 * That's why code that manipulates fl->pidx/fl->needed needs the fl
1574 * lock but this routine does not).
1577 KASSERT((fl->flags & FL_BUF_PACKING) == 0,
1578 ("%s: buffer packing enabled for fl %p", __func__, fl));
1579 if (__predict_false((len_newbuf & F_RSPD_NEWBUF) == 0))
1580 panic("%s: cannot handle packed frames", __func__);
1581 len = G_RSPD_LEN(len_newbuf);
1584 * We never want to run out of mbufs in between a frame when a frame
1585 * spans multiple fl buffers. If the fl's mbuf stash isn't full and
1586 * can't be filled up to the brim then fail early.
1588 if (len > FL_BUF_SIZE(sc, sd->tag_idx) && fill_mbuf_stash(fl) != 0)
1591 m0 = get_mbuf_from_stash(fl);
1593 m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR) != 0) {
1594 return_mbuf_to_stash(fl, m0);
1598 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD);
1600 if (len < RX_COPY_THRESHOLD) {
1601 #ifdef T4_PKT_TIMESTAMP
1602 /* Leave room for a timestamp */
1605 /* copy data to mbuf, buffer will be recycled */
1606 bcopy(sd->cl, mtod(m0, caddr_t), len);
1609 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map);
1610 m_cljset(m0, sd->cl, FL_BUF_TYPE(sc, sd->tag_idx));
1611 sd->cl = NULL; /* consumed */
1612 m0->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx));
1614 m0->m_pkthdr.len = len;
1617 if (__predict_false(++fl->cidx == fl->cap)) {
1624 nbuf = 1; /* # of fl buffers used */
1627 /* Can't fail, we checked earlier that the stash was full. */
1628 m->m_next = get_mbuf_from_stash(fl);
1631 bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map,
1632 BUS_DMASYNC_POSTREAD);
1634 /* m_init for !M_PKTHDR can't fail so don't bother */
1635 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0);
1637 bcopy(sd->cl, mtod(m, caddr_t), len);
1640 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map);
1641 m_cljset(m, sd->cl, FL_BUF_TYPE(sc, sd->tag_idx));
1642 sd->cl = NULL; /* consumed */
1643 m->m_len = min(len, FL_BUF_SIZE(sc, sd->tag_idx));
1647 if (__predict_false(++fl->cidx == fl->cap)) {
1656 (*fl_bufs_used) += nbuf;
1662 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1664 struct sge_rxq *rxq = iq_to_rxq(iq);
1665 struct ifnet *ifp = rxq->ifp;
1666 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1667 #if defined(INET) || defined(INET6)
1668 struct lro_ctrl *lro = &rxq->lro;
1671 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1674 m0->m_pkthdr.len -= fl_pktshift;
1675 m0->m_len -= fl_pktshift;
1676 m0->m_data += fl_pktshift;
1678 m0->m_pkthdr.rcvif = ifp;
1679 m0->m_flags |= M_FLOWID;
1680 m0->m_pkthdr.flowid = rss->hash_val;
1682 if (cpl->csum_calc && !cpl->err_vec) {
1683 if (ifp->if_capenable & IFCAP_RXCSUM &&
1684 cpl->l2info & htobe32(F_RXF_IP)) {
1685 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1686 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1688 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1689 cpl->l2info & htobe32(F_RXF_IP6)) {
1690 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1695 if (__predict_false(cpl->ip_frag))
1696 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1698 m0->m_pkthdr.csum_data = 0xffff;
1702 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1703 m0->m_flags |= M_VLANTAG;
1704 rxq->vlan_extraction++;
1707 #if defined(INET) || defined(INET6)
1708 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1709 iq->flags & IQ_LRO_ENABLED &&
1710 tcp_lro_rx(lro, m0, 0) == 0) {
1711 /* queued for LRO */
1714 ifp->if_input(ifp, m0);
1720 * Doesn't fail. Holds on to work requests it can't send right away.
1723 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1725 struct sge_eq *eq = &wrq->eq;
1729 TXQ_LOCK_ASSERT_OWNED(wrq);
1731 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD ||
1732 (eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1733 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1735 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1736 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1739 if (__predict_true(wr != NULL))
1740 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1742 can_reclaim = reclaimable(eq);
1743 if (__predict_false(eq->flags & EQ_STALLED)) {
1744 if (can_reclaim < tx_resume_threshold(eq))
1746 eq->flags &= ~EQ_STALLED;
1749 eq->cidx += can_reclaim;
1750 eq->avail += can_reclaim;
1751 if (__predict_false(eq->cidx >= eq->cap))
1752 eq->cidx -= eq->cap;
1754 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
1757 if (__predict_false(wr->wr_len < 0 ||
1758 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) {
1761 panic("%s: work request with length %d", __func__,
1767 log(LOG_ERR, "%s: %s work request with length %d",
1768 device_get_nameunit(sc->dev), __func__, wr->wr_len);
1769 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1774 ndesc = howmany(wr->wr_len, EQ_ESIZE);
1775 if (eq->avail < ndesc) {
1780 dst = (void *)&eq->desc[eq->pidx];
1781 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len);
1785 if (__predict_false(eq->pidx >= eq->cap))
1786 eq->pidx -= eq->cap;
1788 eq->pending += ndesc;
1789 if (eq->pending >= 8)
1793 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1796 if (eq->avail < 8) {
1797 can_reclaim = reclaimable(eq);
1798 eq->cidx += can_reclaim;
1799 eq->avail += can_reclaim;
1800 if (__predict_false(eq->cidx >= eq->cap))
1801 eq->cidx -= eq->cap;
1809 eq->flags |= EQ_STALLED;
1810 if (callout_pending(&eq->tx_callout) == 0)
1811 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
1815 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */
1816 #define TXPKTS_PKT_HDR ((\
1817 sizeof(struct ulp_txpkt) + \
1818 sizeof(struct ulptx_idata) + \
1819 sizeof(struct cpl_tx_pkt_core) \
1822 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */
1823 #define TXPKTS_WR_HDR (\
1824 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \
1827 /* Header of a tx WR, before SGL of first packet (in flits) */
1828 #define TXPKT_WR_HDR ((\
1829 sizeof(struct fw_eth_tx_pkt_wr) + \
1830 sizeof(struct cpl_tx_pkt_core) \
1833 /* Header of a tx LSO WR, before SGL of first packet (in flits) */
1834 #define TXPKT_LSO_WR_HDR ((\
1835 sizeof(struct fw_eth_tx_pkt_wr) + \
1836 sizeof(struct cpl_tx_pkt_lso_core) + \
1837 sizeof(struct cpl_tx_pkt_core) \
1841 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
1843 struct port_info *pi = (void *)ifp->if_softc;
1844 struct adapter *sc = pi->adapter;
1845 struct sge_eq *eq = &txq->eq;
1846 struct buf_ring *br = txq->br;
1848 int rc, coalescing, can_reclaim;
1849 struct txpkts txpkts;
1852 TXQ_LOCK_ASSERT_OWNED(txq);
1853 KASSERT(m, ("%s: called with nothing to do.", __func__));
1854 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH,
1855 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1857 prefetch(&eq->desc[eq->pidx]);
1858 prefetch(&txq->sdesc[eq->pidx]);
1860 txpkts.npkt = 0;/* indicates there's nothing in txpkts */
1863 can_reclaim = reclaimable(eq);
1864 if (__predict_false(eq->flags & EQ_STALLED)) {
1865 if (can_reclaim < tx_resume_threshold(eq)) {
1869 eq->flags &= ~EQ_STALLED;
1873 if (__predict_false(eq->flags & EQ_DOOMED)) {
1875 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
1880 if (eq->avail < 8 && can_reclaim)
1881 reclaim_tx_descs(txq, can_reclaim, 32);
1883 for (; m; m = next ? next : drbr_dequeue(ifp, br)) {
1888 next = m->m_nextpkt;
1889 m->m_nextpkt = NULL;
1891 if (next || buf_ring_peek(br))
1894 rc = get_pkt_sgl(txq, &m, &sgl, coalescing);
1898 /* Short of resources, suspend tx */
1900 m->m_nextpkt = next;
1905 * Unrecoverable error for this packet, throw it away
1906 * and move on to the next. get_pkt_sgl may already
1907 * have freed m (it will be NULL in that case and the
1908 * m_freem here is still safe).
1916 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) {
1918 /* Successfully absorbed into txpkts */
1920 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl);
1925 * We weren't coalescing to begin with, or current frame could
1926 * not be coalesced (add_to_txpkts flushes txpkts if a frame
1927 * given to it can't be coalesced). Either way there should be
1928 * nothing in txpkts.
1930 KASSERT(txpkts.npkt == 0,
1931 ("%s: txpkts not empty: %d", __func__, txpkts.npkt));
1933 /* We're sending out individual packets now */
1937 reclaim_tx_descs(txq, 0, 8);
1938 rc = write_txpkt_wr(pi, txq, m, &sgl);
1941 /* Short of hardware descriptors, suspend tx */
1944 * This is an unlikely but expensive failure. We've
1945 * done all the hard work (DMA mappings etc.) and now we
1946 * can't send out the packet. What's worse, we have to
1947 * spend even more time freeing up everything in sgl.
1950 free_pkt_sgl(txq, &sgl);
1952 m->m_nextpkt = next;
1956 ETHER_BPF_MTAP(ifp, m);
1960 if (eq->pending >= 8)
1963 can_reclaim = reclaimable(eq);
1964 if (can_reclaim >= 32)
1965 reclaim_tx_descs(txq, can_reclaim, 64);
1968 if (txpkts.npkt > 0)
1969 write_txpkts_wr(txq, &txpkts);
1972 * m not NULL means there was an error but we haven't thrown it away.
1973 * This can happen when we're short of tx descriptors (no_desc) or maybe
1974 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim
1975 * will get things going again.
1977 if (m && !(eq->flags & EQ_CRFLUSHED)) {
1978 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx];
1981 * If EQ_CRFLUSHED is not set then we know we have at least one
1982 * available descriptor because any WR that reduces eq->avail to
1983 * 0 also sets EQ_CRFLUSHED.
1985 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__));
1987 txsd->desc_used = 1;
1989 write_eqflush_wr(eq);
1996 reclaim_tx_descs(txq, 0, 128);
1998 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0)
1999 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
2005 t4_update_fl_bufsize(struct ifnet *ifp)
2007 struct port_info *pi = ifp->if_softc;
2008 struct adapter *sc = pi->adapter;
2009 struct sge_rxq *rxq;
2011 struct sge_ofld_rxq *ofld_rxq;
2016 bufsize = mtu_to_bufsize(ifp->if_mtu);
2017 for_each_rxq(pi, i, rxq) {
2021 set_fl_tag_idx(sc, fl, bufsize);
2025 bufsize = mtu_to_bufsize_toe(pi->adapter, ifp->if_mtu);
2026 for_each_ofld_rxq(pi, i, ofld_rxq) {
2030 set_fl_tag_idx(sc, fl, bufsize);
2037 can_resume_tx(struct sge_eq *eq)
2039 return (reclaimable(eq) >= tx_resume_threshold(eq));
2043 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2044 int qsize, int esize)
2046 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2047 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2048 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2049 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2053 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2054 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2055 if (pktc_idx >= 0) {
2056 iq->intr_params |= F_QINTR_CNT_EN;
2057 iq->intr_pktc_idx = pktc_idx;
2059 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2060 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */
2064 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int bufsize, int pack,
2069 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2071 fl->flags |= FL_BUF_PACKING;
2072 set_fl_tag_idx(sc, fl, bufsize);
2076 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
2077 uint16_t iqid, char *name)
2079 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
2080 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2082 eq->flags = eqtype & EQ_TYPEMASK;
2083 eq->tx_chan = tx_chan;
2086 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2088 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq);
2089 callout_init(&eq->tx_callout, CALLOUT_MPSAFE);
2093 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2094 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2098 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2099 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2101 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2105 rc = bus_dmamem_alloc(*tag, va,
2106 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2108 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2112 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2114 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2119 free_ring(sc, *tag, *map, *pa, *va);
2125 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2126 bus_addr_t pa, void *va)
2129 bus_dmamap_unload(tag, map);
2131 bus_dmamem_free(tag, va, map);
2133 bus_dma_tag_destroy(tag);
2139 * Allocates the ring for an ingress queue and an optional freelist. If the
2140 * freelist is specified it will be allocated and then associated with the
2143 * Returns errno on failure. Resources allocated up to that point may still be
2144 * allocated. Caller is responsible for cleanup in case this function fails.
2146 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2147 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2148 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2151 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
2152 int intr_idx, int cong)
2154 int rc, i, cntxt_id;
2157 struct adapter *sc = iq->adapter;
2160 len = iq->qsize * iq->esize;
2161 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2162 (void **)&iq->desc);
2166 bzero(&c, sizeof(c));
2167 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2168 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2169 V_FW_IQ_CMD_VFN(0));
2171 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2174 /* Special handling for firmware event queue */
2175 if (iq == &sc->sge.fwq)
2176 v |= F_FW_IQ_CMD_IQASYNCH;
2178 if (iq->flags & IQ_INTR) {
2179 KASSERT(intr_idx < sc->intr_count,
2180 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2182 v |= F_FW_IQ_CMD_IQANDST;
2183 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2185 c.type_to_iqandstindex = htobe32(v |
2186 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2187 V_FW_IQ_CMD_VIID(pi->viid) |
2188 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2189 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2190 F_FW_IQ_CMD_IQGTSMODE |
2191 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2192 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4));
2193 c.iqsize = htobe16(iq->qsize);
2194 c.iqaddr = htobe64(iq->ba);
2196 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2199 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2201 for (i = 0; i < FL_BUF_SIZES(sc); i++) {
2204 * A freelist buffer must be 16 byte aligned as the SGE
2205 * uses the low 4 bits of the bus addr to figure out the
2208 rc = bus_dma_tag_create(sc->dmat, 16, 0,
2209 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2210 FL_BUF_SIZE(sc, i), 1, FL_BUF_SIZE(sc, i),
2211 BUS_DMA_ALLOCNOW, NULL, NULL, &fl->tag[i]);
2213 device_printf(sc->dev,
2214 "failed to create fl DMA tag[%d]: %d\n",
2219 len = fl->qsize * RX_FL_ESIZE;
2220 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2221 &fl->ba, (void **)&fl->desc);
2225 /* Allocate space for one software descriptor per buffer. */
2226 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8;
2227 rc = alloc_fl_sdesc(fl);
2229 device_printf(sc->dev,
2230 "failed to setup fl software descriptors: %d\n",
2234 fl->needed = fl->cap;
2235 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
2237 c.iqns_to_fl0congen |=
2238 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2239 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2240 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2241 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2244 c.iqns_to_fl0congen |=
2245 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2246 F_FW_IQ_CMD_FL0CONGCIF |
2247 F_FW_IQ_CMD_FL0CONGEN);
2249 c.fl0dcaen_to_fl0cidxfthresh =
2250 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) |
2251 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2252 c.fl0size = htobe16(fl->qsize);
2253 c.fl0addr = htobe64(fl->ba);
2256 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2258 device_printf(sc->dev,
2259 "failed to create ingress queue: %d\n", rc);
2263 iq->cdesc = iq->desc;
2266 iq->intr_next = iq->intr_params;
2267 iq->cntxt_id = be16toh(c.iqid);
2268 iq->abs_id = be16toh(c.physiqid);
2269 iq->flags |= IQ_ALLOCATED;
2271 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2272 if (cntxt_id >= sc->sge.niq) {
2273 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2274 cntxt_id, sc->sge.niq - 1);
2276 sc->sge.iqmap[cntxt_id] = iq;
2279 fl->cntxt_id = be16toh(c.fl0id);
2280 fl->pidx = fl->cidx = 0;
2282 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2283 if (cntxt_id >= sc->sge.neq) {
2284 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2285 __func__, cntxt_id, sc->sge.neq - 1);
2287 sc->sge.eqmap[cntxt_id] = (void *)fl;
2290 /* Enough to make sure the SGE doesn't think it's starved */
2291 refill_fl(sc, fl, fl->lowat);
2294 iq->flags |= IQ_HAS_FL;
2297 if (is_t5(sc) && cong >= 0) {
2298 uint32_t param, val;
2300 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2301 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2302 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2307 for (i = 0; i < 4; i++) {
2308 if (cong & (1 << i))
2309 val |= 1 << (i << 2);
2313 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2315 /* report error but carry on */
2316 device_printf(sc->dev,
2317 "failed to set congestion manager context for "
2318 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2322 /* Enable IQ interrupts */
2323 atomic_store_rel_int(&iq->state, IQS_IDLE);
2324 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2325 V_INGRESSQID(iq->cntxt_id));
2331 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
2334 struct adapter *sc = iq->adapter;
2338 return (0); /* nothing to do */
2340 dev = pi ? pi->dev : sc->dev;
2342 if (iq->flags & IQ_ALLOCATED) {
2343 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2344 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2345 fl ? fl->cntxt_id : 0xffff, 0xffff);
2348 "failed to free queue %p: %d\n", iq, rc);
2351 iq->flags &= ~IQ_ALLOCATED;
2354 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2356 bzero(iq, sizeof(*iq));
2359 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2363 free_fl_sdesc(sc, fl);
2365 for (i = 0; i < nitems(fl->mstash); i++) {
2366 struct mbuf *m = fl->mstash[i];
2369 m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0);
2374 if (mtx_initialized(&fl->fl_lock))
2375 mtx_destroy(&fl->fl_lock);
2377 for (i = 0; i < FL_BUF_SIZES(sc); i++) {
2379 bus_dma_tag_destroy(fl->tag[i]);
2382 bzero(fl, sizeof(*fl));
2389 alloc_fwq(struct adapter *sc)
2392 struct sge_iq *fwq = &sc->sge.fwq;
2393 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2394 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2396 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE);
2397 fwq->flags |= IQ_INTR; /* always */
2398 intr_idx = sc->intr_count > 1 ? 1 : 0;
2399 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
2401 device_printf(sc->dev,
2402 "failed to create firmware event queue: %d\n", rc);
2406 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2407 NULL, "firmware event queue");
2408 children = SYSCTL_CHILDREN(oid);
2410 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2411 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2412 "absolute id of the queue");
2413 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2414 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2415 "SGE context id of the queue");
2416 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2417 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2424 free_fwq(struct adapter *sc)
2426 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2430 alloc_mgmtq(struct adapter *sc)
2433 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2435 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2436 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2438 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2439 NULL, "management queue");
2441 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2442 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2443 sc->sge.fwq.cntxt_id, name);
2444 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2446 device_printf(sc->dev,
2447 "failed to create management queue: %d\n", rc);
2455 free_mgmtq(struct adapter *sc)
2458 return free_wrq(sc, &sc->sge.mgmtq);
2462 tnl_cong(struct port_info *pi)
2465 if (cong_drop == -1)
2467 else if (cong_drop == 1)
2470 return (1 << pi->tx_chan);
2474 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
2475 struct sysctl_oid *oid)
2478 struct sysctl_oid_list *children;
2481 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi));
2486 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8);
2487 FL_UNLOCK(&rxq->fl);
2489 #if defined(INET) || defined(INET6)
2490 rc = tcp_lro_init(&rxq->lro);
2493 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
2495 if (pi->ifp->if_capenable & IFCAP_LRO)
2496 rxq->iq.flags |= IQ_LRO_ENABLED;
2500 children = SYSCTL_CHILDREN(oid);
2502 snprintf(name, sizeof(name), "%d", idx);
2503 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2505 children = SYSCTL_CHILDREN(oid);
2507 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2508 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2509 "absolute id of the queue");
2510 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2511 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2512 "SGE context id of the queue");
2513 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2514 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2516 #if defined(INET) || defined(INET6)
2517 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2518 &rxq->lro.lro_queued, 0, NULL);
2519 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2520 &rxq->lro.lro_flushed, 0, NULL);
2522 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2523 &rxq->rxcsum, "# of times hardware assisted with checksum");
2524 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction",
2525 CTLFLAG_RD, &rxq->vlan_extraction,
2526 "# of times hardware extracted 802.1Q tag");
2528 children = SYSCTL_CHILDREN(oid);
2529 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD,
2531 children = SYSCTL_CHILDREN(oid);
2533 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2534 CTLTYPE_INT | CTLFLAG_RD, &rxq->fl.cntxt_id, 0, sysctl_uint16, "I",
2535 "SGE context id of the queue");
2536 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
2537 &rxq->fl.cidx, 0, "consumer index");
2538 if (rxq->fl.flags & FL_BUF_PACKING) {
2539 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "rx_offset",
2540 CTLFLAG_RD, &rxq->fl.rx_offset, 0, "packing rx offset");
2542 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
2543 &rxq->fl.pidx, 0, "producer index");
2549 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
2553 #if defined(INET) || defined(INET6)
2555 tcp_lro_free(&rxq->lro);
2556 rxq->lro.ifp = NULL;
2560 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
2562 bzero(rxq, sizeof(*rxq));
2569 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
2570 int intr_idx, int idx, struct sysctl_oid *oid)
2573 struct sysctl_oid_list *children;
2576 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2581 children = SYSCTL_CHILDREN(oid);
2583 snprintf(name, sizeof(name), "%d", idx);
2584 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2586 children = SYSCTL_CHILDREN(oid);
2588 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2589 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2590 "I", "absolute id of the queue");
2591 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2592 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2593 "I", "SGE context id of the queue");
2594 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2595 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2598 children = SYSCTL_CHILDREN(oid);
2599 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "fl", CTLFLAG_RD,
2601 children = SYSCTL_CHILDREN(oid);
2603 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2604 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->fl.cntxt_id, 0, sysctl_uint16,
2605 "I", "SGE context id of the queue");
2606 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
2607 &ofld_rxq->fl.cidx, 0, "consumer index");
2608 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
2609 &ofld_rxq->fl.pidx, 0, "producer index");
2615 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
2619 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
2621 bzero(ofld_rxq, sizeof(*ofld_rxq));
2628 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
2631 struct fw_eq_ctrl_cmd c;
2633 bzero(&c, sizeof(c));
2635 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
2636 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
2637 V_FW_EQ_CTRL_CMD_VFN(0));
2638 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
2639 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
2640 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */
2641 c.physeqid_pkd = htobe32(0);
2642 c.fetchszm_to_iqid =
2643 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2644 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
2645 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
2647 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2648 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2649 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2650 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize));
2651 c.eqaddr = htobe64(eq->ba);
2653 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2655 device_printf(sc->dev,
2656 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
2659 eq->flags |= EQ_ALLOCATED;
2661 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
2662 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2663 if (cntxt_id >= sc->sge.neq)
2664 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2665 cntxt_id, sc->sge.neq - 1);
2666 sc->sge.eqmap[cntxt_id] = eq;
2672 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2675 struct fw_eq_eth_cmd c;
2677 bzero(&c, sizeof(c));
2679 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
2680 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
2681 V_FW_EQ_ETH_CMD_VFN(0));
2682 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
2683 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
2684 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
2685 c.fetchszm_to_iqid =
2686 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2687 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
2688 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
2689 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2690 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2691 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2692 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize));
2693 c.eqaddr = htobe64(eq->ba);
2695 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2697 device_printf(pi->dev,
2698 "failed to create Ethernet egress queue: %d\n", rc);
2701 eq->flags |= EQ_ALLOCATED;
2703 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
2704 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2705 if (cntxt_id >= sc->sge.neq)
2706 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2707 cntxt_id, sc->sge.neq - 1);
2708 sc->sge.eqmap[cntxt_id] = eq;
2715 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2718 struct fw_eq_ofld_cmd c;
2720 bzero(&c, sizeof(c));
2722 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
2723 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
2724 V_FW_EQ_OFLD_CMD_VFN(0));
2725 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
2726 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
2727 c.fetchszm_to_iqid =
2728 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2729 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
2730 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
2732 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2733 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2734 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2735 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize));
2736 c.eqaddr = htobe64(eq->ba);
2738 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2740 device_printf(pi->dev,
2741 "failed to create egress queue for TCP offload: %d\n", rc);
2744 eq->flags |= EQ_ALLOCATED;
2746 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
2747 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2748 if (cntxt_id >= sc->sge.neq)
2749 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2750 cntxt_id, sc->sge.neq - 1);
2751 sc->sge.eqmap[cntxt_id] = eq;
2758 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2763 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
2765 len = eq->qsize * EQ_ESIZE;
2766 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
2767 &eq->ba, (void **)&eq->desc);
2771 eq->cap = eq->qsize - spg_len / EQ_ESIZE;
2772 eq->spg = (void *)&eq->desc[eq->cap];
2773 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */
2774 eq->pidx = eq->cidx = 0;
2775 eq->doorbells = sc->doorbells;
2777 switch (eq->flags & EQ_TYPEMASK) {
2779 rc = ctrl_eq_alloc(sc, eq);
2783 rc = eth_eq_alloc(sc, pi, eq);
2788 rc = ofld_eq_alloc(sc, pi, eq);
2793 panic("%s: invalid eq type %d.", __func__,
2794 eq->flags & EQ_TYPEMASK);
2797 device_printf(sc->dev,
2798 "failed to allocate egress queue(%d): %d",
2799 eq->flags & EQ_TYPEMASK, rc);
2802 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus;
2804 if (isset(&eq->doorbells, DOORBELL_UDB) ||
2805 isset(&eq->doorbells, DOORBELL_UDBWC) ||
2806 isset(&eq->doorbells, DOORBELL_WCWR)) {
2807 uint32_t s_qpp = sc->sge.eq_s_qpp;
2808 uint32_t mask = (1 << s_qpp) - 1;
2809 volatile uint8_t *udb;
2811 udb = sc->udbs_base + UDBS_DB_OFFSET;
2812 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
2813 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
2814 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE)
2815 clrbit(&eq->doorbells, DOORBELL_WCWR);
2817 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
2820 eq->udb = (volatile void *)udb;
2827 free_eq(struct adapter *sc, struct sge_eq *eq)
2831 if (eq->flags & EQ_ALLOCATED) {
2832 switch (eq->flags & EQ_TYPEMASK) {
2834 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
2839 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
2845 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
2851 panic("%s: invalid eq type %d.", __func__,
2852 eq->flags & EQ_TYPEMASK);
2855 device_printf(sc->dev,
2856 "failed to free egress queue (%d): %d\n",
2857 eq->flags & EQ_TYPEMASK, rc);
2860 eq->flags &= ~EQ_ALLOCATED;
2863 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
2865 if (mtx_initialized(&eq->eq_lock))
2866 mtx_destroy(&eq->eq_lock);
2868 bzero(eq, sizeof(*eq));
2873 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
2874 struct sysctl_oid *oid)
2877 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
2878 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2880 rc = alloc_eq(sc, pi, &wrq->eq);
2885 STAILQ_INIT(&wrq->wr_list);
2887 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
2888 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
2889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
2890 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
2892 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
2893 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
2895 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD,
2896 &wrq->tx_wrs, "# of work requests");
2897 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
2899 "# of times queue ran out of hardware descriptors");
2900 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
2901 &wrq->eq.unstalled, 0, "# of times queue recovered after stall");
2908 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
2912 rc = free_eq(sc, &wrq->eq);
2916 bzero(wrq, sizeof(*wrq));
2921 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
2922 struct sysctl_oid *oid)
2925 struct adapter *sc = pi->adapter;
2926 struct sge_eq *eq = &txq->eq;
2928 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2930 rc = alloc_eq(sc, pi, eq);
2936 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE,
2938 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock);
2940 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR,
2941 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS,
2942 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag);
2944 device_printf(sc->dev,
2945 "failed to create tx DMA tag: %d\n", rc);
2950 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE
2951 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is
2952 * sized for the worst case.
2954 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8,
2957 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc);
2961 snprintf(name, sizeof(name), "%d", idx);
2962 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2964 children = SYSCTL_CHILDREN(oid);
2966 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
2967 &eq->cntxt_id, 0, "SGE context id of the queue");
2968 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2969 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
2971 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
2972 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
2975 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
2976 &txq->txcsum, "# of times hardware assisted with checksum");
2977 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion",
2978 CTLFLAG_RD, &txq->vlan_insertion,
2979 "# of times hardware inserted 802.1Q tag");
2980 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
2981 &txq->tso_wrs, "# of TSO work requests");
2982 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
2983 &txq->imm_wrs, "# of work requests with immediate data");
2984 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
2985 &txq->sgl_wrs, "# of work requests with direct SGL");
2986 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
2987 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
2988 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD,
2989 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)");
2990 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD,
2991 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests");
2993 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD,
2994 &txq->br->br_drops, "# of drops in the buf_ring for this queue");
2995 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD,
2996 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps");
2997 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
2998 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors");
2999 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD,
3000 &eq->egr_update, 0, "egress update notifications from the SGE");
3001 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
3002 &eq->unstalled, 0, "# of times txq recovered after stall");
3008 free_txq(struct port_info *pi, struct sge_txq *txq)
3011 struct adapter *sc = pi->adapter;
3012 struct sge_eq *eq = &txq->eq;
3014 rc = free_eq(sc, eq);
3018 free(txq->sdesc, M_CXGBE);
3020 if (txq->txmaps.maps)
3021 t4_free_tx_maps(&txq->txmaps, txq->tx_tag);
3023 buf_ring_free(txq->br, M_CXGBE);
3026 bus_dma_tag_destroy(txq->tx_tag);
3028 bzero(txq, sizeof(*txq));
3033 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3035 bus_addr_t *ba = arg;
3038 ("%s meant for single segment mappings only.", __func__));
3040 *ba = error ? 0 : segs->ds_addr;
3044 is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl)
3046 *ctrl = (void *)((uintptr_t)iq->cdesc +
3047 (iq->esize - sizeof(struct rsp_ctrl)));
3049 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen);
3053 iq_next(struct sge_iq *iq)
3055 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize);
3056 if (__predict_false(++iq->cidx == iq->qsize - 1)) {
3059 iq->cdesc = iq->desc;
3063 #define FL_HW_IDX(x) ((x) >> 3)
3065 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3067 int ndesc = fl->pending / 8;
3070 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx))
3071 ndesc--; /* hold back one credit */
3074 return; /* nothing to do */
3076 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc);
3082 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3083 fl->pending -= ndesc * 8;
3087 * Fill up the freelist by upto nbufs and maybe ring its doorbell.
3089 * Returns non-zero to indicate that it should be added to the list of starving
3093 refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs)
3095 __be64 *d = &fl->desc[fl->pidx];
3096 struct fl_sdesc *sd = &fl->sdesc[fl->pidx];
3102 FL_LOCK_ASSERT_OWNED(fl);
3104 if (fl->flags & FL_BUF_PACKING)
3105 KASSERT(sd->tag_idx == 0,
3106 ("%s: expected tag 0 but found tag %d at pidx %u instead",
3107 __func__, sd->tag_idx, fl->pidx));
3110 if (nbufs > fl->needed)
3115 if (sd->cl != NULL) {
3117 KASSERT(*d == sd->ba_hwtag,
3118 ("%s: recyling problem at pidx %d",
3119 __func__, fl->pidx));
3121 if (fl->flags & FL_BUF_PACKING) {
3122 u_int *refcount = find_buf_refcnt(sd->cl);
3124 if (atomic_fetchadd_int(refcount, -1) == 1) {
3125 *refcount = 1; /* reinstate */
3129 sd->cl = NULL; /* gave up my reference */
3132 * This happens when a frame small enough to fit
3133 * entirely in an mbuf was received in cl last
3134 * time. We'd held on to cl and can reuse it
3135 * now. Note that we reuse a cluster of the old
3136 * size if fl->tag_idx is no longer the same as
3144 if (__predict_false(fl->tag_idx != sd->tag_idx)) {
3146 bus_dma_tag_t newtag = fl->tag[fl->tag_idx];
3147 bus_dma_tag_t oldtag = fl->tag[sd->tag_idx];
3150 * An MTU change can get us here. Discard the old map
3151 * which was created with the old tag, but only if
3152 * we're able to get a new one.
3154 rc = bus_dmamap_create(newtag, 0, &map);
3156 bus_dmamap_destroy(oldtag, sd->map);
3158 sd->tag_idx = fl->tag_idx;
3162 tag = fl->tag[sd->tag_idx];
3164 cl = uma_zalloc(FL_BUF_ZONE(sc, sd->tag_idx), M_NOWAIT);
3167 if (fl->flags & FL_BUF_PACKING) {
3168 *find_buf_refcnt(cl) = 1;
3172 rc = bus_dmamap_load(tag, sd->map, cl,
3173 FL_BUF_SIZE(sc, sd->tag_idx), oneseg_dma_callback, &pa, 0);
3174 if (rc != 0 || pa == 0) {
3175 fl->dmamap_failed++;
3176 if (fl->flags & FL_BUF_PACKING)
3178 uma_zfree(FL_BUF_ZONE(sc, sd->tag_idx), cl);
3183 *d++ = htobe64(pa | FL_BUF_HWTAG(sc, sd->tag_idx));
3186 sd->ba_hwtag = htobe64(pa | FL_BUF_HWTAG(sc, sd->tag_idx));
3193 if (++fl->pidx == fl->cap) {
3200 if (fl->pending >= 8)
3203 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3207 * Attempt to refill all starving freelists.
3210 refill_sfl(void *arg)
3212 struct adapter *sc = arg;
3213 struct sge_fl *fl, *fl_temp;
3215 mtx_lock(&sc->sfl_lock);
3216 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3218 refill_fl(sc, fl, 64);
3219 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3220 TAILQ_REMOVE(&sc->sfl, fl, link);
3221 fl->flags &= ~FL_STARVING;
3226 if (!TAILQ_EMPTY(&sc->sfl))
3227 callout_schedule(&sc->sfl_callout, hz / 5);
3228 mtx_unlock(&sc->sfl_lock);
3232 alloc_fl_sdesc(struct sge_fl *fl)
3234 struct fl_sdesc *sd;
3238 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE,
3241 tag = fl->tag[fl->tag_idx];
3243 for (i = 0; i < fl->cap; i++, sd++) {
3245 sd->tag_idx = fl->tag_idx;
3246 rc = bus_dmamap_create(tag, 0, &sd->map);
3255 bus_dmamap_destroy(tag, sd->map);
3257 KASSERT(sd == fl->sdesc, ("%s: EDOOFUS", __func__));
3259 free(fl->sdesc, M_CXGBE);
3266 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3268 struct fl_sdesc *sd;
3272 for (i = 0; i < fl->cap; i++, sd++) {
3275 bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map);
3276 uma_zfree(FL_BUF_ZONE(sc, sd->tag_idx), sd->cl);
3280 bus_dmamap_destroy(fl->tag[sd->tag_idx], sd->map);
3283 free(fl->sdesc, M_CXGBE);
3288 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count,
3294 txmaps->map_total = txmaps->map_avail = count;
3295 txmaps->map_cidx = txmaps->map_pidx = 0;
3297 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE,
3301 for (i = 0; i < count; i++, txm++) {
3302 rc = bus_dmamap_create(tx_tag, 0, &txm->map);
3311 bus_dmamap_destroy(tx_tag, txm->map);
3313 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__));
3315 free(txmaps->maps, M_CXGBE);
3316 txmaps->maps = NULL;
3322 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag)
3328 for (i = 0; i < txmaps->map_total; i++, txm++) {
3331 bus_dmamap_unload(tx_tag, txm->map);
3336 bus_dmamap_destroy(tx_tag, txm->map);
3339 free(txmaps->maps, M_CXGBE);
3340 txmaps->maps = NULL;
3344 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're
3345 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes
3346 * of immediate data.
3350 - sizeof(struct fw_eth_tx_pkt_wr) \
3351 - sizeof(struct cpl_tx_pkt_core))
3354 * Returns non-zero on failure, no need to cleanup anything in that case.
3356 * Note 1: We always try to defrag the mbuf if required and return EFBIG only
3357 * if the resulting chain still won't fit in a tx descriptor.
3359 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf
3360 * does not have the TCP header in it.
3363 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl,
3366 struct mbuf *m = *fp;
3367 struct tx_maps *txmaps;
3369 int rc, defragged = 0, n;
3371 TXQ_LOCK_ASSERT_OWNED(txq);
3373 if (m->m_pkthdr.tso_segsz)
3374 sgl_only = 1; /* Do not allow immediate data with LSO */
3376 start: sgl->nsegs = 0;
3378 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only)
3379 return (0); /* nsegs = 0 tells caller to use imm. tx */
3381 txmaps = &txq->txmaps;
3382 if (txmaps->map_avail == 0) {
3386 txm = &txmaps->maps[txmaps->map_pidx];
3388 if (m->m_pkthdr.tso_segsz && m->m_len < 50) {
3389 *fp = m_pullup(m, 50);
3395 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg,
3396 &sgl->nsegs, BUS_DMA_NOWAIT);
3397 if (rc == EFBIG && defragged == 0) {
3398 m = m_defrag(m, M_NOWAIT);
3410 txmaps->map_avail--;
3411 if (++txmaps->map_pidx == txmaps->map_total)
3412 txmaps->map_pidx = 0;
3414 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS,
3415 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs));
3418 * Store the # of flits required to hold this frame's SGL in nflits. An
3419 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by
3420 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used
3421 * then len1 must be set to 0.
3424 sgl->nflits = (3 * n) / 2 + (n & 1) + 2;
3431 * Releases all the txq resources used up in the specified sgl.
3434 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl)
3436 struct tx_maps *txmaps;
3439 TXQ_LOCK_ASSERT_OWNED(txq);
3441 if (sgl->nsegs == 0)
3442 return (0); /* didn't use any map */
3444 txmaps = &txq->txmaps;
3446 /* 1 pkt uses exactly 1 map, back it out */
3448 txmaps->map_avail++;
3449 if (txmaps->map_pidx > 0)
3452 txmaps->map_pidx = txmaps->map_total - 1;
3454 txm = &txmaps->maps[txmaps->map_pidx];
3455 bus_dmamap_unload(txq->tx_tag, txm->map);
3462 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m,
3465 struct sge_eq *eq = &txq->eq;
3466 struct fw_eth_tx_pkt_wr *wr;
3467 struct cpl_tx_pkt_core *cpl;
3468 uint32_t ctrl; /* used in many unrelated places */
3470 int nflits, ndesc, pktlen;
3471 struct tx_sdesc *txsd;
3474 TXQ_LOCK_ASSERT_OWNED(txq);
3476 pktlen = m->m_pkthdr.len;
3479 * Do we have enough flits to send this frame out?
3481 ctrl = sizeof(struct cpl_tx_pkt_core);
3482 if (m->m_pkthdr.tso_segsz) {
3483 nflits = TXPKT_LSO_WR_HDR;
3484 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3486 nflits = TXPKT_WR_HDR;
3488 nflits += sgl->nflits;
3490 nflits += howmany(pktlen, 8);
3493 ndesc = howmany(nflits, 8);
3494 if (ndesc > eq->avail)
3497 /* Firmware work request header */
3498 wr = (void *)&eq->desc[eq->pidx];
3499 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3500 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3501 ctrl = V_FW_WR_LEN16(howmany(nflits, 2));
3502 if (eq->avail == ndesc) {
3503 if (!(eq->flags & EQ_CRFLUSHED)) {
3504 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3505 eq->flags |= EQ_CRFLUSHED;
3507 eq->flags |= EQ_STALLED;
3510 wr->equiq_to_len16 = htobe32(ctrl);
3513 if (m->m_pkthdr.tso_segsz) {
3514 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3515 struct ether_header *eh;
3517 #if defined(INET) || defined(INET6)
3522 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3525 eh = mtod(m, struct ether_header *);
3526 eh_type = ntohs(eh->ether_type);
3527 if (eh_type == ETHERTYPE_VLAN) {
3528 struct ether_vlan_header *evh = (void *)eh;
3530 ctrl |= V_LSO_ETHHDR_LEN(1);
3532 eh_type = ntohs(evh->evl_proto);
3538 case ETHERTYPE_IPV6:
3540 struct ip6_hdr *ip6 = l3hdr;
3543 * XXX-BZ For now we do not pretend to support
3544 * IPv6 extension headers.
3546 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO "
3547 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt));
3548 tcp = (struct tcphdr *)(ip6 + 1);
3550 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) |
3551 V_LSO_TCPHDR_LEN(tcp->th_off);
3558 struct ip *ip = l3hdr;
3560 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4);
3561 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) |
3562 V_LSO_TCPHDR_LEN(tcp->th_off);
3567 panic("%s: CSUM_TSO but no supported IP version "
3568 "(0x%04x)", __func__, eh_type);
3571 lso->lso_ctrl = htobe32(ctrl);
3572 lso->ipid_ofst = htobe16(0);
3573 lso->mss = htobe16(m->m_pkthdr.tso_segsz);
3574 lso->seqno_offset = htobe32(0);
3575 lso->len = htobe32(pktlen);
3577 cpl = (void *)(lso + 1);
3581 cpl = (void *)(wr + 1);
3583 /* Checksum offload */
3585 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3586 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3587 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3588 CSUM_TCP_IPV6 | CSUM_TSO)))
3589 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3590 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3591 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3592 txq->txcsum++; /* some hardware assistance provided */
3594 /* VLAN tag insertion */
3595 if (m->m_flags & M_VLANTAG) {
3596 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3597 txq->vlan_insertion++;
3601 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3602 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
3604 cpl->len = htobe16(pktlen);
3605 cpl->ctrl1 = htobe64(ctrl1);
3607 /* Software descriptor */
3608 txsd = &txq->sdesc[eq->pidx];
3609 txsd->desc_used = ndesc;
3611 eq->pending += ndesc;
3614 if (eq->pidx >= eq->cap)
3615 eq->pidx -= eq->cap;
3618 dst = (void *)(cpl + 1);
3619 if (sgl->nsegs > 0) {
3622 write_sgl_to_txd(eq, sgl, &dst);
3626 for (; m; m = m->m_next) {
3627 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3633 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3643 * Returns 0 to indicate that m has been accepted into a coalesced tx work
3644 * request. It has either been folded into txpkts or txpkts was flushed and m
3645 * has started a new coalesced work request (as the first frame in a fresh
3648 * Returns non-zero to indicate a failure - caller is responsible for
3649 * transmitting m, if there was anything in txpkts it has been flushed.
3652 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts,
3653 struct mbuf *m, struct sgl *sgl)
3655 struct sge_eq *eq = &txq->eq;
3657 struct tx_sdesc *txsd;
3660 TXQ_LOCK_ASSERT_OWNED(txq);
3662 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__));
3664 if (txpkts->npkt > 0) {
3665 flits = TXPKTS_PKT_HDR + sgl->nflits;
3666 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3667 txpkts->nflits + flits <= TX_WR_FLITS &&
3668 txpkts->nflits + flits <= eq->avail * 8 &&
3669 txpkts->plen + m->m_pkthdr.len < 65536;
3673 txpkts->nflits += flits;
3674 txpkts->plen += m->m_pkthdr.len;
3676 txsd = &txq->sdesc[eq->pidx];
3683 * Couldn't coalesce m into txpkts. The first order of business
3684 * is to send txpkts on its way. Then we'll revisit m.
3686 write_txpkts_wr(txq, txpkts);
3690 * Check if we can start a new coalesced tx work request with m as
3691 * the first packet in it.
3694 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__));
3696 flits = TXPKTS_WR_HDR + sgl->nflits;
3697 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3698 flits <= eq->avail * 8 && flits <= TX_WR_FLITS;
3700 if (can_coalesce == 0)
3704 * Start a fresh coalesced tx WR with m as the first frame in it.
3707 txpkts->nflits = flits;
3708 txpkts->flitp = &eq->desc[eq->pidx].flit[2];
3709 txpkts->plen = m->m_pkthdr.len;
3711 txsd = &txq->sdesc[eq->pidx];
3718 * Note that write_txpkts_wr can never run out of hardware descriptors (but
3719 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for
3720 * coalescing only if sufficient hardware descriptors are available.
3723 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts)
3725 struct sge_eq *eq = &txq->eq;
3726 struct fw_eth_tx_pkts_wr *wr;
3727 struct tx_sdesc *txsd;
3731 TXQ_LOCK_ASSERT_OWNED(txq);
3733 ndesc = howmany(txpkts->nflits, 8);
3735 wr = (void *)&eq->desc[eq->pidx];
3736 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
3737 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2));
3738 if (eq->avail == ndesc) {
3739 if (!(eq->flags & EQ_CRFLUSHED)) {
3740 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3741 eq->flags |= EQ_CRFLUSHED;
3743 eq->flags |= EQ_STALLED;
3745 wr->equiq_to_len16 = htobe32(ctrl);
3746 wr->plen = htobe16(txpkts->plen);
3747 wr->npkt = txpkts->npkt;
3748 wr->r3 = wr->type = 0;
3750 /* Everything else already written */
3752 txsd = &txq->sdesc[eq->pidx];
3753 txsd->desc_used = ndesc;
3755 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__));
3757 eq->pending += ndesc;
3760 if (eq->pidx >= eq->cap)
3761 eq->pidx -= eq->cap;
3763 txq->txpkts_pkts += txpkts->npkt;
3765 txpkts->npkt = 0; /* emptied */
3769 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq,
3770 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl)
3772 struct ulp_txpkt *ulpmc;
3773 struct ulptx_idata *ulpsc;
3774 struct cpl_tx_pkt_core *cpl;
3775 struct sge_eq *eq = &txq->eq;
3776 uintptr_t flitp, start, end;
3780 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__));
3782 start = (uintptr_t)eq->desc;
3783 end = (uintptr_t)eq->spg;
3785 /* Checksum offload */
3787 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3788 ctrl |= F_TXPKT_IPCSUM_DIS;
3789 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3790 CSUM_TCP_IPV6 | CSUM_TSO)))
3791 ctrl |= F_TXPKT_L4CSUM_DIS;
3792 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3793 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3794 txq->txcsum++; /* some hardware assistance provided */
3796 /* VLAN tag insertion */
3797 if (m->m_flags & M_VLANTAG) {
3798 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3799 txq->vlan_insertion++;
3803 * The previous packet's SGL must have ended at a 16 byte boundary (this
3804 * is required by the firmware/hardware). It follows that flitp cannot
3805 * wrap around between the ULPTX master command and ULPTX subcommand (8
3806 * bytes each), and that it can not wrap around in the middle of the
3807 * cpl_tx_pkt_core either.
3809 flitp = (uintptr_t)txpkts->flitp;
3810 KASSERT((flitp & 0xf) == 0,
3811 ("%s: last SGL did not end at 16 byte boundary: %p",
3812 __func__, txpkts->flitp));
3814 /* ULP master command */
3815 ulpmc = (void *)flitp;
3816 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) |
3817 V_ULP_TXPKT_FID(eq->iqid));
3818 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) +
3819 sizeof(*cpl) + 8 * sgl->nflits, 16));
3821 /* ULP subcommand */
3822 ulpsc = (void *)(ulpmc + 1);
3823 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) |
3825 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
3827 flitp += sizeof(*ulpmc) + sizeof(*ulpsc);
3832 cpl = (void *)flitp;
3833 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3834 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
3836 cpl->len = htobe16(m->m_pkthdr.len);
3837 cpl->ctrl1 = htobe64(ctrl);
3839 flitp += sizeof(*cpl);
3843 /* SGL for this frame */
3844 dst = (caddr_t)flitp;
3845 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst);
3846 txpkts->flitp = (void *)dst;
3848 KASSERT(((uintptr_t)dst & 0xf) == 0,
3849 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst));
3853 * If the SGL ends on an address that is not 16 byte aligned, this function will
3854 * add a 0 filled flit at the end. It returns 1 in that case.
3857 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to)
3859 __be64 *flitp, *end;
3860 struct ulptx_sgl *usgl;
3861 bus_dma_segment_t *seg;
3864 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0,
3865 ("%s: bad SGL - nsegs=%d, nflits=%d",
3866 __func__, sgl->nsegs, sgl->nflits));
3868 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
3869 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
3871 flitp = (__be64 *)(*to);
3872 end = flitp + sgl->nflits;
3874 usgl = (void *)flitp;
3877 * We start at a 16 byte boundary somewhere inside the tx descriptor
3878 * ring, so we're at least 16 bytes away from the status page. There is
3879 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
3882 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
3883 V_ULPTX_NSGE(sgl->nsegs));
3884 usgl->len0 = htobe32(seg->ds_len);
3885 usgl->addr0 = htobe64(seg->ds_addr);
3888 if ((uintptr_t)end <= (uintptr_t)eq->spg) {
3890 /* Won't wrap around at all */
3892 for (i = 0; i < sgl->nsegs - 1; i++, seg++) {
3893 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len);
3894 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr);
3897 usgl->sge[i / 2].len[1] = htobe32(0);
3900 /* Will wrap somewhere in the rest of the SGL */
3902 /* 2 flits already written, write the rest flit by flit */
3903 flitp = (void *)(usgl + 1);
3904 for (i = 0; i < sgl->nflits - 2; i++) {
3905 if ((uintptr_t)flitp == (uintptr_t)eq->spg)
3906 flitp = (void *)eq->desc;
3907 *flitp++ = get_flit(seg, sgl->nsegs - 1, i);
3912 if ((uintptr_t)end & 0xf) {
3913 *(uint64_t *)end = 0;
3919 if ((uintptr_t)end == (uintptr_t)eq->spg)
3920 *to = (void *)eq->desc;
3928 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
3930 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) {
3931 bcopy(from, *to, len);
3934 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to);
3936 bcopy(from, *to, portion);
3938 portion = len - portion; /* remaining */
3939 bcopy(from, (void *)eq->desc, portion);
3940 (*to) = (caddr_t)eq->desc + portion;
3945 ring_eq_db(struct adapter *sc, struct sge_eq *eq)
3950 pending = eq->pending;
3952 clrbit(&db, DOORBELL_WCWR);
3956 switch (ffs(db) - 1) {
3958 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
3961 case DOORBELL_WCWR: {
3962 volatile uint64_t *dst, *src;
3966 * Queues whose 128B doorbell segment fits in the page do not
3967 * use relative qid (udb_qid is always 0). Only queues with
3968 * doorbell segments can do WCWR.
3970 KASSERT(eq->udb_qid == 0 && pending == 1,
3971 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
3972 __func__, eq->doorbells, pending, eq->pidx, eq));
3974 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
3976 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1;
3977 src = (void *)&eq->desc[i];
3978 while (src != (void *)&eq->desc[i + 1])
3984 case DOORBELL_UDBWC:
3985 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
3990 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
3991 V_QID(eq->cntxt_id) | V_PIDX(pending));
3997 reclaimable(struct sge_eq *eq)
4001 cidx = eq->spg->cidx; /* stable snapshot */
4002 cidx = be16toh(cidx);
4004 if (cidx >= eq->cidx)
4005 return (cidx - eq->cidx);
4007 return (cidx + eq->cap - eq->cidx);
4011 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as
4012 * many as possible but stop when there are around "n" mbufs to free.
4014 * The actual number reclaimed is provided as the return value.
4017 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
4019 struct tx_sdesc *txsd;
4020 struct tx_maps *txmaps;
4022 unsigned int reclaimed, maps;
4023 struct sge_eq *eq = &txq->eq;
4025 TXQ_LOCK_ASSERT_OWNED(txq);
4027 if (can_reclaim == 0)
4028 can_reclaim = reclaimable(eq);
4030 maps = reclaimed = 0;
4031 while (can_reclaim && maps < n) {
4034 txsd = &txq->sdesc[eq->cidx];
4035 ndesc = txsd->desc_used;
4037 /* Firmware doesn't return "partial" credits. */
4038 KASSERT(can_reclaim >= ndesc,
4039 ("%s: unexpected number of credits: %d, %d",
4040 __func__, can_reclaim, ndesc));
4042 maps += txsd->credits;
4045 can_reclaim -= ndesc;
4048 if (__predict_false(eq->cidx >= eq->cap))
4049 eq->cidx -= eq->cap;
4052 txmaps = &txq->txmaps;
4053 txm = &txmaps->maps[txmaps->map_cidx];
4057 eq->avail += reclaimed;
4058 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */
4059 ("%s: too many descriptors available", __func__));
4061 txmaps->map_avail += maps;
4062 KASSERT(txmaps->map_avail <= txmaps->map_total,
4063 ("%s: too many maps available", __func__));
4066 struct tx_map *next;
4069 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total))
4070 next = txmaps->maps;
4073 bus_dmamap_unload(txq->tx_tag, txm->map);
4078 if (__predict_false(++txmaps->map_cidx == txmaps->map_total))
4079 txmaps->map_cidx = 0;
4086 write_eqflush_wr(struct sge_eq *eq)
4088 struct fw_eq_flush_wr *wr;
4090 EQ_LOCK_ASSERT_OWNED(eq);
4091 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__));
4092 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__));
4094 wr = (void *)&eq->desc[eq->pidx];
4095 bzero(wr, sizeof(*wr));
4096 wr->opcode = FW_EQ_FLUSH_WR;
4097 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) |
4098 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
4100 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED);
4103 if (++eq->pidx == eq->cap)
4108 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx)
4110 int i = (idx / 3) * 2;
4116 rc = htobe32(sgl[i].ds_len);
4118 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32;
4123 return htobe64(sgl[i].ds_addr);
4125 return htobe64(sgl[i + 1].ds_addr);
4132 * Find an SGE FL buffer size to use for the given bufsize. Look for the the
4133 * smallest size that is large enough to hold bufsize or pick the largest size
4134 * if all sizes are less than bufsize.
4137 set_fl_tag_idx(struct adapter *sc, struct sge_fl *fl, int bufsize)
4139 int i, largest, best, delta, start;
4141 if (fl->flags & FL_BUF_PACKING) {
4142 fl->tag_idx = 0; /* first tag is the one for packing */
4146 start = sc->flags & BUF_PACKING_OK ? 1 : 0;
4147 delta = FL_BUF_SIZE(sc, start) - bufsize;
4149 fl->tag_idx = start; /* ideal fit, look no further */
4155 for (i = start + 1; i < FL_BUF_SIZES(sc); i++) {
4158 fl_buf_size = FL_BUF_SIZE(sc, i);
4159 d = fl_buf_size - bufsize;
4162 fl->tag_idx = i; /* ideal fit, look no further */
4165 if (fl_buf_size > FL_BUF_SIZE(sc, largest))
4167 if (d > 0 && (delta < 0 || delta > d)) {
4174 fl->tag_idx = best; /* Found a buf bigger than bufsize */
4176 fl->tag_idx = largest; /* No buf large enough for bufsize */
4180 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4182 mtx_lock(&sc->sfl_lock);
4184 if ((fl->flags & FL_DOOMED) == 0) {
4185 fl->flags |= FL_STARVING;
4186 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4187 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4190 mtx_unlock(&sc->sfl_lock);
4194 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4197 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4198 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4199 struct adapter *sc = iq->adapter;
4200 struct sge *s = &sc->sge;
4203 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4206 eq = s->eqmap[qid - s->eq_start];
4208 KASSERT(eq->flags & EQ_CRFLUSHED,
4209 ("%s: unsolicited egress update", __func__));
4210 eq->flags &= ~EQ_CRFLUSHED;
4213 if (__predict_false(eq->flags & EQ_DOOMED))
4215 else if (eq->flags & EQ_STALLED && can_resume_tx(eq))
4216 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
4222 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4223 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4224 offsetof(struct cpl_fw6_msg, data));
4227 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4229 struct adapter *sc = iq->adapter;
4230 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4232 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4235 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4236 const struct rss_header *rss2;
4238 rss2 = (const struct rss_header *)&cpl->data[0];
4239 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4242 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4246 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4248 uint16_t *id = arg1;
4251 return sysctl_handle_int(oidp, &i, 0, req);