2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
32 #include "opt_inet6.h"
33 #include "opt_kern_tls.h"
34 #include "opt_ratelimit.h"
36 #include <sys/types.h>
37 #include <sys/eventhandler.h>
39 #include <sys/socket.h>
40 #include <sys/kernel.h>
42 #include <sys/malloc.h>
44 #include <sys/queue.h>
46 #include <sys/taskqueue.h>
48 #include <sys/sglist.h>
49 #include <sys/sysctl.h>
51 #include <sys/socketvar.h>
52 #include <sys/counter.h>
54 #include <net/ethernet.h>
56 #include <net/if_vlan_var.h>
57 #include <net/if_vxlan.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/ip6.h>
61 #include <netinet/tcp.h>
62 #include <netinet/udp.h>
63 #include <machine/in_cksum.h>
64 #include <machine/md_var.h>
68 #include <machine/bus.h>
69 #include <sys/selinfo.h>
70 #include <net/if_var.h>
71 #include <net/netmap.h>
72 #include <dev/netmap/netmap_kern.h>
75 #include "common/common.h"
76 #include "common/t4_regs.h"
77 #include "common/t4_regs_values.h"
78 #include "common/t4_msg.h"
80 #include "t4_mp_ring.h"
82 #define RX_COPY_THRESHOLD MINCLSIZE
85 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
86 * 0-7 are valid values.
88 static int fl_pktshift = 0;
89 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
90 "payload DMA offset in rx buffer (bytes)");
93 * Pad ethernet payload up to this boundary.
94 * -1: driver should figure out a good value.
96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
100 "payload pad boundary (bytes)");
103 * Status page length.
104 * -1: driver should figure out a good value.
105 * 64 or 128 are the only other valid values.
107 static int spg_len = -1;
108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
109 "status page size (bytes)");
113 * -1: no congestion feedback (not recommended).
114 * 0: backpressure the channel instead of dropping packets right away.
115 * 1: no backpressure, drop packets for the congested queue immediately.
116 * 2: both backpressure and drop.
118 static int cong_drop = 0;
119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
120 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both");
122 static int ofld_cong_drop = 0;
123 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0,
124 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both");
128 * Deliver multiple frames in the same free list buffer if they fit.
129 * -1: let the driver decide whether to enable buffer packing or not.
130 * 0: disable buffer packing.
131 * 1: enable buffer packing.
133 static int buffer_packing = -1;
134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
135 0, "Enable buffer packing");
138 * Start next frame in a packed buffer at this boundary.
139 * -1: driver should figure out a good value.
140 * T4: driver will ignore this and use the same value as fl_pad above.
141 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
143 static int fl_pack = -1;
144 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
145 "payload pack boundary (bytes)");
148 * Largest rx cluster size that the driver is allowed to allocate.
150 static int largest_rx_cluster = MJUM16BYTES;
151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
152 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
155 * Size of cluster allocation that's most likely to succeed. The driver will
156 * fall back to this size if it fails to allocate clusters larger than this.
158 static int safest_rx_cluster = PAGE_SIZE;
159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
160 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
164 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
165 * for rewriting. -1 and 0-3 are all valid values.
166 * -1: hardware should leave the TCP timestamps alone.
172 static int tsclk = -1;
173 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
174 "Control TCP timestamp rewriting when using pacing");
176 static int eo_max_backlog = 1024 * 1024;
177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
178 0, "Maximum backlog of ratelimited data per flow");
182 * The interrupt holdoff timers are multiplied by this value on T6+.
183 * 1 and 3-17 (both inclusive) are legal values.
185 static int tscale = 1;
186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
187 "Interrupt holdoff timer scale on T6+");
190 * Number of LRO entries in the lro_ctrl structure per rx queue.
192 static int lro_entries = TCP_LRO_ENTRIES;
193 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
194 "Number of LRO entries per RX queue");
197 * This enables presorting of frames before they're fed into tcp_lro_rx.
199 static int lro_mbufs = 0;
200 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
201 "Enable presorting of LRO frames");
203 static counter_u64_t pullups;
204 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
205 "Number of mbuf pullups performed");
207 static counter_u64_t defrags;
208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
209 "Number of mbuf defrags performed");
211 static int t4_tx_coalesce = 1;
212 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
213 "tx coalescing allowed");
216 * The driver will make aggressive attempts at tx coalescing if it sees these
217 * many packets eligible for coalescing in quick succession, with no more than
218 * the specified gap in between the eth_tx calls that delivered the packets.
220 static int t4_tx_coalesce_pkts = 32;
221 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
222 &t4_tx_coalesce_pkts, 0,
223 "# of consecutive packets (1 - 255) that will trigger tx coalescing");
224 static int t4_tx_coalesce_gap = 5;
225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
226 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
228 static int service_iq(struct sge_iq *, int);
229 static int service_iq_fl(struct sge_iq *, int);
230 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
231 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
233 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
235 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
236 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
237 struct sge_iq *, char *);
238 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
239 struct sysctl_ctx_list *, struct sysctl_oid *);
240 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
241 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
243 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
244 struct sysctl_oid *, struct sge_fl *);
245 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *);
246 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *);
247 static int alloc_fwq(struct adapter *);
248 static void free_fwq(struct adapter *);
249 static int alloc_ctrlq(struct adapter *, int);
250 static void free_ctrlq(struct adapter *, int);
251 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int);
252 static void free_rxq(struct vi_info *, struct sge_rxq *);
253 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
258 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
259 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
260 struct sge_ofld_rxq *);
262 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
263 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
264 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
265 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
267 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
268 struct sysctl_oid *);
269 static void free_eq(struct adapter *, struct sge_eq *);
270 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
271 struct sysctl_oid *, struct sge_eq *);
272 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
273 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
274 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
275 struct sysctl_ctx_list *, struct sysctl_oid *);
276 static void free_wrq(struct adapter *, struct sge_wrq *);
277 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
279 static int alloc_txq(struct vi_info *, struct sge_txq *, int);
280 static void free_txq(struct vi_info *, struct sge_txq *);
281 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *,
282 struct sysctl_oid *, struct sge_txq *);
283 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
284 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int);
285 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *);
286 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
287 struct sge_ofld_txq *);
289 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
290 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
291 static int refill_fl(struct adapter *, struct sge_fl *, int);
292 static void refill_sfl(void *);
293 static int find_refill_source(struct adapter *, int, bool);
294 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
296 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
297 static inline u_int txpkt_len16(u_int, const u_int);
298 static inline u_int txpkt_vm_len16(u_int, const u_int);
299 static inline void calculate_mbuf_len16(struct mbuf *, bool);
300 static inline u_int txpkts0_len16(u_int);
301 static inline u_int txpkts1_len16(void);
302 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
303 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
305 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
307 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
309 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
311 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
312 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
313 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
314 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
315 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
316 static inline uint16_t read_hw_cidx(struct sge_eq *);
317 static inline u_int reclaimable_tx_desc(struct sge_eq *);
318 static inline u_int total_available_tx_desc(struct sge_eq *);
319 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
320 static void tx_reclaim(void *, int);
321 static __be64 get_flit(struct sglist_seg *, int, int);
322 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
324 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
326 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
327 static void wrq_tx_drain(void *, int);
328 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
330 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
332 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
334 #if defined(INET) || defined(INET6)
335 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
336 static int ethofld_transmit(if_t, struct mbuf *);
340 static counter_u64_t extfree_refs;
341 static counter_u64_t extfree_rels;
343 an_handler_t t4_an_handler;
344 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
345 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
346 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
347 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
348 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
349 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
350 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
353 t4_register_an_handler(an_handler_t h)
357 MPASS(h == NULL || t4_an_handler == NULL);
359 loc = (uintptr_t *)&t4_an_handler;
360 atomic_store_rel_ptr(loc, (uintptr_t)h);
364 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
368 MPASS(type < nitems(t4_fw_msg_handler));
369 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
371 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
372 * handler dispatch table. Reject any attempt to install a handler for
375 MPASS(type != FW_TYPE_RSSCPL);
376 MPASS(type != FW6_TYPE_RSSCPL);
378 loc = (uintptr_t *)&t4_fw_msg_handler[type];
379 atomic_store_rel_ptr(loc, (uintptr_t)h);
383 t4_register_cpl_handler(int opcode, cpl_handler_t h)
387 MPASS(opcode < nitems(t4_cpl_handler));
388 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
390 loc = (uintptr_t *)&t4_cpl_handler[opcode];
391 atomic_store_rel_ptr(loc, (uintptr_t)h);
395 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
398 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
405 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
407 * The return code for filter-write is put in the CPL cookie so
408 * we have to rely on the hardware tid (is_ftid) to determine
409 * that this is a response to a filter.
411 cookie = CPL_COOKIE_FILTER;
413 cookie = G_COOKIE(cpl->cookie);
415 MPASS(cookie > CPL_COOKIE_RESERVED);
416 MPASS(cookie < nitems(set_tcb_rpl_handlers));
418 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
422 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
425 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
430 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
431 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
435 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
438 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
439 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
442 MPASS(cookie != CPL_COOKIE_RESERVED);
444 return (act_open_rpl_handlers[cookie](iq, rss, m));
448 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
451 struct adapter *sc = iq->adapter;
455 if (is_hashfilter(sc))
456 cookie = CPL_COOKIE_HASHFILTER;
458 cookie = CPL_COOKIE_TOM;
460 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
464 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
466 struct adapter *sc = iq->adapter;
467 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
468 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
472 if (is_etid(sc, tid))
473 cookie = CPL_COOKIE_ETHOFLD;
475 cookie = CPL_COOKIE_TOM;
477 return (fw4_ack_handlers[cookie](iq, rss, m));
481 t4_init_shared_cpl_handlers(void)
484 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
485 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
486 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
487 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
488 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
492 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
496 MPASS(opcode < nitems(t4_cpl_handler));
497 MPASS(cookie > CPL_COOKIE_RESERVED);
498 MPASS(cookie < NUM_CPL_COOKIES);
499 MPASS(t4_cpl_handler[opcode] != NULL);
502 case CPL_SET_TCB_RPL:
503 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
505 case CPL_L2T_WRITE_RPL:
506 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
508 case CPL_ACT_OPEN_RPL:
509 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
511 case CPL_ABORT_RPL_RSS:
512 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
515 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
521 MPASS(h == NULL || *loc == (uintptr_t)NULL);
522 atomic_store_rel_ptr(loc, (uintptr_t)h);
526 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
532 if (fl_pktshift < 0 || fl_pktshift > 7) {
533 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
534 " using 0 instead.\n", fl_pktshift);
538 if (spg_len != 64 && spg_len != 128) {
541 #if defined(__i386__) || defined(__amd64__)
542 len = cpu_clflush_line_size > 64 ? 128 : 64;
547 printf("Invalid hw.cxgbe.spg_len value (%d),"
548 " using %d instead.\n", spg_len, len);
553 if (cong_drop < -1 || cong_drop > 2) {
554 printf("Invalid hw.cxgbe.cong_drop value (%d),"
555 " using 0 instead.\n", cong_drop);
559 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) {
560 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d),"
561 " using 0 instead.\n", ofld_cong_drop);
566 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
567 printf("Invalid hw.cxgbe.tscale value (%d),"
568 " using 1 instead.\n", tscale);
572 if (largest_rx_cluster != MCLBYTES &&
573 largest_rx_cluster != MJUMPAGESIZE &&
574 largest_rx_cluster != MJUM9BYTES &&
575 largest_rx_cluster != MJUM16BYTES) {
576 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
577 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
578 largest_rx_cluster = MJUM16BYTES;
581 if (safest_rx_cluster != MCLBYTES &&
582 safest_rx_cluster != MJUMPAGESIZE &&
583 safest_rx_cluster != MJUM9BYTES &&
584 safest_rx_cluster != MJUM16BYTES) {
585 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
586 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
587 safest_rx_cluster = MJUMPAGESIZE;
590 extfree_refs = counter_u64_alloc(M_WAITOK);
591 extfree_rels = counter_u64_alloc(M_WAITOK);
592 pullups = counter_u64_alloc(M_WAITOK);
593 defrags = counter_u64_alloc(M_WAITOK);
594 counter_u64_zero(extfree_refs);
595 counter_u64_zero(extfree_rels);
596 counter_u64_zero(pullups);
597 counter_u64_zero(defrags);
599 t4_init_shared_cpl_handlers();
600 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
601 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
602 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
604 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
607 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
608 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
612 t4_sge_modunload(void)
615 counter_u64_free(extfree_refs);
616 counter_u64_free(extfree_rels);
617 counter_u64_free(pullups);
618 counter_u64_free(defrags);
622 t4_sge_extfree_refs(void)
626 rels = counter_u64_fetch(extfree_rels);
627 refs = counter_u64_fetch(extfree_refs);
629 return (refs - rels);
633 #define MAX_PACK_BOUNDARY 512
636 setup_pad_and_pack_boundaries(struct adapter *sc)
639 int pad, pack, pad_shift;
641 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
642 X_INGPADBOUNDARY_SHIFT;
644 if (fl_pad < (1 << pad_shift) ||
645 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
648 * If there is any chance that we might use buffer packing and
649 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
650 * it to the minimum allowed in all other cases.
652 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
655 * For fl_pad = 0 we'll still write a reasonable value to the
656 * register but all the freelists will opt out of padding.
657 * We'll complain here only if the user tried to set it to a
658 * value greater than 0 that was invalid.
661 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
662 " (%d), using %d instead.\n", fl_pad, pad);
665 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
666 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
667 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
670 if (fl_pack != -1 && fl_pack != pad) {
671 /* Complain but carry on. */
672 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
673 " using %d instead.\n", fl_pack, pad);
679 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
680 !powerof2(fl_pack)) {
681 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
682 pack = MAX_PACK_BOUNDARY;
684 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
685 MPASS(powerof2(pack));
693 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
694 " (%d), using %d instead.\n", fl_pack, pack);
697 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
699 v = V_INGPACKBOUNDARY(0);
701 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
703 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
704 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
708 * adap->params.vpd.cclk must be set up before this is called.
711 t4_tweak_chip_settings(struct adapter *sc)
715 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
716 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
717 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
718 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
719 static int sw_buf_sizes[] = {
726 KASSERT(sc->flags & MASTER_PF,
727 ("%s: trying to change chip settings when not master.", __func__));
729 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
730 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
731 V_EGRSTATUSPAGESIZE(spg_len == 128);
732 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
734 setup_pad_and_pack_boundaries(sc);
736 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
737 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
738 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
739 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
740 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
741 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
742 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
743 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
744 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
746 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
747 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
748 reg = A_SGE_FL_BUFFER_SIZE2;
749 for (i = 0; i < nitems(sw_buf_sizes); i++) {
750 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
751 t4_write_reg(sc, reg, sw_buf_sizes[i]);
753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
754 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
758 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
759 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
760 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
762 KASSERT(intr_timer[0] <= timer_max,
763 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
765 for (i = 1; i < nitems(intr_timer); i++) {
766 KASSERT(intr_timer[i] >= intr_timer[i - 1],
767 ("%s: timers not listed in increasing order (%d)",
770 while (intr_timer[i] > timer_max) {
771 if (i == nitems(intr_timer) - 1) {
772 intr_timer[i] = timer_max;
775 intr_timer[i] += intr_timer[i - 1];
780 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
781 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
782 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
783 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
784 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
785 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
786 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
787 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
788 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
790 if (chip_id(sc) >= CHELSIO_T6) {
791 m = V_TSCALE(M_TSCALE);
795 v = V_TSCALE(tscale - 2);
796 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
798 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
799 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
800 V_WRTHRTHRESH(M_WRTHRTHRESH);
801 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
803 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
805 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
809 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
810 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
811 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
814 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
815 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
816 * may have to deal with is MAXPHYS + 1 page.
818 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
819 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
821 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
822 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
823 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
825 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
827 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
828 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
832 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its
833 * address mut be 16B aligned. If padding is in use the buffer's start and end
834 * need to be aligned to the pad boundary as well. We'll just make sure that
835 * the size is a multiple of the pad boundary here, it is up to the buffer
836 * allocation code to make sure the start of the buffer is aligned.
839 hwsz_ok(struct adapter *sc, int hwsz)
841 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
843 return (hwsz >= 64 && (hwsz & mask) == 0);
847 * Initialize the rx buffer sizes and figure out which zones the buffers will
851 t4_init_rx_buf_info(struct adapter *sc)
853 struct sge *s = &sc->sge;
854 struct sge_params *sp = &sc->params.sge;
856 static int sw_buf_sizes[] = { /* Sorted by size */
862 struct rx_buf_info *rxb;
865 rxb = &s->rx_buf_info[0];
866 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
867 rxb->size1 = sw_buf_sizes[i];
868 rxb->zone = m_getzone(rxb->size1);
869 rxb->type = m_gettype(rxb->size1);
873 for (j = 0; j < SGE_FLBUF_SIZES; j++) {
874 int hwsize = sp->sge_fl_buffer_size[j];
876 if (!hwsz_ok(sc, hwsize))
879 /* hwidx for size1 */
880 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
883 /* hwidx for size2 (buffer packing) */
884 if (rxb->size1 - CL_METADATA_SIZE < hwsize)
886 n = rxb->size1 - hwsize - CL_METADATA_SIZE;
890 break; /* stop looking */
892 if (rxb->hwidx2 != -1) {
893 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
894 hwsize - CL_METADATA_SIZE) {
898 } else if (n <= 2 * CL_METADATA_SIZE) {
903 if (rxb->hwidx2 != -1)
904 sc->flags |= BUF_PACKING_OK;
905 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
911 * Verify some basic SGE settings for the PF and VF driver, and other
912 * miscellaneous settings for the PF driver.
915 t4_verify_chip_settings(struct adapter *sc)
917 struct sge_params *sp = &sc->params.sge;
920 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
926 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
931 * If this changes then every single use of PAGE_SHIFT in the driver
932 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
934 if (sp->page_shift != PAGE_SHIFT) {
935 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
939 if (sc->flags & IS_VF)
942 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
943 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
945 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
946 if (sc->vres.ddp.size != 0)
950 m = v = F_TDDPTAGTCB;
951 r = t4_read_reg(sc, A_ULP_RX_CTL);
953 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
954 if (sc->vres.ddp.size != 0)
958 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
960 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
961 r = t4_read_reg(sc, A_TP_PARA_REG5);
963 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
964 if (sc->vres.ddp.size != 0)
972 t4_create_dma_tag(struct adapter *sc)
976 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
978 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
981 device_printf(sc->dev,
982 "failed to create main DMA tag: %d\n", rc);
989 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
990 struct sysctl_oid_list *children)
992 struct sge_params *sp = &sc->params.sge;
994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
996 sysctl_bufsizes, "A", "freelist buffer sizes");
998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
999 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1002 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1004 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1005 NULL, sp->spg_len, "status page size (bytes)");
1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1008 NULL, cong_drop, "congestion drop setting");
1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD,
1011 NULL, ofld_cong_drop, "congestion drop setting");
1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1015 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1019 t4_destroy_dma_tag(struct adapter *sc)
1022 bus_dma_tag_destroy(sc->dmat);
1028 * Allocate and initialize the firmware event queue, control queues, and special
1029 * purpose rx queues owned by the adapter.
1031 * Returns errno on failure. Resources allocated up to that point may still be
1032 * allocated. Caller is responsible for cleanup in case this function fails.
1035 t4_setup_adapter_queues(struct adapter *sc)
1039 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1042 * Firmware event queue
1049 * That's all for the VF driver.
1051 if (sc->flags & IS_VF)
1055 * XXX: General purpose rx queues, one per port.
1059 * Control queues, one per port.
1061 for_each_port(sc, i) {
1062 rc = alloc_ctrlq(sc, i);
1074 t4_teardown_adapter_queues(struct adapter *sc)
1078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1080 if (sc->sge.ctrlq != NULL) {
1081 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */
1082 for_each_port(sc, i)
1090 /* Maximum payload that could arrive with a single iq descriptor. */
1092 max_rx_payload(struct adapter *sc, if_t ifp, const bool ofld)
1096 /* large enough even when hw VLAN extraction is disabled */
1097 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1098 ETHER_VLAN_ENCAP_LEN + if_getmtu(ifp);
1099 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1100 maxp < sc->params.tp.max_rx_pdu)
1101 maxp = sc->params.tp.max_rx_pdu;
1106 t4_setup_vi_queues(struct vi_info *vi)
1108 int rc = 0, i, intr_idx;
1109 struct sge_rxq *rxq;
1110 struct sge_txq *txq;
1112 struct sge_ofld_rxq *ofld_rxq;
1114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1115 struct sge_ofld_txq *ofld_txq;
1118 int saved_idx, iqidx;
1119 struct sge_nm_rxq *nm_rxq;
1120 struct sge_nm_txq *nm_txq;
1122 struct adapter *sc = vi->adapter;
1126 /* Interrupt vector to start from (when using multiple vectors) */
1127 intr_idx = vi->first_intr;
1130 saved_idx = intr_idx;
1131 if (if_getcapabilities(ifp) & IFCAP_NETMAP) {
1133 /* netmap is supported with direct interrupts only. */
1134 MPASS(!forwarding_intr_to_fwq(sc));
1135 MPASS(vi->first_intr >= 0);
1138 * We don't have buffers to back the netmap rx queues
1139 * right now so we create the queues in a way that
1140 * doesn't set off any congestion signal in the chip.
1142 for_each_nm_rxq(vi, i, nm_rxq) {
1143 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i);
1149 for_each_nm_txq(vi, i, nm_txq) {
1150 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1151 rc = alloc_nm_txq(vi, nm_txq, iqidx, i);
1157 /* Normal rx queues and netmap rx queues share the same interrupts. */
1158 intr_idx = saved_idx;
1162 * Allocate rx queues first because a default iqid is required when
1163 * creating a tx queue.
1165 maxp = max_rx_payload(sc, ifp, false);
1166 for_each_rxq(vi, i, rxq) {
1167 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp);
1170 if (!forwarding_intr_to_fwq(sc))
1174 if (if_getcapabilities(ifp) & IFCAP_NETMAP)
1175 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1178 maxp = max_rx_payload(sc, ifp, true);
1179 for_each_ofld_rxq(vi, i, ofld_rxq) {
1180 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp);
1183 if (!forwarding_intr_to_fwq(sc))
1189 * Now the tx queues.
1191 for_each_txq(vi, i, txq) {
1192 rc = alloc_txq(vi, txq, i);
1196 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1197 for_each_ofld_txq(vi, i, ofld_txq) {
1198 rc = alloc_ofld_txq(vi, ofld_txq, i);
1205 t4_teardown_vi_queues(vi);
1214 t4_teardown_vi_queues(struct vi_info *vi)
1217 struct sge_rxq *rxq;
1218 struct sge_txq *txq;
1219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1220 struct sge_ofld_txq *ofld_txq;
1223 struct sge_ofld_rxq *ofld_rxq;
1226 struct sge_nm_rxq *nm_rxq;
1227 struct sge_nm_txq *nm_txq;
1231 if (if_getcapabilities(vi->ifp) & IFCAP_NETMAP) {
1232 for_each_nm_txq(vi, i, nm_txq) {
1233 free_nm_txq(vi, nm_txq);
1236 for_each_nm_rxq(vi, i, nm_rxq) {
1237 free_nm_rxq(vi, nm_rxq);
1243 * Take down all the tx queues first, as they reference the rx queues
1244 * (for egress updates, etc.).
1247 for_each_txq(vi, i, txq) {
1250 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1251 for_each_ofld_txq(vi, i, ofld_txq) {
1252 free_ofld_txq(vi, ofld_txq);
1257 * Then take down the rx queues.
1260 for_each_rxq(vi, i, rxq) {
1264 for_each_ofld_rxq(vi, i, ofld_rxq) {
1265 free_ofld_rxq(vi, ofld_rxq);
1273 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1276 * a) Deals with errors, if any.
1277 * b) Services firmware event queue, which is taking interrupts for all other
1281 t4_intr_all(void *arg)
1283 struct adapter *sc = arg;
1284 struct sge_iq *fwq = &sc->sge.fwq;
1286 MPASS(sc->intr_count == 1);
1288 if (sc->intr_type == INTR_INTX)
1289 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1296 * Interrupt handler for errors (installed directly when multiple interrupts are
1297 * being used, or called by t4_intr_all).
1300 t4_intr_err(void *arg)
1302 struct adapter *sc = arg;
1304 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1306 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR)
1309 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1312 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1315 if (t4_slow_intr_handler(sc, verbose))
1316 t4_fatal_err(sc, false);
1320 * Interrupt handler for iq-only queues. The firmware event queue is the only
1321 * such queue right now.
1324 t4_intr_evt(void *arg)
1326 struct sge_iq *iq = arg;
1328 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1330 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1335 * Interrupt handler for iq+fl queues.
1340 struct sge_iq *iq = arg;
1342 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1343 service_iq_fl(iq, 0);
1344 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1350 * Interrupt handler for netmap rx queues.
1353 t4_nm_intr(void *arg)
1355 struct sge_nm_rxq *nm_rxq = arg;
1357 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1358 service_nm_rxq(nm_rxq);
1359 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1364 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1367 t4_vi_intr(void *arg)
1369 struct irq *irq = arg;
1371 MPASS(irq->nm_rxq != NULL);
1372 t4_nm_intr(irq->nm_rxq);
1374 MPASS(irq->rxq != NULL);
1380 * Deals with interrupts on an iq-only (no freelist) queue.
1383 service_iq(struct sge_iq *iq, int budget)
1386 struct adapter *sc = iq->adapter;
1387 struct iq_desc *d = &iq->desc[iq->cidx];
1388 int ndescs = 0, limit;
1391 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1393 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1394 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1395 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1397 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1398 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1400 limit = budget ? budget : iq->qsize / 16;
1403 * We always come back and check the descriptor ring for new indirect
1404 * interrupts and other responses after running a single handler.
1407 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1411 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1412 lq = be32toh(d->rsp.pldbuflen_qid);
1415 case X_RSPD_TYPE_FLBUF:
1416 panic("%s: data for an iq (%p) with no freelist",
1421 case X_RSPD_TYPE_CPL:
1422 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1423 ("%s: bad opcode %02x.", __func__,
1425 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1428 case X_RSPD_TYPE_INTR:
1430 * There are 1K interrupt-capable queues (qids 0
1431 * through 1023). A response type indicating a
1432 * forwarded interrupt with a qid >= 1K is an
1433 * iWARP async notification.
1435 if (__predict_true(lq >= 1024)) {
1436 t4_an_handler(iq, &d->rsp);
1440 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1442 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1444 if (service_iq_fl(q, q->qsize / 16) == 0) {
1445 (void) atomic_cmpset_int(&q->state,
1446 IQS_BUSY, IQS_IDLE);
1448 STAILQ_INSERT_TAIL(&iql, q,
1456 ("%s: illegal response type %d on iq %p",
1457 __func__, rsp_type, iq));
1459 "%s: illegal response type %d on iq %p",
1460 device_get_nameunit(sc->dev), rsp_type, iq);
1465 if (__predict_false(++iq->cidx == iq->sidx)) {
1467 iq->gen ^= F_RSPD_GEN;
1470 if (__predict_false(++ndescs == limit)) {
1471 t4_write_reg(sc, sc->sge_gts_reg,
1473 V_INGRESSQID(iq->cntxt_id) |
1474 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1478 return (EINPROGRESS);
1483 if (STAILQ_EMPTY(&iql))
1487 * Process the head only, and send it to the back of the list if
1488 * it's still not done.
1490 q = STAILQ_FIRST(&iql);
1491 STAILQ_REMOVE_HEAD(&iql, link);
1492 if (service_iq_fl(q, q->qsize / 8) == 0)
1493 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1495 STAILQ_INSERT_TAIL(&iql, q, link);
1498 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1499 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1504 #if defined(INET) || defined(INET6)
1506 sort_before_lro(struct lro_ctrl *lro)
1509 return (lro->lro_mbuf_max != 0);
1513 #define CGBE_SHIFT_SCALE 10
1515 static inline uint64_t
1516 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf)
1518 struct clock_sync *cur, dcur;
1520 uint64_t hw_clk_div;
1521 sbintime_t sbt_cur_to_prev, sbt;
1522 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */
1526 cur = &sc->cal_info[sc->cal_current];
1527 gen = seqc_read(&cur->gen);
1531 if (seqc_consistent(&cur->gen, gen))
1536 * Our goal here is to have a result that is:
1538 * ( (cur_time - prev_time) )
1539 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time
1540 * ( (hw_cur - hw_prev) )
1542 * With the constraints that we cannot use float and we
1543 * don't want to overflow the uint64_t numbers we are using.
1545 hw_clocks = hw_tstmp - dcur.hw_prev;
1546 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev);
1547 hw_clk_div = dcur.hw_cur - dcur.hw_prev;
1548 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev;
1549 return (sbttons(sbt));
1553 move_to_next_rxbuf(struct sge_fl *fl)
1557 if (__predict_false((++fl->cidx & 7) == 0)) {
1558 uint16_t cidx = fl->cidx >> 3;
1560 if (__predict_false(cidx == fl->sidx))
1561 fl->cidx = cidx = 0;
1567 * Deals with interrupts on an iq+fl queue.
1570 service_iq_fl(struct sge_iq *iq, int budget)
1572 struct sge_rxq *rxq = iq_to_rxq(iq);
1574 struct adapter *sc = iq->adapter;
1575 struct iq_desc *d = &iq->desc[iq->cidx];
1577 int rsp_type, starved;
1579 uint16_t fl_hw_cidx;
1581 #if defined(INET) || defined(INET6)
1582 const struct timeval lro_timeout = {0, sc->lro_timeout};
1583 struct lro_ctrl *lro = &rxq->lro;
1586 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1587 MPASS(iq->flags & IQ_HAS_FL);
1590 #if defined(INET) || defined(INET6)
1591 if (iq->flags & IQ_ADJ_CREDIT) {
1592 MPASS(sort_before_lro(lro));
1593 iq->flags &= ~IQ_ADJ_CREDIT;
1594 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1595 tcp_lro_flush_all(lro);
1596 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1597 V_INGRESSQID((u32)iq->cntxt_id) |
1598 V_SEINTARM(iq->intr_params));
1604 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1607 limit = budget ? budget : iq->qsize / 16;
1609 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1610 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1615 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1616 lq = be32toh(d->rsp.pldbuflen_qid);
1619 case X_RSPD_TYPE_FLBUF:
1620 if (lq & F_RSPD_NEWBUF) {
1621 if (fl->rx_offset > 0)
1622 move_to_next_rxbuf(fl);
1623 lq = G_RSPD_LEN(lq);
1625 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1627 refill_fl(sc, fl, 64);
1629 fl_hw_cidx = fl->hw_cidx;
1632 if (d->rss.opcode == CPL_RX_PKT) {
1633 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1637 m0 = get_fl_payload(sc, fl, lq);
1638 if (__predict_false(m0 == NULL))
1643 case X_RSPD_TYPE_CPL:
1644 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1645 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1646 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1649 case X_RSPD_TYPE_INTR:
1652 * There are 1K interrupt-capable queues (qids 0
1653 * through 1023). A response type indicating a
1654 * forwarded interrupt with a qid >= 1K is an
1655 * iWARP async notification. That is the only
1656 * acceptable indirect interrupt on this queue.
1658 if (__predict_false(lq < 1024)) {
1659 panic("%s: indirect interrupt on iq_fl %p "
1660 "with qid %u", __func__, iq, lq);
1663 t4_an_handler(iq, &d->rsp);
1667 KASSERT(0, ("%s: illegal response type %d on iq %p",
1668 __func__, rsp_type, iq));
1669 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1670 device_get_nameunit(sc->dev), rsp_type, iq);
1675 if (__predict_false(++iq->cidx == iq->sidx)) {
1677 iq->gen ^= F_RSPD_GEN;
1680 if (__predict_false(++ndescs == limit)) {
1681 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1682 V_INGRESSQID(iq->cntxt_id) |
1683 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1685 #if defined(INET) || defined(INET6)
1686 if (iq->flags & IQ_LRO_ENABLED &&
1687 !sort_before_lro(lro) &&
1688 sc->lro_timeout != 0) {
1689 tcp_lro_flush_inactive(lro, &lro_timeout);
1693 return (EINPROGRESS);
1698 #if defined(INET) || defined(INET6)
1699 if (iq->flags & IQ_LRO_ENABLED) {
1700 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1701 MPASS(sort_before_lro(lro));
1702 /* hold back one credit and don't flush LRO state */
1703 iq->flags |= IQ_ADJ_CREDIT;
1706 tcp_lro_flush_all(lro);
1711 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1712 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1715 starved = refill_fl(sc, fl, 64);
1717 if (__predict_false(starved != 0))
1718 add_fl_to_sfl(sc, fl);
1723 static inline struct cluster_metadata *
1724 cl_metadata(struct fl_sdesc *sd)
1727 return ((void *)(sd->cl + sd->moff));
1731 rxb_free(struct mbuf *m)
1733 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1735 uma_zfree(clm->zone, clm->cl);
1736 counter_u64_add(extfree_rels, 1);
1740 * The mbuf returned comes from zone_muf and carries the payload in one of these
1742 * a) complete frame inside the mbuf
1743 * b) m_cljset (for clusters without metadata)
1744 * d) m_extaddref (cluster with metadata)
1746 static struct mbuf *
1747 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1751 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1752 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1753 struct cluster_metadata *clm;
1757 if (fl->flags & FL_BUF_PACKING) {
1760 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1761 len = min(remaining, blen);
1762 payload = sd->cl + fl->rx_offset;
1764 l = fr_offset + len;
1765 pad = roundup2(l, fl->buf_boundary) - l;
1766 if (fl->rx_offset + len + pad < rxb->size2)
1768 MPASS(fl->rx_offset + blen <= rxb->size2);
1770 MPASS(fl->rx_offset == 0); /* not packing */
1772 len = min(remaining, blen);
1776 if (fr_offset == 0) {
1777 m = m_gethdr(M_NOWAIT, MT_DATA);
1778 if (__predict_false(m == NULL))
1780 m->m_pkthdr.len = remaining;
1782 m = m_get(M_NOWAIT, MT_DATA);
1783 if (__predict_false(m == NULL))
1787 kmsan_mark(payload, len, KMSAN_STATE_INITED);
1789 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1790 /* copy data to mbuf */
1791 bcopy(payload, mtod(m, caddr_t), len);
1792 if (fl->flags & FL_BUF_PACKING) {
1793 fl->rx_offset += blen;
1794 MPASS(fl->rx_offset <= rxb->size2);
1795 if (fl->rx_offset < rxb->size2)
1796 return (m); /* without advancing the cidx */
1798 } else if (fl->flags & FL_BUF_PACKING) {
1799 clm = cl_metadata(sd);
1800 if (sd->nmbuf++ == 0) {
1802 clm->zone = rxb->zone;
1804 counter_u64_add(extfree_refs, 1);
1806 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1809 fl->rx_offset += blen;
1810 MPASS(fl->rx_offset <= rxb->size2);
1811 if (fl->rx_offset < rxb->size2)
1812 return (m); /* without advancing the cidx */
1814 m_cljset(m, sd->cl, rxb->type);
1815 sd->cl = NULL; /* consumed, not a recycle candidate */
1818 move_to_next_rxbuf(fl);
1823 static struct mbuf *
1824 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1826 struct mbuf *m0, *m, **pnext;
1829 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1830 M_ASSERTPKTHDR(fl->m0);
1831 MPASS(fl->m0->m_pkthdr.len == plen);
1832 MPASS(fl->remaining < plen);
1836 remaining = fl->remaining;
1837 fl->flags &= ~FL_BUF_RESUME;
1842 * Payload starts at rx_offset in the current hw buffer. Its length is
1843 * 'len' and it may span multiple hw buffers.
1846 m0 = get_scatter_segment(sc, fl, 0, plen);
1849 remaining = plen - m0->m_len;
1850 pnext = &m0->m_next;
1851 while (remaining > 0) {
1853 MPASS(fl->rx_offset == 0);
1854 m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1855 if (__predict_false(m == NULL)) {
1858 fl->remaining = remaining;
1859 fl->flags |= FL_BUF_RESUME;
1864 remaining -= m->m_len;
1873 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1876 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1877 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1880 if (fl->flags & FL_BUF_PACKING) {
1883 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1884 len = min(remaining, blen);
1886 l = fr_offset + len;
1887 pad = roundup2(l, fl->buf_boundary) - l;
1888 if (fl->rx_offset + len + pad < rxb->size2)
1890 fl->rx_offset += blen;
1891 MPASS(fl->rx_offset <= rxb->size2);
1892 if (fl->rx_offset < rxb->size2)
1893 return (len); /* without advancing the cidx */
1895 MPASS(fl->rx_offset == 0); /* not packing */
1897 len = min(remaining, blen);
1899 move_to_next_rxbuf(fl);
1904 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1906 int remaining, fr_offset, len;
1910 while (remaining > 0) {
1911 len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1918 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1921 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1922 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1924 if (fl->flags & FL_BUF_PACKING)
1925 len = rxb->size2 - fl->rx_offset;
1929 return (min(plen, len));
1933 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1937 if_t ifp = rxq->ifp;
1938 struct sge_fl *fl = &rxq->fl;
1939 struct vi_info *vi = if_getsoftc(ifp);
1940 const struct cpl_rx_pkt *cpl;
1941 #if defined(INET) || defined(INET6)
1942 struct lro_ctrl *lro = &rxq->lro;
1944 uint16_t err_vec, tnl_type, tnlhdr_len;
1945 static const int sw_hashtype[4][2] = {
1946 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1947 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1948 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1949 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1951 static const int sw_csum_flags[2][2] = {
1955 CSUM_L3_CALC | CSUM_L3_VALID |
1956 CSUM_L4_CALC | CSUM_L4_VALID |
1957 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1958 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1962 CSUM_L3_CALC | CSUM_L3_VALID |
1963 CSUM_L4_CALC | CSUM_L4_VALID |
1964 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1969 CSUM_L4_CALC | CSUM_L4_VALID |
1970 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1971 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1973 /* IP6, inner IP6 */
1975 CSUM_L4_CALC | CSUM_L4_VALID |
1976 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1980 MPASS(plen > sc->params.sge.fl_pktshift);
1981 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1982 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1983 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1987 slen = get_segment_len(sc, fl, plen) -
1988 sc->params.sge.fl_pktshift;
1989 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1990 CURVNET_SET_QUIET(if_getvnet(ifp));
1991 rc = pfil_mem_in(vi->pfil, frame, slen, ifp, &m0);
1993 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1994 skip_fl_payload(sc, fl, plen);
1997 if (rc == PFIL_REALLOCED) {
1998 skip_fl_payload(sc, fl, plen);
2003 m0 = get_fl_payload(sc, fl, plen);
2004 if (__predict_false(m0 == NULL))
2007 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2008 m0->m_len -= sc->params.sge.fl_pktshift;
2009 m0->m_data += sc->params.sge.fl_pktshift;
2012 m0->m_pkthdr.rcvif = ifp;
2013 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
2014 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
2016 cpl = (const void *)(&d->rss + 1);
2017 if (sc->params.tp.rx_pkt_encap) {
2018 const uint16_t ev = be16toh(cpl->err_vec);
2020 err_vec = G_T6_COMPR_RXERR_VEC(ev);
2021 tnl_type = G_T6_RX_TNL_TYPE(ev);
2022 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
2024 err_vec = be16toh(cpl->err_vec);
2028 if (cpl->csum_calc && err_vec == 0) {
2029 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
2031 /* checksum(s) calculated and found to be correct. */
2033 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2034 (cpl->l2info & htobe32(F_RXF_IP6)));
2035 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2036 if (tnl_type == 0) {
2037 if (!ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM) {
2038 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2039 CSUM_L3_VALID | CSUM_L4_CALC |
2041 } else if (ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM_IPV6) {
2042 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2047 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2049 M_HASHTYPE_SETINNER(m0);
2050 if (__predict_false(cpl->ip_frag)) {
2052 * csum_data is for the inner frame (which is an
2053 * IP fragment) and is not 0xffff. There is no
2054 * way to pass the inner csum_data to the stack.
2055 * We don't want the stack to use the inner
2056 * csum_data to validate the outer frame or it
2057 * will get rejected. So we fix csum_data here
2058 * and let sw do the checksum of inner IP
2061 * XXX: Need 32b for csum_data2 in an rx mbuf.
2062 * Maybe stuff it into rcv_tstmp?
2064 m0->m_pkthdr.csum_data = 0xffff;
2066 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2069 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2070 CSUM_L3_VALID | CSUM_L4_CALC |
2076 MPASS(m0->m_pkthdr.csum_data == 0xffff);
2078 outer_ipv6 = tnlhdr_len >=
2079 sizeof(struct ether_header) +
2080 sizeof(struct ip6_hdr);
2081 m0->m_pkthdr.csum_flags =
2082 sw_csum_flags[outer_ipv6][ipv6];
2084 rxq->vxlan_rxcsum++;
2089 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2090 m0->m_flags |= M_VLANTAG;
2091 rxq->vlan_extraction++;
2094 if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2096 * Fill up rcv_tstmp but do not set M_TSTMP as
2097 * long as we get a non-zero back from t4_tstmp_to_ns().
2099 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc,
2100 be64toh(d->rsp.u.last_flit));
2101 if (m0->m_pkthdr.rcv_tstmp != 0)
2102 m0->m_flags |= M_TSTMP;
2106 m0->m_pkthdr.numa_domain = if_getnumadomain(ifp);
2108 #if defined(INET) || defined(INET6)
2109 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2110 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2111 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2112 if (sort_before_lro(lro)) {
2113 tcp_lro_queue_mbuf(lro, m0);
2114 return (0); /* queued for sort, then LRO */
2116 if (tcp_lro_rx(lro, m0, 0) == 0)
2117 return (0); /* queued for LRO */
2126 * Must drain the wrq or make sure that someone else will.
2129 wrq_tx_drain(void *arg, int n)
2131 struct sge_wrq *wrq = arg;
2132 struct sge_eq *eq = &wrq->eq;
2135 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2136 drain_wrq_wr_list(wrq->adapter, wrq);
2141 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2143 struct sge_eq *eq = &wrq->eq;
2144 u_int available, dbdiff; /* # of hardware descriptors */
2147 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2149 EQ_LOCK_ASSERT_OWNED(eq);
2150 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2151 wr = STAILQ_FIRST(&wrq->wr_list);
2152 MPASS(wr != NULL); /* Must be called with something useful to do */
2153 MPASS(eq->pidx == eq->dbidx);
2157 eq->cidx = read_hw_cidx(eq);
2158 if (eq->pidx == eq->cidx)
2159 available = eq->sidx - 1;
2161 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2163 MPASS(wr->wrq == wrq);
2164 n = howmany(wr->wr_len, EQ_ESIZE);
2168 dst = (void *)&eq->desc[eq->pidx];
2169 if (__predict_true(eq->sidx - eq->pidx > n)) {
2170 /* Won't wrap, won't end exactly at the status page. */
2171 bcopy(&wr->wr[0], dst, wr->wr_len);
2174 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2176 bcopy(&wr->wr[0], dst, first_portion);
2177 if (wr->wr_len > first_portion) {
2178 bcopy(&wr->wr[first_portion], &eq->desc[0],
2179 wr->wr_len - first_portion);
2181 eq->pidx = n - (eq->sidx - eq->pidx);
2183 wrq->tx_wrs_copied++;
2185 if (available < eq->sidx / 4 &&
2186 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2188 * XXX: This is not 100% reliable with some
2189 * types of WRs. But this is a very unusual
2190 * situation for an ofld/ctrl queue anyway.
2192 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2198 ring_eq_db(sc, eq, dbdiff);
2202 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2204 MPASS(wrq->nwr_pending > 0);
2206 MPASS(wrq->ndesc_needed >= n);
2207 wrq->ndesc_needed -= n;
2208 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2211 ring_eq_db(sc, eq, dbdiff);
2215 * Doesn't fail. Holds on to work requests it can't send right away.
2218 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2221 struct sge_eq *eq = &wrq->eq;
2224 EQ_LOCK_ASSERT_OWNED(eq);
2226 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2227 MPASS((wr->wr_len & 0x7) == 0);
2229 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2231 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2233 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2234 return; /* commit_wrq_wr will drain wr_list as well. */
2236 drain_wrq_wr_list(sc, wrq);
2238 /* Doorbell must have caught up to the pidx. */
2239 MPASS(eq->pidx == eq->dbidx);
2243 t4_update_fl_bufsize(if_t ifp)
2245 struct vi_info *vi = if_getsoftc(ifp);
2246 struct adapter *sc = vi->adapter;
2247 struct sge_rxq *rxq;
2249 struct sge_ofld_rxq *ofld_rxq;
2254 maxp = max_rx_payload(sc, ifp, false);
2255 for_each_rxq(vi, i, rxq) {
2259 fl->zidx = find_refill_source(sc, maxp,
2260 fl->flags & FL_BUF_PACKING);
2264 maxp = max_rx_payload(sc, ifp, true);
2265 for_each_ofld_rxq(vi, i, ofld_rxq) {
2269 fl->zidx = find_refill_source(sc, maxp,
2270 fl->flags & FL_BUF_PACKING);
2278 mbuf_eo_nsegs(struct mbuf *m)
2282 return (m->m_pkthdr.PH_loc.eight[1]);
2285 #if defined(INET) || defined(INET6)
2287 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2291 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2296 mbuf_eo_len16(struct mbuf *m)
2301 n = m->m_pkthdr.PH_loc.eight[2];
2302 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2307 #if defined(INET) || defined(INET6)
2309 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2313 m->m_pkthdr.PH_loc.eight[2] = len16;
2318 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2322 return (m->m_pkthdr.PH_loc.eight[3]);
2325 #if defined(INET) || defined(INET6)
2327 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2331 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2336 needs_eo(struct m_snd_tag *mst)
2339 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2344 * Try to allocate an mbuf to contain a raw work request. To make it
2345 * easy to construct the work request, don't allocate a chain but a
2349 alloc_wr_mbuf(int len, int how)
2354 m = m_gethdr(how, MT_DATA);
2355 else if (len <= MCLBYTES)
2356 m = m_getcl(how, MT_DATA, M_PKTHDR);
2361 m->m_pkthdr.len = len;
2363 set_mbuf_cflags(m, MC_RAW_WR);
2364 set_mbuf_len16(m, howmany(len, 16));
2369 needs_hwcsum(struct mbuf *m)
2371 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2372 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2373 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2374 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2375 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2379 return (m->m_pkthdr.csum_flags & csum_flags);
2383 needs_tso(struct mbuf *m)
2385 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2386 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2390 return (m->m_pkthdr.csum_flags & csum_flags);
2394 needs_vxlan_csum(struct mbuf *m)
2399 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2403 needs_vxlan_tso(struct mbuf *m)
2405 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2410 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2411 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2414 #if defined(INET) || defined(INET6)
2416 needs_inner_tcp_csum(struct mbuf *m)
2418 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2422 return (m->m_pkthdr.csum_flags & csum_flags);
2427 needs_l3_csum(struct mbuf *m)
2429 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2434 return (m->m_pkthdr.csum_flags & csum_flags);
2438 needs_outer_tcp_csum(struct mbuf *m)
2440 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2445 return (m->m_pkthdr.csum_flags & csum_flags);
2450 needs_outer_l4_csum(struct mbuf *m)
2452 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2453 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2457 return (m->m_pkthdr.csum_flags & csum_flags);
2461 needs_outer_udp_csum(struct mbuf *m)
2463 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2467 return (m->m_pkthdr.csum_flags & csum_flags);
2472 needs_vlan_insertion(struct mbuf *m)
2477 return (m->m_flags & M_VLANTAG);
2480 #if defined(INET) || defined(INET6)
2482 m_advance(struct mbuf **pm, int *poffset, int len)
2484 struct mbuf *m = *pm;
2485 int offset = *poffset;
2491 if (offset + len < m->m_len) {
2493 p = mtod(m, uintptr_t) + offset;
2496 len -= m->m_len - offset;
2508 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2511 int i, len, off, pglen, pgoff, seglen, segoff;
2515 off = mtod(m, vm_offset_t);
2520 if (m->m_epg_hdrlen != 0) {
2521 if (off >= m->m_epg_hdrlen) {
2522 off -= m->m_epg_hdrlen;
2524 seglen = m->m_epg_hdrlen - off;
2526 seglen = min(seglen, len);
2529 paddr = pmap_kextract(
2530 (vm_offset_t)&m->m_epg_hdr[segoff]);
2531 if (*nextaddr != paddr)
2533 *nextaddr = paddr + seglen;
2536 pgoff = m->m_epg_1st_off;
2537 for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2538 pglen = m_epg_pagelen(m, i, pgoff);
2544 seglen = pglen - off;
2545 segoff = pgoff + off;
2547 seglen = min(seglen, len);
2549 paddr = m->m_epg_pa[i] + segoff;
2550 if (*nextaddr != paddr)
2552 *nextaddr = paddr + seglen;
2556 seglen = min(len, m->m_epg_trllen - off);
2558 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2559 if (*nextaddr != paddr)
2561 *nextaddr = paddr + seglen;
2569 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2570 * must have at least one mbuf that's not empty. It is possible for this
2571 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2574 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2576 vm_paddr_t nextaddr, paddr;
2581 MPASS(m->m_pkthdr.len > 0);
2582 MPASS(m->m_pkthdr.len >= skip);
2586 for (; m; m = m->m_next) {
2588 if (__predict_false(len == 0))
2594 if ((m->m_flags & M_EXTPG) != 0) {
2595 *cflags |= MC_NOMAP;
2596 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2600 va = mtod(m, vm_offset_t) + skip;
2603 paddr = pmap_kextract(va);
2604 nsegs += sglist_count((void *)(uintptr_t)va, len);
2605 if (paddr == nextaddr)
2607 nextaddr = pmap_kextract(va + len - 1) + 1;
2614 * The maximum number of segments that can fit in a WR.
2617 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2622 return (TX_SGL_SEGS_VM_TSO);
2623 return (TX_SGL_SEGS_VM);
2627 if (needs_vxlan_tso(m))
2628 return (TX_SGL_SEGS_VXLAN_TSO);
2630 return (TX_SGL_SEGS_TSO);
2633 return (TX_SGL_SEGS);
2636 static struct timeval txerr_ratecheck = {0};
2637 static const struct timeval txerr_interval = {3, 0};
2640 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2641 * a) caller can assume it's been freed if this function returns with an error.
2642 * b) it may get defragged up if the gather list is too long for the hardware.
2645 parse_pkt(struct mbuf **mp, bool vm_wr)
2647 struct mbuf *m0 = *mp, *m;
2648 int rc, nsegs, defragged = 0;
2649 struct ether_header *eh;
2653 #if defined(INET) || defined(INET6)
2657 #if defined(KERN_TLS) || defined(RATELIMIT)
2658 struct m_snd_tag *mst;
2665 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2674 * First count the number of gather list segments in the payload.
2675 * Defrag the mbuf if nsegs exceeds the hardware limit.
2678 MPASS(m0->m_pkthdr.len > 0);
2679 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2680 #if defined(KERN_TLS) || defined(RATELIMIT)
2681 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2682 mst = m0->m_pkthdr.snd_tag;
2687 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) {
2689 set_mbuf_cflags(m0, cflags);
2690 rc = t6_ktls_parse_pkt(m0);
2693 return (EINPROGRESS);
2696 if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2697 if (defragged++ > 0) {
2701 counter_u64_add(defrags, 1);
2702 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2706 *mp = m0 = m; /* update caller's copy after defrag */
2710 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2711 !(cflags & MC_NOMAP))) {
2712 counter_u64_add(pullups, 1);
2713 m0 = m_pullup(m0, m0->m_pkthdr.len);
2715 /* Should have left well enough alone. */
2719 *mp = m0; /* update caller's copy after pullup */
2722 set_mbuf_nsegs(m0, nsegs);
2723 set_mbuf_cflags(m0, cflags);
2724 calculate_mbuf_len16(m0, vm_wr);
2728 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2729 * checksumming is enabled. needs_outer_l4_csum happens to check for
2730 * all the right things.
2732 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2733 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2734 m0->m_pkthdr.snd_tag = NULL;
2735 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2740 if (!needs_hwcsum(m0)
2748 eh = mtod(m, struct ether_header *);
2749 eh_type = ntohs(eh->ether_type);
2750 if (eh_type == ETHERTYPE_VLAN) {
2751 struct ether_vlan_header *evh = (void *)eh;
2753 eh_type = ntohs(evh->evl_proto);
2754 m0->m_pkthdr.l2hlen = sizeof(*evh);
2756 m0->m_pkthdr.l2hlen = sizeof(*eh);
2758 #if defined(INET) || defined(INET6)
2761 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2763 m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2769 case ETHERTYPE_IPV6:
2770 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2776 struct ip *ip = l3hdr;
2778 if (needs_vxlan_csum(m0)) {
2779 /* Driver will do the outer IP hdr checksum. */
2781 if (needs_vxlan_tso(m0)) {
2782 const uint16_t ipl = ip->ip_len;
2785 ip->ip_sum = ~in_cksum_hdr(ip);
2788 ip->ip_sum = in_cksum_hdr(ip);
2790 m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2795 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2796 log(LOG_ERR, "%s: ethertype 0x%04x unknown. "
2797 "if_cxgbe must be compiled with the same "
2798 "INET/INET6 options as the kernel.\n", __func__,
2805 #if defined(INET) || defined(INET6)
2806 if (needs_vxlan_csum(m0)) {
2807 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2808 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2810 /* Inner headers. */
2811 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2812 sizeof(struct udphdr) + sizeof(struct vxlan_header));
2813 eh_type = ntohs(eh->ether_type);
2814 if (eh_type == ETHERTYPE_VLAN) {
2815 struct ether_vlan_header *evh = (void *)eh;
2817 eh_type = ntohs(evh->evl_proto);
2818 m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2820 m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2822 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2824 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2829 case ETHERTYPE_IPV6:
2830 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2836 struct ip *ip = l3hdr;
2838 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2843 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2844 log(LOG_ERR, "%s: VXLAN hw offload requested"
2845 "with unknown ethertype 0x%04x. if_cxgbe "
2846 "must be compiled with the same INET/INET6 "
2847 "options as the kernel.\n", __func__,
2853 if (needs_inner_tcp_csum(m0)) {
2854 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2855 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2857 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2858 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2859 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2860 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2864 if (needs_outer_tcp_csum(m0)) {
2865 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2866 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2868 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2869 set_mbuf_eo_tsclk_tsoff(m0,
2870 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2871 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2873 set_mbuf_eo_tsclk_tsoff(m0, 0);
2874 } else if (needs_outer_udp_csum(m0)) {
2875 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2879 if (needs_eo(mst)) {
2882 /* EO WRs have the headers in the WR and not the GL. */
2883 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2884 m0->m_pkthdr.l4hlen;
2886 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2887 MPASS(cflags == mbuf_cflags(m0));
2888 set_mbuf_eo_nsegs(m0, nsegs);
2889 set_mbuf_eo_len16(m0,
2890 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2891 rc = ethofld_transmit(mst->ifp, m0);
2894 return (EINPROGRESS);
2903 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2905 struct sge_eq *eq = &wrq->eq;
2906 struct adapter *sc = wrq->adapter;
2907 int ndesc, available;
2912 ndesc = tx_len16_to_desc(len16);
2913 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2917 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2918 drain_wrq_wr_list(sc, wrq);
2920 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2923 wr = alloc_wrqe(len16 * 16, wrq);
2924 if (__predict_false(wr == NULL))
2927 cookie->ndesc = ndesc;
2931 eq->cidx = read_hw_cidx(eq);
2932 if (eq->pidx == eq->cidx)
2933 available = eq->sidx - 1;
2935 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2936 if (available < ndesc)
2939 cookie->pidx = eq->pidx;
2940 cookie->ndesc = ndesc;
2941 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2943 w = &eq->desc[eq->pidx];
2944 IDXINCR(eq->pidx, ndesc, eq->sidx);
2945 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2947 wrq->ss_pidx = cookie->pidx;
2948 wrq->ss_len = len16 * 16;
2957 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2959 struct sge_eq *eq = &wrq->eq;
2960 struct adapter *sc = wrq->adapter;
2962 struct wrq_cookie *prev, *next;
2964 if (cookie->pidx == -1) {
2965 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2971 if (__predict_false(w == &wrq->ss[0])) {
2972 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2974 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2975 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2976 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2979 wrq->tx_wrs_direct++;
2982 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2983 pidx = cookie->pidx;
2984 MPASS(pidx >= 0 && pidx < eq->sidx);
2985 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2986 next = TAILQ_NEXT(cookie, link);
2988 MPASS(pidx == eq->dbidx);
2989 if (next == NULL || ndesc >= 16) {
2991 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2994 * Note that the WR via which we'll request tx updates
2995 * is at pidx and not eq->pidx, which has moved on
2998 dst = (void *)&eq->desc[pidx];
2999 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3000 if (available < eq->sidx / 4 &&
3001 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3003 * XXX: This is not 100% reliable with some
3004 * types of WRs. But this is a very unusual
3005 * situation for an ofld/ctrl queue anyway.
3007 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3011 ring_eq_db(wrq->adapter, eq, ndesc);
3013 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3015 next->ndesc += ndesc;
3018 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3019 prev->ndesc += ndesc;
3021 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3023 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3024 drain_wrq_wr_list(sc, wrq);
3027 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3028 /* Doorbell must have caught up to the pidx. */
3029 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3036 can_resume_eth_tx(struct mp_ring *r)
3038 struct sge_eq *eq = r->cookie;
3040 return (total_available_tx_desc(eq) > eq->sidx / 8);
3044 cannot_use_txpkts(struct mbuf *m)
3046 /* maybe put a GL limit too, to avoid silliness? */
3048 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3052 discard_tx(struct sge_eq *eq)
3055 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3059 wr_can_update_eq(void *p)
3061 struct fw_eth_tx_pkts_wr *wr = p;
3063 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3065 case FW_ETH_TX_PKT_WR:
3066 case FW_ETH_TX_PKTS_WR:
3067 case FW_ETH_TX_PKTS2_WR:
3068 case FW_ETH_TX_PKT_VM_WR:
3069 case FW_ETH_TX_PKTS_VM_WR:
3077 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3078 struct fw_eth_tx_pkt_wr *wr)
3080 struct sge_eq *eq = &txq->eq;
3081 struct txpkts *txp = &txq->txp;
3083 if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3084 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3085 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3086 eq->equeqidx = eq->pidx;
3087 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3088 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3089 eq->equeqidx = eq->pidx;
3093 #if defined(__i386__) || defined(__amd64__)
3094 extern uint64_t tsc_freq;
3098 record_eth_tx_time(struct sge_txq *txq)
3100 const uint64_t cycles = get_cyclecount();
3101 const uint64_t last_tx = txq->last_tx;
3102 #if defined(__i386__) || defined(__amd64__)
3103 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3105 const uint64_t itg = 0;
3108 MPASS(cycles >= last_tx);
3109 txq->last_tx = cycles;
3110 return (cycles - last_tx < itg);
3114 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3115 * be consumed. Return the actual number consumed. 0 indicates a stall.
3118 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3120 struct sge_txq *txq = r->cookie;
3121 if_t ifp = txq->ifp;
3122 struct sge_eq *eq = &txq->eq;
3123 struct txpkts *txp = &txq->txp;
3124 struct vi_info *vi = if_getsoftc(ifp);
3125 struct adapter *sc = vi->adapter;
3126 u_int total, remaining; /* # of packets */
3127 u_int n, avail, dbdiff; /* # of hardware descriptors */
3130 bool snd, recent_tx;
3131 void *wr; /* start of the last WR written to the ring */
3133 TXQ_LOCK_ASSERT_OWNED(txq);
3134 recent_tx = record_eth_tx_time(txq);
3136 remaining = IDXDIFF(pidx, cidx, r->size);
3137 if (__predict_false(discard_tx(eq))) {
3138 for (i = 0; i < txp->npkt; i++)
3139 m_freem(txp->mb[i]);
3141 while (cidx != pidx) {
3142 m0 = r->items[cidx];
3144 if (++cidx == r->size)
3147 reclaim_tx_descs(txq, eq->sidx);
3148 *coalescing = false;
3149 return (remaining); /* emptied */
3152 /* How many hardware descriptors do we have readily available. */
3153 if (eq->pidx == eq->cidx)
3154 avail = eq->sidx - 1;
3156 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3159 if (remaining == 0) {
3161 txq->txpkts_flush++;
3166 MPASS(remaining > 0);
3167 while (remaining > 0) {
3168 m0 = r->items[cidx];
3170 MPASS(m0->m_nextpkt == NULL);
3172 if (avail < 2 * SGE_MAX_WR_NDESC)
3173 avail += reclaim_tx_descs(txq, 64);
3175 if (t4_tx_coalesce == 0 && txp->npkt == 0)
3176 goto skip_coalescing;
3177 if (cannot_use_txpkts(m0))
3179 else if (recent_tx) {
3180 if (++txp->score == 0)
3181 txp->score = UINT8_MAX;
3184 if (txp->npkt > 0 || remaining > 1 ||
3185 txp->score >= t4_tx_coalesce_pkts ||
3186 atomic_load_int(&txq->eq.equiq) != 0) {
3187 if (vi->flags & TX_USES_VM_WR)
3188 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3190 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3196 MPASS(txp->npkt > 0);
3197 for (i = 0; i < txp->npkt; i++)
3198 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3199 if (txp->npkt > 1) {
3200 MPASS(avail >= tx_len16_to_desc(txp->len16));
3201 if (vi->flags & TX_USES_VM_WR)
3202 n = write_txpkts_vm_wr(sc, txq);
3204 n = write_txpkts_wr(sc, txq);
3207 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3208 if (vi->flags & TX_USES_VM_WR)
3209 n = write_txpkt_vm_wr(sc, txq,
3212 n = write_txpkt_wr(sc, txq, txp->mb[0],
3215 MPASS(n <= SGE_MAX_WR_NDESC);
3218 wr = &eq->desc[eq->pidx];
3219 IDXINCR(eq->pidx, n, eq->sidx);
3220 txp->npkt = 0; /* emptied */
3223 /* m0 was coalesced into txq->txpkts. */
3228 * m0 is suitable for tx coalescing but could not be
3229 * combined with the existing txq->txpkts, which has now
3230 * been transmitted. Start a new txpkts with m0.
3233 MPASS(txp->npkt == 0);
3237 MPASS(rc != 0 && rc != EAGAIN);
3238 MPASS(txp->npkt == 0);
3240 n = tx_len16_to_desc(mbuf_len16(m0));
3241 if (__predict_false(avail < n)) {
3242 avail += reclaim_tx_descs(txq, min(n, 32));
3244 break; /* out of descriptors */
3247 wr = &eq->desc[eq->pidx];
3248 if (mbuf_cflags(m0) & MC_RAW_WR) {
3249 n = write_raw_wr(txq, wr, m0, avail);
3251 } else if (mbuf_cflags(m0) & MC_TLS) {
3252 ETHER_BPF_MTAP(ifp, m0);
3253 n = t6_ktls_write_wr(txq, wr, m0, avail);
3256 ETHER_BPF_MTAP(ifp, m0);
3257 if (vi->flags & TX_USES_VM_WR)
3258 n = write_txpkt_vm_wr(sc, txq, m0);
3260 n = write_txpkt_wr(sc, txq, m0, avail);
3262 MPASS(n >= 1 && n <= avail);
3263 if (!(mbuf_cflags(m0) & MC_TLS))
3264 MPASS(n <= SGE_MAX_WR_NDESC);
3268 IDXINCR(eq->pidx, n, eq->sidx);
3270 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */
3271 if (wr_can_update_eq(wr))
3272 set_txupdate_flags(txq, avail, wr);
3273 ring_eq_db(sc, eq, dbdiff);
3274 avail += reclaim_tx_descs(txq, 32);
3280 if (__predict_false(++cidx == r->size))
3284 if (wr_can_update_eq(wr))
3285 set_txupdate_flags(txq, avail, wr);
3286 ring_eq_db(sc, eq, dbdiff);
3287 reclaim_tx_descs(txq, 32);
3288 } else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3289 atomic_load_int(&txq->eq.equiq) == 0) {
3291 * If nothing was submitted to the chip for tx (it was coalesced
3292 * into txpkts instead) and there is no tx update outstanding
3293 * then we need to send txpkts now.
3296 MPASS(txp->npkt > 0);
3297 for (i = 0; i < txp->npkt; i++)
3298 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3299 if (txp->npkt > 1) {
3300 MPASS(avail >= tx_len16_to_desc(txp->len16));
3301 if (vi->flags & TX_USES_VM_WR)
3302 n = write_txpkts_vm_wr(sc, txq);
3304 n = write_txpkts_wr(sc, txq);
3307 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3308 if (vi->flags & TX_USES_VM_WR)
3309 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3311 n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3313 MPASS(n <= SGE_MAX_WR_NDESC);
3314 wr = &eq->desc[eq->pidx];
3315 IDXINCR(eq->pidx, n, eq->sidx);
3316 txp->npkt = 0; /* emptied */
3318 MPASS(wr_can_update_eq(wr));
3319 set_txupdate_flags(txq, avail - n, wr);
3320 ring_eq_db(sc, eq, n);
3321 reclaim_tx_descs(txq, 32);
3323 *coalescing = txp->npkt > 0;
3329 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3330 int qsize, int intr_idx, int cong, int qtype)
3333 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3334 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3335 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3336 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3337 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count,
3338 ("%s: bad intr_idx %d", __func__, intr_idx));
3339 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC ||
3340 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype));
3343 iq->state = IQS_DISABLED;
3346 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3347 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3348 if (pktc_idx >= 0) {
3349 iq->intr_params |= F_QINTR_CNT_EN;
3350 iq->intr_pktc_idx = pktc_idx;
3352 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3353 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3354 iq->intr_idx = intr_idx;
3355 iq->cong_drop = cong;
3359 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3361 struct sge_params *sp = &sc->params.sge;
3364 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3365 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3366 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3367 if (sc->flags & BUF_PACKING_OK &&
3368 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3369 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3370 fl->flags |= FL_BUF_PACKING;
3371 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3372 fl->safe_zidx = sc->sge.safe_zidx;
3373 if (fl->flags & FL_BUF_PACKING) {
3374 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3375 fl->buf_boundary = sp->pack_boundary;
3377 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3378 fl->buf_boundary = 16;
3380 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3381 fl->buf_boundary = sp->pad_boundary;
3385 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3386 uint8_t tx_chan, struct sge_iq *iq, char *name)
3388 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD,
3389 ("%s: bad qtype %d", __func__, eqtype));
3392 eq->tx_chan = tx_chan;
3394 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3395 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3396 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3400 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3401 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3405 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3406 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3408 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc);
3412 rc = bus_dmamem_alloc(*tag, va,
3413 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3415 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc);
3419 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3421 CH_ERR(sc, "cannot load DMA map: %d\n", rc);
3426 free_ring(sc, *tag, *map, *pa, *va);
3432 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3433 bus_addr_t pa, void *va)
3436 bus_dmamap_unload(tag, map);
3438 bus_dmamem_free(tag, va, map);
3440 bus_dma_tag_destroy(tag);
3446 * Allocates the software resources (mainly memory and sysctl nodes) for an
3447 * ingress queue and an optional freelist.
3449 * Sets IQ_SW_ALLOCATED and returns 0 on success.
3452 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3453 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
3457 struct adapter *sc = vi->adapter;
3459 MPASS(!(iq->flags & IQ_SW_ALLOCATED));
3461 len = iq->qsize * IQ_ESIZE;
3462 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3463 (void **)&iq->desc);
3468 len = fl->qsize * EQ_ESIZE;
3469 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3470 &fl->ba, (void **)&fl->desc);
3472 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba,
3477 /* Allocate space for one software descriptor per buffer. */
3478 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc),
3479 M_CXGBE, M_ZERO | M_WAITOK);
3481 add_fl_sysctls(sc, ctx, oid, fl);
3482 iq->flags |= IQ_HAS_FL;
3484 add_iq_sysctls(ctx, oid, iq);
3485 iq->flags |= IQ_SW_ALLOCATED;
3491 * Frees all software resources (memory and locks) associated with an ingress
3492 * queue and an optional freelist.
3495 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3497 MPASS(iq->flags & IQ_SW_ALLOCATED);
3500 MPASS(iq->flags & IQ_HAS_FL);
3501 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc);
3502 free_fl_buffers(sc, fl);
3503 free(fl->sdesc, M_CXGBE);
3504 mtx_destroy(&fl->fl_lock);
3505 bzero(fl, sizeof(*fl));
3507 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3508 bzero(iq, sizeof(*iq));
3512 * Allocates a hardware ingress queue and an optional freelist that will be
3513 * associated with it.
3515 * Returns errno on failure. Resources allocated up to that point may still be
3516 * allocated. Caller is responsible for cleanup in case this function fails.
3519 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3521 int rc, cntxt_id, cong_map;
3523 struct adapter *sc = vi->adapter;
3524 struct port_info *pi = vi->pi;
3527 MPASS (!(iq->flags & IQ_HW_ALLOCATED));
3529 bzero(&c, sizeof(c));
3530 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3531 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3532 V_FW_IQ_CMD_VFN(0));
3534 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3537 /* Special handling for firmware event queue */
3538 if (iq == &sc->sge.fwq)
3539 v |= F_FW_IQ_CMD_IQASYNCH;
3541 if (iq->intr_idx < 0) {
3542 /* Forwarded interrupts, all headed to fwq */
3543 v |= F_FW_IQ_CMD_IQANDST;
3544 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3546 KASSERT(iq->intr_idx < sc->intr_count,
3547 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx));
3548 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx);
3551 bzero(iq->desc, iq->qsize * IQ_ESIZE);
3552 c.type_to_iqandstindex = htobe32(v |
3553 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3554 V_FW_IQ_CMD_VIID(vi->viid) |
3555 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3556 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3557 F_FW_IQ_CMD_IQGTSMODE |
3558 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3559 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3560 c.iqsize = htobe16(iq->qsize);
3561 c.iqaddr = htobe64(iq->ba);
3562 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
3563 if (iq->cong_drop != -1) {
3564 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0;
3565 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3569 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
3570 c.iqns_to_fl0congen |=
3571 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3572 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3573 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3574 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3576 if (iq->cong_drop != -1) {
3577 c.iqns_to_fl0congen |=
3578 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) |
3579 F_FW_IQ_CMD_FL0CONGCIF |
3580 F_FW_IQ_CMD_FL0CONGEN);
3582 c.fl0dcaen_to_fl0cidxfthresh =
3583 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3584 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3585 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3586 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3587 c.fl0size = htobe16(fl->qsize);
3588 c.fl0addr = htobe64(fl->ba);
3591 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3593 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc);
3598 iq->gen = F_RSPD_GEN;
3599 iq->cntxt_id = be16toh(c.iqid);
3600 iq->abs_id = be16toh(c.physiqid);
3602 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3603 if (cntxt_id >= sc->sge.iqmap_sz) {
3604 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3605 cntxt_id, sc->sge.iqmap_sz - 1);
3607 sc->sge.iqmap[cntxt_id] = iq;
3614 MPASS(!(fl->flags & FL_BUF_RESUME));
3615 for (i = 0; i < fl->sidx * 8; i++)
3616 MPASS(fl->sdesc[i].cl == NULL);
3618 fl->cntxt_id = be16toh(c.fl0id);
3619 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0;
3621 fl->flags &= ~(FL_STARVING | FL_DOOMED);
3623 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3624 if (cntxt_id >= sc->sge.eqmap_sz) {
3625 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3626 __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3628 sc->sge.eqmap[cntxt_id] = (void *)fl;
3631 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3632 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3633 uint32_t mask = (1 << s_qpp) - 1;
3634 volatile uint8_t *udb;
3636 udb = sc->udbs_base + UDBS_DB_OFFSET;
3637 udb += (qid >> s_qpp) << PAGE_SHIFT;
3639 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3640 udb += qid << UDBS_SEG_SHIFT;
3643 fl->udb = (volatile void *)udb;
3645 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3648 /* Enough to make sure the SGE doesn't think it's starved */
3649 refill_fl(sc, fl, fl->lowat);
3653 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) &&
3654 iq->cong_drop != -1) {
3655 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop,
3659 /* Enable IQ interrupts */
3660 atomic_store_rel_int(&iq->state, IQS_IDLE);
3661 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3662 V_INGRESSQID(iq->cntxt_id));
3664 iq->flags |= IQ_HW_ALLOCATED;
3670 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3674 MPASS(iq->flags & IQ_HW_ALLOCATED);
3675 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
3676 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
3678 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc);
3681 iq->flags &= ~IQ_HW_ALLOCATED;
3687 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3690 struct sysctl_oid_list *children;
3692 if (ctx == NULL || oid == NULL)
3695 children = SYSCTL_CHILDREN(oid);
3696 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3697 "bus address of descriptor ring");
3698 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3699 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3700 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3701 &iq->abs_id, 0, "absolute id of the queue");
3702 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3703 &iq->cntxt_id, 0, "SGE context id of the queue");
3704 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3705 0, "consumer index");
3709 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3710 struct sysctl_oid *oid, struct sge_fl *fl)
3712 struct sysctl_oid_list *children;
3714 if (ctx == NULL || oid == NULL)
3717 children = SYSCTL_CHILDREN(oid);
3718 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3719 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3720 children = SYSCTL_CHILDREN(oid);
3722 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3723 &fl->ba, "bus address of descriptor ring");
3724 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3725 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3726 "desc ring size in bytes");
3727 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3728 &fl->cntxt_id, 0, "SGE context id of the freelist");
3729 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3730 fl_pad ? 1 : 0, "padding enabled");
3731 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3732 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3733 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3734 0, "consumer index");
3735 if (fl->flags & FL_BUF_PACKING) {
3736 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3737 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3739 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3740 0, "producer index");
3741 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3742 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3743 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3744 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3745 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3746 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3753 alloc_fwq(struct adapter *sc)
3756 struct sge_iq *fwq = &sc->sge.fwq;
3757 struct vi_info *vi = &sc->port[0]->vi[0];
3759 if (!(fwq->flags & IQ_SW_ALLOCATED)) {
3760 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3762 if (sc->flags & IS_VF)
3765 intr_idx = sc->intr_count > 1 ? 1 : 0;
3766 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER);
3767 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid);
3769 CH_ERR(sc, "failed to allocate fwq: %d\n", rc);
3772 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3775 if (!(fwq->flags & IQ_HW_ALLOCATED)) {
3776 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3778 rc = alloc_iq_fl_hwq(vi, fwq, NULL);
3780 CH_ERR(sc, "failed to create hw fwq: %d\n", rc);
3783 MPASS(fwq->flags & IQ_HW_ALLOCATED);
3793 free_fwq(struct adapter *sc)
3795 struct sge_iq *fwq = &sc->sge.fwq;
3797 if (fwq->flags & IQ_HW_ALLOCATED) {
3798 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3799 free_iq_fl_hwq(sc, fwq, NULL);
3800 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3803 if (fwq->flags & IQ_SW_ALLOCATED) {
3804 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3805 free_iq_fl(sc, fwq, NULL);
3806 MPASS(!(fwq->flags & IQ_SW_ALLOCATED));
3814 alloc_ctrlq(struct adapter *sc, int idx)
3818 struct sysctl_oid *oid;
3819 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3821 MPASS(idx < sc->params.nports);
3823 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
3824 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3826 snprintf(name, sizeof(name), "%d", idx);
3827 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid),
3828 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3831 snprintf(name, sizeof(name), "%s ctrlq%d",
3832 device_get_nameunit(sc->dev), idx);
3833 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE,
3834 sc->port[idx]->tx_chan, &sc->sge.fwq, name);
3835 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
3837 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
3838 sysctl_remove_oid(oid, 1, 1);
3841 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3844 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) {
3845 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3847 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
3849 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
3852 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED);
3862 free_ctrlq(struct adapter *sc, int idx)
3864 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3866 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) {
3867 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3868 free_eq_hwq(sc, NULL, &ctrlq->eq);
3869 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3872 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) {
3873 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3874 free_wrq(sc, ctrlq);
3875 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED));
3880 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop,
3883 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log;
3884 uint32_t param, val;
3886 int cong_mode, rc, i;
3888 if (chip_id(sc) < CHELSIO_T5)
3891 /* Convert the driver knob to the mode understood by the firmware. */
3892 switch (cong_drop) {
3894 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE;
3897 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL;
3900 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE;
3903 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH;
3907 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n",
3908 cong_drop, cntxt_id);
3912 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3913 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3914 V_FW_PARAMS_PARAM_YZ(cntxt_id);
3915 val = V_CONMCTXT_CNGTPMODE(cong_mode);
3916 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
3917 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
3918 for (i = 0, ch_map = 0; i < 4; i++) {
3919 if (cong_map & (1 << i))
3920 ch_map |= 1 << (i << cng_ch_bits_log);
3922 val |= V_CONMCTXT_CNGCHMAP(ch_map);
3924 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3926 CH_ERR(sc, "failed to set congestion manager context "
3927 "for ingress queue %d: %d\n", cntxt_id, rc);
3937 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
3941 struct adapter *sc = vi->adapter;
3943 struct sysctl_oid *oid;
3946 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) {
3947 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
3948 #if defined(INET) || defined(INET6)
3949 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs);
3952 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */
3956 snprintf(name, sizeof(name), "%d", idx);
3957 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid),
3958 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3961 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
3962 intr_idx, cong_drop, IQ_ETH);
3963 #if defined(INET) || defined(INET6)
3964 if (if_getcapenable(ifp) & IFCAP_LRO)
3965 rxq->iq.flags |= IQ_LRO_ENABLED;
3967 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
3968 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3969 snprintf(name, sizeof(name), "%s rxq%d-fl",
3970 device_get_nameunit(vi->dev), idx);
3971 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
3972 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid);
3974 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc);
3975 sysctl_remove_oid(oid, 1, 1);
3976 #if defined(INET) || defined(INET6)
3977 tcp_lro_free(&rxq->lro);
3978 rxq->lro.ifp = NULL;
3982 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3983 add_rxq_sysctls(&vi->ctx, oid, rxq);
3986 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) {
3987 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3988 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl);
3990 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc);
3993 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED);
3996 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3998 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3999 ("iq_base mismatch"));
4000 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
4001 ("PF with non-zero iq_base"));
4004 * The freelist is just barely above the starvation threshold
4005 * right now, fill it up a bit more.
4008 refill_fl(sc, &rxq->fl, 128);
4009 FL_UNLOCK(&rxq->fl);
4019 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
4021 if (rxq->iq.flags & IQ_HW_ALLOCATED) {
4022 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4023 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl);
4024 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4027 if (rxq->iq.flags & IQ_SW_ALLOCATED) {
4028 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4029 #if defined(INET) || defined(INET6)
4030 tcp_lro_free(&rxq->lro);
4032 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl);
4033 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED));
4034 bzero(rxq, sizeof(*rxq));
4039 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4040 struct sge_rxq *rxq)
4042 struct sysctl_oid_list *children;
4044 if (ctx == NULL || oid == NULL)
4047 children = SYSCTL_CHILDREN(oid);
4048 #if defined(INET) || defined(INET6)
4049 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
4050 &rxq->lro.lro_queued, 0, NULL);
4051 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
4052 &rxq->lro.lro_flushed, 0, NULL);
4054 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
4055 &rxq->rxcsum, "# of times hardware assisted with checksum");
4056 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD,
4057 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag");
4058 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD,
4060 "# of times hardware assisted with inner checksum (VXLAN)");
4068 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx,
4069 int intr_idx, int maxp)
4072 struct adapter *sc = vi->adapter;
4073 struct sysctl_oid *oid;
4076 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) {
4077 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4079 snprintf(name, sizeof(name), "%d", idx);
4080 oid = SYSCTL_ADD_NODE(&vi->ctx,
4081 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name,
4082 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue");
4084 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
4085 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD);
4086 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
4087 device_get_nameunit(vi->dev), idx);
4088 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
4089 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx,
4092 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx,
4094 sysctl_remove_oid(oid, 1, 1);
4097 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4098 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK);
4099 ofld_rxq->rx_iscsi_ddp_setup_error =
4100 counter_u64_alloc(M_WAITOK);
4101 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq);
4104 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) {
4105 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4106 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl);
4108 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx,
4112 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED);
4121 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
4123 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) {
4124 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4125 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4126 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4129 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) {
4130 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4131 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4132 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED));
4133 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok);
4134 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error);
4135 bzero(ofld_rxq, sizeof(*ofld_rxq));
4140 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4141 struct sge_ofld_rxq *ofld_rxq)
4143 struct sysctl_oid_list *children;
4145 if (ctx == NULL || oid == NULL)
4148 children = SYSCTL_CHILDREN(oid);
4149 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4150 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records,
4151 "# of TOE TLS records received");
4152 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4153 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets,
4154 "# of payload octets in received TOE TLS records");
4156 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi",
4157 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics");
4158 children = SYSCTL_CHILDREN(oid);
4160 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok",
4161 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok,
4162 "# of times DDP buffer was setup successfully.");
4163 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error",
4164 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error,
4165 "# of times DDP buffer setup failed.");
4166 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets",
4167 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0,
4168 "# of octets placed directly");
4169 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus",
4170 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0,
4171 "# of PDUs with data placed directly.");
4172 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets",
4173 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0,
4174 "# of data octets delivered in freelist");
4175 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus",
4176 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0,
4177 "# of PDUs with data delivered in freelist");
4178 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors",
4179 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0,
4180 "# of PDUs with invalid padding");
4181 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors",
4182 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0,
4183 "# of PDUs with invalid header digests");
4184 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors",
4185 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0,
4186 "# of PDUs with invalid data digests");
4191 * Returns a reasonable automatic cidx flush threshold for a given queue size.
4194 qsize_to_fthresh(int qsize)
4198 while (!powerof2(qsize))
4200 fthresh = ilog2(qsize);
4201 if (fthresh > X_CIDXFLUSHTHRESH_128)
4202 fthresh = X_CIDXFLUSHTHRESH_128;
4208 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4211 struct fw_eq_ctrl_cmd c;
4212 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4214 bzero(&c, sizeof(c));
4216 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4217 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4218 V_FW_EQ_CTRL_CMD_VFN(0));
4219 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4220 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4221 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4222 c.physeqid_pkd = htobe32(0);
4223 c.fetchszm_to_iqid =
4224 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4225 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4226 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4228 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4229 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4230 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4231 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4232 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4233 c.eqaddr = htobe64(eq->ba);
4235 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4237 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
4242 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4243 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4244 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4245 if (cntxt_id >= sc->sge.eqmap_sz)
4246 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4247 cntxt_id, sc->sge.eqmap_sz - 1);
4248 sc->sge.eqmap[cntxt_id] = eq;
4254 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4257 struct fw_eq_eth_cmd c;
4258 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4260 bzero(&c, sizeof(c));
4262 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4263 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4264 V_FW_EQ_ETH_CMD_VFN(0));
4265 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4266 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4267 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4268 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4269 c.fetchszm_to_iqid =
4270 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4271 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4272 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4274 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4275 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4276 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4277 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4278 c.eqaddr = htobe64(eq->ba);
4280 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4282 device_printf(vi->dev,
4283 "failed to create Ethernet egress queue: %d\n", rc);
4287 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4288 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4289 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4290 if (cntxt_id >= sc->sge.eqmap_sz)
4291 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4292 cntxt_id, sc->sge.eqmap_sz - 1);
4293 sc->sge.eqmap[cntxt_id] = eq;
4298 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4300 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4303 struct fw_eq_ofld_cmd c;
4304 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4306 bzero(&c, sizeof(c));
4308 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4309 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4310 V_FW_EQ_OFLD_CMD_VFN(0));
4311 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4312 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4313 c.fetchszm_to_iqid =
4314 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4315 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4316 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4318 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4319 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4320 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4321 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4322 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4323 c.eqaddr = htobe64(eq->ba);
4325 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4327 device_printf(vi->dev,
4328 "failed to create egress queue for TCP offload: %d\n", rc);
4332 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4333 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4334 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4335 if (cntxt_id >= sc->sge.eqmap_sz)
4336 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4337 cntxt_id, sc->sge.eqmap_sz - 1);
4338 sc->sge.eqmap[cntxt_id] = eq;
4346 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx,
4347 struct sysctl_oid *oid)
4352 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4354 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4355 len = qsize * EQ_ESIZE;
4356 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba,
4357 (void **)&eq->desc);
4360 if (ctx != NULL && oid != NULL)
4361 add_eq_sysctls(sc, ctx, oid, eq);
4362 eq->flags |= EQ_SW_ALLOCATED;
4369 free_eq(struct adapter *sc, struct sge_eq *eq)
4371 MPASS(eq->flags & EQ_SW_ALLOCATED);
4372 if (eq->type == EQ_ETH)
4373 MPASS(eq->pidx == eq->cidx);
4375 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4376 mtx_destroy(&eq->eq_lock);
4377 bzero(eq, sizeof(*eq));
4381 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
4382 struct sysctl_oid *oid, struct sge_eq *eq)
4384 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4386 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba,
4387 "bus address of descriptor ring");
4388 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4389 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4390 "desc ring size in bytes");
4391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4392 &eq->abs_id, 0, "absolute id of the queue");
4393 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4394 &eq->cntxt_id, 0, "SGE context id of the queue");
4395 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx,
4396 0, "consumer index");
4397 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx,
4398 0, "producer index");
4399 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4400 eq->sidx, "status page index");
4404 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4408 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4410 eq->iqid = eq->iq->cntxt_id;
4411 eq->pidx = eq->cidx = eq->dbidx = 0;
4412 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4414 eq->doorbells = sc->doorbells;
4415 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len);
4419 rc = ctrl_eq_alloc(sc, eq);
4423 rc = eth_eq_alloc(sc, vi, eq);
4426 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4428 rc = ofld_eq_alloc(sc, vi, eq);
4433 panic("%s: invalid eq type %d.", __func__, eq->type);
4436 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n",
4441 if (isset(&eq->doorbells, DOORBELL_UDB) ||
4442 isset(&eq->doorbells, DOORBELL_UDBWC) ||
4443 isset(&eq->doorbells, DOORBELL_WCWR)) {
4444 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4445 uint32_t mask = (1 << s_qpp) - 1;
4446 volatile uint8_t *udb;
4448 udb = sc->udbs_base + UDBS_DB_OFFSET;
4449 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
4450 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
4451 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4452 clrbit(&eq->doorbells, DOORBELL_WCWR);
4454 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
4457 eq->udb = (volatile void *)udb;
4460 eq->flags |= EQ_HW_ALLOCATED;
4465 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq)
4469 MPASS(eq->flags & EQ_HW_ALLOCATED);
4473 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4476 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4478 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4480 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4484 panic("%s: invalid eq type %d.", __func__, eq->type);
4487 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc);
4490 eq->flags &= ~EQ_HW_ALLOCATED;
4496 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4497 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
4499 struct sge_eq *eq = &wrq->eq;
4502 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4504 rc = alloc_eq(sc, eq, ctx, oid);
4507 MPASS(eq->flags & EQ_SW_ALLOCATED);
4508 /* Can't fail after this. */
4511 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4512 TAILQ_INIT(&wrq->incomplete_wrs);
4513 STAILQ_INIT(&wrq->wr_list);
4514 wrq->nwr_pending = 0;
4515 wrq->ndesc_needed = 0;
4516 add_wrq_sysctls(ctx, oid, wrq);
4522 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4524 free_eq(sc, &wrq->eq);
4525 MPASS(wrq->nwr_pending == 0);
4526 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
4527 MPASS(STAILQ_EMPTY(&wrq->wr_list));
4528 bzero(wrq, sizeof(*wrq));
4532 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4533 struct sge_wrq *wrq)
4535 struct sysctl_oid_list *children;
4537 if (ctx == NULL || oid == NULL)
4540 children = SYSCTL_CHILDREN(oid);
4541 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4542 &wrq->tx_wrs_direct, "# of work requests (direct)");
4543 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4544 &wrq->tx_wrs_copied, "# of work requests (copied)");
4545 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4546 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4553 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx)
4556 struct port_info *pi = vi->pi;
4557 struct adapter *sc = vi->adapter;
4558 struct sge_eq *eq = &txq->eq;
4561 struct sysctl_oid *oid;
4563 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4564 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4566 snprintf(name, sizeof(name), "%d", idx);
4567 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid),
4568 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4571 iqidx = vi->first_rxq + (idx % vi->nrxq);
4572 snprintf(name, sizeof(name), "%s txq%d",
4573 device_get_nameunit(vi->dev), idx);
4574 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
4575 &sc->sge.rxq[iqidx].iq, name);
4577 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx,
4578 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK);
4580 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n",
4583 sysctl_remove_oid(oid, 1, 1);
4587 rc = alloc_eq(sc, eq, &vi->ctx, oid);
4589 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc);
4590 mp_ring_free(txq->r);
4593 MPASS(eq->flags & EQ_SW_ALLOCATED);
4594 /* Can't fail after this point. */
4596 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4598 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4599 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4602 add_txq_sysctls(vi, &vi->ctx, oid, txq);
4605 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4606 MPASS(eq->flags & EQ_SW_ALLOCATED);
4607 rc = alloc_eq_hwq(sc, vi, eq);
4609 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
4612 MPASS(eq->flags & EQ_HW_ALLOCATED);
4613 /* Can't fail after this point. */
4616 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4618 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4619 ("eq_base mismatch"));
4620 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4621 ("PF with non-zero eq_base"));
4624 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4625 txq->txp.max_npkt = min(nitems(txp->mb),
4626 sc->params.max_pkts_per_eth_tx_pkts_wr);
4627 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4628 txq->txp.max_npkt--;
4630 if (vi->flags & TX_USES_VM_WR)
4631 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4632 V_TXPKT_INTF(pi->tx_chan));
4634 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4635 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4636 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4648 free_txq(struct vi_info *vi, struct sge_txq *txq)
4650 struct adapter *sc = vi->adapter;
4651 struct sge_eq *eq = &txq->eq;
4653 if (eq->flags & EQ_HW_ALLOCATED) {
4654 MPASS(eq->flags & EQ_SW_ALLOCATED);
4655 free_eq_hwq(sc, NULL, eq);
4656 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4659 if (eq->flags & EQ_SW_ALLOCATED) {
4660 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4661 sglist_free(txq->gl);
4662 free(txq->sdesc, M_CXGBE);
4663 mp_ring_free(txq->r);
4665 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4666 bzero(txq, sizeof(*txq));
4671 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
4672 struct sysctl_oid *oid, struct sge_txq *txq)
4675 struct sysctl_oid_list *children;
4677 if (ctx == NULL || oid == NULL)
4681 children = SYSCTL_CHILDREN(oid);
4683 mp_ring_sysctls(txq->r, ctx, children);
4685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc",
4686 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq,
4687 sysctl_tc, "I", "traffic class (-1 means none)");
4689 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4690 &txq->txcsum, "# of times hardware assisted with checksum");
4691 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD,
4692 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag");
4693 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4694 &txq->tso_wrs, "# of TSO work requests");
4695 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4696 &txq->imm_wrs, "# of work requests with immediate data");
4697 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4698 &txq->sgl_wrs, "# of work requests with direct SGL");
4699 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4700 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4701 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD,
4702 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests");
4703 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD,
4704 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests");
4705 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD,
4707 "# of frames tx'd using type0 txpkts work requests");
4708 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD,
4710 "# of frames tx'd using type1 txpkts work requests");
4711 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD,
4713 "# of times txpkts had to be flushed out by an egress-update");
4714 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4715 &txq->raw_wrs, "# of raw work requests (non-packets)");
4716 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD,
4717 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4718 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD,
4720 "# of times hardware assisted with inner checksums (VXLAN)");
4724 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records",
4725 CTLFLAG_RD, &txq->kern_tls_records,
4726 "# of NIC TLS records transmitted");
4727 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short",
4728 CTLFLAG_RD, &txq->kern_tls_short,
4729 "# of short NIC TLS records transmitted");
4730 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial",
4731 CTLFLAG_RD, &txq->kern_tls_partial,
4732 "# of partial NIC TLS records transmitted");
4733 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full",
4734 CTLFLAG_RD, &txq->kern_tls_full,
4735 "# of full NIC TLS records transmitted");
4736 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets",
4737 CTLFLAG_RD, &txq->kern_tls_octets,
4738 "# of payload octets in transmitted NIC TLS records");
4739 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
4740 CTLFLAG_RD, &txq->kern_tls_waste,
4741 "# of octets DMAd but not transmitted in NIC TLS records");
4742 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
4743 CTLFLAG_RD, &txq->kern_tls_options,
4744 "# of NIC TLS options-only packets transmitted");
4745 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
4746 CTLFLAG_RD, &txq->kern_tls_header,
4747 "# of NIC TLS header-only packets transmitted");
4748 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
4749 CTLFLAG_RD, &txq->kern_tls_fin,
4750 "# of NIC TLS FIN-only packets transmitted");
4751 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
4752 CTLFLAG_RD, &txq->kern_tls_fin_short,
4753 "# of NIC TLS padded FIN packets on short TLS records");
4754 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
4755 CTLFLAG_RD, &txq->kern_tls_cbc,
4756 "# of NIC TLS sessions using AES-CBC");
4757 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm",
4758 CTLFLAG_RD, &txq->kern_tls_gcm,
4759 "# of NIC TLS sessions using AES-GCM");
4764 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4769 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
4771 struct sysctl_oid *oid;
4772 struct port_info *pi = vi->pi;
4773 struct adapter *sc = vi->adapter;
4774 struct sge_eq *eq = &ofld_txq->wrq.eq;
4779 MPASS(idx < vi->nofldtxq);
4781 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4782 snprintf(name, sizeof(name), "%d", idx);
4783 oid = SYSCTL_ADD_NODE(&vi->ctx,
4784 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name,
4785 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
4787 snprintf(name, sizeof(name), "%s ofld_txq%d",
4788 device_get_nameunit(vi->dev), idx);
4789 if (vi->nofldrxq > 0) {
4790 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq);
4791 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4792 &sc->sge.ofld_rxq[iqidx].iq, name);
4794 iqidx = vi->first_rxq + (idx % vi->nrxq);
4795 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
4796 &sc->sge.rxq[iqidx].iq, name);
4799 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid);
4801 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx,
4803 sysctl_remove_oid(oid, 1, 1);
4806 MPASS(eq->flags & EQ_SW_ALLOCATED);
4807 /* Can't fail after this point. */
4809 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK);
4810 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK);
4811 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK);
4812 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK);
4813 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK);
4814 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq);
4817 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4818 rc = alloc_eq_hwq(sc, vi, eq);
4820 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
4824 MPASS(eq->flags & EQ_HW_ALLOCATED);
4834 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq)
4836 struct adapter *sc = vi->adapter;
4837 struct sge_eq *eq = &ofld_txq->wrq.eq;
4839 if (eq->flags & EQ_HW_ALLOCATED) {
4840 MPASS(eq->flags & EQ_SW_ALLOCATED);
4841 free_eq_hwq(sc, NULL, eq);
4842 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4845 if (eq->flags & EQ_SW_ALLOCATED) {
4846 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4847 counter_u64_free(ofld_txq->tx_iscsi_pdus);
4848 counter_u64_free(ofld_txq->tx_iscsi_octets);
4849 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs);
4850 counter_u64_free(ofld_txq->tx_toe_tls_records);
4851 counter_u64_free(ofld_txq->tx_toe_tls_octets);
4852 free_wrq(sc, &ofld_txq->wrq);
4853 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4854 bzero(ofld_txq, sizeof(*ofld_txq));
4859 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4860 struct sge_ofld_txq *ofld_txq)
4862 struct sysctl_oid_list *children;
4864 if (ctx == NULL || oid == NULL)
4867 children = SYSCTL_CHILDREN(oid);
4868 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus",
4869 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus,
4870 "# of iSCSI PDUs transmitted");
4871 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets",
4872 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets,
4873 "# of payload octets in transmitted iSCSI PDUs");
4874 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs",
4875 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs,
4876 "# of iSCSI segmentation offload work requests");
4877 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records",
4878 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records,
4879 "# of TOE TLS records transmitted");
4880 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets",
4881 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets,
4882 "# of payload octets in transmitted TOE TLS records");
4887 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4889 bus_addr_t *ba = arg;
4892 ("%s meant for single segment mappings only.", __func__));
4894 *ba = error ? 0 : segs->ds_addr;
4898 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4902 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4906 v = fl->dbval | V_PIDX(n);
4908 *fl->udb = htole32(v);
4910 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4911 IDXINCR(fl->dbidx, n, fl->sidx);
4915 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4916 * recycled do not count towards this allocation budget.
4918 * Returns non-zero to indicate that this freelist should be added to the list
4919 * of starving freelists.
4922 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4925 struct fl_sdesc *sd;
4928 struct rx_buf_info *rxb;
4929 struct cluster_metadata *clm;
4930 uint16_t max_pidx, zidx = fl->zidx;
4931 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4933 FL_LOCK_ASSERT_OWNED(fl);
4936 * We always stop at the beginning of the hardware descriptor that's just
4937 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4938 * which would mean an empty freelist to the chip.
4940 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4941 if (fl->pidx == max_pidx * 8)
4944 d = &fl->desc[fl->pidx];
4945 sd = &fl->sdesc[fl->pidx];
4946 rxb = &sc->sge.rx_buf_info[zidx];
4950 if (sd->cl != NULL) {
4952 if (sd->nmbuf == 0) {
4954 * Fast recycle without involving any atomics on
4955 * the cluster's metadata (if the cluster has
4956 * metadata). This happens when all frames
4957 * received in the cluster were small enough to
4958 * fit within a single mbuf each.
4960 fl->cl_fast_recycled++;
4965 * Cluster is guaranteed to have metadata. Clusters
4966 * without metadata always take the fast recycle path
4967 * when they're recycled.
4969 clm = cl_metadata(sd);
4972 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4974 counter_u64_add(extfree_rels, 1);
4977 sd->cl = NULL; /* gave up my reference */
4979 MPASS(sd->cl == NULL);
4980 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4981 if (__predict_false(cl == NULL)) {
4982 if (zidx != fl->safe_zidx) {
4983 zidx = fl->safe_zidx;
4984 rxb = &sc->sge.rx_buf_info[zidx];
4985 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4993 pa = pmap_kextract((vm_offset_t)cl);
4997 if (fl->flags & FL_BUF_PACKING) {
4998 *d = htobe64(pa | rxb->hwidx2);
4999 sd->moff = rxb->size2;
5001 *d = htobe64(pa | rxb->hwidx1);
5008 if (__predict_false((++fl->pidx & 7) == 0)) {
5009 uint16_t pidx = fl->pidx >> 3;
5011 if (__predict_false(pidx == fl->sidx)) {
5017 if (n < 8 || pidx == max_pidx)
5020 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
5025 if ((fl->pidx >> 3) != fl->dbidx)
5028 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
5032 * Attempt to refill all starving freelists.
5035 refill_sfl(void *arg)
5037 struct adapter *sc = arg;
5038 struct sge_fl *fl, *fl_temp;
5040 mtx_assert(&sc->sfl_lock, MA_OWNED);
5041 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
5043 refill_fl(sc, fl, 64);
5044 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
5045 TAILQ_REMOVE(&sc->sfl, fl, link);
5046 fl->flags &= ~FL_STARVING;
5051 if (!TAILQ_EMPTY(&sc->sfl))
5052 callout_schedule(&sc->sfl_callout, hz / 5);
5056 * Release the driver's reference on all buffers in the given freelist. Buffers
5057 * with kernel references cannot be freed and will prevent the driver from being
5061 free_fl_buffers(struct adapter *sc, struct sge_fl *fl)
5063 struct fl_sdesc *sd;
5064 struct cluster_metadata *clm;
5068 for (i = 0; i < fl->sidx * 8; i++, sd++) {
5073 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
5074 else if (fl->flags & FL_BUF_PACKING) {
5075 clm = cl_metadata(sd);
5076 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5077 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
5079 counter_u64_add(extfree_rels, 1);
5085 if (fl->flags & FL_BUF_RESUME) {
5087 fl->flags &= ~FL_BUF_RESUME;
5092 get_pkt_gl(struct mbuf *m, struct sglist *gl)
5099 rc = sglist_append_mbuf(gl, m);
5100 if (__predict_false(rc != 0)) {
5101 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
5102 "with %d.", __func__, m, mbuf_nsegs(m), rc);
5105 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
5106 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
5107 mbuf_nsegs(m), gl->sg_nseg));
5108 #if 0 /* vm_wr not readily available here. */
5109 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
5110 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
5111 gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
5116 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5119 txpkt_len16(u_int nsegs, const u_int extra)
5125 nsegs--; /* first segment is part of ulptx_sgl */
5126 n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
5127 sizeof(struct cpl_tx_pkt_core) +
5128 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5130 return (howmany(n, 16));
5134 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
5138 txpkt_vm_len16(u_int nsegs, const u_int extra)
5144 nsegs--; /* first segment is part of ulptx_sgl */
5145 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
5146 sizeof(struct cpl_tx_pkt_core) +
5147 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5149 return (howmany(n, 16));
5153 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
5155 const int lso = sizeof(struct cpl_tx_pkt_lso_core);
5156 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
5160 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
5162 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
5167 if (needs_vxlan_tso(m))
5168 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
5170 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
5172 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
5176 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
5180 txpkts0_len16(u_int nsegs)
5186 nsegs--; /* first segment is part of ulptx_sgl */
5187 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
5188 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
5189 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5191 return (howmany(n, 16));
5195 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
5203 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
5205 return (howmany(n, 16));
5209 imm_payload(u_int ndesc)
5213 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
5214 sizeof(struct cpl_tx_pkt_core);
5219 static inline uint64_t
5220 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
5223 int csum_type, l2hlen, l3hlen;
5225 static const int csum_types[3][2] = {
5226 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
5227 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
5233 if (!needs_hwcsum(m))
5234 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
5236 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
5237 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
5239 if (needs_vxlan_csum(m)) {
5240 MPASS(m->m_pkthdr.l4hlen > 0);
5241 MPASS(m->m_pkthdr.l5hlen > 0);
5242 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
5243 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
5245 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
5246 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
5247 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
5248 l3hlen = m->m_pkthdr.inner_l3hlen;
5250 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
5251 l3hlen = m->m_pkthdr.l3hlen;
5255 if (!needs_l3_csum(m))
5256 ctrl |= F_TXPKT_IPCSUM_DIS;
5258 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
5259 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
5261 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
5262 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
5267 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
5268 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
5271 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
5272 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
5276 * needs_hwcsum returned true earlier so there must be some kind of
5277 * checksum to calculate.
5279 csum_type = csum_types[x][y];
5280 MPASS(csum_type != 0);
5281 if (csum_type == TX_CSUM_IP)
5282 ctrl |= F_TXPKT_L4CSUM_DIS;
5283 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
5284 if (chip_id(sc) <= CHELSIO_T5)
5285 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
5287 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
5292 static inline void *
5293 write_lso_cpl(void *cpl, struct mbuf *m0)
5295 struct cpl_tx_pkt_lso_core *lso;
5298 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5299 m0->m_pkthdr.l4hlen > 0,
5300 ("%s: mbuf %p needs TSO but missing header lengths",
5303 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5304 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5305 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5306 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5307 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5308 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5312 lso->lso_ctrl = htobe32(ctrl);
5313 lso->ipid_ofst = htobe16(0);
5314 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5315 lso->seqno_offset = htobe32(0);
5316 lso->len = htobe32(m0->m_pkthdr.len);
5322 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
5324 struct cpl_tx_tnl_lso *tnl_lso = cpl;
5327 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
5328 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
5329 m0->m_pkthdr.inner_l5hlen > 0,
5330 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
5332 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5333 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
5334 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
5337 /* Outer headers. */
5338 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
5339 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
5340 V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
5341 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5342 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
5343 F_CPL_TX_TNL_LSO_IPLENSETOUT;
5344 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5345 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
5347 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
5348 F_CPL_TX_TNL_LSO_IPIDINCOUT;
5350 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
5351 tnl_lso->IpIdOffsetOut = 0;
5352 tnl_lso->UdpLenSetOut_to_TnlHdrLen =
5353 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
5354 F_CPL_TX_TNL_LSO_UDPLENSETOUT |
5355 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
5356 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
5357 m0->m_pkthdr.l5hlen) |
5358 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
5361 /* Inner headers. */
5362 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
5363 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
5364 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
5365 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
5366 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
5367 ctrl |= F_CPL_TX_TNL_LSO_IPV6;
5368 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
5369 tnl_lso->IpIdOffset = 0;
5370 tnl_lso->IpIdSplit_to_Mss =
5371 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
5372 tnl_lso->TCPSeqOffset = 0;
5373 tnl_lso->EthLenOffset_Size =
5374 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
5376 return (tnl_lso + 1);
5379 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */
5382 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
5383 * software descriptor, and advance the pidx. It is guaranteed that enough
5384 * descriptors are available.
5386 * The return value is the # of hardware descriptors used.
5389 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
5392 struct fw_eth_tx_pkt_vm_wr *wr;
5393 struct tx_sdesc *txsd;
5394 struct cpl_tx_pkt_core *cpl;
5395 uint32_t ctrl; /* used in many unrelated places */
5397 int len16, ndesc, pktlen;
5400 TXQ_LOCK_ASSERT_OWNED(txq);
5403 len16 = mbuf_len16(m0);
5404 pktlen = m0->m_pkthdr.len;
5405 ctrl = sizeof(struct cpl_tx_pkt_core);
5407 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5408 ndesc = tx_len16_to_desc(len16);
5410 /* Firmware work request header */
5412 wr = (void *)&eq->desc[eq->pidx];
5413 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5414 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5416 ctrl = V_FW_WR_LEN16(len16);
5417 wr->equiq_to_len16 = htobe32(ctrl);
5422 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5423 * vlantci is ignored unless the ethtype is 0x8100, so it's
5424 * simpler to always copy it rather than making it
5425 * conditional. Also, it seems that we do not have to set
5426 * vlantci or fake the ethtype when doing VLAN tag insertion.
5428 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5430 if (needs_tso(m0)) {
5431 cpl = write_lso_cpl(wr + 1, m0);
5434 cpl = (void *)(wr + 1);
5436 /* Checksum offload */
5437 ctrl1 = csum_to_ctrl(sc, m0);
5438 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5439 txq->txcsum++; /* some hardware assistance provided */
5441 /* VLAN tag insertion */
5442 if (needs_vlan_insertion(m0)) {
5443 ctrl1 |= F_TXPKT_VLAN_VLD |
5444 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5445 txq->vlan_insertion++;
5449 cpl->ctrl0 = txq->cpl_ctrl0;
5451 cpl->len = htobe16(pktlen);
5452 cpl->ctrl1 = htobe64(ctrl1);
5455 dst = (void *)(cpl + 1);
5458 * A packet using TSO will use up an entire descriptor for the
5459 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5460 * If this descriptor is the last descriptor in the ring, wrap
5461 * around to the front of the ring explicitly for the start of
5464 if (dst == (void *)&eq->desc[eq->sidx]) {
5465 dst = (void *)&eq->desc[0];
5466 write_gl_to_txd(txq, m0, &dst, 0);
5468 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5472 txsd = &txq->sdesc[eq->pidx];
5474 txsd->desc_used = ndesc;
5480 * Write a raw WR to the hardware descriptors, update the software
5481 * descriptor, and advance the pidx. It is guaranteed that enough
5482 * descriptors are available.
5484 * The return value is the # of hardware descriptors used.
5487 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5489 struct sge_eq *eq = &txq->eq;
5490 struct tx_sdesc *txsd;
5495 len16 = mbuf_len16(m0);
5496 ndesc = tx_len16_to_desc(len16);
5497 MPASS(ndesc <= available);
5500 for (m = m0; m != NULL; m = m->m_next)
5501 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5505 txsd = &txq->sdesc[eq->pidx];
5507 txsd->desc_used = ndesc;
5513 * Write a txpkt WR for this packet to the hardware descriptors, update the
5514 * software descriptor, and advance the pidx. It is guaranteed that enough
5515 * descriptors are available.
5517 * The return value is the # of hardware descriptors used.
5520 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5524 struct fw_eth_tx_pkt_wr *wr;
5525 struct tx_sdesc *txsd;
5526 struct cpl_tx_pkt_core *cpl;
5527 uint32_t ctrl; /* used in many unrelated places */
5529 int len16, ndesc, pktlen, nsegs;
5532 TXQ_LOCK_ASSERT_OWNED(txq);
5535 len16 = mbuf_len16(m0);
5536 nsegs = mbuf_nsegs(m0);
5537 pktlen = m0->m_pkthdr.len;
5538 ctrl = sizeof(struct cpl_tx_pkt_core);
5539 if (needs_tso(m0)) {
5540 if (needs_vxlan_tso(m0))
5541 ctrl += sizeof(struct cpl_tx_tnl_lso);
5543 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5544 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5546 /* Immediate data. Recalculate len16 and set nsegs to 0. */
5548 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5549 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5552 ndesc = tx_len16_to_desc(len16);
5553 MPASS(ndesc <= available);
5555 /* Firmware work request header */
5557 wr = (void *)&eq->desc[eq->pidx];
5558 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5559 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5561 ctrl = V_FW_WR_LEN16(len16);
5562 wr->equiq_to_len16 = htobe32(ctrl);
5565 if (needs_tso(m0)) {
5566 if (needs_vxlan_tso(m0)) {
5567 cpl = write_tnl_lso_cpl(wr + 1, m0);
5568 txq->vxlan_tso_wrs++;
5570 cpl = write_lso_cpl(wr + 1, m0);
5574 cpl = (void *)(wr + 1);
5576 /* Checksum offload */
5577 ctrl1 = csum_to_ctrl(sc, m0);
5578 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5579 /* some hardware assistance provided */
5580 if (needs_vxlan_csum(m0))
5581 txq->vxlan_txcsum++;
5586 /* VLAN tag insertion */
5587 if (needs_vlan_insertion(m0)) {
5588 ctrl1 |= F_TXPKT_VLAN_VLD |
5589 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5590 txq->vlan_insertion++;
5594 cpl->ctrl0 = txq->cpl_ctrl0;
5596 cpl->len = htobe16(pktlen);
5597 cpl->ctrl1 = htobe64(ctrl1);
5600 dst = (void *)(cpl + 1);
5601 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5602 dst = (caddr_t)&eq->desc[0];
5605 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5610 for (m = m0; m != NULL; m = m->m_next) {
5611 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5617 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5624 txsd = &txq->sdesc[eq->pidx];
5626 txsd->desc_used = ndesc;
5632 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5636 MPASS(txp->npkt > 0);
5637 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5639 if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5640 len = VM_TX_L2HDR_LEN;
5642 len = sizeof(struct ether_header);
5644 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5648 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5650 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5652 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5656 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5657 int avail, bool *send)
5659 struct txpkts *txp = &txq->txp;
5661 /* Cannot have TSO and coalesce at the same time. */
5662 if (cannot_use_txpkts(m)) {
5664 *send = txp->npkt > 0;
5668 /* VF allows coalescing of type 1 (1 GL) only */
5669 if (mbuf_nsegs(m) > 1)
5670 goto cannot_coalesce;
5673 if (txp->npkt > 0) {
5674 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5675 MPASS(txp->npkt < txp->max_npkt);
5676 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5678 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5683 if (m->m_pkthdr.len + txp->plen > 65535)
5684 goto retry_after_send;
5685 if (cmp_l2hdr(txp, m))
5686 goto retry_after_send;
5688 txp->len16 += txpkts1_len16();
5689 txp->plen += m->m_pkthdr.len;
5690 txp->mb[txp->npkt++] = m;
5691 if (txp->npkt == txp->max_npkt)
5694 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5696 if (tx_len16_to_desc(txp->len16) > avail)
5697 goto cannot_coalesce;
5700 txp->plen = m->m_pkthdr.len;
5708 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5709 int avail, bool *send)
5711 struct txpkts *txp = &txq->txp;
5714 MPASS(!(sc->flags & IS_VF));
5716 /* Cannot have TSO and coalesce at the same time. */
5717 if (cannot_use_txpkts(m)) {
5719 *send = txp->npkt > 0;
5724 nsegs = mbuf_nsegs(m);
5725 if (txp->npkt == 0) {
5726 if (m->m_pkthdr.len > 65535)
5727 goto cannot_coalesce;
5731 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5732 txpkts0_len16(nsegs);
5736 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5739 if (tx_len16_to_desc(txp->len16) > avail)
5740 goto cannot_coalesce;
5742 txp->plen = m->m_pkthdr.len;
5745 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5746 MPASS(txp->npkt < txp->max_npkt);
5748 if (m->m_pkthdr.len + txp->plen > 65535) {
5754 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5755 if (txp->wr_type == 0) {
5756 if (tx_len16_to_desc(txp->len16 +
5757 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5758 goto retry_after_send;
5759 txp->len16 += txpkts0_len16(nsegs);
5762 goto retry_after_send;
5763 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5765 goto retry_after_send;
5766 txp->len16 += txpkts1_len16();
5769 txp->plen += m->m_pkthdr.len;
5770 txp->mb[txp->npkt++] = m;
5771 if (txp->npkt == txp->max_npkt)
5778 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5779 * the software descriptor, and advance the pidx. It is guaranteed that enough
5780 * descriptors are available.
5782 * The return value is the # of hardware descriptors used.
5785 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5787 const struct txpkts *txp = &txq->txp;
5788 struct sge_eq *eq = &txq->eq;
5789 struct fw_eth_tx_pkts_wr *wr;
5790 struct tx_sdesc *txsd;
5791 struct cpl_tx_pkt_core *cpl;
5793 int ndesc, i, checkwrap;
5794 struct mbuf *m, *last;
5797 TXQ_LOCK_ASSERT_OWNED(txq);
5798 MPASS(txp->npkt > 0);
5799 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5801 wr = (void *)&eq->desc[eq->pidx];
5802 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5803 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5804 wr->plen = htobe16(txp->plen);
5805 wr->npkt = txp->npkt;
5807 wr->type = txp->wr_type;
5811 * At this point we are 16B into a hardware descriptor. If checkwrap is
5812 * set then we know the WR is going to wrap around somewhere. We'll
5813 * check for that at appropriate points.
5815 ndesc = tx_len16_to_desc(txp->len16);
5817 checkwrap = eq->sidx - ndesc < eq->pidx;
5818 for (i = 0; i < txp->npkt; i++) {
5820 if (txp->wr_type == 0) {
5821 struct ulp_txpkt *ulpmc;
5822 struct ulptx_idata *ulpsc;
5824 /* ULP master command */
5826 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5827 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5828 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5830 /* ULP subcommand */
5831 ulpsc = (void *)(ulpmc + 1);
5832 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5834 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5836 cpl = (void *)(ulpsc + 1);
5838 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5839 cpl = (void *)&eq->desc[0];
5844 /* Checksum offload */
5845 ctrl1 = csum_to_ctrl(sc, m);
5846 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5847 /* some hardware assistance provided */
5848 if (needs_vxlan_csum(m))
5849 txq->vxlan_txcsum++;
5854 /* VLAN tag insertion */
5855 if (needs_vlan_insertion(m)) {
5856 ctrl1 |= F_TXPKT_VLAN_VLD |
5857 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5858 txq->vlan_insertion++;
5862 cpl->ctrl0 = txq->cpl_ctrl0;
5864 cpl->len = htobe16(m->m_pkthdr.len);
5865 cpl->ctrl1 = htobe64(ctrl1);
5869 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5870 flitp = (void *)&eq->desc[0];
5872 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5875 last->m_nextpkt = m;
5880 if (txp->wr_type == 0) {
5881 txq->txpkts0_pkts += txp->npkt;
5884 txq->txpkts1_pkts += txp->npkt;
5888 txsd = &txq->sdesc[eq->pidx];
5889 txsd->m = txp->mb[0];
5890 txsd->desc_used = ndesc;
5896 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5898 const struct txpkts *txp = &txq->txp;
5899 struct sge_eq *eq = &txq->eq;
5900 struct fw_eth_tx_pkts_vm_wr *wr;
5901 struct tx_sdesc *txsd;
5902 struct cpl_tx_pkt_core *cpl;
5905 struct mbuf *m, *last;
5908 TXQ_LOCK_ASSERT_OWNED(txq);
5909 MPASS(txp->npkt > 0);
5910 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5911 MPASS(txp->mb[0] != NULL);
5912 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5914 wr = (void *)&eq->desc[eq->pidx];
5915 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5916 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5918 wr->plen = htobe16(txp->plen);
5919 wr->npkt = txp->npkt;
5921 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5925 * At this point we are 32B into a hardware descriptor. Each mbuf in
5926 * the WR will take 32B so we check for the end of the descriptor ring
5927 * before writing odd mbufs (mb[1], 3, 5, ..)
5929 ndesc = tx_len16_to_desc(txp->len16);
5931 for (i = 0; i < txp->npkt; i++) {
5933 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5934 flitp = &eq->desc[0];
5937 /* Checksum offload */
5938 ctrl1 = csum_to_ctrl(sc, m);
5939 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5940 txq->txcsum++; /* some hardware assistance provided */
5942 /* VLAN tag insertion */
5943 if (needs_vlan_insertion(m)) {
5944 ctrl1 |= F_TXPKT_VLAN_VLD |
5945 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5946 txq->vlan_insertion++;
5950 cpl->ctrl0 = txq->cpl_ctrl0;
5952 cpl->len = htobe16(m->m_pkthdr.len);
5953 cpl->ctrl1 = htobe64(ctrl1);
5956 MPASS(mbuf_nsegs(m) == 1);
5957 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
5960 last->m_nextpkt = m;
5965 txq->txpkts1_pkts += txp->npkt;
5968 txsd = &txq->sdesc[eq->pidx];
5969 txsd->m = txp->mb[0];
5970 txsd->desc_used = ndesc;
5976 * If the SGL ends on an address that is not 16 byte aligned, this function will
5977 * add a 0 filled flit at the end.
5980 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5982 struct sge_eq *eq = &txq->eq;
5983 struct sglist *gl = txq->gl;
5984 struct sglist_seg *seg;
5985 __be64 *flitp, *wrap;
5986 struct ulptx_sgl *usgl;
5987 int i, nflits, nsegs;
5989 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5990 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5991 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5992 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5995 nsegs = gl->sg_nseg;
5998 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5999 flitp = (__be64 *)(*to);
6000 wrap = (__be64 *)(&eq->desc[eq->sidx]);
6001 seg = &gl->sg_segs[0];
6002 usgl = (void *)flitp;
6005 * We start at a 16 byte boundary somewhere inside the tx descriptor
6006 * ring, so we're at least 16 bytes away from the status page. There is
6007 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
6010 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6011 V_ULPTX_NSGE(nsegs));
6012 usgl->len0 = htobe32(seg->ss_len);
6013 usgl->addr0 = htobe64(seg->ss_paddr);
6016 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
6018 /* Won't wrap around at all */
6020 for (i = 0; i < nsegs - 1; i++, seg++) {
6021 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
6022 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
6025 usgl->sge[i / 2].len[1] = htobe32(0);
6029 /* Will wrap somewhere in the rest of the SGL */
6031 /* 2 flits already written, write the rest flit by flit */
6032 flitp = (void *)(usgl + 1);
6033 for (i = 0; i < nflits - 2; i++) {
6035 flitp = (void *)eq->desc;
6036 *flitp++ = get_flit(seg, nsegs - 1, i);
6041 MPASS(((uintptr_t)flitp) & 0xf);
6045 MPASS((((uintptr_t)flitp) & 0xf) == 0);
6046 if (__predict_false(flitp == wrap))
6047 *to = (void *)eq->desc;
6049 *to = (void *)flitp;
6053 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
6056 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6057 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6059 if (__predict_true((uintptr_t)(*to) + len <=
6060 (uintptr_t)&eq->desc[eq->sidx])) {
6061 bcopy(from, *to, len);
6064 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
6066 bcopy(from, *to, portion);
6068 portion = len - portion; /* remaining */
6069 bcopy(from, (void *)eq->desc, portion);
6070 (*to) = (caddr_t)eq->desc + portion;
6075 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
6083 clrbit(&db, DOORBELL_WCWR);
6086 switch (ffs(db) - 1) {
6088 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6091 case DOORBELL_WCWR: {
6092 volatile uint64_t *dst, *src;
6096 * Queues whose 128B doorbell segment fits in the page do not
6097 * use relative qid (udb_qid is always 0). Only queues with
6098 * doorbell segments can do WCWR.
6100 KASSERT(eq->udb_qid == 0 && n == 1,
6101 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
6102 __func__, eq->doorbells, n, eq->dbidx, eq));
6104 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
6107 src = (void *)&eq->desc[i];
6108 while (src != (void *)&eq->desc[i + 1])
6114 case DOORBELL_UDBWC:
6115 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6120 t4_write_reg(sc, sc->sge_kdoorbell_reg,
6121 V_QID(eq->cntxt_id) | V_PIDX(n));
6125 IDXINCR(eq->dbidx, n, eq->sidx);
6129 reclaimable_tx_desc(struct sge_eq *eq)
6133 hw_cidx = read_hw_cidx(eq);
6134 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
6138 total_available_tx_desc(struct sge_eq *eq)
6140 uint16_t hw_cidx, pidx;
6142 hw_cidx = read_hw_cidx(eq);
6145 if (pidx == hw_cidx)
6146 return (eq->sidx - 1);
6148 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
6151 static inline uint16_t
6152 read_hw_cidx(struct sge_eq *eq)
6154 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6155 uint16_t cidx = spg->cidx; /* stable snapshot */
6157 return (be16toh(cidx));
6161 * Reclaim 'n' descriptors approximately.
6164 reclaim_tx_descs(struct sge_txq *txq, u_int n)
6166 struct tx_sdesc *txsd;
6167 struct sge_eq *eq = &txq->eq;
6168 u_int can_reclaim, reclaimed;
6170 TXQ_LOCK_ASSERT_OWNED(txq);
6174 can_reclaim = reclaimable_tx_desc(eq);
6175 while (can_reclaim && reclaimed < n) {
6177 struct mbuf *m, *nextpkt;
6179 txsd = &txq->sdesc[eq->cidx];
6180 ndesc = txsd->desc_used;
6182 /* Firmware doesn't return "partial" credits. */
6183 KASSERT(can_reclaim >= ndesc,
6184 ("%s: unexpected number of credits: %d, %d",
6185 __func__, can_reclaim, ndesc));
6187 ("%s: descriptor with no credits: cidx %d",
6188 __func__, eq->cidx));
6190 for (m = txsd->m; m != NULL; m = nextpkt) {
6191 nextpkt = m->m_nextpkt;
6192 m->m_nextpkt = NULL;
6196 can_reclaim -= ndesc;
6197 IDXINCR(eq->cidx, ndesc, eq->sidx);
6204 tx_reclaim(void *arg, int n)
6206 struct sge_txq *txq = arg;
6207 struct sge_eq *eq = &txq->eq;
6210 if (TXQ_TRYLOCK(txq) == 0)
6212 n = reclaim_tx_descs(txq, 32);
6213 if (eq->cidx == eq->pidx)
6214 eq->equeqidx = eq->pidx;
6220 get_flit(struct sglist_seg *segs, int nsegs, int idx)
6222 int i = (idx / 3) * 2;
6228 rc = (uint64_t)segs[i].ss_len << 32;
6230 rc |= (uint64_t)(segs[i + 1].ss_len);
6232 return (htobe64(rc));
6235 return (htobe64(segs[i].ss_paddr));
6237 return (htobe64(segs[i + 1].ss_paddr));
6244 find_refill_source(struct adapter *sc, int maxp, bool packing)
6247 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6250 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6251 if (rxb->hwidx2 == -1)
6253 if (rxb->size1 < PAGE_SIZE &&
6254 rxb->size1 < largest_rx_cluster)
6256 if (rxb->size1 > largest_rx_cluster)
6258 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
6259 if (rxb->size2 >= maxp)
6264 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6265 if (rxb->hwidx1 == -1)
6267 if (rxb->size1 > largest_rx_cluster)
6269 if (rxb->size1 >= maxp)
6279 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
6281 mtx_lock(&sc->sfl_lock);
6283 if ((fl->flags & FL_DOOMED) == 0) {
6284 fl->flags |= FL_STARVING;
6285 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
6286 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
6289 mtx_unlock(&sc->sfl_lock);
6293 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
6295 struct sge_wrq *wrq = (void *)eq;
6297 atomic_readandclear_int(&eq->equiq);
6298 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
6302 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
6304 struct sge_txq *txq = (void *)eq;
6306 MPASS(eq->type == EQ_ETH);
6308 atomic_readandclear_int(&eq->equiq);
6309 if (mp_ring_is_idle(txq->r))
6310 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
6312 mp_ring_check_drainage(txq->r, 64);
6316 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
6319 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
6320 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
6321 struct adapter *sc = iq->adapter;
6322 struct sge *s = &sc->sge;
6324 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
6325 &handle_wrq_egr_update, &handle_eth_egr_update,
6326 &handle_wrq_egr_update};
6328 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6331 eq = s->eqmap[qid - s->eq_start - s->eq_base];
6332 (*h[eq->type])(sc, eq);
6337 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
6338 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
6339 offsetof(struct cpl_fw6_msg, data));
6342 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
6344 struct adapter *sc = iq->adapter;
6345 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
6347 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6350 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
6351 const struct rss_header *rss2;
6353 rss2 = (const struct rss_header *)&cpl->data[0];
6354 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
6357 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
6361 * t4_handle_wrerr_rpl - process a FW work request error message
6362 * @adap: the adapter
6363 * @rpl: start of the FW message
6366 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
6368 u8 opcode = *(const u8 *)rpl;
6369 const struct fw_error_cmd *e = (const void *)rpl;
6372 if (opcode != FW_ERROR_CMD) {
6374 "%s: Received WRERR_RPL message with opcode %#x\n",
6375 device_get_nameunit(adap->dev), opcode);
6378 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
6379 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
6381 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
6382 case FW_ERROR_TYPE_EXCEPTION:
6383 log(LOG_ERR, "exception info:\n");
6384 for (i = 0; i < nitems(e->u.exception.info); i++)
6385 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
6386 be32toh(e->u.exception.info[i]));
6389 case FW_ERROR_TYPE_HWMODULE:
6390 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
6391 be32toh(e->u.hwmodule.regaddr),
6392 be32toh(e->u.hwmodule.regval));
6394 case FW_ERROR_TYPE_WR:
6395 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
6396 be16toh(e->u.wr.cidx),
6397 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6398 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6399 be32toh(e->u.wr.eqid));
6400 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6401 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6405 case FW_ERROR_TYPE_ACL:
6406 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6407 be16toh(e->u.acl.cidx),
6408 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6409 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6410 be32toh(e->u.acl.eqid),
6411 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6413 for (i = 0; i < nitems(e->u.acl.val); i++)
6414 log(LOG_ERR, " %02x", e->u.acl.val[i]);
6418 log(LOG_ERR, "type %#x\n",
6419 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6426 bufidx_used(struct adapter *sc, int idx)
6428 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6431 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6432 if (rxb->size1 > largest_rx_cluster)
6434 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6442 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6444 struct adapter *sc = arg1;
6445 struct sge_params *sp = &sc->params.sge;
6450 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6451 for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6452 if (bufidx_used(sc, i))
6457 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6461 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6467 #if defined(INET) || defined(INET6)
6469 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
6472 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6478 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6479 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6480 if (__predict_false(nsegs == 0))
6483 nsegs--; /* first segment is part of ulptx_sgl */
6484 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6486 n += sizeof(struct cpl_tx_pkt_lso_core);
6489 return (howmany(n, 16));
6493 #define ETID_FLOWC_NPARAMS 6
6494 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6495 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6496 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6498 #if defined(INET) || defined(INET6)
6500 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6503 struct wrq_cookie cookie;
6504 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6505 struct fw_flowc_wr *flowc;
6507 mtx_assert(&cst->lock, MA_OWNED);
6508 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6511 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie);
6512 if (__predict_false(flowc == NULL))
6515 bzero(flowc, ETID_FLOWC_LEN);
6516 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6517 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6518 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6519 V_FW_WR_FLOWID(cst->etid));
6520 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6521 flowc->mnemval[0].val = htobe32(pfvf);
6522 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6523 flowc->mnemval[1].val = htobe32(pi->tx_chan);
6524 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6525 flowc->mnemval[2].val = htobe32(pi->tx_chan);
6526 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6527 flowc->mnemval[3].val = htobe32(cst->iqid);
6528 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6529 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6530 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6531 flowc->mnemval[5].val = htobe32(cst->schedcl);
6533 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6535 cst->flags &= ~EO_FLOWC_PENDING;
6536 cst->flags |= EO_FLOWC_RPL_PENDING;
6537 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
6538 cst->tx_credits -= ETID_FLOWC_LEN16;
6544 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6547 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6549 struct fw_flowc_wr *flowc;
6550 struct wrq_cookie cookie;
6552 mtx_assert(&cst->lock, MA_OWNED);
6554 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie);
6555 if (__predict_false(flowc == NULL))
6556 CXGBE_UNIMPLEMENTED(__func__);
6558 bzero(flowc, ETID_FLUSH_LEN16 * 16);
6559 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6560 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6561 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6562 V_FW_WR_FLOWID(cst->etid));
6564 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6566 cst->flags |= EO_FLUSH_RPL_PENDING;
6567 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6568 cst->tx_credits -= ETID_FLUSH_LEN16;
6573 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6574 struct mbuf *m0, int compl)
6576 struct cpl_tx_pkt_core *cpl;
6578 uint32_t ctrl; /* used in many unrelated places */
6579 int len16, pktlen, nsegs, immhdrs;
6581 struct ulptx_sgl *usgl;
6583 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
6585 mtx_assert(&cst->lock, MA_OWNED);
6587 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6588 m0->m_pkthdr.l4hlen > 0,
6589 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6591 len16 = mbuf_eo_len16(m0);
6592 nsegs = mbuf_eo_nsegs(m0);
6593 pktlen = m0->m_pkthdr.len;
6594 ctrl = sizeof(struct cpl_tx_pkt_core);
6596 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6597 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6600 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6601 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6602 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6603 V_FW_WR_FLOWID(cst->etid));
6605 if (needs_outer_udp_csum(m0)) {
6606 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6607 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6608 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6609 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6610 wr->u.udpseg.rtplen = 0;
6611 wr->u.udpseg.r4 = 0;
6612 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6613 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6614 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6615 cpl = (void *)(wr + 1);
6617 MPASS(needs_outer_tcp_csum(m0));
6618 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6619 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6620 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6621 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6622 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6623 wr->u.tcpseg.r4 = 0;
6624 wr->u.tcpseg.r5 = 0;
6625 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6627 if (needs_tso(m0)) {
6628 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6630 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6632 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6633 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6634 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6635 ETHER_HDR_LEN) >> 2) |
6636 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6637 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6638 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6640 lso->lso_ctrl = htobe32(ctrl);
6641 lso->ipid_ofst = htobe16(0);
6642 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6643 lso->seqno_offset = htobe32(0);
6644 lso->len = htobe32(pktlen);
6646 cpl = (void *)(lso + 1);
6648 wr->u.tcpseg.mss = htobe16(0xffff);
6649 cpl = (void *)(wr + 1);
6653 /* Checksum offload must be requested for ethofld. */
6654 MPASS(needs_outer_l4_csum(m0));
6655 ctrl1 = csum_to_ctrl(cst->adapter, m0);
6657 /* VLAN tag insertion */
6658 if (needs_vlan_insertion(m0)) {
6659 ctrl1 |= F_TXPKT_VLAN_VLD |
6660 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6664 cpl->ctrl0 = cst->ctrl0;
6666 cpl->len = htobe16(pktlen);
6667 cpl->ctrl1 = htobe64(ctrl1);
6669 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6670 p = (uintptr_t)(cpl + 1);
6671 m_copydata(m0, 0, immhdrs, (void *)p);
6677 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6679 pad = 16 - (immhdrs & 0xf);
6680 bzero((void *)p, pad);
6682 usgl = (void *)(p + pad);
6683 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6684 V_ULPTX_NSGE(nsegs));
6686 sglist_init(&sg, nitems(segs), segs);
6687 for (; m0 != NULL; m0 = m0->m_next) {
6688 if (__predict_false(m0->m_len == 0))
6690 if (immhdrs >= m0->m_len) {
6691 immhdrs -= m0->m_len;
6694 if (m0->m_flags & M_EXTPG)
6695 sglist_append_mbuf_epg(&sg, m0,
6696 mtod(m0, vm_offset_t), m0->m_len);
6698 sglist_append(&sg, mtod(m0, char *) + immhdrs,
6699 m0->m_len - immhdrs);
6702 MPASS(sg.sg_nseg == nsegs);
6705 * Zero pad last 8B in case the WR doesn't end on a 16B
6708 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6710 usgl->len0 = htobe32(segs[0].ss_len);
6711 usgl->addr0 = htobe64(segs[0].ss_paddr);
6712 for (i = 0; i < nsegs - 1; i++) {
6713 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6714 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6717 usgl->sge[i / 2].len[1] = htobe32(0);
6723 ethofld_tx(struct cxgbe_rate_tag *cst)
6726 struct wrq_cookie cookie;
6727 int next_credits, compl;
6728 struct fw_eth_tx_eo_wr *wr;
6730 mtx_assert(&cst->lock, MA_OWNED);
6732 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6735 /* How many len16 credits do we need to send this mbuf. */
6736 next_credits = mbuf_eo_len16(m);
6737 MPASS(next_credits > 0);
6738 if (next_credits > cst->tx_credits) {
6740 * Tx will make progress eventually because there is at
6741 * least one outstanding fw4_ack that will return
6742 * credits and kick the tx.
6744 MPASS(cst->ncompl > 0);
6747 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie);
6748 if (__predict_false(wr == NULL)) {
6749 /* XXX: wishful thinking, not a real assertion. */
6750 MPASS(cst->ncompl > 0);
6753 cst->tx_credits -= next_credits;
6754 cst->tx_nocompl += next_credits;
6755 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6756 ETHER_BPF_MTAP(cst->com.ifp, m);
6757 write_ethofld_wr(cst, wr, m, compl);
6758 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie);
6761 cst->tx_nocompl = 0;
6763 (void) mbufq_dequeue(&cst->pending_tx);
6766 * Drop the mbuf's reference on the tag now rather
6767 * than waiting until m_freem(). This ensures that
6768 * cxgbe_rate_tag_free gets called when the inp drops
6769 * its reference on the tag and there are no more
6770 * mbufs in the pending_tx queue and can flush any
6771 * pending requests. Otherwise if the last mbuf
6772 * doesn't request a completion the etid will never be
6775 m->m_pkthdr.snd_tag = NULL;
6776 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6777 m_snd_tag_rele(&cst->com);
6779 mbufq_enqueue(&cst->pending_fwack, m);
6783 #if defined(INET) || defined(INET6)
6785 ethofld_transmit(if_t ifp, struct mbuf *m0)
6787 struct cxgbe_rate_tag *cst;
6790 MPASS(m0->m_nextpkt == NULL);
6791 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6792 MPASS(m0->m_pkthdr.snd_tag != NULL);
6793 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6795 mtx_lock(&cst->lock);
6796 MPASS(cst->flags & EO_SND_TAG_REF);
6798 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6799 struct vi_info *vi = if_getsoftc(ifp);
6800 struct port_info *pi = vi->pi;
6801 struct adapter *sc = pi->adapter;
6802 const uint32_t rss_mask = vi->rss_size - 1;
6805 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6806 if (M_HASHTYPE_ISHASH(m0))
6807 rss_hash = m0->m_pkthdr.flowid;
6809 rss_hash = arc4random();
6810 /* We assume RSS hashing */
6811 cst->iqid = vi->rss[rss_hash & rss_mask];
6812 cst->eo_txq += rss_hash % vi->nofldtxq;
6813 rc = send_etid_flowc_wr(cst, pi, vi);
6818 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6823 mbufq_enqueue(&cst->pending_tx, m0);
6824 cst->plen += m0->m_pkthdr.len;
6827 * Hold an extra reference on the tag while generating work
6828 * requests to ensure that we don't try to free the tag during
6829 * ethofld_tx() in case we are sending the final mbuf after
6830 * the inp was freed.
6832 m_snd_tag_ref(&cst->com);
6834 mtx_unlock(&cst->lock);
6835 m_snd_tag_rele(&cst->com);
6839 mtx_unlock(&cst->lock);
6845 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6847 struct adapter *sc = iq->adapter;
6848 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6850 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6851 struct cxgbe_rate_tag *cst;
6852 uint8_t credits = cpl->credits;
6854 cst = lookup_etid(sc, etid);
6855 mtx_lock(&cst->lock);
6856 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6857 MPASS(credits >= ETID_FLOWC_LEN16);
6858 credits -= ETID_FLOWC_LEN16;
6859 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6862 KASSERT(cst->ncompl > 0,
6863 ("%s: etid %u (%p) wasn't expecting completion.",
6864 __func__, etid, cst));
6867 while (credits > 0) {
6868 m = mbufq_dequeue(&cst->pending_fwack);
6869 if (__predict_false(m == NULL)) {
6871 * The remaining credits are for the final flush that
6872 * was issued when the tag was freed by the kernel.
6875 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6876 EO_FLUSH_RPL_PENDING);
6877 MPASS(credits == ETID_FLUSH_LEN16);
6878 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6879 MPASS(cst->ncompl == 0);
6881 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6882 cst->tx_credits += cpl->credits;
6883 cxgbe_rate_tag_free_locked(cst);
6884 return (0); /* cst is gone. */
6887 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6889 KASSERT(credits >= mbuf_eo_len16(m),
6890 ("%s: too few credits (%u, %u, %u)", __func__,
6891 cpl->credits, credits, mbuf_eo_len16(m)));
6892 credits -= mbuf_eo_len16(m);
6893 cst->plen -= m->m_pkthdr.len;
6897 cst->tx_credits += cpl->credits;
6898 MPASS(cst->tx_credits <= cst->tx_total);
6900 if (cst->flags & EO_SND_TAG_REF) {
6902 * As with ethofld_transmit(), hold an extra reference
6903 * so that the tag is stable across ethold_tx().
6905 m_snd_tag_ref(&cst->com);
6906 m = mbufq_first(&cst->pending_tx);
6907 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6909 mtx_unlock(&cst->lock);
6910 m_snd_tag_rele(&cst->com);
6913 * There shouldn't be any pending packets if the tag
6914 * was freed by the kernel since any pending packet
6915 * should hold a reference to the tag.
6917 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6918 mtx_unlock(&cst->lock);