2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/in_cksum.h>
57 #include <machine/md_var.h>
61 #include <machine/bus.h>
62 #include <sys/selinfo.h>
63 #include <net/if_var.h>
64 #include <net/netmap.h>
65 #include <dev/netmap/netmap_kern.h>
68 #include "common/common.h"
69 #include "common/t4_regs.h"
70 #include "common/t4_regs_values.h"
71 #include "common/t4_msg.h"
73 #include "t4_mp_ring.h"
75 #ifdef T4_PKT_TIMESTAMP
76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
78 #define RX_COPY_THRESHOLD MINCLSIZE
82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
83 * 0-7 are valid values.
85 static int fl_pktshift = 2;
86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
89 * Pad ethernet payload up to this boundary.
90 * -1: driver should figure out a good value.
92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
99 * -1: driver should figure out a good value.
100 * 64 or 128 are the only other valid values.
102 static int spg_len = -1;
103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
107 * -1: no congestion feedback (not recommended).
108 * 0: backpressure the channel instead of dropping packets right away.
109 * 1: no backpressure, drop packets for the congested queue immediately.
111 static int cong_drop = 0;
112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
115 * Deliver multiple frames in the same free list buffer if they fit.
116 * -1: let the driver decide whether to enable buffer packing or not.
117 * 0: disable buffer packing.
118 * 1: enable buffer packing.
120 static int buffer_packing = -1;
121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
124 * Start next frame in a packed buffer at this boundary.
125 * -1: driver should figure out a good value.
126 * T4: driver will ignore this and use the same value as fl_pad above.
127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
129 static int fl_pack = -1;
130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
133 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
135 * 1: ok to create mbuf(s) within a cluster if there is room.
137 static int allow_mbufs_in_cluster = 1;
138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
141 * Largest rx cluster size that the driver is allowed to allocate.
143 static int largest_rx_cluster = MJUM16BYTES;
144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
147 * Size of cluster allocation that's most likely to succeed. The driver will
148 * fall back to this size if it fails to allocate clusters larger than this.
150 static int safest_rx_cluster = PAGE_SIZE;
151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
154 u_int wr_type; /* type 0 or type 1 */
155 u_int npkt; /* # of packets in this work request */
156 u_int plen; /* total payload (sum of all packets) */
157 u_int len16; /* # of 16B pieces used by this work request */
160 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
163 struct sglist_seg seg[TX_SGL_SEGS];
166 static int service_iq(struct sge_iq *, int);
167 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
168 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
169 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
170 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
171 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
173 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
174 bus_addr_t *, void **);
175 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
177 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
179 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
180 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
181 struct sysctl_oid *, struct sge_fl *);
182 static int alloc_fwq(struct adapter *);
183 static int free_fwq(struct adapter *);
184 static int alloc_mgmtq(struct adapter *);
185 static int free_mgmtq(struct adapter *);
186 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
187 struct sysctl_oid *);
188 static int free_rxq(struct vi_info *, struct sge_rxq *);
190 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
191 struct sysctl_oid *);
192 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
195 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
196 struct sysctl_oid *);
197 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
198 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
199 struct sysctl_oid *);
200 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
202 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
203 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
205 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
207 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
208 static int free_eq(struct adapter *, struct sge_eq *);
209 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
210 struct sysctl_oid *);
211 static int free_wrq(struct adapter *, struct sge_wrq *);
212 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
213 struct sysctl_oid *);
214 static int free_txq(struct vi_info *, struct sge_txq *);
215 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
216 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
217 static int refill_fl(struct adapter *, struct sge_fl *, int);
218 static void refill_sfl(void *);
219 static int alloc_fl_sdesc(struct sge_fl *);
220 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
221 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
222 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
223 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
225 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
226 static inline u_int txpkt_len16(u_int, u_int);
227 static inline u_int txpkt_vm_len16(u_int, u_int);
228 static inline u_int txpkts0_len16(u_int);
229 static inline u_int txpkts1_len16(void);
230 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
231 struct mbuf *, u_int);
232 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
233 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
234 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
235 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
236 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
237 struct mbuf *, const struct txpkts *, u_int);
238 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
239 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
240 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
241 static inline uint16_t read_hw_cidx(struct sge_eq *);
242 static inline u_int reclaimable_tx_desc(struct sge_eq *);
243 static inline u_int total_available_tx_desc(struct sge_eq *);
244 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
245 static void tx_reclaim(void *, int);
246 static __be64 get_flit(struct sglist_seg *, int, int);
247 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
249 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
251 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
252 static void wrq_tx_drain(void *, int);
253 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
255 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
256 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
257 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
259 static counter_u64_t extfree_refs;
260 static counter_u64_t extfree_rels;
262 an_handler_t t4_an_handler;
263 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
264 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
268 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
272 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
274 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
281 t4_register_an_handler(an_handler_t h)
285 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
286 loc = (uintptr_t *) &t4_an_handler;
287 atomic_store_rel_ptr(loc, new);
293 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
295 const struct cpl_fw6_msg *cpl =
296 __containerof(rpl, struct cpl_fw6_msg, data[0]);
299 panic("%s: fw_msg type %d", __func__, cpl->type);
301 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
307 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
311 if (type >= nitems(t4_fw_msg_handler))
315 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
316 * handler dispatch table. Reject any attempt to install a handler for
319 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
322 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
323 loc = (uintptr_t *) &t4_fw_msg_handler[type];
324 atomic_store_rel_ptr(loc, new);
330 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
334 panic("%s: opcode 0x%02x on iq %p with payload %p",
335 __func__, rss->opcode, iq, m);
337 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
338 __func__, rss->opcode, iq, m);
345 t4_register_cpl_handler(int opcode, cpl_handler_t h)
349 if (opcode >= nitems(t4_cpl_handler))
352 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
353 loc = (uintptr_t *) &t4_cpl_handler[opcode];
354 atomic_store_rel_ptr(loc, new);
360 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
367 if (fl_pktshift < 0 || fl_pktshift > 7) {
368 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
369 " using 2 instead.\n", fl_pktshift);
373 if (spg_len != 64 && spg_len != 128) {
376 #if defined(__i386__) || defined(__amd64__)
377 len = cpu_clflush_line_size > 64 ? 128 : 64;
382 printf("Invalid hw.cxgbe.spg_len value (%d),"
383 " using %d instead.\n", spg_len, len);
388 if (cong_drop < -1 || cong_drop > 1) {
389 printf("Invalid hw.cxgbe.cong_drop value (%d),"
390 " using 0 instead.\n", cong_drop);
394 extfree_refs = counter_u64_alloc(M_WAITOK);
395 extfree_rels = counter_u64_alloc(M_WAITOK);
396 counter_u64_zero(extfree_refs);
397 counter_u64_zero(extfree_rels);
399 t4_an_handler = an_not_handled;
400 for (i = 0; i < nitems(t4_fw_msg_handler); i++)
401 t4_fw_msg_handler[i] = fw_msg_not_handled;
402 for (i = 0; i < nitems(t4_cpl_handler); i++)
403 t4_cpl_handler[i] = cpl_not_handled;
405 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
406 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
407 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
408 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
409 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
410 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
414 t4_sge_modunload(void)
417 counter_u64_free(extfree_refs);
418 counter_u64_free(extfree_rels);
422 t4_sge_extfree_refs(void)
426 rels = counter_u64_fetch(extfree_rels);
427 refs = counter_u64_fetch(extfree_refs);
429 return (refs - rels);
433 setup_pad_and_pack_boundaries(struct adapter *sc)
436 int pad, pack, pad_shift;
438 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
439 X_INGPADBOUNDARY_SHIFT;
441 if (fl_pad < (1 << pad_shift) ||
442 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
445 * If there is any chance that we might use buffer packing and
446 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
447 * it to the minimum allowed in all other cases.
449 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
452 * For fl_pad = 0 we'll still write a reasonable value to the
453 * register but all the freelists will opt out of padding.
454 * We'll complain here only if the user tried to set it to a
455 * value greater than 0 that was invalid.
458 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
459 " (%d), using %d instead.\n", fl_pad, pad);
462 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
463 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
464 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
467 if (fl_pack != -1 && fl_pack != pad) {
468 /* Complain but carry on. */
469 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
470 " using %d instead.\n", fl_pack, pad);
476 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
477 !powerof2(fl_pack)) {
478 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
479 MPASS(powerof2(pack));
487 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
488 " (%d), using %d instead.\n", fl_pack, pack);
491 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
493 v = V_INGPACKBOUNDARY(0);
495 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
497 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
498 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
502 * adap->params.vpd.cclk must be set up before this is called.
505 t4_tweak_chip_settings(struct adapter *sc)
509 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
510 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
511 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
512 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
513 static int sge_flbuf_sizes[] = {
515 #if MJUMPAGESIZE != MCLBYTES
517 MJUMPAGESIZE - CL_METADATA_SIZE,
518 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
522 MCLBYTES - MSIZE - CL_METADATA_SIZE,
523 MJUM9BYTES - CL_METADATA_SIZE,
524 MJUM16BYTES - CL_METADATA_SIZE,
527 KASSERT(sc->flags & MASTER_PF,
528 ("%s: trying to change chip settings when not master.", __func__));
530 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
531 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
532 V_EGRSTATUSPAGESIZE(spg_len == 128);
533 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
535 setup_pad_and_pack_boundaries(sc);
537 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
538 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
539 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
540 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
541 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
542 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
543 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
544 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
545 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
547 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
548 ("%s: hw buffer size table too big", __func__));
549 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
550 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
554 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
555 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
556 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
558 KASSERT(intr_timer[0] <= timer_max,
559 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
561 for (i = 1; i < nitems(intr_timer); i++) {
562 KASSERT(intr_timer[i] >= intr_timer[i - 1],
563 ("%s: timers not listed in increasing order (%d)",
566 while (intr_timer[i] > timer_max) {
567 if (i == nitems(intr_timer) - 1) {
568 intr_timer[i] = timer_max;
571 intr_timer[i] += intr_timer[i - 1];
576 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
577 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
578 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
579 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
580 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
581 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
582 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
583 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
584 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
586 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
587 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
588 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
591 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
592 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
593 * may have to deal with is MAXPHYS + 1 page.
595 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
596 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
598 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
599 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
600 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
602 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
604 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
605 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
609 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
610 * padding is in use, the buffer's start and end need to be aligned to the pad
611 * boundary as well. We'll just make sure that the size is a multiple of the
612 * boundary here, it is up to the buffer allocation code to make sure the start
613 * of the buffer is aligned as well.
616 hwsz_ok(struct adapter *sc, int hwsz)
618 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
620 return (hwsz >= 64 && (hwsz & mask) == 0);
624 * XXX: driver really should be able to deal with unexpected settings.
627 t4_read_chip_settings(struct adapter *sc)
629 struct sge *s = &sc->sge;
630 struct sge_params *sp = &sc->params.sge;
633 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
634 static int sw_buf_sizes[] = { /* Sorted by size */
636 #if MJUMPAGESIZE != MCLBYTES
642 struct sw_zone_info *swz, *safe_swz;
643 struct hw_buf_info *hwb;
647 r = sc->params.sge.sge_control;
649 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
654 * If this changes then every single use of PAGE_SHIFT in the driver
655 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
657 if (sp->page_shift != PAGE_SHIFT) {
658 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
662 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
663 hwb = &s->hw_buf_info[0];
664 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
665 r = sc->params.sge.sge_fl_buffer_size[i];
667 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
672 * Create a sorted list in decreasing order of hw buffer sizes (and so
673 * increasing order of spare area) for each software zone.
675 * If padding is enabled then the start and end of the buffer must align
676 * to the pad boundary; if packing is enabled then they must align with
677 * the pack boundary as well. Allocations from the cluster zones are
678 * aligned to min(size, 4K), so the buffer starts at that alignment and
679 * ends at hwb->size alignment. If mbuf inlining is allowed the
680 * starting alignment will be reduced to MSIZE and the driver will
681 * exercise appropriate caution when deciding on the best buffer layout
684 n = 0; /* no usable buffer size to begin with */
685 swz = &s->sw_zone_info[0];
687 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
688 int8_t head = -1, tail = -1;
690 swz->size = sw_buf_sizes[i];
691 swz->zone = m_getzone(swz->size);
692 swz->type = m_gettype(swz->size);
694 if (swz->size < PAGE_SIZE) {
695 MPASS(powerof2(swz->size));
696 if (fl_pad && (swz->size % sp->pad_boundary != 0))
700 if (swz->size == safest_rx_cluster)
703 hwb = &s->hw_buf_info[0];
704 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
705 if (hwb->zidx != -1 || hwb->size > swz->size)
709 MPASS(hwb->size % sp->pad_boundary == 0);
714 else if (hwb->size < s->hw_buf_info[tail].size) {
715 s->hw_buf_info[tail].next = j;
719 struct hw_buf_info *t;
721 for (cur = &head; *cur != -1; cur = &t->next) {
722 t = &s->hw_buf_info[*cur];
723 if (hwb->size == t->size) {
727 if (hwb->size > t->size) {
735 swz->head_hwidx = head;
736 swz->tail_hwidx = tail;
740 if (swz->size - s->hw_buf_info[tail].size >=
742 sc->flags |= BUF_PACKING_OK;
746 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
752 if (safe_swz != NULL) {
753 s->safe_hwidx1 = safe_swz->head_hwidx;
754 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
757 hwb = &s->hw_buf_info[i];
760 MPASS(hwb->size % sp->pad_boundary == 0);
762 spare = safe_swz->size - hwb->size;
763 if (spare >= CL_METADATA_SIZE) {
770 if (sc->flags & IS_VF)
773 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
774 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
776 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
780 m = v = F_TDDPTAGTCB;
781 r = t4_read_reg(sc, A_ULP_RX_CTL);
783 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
787 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
789 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
790 r = t4_read_reg(sc, A_TP_PARA_REG5);
792 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
796 t4_init_tp_params(sc);
798 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
799 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
805 t4_create_dma_tag(struct adapter *sc)
809 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
810 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
811 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
814 device_printf(sc->dev,
815 "failed to create main DMA tag: %d\n", rc);
822 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
823 struct sysctl_oid_list *children)
825 struct sge_params *sp = &sc->params.sge;
827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
828 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
829 "freelist buffer sizes");
831 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
832 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
834 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
835 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
837 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
838 NULL, sp->spg_len, "status page size (bytes)");
840 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
841 NULL, cong_drop, "congestion drop setting");
843 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
844 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
848 t4_destroy_dma_tag(struct adapter *sc)
851 bus_dma_tag_destroy(sc->dmat);
857 * Allocate and initialize the firmware event queue and the management queue.
859 * Returns errno on failure. Resources allocated up to that point may still be
860 * allocated. Caller is responsible for cleanup in case this function fails.
863 t4_setup_adapter_queues(struct adapter *sc)
867 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
869 sysctl_ctx_init(&sc->ctx);
870 sc->flags |= ADAP_SYSCTL_CTX;
873 * Firmware event queue
880 * Management queue. This is just a control queue that uses the fwq as
883 if (!(sc->flags & IS_VF))
884 rc = alloc_mgmtq(sc);
893 t4_teardown_adapter_queues(struct adapter *sc)
896 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
898 /* Do this before freeing the queue */
899 if (sc->flags & ADAP_SYSCTL_CTX) {
900 sysctl_ctx_free(&sc->ctx);
901 sc->flags &= ~ADAP_SYSCTL_CTX;
911 first_vector(struct vi_info *vi)
913 struct adapter *sc = vi->pi->adapter;
915 if (sc->intr_count == 1)
918 return (vi->first_intr);
922 * Given an arbitrary "index," come up with an iq that can be used by other
923 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
924 * The iq returned is guaranteed to be something that takes direct interrupts.
926 static struct sge_iq *
927 vi_intr_iq(struct vi_info *vi, int idx)
929 struct adapter *sc = vi->pi->adapter;
930 struct sge *s = &sc->sge;
931 struct sge_iq *iq = NULL;
934 if (sc->intr_count == 1)
935 return (&sc->sge.fwq);
939 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
940 __func__, vi, sc->intr_count));
943 if (vi->flags & INTR_RXQ) {
945 iq = &s->rxq[vi->first_rxq + i].iq;
951 if (vi->flags & INTR_OFLD_RXQ) {
952 if (i < vi->nofldrxq) {
953 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
959 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
960 vi, vi->flags & INTR_ALL, idx, nintr);
963 KASSERT(iq->flags & IQ_INTR,
964 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
965 vi->flags & INTR_ALL, idx));
969 /* Maximum payload that can be delivered with a single iq descriptor */
971 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
977 payload = sc->tt.rx_coalesce ?
978 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
981 /* large enough even when hw VLAN extraction is disabled */
982 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
983 ETHER_VLAN_ENCAP_LEN + mtu;
992 t4_setup_vi_queues(struct vi_info *vi)
994 int rc = 0, i, j, intr_idx, iqid;
997 struct sge_wrq *ctrlq;
999 struct sge_ofld_rxq *ofld_rxq;
1000 struct sge_wrq *ofld_txq;
1004 struct sge_nm_rxq *nm_rxq;
1005 struct sge_nm_txq *nm_txq;
1008 struct port_info *pi = vi->pi;
1009 struct adapter *sc = pi->adapter;
1010 struct ifnet *ifp = vi->ifp;
1011 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1012 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1013 int maxp, mtu = ifp->if_mtu;
1015 /* Interrupt vector to start from (when using multiple vectors) */
1016 intr_idx = first_vector(vi);
1019 saved_idx = intr_idx;
1020 if (ifp->if_capabilities & IFCAP_NETMAP) {
1022 /* netmap is supported with direct interrupts only. */
1023 MPASS(vi->flags & INTR_RXQ);
1026 * We don't have buffers to back the netmap rx queues
1027 * right now so we create the queues in a way that
1028 * doesn't set off any congestion signal in the chip.
1030 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1031 CTLFLAG_RD, NULL, "rx queues");
1032 for_each_nm_rxq(vi, i, nm_rxq) {
1033 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1039 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1040 CTLFLAG_RD, NULL, "tx queues");
1041 for_each_nm_txq(vi, i, nm_txq) {
1042 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
1043 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
1049 /* Normal rx queues and netmap rx queues share the same interrupts. */
1050 intr_idx = saved_idx;
1054 * First pass over all NIC and TOE rx queues:
1055 * a) initialize iq and fl
1056 * b) allocate queue iff it will take direct interrupts.
1058 maxp = mtu_to_max_payload(sc, mtu, 0);
1059 if (vi->flags & INTR_RXQ) {
1060 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1061 CTLFLAG_RD, NULL, "rx queues");
1063 for_each_rxq(vi, i, rxq) {
1065 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1067 snprintf(name, sizeof(name), "%s rxq%d-fl",
1068 device_get_nameunit(vi->dev), i);
1069 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1071 if (vi->flags & INTR_RXQ) {
1072 rxq->iq.flags |= IQ_INTR;
1073 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1080 if (ifp->if_capabilities & IFCAP_NETMAP)
1081 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1084 maxp = mtu_to_max_payload(sc, mtu, 1);
1085 if (vi->flags & INTR_OFLD_RXQ) {
1086 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1088 "rx queues for offloaded TCP connections");
1090 for_each_ofld_rxq(vi, i, ofld_rxq) {
1092 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
1095 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1096 device_get_nameunit(vi->dev), i);
1097 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1099 if (vi->flags & INTR_OFLD_RXQ) {
1100 ofld_rxq->iq.flags |= IQ_INTR;
1101 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1110 * Second pass over all NIC and TOE rx queues. The queues forwarding
1111 * their interrupts are allocated now.
1114 if (!(vi->flags & INTR_RXQ)) {
1115 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1116 CTLFLAG_RD, NULL, "rx queues");
1117 for_each_rxq(vi, i, rxq) {
1118 MPASS(!(rxq->iq.flags & IQ_INTR));
1120 intr_idx = vi_intr_iq(vi, j)->abs_id;
1122 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1129 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1130 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1132 "rx queues for offloaded TCP connections");
1133 for_each_ofld_rxq(vi, i, ofld_rxq) {
1134 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1136 intr_idx = vi_intr_iq(vi, j)->abs_id;
1138 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1147 * Now the tx queues. Only one pass needed.
1149 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1152 for_each_txq(vi, i, txq) {
1153 iqid = vi_intr_iq(vi, j)->cntxt_id;
1154 snprintf(name, sizeof(name), "%s txq%d",
1155 device_get_nameunit(vi->dev), i);
1156 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1159 rc = alloc_txq(vi, txq, i, oid);
1165 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1166 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1167 for_each_ofld_txq(vi, i, ofld_txq) {
1168 struct sysctl_oid *oid2;
1170 iqid = vi_intr_iq(vi, j)->cntxt_id;
1171 snprintf(name, sizeof(name), "%s ofld_txq%d",
1172 device_get_nameunit(vi->dev), i);
1173 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1176 snprintf(name, sizeof(name), "%d", i);
1177 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1178 name, CTLFLAG_RD, NULL, "offload tx queue");
1180 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1188 * Finally, the control queue.
1190 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1192 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1193 NULL, "ctrl queue");
1194 ctrlq = &sc->sge.ctrlq[pi->port_id];
1195 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1196 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1197 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1199 rc = alloc_wrq(sc, vi, ctrlq, oid);
1203 t4_teardown_vi_queues(vi);
1212 t4_teardown_vi_queues(struct vi_info *vi)
1215 struct port_info *pi = vi->pi;
1216 struct adapter *sc = pi->adapter;
1217 struct sge_rxq *rxq;
1218 struct sge_txq *txq;
1220 struct sge_ofld_rxq *ofld_rxq;
1221 struct sge_wrq *ofld_txq;
1224 struct sge_nm_rxq *nm_rxq;
1225 struct sge_nm_txq *nm_txq;
1228 /* Do this before freeing the queues */
1229 if (vi->flags & VI_SYSCTL_CTX) {
1230 sysctl_ctx_free(&vi->ctx);
1231 vi->flags &= ~VI_SYSCTL_CTX;
1235 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1236 for_each_nm_txq(vi, i, nm_txq) {
1237 free_nm_txq(vi, nm_txq);
1240 for_each_nm_rxq(vi, i, nm_rxq) {
1241 free_nm_rxq(vi, nm_rxq);
1247 * Take down all the tx queues first, as they reference the rx queues
1248 * (for egress updates, etc.).
1251 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1252 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1254 for_each_txq(vi, i, txq) {
1258 for_each_ofld_txq(vi, i, ofld_txq) {
1259 free_wrq(sc, ofld_txq);
1264 * Then take down the rx queues that forward their interrupts, as they
1265 * reference other rx queues.
1268 for_each_rxq(vi, i, rxq) {
1269 if ((rxq->iq.flags & IQ_INTR) == 0)
1273 for_each_ofld_rxq(vi, i, ofld_rxq) {
1274 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1275 free_ofld_rxq(vi, ofld_rxq);
1280 * Then take down the rx queues that take direct interrupts.
1283 for_each_rxq(vi, i, rxq) {
1284 if (rxq->iq.flags & IQ_INTR)
1288 for_each_ofld_rxq(vi, i, ofld_rxq) {
1289 if (ofld_rxq->iq.flags & IQ_INTR)
1290 free_ofld_rxq(vi, ofld_rxq);
1298 * Deals with errors and the firmware event queue. All data rx queues forward
1299 * their interrupt to the firmware event queue.
1302 t4_intr_all(void *arg)
1304 struct adapter *sc = arg;
1305 struct sge_iq *fwq = &sc->sge.fwq;
1308 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1310 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1314 /* Deals with error interrupts */
1316 t4_intr_err(void *arg)
1318 struct adapter *sc = arg;
1320 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1321 t4_slow_intr_handler(sc);
1325 t4_intr_evt(void *arg)
1327 struct sge_iq *iq = arg;
1329 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1331 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1338 struct sge_iq *iq = arg;
1340 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1342 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1347 t4_vi_intr(void *arg)
1349 struct irq *irq = arg;
1352 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1353 t4_nm_intr(irq->nm_rxq);
1354 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1357 if (irq->rxq != NULL)
1362 * Deals with anything and everything on the given ingress queue.
1365 service_iq(struct sge_iq *iq, int budget)
1368 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1369 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1370 struct adapter *sc = iq->adapter;
1371 struct iq_desc *d = &iq->desc[iq->cidx];
1372 int ndescs = 0, limit;
1373 int rsp_type, refill;
1375 uint16_t fl_hw_cidx;
1377 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1378 #if defined(INET) || defined(INET6)
1379 const struct timeval lro_timeout = {0, sc->lro_timeout};
1382 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1384 limit = budget ? budget : iq->qsize / 16;
1386 if (iq->flags & IQ_HAS_FL) {
1388 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1391 fl_hw_cidx = 0; /* to silence gcc warning */
1395 * We always come back and check the descriptor ring for new indirect
1396 * interrupts and other responses after running a single handler.
1399 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1405 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1406 lq = be32toh(d->rsp.pldbuflen_qid);
1409 case X_RSPD_TYPE_FLBUF:
1411 KASSERT(iq->flags & IQ_HAS_FL,
1412 ("%s: data for an iq (%p) with no freelist",
1415 m0 = get_fl_payload(sc, fl, lq);
1416 if (__predict_false(m0 == NULL))
1418 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1419 #ifdef T4_PKT_TIMESTAMP
1421 * 60 bit timestamp for the payload is
1422 * *(uint64_t *)m0->m_pktdat. Note that it is
1423 * in the leading free-space in the mbuf. The
1424 * kernel can clobber it during a pullup,
1425 * m_copymdata, etc. You need to make sure that
1426 * the mbuf reaches you unmolested if you care
1427 * about the timestamp.
1429 *(uint64_t *)m0->m_pktdat =
1430 be64toh(ctrl->u.last_flit) &
1436 case X_RSPD_TYPE_CPL:
1437 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1438 ("%s: bad opcode %02x.", __func__,
1440 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1443 case X_RSPD_TYPE_INTR:
1446 * Interrupts should be forwarded only to queues
1447 * that are not forwarding their interrupts.
1448 * This means service_iq can recurse but only 1
1451 KASSERT(budget == 0,
1452 ("%s: budget %u, rsp_type %u", __func__,
1456 * There are 1K interrupt-capable queues (qids 0
1457 * through 1023). A response type indicating a
1458 * forwarded interrupt with a qid >= 1K is an
1459 * iWARP async notification.
1462 t4_an_handler(iq, &d->rsp);
1466 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1468 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1470 if (service_iq(q, q->qsize / 16) == 0) {
1471 atomic_cmpset_int(&q->state,
1472 IQS_BUSY, IQS_IDLE);
1474 STAILQ_INSERT_TAIL(&iql, q,
1482 ("%s: illegal response type %d on iq %p",
1483 __func__, rsp_type, iq));
1485 "%s: illegal response type %d on iq %p",
1486 device_get_nameunit(sc->dev), rsp_type, iq);
1491 if (__predict_false(++iq->cidx == iq->sidx)) {
1493 iq->gen ^= F_RSPD_GEN;
1496 if (__predict_false(++ndescs == limit)) {
1497 t4_write_reg(sc, sc->sge_gts_reg,
1499 V_INGRESSQID(iq->cntxt_id) |
1500 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1503 #if defined(INET) || defined(INET6)
1504 if (iq->flags & IQ_LRO_ENABLED &&
1505 sc->lro_timeout != 0) {
1506 tcp_lro_flush_inactive(&rxq->lro,
1512 if (iq->flags & IQ_HAS_FL) {
1514 refill_fl(sc, fl, 32);
1517 return (EINPROGRESS);
1522 refill_fl(sc, fl, 32);
1524 fl_hw_cidx = fl->hw_cidx;
1529 if (STAILQ_EMPTY(&iql))
1533 * Process the head only, and send it to the back of the list if
1534 * it's still not done.
1536 q = STAILQ_FIRST(&iql);
1537 STAILQ_REMOVE_HEAD(&iql, link);
1538 if (service_iq(q, q->qsize / 8) == 0)
1539 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1541 STAILQ_INSERT_TAIL(&iql, q, link);
1544 #if defined(INET) || defined(INET6)
1545 if (iq->flags & IQ_LRO_ENABLED) {
1546 struct lro_ctrl *lro = &rxq->lro;
1548 tcp_lro_flush_all(lro);
1552 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1553 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1555 if (iq->flags & IQ_HAS_FL) {
1559 starved = refill_fl(sc, fl, 64);
1561 if (__predict_false(starved != 0))
1562 add_fl_to_sfl(sc, fl);
1569 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1571 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1574 MPASS(cll->region3 >= CL_METADATA_SIZE);
1579 static inline struct cluster_metadata *
1580 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1584 if (cl_has_metadata(fl, cll)) {
1585 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1587 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1593 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1595 uma_zone_t zone = arg1;
1598 uma_zfree(zone, cl);
1599 counter_u64_add(extfree_rels, 1);
1603 * The mbuf returned by this function could be allocated from zone_mbuf or
1604 * constructed in spare room in the cluster.
1606 * The mbuf carries the payload in one of these ways
1607 * a) frame inside the mbuf (mbuf from zone_mbuf)
1608 * b) m_cljset (for clusters without metadata) zone_mbuf
1609 * c) m_extaddref (cluster with metadata) inline mbuf
1610 * d) m_extaddref (cluster with metadata) zone_mbuf
1612 static struct mbuf *
1613 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1617 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1618 struct cluster_layout *cll = &sd->cll;
1619 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1620 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1621 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1625 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1626 len = min(remaining, blen);
1627 payload = sd->cl + cll->region1 + fl->rx_offset;
1628 if (fl->flags & FL_BUF_PACKING) {
1629 const u_int l = fr_offset + len;
1630 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1632 if (fl->rx_offset + len + pad < hwb->size)
1634 MPASS(fl->rx_offset + blen <= hwb->size);
1636 MPASS(fl->rx_offset == 0); /* not packing */
1640 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1643 * Copy payload into a freshly allocated mbuf.
1646 m = fr_offset == 0 ?
1647 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1650 fl->mbuf_allocated++;
1651 #ifdef T4_PKT_TIMESTAMP
1652 /* Leave room for a timestamp */
1655 /* copy data to mbuf */
1656 bcopy(payload, mtod(m, caddr_t), len);
1658 } else if (sd->nmbuf * MSIZE < cll->region1) {
1661 * There's spare room in the cluster for an mbuf. Create one
1662 * and associate it with the payload that's in the cluster.
1666 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1667 /* No bzero required */
1668 if (m_init(m, M_NOWAIT, MT_DATA,
1669 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1672 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1674 if (sd->nmbuf++ == 0)
1675 counter_u64_add(extfree_refs, 1);
1680 * Grab an mbuf from zone_mbuf and associate it with the
1681 * payload in the cluster.
1684 m = fr_offset == 0 ?
1685 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1688 fl->mbuf_allocated++;
1690 m_extaddref(m, payload, blen, &clm->refcount,
1691 rxb_free, swz->zone, sd->cl);
1692 if (sd->nmbuf++ == 0)
1693 counter_u64_add(extfree_refs, 1);
1695 m_cljset(m, sd->cl, swz->type);
1696 sd->cl = NULL; /* consumed, not a recycle candidate */
1700 m->m_pkthdr.len = remaining;
1703 if (fl->flags & FL_BUF_PACKING) {
1704 fl->rx_offset += blen;
1705 MPASS(fl->rx_offset <= hwb->size);
1706 if (fl->rx_offset < hwb->size)
1707 return (m); /* without advancing the cidx */
1710 if (__predict_false(++fl->cidx % 8 == 0)) {
1711 uint16_t cidx = fl->cidx / 8;
1713 if (__predict_false(cidx == fl->sidx))
1714 fl->cidx = cidx = 0;
1722 static struct mbuf *
1723 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1725 struct mbuf *m0, *m, **pnext;
1727 const u_int total = G_RSPD_LEN(len_newbuf);
1729 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1730 M_ASSERTPKTHDR(fl->m0);
1731 MPASS(fl->m0->m_pkthdr.len == total);
1732 MPASS(fl->remaining < total);
1736 remaining = fl->remaining;
1737 fl->flags &= ~FL_BUF_RESUME;
1741 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1743 if (__predict_false(++fl->cidx % 8 == 0)) {
1744 uint16_t cidx = fl->cidx / 8;
1746 if (__predict_false(cidx == fl->sidx))
1747 fl->cidx = cidx = 0;
1753 * Payload starts at rx_offset in the current hw buffer. Its length is
1754 * 'len' and it may span multiple hw buffers.
1757 m0 = get_scatter_segment(sc, fl, 0, total);
1760 remaining = total - m0->m_len;
1761 pnext = &m0->m_next;
1762 while (remaining > 0) {
1764 MPASS(fl->rx_offset == 0);
1765 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1766 if (__predict_false(m == NULL)) {
1769 fl->remaining = remaining;
1770 fl->flags |= FL_BUF_RESUME;
1775 remaining -= m->m_len;
1784 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1786 struct sge_rxq *rxq = iq_to_rxq(iq);
1787 struct ifnet *ifp = rxq->ifp;
1788 struct adapter *sc = iq->adapter;
1789 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1790 #if defined(INET) || defined(INET6)
1791 struct lro_ctrl *lro = &rxq->lro;
1793 static const int sw_hashtype[4][2] = {
1794 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1795 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1796 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1797 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1800 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1803 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1804 m0->m_len -= sc->params.sge.fl_pktshift;
1805 m0->m_data += sc->params.sge.fl_pktshift;
1807 m0->m_pkthdr.rcvif = ifp;
1808 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1809 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1811 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1812 if (ifp->if_capenable & IFCAP_RXCSUM &&
1813 cpl->l2info & htobe32(F_RXF_IP)) {
1814 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1815 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1817 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1818 cpl->l2info & htobe32(F_RXF_IP6)) {
1819 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1824 if (__predict_false(cpl->ip_frag))
1825 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1827 m0->m_pkthdr.csum_data = 0xffff;
1831 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1832 m0->m_flags |= M_VLANTAG;
1833 rxq->vlan_extraction++;
1836 #if defined(INET) || defined(INET6)
1837 if (iq->flags & IQ_LRO_ENABLED &&
1838 tcp_lro_rx(lro, m0, 0) == 0) {
1839 /* queued for LRO */
1842 ifp->if_input(ifp, m0);
1848 * Must drain the wrq or make sure that someone else will.
1851 wrq_tx_drain(void *arg, int n)
1853 struct sge_wrq *wrq = arg;
1854 struct sge_eq *eq = &wrq->eq;
1857 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1858 drain_wrq_wr_list(wrq->adapter, wrq);
1863 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1865 struct sge_eq *eq = &wrq->eq;
1866 u_int available, dbdiff; /* # of hardware descriptors */
1869 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1871 EQ_LOCK_ASSERT_OWNED(eq);
1872 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1873 wr = STAILQ_FIRST(&wrq->wr_list);
1874 MPASS(wr != NULL); /* Must be called with something useful to do */
1875 MPASS(eq->pidx == eq->dbidx);
1879 eq->cidx = read_hw_cidx(eq);
1880 if (eq->pidx == eq->cidx)
1881 available = eq->sidx - 1;
1883 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1885 MPASS(wr->wrq == wrq);
1886 n = howmany(wr->wr_len, EQ_ESIZE);
1890 dst = (void *)&eq->desc[eq->pidx];
1891 if (__predict_true(eq->sidx - eq->pidx > n)) {
1892 /* Won't wrap, won't end exactly at the status page. */
1893 bcopy(&wr->wr[0], dst, wr->wr_len);
1896 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1898 bcopy(&wr->wr[0], dst, first_portion);
1899 if (wr->wr_len > first_portion) {
1900 bcopy(&wr->wr[first_portion], &eq->desc[0],
1901 wr->wr_len - first_portion);
1903 eq->pidx = n - (eq->sidx - eq->pidx);
1905 wrq->tx_wrs_copied++;
1907 if (available < eq->sidx / 4 &&
1908 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1909 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1911 eq->equeqidx = eq->pidx;
1912 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1913 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1914 eq->equeqidx = eq->pidx;
1919 ring_eq_db(sc, eq, dbdiff);
1923 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1925 MPASS(wrq->nwr_pending > 0);
1927 MPASS(wrq->ndesc_needed >= n);
1928 wrq->ndesc_needed -= n;
1929 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1932 ring_eq_db(sc, eq, dbdiff);
1936 * Doesn't fail. Holds on to work requests it can't send right away.
1939 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1942 struct sge_eq *eq = &wrq->eq;
1945 EQ_LOCK_ASSERT_OWNED(eq);
1947 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1948 MPASS((wr->wr_len & 0x7) == 0);
1950 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1952 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1954 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1955 return; /* commit_wrq_wr will drain wr_list as well. */
1957 drain_wrq_wr_list(sc, wrq);
1959 /* Doorbell must have caught up to the pidx. */
1960 MPASS(eq->pidx == eq->dbidx);
1964 t4_update_fl_bufsize(struct ifnet *ifp)
1966 struct vi_info *vi = ifp->if_softc;
1967 struct adapter *sc = vi->pi->adapter;
1968 struct sge_rxq *rxq;
1970 struct sge_ofld_rxq *ofld_rxq;
1973 int i, maxp, mtu = ifp->if_mtu;
1975 maxp = mtu_to_max_payload(sc, mtu, 0);
1976 for_each_rxq(vi, i, rxq) {
1980 find_best_refill_source(sc, fl, maxp);
1984 maxp = mtu_to_max_payload(sc, mtu, 1);
1985 for_each_ofld_rxq(vi, i, ofld_rxq) {
1989 find_best_refill_source(sc, fl, maxp);
1996 mbuf_nsegs(struct mbuf *m)
2000 KASSERT(m->m_pkthdr.l5hlen > 0,
2001 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2003 return (m->m_pkthdr.l5hlen);
2007 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2011 m->m_pkthdr.l5hlen = nsegs;
2015 mbuf_len16(struct mbuf *m)
2020 n = m->m_pkthdr.PH_loc.eight[0];
2021 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2027 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2031 m->m_pkthdr.PH_loc.eight[0] = len16;
2035 needs_tso(struct mbuf *m)
2040 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2041 KASSERT(m->m_pkthdr.tso_segsz > 0,
2042 ("%s: TSO requested in mbuf %p but MSS not provided",
2051 needs_l3_csum(struct mbuf *m)
2056 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2062 needs_l4_csum(struct mbuf *m)
2067 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2068 CSUM_TCP_IPV6 | CSUM_TSO))
2074 needs_vlan_insertion(struct mbuf *m)
2079 if (m->m_flags & M_VLANTAG) {
2080 KASSERT(m->m_pkthdr.ether_vtag != 0,
2081 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2089 m_advance(struct mbuf **pm, int *poffset, int len)
2091 struct mbuf *m = *pm;
2092 int offset = *poffset;
2098 if (offset + len < m->m_len) {
2100 p = mtod(m, uintptr_t) + offset;
2103 len -= m->m_len - offset;
2114 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2115 * must have at least one mbuf that's not empty.
2118 count_mbuf_nsegs(struct mbuf *m)
2120 vm_paddr_t lastb, next;
2128 for (; m; m = m->m_next) {
2131 if (__predict_false(len == 0))
2133 va = mtod(m, vm_offset_t);
2134 next = pmap_kextract(va);
2135 nsegs += sglist_count(m->m_data, len);
2136 if (lastb + 1 == next)
2138 lastb = pmap_kextract(va + len - 1);
2146 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2147 * a) caller can assume it's been freed if this function returns with an error.
2148 * b) it may get defragged up if the gather list is too long for the hardware.
2151 parse_pkt(struct adapter *sc, struct mbuf **mp)
2153 struct mbuf *m0 = *mp, *m;
2154 int rc, nsegs, defragged = 0, offset;
2155 struct ether_header *eh;
2157 #if defined(INET) || defined(INET6)
2163 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2172 * First count the number of gather list segments in the payload.
2173 * Defrag the mbuf if nsegs exceeds the hardware limit.
2176 MPASS(m0->m_pkthdr.len > 0);
2177 nsegs = count_mbuf_nsegs(m0);
2178 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2179 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2183 *mp = m0 = m; /* update caller's copy after defrag */
2187 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2188 m0 = m_pullup(m0, m0->m_pkthdr.len);
2190 /* Should have left well enough alone. */
2194 *mp = m0; /* update caller's copy after pullup */
2197 set_mbuf_nsegs(m0, nsegs);
2198 if (sc->flags & IS_VF)
2199 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2201 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2203 if (!needs_tso(m0) &&
2204 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2208 eh = mtod(m, struct ether_header *);
2209 eh_type = ntohs(eh->ether_type);
2210 if (eh_type == ETHERTYPE_VLAN) {
2211 struct ether_vlan_header *evh = (void *)eh;
2213 eh_type = ntohs(evh->evl_proto);
2214 m0->m_pkthdr.l2hlen = sizeof(*evh);
2216 m0->m_pkthdr.l2hlen = sizeof(*eh);
2219 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2223 case ETHERTYPE_IPV6:
2225 struct ip6_hdr *ip6 = l3hdr;
2227 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2229 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2236 struct ip *ip = l3hdr;
2238 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2243 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2244 " with the same INET/INET6 options as the kernel.",
2248 #if defined(INET) || defined(INET6)
2249 if (needs_tso(m0)) {
2250 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2251 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2259 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2261 struct sge_eq *eq = &wrq->eq;
2262 struct adapter *sc = wrq->adapter;
2263 int ndesc, available;
2268 ndesc = howmany(len16, EQ_ESIZE / 16);
2269 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2273 if (!STAILQ_EMPTY(&wrq->wr_list))
2274 drain_wrq_wr_list(sc, wrq);
2276 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2279 wr = alloc_wrqe(len16 * 16, wrq);
2280 if (__predict_false(wr == NULL))
2283 cookie->ndesc = ndesc;
2287 eq->cidx = read_hw_cidx(eq);
2288 if (eq->pidx == eq->cidx)
2289 available = eq->sidx - 1;
2291 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2292 if (available < ndesc)
2295 cookie->pidx = eq->pidx;
2296 cookie->ndesc = ndesc;
2297 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2299 w = &eq->desc[eq->pidx];
2300 IDXINCR(eq->pidx, ndesc, eq->sidx);
2301 if (__predict_false(eq->pidx < ndesc - 1)) {
2303 wrq->ss_pidx = cookie->pidx;
2304 wrq->ss_len = len16 * 16;
2313 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2315 struct sge_eq *eq = &wrq->eq;
2316 struct adapter *sc = wrq->adapter;
2318 struct wrq_cookie *prev, *next;
2320 if (cookie->pidx == -1) {
2321 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2327 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2328 pidx = cookie->pidx;
2329 MPASS(pidx >= 0 && pidx < eq->sidx);
2330 if (__predict_false(w == &wrq->ss[0])) {
2331 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2333 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2334 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2335 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2338 wrq->tx_wrs_direct++;
2341 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2342 next = TAILQ_NEXT(cookie, link);
2344 MPASS(pidx == eq->dbidx);
2345 if (next == NULL || ndesc >= 16)
2346 ring_eq_db(wrq->adapter, eq, ndesc);
2348 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2350 next->ndesc += ndesc;
2353 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2354 prev->ndesc += ndesc;
2356 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2358 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2359 drain_wrq_wr_list(sc, wrq);
2362 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2363 /* Doorbell must have caught up to the pidx. */
2364 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2371 can_resume_eth_tx(struct mp_ring *r)
2373 struct sge_eq *eq = r->cookie;
2375 return (total_available_tx_desc(eq) > eq->sidx / 8);
2379 cannot_use_txpkts(struct mbuf *m)
2381 /* maybe put a GL limit too, to avoid silliness? */
2383 return (needs_tso(m));
2387 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2388 * be consumed. Return the actual number consumed. 0 indicates a stall.
2391 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2393 struct sge_txq *txq = r->cookie;
2394 struct sge_eq *eq = &txq->eq;
2395 struct ifnet *ifp = txq->ifp;
2396 struct vi_info *vi = ifp->if_softc;
2397 struct port_info *pi = vi->pi;
2398 struct adapter *sc = pi->adapter;
2399 u_int total, remaining; /* # of packets */
2400 u_int available, dbdiff; /* # of hardware descriptors */
2402 struct mbuf *m0, *tail;
2404 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2406 remaining = IDXDIFF(pidx, cidx, r->size);
2407 MPASS(remaining > 0); /* Must not be called without work to do. */
2411 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2412 while (cidx != pidx) {
2413 m0 = r->items[cidx];
2415 if (++cidx == r->size)
2418 reclaim_tx_descs(txq, 2048);
2423 /* How many hardware descriptors do we have readily available. */
2424 if (eq->pidx == eq->cidx)
2425 available = eq->sidx - 1;
2427 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2428 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2430 while (remaining > 0) {
2432 m0 = r->items[cidx];
2434 MPASS(m0->m_nextpkt == NULL);
2436 if (available < SGE_MAX_WR_NDESC) {
2437 available += reclaim_tx_descs(txq, 64);
2438 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2439 break; /* out of descriptors */
2442 next_cidx = cidx + 1;
2443 if (__predict_false(next_cidx == r->size))
2446 wr = (void *)&eq->desc[eq->pidx];
2447 if (sc->flags & IS_VF) {
2450 ETHER_BPF_MTAP(ifp, m0);
2451 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2453 } else if (remaining > 1 &&
2454 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2456 /* pkts at cidx, next_cidx should both be in txp. */
2457 MPASS(txp.npkt == 2);
2458 tail = r->items[next_cidx];
2459 MPASS(tail->m_nextpkt == NULL);
2460 ETHER_BPF_MTAP(ifp, m0);
2461 ETHER_BPF_MTAP(ifp, tail);
2462 m0->m_nextpkt = tail;
2464 if (__predict_false(++next_cidx == r->size))
2467 while (next_cidx != pidx) {
2468 if (add_to_txpkts(r->items[next_cidx], &txp,
2471 tail->m_nextpkt = r->items[next_cidx];
2472 tail = tail->m_nextpkt;
2473 ETHER_BPF_MTAP(ifp, tail);
2474 if (__predict_false(++next_cidx == r->size))
2478 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2480 remaining -= txp.npkt;
2484 ETHER_BPF_MTAP(ifp, m0);
2485 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2487 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2491 IDXINCR(eq->pidx, n, eq->sidx);
2493 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2494 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2495 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2497 eq->equeqidx = eq->pidx;
2498 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2499 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2500 eq->equeqidx = eq->pidx;
2503 if (dbdiff >= 16 && remaining >= 4) {
2504 ring_eq_db(sc, eq, dbdiff);
2505 available += reclaim_tx_descs(txq, 4 * dbdiff);
2512 ring_eq_db(sc, eq, dbdiff);
2513 reclaim_tx_descs(txq, 32);
2522 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2526 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2527 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2528 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2529 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2533 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2534 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2535 if (pktc_idx >= 0) {
2536 iq->intr_params |= F_QINTR_CNT_EN;
2537 iq->intr_pktc_idx = pktc_idx;
2539 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2540 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2544 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2548 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2549 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2550 if (sc->flags & BUF_PACKING_OK &&
2551 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2552 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2553 fl->flags |= FL_BUF_PACKING;
2554 find_best_refill_source(sc, fl, maxp);
2555 find_safe_refill_source(sc, fl);
2559 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2560 uint8_t tx_chan, uint16_t iqid, char *name)
2562 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2564 eq->flags = eqtype & EQ_TYPEMASK;
2565 eq->tx_chan = tx_chan;
2567 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2568 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2572 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2573 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2577 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2578 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2580 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2584 rc = bus_dmamem_alloc(*tag, va,
2585 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2587 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2591 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2593 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2598 free_ring(sc, *tag, *map, *pa, *va);
2604 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2605 bus_addr_t pa, void *va)
2608 bus_dmamap_unload(tag, map);
2610 bus_dmamem_free(tag, va, map);
2612 bus_dma_tag_destroy(tag);
2618 * Allocates the ring for an ingress queue and an optional freelist. If the
2619 * freelist is specified it will be allocated and then associated with the
2622 * Returns errno on failure. Resources allocated up to that point may still be
2623 * allocated. Caller is responsible for cleanup in case this function fails.
2625 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2626 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2627 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2630 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2631 int intr_idx, int cong)
2633 int rc, i, cntxt_id;
2636 struct port_info *pi = vi->pi;
2637 struct adapter *sc = iq->adapter;
2638 struct sge_params *sp = &sc->params.sge;
2641 len = iq->qsize * IQ_ESIZE;
2642 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2643 (void **)&iq->desc);
2647 bzero(&c, sizeof(c));
2648 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2649 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2650 V_FW_IQ_CMD_VFN(0));
2652 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2655 /* Special handling for firmware event queue */
2656 if (iq == &sc->sge.fwq)
2657 v |= F_FW_IQ_CMD_IQASYNCH;
2659 if (iq->flags & IQ_INTR) {
2660 KASSERT(intr_idx < sc->intr_count,
2661 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2663 v |= F_FW_IQ_CMD_IQANDST;
2664 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2666 c.type_to_iqandstindex = htobe32(v |
2667 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2668 V_FW_IQ_CMD_VIID(vi->viid) |
2669 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2670 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2671 F_FW_IQ_CMD_IQGTSMODE |
2672 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2673 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2674 c.iqsize = htobe16(iq->qsize);
2675 c.iqaddr = htobe64(iq->ba);
2677 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2680 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2682 len = fl->qsize * EQ_ESIZE;
2683 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2684 &fl->ba, (void **)&fl->desc);
2688 /* Allocate space for one software descriptor per buffer. */
2689 rc = alloc_fl_sdesc(fl);
2691 device_printf(sc->dev,
2692 "failed to setup fl software descriptors: %d\n",
2697 if (fl->flags & FL_BUF_PACKING) {
2698 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2699 fl->buf_boundary = sp->pack_boundary;
2701 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2702 fl->buf_boundary = 16;
2704 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2705 fl->buf_boundary = sp->pad_boundary;
2707 c.iqns_to_fl0congen |=
2708 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2709 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2710 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2711 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2714 c.iqns_to_fl0congen |=
2715 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2716 F_FW_IQ_CMD_FL0CONGCIF |
2717 F_FW_IQ_CMD_FL0CONGEN);
2719 c.fl0dcaen_to_fl0cidxfthresh =
2720 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2721 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2722 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2723 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2724 c.fl0size = htobe16(fl->qsize);
2725 c.fl0addr = htobe64(fl->ba);
2728 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2730 device_printf(sc->dev,
2731 "failed to create ingress queue: %d\n", rc);
2736 iq->gen = F_RSPD_GEN;
2737 iq->intr_next = iq->intr_params;
2738 iq->cntxt_id = be16toh(c.iqid);
2739 iq->abs_id = be16toh(c.physiqid);
2740 iq->flags |= IQ_ALLOCATED;
2742 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2743 if (cntxt_id >= sc->sge.niq) {
2744 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2745 cntxt_id, sc->sge.niq - 1);
2747 sc->sge.iqmap[cntxt_id] = iq;
2752 iq->flags |= IQ_HAS_FL;
2753 fl->cntxt_id = be16toh(c.fl0id);
2754 fl->pidx = fl->cidx = 0;
2756 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2757 if (cntxt_id >= sc->sge.neq) {
2758 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2759 __func__, cntxt_id, sc->sge.neq - 1);
2761 sc->sge.eqmap[cntxt_id] = (void *)fl;
2764 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2765 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2766 uint32_t mask = (1 << s_qpp) - 1;
2767 volatile uint8_t *udb;
2769 udb = sc->udbs_base + UDBS_DB_OFFSET;
2770 udb += (qid >> s_qpp) << PAGE_SHIFT;
2772 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2773 udb += qid << UDBS_SEG_SHIFT;
2776 fl->udb = (volatile void *)udb;
2778 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2781 /* Enough to make sure the SGE doesn't think it's starved */
2782 refill_fl(sc, fl, fl->lowat);
2786 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2787 uint32_t param, val;
2789 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2790 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2791 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2796 for (i = 0; i < 4; i++) {
2797 if (cong & (1 << i))
2798 val |= 1 << (i << 2);
2802 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2804 /* report error but carry on */
2805 device_printf(sc->dev,
2806 "failed to set congestion manager context for "
2807 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2811 /* Enable IQ interrupts */
2812 atomic_store_rel_int(&iq->state, IQS_IDLE);
2813 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2814 V_INGRESSQID(iq->cntxt_id));
2820 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2823 struct adapter *sc = iq->adapter;
2827 return (0); /* nothing to do */
2829 dev = vi ? vi->dev : sc->dev;
2831 if (iq->flags & IQ_ALLOCATED) {
2832 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2833 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2834 fl ? fl->cntxt_id : 0xffff, 0xffff);
2837 "failed to free queue %p: %d\n", iq, rc);
2840 iq->flags &= ~IQ_ALLOCATED;
2843 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2845 bzero(iq, sizeof(*iq));
2848 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2852 free_fl_sdesc(sc, fl);
2854 if (mtx_initialized(&fl->fl_lock))
2855 mtx_destroy(&fl->fl_lock);
2857 bzero(fl, sizeof(*fl));
2864 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2865 struct sysctl_oid *oid, struct sge_fl *fl)
2867 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2869 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2871 children = SYSCTL_CHILDREN(oid);
2873 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2874 &fl->ba, "bus address of descriptor ring");
2875 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2876 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2877 "desc ring size in bytes");
2878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2879 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2880 "SGE context id of the freelist");
2881 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2882 fl_pad ? 1 : 0, "padding enabled");
2883 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2884 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2885 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2886 0, "consumer index");
2887 if (fl->flags & FL_BUF_PACKING) {
2888 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2889 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2891 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2892 0, "producer index");
2893 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2894 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2895 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2896 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2897 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2898 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2899 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2900 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2901 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2902 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2906 alloc_fwq(struct adapter *sc)
2909 struct sge_iq *fwq = &sc->sge.fwq;
2910 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2911 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2913 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2914 fwq->flags |= IQ_INTR; /* always */
2915 if (sc->flags & IS_VF)
2918 intr_idx = sc->intr_count > 1 ? 1 : 0;
2919 fwq->set_tcb_rpl = t4_filter_rpl;
2920 fwq->l2t_write_rpl = do_l2t_write_rpl;
2922 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2924 device_printf(sc->dev,
2925 "failed to create firmware event queue: %d\n", rc);
2929 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2930 NULL, "firmware event queue");
2931 children = SYSCTL_CHILDREN(oid);
2933 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2934 &fwq->ba, "bus address of descriptor ring");
2935 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2936 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
2937 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2938 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2939 "absolute id of the queue");
2940 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2941 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2942 "SGE context id of the queue");
2943 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2944 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2951 free_fwq(struct adapter *sc)
2953 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2957 alloc_mgmtq(struct adapter *sc)
2960 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2962 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2963 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2965 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2966 NULL, "management queue");
2968 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2969 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2970 sc->sge.fwq.cntxt_id, name);
2971 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2973 device_printf(sc->dev,
2974 "failed to create management queue: %d\n", rc);
2982 free_mgmtq(struct adapter *sc)
2985 return free_wrq(sc, &sc->sge.mgmtq);
2989 tnl_cong(struct port_info *pi, int drop)
2997 return (pi->rx_chan_map);
3001 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3002 struct sysctl_oid *oid)
3005 struct adapter *sc = vi->pi->adapter;
3006 struct sysctl_oid_list *children;
3009 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3010 tnl_cong(vi->pi, cong_drop));
3015 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3017 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3018 ("iq_base mismatch"));
3019 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3020 ("PF with non-zero iq_base"));
3023 * The freelist is just barely above the starvation threshold right now,
3024 * fill it up a bit more.
3027 refill_fl(sc, &rxq->fl, 128);
3028 FL_UNLOCK(&rxq->fl);
3030 #if defined(INET) || defined(INET6)
3031 rc = tcp_lro_init(&rxq->lro);
3034 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
3036 if (vi->ifp->if_capenable & IFCAP_LRO)
3037 rxq->iq.flags |= IQ_LRO_ENABLED;
3041 children = SYSCTL_CHILDREN(oid);
3043 snprintf(name, sizeof(name), "%d", idx);
3044 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3046 children = SYSCTL_CHILDREN(oid);
3048 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3049 &rxq->iq.ba, "bus address of descriptor ring");
3050 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3051 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3052 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3053 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
3054 "absolute id of the queue");
3055 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3056 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
3057 "SGE context id of the queue");
3058 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3059 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
3061 #if defined(INET) || defined(INET6)
3062 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3063 &rxq->lro.lro_queued, 0, NULL);
3064 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3065 &rxq->lro.lro_flushed, 0, NULL);
3067 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3068 &rxq->rxcsum, "# of times hardware assisted with checksum");
3069 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3070 CTLFLAG_RD, &rxq->vlan_extraction,
3071 "# of times hardware extracted 802.1Q tag");
3073 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3079 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3083 #if defined(INET) || defined(INET6)
3085 tcp_lro_free(&rxq->lro);
3086 rxq->lro.ifp = NULL;
3090 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3092 bzero(rxq, sizeof(*rxq));
3099 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3100 int intr_idx, int idx, struct sysctl_oid *oid)
3102 struct port_info *pi = vi->pi;
3104 struct sysctl_oid_list *children;
3107 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3112 children = SYSCTL_CHILDREN(oid);
3114 snprintf(name, sizeof(name), "%d", idx);
3115 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3117 children = SYSCTL_CHILDREN(oid);
3119 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3120 &ofld_rxq->iq.ba, "bus address of descriptor ring");
3121 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3122 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3123 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3124 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3125 "I", "absolute id of the queue");
3126 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3127 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3128 "I", "SGE context id of the queue");
3129 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3130 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3133 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3139 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3143 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3145 bzero(ofld_rxq, sizeof(*ofld_rxq));
3153 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3154 int idx, struct sysctl_oid *oid)
3157 struct sysctl_oid_list *children;
3158 struct sysctl_ctx_list *ctx;
3161 struct adapter *sc = vi->pi->adapter;
3162 struct netmap_adapter *na = NA(vi->ifp);
3166 len = vi->qsize_rxq * IQ_ESIZE;
3167 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3168 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3172 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3173 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3174 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3180 nm_rxq->iq_cidx = 0;
3181 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3182 nm_rxq->iq_gen = F_RSPD_GEN;
3183 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3184 nm_rxq->fl_sidx = na->num_rx_desc;
3185 nm_rxq->intr_idx = intr_idx;
3188 children = SYSCTL_CHILDREN(oid);
3190 snprintf(name, sizeof(name), "%d", idx);
3191 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3193 children = SYSCTL_CHILDREN(oid);
3195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3196 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3197 "I", "absolute id of the queue");
3198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3199 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3200 "I", "SGE context id of the queue");
3201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3202 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3205 children = SYSCTL_CHILDREN(oid);
3206 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3208 children = SYSCTL_CHILDREN(oid);
3210 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3211 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3212 "I", "SGE context id of the freelist");
3213 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3214 &nm_rxq->fl_cidx, 0, "consumer index");
3215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3216 &nm_rxq->fl_pidx, 0, "producer index");
3223 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3225 struct adapter *sc = vi->pi->adapter;
3227 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3229 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3236 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3237 struct sysctl_oid *oid)
3241 struct port_info *pi = vi->pi;
3242 struct adapter *sc = pi->adapter;
3243 struct netmap_adapter *na = NA(vi->ifp);
3245 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3247 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3248 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3249 &nm_txq->ba, (void **)&nm_txq->desc);
3253 nm_txq->pidx = nm_txq->cidx = 0;
3254 nm_txq->sidx = na->num_tx_desc;
3256 nm_txq->iqidx = iqidx;
3257 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3258 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3259 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3260 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3262 snprintf(name, sizeof(name), "%d", idx);
3263 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3264 NULL, "netmap tx queue");
3265 children = SYSCTL_CHILDREN(oid);
3267 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3268 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3269 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3270 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3272 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3273 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3280 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3282 struct adapter *sc = vi->pi->adapter;
3284 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3292 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3295 struct fw_eq_ctrl_cmd c;
3296 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3298 bzero(&c, sizeof(c));
3300 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3301 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3302 V_FW_EQ_CTRL_CMD_VFN(0));
3303 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3304 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3305 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3306 c.physeqid_pkd = htobe32(0);
3307 c.fetchszm_to_iqid =
3308 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3309 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3310 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3312 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3313 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3314 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3315 c.eqaddr = htobe64(eq->ba);
3317 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3319 device_printf(sc->dev,
3320 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3323 eq->flags |= EQ_ALLOCATED;
3325 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3326 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3327 if (cntxt_id >= sc->sge.neq)
3328 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3329 cntxt_id, sc->sge.neq - 1);
3330 sc->sge.eqmap[cntxt_id] = eq;
3336 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3339 struct fw_eq_eth_cmd c;
3340 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3342 bzero(&c, sizeof(c));
3344 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3345 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3346 V_FW_EQ_ETH_CMD_VFN(0));
3347 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3348 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3349 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3350 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3351 c.fetchszm_to_iqid =
3352 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3353 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3354 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3355 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3356 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3357 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3358 c.eqaddr = htobe64(eq->ba);
3360 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3362 device_printf(vi->dev,
3363 "failed to create Ethernet egress queue: %d\n", rc);
3366 eq->flags |= EQ_ALLOCATED;
3368 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3369 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3370 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3371 if (cntxt_id >= sc->sge.neq)
3372 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3373 cntxt_id, sc->sge.neq - 1);
3374 sc->sge.eqmap[cntxt_id] = eq;
3381 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3384 struct fw_eq_ofld_cmd c;
3385 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3387 bzero(&c, sizeof(c));
3389 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3390 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3391 V_FW_EQ_OFLD_CMD_VFN(0));
3392 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3393 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3394 c.fetchszm_to_iqid =
3395 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3396 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3397 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3399 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3400 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3401 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3402 c.eqaddr = htobe64(eq->ba);
3404 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3406 device_printf(vi->dev,
3407 "failed to create egress queue for TCP offload: %d\n", rc);
3410 eq->flags |= EQ_ALLOCATED;
3412 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3413 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3414 if (cntxt_id >= sc->sge.neq)
3415 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3416 cntxt_id, sc->sge.neq - 1);
3417 sc->sge.eqmap[cntxt_id] = eq;
3424 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3429 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3431 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3432 len = qsize * EQ_ESIZE;
3433 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3434 &eq->ba, (void **)&eq->desc);
3438 eq->pidx = eq->cidx = 0;
3439 eq->equeqidx = eq->dbidx = 0;
3440 eq->doorbells = sc->doorbells;
3442 switch (eq->flags & EQ_TYPEMASK) {
3444 rc = ctrl_eq_alloc(sc, eq);
3448 rc = eth_eq_alloc(sc, vi, eq);
3453 rc = ofld_eq_alloc(sc, vi, eq);
3458 panic("%s: invalid eq type %d.", __func__,
3459 eq->flags & EQ_TYPEMASK);
3462 device_printf(sc->dev,
3463 "failed to allocate egress queue(%d): %d\n",
3464 eq->flags & EQ_TYPEMASK, rc);
3467 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3468 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3469 isset(&eq->doorbells, DOORBELL_WCWR)) {
3470 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3471 uint32_t mask = (1 << s_qpp) - 1;
3472 volatile uint8_t *udb;
3474 udb = sc->udbs_base + UDBS_DB_OFFSET;
3475 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3476 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3477 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3478 clrbit(&eq->doorbells, DOORBELL_WCWR);
3480 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3483 eq->udb = (volatile void *)udb;
3490 free_eq(struct adapter *sc, struct sge_eq *eq)
3494 if (eq->flags & EQ_ALLOCATED) {
3495 switch (eq->flags & EQ_TYPEMASK) {
3497 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3502 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3508 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3514 panic("%s: invalid eq type %d.", __func__,
3515 eq->flags & EQ_TYPEMASK);
3518 device_printf(sc->dev,
3519 "failed to free egress queue (%d): %d\n",
3520 eq->flags & EQ_TYPEMASK, rc);
3523 eq->flags &= ~EQ_ALLOCATED;
3526 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3528 if (mtx_initialized(&eq->eq_lock))
3529 mtx_destroy(&eq->eq_lock);
3531 bzero(eq, sizeof(*eq));
3536 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3537 struct sysctl_oid *oid)
3540 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3541 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3543 rc = alloc_eq(sc, vi, &wrq->eq);
3548 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3549 TAILQ_INIT(&wrq->incomplete_wrs);
3550 STAILQ_INIT(&wrq->wr_list);
3551 wrq->nwr_pending = 0;
3552 wrq->ndesc_needed = 0;
3554 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3555 &wrq->eq.ba, "bus address of descriptor ring");
3556 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3557 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3558 "desc ring size in bytes");
3559 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3560 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3562 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3564 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3565 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3567 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3568 wrq->eq.sidx, "status page index");
3569 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3570 &wrq->tx_wrs_direct, "# of work requests (direct)");
3571 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3572 &wrq->tx_wrs_copied, "# of work requests (copied)");
3573 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3574 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3580 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3584 rc = free_eq(sc, &wrq->eq);
3588 bzero(wrq, sizeof(*wrq));
3593 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3594 struct sysctl_oid *oid)
3597 struct port_info *pi = vi->pi;
3598 struct adapter *sc = pi->adapter;
3599 struct sge_eq *eq = &txq->eq;
3601 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3603 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3606 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3610 rc = alloc_eq(sc, vi, eq);
3612 mp_ring_free(txq->r);
3617 /* Can't fail after this point. */
3620 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3622 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3623 ("eq_base mismatch"));
3624 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3625 ("PF with non-zero eq_base"));
3627 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3629 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3630 if (sc->flags & IS_VF)
3631 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3632 V_TXPKT_INTF(pi->tx_chan));
3634 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3635 V_TXPKT_INTF(pi->tx_chan) |
3636 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3637 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3638 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3640 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3643 snprintf(name, sizeof(name), "%d", idx);
3644 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3646 children = SYSCTL_CHILDREN(oid);
3648 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3649 &eq->ba, "bus address of descriptor ring");
3650 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3651 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3652 "desc ring size in bytes");
3653 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3654 &eq->abs_id, 0, "absolute id of the queue");
3655 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3656 &eq->cntxt_id, 0, "SGE context id of the queue");
3657 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3658 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3660 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3661 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3663 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3664 eq->sidx, "status page index");
3666 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3667 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3668 "traffic class (-1 means none)");
3670 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3671 &txq->txcsum, "# of times hardware assisted with checksum");
3672 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3673 CTLFLAG_RD, &txq->vlan_insertion,
3674 "# of times hardware inserted 802.1Q tag");
3675 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3676 &txq->tso_wrs, "# of TSO work requests");
3677 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3678 &txq->imm_wrs, "# of work requests with immediate data");
3679 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3680 &txq->sgl_wrs, "# of work requests with direct SGL");
3681 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3682 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3683 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3684 CTLFLAG_RD, &txq->txpkts0_wrs,
3685 "# of txpkts (type 0) work requests");
3686 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3687 CTLFLAG_RD, &txq->txpkts1_wrs,
3688 "# of txpkts (type 1) work requests");
3689 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3690 CTLFLAG_RD, &txq->txpkts0_pkts,
3691 "# of frames tx'd using type0 txpkts work requests");
3692 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3693 CTLFLAG_RD, &txq->txpkts1_pkts,
3694 "# of frames tx'd using type1 txpkts work requests");
3696 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3697 CTLFLAG_RD, &txq->r->enqueues,
3698 "# of enqueues to the mp_ring for this queue");
3699 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3700 CTLFLAG_RD, &txq->r->drops,
3701 "# of drops in the mp_ring for this queue");
3702 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3703 CTLFLAG_RD, &txq->r->starts,
3704 "# of normal consumer starts in the mp_ring for this queue");
3705 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3706 CTLFLAG_RD, &txq->r->stalls,
3707 "# of consumer stalls in the mp_ring for this queue");
3708 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3709 CTLFLAG_RD, &txq->r->restarts,
3710 "# of consumer restarts in the mp_ring for this queue");
3711 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3712 CTLFLAG_RD, &txq->r->abdications,
3713 "# of consumer abdications in the mp_ring for this queue");
3719 free_txq(struct vi_info *vi, struct sge_txq *txq)
3722 struct adapter *sc = vi->pi->adapter;
3723 struct sge_eq *eq = &txq->eq;
3725 rc = free_eq(sc, eq);
3729 sglist_free(txq->gl);
3730 free(txq->sdesc, M_CXGBE);
3731 mp_ring_free(txq->r);
3733 bzero(txq, sizeof(*txq));
3738 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3740 bus_addr_t *ba = arg;
3743 ("%s meant for single segment mappings only.", __func__));
3745 *ba = error ? 0 : segs->ds_addr;
3749 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3753 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3757 v = fl->dbval | V_PIDX(n);
3759 *fl->udb = htole32(v);
3761 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3762 IDXINCR(fl->dbidx, n, fl->sidx);
3766 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
3767 * recycled do not count towards this allocation budget.
3769 * Returns non-zero to indicate that this freelist should be added to the list
3770 * of starving freelists.
3773 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3776 struct fl_sdesc *sd;
3779 struct cluster_layout *cll;
3780 struct sw_zone_info *swz;
3781 struct cluster_metadata *clm;
3783 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3785 FL_LOCK_ASSERT_OWNED(fl);
3788 * We always stop at the beginning of the hardware descriptor that's just
3789 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3790 * which would mean an empty freelist to the chip.
3792 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3793 if (fl->pidx == max_pidx * 8)
3796 d = &fl->desc[fl->pidx];
3797 sd = &fl->sdesc[fl->pidx];
3798 cll = &fl->cll_def; /* default layout */
3799 swz = &sc->sge.sw_zone_info[cll->zidx];
3803 if (sd->cl != NULL) {
3805 if (sd->nmbuf == 0) {
3807 * Fast recycle without involving any atomics on
3808 * the cluster's metadata (if the cluster has
3809 * metadata). This happens when all frames
3810 * received in the cluster were small enough to
3811 * fit within a single mbuf each.
3813 fl->cl_fast_recycled++;
3815 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3817 MPASS(clm->refcount == 1);
3823 * Cluster is guaranteed to have metadata. Clusters
3824 * without metadata always take the fast recycle path
3825 * when they're recycled.
3827 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3830 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3832 counter_u64_add(extfree_rels, 1);
3835 sd->cl = NULL; /* gave up my reference */
3837 MPASS(sd->cl == NULL);
3839 cl = uma_zalloc(swz->zone, M_NOWAIT);
3840 if (__predict_false(cl == NULL)) {
3841 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3842 fl->cll_def.zidx == fl->cll_alt.zidx)
3845 /* fall back to the safe zone */
3847 swz = &sc->sge.sw_zone_info[cll->zidx];
3853 pa = pmap_kextract((vm_offset_t)cl);
3857 *d = htobe64(pa | cll->hwidx);
3858 clm = cl_metadata(sc, fl, cll, cl);
3870 if (__predict_false(++fl->pidx % 8 == 0)) {
3871 uint16_t pidx = fl->pidx / 8;
3873 if (__predict_false(pidx == fl->sidx)) {
3879 if (pidx == max_pidx)
3882 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3887 if (fl->pidx / 8 != fl->dbidx)
3890 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3894 * Attempt to refill all starving freelists.
3897 refill_sfl(void *arg)
3899 struct adapter *sc = arg;
3900 struct sge_fl *fl, *fl_temp;
3902 mtx_assert(&sc->sfl_lock, MA_OWNED);
3903 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3905 refill_fl(sc, fl, 64);
3906 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3907 TAILQ_REMOVE(&sc->sfl, fl, link);
3908 fl->flags &= ~FL_STARVING;
3913 if (!TAILQ_EMPTY(&sc->sfl))
3914 callout_schedule(&sc->sfl_callout, hz / 5);
3918 alloc_fl_sdesc(struct sge_fl *fl)
3921 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3928 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3930 struct fl_sdesc *sd;
3931 struct cluster_metadata *clm;
3932 struct cluster_layout *cll;
3936 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3941 clm = cl_metadata(sc, fl, cll, sd->cl);
3943 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3944 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3945 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3946 counter_u64_add(extfree_rels, 1);
3951 free(fl->sdesc, M_CXGBE);
3956 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3963 rc = sglist_append_mbuf(gl, m);
3964 if (__predict_false(rc != 0)) {
3965 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3966 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3969 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3970 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3971 mbuf_nsegs(m), gl->sg_nseg));
3972 KASSERT(gl->sg_nseg > 0 &&
3973 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3974 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3975 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3979 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3982 txpkt_len16(u_int nsegs, u_int tso)
3988 nsegs--; /* first segment is part of ulptx_sgl */
3989 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3990 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3992 n += sizeof(struct cpl_tx_pkt_lso_core);
3994 return (howmany(n, 16));
3998 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4002 txpkt_vm_len16(u_int nsegs, u_int tso)
4008 nsegs--; /* first segment is part of ulptx_sgl */
4009 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4010 sizeof(struct cpl_tx_pkt_core) +
4011 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4013 n += sizeof(struct cpl_tx_pkt_lso_core);
4015 return (howmany(n, 16));
4019 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4023 txpkts0_len16(u_int nsegs)
4029 nsegs--; /* first segment is part of ulptx_sgl */
4030 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4031 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4032 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4034 return (howmany(n, 16));
4038 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4046 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4048 return (howmany(n, 16));
4052 imm_payload(u_int ndesc)
4056 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4057 sizeof(struct cpl_tx_pkt_core);
4063 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4064 * software descriptor, and advance the pidx. It is guaranteed that enough
4065 * descriptors are available.
4067 * The return value is the # of hardware descriptors used.
4070 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4071 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4073 struct sge_eq *eq = &txq->eq;
4074 struct tx_sdesc *txsd;
4075 struct cpl_tx_pkt_core *cpl;
4076 uint32_t ctrl; /* used in many unrelated places */
4078 int csum_type, len16, ndesc, pktlen, nsegs;
4081 TXQ_LOCK_ASSERT_OWNED(txq);
4083 MPASS(available > 0 && available < eq->sidx);
4085 len16 = mbuf_len16(m0);
4086 nsegs = mbuf_nsegs(m0);
4087 pktlen = m0->m_pkthdr.len;
4088 ctrl = sizeof(struct cpl_tx_pkt_core);
4090 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4091 ndesc = howmany(len16, EQ_ESIZE / 16);
4092 MPASS(ndesc <= available);
4094 /* Firmware work request header */
4095 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4096 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4097 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4099 ctrl = V_FW_WR_LEN16(len16);
4100 wr->equiq_to_len16 = htobe32(ctrl);
4105 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4106 * vlantci is ignored unless the ethtype is 0x8100, so it's
4107 * simpler to always copy it rather than making it
4108 * conditional. Also, it seems that we do not have to set
4109 * vlantci or fake the ethtype when doing VLAN tag insertion.
4111 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4114 if (needs_tso(m0)) {
4115 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4117 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4118 m0->m_pkthdr.l4hlen > 0,
4119 ("%s: mbuf %p needs TSO but missing header lengths",
4122 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4123 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4124 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4125 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4126 ctrl |= V_LSO_ETHHDR_LEN(1);
4127 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4130 lso->lso_ctrl = htobe32(ctrl);
4131 lso->ipid_ofst = htobe16(0);
4132 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4133 lso->seqno_offset = htobe32(0);
4134 lso->len = htobe32(pktlen);
4136 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4137 csum_type = TX_CSUM_TCPIP6;
4139 csum_type = TX_CSUM_TCPIP;
4141 cpl = (void *)(lso + 1);
4145 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4146 csum_type = TX_CSUM_TCPIP;
4147 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4148 csum_type = TX_CSUM_UDPIP;
4149 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4150 csum_type = TX_CSUM_TCPIP6;
4151 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4152 csum_type = TX_CSUM_UDPIP6;
4154 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4156 * XXX: The firmware appears to stomp on the
4157 * fragment/flags field of the IP header when
4158 * using TX_CSUM_IP. Fall back to doing
4159 * software checksums.
4167 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4168 offsetof(struct ip, ip_sum));
4169 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4170 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4171 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4175 cpl = (void *)(wr + 1);
4178 /* Checksum offload */
4180 if (needs_l3_csum(m0) == 0)
4181 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4182 if (csum_type >= 0) {
4183 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4184 ("%s: mbuf %p needs checksum offload but missing header lengths",
4187 if (chip_id(sc) <= CHELSIO_T5) {
4188 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4191 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4194 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4195 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4197 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4198 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4199 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4200 txq->txcsum++; /* some hardware assistance provided */
4202 /* VLAN tag insertion */
4203 if (needs_vlan_insertion(m0)) {
4204 ctrl1 |= F_TXPKT_VLAN_VLD |
4205 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4206 txq->vlan_insertion++;
4210 cpl->ctrl0 = txq->cpl_ctrl0;
4212 cpl->len = htobe16(pktlen);
4213 cpl->ctrl1 = htobe64(ctrl1);
4216 dst = (void *)(cpl + 1);
4219 * A packet using TSO will use up an entire descriptor for the
4220 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4221 * If this descriptor is the last descriptor in the ring, wrap
4222 * around to the front of the ring explicitly for the start of
4225 if (dst == (void *)&eq->desc[eq->sidx]) {
4226 dst = (void *)&eq->desc[0];
4227 write_gl_to_txd(txq, m0, &dst, 0);
4229 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4234 txsd = &txq->sdesc[eq->pidx];
4236 txsd->desc_used = ndesc;
4242 * Write a txpkt WR for this packet to the hardware descriptors, update the
4243 * software descriptor, and advance the pidx. It is guaranteed that enough
4244 * descriptors are available.
4246 * The return value is the # of hardware descriptors used.
4249 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4250 struct mbuf *m0, u_int available)
4252 struct sge_eq *eq = &txq->eq;
4253 struct tx_sdesc *txsd;
4254 struct cpl_tx_pkt_core *cpl;
4255 uint32_t ctrl; /* used in many unrelated places */
4257 int len16, ndesc, pktlen, nsegs;
4260 TXQ_LOCK_ASSERT_OWNED(txq);
4262 MPASS(available > 0 && available < eq->sidx);
4264 len16 = mbuf_len16(m0);
4265 nsegs = mbuf_nsegs(m0);
4266 pktlen = m0->m_pkthdr.len;
4267 ctrl = sizeof(struct cpl_tx_pkt_core);
4269 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4270 else if (pktlen <= imm_payload(2) && available >= 2) {
4271 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4273 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4274 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4277 ndesc = howmany(len16, EQ_ESIZE / 16);
4278 MPASS(ndesc <= available);
4280 /* Firmware work request header */
4281 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4282 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4283 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4285 ctrl = V_FW_WR_LEN16(len16);
4286 wr->equiq_to_len16 = htobe32(ctrl);
4289 if (needs_tso(m0)) {
4290 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4292 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4293 m0->m_pkthdr.l4hlen > 0,
4294 ("%s: mbuf %p needs TSO but missing header lengths",
4297 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4298 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4299 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4300 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4301 ctrl |= V_LSO_ETHHDR_LEN(1);
4302 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4305 lso->lso_ctrl = htobe32(ctrl);
4306 lso->ipid_ofst = htobe16(0);
4307 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4308 lso->seqno_offset = htobe32(0);
4309 lso->len = htobe32(pktlen);
4311 cpl = (void *)(lso + 1);
4315 cpl = (void *)(wr + 1);
4317 /* Checksum offload */
4319 if (needs_l3_csum(m0) == 0)
4320 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4321 if (needs_l4_csum(m0) == 0)
4322 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4323 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4324 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4325 txq->txcsum++; /* some hardware assistance provided */
4327 /* VLAN tag insertion */
4328 if (needs_vlan_insertion(m0)) {
4329 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4330 txq->vlan_insertion++;
4334 cpl->ctrl0 = txq->cpl_ctrl0;
4336 cpl->len = htobe16(pktlen);
4337 cpl->ctrl1 = htobe64(ctrl1);
4340 dst = (void *)(cpl + 1);
4343 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4348 for (m = m0; m != NULL; m = m->m_next) {
4349 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4355 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4362 txsd = &txq->sdesc[eq->pidx];
4364 txsd->desc_used = ndesc;
4370 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4372 u_int needed, nsegs1, nsegs2, l1, l2;
4374 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4377 nsegs1 = mbuf_nsegs(m);
4378 nsegs2 = mbuf_nsegs(n);
4379 if (nsegs1 + nsegs2 == 2) {
4381 l1 = l2 = txpkts1_len16();
4384 l1 = txpkts0_len16(nsegs1);
4385 l2 = txpkts0_len16(nsegs2);
4387 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4388 needed = howmany(txp->len16, EQ_ESIZE / 16);
4389 if (needed > SGE_MAX_WR_NDESC || needed > available)
4392 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4393 if (txp->plen > 65535)
4397 set_mbuf_len16(m, l1);
4398 set_mbuf_len16(n, l2);
4404 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4406 u_int plen, len16, needed, nsegs;
4408 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4410 nsegs = mbuf_nsegs(m);
4411 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4414 plen = txp->plen + m->m_pkthdr.len;
4418 if (txp->wr_type == 0)
4419 len16 = txpkts0_len16(nsegs);
4421 len16 = txpkts1_len16();
4422 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4423 if (needed > SGE_MAX_WR_NDESC || needed > available)
4428 txp->len16 += len16;
4429 set_mbuf_len16(m, len16);
4435 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4436 * the software descriptor, and advance the pidx. It is guaranteed that enough
4437 * descriptors are available.
4439 * The return value is the # of hardware descriptors used.
4442 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4443 struct mbuf *m0, const struct txpkts *txp, u_int available)
4445 struct sge_eq *eq = &txq->eq;
4446 struct tx_sdesc *txsd;
4447 struct cpl_tx_pkt_core *cpl;
4450 int ndesc, checkwrap;
4454 TXQ_LOCK_ASSERT_OWNED(txq);
4455 MPASS(txp->npkt > 0);
4456 MPASS(txp->plen < 65536);
4458 MPASS(m0->m_nextpkt != NULL);
4459 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4460 MPASS(available > 0 && available < eq->sidx);
4462 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4463 MPASS(ndesc <= available);
4465 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4466 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4467 ctrl = V_FW_WR_LEN16(txp->len16);
4468 wr->equiq_to_len16 = htobe32(ctrl);
4469 wr->plen = htobe16(txp->plen);
4470 wr->npkt = txp->npkt;
4472 wr->type = txp->wr_type;
4476 * At this point we are 16B into a hardware descriptor. If checkwrap is
4477 * set then we know the WR is going to wrap around somewhere. We'll
4478 * check for that at appropriate points.
4480 checkwrap = eq->sidx - ndesc < eq->pidx;
4481 for (m = m0; m != NULL; m = m->m_nextpkt) {
4482 if (txp->wr_type == 0) {
4483 struct ulp_txpkt *ulpmc;
4484 struct ulptx_idata *ulpsc;
4486 /* ULP master command */
4488 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4489 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4490 ulpmc->len = htobe32(mbuf_len16(m));
4492 /* ULP subcommand */
4493 ulpsc = (void *)(ulpmc + 1);
4494 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4496 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4498 cpl = (void *)(ulpsc + 1);
4500 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4501 cpl = (void *)&eq->desc[0];
4502 txq->txpkts0_pkts += txp->npkt;
4506 txq->txpkts1_pkts += txp->npkt;
4510 /* Checksum offload */
4512 if (needs_l3_csum(m) == 0)
4513 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4514 if (needs_l4_csum(m) == 0)
4515 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4516 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4517 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4518 txq->txcsum++; /* some hardware assistance provided */
4520 /* VLAN tag insertion */
4521 if (needs_vlan_insertion(m)) {
4522 ctrl1 |= F_TXPKT_VLAN_VLD |
4523 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4524 txq->vlan_insertion++;
4528 cpl->ctrl0 = txq->cpl_ctrl0;
4530 cpl->len = htobe16(m->m_pkthdr.len);
4531 cpl->ctrl1 = htobe64(ctrl1);
4535 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4536 flitp = (void *)&eq->desc[0];
4538 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4542 txsd = &txq->sdesc[eq->pidx];
4544 txsd->desc_used = ndesc;
4550 * If the SGL ends on an address that is not 16 byte aligned, this function will
4551 * add a 0 filled flit at the end.
4554 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4556 struct sge_eq *eq = &txq->eq;
4557 struct sglist *gl = txq->gl;
4558 struct sglist_seg *seg;
4559 __be64 *flitp, *wrap;
4560 struct ulptx_sgl *usgl;
4561 int i, nflits, nsegs;
4563 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4564 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4565 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4566 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4569 nsegs = gl->sg_nseg;
4572 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4573 flitp = (__be64 *)(*to);
4574 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4575 seg = &gl->sg_segs[0];
4576 usgl = (void *)flitp;
4579 * We start at a 16 byte boundary somewhere inside the tx descriptor
4580 * ring, so we're at least 16 bytes away from the status page. There is
4581 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4584 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4585 V_ULPTX_NSGE(nsegs));
4586 usgl->len0 = htobe32(seg->ss_len);
4587 usgl->addr0 = htobe64(seg->ss_paddr);
4590 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4592 /* Won't wrap around at all */
4594 for (i = 0; i < nsegs - 1; i++, seg++) {
4595 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4596 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4599 usgl->sge[i / 2].len[1] = htobe32(0);
4603 /* Will wrap somewhere in the rest of the SGL */
4605 /* 2 flits already written, write the rest flit by flit */
4606 flitp = (void *)(usgl + 1);
4607 for (i = 0; i < nflits - 2; i++) {
4609 flitp = (void *)eq->desc;
4610 *flitp++ = get_flit(seg, nsegs - 1, i);
4615 MPASS(((uintptr_t)flitp) & 0xf);
4619 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4620 if (__predict_false(flitp == wrap))
4621 *to = (void *)eq->desc;
4623 *to = (void *)flitp;
4627 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4630 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4631 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4633 if (__predict_true((uintptr_t)(*to) + len <=
4634 (uintptr_t)&eq->desc[eq->sidx])) {
4635 bcopy(from, *to, len);
4638 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4640 bcopy(from, *to, portion);
4642 portion = len - portion; /* remaining */
4643 bcopy(from, (void *)eq->desc, portion);
4644 (*to) = (caddr_t)eq->desc + portion;
4649 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4657 clrbit(&db, DOORBELL_WCWR);
4660 switch (ffs(db) - 1) {
4662 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4665 case DOORBELL_WCWR: {
4666 volatile uint64_t *dst, *src;
4670 * Queues whose 128B doorbell segment fits in the page do not
4671 * use relative qid (udb_qid is always 0). Only queues with
4672 * doorbell segments can do WCWR.
4674 KASSERT(eq->udb_qid == 0 && n == 1,
4675 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4676 __func__, eq->doorbells, n, eq->dbidx, eq));
4678 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4681 src = (void *)&eq->desc[i];
4682 while (src != (void *)&eq->desc[i + 1])
4688 case DOORBELL_UDBWC:
4689 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4694 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4695 V_QID(eq->cntxt_id) | V_PIDX(n));
4699 IDXINCR(eq->dbidx, n, eq->sidx);
4703 reclaimable_tx_desc(struct sge_eq *eq)
4707 hw_cidx = read_hw_cidx(eq);
4708 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4712 total_available_tx_desc(struct sge_eq *eq)
4714 uint16_t hw_cidx, pidx;
4716 hw_cidx = read_hw_cidx(eq);
4719 if (pidx == hw_cidx)
4720 return (eq->sidx - 1);
4722 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4725 static inline uint16_t
4726 read_hw_cidx(struct sge_eq *eq)
4728 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4729 uint16_t cidx = spg->cidx; /* stable snapshot */
4731 return (be16toh(cidx));
4735 * Reclaim 'n' descriptors approximately.
4738 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4740 struct tx_sdesc *txsd;
4741 struct sge_eq *eq = &txq->eq;
4742 u_int can_reclaim, reclaimed;
4744 TXQ_LOCK_ASSERT_OWNED(txq);
4748 can_reclaim = reclaimable_tx_desc(eq);
4749 while (can_reclaim && reclaimed < n) {
4751 struct mbuf *m, *nextpkt;
4753 txsd = &txq->sdesc[eq->cidx];
4754 ndesc = txsd->desc_used;
4756 /* Firmware doesn't return "partial" credits. */
4757 KASSERT(can_reclaim >= ndesc,
4758 ("%s: unexpected number of credits: %d, %d",
4759 __func__, can_reclaim, ndesc));
4761 for (m = txsd->m; m != NULL; m = nextpkt) {
4762 nextpkt = m->m_nextpkt;
4763 m->m_nextpkt = NULL;
4767 can_reclaim -= ndesc;
4768 IDXINCR(eq->cidx, ndesc, eq->sidx);
4775 tx_reclaim(void *arg, int n)
4777 struct sge_txq *txq = arg;
4778 struct sge_eq *eq = &txq->eq;
4781 if (TXQ_TRYLOCK(txq) == 0)
4783 n = reclaim_tx_descs(txq, 32);
4784 if (eq->cidx == eq->pidx)
4785 eq->equeqidx = eq->pidx;
4791 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4793 int i = (idx / 3) * 2;
4799 rc = htobe32(segs[i].ss_len);
4801 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4806 return (htobe64(segs[i].ss_paddr));
4808 return (htobe64(segs[i + 1].ss_paddr));
4815 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4817 int8_t zidx, hwidx, idx;
4818 uint16_t region1, region3;
4819 int spare, spare_needed, n;
4820 struct sw_zone_info *swz;
4821 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4824 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4825 * large enough for the max payload and cluster metadata. Otherwise
4826 * settle for the largest bufsize that leaves enough room in the cluster
4829 * Without buffer packing: Look for the smallest zone which has a
4830 * bufsize large enough for the max payload. Settle for the largest
4831 * bufsize available if there's nothing big enough for max payload.
4833 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4834 swz = &sc->sge.sw_zone_info[0];
4836 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4837 if (swz->size > largest_rx_cluster) {
4838 if (__predict_true(hwidx != -1))
4842 * This is a misconfiguration. largest_rx_cluster is
4843 * preventing us from finding a refill source. See
4844 * dev.t5nex.<n>.buffer_sizes to figure out why.
4846 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4847 " refill source for fl %p (dma %u). Ignored.\n",
4848 largest_rx_cluster, fl, maxp);
4850 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4851 hwb = &hwb_list[idx];
4852 spare = swz->size - hwb->size;
4853 if (spare < spare_needed)
4856 hwidx = idx; /* best option so far */
4857 if (hwb->size >= maxp) {
4859 if ((fl->flags & FL_BUF_PACKING) == 0)
4860 goto done; /* stop looking (not packing) */
4862 if (swz->size >= safest_rx_cluster)
4863 goto done; /* stop looking (packing) */
4865 break; /* keep looking, next zone */
4869 /* A usable hwidx has been located. */
4871 hwb = &hwb_list[hwidx];
4873 swz = &sc->sge.sw_zone_info[zidx];
4875 region3 = swz->size - hwb->size;
4878 * Stay within this zone and see if there is a better match when mbuf
4879 * inlining is allowed. Remember that the hwidx's are sorted in
4880 * decreasing order of size (so in increasing order of spare area).
4882 for (idx = hwidx; idx != -1; idx = hwb->next) {
4883 hwb = &hwb_list[idx];
4884 spare = swz->size - hwb->size;
4886 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4890 * Do not inline mbufs if doing so would violate the pad/pack
4891 * boundary alignment requirement.
4893 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4895 if (fl->flags & FL_BUF_PACKING &&
4896 (MSIZE % sc->params.sge.pack_boundary) != 0)
4899 if (spare < CL_METADATA_SIZE + MSIZE)
4901 n = (spare - CL_METADATA_SIZE) / MSIZE;
4902 if (n > howmany(hwb->size, maxp))
4906 if (fl->flags & FL_BUF_PACKING) {
4907 region1 = n * MSIZE;
4908 region3 = spare - region1;
4911 region3 = spare - region1;
4916 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4917 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4918 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4919 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4920 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4921 sc->sge.sw_zone_info[zidx].size,
4922 ("%s: bad buffer layout for fl %p, maxp %d. "
4923 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4924 sc->sge.sw_zone_info[zidx].size, region1,
4925 sc->sge.hw_buf_info[hwidx].size, region3));
4926 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4927 KASSERT(region3 >= CL_METADATA_SIZE,
4928 ("%s: no room for metadata. fl %p, maxp %d; "
4929 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4930 sc->sge.sw_zone_info[zidx].size, region1,
4931 sc->sge.hw_buf_info[hwidx].size, region3));
4932 KASSERT(region1 % MSIZE == 0,
4933 ("%s: bad mbuf region for fl %p, maxp %d. "
4934 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4935 sc->sge.sw_zone_info[zidx].size, region1,
4936 sc->sge.hw_buf_info[hwidx].size, region3));
4939 fl->cll_def.zidx = zidx;
4940 fl->cll_def.hwidx = hwidx;
4941 fl->cll_def.region1 = region1;
4942 fl->cll_def.region3 = region3;
4946 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4948 struct sge *s = &sc->sge;
4949 struct hw_buf_info *hwb;
4950 struct sw_zone_info *swz;
4954 if (fl->flags & FL_BUF_PACKING)
4955 hwidx = s->safe_hwidx2; /* with room for metadata */
4956 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4957 hwidx = s->safe_hwidx2;
4958 hwb = &s->hw_buf_info[hwidx];
4959 swz = &s->sw_zone_info[hwb->zidx];
4960 spare = swz->size - hwb->size;
4962 /* no good if there isn't room for an mbuf as well */
4963 if (spare < CL_METADATA_SIZE + MSIZE)
4964 hwidx = s->safe_hwidx1;
4966 hwidx = s->safe_hwidx1;
4969 /* No fallback source */
4970 fl->cll_alt.hwidx = -1;
4971 fl->cll_alt.zidx = -1;
4976 hwb = &s->hw_buf_info[hwidx];
4977 swz = &s->sw_zone_info[hwb->zidx];
4978 spare = swz->size - hwb->size;
4979 fl->cll_alt.hwidx = hwidx;
4980 fl->cll_alt.zidx = hwb->zidx;
4981 if (allow_mbufs_in_cluster &&
4982 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
4983 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4985 fl->cll_alt.region1 = 0;
4986 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4990 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4992 mtx_lock(&sc->sfl_lock);
4994 if ((fl->flags & FL_DOOMED) == 0) {
4995 fl->flags |= FL_STARVING;
4996 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4997 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5000 mtx_unlock(&sc->sfl_lock);
5004 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5006 struct sge_wrq *wrq = (void *)eq;
5008 atomic_readandclear_int(&eq->equiq);
5009 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5013 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5015 struct sge_txq *txq = (void *)eq;
5017 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5019 atomic_readandclear_int(&eq->equiq);
5020 mp_ring_check_drainage(txq->r, 0);
5021 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5025 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5028 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5029 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5030 struct adapter *sc = iq->adapter;
5031 struct sge *s = &sc->sge;
5033 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5034 &handle_wrq_egr_update, &handle_eth_egr_update,
5035 &handle_wrq_egr_update};
5037 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5040 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5041 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5046 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5047 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5048 offsetof(struct cpl_fw6_msg, data));
5051 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5053 struct adapter *sc = iq->adapter;
5054 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5056 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5059 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5060 const struct rss_header *rss2;
5062 rss2 = (const struct rss_header *)&cpl->data[0];
5063 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5066 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5070 * t4_handle_wrerr_rpl - process a FW work request error message
5071 * @adap: the adapter
5072 * @rpl: start of the FW message
5075 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5077 u8 opcode = *(const u8 *)rpl;
5078 const struct fw_error_cmd *e = (const void *)rpl;
5081 if (opcode != FW_ERROR_CMD) {
5083 "%s: Received WRERR_RPL message with opcode %#x\n",
5084 device_get_nameunit(adap->dev), opcode);
5087 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5088 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5090 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5091 case FW_ERROR_TYPE_EXCEPTION:
5092 log(LOG_ERR, "exception info:\n");
5093 for (i = 0; i < nitems(e->u.exception.info); i++)
5094 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5095 be32toh(e->u.exception.info[i]));
5098 case FW_ERROR_TYPE_HWMODULE:
5099 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5100 be32toh(e->u.hwmodule.regaddr),
5101 be32toh(e->u.hwmodule.regval));
5103 case FW_ERROR_TYPE_WR:
5104 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5105 be16toh(e->u.wr.cidx),
5106 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5107 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5108 be32toh(e->u.wr.eqid));
5109 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5110 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5114 case FW_ERROR_TYPE_ACL:
5115 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5116 be16toh(e->u.acl.cidx),
5117 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5118 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5119 be32toh(e->u.acl.eqid),
5120 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5122 for (i = 0; i < nitems(e->u.acl.val); i++)
5123 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5127 log(LOG_ERR, "type %#x\n",
5128 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5135 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5137 uint16_t *id = arg1;
5140 return sysctl_handle_int(oidp, &i, 0, req);
5144 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5146 struct sge *s = arg1;
5147 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5148 struct sw_zone_info *swz = &s->sw_zone_info[0];
5153 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5154 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5155 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5160 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5164 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5170 sysctl_tc(SYSCTL_HANDLER_ARGS)
5172 struct vi_info *vi = arg1;
5173 struct port_info *pi;
5175 struct sge_txq *txq;
5176 struct tx_sched_class *tc;
5177 int qidx = arg2, rc, tc_idx;
5178 uint32_t fw_queue, fw_class;
5180 MPASS(qidx >= 0 && qidx < vi->ntxq);
5183 txq = &sc->sge.txq[vi->first_txq + qidx];
5185 tc_idx = txq->tc_idx;
5186 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5187 if (rc != 0 || req->newptr == NULL)
5190 /* Note that -1 is legitimate input (it means unbind). */
5191 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5194 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5198 if (tc_idx == txq->tc_idx) {
5199 rc = 0; /* No change, nothing to do. */
5203 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5204 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5205 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5208 fw_class = 0xffffffff; /* Unbind. */
5211 * Bind to a different class. Ethernet txq's are only allowed
5212 * to bind to cl-rl mode-class for now. XXX: too restrictive.
5214 tc = &pi->tc[tc_idx];
5215 if (tc->flags & TX_SC_OK &&
5216 tc->params.level == SCHED_CLASS_LEVEL_CL_RL &&
5217 tc->params.mode == SCHED_CLASS_MODE_CLASS) {
5218 /* Ok to proceed. */
5221 rc = tc->flags & TX_SC_OK ? EBUSY : ENXIO;
5226 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5228 if (txq->tc_idx != -1) {
5229 tc = &pi->tc[txq->tc_idx];
5230 MPASS(tc->refcount > 0);
5234 tc = &pi->tc[tc_idx];
5237 txq->tc_idx = tc_idx;
5240 end_synchronized_op(sc, 0);