2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
71 #include "t4_mp_ring.h"
73 #ifdef T4_PKT_TIMESTAMP
74 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
76 #define RX_COPY_THRESHOLD MINCLSIZE
80 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
81 * 0-7 are valid values.
84 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
87 * Pad ethernet payload up to this boundary.
88 * -1: driver should figure out a good value.
90 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
93 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
97 * -1: driver should figure out a good value.
98 * 64 or 128 are the only other valid values.
101 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
105 * -1: no congestion feedback (not recommended).
106 * 0: backpressure the channel instead of dropping packets right away.
107 * 1: no backpressure, drop packets for the congested queue immediately.
109 static int cong_drop = 0;
110 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
113 * Deliver multiple frames in the same free list buffer if they fit.
114 * -1: let the driver decide whether to enable buffer packing or not.
115 * 0: disable buffer packing.
116 * 1: enable buffer packing.
118 static int buffer_packing = -1;
119 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
122 * Start next frame in a packed buffer at this boundary.
123 * -1: driver should figure out a good value.
124 * T4: driver will ignore this and use the same value as fl_pad above.
125 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
127 static int fl_pack = -1;
128 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
131 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
132 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
133 * 1: ok to create mbuf(s) within a cluster if there is room.
135 static int allow_mbufs_in_cluster = 1;
136 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
139 * Largest rx cluster size that the driver is allowed to allocate.
141 static int largest_rx_cluster = MJUM16BYTES;
142 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
145 * Size of cluster allocation that's most likely to succeed. The driver will
146 * fall back to this size if it fails to allocate clusters larger than this.
148 static int safest_rx_cluster = PAGE_SIZE;
149 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
152 u_int wr_type; /* type 0 or type 1 */
153 u_int npkt; /* # of packets in this work request */
154 u_int plen; /* total payload (sum of all packets) */
155 u_int len16; /* # of 16B pieces used by this work request */
158 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
161 struct sglist_seg seg[TX_SGL_SEGS];
164 static int service_iq(struct sge_iq *, int);
165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
169 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
172 bus_addr_t *, void **);
173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
175 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
177 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
180 static int alloc_fwq(struct adapter *);
181 static int free_fwq(struct adapter *);
182 static int alloc_mgmtq(struct adapter *);
183 static int free_mgmtq(struct adapter *);
184 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
185 struct sysctl_oid *);
186 static int free_rxq(struct vi_info *, struct sge_rxq *);
188 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
189 struct sysctl_oid *);
190 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
193 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
194 struct sysctl_oid *);
195 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
196 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
197 struct sysctl_oid *);
198 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
201 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
203 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
205 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
206 static int free_eq(struct adapter *, struct sge_eq *);
207 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
208 struct sysctl_oid *);
209 static int free_wrq(struct adapter *, struct sge_wrq *);
210 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
211 struct sysctl_oid *);
212 static int free_txq(struct vi_info *, struct sge_txq *);
213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
214 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
215 static int refill_fl(struct adapter *, struct sge_fl *, int);
216 static void refill_sfl(void *);
217 static int alloc_fl_sdesc(struct sge_fl *);
218 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
220 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
223 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
224 static inline u_int txpkt_len16(u_int, u_int);
225 static inline u_int txpkts0_len16(u_int);
226 static inline u_int txpkts1_len16(void);
227 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
228 struct mbuf *, u_int);
229 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
230 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
231 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
232 struct mbuf *, const struct txpkts *, u_int);
233 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
234 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
235 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
236 static inline uint16_t read_hw_cidx(struct sge_eq *);
237 static inline u_int reclaimable_tx_desc(struct sge_eq *);
238 static inline u_int total_available_tx_desc(struct sge_eq *);
239 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
240 static void tx_reclaim(void *, int);
241 static __be64 get_flit(struct sglist_seg *, int, int);
242 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
244 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
246 static void wrq_tx_drain(void *, int);
247 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
249 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
250 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
252 static counter_u64_t extfree_refs;
253 static counter_u64_t extfree_rels;
256 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
262 if (fl_pktshift < 0 || fl_pktshift > 7) {
263 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
264 " using 2 instead.\n", fl_pktshift);
268 if (spg_len != 64 && spg_len != 128) {
271 #if defined(__i386__) || defined(__amd64__)
272 len = cpu_clflush_line_size > 64 ? 128 : 64;
277 printf("Invalid hw.cxgbe.spg_len value (%d),"
278 " using %d instead.\n", spg_len, len);
283 if (cong_drop < -1 || cong_drop > 1) {
284 printf("Invalid hw.cxgbe.cong_drop value (%d),"
285 " using 0 instead.\n", cong_drop);
289 extfree_refs = counter_u64_alloc(M_WAITOK);
290 extfree_rels = counter_u64_alloc(M_WAITOK);
291 counter_u64_zero(extfree_refs);
292 counter_u64_zero(extfree_rels);
296 t4_sge_modunload(void)
299 counter_u64_free(extfree_refs);
300 counter_u64_free(extfree_rels);
304 t4_sge_extfree_refs(void)
308 rels = counter_u64_fetch(extfree_rels);
309 refs = counter_u64_fetch(extfree_refs);
311 return (refs - rels);
315 t4_init_sge_cpl_handlers(struct adapter *sc)
318 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
319 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
320 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
321 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
322 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
326 setup_pad_and_pack_boundaries(struct adapter *sc)
332 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
334 * If there is any chance that we might use buffer packing and
335 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
336 * it to 32 in all other cases.
338 pad = is_t4(sc) && buffer_packing ? 64 : 32;
341 * For fl_pad = 0 we'll still write a reasonable value to the
342 * register but all the freelists will opt out of padding.
343 * We'll complain here only if the user tried to set it to a
344 * value greater than 0 that was invalid.
347 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
348 " (%d), using %d instead.\n", fl_pad, pad);
351 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
352 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
353 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
356 if (fl_pack != -1 && fl_pack != pad) {
357 /* Complain but carry on. */
358 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
359 " using %d instead.\n", fl_pack, pad);
365 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
366 !powerof2(fl_pack)) {
367 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
368 MPASS(powerof2(pack));
376 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
377 " (%d), using %d instead.\n", fl_pack, pack);
380 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
382 v = V_INGPACKBOUNDARY(0);
384 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
386 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
387 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
391 * adap->params.vpd.cclk must be set up before this is called.
394 t4_tweak_chip_settings(struct adapter *sc)
398 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
399 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
400 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
401 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
402 static int sge_flbuf_sizes[] = {
404 #if MJUMPAGESIZE != MCLBYTES
406 MJUMPAGESIZE - CL_METADATA_SIZE,
407 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
411 MCLBYTES - MSIZE - CL_METADATA_SIZE,
412 MJUM9BYTES - CL_METADATA_SIZE,
413 MJUM16BYTES - CL_METADATA_SIZE,
416 KASSERT(sc->flags & MASTER_PF,
417 ("%s: trying to change chip settings when not master.", __func__));
419 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
420 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
421 V_EGRSTATUSPAGESIZE(spg_len == 128);
422 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
424 setup_pad_and_pack_boundaries(sc);
426 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
429 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
430 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
431 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
432 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
433 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
434 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
436 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
437 ("%s: hw buffer size table too big", __func__));
438 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
439 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
443 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
444 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
445 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
447 KASSERT(intr_timer[0] <= timer_max,
448 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
450 for (i = 1; i < nitems(intr_timer); i++) {
451 KASSERT(intr_timer[i] >= intr_timer[i - 1],
452 ("%s: timers not listed in increasing order (%d)",
455 while (intr_timer[i] > timer_max) {
456 if (i == nitems(intr_timer) - 1) {
457 intr_timer[i] = timer_max;
460 intr_timer[i] += intr_timer[i - 1];
465 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
466 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
467 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
468 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
469 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
470 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
471 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
472 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
473 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
475 /* 4K, 16K, 64K, 256K DDP "page sizes" */
476 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
477 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
479 m = v = F_TDDPTAGTCB;
480 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
482 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
484 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
485 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
489 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
490 * padding is is use the buffer's start and end need to be aligned to the pad
491 * boundary as well. We'll just make sure that the size is a multiple of the
492 * boundary here, it is up to the buffer allocation code to make sure the start
493 * of the buffer is aligned as well.
496 hwsz_ok(struct adapter *sc, int hwsz)
498 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
500 return (hwsz >= 64 && (hwsz & mask) == 0);
504 * XXX: driver really should be able to deal with unexpected settings.
507 t4_read_chip_settings(struct adapter *sc)
509 struct sge *s = &sc->sge;
510 struct sge_params *sp = &sc->params.sge;
513 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
514 static int sw_buf_sizes[] = { /* Sorted by size */
516 #if MJUMPAGESIZE != MCLBYTES
522 struct sw_zone_info *swz, *safe_swz;
523 struct hw_buf_info *hwb;
525 t4_init_sge_params(sc);
529 r = t4_read_reg(sc, A_SGE_CONTROL);
531 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
536 * If this changes then every single use of PAGE_SHIFT in the driver
537 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
539 if (sp->page_shift != PAGE_SHIFT) {
540 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
544 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
545 hwb = &s->hw_buf_info[0];
546 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
547 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
549 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
554 * Create a sorted list in decreasing order of hw buffer sizes (and so
555 * increasing order of spare area) for each software zone.
557 * If padding is enabled then the start and end of the buffer must align
558 * to the pad boundary; if packing is enabled then they must align with
559 * the pack boundary as well. Allocations from the cluster zones are
560 * aligned to min(size, 4K), so the buffer starts at that alignment and
561 * ends at hwb->size alignment. If mbuf inlining is allowed the
562 * starting alignment will be reduced to MSIZE and the driver will
563 * exercise appropriate caution when deciding on the best buffer layout
566 n = 0; /* no usable buffer size to begin with */
567 swz = &s->sw_zone_info[0];
569 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
570 int8_t head = -1, tail = -1;
572 swz->size = sw_buf_sizes[i];
573 swz->zone = m_getzone(swz->size);
574 swz->type = m_gettype(swz->size);
576 if (swz->size < PAGE_SIZE) {
577 MPASS(powerof2(swz->size));
578 if (fl_pad && (swz->size % sp->pad_boundary != 0))
582 if (swz->size == safest_rx_cluster)
585 hwb = &s->hw_buf_info[0];
586 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
587 if (hwb->zidx != -1 || hwb->size > swz->size)
591 MPASS(hwb->size % sp->pad_boundary == 0);
596 else if (hwb->size < s->hw_buf_info[tail].size) {
597 s->hw_buf_info[tail].next = j;
601 struct hw_buf_info *t;
603 for (cur = &head; *cur != -1; cur = &t->next) {
604 t = &s->hw_buf_info[*cur];
605 if (hwb->size == t->size) {
609 if (hwb->size > t->size) {
617 swz->head_hwidx = head;
618 swz->tail_hwidx = tail;
622 if (swz->size - s->hw_buf_info[tail].size >=
624 sc->flags |= BUF_PACKING_OK;
628 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
634 if (safe_swz != NULL) {
635 s->safe_hwidx1 = safe_swz->head_hwidx;
636 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
639 hwb = &s->hw_buf_info[i];
642 MPASS(hwb->size % sp->pad_boundary == 0);
644 spare = safe_swz->size - hwb->size;
645 if (spare >= CL_METADATA_SIZE) {
652 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
653 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
655 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
659 m = v = F_TDDPTAGTCB;
660 r = t4_read_reg(sc, A_ULP_RX_CTL);
662 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
666 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
668 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
669 r = t4_read_reg(sc, A_TP_PARA_REG5);
671 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
675 t4_init_tp_params(sc);
677 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
678 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
684 t4_create_dma_tag(struct adapter *sc)
688 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
689 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
690 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
693 device_printf(sc->dev,
694 "failed to create main DMA tag: %d\n", rc);
701 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
702 struct sysctl_oid_list *children)
704 struct sge_params *sp = &sc->params.sge;
706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
707 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
708 "freelist buffer sizes");
710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
711 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
713 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
714 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
716 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
717 NULL, sp->spg_len, "status page size (bytes)");
719 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
720 NULL, cong_drop, "congestion drop setting");
722 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
723 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
727 t4_destroy_dma_tag(struct adapter *sc)
730 bus_dma_tag_destroy(sc->dmat);
736 * Allocate and initialize the firmware event queue and the management queue.
738 * Returns errno on failure. Resources allocated up to that point may still be
739 * allocated. Caller is responsible for cleanup in case this function fails.
742 t4_setup_adapter_queues(struct adapter *sc)
746 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
748 sysctl_ctx_init(&sc->ctx);
749 sc->flags |= ADAP_SYSCTL_CTX;
752 * Firmware event queue
759 * Management queue. This is just a control queue that uses the fwq as
762 rc = alloc_mgmtq(sc);
771 t4_teardown_adapter_queues(struct adapter *sc)
774 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
776 /* Do this before freeing the queue */
777 if (sc->flags & ADAP_SYSCTL_CTX) {
778 sysctl_ctx_free(&sc->ctx);
779 sc->flags &= ~ADAP_SYSCTL_CTX;
789 first_vector(struct vi_info *vi)
791 struct adapter *sc = vi->pi->adapter;
793 if (sc->intr_count == 1)
796 return (vi->first_intr);
800 * Given an arbitrary "index," come up with an iq that can be used by other
801 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
802 * The iq returned is guaranteed to be something that takes direct interrupts.
804 static struct sge_iq *
805 vi_intr_iq(struct vi_info *vi, int idx)
807 struct adapter *sc = vi->pi->adapter;
808 struct sge *s = &sc->sge;
809 struct sge_iq *iq = NULL;
812 if (sc->intr_count == 1)
813 return (&sc->sge.fwq);
815 KASSERT(!(vi->flags & VI_NETMAP),
816 ("%s: called on netmap VI", __func__));
819 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
820 __func__, vi, sc->intr_count));
823 if (vi->flags & INTR_RXQ) {
825 iq = &s->rxq[vi->first_rxq + i].iq;
831 if (vi->flags & INTR_OFLD_RXQ) {
832 if (i < vi->nofldrxq) {
833 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
839 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
840 vi, vi->flags & INTR_ALL, idx, nintr);
843 KASSERT(iq->flags & IQ_INTR,
844 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
845 vi->flags & INTR_ALL, idx));
849 /* Maximum payload that can be delivered with a single iq descriptor */
851 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
857 payload = sc->tt.rx_coalesce ?
858 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
861 /* large enough even when hw VLAN extraction is disabled */
862 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
863 ETHER_VLAN_ENCAP_LEN + mtu;
872 t4_setup_vi_queues(struct vi_info *vi)
874 int rc = 0, i, j, intr_idx, iqid;
877 struct sge_wrq *ctrlq;
879 struct sge_ofld_rxq *ofld_rxq;
880 struct sge_wrq *ofld_txq;
883 struct sge_nm_rxq *nm_rxq;
884 struct sge_nm_txq *nm_txq;
887 struct port_info *pi = vi->pi;
888 struct adapter *sc = pi->adapter;
889 struct ifnet *ifp = vi->ifp;
890 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
891 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
892 int maxp, mtu = ifp->if_mtu;
894 /* Interrupt vector to start from (when using multiple vectors) */
895 intr_idx = first_vector(vi);
898 if (vi->flags & VI_NETMAP) {
900 * We don't have buffers to back the netmap rx queues
901 * right now so we create the queues in a way that
902 * doesn't set off any congestion signal in the chip.
904 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
905 CTLFLAG_RD, NULL, "rx queues");
906 for_each_nm_rxq(vi, i, nm_rxq) {
907 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
913 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq",
914 CTLFLAG_RD, NULL, "tx queues");
915 for_each_nm_txq(vi, i, nm_txq) {
916 iqid = vi->first_rxq + (i % vi->nrxq);
917 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
926 * First pass over all NIC and TOE rx queues:
927 * a) initialize iq and fl
928 * b) allocate queue iff it will take direct interrupts.
930 maxp = mtu_to_max_payload(sc, mtu, 0);
931 if (vi->flags & INTR_RXQ) {
932 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
933 CTLFLAG_RD, NULL, "rx queues");
935 for_each_rxq(vi, i, rxq) {
937 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
939 snprintf(name, sizeof(name), "%s rxq%d-fl",
940 device_get_nameunit(vi->dev), i);
941 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
943 if (vi->flags & INTR_RXQ) {
944 rxq->iq.flags |= IQ_INTR;
945 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
952 maxp = mtu_to_max_payload(sc, mtu, 1);
953 if (vi->flags & INTR_OFLD_RXQ) {
954 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
956 "rx queues for offloaded TCP connections");
958 for_each_ofld_rxq(vi, i, ofld_rxq) {
960 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
963 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
964 device_get_nameunit(vi->dev), i);
965 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
967 if (vi->flags & INTR_OFLD_RXQ) {
968 ofld_rxq->iq.flags |= IQ_INTR;
969 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
978 * Second pass over all NIC and TOE rx queues. The queues forwarding
979 * their interrupts are allocated now.
982 if (!(vi->flags & INTR_RXQ)) {
983 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
984 CTLFLAG_RD, NULL, "rx queues");
985 for_each_rxq(vi, i, rxq) {
986 MPASS(!(rxq->iq.flags & IQ_INTR));
988 intr_idx = vi_intr_iq(vi, j)->abs_id;
990 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
997 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
998 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1000 "rx queues for offloaded TCP connections");
1001 for_each_ofld_rxq(vi, i, ofld_rxq) {
1002 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1004 intr_idx = vi_intr_iq(vi, j)->abs_id;
1006 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1015 * Now the tx queues. Only one pass needed.
1017 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1020 for_each_txq(vi, i, txq) {
1021 iqid = vi_intr_iq(vi, j)->cntxt_id;
1022 snprintf(name, sizeof(name), "%s txq%d",
1023 device_get_nameunit(vi->dev), i);
1024 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1027 rc = alloc_txq(vi, txq, i, oid);
1033 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1034 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1035 for_each_ofld_txq(vi, i, ofld_txq) {
1036 struct sysctl_oid *oid2;
1038 iqid = vi_intr_iq(vi, j)->cntxt_id;
1039 snprintf(name, sizeof(name), "%s ofld_txq%d",
1040 device_get_nameunit(vi->dev), i);
1041 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1044 snprintf(name, sizeof(name), "%d", i);
1045 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1046 name, CTLFLAG_RD, NULL, "offload tx queue");
1048 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1056 * Finally, the control queue.
1058 if (!IS_MAIN_VI(vi))
1060 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1061 NULL, "ctrl queue");
1062 ctrlq = &sc->sge.ctrlq[pi->port_id];
1063 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1064 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1065 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1067 rc = alloc_wrq(sc, vi, ctrlq, oid);
1071 t4_teardown_vi_queues(vi);
1080 t4_teardown_vi_queues(struct vi_info *vi)
1083 struct port_info *pi = vi->pi;
1084 struct adapter *sc = pi->adapter;
1085 struct sge_rxq *rxq;
1086 struct sge_txq *txq;
1088 struct sge_ofld_rxq *ofld_rxq;
1089 struct sge_wrq *ofld_txq;
1092 struct sge_nm_rxq *nm_rxq;
1093 struct sge_nm_txq *nm_txq;
1096 /* Do this before freeing the queues */
1097 if (vi->flags & VI_SYSCTL_CTX) {
1098 sysctl_ctx_free(&vi->ctx);
1099 vi->flags &= ~VI_SYSCTL_CTX;
1103 if (vi->flags & VI_NETMAP) {
1104 for_each_nm_txq(vi, i, nm_txq) {
1105 free_nm_txq(vi, nm_txq);
1108 for_each_nm_rxq(vi, i, nm_rxq) {
1109 free_nm_rxq(vi, nm_rxq);
1116 * Take down all the tx queues first, as they reference the rx queues
1117 * (for egress updates, etc.).
1121 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1123 for_each_txq(vi, i, txq) {
1127 for_each_ofld_txq(vi, i, ofld_txq) {
1128 free_wrq(sc, ofld_txq);
1133 * Then take down the rx queues that forward their interrupts, as they
1134 * reference other rx queues.
1137 for_each_rxq(vi, i, rxq) {
1138 if ((rxq->iq.flags & IQ_INTR) == 0)
1142 for_each_ofld_rxq(vi, i, ofld_rxq) {
1143 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1144 free_ofld_rxq(vi, ofld_rxq);
1149 * Then take down the rx queues that take direct interrupts.
1152 for_each_rxq(vi, i, rxq) {
1153 if (rxq->iq.flags & IQ_INTR)
1157 for_each_ofld_rxq(vi, i, ofld_rxq) {
1158 if (ofld_rxq->iq.flags & IQ_INTR)
1159 free_ofld_rxq(vi, ofld_rxq);
1167 * Deals with errors and the firmware event queue. All data rx queues forward
1168 * their interrupt to the firmware event queue.
1171 t4_intr_all(void *arg)
1173 struct adapter *sc = arg;
1174 struct sge_iq *fwq = &sc->sge.fwq;
1177 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1179 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1183 /* Deals with error interrupts */
1185 t4_intr_err(void *arg)
1187 struct adapter *sc = arg;
1189 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1190 t4_slow_intr_handler(sc);
1194 t4_intr_evt(void *arg)
1196 struct sge_iq *iq = arg;
1198 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1200 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1207 struct sge_iq *iq = arg;
1209 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1211 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1216 * Deals with anything and everything on the given ingress queue.
1219 service_iq(struct sge_iq *iq, int budget)
1222 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1223 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1224 struct adapter *sc = iq->adapter;
1225 struct iq_desc *d = &iq->desc[iq->cidx];
1226 int ndescs = 0, limit;
1227 int rsp_type, refill;
1229 uint16_t fl_hw_cidx;
1231 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1232 #if defined(INET) || defined(INET6)
1233 const struct timeval lro_timeout = {0, sc->lro_timeout};
1236 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1238 limit = budget ? budget : iq->qsize / 16;
1240 if (iq->flags & IQ_HAS_FL) {
1242 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1245 fl_hw_cidx = 0; /* to silence gcc warning */
1249 * We always come back and check the descriptor ring for new indirect
1250 * interrupts and other responses after running a single handler.
1253 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1259 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1260 lq = be32toh(d->rsp.pldbuflen_qid);
1263 case X_RSPD_TYPE_FLBUF:
1265 KASSERT(iq->flags & IQ_HAS_FL,
1266 ("%s: data for an iq (%p) with no freelist",
1269 m0 = get_fl_payload(sc, fl, lq);
1270 if (__predict_false(m0 == NULL))
1272 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1273 #ifdef T4_PKT_TIMESTAMP
1275 * 60 bit timestamp for the payload is
1276 * *(uint64_t *)m0->m_pktdat. Note that it is
1277 * in the leading free-space in the mbuf. The
1278 * kernel can clobber it during a pullup,
1279 * m_copymdata, etc. You need to make sure that
1280 * the mbuf reaches you unmolested if you care
1281 * about the timestamp.
1283 *(uint64_t *)m0->m_pktdat =
1284 be64toh(ctrl->u.last_flit) &
1290 case X_RSPD_TYPE_CPL:
1291 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1292 ("%s: bad opcode %02x.", __func__,
1294 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1297 case X_RSPD_TYPE_INTR:
1300 * Interrupts should be forwarded only to queues
1301 * that are not forwarding their interrupts.
1302 * This means service_iq can recurse but only 1
1305 KASSERT(budget == 0,
1306 ("%s: budget %u, rsp_type %u", __func__,
1310 * There are 1K interrupt-capable queues (qids 0
1311 * through 1023). A response type indicating a
1312 * forwarded interrupt with a qid >= 1K is an
1313 * iWARP async notification.
1316 sc->an_handler(iq, &d->rsp);
1320 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1321 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1323 if (service_iq(q, q->qsize / 16) == 0) {
1324 atomic_cmpset_int(&q->state,
1325 IQS_BUSY, IQS_IDLE);
1327 STAILQ_INSERT_TAIL(&iql, q,
1335 ("%s: illegal response type %d on iq %p",
1336 __func__, rsp_type, iq));
1338 "%s: illegal response type %d on iq %p",
1339 device_get_nameunit(sc->dev), rsp_type, iq);
1344 if (__predict_false(++iq->cidx == iq->sidx)) {
1346 iq->gen ^= F_RSPD_GEN;
1349 if (__predict_false(++ndescs == limit)) {
1350 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1352 V_INGRESSQID(iq->cntxt_id) |
1353 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1356 #if defined(INET) || defined(INET6)
1357 if (iq->flags & IQ_LRO_ENABLED &&
1358 sc->lro_timeout != 0) {
1359 tcp_lro_flush_inactive(&rxq->lro,
1365 if (iq->flags & IQ_HAS_FL) {
1367 refill_fl(sc, fl, 32);
1370 return (EINPROGRESS);
1375 refill_fl(sc, fl, 32);
1377 fl_hw_cidx = fl->hw_cidx;
1382 if (STAILQ_EMPTY(&iql))
1386 * Process the head only, and send it to the back of the list if
1387 * it's still not done.
1389 q = STAILQ_FIRST(&iql);
1390 STAILQ_REMOVE_HEAD(&iql, link);
1391 if (service_iq(q, q->qsize / 8) == 0)
1392 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1394 STAILQ_INSERT_TAIL(&iql, q, link);
1397 #if defined(INET) || defined(INET6)
1398 if (iq->flags & IQ_LRO_ENABLED) {
1399 struct lro_ctrl *lro = &rxq->lro;
1401 tcp_lro_flush_all(lro);
1405 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1406 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1408 if (iq->flags & IQ_HAS_FL) {
1412 starved = refill_fl(sc, fl, 64);
1414 if (__predict_false(starved != 0))
1415 add_fl_to_sfl(sc, fl);
1422 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1424 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1427 MPASS(cll->region3 >= CL_METADATA_SIZE);
1432 static inline struct cluster_metadata *
1433 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1437 if (cl_has_metadata(fl, cll)) {
1438 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1440 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1446 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1448 uma_zone_t zone = arg1;
1451 uma_zfree(zone, cl);
1452 counter_u64_add(extfree_rels, 1);
1456 * The mbuf returned by this function could be allocated from zone_mbuf or
1457 * constructed in spare room in the cluster.
1459 * The mbuf carries the payload in one of these ways
1460 * a) frame inside the mbuf (mbuf from zone_mbuf)
1461 * b) m_cljset (for clusters without metadata) zone_mbuf
1462 * c) m_extaddref (cluster with metadata) inline mbuf
1463 * d) m_extaddref (cluster with metadata) zone_mbuf
1465 static struct mbuf *
1466 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1470 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1471 struct cluster_layout *cll = &sd->cll;
1472 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1473 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1474 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1478 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1479 len = min(remaining, blen);
1480 payload = sd->cl + cll->region1 + fl->rx_offset;
1481 if (fl->flags & FL_BUF_PACKING) {
1482 const u_int l = fr_offset + len;
1483 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1485 if (fl->rx_offset + len + pad < hwb->size)
1487 MPASS(fl->rx_offset + blen <= hwb->size);
1489 MPASS(fl->rx_offset == 0); /* not packing */
1493 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1496 * Copy payload into a freshly allocated mbuf.
1499 m = fr_offset == 0 ?
1500 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1503 fl->mbuf_allocated++;
1504 #ifdef T4_PKT_TIMESTAMP
1505 /* Leave room for a timestamp */
1508 /* copy data to mbuf */
1509 bcopy(payload, mtod(m, caddr_t), len);
1511 } else if (sd->nmbuf * MSIZE < cll->region1) {
1514 * There's spare room in the cluster for an mbuf. Create one
1515 * and associate it with the payload that's in the cluster.
1519 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1520 /* No bzero required */
1521 if (m_init(m, M_NOWAIT, MT_DATA,
1522 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1525 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1527 if (sd->nmbuf++ == 0)
1528 counter_u64_add(extfree_refs, 1);
1533 * Grab an mbuf from zone_mbuf and associate it with the
1534 * payload in the cluster.
1537 m = fr_offset == 0 ?
1538 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1541 fl->mbuf_allocated++;
1543 m_extaddref(m, payload, blen, &clm->refcount,
1544 rxb_free, swz->zone, sd->cl);
1545 if (sd->nmbuf++ == 0)
1546 counter_u64_add(extfree_refs, 1);
1548 m_cljset(m, sd->cl, swz->type);
1549 sd->cl = NULL; /* consumed, not a recycle candidate */
1553 m->m_pkthdr.len = remaining;
1556 if (fl->flags & FL_BUF_PACKING) {
1557 fl->rx_offset += blen;
1558 MPASS(fl->rx_offset <= hwb->size);
1559 if (fl->rx_offset < hwb->size)
1560 return (m); /* without advancing the cidx */
1563 if (__predict_false(++fl->cidx % 8 == 0)) {
1564 uint16_t cidx = fl->cidx / 8;
1566 if (__predict_false(cidx == fl->sidx))
1567 fl->cidx = cidx = 0;
1575 static struct mbuf *
1576 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1578 struct mbuf *m0, *m, **pnext;
1580 const u_int total = G_RSPD_LEN(len_newbuf);
1582 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1583 M_ASSERTPKTHDR(fl->m0);
1584 MPASS(fl->m0->m_pkthdr.len == total);
1585 MPASS(fl->remaining < total);
1589 remaining = fl->remaining;
1590 fl->flags &= ~FL_BUF_RESUME;
1594 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1596 if (__predict_false(++fl->cidx % 8 == 0)) {
1597 uint16_t cidx = fl->cidx / 8;
1599 if (__predict_false(cidx == fl->sidx))
1600 fl->cidx = cidx = 0;
1606 * Payload starts at rx_offset in the current hw buffer. Its length is
1607 * 'len' and it may span multiple hw buffers.
1610 m0 = get_scatter_segment(sc, fl, 0, total);
1613 remaining = total - m0->m_len;
1614 pnext = &m0->m_next;
1615 while (remaining > 0) {
1617 MPASS(fl->rx_offset == 0);
1618 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1619 if (__predict_false(m == NULL)) {
1622 fl->remaining = remaining;
1623 fl->flags |= FL_BUF_RESUME;
1628 remaining -= m->m_len;
1637 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1639 struct sge_rxq *rxq = iq_to_rxq(iq);
1640 struct ifnet *ifp = rxq->ifp;
1641 struct adapter *sc = iq->adapter;
1642 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1643 #if defined(INET) || defined(INET6)
1644 struct lro_ctrl *lro = &rxq->lro;
1646 static const int sw_hashtype[4][2] = {
1647 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1648 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1649 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1650 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1653 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1656 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1657 m0->m_len -= sc->params.sge.fl_pktshift;
1658 m0->m_data += sc->params.sge.fl_pktshift;
1660 m0->m_pkthdr.rcvif = ifp;
1661 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1662 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1664 if (cpl->csum_calc && !cpl->err_vec) {
1665 if (ifp->if_capenable & IFCAP_RXCSUM &&
1666 cpl->l2info & htobe32(F_RXF_IP)) {
1667 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1668 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1670 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1671 cpl->l2info & htobe32(F_RXF_IP6)) {
1672 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1677 if (__predict_false(cpl->ip_frag))
1678 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1680 m0->m_pkthdr.csum_data = 0xffff;
1684 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1685 m0->m_flags |= M_VLANTAG;
1686 rxq->vlan_extraction++;
1689 #if defined(INET) || defined(INET6)
1690 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1691 iq->flags & IQ_LRO_ENABLED &&
1692 tcp_lro_rx(lro, m0, 0) == 0) {
1693 /* queued for LRO */
1696 ifp->if_input(ifp, m0);
1702 * Must drain the wrq or make sure that someone else will.
1705 wrq_tx_drain(void *arg, int n)
1707 struct sge_wrq *wrq = arg;
1708 struct sge_eq *eq = &wrq->eq;
1711 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1712 drain_wrq_wr_list(wrq->adapter, wrq);
1717 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1719 struct sge_eq *eq = &wrq->eq;
1720 u_int available, dbdiff; /* # of hardware descriptors */
1723 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1725 EQ_LOCK_ASSERT_OWNED(eq);
1726 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1727 wr = STAILQ_FIRST(&wrq->wr_list);
1728 MPASS(wr != NULL); /* Must be called with something useful to do */
1729 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
1732 eq->cidx = read_hw_cidx(eq);
1733 if (eq->pidx == eq->cidx)
1734 available = eq->sidx - 1;
1736 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1738 MPASS(wr->wrq == wrq);
1739 n = howmany(wr->wr_len, EQ_ESIZE);
1743 dst = (void *)&eq->desc[eq->pidx];
1744 if (__predict_true(eq->sidx - eq->pidx > n)) {
1745 /* Won't wrap, won't end exactly at the status page. */
1746 bcopy(&wr->wr[0], dst, wr->wr_len);
1749 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1751 bcopy(&wr->wr[0], dst, first_portion);
1752 if (wr->wr_len > first_portion) {
1753 bcopy(&wr->wr[first_portion], &eq->desc[0],
1754 wr->wr_len - first_portion);
1756 eq->pidx = n - (eq->sidx - eq->pidx);
1759 if (available < eq->sidx / 4 &&
1760 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1761 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1763 eq->equeqidx = eq->pidx;
1764 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1765 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1766 eq->equeqidx = eq->pidx;
1771 ring_eq_db(sc, eq, dbdiff);
1775 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1777 MPASS(wrq->nwr_pending > 0);
1779 MPASS(wrq->ndesc_needed >= n);
1780 wrq->ndesc_needed -= n;
1781 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1784 ring_eq_db(sc, eq, dbdiff);
1788 * Doesn't fail. Holds on to work requests it can't send right away.
1791 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1794 struct sge_eq *eq = &wrq->eq;
1797 EQ_LOCK_ASSERT_OWNED(eq);
1799 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1800 MPASS((wr->wr_len & 0x7) == 0);
1802 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1804 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1806 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1807 return; /* commit_wrq_wr will drain wr_list as well. */
1809 drain_wrq_wr_list(sc, wrq);
1811 /* Doorbell must have caught up to the pidx. */
1812 MPASS(eq->pidx == eq->dbidx);
1816 t4_update_fl_bufsize(struct ifnet *ifp)
1818 struct vi_info *vi = ifp->if_softc;
1819 struct adapter *sc = vi->pi->adapter;
1820 struct sge_rxq *rxq;
1822 struct sge_ofld_rxq *ofld_rxq;
1825 int i, maxp, mtu = ifp->if_mtu;
1827 maxp = mtu_to_max_payload(sc, mtu, 0);
1828 for_each_rxq(vi, i, rxq) {
1832 find_best_refill_source(sc, fl, maxp);
1836 maxp = mtu_to_max_payload(sc, mtu, 1);
1837 for_each_ofld_rxq(vi, i, ofld_rxq) {
1841 find_best_refill_source(sc, fl, maxp);
1848 mbuf_nsegs(struct mbuf *m)
1852 KASSERT(m->m_pkthdr.l5hlen > 0,
1853 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1855 return (m->m_pkthdr.l5hlen);
1859 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1863 m->m_pkthdr.l5hlen = nsegs;
1867 mbuf_len16(struct mbuf *m)
1872 n = m->m_pkthdr.PH_loc.eight[0];
1873 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1879 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1883 m->m_pkthdr.PH_loc.eight[0] = len16;
1887 needs_tso(struct mbuf *m)
1892 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1893 KASSERT(m->m_pkthdr.tso_segsz > 0,
1894 ("%s: TSO requested in mbuf %p but MSS not provided",
1903 needs_l3_csum(struct mbuf *m)
1908 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
1914 needs_l4_csum(struct mbuf *m)
1919 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
1920 CSUM_TCP_IPV6 | CSUM_TSO))
1926 needs_vlan_insertion(struct mbuf *m)
1931 if (m->m_flags & M_VLANTAG) {
1932 KASSERT(m->m_pkthdr.ether_vtag != 0,
1933 ("%s: HWVLAN requested in mbuf %p but tag not provided",
1941 m_advance(struct mbuf **pm, int *poffset, int len)
1943 struct mbuf *m = *pm;
1944 int offset = *poffset;
1950 if (offset + len < m->m_len) {
1952 p = mtod(m, uintptr_t) + offset;
1955 len -= m->m_len - offset;
1966 same_paddr(char *a, char *b)
1971 else if (a != NULL && b != NULL) {
1972 vm_offset_t x = (vm_offset_t)a;
1973 vm_offset_t y = (vm_offset_t)b;
1975 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
1976 pmap_kextract(x) == pmap_kextract(y))
1984 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
1985 * must have at least one mbuf that's not empty.
1988 count_mbuf_nsegs(struct mbuf *m)
1990 char *prev_end, *start;
1997 for (; m; m = m->m_next) {
2000 if (__predict_false(len == 0))
2002 start = mtod(m, char *);
2004 nsegs += sglist_count(start, len);
2005 if (same_paddr(prev_end, start))
2007 prev_end = start + len;
2015 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2016 * a) caller can assume it's been freed if this function returns with an error.
2017 * b) it may get defragged up if the gather list is too long for the hardware.
2020 parse_pkt(struct mbuf **mp)
2022 struct mbuf *m0 = *mp, *m;
2023 int rc, nsegs, defragged = 0, offset;
2024 struct ether_header *eh;
2026 #if defined(INET) || defined(INET6)
2032 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2041 * First count the number of gather list segments in the payload.
2042 * Defrag the mbuf if nsegs exceeds the hardware limit.
2045 MPASS(m0->m_pkthdr.len > 0);
2046 nsegs = count_mbuf_nsegs(m0);
2047 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2048 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2052 *mp = m0 = m; /* update caller's copy after defrag */
2056 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2057 m0 = m_pullup(m0, m0->m_pkthdr.len);
2059 /* Should have left well enough alone. */
2063 *mp = m0; /* update caller's copy after pullup */
2066 set_mbuf_nsegs(m0, nsegs);
2067 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2073 eh = mtod(m, struct ether_header *);
2074 eh_type = ntohs(eh->ether_type);
2075 if (eh_type == ETHERTYPE_VLAN) {
2076 struct ether_vlan_header *evh = (void *)eh;
2078 eh_type = ntohs(evh->evl_proto);
2079 m0->m_pkthdr.l2hlen = sizeof(*evh);
2081 m0->m_pkthdr.l2hlen = sizeof(*eh);
2084 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2088 case ETHERTYPE_IPV6:
2090 struct ip6_hdr *ip6 = l3hdr;
2092 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
2094 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2101 struct ip *ip = l3hdr;
2103 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2108 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2109 " with the same INET/INET6 options as the kernel.",
2113 #if defined(INET) || defined(INET6)
2114 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2115 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2122 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2124 struct sge_eq *eq = &wrq->eq;
2125 struct adapter *sc = wrq->adapter;
2126 int ndesc, available;
2131 ndesc = howmany(len16, EQ_ESIZE / 16);
2132 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2136 if (!STAILQ_EMPTY(&wrq->wr_list))
2137 drain_wrq_wr_list(sc, wrq);
2139 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2142 wr = alloc_wrqe(len16 * 16, wrq);
2143 if (__predict_false(wr == NULL))
2146 cookie->ndesc = ndesc;
2150 eq->cidx = read_hw_cidx(eq);
2151 if (eq->pidx == eq->cidx)
2152 available = eq->sidx - 1;
2154 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2155 if (available < ndesc)
2158 cookie->pidx = eq->pidx;
2159 cookie->ndesc = ndesc;
2160 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2162 w = &eq->desc[eq->pidx];
2163 IDXINCR(eq->pidx, ndesc, eq->sidx);
2164 if (__predict_false(eq->pidx < ndesc - 1)) {
2166 wrq->ss_pidx = cookie->pidx;
2167 wrq->ss_len = len16 * 16;
2176 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2178 struct sge_eq *eq = &wrq->eq;
2179 struct adapter *sc = wrq->adapter;
2181 struct wrq_cookie *prev, *next;
2183 if (cookie->pidx == -1) {
2184 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2190 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2191 pidx = cookie->pidx;
2192 MPASS(pidx >= 0 && pidx < eq->sidx);
2193 if (__predict_false(w == &wrq->ss[0])) {
2194 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2196 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2197 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2198 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2201 wrq->tx_wrs_direct++;
2204 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2205 next = TAILQ_NEXT(cookie, link);
2207 MPASS(pidx == eq->dbidx);
2208 if (next == NULL || ndesc >= 16)
2209 ring_eq_db(wrq->adapter, eq, ndesc);
2211 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2213 next->ndesc += ndesc;
2216 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2217 prev->ndesc += ndesc;
2219 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2221 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2222 drain_wrq_wr_list(sc, wrq);
2225 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2226 /* Doorbell must have caught up to the pidx. */
2227 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2234 can_resume_eth_tx(struct mp_ring *r)
2236 struct sge_eq *eq = r->cookie;
2238 return (total_available_tx_desc(eq) > eq->sidx / 8);
2242 cannot_use_txpkts(struct mbuf *m)
2244 /* maybe put a GL limit too, to avoid silliness? */
2246 return (needs_tso(m));
2250 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2251 * be consumed. Return the actual number consumed. 0 indicates a stall.
2254 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2256 struct sge_txq *txq = r->cookie;
2257 struct sge_eq *eq = &txq->eq;
2258 struct ifnet *ifp = txq->ifp;
2259 struct vi_info *vi = ifp->if_softc;
2260 struct port_info *pi = vi->pi;
2261 struct adapter *sc = pi->adapter;
2262 u_int total, remaining; /* # of packets */
2263 u_int available, dbdiff; /* # of hardware descriptors */
2265 struct mbuf *m0, *tail;
2267 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2269 remaining = IDXDIFF(pidx, cidx, r->size);
2270 MPASS(remaining > 0); /* Must not be called without work to do. */
2274 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2275 while (cidx != pidx) {
2276 m0 = r->items[cidx];
2278 if (++cidx == r->size)
2281 reclaim_tx_descs(txq, 2048);
2286 /* How many hardware descriptors do we have readily available. */
2287 if (eq->pidx == eq->cidx)
2288 available = eq->sidx - 1;
2290 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2291 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2293 while (remaining > 0) {
2295 m0 = r->items[cidx];
2297 MPASS(m0->m_nextpkt == NULL);
2299 if (available < SGE_MAX_WR_NDESC) {
2300 available += reclaim_tx_descs(txq, 64);
2301 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2302 break; /* out of descriptors */
2305 next_cidx = cidx + 1;
2306 if (__predict_false(next_cidx == r->size))
2309 wr = (void *)&eq->desc[eq->pidx];
2310 if (remaining > 1 &&
2311 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2313 /* pkts at cidx, next_cidx should both be in txp. */
2314 MPASS(txp.npkt == 2);
2315 tail = r->items[next_cidx];
2316 MPASS(tail->m_nextpkt == NULL);
2317 ETHER_BPF_MTAP(ifp, m0);
2318 ETHER_BPF_MTAP(ifp, tail);
2319 m0->m_nextpkt = tail;
2321 if (__predict_false(++next_cidx == r->size))
2324 while (next_cidx != pidx) {
2325 if (add_to_txpkts(r->items[next_cidx], &txp,
2328 tail->m_nextpkt = r->items[next_cidx];
2329 tail = tail->m_nextpkt;
2330 ETHER_BPF_MTAP(ifp, tail);
2331 if (__predict_false(++next_cidx == r->size))
2335 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2337 remaining -= txp.npkt;
2341 ETHER_BPF_MTAP(ifp, m0);
2342 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2344 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2348 IDXINCR(eq->pidx, n, eq->sidx);
2350 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2351 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2352 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2354 eq->equeqidx = eq->pidx;
2355 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2356 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2357 eq->equeqidx = eq->pidx;
2360 if (dbdiff >= 16 && remaining >= 4) {
2361 ring_eq_db(sc, eq, dbdiff);
2362 available += reclaim_tx_descs(txq, 4 * dbdiff);
2369 ring_eq_db(sc, eq, dbdiff);
2370 reclaim_tx_descs(txq, 32);
2379 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2383 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2384 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2385 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2386 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2390 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2391 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2392 if (pktc_idx >= 0) {
2393 iq->intr_params |= F_QINTR_CNT_EN;
2394 iq->intr_pktc_idx = pktc_idx;
2396 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2397 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2401 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2405 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2406 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2407 if (sc->flags & BUF_PACKING_OK &&
2408 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2409 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2410 fl->flags |= FL_BUF_PACKING;
2411 find_best_refill_source(sc, fl, maxp);
2412 find_safe_refill_source(sc, fl);
2416 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2417 uint8_t tx_chan, uint16_t iqid, char *name)
2419 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2421 eq->flags = eqtype & EQ_TYPEMASK;
2422 eq->tx_chan = tx_chan;
2424 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2425 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2429 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2430 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2434 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2435 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2437 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2441 rc = bus_dmamem_alloc(*tag, va,
2442 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2444 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2448 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2450 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2455 free_ring(sc, *tag, *map, *pa, *va);
2461 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2462 bus_addr_t pa, void *va)
2465 bus_dmamap_unload(tag, map);
2467 bus_dmamem_free(tag, va, map);
2469 bus_dma_tag_destroy(tag);
2475 * Allocates the ring for an ingress queue and an optional freelist. If the
2476 * freelist is specified it will be allocated and then associated with the
2479 * Returns errno on failure. Resources allocated up to that point may still be
2480 * allocated. Caller is responsible for cleanup in case this function fails.
2482 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2483 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2484 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2487 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2488 int intr_idx, int cong)
2490 int rc, i, cntxt_id;
2493 struct port_info *pi = vi->pi;
2494 struct adapter *sc = iq->adapter;
2495 struct sge_params *sp = &sc->params.sge;
2498 len = iq->qsize * IQ_ESIZE;
2499 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2500 (void **)&iq->desc);
2504 bzero(&c, sizeof(c));
2505 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2506 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2507 V_FW_IQ_CMD_VFN(0));
2509 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2512 /* Special handling for firmware event queue */
2513 if (iq == &sc->sge.fwq)
2514 v |= F_FW_IQ_CMD_IQASYNCH;
2516 if (iq->flags & IQ_INTR) {
2517 KASSERT(intr_idx < sc->intr_count,
2518 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2520 v |= F_FW_IQ_CMD_IQANDST;
2521 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2523 c.type_to_iqandstindex = htobe32(v |
2524 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2525 V_FW_IQ_CMD_VIID(vi->viid) |
2526 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2527 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2528 F_FW_IQ_CMD_IQGTSMODE |
2529 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2530 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2531 c.iqsize = htobe16(iq->qsize);
2532 c.iqaddr = htobe64(iq->ba);
2534 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2537 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2539 len = fl->qsize * EQ_ESIZE;
2540 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2541 &fl->ba, (void **)&fl->desc);
2545 /* Allocate space for one software descriptor per buffer. */
2546 rc = alloc_fl_sdesc(fl);
2548 device_printf(sc->dev,
2549 "failed to setup fl software descriptors: %d\n",
2554 if (fl->flags & FL_BUF_PACKING) {
2555 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2556 fl->buf_boundary = sp->pack_boundary;
2558 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2559 fl->buf_boundary = 16;
2561 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2562 fl->buf_boundary = sp->pad_boundary;
2564 c.iqns_to_fl0congen |=
2565 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2566 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2567 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2568 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2571 c.iqns_to_fl0congen |=
2572 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2573 F_FW_IQ_CMD_FL0CONGCIF |
2574 F_FW_IQ_CMD_FL0CONGEN);
2576 c.fl0dcaen_to_fl0cidxfthresh =
2577 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
2578 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2579 c.fl0size = htobe16(fl->qsize);
2580 c.fl0addr = htobe64(fl->ba);
2583 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2585 device_printf(sc->dev,
2586 "failed to create ingress queue: %d\n", rc);
2591 iq->gen = F_RSPD_GEN;
2592 iq->intr_next = iq->intr_params;
2593 iq->cntxt_id = be16toh(c.iqid);
2594 iq->abs_id = be16toh(c.physiqid);
2595 iq->flags |= IQ_ALLOCATED;
2597 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2598 if (cntxt_id >= sc->sge.niq) {
2599 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2600 cntxt_id, sc->sge.niq - 1);
2602 sc->sge.iqmap[cntxt_id] = iq;
2607 iq->flags |= IQ_HAS_FL;
2608 fl->cntxt_id = be16toh(c.fl0id);
2609 fl->pidx = fl->cidx = 0;
2611 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2612 if (cntxt_id >= sc->sge.neq) {
2613 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2614 __func__, cntxt_id, sc->sge.neq - 1);
2616 sc->sge.eqmap[cntxt_id] = (void *)fl;
2619 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2620 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2621 uint32_t mask = (1 << s_qpp) - 1;
2622 volatile uint8_t *udb;
2624 udb = sc->udbs_base + UDBS_DB_OFFSET;
2625 udb += (qid >> s_qpp) << PAGE_SHIFT;
2627 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2628 udb += qid << UDBS_SEG_SHIFT;
2631 fl->udb = (volatile void *)udb;
2633 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2636 /* Enough to make sure the SGE doesn't think it's starved */
2637 refill_fl(sc, fl, fl->lowat);
2641 if (is_t5(sc) && cong >= 0) {
2642 uint32_t param, val;
2644 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2645 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2646 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2651 for (i = 0; i < 4; i++) {
2652 if (cong & (1 << i))
2653 val |= 1 << (i << 2);
2657 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2659 /* report error but carry on */
2660 device_printf(sc->dev,
2661 "failed to set congestion manager context for "
2662 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2666 /* Enable IQ interrupts */
2667 atomic_store_rel_int(&iq->state, IQS_IDLE);
2668 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2669 V_INGRESSQID(iq->cntxt_id));
2675 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2678 struct adapter *sc = iq->adapter;
2682 return (0); /* nothing to do */
2684 dev = vi ? vi->dev : sc->dev;
2686 if (iq->flags & IQ_ALLOCATED) {
2687 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2688 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2689 fl ? fl->cntxt_id : 0xffff, 0xffff);
2692 "failed to free queue %p: %d\n", iq, rc);
2695 iq->flags &= ~IQ_ALLOCATED;
2698 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2700 bzero(iq, sizeof(*iq));
2703 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2707 free_fl_sdesc(sc, fl);
2709 if (mtx_initialized(&fl->fl_lock))
2710 mtx_destroy(&fl->fl_lock);
2712 bzero(fl, sizeof(*fl));
2719 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2722 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2724 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2726 children = SYSCTL_CHILDREN(oid);
2728 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2729 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2730 "SGE context id of the freelist");
2731 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2732 fl_pad ? 1 : 0, "padding enabled");
2733 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2734 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2735 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2736 0, "consumer index");
2737 if (fl->flags & FL_BUF_PACKING) {
2738 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2739 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2741 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2742 0, "producer index");
2743 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2744 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2745 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2746 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2747 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2748 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2749 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2750 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2751 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2752 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2756 alloc_fwq(struct adapter *sc)
2759 struct sge_iq *fwq = &sc->sge.fwq;
2760 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2761 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2763 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2764 fwq->flags |= IQ_INTR; /* always */
2765 intr_idx = sc->intr_count > 1 ? 1 : 0;
2766 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2768 device_printf(sc->dev,
2769 "failed to create firmware event queue: %d\n", rc);
2773 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2774 NULL, "firmware event queue");
2775 children = SYSCTL_CHILDREN(oid);
2777 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2778 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2779 "absolute id of the queue");
2780 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2781 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2782 "SGE context id of the queue");
2783 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2784 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2791 free_fwq(struct adapter *sc)
2793 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2797 alloc_mgmtq(struct adapter *sc)
2800 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2802 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2803 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2805 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2806 NULL, "management queue");
2808 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2809 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2810 sc->sge.fwq.cntxt_id, name);
2811 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2813 device_printf(sc->dev,
2814 "failed to create management queue: %d\n", rc);
2822 free_mgmtq(struct adapter *sc)
2825 return free_wrq(sc, &sc->sge.mgmtq);
2829 tnl_cong(struct port_info *pi, int drop)
2837 return (pi->rx_chan_map);
2841 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
2842 struct sysctl_oid *oid)
2845 struct sysctl_oid_list *children;
2848 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
2849 tnl_cong(vi->pi, cong_drop));
2854 * The freelist is just barely above the starvation threshold right now,
2855 * fill it up a bit more.
2858 refill_fl(vi->pi->adapter, &rxq->fl, 128);
2859 FL_UNLOCK(&rxq->fl);
2861 #if defined(INET) || defined(INET6)
2862 rc = tcp_lro_init(&rxq->lro);
2865 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
2867 if (vi->ifp->if_capenable & IFCAP_LRO)
2868 rxq->iq.flags |= IQ_LRO_ENABLED;
2872 children = SYSCTL_CHILDREN(oid);
2874 snprintf(name, sizeof(name), "%d", idx);
2875 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2877 children = SYSCTL_CHILDREN(oid);
2879 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2880 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2881 "absolute id of the queue");
2882 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2883 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2884 "SGE context id of the queue");
2885 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2886 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2888 #if defined(INET) || defined(INET6)
2889 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2890 &rxq->lro.lro_queued, 0, NULL);
2891 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2892 &rxq->lro.lro_flushed, 0, NULL);
2894 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2895 &rxq->rxcsum, "# of times hardware assisted with checksum");
2896 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
2897 CTLFLAG_RD, &rxq->vlan_extraction,
2898 "# of times hardware extracted 802.1Q tag");
2900 add_fl_sysctls(&vi->ctx, oid, &rxq->fl);
2906 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
2910 #if defined(INET) || defined(INET6)
2912 tcp_lro_free(&rxq->lro);
2913 rxq->lro.ifp = NULL;
2917 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
2919 bzero(rxq, sizeof(*rxq));
2926 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
2927 int intr_idx, int idx, struct sysctl_oid *oid)
2930 struct sysctl_oid_list *children;
2933 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2934 vi->pi->rx_chan_map);
2938 children = SYSCTL_CHILDREN(oid);
2940 snprintf(name, sizeof(name), "%d", idx);
2941 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2943 children = SYSCTL_CHILDREN(oid);
2945 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2946 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2947 "I", "absolute id of the queue");
2948 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2949 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2950 "I", "SGE context id of the queue");
2951 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2952 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2955 add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl);
2961 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
2965 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
2967 bzero(ofld_rxq, sizeof(*ofld_rxq));
2975 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
2976 int idx, struct sysctl_oid *oid)
2979 struct sysctl_oid_list *children;
2980 struct sysctl_ctx_list *ctx;
2983 struct adapter *sc = vi->pi->adapter;
2984 struct netmap_adapter *na = NA(vi->ifp);
2988 len = vi->qsize_rxq * IQ_ESIZE;
2989 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
2990 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
2994 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
2995 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
2996 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3002 nm_rxq->iq_cidx = 0;
3003 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3004 nm_rxq->iq_gen = F_RSPD_GEN;
3005 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3006 nm_rxq->fl_sidx = na->num_rx_desc;
3007 nm_rxq->intr_idx = intr_idx;
3010 children = SYSCTL_CHILDREN(oid);
3012 snprintf(name, sizeof(name), "%d", idx);
3013 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3015 children = SYSCTL_CHILDREN(oid);
3017 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3018 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3019 "I", "absolute id of the queue");
3020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3021 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3022 "I", "SGE context id of the queue");
3023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3024 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3027 children = SYSCTL_CHILDREN(oid);
3028 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3030 children = SYSCTL_CHILDREN(oid);
3032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3033 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3034 "I", "SGE context id of the freelist");
3035 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3036 &nm_rxq->fl_cidx, 0, "consumer index");
3037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3038 &nm_rxq->fl_pidx, 0, "producer index");
3045 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3047 struct adapter *sc = vi->pi->adapter;
3049 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3051 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3058 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3059 struct sysctl_oid *oid)
3063 struct port_info *pi = vi->pi;
3064 struct adapter *sc = pi->adapter;
3065 struct netmap_adapter *na = NA(vi->ifp);
3067 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3069 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3070 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3071 &nm_txq->ba, (void **)&nm_txq->desc);
3075 nm_txq->pidx = nm_txq->cidx = 0;
3076 nm_txq->sidx = na->num_tx_desc;
3078 nm_txq->iqidx = iqidx;
3079 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3080 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3081 V_TXPKT_VF(vi->viid));
3083 snprintf(name, sizeof(name), "%d", idx);
3084 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3085 NULL, "netmap tx queue");
3086 children = SYSCTL_CHILDREN(oid);
3088 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3089 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3090 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3091 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3093 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3094 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3101 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3103 struct adapter *sc = vi->pi->adapter;
3105 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3113 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3116 struct fw_eq_ctrl_cmd c;
3117 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3119 bzero(&c, sizeof(c));
3121 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3122 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3123 V_FW_EQ_CTRL_CMD_VFN(0));
3124 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3125 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3126 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3127 c.physeqid_pkd = htobe32(0);
3128 c.fetchszm_to_iqid =
3129 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3130 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3131 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3133 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3134 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3135 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3136 c.eqaddr = htobe64(eq->ba);
3138 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3140 device_printf(sc->dev,
3141 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3144 eq->flags |= EQ_ALLOCATED;
3146 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3147 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3148 if (cntxt_id >= sc->sge.neq)
3149 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3150 cntxt_id, sc->sge.neq - 1);
3151 sc->sge.eqmap[cntxt_id] = eq;
3157 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3160 struct fw_eq_eth_cmd c;
3161 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3163 bzero(&c, sizeof(c));
3165 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3166 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3167 V_FW_EQ_ETH_CMD_VFN(0));
3168 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3169 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3170 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3171 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3172 c.fetchszm_to_iqid =
3173 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3174 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3175 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3176 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3177 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3178 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3179 c.eqaddr = htobe64(eq->ba);
3181 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3183 device_printf(vi->dev,
3184 "failed to create Ethernet egress queue: %d\n", rc);
3187 eq->flags |= EQ_ALLOCATED;
3189 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3190 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3191 if (cntxt_id >= sc->sge.neq)
3192 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3193 cntxt_id, sc->sge.neq - 1);
3194 sc->sge.eqmap[cntxt_id] = eq;
3201 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3204 struct fw_eq_ofld_cmd c;
3205 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3207 bzero(&c, sizeof(c));
3209 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3210 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3211 V_FW_EQ_OFLD_CMD_VFN(0));
3212 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3213 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3214 c.fetchszm_to_iqid =
3215 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3216 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3217 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3219 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3220 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3221 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3222 c.eqaddr = htobe64(eq->ba);
3224 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3226 device_printf(vi->dev,
3227 "failed to create egress queue for TCP offload: %d\n", rc);
3230 eq->flags |= EQ_ALLOCATED;
3232 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3233 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3234 if (cntxt_id >= sc->sge.neq)
3235 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3236 cntxt_id, sc->sge.neq - 1);
3237 sc->sge.eqmap[cntxt_id] = eq;
3244 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3249 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3251 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3252 len = qsize * EQ_ESIZE;
3253 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3254 &eq->ba, (void **)&eq->desc);
3258 eq->pidx = eq->cidx = 0;
3259 eq->equeqidx = eq->dbidx = 0;
3260 eq->doorbells = sc->doorbells;
3262 switch (eq->flags & EQ_TYPEMASK) {
3264 rc = ctrl_eq_alloc(sc, eq);
3268 rc = eth_eq_alloc(sc, vi, eq);
3273 rc = ofld_eq_alloc(sc, vi, eq);
3278 panic("%s: invalid eq type %d.", __func__,
3279 eq->flags & EQ_TYPEMASK);
3282 device_printf(sc->dev,
3283 "failed to allocate egress queue(%d): %d\n",
3284 eq->flags & EQ_TYPEMASK, rc);
3287 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3288 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3289 isset(&eq->doorbells, DOORBELL_WCWR)) {
3290 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3291 uint32_t mask = (1 << s_qpp) - 1;
3292 volatile uint8_t *udb;
3294 udb = sc->udbs_base + UDBS_DB_OFFSET;
3295 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3296 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3297 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3298 clrbit(&eq->doorbells, DOORBELL_WCWR);
3300 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3303 eq->udb = (volatile void *)udb;
3310 free_eq(struct adapter *sc, struct sge_eq *eq)
3314 if (eq->flags & EQ_ALLOCATED) {
3315 switch (eq->flags & EQ_TYPEMASK) {
3317 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3322 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3328 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3334 panic("%s: invalid eq type %d.", __func__,
3335 eq->flags & EQ_TYPEMASK);
3338 device_printf(sc->dev,
3339 "failed to free egress queue (%d): %d\n",
3340 eq->flags & EQ_TYPEMASK, rc);
3343 eq->flags &= ~EQ_ALLOCATED;
3346 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3348 if (mtx_initialized(&eq->eq_lock))
3349 mtx_destroy(&eq->eq_lock);
3351 bzero(eq, sizeof(*eq));
3356 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3357 struct sysctl_oid *oid)
3360 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3361 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3363 rc = alloc_eq(sc, vi, &wrq->eq);
3368 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3369 TAILQ_INIT(&wrq->incomplete_wrs);
3370 STAILQ_INIT(&wrq->wr_list);
3371 wrq->nwr_pending = 0;
3372 wrq->ndesc_needed = 0;
3374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3375 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3376 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3377 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3379 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3380 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3382 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3383 &wrq->tx_wrs_direct, "# of work requests (direct)");
3384 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3385 &wrq->tx_wrs_copied, "# of work requests (copied)");
3391 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3395 rc = free_eq(sc, &wrq->eq);
3399 bzero(wrq, sizeof(*wrq));
3404 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3405 struct sysctl_oid *oid)
3408 struct port_info *pi = vi->pi;
3409 struct adapter *sc = pi->adapter;
3410 struct sge_eq *eq = &txq->eq;
3412 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3414 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3417 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3421 rc = alloc_eq(sc, vi, eq);
3423 mp_ring_free(txq->r);
3428 /* Can't fail after this point. */
3430 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3432 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3433 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3434 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3435 V_TXPKT_VF(vi->viid));
3436 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3439 snprintf(name, sizeof(name), "%d", idx);
3440 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3442 children = SYSCTL_CHILDREN(oid);
3444 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3445 &eq->cntxt_id, 0, "SGE context id of the queue");
3446 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3447 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3449 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3450 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3453 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3454 &txq->txcsum, "# of times hardware assisted with checksum");
3455 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3456 CTLFLAG_RD, &txq->vlan_insertion,
3457 "# of times hardware inserted 802.1Q tag");
3458 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3459 &txq->tso_wrs, "# of TSO work requests");
3460 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3461 &txq->imm_wrs, "# of work requests with immediate data");
3462 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3463 &txq->sgl_wrs, "# of work requests with direct SGL");
3464 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3465 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3466 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3467 CTLFLAG_RD, &txq->txpkts0_wrs,
3468 "# of txpkts (type 0) work requests");
3469 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3470 CTLFLAG_RD, &txq->txpkts1_wrs,
3471 "# of txpkts (type 1) work requests");
3472 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3473 CTLFLAG_RD, &txq->txpkts0_pkts,
3474 "# of frames tx'd using type0 txpkts work requests");
3475 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3476 CTLFLAG_RD, &txq->txpkts1_pkts,
3477 "# of frames tx'd using type1 txpkts work requests");
3479 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3480 CTLFLAG_RD, &txq->r->enqueues,
3481 "# of enqueues to the mp_ring for this queue");
3482 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3483 CTLFLAG_RD, &txq->r->drops,
3484 "# of drops in the mp_ring for this queue");
3485 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3486 CTLFLAG_RD, &txq->r->starts,
3487 "# of normal consumer starts in the mp_ring for this queue");
3488 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3489 CTLFLAG_RD, &txq->r->stalls,
3490 "# of consumer stalls in the mp_ring for this queue");
3491 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3492 CTLFLAG_RD, &txq->r->restarts,
3493 "# of consumer restarts in the mp_ring for this queue");
3494 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3495 CTLFLAG_RD, &txq->r->abdications,
3496 "# of consumer abdications in the mp_ring for this queue");
3502 free_txq(struct vi_info *vi, struct sge_txq *txq)
3505 struct adapter *sc = vi->pi->adapter;
3506 struct sge_eq *eq = &txq->eq;
3508 rc = free_eq(sc, eq);
3512 sglist_free(txq->gl);
3513 free(txq->sdesc, M_CXGBE);
3514 mp_ring_free(txq->r);
3516 bzero(txq, sizeof(*txq));
3521 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3523 bus_addr_t *ba = arg;
3526 ("%s meant for single segment mappings only.", __func__));
3528 *ba = error ? 0 : segs->ds_addr;
3532 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3536 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3540 v = fl->dbval | V_PIDX(n);
3542 *fl->udb = htole32(v);
3544 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3545 IDXINCR(fl->dbidx, n, fl->sidx);
3549 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3550 * recycled do not count towards this allocation budget.
3552 * Returns non-zero to indicate that this freelist should be added to the list
3553 * of starving freelists.
3556 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3559 struct fl_sdesc *sd;
3562 struct cluster_layout *cll;
3563 struct sw_zone_info *swz;
3564 struct cluster_metadata *clm;
3566 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3568 FL_LOCK_ASSERT_OWNED(fl);
3571 * We always stop at the begining of the hardware descriptor that's just
3572 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3573 * which would mean an empty freelist to the chip.
3575 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3576 if (fl->pidx == max_pidx * 8)
3579 d = &fl->desc[fl->pidx];
3580 sd = &fl->sdesc[fl->pidx];
3581 cll = &fl->cll_def; /* default layout */
3582 swz = &sc->sge.sw_zone_info[cll->zidx];
3586 if (sd->cl != NULL) {
3588 if (sd->nmbuf == 0) {
3590 * Fast recycle without involving any atomics on
3591 * the cluster's metadata (if the cluster has
3592 * metadata). This happens when all frames
3593 * received in the cluster were small enough to
3594 * fit within a single mbuf each.
3596 fl->cl_fast_recycled++;
3598 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3600 MPASS(clm->refcount == 1);
3606 * Cluster is guaranteed to have metadata. Clusters
3607 * without metadata always take the fast recycle path
3608 * when they're recycled.
3610 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3613 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3615 counter_u64_add(extfree_rels, 1);
3618 sd->cl = NULL; /* gave up my reference */
3620 MPASS(sd->cl == NULL);
3622 cl = uma_zalloc(swz->zone, M_NOWAIT);
3623 if (__predict_false(cl == NULL)) {
3624 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3625 fl->cll_def.zidx == fl->cll_alt.zidx)
3628 /* fall back to the safe zone */
3630 swz = &sc->sge.sw_zone_info[cll->zidx];
3636 pa = pmap_kextract((vm_offset_t)cl);
3640 *d = htobe64(pa | cll->hwidx);
3641 clm = cl_metadata(sc, fl, cll, cl);
3653 if (__predict_false(++fl->pidx % 8 == 0)) {
3654 uint16_t pidx = fl->pidx / 8;
3656 if (__predict_false(pidx == fl->sidx)) {
3662 if (pidx == max_pidx)
3665 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3670 if (fl->pidx / 8 != fl->dbidx)
3673 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3677 * Attempt to refill all starving freelists.
3680 refill_sfl(void *arg)
3682 struct adapter *sc = arg;
3683 struct sge_fl *fl, *fl_temp;
3685 mtx_assert(&sc->sfl_lock, MA_OWNED);
3686 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3688 refill_fl(sc, fl, 64);
3689 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3690 TAILQ_REMOVE(&sc->sfl, fl, link);
3691 fl->flags &= ~FL_STARVING;
3696 if (!TAILQ_EMPTY(&sc->sfl))
3697 callout_schedule(&sc->sfl_callout, hz / 5);
3701 alloc_fl_sdesc(struct sge_fl *fl)
3704 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3711 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3713 struct fl_sdesc *sd;
3714 struct cluster_metadata *clm;
3715 struct cluster_layout *cll;
3719 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3724 clm = cl_metadata(sc, fl, cll, sd->cl);
3726 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3727 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3728 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3729 counter_u64_add(extfree_rels, 1);
3734 free(fl->sdesc, M_CXGBE);
3739 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3746 rc = sglist_append_mbuf(gl, m);
3747 if (__predict_false(rc != 0)) {
3748 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3749 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3752 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3753 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3754 mbuf_nsegs(m), gl->sg_nseg));
3755 KASSERT(gl->sg_nseg > 0 &&
3756 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3757 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3758 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3762 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3765 txpkt_len16(u_int nsegs, u_int tso)
3771 nsegs--; /* first segment is part of ulptx_sgl */
3772 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3773 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3775 n += sizeof(struct cpl_tx_pkt_lso_core);
3777 return (howmany(n, 16));
3781 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
3785 txpkts0_len16(u_int nsegs)
3791 nsegs--; /* first segment is part of ulptx_sgl */
3792 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
3793 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
3794 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3796 return (howmany(n, 16));
3800 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
3808 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
3810 return (howmany(n, 16));
3814 imm_payload(u_int ndesc)
3818 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
3819 sizeof(struct cpl_tx_pkt_core);
3825 * Write a txpkt WR for this packet to the hardware descriptors, update the
3826 * software descriptor, and advance the pidx. It is guaranteed that enough
3827 * descriptors are available.
3829 * The return value is the # of hardware descriptors used.
3832 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
3833 struct mbuf *m0, u_int available)
3835 struct sge_eq *eq = &txq->eq;
3836 struct tx_sdesc *txsd;
3837 struct cpl_tx_pkt_core *cpl;
3838 uint32_t ctrl; /* used in many unrelated places */
3840 int len16, ndesc, pktlen, nsegs;
3843 TXQ_LOCK_ASSERT_OWNED(txq);
3845 MPASS(available > 0 && available < eq->sidx);
3847 len16 = mbuf_len16(m0);
3848 nsegs = mbuf_nsegs(m0);
3849 pktlen = m0->m_pkthdr.len;
3850 ctrl = sizeof(struct cpl_tx_pkt_core);
3852 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3853 else if (pktlen <= imm_payload(2) && available >= 2) {
3854 /* Immediate data. Recalculate len16 and set nsegs to 0. */
3856 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
3857 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
3860 ndesc = howmany(len16, EQ_ESIZE / 16);
3861 MPASS(ndesc <= available);
3863 /* Firmware work request header */
3864 MPASS(wr == (void *)&eq->desc[eq->pidx]);
3865 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3866 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3868 ctrl = V_FW_WR_LEN16(len16);
3869 wr->equiq_to_len16 = htobe32(ctrl);
3872 if (needs_tso(m0)) {
3873 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3875 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
3876 m0->m_pkthdr.l4hlen > 0,
3877 ("%s: mbuf %p needs TSO but missing header lengths",
3880 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3881 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
3882 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
3883 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
3884 ctrl |= V_LSO_ETHHDR_LEN(1);
3885 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
3888 lso->lso_ctrl = htobe32(ctrl);
3889 lso->ipid_ofst = htobe16(0);
3890 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
3891 lso->seqno_offset = htobe32(0);
3892 lso->len = htobe32(pktlen);
3894 cpl = (void *)(lso + 1);
3898 cpl = (void *)(wr + 1);
3900 /* Checksum offload */
3902 if (needs_l3_csum(m0) == 0)
3903 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3904 if (needs_l4_csum(m0) == 0)
3905 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3906 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3907 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3908 txq->txcsum++; /* some hardware assistance provided */
3910 /* VLAN tag insertion */
3911 if (needs_vlan_insertion(m0)) {
3912 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
3913 txq->vlan_insertion++;
3917 cpl->ctrl0 = txq->cpl_ctrl0;
3919 cpl->len = htobe16(pktlen);
3920 cpl->ctrl1 = htobe64(ctrl1);
3923 dst = (void *)(cpl + 1);
3926 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
3931 for (m = m0; m != NULL; m = m->m_next) {
3932 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3938 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3945 txsd = &txq->sdesc[eq->pidx];
3947 txsd->desc_used = ndesc;
3953 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
3955 u_int needed, nsegs1, nsegs2, l1, l2;
3957 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
3960 nsegs1 = mbuf_nsegs(m);
3961 nsegs2 = mbuf_nsegs(n);
3962 if (nsegs1 + nsegs2 == 2) {
3964 l1 = l2 = txpkts1_len16();
3967 l1 = txpkts0_len16(nsegs1);
3968 l2 = txpkts0_len16(nsegs2);
3970 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
3971 needed = howmany(txp->len16, EQ_ESIZE / 16);
3972 if (needed > SGE_MAX_WR_NDESC || needed > available)
3975 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
3976 if (txp->plen > 65535)
3980 set_mbuf_len16(m, l1);
3981 set_mbuf_len16(n, l2);
3987 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
3989 u_int plen, len16, needed, nsegs;
3991 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
3993 nsegs = mbuf_nsegs(m);
3994 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
3997 plen = txp->plen + m->m_pkthdr.len;
4001 if (txp->wr_type == 0)
4002 len16 = txpkts0_len16(nsegs);
4004 len16 = txpkts1_len16();
4005 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4006 if (needed > SGE_MAX_WR_NDESC || needed > available)
4011 txp->len16 += len16;
4012 set_mbuf_len16(m, len16);
4018 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4019 * the software descriptor, and advance the pidx. It is guaranteed that enough
4020 * descriptors are available.
4022 * The return value is the # of hardware descriptors used.
4025 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4026 struct mbuf *m0, const struct txpkts *txp, u_int available)
4028 struct sge_eq *eq = &txq->eq;
4029 struct tx_sdesc *txsd;
4030 struct cpl_tx_pkt_core *cpl;
4033 int ndesc, checkwrap;
4037 TXQ_LOCK_ASSERT_OWNED(txq);
4038 MPASS(txp->npkt > 0);
4039 MPASS(txp->plen < 65536);
4041 MPASS(m0->m_nextpkt != NULL);
4042 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4043 MPASS(available > 0 && available < eq->sidx);
4045 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4046 MPASS(ndesc <= available);
4048 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4049 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4050 ctrl = V_FW_WR_LEN16(txp->len16);
4051 wr->equiq_to_len16 = htobe32(ctrl);
4052 wr->plen = htobe16(txp->plen);
4053 wr->npkt = txp->npkt;
4055 wr->type = txp->wr_type;
4059 * At this point we are 16B into a hardware descriptor. If checkwrap is
4060 * set then we know the WR is going to wrap around somewhere. We'll
4061 * check for that at appropriate points.
4063 checkwrap = eq->sidx - ndesc < eq->pidx;
4064 for (m = m0; m != NULL; m = m->m_nextpkt) {
4065 if (txp->wr_type == 0) {
4066 struct ulp_txpkt *ulpmc;
4067 struct ulptx_idata *ulpsc;
4069 /* ULP master command */
4071 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4072 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4073 ulpmc->len = htobe32(mbuf_len16(m));
4075 /* ULP subcommand */
4076 ulpsc = (void *)(ulpmc + 1);
4077 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4079 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4081 cpl = (void *)(ulpsc + 1);
4083 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4084 cpl = (void *)&eq->desc[0];
4085 txq->txpkts0_pkts += txp->npkt;
4089 txq->txpkts1_pkts += txp->npkt;
4093 /* Checksum offload */
4095 if (needs_l3_csum(m) == 0)
4096 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4097 if (needs_l4_csum(m) == 0)
4098 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4099 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4100 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4101 txq->txcsum++; /* some hardware assistance provided */
4103 /* VLAN tag insertion */
4104 if (needs_vlan_insertion(m)) {
4105 ctrl1 |= F_TXPKT_VLAN_VLD |
4106 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4107 txq->vlan_insertion++;
4111 cpl->ctrl0 = txq->cpl_ctrl0;
4113 cpl->len = htobe16(m->m_pkthdr.len);
4114 cpl->ctrl1 = htobe64(ctrl1);
4118 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4119 flitp = (void *)&eq->desc[0];
4121 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4125 txsd = &txq->sdesc[eq->pidx];
4127 txsd->desc_used = ndesc;
4133 * If the SGL ends on an address that is not 16 byte aligned, this function will
4134 * add a 0 filled flit at the end.
4137 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4139 struct sge_eq *eq = &txq->eq;
4140 struct sglist *gl = txq->gl;
4141 struct sglist_seg *seg;
4142 __be64 *flitp, *wrap;
4143 struct ulptx_sgl *usgl;
4144 int i, nflits, nsegs;
4146 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4147 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4148 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4149 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4152 nsegs = gl->sg_nseg;
4155 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4156 flitp = (__be64 *)(*to);
4157 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4158 seg = &gl->sg_segs[0];
4159 usgl = (void *)flitp;
4162 * We start at a 16 byte boundary somewhere inside the tx descriptor
4163 * ring, so we're at least 16 bytes away from the status page. There is
4164 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4167 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4168 V_ULPTX_NSGE(nsegs));
4169 usgl->len0 = htobe32(seg->ss_len);
4170 usgl->addr0 = htobe64(seg->ss_paddr);
4173 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4175 /* Won't wrap around at all */
4177 for (i = 0; i < nsegs - 1; i++, seg++) {
4178 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4179 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4182 usgl->sge[i / 2].len[1] = htobe32(0);
4186 /* Will wrap somewhere in the rest of the SGL */
4188 /* 2 flits already written, write the rest flit by flit */
4189 flitp = (void *)(usgl + 1);
4190 for (i = 0; i < nflits - 2; i++) {
4192 flitp = (void *)eq->desc;
4193 *flitp++ = get_flit(seg, nsegs - 1, i);
4198 MPASS(((uintptr_t)flitp) & 0xf);
4202 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4203 if (__predict_false(flitp == wrap))
4204 *to = (void *)eq->desc;
4206 *to = (void *)flitp;
4210 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4213 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4214 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4216 if (__predict_true((uintptr_t)(*to) + len <=
4217 (uintptr_t)&eq->desc[eq->sidx])) {
4218 bcopy(from, *to, len);
4221 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4223 bcopy(from, *to, portion);
4225 portion = len - portion; /* remaining */
4226 bcopy(from, (void *)eq->desc, portion);
4227 (*to) = (caddr_t)eq->desc + portion;
4232 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4240 clrbit(&db, DOORBELL_WCWR);
4243 switch (ffs(db) - 1) {
4245 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4248 case DOORBELL_WCWR: {
4249 volatile uint64_t *dst, *src;
4253 * Queues whose 128B doorbell segment fits in the page do not
4254 * use relative qid (udb_qid is always 0). Only queues with
4255 * doorbell segments can do WCWR.
4257 KASSERT(eq->udb_qid == 0 && n == 1,
4258 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4259 __func__, eq->doorbells, n, eq->dbidx, eq));
4261 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4264 src = (void *)&eq->desc[i];
4265 while (src != (void *)&eq->desc[i + 1])
4271 case DOORBELL_UDBWC:
4272 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4277 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4278 V_QID(eq->cntxt_id) | V_PIDX(n));
4282 IDXINCR(eq->dbidx, n, eq->sidx);
4286 reclaimable_tx_desc(struct sge_eq *eq)
4290 hw_cidx = read_hw_cidx(eq);
4291 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4295 total_available_tx_desc(struct sge_eq *eq)
4297 uint16_t hw_cidx, pidx;
4299 hw_cidx = read_hw_cidx(eq);
4302 if (pidx == hw_cidx)
4303 return (eq->sidx - 1);
4305 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4308 static inline uint16_t
4309 read_hw_cidx(struct sge_eq *eq)
4311 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4312 uint16_t cidx = spg->cidx; /* stable snapshot */
4314 return (be16toh(cidx));
4318 * Reclaim 'n' descriptors approximately.
4321 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4323 struct tx_sdesc *txsd;
4324 struct sge_eq *eq = &txq->eq;
4325 u_int can_reclaim, reclaimed;
4327 TXQ_LOCK_ASSERT_OWNED(txq);
4331 can_reclaim = reclaimable_tx_desc(eq);
4332 while (can_reclaim && reclaimed < n) {
4334 struct mbuf *m, *nextpkt;
4336 txsd = &txq->sdesc[eq->cidx];
4337 ndesc = txsd->desc_used;
4339 /* Firmware doesn't return "partial" credits. */
4340 KASSERT(can_reclaim >= ndesc,
4341 ("%s: unexpected number of credits: %d, %d",
4342 __func__, can_reclaim, ndesc));
4344 for (m = txsd->m; m != NULL; m = nextpkt) {
4345 nextpkt = m->m_nextpkt;
4346 m->m_nextpkt = NULL;
4350 can_reclaim -= ndesc;
4351 IDXINCR(eq->cidx, ndesc, eq->sidx);
4358 tx_reclaim(void *arg, int n)
4360 struct sge_txq *txq = arg;
4361 struct sge_eq *eq = &txq->eq;
4364 if (TXQ_TRYLOCK(txq) == 0)
4366 n = reclaim_tx_descs(txq, 32);
4367 if (eq->cidx == eq->pidx)
4368 eq->equeqidx = eq->pidx;
4374 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4376 int i = (idx / 3) * 2;
4382 rc = htobe32(segs[i].ss_len);
4384 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4389 return (htobe64(segs[i].ss_paddr));
4391 return (htobe64(segs[i + 1].ss_paddr));
4398 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4400 int8_t zidx, hwidx, idx;
4401 uint16_t region1, region3;
4402 int spare, spare_needed, n;
4403 struct sw_zone_info *swz;
4404 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4407 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4408 * large enough for the max payload and cluster metadata. Otherwise
4409 * settle for the largest bufsize that leaves enough room in the cluster
4412 * Without buffer packing: Look for the smallest zone which has a
4413 * bufsize large enough for the max payload. Settle for the largest
4414 * bufsize available if there's nothing big enough for max payload.
4416 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4417 swz = &sc->sge.sw_zone_info[0];
4419 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4420 if (swz->size > largest_rx_cluster) {
4421 if (__predict_true(hwidx != -1))
4425 * This is a misconfiguration. largest_rx_cluster is
4426 * preventing us from finding a refill source. See
4427 * dev.t5nex.<n>.buffer_sizes to figure out why.
4429 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4430 " refill source for fl %p (dma %u). Ignored.\n",
4431 largest_rx_cluster, fl, maxp);
4433 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4434 hwb = &hwb_list[idx];
4435 spare = swz->size - hwb->size;
4436 if (spare < spare_needed)
4439 hwidx = idx; /* best option so far */
4440 if (hwb->size >= maxp) {
4442 if ((fl->flags & FL_BUF_PACKING) == 0)
4443 goto done; /* stop looking (not packing) */
4445 if (swz->size >= safest_rx_cluster)
4446 goto done; /* stop looking (packing) */
4448 break; /* keep looking, next zone */
4452 /* A usable hwidx has been located. */
4454 hwb = &hwb_list[hwidx];
4456 swz = &sc->sge.sw_zone_info[zidx];
4458 region3 = swz->size - hwb->size;
4461 * Stay within this zone and see if there is a better match when mbuf
4462 * inlining is allowed. Remember that the hwidx's are sorted in
4463 * decreasing order of size (so in increasing order of spare area).
4465 for (idx = hwidx; idx != -1; idx = hwb->next) {
4466 hwb = &hwb_list[idx];
4467 spare = swz->size - hwb->size;
4469 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4473 * Do not inline mbufs if doing so would violate the pad/pack
4474 * boundary alignment requirement.
4476 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4478 if (fl->flags & FL_BUF_PACKING &&
4479 (MSIZE % sc->params.sge.pack_boundary) != 0)
4482 if (spare < CL_METADATA_SIZE + MSIZE)
4484 n = (spare - CL_METADATA_SIZE) / MSIZE;
4485 if (n > howmany(hwb->size, maxp))
4489 if (fl->flags & FL_BUF_PACKING) {
4490 region1 = n * MSIZE;
4491 region3 = spare - region1;
4494 region3 = spare - region1;
4499 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4500 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4501 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4502 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4503 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4504 sc->sge.sw_zone_info[zidx].size,
4505 ("%s: bad buffer layout for fl %p, maxp %d. "
4506 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4507 sc->sge.sw_zone_info[zidx].size, region1,
4508 sc->sge.hw_buf_info[hwidx].size, region3));
4509 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4510 KASSERT(region3 >= CL_METADATA_SIZE,
4511 ("%s: no room for metadata. fl %p, maxp %d; "
4512 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4513 sc->sge.sw_zone_info[zidx].size, region1,
4514 sc->sge.hw_buf_info[hwidx].size, region3));
4515 KASSERT(region1 % MSIZE == 0,
4516 ("%s: bad mbuf region for fl %p, maxp %d. "
4517 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4518 sc->sge.sw_zone_info[zidx].size, region1,
4519 sc->sge.hw_buf_info[hwidx].size, region3));
4522 fl->cll_def.zidx = zidx;
4523 fl->cll_def.hwidx = hwidx;
4524 fl->cll_def.region1 = region1;
4525 fl->cll_def.region3 = region3;
4529 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4531 struct sge *s = &sc->sge;
4532 struct hw_buf_info *hwb;
4533 struct sw_zone_info *swz;
4537 if (fl->flags & FL_BUF_PACKING)
4538 hwidx = s->safe_hwidx2; /* with room for metadata */
4539 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4540 hwidx = s->safe_hwidx2;
4541 hwb = &s->hw_buf_info[hwidx];
4542 swz = &s->sw_zone_info[hwb->zidx];
4543 spare = swz->size - hwb->size;
4545 /* no good if there isn't room for an mbuf as well */
4546 if (spare < CL_METADATA_SIZE + MSIZE)
4547 hwidx = s->safe_hwidx1;
4549 hwidx = s->safe_hwidx1;
4552 /* No fallback source */
4553 fl->cll_alt.hwidx = -1;
4554 fl->cll_alt.zidx = -1;
4559 hwb = &s->hw_buf_info[hwidx];
4560 swz = &s->sw_zone_info[hwb->zidx];
4561 spare = swz->size - hwb->size;
4562 fl->cll_alt.hwidx = hwidx;
4563 fl->cll_alt.zidx = hwb->zidx;
4564 if (allow_mbufs_in_cluster &&
4565 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
4566 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4568 fl->cll_alt.region1 = 0;
4569 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4573 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4575 mtx_lock(&sc->sfl_lock);
4577 if ((fl->flags & FL_DOOMED) == 0) {
4578 fl->flags |= FL_STARVING;
4579 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4580 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4583 mtx_unlock(&sc->sfl_lock);
4587 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
4589 struct sge_wrq *wrq = (void *)eq;
4591 atomic_readandclear_int(&eq->equiq);
4592 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
4596 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
4598 struct sge_txq *txq = (void *)eq;
4600 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
4602 atomic_readandclear_int(&eq->equiq);
4603 mp_ring_check_drainage(txq->r, 0);
4604 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
4608 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4611 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4612 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4613 struct adapter *sc = iq->adapter;
4614 struct sge *s = &sc->sge;
4616 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
4617 &handle_wrq_egr_update, &handle_eth_egr_update,
4618 &handle_wrq_egr_update};
4620 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4623 eq = s->eqmap[qid - s->eq_start];
4624 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
4629 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4630 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4631 offsetof(struct cpl_fw6_msg, data));
4634 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4636 struct adapter *sc = iq->adapter;
4637 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4639 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4642 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4643 const struct rss_header *rss2;
4645 rss2 = (const struct rss_header *)&cpl->data[0];
4646 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4649 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4653 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4655 uint16_t *id = arg1;
4658 return sysctl_handle_int(oidp, &i, 0, req);
4662 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4664 struct sge *s = arg1;
4665 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4666 struct sw_zone_info *swz = &s->sw_zone_info[0];
4671 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4672 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4673 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4678 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4682 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);