2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_ratelimit.h"
37 #include <sys/types.h>
38 #include <sys/eventhandler.h>
40 #include <sys/socket.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
47 #include <sys/sglist.h>
48 #include <sys/sysctl.h>
50 #include <sys/counter.h>
52 #include <net/ethernet.h>
54 #include <net/if_vlan_var.h>
55 #include <netinet/in.h>
56 #include <netinet/ip.h>
57 #include <netinet/ip6.h>
58 #include <netinet/tcp.h>
59 #include <netinet/udp.h>
60 #include <machine/in_cksum.h>
61 #include <machine/md_var.h>
65 #include <machine/bus.h>
66 #include <sys/selinfo.h>
67 #include <net/if_var.h>
68 #include <net/netmap.h>
69 #include <dev/netmap/netmap_kern.h>
72 #include "common/common.h"
73 #include "common/t4_regs.h"
74 #include "common/t4_regs_values.h"
75 #include "common/t4_msg.h"
77 #include "t4_mp_ring.h"
79 #ifdef T4_PKT_TIMESTAMP
80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
82 #define RX_COPY_THRESHOLD MINCLSIZE
85 /* Internal mbuf flags stored in PH_loc.eight[1]. */
86 #define MC_RAW_WR 0x02
89 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
90 * 0-7 are valid values.
92 static int fl_pktshift = 0;
93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
94 "payload DMA offset in rx buffer (bytes)");
97 * Pad ethernet payload up to this boundary.
98 * -1: driver should figure out a good value.
100 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
103 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
104 "payload pad boundary (bytes)");
107 * Status page length.
108 * -1: driver should figure out a good value.
109 * 64 or 128 are the only other valid values.
111 static int spg_len = -1;
112 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
113 "status page size (bytes)");
117 * -1: no congestion feedback (not recommended).
118 * 0: backpressure the channel instead of dropping packets right away.
119 * 1: no backpressure, drop packets for the congested queue immediately.
121 static int cong_drop = 0;
122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
123 "Congestion control for RX queues (0 = backpressure, 1 = drop");
126 * Deliver multiple frames in the same free list buffer if they fit.
127 * -1: let the driver decide whether to enable buffer packing or not.
128 * 0: disable buffer packing.
129 * 1: enable buffer packing.
131 static int buffer_packing = -1;
132 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
133 0, "Enable buffer packing");
136 * Start next frame in a packed buffer at this boundary.
137 * -1: driver should figure out a good value.
138 * T4: driver will ignore this and use the same value as fl_pad above.
139 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
141 static int fl_pack = -1;
142 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
143 "payload pack boundary (bytes)");
146 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
147 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
148 * 1: ok to create mbuf(s) within a cluster if there is room.
150 static int allow_mbufs_in_cluster = 1;
151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN,
152 &allow_mbufs_in_cluster, 0,
153 "Allow driver to create mbufs within a rx cluster");
156 * Largest rx cluster size that the driver is allowed to allocate.
158 static int largest_rx_cluster = MJUM16BYTES;
159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
160 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
163 * Size of cluster allocation that's most likely to succeed. The driver will
164 * fall back to this size if it fails to allocate clusters larger than this.
166 static int safest_rx_cluster = PAGE_SIZE;
167 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
168 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
172 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
173 * for rewriting. -1 and 0-3 are all valid values.
174 * -1: hardware should leave the TCP timestamps alone.
180 static int tsclk = -1;
181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
182 "Control TCP timestamp rewriting when using pacing");
184 static int eo_max_backlog = 1024 * 1024;
185 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
186 0, "Maximum backlog of ratelimited data per flow");
190 * The interrupt holdoff timers are multiplied by this value on T6+.
191 * 1 and 3-17 (both inclusive) are legal values.
193 static int tscale = 1;
194 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
195 "Interrupt holdoff timer scale on T6+");
198 * Number of LRO entries in the lro_ctrl structure per rx queue.
200 static int lro_entries = TCP_LRO_ENTRIES;
201 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
202 "Number of LRO entries per RX queue");
205 * This enables presorting of frames before they're fed into tcp_lro_rx.
207 static int lro_mbufs = 0;
208 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
209 "Enable presorting of LRO frames");
212 u_int wr_type; /* type 0 or type 1 */
213 u_int npkt; /* # of packets in this work request */
214 u_int plen; /* total payload (sum of all packets) */
215 u_int len16; /* # of 16B pieces used by this work request */
218 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
221 struct sglist_seg seg[TX_SGL_SEGS];
224 static int service_iq(struct sge_iq *, int);
225 static int service_iq_fl(struct sge_iq *, int);
226 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
227 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
228 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
229 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
230 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
232 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
233 bus_addr_t *, void **);
234 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
236 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
238 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
239 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
241 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
242 struct sysctl_oid *, struct sge_fl *);
243 static int alloc_fwq(struct adapter *);
244 static int free_fwq(struct adapter *);
245 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
246 struct sysctl_oid *);
247 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
248 struct sysctl_oid *);
249 static int free_rxq(struct vi_info *, struct sge_rxq *);
251 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
252 struct sysctl_oid *);
253 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
256 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
257 struct sysctl_oid *);
258 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
259 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
260 struct sysctl_oid *);
261 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
263 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
264 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
265 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
266 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
268 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
269 static int free_eq(struct adapter *, struct sge_eq *);
270 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
271 struct sysctl_oid *);
272 static int free_wrq(struct adapter *, struct sge_wrq *);
273 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
274 struct sysctl_oid *);
275 static int free_txq(struct vi_info *, struct sge_txq *);
276 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
277 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
278 static int refill_fl(struct adapter *, struct sge_fl *, int);
279 static void refill_sfl(void *);
280 static int alloc_fl_sdesc(struct sge_fl *);
281 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
282 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
283 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
284 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
286 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
287 static inline u_int txpkt_len16(u_int, u_int);
288 static inline u_int txpkt_vm_len16(u_int, u_int);
289 static inline u_int txpkts0_len16(u_int);
290 static inline u_int txpkts1_len16(void);
291 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
292 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
293 struct mbuf *, u_int);
294 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
295 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
296 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
297 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
298 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
299 struct mbuf *, const struct txpkts *, u_int);
300 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
301 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
302 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
303 static inline uint16_t read_hw_cidx(struct sge_eq *);
304 static inline u_int reclaimable_tx_desc(struct sge_eq *);
305 static inline u_int total_available_tx_desc(struct sge_eq *);
306 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
307 static void tx_reclaim(void *, int);
308 static __be64 get_flit(struct sglist_seg *, int, int);
309 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
311 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
313 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
314 static void wrq_tx_drain(void *, int);
315 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
317 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
318 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
320 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
321 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
325 static counter_u64_t extfree_refs;
326 static counter_u64_t extfree_rels;
328 an_handler_t t4_an_handler;
329 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
330 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
331 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
332 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
333 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
334 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
335 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
338 t4_register_an_handler(an_handler_t h)
342 MPASS(h == NULL || t4_an_handler == NULL);
344 loc = (uintptr_t *)&t4_an_handler;
345 atomic_store_rel_ptr(loc, (uintptr_t)h);
349 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
353 MPASS(type < nitems(t4_fw_msg_handler));
354 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
356 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
357 * handler dispatch table. Reject any attempt to install a handler for
360 MPASS(type != FW_TYPE_RSSCPL);
361 MPASS(type != FW6_TYPE_RSSCPL);
363 loc = (uintptr_t *)&t4_fw_msg_handler[type];
364 atomic_store_rel_ptr(loc, (uintptr_t)h);
368 t4_register_cpl_handler(int opcode, cpl_handler_t h)
372 MPASS(opcode < nitems(t4_cpl_handler));
373 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
375 loc = (uintptr_t *)&t4_cpl_handler[opcode];
376 atomic_store_rel_ptr(loc, (uintptr_t)h);
380 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
383 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
390 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
392 * The return code for filter-write is put in the CPL cookie so
393 * we have to rely on the hardware tid (is_ftid) to determine
394 * that this is a response to a filter.
396 cookie = CPL_COOKIE_FILTER;
398 cookie = G_COOKIE(cpl->cookie);
400 MPASS(cookie > CPL_COOKIE_RESERVED);
401 MPASS(cookie < nitems(set_tcb_rpl_handlers));
403 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
407 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
410 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
415 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
416 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
420 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
423 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
424 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
427 MPASS(cookie != CPL_COOKIE_RESERVED);
429 return (act_open_rpl_handlers[cookie](iq, rss, m));
433 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
436 struct adapter *sc = iq->adapter;
440 if (is_hashfilter(sc))
441 cookie = CPL_COOKIE_HASHFILTER;
443 cookie = CPL_COOKIE_TOM;
445 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
449 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
451 struct adapter *sc = iq->adapter;
452 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
453 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
457 if (is_etid(sc, tid))
458 cookie = CPL_COOKIE_ETHOFLD;
460 cookie = CPL_COOKIE_TOM;
462 return (fw4_ack_handlers[cookie](iq, rss, m));
466 t4_init_shared_cpl_handlers(void)
469 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
470 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
471 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
472 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
473 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
477 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
481 MPASS(opcode < nitems(t4_cpl_handler));
482 MPASS(cookie > CPL_COOKIE_RESERVED);
483 MPASS(cookie < NUM_CPL_COOKIES);
484 MPASS(t4_cpl_handler[opcode] != NULL);
487 case CPL_SET_TCB_RPL:
488 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
490 case CPL_L2T_WRITE_RPL:
491 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
493 case CPL_ACT_OPEN_RPL:
494 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
496 case CPL_ABORT_RPL_RSS:
497 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
500 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
506 MPASS(h == NULL || *loc == (uintptr_t)NULL);
507 atomic_store_rel_ptr(loc, (uintptr_t)h);
511 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
517 if (fl_pktshift < 0 || fl_pktshift > 7) {
518 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
519 " using 0 instead.\n", fl_pktshift);
523 if (spg_len != 64 && spg_len != 128) {
526 #if defined(__i386__) || defined(__amd64__)
527 len = cpu_clflush_line_size > 64 ? 128 : 64;
532 printf("Invalid hw.cxgbe.spg_len value (%d),"
533 " using %d instead.\n", spg_len, len);
538 if (cong_drop < -1 || cong_drop > 1) {
539 printf("Invalid hw.cxgbe.cong_drop value (%d),"
540 " using 0 instead.\n", cong_drop);
544 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
545 printf("Invalid hw.cxgbe.tscale value (%d),"
546 " using 1 instead.\n", tscale);
550 extfree_refs = counter_u64_alloc(M_WAITOK);
551 extfree_rels = counter_u64_alloc(M_WAITOK);
552 counter_u64_zero(extfree_refs);
553 counter_u64_zero(extfree_rels);
555 t4_init_shared_cpl_handlers();
556 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
557 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
558 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
559 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
561 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
564 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
565 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
569 t4_sge_modunload(void)
572 counter_u64_free(extfree_refs);
573 counter_u64_free(extfree_rels);
577 t4_sge_extfree_refs(void)
581 rels = counter_u64_fetch(extfree_rels);
582 refs = counter_u64_fetch(extfree_refs);
584 return (refs - rels);
588 setup_pad_and_pack_boundaries(struct adapter *sc)
591 int pad, pack, pad_shift;
593 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
594 X_INGPADBOUNDARY_SHIFT;
596 if (fl_pad < (1 << pad_shift) ||
597 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
600 * If there is any chance that we might use buffer packing and
601 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
602 * it to the minimum allowed in all other cases.
604 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
607 * For fl_pad = 0 we'll still write a reasonable value to the
608 * register but all the freelists will opt out of padding.
609 * We'll complain here only if the user tried to set it to a
610 * value greater than 0 that was invalid.
613 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
614 " (%d), using %d instead.\n", fl_pad, pad);
617 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
618 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
619 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
622 if (fl_pack != -1 && fl_pack != pad) {
623 /* Complain but carry on. */
624 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
625 " using %d instead.\n", fl_pack, pad);
631 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
632 !powerof2(fl_pack)) {
633 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
634 MPASS(powerof2(pack));
642 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
643 " (%d), using %d instead.\n", fl_pack, pack);
646 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
648 v = V_INGPACKBOUNDARY(0);
650 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
652 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
653 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
657 * adap->params.vpd.cclk must be set up before this is called.
660 t4_tweak_chip_settings(struct adapter *sc)
664 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
665 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
666 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
668 static int sge_flbuf_sizes[] = {
670 #if MJUMPAGESIZE != MCLBYTES
672 MJUMPAGESIZE - CL_METADATA_SIZE,
673 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
677 MCLBYTES - MSIZE - CL_METADATA_SIZE,
678 MJUM9BYTES - CL_METADATA_SIZE,
679 MJUM16BYTES - CL_METADATA_SIZE,
682 KASSERT(sc->flags & MASTER_PF,
683 ("%s: trying to change chip settings when not master.", __func__));
685 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
686 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
687 V_EGRSTATUSPAGESIZE(spg_len == 128);
688 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
690 setup_pad_and_pack_boundaries(sc);
692 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
693 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
694 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
695 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
696 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
697 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
698 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
699 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
700 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
702 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
703 ("%s: hw buffer size table too big", __func__));
704 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
706 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
707 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i),
711 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
712 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
713 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
715 KASSERT(intr_timer[0] <= timer_max,
716 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
718 for (i = 1; i < nitems(intr_timer); i++) {
719 KASSERT(intr_timer[i] >= intr_timer[i - 1],
720 ("%s: timers not listed in increasing order (%d)",
723 while (intr_timer[i] > timer_max) {
724 if (i == nitems(intr_timer) - 1) {
725 intr_timer[i] = timer_max;
728 intr_timer[i] += intr_timer[i - 1];
733 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
734 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
735 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
736 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
737 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
738 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
739 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
740 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
741 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
743 if (chip_id(sc) >= CHELSIO_T6) {
744 m = V_TSCALE(M_TSCALE);
748 v = V_TSCALE(tscale - 2);
749 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
751 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
752 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
753 V_WRTHRTHRESH(M_WRTHRTHRESH);
754 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
756 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
758 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
762 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
763 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
764 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
767 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
768 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
769 * may have to deal with is MAXPHYS + 1 page.
771 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
772 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
774 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
775 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
776 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
778 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
780 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
781 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
785 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
786 * padding is in use, the buffer's start and end need to be aligned to the pad
787 * boundary as well. We'll just make sure that the size is a multiple of the
788 * boundary here, it is up to the buffer allocation code to make sure the start
789 * of the buffer is aligned as well.
792 hwsz_ok(struct adapter *sc, int hwsz)
794 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
796 return (hwsz >= 64 && (hwsz & mask) == 0);
800 * XXX: driver really should be able to deal with unexpected settings.
803 t4_read_chip_settings(struct adapter *sc)
805 struct sge *s = &sc->sge;
806 struct sge_params *sp = &sc->params.sge;
809 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
810 static int sw_buf_sizes[] = { /* Sorted by size */
812 #if MJUMPAGESIZE != MCLBYTES
818 struct sw_zone_info *swz, *safe_swz;
819 struct hw_buf_info *hwb;
823 r = sc->params.sge.sge_control;
825 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
830 * If this changes then every single use of PAGE_SHIFT in the driver
831 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
833 if (sp->page_shift != PAGE_SHIFT) {
834 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
838 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
839 hwb = &s->hw_buf_info[0];
840 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
841 r = sc->params.sge.sge_fl_buffer_size[i];
843 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
848 * Create a sorted list in decreasing order of hw buffer sizes (and so
849 * increasing order of spare area) for each software zone.
851 * If padding is enabled then the start and end of the buffer must align
852 * to the pad boundary; if packing is enabled then they must align with
853 * the pack boundary as well. Allocations from the cluster zones are
854 * aligned to min(size, 4K), so the buffer starts at that alignment and
855 * ends at hwb->size alignment. If mbuf inlining is allowed the
856 * starting alignment will be reduced to MSIZE and the driver will
857 * exercise appropriate caution when deciding on the best buffer layout
860 n = 0; /* no usable buffer size to begin with */
861 swz = &s->sw_zone_info[0];
863 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
864 int8_t head = -1, tail = -1;
866 swz->size = sw_buf_sizes[i];
867 swz->zone = m_getzone(swz->size);
868 swz->type = m_gettype(swz->size);
870 if (swz->size < PAGE_SIZE) {
871 MPASS(powerof2(swz->size));
872 if (fl_pad && (swz->size % sp->pad_boundary != 0))
876 if (swz->size == safest_rx_cluster)
879 hwb = &s->hw_buf_info[0];
880 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
881 if (hwb->zidx != -1 || hwb->size > swz->size)
885 MPASS(hwb->size % sp->pad_boundary == 0);
890 else if (hwb->size < s->hw_buf_info[tail].size) {
891 s->hw_buf_info[tail].next = j;
895 struct hw_buf_info *t;
897 for (cur = &head; *cur != -1; cur = &t->next) {
898 t = &s->hw_buf_info[*cur];
899 if (hwb->size == t->size) {
903 if (hwb->size > t->size) {
911 swz->head_hwidx = head;
912 swz->tail_hwidx = tail;
916 if (swz->size - s->hw_buf_info[tail].size >=
918 sc->flags |= BUF_PACKING_OK;
922 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
928 if (safe_swz != NULL) {
929 s->safe_hwidx1 = safe_swz->head_hwidx;
930 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
933 hwb = &s->hw_buf_info[i];
936 MPASS(hwb->size % sp->pad_boundary == 0);
938 spare = safe_swz->size - hwb->size;
939 if (spare >= CL_METADATA_SIZE) {
946 if (sc->flags & IS_VF)
949 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
950 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
952 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
956 m = v = F_TDDPTAGTCB;
957 r = t4_read_reg(sc, A_ULP_RX_CTL);
959 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
963 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
965 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
966 r = t4_read_reg(sc, A_TP_PARA_REG5);
968 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
972 t4_init_tp_params(sc, 1);
974 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
975 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
981 t4_create_dma_tag(struct adapter *sc)
985 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
986 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
987 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
990 device_printf(sc->dev,
991 "failed to create main DMA tag: %d\n", rc);
998 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
999 struct sysctl_oid_list *children)
1001 struct sge_params *sp = &sc->params.sge;
1003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
1004 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
1005 "freelist buffer sizes");
1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1008 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1011 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1013 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1014 NULL, sp->spg_len, "status page size (bytes)");
1016 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1017 NULL, cong_drop, "congestion drop setting");
1019 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1020 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1024 t4_destroy_dma_tag(struct adapter *sc)
1027 bus_dma_tag_destroy(sc->dmat);
1033 * Allocate and initialize the firmware event queue, control queues, and special
1034 * purpose rx queues owned by the adapter.
1036 * Returns errno on failure. Resources allocated up to that point may still be
1037 * allocated. Caller is responsible for cleanup in case this function fails.
1040 t4_setup_adapter_queues(struct adapter *sc)
1042 struct sysctl_oid *oid;
1043 struct sysctl_oid_list *children;
1046 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1048 sysctl_ctx_init(&sc->ctx);
1049 sc->flags |= ADAP_SYSCTL_CTX;
1052 * Firmware event queue
1059 * That's all for the VF driver.
1061 if (sc->flags & IS_VF)
1064 oid = device_get_sysctl_tree(sc->dev);
1065 children = SYSCTL_CHILDREN(oid);
1068 * XXX: General purpose rx queues, one per port.
1072 * Control queues, one per port.
1074 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1075 CTLFLAG_RD, NULL, "control queues");
1076 for_each_port(sc, i) {
1077 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1079 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1091 t4_teardown_adapter_queues(struct adapter *sc)
1095 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1097 /* Do this before freeing the queue */
1098 if (sc->flags & ADAP_SYSCTL_CTX) {
1099 sysctl_ctx_free(&sc->ctx);
1100 sc->flags &= ~ADAP_SYSCTL_CTX;
1103 if (!(sc->flags & IS_VF)) {
1104 for_each_port(sc, i)
1105 free_wrq(sc, &sc->sge.ctrlq[i]);
1112 /* Maximum payload that can be delivered with a single iq descriptor */
1114 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
1120 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
1122 /* Note that COP can set rx_coalesce on/off per connection. */
1123 payload = max(mtu, rxcs);
1126 /* large enough even when hw VLAN extraction is disabled */
1127 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1128 ETHER_VLAN_ENCAP_LEN + mtu;
1137 t4_setup_vi_queues(struct vi_info *vi)
1139 int rc = 0, i, intr_idx, iqidx;
1140 struct sge_rxq *rxq;
1141 struct sge_txq *txq;
1143 struct sge_ofld_rxq *ofld_rxq;
1145 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1146 struct sge_wrq *ofld_txq;
1150 struct sge_nm_rxq *nm_rxq;
1151 struct sge_nm_txq *nm_txq;
1154 struct port_info *pi = vi->pi;
1155 struct adapter *sc = pi->adapter;
1156 struct ifnet *ifp = vi->ifp;
1157 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1158 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1159 int maxp, mtu = ifp->if_mtu;
1161 /* Interrupt vector to start from (when using multiple vectors) */
1162 intr_idx = vi->first_intr;
1165 saved_idx = intr_idx;
1166 if (ifp->if_capabilities & IFCAP_NETMAP) {
1168 /* netmap is supported with direct interrupts only. */
1169 MPASS(!forwarding_intr_to_fwq(sc));
1172 * We don't have buffers to back the netmap rx queues
1173 * right now so we create the queues in a way that
1174 * doesn't set off any congestion signal in the chip.
1176 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1177 CTLFLAG_RD, NULL, "rx queues");
1178 for_each_nm_rxq(vi, i, nm_rxq) {
1179 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1185 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1186 CTLFLAG_RD, NULL, "tx queues");
1187 for_each_nm_txq(vi, i, nm_txq) {
1188 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1189 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1195 /* Normal rx queues and netmap rx queues share the same interrupts. */
1196 intr_idx = saved_idx;
1200 * Allocate rx queues first because a default iqid is required when
1201 * creating a tx queue.
1203 maxp = mtu_to_max_payload(sc, mtu, 0);
1204 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1205 CTLFLAG_RD, NULL, "rx queues");
1206 for_each_rxq(vi, i, rxq) {
1208 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1210 snprintf(name, sizeof(name), "%s rxq%d-fl",
1211 device_get_nameunit(vi->dev), i);
1212 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1214 rc = alloc_rxq(vi, rxq,
1215 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1221 if (ifp->if_capabilities & IFCAP_NETMAP)
1222 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1225 maxp = mtu_to_max_payload(sc, mtu, 1);
1226 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1227 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections");
1228 for_each_ofld_rxq(vi, i, ofld_rxq) {
1230 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1233 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1234 device_get_nameunit(vi->dev), i);
1235 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1237 rc = alloc_ofld_rxq(vi, ofld_rxq,
1238 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1246 * Now the tx queues.
1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1250 for_each_txq(vi, i, txq) {
1251 iqidx = vi->first_rxq + (i % vi->nrxq);
1252 snprintf(name, sizeof(name), "%s txq%d",
1253 device_get_nameunit(vi->dev), i);
1254 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1255 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1257 rc = alloc_txq(vi, txq, i, oid);
1261 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1262 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1263 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD");
1264 for_each_ofld_txq(vi, i, ofld_txq) {
1265 struct sysctl_oid *oid2;
1267 snprintf(name, sizeof(name), "%s ofld_txq%d",
1268 device_get_nameunit(vi->dev), i);
1269 if (vi->nofldrxq > 0) {
1270 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1271 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1272 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id,
1275 iqidx = vi->first_rxq + (i % vi->nrxq);
1276 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1277 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name);
1280 snprintf(name, sizeof(name), "%d", i);
1281 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1282 name, CTLFLAG_RD, NULL, "offload tx queue");
1284 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1291 t4_teardown_vi_queues(vi);
1300 t4_teardown_vi_queues(struct vi_info *vi)
1303 struct sge_rxq *rxq;
1304 struct sge_txq *txq;
1305 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1306 struct port_info *pi = vi->pi;
1307 struct adapter *sc = pi->adapter;
1308 struct sge_wrq *ofld_txq;
1311 struct sge_ofld_rxq *ofld_rxq;
1314 struct sge_nm_rxq *nm_rxq;
1315 struct sge_nm_txq *nm_txq;
1318 /* Do this before freeing the queues */
1319 if (vi->flags & VI_SYSCTL_CTX) {
1320 sysctl_ctx_free(&vi->ctx);
1321 vi->flags &= ~VI_SYSCTL_CTX;
1325 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1326 for_each_nm_txq(vi, i, nm_txq) {
1327 free_nm_txq(vi, nm_txq);
1330 for_each_nm_rxq(vi, i, nm_rxq) {
1331 free_nm_rxq(vi, nm_rxq);
1337 * Take down all the tx queues first, as they reference the rx queues
1338 * (for egress updates, etc.).
1341 for_each_txq(vi, i, txq) {
1344 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1345 for_each_ofld_txq(vi, i, ofld_txq) {
1346 free_wrq(sc, ofld_txq);
1351 * Then take down the rx queues.
1354 for_each_rxq(vi, i, rxq) {
1358 for_each_ofld_rxq(vi, i, ofld_rxq) {
1359 free_ofld_rxq(vi, ofld_rxq);
1367 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1370 * a) Deals with errors, if any.
1371 * b) Services firmware event queue, which is taking interrupts for all other
1375 t4_intr_all(void *arg)
1377 struct adapter *sc = arg;
1378 struct sge_iq *fwq = &sc->sge.fwq;
1380 MPASS(sc->intr_count == 1);
1382 if (sc->intr_type == INTR_INTX)
1383 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1390 * Interrupt handler for errors (installed directly when multiple interrupts are
1391 * being used, or called by t4_intr_all).
1394 t4_intr_err(void *arg)
1396 struct adapter *sc = arg;
1398 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1400 if (sc->flags & ADAP_ERR)
1403 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1406 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1409 t4_slow_intr_handler(sc, verbose);
1413 * Interrupt handler for iq-only queues. The firmware event queue is the only
1414 * such queue right now.
1417 t4_intr_evt(void *arg)
1419 struct sge_iq *iq = arg;
1421 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1423 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1428 * Interrupt handler for iq+fl queues.
1433 struct sge_iq *iq = arg;
1435 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1436 service_iq_fl(iq, 0);
1437 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1443 * Interrupt handler for netmap rx queues.
1446 t4_nm_intr(void *arg)
1448 struct sge_nm_rxq *nm_rxq = arg;
1450 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1451 service_nm_rxq(nm_rxq);
1452 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1457 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1460 t4_vi_intr(void *arg)
1462 struct irq *irq = arg;
1464 MPASS(irq->nm_rxq != NULL);
1465 t4_nm_intr(irq->nm_rxq);
1467 MPASS(irq->rxq != NULL);
1473 * Deals with interrupts on an iq-only (no freelist) queue.
1476 service_iq(struct sge_iq *iq, int budget)
1479 struct adapter *sc = iq->adapter;
1480 struct iq_desc *d = &iq->desc[iq->cidx];
1481 int ndescs = 0, limit;
1484 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1486 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1487 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1488 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1490 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1491 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1493 limit = budget ? budget : iq->qsize / 16;
1496 * We always come back and check the descriptor ring for new indirect
1497 * interrupts and other responses after running a single handler.
1500 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1504 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1505 lq = be32toh(d->rsp.pldbuflen_qid);
1508 case X_RSPD_TYPE_FLBUF:
1509 panic("%s: data for an iq (%p) with no freelist",
1514 case X_RSPD_TYPE_CPL:
1515 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1516 ("%s: bad opcode %02x.", __func__,
1518 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1521 case X_RSPD_TYPE_INTR:
1523 * There are 1K interrupt-capable queues (qids 0
1524 * through 1023). A response type indicating a
1525 * forwarded interrupt with a qid >= 1K is an
1526 * iWARP async notification.
1528 if (__predict_true(lq >= 1024)) {
1529 t4_an_handler(iq, &d->rsp);
1533 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1535 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1537 if (service_iq_fl(q, q->qsize / 16) == 0) {
1538 (void) atomic_cmpset_int(&q->state,
1539 IQS_BUSY, IQS_IDLE);
1541 STAILQ_INSERT_TAIL(&iql, q,
1549 ("%s: illegal response type %d on iq %p",
1550 __func__, rsp_type, iq));
1552 "%s: illegal response type %d on iq %p",
1553 device_get_nameunit(sc->dev), rsp_type, iq);
1558 if (__predict_false(++iq->cidx == iq->sidx)) {
1560 iq->gen ^= F_RSPD_GEN;
1563 if (__predict_false(++ndescs == limit)) {
1564 t4_write_reg(sc, sc->sge_gts_reg,
1566 V_INGRESSQID(iq->cntxt_id) |
1567 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1571 return (EINPROGRESS);
1576 if (STAILQ_EMPTY(&iql))
1580 * Process the head only, and send it to the back of the list if
1581 * it's still not done.
1583 q = STAILQ_FIRST(&iql);
1584 STAILQ_REMOVE_HEAD(&iql, link);
1585 if (service_iq_fl(q, q->qsize / 8) == 0)
1586 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1588 STAILQ_INSERT_TAIL(&iql, q, link);
1591 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1592 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1598 sort_before_lro(struct lro_ctrl *lro)
1601 return (lro->lro_mbuf_max != 0);
1604 static inline uint64_t
1605 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1607 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1609 if (n > UINT64_MAX / 1000000)
1610 return (n / sc->params.vpd.cclk * 1000000);
1612 return (n * 1000000 / sc->params.vpd.cclk);
1616 * Deals with interrupts on an iq+fl queue.
1619 service_iq_fl(struct sge_iq *iq, int budget)
1621 struct sge_rxq *rxq = iq_to_rxq(iq);
1623 struct adapter *sc = iq->adapter;
1624 struct iq_desc *d = &iq->desc[iq->cidx];
1625 int ndescs = 0, limit;
1626 int rsp_type, refill, starved;
1628 uint16_t fl_hw_cidx;
1630 #if defined(INET) || defined(INET6)
1631 const struct timeval lro_timeout = {0, sc->lro_timeout};
1632 struct lro_ctrl *lro = &rxq->lro;
1635 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1636 MPASS(iq->flags & IQ_HAS_FL);
1638 limit = budget ? budget : iq->qsize / 16;
1640 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1642 #if defined(INET) || defined(INET6)
1643 if (iq->flags & IQ_ADJ_CREDIT) {
1644 MPASS(sort_before_lro(lro));
1645 iq->flags &= ~IQ_ADJ_CREDIT;
1646 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1647 tcp_lro_flush_all(lro);
1648 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1649 V_INGRESSQID((u32)iq->cntxt_id) |
1650 V_SEINTARM(iq->intr_params));
1656 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1659 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1665 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1666 lq = be32toh(d->rsp.pldbuflen_qid);
1669 case X_RSPD_TYPE_FLBUF:
1671 m0 = get_fl_payload(sc, fl, lq);
1672 if (__predict_false(m0 == NULL))
1674 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1676 if (iq->flags & IQ_RX_TIMESTAMP) {
1678 * Fill up rcv_tstmp but do not set M_TSTMP.
1679 * rcv_tstmp is not in the format that the
1680 * kernel expects and we don't want to mislead
1681 * it. For now this is only for custom code
1682 * that knows how to interpret cxgbe's stamp.
1684 m0->m_pkthdr.rcv_tstmp =
1685 last_flit_to_ns(sc, d->rsp.u.last_flit);
1687 m0->m_flags |= M_TSTMP;
1693 case X_RSPD_TYPE_CPL:
1694 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1695 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1696 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1699 case X_RSPD_TYPE_INTR:
1702 * There are 1K interrupt-capable queues (qids 0
1703 * through 1023). A response type indicating a
1704 * forwarded interrupt with a qid >= 1K is an
1705 * iWARP async notification. That is the only
1706 * acceptable indirect interrupt on this queue.
1708 if (__predict_false(lq < 1024)) {
1709 panic("%s: indirect interrupt on iq_fl %p "
1710 "with qid %u", __func__, iq, lq);
1713 t4_an_handler(iq, &d->rsp);
1717 KASSERT(0, ("%s: illegal response type %d on iq %p",
1718 __func__, rsp_type, iq));
1719 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1720 device_get_nameunit(sc->dev), rsp_type, iq);
1725 if (__predict_false(++iq->cidx == iq->sidx)) {
1727 iq->gen ^= F_RSPD_GEN;
1730 if (__predict_false(++ndescs == limit)) {
1731 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1732 V_INGRESSQID(iq->cntxt_id) |
1733 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1736 #if defined(INET) || defined(INET6)
1737 if (iq->flags & IQ_LRO_ENABLED &&
1738 !sort_before_lro(lro) &&
1739 sc->lro_timeout != 0) {
1740 tcp_lro_flush_inactive(lro, &lro_timeout);
1745 refill_fl(sc, fl, 32);
1748 return (EINPROGRESS);
1753 refill_fl(sc, fl, 32);
1755 fl_hw_cidx = fl->hw_cidx;
1759 #if defined(INET) || defined(INET6)
1760 if (iq->flags & IQ_LRO_ENABLED) {
1761 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1762 MPASS(sort_before_lro(lro));
1763 /* hold back one credit and don't flush LRO state */
1764 iq->flags |= IQ_ADJ_CREDIT;
1767 tcp_lro_flush_all(lro);
1772 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1773 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1776 starved = refill_fl(sc, fl, 64);
1778 if (__predict_false(starved != 0))
1779 add_fl_to_sfl(sc, fl);
1785 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1787 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1790 MPASS(cll->region3 >= CL_METADATA_SIZE);
1795 static inline struct cluster_metadata *
1796 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1800 if (cl_has_metadata(fl, cll)) {
1801 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1803 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1809 rxb_free(struct mbuf *m)
1811 uma_zone_t zone = m->m_ext.ext_arg1;
1812 void *cl = m->m_ext.ext_arg2;
1814 uma_zfree(zone, cl);
1815 counter_u64_add(extfree_rels, 1);
1819 * The mbuf returned by this function could be allocated from zone_mbuf or
1820 * constructed in spare room in the cluster.
1822 * The mbuf carries the payload in one of these ways
1823 * a) frame inside the mbuf (mbuf from zone_mbuf)
1824 * b) m_cljset (for clusters without metadata) zone_mbuf
1825 * c) m_extaddref (cluster with metadata) inline mbuf
1826 * d) m_extaddref (cluster with metadata) zone_mbuf
1828 static struct mbuf *
1829 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1833 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1834 struct cluster_layout *cll = &sd->cll;
1835 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1836 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1837 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1841 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1842 len = min(remaining, blen);
1843 payload = sd->cl + cll->region1 + fl->rx_offset;
1844 if (fl->flags & FL_BUF_PACKING) {
1845 const u_int l = fr_offset + len;
1846 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1848 if (fl->rx_offset + len + pad < hwb->size)
1850 MPASS(fl->rx_offset + blen <= hwb->size);
1852 MPASS(fl->rx_offset == 0); /* not packing */
1856 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1859 * Copy payload into a freshly allocated mbuf.
1862 m = fr_offset == 0 ?
1863 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1866 fl->mbuf_allocated++;
1868 /* copy data to mbuf */
1869 bcopy(payload, mtod(m, caddr_t), len);
1871 } else if (sd->nmbuf * MSIZE < cll->region1) {
1874 * There's spare room in the cluster for an mbuf. Create one
1875 * and associate it with the payload that's in the cluster.
1879 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1880 /* No bzero required */
1881 if (m_init(m, M_NOWAIT, MT_DATA,
1882 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1885 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1887 if (sd->nmbuf++ == 0)
1888 counter_u64_add(extfree_refs, 1);
1893 * Grab an mbuf from zone_mbuf and associate it with the
1894 * payload in the cluster.
1897 m = fr_offset == 0 ?
1898 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1901 fl->mbuf_allocated++;
1903 m_extaddref(m, payload, blen, &clm->refcount,
1904 rxb_free, swz->zone, sd->cl);
1905 if (sd->nmbuf++ == 0)
1906 counter_u64_add(extfree_refs, 1);
1908 m_cljset(m, sd->cl, swz->type);
1909 sd->cl = NULL; /* consumed, not a recycle candidate */
1913 m->m_pkthdr.len = remaining;
1916 if (fl->flags & FL_BUF_PACKING) {
1917 fl->rx_offset += blen;
1918 MPASS(fl->rx_offset <= hwb->size);
1919 if (fl->rx_offset < hwb->size)
1920 return (m); /* without advancing the cidx */
1923 if (__predict_false(++fl->cidx % 8 == 0)) {
1924 uint16_t cidx = fl->cidx / 8;
1926 if (__predict_false(cidx == fl->sidx))
1927 fl->cidx = cidx = 0;
1935 static struct mbuf *
1936 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1938 struct mbuf *m0, *m, **pnext;
1940 const u_int total = G_RSPD_LEN(len_newbuf);
1942 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1943 M_ASSERTPKTHDR(fl->m0);
1944 MPASS(fl->m0->m_pkthdr.len == total);
1945 MPASS(fl->remaining < total);
1949 remaining = fl->remaining;
1950 fl->flags &= ~FL_BUF_RESUME;
1954 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1956 if (__predict_false(++fl->cidx % 8 == 0)) {
1957 uint16_t cidx = fl->cidx / 8;
1959 if (__predict_false(cidx == fl->sidx))
1960 fl->cidx = cidx = 0;
1966 * Payload starts at rx_offset in the current hw buffer. Its length is
1967 * 'len' and it may span multiple hw buffers.
1970 m0 = get_scatter_segment(sc, fl, 0, total);
1973 remaining = total - m0->m_len;
1974 pnext = &m0->m_next;
1975 while (remaining > 0) {
1977 MPASS(fl->rx_offset == 0);
1978 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1979 if (__predict_false(m == NULL)) {
1982 fl->remaining = remaining;
1983 fl->flags |= FL_BUF_RESUME;
1988 remaining -= m->m_len;
1997 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1999 struct sge_rxq *rxq = iq_to_rxq(iq);
2000 struct ifnet *ifp = rxq->ifp;
2001 struct adapter *sc = iq->adapter;
2002 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
2003 #if defined(INET) || defined(INET6)
2004 struct lro_ctrl *lro = &rxq->lro;
2006 static const int sw_hashtype[4][2] = {
2007 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
2008 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
2009 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
2010 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
2013 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
2016 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2017 m0->m_len -= sc->params.sge.fl_pktshift;
2018 m0->m_data += sc->params.sge.fl_pktshift;
2020 m0->m_pkthdr.rcvif = ifp;
2021 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
2022 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
2024 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
2025 if (ifp->if_capenable & IFCAP_RXCSUM &&
2026 cpl->l2info & htobe32(F_RXF_IP)) {
2027 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
2028 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
2030 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
2031 cpl->l2info & htobe32(F_RXF_IP6)) {
2032 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
2037 if (__predict_false(cpl->ip_frag))
2038 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2040 m0->m_pkthdr.csum_data = 0xffff;
2044 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2045 m0->m_flags |= M_VLANTAG;
2046 rxq->vlan_extraction++;
2049 #if defined(INET) || defined(INET6)
2050 if (iq->flags & IQ_LRO_ENABLED) {
2051 if (sort_before_lro(lro)) {
2052 tcp_lro_queue_mbuf(lro, m0);
2053 return (0); /* queued for sort, then LRO */
2055 if (tcp_lro_rx(lro, m0, 0) == 0)
2056 return (0); /* queued for LRO */
2059 ifp->if_input(ifp, m0);
2065 * Must drain the wrq or make sure that someone else will.
2068 wrq_tx_drain(void *arg, int n)
2070 struct sge_wrq *wrq = arg;
2071 struct sge_eq *eq = &wrq->eq;
2074 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2075 drain_wrq_wr_list(wrq->adapter, wrq);
2080 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2082 struct sge_eq *eq = &wrq->eq;
2083 u_int available, dbdiff; /* # of hardware descriptors */
2086 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2088 EQ_LOCK_ASSERT_OWNED(eq);
2089 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2090 wr = STAILQ_FIRST(&wrq->wr_list);
2091 MPASS(wr != NULL); /* Must be called with something useful to do */
2092 MPASS(eq->pidx == eq->dbidx);
2096 eq->cidx = read_hw_cidx(eq);
2097 if (eq->pidx == eq->cidx)
2098 available = eq->sidx - 1;
2100 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2102 MPASS(wr->wrq == wrq);
2103 n = howmany(wr->wr_len, EQ_ESIZE);
2107 dst = (void *)&eq->desc[eq->pidx];
2108 if (__predict_true(eq->sidx - eq->pidx > n)) {
2109 /* Won't wrap, won't end exactly at the status page. */
2110 bcopy(&wr->wr[0], dst, wr->wr_len);
2113 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2115 bcopy(&wr->wr[0], dst, first_portion);
2116 if (wr->wr_len > first_portion) {
2117 bcopy(&wr->wr[first_portion], &eq->desc[0],
2118 wr->wr_len - first_portion);
2120 eq->pidx = n - (eq->sidx - eq->pidx);
2122 wrq->tx_wrs_copied++;
2124 if (available < eq->sidx / 4 &&
2125 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2127 * XXX: This is not 100% reliable with some
2128 * types of WRs. But this is a very unusual
2129 * situation for an ofld/ctrl queue anyway.
2131 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2137 ring_eq_db(sc, eq, dbdiff);
2141 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2143 MPASS(wrq->nwr_pending > 0);
2145 MPASS(wrq->ndesc_needed >= n);
2146 wrq->ndesc_needed -= n;
2147 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2150 ring_eq_db(sc, eq, dbdiff);
2154 * Doesn't fail. Holds on to work requests it can't send right away.
2157 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2160 struct sge_eq *eq = &wrq->eq;
2163 EQ_LOCK_ASSERT_OWNED(eq);
2165 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2166 MPASS((wr->wr_len & 0x7) == 0);
2168 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2170 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2172 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2173 return; /* commit_wrq_wr will drain wr_list as well. */
2175 drain_wrq_wr_list(sc, wrq);
2177 /* Doorbell must have caught up to the pidx. */
2178 MPASS(eq->pidx == eq->dbidx);
2182 t4_update_fl_bufsize(struct ifnet *ifp)
2184 struct vi_info *vi = ifp->if_softc;
2185 struct adapter *sc = vi->pi->adapter;
2186 struct sge_rxq *rxq;
2188 struct sge_ofld_rxq *ofld_rxq;
2191 int i, maxp, mtu = ifp->if_mtu;
2193 maxp = mtu_to_max_payload(sc, mtu, 0);
2194 for_each_rxq(vi, i, rxq) {
2198 find_best_refill_source(sc, fl, maxp);
2202 maxp = mtu_to_max_payload(sc, mtu, 1);
2203 for_each_ofld_rxq(vi, i, ofld_rxq) {
2207 find_best_refill_source(sc, fl, maxp);
2214 mbuf_nsegs(struct mbuf *m)
2218 KASSERT(m->m_pkthdr.l5hlen > 0,
2219 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2221 return (m->m_pkthdr.l5hlen);
2225 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2229 m->m_pkthdr.l5hlen = nsegs;
2233 mbuf_cflags(struct mbuf *m)
2237 return (m->m_pkthdr.PH_loc.eight[4]);
2241 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2245 m->m_pkthdr.PH_loc.eight[4] = flags;
2249 mbuf_len16(struct mbuf *m)
2254 n = m->m_pkthdr.PH_loc.eight[0];
2255 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2261 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2265 m->m_pkthdr.PH_loc.eight[0] = len16;
2270 mbuf_eo_nsegs(struct mbuf *m)
2274 return (m->m_pkthdr.PH_loc.eight[1]);
2278 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2282 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2286 mbuf_eo_len16(struct mbuf *m)
2291 n = m->m_pkthdr.PH_loc.eight[2];
2292 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2298 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2302 m->m_pkthdr.PH_loc.eight[2] = len16;
2306 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2310 return (m->m_pkthdr.PH_loc.eight[3]);
2314 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2318 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2322 needs_eo(struct mbuf *m)
2325 return (m->m_pkthdr.snd_tag != NULL);
2330 * Try to allocate an mbuf to contain a raw work request. To make it
2331 * easy to construct the work request, don't allocate a chain but a
2335 alloc_wr_mbuf(int len, int how)
2340 m = m_gethdr(how, MT_DATA);
2341 else if (len <= MCLBYTES)
2342 m = m_getcl(how, MT_DATA, M_PKTHDR);
2347 m->m_pkthdr.len = len;
2349 set_mbuf_cflags(m, MC_RAW_WR);
2350 set_mbuf_len16(m, howmany(len, 16));
2355 needs_tso(struct mbuf *m)
2360 return (m->m_pkthdr.csum_flags & CSUM_TSO);
2364 needs_l3_csum(struct mbuf *m)
2369 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO));
2373 needs_l4_csum(struct mbuf *m)
2378 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2379 CSUM_TCP_IPV6 | CSUM_TSO));
2383 needs_tcp_csum(struct mbuf *m)
2387 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO));
2392 needs_udp_csum(struct mbuf *m)
2396 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6));
2401 needs_vlan_insertion(struct mbuf *m)
2406 return (m->m_flags & M_VLANTAG);
2410 m_advance(struct mbuf **pm, int *poffset, int len)
2412 struct mbuf *m = *pm;
2413 int offset = *poffset;
2419 if (offset + len < m->m_len) {
2421 p = mtod(m, uintptr_t) + offset;
2424 len -= m->m_len - offset;
2435 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2436 * must have at least one mbuf that's not empty. It is possible for this
2437 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2440 count_mbuf_nsegs(struct mbuf *m, int skip)
2442 vm_paddr_t lastb, next;
2447 MPASS(m->m_pkthdr.len > 0);
2448 MPASS(m->m_pkthdr.len >= skip);
2452 for (; m; m = m->m_next) {
2455 if (__predict_false(len == 0))
2461 va = mtod(m, vm_offset_t) + skip;
2464 next = pmap_kextract(va);
2465 nsegs += sglist_count((void *)(uintptr_t)va, len);
2466 if (lastb + 1 == next)
2468 lastb = pmap_kextract(va + len - 1);
2475 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2476 * a) caller can assume it's been freed if this function returns with an error.
2477 * b) it may get defragged up if the gather list is too long for the hardware.
2480 parse_pkt(struct adapter *sc, struct mbuf **mp)
2482 struct mbuf *m0 = *mp, *m;
2483 int rc, nsegs, defragged = 0, offset;
2484 struct ether_header *eh;
2486 #if defined(INET) || defined(INET6)
2492 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2501 * First count the number of gather list segments in the payload.
2502 * Defrag the mbuf if nsegs exceeds the hardware limit.
2505 MPASS(m0->m_pkthdr.len > 0);
2506 nsegs = count_mbuf_nsegs(m0, 0);
2507 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2508 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2512 *mp = m0 = m; /* update caller's copy after defrag */
2516 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2517 m0 = m_pullup(m0, m0->m_pkthdr.len);
2519 /* Should have left well enough alone. */
2523 *mp = m0; /* update caller's copy after pullup */
2526 set_mbuf_nsegs(m0, nsegs);
2527 set_mbuf_cflags(m0, 0);
2528 if (sc->flags & IS_VF)
2529 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2531 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2535 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2536 * checksumming is enabled. needs_l4_csum happens to check for all the
2539 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0)))
2540 m0->m_pkthdr.snd_tag = NULL;
2543 if (!needs_tso(m0) &&
2547 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2551 eh = mtod(m, struct ether_header *);
2552 eh_type = ntohs(eh->ether_type);
2553 if (eh_type == ETHERTYPE_VLAN) {
2554 struct ether_vlan_header *evh = (void *)eh;
2556 eh_type = ntohs(evh->evl_proto);
2557 m0->m_pkthdr.l2hlen = sizeof(*evh);
2559 m0->m_pkthdr.l2hlen = sizeof(*eh);
2562 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2566 case ETHERTYPE_IPV6:
2568 struct ip6_hdr *ip6 = l3hdr;
2570 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2572 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2579 struct ip *ip = l3hdr;
2581 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2586 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2587 " with the same INET/INET6 options as the kernel.",
2591 #if defined(INET) || defined(INET6)
2592 if (needs_tcp_csum(m0)) {
2593 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2594 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2596 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2597 set_mbuf_eo_tsclk_tsoff(m0,
2598 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2599 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2601 set_mbuf_eo_tsclk_tsoff(m0, 0);
2602 } else if (needs_udp_csum(m)) {
2603 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2610 /* EO WRs have the headers in the WR and not the GL. */
2611 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2612 m0->m_pkthdr.l4hlen;
2613 nsegs = count_mbuf_nsegs(m0, immhdrs);
2614 set_mbuf_eo_nsegs(m0, nsegs);
2615 set_mbuf_eo_len16(m0,
2616 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2625 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2627 struct sge_eq *eq = &wrq->eq;
2628 struct adapter *sc = wrq->adapter;
2629 int ndesc, available;
2634 ndesc = howmany(len16, EQ_ESIZE / 16);
2635 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2639 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2640 drain_wrq_wr_list(sc, wrq);
2642 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2645 wr = alloc_wrqe(len16 * 16, wrq);
2646 if (__predict_false(wr == NULL))
2649 cookie->ndesc = ndesc;
2653 eq->cidx = read_hw_cidx(eq);
2654 if (eq->pidx == eq->cidx)
2655 available = eq->sidx - 1;
2657 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2658 if (available < ndesc)
2661 cookie->pidx = eq->pidx;
2662 cookie->ndesc = ndesc;
2663 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2665 w = &eq->desc[eq->pidx];
2666 IDXINCR(eq->pidx, ndesc, eq->sidx);
2667 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2669 wrq->ss_pidx = cookie->pidx;
2670 wrq->ss_len = len16 * 16;
2679 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2681 struct sge_eq *eq = &wrq->eq;
2682 struct adapter *sc = wrq->adapter;
2684 struct wrq_cookie *prev, *next;
2686 if (cookie->pidx == -1) {
2687 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2693 if (__predict_false(w == &wrq->ss[0])) {
2694 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2696 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2697 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2698 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2701 wrq->tx_wrs_direct++;
2704 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2705 pidx = cookie->pidx;
2706 MPASS(pidx >= 0 && pidx < eq->sidx);
2707 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2708 next = TAILQ_NEXT(cookie, link);
2710 MPASS(pidx == eq->dbidx);
2711 if (next == NULL || ndesc >= 16) {
2713 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2716 * Note that the WR via which we'll request tx updates
2717 * is at pidx and not eq->pidx, which has moved on
2720 dst = (void *)&eq->desc[pidx];
2721 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2722 if (available < eq->sidx / 4 &&
2723 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2725 * XXX: This is not 100% reliable with some
2726 * types of WRs. But this is a very unusual
2727 * situation for an ofld/ctrl queue anyway.
2729 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2733 ring_eq_db(wrq->adapter, eq, ndesc);
2735 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2737 next->ndesc += ndesc;
2740 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2741 prev->ndesc += ndesc;
2743 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2745 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2746 drain_wrq_wr_list(sc, wrq);
2749 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2750 /* Doorbell must have caught up to the pidx. */
2751 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2758 can_resume_eth_tx(struct mp_ring *r)
2760 struct sge_eq *eq = r->cookie;
2762 return (total_available_tx_desc(eq) > eq->sidx / 8);
2766 cannot_use_txpkts(struct mbuf *m)
2768 /* maybe put a GL limit too, to avoid silliness? */
2770 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0);
2774 discard_tx(struct sge_eq *eq)
2777 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2781 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr)
2784 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
2786 case FW_ETH_TX_PKT_WR:
2787 case FW_ETH_TX_PKTS_WR:
2788 case FW_ETH_TX_PKT_VM_WR:
2796 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2797 * be consumed. Return the actual number consumed. 0 indicates a stall.
2800 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2802 struct sge_txq *txq = r->cookie;
2803 struct sge_eq *eq = &txq->eq;
2804 struct ifnet *ifp = txq->ifp;
2805 struct vi_info *vi = ifp->if_softc;
2806 struct port_info *pi = vi->pi;
2807 struct adapter *sc = pi->adapter;
2808 u_int total, remaining; /* # of packets */
2809 u_int available, dbdiff; /* # of hardware descriptors */
2811 struct mbuf *m0, *tail;
2813 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2815 remaining = IDXDIFF(pidx, cidx, r->size);
2816 MPASS(remaining > 0); /* Must not be called without work to do. */
2820 if (__predict_false(discard_tx(eq))) {
2821 while (cidx != pidx) {
2822 m0 = r->items[cidx];
2824 if (++cidx == r->size)
2827 reclaim_tx_descs(txq, 2048);
2832 /* How many hardware descriptors do we have readily available. */
2833 if (eq->pidx == eq->cidx)
2834 available = eq->sidx - 1;
2836 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2837 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2839 while (remaining > 0) {
2841 m0 = r->items[cidx];
2843 MPASS(m0->m_nextpkt == NULL);
2845 if (available < SGE_MAX_WR_NDESC) {
2846 available += reclaim_tx_descs(txq, 64);
2847 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2848 break; /* out of descriptors */
2851 next_cidx = cidx + 1;
2852 if (__predict_false(next_cidx == r->size))
2855 wr = (void *)&eq->desc[eq->pidx];
2856 if (sc->flags & IS_VF) {
2859 ETHER_BPF_MTAP(ifp, m0);
2860 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2862 } else if (remaining > 1 &&
2863 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2865 /* pkts at cidx, next_cidx should both be in txp. */
2866 MPASS(txp.npkt == 2);
2867 tail = r->items[next_cidx];
2868 MPASS(tail->m_nextpkt == NULL);
2869 ETHER_BPF_MTAP(ifp, m0);
2870 ETHER_BPF_MTAP(ifp, tail);
2871 m0->m_nextpkt = tail;
2873 if (__predict_false(++next_cidx == r->size))
2876 while (next_cidx != pidx) {
2877 if (add_to_txpkts(r->items[next_cidx], &txp,
2880 tail->m_nextpkt = r->items[next_cidx];
2881 tail = tail->m_nextpkt;
2882 ETHER_BPF_MTAP(ifp, tail);
2883 if (__predict_false(++next_cidx == r->size))
2887 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2889 remaining -= txp.npkt;
2890 } else if (mbuf_cflags(m0) & MC_RAW_WR) {
2893 n = write_raw_wr(txq, (void *)wr, m0, available);
2897 ETHER_BPF_MTAP(ifp, m0);
2898 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2900 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2904 IDXINCR(eq->pidx, n, eq->sidx);
2906 if (wr_can_update_eq(wr)) {
2907 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2908 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2909 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2911 eq->equeqidx = eq->pidx;
2912 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >=
2914 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2915 eq->equeqidx = eq->pidx;
2919 if (dbdiff >= 16 && remaining >= 4) {
2920 ring_eq_db(sc, eq, dbdiff);
2921 available += reclaim_tx_descs(txq, 4 * dbdiff);
2928 ring_eq_db(sc, eq, dbdiff);
2929 reclaim_tx_descs(txq, 32);
2938 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2942 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2943 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2944 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2945 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2949 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2950 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2951 if (pktc_idx >= 0) {
2952 iq->intr_params |= F_QINTR_CNT_EN;
2953 iq->intr_pktc_idx = pktc_idx;
2955 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2956 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2960 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2964 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2965 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2966 if (sc->flags & BUF_PACKING_OK &&
2967 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2968 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2969 fl->flags |= FL_BUF_PACKING;
2970 find_best_refill_source(sc, fl, maxp);
2971 find_safe_refill_source(sc, fl);
2975 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2976 uint8_t tx_chan, uint16_t iqid, char *name)
2978 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2980 eq->flags = eqtype & EQ_TYPEMASK;
2981 eq->tx_chan = tx_chan;
2983 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2984 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2988 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2989 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2993 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2994 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2996 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
3000 rc = bus_dmamem_alloc(*tag, va,
3001 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3003 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
3007 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3009 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
3014 free_ring(sc, *tag, *map, *pa, *va);
3020 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3021 bus_addr_t pa, void *va)
3024 bus_dmamap_unload(tag, map);
3026 bus_dmamem_free(tag, va, map);
3028 bus_dma_tag_destroy(tag);
3034 * Allocates the ring for an ingress queue and an optional freelist. If the
3035 * freelist is specified it will be allocated and then associated with the
3038 * Returns errno on failure. Resources allocated up to that point may still be
3039 * allocated. Caller is responsible for cleanup in case this function fails.
3041 * If the ingress queue will take interrupts directly then the intr_idx
3042 * specifies the vector, starting from 0. -1 means the interrupts for this
3043 * queue should be forwarded to the fwq.
3046 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3047 int intr_idx, int cong)
3049 int rc, i, cntxt_id;
3052 struct port_info *pi = vi->pi;
3053 struct adapter *sc = iq->adapter;
3054 struct sge_params *sp = &sc->params.sge;
3057 len = iq->qsize * IQ_ESIZE;
3058 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3059 (void **)&iq->desc);
3063 bzero(&c, sizeof(c));
3064 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3065 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3066 V_FW_IQ_CMD_VFN(0));
3068 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3071 /* Special handling for firmware event queue */
3072 if (iq == &sc->sge.fwq)
3073 v |= F_FW_IQ_CMD_IQASYNCH;
3076 /* Forwarded interrupts, all headed to fwq */
3077 v |= F_FW_IQ_CMD_IQANDST;
3078 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3080 KASSERT(intr_idx < sc->intr_count,
3081 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
3082 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
3085 c.type_to_iqandstindex = htobe32(v |
3086 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3087 V_FW_IQ_CMD_VIID(vi->viid) |
3088 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3089 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3090 F_FW_IQ_CMD_IQGTSMODE |
3091 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3092 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3093 c.iqsize = htobe16(iq->qsize);
3094 c.iqaddr = htobe64(iq->ba);
3096 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3099 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3101 len = fl->qsize * EQ_ESIZE;
3102 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3103 &fl->ba, (void **)&fl->desc);
3107 /* Allocate space for one software descriptor per buffer. */
3108 rc = alloc_fl_sdesc(fl);
3110 device_printf(sc->dev,
3111 "failed to setup fl software descriptors: %d\n",
3116 if (fl->flags & FL_BUF_PACKING) {
3117 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3118 fl->buf_boundary = sp->pack_boundary;
3120 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3121 fl->buf_boundary = 16;
3123 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3124 fl->buf_boundary = sp->pad_boundary;
3126 c.iqns_to_fl0congen |=
3127 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3128 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3129 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3130 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3133 c.iqns_to_fl0congen |=
3134 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3135 F_FW_IQ_CMD_FL0CONGCIF |
3136 F_FW_IQ_CMD_FL0CONGEN);
3138 c.fl0dcaen_to_fl0cidxfthresh =
3139 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3140 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
3141 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3142 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3143 c.fl0size = htobe16(fl->qsize);
3144 c.fl0addr = htobe64(fl->ba);
3147 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3149 device_printf(sc->dev,
3150 "failed to create ingress queue: %d\n", rc);
3155 iq->gen = F_RSPD_GEN;
3156 iq->intr_next = iq->intr_params;
3157 iq->cntxt_id = be16toh(c.iqid);
3158 iq->abs_id = be16toh(c.physiqid);
3159 iq->flags |= IQ_ALLOCATED;
3161 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3162 if (cntxt_id >= sc->sge.niq) {
3163 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3164 cntxt_id, sc->sge.niq - 1);
3166 sc->sge.iqmap[cntxt_id] = iq;
3171 iq->flags |= IQ_HAS_FL;
3172 fl->cntxt_id = be16toh(c.fl0id);
3173 fl->pidx = fl->cidx = 0;
3175 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3176 if (cntxt_id >= sc->sge.neq) {
3177 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3178 __func__, cntxt_id, sc->sge.neq - 1);
3180 sc->sge.eqmap[cntxt_id] = (void *)fl;
3183 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3184 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3185 uint32_t mask = (1 << s_qpp) - 1;
3186 volatile uint8_t *udb;
3188 udb = sc->udbs_base + UDBS_DB_OFFSET;
3189 udb += (qid >> s_qpp) << PAGE_SHIFT;
3191 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3192 udb += qid << UDBS_SEG_SHIFT;
3195 fl->udb = (volatile void *)udb;
3197 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3200 /* Enough to make sure the SGE doesn't think it's starved */
3201 refill_fl(sc, fl, fl->lowat);
3205 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3206 uint32_t param, val;
3208 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3209 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3210 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3215 for (i = 0; i < 4; i++) {
3216 if (cong & (1 << i))
3217 val |= 1 << (i << 2);
3221 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3223 /* report error but carry on */
3224 device_printf(sc->dev,
3225 "failed to set congestion manager context for "
3226 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3230 /* Enable IQ interrupts */
3231 atomic_store_rel_int(&iq->state, IQS_IDLE);
3232 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3233 V_INGRESSQID(iq->cntxt_id));
3239 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3242 struct adapter *sc = iq->adapter;
3246 return (0); /* nothing to do */
3248 dev = vi ? vi->dev : sc->dev;
3250 if (iq->flags & IQ_ALLOCATED) {
3251 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3252 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3253 fl ? fl->cntxt_id : 0xffff, 0xffff);
3256 "failed to free queue %p: %d\n", iq, rc);
3259 iq->flags &= ~IQ_ALLOCATED;
3262 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3264 bzero(iq, sizeof(*iq));
3267 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3271 free_fl_sdesc(sc, fl);
3273 if (mtx_initialized(&fl->fl_lock))
3274 mtx_destroy(&fl->fl_lock);
3276 bzero(fl, sizeof(*fl));
3283 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3286 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3288 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3289 "bus address of descriptor ring");
3290 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3291 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3293 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I",
3294 "absolute id of the queue");
3295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3296 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I",
3297 "SGE context id of the queue");
3298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3299 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
3304 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3305 struct sysctl_oid *oid, struct sge_fl *fl)
3307 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3309 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3311 children = SYSCTL_CHILDREN(oid);
3313 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3314 &fl->ba, "bus address of descriptor ring");
3315 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3316 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3317 "desc ring size in bytes");
3318 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3319 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
3320 "SGE context id of the freelist");
3321 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3322 fl_pad ? 1 : 0, "padding enabled");
3323 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3324 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3325 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3326 0, "consumer index");
3327 if (fl->flags & FL_BUF_PACKING) {
3328 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3329 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3331 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3332 0, "producer index");
3333 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
3334 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
3335 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
3336 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
3337 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3338 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3339 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3340 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3341 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3342 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3346 alloc_fwq(struct adapter *sc)
3349 struct sge_iq *fwq = &sc->sge.fwq;
3350 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3351 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3353 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3354 if (sc->flags & IS_VF)
3357 intr_idx = sc->intr_count > 1 ? 1 : 0;
3358 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3360 device_printf(sc->dev,
3361 "failed to create firmware event queue: %d\n", rc);
3365 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
3366 NULL, "firmware event queue");
3367 add_iq_sysctls(&sc->ctx, oid, fwq);
3373 free_fwq(struct adapter *sc)
3375 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3379 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3380 struct sysctl_oid *oid)
3384 struct sysctl_oid_list *children;
3386 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3388 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3389 sc->sge.fwq.cntxt_id, name);
3391 children = SYSCTL_CHILDREN(oid);
3392 snprintf(name, sizeof(name), "%d", idx);
3393 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3394 NULL, "ctrl queue");
3395 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3401 tnl_cong(struct port_info *pi, int drop)
3409 return (pi->rx_e_chan_map);
3413 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3414 struct sysctl_oid *oid)
3417 struct adapter *sc = vi->pi->adapter;
3418 struct sysctl_oid_list *children;
3421 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3422 tnl_cong(vi->pi, cong_drop));
3427 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3429 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3430 ("iq_base mismatch"));
3431 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3432 ("PF with non-zero iq_base"));
3435 * The freelist is just barely above the starvation threshold right now,
3436 * fill it up a bit more.
3439 refill_fl(sc, &rxq->fl, 128);
3440 FL_UNLOCK(&rxq->fl);
3442 #if defined(INET) || defined(INET6)
3443 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3446 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3448 if (vi->ifp->if_capenable & IFCAP_LRO)
3449 rxq->iq.flags |= IQ_LRO_ENABLED;
3451 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP)
3452 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3455 children = SYSCTL_CHILDREN(oid);
3457 snprintf(name, sizeof(name), "%d", idx);
3458 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3460 children = SYSCTL_CHILDREN(oid);
3462 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3463 #if defined(INET) || defined(INET6)
3464 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3465 &rxq->lro.lro_queued, 0, NULL);
3466 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3467 &rxq->lro.lro_flushed, 0, NULL);
3469 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3470 &rxq->rxcsum, "# of times hardware assisted with checksum");
3471 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3472 CTLFLAG_RD, &rxq->vlan_extraction,
3473 "# of times hardware extracted 802.1Q tag");
3475 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3481 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3485 #if defined(INET) || defined(INET6)
3487 tcp_lro_free(&rxq->lro);
3488 rxq->lro.ifp = NULL;
3492 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3494 bzero(rxq, sizeof(*rxq));
3501 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3502 int intr_idx, int idx, struct sysctl_oid *oid)
3504 struct port_info *pi = vi->pi;
3506 struct sysctl_oid_list *children;
3509 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3513 children = SYSCTL_CHILDREN(oid);
3515 snprintf(name, sizeof(name), "%d", idx);
3516 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3518 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3519 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3525 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3529 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3531 bzero(ofld_rxq, sizeof(*ofld_rxq));
3539 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3540 int idx, struct sysctl_oid *oid)
3543 struct sysctl_oid_list *children;
3544 struct sysctl_ctx_list *ctx;
3547 struct adapter *sc = vi->pi->adapter;
3548 struct netmap_adapter *na = NA(vi->ifp);
3552 len = vi->qsize_rxq * IQ_ESIZE;
3553 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3554 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3558 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3559 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3560 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3566 nm_rxq->iq_cidx = 0;
3567 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3568 nm_rxq->iq_gen = F_RSPD_GEN;
3569 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3570 nm_rxq->fl_sidx = na->num_rx_desc;
3571 nm_rxq->intr_idx = intr_idx;
3572 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3575 children = SYSCTL_CHILDREN(oid);
3577 snprintf(name, sizeof(name), "%d", idx);
3578 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3580 children = SYSCTL_CHILDREN(oid);
3582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3583 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3584 "I", "absolute id of the queue");
3585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3586 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3587 "I", "SGE context id of the queue");
3588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3589 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3592 children = SYSCTL_CHILDREN(oid);
3593 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3595 children = SYSCTL_CHILDREN(oid);
3597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3598 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3599 "I", "SGE context id of the freelist");
3600 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3601 &nm_rxq->fl_cidx, 0, "consumer index");
3602 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3603 &nm_rxq->fl_pidx, 0, "producer index");
3610 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3612 struct adapter *sc = vi->pi->adapter;
3614 if (vi->flags & VI_INIT_DONE)
3615 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3617 MPASS(nm_rxq->iq_cntxt_id == 0);
3619 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3621 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3628 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3629 struct sysctl_oid *oid)
3633 struct port_info *pi = vi->pi;
3634 struct adapter *sc = pi->adapter;
3635 struct netmap_adapter *na = NA(vi->ifp);
3637 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3639 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3640 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3641 &nm_txq->ba, (void **)&nm_txq->desc);
3645 nm_txq->pidx = nm_txq->cidx = 0;
3646 nm_txq->sidx = na->num_tx_desc;
3648 nm_txq->iqidx = iqidx;
3649 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3650 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
3651 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
3652 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3654 snprintf(name, sizeof(name), "%d", idx);
3655 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3656 NULL, "netmap tx queue");
3657 children = SYSCTL_CHILDREN(oid);
3659 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3660 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3661 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3662 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3664 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3665 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3672 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3674 struct adapter *sc = vi->pi->adapter;
3676 if (vi->flags & VI_INIT_DONE)
3677 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3679 MPASS(nm_txq->cntxt_id == 0);
3681 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3689 * Returns a reasonable automatic cidx flush threshold for a given queue size.
3692 qsize_to_fthresh(int qsize)
3696 while (!powerof2(qsize))
3698 fthresh = ilog2(qsize);
3699 if (fthresh > X_CIDXFLUSHTHRESH_128)
3700 fthresh = X_CIDXFLUSHTHRESH_128;
3706 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3709 struct fw_eq_ctrl_cmd c;
3710 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3712 bzero(&c, sizeof(c));
3714 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3715 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3716 V_FW_EQ_CTRL_CMD_VFN(0));
3717 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3718 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3719 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3720 c.physeqid_pkd = htobe32(0);
3721 c.fetchszm_to_iqid =
3722 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3723 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3724 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3726 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3727 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3728 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3729 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3730 c.eqaddr = htobe64(eq->ba);
3732 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3734 device_printf(sc->dev,
3735 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3738 eq->flags |= EQ_ALLOCATED;
3740 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3741 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3742 if (cntxt_id >= sc->sge.neq)
3743 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3744 cntxt_id, sc->sge.neq - 1);
3745 sc->sge.eqmap[cntxt_id] = eq;
3751 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3754 struct fw_eq_eth_cmd c;
3755 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3757 bzero(&c, sizeof(c));
3759 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3760 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3761 V_FW_EQ_ETH_CMD_VFN(0));
3762 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3763 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3764 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3765 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3766 c.fetchszm_to_iqid =
3767 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3768 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3769 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3770 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3771 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3772 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3773 c.eqaddr = htobe64(eq->ba);
3775 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3777 device_printf(vi->dev,
3778 "failed to create Ethernet egress queue: %d\n", rc);
3781 eq->flags |= EQ_ALLOCATED;
3783 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3784 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3785 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3786 if (cntxt_id >= sc->sge.neq)
3787 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3788 cntxt_id, sc->sge.neq - 1);
3789 sc->sge.eqmap[cntxt_id] = eq;
3794 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3796 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3799 struct fw_eq_ofld_cmd c;
3800 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3802 bzero(&c, sizeof(c));
3804 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3805 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3806 V_FW_EQ_OFLD_CMD_VFN(0));
3807 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3808 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3809 c.fetchszm_to_iqid =
3810 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3811 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3812 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3814 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3815 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3816 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3817 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3818 c.eqaddr = htobe64(eq->ba);
3820 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3822 device_printf(vi->dev,
3823 "failed to create egress queue for TCP offload: %d\n", rc);
3826 eq->flags |= EQ_ALLOCATED;
3828 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3829 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3830 if (cntxt_id >= sc->sge.neq)
3831 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3832 cntxt_id, sc->sge.neq - 1);
3833 sc->sge.eqmap[cntxt_id] = eq;
3840 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3845 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3847 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3848 len = qsize * EQ_ESIZE;
3849 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3850 &eq->ba, (void **)&eq->desc);
3854 eq->pidx = eq->cidx = eq->dbidx = 0;
3855 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
3857 eq->doorbells = sc->doorbells;
3859 switch (eq->flags & EQ_TYPEMASK) {
3861 rc = ctrl_eq_alloc(sc, eq);
3865 rc = eth_eq_alloc(sc, vi, eq);
3868 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3870 rc = ofld_eq_alloc(sc, vi, eq);
3875 panic("%s: invalid eq type %d.", __func__,
3876 eq->flags & EQ_TYPEMASK);
3879 device_printf(sc->dev,
3880 "failed to allocate egress queue(%d): %d\n",
3881 eq->flags & EQ_TYPEMASK, rc);
3884 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3885 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3886 isset(&eq->doorbells, DOORBELL_WCWR)) {
3887 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3888 uint32_t mask = (1 << s_qpp) - 1;
3889 volatile uint8_t *udb;
3891 udb = sc->udbs_base + UDBS_DB_OFFSET;
3892 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3893 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3894 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3895 clrbit(&eq->doorbells, DOORBELL_WCWR);
3897 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3900 eq->udb = (volatile void *)udb;
3907 free_eq(struct adapter *sc, struct sge_eq *eq)
3911 if (eq->flags & EQ_ALLOCATED) {
3912 switch (eq->flags & EQ_TYPEMASK) {
3914 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3919 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3923 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3925 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3931 panic("%s: invalid eq type %d.", __func__,
3932 eq->flags & EQ_TYPEMASK);
3935 device_printf(sc->dev,
3936 "failed to free egress queue (%d): %d\n",
3937 eq->flags & EQ_TYPEMASK, rc);
3940 eq->flags &= ~EQ_ALLOCATED;
3943 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3945 if (mtx_initialized(&eq->eq_lock))
3946 mtx_destroy(&eq->eq_lock);
3948 bzero(eq, sizeof(*eq));
3953 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3954 struct sysctl_oid *oid)
3957 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3958 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3960 rc = alloc_eq(sc, vi, &wrq->eq);
3965 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3966 TAILQ_INIT(&wrq->incomplete_wrs);
3967 STAILQ_INIT(&wrq->wr_list);
3968 wrq->nwr_pending = 0;
3969 wrq->ndesc_needed = 0;
3971 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3972 &wrq->eq.ba, "bus address of descriptor ring");
3973 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3974 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3975 "desc ring size in bytes");
3976 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3977 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3978 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3979 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3982 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3984 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3985 wrq->eq.sidx, "status page index");
3986 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3987 &wrq->tx_wrs_direct, "# of work requests (direct)");
3988 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3989 &wrq->tx_wrs_copied, "# of work requests (copied)");
3990 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3991 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3997 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4001 rc = free_eq(sc, &wrq->eq);
4005 bzero(wrq, sizeof(*wrq));
4010 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
4011 struct sysctl_oid *oid)
4014 struct port_info *pi = vi->pi;
4015 struct adapter *sc = pi->adapter;
4016 struct sge_eq *eq = &txq->eq;
4018 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4020 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
4023 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
4027 rc = alloc_eq(sc, vi, eq);
4029 mp_ring_free(txq->r);
4034 /* Can't fail after this point. */
4037 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4039 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4040 ("eq_base mismatch"));
4041 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4042 ("PF with non-zero eq_base"));
4044 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4046 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4047 if (sc->flags & IS_VF)
4048 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4049 V_TXPKT_INTF(pi->tx_chan));
4051 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
4052 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4053 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4055 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4058 snprintf(name, sizeof(name), "%d", idx);
4059 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
4061 children = SYSCTL_CHILDREN(oid);
4063 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4064 &eq->ba, "bus address of descriptor ring");
4065 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4066 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4067 "desc ring size in bytes");
4068 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4069 &eq->abs_id, 0, "absolute id of the queue");
4070 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4071 &eq->cntxt_id, 0, "SGE context id of the queue");
4072 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
4073 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
4075 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
4076 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
4078 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4079 eq->sidx, "status page index");
4081 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
4082 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
4083 "traffic class (-1 means none)");
4085 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4086 &txq->txcsum, "# of times hardware assisted with checksum");
4087 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
4088 CTLFLAG_RD, &txq->vlan_insertion,
4089 "# of times hardware inserted 802.1Q tag");
4090 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4091 &txq->tso_wrs, "# of TSO work requests");
4092 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4093 &txq->imm_wrs, "# of work requests with immediate data");
4094 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4095 &txq->sgl_wrs, "# of work requests with direct SGL");
4096 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4097 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4098 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
4099 CTLFLAG_RD, &txq->txpkts0_wrs,
4100 "# of txpkts (type 0) work requests");
4101 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
4102 CTLFLAG_RD, &txq->txpkts1_wrs,
4103 "# of txpkts (type 1) work requests");
4104 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
4105 CTLFLAG_RD, &txq->txpkts0_pkts,
4106 "# of frames tx'd using type0 txpkts work requests");
4107 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
4108 CTLFLAG_RD, &txq->txpkts1_pkts,
4109 "# of frames tx'd using type1 txpkts work requests");
4110 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4111 &txq->raw_wrs, "# of raw work requests (non-packets)");
4113 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
4114 CTLFLAG_RD, &txq->r->enqueues,
4115 "# of enqueues to the mp_ring for this queue");
4116 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
4117 CTLFLAG_RD, &txq->r->drops,
4118 "# of drops in the mp_ring for this queue");
4119 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
4120 CTLFLAG_RD, &txq->r->starts,
4121 "# of normal consumer starts in the mp_ring for this queue");
4122 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
4123 CTLFLAG_RD, &txq->r->stalls,
4124 "# of consumer stalls in the mp_ring for this queue");
4125 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
4126 CTLFLAG_RD, &txq->r->restarts,
4127 "# of consumer restarts in the mp_ring for this queue");
4128 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
4129 CTLFLAG_RD, &txq->r->abdications,
4130 "# of consumer abdications in the mp_ring for this queue");
4136 free_txq(struct vi_info *vi, struct sge_txq *txq)
4139 struct adapter *sc = vi->pi->adapter;
4140 struct sge_eq *eq = &txq->eq;
4142 rc = free_eq(sc, eq);
4146 sglist_free(txq->gl);
4147 free(txq->sdesc, M_CXGBE);
4148 mp_ring_free(txq->r);
4150 bzero(txq, sizeof(*txq));
4155 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4157 bus_addr_t *ba = arg;
4160 ("%s meant for single segment mappings only.", __func__));
4162 *ba = error ? 0 : segs->ds_addr;
4166 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4170 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
4174 v = fl->dbval | V_PIDX(n);
4176 *fl->udb = htole32(v);
4178 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4179 IDXINCR(fl->dbidx, n, fl->sidx);
4183 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4184 * recycled do not count towards this allocation budget.
4186 * Returns non-zero to indicate that this freelist should be added to the list
4187 * of starving freelists.
4190 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4193 struct fl_sdesc *sd;
4196 struct cluster_layout *cll;
4197 struct sw_zone_info *swz;
4198 struct cluster_metadata *clm;
4200 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4202 FL_LOCK_ASSERT_OWNED(fl);
4205 * We always stop at the beginning of the hardware descriptor that's just
4206 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4207 * which would mean an empty freelist to the chip.
4209 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4210 if (fl->pidx == max_pidx * 8)
4213 d = &fl->desc[fl->pidx];
4214 sd = &fl->sdesc[fl->pidx];
4215 cll = &fl->cll_def; /* default layout */
4216 swz = &sc->sge.sw_zone_info[cll->zidx];
4220 if (sd->cl != NULL) {
4222 if (sd->nmbuf == 0) {
4224 * Fast recycle without involving any atomics on
4225 * the cluster's metadata (if the cluster has
4226 * metadata). This happens when all frames
4227 * received in the cluster were small enough to
4228 * fit within a single mbuf each.
4230 fl->cl_fast_recycled++;
4232 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4234 MPASS(clm->refcount == 1);
4240 * Cluster is guaranteed to have metadata. Clusters
4241 * without metadata always take the fast recycle path
4242 * when they're recycled.
4244 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4247 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4249 counter_u64_add(extfree_rels, 1);
4252 sd->cl = NULL; /* gave up my reference */
4254 MPASS(sd->cl == NULL);
4256 cl = uma_zalloc(swz->zone, M_NOWAIT);
4257 if (__predict_false(cl == NULL)) {
4258 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
4259 fl->cll_def.zidx == fl->cll_alt.zidx)
4262 /* fall back to the safe zone */
4264 swz = &sc->sge.sw_zone_info[cll->zidx];
4270 pa = pmap_kextract((vm_offset_t)cl);
4274 *d = htobe64(pa | cll->hwidx);
4275 clm = cl_metadata(sc, fl, cll, cl);
4287 if (__predict_false(++fl->pidx % 8 == 0)) {
4288 uint16_t pidx = fl->pidx / 8;
4290 if (__predict_false(pidx == fl->sidx)) {
4296 if (pidx == max_pidx)
4299 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4304 if (fl->pidx / 8 != fl->dbidx)
4307 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4311 * Attempt to refill all starving freelists.
4314 refill_sfl(void *arg)
4316 struct adapter *sc = arg;
4317 struct sge_fl *fl, *fl_temp;
4319 mtx_assert(&sc->sfl_lock, MA_OWNED);
4320 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4322 refill_fl(sc, fl, 64);
4323 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4324 TAILQ_REMOVE(&sc->sfl, fl, link);
4325 fl->flags &= ~FL_STARVING;
4330 if (!TAILQ_EMPTY(&sc->sfl))
4331 callout_schedule(&sc->sfl_callout, hz / 5);
4335 alloc_fl_sdesc(struct sge_fl *fl)
4338 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4345 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4347 struct fl_sdesc *sd;
4348 struct cluster_metadata *clm;
4349 struct cluster_layout *cll;
4353 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4358 clm = cl_metadata(sc, fl, cll, sd->cl);
4360 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4361 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4362 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4363 counter_u64_add(extfree_rels, 1);
4368 free(fl->sdesc, M_CXGBE);
4373 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4380 rc = sglist_append_mbuf(gl, m);
4381 if (__predict_false(rc != 0)) {
4382 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4383 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4386 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4387 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4388 mbuf_nsegs(m), gl->sg_nseg));
4389 KASSERT(gl->sg_nseg > 0 &&
4390 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4391 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4392 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4396 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4399 txpkt_len16(u_int nsegs, u_int tso)
4405 nsegs--; /* first segment is part of ulptx_sgl */
4406 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4407 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4409 n += sizeof(struct cpl_tx_pkt_lso_core);
4411 return (howmany(n, 16));
4415 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4419 txpkt_vm_len16(u_int nsegs, u_int tso)
4425 nsegs--; /* first segment is part of ulptx_sgl */
4426 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4427 sizeof(struct cpl_tx_pkt_core) +
4428 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4430 n += sizeof(struct cpl_tx_pkt_lso_core);
4432 return (howmany(n, 16));
4436 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4440 txpkts0_len16(u_int nsegs)
4446 nsegs--; /* first segment is part of ulptx_sgl */
4447 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4448 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4449 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4451 return (howmany(n, 16));
4455 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4463 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4465 return (howmany(n, 16));
4469 imm_payload(u_int ndesc)
4473 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4474 sizeof(struct cpl_tx_pkt_core);
4480 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4481 * software descriptor, and advance the pidx. It is guaranteed that enough
4482 * descriptors are available.
4484 * The return value is the # of hardware descriptors used.
4487 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4488 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4490 struct sge_eq *eq = &txq->eq;
4491 struct tx_sdesc *txsd;
4492 struct cpl_tx_pkt_core *cpl;
4493 uint32_t ctrl; /* used in many unrelated places */
4495 int csum_type, len16, ndesc, pktlen, nsegs;
4498 TXQ_LOCK_ASSERT_OWNED(txq);
4500 MPASS(available > 0 && available < eq->sidx);
4502 len16 = mbuf_len16(m0);
4503 nsegs = mbuf_nsegs(m0);
4504 pktlen = m0->m_pkthdr.len;
4505 ctrl = sizeof(struct cpl_tx_pkt_core);
4507 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4508 ndesc = howmany(len16, EQ_ESIZE / 16);
4509 MPASS(ndesc <= available);
4511 /* Firmware work request header */
4512 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4513 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4514 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4516 ctrl = V_FW_WR_LEN16(len16);
4517 wr->equiq_to_len16 = htobe32(ctrl);
4522 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4523 * vlantci is ignored unless the ethtype is 0x8100, so it's
4524 * simpler to always copy it rather than making it
4525 * conditional. Also, it seems that we do not have to set
4526 * vlantci or fake the ethtype when doing VLAN tag insertion.
4528 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4531 if (needs_tso(m0)) {
4532 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4534 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4535 m0->m_pkthdr.l4hlen > 0,
4536 ("%s: mbuf %p needs TSO but missing header lengths",
4539 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4540 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4541 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4542 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4543 ctrl |= V_LSO_ETHHDR_LEN(1);
4544 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4547 lso->lso_ctrl = htobe32(ctrl);
4548 lso->ipid_ofst = htobe16(0);
4549 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4550 lso->seqno_offset = htobe32(0);
4551 lso->len = htobe32(pktlen);
4553 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4554 csum_type = TX_CSUM_TCPIP6;
4556 csum_type = TX_CSUM_TCPIP;
4558 cpl = (void *)(lso + 1);
4562 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4563 csum_type = TX_CSUM_TCPIP;
4564 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4565 csum_type = TX_CSUM_UDPIP;
4566 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4567 csum_type = TX_CSUM_TCPIP6;
4568 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4569 csum_type = TX_CSUM_UDPIP6;
4571 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4573 * XXX: The firmware appears to stomp on the
4574 * fragment/flags field of the IP header when
4575 * using TX_CSUM_IP. Fall back to doing
4576 * software checksums.
4584 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4585 offsetof(struct ip, ip_sum));
4586 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4587 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4588 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4592 cpl = (void *)(wr + 1);
4595 /* Checksum offload */
4597 if (needs_l3_csum(m0) == 0)
4598 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4599 if (csum_type >= 0) {
4600 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4601 ("%s: mbuf %p needs checksum offload but missing header lengths",
4604 if (chip_id(sc) <= CHELSIO_T5) {
4605 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4608 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4611 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4612 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4614 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4615 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4616 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4617 txq->txcsum++; /* some hardware assistance provided */
4619 /* VLAN tag insertion */
4620 if (needs_vlan_insertion(m0)) {
4621 ctrl1 |= F_TXPKT_VLAN_VLD |
4622 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4623 txq->vlan_insertion++;
4627 cpl->ctrl0 = txq->cpl_ctrl0;
4629 cpl->len = htobe16(pktlen);
4630 cpl->ctrl1 = htobe64(ctrl1);
4633 dst = (void *)(cpl + 1);
4636 * A packet using TSO will use up an entire descriptor for the
4637 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4638 * If this descriptor is the last descriptor in the ring, wrap
4639 * around to the front of the ring explicitly for the start of
4642 if (dst == (void *)&eq->desc[eq->sidx]) {
4643 dst = (void *)&eq->desc[0];
4644 write_gl_to_txd(txq, m0, &dst, 0);
4646 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4651 txsd = &txq->sdesc[eq->pidx];
4653 txsd->desc_used = ndesc;
4659 * Write a raw WR to the hardware descriptors, update the software
4660 * descriptor, and advance the pidx. It is guaranteed that enough
4661 * descriptors are available.
4663 * The return value is the # of hardware descriptors used.
4666 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
4668 struct sge_eq *eq = &txq->eq;
4669 struct tx_sdesc *txsd;
4674 len16 = mbuf_len16(m0);
4675 ndesc = howmany(len16, EQ_ESIZE / 16);
4676 MPASS(ndesc <= available);
4679 for (m = m0; m != NULL; m = m->m_next)
4680 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4684 txsd = &txq->sdesc[eq->pidx];
4686 txsd->desc_used = ndesc;
4692 * Write a txpkt WR for this packet to the hardware descriptors, update the
4693 * software descriptor, and advance the pidx. It is guaranteed that enough
4694 * descriptors are available.
4696 * The return value is the # of hardware descriptors used.
4699 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4700 struct mbuf *m0, u_int available)
4702 struct sge_eq *eq = &txq->eq;
4703 struct tx_sdesc *txsd;
4704 struct cpl_tx_pkt_core *cpl;
4705 uint32_t ctrl; /* used in many unrelated places */
4707 int len16, ndesc, pktlen, nsegs;
4710 TXQ_LOCK_ASSERT_OWNED(txq);
4712 MPASS(available > 0 && available < eq->sidx);
4714 len16 = mbuf_len16(m0);
4715 nsegs = mbuf_nsegs(m0);
4716 pktlen = m0->m_pkthdr.len;
4717 ctrl = sizeof(struct cpl_tx_pkt_core);
4719 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4720 else if (pktlen <= imm_payload(2) && available >= 2) {
4721 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4723 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4724 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4727 ndesc = howmany(len16, EQ_ESIZE / 16);
4728 MPASS(ndesc <= available);
4730 /* Firmware work request header */
4731 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4732 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4733 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4735 ctrl = V_FW_WR_LEN16(len16);
4736 wr->equiq_to_len16 = htobe32(ctrl);
4739 if (needs_tso(m0)) {
4740 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4742 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4743 m0->m_pkthdr.l4hlen > 0,
4744 ("%s: mbuf %p needs TSO but missing header lengths",
4747 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4748 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4749 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4750 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4751 ctrl |= V_LSO_ETHHDR_LEN(1);
4752 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4755 lso->lso_ctrl = htobe32(ctrl);
4756 lso->ipid_ofst = htobe16(0);
4757 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4758 lso->seqno_offset = htobe32(0);
4759 lso->len = htobe32(pktlen);
4761 cpl = (void *)(lso + 1);
4765 cpl = (void *)(wr + 1);
4767 /* Checksum offload */
4769 if (needs_l3_csum(m0) == 0)
4770 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4771 if (needs_l4_csum(m0) == 0)
4772 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4773 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4774 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4775 txq->txcsum++; /* some hardware assistance provided */
4777 /* VLAN tag insertion */
4778 if (needs_vlan_insertion(m0)) {
4779 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4780 txq->vlan_insertion++;
4784 cpl->ctrl0 = txq->cpl_ctrl0;
4786 cpl->len = htobe16(pktlen);
4787 cpl->ctrl1 = htobe64(ctrl1);
4790 dst = (void *)(cpl + 1);
4793 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4798 for (m = m0; m != NULL; m = m->m_next) {
4799 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4805 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4812 txsd = &txq->sdesc[eq->pidx];
4814 txsd->desc_used = ndesc;
4820 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4822 u_int needed, nsegs1, nsegs2, l1, l2;
4824 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4827 nsegs1 = mbuf_nsegs(m);
4828 nsegs2 = mbuf_nsegs(n);
4829 if (nsegs1 + nsegs2 == 2) {
4831 l1 = l2 = txpkts1_len16();
4834 l1 = txpkts0_len16(nsegs1);
4835 l2 = txpkts0_len16(nsegs2);
4837 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4838 needed = howmany(txp->len16, EQ_ESIZE / 16);
4839 if (needed > SGE_MAX_WR_NDESC || needed > available)
4842 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4843 if (txp->plen > 65535)
4847 set_mbuf_len16(m, l1);
4848 set_mbuf_len16(n, l2);
4854 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4856 u_int plen, len16, needed, nsegs;
4858 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4860 if (cannot_use_txpkts(m))
4863 nsegs = mbuf_nsegs(m);
4864 if (txp->wr_type == 1 && nsegs != 1)
4867 plen = txp->plen + m->m_pkthdr.len;
4871 if (txp->wr_type == 0)
4872 len16 = txpkts0_len16(nsegs);
4874 len16 = txpkts1_len16();
4875 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4876 if (needed > SGE_MAX_WR_NDESC || needed > available)
4881 txp->len16 += len16;
4882 set_mbuf_len16(m, len16);
4888 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4889 * the software descriptor, and advance the pidx. It is guaranteed that enough
4890 * descriptors are available.
4892 * The return value is the # of hardware descriptors used.
4895 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4896 struct mbuf *m0, const struct txpkts *txp, u_int available)
4898 struct sge_eq *eq = &txq->eq;
4899 struct tx_sdesc *txsd;
4900 struct cpl_tx_pkt_core *cpl;
4903 int ndesc, checkwrap;
4907 TXQ_LOCK_ASSERT_OWNED(txq);
4908 MPASS(txp->npkt > 0);
4909 MPASS(txp->plen < 65536);
4911 MPASS(m0->m_nextpkt != NULL);
4912 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4913 MPASS(available > 0 && available < eq->sidx);
4915 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4916 MPASS(ndesc <= available);
4918 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4919 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4920 ctrl = V_FW_WR_LEN16(txp->len16);
4921 wr->equiq_to_len16 = htobe32(ctrl);
4922 wr->plen = htobe16(txp->plen);
4923 wr->npkt = txp->npkt;
4925 wr->type = txp->wr_type;
4929 * At this point we are 16B into a hardware descriptor. If checkwrap is
4930 * set then we know the WR is going to wrap around somewhere. We'll
4931 * check for that at appropriate points.
4933 checkwrap = eq->sidx - ndesc < eq->pidx;
4934 for (m = m0; m != NULL; m = m->m_nextpkt) {
4935 if (txp->wr_type == 0) {
4936 struct ulp_txpkt *ulpmc;
4937 struct ulptx_idata *ulpsc;
4939 /* ULP master command */
4941 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4942 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4943 ulpmc->len = htobe32(mbuf_len16(m));
4945 /* ULP subcommand */
4946 ulpsc = (void *)(ulpmc + 1);
4947 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4949 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4951 cpl = (void *)(ulpsc + 1);
4953 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4954 cpl = (void *)&eq->desc[0];
4959 /* Checksum offload */
4961 if (needs_l3_csum(m) == 0)
4962 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4963 if (needs_l4_csum(m) == 0)
4964 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4965 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4966 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4967 txq->txcsum++; /* some hardware assistance provided */
4969 /* VLAN tag insertion */
4970 if (needs_vlan_insertion(m)) {
4971 ctrl1 |= F_TXPKT_VLAN_VLD |
4972 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4973 txq->vlan_insertion++;
4977 cpl->ctrl0 = txq->cpl_ctrl0;
4979 cpl->len = htobe16(m->m_pkthdr.len);
4980 cpl->ctrl1 = htobe64(ctrl1);
4984 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4985 flitp = (void *)&eq->desc[0];
4987 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4991 if (txp->wr_type == 0) {
4992 txq->txpkts0_pkts += txp->npkt;
4995 txq->txpkts1_pkts += txp->npkt;
4999 txsd = &txq->sdesc[eq->pidx];
5001 txsd->desc_used = ndesc;
5007 * If the SGL ends on an address that is not 16 byte aligned, this function will
5008 * add a 0 filled flit at the end.
5011 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5013 struct sge_eq *eq = &txq->eq;
5014 struct sglist *gl = txq->gl;
5015 struct sglist_seg *seg;
5016 __be64 *flitp, *wrap;
5017 struct ulptx_sgl *usgl;
5018 int i, nflits, nsegs;
5020 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5021 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5022 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5023 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5026 nsegs = gl->sg_nseg;
5029 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5030 flitp = (__be64 *)(*to);
5031 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5032 seg = &gl->sg_segs[0];
5033 usgl = (void *)flitp;
5036 * We start at a 16 byte boundary somewhere inside the tx descriptor
5037 * ring, so we're at least 16 bytes away from the status page. There is
5038 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5041 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5042 V_ULPTX_NSGE(nsegs));
5043 usgl->len0 = htobe32(seg->ss_len);
5044 usgl->addr0 = htobe64(seg->ss_paddr);
5047 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5049 /* Won't wrap around at all */
5051 for (i = 0; i < nsegs - 1; i++, seg++) {
5052 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5053 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5056 usgl->sge[i / 2].len[1] = htobe32(0);
5060 /* Will wrap somewhere in the rest of the SGL */
5062 /* 2 flits already written, write the rest flit by flit */
5063 flitp = (void *)(usgl + 1);
5064 for (i = 0; i < nflits - 2; i++) {
5066 flitp = (void *)eq->desc;
5067 *flitp++ = get_flit(seg, nsegs - 1, i);
5072 MPASS(((uintptr_t)flitp) & 0xf);
5076 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5077 if (__predict_false(flitp == wrap))
5078 *to = (void *)eq->desc;
5080 *to = (void *)flitp;
5084 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5087 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5088 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5090 if (__predict_true((uintptr_t)(*to) + len <=
5091 (uintptr_t)&eq->desc[eq->sidx])) {
5092 bcopy(from, *to, len);
5095 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5097 bcopy(from, *to, portion);
5099 portion = len - portion; /* remaining */
5100 bcopy(from, (void *)eq->desc, portion);
5101 (*to) = (caddr_t)eq->desc + portion;
5106 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
5114 clrbit(&db, DOORBELL_WCWR);
5117 switch (ffs(db) - 1) {
5119 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5122 case DOORBELL_WCWR: {
5123 volatile uint64_t *dst, *src;
5127 * Queues whose 128B doorbell segment fits in the page do not
5128 * use relative qid (udb_qid is always 0). Only queues with
5129 * doorbell segments can do WCWR.
5131 KASSERT(eq->udb_qid == 0 && n == 1,
5132 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
5133 __func__, eq->doorbells, n, eq->dbidx, eq));
5135 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
5138 src = (void *)&eq->desc[i];
5139 while (src != (void *)&eq->desc[i + 1])
5145 case DOORBELL_UDBWC:
5146 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5151 t4_write_reg(sc, sc->sge_kdoorbell_reg,
5152 V_QID(eq->cntxt_id) | V_PIDX(n));
5156 IDXINCR(eq->dbidx, n, eq->sidx);
5160 reclaimable_tx_desc(struct sge_eq *eq)
5164 hw_cidx = read_hw_cidx(eq);
5165 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5169 total_available_tx_desc(struct sge_eq *eq)
5171 uint16_t hw_cidx, pidx;
5173 hw_cidx = read_hw_cidx(eq);
5176 if (pidx == hw_cidx)
5177 return (eq->sidx - 1);
5179 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5182 static inline uint16_t
5183 read_hw_cidx(struct sge_eq *eq)
5185 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5186 uint16_t cidx = spg->cidx; /* stable snapshot */
5188 return (be16toh(cidx));
5192 * Reclaim 'n' descriptors approximately.
5195 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5197 struct tx_sdesc *txsd;
5198 struct sge_eq *eq = &txq->eq;
5199 u_int can_reclaim, reclaimed;
5201 TXQ_LOCK_ASSERT_OWNED(txq);
5205 can_reclaim = reclaimable_tx_desc(eq);
5206 while (can_reclaim && reclaimed < n) {
5208 struct mbuf *m, *nextpkt;
5210 txsd = &txq->sdesc[eq->cidx];
5211 ndesc = txsd->desc_used;
5213 /* Firmware doesn't return "partial" credits. */
5214 KASSERT(can_reclaim >= ndesc,
5215 ("%s: unexpected number of credits: %d, %d",
5216 __func__, can_reclaim, ndesc));
5218 ("%s: descriptor with no credits: cidx %d",
5219 __func__, eq->cidx));
5221 for (m = txsd->m; m != NULL; m = nextpkt) {
5222 nextpkt = m->m_nextpkt;
5223 m->m_nextpkt = NULL;
5227 can_reclaim -= ndesc;
5228 IDXINCR(eq->cidx, ndesc, eq->sidx);
5235 tx_reclaim(void *arg, int n)
5237 struct sge_txq *txq = arg;
5238 struct sge_eq *eq = &txq->eq;
5241 if (TXQ_TRYLOCK(txq) == 0)
5243 n = reclaim_tx_descs(txq, 32);
5244 if (eq->cidx == eq->pidx)
5245 eq->equeqidx = eq->pidx;
5251 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5253 int i = (idx / 3) * 2;
5259 rc = (uint64_t)segs[i].ss_len << 32;
5261 rc |= (uint64_t)(segs[i + 1].ss_len);
5263 return (htobe64(rc));
5266 return (htobe64(segs[i].ss_paddr));
5268 return (htobe64(segs[i + 1].ss_paddr));
5275 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
5277 int8_t zidx, hwidx, idx;
5278 uint16_t region1, region3;
5279 int spare, spare_needed, n;
5280 struct sw_zone_info *swz;
5281 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
5284 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
5285 * large enough for the max payload and cluster metadata. Otherwise
5286 * settle for the largest bufsize that leaves enough room in the cluster
5289 * Without buffer packing: Look for the smallest zone which has a
5290 * bufsize large enough for the max payload. Settle for the largest
5291 * bufsize available if there's nothing big enough for max payload.
5293 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
5294 swz = &sc->sge.sw_zone_info[0];
5296 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
5297 if (swz->size > largest_rx_cluster) {
5298 if (__predict_true(hwidx != -1))
5302 * This is a misconfiguration. largest_rx_cluster is
5303 * preventing us from finding a refill source. See
5304 * dev.t5nex.<n>.buffer_sizes to figure out why.
5306 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
5307 " refill source for fl %p (dma %u). Ignored.\n",
5308 largest_rx_cluster, fl, maxp);
5310 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
5311 hwb = &hwb_list[idx];
5312 spare = swz->size - hwb->size;
5313 if (spare < spare_needed)
5316 hwidx = idx; /* best option so far */
5317 if (hwb->size >= maxp) {
5319 if ((fl->flags & FL_BUF_PACKING) == 0)
5320 goto done; /* stop looking (not packing) */
5322 if (swz->size >= safest_rx_cluster)
5323 goto done; /* stop looking (packing) */
5325 break; /* keep looking, next zone */
5329 /* A usable hwidx has been located. */
5331 hwb = &hwb_list[hwidx];
5333 swz = &sc->sge.sw_zone_info[zidx];
5335 region3 = swz->size - hwb->size;
5338 * Stay within this zone and see if there is a better match when mbuf
5339 * inlining is allowed. Remember that the hwidx's are sorted in
5340 * decreasing order of size (so in increasing order of spare area).
5342 for (idx = hwidx; idx != -1; idx = hwb->next) {
5343 hwb = &hwb_list[idx];
5344 spare = swz->size - hwb->size;
5346 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
5350 * Do not inline mbufs if doing so would violate the pad/pack
5351 * boundary alignment requirement.
5353 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
5355 if (fl->flags & FL_BUF_PACKING &&
5356 (MSIZE % sc->params.sge.pack_boundary) != 0)
5359 if (spare < CL_METADATA_SIZE + MSIZE)
5361 n = (spare - CL_METADATA_SIZE) / MSIZE;
5362 if (n > howmany(hwb->size, maxp))
5366 if (fl->flags & FL_BUF_PACKING) {
5367 region1 = n * MSIZE;
5368 region3 = spare - region1;
5371 region3 = spare - region1;
5376 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
5377 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
5378 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
5379 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
5380 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
5381 sc->sge.sw_zone_info[zidx].size,
5382 ("%s: bad buffer layout for fl %p, maxp %d. "
5383 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5384 sc->sge.sw_zone_info[zidx].size, region1,
5385 sc->sge.hw_buf_info[hwidx].size, region3));
5386 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
5387 KASSERT(region3 >= CL_METADATA_SIZE,
5388 ("%s: no room for metadata. fl %p, maxp %d; "
5389 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5390 sc->sge.sw_zone_info[zidx].size, region1,
5391 sc->sge.hw_buf_info[hwidx].size, region3));
5392 KASSERT(region1 % MSIZE == 0,
5393 ("%s: bad mbuf region for fl %p, maxp %d. "
5394 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5395 sc->sge.sw_zone_info[zidx].size, region1,
5396 sc->sge.hw_buf_info[hwidx].size, region3));
5399 fl->cll_def.zidx = zidx;
5400 fl->cll_def.hwidx = hwidx;
5401 fl->cll_def.region1 = region1;
5402 fl->cll_def.region3 = region3;
5406 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
5408 struct sge *s = &sc->sge;
5409 struct hw_buf_info *hwb;
5410 struct sw_zone_info *swz;
5414 if (fl->flags & FL_BUF_PACKING)
5415 hwidx = s->safe_hwidx2; /* with room for metadata */
5416 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
5417 hwidx = s->safe_hwidx2;
5418 hwb = &s->hw_buf_info[hwidx];
5419 swz = &s->sw_zone_info[hwb->zidx];
5420 spare = swz->size - hwb->size;
5422 /* no good if there isn't room for an mbuf as well */
5423 if (spare < CL_METADATA_SIZE + MSIZE)
5424 hwidx = s->safe_hwidx1;
5426 hwidx = s->safe_hwidx1;
5429 /* No fallback source */
5430 fl->cll_alt.hwidx = -1;
5431 fl->cll_alt.zidx = -1;
5436 hwb = &s->hw_buf_info[hwidx];
5437 swz = &s->sw_zone_info[hwb->zidx];
5438 spare = swz->size - hwb->size;
5439 fl->cll_alt.hwidx = hwidx;
5440 fl->cll_alt.zidx = hwb->zidx;
5441 if (allow_mbufs_in_cluster &&
5442 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5443 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5445 fl->cll_alt.region1 = 0;
5446 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5450 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5452 mtx_lock(&sc->sfl_lock);
5454 if ((fl->flags & FL_DOOMED) == 0) {
5455 fl->flags |= FL_STARVING;
5456 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5457 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5460 mtx_unlock(&sc->sfl_lock);
5464 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5466 struct sge_wrq *wrq = (void *)eq;
5468 atomic_readandclear_int(&eq->equiq);
5469 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5473 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5475 struct sge_txq *txq = (void *)eq;
5477 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5479 atomic_readandclear_int(&eq->equiq);
5480 mp_ring_check_drainage(txq->r, 0);
5481 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5485 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5488 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5489 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5490 struct adapter *sc = iq->adapter;
5491 struct sge *s = &sc->sge;
5493 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5494 &handle_wrq_egr_update, &handle_eth_egr_update,
5495 &handle_wrq_egr_update};
5497 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5500 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5501 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5506 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5507 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5508 offsetof(struct cpl_fw6_msg, data));
5511 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5513 struct adapter *sc = iq->adapter;
5514 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5516 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5519 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5520 const struct rss_header *rss2;
5522 rss2 = (const struct rss_header *)&cpl->data[0];
5523 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5526 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5530 * t4_handle_wrerr_rpl - process a FW work request error message
5531 * @adap: the adapter
5532 * @rpl: start of the FW message
5535 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5537 u8 opcode = *(const u8 *)rpl;
5538 const struct fw_error_cmd *e = (const void *)rpl;
5541 if (opcode != FW_ERROR_CMD) {
5543 "%s: Received WRERR_RPL message with opcode %#x\n",
5544 device_get_nameunit(adap->dev), opcode);
5547 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5548 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5550 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5551 case FW_ERROR_TYPE_EXCEPTION:
5552 log(LOG_ERR, "exception info:\n");
5553 for (i = 0; i < nitems(e->u.exception.info); i++)
5554 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5555 be32toh(e->u.exception.info[i]));
5558 case FW_ERROR_TYPE_HWMODULE:
5559 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5560 be32toh(e->u.hwmodule.regaddr),
5561 be32toh(e->u.hwmodule.regval));
5563 case FW_ERROR_TYPE_WR:
5564 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5565 be16toh(e->u.wr.cidx),
5566 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5567 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5568 be32toh(e->u.wr.eqid));
5569 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5570 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5574 case FW_ERROR_TYPE_ACL:
5575 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5576 be16toh(e->u.acl.cidx),
5577 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5578 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5579 be32toh(e->u.acl.eqid),
5580 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5582 for (i = 0; i < nitems(e->u.acl.val); i++)
5583 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5587 log(LOG_ERR, "type %#x\n",
5588 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5595 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5597 uint16_t *id = arg1;
5600 return sysctl_handle_int(oidp, &i, 0, req);
5604 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5606 struct sge *s = arg1;
5607 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5608 struct sw_zone_info *swz = &s->sw_zone_info[0];
5613 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5614 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5615 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5620 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5624 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5631 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5634 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
5640 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
5641 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
5642 if (__predict_false(nsegs == 0))
5645 nsegs--; /* first segment is part of ulptx_sgl */
5646 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5648 n += sizeof(struct cpl_tx_pkt_lso_core);
5651 return (howmany(n, 16));
5654 #define ETID_FLOWC_NPARAMS 6
5655 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
5656 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
5657 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
5660 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi,
5663 struct wrq_cookie cookie;
5664 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
5665 struct fw_flowc_wr *flowc;
5667 mtx_assert(&cst->lock, MA_OWNED);
5668 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
5671 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
5672 if (__predict_false(flowc == NULL))
5675 bzero(flowc, ETID_FLOWC_LEN);
5676 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5677 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
5678 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
5679 V_FW_WR_FLOWID(cst->etid));
5680 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
5681 flowc->mnemval[0].val = htobe32(pfvf);
5682 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
5683 flowc->mnemval[1].val = htobe32(pi->tx_chan);
5684 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
5685 flowc->mnemval[2].val = htobe32(pi->tx_chan);
5686 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
5687 flowc->mnemval[3].val = htobe32(cst->iqid);
5688 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
5689 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
5690 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
5691 flowc->mnemval[5].val = htobe32(cst->schedcl);
5693 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5695 cst->flags &= ~EO_FLOWC_PENDING;
5696 cst->flags |= EO_FLOWC_RPL_PENDING;
5697 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
5698 cst->tx_credits -= ETID_FLOWC_LEN16;
5703 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
5706 send_etid_flush_wr(struct cxgbe_snd_tag *cst)
5708 struct fw_flowc_wr *flowc;
5709 struct wrq_cookie cookie;
5711 mtx_assert(&cst->lock, MA_OWNED);
5713 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
5714 if (__predict_false(flowc == NULL))
5715 CXGBE_UNIMPLEMENTED(__func__);
5717 bzero(flowc, ETID_FLUSH_LEN16 * 16);
5718 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5719 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
5720 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
5721 V_FW_WR_FLOWID(cst->etid));
5723 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5725 cst->flags |= EO_FLUSH_RPL_PENDING;
5726 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
5727 cst->tx_credits -= ETID_FLUSH_LEN16;
5732 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr,
5733 struct mbuf *m0, int compl)
5735 struct cpl_tx_pkt_core *cpl;
5737 uint32_t ctrl; /* used in many unrelated places */
5738 int len16, pktlen, nsegs, immhdrs;
5741 struct ulptx_sgl *usgl;
5743 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
5745 mtx_assert(&cst->lock, MA_OWNED);
5747 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5748 m0->m_pkthdr.l4hlen > 0,
5749 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
5751 len16 = mbuf_eo_len16(m0);
5752 nsegs = mbuf_eo_nsegs(m0);
5753 pktlen = m0->m_pkthdr.len;
5754 ctrl = sizeof(struct cpl_tx_pkt_core);
5756 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5757 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
5760 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
5761 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
5762 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
5763 V_FW_WR_FLOWID(cst->etid));
5765 if (needs_udp_csum(m0)) {
5766 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
5767 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
5768 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5769 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
5770 wr->u.udpseg.rtplen = 0;
5771 wr->u.udpseg.r4 = 0;
5772 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
5773 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
5774 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
5775 cpl = (void *)(wr + 1);
5777 MPASS(needs_tcp_csum(m0));
5778 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
5779 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
5780 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5781 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
5782 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
5783 wr->u.tcpseg.r4 = 0;
5784 wr->u.tcpseg.r5 = 0;
5785 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
5787 if (needs_tso(m0)) {
5788 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
5790 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
5792 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5793 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5794 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5795 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5796 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
5797 ctrl |= V_LSO_ETHHDR_LEN(1);
5798 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5800 lso->lso_ctrl = htobe32(ctrl);
5801 lso->ipid_ofst = htobe16(0);
5802 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5803 lso->seqno_offset = htobe32(0);
5804 lso->len = htobe32(pktlen);
5806 cpl = (void *)(lso + 1);
5808 wr->u.tcpseg.mss = htobe16(0xffff);
5809 cpl = (void *)(wr + 1);
5813 /* Checksum offload must be requested for ethofld. */
5815 MPASS(needs_l4_csum(m0));
5817 /* VLAN tag insertion */
5818 if (needs_vlan_insertion(m0)) {
5819 ctrl1 |= F_TXPKT_VLAN_VLD |
5820 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5824 cpl->ctrl0 = cst->ctrl0;
5826 cpl->len = htobe16(pktlen);
5827 cpl->ctrl1 = htobe64(ctrl1);
5829 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
5830 p = (uintptr_t)(cpl + 1);
5831 m_copydata(m0, 0, immhdrs, (void *)p);
5834 dst = (void *)(cpl + 1);
5838 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
5840 pad = 16 - (immhdrs & 0xf);
5841 bzero((void *)p, pad);
5843 usgl = (void *)(p + pad);
5844 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5845 V_ULPTX_NSGE(nsegs));
5847 sglist_init(&sg, nitems(segs), segs);
5848 for (; m0 != NULL; m0 = m0->m_next) {
5849 if (__predict_false(m0->m_len == 0))
5851 if (immhdrs >= m0->m_len) {
5852 immhdrs -= m0->m_len;
5856 sglist_append(&sg, mtod(m0, char *) + immhdrs,
5857 m0->m_len - immhdrs);
5860 MPASS(sg.sg_nseg == nsegs);
5863 * Zero pad last 8B in case the WR doesn't end on a 16B
5866 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
5868 usgl->len0 = htobe32(segs[0].ss_len);
5869 usgl->addr0 = htobe64(segs[0].ss_paddr);
5870 for (i = 0; i < nsegs - 1; i++) {
5871 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
5872 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
5875 usgl->sge[i / 2].len[1] = htobe32(0);
5881 ethofld_tx(struct cxgbe_snd_tag *cst)
5884 struct wrq_cookie cookie;
5885 int next_credits, compl;
5886 struct fw_eth_tx_eo_wr *wr;
5888 mtx_assert(&cst->lock, MA_OWNED);
5890 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
5893 /* How many len16 credits do we need to send this mbuf. */
5894 next_credits = mbuf_eo_len16(m);
5895 MPASS(next_credits > 0);
5896 if (next_credits > cst->tx_credits) {
5898 * Tx will make progress eventually because there is at
5899 * least one outstanding fw4_ack that will return
5900 * credits and kick the tx.
5902 MPASS(cst->ncompl > 0);
5905 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
5906 if (__predict_false(wr == NULL)) {
5907 /* XXX: wishful thinking, not a real assertion. */
5908 MPASS(cst->ncompl > 0);
5911 cst->tx_credits -= next_credits;
5912 cst->tx_nocompl += next_credits;
5913 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
5914 ETHER_BPF_MTAP(cst->com.ifp, m);
5915 write_ethofld_wr(cst, wr, m, compl);
5916 commit_wrq_wr(cst->eo_txq, wr, &cookie);
5919 cst->tx_nocompl = 0;
5921 (void) mbufq_dequeue(&cst->pending_tx);
5922 mbufq_enqueue(&cst->pending_fwack, m);
5927 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
5929 struct cxgbe_snd_tag *cst;
5932 MPASS(m0->m_nextpkt == NULL);
5933 MPASS(m0->m_pkthdr.snd_tag != NULL);
5934 cst = mst_to_cst(m0->m_pkthdr.snd_tag);
5936 mtx_lock(&cst->lock);
5937 MPASS(cst->flags & EO_SND_TAG_REF);
5939 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
5940 struct vi_info *vi = ifp->if_softc;
5941 struct port_info *pi = vi->pi;
5942 struct adapter *sc = pi->adapter;
5943 const uint32_t rss_mask = vi->rss_size - 1;
5946 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
5947 if (M_HASHTYPE_ISHASH(m0))
5948 rss_hash = m0->m_pkthdr.flowid;
5950 rss_hash = arc4random();
5951 /* We assume RSS hashing */
5952 cst->iqid = vi->rss[rss_hash & rss_mask];
5953 cst->eo_txq += rss_hash % vi->nofldtxq;
5954 rc = send_etid_flowc_wr(cst, pi, vi);
5959 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
5964 mbufq_enqueue(&cst->pending_tx, m0);
5965 cst->plen += m0->m_pkthdr.len;
5970 mtx_unlock(&cst->lock);
5971 if (__predict_false(rc != 0))
5977 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
5979 struct adapter *sc = iq->adapter;
5980 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
5982 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
5983 struct cxgbe_snd_tag *cst;
5984 uint8_t credits = cpl->credits;
5986 cst = lookup_etid(sc, etid);
5987 mtx_lock(&cst->lock);
5988 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
5989 MPASS(credits >= ETID_FLOWC_LEN16);
5990 credits -= ETID_FLOWC_LEN16;
5991 cst->flags &= ~EO_FLOWC_RPL_PENDING;
5994 KASSERT(cst->ncompl > 0,
5995 ("%s: etid %u (%p) wasn't expecting completion.",
5996 __func__, etid, cst));
5999 while (credits > 0) {
6000 m = mbufq_dequeue(&cst->pending_fwack);
6001 if (__predict_false(m == NULL)) {
6003 * The remaining credits are for the final flush that
6004 * was issued when the tag was freed by the kernel.
6007 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6008 EO_FLUSH_RPL_PENDING);
6009 MPASS(credits == ETID_FLUSH_LEN16);
6010 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6011 MPASS(cst->ncompl == 0);
6013 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6014 cst->tx_credits += cpl->credits;
6016 cxgbe_snd_tag_free_locked(cst);
6017 return (0); /* cst is gone. */
6020 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6022 KASSERT(credits >= mbuf_eo_len16(m),
6023 ("%s: too few credits (%u, %u, %u)", __func__,
6024 cpl->credits, credits, mbuf_eo_len16(m)));
6025 credits -= mbuf_eo_len16(m);
6026 cst->plen -= m->m_pkthdr.len;
6030 cst->tx_credits += cpl->credits;
6031 MPASS(cst->tx_credits <= cst->tx_total);
6033 m = mbufq_first(&cst->pending_tx);
6034 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6037 if (__predict_false((cst->flags & EO_SND_TAG_REF) == 0) &&
6039 if (cst->tx_credits == cst->tx_total)
6042 MPASS((cst->flags & EO_FLUSH_RPL_PENDING) == 0);
6043 send_etid_flush_wr(cst);
6047 mtx_unlock(&cst->lock);