2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_ratelimit.h"
37 #include <sys/types.h>
38 #include <sys/eventhandler.h>
40 #include <sys/socket.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
47 #include <sys/sglist.h>
48 #include <sys/sysctl.h>
50 #include <sys/counter.h>
52 #include <net/ethernet.h>
54 #include <net/if_vlan_var.h>
55 #include <netinet/in.h>
56 #include <netinet/ip.h>
57 #include <netinet/ip6.h>
58 #include <netinet/tcp.h>
59 #include <machine/in_cksum.h>
60 #include <machine/md_var.h>
64 #include <machine/bus.h>
65 #include <sys/selinfo.h>
66 #include <net/if_var.h>
67 #include <net/netmap.h>
68 #include <dev/netmap/netmap_kern.h>
71 #include "common/common.h"
72 #include "common/t4_regs.h"
73 #include "common/t4_regs_values.h"
74 #include "common/t4_msg.h"
76 #include "t4_mp_ring.h"
78 #ifdef T4_PKT_TIMESTAMP
79 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
81 #define RX_COPY_THRESHOLD MINCLSIZE
85 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
86 * 0-7 are valid values.
88 static int fl_pktshift = 2;
89 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
92 * Pad ethernet payload up to this boundary.
93 * -1: driver should figure out a good value.
95 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
98 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
101 * Status page length.
102 * -1: driver should figure out a good value.
103 * 64 or 128 are the only other valid values.
105 static int spg_len = -1;
106 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
110 * -1: no congestion feedback (not recommended).
111 * 0: backpressure the channel instead of dropping packets right away.
112 * 1: no backpressure, drop packets for the congested queue immediately.
114 static int cong_drop = 0;
115 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
118 * Deliver multiple frames in the same free list buffer if they fit.
119 * -1: let the driver decide whether to enable buffer packing or not.
120 * 0: disable buffer packing.
121 * 1: enable buffer packing.
123 static int buffer_packing = -1;
124 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
127 * Start next frame in a packed buffer at this boundary.
128 * -1: driver should figure out a good value.
129 * T4: driver will ignore this and use the same value as fl_pad above.
130 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
132 static int fl_pack = -1;
133 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
136 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
137 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
138 * 1: ok to create mbuf(s) within a cluster if there is room.
140 static int allow_mbufs_in_cluster = 1;
141 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
144 * Largest rx cluster size that the driver is allowed to allocate.
146 static int largest_rx_cluster = MJUM16BYTES;
147 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
150 * Size of cluster allocation that's most likely to succeed. The driver will
151 * fall back to this size if it fails to allocate clusters larger than this.
153 static int safest_rx_cluster = PAGE_SIZE;
154 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
157 * The interrupt holdoff timers are multiplied by this value on T6+.
158 * 1 and 3-17 (both inclusive) are legal values.
160 static int tscale = 1;
161 TUNABLE_INT("hw.cxgbe.tscale", &tscale);
164 * Number of LRO entries in the lro_ctrl structure per rx queue.
166 static int lro_entries = TCP_LRO_ENTRIES;
167 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries);
170 * This enables presorting of frames before they're fed into tcp_lro_rx.
172 static int lro_mbufs = 0;
173 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs);
176 u_int wr_type; /* type 0 or type 1 */
177 u_int npkt; /* # of packets in this work request */
178 u_int plen; /* total payload (sum of all packets) */
179 u_int len16; /* # of 16B pieces used by this work request */
182 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
185 struct sglist_seg seg[TX_SGL_SEGS];
188 static int service_iq(struct sge_iq *, int);
189 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
190 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
191 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
192 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
193 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
195 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
196 bus_addr_t *, void **);
197 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
199 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
201 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
202 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
204 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
205 struct sysctl_oid *, struct sge_fl *);
206 static int alloc_fwq(struct adapter *);
207 static int free_fwq(struct adapter *);
208 static int alloc_mgmtq(struct adapter *);
209 static int free_mgmtq(struct adapter *);
210 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
211 struct sysctl_oid *);
212 static int free_rxq(struct vi_info *, struct sge_rxq *);
214 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
215 struct sysctl_oid *);
216 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
219 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
220 struct sysctl_oid *);
221 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
222 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
223 struct sysctl_oid *);
224 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
226 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
227 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
228 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
229 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
231 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
232 static int free_eq(struct adapter *, struct sge_eq *);
233 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
234 struct sysctl_oid *);
235 static int free_wrq(struct adapter *, struct sge_wrq *);
236 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
237 struct sysctl_oid *);
238 static int free_txq(struct vi_info *, struct sge_txq *);
239 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
240 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
241 static int refill_fl(struct adapter *, struct sge_fl *, int);
242 static void refill_sfl(void *);
243 static int alloc_fl_sdesc(struct sge_fl *);
244 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
245 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
246 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
247 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
249 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
250 static inline u_int txpkt_len16(u_int, u_int);
251 static inline u_int txpkt_vm_len16(u_int, u_int);
252 static inline u_int txpkts0_len16(u_int);
253 static inline u_int txpkts1_len16(void);
254 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
255 struct mbuf *, u_int);
256 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
257 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
258 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
259 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
260 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
261 struct mbuf *, const struct txpkts *, u_int);
262 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
263 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
264 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
265 static inline uint16_t read_hw_cidx(struct sge_eq *);
266 static inline u_int reclaimable_tx_desc(struct sge_eq *);
267 static inline u_int total_available_tx_desc(struct sge_eq *);
268 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
269 static void tx_reclaim(void *, int);
270 static __be64 get_flit(struct sglist_seg *, int, int);
271 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
273 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
275 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
276 static void wrq_tx_drain(void *, int);
277 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
279 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
280 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
281 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
283 static counter_u64_t extfree_refs;
284 static counter_u64_t extfree_rels;
286 an_handler_t t4_an_handler;
287 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
288 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
289 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
290 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
291 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
292 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
295 t4_register_an_handler(an_handler_t h)
299 MPASS(h == NULL || t4_an_handler == NULL);
301 loc = (uintptr_t *)&t4_an_handler;
302 atomic_store_rel_ptr(loc, (uintptr_t)h);
306 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
310 MPASS(type < nitems(t4_fw_msg_handler));
311 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
313 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
314 * handler dispatch table. Reject any attempt to install a handler for
317 MPASS(type != FW_TYPE_RSSCPL);
318 MPASS(type != FW6_TYPE_RSSCPL);
320 loc = (uintptr_t *)&t4_fw_msg_handler[type];
321 atomic_store_rel_ptr(loc, (uintptr_t)h);
325 t4_register_cpl_handler(int opcode, cpl_handler_t h)
329 MPASS(opcode < nitems(t4_cpl_handler));
330 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
332 loc = (uintptr_t *)&t4_cpl_handler[opcode];
333 atomic_store_rel_ptr(loc, (uintptr_t)h);
337 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
340 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
347 if (is_ftid(iq->adapter, tid)) {
349 * The return code for filter-write is put in the CPL cookie so
350 * we have to rely on the hardware tid (is_ftid) to determine
351 * that this is a response to a filter.
353 cookie = CPL_COOKIE_FILTER;
355 cookie = G_COOKIE(cpl->cookie);
357 MPASS(cookie > CPL_COOKIE_RESERVED);
358 MPASS(cookie < nitems(set_tcb_rpl_handlers));
360 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
364 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
367 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
372 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
373 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
377 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
380 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
381 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
384 MPASS(cookie != CPL_COOKIE_RESERVED);
386 return (act_open_rpl_handlers[cookie](iq, rss, m));
390 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
393 struct adapter *sc = iq->adapter;
397 if (is_hashfilter(sc))
398 cookie = CPL_COOKIE_HASHFILTER;
400 cookie = CPL_COOKIE_TOM;
402 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
406 t4_init_shared_cpl_handlers(void)
409 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
410 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
411 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
412 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
416 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
420 MPASS(opcode < nitems(t4_cpl_handler));
421 MPASS(cookie > CPL_COOKIE_RESERVED);
422 MPASS(cookie < NUM_CPL_COOKIES);
423 MPASS(t4_cpl_handler[opcode] != NULL);
426 case CPL_SET_TCB_RPL:
427 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
429 case CPL_L2T_WRITE_RPL:
430 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
432 case CPL_ACT_OPEN_RPL:
433 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
435 case CPL_ABORT_RPL_RSS:
436 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
442 MPASS(h == NULL || *loc == (uintptr_t)NULL);
443 atomic_store_rel_ptr(loc, (uintptr_t)h);
447 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
453 if (fl_pktshift < 0 || fl_pktshift > 7) {
454 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
455 " using 2 instead.\n", fl_pktshift);
459 if (spg_len != 64 && spg_len != 128) {
462 #if defined(__i386__) || defined(__amd64__)
463 len = cpu_clflush_line_size > 64 ? 128 : 64;
468 printf("Invalid hw.cxgbe.spg_len value (%d),"
469 " using %d instead.\n", spg_len, len);
474 if (cong_drop < -1 || cong_drop > 1) {
475 printf("Invalid hw.cxgbe.cong_drop value (%d),"
476 " using 0 instead.\n", cong_drop);
480 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
481 printf("Invalid hw.cxgbe.tscale value (%d),"
482 " using 1 instead.\n", tscale);
486 extfree_refs = counter_u64_alloc(M_WAITOK);
487 extfree_rels = counter_u64_alloc(M_WAITOK);
488 counter_u64_zero(extfree_refs);
489 counter_u64_zero(extfree_rels);
491 t4_init_shared_cpl_handlers();
492 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
493 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
494 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
495 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
496 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
497 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
501 t4_sge_modunload(void)
504 counter_u64_free(extfree_refs);
505 counter_u64_free(extfree_rels);
509 t4_sge_extfree_refs(void)
513 rels = counter_u64_fetch(extfree_rels);
514 refs = counter_u64_fetch(extfree_refs);
516 return (refs - rels);
520 setup_pad_and_pack_boundaries(struct adapter *sc)
523 int pad, pack, pad_shift;
525 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
526 X_INGPADBOUNDARY_SHIFT;
528 if (fl_pad < (1 << pad_shift) ||
529 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
532 * If there is any chance that we might use buffer packing and
533 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
534 * it to the minimum allowed in all other cases.
536 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
539 * For fl_pad = 0 we'll still write a reasonable value to the
540 * register but all the freelists will opt out of padding.
541 * We'll complain here only if the user tried to set it to a
542 * value greater than 0 that was invalid.
545 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
546 " (%d), using %d instead.\n", fl_pad, pad);
549 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
550 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
551 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
554 if (fl_pack != -1 && fl_pack != pad) {
555 /* Complain but carry on. */
556 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
557 " using %d instead.\n", fl_pack, pad);
563 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
564 !powerof2(fl_pack)) {
565 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
566 MPASS(powerof2(pack));
574 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
575 " (%d), using %d instead.\n", fl_pack, pack);
578 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
580 v = V_INGPACKBOUNDARY(0);
582 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
584 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
585 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
589 * adap->params.vpd.cclk must be set up before this is called.
592 t4_tweak_chip_settings(struct adapter *sc)
596 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
597 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
598 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
599 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
600 static int sge_flbuf_sizes[] = {
602 #if MJUMPAGESIZE != MCLBYTES
604 MJUMPAGESIZE - CL_METADATA_SIZE,
605 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
609 MCLBYTES - MSIZE - CL_METADATA_SIZE,
610 MJUM9BYTES - CL_METADATA_SIZE,
611 MJUM16BYTES - CL_METADATA_SIZE,
614 KASSERT(sc->flags & MASTER_PF,
615 ("%s: trying to change chip settings when not master.", __func__));
617 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
618 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
619 V_EGRSTATUSPAGESIZE(spg_len == 128);
620 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
622 setup_pad_and_pack_boundaries(sc);
624 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
625 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
626 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
627 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
628 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
629 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
630 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
631 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
632 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
634 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
635 ("%s: hw buffer size table too big", __func__));
636 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
637 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
641 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
642 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
643 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
645 KASSERT(intr_timer[0] <= timer_max,
646 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
648 for (i = 1; i < nitems(intr_timer); i++) {
649 KASSERT(intr_timer[i] >= intr_timer[i - 1],
650 ("%s: timers not listed in increasing order (%d)",
653 while (intr_timer[i] > timer_max) {
654 if (i == nitems(intr_timer) - 1) {
655 intr_timer[i] = timer_max;
658 intr_timer[i] += intr_timer[i - 1];
663 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
664 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
665 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
666 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
667 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
668 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
669 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
670 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
671 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
673 if (chip_id(sc) >= CHELSIO_T6) {
674 m = V_TSCALE(M_TSCALE);
678 v = V_TSCALE(tscale - 2);
679 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
681 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
682 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
683 V_WRTHRTHRESH(M_WRTHRTHRESH);
684 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
686 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
688 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
692 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
693 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
694 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
697 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
698 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
699 * may have to deal with is MAXPHYS + 1 page.
701 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
702 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
704 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
705 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
706 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
708 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
710 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
711 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
715 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
716 * padding is in use, the buffer's start and end need to be aligned to the pad
717 * boundary as well. We'll just make sure that the size is a multiple of the
718 * boundary here, it is up to the buffer allocation code to make sure the start
719 * of the buffer is aligned as well.
722 hwsz_ok(struct adapter *sc, int hwsz)
724 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
726 return (hwsz >= 64 && (hwsz & mask) == 0);
730 * XXX: driver really should be able to deal with unexpected settings.
733 t4_read_chip_settings(struct adapter *sc)
735 struct sge *s = &sc->sge;
736 struct sge_params *sp = &sc->params.sge;
739 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
740 static int sw_buf_sizes[] = { /* Sorted by size */
742 #if MJUMPAGESIZE != MCLBYTES
748 struct sw_zone_info *swz, *safe_swz;
749 struct hw_buf_info *hwb;
753 r = sc->params.sge.sge_control;
755 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
760 * If this changes then every single use of PAGE_SHIFT in the driver
761 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
763 if (sp->page_shift != PAGE_SHIFT) {
764 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
768 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
769 hwb = &s->hw_buf_info[0];
770 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
771 r = sc->params.sge.sge_fl_buffer_size[i];
773 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
778 * Create a sorted list in decreasing order of hw buffer sizes (and so
779 * increasing order of spare area) for each software zone.
781 * If padding is enabled then the start and end of the buffer must align
782 * to the pad boundary; if packing is enabled then they must align with
783 * the pack boundary as well. Allocations from the cluster zones are
784 * aligned to min(size, 4K), so the buffer starts at that alignment and
785 * ends at hwb->size alignment. If mbuf inlining is allowed the
786 * starting alignment will be reduced to MSIZE and the driver will
787 * exercise appropriate caution when deciding on the best buffer layout
790 n = 0; /* no usable buffer size to begin with */
791 swz = &s->sw_zone_info[0];
793 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
794 int8_t head = -1, tail = -1;
796 swz->size = sw_buf_sizes[i];
797 swz->zone = m_getzone(swz->size);
798 swz->type = m_gettype(swz->size);
800 if (swz->size < PAGE_SIZE) {
801 MPASS(powerof2(swz->size));
802 if (fl_pad && (swz->size % sp->pad_boundary != 0))
806 if (swz->size == safest_rx_cluster)
809 hwb = &s->hw_buf_info[0];
810 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
811 if (hwb->zidx != -1 || hwb->size > swz->size)
815 MPASS(hwb->size % sp->pad_boundary == 0);
820 else if (hwb->size < s->hw_buf_info[tail].size) {
821 s->hw_buf_info[tail].next = j;
825 struct hw_buf_info *t;
827 for (cur = &head; *cur != -1; cur = &t->next) {
828 t = &s->hw_buf_info[*cur];
829 if (hwb->size == t->size) {
833 if (hwb->size > t->size) {
841 swz->head_hwidx = head;
842 swz->tail_hwidx = tail;
846 if (swz->size - s->hw_buf_info[tail].size >=
848 sc->flags |= BUF_PACKING_OK;
852 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
858 if (safe_swz != NULL) {
859 s->safe_hwidx1 = safe_swz->head_hwidx;
860 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
863 hwb = &s->hw_buf_info[i];
866 MPASS(hwb->size % sp->pad_boundary == 0);
868 spare = safe_swz->size - hwb->size;
869 if (spare >= CL_METADATA_SIZE) {
876 if (sc->flags & IS_VF)
879 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
880 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
882 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
886 m = v = F_TDDPTAGTCB;
887 r = t4_read_reg(sc, A_ULP_RX_CTL);
889 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
893 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
895 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
896 r = t4_read_reg(sc, A_TP_PARA_REG5);
898 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
902 t4_init_tp_params(sc, 1);
904 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
905 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
911 t4_create_dma_tag(struct adapter *sc)
915 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
916 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
917 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
920 device_printf(sc->dev,
921 "failed to create main DMA tag: %d\n", rc);
928 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
929 struct sysctl_oid_list *children)
931 struct sge_params *sp = &sc->params.sge;
933 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
934 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
935 "freelist buffer sizes");
937 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
938 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
940 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
941 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
943 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
944 NULL, sp->spg_len, "status page size (bytes)");
946 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
947 NULL, cong_drop, "congestion drop setting");
949 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
950 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
954 t4_destroy_dma_tag(struct adapter *sc)
957 bus_dma_tag_destroy(sc->dmat);
963 * Allocate and initialize the firmware event queue and the management queue.
965 * Returns errno on failure. Resources allocated up to that point may still be
966 * allocated. Caller is responsible for cleanup in case this function fails.
969 t4_setup_adapter_queues(struct adapter *sc)
973 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
975 sysctl_ctx_init(&sc->ctx);
976 sc->flags |= ADAP_SYSCTL_CTX;
979 * Firmware event queue
986 * Management queue. This is just a control queue that uses the fwq as
989 if (!(sc->flags & IS_VF))
990 rc = alloc_mgmtq(sc);
999 t4_teardown_adapter_queues(struct adapter *sc)
1002 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1004 /* Do this before freeing the queue */
1005 if (sc->flags & ADAP_SYSCTL_CTX) {
1006 sysctl_ctx_free(&sc->ctx);
1007 sc->flags &= ~ADAP_SYSCTL_CTX;
1016 /* Maximum payload that can be delivered with a single iq descriptor */
1018 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
1024 int rxcs = G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
1026 /* Note that COP can set rx_coalesce on/off per connection. */
1027 payload = max(mtu, rxcs);
1030 /* large enough even when hw VLAN extraction is disabled */
1031 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1032 ETHER_VLAN_ENCAP_LEN + mtu;
1041 t4_setup_vi_queues(struct vi_info *vi)
1043 int rc = 0, i, intr_idx, iqidx;
1044 struct sge_rxq *rxq;
1045 struct sge_txq *txq;
1046 struct sge_wrq *ctrlq;
1048 struct sge_ofld_rxq *ofld_rxq;
1050 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1051 struct sge_wrq *ofld_txq;
1055 struct sge_nm_rxq *nm_rxq;
1056 struct sge_nm_txq *nm_txq;
1059 struct port_info *pi = vi->pi;
1060 struct adapter *sc = pi->adapter;
1061 struct ifnet *ifp = vi->ifp;
1062 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1063 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1064 int maxp, mtu = ifp->if_mtu;
1066 /* Interrupt vector to start from (when using multiple vectors) */
1067 intr_idx = vi->first_intr;
1070 saved_idx = intr_idx;
1071 if (ifp->if_capabilities & IFCAP_NETMAP) {
1073 /* netmap is supported with direct interrupts only. */
1074 MPASS(!forwarding_intr_to_fwq(sc));
1077 * We don't have buffers to back the netmap rx queues
1078 * right now so we create the queues in a way that
1079 * doesn't set off any congestion signal in the chip.
1081 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1082 CTLFLAG_RD, NULL, "rx queues");
1083 for_each_nm_rxq(vi, i, nm_rxq) {
1084 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1090 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1091 CTLFLAG_RD, NULL, "tx queues");
1092 for_each_nm_txq(vi, i, nm_txq) {
1093 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1094 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1100 /* Normal rx queues and netmap rx queues share the same interrupts. */
1101 intr_idx = saved_idx;
1105 * Allocate rx queues first because a default iqid is required when
1106 * creating a tx queue.
1108 maxp = mtu_to_max_payload(sc, mtu, 0);
1109 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1110 CTLFLAG_RD, NULL, "rx queues");
1111 for_each_rxq(vi, i, rxq) {
1113 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1115 snprintf(name, sizeof(name), "%s rxq%d-fl",
1116 device_get_nameunit(vi->dev), i);
1117 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1119 rc = alloc_rxq(vi, rxq,
1120 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1126 if (ifp->if_capabilities & IFCAP_NETMAP)
1127 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1130 maxp = mtu_to_max_payload(sc, mtu, 1);
1131 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1132 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections");
1133 for_each_ofld_rxq(vi, i, ofld_rxq) {
1135 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1138 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1139 device_get_nameunit(vi->dev), i);
1140 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1142 rc = alloc_ofld_rxq(vi, ofld_rxq,
1143 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1151 * Now the tx queues.
1153 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1155 for_each_txq(vi, i, txq) {
1156 iqidx = vi->first_rxq + (i % vi->nrxq);
1157 snprintf(name, sizeof(name), "%s txq%d",
1158 device_get_nameunit(vi->dev), i);
1159 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1160 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1162 rc = alloc_txq(vi, txq, i, oid);
1166 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1167 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1168 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD");
1169 for_each_ofld_txq(vi, i, ofld_txq) {
1170 struct sysctl_oid *oid2;
1172 snprintf(name, sizeof(name), "%s ofld_txq%d",
1173 device_get_nameunit(vi->dev), i);
1175 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1176 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1177 sc->sge.ofld_rxq[iqidx].iq.cntxt_id, name);
1179 iqidx = vi->first_rxq + (i % vi->nrxq);
1180 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1181 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1184 snprintf(name, sizeof(name), "%d", i);
1185 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1186 name, CTLFLAG_RD, NULL, "offload tx queue");
1188 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1195 * Finally, the control queue.
1197 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1199 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1200 NULL, "ctrl queue");
1201 ctrlq = &sc->sge.ctrlq[pi->port_id];
1202 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1203 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan,
1204 sc->sge.rxq[vi->first_rxq].iq.cntxt_id, name);
1205 rc = alloc_wrq(sc, vi, ctrlq, oid);
1209 t4_teardown_vi_queues(vi);
1218 t4_teardown_vi_queues(struct vi_info *vi)
1221 struct port_info *pi = vi->pi;
1222 struct adapter *sc = pi->adapter;
1223 struct sge_rxq *rxq;
1224 struct sge_txq *txq;
1226 struct sge_ofld_rxq *ofld_rxq;
1228 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1229 struct sge_wrq *ofld_txq;
1232 struct sge_nm_rxq *nm_rxq;
1233 struct sge_nm_txq *nm_txq;
1236 /* Do this before freeing the queues */
1237 if (vi->flags & VI_SYSCTL_CTX) {
1238 sysctl_ctx_free(&vi->ctx);
1239 vi->flags &= ~VI_SYSCTL_CTX;
1243 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1244 for_each_nm_txq(vi, i, nm_txq) {
1245 free_nm_txq(vi, nm_txq);
1248 for_each_nm_rxq(vi, i, nm_rxq) {
1249 free_nm_rxq(vi, nm_rxq);
1255 * Take down all the tx queues first, as they reference the rx queues
1256 * (for egress updates, etc.).
1259 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1260 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1262 for_each_txq(vi, i, txq) {
1265 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1266 for_each_ofld_txq(vi, i, ofld_txq) {
1267 free_wrq(sc, ofld_txq);
1272 * Then take down the rx queues.
1275 for_each_rxq(vi, i, rxq) {
1279 for_each_ofld_rxq(vi, i, ofld_rxq) {
1280 free_ofld_rxq(vi, ofld_rxq);
1288 * Deals with errors and the firmware event queue. All data rx queues forward
1289 * their interrupt to the firmware event queue.
1292 t4_intr_all(void *arg)
1294 struct adapter *sc = arg;
1295 struct sge_iq *fwq = &sc->sge.fwq;
1298 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1300 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1304 /* Deals with error interrupts */
1306 t4_intr_err(void *arg)
1308 struct adapter *sc = arg;
1310 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1311 t4_slow_intr_handler(sc);
1315 t4_intr_evt(void *arg)
1317 struct sge_iq *iq = arg;
1319 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1321 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1328 struct sge_iq *iq = arg;
1330 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1332 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1337 t4_vi_intr(void *arg)
1339 struct irq *irq = arg;
1342 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1343 t4_nm_intr(irq->nm_rxq);
1344 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1347 if (irq->rxq != NULL)
1352 sort_before_lro(struct lro_ctrl *lro)
1355 return (lro->lro_mbuf_max != 0);
1359 * Deals with anything and everything on the given ingress queue.
1362 service_iq(struct sge_iq *iq, int budget)
1365 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1366 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1367 struct adapter *sc = iq->adapter;
1368 struct iq_desc *d = &iq->desc[iq->cidx];
1369 int ndescs = 0, limit;
1370 int rsp_type, refill;
1372 uint16_t fl_hw_cidx;
1374 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1375 #if defined(INET) || defined(INET6)
1376 const struct timeval lro_timeout = {0, sc->lro_timeout};
1377 struct lro_ctrl *lro = &rxq->lro;
1380 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1382 limit = budget ? budget : iq->qsize / 16;
1384 if (iq->flags & IQ_HAS_FL) {
1386 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1389 fl_hw_cidx = 0; /* to silence gcc warning */
1392 #if defined(INET) || defined(INET6)
1393 if (iq->flags & IQ_ADJ_CREDIT) {
1394 MPASS(sort_before_lro(lro));
1395 iq->flags &= ~IQ_ADJ_CREDIT;
1396 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1397 tcp_lro_flush_all(lro);
1398 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1399 V_INGRESSQID((u32)iq->cntxt_id) |
1400 V_SEINTARM(iq->intr_params));
1406 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1410 * We always come back and check the descriptor ring for new indirect
1411 * interrupts and other responses after running a single handler.
1414 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1420 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1421 lq = be32toh(d->rsp.pldbuflen_qid);
1424 case X_RSPD_TYPE_FLBUF:
1426 KASSERT(iq->flags & IQ_HAS_FL,
1427 ("%s: data for an iq (%p) with no freelist",
1430 m0 = get_fl_payload(sc, fl, lq);
1431 if (__predict_false(m0 == NULL))
1433 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1434 #ifdef T4_PKT_TIMESTAMP
1436 * 60 bit timestamp for the payload is
1437 * *(uint64_t *)m0->m_pktdat. Note that it is
1438 * in the leading free-space in the mbuf. The
1439 * kernel can clobber it during a pullup,
1440 * m_copymdata, etc. You need to make sure that
1441 * the mbuf reaches you unmolested if you care
1442 * about the timestamp.
1444 *(uint64_t *)m0->m_pktdat =
1445 be64toh(ctrl->u.last_flit) &
1451 case X_RSPD_TYPE_CPL:
1452 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1453 ("%s: bad opcode %02x.", __func__,
1455 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1458 case X_RSPD_TYPE_INTR:
1461 * Interrupts should be forwarded only to queues
1462 * that are not forwarding their interrupts.
1463 * This means service_iq can recurse but only 1
1466 KASSERT(budget == 0,
1467 ("%s: budget %u, rsp_type %u", __func__,
1471 * There are 1K interrupt-capable queues (qids 0
1472 * through 1023). A response type indicating a
1473 * forwarded interrupt with a qid >= 1K is an
1474 * iWARP async notification.
1477 t4_an_handler(iq, &d->rsp);
1481 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1483 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1485 if (service_iq(q, q->qsize / 16) == 0) {
1486 atomic_cmpset_int(&q->state,
1487 IQS_BUSY, IQS_IDLE);
1489 STAILQ_INSERT_TAIL(&iql, q,
1497 ("%s: illegal response type %d on iq %p",
1498 __func__, rsp_type, iq));
1500 "%s: illegal response type %d on iq %p",
1501 device_get_nameunit(sc->dev), rsp_type, iq);
1506 if (__predict_false(++iq->cidx == iq->sidx)) {
1508 iq->gen ^= F_RSPD_GEN;
1511 if (__predict_false(++ndescs == limit)) {
1512 t4_write_reg(sc, sc->sge_gts_reg,
1514 V_INGRESSQID(iq->cntxt_id) |
1515 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1518 #if defined(INET) || defined(INET6)
1519 if (iq->flags & IQ_LRO_ENABLED &&
1520 !sort_before_lro(lro) &&
1521 sc->lro_timeout != 0) {
1522 tcp_lro_flush_inactive(lro,
1528 if (iq->flags & IQ_HAS_FL) {
1530 refill_fl(sc, fl, 32);
1533 return (EINPROGRESS);
1538 refill_fl(sc, fl, 32);
1540 fl_hw_cidx = fl->hw_cidx;
1545 if (STAILQ_EMPTY(&iql))
1549 * Process the head only, and send it to the back of the list if
1550 * it's still not done.
1552 q = STAILQ_FIRST(&iql);
1553 STAILQ_REMOVE_HEAD(&iql, link);
1554 if (service_iq(q, q->qsize / 8) == 0)
1555 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1557 STAILQ_INSERT_TAIL(&iql, q, link);
1560 #if defined(INET) || defined(INET6)
1561 if (iq->flags & IQ_LRO_ENABLED) {
1562 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1563 MPASS(sort_before_lro(lro));
1564 /* hold back one credit and don't flush LRO state */
1565 iq->flags |= IQ_ADJ_CREDIT;
1568 tcp_lro_flush_all(lro);
1573 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1574 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1576 if (iq->flags & IQ_HAS_FL) {
1580 starved = refill_fl(sc, fl, 64);
1582 if (__predict_false(starved != 0))
1583 add_fl_to_sfl(sc, fl);
1590 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1592 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1595 MPASS(cll->region3 >= CL_METADATA_SIZE);
1600 static inline struct cluster_metadata *
1601 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1605 if (cl_has_metadata(fl, cll)) {
1606 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1608 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1614 rxb_free(struct mbuf *m)
1616 uma_zone_t zone = m->m_ext.ext_arg1;
1617 void *cl = m->m_ext.ext_arg2;
1619 uma_zfree(zone, cl);
1620 counter_u64_add(extfree_rels, 1);
1624 * The mbuf returned by this function could be allocated from zone_mbuf or
1625 * constructed in spare room in the cluster.
1627 * The mbuf carries the payload in one of these ways
1628 * a) frame inside the mbuf (mbuf from zone_mbuf)
1629 * b) m_cljset (for clusters without metadata) zone_mbuf
1630 * c) m_extaddref (cluster with metadata) inline mbuf
1631 * d) m_extaddref (cluster with metadata) zone_mbuf
1633 static struct mbuf *
1634 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1638 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1639 struct cluster_layout *cll = &sd->cll;
1640 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1641 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1642 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1646 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1647 len = min(remaining, blen);
1648 payload = sd->cl + cll->region1 + fl->rx_offset;
1649 if (fl->flags & FL_BUF_PACKING) {
1650 const u_int l = fr_offset + len;
1651 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1653 if (fl->rx_offset + len + pad < hwb->size)
1655 MPASS(fl->rx_offset + blen <= hwb->size);
1657 MPASS(fl->rx_offset == 0); /* not packing */
1661 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1664 * Copy payload into a freshly allocated mbuf.
1667 m = fr_offset == 0 ?
1668 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1671 fl->mbuf_allocated++;
1672 #ifdef T4_PKT_TIMESTAMP
1673 /* Leave room for a timestamp */
1676 /* copy data to mbuf */
1677 bcopy(payload, mtod(m, caddr_t), len);
1679 } else if (sd->nmbuf * MSIZE < cll->region1) {
1682 * There's spare room in the cluster for an mbuf. Create one
1683 * and associate it with the payload that's in the cluster.
1687 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1688 /* No bzero required */
1689 if (m_init(m, M_NOWAIT, MT_DATA,
1690 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1693 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1695 if (sd->nmbuf++ == 0)
1696 counter_u64_add(extfree_refs, 1);
1701 * Grab an mbuf from zone_mbuf and associate it with the
1702 * payload in the cluster.
1705 m = fr_offset == 0 ?
1706 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1709 fl->mbuf_allocated++;
1711 m_extaddref(m, payload, blen, &clm->refcount,
1712 rxb_free, swz->zone, sd->cl);
1713 if (sd->nmbuf++ == 0)
1714 counter_u64_add(extfree_refs, 1);
1716 m_cljset(m, sd->cl, swz->type);
1717 sd->cl = NULL; /* consumed, not a recycle candidate */
1721 m->m_pkthdr.len = remaining;
1724 if (fl->flags & FL_BUF_PACKING) {
1725 fl->rx_offset += blen;
1726 MPASS(fl->rx_offset <= hwb->size);
1727 if (fl->rx_offset < hwb->size)
1728 return (m); /* without advancing the cidx */
1731 if (__predict_false(++fl->cidx % 8 == 0)) {
1732 uint16_t cidx = fl->cidx / 8;
1734 if (__predict_false(cidx == fl->sidx))
1735 fl->cidx = cidx = 0;
1743 static struct mbuf *
1744 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1746 struct mbuf *m0, *m, **pnext;
1748 const u_int total = G_RSPD_LEN(len_newbuf);
1750 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1751 M_ASSERTPKTHDR(fl->m0);
1752 MPASS(fl->m0->m_pkthdr.len == total);
1753 MPASS(fl->remaining < total);
1757 remaining = fl->remaining;
1758 fl->flags &= ~FL_BUF_RESUME;
1762 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1764 if (__predict_false(++fl->cidx % 8 == 0)) {
1765 uint16_t cidx = fl->cidx / 8;
1767 if (__predict_false(cidx == fl->sidx))
1768 fl->cidx = cidx = 0;
1774 * Payload starts at rx_offset in the current hw buffer. Its length is
1775 * 'len' and it may span multiple hw buffers.
1778 m0 = get_scatter_segment(sc, fl, 0, total);
1781 remaining = total - m0->m_len;
1782 pnext = &m0->m_next;
1783 while (remaining > 0) {
1785 MPASS(fl->rx_offset == 0);
1786 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1787 if (__predict_false(m == NULL)) {
1790 fl->remaining = remaining;
1791 fl->flags |= FL_BUF_RESUME;
1796 remaining -= m->m_len;
1805 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1807 struct sge_rxq *rxq = iq_to_rxq(iq);
1808 struct ifnet *ifp = rxq->ifp;
1809 struct adapter *sc = iq->adapter;
1810 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1811 #if defined(INET) || defined(INET6)
1812 struct lro_ctrl *lro = &rxq->lro;
1814 static const int sw_hashtype[4][2] = {
1815 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1816 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1817 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1818 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1821 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1824 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1825 m0->m_len -= sc->params.sge.fl_pktshift;
1826 m0->m_data += sc->params.sge.fl_pktshift;
1828 m0->m_pkthdr.rcvif = ifp;
1829 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1830 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1832 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1833 if (ifp->if_capenable & IFCAP_RXCSUM &&
1834 cpl->l2info & htobe32(F_RXF_IP)) {
1835 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1836 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1838 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1839 cpl->l2info & htobe32(F_RXF_IP6)) {
1840 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1845 if (__predict_false(cpl->ip_frag))
1846 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1848 m0->m_pkthdr.csum_data = 0xffff;
1852 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1853 m0->m_flags |= M_VLANTAG;
1854 rxq->vlan_extraction++;
1857 #if defined(INET) || defined(INET6)
1858 if (iq->flags & IQ_LRO_ENABLED) {
1859 if (sort_before_lro(lro)) {
1860 tcp_lro_queue_mbuf(lro, m0);
1861 return (0); /* queued for sort, then LRO */
1863 if (tcp_lro_rx(lro, m0, 0) == 0)
1864 return (0); /* queued for LRO */
1867 ifp->if_input(ifp, m0);
1873 * Must drain the wrq or make sure that someone else will.
1876 wrq_tx_drain(void *arg, int n)
1878 struct sge_wrq *wrq = arg;
1879 struct sge_eq *eq = &wrq->eq;
1882 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1883 drain_wrq_wr_list(wrq->adapter, wrq);
1888 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1890 struct sge_eq *eq = &wrq->eq;
1891 u_int available, dbdiff; /* # of hardware descriptors */
1894 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1896 EQ_LOCK_ASSERT_OWNED(eq);
1897 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1898 wr = STAILQ_FIRST(&wrq->wr_list);
1899 MPASS(wr != NULL); /* Must be called with something useful to do */
1900 MPASS(eq->pidx == eq->dbidx);
1904 eq->cidx = read_hw_cidx(eq);
1905 if (eq->pidx == eq->cidx)
1906 available = eq->sidx - 1;
1908 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1910 MPASS(wr->wrq == wrq);
1911 n = howmany(wr->wr_len, EQ_ESIZE);
1915 dst = (void *)&eq->desc[eq->pidx];
1916 if (__predict_true(eq->sidx - eq->pidx > n)) {
1917 /* Won't wrap, won't end exactly at the status page. */
1918 bcopy(&wr->wr[0], dst, wr->wr_len);
1921 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1923 bcopy(&wr->wr[0], dst, first_portion);
1924 if (wr->wr_len > first_portion) {
1925 bcopy(&wr->wr[first_portion], &eq->desc[0],
1926 wr->wr_len - first_portion);
1928 eq->pidx = n - (eq->sidx - eq->pidx);
1930 wrq->tx_wrs_copied++;
1932 if (available < eq->sidx / 4 &&
1933 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1934 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1936 eq->equeqidx = eq->pidx;
1937 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1938 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1939 eq->equeqidx = eq->pidx;
1944 ring_eq_db(sc, eq, dbdiff);
1948 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1950 MPASS(wrq->nwr_pending > 0);
1952 MPASS(wrq->ndesc_needed >= n);
1953 wrq->ndesc_needed -= n;
1954 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1957 ring_eq_db(sc, eq, dbdiff);
1961 * Doesn't fail. Holds on to work requests it can't send right away.
1964 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1967 struct sge_eq *eq = &wrq->eq;
1970 EQ_LOCK_ASSERT_OWNED(eq);
1972 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1973 MPASS((wr->wr_len & 0x7) == 0);
1975 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1977 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1979 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1980 return; /* commit_wrq_wr will drain wr_list as well. */
1982 drain_wrq_wr_list(sc, wrq);
1984 /* Doorbell must have caught up to the pidx. */
1985 MPASS(eq->pidx == eq->dbidx);
1989 t4_update_fl_bufsize(struct ifnet *ifp)
1991 struct vi_info *vi = ifp->if_softc;
1992 struct adapter *sc = vi->pi->adapter;
1993 struct sge_rxq *rxq;
1995 struct sge_ofld_rxq *ofld_rxq;
1998 int i, maxp, mtu = ifp->if_mtu;
2000 maxp = mtu_to_max_payload(sc, mtu, 0);
2001 for_each_rxq(vi, i, rxq) {
2005 find_best_refill_source(sc, fl, maxp);
2009 maxp = mtu_to_max_payload(sc, mtu, 1);
2010 for_each_ofld_rxq(vi, i, ofld_rxq) {
2014 find_best_refill_source(sc, fl, maxp);
2021 mbuf_nsegs(struct mbuf *m)
2025 KASSERT(m->m_pkthdr.l5hlen > 0,
2026 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2028 return (m->m_pkthdr.l5hlen);
2032 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2036 m->m_pkthdr.l5hlen = nsegs;
2040 mbuf_len16(struct mbuf *m)
2045 n = m->m_pkthdr.PH_loc.eight[0];
2046 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2052 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2056 m->m_pkthdr.PH_loc.eight[0] = len16;
2060 needs_tso(struct mbuf *m)
2065 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2066 KASSERT(m->m_pkthdr.tso_segsz > 0,
2067 ("%s: TSO requested in mbuf %p but MSS not provided",
2076 needs_l3_csum(struct mbuf *m)
2081 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2087 needs_l4_csum(struct mbuf *m)
2092 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2093 CSUM_TCP_IPV6 | CSUM_TSO))
2099 needs_vlan_insertion(struct mbuf *m)
2104 if (m->m_flags & M_VLANTAG) {
2105 KASSERT(m->m_pkthdr.ether_vtag != 0,
2106 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2114 m_advance(struct mbuf **pm, int *poffset, int len)
2116 struct mbuf *m = *pm;
2117 int offset = *poffset;
2123 if (offset + len < m->m_len) {
2125 p = mtod(m, uintptr_t) + offset;
2128 len -= m->m_len - offset;
2139 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2140 * must have at least one mbuf that's not empty.
2143 count_mbuf_nsegs(struct mbuf *m)
2145 vm_paddr_t lastb, next;
2153 for (; m; m = m->m_next) {
2156 if (__predict_false(len == 0))
2158 va = mtod(m, vm_offset_t);
2159 next = pmap_kextract(va);
2160 nsegs += sglist_count(m->m_data, len);
2161 if (lastb + 1 == next)
2163 lastb = pmap_kextract(va + len - 1);
2171 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2172 * a) caller can assume it's been freed if this function returns with an error.
2173 * b) it may get defragged up if the gather list is too long for the hardware.
2176 parse_pkt(struct adapter *sc, struct mbuf **mp)
2178 struct mbuf *m0 = *mp, *m;
2179 int rc, nsegs, defragged = 0, offset;
2180 struct ether_header *eh;
2182 #if defined(INET) || defined(INET6)
2188 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2197 * First count the number of gather list segments in the payload.
2198 * Defrag the mbuf if nsegs exceeds the hardware limit.
2201 MPASS(m0->m_pkthdr.len > 0);
2202 nsegs = count_mbuf_nsegs(m0);
2203 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2204 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2208 *mp = m0 = m; /* update caller's copy after defrag */
2212 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2213 m0 = m_pullup(m0, m0->m_pkthdr.len);
2215 /* Should have left well enough alone. */
2219 *mp = m0; /* update caller's copy after pullup */
2222 set_mbuf_nsegs(m0, nsegs);
2223 if (sc->flags & IS_VF)
2224 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2226 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2228 if (!needs_tso(m0) &&
2229 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2233 eh = mtod(m, struct ether_header *);
2234 eh_type = ntohs(eh->ether_type);
2235 if (eh_type == ETHERTYPE_VLAN) {
2236 struct ether_vlan_header *evh = (void *)eh;
2238 eh_type = ntohs(evh->evl_proto);
2239 m0->m_pkthdr.l2hlen = sizeof(*evh);
2241 m0->m_pkthdr.l2hlen = sizeof(*eh);
2244 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2248 case ETHERTYPE_IPV6:
2250 struct ip6_hdr *ip6 = l3hdr;
2252 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2254 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2261 struct ip *ip = l3hdr;
2263 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2268 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2269 " with the same INET/INET6 options as the kernel.",
2273 #if defined(INET) || defined(INET6)
2274 if (needs_tso(m0)) {
2275 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2276 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2284 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2286 struct sge_eq *eq = &wrq->eq;
2287 struct adapter *sc = wrq->adapter;
2288 int ndesc, available;
2293 ndesc = howmany(len16, EQ_ESIZE / 16);
2294 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2298 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2299 drain_wrq_wr_list(sc, wrq);
2301 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2304 wr = alloc_wrqe(len16 * 16, wrq);
2305 if (__predict_false(wr == NULL))
2308 cookie->ndesc = ndesc;
2312 eq->cidx = read_hw_cidx(eq);
2313 if (eq->pidx == eq->cidx)
2314 available = eq->sidx - 1;
2316 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2317 if (available < ndesc)
2320 cookie->pidx = eq->pidx;
2321 cookie->ndesc = ndesc;
2322 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2324 w = &eq->desc[eq->pidx];
2325 IDXINCR(eq->pidx, ndesc, eq->sidx);
2326 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2328 wrq->ss_pidx = cookie->pidx;
2329 wrq->ss_len = len16 * 16;
2338 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2340 struct sge_eq *eq = &wrq->eq;
2341 struct adapter *sc = wrq->adapter;
2343 struct wrq_cookie *prev, *next;
2345 if (cookie->pidx == -1) {
2346 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2352 if (__predict_false(w == &wrq->ss[0])) {
2353 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2355 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2356 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2357 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2360 wrq->tx_wrs_direct++;
2363 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2364 pidx = cookie->pidx;
2365 MPASS(pidx >= 0 && pidx < eq->sidx);
2366 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2367 next = TAILQ_NEXT(cookie, link);
2369 MPASS(pidx == eq->dbidx);
2370 if (next == NULL || ndesc >= 16)
2371 ring_eq_db(wrq->adapter, eq, ndesc);
2373 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2375 next->ndesc += ndesc;
2378 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2379 prev->ndesc += ndesc;
2381 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2383 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2384 drain_wrq_wr_list(sc, wrq);
2387 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2388 /* Doorbell must have caught up to the pidx. */
2389 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2396 can_resume_eth_tx(struct mp_ring *r)
2398 struct sge_eq *eq = r->cookie;
2400 return (total_available_tx_desc(eq) > eq->sidx / 8);
2404 cannot_use_txpkts(struct mbuf *m)
2406 /* maybe put a GL limit too, to avoid silliness? */
2408 return (needs_tso(m));
2412 discard_tx(struct sge_eq *eq)
2415 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2419 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2420 * be consumed. Return the actual number consumed. 0 indicates a stall.
2423 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2425 struct sge_txq *txq = r->cookie;
2426 struct sge_eq *eq = &txq->eq;
2427 struct ifnet *ifp = txq->ifp;
2428 struct vi_info *vi = ifp->if_softc;
2429 struct port_info *pi = vi->pi;
2430 struct adapter *sc = pi->adapter;
2431 u_int total, remaining; /* # of packets */
2432 u_int available, dbdiff; /* # of hardware descriptors */
2434 struct mbuf *m0, *tail;
2436 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2438 remaining = IDXDIFF(pidx, cidx, r->size);
2439 MPASS(remaining > 0); /* Must not be called without work to do. */
2443 if (__predict_false(discard_tx(eq))) {
2444 while (cidx != pidx) {
2445 m0 = r->items[cidx];
2447 if (++cidx == r->size)
2450 reclaim_tx_descs(txq, 2048);
2455 /* How many hardware descriptors do we have readily available. */
2456 if (eq->pidx == eq->cidx)
2457 available = eq->sidx - 1;
2459 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2460 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2462 while (remaining > 0) {
2464 m0 = r->items[cidx];
2466 MPASS(m0->m_nextpkt == NULL);
2468 if (available < SGE_MAX_WR_NDESC) {
2469 available += reclaim_tx_descs(txq, 64);
2470 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2471 break; /* out of descriptors */
2474 next_cidx = cidx + 1;
2475 if (__predict_false(next_cidx == r->size))
2478 wr = (void *)&eq->desc[eq->pidx];
2479 if (sc->flags & IS_VF) {
2482 ETHER_BPF_MTAP(ifp, m0);
2483 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2485 } else if (remaining > 1 &&
2486 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2488 /* pkts at cidx, next_cidx should both be in txp. */
2489 MPASS(txp.npkt == 2);
2490 tail = r->items[next_cidx];
2491 MPASS(tail->m_nextpkt == NULL);
2492 ETHER_BPF_MTAP(ifp, m0);
2493 ETHER_BPF_MTAP(ifp, tail);
2494 m0->m_nextpkt = tail;
2496 if (__predict_false(++next_cidx == r->size))
2499 while (next_cidx != pidx) {
2500 if (add_to_txpkts(r->items[next_cidx], &txp,
2503 tail->m_nextpkt = r->items[next_cidx];
2504 tail = tail->m_nextpkt;
2505 ETHER_BPF_MTAP(ifp, tail);
2506 if (__predict_false(++next_cidx == r->size))
2510 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2512 remaining -= txp.npkt;
2516 ETHER_BPF_MTAP(ifp, m0);
2517 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2519 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2523 IDXINCR(eq->pidx, n, eq->sidx);
2525 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2526 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2527 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2529 eq->equeqidx = eq->pidx;
2530 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2531 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2532 eq->equeqidx = eq->pidx;
2535 if (dbdiff >= 16 && remaining >= 4) {
2536 ring_eq_db(sc, eq, dbdiff);
2537 available += reclaim_tx_descs(txq, 4 * dbdiff);
2544 ring_eq_db(sc, eq, dbdiff);
2545 reclaim_tx_descs(txq, 32);
2554 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2558 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2559 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2560 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2561 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2565 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2566 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2567 if (pktc_idx >= 0) {
2568 iq->intr_params |= F_QINTR_CNT_EN;
2569 iq->intr_pktc_idx = pktc_idx;
2571 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2572 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2576 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2580 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2581 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2582 if (sc->flags & BUF_PACKING_OK &&
2583 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2584 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2585 fl->flags |= FL_BUF_PACKING;
2586 find_best_refill_source(sc, fl, maxp);
2587 find_safe_refill_source(sc, fl);
2591 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2592 uint8_t tx_chan, uint16_t iqid, char *name)
2594 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2596 eq->flags = eqtype & EQ_TYPEMASK;
2597 eq->tx_chan = tx_chan;
2599 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2600 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2604 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2605 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2609 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2610 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2612 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2616 rc = bus_dmamem_alloc(*tag, va,
2617 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2619 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2623 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2625 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2630 free_ring(sc, *tag, *map, *pa, *va);
2636 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2637 bus_addr_t pa, void *va)
2640 bus_dmamap_unload(tag, map);
2642 bus_dmamem_free(tag, va, map);
2644 bus_dma_tag_destroy(tag);
2650 * Allocates the ring for an ingress queue and an optional freelist. If the
2651 * freelist is specified it will be allocated and then associated with the
2654 * Returns errno on failure. Resources allocated up to that point may still be
2655 * allocated. Caller is responsible for cleanup in case this function fails.
2657 * If the ingress queue will take interrupts directly then the intr_idx
2658 * specifies the vector, starting from 0. -1 means the interrupts for this
2659 * queue should be forwarded to the fwq.
2662 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2663 int intr_idx, int cong)
2665 int rc, i, cntxt_id;
2668 struct port_info *pi = vi->pi;
2669 struct adapter *sc = iq->adapter;
2670 struct sge_params *sp = &sc->params.sge;
2673 len = iq->qsize * IQ_ESIZE;
2674 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2675 (void **)&iq->desc);
2679 bzero(&c, sizeof(c));
2680 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2681 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2682 V_FW_IQ_CMD_VFN(0));
2684 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2687 /* Special handling for firmware event queue */
2688 if (iq == &sc->sge.fwq)
2689 v |= F_FW_IQ_CMD_IQASYNCH;
2692 /* Forwarded interrupts, all headed to fwq */
2693 v |= F_FW_IQ_CMD_IQANDST;
2694 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
2696 KASSERT(intr_idx < sc->intr_count,
2697 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2698 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2701 c.type_to_iqandstindex = htobe32(v |
2702 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2703 V_FW_IQ_CMD_VIID(vi->viid) |
2704 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2705 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2706 F_FW_IQ_CMD_IQGTSMODE |
2707 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2708 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2709 c.iqsize = htobe16(iq->qsize);
2710 c.iqaddr = htobe64(iq->ba);
2712 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2715 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2717 len = fl->qsize * EQ_ESIZE;
2718 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2719 &fl->ba, (void **)&fl->desc);
2723 /* Allocate space for one software descriptor per buffer. */
2724 rc = alloc_fl_sdesc(fl);
2726 device_printf(sc->dev,
2727 "failed to setup fl software descriptors: %d\n",
2732 if (fl->flags & FL_BUF_PACKING) {
2733 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2734 fl->buf_boundary = sp->pack_boundary;
2736 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2737 fl->buf_boundary = 16;
2739 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2740 fl->buf_boundary = sp->pad_boundary;
2742 c.iqns_to_fl0congen |=
2743 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2744 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2745 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2746 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2749 c.iqns_to_fl0congen |=
2750 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2751 F_FW_IQ_CMD_FL0CONGCIF |
2752 F_FW_IQ_CMD_FL0CONGEN);
2754 c.fl0dcaen_to_fl0cidxfthresh =
2755 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2756 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2757 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2758 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2759 c.fl0size = htobe16(fl->qsize);
2760 c.fl0addr = htobe64(fl->ba);
2763 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2765 device_printf(sc->dev,
2766 "failed to create ingress queue: %d\n", rc);
2771 iq->gen = F_RSPD_GEN;
2772 iq->intr_next = iq->intr_params;
2773 iq->cntxt_id = be16toh(c.iqid);
2774 iq->abs_id = be16toh(c.physiqid);
2775 iq->flags |= IQ_ALLOCATED;
2777 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2778 if (cntxt_id >= sc->sge.niq) {
2779 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2780 cntxt_id, sc->sge.niq - 1);
2782 sc->sge.iqmap[cntxt_id] = iq;
2787 iq->flags |= IQ_HAS_FL;
2788 fl->cntxt_id = be16toh(c.fl0id);
2789 fl->pidx = fl->cidx = 0;
2791 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2792 if (cntxt_id >= sc->sge.neq) {
2793 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2794 __func__, cntxt_id, sc->sge.neq - 1);
2796 sc->sge.eqmap[cntxt_id] = (void *)fl;
2799 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2800 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2801 uint32_t mask = (1 << s_qpp) - 1;
2802 volatile uint8_t *udb;
2804 udb = sc->udbs_base + UDBS_DB_OFFSET;
2805 udb += (qid >> s_qpp) << PAGE_SHIFT;
2807 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2808 udb += qid << UDBS_SEG_SHIFT;
2811 fl->udb = (volatile void *)udb;
2813 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2816 /* Enough to make sure the SGE doesn't think it's starved */
2817 refill_fl(sc, fl, fl->lowat);
2821 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2822 uint32_t param, val;
2824 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2825 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2826 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2831 for (i = 0; i < 4; i++) {
2832 if (cong & (1 << i))
2833 val |= 1 << (i << 2);
2837 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2839 /* report error but carry on */
2840 device_printf(sc->dev,
2841 "failed to set congestion manager context for "
2842 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2846 /* Enable IQ interrupts */
2847 atomic_store_rel_int(&iq->state, IQS_IDLE);
2848 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2849 V_INGRESSQID(iq->cntxt_id));
2855 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2858 struct adapter *sc = iq->adapter;
2862 return (0); /* nothing to do */
2864 dev = vi ? vi->dev : sc->dev;
2866 if (iq->flags & IQ_ALLOCATED) {
2867 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2868 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2869 fl ? fl->cntxt_id : 0xffff, 0xffff);
2872 "failed to free queue %p: %d\n", iq, rc);
2875 iq->flags &= ~IQ_ALLOCATED;
2878 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2880 bzero(iq, sizeof(*iq));
2883 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2887 free_fl_sdesc(sc, fl);
2889 if (mtx_initialized(&fl->fl_lock))
2890 mtx_destroy(&fl->fl_lock);
2892 bzero(fl, sizeof(*fl));
2899 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2902 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2904 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
2905 "bus address of descriptor ring");
2906 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2907 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
2908 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
2909 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I",
2910 "absolute id of the queue");
2911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2912 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I",
2913 "SGE context id of the queue");
2914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
2915 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
2920 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2921 struct sysctl_oid *oid, struct sge_fl *fl)
2923 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2925 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2927 children = SYSCTL_CHILDREN(oid);
2929 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2930 &fl->ba, "bus address of descriptor ring");
2931 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2932 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2933 "desc ring size in bytes");
2934 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2935 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2936 "SGE context id of the freelist");
2937 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2938 fl_pad ? 1 : 0, "padding enabled");
2939 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2940 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2941 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2942 0, "consumer index");
2943 if (fl->flags & FL_BUF_PACKING) {
2944 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2945 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2947 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2948 0, "producer index");
2949 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2950 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2951 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2952 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2953 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2954 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2955 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2956 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2957 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2958 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2962 alloc_fwq(struct adapter *sc)
2965 struct sge_iq *fwq = &sc->sge.fwq;
2966 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2967 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2969 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2970 if (sc->flags & IS_VF)
2973 intr_idx = sc->intr_count > 1 ? 1 : 0;
2974 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2976 device_printf(sc->dev,
2977 "failed to create firmware event queue: %d\n", rc);
2981 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2982 NULL, "firmware event queue");
2983 add_iq_sysctls(&sc->ctx, oid, fwq);
2989 free_fwq(struct adapter *sc)
2991 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2995 alloc_mgmtq(struct adapter *sc)
2998 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
3000 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3001 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3003 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
3004 NULL, "management queue");
3006 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
3007 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
3008 sc->sge.fwq.cntxt_id, name);
3009 rc = alloc_wrq(sc, NULL, mgmtq, oid);
3011 device_printf(sc->dev,
3012 "failed to create management queue: %d\n", rc);
3020 free_mgmtq(struct adapter *sc)
3023 return free_wrq(sc, &sc->sge.mgmtq);
3027 tnl_cong(struct port_info *pi, int drop)
3035 return (pi->rx_e_chan_map);
3039 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3040 struct sysctl_oid *oid)
3043 struct adapter *sc = vi->pi->adapter;
3044 struct sysctl_oid_list *children;
3047 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3048 tnl_cong(vi->pi, cong_drop));
3053 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3055 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3056 ("iq_base mismatch"));
3057 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3058 ("PF with non-zero iq_base"));
3061 * The freelist is just barely above the starvation threshold right now,
3062 * fill it up a bit more.
3065 refill_fl(sc, &rxq->fl, 128);
3066 FL_UNLOCK(&rxq->fl);
3068 #if defined(INET) || defined(INET6)
3069 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3072 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3074 if (vi->ifp->if_capenable & IFCAP_LRO)
3075 rxq->iq.flags |= IQ_LRO_ENABLED;
3079 children = SYSCTL_CHILDREN(oid);
3081 snprintf(name, sizeof(name), "%d", idx);
3082 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3084 children = SYSCTL_CHILDREN(oid);
3086 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3087 #if defined(INET) || defined(INET6)
3088 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3089 &rxq->lro.lro_queued, 0, NULL);
3090 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3091 &rxq->lro.lro_flushed, 0, NULL);
3093 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3094 &rxq->rxcsum, "# of times hardware assisted with checksum");
3095 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3096 CTLFLAG_RD, &rxq->vlan_extraction,
3097 "# of times hardware extracted 802.1Q tag");
3099 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3105 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3109 #if defined(INET) || defined(INET6)
3111 tcp_lro_free(&rxq->lro);
3112 rxq->lro.ifp = NULL;
3116 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3118 bzero(rxq, sizeof(*rxq));
3125 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3126 int intr_idx, int idx, struct sysctl_oid *oid)
3128 struct port_info *pi = vi->pi;
3130 struct sysctl_oid_list *children;
3133 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3137 children = SYSCTL_CHILDREN(oid);
3139 snprintf(name, sizeof(name), "%d", idx);
3140 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3142 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3143 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3149 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3153 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3155 bzero(ofld_rxq, sizeof(*ofld_rxq));
3163 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3164 int idx, struct sysctl_oid *oid)
3167 struct sysctl_oid_list *children;
3168 struct sysctl_ctx_list *ctx;
3171 struct adapter *sc = vi->pi->adapter;
3172 struct netmap_adapter *na = NA(vi->ifp);
3176 len = vi->qsize_rxq * IQ_ESIZE;
3177 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3178 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3182 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3183 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3184 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3190 nm_rxq->iq_cidx = 0;
3191 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3192 nm_rxq->iq_gen = F_RSPD_GEN;
3193 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3194 nm_rxq->fl_sidx = na->num_rx_desc;
3195 nm_rxq->intr_idx = intr_idx;
3196 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3199 children = SYSCTL_CHILDREN(oid);
3201 snprintf(name, sizeof(name), "%d", idx);
3202 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3204 children = SYSCTL_CHILDREN(oid);
3206 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3207 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3208 "I", "absolute id of the queue");
3209 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3210 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3211 "I", "SGE context id of the queue");
3212 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3213 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3216 children = SYSCTL_CHILDREN(oid);
3217 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3219 children = SYSCTL_CHILDREN(oid);
3221 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3222 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3223 "I", "SGE context id of the freelist");
3224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3225 &nm_rxq->fl_cidx, 0, "consumer index");
3226 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3227 &nm_rxq->fl_pidx, 0, "producer index");
3234 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3236 struct adapter *sc = vi->pi->adapter;
3238 if (vi->flags & VI_INIT_DONE)
3239 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3241 MPASS(nm_rxq->iq_cntxt_id == 0);
3243 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3245 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3252 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3253 struct sysctl_oid *oid)
3257 struct port_info *pi = vi->pi;
3258 struct adapter *sc = pi->adapter;
3259 struct netmap_adapter *na = NA(vi->ifp);
3261 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3263 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3264 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3265 &nm_txq->ba, (void **)&nm_txq->desc);
3269 nm_txq->pidx = nm_txq->cidx = 0;
3270 nm_txq->sidx = na->num_tx_desc;
3272 nm_txq->iqidx = iqidx;
3273 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3274 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3275 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3276 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3277 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3279 snprintf(name, sizeof(name), "%d", idx);
3280 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3281 NULL, "netmap tx queue");
3282 children = SYSCTL_CHILDREN(oid);
3284 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3285 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3286 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3287 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3289 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3290 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3297 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3299 struct adapter *sc = vi->pi->adapter;
3301 if (vi->flags & VI_INIT_DONE)
3302 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3304 MPASS(nm_txq->cntxt_id == 0);
3306 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3314 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3317 struct fw_eq_ctrl_cmd c;
3318 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3320 bzero(&c, sizeof(c));
3322 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3323 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3324 V_FW_EQ_CTRL_CMD_VFN(0));
3325 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3326 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3327 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3328 c.physeqid_pkd = htobe32(0);
3329 c.fetchszm_to_iqid =
3330 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3331 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3332 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3334 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3335 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3336 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
3337 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3338 c.eqaddr = htobe64(eq->ba);
3340 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3342 device_printf(sc->dev,
3343 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3346 eq->flags |= EQ_ALLOCATED;
3348 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3349 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3350 if (cntxt_id >= sc->sge.neq)
3351 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3352 cntxt_id, sc->sge.neq - 1);
3353 sc->sge.eqmap[cntxt_id] = eq;
3359 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3362 struct fw_eq_eth_cmd c;
3363 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3365 bzero(&c, sizeof(c));
3367 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3368 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3369 V_FW_EQ_ETH_CMD_VFN(0));
3370 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3371 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3372 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3373 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3374 c.fetchszm_to_iqid =
3375 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3376 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3377 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3378 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3379 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3380 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3381 c.eqaddr = htobe64(eq->ba);
3383 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3385 device_printf(vi->dev,
3386 "failed to create Ethernet egress queue: %d\n", rc);
3389 eq->flags |= EQ_ALLOCATED;
3391 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3392 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3393 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3394 if (cntxt_id >= sc->sge.neq)
3395 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3396 cntxt_id, sc->sge.neq - 1);
3397 sc->sge.eqmap[cntxt_id] = eq;
3402 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3404 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3407 struct fw_eq_ofld_cmd c;
3408 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3410 bzero(&c, sizeof(c));
3412 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3413 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3414 V_FW_EQ_OFLD_CMD_VFN(0));
3415 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3416 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3417 c.fetchszm_to_iqid =
3418 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3419 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3420 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3422 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3423 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3424 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3425 c.eqaddr = htobe64(eq->ba);
3427 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3429 device_printf(vi->dev,
3430 "failed to create egress queue for TCP offload: %d\n", rc);
3433 eq->flags |= EQ_ALLOCATED;
3435 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3436 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3437 if (cntxt_id >= sc->sge.neq)
3438 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3439 cntxt_id, sc->sge.neq - 1);
3440 sc->sge.eqmap[cntxt_id] = eq;
3447 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3452 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3454 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3455 len = qsize * EQ_ESIZE;
3456 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3457 &eq->ba, (void **)&eq->desc);
3461 eq->pidx = eq->cidx = 0;
3462 eq->equeqidx = eq->dbidx = 0;
3463 eq->doorbells = sc->doorbells;
3465 switch (eq->flags & EQ_TYPEMASK) {
3467 rc = ctrl_eq_alloc(sc, eq);
3471 rc = eth_eq_alloc(sc, vi, eq);
3474 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3476 rc = ofld_eq_alloc(sc, vi, eq);
3481 panic("%s: invalid eq type %d.", __func__,
3482 eq->flags & EQ_TYPEMASK);
3485 device_printf(sc->dev,
3486 "failed to allocate egress queue(%d): %d\n",
3487 eq->flags & EQ_TYPEMASK, rc);
3490 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3491 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3492 isset(&eq->doorbells, DOORBELL_WCWR)) {
3493 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3494 uint32_t mask = (1 << s_qpp) - 1;
3495 volatile uint8_t *udb;
3497 udb = sc->udbs_base + UDBS_DB_OFFSET;
3498 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3499 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3500 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3501 clrbit(&eq->doorbells, DOORBELL_WCWR);
3503 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3506 eq->udb = (volatile void *)udb;
3513 free_eq(struct adapter *sc, struct sge_eq *eq)
3517 if (eq->flags & EQ_ALLOCATED) {
3518 switch (eq->flags & EQ_TYPEMASK) {
3520 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3525 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3529 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3531 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3537 panic("%s: invalid eq type %d.", __func__,
3538 eq->flags & EQ_TYPEMASK);
3541 device_printf(sc->dev,
3542 "failed to free egress queue (%d): %d\n",
3543 eq->flags & EQ_TYPEMASK, rc);
3546 eq->flags &= ~EQ_ALLOCATED;
3549 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3551 if (mtx_initialized(&eq->eq_lock))
3552 mtx_destroy(&eq->eq_lock);
3554 bzero(eq, sizeof(*eq));
3559 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3560 struct sysctl_oid *oid)
3563 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3564 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3566 rc = alloc_eq(sc, vi, &wrq->eq);
3571 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3572 TAILQ_INIT(&wrq->incomplete_wrs);
3573 STAILQ_INIT(&wrq->wr_list);
3574 wrq->nwr_pending = 0;
3575 wrq->ndesc_needed = 0;
3577 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3578 &wrq->eq.ba, "bus address of descriptor ring");
3579 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3580 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3581 "desc ring size in bytes");
3582 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3583 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3585 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3588 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3590 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3591 wrq->eq.sidx, "status page index");
3592 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3593 &wrq->tx_wrs_direct, "# of work requests (direct)");
3594 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3595 &wrq->tx_wrs_copied, "# of work requests (copied)");
3596 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3597 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3603 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3607 rc = free_eq(sc, &wrq->eq);
3611 bzero(wrq, sizeof(*wrq));
3616 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3617 struct sysctl_oid *oid)
3620 struct port_info *pi = vi->pi;
3621 struct adapter *sc = pi->adapter;
3622 struct sge_eq *eq = &txq->eq;
3624 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3626 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3629 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3633 rc = alloc_eq(sc, vi, eq);
3635 mp_ring_free(txq->r);
3640 /* Can't fail after this point. */
3643 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3645 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3646 ("eq_base mismatch"));
3647 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3648 ("PF with non-zero eq_base"));
3650 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3652 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3653 if (sc->flags & IS_VF)
3654 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3655 V_TXPKT_INTF(pi->tx_chan));
3657 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3658 V_TXPKT_INTF(pi->tx_chan) |
3659 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3660 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3661 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3663 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3666 snprintf(name, sizeof(name), "%d", idx);
3667 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3669 children = SYSCTL_CHILDREN(oid);
3671 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3672 &eq->ba, "bus address of descriptor ring");
3673 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3674 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3675 "desc ring size in bytes");
3676 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3677 &eq->abs_id, 0, "absolute id of the queue");
3678 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3679 &eq->cntxt_id, 0, "SGE context id of the queue");
3680 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3681 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3683 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3684 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3686 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3687 eq->sidx, "status page index");
3689 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3690 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3691 "traffic class (-1 means none)");
3693 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3694 &txq->txcsum, "# of times hardware assisted with checksum");
3695 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3696 CTLFLAG_RD, &txq->vlan_insertion,
3697 "# of times hardware inserted 802.1Q tag");
3698 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3699 &txq->tso_wrs, "# of TSO work requests");
3700 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3701 &txq->imm_wrs, "# of work requests with immediate data");
3702 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3703 &txq->sgl_wrs, "# of work requests with direct SGL");
3704 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3705 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3706 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3707 CTLFLAG_RD, &txq->txpkts0_wrs,
3708 "# of txpkts (type 0) work requests");
3709 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3710 CTLFLAG_RD, &txq->txpkts1_wrs,
3711 "# of txpkts (type 1) work requests");
3712 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3713 CTLFLAG_RD, &txq->txpkts0_pkts,
3714 "# of frames tx'd using type0 txpkts work requests");
3715 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3716 CTLFLAG_RD, &txq->txpkts1_pkts,
3717 "# of frames tx'd using type1 txpkts work requests");
3719 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3720 CTLFLAG_RD, &txq->r->enqueues,
3721 "# of enqueues to the mp_ring for this queue");
3722 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3723 CTLFLAG_RD, &txq->r->drops,
3724 "# of drops in the mp_ring for this queue");
3725 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3726 CTLFLAG_RD, &txq->r->starts,
3727 "# of normal consumer starts in the mp_ring for this queue");
3728 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3729 CTLFLAG_RD, &txq->r->stalls,
3730 "# of consumer stalls in the mp_ring for this queue");
3731 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3732 CTLFLAG_RD, &txq->r->restarts,
3733 "# of consumer restarts in the mp_ring for this queue");
3734 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3735 CTLFLAG_RD, &txq->r->abdications,
3736 "# of consumer abdications in the mp_ring for this queue");
3742 free_txq(struct vi_info *vi, struct sge_txq *txq)
3745 struct adapter *sc = vi->pi->adapter;
3746 struct sge_eq *eq = &txq->eq;
3748 rc = free_eq(sc, eq);
3752 sglist_free(txq->gl);
3753 free(txq->sdesc, M_CXGBE);
3754 mp_ring_free(txq->r);
3756 bzero(txq, sizeof(*txq));
3761 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3763 bus_addr_t *ba = arg;
3766 ("%s meant for single segment mappings only.", __func__));
3768 *ba = error ? 0 : segs->ds_addr;
3772 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3776 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3780 v = fl->dbval | V_PIDX(n);
3782 *fl->udb = htole32(v);
3784 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3785 IDXINCR(fl->dbidx, n, fl->sidx);
3789 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
3790 * recycled do not count towards this allocation budget.
3792 * Returns non-zero to indicate that this freelist should be added to the list
3793 * of starving freelists.
3796 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3799 struct fl_sdesc *sd;
3802 struct cluster_layout *cll;
3803 struct sw_zone_info *swz;
3804 struct cluster_metadata *clm;
3806 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3808 FL_LOCK_ASSERT_OWNED(fl);
3811 * We always stop at the beginning of the hardware descriptor that's just
3812 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3813 * which would mean an empty freelist to the chip.
3815 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3816 if (fl->pidx == max_pidx * 8)
3819 d = &fl->desc[fl->pidx];
3820 sd = &fl->sdesc[fl->pidx];
3821 cll = &fl->cll_def; /* default layout */
3822 swz = &sc->sge.sw_zone_info[cll->zidx];
3826 if (sd->cl != NULL) {
3828 if (sd->nmbuf == 0) {
3830 * Fast recycle without involving any atomics on
3831 * the cluster's metadata (if the cluster has
3832 * metadata). This happens when all frames
3833 * received in the cluster were small enough to
3834 * fit within a single mbuf each.
3836 fl->cl_fast_recycled++;
3838 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3840 MPASS(clm->refcount == 1);
3846 * Cluster is guaranteed to have metadata. Clusters
3847 * without metadata always take the fast recycle path
3848 * when they're recycled.
3850 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3853 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3855 counter_u64_add(extfree_rels, 1);
3858 sd->cl = NULL; /* gave up my reference */
3860 MPASS(sd->cl == NULL);
3862 cl = uma_zalloc(swz->zone, M_NOWAIT);
3863 if (__predict_false(cl == NULL)) {
3864 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3865 fl->cll_def.zidx == fl->cll_alt.zidx)
3868 /* fall back to the safe zone */
3870 swz = &sc->sge.sw_zone_info[cll->zidx];
3876 pa = pmap_kextract((vm_offset_t)cl);
3880 *d = htobe64(pa | cll->hwidx);
3881 clm = cl_metadata(sc, fl, cll, cl);
3893 if (__predict_false(++fl->pidx % 8 == 0)) {
3894 uint16_t pidx = fl->pidx / 8;
3896 if (__predict_false(pidx == fl->sidx)) {
3902 if (pidx == max_pidx)
3905 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3910 if (fl->pidx / 8 != fl->dbidx)
3913 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3917 * Attempt to refill all starving freelists.
3920 refill_sfl(void *arg)
3922 struct adapter *sc = arg;
3923 struct sge_fl *fl, *fl_temp;
3925 mtx_assert(&sc->sfl_lock, MA_OWNED);
3926 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3928 refill_fl(sc, fl, 64);
3929 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3930 TAILQ_REMOVE(&sc->sfl, fl, link);
3931 fl->flags &= ~FL_STARVING;
3936 if (!TAILQ_EMPTY(&sc->sfl))
3937 callout_schedule(&sc->sfl_callout, hz / 5);
3941 alloc_fl_sdesc(struct sge_fl *fl)
3944 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3951 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3953 struct fl_sdesc *sd;
3954 struct cluster_metadata *clm;
3955 struct cluster_layout *cll;
3959 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3964 clm = cl_metadata(sc, fl, cll, sd->cl);
3966 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3967 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3968 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3969 counter_u64_add(extfree_rels, 1);
3974 free(fl->sdesc, M_CXGBE);
3979 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3986 rc = sglist_append_mbuf(gl, m);
3987 if (__predict_false(rc != 0)) {
3988 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3989 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3992 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3993 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3994 mbuf_nsegs(m), gl->sg_nseg));
3995 KASSERT(gl->sg_nseg > 0 &&
3996 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3997 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3998 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4002 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4005 txpkt_len16(u_int nsegs, u_int tso)
4011 nsegs--; /* first segment is part of ulptx_sgl */
4012 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4013 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4015 n += sizeof(struct cpl_tx_pkt_lso_core);
4017 return (howmany(n, 16));
4021 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4025 txpkt_vm_len16(u_int nsegs, u_int tso)
4031 nsegs--; /* first segment is part of ulptx_sgl */
4032 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4033 sizeof(struct cpl_tx_pkt_core) +
4034 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4036 n += sizeof(struct cpl_tx_pkt_lso_core);
4038 return (howmany(n, 16));
4042 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4046 txpkts0_len16(u_int nsegs)
4052 nsegs--; /* first segment is part of ulptx_sgl */
4053 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4054 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4055 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4057 return (howmany(n, 16));
4061 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4069 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4071 return (howmany(n, 16));
4075 imm_payload(u_int ndesc)
4079 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4080 sizeof(struct cpl_tx_pkt_core);
4086 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4087 * software descriptor, and advance the pidx. It is guaranteed that enough
4088 * descriptors are available.
4090 * The return value is the # of hardware descriptors used.
4093 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4094 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4096 struct sge_eq *eq = &txq->eq;
4097 struct tx_sdesc *txsd;
4098 struct cpl_tx_pkt_core *cpl;
4099 uint32_t ctrl; /* used in many unrelated places */
4101 int csum_type, len16, ndesc, pktlen, nsegs;
4104 TXQ_LOCK_ASSERT_OWNED(txq);
4106 MPASS(available > 0 && available < eq->sidx);
4108 len16 = mbuf_len16(m0);
4109 nsegs = mbuf_nsegs(m0);
4110 pktlen = m0->m_pkthdr.len;
4111 ctrl = sizeof(struct cpl_tx_pkt_core);
4113 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4114 ndesc = howmany(len16, EQ_ESIZE / 16);
4115 MPASS(ndesc <= available);
4117 /* Firmware work request header */
4118 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4119 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4120 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4122 ctrl = V_FW_WR_LEN16(len16);
4123 wr->equiq_to_len16 = htobe32(ctrl);
4128 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4129 * vlantci is ignored unless the ethtype is 0x8100, so it's
4130 * simpler to always copy it rather than making it
4131 * conditional. Also, it seems that we do not have to set
4132 * vlantci or fake the ethtype when doing VLAN tag insertion.
4134 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4137 if (needs_tso(m0)) {
4138 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4140 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4141 m0->m_pkthdr.l4hlen > 0,
4142 ("%s: mbuf %p needs TSO but missing header lengths",
4145 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4146 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4147 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4148 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4149 ctrl |= V_LSO_ETHHDR_LEN(1);
4150 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4153 lso->lso_ctrl = htobe32(ctrl);
4154 lso->ipid_ofst = htobe16(0);
4155 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4156 lso->seqno_offset = htobe32(0);
4157 lso->len = htobe32(pktlen);
4159 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4160 csum_type = TX_CSUM_TCPIP6;
4162 csum_type = TX_CSUM_TCPIP;
4164 cpl = (void *)(lso + 1);
4168 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4169 csum_type = TX_CSUM_TCPIP;
4170 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4171 csum_type = TX_CSUM_UDPIP;
4172 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4173 csum_type = TX_CSUM_TCPIP6;
4174 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4175 csum_type = TX_CSUM_UDPIP6;
4177 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4179 * XXX: The firmware appears to stomp on the
4180 * fragment/flags field of the IP header when
4181 * using TX_CSUM_IP. Fall back to doing
4182 * software checksums.
4190 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4191 offsetof(struct ip, ip_sum));
4192 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4193 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4194 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4198 cpl = (void *)(wr + 1);
4201 /* Checksum offload */
4203 if (needs_l3_csum(m0) == 0)
4204 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4205 if (csum_type >= 0) {
4206 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4207 ("%s: mbuf %p needs checksum offload but missing header lengths",
4210 if (chip_id(sc) <= CHELSIO_T5) {
4211 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4214 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4217 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4218 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4220 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4221 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4222 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4223 txq->txcsum++; /* some hardware assistance provided */
4225 /* VLAN tag insertion */
4226 if (needs_vlan_insertion(m0)) {
4227 ctrl1 |= F_TXPKT_VLAN_VLD |
4228 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4229 txq->vlan_insertion++;
4233 cpl->ctrl0 = txq->cpl_ctrl0;
4235 cpl->len = htobe16(pktlen);
4236 cpl->ctrl1 = htobe64(ctrl1);
4239 dst = (void *)(cpl + 1);
4242 * A packet using TSO will use up an entire descriptor for the
4243 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4244 * If this descriptor is the last descriptor in the ring, wrap
4245 * around to the front of the ring explicitly for the start of
4248 if (dst == (void *)&eq->desc[eq->sidx]) {
4249 dst = (void *)&eq->desc[0];
4250 write_gl_to_txd(txq, m0, &dst, 0);
4252 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4257 txsd = &txq->sdesc[eq->pidx];
4259 txsd->desc_used = ndesc;
4265 * Write a txpkt WR for this packet to the hardware descriptors, update the
4266 * software descriptor, and advance the pidx. It is guaranteed that enough
4267 * descriptors are available.
4269 * The return value is the # of hardware descriptors used.
4272 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4273 struct mbuf *m0, u_int available)
4275 struct sge_eq *eq = &txq->eq;
4276 struct tx_sdesc *txsd;
4277 struct cpl_tx_pkt_core *cpl;
4278 uint32_t ctrl; /* used in many unrelated places */
4280 int len16, ndesc, pktlen, nsegs;
4283 TXQ_LOCK_ASSERT_OWNED(txq);
4285 MPASS(available > 0 && available < eq->sidx);
4287 len16 = mbuf_len16(m0);
4288 nsegs = mbuf_nsegs(m0);
4289 pktlen = m0->m_pkthdr.len;
4290 ctrl = sizeof(struct cpl_tx_pkt_core);
4292 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4293 else if (pktlen <= imm_payload(2) && available >= 2) {
4294 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4296 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4297 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4300 ndesc = howmany(len16, EQ_ESIZE / 16);
4301 MPASS(ndesc <= available);
4303 /* Firmware work request header */
4304 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4305 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4306 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4308 ctrl = V_FW_WR_LEN16(len16);
4309 wr->equiq_to_len16 = htobe32(ctrl);
4312 if (needs_tso(m0)) {
4313 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4315 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4316 m0->m_pkthdr.l4hlen > 0,
4317 ("%s: mbuf %p needs TSO but missing header lengths",
4320 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4321 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4322 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4323 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4324 ctrl |= V_LSO_ETHHDR_LEN(1);
4325 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4328 lso->lso_ctrl = htobe32(ctrl);
4329 lso->ipid_ofst = htobe16(0);
4330 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4331 lso->seqno_offset = htobe32(0);
4332 lso->len = htobe32(pktlen);
4334 cpl = (void *)(lso + 1);
4338 cpl = (void *)(wr + 1);
4340 /* Checksum offload */
4342 if (needs_l3_csum(m0) == 0)
4343 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4344 if (needs_l4_csum(m0) == 0)
4345 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4346 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4347 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4348 txq->txcsum++; /* some hardware assistance provided */
4350 /* VLAN tag insertion */
4351 if (needs_vlan_insertion(m0)) {
4352 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4353 txq->vlan_insertion++;
4357 cpl->ctrl0 = txq->cpl_ctrl0;
4359 cpl->len = htobe16(pktlen);
4360 cpl->ctrl1 = htobe64(ctrl1);
4363 dst = (void *)(cpl + 1);
4366 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4371 for (m = m0; m != NULL; m = m->m_next) {
4372 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4378 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4385 txsd = &txq->sdesc[eq->pidx];
4387 txsd->desc_used = ndesc;
4393 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4395 u_int needed, nsegs1, nsegs2, l1, l2;
4397 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4400 nsegs1 = mbuf_nsegs(m);
4401 nsegs2 = mbuf_nsegs(n);
4402 if (nsegs1 + nsegs2 == 2) {
4404 l1 = l2 = txpkts1_len16();
4407 l1 = txpkts0_len16(nsegs1);
4408 l2 = txpkts0_len16(nsegs2);
4410 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4411 needed = howmany(txp->len16, EQ_ESIZE / 16);
4412 if (needed > SGE_MAX_WR_NDESC || needed > available)
4415 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4416 if (txp->plen > 65535)
4420 set_mbuf_len16(m, l1);
4421 set_mbuf_len16(n, l2);
4427 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4429 u_int plen, len16, needed, nsegs;
4431 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4433 nsegs = mbuf_nsegs(m);
4434 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4437 plen = txp->plen + m->m_pkthdr.len;
4441 if (txp->wr_type == 0)
4442 len16 = txpkts0_len16(nsegs);
4444 len16 = txpkts1_len16();
4445 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4446 if (needed > SGE_MAX_WR_NDESC || needed > available)
4451 txp->len16 += len16;
4452 set_mbuf_len16(m, len16);
4458 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4459 * the software descriptor, and advance the pidx. It is guaranteed that enough
4460 * descriptors are available.
4462 * The return value is the # of hardware descriptors used.
4465 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4466 struct mbuf *m0, const struct txpkts *txp, u_int available)
4468 struct sge_eq *eq = &txq->eq;
4469 struct tx_sdesc *txsd;
4470 struct cpl_tx_pkt_core *cpl;
4473 int ndesc, checkwrap;
4477 TXQ_LOCK_ASSERT_OWNED(txq);
4478 MPASS(txp->npkt > 0);
4479 MPASS(txp->plen < 65536);
4481 MPASS(m0->m_nextpkt != NULL);
4482 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4483 MPASS(available > 0 && available < eq->sidx);
4485 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4486 MPASS(ndesc <= available);
4488 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4489 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4490 ctrl = V_FW_WR_LEN16(txp->len16);
4491 wr->equiq_to_len16 = htobe32(ctrl);
4492 wr->plen = htobe16(txp->plen);
4493 wr->npkt = txp->npkt;
4495 wr->type = txp->wr_type;
4499 * At this point we are 16B into a hardware descriptor. If checkwrap is
4500 * set then we know the WR is going to wrap around somewhere. We'll
4501 * check for that at appropriate points.
4503 checkwrap = eq->sidx - ndesc < eq->pidx;
4504 for (m = m0; m != NULL; m = m->m_nextpkt) {
4505 if (txp->wr_type == 0) {
4506 struct ulp_txpkt *ulpmc;
4507 struct ulptx_idata *ulpsc;
4509 /* ULP master command */
4511 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4512 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4513 ulpmc->len = htobe32(mbuf_len16(m));
4515 /* ULP subcommand */
4516 ulpsc = (void *)(ulpmc + 1);
4517 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4519 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4521 cpl = (void *)(ulpsc + 1);
4523 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4524 cpl = (void *)&eq->desc[0];
4529 /* Checksum offload */
4531 if (needs_l3_csum(m) == 0)
4532 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4533 if (needs_l4_csum(m) == 0)
4534 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4535 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4536 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4537 txq->txcsum++; /* some hardware assistance provided */
4539 /* VLAN tag insertion */
4540 if (needs_vlan_insertion(m)) {
4541 ctrl1 |= F_TXPKT_VLAN_VLD |
4542 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4543 txq->vlan_insertion++;
4547 cpl->ctrl0 = txq->cpl_ctrl0;
4549 cpl->len = htobe16(m->m_pkthdr.len);
4550 cpl->ctrl1 = htobe64(ctrl1);
4554 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4555 flitp = (void *)&eq->desc[0];
4557 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4561 if (txp->wr_type == 0) {
4562 txq->txpkts0_pkts += txp->npkt;
4565 txq->txpkts1_pkts += txp->npkt;
4569 txsd = &txq->sdesc[eq->pidx];
4571 txsd->desc_used = ndesc;
4577 * If the SGL ends on an address that is not 16 byte aligned, this function will
4578 * add a 0 filled flit at the end.
4581 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4583 struct sge_eq *eq = &txq->eq;
4584 struct sglist *gl = txq->gl;
4585 struct sglist_seg *seg;
4586 __be64 *flitp, *wrap;
4587 struct ulptx_sgl *usgl;
4588 int i, nflits, nsegs;
4590 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4591 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4592 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4593 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4596 nsegs = gl->sg_nseg;
4599 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4600 flitp = (__be64 *)(*to);
4601 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4602 seg = &gl->sg_segs[0];
4603 usgl = (void *)flitp;
4606 * We start at a 16 byte boundary somewhere inside the tx descriptor
4607 * ring, so we're at least 16 bytes away from the status page. There is
4608 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4611 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4612 V_ULPTX_NSGE(nsegs));
4613 usgl->len0 = htobe32(seg->ss_len);
4614 usgl->addr0 = htobe64(seg->ss_paddr);
4617 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4619 /* Won't wrap around at all */
4621 for (i = 0; i < nsegs - 1; i++, seg++) {
4622 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4623 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4626 usgl->sge[i / 2].len[1] = htobe32(0);
4630 /* Will wrap somewhere in the rest of the SGL */
4632 /* 2 flits already written, write the rest flit by flit */
4633 flitp = (void *)(usgl + 1);
4634 for (i = 0; i < nflits - 2; i++) {
4636 flitp = (void *)eq->desc;
4637 *flitp++ = get_flit(seg, nsegs - 1, i);
4642 MPASS(((uintptr_t)flitp) & 0xf);
4646 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4647 if (__predict_false(flitp == wrap))
4648 *to = (void *)eq->desc;
4650 *to = (void *)flitp;
4654 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4657 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4658 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4660 if (__predict_true((uintptr_t)(*to) + len <=
4661 (uintptr_t)&eq->desc[eq->sidx])) {
4662 bcopy(from, *to, len);
4665 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4667 bcopy(from, *to, portion);
4669 portion = len - portion; /* remaining */
4670 bcopy(from, (void *)eq->desc, portion);
4671 (*to) = (caddr_t)eq->desc + portion;
4676 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4684 clrbit(&db, DOORBELL_WCWR);
4687 switch (ffs(db) - 1) {
4689 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4692 case DOORBELL_WCWR: {
4693 volatile uint64_t *dst, *src;
4697 * Queues whose 128B doorbell segment fits in the page do not
4698 * use relative qid (udb_qid is always 0). Only queues with
4699 * doorbell segments can do WCWR.
4701 KASSERT(eq->udb_qid == 0 && n == 1,
4702 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4703 __func__, eq->doorbells, n, eq->dbidx, eq));
4705 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4708 src = (void *)&eq->desc[i];
4709 while (src != (void *)&eq->desc[i + 1])
4715 case DOORBELL_UDBWC:
4716 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4721 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4722 V_QID(eq->cntxt_id) | V_PIDX(n));
4726 IDXINCR(eq->dbidx, n, eq->sidx);
4730 reclaimable_tx_desc(struct sge_eq *eq)
4734 hw_cidx = read_hw_cidx(eq);
4735 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4739 total_available_tx_desc(struct sge_eq *eq)
4741 uint16_t hw_cidx, pidx;
4743 hw_cidx = read_hw_cidx(eq);
4746 if (pidx == hw_cidx)
4747 return (eq->sidx - 1);
4749 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4752 static inline uint16_t
4753 read_hw_cidx(struct sge_eq *eq)
4755 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4756 uint16_t cidx = spg->cidx; /* stable snapshot */
4758 return (be16toh(cidx));
4762 * Reclaim 'n' descriptors approximately.
4765 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4767 struct tx_sdesc *txsd;
4768 struct sge_eq *eq = &txq->eq;
4769 u_int can_reclaim, reclaimed;
4771 TXQ_LOCK_ASSERT_OWNED(txq);
4775 can_reclaim = reclaimable_tx_desc(eq);
4776 while (can_reclaim && reclaimed < n) {
4778 struct mbuf *m, *nextpkt;
4780 txsd = &txq->sdesc[eq->cidx];
4781 ndesc = txsd->desc_used;
4783 /* Firmware doesn't return "partial" credits. */
4784 KASSERT(can_reclaim >= ndesc,
4785 ("%s: unexpected number of credits: %d, %d",
4786 __func__, can_reclaim, ndesc));
4788 for (m = txsd->m; m != NULL; m = nextpkt) {
4789 nextpkt = m->m_nextpkt;
4790 m->m_nextpkt = NULL;
4794 can_reclaim -= ndesc;
4795 IDXINCR(eq->cidx, ndesc, eq->sidx);
4802 tx_reclaim(void *arg, int n)
4804 struct sge_txq *txq = arg;
4805 struct sge_eq *eq = &txq->eq;
4808 if (TXQ_TRYLOCK(txq) == 0)
4810 n = reclaim_tx_descs(txq, 32);
4811 if (eq->cidx == eq->pidx)
4812 eq->equeqidx = eq->pidx;
4818 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4820 int i = (idx / 3) * 2;
4826 rc = (uint64_t)segs[i].ss_len << 32;
4828 rc |= (uint64_t)(segs[i + 1].ss_len);
4830 return (htobe64(rc));
4833 return (htobe64(segs[i].ss_paddr));
4835 return (htobe64(segs[i + 1].ss_paddr));
4842 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4844 int8_t zidx, hwidx, idx;
4845 uint16_t region1, region3;
4846 int spare, spare_needed, n;
4847 struct sw_zone_info *swz;
4848 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4851 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4852 * large enough for the max payload and cluster metadata. Otherwise
4853 * settle for the largest bufsize that leaves enough room in the cluster
4856 * Without buffer packing: Look for the smallest zone which has a
4857 * bufsize large enough for the max payload. Settle for the largest
4858 * bufsize available if there's nothing big enough for max payload.
4860 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4861 swz = &sc->sge.sw_zone_info[0];
4863 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4864 if (swz->size > largest_rx_cluster) {
4865 if (__predict_true(hwidx != -1))
4869 * This is a misconfiguration. largest_rx_cluster is
4870 * preventing us from finding a refill source. See
4871 * dev.t5nex.<n>.buffer_sizes to figure out why.
4873 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4874 " refill source for fl %p (dma %u). Ignored.\n",
4875 largest_rx_cluster, fl, maxp);
4877 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4878 hwb = &hwb_list[idx];
4879 spare = swz->size - hwb->size;
4880 if (spare < spare_needed)
4883 hwidx = idx; /* best option so far */
4884 if (hwb->size >= maxp) {
4886 if ((fl->flags & FL_BUF_PACKING) == 0)
4887 goto done; /* stop looking (not packing) */
4889 if (swz->size >= safest_rx_cluster)
4890 goto done; /* stop looking (packing) */
4892 break; /* keep looking, next zone */
4896 /* A usable hwidx has been located. */
4898 hwb = &hwb_list[hwidx];
4900 swz = &sc->sge.sw_zone_info[zidx];
4902 region3 = swz->size - hwb->size;
4905 * Stay within this zone and see if there is a better match when mbuf
4906 * inlining is allowed. Remember that the hwidx's are sorted in
4907 * decreasing order of size (so in increasing order of spare area).
4909 for (idx = hwidx; idx != -1; idx = hwb->next) {
4910 hwb = &hwb_list[idx];
4911 spare = swz->size - hwb->size;
4913 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4917 * Do not inline mbufs if doing so would violate the pad/pack
4918 * boundary alignment requirement.
4920 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4922 if (fl->flags & FL_BUF_PACKING &&
4923 (MSIZE % sc->params.sge.pack_boundary) != 0)
4926 if (spare < CL_METADATA_SIZE + MSIZE)
4928 n = (spare - CL_METADATA_SIZE) / MSIZE;
4929 if (n > howmany(hwb->size, maxp))
4933 if (fl->flags & FL_BUF_PACKING) {
4934 region1 = n * MSIZE;
4935 region3 = spare - region1;
4938 region3 = spare - region1;
4943 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4944 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4945 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4946 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4947 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4948 sc->sge.sw_zone_info[zidx].size,
4949 ("%s: bad buffer layout for fl %p, maxp %d. "
4950 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4951 sc->sge.sw_zone_info[zidx].size, region1,
4952 sc->sge.hw_buf_info[hwidx].size, region3));
4953 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4954 KASSERT(region3 >= CL_METADATA_SIZE,
4955 ("%s: no room for metadata. fl %p, maxp %d; "
4956 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4957 sc->sge.sw_zone_info[zidx].size, region1,
4958 sc->sge.hw_buf_info[hwidx].size, region3));
4959 KASSERT(region1 % MSIZE == 0,
4960 ("%s: bad mbuf region for fl %p, maxp %d. "
4961 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4962 sc->sge.sw_zone_info[zidx].size, region1,
4963 sc->sge.hw_buf_info[hwidx].size, region3));
4966 fl->cll_def.zidx = zidx;
4967 fl->cll_def.hwidx = hwidx;
4968 fl->cll_def.region1 = region1;
4969 fl->cll_def.region3 = region3;
4973 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4975 struct sge *s = &sc->sge;
4976 struct hw_buf_info *hwb;
4977 struct sw_zone_info *swz;
4981 if (fl->flags & FL_BUF_PACKING)
4982 hwidx = s->safe_hwidx2; /* with room for metadata */
4983 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4984 hwidx = s->safe_hwidx2;
4985 hwb = &s->hw_buf_info[hwidx];
4986 swz = &s->sw_zone_info[hwb->zidx];
4987 spare = swz->size - hwb->size;
4989 /* no good if there isn't room for an mbuf as well */
4990 if (spare < CL_METADATA_SIZE + MSIZE)
4991 hwidx = s->safe_hwidx1;
4993 hwidx = s->safe_hwidx1;
4996 /* No fallback source */
4997 fl->cll_alt.hwidx = -1;
4998 fl->cll_alt.zidx = -1;
5003 hwb = &s->hw_buf_info[hwidx];
5004 swz = &s->sw_zone_info[hwb->zidx];
5005 spare = swz->size - hwb->size;
5006 fl->cll_alt.hwidx = hwidx;
5007 fl->cll_alt.zidx = hwb->zidx;
5008 if (allow_mbufs_in_cluster &&
5009 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5010 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5012 fl->cll_alt.region1 = 0;
5013 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5017 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5019 mtx_lock(&sc->sfl_lock);
5021 if ((fl->flags & FL_DOOMED) == 0) {
5022 fl->flags |= FL_STARVING;
5023 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5024 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5027 mtx_unlock(&sc->sfl_lock);
5031 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5033 struct sge_wrq *wrq = (void *)eq;
5035 atomic_readandclear_int(&eq->equiq);
5036 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5040 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5042 struct sge_txq *txq = (void *)eq;
5044 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5046 atomic_readandclear_int(&eq->equiq);
5047 mp_ring_check_drainage(txq->r, 0);
5048 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5052 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5055 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5056 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5057 struct adapter *sc = iq->adapter;
5058 struct sge *s = &sc->sge;
5060 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5061 &handle_wrq_egr_update, &handle_eth_egr_update,
5062 &handle_wrq_egr_update};
5064 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5067 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5068 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5073 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5074 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5075 offsetof(struct cpl_fw6_msg, data));
5078 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5080 struct adapter *sc = iq->adapter;
5081 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5083 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5086 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5087 const struct rss_header *rss2;
5089 rss2 = (const struct rss_header *)&cpl->data[0];
5090 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5093 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5097 * t4_handle_wrerr_rpl - process a FW work request error message
5098 * @adap: the adapter
5099 * @rpl: start of the FW message
5102 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5104 u8 opcode = *(const u8 *)rpl;
5105 const struct fw_error_cmd *e = (const void *)rpl;
5108 if (opcode != FW_ERROR_CMD) {
5110 "%s: Received WRERR_RPL message with opcode %#x\n",
5111 device_get_nameunit(adap->dev), opcode);
5114 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5115 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5117 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5118 case FW_ERROR_TYPE_EXCEPTION:
5119 log(LOG_ERR, "exception info:\n");
5120 for (i = 0; i < nitems(e->u.exception.info); i++)
5121 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5122 be32toh(e->u.exception.info[i]));
5125 case FW_ERROR_TYPE_HWMODULE:
5126 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5127 be32toh(e->u.hwmodule.regaddr),
5128 be32toh(e->u.hwmodule.regval));
5130 case FW_ERROR_TYPE_WR:
5131 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5132 be16toh(e->u.wr.cidx),
5133 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5134 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5135 be32toh(e->u.wr.eqid));
5136 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5137 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5141 case FW_ERROR_TYPE_ACL:
5142 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5143 be16toh(e->u.acl.cidx),
5144 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5145 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5146 be32toh(e->u.acl.eqid),
5147 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5149 for (i = 0; i < nitems(e->u.acl.val); i++)
5150 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5154 log(LOG_ERR, "type %#x\n",
5155 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5162 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5164 uint16_t *id = arg1;
5167 return sysctl_handle_int(oidp, &i, 0, req);
5171 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5173 struct sge *s = arg1;
5174 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5175 struct sw_zone_info *swz = &s->sw_zone_info[0];
5180 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5181 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5182 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5187 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5191 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5197 sysctl_tc(SYSCTL_HANDLER_ARGS)
5199 struct vi_info *vi = arg1;
5200 struct port_info *pi;
5202 struct sge_txq *txq;
5203 struct tx_cl_rl_params *tc;
5204 int qidx = arg2, rc, tc_idx;
5205 uint32_t fw_queue, fw_class;
5207 MPASS(qidx >= 0 && qidx < vi->ntxq);
5210 txq = &sc->sge.txq[vi->first_txq + qidx];
5212 tc_idx = txq->tc_idx;
5213 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5214 if (rc != 0 || req->newptr == NULL)
5217 if (sc->flags & IS_VF)
5220 /* Note that -1 is legitimate input (it means unbind). */
5221 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5224 mtx_lock(&sc->tc_lock);
5225 if (tc_idx == txq->tc_idx) {
5226 rc = 0; /* No change, nothing to do. */
5230 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5231 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5232 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5235 fw_class = 0xffffffff; /* Unbind. */
5238 * Bind to a different class.
5240 tc = &pi->sched_params->cl_rl[tc_idx];
5241 if (tc->flags & TX_CLRL_ERROR) {
5242 /* Previous attempt to set the cl-rl params failed. */
5247 * Ok to proceed. Place a reference on the new class
5248 * while still holding on to the reference on the
5249 * previous class, if any.
5255 mtx_unlock(&sc->tc_lock);
5257 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5260 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5261 end_synchronized_op(sc, 0);
5263 mtx_lock(&sc->tc_lock);
5265 if (txq->tc_idx != -1) {
5266 tc = &pi->sched_params->cl_rl[txq->tc_idx];
5267 MPASS(tc->refcount > 0);
5270 txq->tc_idx = tc_idx;
5271 } else if (tc_idx != -1) {
5272 tc = &pi->sched_params->cl_rl[tc_idx];
5273 MPASS(tc->refcount > 0);
5277 mtx_unlock(&sc->tc_lock);