2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/queue.h>
43 #include <sys/taskqueue.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
72 #ifdef T4_PKT_TIMESTAMP
73 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
75 #define RX_COPY_THRESHOLD MINCLSIZE
79 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
80 * 0-7 are valid values.
83 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
86 * Pad ethernet payload up to this boundary.
87 * -1: driver should figure out a good value.
89 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
92 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
96 * -1: driver should figure out a good value.
97 * 64 or 128 are the only other valid values.
100 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
104 * -1: no congestion feedback (not recommended).
105 * 0: backpressure the channel instead of dropping packets right away.
106 * 1: no backpressure, drop packets for the congested queue immediately.
108 static int cong_drop = 0;
109 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
112 * Deliver multiple frames in the same free list buffer if they fit.
113 * -1: let the driver decide whether to enable buffer packing or not.
114 * 0: disable buffer packing.
115 * 1: enable buffer packing.
117 static int buffer_packing = -1;
118 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
121 * Start next frame in a packed buffer at this boundary.
122 * -1: driver should figure out a good value.
126 * value specified here will be overridden by fl_pad.
128 * power of 2 from 32 to 4096 (both inclusive) is a valid value here.
131 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
133 static int fl_pack = -1;
134 static int t4_fl_pack;
135 static int t5_fl_pack;
136 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
139 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
140 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
141 * 1: ok to create mbuf(s) within a cluster if there is room.
143 static int allow_mbufs_in_cluster = 1;
144 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
147 * Largest rx cluster size that the driver is allowed to allocate.
149 static int largest_rx_cluster = MJUM16BYTES;
150 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
153 * Size of cluster allocation that's most likely to succeed. The driver will
154 * fall back to this size if it fails to allocate clusters larger than this.
156 static int safest_rx_cluster = PAGE_SIZE;
157 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
159 /* Used to track coalesced tx work request */
161 uint64_t *flitp; /* ptr to flit where next pkt should start */
162 uint8_t npkt; /* # of packets in this work request */
163 uint8_t nflits; /* # of flits used by this work request */
164 uint16_t plen; /* total payload (sum of all packets) */
167 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
169 int nsegs; /* # of segments in the SGL, 0 means imm. tx */
170 int nflits; /* # of flits needed for the SGL */
171 bus_dma_segment_t seg[TX_SGL_SEGS];
174 static int service_iq(struct sge_iq *, int);
175 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
176 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
177 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
178 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int,
180 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
182 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
183 bus_addr_t *, void **);
184 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
186 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
188 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
189 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
191 static int alloc_fwq(struct adapter *);
192 static int free_fwq(struct adapter *);
193 static int alloc_mgmtq(struct adapter *);
194 static int free_mgmtq(struct adapter *);
195 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
196 struct sysctl_oid *);
197 static int free_rxq(struct port_info *, struct sge_rxq *);
199 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
200 struct sysctl_oid *);
201 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
204 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int,
205 struct sysctl_oid *);
206 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *);
207 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int,
208 struct sysctl_oid *);
209 static int free_nm_txq(struct port_info *, struct sge_nm_txq *);
211 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
212 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
214 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
216 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
217 static int free_eq(struct adapter *, struct sge_eq *);
218 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
219 struct sysctl_oid *);
220 static int free_wrq(struct adapter *, struct sge_wrq *);
221 static int alloc_txq(struct port_info *, struct sge_txq *, int,
222 struct sysctl_oid *);
223 static int free_txq(struct port_info *, struct sge_txq *);
224 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
225 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
226 static int refill_fl(struct adapter *, struct sge_fl *, int);
227 static void refill_sfl(void *);
228 static int alloc_fl_sdesc(struct sge_fl *);
229 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
230 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
231 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
232 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
234 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int);
235 static int free_pkt_sgl(struct sge_txq *, struct sgl *);
236 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *,
238 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *,
239 struct mbuf *, struct sgl *);
240 static void write_txpkts_wr(struct sge_txq *, struct txpkts *);
241 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *,
242 struct txpkts *, struct mbuf *, struct sgl *);
243 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *);
244 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
245 static inline void ring_eq_db(struct adapter *, struct sge_eq *);
246 static inline int reclaimable(struct sge_eq *);
247 static int reclaim_tx_descs(struct sge_txq *, int, int);
248 static void write_eqflush_wr(struct sge_eq *);
249 static __be64 get_flit(bus_dma_segment_t *, int, int);
250 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
252 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
255 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
256 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
258 static counter_u64_t extfree_refs;
259 static counter_u64_t extfree_rels;
262 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
269 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */
270 #if defined(__i386__) || defined(__amd64__)
271 pad = max(cpu_clflush_line_size, 16);
273 pad = max(CACHE_LINE_SIZE, 16);
275 pad = min(pad, 4096);
277 if (fl_pktshift < 0 || fl_pktshift > 7) {
278 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
279 " using 2 instead.\n", fl_pktshift);
284 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) {
287 printf("Invalid hw.cxgbe.fl_pad value (%d),"
288 " using %d instead.\n", fl_pad, max(pad, 32));
290 fl_pad = max(pad, 32);
294 * T4 has the same pad and pack boundary. If a pad boundary is set,
295 * pack boundary must be set to the same value. Otherwise take the
296 * specified value or auto-calculate something reasonable.
300 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack))
301 t4_fl_pack = max(pad, 32);
303 t4_fl_pack = fl_pack;
305 /* T5's pack boundary is independent of the pad boundary. */
306 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
308 t5_fl_pack = max(pad, CACHE_LINE_SIZE);
310 t5_fl_pack = fl_pack;
312 if (spg_len != 64 && spg_len != 128) {
315 #if defined(__i386__) || defined(__amd64__)
316 len = cpu_clflush_line_size > 64 ? 128 : 64;
321 printf("Invalid hw.cxgbe.spg_len value (%d),"
322 " using %d instead.\n", spg_len, len);
327 if (cong_drop < -1 || cong_drop > 1) {
328 printf("Invalid hw.cxgbe.cong_drop value (%d),"
329 " using 0 instead.\n", cong_drop);
333 extfree_refs = counter_u64_alloc(M_WAITOK);
334 extfree_rels = counter_u64_alloc(M_WAITOK);
335 counter_u64_zero(extfree_refs);
336 counter_u64_zero(extfree_rels);
340 t4_sge_modunload(void)
343 counter_u64_free(extfree_refs);
344 counter_u64_free(extfree_rels);
348 t4_sge_extfree_refs(void)
352 rels = counter_u64_fetch(extfree_rels);
353 refs = counter_u64_fetch(extfree_refs);
355 return (refs - rels);
359 t4_init_sge_cpl_handlers(struct adapter *sc)
362 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
363 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
364 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
365 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
366 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
370 * adap->params.vpd.cclk must be set up before this is called.
373 t4_tweak_chip_settings(struct adapter *sc)
377 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
378 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
379 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
380 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
381 static int sge_flbuf_sizes[] = {
383 #if MJUMPAGESIZE != MCLBYTES
385 MJUMPAGESIZE - CL_METADATA_SIZE,
386 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
390 MCLBYTES - MSIZE - CL_METADATA_SIZE,
391 MJUM9BYTES - CL_METADATA_SIZE,
392 MJUM16BYTES - CL_METADATA_SIZE,
395 KASSERT(sc->flags & MASTER_PF,
396 ("%s: trying to change chip settings when not master.", __func__));
398 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
399 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
400 V_EGRSTATUSPAGESIZE(spg_len == 128);
401 if (is_t4(sc) && (fl_pad || buffer_packing)) {
402 /* t4_fl_pack has the correct value even when fl_pad = 0 */
403 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
404 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
405 } else if (is_t5(sc) && fl_pad) {
406 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
407 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
409 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
411 if (is_t5(sc) && buffer_packing) {
412 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
413 if (t5_fl_pack == 16)
414 v = V_INGPACKBOUNDARY(0);
416 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
417 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
420 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
421 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
422 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
423 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
424 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
425 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
426 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
428 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
430 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
431 ("%s: hw buffer size table too big", __func__));
432 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
433 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
437 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
438 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
439 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
441 KASSERT(intr_timer[0] <= timer_max,
442 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
444 for (i = 1; i < nitems(intr_timer); i++) {
445 KASSERT(intr_timer[i] >= intr_timer[i - 1],
446 ("%s: timers not listed in increasing order (%d)",
449 while (intr_timer[i] > timer_max) {
450 if (i == nitems(intr_timer) - 1) {
451 intr_timer[i] = timer_max;
454 intr_timer[i] += intr_timer[i - 1];
459 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
460 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
461 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
462 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
463 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
464 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
465 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
466 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
467 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
469 if (cong_drop == 0) {
470 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
472 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0);
475 /* 4K, 16K, 64K, 256K DDP "page sizes" */
476 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
477 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
479 m = v = F_TDDPTAGTCB;
480 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
482 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
484 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
485 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
489 * SGE wants the buffer to be at least 64B and then a multiple of the pad
490 * boundary or 16, whichever is greater.
495 int mask = max(fl_pad, 16) - 1;
497 return (hwsz >= 64 && (hwsz & mask) == 0);
501 * XXX: driver really should be able to deal with unexpected settings.
504 t4_read_chip_settings(struct adapter *sc)
506 struct sge *s = &sc->sge;
509 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
510 static int sw_buf_sizes[] = { /* Sorted by size */
512 #if MJUMPAGESIZE != MCLBYTES
518 struct sw_zone_info *swz, *safe_swz;
519 struct hw_buf_info *hwb;
521 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
522 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
523 V_EGRSTATUSPAGESIZE(spg_len == 128);
524 if (is_t4(sc) && (fl_pad || buffer_packing)) {
525 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
526 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5);
527 } else if (is_t5(sc) && fl_pad) {
528 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY);
529 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5);
531 r = t4_read_reg(sc, A_SGE_CONTROL);
533 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
537 if (is_t5(sc) && buffer_packing) {
538 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
539 if (t5_fl_pack == 16)
540 v = V_INGPACKBOUNDARY(0);
542 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5);
543 r = t4_read_reg(sc, A_SGE_CONTROL2);
545 device_printf(sc->dev,
546 "invalid SGE_CONTROL2(0x%x)\n", r);
550 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack;
552 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
553 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
554 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
555 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
556 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
557 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
558 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
559 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
560 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
562 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
566 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
567 hwb = &s->hw_buf_info[0];
568 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
569 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
571 hwb->zidx = hwsz_ok(r) ? -1 : -2;
576 * Create a sorted list in decreasing order of hw buffer sizes (and so
577 * increasing order of spare area) for each software zone.
579 n = 0; /* no usable buffer size to begin with */
580 swz = &s->sw_zone_info[0];
582 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
583 int8_t head = -1, tail = -1;
585 swz->size = sw_buf_sizes[i];
586 swz->zone = m_getzone(swz->size);
587 swz->type = m_gettype(swz->size);
589 if (swz->size == safest_rx_cluster)
592 hwb = &s->hw_buf_info[0];
593 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
594 if (hwb->zidx != -1 || hwb->size > swz->size)
599 else if (hwb->size < s->hw_buf_info[tail].size) {
600 s->hw_buf_info[tail].next = j;
604 struct hw_buf_info *t;
606 for (cur = &head; *cur != -1; cur = &t->next) {
607 t = &s->hw_buf_info[*cur];
608 if (hwb->size == t->size) {
612 if (hwb->size > t->size) {
620 swz->head_hwidx = head;
621 swz->tail_hwidx = tail;
625 if (swz->size - s->hw_buf_info[tail].size >=
627 sc->flags |= BUF_PACKING_OK;
631 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
637 if (safe_swz != NULL) {
638 s->safe_hwidx1 = safe_swz->head_hwidx;
639 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
642 hwb = &s->hw_buf_info[i];
643 spare = safe_swz->size - hwb->size;
644 if (spare < CL_METADATA_SIZE)
646 if (s->safe_hwidx2 == -1 ||
647 spare == CL_METADATA_SIZE + MSIZE)
649 if (spare >= CL_METADATA_SIZE + MSIZE)
654 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
655 s->counter_val[0] = G_THRESHOLD_0(r);
656 s->counter_val[1] = G_THRESHOLD_1(r);
657 s->counter_val[2] = G_THRESHOLD_2(r);
658 s->counter_val[3] = G_THRESHOLD_3(r);
660 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
661 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc);
662 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc);
663 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
664 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc);
665 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc);
666 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
667 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc);
668 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc);
670 if (cong_drop == 0) {
671 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
673 r = t4_read_reg(sc, A_TP_PARA_REG3);
675 device_printf(sc->dev,
676 "invalid TP_PARA_REG3(0x%x)\n", r);
681 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
682 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
684 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
688 m = v = F_TDDPTAGTCB;
689 r = t4_read_reg(sc, A_ULP_RX_CTL);
691 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
695 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
697 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
698 r = t4_read_reg(sc, A_TP_PARA_REG5);
700 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
704 r = t4_read_reg(sc, A_SGE_CONM_CTRL);
705 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
707 s->fl_starve_threshold2 = s->fl_starve_threshold;
709 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
711 /* egress queues: log2 of # of doorbells per BAR2 page */
712 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
713 r >>= S_QUEUESPERPAGEPF0 +
714 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
715 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
717 /* ingress queues: log2 of # of doorbells per BAR2 page */
718 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
719 r >>= S_QUEUESPERPAGEPF0 +
720 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
721 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
723 t4_init_tp_params(sc);
725 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
726 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
732 t4_create_dma_tag(struct adapter *sc)
736 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
737 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
738 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
741 device_printf(sc->dev,
742 "failed to create main DMA tag: %d\n", rc);
749 enable_buffer_packing(struct adapter *sc)
752 if (sc->flags & BUF_PACKING_OK &&
753 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */
754 (is_t4(sc) && buffer_packing == 1)))
760 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
761 struct sysctl_oid_list *children)
764 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
765 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
766 "freelist buffer sizes");
768 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
769 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
771 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
772 NULL, fl_pad, "payload pad boundary (bytes)");
774 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
775 NULL, spg_len, "status page size (bytes)");
777 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
778 NULL, cong_drop, "congestion drop setting");
780 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD,
781 NULL, enable_buffer_packing(sc),
782 "pack multiple frames in one fl buffer");
784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
785 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)");
789 t4_destroy_dma_tag(struct adapter *sc)
792 bus_dma_tag_destroy(sc->dmat);
798 * Allocate and initialize the firmware event queue and the management queue.
800 * Returns errno on failure. Resources allocated up to that point may still be
801 * allocated. Caller is responsible for cleanup in case this function fails.
804 t4_setup_adapter_queues(struct adapter *sc)
808 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
810 sysctl_ctx_init(&sc->ctx);
811 sc->flags |= ADAP_SYSCTL_CTX;
814 * Firmware event queue
821 * Management queue. This is just a control queue that uses the fwq as
824 rc = alloc_mgmtq(sc);
833 t4_teardown_adapter_queues(struct adapter *sc)
836 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
838 /* Do this before freeing the queue */
839 if (sc->flags & ADAP_SYSCTL_CTX) {
840 sysctl_ctx_free(&sc->ctx);
841 sc->flags &= ~ADAP_SYSCTL_CTX;
851 port_intr_count(struct port_info *pi)
855 if (pi->flags & INTR_RXQ)
858 if (pi->flags & INTR_OFLD_RXQ)
862 if (pi->flags & INTR_NM_RXQ)
869 first_vector(struct port_info *pi)
871 struct adapter *sc = pi->adapter;
872 int rc = T4_EXTRA_INTR, i;
874 if (sc->intr_count == 1)
877 for_each_port(sc, i) {
878 if (i == pi->port_id)
881 rc += port_intr_count(sc->port[i]);
888 * Given an arbitrary "index," come up with an iq that can be used by other
889 * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
890 * The iq returned is guaranteed to be something that takes direct interrupts.
892 static struct sge_iq *
893 port_intr_iq(struct port_info *pi, int idx)
895 struct adapter *sc = pi->adapter;
896 struct sge *s = &sc->sge;
897 struct sge_iq *iq = NULL;
900 if (sc->intr_count == 1)
901 return (&sc->sge.fwq);
903 nintr = port_intr_count(pi);
905 ("%s: pi %p has no exclusive interrupts, total interrupts = %d",
906 __func__, pi, sc->intr_count));
908 /* Exclude netmap queues as they can't take anyone else's interrupts */
909 if (pi->flags & INTR_NM_RXQ)
912 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__,
913 pi, nintr, pi->nnmrxq));
917 if (pi->flags & INTR_RXQ) {
919 iq = &s->rxq[pi->first_rxq + i].iq;
925 if (pi->flags & INTR_OFLD_RXQ) {
926 if (i < pi->nofldrxq) {
927 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq;
933 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
934 pi, pi->flags & INTR_ALL, idx, nintr);
937 KASSERT(iq->flags & IQ_INTR,
938 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi,
939 pi->flags & INTR_ALL, idx));
943 /* Maximum payload that can be delivered with a single iq descriptor */
945 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
951 payload = sc->tt.rx_coalesce ?
952 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
955 /* large enough even when hw VLAN extraction is disabled */
956 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
961 payload = roundup2(payload, fl_pad);
967 t4_setup_port_queues(struct port_info *pi)
969 int rc = 0, i, j, intr_idx, iqid;
972 struct sge_wrq *ctrlq;
974 struct sge_ofld_rxq *ofld_rxq;
975 struct sge_wrq *ofld_txq;
978 struct sge_nm_rxq *nm_rxq;
979 struct sge_nm_txq *nm_txq;
982 struct adapter *sc = pi->adapter;
983 struct ifnet *ifp = pi->ifp;
984 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
985 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
986 int maxp, pack, mtu = ifp->if_mtu;
988 /* Interrupt vector to start from (when using multiple vectors) */
989 intr_idx = first_vector(pi);
992 * First pass over all NIC and TOE rx queues:
993 * a) initialize iq and fl
994 * b) allocate queue iff it will take direct interrupts.
996 maxp = mtu_to_max_payload(sc, mtu, 0);
997 pack = enable_buffer_packing(sc);
998 if (pi->flags & INTR_RXQ) {
999 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1000 CTLFLAG_RD, NULL, "rx queues");
1002 for_each_rxq(pi, i, rxq) {
1004 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq);
1006 snprintf(name, sizeof(name), "%s rxq%d-fl",
1007 device_get_nameunit(pi->dev), i);
1008 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name);
1010 if (pi->flags & INTR_RXQ) {
1011 rxq->iq.flags |= IQ_INTR;
1012 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1019 maxp = mtu_to_max_payload(sc, mtu, 1);
1020 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) {
1021 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1023 "rx queues for offloaded TCP connections");
1025 for_each_ofld_rxq(pi, i, ofld_rxq) {
1027 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
1030 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1031 device_get_nameunit(pi->dev), i);
1032 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name);
1034 if (pi->flags & INTR_OFLD_RXQ) {
1035 ofld_rxq->iq.flags |= IQ_INTR;
1036 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1045 * We don't have buffers to back the netmap rx queues right now so we
1046 * create the queues in a way that doesn't set off any congestion signal
1049 if (pi->flags & INTR_NM_RXQ) {
1050 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq",
1051 CTLFLAG_RD, NULL, "rx queues for netmap");
1052 for_each_nm_rxq(pi, i, nm_rxq) {
1053 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid);
1062 * Second pass over all NIC and TOE rx queues. The queues forwarding
1063 * their interrupts are allocated now.
1066 if (!(pi->flags & INTR_RXQ)) {
1067 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1068 CTLFLAG_RD, NULL, "rx queues");
1069 for_each_rxq(pi, i, rxq) {
1070 MPASS(!(rxq->iq.flags & IQ_INTR));
1072 intr_idx = port_intr_iq(pi, j)->abs_id;
1074 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1081 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) {
1082 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1084 "rx queues for offloaded TCP connections");
1085 for_each_ofld_rxq(pi, i, ofld_rxq) {
1086 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1088 intr_idx = port_intr_iq(pi, j)->abs_id;
1090 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1098 if (!(pi->flags & INTR_NM_RXQ))
1099 CXGBE_UNIMPLEMENTED(__func__);
1103 * Now the tx queues. Only one pass needed.
1105 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1108 for_each_txq(pi, i, txq) {
1109 iqid = port_intr_iq(pi, j)->cntxt_id;
1110 snprintf(name, sizeof(name), "%s txq%d",
1111 device_get_nameunit(pi->dev), i);
1112 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
1115 rc = alloc_txq(pi, txq, i, oid);
1121 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
1122 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1123 for_each_ofld_txq(pi, i, ofld_txq) {
1124 struct sysctl_oid *oid2;
1126 iqid = port_intr_iq(pi, j)->cntxt_id;
1127 snprintf(name, sizeof(name), "%s ofld_txq%d",
1128 device_get_nameunit(pi->dev), i);
1129 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
1132 snprintf(name, sizeof(name), "%d", i);
1133 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1134 name, CTLFLAG_RD, NULL, "offload tx queue");
1136 rc = alloc_wrq(sc, pi, ofld_txq, oid2);
1143 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq",
1144 CTLFLAG_RD, NULL, "tx queues for netmap use");
1145 for_each_nm_txq(pi, i, nm_txq) {
1146 iqid = pi->first_nm_rxq + (j % pi->nnmrxq);
1147 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid);
1155 * Finally, the control queue.
1157 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1158 NULL, "ctrl queue");
1159 ctrlq = &sc->sge.ctrlq[pi->port_id];
1160 iqid = port_intr_iq(pi, 0)->cntxt_id;
1161 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
1162 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
1163 rc = alloc_wrq(sc, pi, ctrlq, oid);
1167 t4_teardown_port_queues(pi);
1176 t4_teardown_port_queues(struct port_info *pi)
1179 struct adapter *sc = pi->adapter;
1180 struct sge_rxq *rxq;
1181 struct sge_txq *txq;
1183 struct sge_ofld_rxq *ofld_rxq;
1184 struct sge_wrq *ofld_txq;
1187 struct sge_nm_rxq *nm_rxq;
1188 struct sge_nm_txq *nm_txq;
1191 /* Do this before freeing the queues */
1192 if (pi->flags & PORT_SYSCTL_CTX) {
1193 sysctl_ctx_free(&pi->ctx);
1194 pi->flags &= ~PORT_SYSCTL_CTX;
1198 * Take down all the tx queues first, as they reference the rx queues
1199 * (for egress updates, etc.).
1202 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1204 for_each_txq(pi, i, txq) {
1208 for_each_ofld_txq(pi, i, ofld_txq) {
1209 free_wrq(sc, ofld_txq);
1213 for_each_nm_txq(pi, i, nm_txq)
1214 free_nm_txq(pi, nm_txq);
1218 * Then take down the rx queues that forward their interrupts, as they
1219 * reference other rx queues.
1222 for_each_rxq(pi, i, rxq) {
1223 if ((rxq->iq.flags & IQ_INTR) == 0)
1227 for_each_ofld_rxq(pi, i, ofld_rxq) {
1228 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1229 free_ofld_rxq(pi, ofld_rxq);
1233 for_each_nm_rxq(pi, i, nm_rxq)
1234 free_nm_rxq(pi, nm_rxq);
1238 * Then take down the rx queues that take direct interrupts.
1241 for_each_rxq(pi, i, rxq) {
1242 if (rxq->iq.flags & IQ_INTR)
1246 for_each_ofld_rxq(pi, i, ofld_rxq) {
1247 if (ofld_rxq->iq.flags & IQ_INTR)
1248 free_ofld_rxq(pi, ofld_rxq);
1252 CXGBE_UNIMPLEMENTED(__func__);
1259 * Deals with errors and the firmware event queue. All data rx queues forward
1260 * their interrupt to the firmware event queue.
1263 t4_intr_all(void *arg)
1265 struct adapter *sc = arg;
1266 struct sge_iq *fwq = &sc->sge.fwq;
1269 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1271 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1275 /* Deals with error interrupts */
1277 t4_intr_err(void *arg)
1279 struct adapter *sc = arg;
1281 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1282 t4_slow_intr_handler(sc);
1286 t4_intr_evt(void *arg)
1288 struct sge_iq *iq = arg;
1290 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1292 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1299 struct sge_iq *iq = arg;
1301 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1303 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1308 * Deals with anything and everything on the given ingress queue.
1311 service_iq(struct sge_iq *iq, int budget)
1314 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1315 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1316 struct adapter *sc = iq->adapter;
1317 struct iq_desc *d = &iq->desc[iq->cidx];
1318 int ndescs = 0, limit;
1319 int rsp_type, refill;
1321 uint16_t fl_hw_cidx;
1323 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1324 #if defined(INET) || defined(INET6)
1325 const struct timeval lro_timeout = {0, sc->lro_timeout};
1328 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1330 limit = budget ? budget : iq->qsize / 16;
1332 if (iq->flags & IQ_HAS_FL) {
1334 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1337 fl_hw_cidx = 0; /* to silence gcc warning */
1341 * We always come back and check the descriptor ring for new indirect
1342 * interrupts and other responses after running a single handler.
1345 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1351 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1352 lq = be32toh(d->rsp.pldbuflen_qid);
1355 case X_RSPD_TYPE_FLBUF:
1357 KASSERT(iq->flags & IQ_HAS_FL,
1358 ("%s: data for an iq (%p) with no freelist",
1361 m0 = get_fl_payload(sc, fl, lq);
1362 if (__predict_false(m0 == NULL))
1364 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1365 #ifdef T4_PKT_TIMESTAMP
1367 * 60 bit timestamp for the payload is
1368 * *(uint64_t *)m0->m_pktdat. Note that it is
1369 * in the leading free-space in the mbuf. The
1370 * kernel can clobber it during a pullup,
1371 * m_copymdata, etc. You need to make sure that
1372 * the mbuf reaches you unmolested if you care
1373 * about the timestamp.
1375 *(uint64_t *)m0->m_pktdat =
1376 be64toh(ctrl->u.last_flit) &
1382 case X_RSPD_TYPE_CPL:
1383 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1384 ("%s: bad opcode %02x.", __func__,
1386 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1389 case X_RSPD_TYPE_INTR:
1392 * Interrupts should be forwarded only to queues
1393 * that are not forwarding their interrupts.
1394 * This means service_iq can recurse but only 1
1397 KASSERT(budget == 0,
1398 ("%s: budget %u, rsp_type %u", __func__,
1402 * There are 1K interrupt-capable queues (qids 0
1403 * through 1023). A response type indicating a
1404 * forwarded interrupt with a qid >= 1K is an
1405 * iWARP async notification.
1408 sc->an_handler(iq, &d->rsp);
1412 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1413 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1415 if (service_iq(q, q->qsize / 16) == 0) {
1416 atomic_cmpset_int(&q->state,
1417 IQS_BUSY, IQS_IDLE);
1419 STAILQ_INSERT_TAIL(&iql, q,
1427 ("%s: illegal response type %d on iq %p",
1428 __func__, rsp_type, iq));
1430 "%s: illegal response type %d on iq %p",
1431 device_get_nameunit(sc->dev), rsp_type, iq);
1436 if (__predict_false(++iq->cidx == iq->sidx)) {
1438 iq->gen ^= F_RSPD_GEN;
1441 if (__predict_false(++ndescs == limit)) {
1442 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1444 V_INGRESSQID(iq->cntxt_id) |
1445 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1448 #if defined(INET) || defined(INET6)
1449 if (iq->flags & IQ_LRO_ENABLED &&
1450 sc->lro_timeout != 0) {
1451 tcp_lro_flush_inactive(&rxq->lro,
1457 if (iq->flags & IQ_HAS_FL) {
1459 refill_fl(sc, fl, 32);
1462 return (EINPROGRESS);
1467 refill_fl(sc, fl, 32);
1469 fl_hw_cidx = fl->hw_cidx;
1474 if (STAILQ_EMPTY(&iql))
1478 * Process the head only, and send it to the back of the list if
1479 * it's still not done.
1481 q = STAILQ_FIRST(&iql);
1482 STAILQ_REMOVE_HEAD(&iql, link);
1483 if (service_iq(q, q->qsize / 8) == 0)
1484 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1486 STAILQ_INSERT_TAIL(&iql, q, link);
1489 #if defined(INET) || defined(INET6)
1490 if (iq->flags & IQ_LRO_ENABLED) {
1491 struct lro_ctrl *lro = &rxq->lro;
1492 struct lro_entry *l;
1494 while (!SLIST_EMPTY(&lro->lro_active)) {
1495 l = SLIST_FIRST(&lro->lro_active);
1496 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1497 tcp_lro_flush(lro, l);
1502 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1503 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1505 if (iq->flags & IQ_HAS_FL) {
1509 starved = refill_fl(sc, fl, 64);
1511 if (__predict_false(starved != 0))
1512 add_fl_to_sfl(sc, fl);
1519 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1521 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1524 MPASS(cll->region3 >= CL_METADATA_SIZE);
1529 static inline struct cluster_metadata *
1530 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1534 if (cl_has_metadata(fl, cll)) {
1535 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1537 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1543 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1545 uma_zone_t zone = arg1;
1548 uma_zfree(zone, cl);
1549 counter_u64_add(extfree_rels, 1);
1553 * The mbuf returned by this function could be allocated from zone_mbuf or
1554 * constructed in spare room in the cluster.
1556 * The mbuf carries the payload in one of these ways
1557 * a) frame inside the mbuf (mbuf from zone_mbuf)
1558 * b) m_cljset (for clusters without metadata) zone_mbuf
1559 * c) m_extaddref (cluster with metadata) inline mbuf
1560 * d) m_extaddref (cluster with metadata) zone_mbuf
1562 static struct mbuf *
1563 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags)
1566 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1567 struct cluster_layout *cll = &sd->cll;
1568 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1569 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1570 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1571 int len, padded_len;
1574 len = min(total, hwb->size - fl->rx_offset);
1575 padded_len = roundup2(len, fl->buf_boundary);
1576 payload = sd->cl + cll->region1 + fl->rx_offset;
1578 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1581 * Copy payload into a freshly allocated mbuf.
1584 m = flags & M_PKTHDR ?
1585 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1588 fl->mbuf_allocated++;
1589 #ifdef T4_PKT_TIMESTAMP
1590 /* Leave room for a timestamp */
1593 /* copy data to mbuf */
1594 bcopy(payload, mtod(m, caddr_t), len);
1596 } else if (sd->nmbuf * MSIZE < cll->region1) {
1599 * There's spare room in the cluster for an mbuf. Create one
1600 * and associate it with the payload that's in the cluster.
1604 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1605 /* No bzero required */
1606 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE))
1609 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free,
1611 if (sd->nmbuf++ == 0)
1612 counter_u64_add(extfree_refs, 1);
1617 * Grab an mbuf from zone_mbuf and associate it with the
1618 * payload in the cluster.
1621 m = flags & M_PKTHDR ?
1622 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1625 fl->mbuf_allocated++;
1627 m_extaddref(m, payload, padded_len, &clm->refcount,
1628 rxb_free, swz->zone, sd->cl);
1629 if (sd->nmbuf++ == 0)
1630 counter_u64_add(extfree_refs, 1);
1632 m_cljset(m, sd->cl, swz->type);
1633 sd->cl = NULL; /* consumed, not a recycle candidate */
1636 if (flags & M_PKTHDR)
1637 m->m_pkthdr.len = total;
1640 if (fl->flags & FL_BUF_PACKING) {
1641 fl->rx_offset += padded_len;
1642 MPASS(fl->rx_offset <= hwb->size);
1643 if (fl->rx_offset < hwb->size)
1644 return (m); /* without advancing the cidx */
1647 if (__predict_false(++fl->cidx % 8 == 0)) {
1648 uint16_t cidx = fl->cidx / 8;
1650 if (__predict_false(cidx == fl->sidx))
1651 fl->cidx = cidx = 0;
1659 static struct mbuf *
1660 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1662 struct mbuf *m0, *m, **pnext;
1665 len = G_RSPD_LEN(len_newbuf);
1666 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1667 M_ASSERTPKTHDR(fl->m0);
1668 MPASS(len == fl->m0->m_pkthdr.len);
1669 MPASS(fl->remaining < len);
1673 len = fl->remaining;
1674 fl->flags &= ~FL_BUF_RESUME;
1678 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1680 if (__predict_false(++fl->cidx % 8 == 0)) {
1681 uint16_t cidx = fl->cidx / 8;
1683 if (__predict_false(cidx == fl->sidx))
1684 fl->cidx = cidx = 0;
1690 * Payload starts at rx_offset in the current hw buffer. Its length is
1691 * 'len' and it may span multiple hw buffers.
1694 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR);
1698 pnext = &m0->m_next;
1701 MPASS(fl->rx_offset == 0);
1702 m = get_scatter_segment(sc, fl, len, 0);
1703 if (__predict_false(m == NULL)) {
1706 fl->remaining = len;
1707 fl->flags |= FL_BUF_RESUME;
1720 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1722 struct sge_rxq *rxq = iq_to_rxq(iq);
1723 struct ifnet *ifp = rxq->ifp;
1724 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1725 #if defined(INET) || defined(INET6)
1726 struct lro_ctrl *lro = &rxq->lro;
1729 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1732 m0->m_pkthdr.len -= fl_pktshift;
1733 m0->m_len -= fl_pktshift;
1734 m0->m_data += fl_pktshift;
1736 m0->m_pkthdr.rcvif = ifp;
1737 m0->m_flags |= M_FLOWID;
1738 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1740 if (cpl->csum_calc && !cpl->err_vec) {
1741 if (ifp->if_capenable & IFCAP_RXCSUM &&
1742 cpl->l2info & htobe32(F_RXF_IP)) {
1743 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1744 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1746 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1747 cpl->l2info & htobe32(F_RXF_IP6)) {
1748 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1753 if (__predict_false(cpl->ip_frag))
1754 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1756 m0->m_pkthdr.csum_data = 0xffff;
1760 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1761 m0->m_flags |= M_VLANTAG;
1762 rxq->vlan_extraction++;
1765 #if defined(INET) || defined(INET6)
1766 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1767 iq->flags & IQ_LRO_ENABLED &&
1768 tcp_lro_rx(lro, m0, 0) == 0) {
1769 /* queued for LRO */
1772 ifp->if_input(ifp, m0);
1778 * Doesn't fail. Holds on to work requests it can't send right away.
1781 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1783 struct sge_eq *eq = &wrq->eq;
1787 TXQ_LOCK_ASSERT_OWNED(wrq);
1789 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD ||
1790 (eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1791 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1793 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1794 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1797 if (__predict_true(wr != NULL))
1798 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1800 can_reclaim = reclaimable(eq);
1801 if (__predict_false(eq->flags & EQ_STALLED)) {
1802 if (eq->avail + can_reclaim < tx_resume_threshold(eq))
1804 eq->flags &= ~EQ_STALLED;
1807 eq->cidx += can_reclaim;
1808 eq->avail += can_reclaim;
1809 if (__predict_false(eq->cidx >= eq->cap))
1810 eq->cidx -= eq->cap;
1812 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
1815 if (__predict_false(wr->wr_len < 0 ||
1816 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) {
1819 panic("%s: work request with length %d", __func__,
1825 log(LOG_ERR, "%s: %s work request with length %d",
1826 device_get_nameunit(sc->dev), __func__, wr->wr_len);
1827 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1832 ndesc = howmany(wr->wr_len, EQ_ESIZE);
1833 if (eq->avail < ndesc) {
1838 dst = (void *)&eq->desc[eq->pidx];
1839 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len);
1843 if (__predict_false(eq->pidx >= eq->cap))
1844 eq->pidx -= eq->cap;
1846 eq->pending += ndesc;
1847 if (eq->pending >= 8)
1851 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1854 if (eq->avail < 8) {
1855 can_reclaim = reclaimable(eq);
1856 eq->cidx += can_reclaim;
1857 eq->avail += can_reclaim;
1858 if (__predict_false(eq->cidx >= eq->cap))
1859 eq->cidx -= eq->cap;
1867 eq->flags |= EQ_STALLED;
1868 if (callout_pending(&eq->tx_callout) == 0)
1869 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
1873 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */
1874 #define TXPKTS_PKT_HDR ((\
1875 sizeof(struct ulp_txpkt) + \
1876 sizeof(struct ulptx_idata) + \
1877 sizeof(struct cpl_tx_pkt_core) \
1880 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */
1881 #define TXPKTS_WR_HDR (\
1882 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \
1885 /* Header of a tx WR, before SGL of first packet (in flits) */
1886 #define TXPKT_WR_HDR ((\
1887 sizeof(struct fw_eth_tx_pkt_wr) + \
1888 sizeof(struct cpl_tx_pkt_core) \
1891 /* Header of a tx LSO WR, before SGL of first packet (in flits) */
1892 #define TXPKT_LSO_WR_HDR ((\
1893 sizeof(struct fw_eth_tx_pkt_wr) + \
1894 sizeof(struct cpl_tx_pkt_lso_core) + \
1895 sizeof(struct cpl_tx_pkt_core) \
1899 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
1901 struct port_info *pi = (void *)ifp->if_softc;
1902 struct adapter *sc = pi->adapter;
1903 struct sge_eq *eq = &txq->eq;
1904 struct buf_ring *br = txq->br;
1906 int rc, coalescing, can_reclaim;
1907 struct txpkts txpkts;
1910 TXQ_LOCK_ASSERT_OWNED(txq);
1911 KASSERT(m, ("%s: called with nothing to do.", __func__));
1912 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH,
1913 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1915 prefetch(&eq->desc[eq->pidx]);
1916 prefetch(&txq->sdesc[eq->pidx]);
1918 txpkts.npkt = 0;/* indicates there's nothing in txpkts */
1921 can_reclaim = reclaimable(eq);
1922 if (__predict_false(eq->flags & EQ_STALLED)) {
1923 if (eq->avail + can_reclaim < tx_resume_threshold(eq)) {
1927 eq->flags &= ~EQ_STALLED;
1931 if (__predict_false(eq->flags & EQ_DOOMED)) {
1933 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
1938 if (eq->avail < 8 && can_reclaim)
1939 reclaim_tx_descs(txq, can_reclaim, 32);
1941 for (; m; m = next ? next : drbr_dequeue(ifp, br)) {
1946 next = m->m_nextpkt;
1947 m->m_nextpkt = NULL;
1949 if (next || buf_ring_peek(br))
1952 rc = get_pkt_sgl(txq, &m, &sgl, coalescing);
1956 /* Short of resources, suspend tx */
1958 m->m_nextpkt = next;
1963 * Unrecoverable error for this packet, throw it away
1964 * and move on to the next. get_pkt_sgl may already
1965 * have freed m (it will be NULL in that case and the
1966 * m_freem here is still safe).
1974 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) {
1976 /* Successfully absorbed into txpkts */
1978 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl);
1983 * We weren't coalescing to begin with, or current frame could
1984 * not be coalesced (add_to_txpkts flushes txpkts if a frame
1985 * given to it can't be coalesced). Either way there should be
1986 * nothing in txpkts.
1988 KASSERT(txpkts.npkt == 0,
1989 ("%s: txpkts not empty: %d", __func__, txpkts.npkt));
1991 /* We're sending out individual packets now */
1995 reclaim_tx_descs(txq, 0, 8);
1996 rc = write_txpkt_wr(pi, txq, m, &sgl);
1999 /* Short of hardware descriptors, suspend tx */
2002 * This is an unlikely but expensive failure. We've
2003 * done all the hard work (DMA mappings etc.) and now we
2004 * can't send out the packet. What's worse, we have to
2005 * spend even more time freeing up everything in sgl.
2008 free_pkt_sgl(txq, &sgl);
2010 m->m_nextpkt = next;
2014 ETHER_BPF_MTAP(ifp, m);
2018 if (eq->pending >= 8)
2021 can_reclaim = reclaimable(eq);
2022 if (can_reclaim >= 32)
2023 reclaim_tx_descs(txq, can_reclaim, 64);
2026 if (txpkts.npkt > 0)
2027 write_txpkts_wr(txq, &txpkts);
2030 * m not NULL means there was an error but we haven't thrown it away.
2031 * This can happen when we're short of tx descriptors (no_desc) or maybe
2032 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim
2033 * will get things going again.
2035 if (m && !(eq->flags & EQ_CRFLUSHED)) {
2036 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx];
2039 * If EQ_CRFLUSHED is not set then we know we have at least one
2040 * available descriptor because any WR that reduces eq->avail to
2041 * 0 also sets EQ_CRFLUSHED.
2043 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__));
2045 txsd->desc_used = 1;
2047 write_eqflush_wr(eq);
2054 reclaim_tx_descs(txq, 0, 128);
2056 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0)
2057 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
2063 t4_update_fl_bufsize(struct ifnet *ifp)
2065 struct port_info *pi = ifp->if_softc;
2066 struct adapter *sc = pi->adapter;
2067 struct sge_rxq *rxq;
2069 struct sge_ofld_rxq *ofld_rxq;
2072 int i, maxp, mtu = ifp->if_mtu;
2074 maxp = mtu_to_max_payload(sc, mtu, 0);
2075 for_each_rxq(pi, i, rxq) {
2079 find_best_refill_source(sc, fl, maxp);
2083 maxp = mtu_to_max_payload(sc, mtu, 1);
2084 for_each_ofld_rxq(pi, i, ofld_rxq) {
2088 find_best_refill_source(sc, fl, maxp);
2095 can_resume_tx(struct sge_eq *eq)
2098 return (eq->avail + reclaimable(eq) >= tx_resume_threshold(eq));
2102 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2106 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2107 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2108 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2109 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2113 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2114 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2115 if (pktc_idx >= 0) {
2116 iq->intr_params |= F_QINTR_CNT_EN;
2117 iq->intr_pktc_idx = pktc_idx;
2119 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2120 iq->sidx = iq->qsize - spg_len / IQ_ESIZE;
2124 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack,
2129 fl->sidx = qsize - spg_len / EQ_ESIZE;
2130 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2132 fl->flags |= FL_BUF_PACKING;
2133 find_best_refill_source(sc, fl, maxp);
2134 find_safe_refill_source(sc, fl);
2138 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
2139 uint16_t iqid, char *name)
2141 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
2142 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2144 eq->flags = eqtype & EQ_TYPEMASK;
2145 eq->tx_chan = tx_chan;
2148 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2150 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq);
2151 callout_init(&eq->tx_callout, CALLOUT_MPSAFE);
2155 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2156 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2160 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2161 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2163 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2167 rc = bus_dmamem_alloc(*tag, va,
2168 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2170 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2174 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2176 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2181 free_ring(sc, *tag, *map, *pa, *va);
2187 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2188 bus_addr_t pa, void *va)
2191 bus_dmamap_unload(tag, map);
2193 bus_dmamem_free(tag, va, map);
2195 bus_dma_tag_destroy(tag);
2201 * Allocates the ring for an ingress queue and an optional freelist. If the
2202 * freelist is specified it will be allocated and then associated with the
2205 * Returns errno on failure. Resources allocated up to that point may still be
2206 * allocated. Caller is responsible for cleanup in case this function fails.
2208 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2209 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2210 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2213 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
2214 int intr_idx, int cong)
2216 int rc, i, cntxt_id;
2219 struct adapter *sc = iq->adapter;
2222 len = iq->qsize * IQ_ESIZE;
2223 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2224 (void **)&iq->desc);
2228 bzero(&c, sizeof(c));
2229 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2230 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2231 V_FW_IQ_CMD_VFN(0));
2233 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2236 /* Special handling for firmware event queue */
2237 if (iq == &sc->sge.fwq)
2238 v |= F_FW_IQ_CMD_IQASYNCH;
2240 if (iq->flags & IQ_INTR) {
2241 KASSERT(intr_idx < sc->intr_count,
2242 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2244 v |= F_FW_IQ_CMD_IQANDST;
2245 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2247 c.type_to_iqandstindex = htobe32(v |
2248 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2249 V_FW_IQ_CMD_VIID(pi->viid) |
2250 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2251 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2252 F_FW_IQ_CMD_IQGTSMODE |
2253 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2254 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2255 c.iqsize = htobe16(iq->qsize);
2256 c.iqaddr = htobe64(iq->ba);
2258 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2261 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2263 len = fl->qsize * EQ_ESIZE;
2264 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2265 &fl->ba, (void **)&fl->desc);
2269 /* Allocate space for one software descriptor per buffer. */
2270 rc = alloc_fl_sdesc(fl);
2272 device_printf(sc->dev,
2273 "failed to setup fl software descriptors: %d\n",
2278 if (fl->flags & FL_BUF_PACKING) {
2279 fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8);
2280 fl->buf_boundary = max(fl_pad, sc->sge.pack_boundary);
2282 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
2283 fl->buf_boundary = fl_pad;
2286 c.iqns_to_fl0congen |=
2287 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2288 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2289 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2290 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2293 c.iqns_to_fl0congen |=
2294 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2295 F_FW_IQ_CMD_FL0CONGCIF |
2296 F_FW_IQ_CMD_FL0CONGEN);
2298 c.fl0dcaen_to_fl0cidxfthresh =
2299 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) |
2300 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2301 c.fl0size = htobe16(fl->qsize);
2302 c.fl0addr = htobe64(fl->ba);
2305 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2307 device_printf(sc->dev,
2308 "failed to create ingress queue: %d\n", rc);
2313 iq->gen = F_RSPD_GEN;
2314 iq->intr_next = iq->intr_params;
2315 iq->cntxt_id = be16toh(c.iqid);
2316 iq->abs_id = be16toh(c.physiqid);
2317 iq->flags |= IQ_ALLOCATED;
2319 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2320 if (cntxt_id >= sc->sge.niq) {
2321 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2322 cntxt_id, sc->sge.niq - 1);
2324 sc->sge.iqmap[cntxt_id] = iq;
2329 iq->flags |= IQ_HAS_FL;
2330 fl->cntxt_id = be16toh(c.fl0id);
2331 fl->pidx = fl->cidx = 0;
2333 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2334 if (cntxt_id >= sc->sge.neq) {
2335 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2336 __func__, cntxt_id, sc->sge.neq - 1);
2338 sc->sge.eqmap[cntxt_id] = (void *)fl;
2341 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2342 uint32_t s_qpp = sc->sge.eq_s_qpp;
2343 uint32_t mask = (1 << s_qpp) - 1;
2344 volatile uint8_t *udb;
2346 udb = sc->udbs_base + UDBS_DB_OFFSET;
2347 udb += (qid >> s_qpp) << PAGE_SHIFT;
2349 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2350 udb += qid << UDBS_SEG_SHIFT;
2353 fl->udb = (volatile void *)udb;
2355 fl->dbval = F_DBPRIO | V_QID(qid);
2357 fl->dbval |= F_DBTYPE;
2360 /* Enough to make sure the SGE doesn't think it's starved */
2361 refill_fl(sc, fl, fl->lowat);
2365 if (is_t5(sc) && cong >= 0) {
2366 uint32_t param, val;
2368 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2369 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2370 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2375 for (i = 0; i < 4; i++) {
2376 if (cong & (1 << i))
2377 val |= 1 << (i << 2);
2381 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2383 /* report error but carry on */
2384 device_printf(sc->dev,
2385 "failed to set congestion manager context for "
2386 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2390 /* Enable IQ interrupts */
2391 atomic_store_rel_int(&iq->state, IQS_IDLE);
2392 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2393 V_INGRESSQID(iq->cntxt_id));
2399 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
2402 struct adapter *sc = iq->adapter;
2406 return (0); /* nothing to do */
2408 dev = pi ? pi->dev : sc->dev;
2410 if (iq->flags & IQ_ALLOCATED) {
2411 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2412 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2413 fl ? fl->cntxt_id : 0xffff, 0xffff);
2416 "failed to free queue %p: %d\n", iq, rc);
2419 iq->flags &= ~IQ_ALLOCATED;
2422 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2424 bzero(iq, sizeof(*iq));
2427 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2431 free_fl_sdesc(sc, fl);
2433 if (mtx_initialized(&fl->fl_lock))
2434 mtx_destroy(&fl->fl_lock);
2436 bzero(fl, sizeof(*fl));
2443 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2446 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2448 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2450 children = SYSCTL_CHILDREN(oid);
2452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2453 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2454 "SGE context id of the freelist");
2455 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2456 0, "consumer index");
2457 if (fl->flags & FL_BUF_PACKING) {
2458 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2459 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2462 0, "producer index");
2463 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2464 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2465 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2466 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2467 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2468 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2469 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2470 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2471 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2472 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2476 alloc_fwq(struct adapter *sc)
2479 struct sge_iq *fwq = &sc->sge.fwq;
2480 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2481 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2483 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2484 fwq->flags |= IQ_INTR; /* always */
2485 intr_idx = sc->intr_count > 1 ? 1 : 0;
2486 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
2488 device_printf(sc->dev,
2489 "failed to create firmware event queue: %d\n", rc);
2493 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2494 NULL, "firmware event queue");
2495 children = SYSCTL_CHILDREN(oid);
2497 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2498 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2499 "absolute id of the queue");
2500 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2501 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2502 "SGE context id of the queue");
2503 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2504 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2511 free_fwq(struct adapter *sc)
2513 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2517 alloc_mgmtq(struct adapter *sc)
2520 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2522 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2523 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2525 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2526 NULL, "management queue");
2528 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2529 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2530 sc->sge.fwq.cntxt_id, name);
2531 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2533 device_printf(sc->dev,
2534 "failed to create management queue: %d\n", rc);
2542 free_mgmtq(struct adapter *sc)
2545 return free_wrq(sc, &sc->sge.mgmtq);
2549 tnl_cong(struct port_info *pi)
2552 if (cong_drop == -1)
2554 else if (cong_drop == 1)
2557 return (pi->rx_chan_map);
2561 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
2562 struct sysctl_oid *oid)
2565 struct sysctl_oid_list *children;
2568 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi));
2573 * The freelist is just barely above the starvation threshold right now,
2574 * fill it up a bit more.
2577 refill_fl(pi->adapter, &rxq->fl, 128);
2578 FL_UNLOCK(&rxq->fl);
2580 #if defined(INET) || defined(INET6)
2581 rc = tcp_lro_init(&rxq->lro);
2584 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
2586 if (pi->ifp->if_capenable & IFCAP_LRO)
2587 rxq->iq.flags |= IQ_LRO_ENABLED;
2591 children = SYSCTL_CHILDREN(oid);
2593 snprintf(name, sizeof(name), "%d", idx);
2594 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2596 children = SYSCTL_CHILDREN(oid);
2598 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2599 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2600 "absolute id of the queue");
2601 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2602 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2603 "SGE context id of the queue");
2604 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2605 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2607 #if defined(INET) || defined(INET6)
2608 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2609 &rxq->lro.lro_queued, 0, NULL);
2610 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2611 &rxq->lro.lro_flushed, 0, NULL);
2613 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2614 &rxq->rxcsum, "# of times hardware assisted with checksum");
2615 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction",
2616 CTLFLAG_RD, &rxq->vlan_extraction,
2617 "# of times hardware extracted 802.1Q tag");
2619 add_fl_sysctls(&pi->ctx, oid, &rxq->fl);
2625 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
2629 #if defined(INET) || defined(INET6)
2631 tcp_lro_free(&rxq->lro);
2632 rxq->lro.ifp = NULL;
2636 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
2638 bzero(rxq, sizeof(*rxq));
2645 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
2646 int intr_idx, int idx, struct sysctl_oid *oid)
2649 struct sysctl_oid_list *children;
2652 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2657 children = SYSCTL_CHILDREN(oid);
2659 snprintf(name, sizeof(name), "%d", idx);
2660 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2662 children = SYSCTL_CHILDREN(oid);
2664 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2665 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2666 "I", "absolute id of the queue");
2667 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2668 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2669 "I", "SGE context id of the queue");
2670 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2671 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2674 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl);
2680 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
2684 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
2686 bzero(ofld_rxq, sizeof(*ofld_rxq));
2694 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx,
2695 int idx, struct sysctl_oid *oid)
2698 struct sysctl_oid_list *children;
2699 struct sysctl_ctx_list *ctx;
2702 struct adapter *sc = pi->adapter;
2703 struct netmap_adapter *na = NA(pi->nm_ifp);
2707 len = pi->qsize_rxq * IQ_ESIZE;
2708 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
2709 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
2713 len = na->num_rx_desc * EQ_ESIZE + spg_len;
2714 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
2715 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
2721 nm_rxq->iq_cidx = 0;
2722 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / IQ_ESIZE;
2723 nm_rxq->iq_gen = F_RSPD_GEN;
2724 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
2725 nm_rxq->fl_sidx = na->num_rx_desc;
2726 nm_rxq->intr_idx = intr_idx;
2729 children = SYSCTL_CHILDREN(oid);
2731 snprintf(name, sizeof(name), "%d", idx);
2732 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
2734 children = SYSCTL_CHILDREN(oid);
2736 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
2737 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
2738 "I", "absolute id of the queue");
2739 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2740 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
2741 "I", "SGE context id of the queue");
2742 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
2743 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
2746 children = SYSCTL_CHILDREN(oid);
2747 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2749 children = SYSCTL_CHILDREN(oid);
2751 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2752 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
2753 "I", "SGE context id of the freelist");
2754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
2755 &nm_rxq->fl_cidx, 0, "consumer index");
2756 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
2757 &nm_rxq->fl_pidx, 0, "producer index");
2764 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
2766 struct adapter *sc = pi->adapter;
2768 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
2770 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
2777 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
2778 struct sysctl_oid *oid)
2782 struct adapter *sc = pi->adapter;
2783 struct netmap_adapter *na = NA(pi->nm_ifp);
2785 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2787 len = na->num_tx_desc * EQ_ESIZE + spg_len;
2788 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
2789 &nm_txq->ba, (void **)&nm_txq->desc);
2793 nm_txq->pidx = nm_txq->cidx = 0;
2794 nm_txq->sidx = na->num_tx_desc;
2796 nm_txq->iqidx = iqidx;
2797 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
2798 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
2800 snprintf(name, sizeof(name), "%d", idx);
2801 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2802 NULL, "netmap tx queue");
2803 children = SYSCTL_CHILDREN(oid);
2805 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
2806 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
2807 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2808 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
2810 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
2811 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
2818 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq)
2820 struct adapter *sc = pi->adapter;
2822 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
2830 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
2833 struct fw_eq_ctrl_cmd c;
2835 bzero(&c, sizeof(c));
2837 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
2838 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
2839 V_FW_EQ_CTRL_CMD_VFN(0));
2840 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
2841 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
2842 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */
2843 c.physeqid_pkd = htobe32(0);
2844 c.fetchszm_to_iqid =
2845 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2846 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
2847 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
2849 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2850 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2851 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2852 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize));
2853 c.eqaddr = htobe64(eq->ba);
2855 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2857 device_printf(sc->dev,
2858 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
2861 eq->flags |= EQ_ALLOCATED;
2863 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
2864 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2865 if (cntxt_id >= sc->sge.neq)
2866 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2867 cntxt_id, sc->sge.neq - 1);
2868 sc->sge.eqmap[cntxt_id] = eq;
2874 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2877 struct fw_eq_eth_cmd c;
2879 bzero(&c, sizeof(c));
2881 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
2882 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
2883 V_FW_EQ_ETH_CMD_VFN(0));
2884 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
2885 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
2886 c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
2887 c.fetchszm_to_iqid =
2888 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2889 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
2890 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
2891 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2892 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2893 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2894 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize));
2895 c.eqaddr = htobe64(eq->ba);
2897 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2899 device_printf(pi->dev,
2900 "failed to create Ethernet egress queue: %d\n", rc);
2903 eq->flags |= EQ_ALLOCATED;
2905 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
2906 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2907 if (cntxt_id >= sc->sge.neq)
2908 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2909 cntxt_id, sc->sge.neq - 1);
2910 sc->sge.eqmap[cntxt_id] = eq;
2917 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2920 struct fw_eq_ofld_cmd c;
2922 bzero(&c, sizeof(c));
2924 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
2925 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
2926 V_FW_EQ_OFLD_CMD_VFN(0));
2927 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
2928 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
2929 c.fetchszm_to_iqid =
2930 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2931 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
2932 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
2934 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2935 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2936 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2937 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize));
2938 c.eqaddr = htobe64(eq->ba);
2940 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2942 device_printf(pi->dev,
2943 "failed to create egress queue for TCP offload: %d\n", rc);
2946 eq->flags |= EQ_ALLOCATED;
2948 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
2949 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2950 if (cntxt_id >= sc->sge.neq)
2951 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2952 cntxt_id, sc->sge.neq - 1);
2953 sc->sge.eqmap[cntxt_id] = eq;
2960 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2965 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
2967 len = eq->qsize * EQ_ESIZE;
2968 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
2969 &eq->ba, (void **)&eq->desc);
2973 eq->cap = eq->qsize - spg_len / EQ_ESIZE;
2974 eq->spg = (void *)&eq->desc[eq->cap];
2975 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */
2976 eq->pidx = eq->cidx = 0;
2977 eq->doorbells = sc->doorbells;
2979 switch (eq->flags & EQ_TYPEMASK) {
2981 rc = ctrl_eq_alloc(sc, eq);
2985 rc = eth_eq_alloc(sc, pi, eq);
2990 rc = ofld_eq_alloc(sc, pi, eq);
2995 panic("%s: invalid eq type %d.", __func__,
2996 eq->flags & EQ_TYPEMASK);
2999 device_printf(sc->dev,
3000 "failed to allocate egress queue(%d): %d\n",
3001 eq->flags & EQ_TYPEMASK, rc);
3004 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus;
3006 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3007 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3008 isset(&eq->doorbells, DOORBELL_WCWR)) {
3009 uint32_t s_qpp = sc->sge.eq_s_qpp;
3010 uint32_t mask = (1 << s_qpp) - 1;
3011 volatile uint8_t *udb;
3013 udb = sc->udbs_base + UDBS_DB_OFFSET;
3014 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3015 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3016 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3017 clrbit(&eq->doorbells, DOORBELL_WCWR);
3019 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3022 eq->udb = (volatile void *)udb;
3029 free_eq(struct adapter *sc, struct sge_eq *eq)
3033 if (eq->flags & EQ_ALLOCATED) {
3034 switch (eq->flags & EQ_TYPEMASK) {
3036 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3041 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3047 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3053 panic("%s: invalid eq type %d.", __func__,
3054 eq->flags & EQ_TYPEMASK);
3057 device_printf(sc->dev,
3058 "failed to free egress queue (%d): %d\n",
3059 eq->flags & EQ_TYPEMASK, rc);
3062 eq->flags &= ~EQ_ALLOCATED;
3065 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3067 if (mtx_initialized(&eq->eq_lock))
3068 mtx_destroy(&eq->eq_lock);
3070 bzero(eq, sizeof(*eq));
3075 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
3076 struct sysctl_oid *oid)
3079 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
3080 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3082 rc = alloc_eq(sc, pi, &wrq->eq);
3087 STAILQ_INIT(&wrq->wr_list);
3089 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3090 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3091 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3092 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3094 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3095 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3097 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD,
3098 &wrq->tx_wrs, "# of work requests");
3099 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
3101 "# of times queue ran out of hardware descriptors");
3102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
3103 &wrq->eq.unstalled, 0, "# of times queue recovered after stall");
3109 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3113 rc = free_eq(sc, &wrq->eq);
3117 bzero(wrq, sizeof(*wrq));
3122 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
3123 struct sysctl_oid *oid)
3126 struct adapter *sc = pi->adapter;
3127 struct sge_eq *eq = &txq->eq;
3129 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3131 rc = alloc_eq(sc, pi, eq);
3137 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE,
3139 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock);
3141 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR,
3142 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS,
3143 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag);
3145 device_printf(sc->dev,
3146 "failed to create tx DMA tag: %d\n", rc);
3151 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE
3152 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is
3153 * sized for the worst case.
3155 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8,
3158 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc);
3162 snprintf(name, sizeof(name), "%d", idx);
3163 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3165 children = SYSCTL_CHILDREN(oid);
3167 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3168 &eq->cntxt_id, 0, "SGE context id of the queue");
3169 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3170 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3172 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3173 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3176 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3177 &txq->txcsum, "# of times hardware assisted with checksum");
3178 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion",
3179 CTLFLAG_RD, &txq->vlan_insertion,
3180 "# of times hardware inserted 802.1Q tag");
3181 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3182 &txq->tso_wrs, "# of TSO work requests");
3183 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3184 &txq->imm_wrs, "# of work requests with immediate data");
3185 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3186 &txq->sgl_wrs, "# of work requests with direct SGL");
3187 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3188 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3189 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD,
3190 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)");
3191 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD,
3192 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests");
3194 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD,
3195 &txq->br->br_drops, "# of drops in the buf_ring for this queue");
3196 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD,
3197 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps");
3198 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
3199 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors");
3200 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD,
3201 &eq->egr_update, 0, "egress update notifications from the SGE");
3202 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
3203 &eq->unstalled, 0, "# of times txq recovered after stall");
3209 free_txq(struct port_info *pi, struct sge_txq *txq)
3212 struct adapter *sc = pi->adapter;
3213 struct sge_eq *eq = &txq->eq;
3215 rc = free_eq(sc, eq);
3219 free(txq->sdesc, M_CXGBE);
3221 if (txq->txmaps.maps)
3222 t4_free_tx_maps(&txq->txmaps, txq->tx_tag);
3224 buf_ring_free(txq->br, M_CXGBE);
3227 bus_dma_tag_destroy(txq->tx_tag);
3229 bzero(txq, sizeof(*txq));
3234 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3236 bus_addr_t *ba = arg;
3239 ("%s meant for single segment mappings only.", __func__));
3241 *ba = error ? 0 : segs->ds_addr;
3245 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3249 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3253 v = fl->dbval | V_PIDX(n);
3255 *fl->udb = htole32(v);
3257 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3258 IDXINCR(fl->dbidx, n, fl->sidx);
3262 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3263 * recycled do not count towards this allocation budget.
3265 * Returns non-zero to indicate that this freelist should be added to the list
3266 * of starving freelists.
3269 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3272 struct fl_sdesc *sd;
3275 struct cluster_layout *cll;
3276 struct sw_zone_info *swz;
3277 struct cluster_metadata *clm;
3279 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3281 FL_LOCK_ASSERT_OWNED(fl);
3284 * We always stop at the begining of the hardware descriptor that's just
3285 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3286 * which would mean an empty freelist to the chip.
3288 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3289 if (fl->pidx == max_pidx * 8)
3292 d = &fl->desc[fl->pidx];
3293 sd = &fl->sdesc[fl->pidx];
3294 cll = &fl->cll_def; /* default layout */
3295 swz = &sc->sge.sw_zone_info[cll->zidx];
3299 if (sd->cl != NULL) {
3301 if (sd->nmbuf == 0) {
3303 * Fast recycle without involving any atomics on
3304 * the cluster's metadata (if the cluster has
3305 * metadata). This happens when all frames
3306 * received in the cluster were small enough to
3307 * fit within a single mbuf each.
3309 fl->cl_fast_recycled++;
3311 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3313 MPASS(clm->refcount == 1);
3319 * Cluster is guaranteed to have metadata. Clusters
3320 * without metadata always take the fast recycle path
3321 * when they're recycled.
3323 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3326 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3328 counter_u64_add(extfree_rels, 1);
3331 sd->cl = NULL; /* gave up my reference */
3333 MPASS(sd->cl == NULL);
3335 cl = uma_zalloc(swz->zone, M_NOWAIT);
3336 if (__predict_false(cl == NULL)) {
3337 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3338 fl->cll_def.zidx == fl->cll_alt.zidx)
3341 /* fall back to the safe zone */
3343 swz = &sc->sge.sw_zone_info[cll->zidx];
3349 pa = pmap_kextract((vm_offset_t)cl);
3353 *d = htobe64(pa | cll->hwidx);
3354 clm = cl_metadata(sc, fl, cll, cl);
3366 if (__predict_false(++fl->pidx % 8 == 0)) {
3367 uint16_t pidx = fl->pidx / 8;
3369 if (__predict_false(pidx == fl->sidx)) {
3375 if (pidx == max_pidx)
3378 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3383 if (fl->pidx / 8 != fl->dbidx)
3386 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3390 * Attempt to refill all starving freelists.
3393 refill_sfl(void *arg)
3395 struct adapter *sc = arg;
3396 struct sge_fl *fl, *fl_temp;
3398 mtx_lock(&sc->sfl_lock);
3399 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3401 refill_fl(sc, fl, 64);
3402 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3403 TAILQ_REMOVE(&sc->sfl, fl, link);
3404 fl->flags &= ~FL_STARVING;
3409 if (!TAILQ_EMPTY(&sc->sfl))
3410 callout_schedule(&sc->sfl_callout, hz / 5);
3411 mtx_unlock(&sc->sfl_lock);
3415 alloc_fl_sdesc(struct sge_fl *fl)
3418 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3425 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3427 struct fl_sdesc *sd;
3428 struct cluster_metadata *clm;
3429 struct cluster_layout *cll;
3433 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3438 clm = cl_metadata(sc, fl, cll, sd->cl);
3440 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3441 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3442 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3443 counter_u64_add(extfree_rels, 1);
3448 free(fl->sdesc, M_CXGBE);
3453 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count,
3459 txmaps->map_total = txmaps->map_avail = count;
3460 txmaps->map_cidx = txmaps->map_pidx = 0;
3462 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE,
3466 for (i = 0; i < count; i++, txm++) {
3467 rc = bus_dmamap_create(tx_tag, 0, &txm->map);
3476 bus_dmamap_destroy(tx_tag, txm->map);
3478 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__));
3480 free(txmaps->maps, M_CXGBE);
3481 txmaps->maps = NULL;
3487 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag)
3493 for (i = 0; i < txmaps->map_total; i++, txm++) {
3496 bus_dmamap_unload(tx_tag, txm->map);
3501 bus_dmamap_destroy(tx_tag, txm->map);
3504 free(txmaps->maps, M_CXGBE);
3505 txmaps->maps = NULL;
3509 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're
3510 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes
3511 * of immediate data.
3515 - sizeof(struct fw_eth_tx_pkt_wr) \
3516 - sizeof(struct cpl_tx_pkt_core))
3519 * Returns non-zero on failure, no need to cleanup anything in that case.
3521 * Note 1: We always try to defrag the mbuf if required and return EFBIG only
3522 * if the resulting chain still won't fit in a tx descriptor.
3524 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf
3525 * does not have the TCP header in it.
3528 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl,
3531 struct mbuf *m = *fp;
3532 struct tx_maps *txmaps;
3534 int rc, defragged = 0, n;
3536 TXQ_LOCK_ASSERT_OWNED(txq);
3538 if (m->m_pkthdr.tso_segsz)
3539 sgl_only = 1; /* Do not allow immediate data with LSO */
3541 start: sgl->nsegs = 0;
3543 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only)
3544 return (0); /* nsegs = 0 tells caller to use imm. tx */
3546 txmaps = &txq->txmaps;
3547 if (txmaps->map_avail == 0) {
3551 txm = &txmaps->maps[txmaps->map_pidx];
3553 if (m->m_pkthdr.tso_segsz && m->m_len < 50) {
3554 *fp = m_pullup(m, 50);
3560 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg,
3561 &sgl->nsegs, BUS_DMA_NOWAIT);
3562 if (rc == EFBIG && defragged == 0) {
3563 m = m_defrag(m, M_NOWAIT);
3575 txmaps->map_avail--;
3576 if (++txmaps->map_pidx == txmaps->map_total)
3577 txmaps->map_pidx = 0;
3579 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS,
3580 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs));
3583 * Store the # of flits required to hold this frame's SGL in nflits. An
3584 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by
3585 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used
3586 * then len1 must be set to 0.
3589 sgl->nflits = (3 * n) / 2 + (n & 1) + 2;
3596 * Releases all the txq resources used up in the specified sgl.
3599 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl)
3601 struct tx_maps *txmaps;
3604 TXQ_LOCK_ASSERT_OWNED(txq);
3606 if (sgl->nsegs == 0)
3607 return (0); /* didn't use any map */
3609 txmaps = &txq->txmaps;
3611 /* 1 pkt uses exactly 1 map, back it out */
3613 txmaps->map_avail++;
3614 if (txmaps->map_pidx > 0)
3617 txmaps->map_pidx = txmaps->map_total - 1;
3619 txm = &txmaps->maps[txmaps->map_pidx];
3620 bus_dmamap_unload(txq->tx_tag, txm->map);
3627 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m,
3630 struct sge_eq *eq = &txq->eq;
3631 struct fw_eth_tx_pkt_wr *wr;
3632 struct cpl_tx_pkt_core *cpl;
3633 uint32_t ctrl; /* used in many unrelated places */
3635 int nflits, ndesc, pktlen;
3636 struct tx_sdesc *txsd;
3639 TXQ_LOCK_ASSERT_OWNED(txq);
3641 pktlen = m->m_pkthdr.len;
3644 * Do we have enough flits to send this frame out?
3646 ctrl = sizeof(struct cpl_tx_pkt_core);
3647 if (m->m_pkthdr.tso_segsz) {
3648 nflits = TXPKT_LSO_WR_HDR;
3649 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3651 nflits = TXPKT_WR_HDR;
3653 nflits += sgl->nflits;
3655 nflits += howmany(pktlen, 8);
3658 ndesc = howmany(nflits, 8);
3659 if (ndesc > eq->avail)
3662 /* Firmware work request header */
3663 wr = (void *)&eq->desc[eq->pidx];
3664 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3665 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3666 ctrl = V_FW_WR_LEN16(howmany(nflits, 2));
3667 if (eq->avail == ndesc) {
3668 if (!(eq->flags & EQ_CRFLUSHED)) {
3669 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3670 eq->flags |= EQ_CRFLUSHED;
3672 eq->flags |= EQ_STALLED;
3675 wr->equiq_to_len16 = htobe32(ctrl);
3678 if (m->m_pkthdr.tso_segsz) {
3679 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3680 struct ether_header *eh;
3682 #if defined(INET) || defined(INET6)
3687 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3690 eh = mtod(m, struct ether_header *);
3691 eh_type = ntohs(eh->ether_type);
3692 if (eh_type == ETHERTYPE_VLAN) {
3693 struct ether_vlan_header *evh = (void *)eh;
3695 ctrl |= V_LSO_ETHHDR_LEN(1);
3697 eh_type = ntohs(evh->evl_proto);
3703 case ETHERTYPE_IPV6:
3705 struct ip6_hdr *ip6 = l3hdr;
3708 * XXX-BZ For now we do not pretend to support
3709 * IPv6 extension headers.
3711 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO "
3712 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt));
3713 tcp = (struct tcphdr *)(ip6 + 1);
3715 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) |
3716 V_LSO_TCPHDR_LEN(tcp->th_off);
3723 struct ip *ip = l3hdr;
3725 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4);
3726 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) |
3727 V_LSO_TCPHDR_LEN(tcp->th_off);
3732 panic("%s: CSUM_TSO but no supported IP version "
3733 "(0x%04x)", __func__, eh_type);
3736 lso->lso_ctrl = htobe32(ctrl);
3737 lso->ipid_ofst = htobe16(0);
3738 lso->mss = htobe16(m->m_pkthdr.tso_segsz);
3739 lso->seqno_offset = htobe32(0);
3740 lso->len = htobe32(pktlen);
3742 cpl = (void *)(lso + 1);
3746 cpl = (void *)(wr + 1);
3748 /* Checksum offload */
3750 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3751 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3752 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3753 CSUM_TCP_IPV6 | CSUM_TSO)))
3754 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3755 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3756 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3757 txq->txcsum++; /* some hardware assistance provided */
3759 /* VLAN tag insertion */
3760 if (m->m_flags & M_VLANTAG) {
3761 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3762 txq->vlan_insertion++;
3766 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3767 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
3769 cpl->len = htobe16(pktlen);
3770 cpl->ctrl1 = htobe64(ctrl1);
3772 /* Software descriptor */
3773 txsd = &txq->sdesc[eq->pidx];
3774 txsd->desc_used = ndesc;
3776 eq->pending += ndesc;
3779 if (eq->pidx >= eq->cap)
3780 eq->pidx -= eq->cap;
3783 dst = (void *)(cpl + 1);
3784 if (sgl->nsegs > 0) {
3787 write_sgl_to_txd(eq, sgl, &dst);
3791 for (; m; m = m->m_next) {
3792 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3798 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3808 * Returns 0 to indicate that m has been accepted into a coalesced tx work
3809 * request. It has either been folded into txpkts or txpkts was flushed and m
3810 * has started a new coalesced work request (as the first frame in a fresh
3813 * Returns non-zero to indicate a failure - caller is responsible for
3814 * transmitting m, if there was anything in txpkts it has been flushed.
3817 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts,
3818 struct mbuf *m, struct sgl *sgl)
3820 struct sge_eq *eq = &txq->eq;
3822 struct tx_sdesc *txsd;
3825 TXQ_LOCK_ASSERT_OWNED(txq);
3827 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__));
3829 if (txpkts->npkt > 0) {
3830 flits = TXPKTS_PKT_HDR + sgl->nflits;
3831 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3832 txpkts->nflits + flits <= TX_WR_FLITS &&
3833 txpkts->nflits + flits <= eq->avail * 8 &&
3834 txpkts->plen + m->m_pkthdr.len < 65536;
3838 txpkts->nflits += flits;
3839 txpkts->plen += m->m_pkthdr.len;
3841 txsd = &txq->sdesc[eq->pidx];
3848 * Couldn't coalesce m into txpkts. The first order of business
3849 * is to send txpkts on its way. Then we'll revisit m.
3851 write_txpkts_wr(txq, txpkts);
3855 * Check if we can start a new coalesced tx work request with m as
3856 * the first packet in it.
3859 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__));
3861 flits = TXPKTS_WR_HDR + sgl->nflits;
3862 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3863 flits <= eq->avail * 8 && flits <= TX_WR_FLITS;
3865 if (can_coalesce == 0)
3869 * Start a fresh coalesced tx WR with m as the first frame in it.
3872 txpkts->nflits = flits;
3873 txpkts->flitp = &eq->desc[eq->pidx].flit[2];
3874 txpkts->plen = m->m_pkthdr.len;
3876 txsd = &txq->sdesc[eq->pidx];
3883 * Note that write_txpkts_wr can never run out of hardware descriptors (but
3884 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for
3885 * coalescing only if sufficient hardware descriptors are available.
3888 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts)
3890 struct sge_eq *eq = &txq->eq;
3891 struct fw_eth_tx_pkts_wr *wr;
3892 struct tx_sdesc *txsd;
3896 TXQ_LOCK_ASSERT_OWNED(txq);
3898 ndesc = howmany(txpkts->nflits, 8);
3900 wr = (void *)&eq->desc[eq->pidx];
3901 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
3902 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2));
3903 if (eq->avail == ndesc) {
3904 if (!(eq->flags & EQ_CRFLUSHED)) {
3905 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3906 eq->flags |= EQ_CRFLUSHED;
3908 eq->flags |= EQ_STALLED;
3910 wr->equiq_to_len16 = htobe32(ctrl);
3911 wr->plen = htobe16(txpkts->plen);
3912 wr->npkt = txpkts->npkt;
3913 wr->r3 = wr->type = 0;
3915 /* Everything else already written */
3917 txsd = &txq->sdesc[eq->pidx];
3918 txsd->desc_used = ndesc;
3920 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__));
3922 eq->pending += ndesc;
3925 if (eq->pidx >= eq->cap)
3926 eq->pidx -= eq->cap;
3928 txq->txpkts_pkts += txpkts->npkt;
3930 txpkts->npkt = 0; /* emptied */
3934 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq,
3935 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl)
3937 struct ulp_txpkt *ulpmc;
3938 struct ulptx_idata *ulpsc;
3939 struct cpl_tx_pkt_core *cpl;
3940 struct sge_eq *eq = &txq->eq;
3941 uintptr_t flitp, start, end;
3945 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__));
3947 start = (uintptr_t)eq->desc;
3948 end = (uintptr_t)eq->spg;
3950 /* Checksum offload */
3952 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3953 ctrl |= F_TXPKT_IPCSUM_DIS;
3954 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3955 CSUM_TCP_IPV6 | CSUM_TSO)))
3956 ctrl |= F_TXPKT_L4CSUM_DIS;
3957 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3958 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3959 txq->txcsum++; /* some hardware assistance provided */
3961 /* VLAN tag insertion */
3962 if (m->m_flags & M_VLANTAG) {
3963 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3964 txq->vlan_insertion++;
3968 * The previous packet's SGL must have ended at a 16 byte boundary (this
3969 * is required by the firmware/hardware). It follows that flitp cannot
3970 * wrap around between the ULPTX master command and ULPTX subcommand (8
3971 * bytes each), and that it can not wrap around in the middle of the
3972 * cpl_tx_pkt_core either.
3974 flitp = (uintptr_t)txpkts->flitp;
3975 KASSERT((flitp & 0xf) == 0,
3976 ("%s: last SGL did not end at 16 byte boundary: %p",
3977 __func__, txpkts->flitp));
3979 /* ULP master command */
3980 ulpmc = (void *)flitp;
3981 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) |
3982 V_ULP_TXPKT_FID(eq->iqid));
3983 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) +
3984 sizeof(*cpl) + 8 * sgl->nflits, 16));
3986 /* ULP subcommand */
3987 ulpsc = (void *)(ulpmc + 1);
3988 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) |
3990 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
3992 flitp += sizeof(*ulpmc) + sizeof(*ulpsc);
3997 cpl = (void *)flitp;
3998 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3999 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
4001 cpl->len = htobe16(m->m_pkthdr.len);
4002 cpl->ctrl1 = htobe64(ctrl);
4004 flitp += sizeof(*cpl);
4008 /* SGL for this frame */
4009 dst = (caddr_t)flitp;
4010 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst);
4011 txpkts->flitp = (void *)dst;
4013 KASSERT(((uintptr_t)dst & 0xf) == 0,
4014 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst));
4018 * If the SGL ends on an address that is not 16 byte aligned, this function will
4019 * add a 0 filled flit at the end. It returns 1 in that case.
4022 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to)
4024 __be64 *flitp, *end;
4025 struct ulptx_sgl *usgl;
4026 bus_dma_segment_t *seg;
4029 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0,
4030 ("%s: bad SGL - nsegs=%d, nflits=%d",
4031 __func__, sgl->nsegs, sgl->nflits));
4033 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4034 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4036 flitp = (__be64 *)(*to);
4037 end = flitp + sgl->nflits;
4039 usgl = (void *)flitp;
4042 * We start at a 16 byte boundary somewhere inside the tx descriptor
4043 * ring, so we're at least 16 bytes away from the status page. There is
4044 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4047 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4048 V_ULPTX_NSGE(sgl->nsegs));
4049 usgl->len0 = htobe32(seg->ds_len);
4050 usgl->addr0 = htobe64(seg->ds_addr);
4053 if ((uintptr_t)end <= (uintptr_t)eq->spg) {
4055 /* Won't wrap around at all */
4057 for (i = 0; i < sgl->nsegs - 1; i++, seg++) {
4058 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len);
4059 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr);
4062 usgl->sge[i / 2].len[1] = htobe32(0);
4065 /* Will wrap somewhere in the rest of the SGL */
4067 /* 2 flits already written, write the rest flit by flit */
4068 flitp = (void *)(usgl + 1);
4069 for (i = 0; i < sgl->nflits - 2; i++) {
4070 if ((uintptr_t)flitp == (uintptr_t)eq->spg)
4071 flitp = (void *)eq->desc;
4072 *flitp++ = get_flit(seg, sgl->nsegs - 1, i);
4077 if ((uintptr_t)end & 0xf) {
4078 *(uint64_t *)end = 0;
4084 if ((uintptr_t)end == (uintptr_t)eq->spg)
4085 *to = (void *)eq->desc;
4093 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4095 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) {
4096 bcopy(from, *to, len);
4099 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to);
4101 bcopy(from, *to, portion);
4103 portion = len - portion; /* remaining */
4104 bcopy(from, (void *)eq->desc, portion);
4105 (*to) = (caddr_t)eq->desc + portion;
4110 ring_eq_db(struct adapter *sc, struct sge_eq *eq)
4115 pending = eq->pending;
4117 clrbit(&db, DOORBELL_WCWR);
4121 switch (ffs(db) - 1) {
4123 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
4126 case DOORBELL_WCWR: {
4127 volatile uint64_t *dst, *src;
4131 * Queues whose 128B doorbell segment fits in the page do not
4132 * use relative qid (udb_qid is always 0). Only queues with
4133 * doorbell segments can do WCWR.
4135 KASSERT(eq->udb_qid == 0 && pending == 1,
4136 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4137 __func__, eq->doorbells, pending, eq->pidx, eq));
4139 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4141 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1;
4142 src = (void *)&eq->desc[i];
4143 while (src != (void *)&eq->desc[i + 1])
4149 case DOORBELL_UDBWC:
4150 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
4155 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4156 V_QID(eq->cntxt_id) | V_PIDX(pending));
4162 reclaimable(struct sge_eq *eq)
4166 cidx = eq->spg->cidx; /* stable snapshot */
4167 cidx = be16toh(cidx);
4169 if (cidx >= eq->cidx)
4170 return (cidx - eq->cidx);
4172 return (cidx + eq->cap - eq->cidx);
4176 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as
4177 * many as possible but stop when there are around "n" mbufs to free.
4179 * The actual number reclaimed is provided as the return value.
4182 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
4184 struct tx_sdesc *txsd;
4185 struct tx_maps *txmaps;
4187 unsigned int reclaimed, maps;
4188 struct sge_eq *eq = &txq->eq;
4190 TXQ_LOCK_ASSERT_OWNED(txq);
4192 if (can_reclaim == 0)
4193 can_reclaim = reclaimable(eq);
4195 maps = reclaimed = 0;
4196 while (can_reclaim && maps < n) {
4199 txsd = &txq->sdesc[eq->cidx];
4200 ndesc = txsd->desc_used;
4202 /* Firmware doesn't return "partial" credits. */
4203 KASSERT(can_reclaim >= ndesc,
4204 ("%s: unexpected number of credits: %d, %d",
4205 __func__, can_reclaim, ndesc));
4207 maps += txsd->credits;
4210 can_reclaim -= ndesc;
4213 if (__predict_false(eq->cidx >= eq->cap))
4214 eq->cidx -= eq->cap;
4217 txmaps = &txq->txmaps;
4218 txm = &txmaps->maps[txmaps->map_cidx];
4222 eq->avail += reclaimed;
4223 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */
4224 ("%s: too many descriptors available", __func__));
4226 txmaps->map_avail += maps;
4227 KASSERT(txmaps->map_avail <= txmaps->map_total,
4228 ("%s: too many maps available", __func__));
4231 struct tx_map *next;
4234 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total))
4235 next = txmaps->maps;
4238 bus_dmamap_unload(txq->tx_tag, txm->map);
4243 if (__predict_false(++txmaps->map_cidx == txmaps->map_total))
4244 txmaps->map_cidx = 0;
4251 write_eqflush_wr(struct sge_eq *eq)
4253 struct fw_eq_flush_wr *wr;
4255 EQ_LOCK_ASSERT_OWNED(eq);
4256 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__));
4257 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__));
4259 wr = (void *)&eq->desc[eq->pidx];
4260 bzero(wr, sizeof(*wr));
4261 wr->opcode = FW_EQ_FLUSH_WR;
4262 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) |
4263 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
4265 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED);
4268 if (++eq->pidx == eq->cap)
4273 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx)
4275 int i = (idx / 3) * 2;
4281 rc = htobe32(sgl[i].ds_len);
4283 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32;
4288 return htobe64(sgl[i].ds_addr);
4290 return htobe64(sgl[i + 1].ds_addr);
4297 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4299 int8_t zidx, hwidx, idx;
4300 uint16_t region1, region3;
4301 int spare, spare_needed, n;
4302 struct sw_zone_info *swz;
4303 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4306 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4307 * large enough for the max payload and cluster metadata. Otherwise
4308 * settle for the largest bufsize that leaves enough room in the cluster
4311 * Without buffer packing: Look for the smallest zone which has a
4312 * bufsize large enough for the max payload. Settle for the largest
4313 * bufsize available if there's nothing big enough for max payload.
4315 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4316 swz = &sc->sge.sw_zone_info[0];
4318 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4319 if (swz->size > largest_rx_cluster) {
4320 if (__predict_true(hwidx != -1))
4324 * This is a misconfiguration. largest_rx_cluster is
4325 * preventing us from finding a refill source. See
4326 * dev.t5nex.<n>.buffer_sizes to figure out why.
4328 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4329 " refill source for fl %p (dma %u). Ignored.\n",
4330 largest_rx_cluster, fl, maxp);
4332 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4333 hwb = &hwb_list[idx];
4334 spare = swz->size - hwb->size;
4335 if (spare < spare_needed)
4338 hwidx = idx; /* best option so far */
4339 if (hwb->size >= maxp) {
4341 if ((fl->flags & FL_BUF_PACKING) == 0)
4342 goto done; /* stop looking (not packing) */
4344 if (swz->size >= safest_rx_cluster)
4345 goto done; /* stop looking (packing) */
4347 break; /* keep looking, next zone */
4351 /* A usable hwidx has been located. */
4353 hwb = &hwb_list[hwidx];
4355 swz = &sc->sge.sw_zone_info[zidx];
4357 region3 = swz->size - hwb->size;
4360 * Stay within this zone and see if there is a better match when mbuf
4361 * inlining is allowed. Remember that the hwidx's are sorted in
4362 * decreasing order of size (so in increasing order of spare area).
4364 for (idx = hwidx; idx != -1; idx = hwb->next) {
4365 hwb = &hwb_list[idx];
4366 spare = swz->size - hwb->size;
4368 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4370 if (spare < CL_METADATA_SIZE + MSIZE)
4372 n = (spare - CL_METADATA_SIZE) / MSIZE;
4373 if (n > howmany(hwb->size, maxp))
4377 if (fl->flags & FL_BUF_PACKING) {
4378 region1 = n * MSIZE;
4379 region3 = spare - region1;
4382 region3 = spare - region1;
4387 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4388 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4389 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4390 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4391 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4392 sc->sge.sw_zone_info[zidx].size,
4393 ("%s: bad buffer layout for fl %p, maxp %d. "
4394 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4395 sc->sge.sw_zone_info[zidx].size, region1,
4396 sc->sge.hw_buf_info[hwidx].size, region3));
4397 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4398 KASSERT(region3 >= CL_METADATA_SIZE,
4399 ("%s: no room for metadata. fl %p, maxp %d; "
4400 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4401 sc->sge.sw_zone_info[zidx].size, region1,
4402 sc->sge.hw_buf_info[hwidx].size, region3));
4403 KASSERT(region1 % MSIZE == 0,
4404 ("%s: bad mbuf region for fl %p, maxp %d. "
4405 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4406 sc->sge.sw_zone_info[zidx].size, region1,
4407 sc->sge.hw_buf_info[hwidx].size, region3));
4410 fl->cll_def.zidx = zidx;
4411 fl->cll_def.hwidx = hwidx;
4412 fl->cll_def.region1 = region1;
4413 fl->cll_def.region3 = region3;
4417 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4419 struct sge *s = &sc->sge;
4420 struct hw_buf_info *hwb;
4421 struct sw_zone_info *swz;
4425 if (fl->flags & FL_BUF_PACKING)
4426 hwidx = s->safe_hwidx2; /* with room for metadata */
4427 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4428 hwidx = s->safe_hwidx2;
4429 hwb = &s->hw_buf_info[hwidx];
4430 swz = &s->sw_zone_info[hwb->zidx];
4431 spare = swz->size - hwb->size;
4433 /* no good if there isn't room for an mbuf as well */
4434 if (spare < CL_METADATA_SIZE + MSIZE)
4435 hwidx = s->safe_hwidx1;
4437 hwidx = s->safe_hwidx1;
4440 /* No fallback source */
4441 fl->cll_alt.hwidx = -1;
4442 fl->cll_alt.zidx = -1;
4447 hwb = &s->hw_buf_info[hwidx];
4448 swz = &s->sw_zone_info[hwb->zidx];
4449 spare = swz->size - hwb->size;
4450 fl->cll_alt.hwidx = hwidx;
4451 fl->cll_alt.zidx = hwb->zidx;
4452 if (allow_mbufs_in_cluster)
4453 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4455 fl->cll_alt.region1 = 0;
4456 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4460 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4462 mtx_lock(&sc->sfl_lock);
4464 if ((fl->flags & FL_DOOMED) == 0) {
4465 fl->flags |= FL_STARVING;
4466 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4467 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4470 mtx_unlock(&sc->sfl_lock);
4474 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4477 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4478 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4479 struct adapter *sc = iq->adapter;
4480 struct sge *s = &sc->sge;
4483 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4486 eq = s->eqmap[qid - s->eq_start];
4488 KASSERT(eq->flags & EQ_CRFLUSHED,
4489 ("%s: unsolicited egress update", __func__));
4490 eq->flags &= ~EQ_CRFLUSHED;
4493 if (__predict_false(eq->flags & EQ_DOOMED))
4495 else if (eq->flags & EQ_STALLED && can_resume_tx(eq))
4496 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
4502 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4503 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4504 offsetof(struct cpl_fw6_msg, data));
4507 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4509 struct adapter *sc = iq->adapter;
4510 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4512 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4515 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4516 const struct rss_header *rss2;
4518 rss2 = (const struct rss_header *)&cpl->data[0];
4519 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4522 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4526 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4528 uint16_t *id = arg1;
4531 return sysctl_handle_int(oidp, &i, 0, req);
4535 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4537 struct sge *s = arg1;
4538 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4539 struct sw_zone_info *swz = &s->sw_zone_info[0];
4544 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4545 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4546 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4551 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4555 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);