2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
71 #include "t4_mp_ring.h"
73 #ifdef T4_PKT_TIMESTAMP
74 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
76 #define RX_COPY_THRESHOLD MINCLSIZE
80 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
81 * 0-7 are valid values.
84 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
87 * Pad ethernet payload up to this boundary.
88 * -1: driver should figure out a good value.
90 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
93 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
97 * -1: driver should figure out a good value.
98 * 64 or 128 are the only other valid values.
101 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
105 * -1: no congestion feedback (not recommended).
106 * 0: backpressure the channel instead of dropping packets right away.
107 * 1: no backpressure, drop packets for the congested queue immediately.
109 static int cong_drop = 0;
110 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
113 * Deliver multiple frames in the same free list buffer if they fit.
114 * -1: let the driver decide whether to enable buffer packing or not.
115 * 0: disable buffer packing.
116 * 1: enable buffer packing.
118 static int buffer_packing = -1;
119 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
122 * Start next frame in a packed buffer at this boundary.
123 * -1: driver should figure out a good value.
124 * T4: driver will ignore this and use the same value as fl_pad above.
125 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
127 static int fl_pack = -1;
128 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
131 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
132 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
133 * 1: ok to create mbuf(s) within a cluster if there is room.
135 static int allow_mbufs_in_cluster = 1;
136 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
139 * Largest rx cluster size that the driver is allowed to allocate.
141 static int largest_rx_cluster = MJUM16BYTES;
142 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
145 * Size of cluster allocation that's most likely to succeed. The driver will
146 * fall back to this size if it fails to allocate clusters larger than this.
148 static int safest_rx_cluster = PAGE_SIZE;
149 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
152 u_int wr_type; /* type 0 or type 1 */
153 u_int npkt; /* # of packets in this work request */
154 u_int plen; /* total payload (sum of all packets) */
155 u_int len16; /* # of 16B pieces used by this work request */
158 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
161 struct sglist_seg seg[TX_SGL_SEGS];
164 static int service_iq(struct sge_iq *, int);
165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
169 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
172 bus_addr_t *, void **);
173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
175 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
177 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
180 static int alloc_fwq(struct adapter *);
181 static int free_fwq(struct adapter *);
182 static int alloc_mgmtq(struct adapter *);
183 static int free_mgmtq(struct adapter *);
184 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
185 struct sysctl_oid *);
186 static int free_rxq(struct port_info *, struct sge_rxq *);
188 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
189 struct sysctl_oid *);
190 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
193 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int,
194 struct sysctl_oid *);
195 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *);
196 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int,
197 struct sysctl_oid *);
198 static int free_nm_txq(struct port_info *, struct sge_nm_txq *);
200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
201 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
203 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
205 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
206 static int free_eq(struct adapter *, struct sge_eq *);
207 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
208 struct sysctl_oid *);
209 static int free_wrq(struct adapter *, struct sge_wrq *);
210 static int alloc_txq(struct port_info *, struct sge_txq *, int,
211 struct sysctl_oid *);
212 static int free_txq(struct port_info *, struct sge_txq *);
213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
214 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
215 static int refill_fl(struct adapter *, struct sge_fl *, int);
216 static void refill_sfl(void *);
217 static int alloc_fl_sdesc(struct sge_fl *);
218 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
220 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
223 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
224 static inline u_int txpkt_len16(u_int, u_int);
225 static inline u_int txpkts0_len16(u_int);
226 static inline u_int txpkts1_len16(void);
227 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
228 struct mbuf *, u_int);
229 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
230 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
231 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
232 struct mbuf *, const struct txpkts *, u_int);
233 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
234 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
235 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
236 static inline uint16_t read_hw_cidx(struct sge_eq *);
237 static inline u_int reclaimable_tx_desc(struct sge_eq *);
238 static inline u_int total_available_tx_desc(struct sge_eq *);
239 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
240 static void tx_reclaim(void *, int);
241 static __be64 get_flit(struct sglist_seg *, int, int);
242 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
244 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
246 static void wrq_tx_drain(void *, int);
247 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
249 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
250 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
252 static counter_u64_t extfree_refs;
253 static counter_u64_t extfree_rels;
256 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
262 if (fl_pktshift < 0 || fl_pktshift > 7) {
263 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
264 " using 2 instead.\n", fl_pktshift);
268 if (spg_len != 64 && spg_len != 128) {
271 #if defined(__i386__) || defined(__amd64__)
272 len = cpu_clflush_line_size > 64 ? 128 : 64;
277 printf("Invalid hw.cxgbe.spg_len value (%d),"
278 " using %d instead.\n", spg_len, len);
283 if (cong_drop < -1 || cong_drop > 1) {
284 printf("Invalid hw.cxgbe.cong_drop value (%d),"
285 " using 0 instead.\n", cong_drop);
289 extfree_refs = counter_u64_alloc(M_WAITOK);
290 extfree_rels = counter_u64_alloc(M_WAITOK);
291 counter_u64_zero(extfree_refs);
292 counter_u64_zero(extfree_rels);
296 t4_sge_modunload(void)
299 counter_u64_free(extfree_refs);
300 counter_u64_free(extfree_rels);
304 t4_sge_extfree_refs(void)
308 rels = counter_u64_fetch(extfree_rels);
309 refs = counter_u64_fetch(extfree_refs);
311 return (refs - rels);
315 t4_init_sge_cpl_handlers(struct adapter *sc)
318 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
319 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
320 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
321 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
322 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
326 setup_pad_and_pack_boundaries(struct adapter *sc)
332 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
334 * If there is any chance that we might use buffer packing and
335 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
336 * it to 32 in all other cases.
338 pad = is_t4(sc) && buffer_packing ? 64 : 32;
341 * For fl_pad = 0 we'll still write a reasonable value to the
342 * register but all the freelists will opt out of padding.
343 * We'll complain here only if the user tried to set it to a
344 * value greater than 0 that was invalid.
347 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
348 " (%d), using %d instead.\n", fl_pad, pad);
351 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
352 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
353 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
356 if (fl_pack != -1 && fl_pack != pad) {
357 /* Complain but carry on. */
358 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
359 " using %d instead.\n", fl_pack, pad);
365 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
366 !powerof2(fl_pack)) {
367 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
368 MPASS(powerof2(pack));
376 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
377 " (%d), using %d instead.\n", fl_pack, pack);
380 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
382 v = V_INGPACKBOUNDARY(0);
384 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
386 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
387 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
391 * adap->params.vpd.cclk must be set up before this is called.
394 t4_tweak_chip_settings(struct adapter *sc)
398 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
399 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
400 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
401 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
402 static int sge_flbuf_sizes[] = {
404 #if MJUMPAGESIZE != MCLBYTES
406 MJUMPAGESIZE - CL_METADATA_SIZE,
407 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
411 MCLBYTES - MSIZE - CL_METADATA_SIZE,
412 MJUM9BYTES - CL_METADATA_SIZE,
413 MJUM16BYTES - CL_METADATA_SIZE,
416 KASSERT(sc->flags & MASTER_PF,
417 ("%s: trying to change chip settings when not master.", __func__));
419 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
420 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
421 V_EGRSTATUSPAGESIZE(spg_len == 128);
422 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
424 setup_pad_and_pack_boundaries(sc);
426 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
429 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
430 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
431 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
432 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
433 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
434 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
436 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
437 ("%s: hw buffer size table too big", __func__));
438 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
439 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
443 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
444 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
445 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
447 KASSERT(intr_timer[0] <= timer_max,
448 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
450 for (i = 1; i < nitems(intr_timer); i++) {
451 KASSERT(intr_timer[i] >= intr_timer[i - 1],
452 ("%s: timers not listed in increasing order (%d)",
455 while (intr_timer[i] > timer_max) {
456 if (i == nitems(intr_timer) - 1) {
457 intr_timer[i] = timer_max;
460 intr_timer[i] += intr_timer[i - 1];
465 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
466 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
467 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
468 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
469 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
470 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
471 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
472 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
473 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
475 if (cong_drop == 0) {
476 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
478 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0);
481 /* 4K, 16K, 64K, 256K DDP "page sizes" */
482 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
483 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
485 m = v = F_TDDPTAGTCB;
486 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
488 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
490 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
491 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
495 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
496 * padding is is use the buffer's start and end need to be aligned to the pad
497 * boundary as well. We'll just make sure that the size is a multiple of the
498 * boundary here, it is up to the buffer allocation code to make sure the start
499 * of the buffer is aligned as well.
502 hwsz_ok(struct adapter *sc, int hwsz)
504 int mask = fl_pad ? sc->sge.pad_boundary - 1 : 16 - 1;
506 return (hwsz >= 64 && (hwsz & mask) == 0);
510 * XXX: driver really should be able to deal with unexpected settings.
513 t4_read_chip_settings(struct adapter *sc)
515 struct sge *s = &sc->sge;
518 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
519 static int sw_buf_sizes[] = { /* Sorted by size */
521 #if MJUMPAGESIZE != MCLBYTES
527 struct sw_zone_info *swz, *safe_swz;
528 struct hw_buf_info *hwb;
530 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
531 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
532 V_EGRSTATUSPAGESIZE(spg_len == 128);
533 r = t4_read_reg(sc, A_SGE_CONTROL);
535 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
538 s->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
541 s->pack_boundary = s->pad_boundary;
543 r = t4_read_reg(sc, A_SGE_CONTROL2);
544 if (G_INGPACKBOUNDARY(r) == 0)
545 s->pack_boundary = 16;
547 s->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
550 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
551 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
552 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
553 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
554 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
555 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
556 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
557 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
558 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
560 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
564 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
565 hwb = &s->hw_buf_info[0];
566 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
567 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
569 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
574 * Create a sorted list in decreasing order of hw buffer sizes (and so
575 * increasing order of spare area) for each software zone.
577 * If padding is enabled then the start and end of the buffer must align
578 * to the pad boundary; if packing is enabled then they must align with
579 * the pack boundary as well. Allocations from the cluster zones are
580 * aligned to min(size, 4K), so the buffer starts at that alignment and
581 * ends at hwb->size alignment. If mbuf inlining is allowed the
582 * starting alignment will be reduced to MSIZE and the driver will
583 * exercise appropriate caution when deciding on the best buffer layout
586 n = 0; /* no usable buffer size to begin with */
587 swz = &s->sw_zone_info[0];
589 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
590 int8_t head = -1, tail = -1;
592 swz->size = sw_buf_sizes[i];
593 swz->zone = m_getzone(swz->size);
594 swz->type = m_gettype(swz->size);
596 if (swz->size < PAGE_SIZE) {
597 MPASS(powerof2(swz->size));
598 if (fl_pad && (swz->size % sc->sge.pad_boundary != 0))
602 if (swz->size == safest_rx_cluster)
605 hwb = &s->hw_buf_info[0];
606 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
607 if (hwb->zidx != -1 || hwb->size > swz->size)
611 MPASS(hwb->size % sc->sge.pad_boundary == 0);
616 else if (hwb->size < s->hw_buf_info[tail].size) {
617 s->hw_buf_info[tail].next = j;
621 struct hw_buf_info *t;
623 for (cur = &head; *cur != -1; cur = &t->next) {
624 t = &s->hw_buf_info[*cur];
625 if (hwb->size == t->size) {
629 if (hwb->size > t->size) {
637 swz->head_hwidx = head;
638 swz->tail_hwidx = tail;
642 if (swz->size - s->hw_buf_info[tail].size >=
644 sc->flags |= BUF_PACKING_OK;
648 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
654 if (safe_swz != NULL) {
655 s->safe_hwidx1 = safe_swz->head_hwidx;
656 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
659 hwb = &s->hw_buf_info[i];
662 MPASS(hwb->size % sc->sge.pad_boundary == 0);
664 spare = safe_swz->size - hwb->size;
665 if (spare >= CL_METADATA_SIZE) {
672 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
673 s->counter_val[0] = G_THRESHOLD_0(r);
674 s->counter_val[1] = G_THRESHOLD_1(r);
675 s->counter_val[2] = G_THRESHOLD_2(r);
676 s->counter_val[3] = G_THRESHOLD_3(r);
678 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
679 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc);
680 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc);
681 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
682 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc);
683 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc);
684 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
685 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc);
686 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc);
688 if (cong_drop == 0) {
689 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
691 r = t4_read_reg(sc, A_TP_PARA_REG3);
693 device_printf(sc->dev,
694 "invalid TP_PARA_REG3(0x%x)\n", r);
699 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
700 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
702 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
706 m = v = F_TDDPTAGTCB;
707 r = t4_read_reg(sc, A_ULP_RX_CTL);
709 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
713 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
715 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
716 r = t4_read_reg(sc, A_TP_PARA_REG5);
718 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
722 r = t4_read_reg(sc, A_SGE_CONM_CTRL);
723 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
725 s->fl_starve_threshold2 = s->fl_starve_threshold;
727 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
729 /* egress queues: log2 of # of doorbells per BAR2 page */
730 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
731 r >>= S_QUEUESPERPAGEPF0 +
732 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
733 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
735 /* ingress queues: log2 of # of doorbells per BAR2 page */
736 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
737 r >>= S_QUEUESPERPAGEPF0 +
738 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
739 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
741 t4_init_tp_params(sc);
743 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
744 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
750 t4_create_dma_tag(struct adapter *sc)
754 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
755 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
756 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
759 device_printf(sc->dev,
760 "failed to create main DMA tag: %d\n", rc);
767 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
768 struct sysctl_oid_list *children)
771 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
772 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
773 "freelist buffer sizes");
775 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
776 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
778 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
779 NULL, sc->sge.pad_boundary, "payload pad boundary (bytes)");
781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
782 NULL, spg_len, "status page size (bytes)");
784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
785 NULL, cong_drop, "congestion drop setting");
787 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
788 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)");
792 t4_destroy_dma_tag(struct adapter *sc)
795 bus_dma_tag_destroy(sc->dmat);
801 * Allocate and initialize the firmware event queue and the management queue.
803 * Returns errno on failure. Resources allocated up to that point may still be
804 * allocated. Caller is responsible for cleanup in case this function fails.
807 t4_setup_adapter_queues(struct adapter *sc)
811 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
813 sysctl_ctx_init(&sc->ctx);
814 sc->flags |= ADAP_SYSCTL_CTX;
817 * Firmware event queue
824 * Management queue. This is just a control queue that uses the fwq as
827 rc = alloc_mgmtq(sc);
836 t4_teardown_adapter_queues(struct adapter *sc)
839 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
841 /* Do this before freeing the queue */
842 if (sc->flags & ADAP_SYSCTL_CTX) {
843 sysctl_ctx_free(&sc->ctx);
844 sc->flags &= ~ADAP_SYSCTL_CTX;
854 port_intr_count(struct port_info *pi)
858 if (pi->flags & INTR_RXQ)
861 if (pi->flags & INTR_OFLD_RXQ)
865 if (pi->flags & INTR_NM_RXQ)
872 first_vector(struct port_info *pi)
874 struct adapter *sc = pi->adapter;
875 int rc = T4_EXTRA_INTR, i;
877 if (sc->intr_count == 1)
880 for_each_port(sc, i) {
881 if (i == pi->port_id)
884 rc += port_intr_count(sc->port[i]);
891 * Given an arbitrary "index," come up with an iq that can be used by other
892 * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
893 * The iq returned is guaranteed to be something that takes direct interrupts.
895 static struct sge_iq *
896 port_intr_iq(struct port_info *pi, int idx)
898 struct adapter *sc = pi->adapter;
899 struct sge *s = &sc->sge;
900 struct sge_iq *iq = NULL;
903 if (sc->intr_count == 1)
904 return (&sc->sge.fwq);
906 nintr = port_intr_count(pi);
908 ("%s: pi %p has no exclusive interrupts, total interrupts = %d",
909 __func__, pi, sc->intr_count));
911 /* Exclude netmap queues as they can't take anyone else's interrupts */
912 if (pi->flags & INTR_NM_RXQ)
915 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__,
916 pi, nintr, pi->nnmrxq));
920 if (pi->flags & INTR_RXQ) {
922 iq = &s->rxq[pi->first_rxq + i].iq;
928 if (pi->flags & INTR_OFLD_RXQ) {
929 if (i < pi->nofldrxq) {
930 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq;
936 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
937 pi, pi->flags & INTR_ALL, idx, nintr);
940 KASSERT(iq->flags & IQ_INTR,
941 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi,
942 pi->flags & INTR_ALL, idx));
946 /* Maximum payload that can be delivered with a single iq descriptor */
948 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
954 payload = sc->tt.rx_coalesce ?
955 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
958 /* large enough even when hw VLAN extraction is disabled */
959 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
969 t4_setup_port_queues(struct port_info *pi)
971 int rc = 0, i, j, intr_idx, iqid;
974 struct sge_wrq *ctrlq;
976 struct sge_ofld_rxq *ofld_rxq;
977 struct sge_wrq *ofld_txq;
980 struct sge_nm_rxq *nm_rxq;
981 struct sge_nm_txq *nm_txq;
984 struct adapter *sc = pi->adapter;
985 struct ifnet *ifp = pi->ifp;
986 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
987 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
988 int maxp, mtu = ifp->if_mtu;
990 /* Interrupt vector to start from (when using multiple vectors) */
991 intr_idx = first_vector(pi);
994 * First pass over all NIC and TOE rx queues:
995 * a) initialize iq and fl
996 * b) allocate queue iff it will take direct interrupts.
998 maxp = mtu_to_max_payload(sc, mtu, 0);
999 if (pi->flags & INTR_RXQ) {
1000 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1001 CTLFLAG_RD, NULL, "rx queues");
1003 for_each_rxq(pi, i, rxq) {
1005 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq);
1007 snprintf(name, sizeof(name), "%s rxq%d-fl",
1008 device_get_nameunit(pi->dev), i);
1009 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, name);
1011 if (pi->flags & INTR_RXQ) {
1012 rxq->iq.flags |= IQ_INTR;
1013 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1020 maxp = mtu_to_max_payload(sc, mtu, 1);
1021 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) {
1022 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1024 "rx queues for offloaded TCP connections");
1026 for_each_ofld_rxq(pi, i, ofld_rxq) {
1028 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
1031 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1032 device_get_nameunit(pi->dev), i);
1033 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, name);
1035 if (pi->flags & INTR_OFLD_RXQ) {
1036 ofld_rxq->iq.flags |= IQ_INTR;
1037 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1046 * We don't have buffers to back the netmap rx queues right now so we
1047 * create the queues in a way that doesn't set off any congestion signal
1050 if (pi->flags & INTR_NM_RXQ) {
1051 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq",
1052 CTLFLAG_RD, NULL, "rx queues for netmap");
1053 for_each_nm_rxq(pi, i, nm_rxq) {
1054 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid);
1063 * Second pass over all NIC and TOE rx queues. The queues forwarding
1064 * their interrupts are allocated now.
1067 if (!(pi->flags & INTR_RXQ)) {
1068 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1069 CTLFLAG_RD, NULL, "rx queues");
1070 for_each_rxq(pi, i, rxq) {
1071 MPASS(!(rxq->iq.flags & IQ_INTR));
1073 intr_idx = port_intr_iq(pi, j)->abs_id;
1075 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1082 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) {
1083 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1085 "rx queues for offloaded TCP connections");
1086 for_each_ofld_rxq(pi, i, ofld_rxq) {
1087 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1089 intr_idx = port_intr_iq(pi, j)->abs_id;
1091 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1099 if (!(pi->flags & INTR_NM_RXQ))
1100 CXGBE_UNIMPLEMENTED(__func__);
1104 * Now the tx queues. Only one pass needed.
1106 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1109 for_each_txq(pi, i, txq) {
1110 iqid = port_intr_iq(pi, j)->cntxt_id;
1111 snprintf(name, sizeof(name), "%s txq%d",
1112 device_get_nameunit(pi->dev), i);
1113 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
1116 rc = alloc_txq(pi, txq, i, oid);
1122 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
1123 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1124 for_each_ofld_txq(pi, i, ofld_txq) {
1125 struct sysctl_oid *oid2;
1127 iqid = port_intr_iq(pi, j)->cntxt_id;
1128 snprintf(name, sizeof(name), "%s ofld_txq%d",
1129 device_get_nameunit(pi->dev), i);
1130 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
1133 snprintf(name, sizeof(name), "%d", i);
1134 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1135 name, CTLFLAG_RD, NULL, "offload tx queue");
1137 rc = alloc_wrq(sc, pi, ofld_txq, oid2);
1144 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq",
1145 CTLFLAG_RD, NULL, "tx queues for netmap use");
1146 for_each_nm_txq(pi, i, nm_txq) {
1147 iqid = pi->first_nm_rxq + (j % pi->nnmrxq);
1148 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid);
1156 * Finally, the control queue.
1158 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1159 NULL, "ctrl queue");
1160 ctrlq = &sc->sge.ctrlq[pi->port_id];
1161 iqid = port_intr_iq(pi, 0)->cntxt_id;
1162 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
1163 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
1164 rc = alloc_wrq(sc, pi, ctrlq, oid);
1168 t4_teardown_port_queues(pi);
1177 t4_teardown_port_queues(struct port_info *pi)
1180 struct adapter *sc = pi->adapter;
1181 struct sge_rxq *rxq;
1182 struct sge_txq *txq;
1184 struct sge_ofld_rxq *ofld_rxq;
1185 struct sge_wrq *ofld_txq;
1188 struct sge_nm_rxq *nm_rxq;
1189 struct sge_nm_txq *nm_txq;
1192 /* Do this before freeing the queues */
1193 if (pi->flags & PORT_SYSCTL_CTX) {
1194 sysctl_ctx_free(&pi->ctx);
1195 pi->flags &= ~PORT_SYSCTL_CTX;
1199 * Take down all the tx queues first, as they reference the rx queues
1200 * (for egress updates, etc.).
1203 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1205 for_each_txq(pi, i, txq) {
1209 for_each_ofld_txq(pi, i, ofld_txq) {
1210 free_wrq(sc, ofld_txq);
1214 for_each_nm_txq(pi, i, nm_txq)
1215 free_nm_txq(pi, nm_txq);
1219 * Then take down the rx queues that forward their interrupts, as they
1220 * reference other rx queues.
1223 for_each_rxq(pi, i, rxq) {
1224 if ((rxq->iq.flags & IQ_INTR) == 0)
1228 for_each_ofld_rxq(pi, i, ofld_rxq) {
1229 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1230 free_ofld_rxq(pi, ofld_rxq);
1234 for_each_nm_rxq(pi, i, nm_rxq)
1235 free_nm_rxq(pi, nm_rxq);
1239 * Then take down the rx queues that take direct interrupts.
1242 for_each_rxq(pi, i, rxq) {
1243 if (rxq->iq.flags & IQ_INTR)
1247 for_each_ofld_rxq(pi, i, ofld_rxq) {
1248 if (ofld_rxq->iq.flags & IQ_INTR)
1249 free_ofld_rxq(pi, ofld_rxq);
1257 * Deals with errors and the firmware event queue. All data rx queues forward
1258 * their interrupt to the firmware event queue.
1261 t4_intr_all(void *arg)
1263 struct adapter *sc = arg;
1264 struct sge_iq *fwq = &sc->sge.fwq;
1267 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1269 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1273 /* Deals with error interrupts */
1275 t4_intr_err(void *arg)
1277 struct adapter *sc = arg;
1279 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1280 t4_slow_intr_handler(sc);
1284 t4_intr_evt(void *arg)
1286 struct sge_iq *iq = arg;
1288 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1290 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1297 struct sge_iq *iq = arg;
1299 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1301 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1306 * Deals with anything and everything on the given ingress queue.
1309 service_iq(struct sge_iq *iq, int budget)
1312 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1313 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1314 struct adapter *sc = iq->adapter;
1315 struct iq_desc *d = &iq->desc[iq->cidx];
1316 int ndescs = 0, limit;
1317 int rsp_type, refill;
1319 uint16_t fl_hw_cidx;
1321 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1322 #if defined(INET) || defined(INET6)
1323 const struct timeval lro_timeout = {0, sc->lro_timeout};
1326 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1328 limit = budget ? budget : iq->qsize / 16;
1330 if (iq->flags & IQ_HAS_FL) {
1332 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1335 fl_hw_cidx = 0; /* to silence gcc warning */
1339 * We always come back and check the descriptor ring for new indirect
1340 * interrupts and other responses after running a single handler.
1343 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1349 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1350 lq = be32toh(d->rsp.pldbuflen_qid);
1353 case X_RSPD_TYPE_FLBUF:
1355 KASSERT(iq->flags & IQ_HAS_FL,
1356 ("%s: data for an iq (%p) with no freelist",
1359 m0 = get_fl_payload(sc, fl, lq);
1360 if (__predict_false(m0 == NULL))
1362 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1363 #ifdef T4_PKT_TIMESTAMP
1365 * 60 bit timestamp for the payload is
1366 * *(uint64_t *)m0->m_pktdat. Note that it is
1367 * in the leading free-space in the mbuf. The
1368 * kernel can clobber it during a pullup,
1369 * m_copymdata, etc. You need to make sure that
1370 * the mbuf reaches you unmolested if you care
1371 * about the timestamp.
1373 *(uint64_t *)m0->m_pktdat =
1374 be64toh(ctrl->u.last_flit) &
1380 case X_RSPD_TYPE_CPL:
1381 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1382 ("%s: bad opcode %02x.", __func__,
1384 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1387 case X_RSPD_TYPE_INTR:
1390 * Interrupts should be forwarded only to queues
1391 * that are not forwarding their interrupts.
1392 * This means service_iq can recurse but only 1
1395 KASSERT(budget == 0,
1396 ("%s: budget %u, rsp_type %u", __func__,
1400 * There are 1K interrupt-capable queues (qids 0
1401 * through 1023). A response type indicating a
1402 * forwarded interrupt with a qid >= 1K is an
1403 * iWARP async notification.
1406 sc->an_handler(iq, &d->rsp);
1410 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1411 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1413 if (service_iq(q, q->qsize / 16) == 0) {
1414 atomic_cmpset_int(&q->state,
1415 IQS_BUSY, IQS_IDLE);
1417 STAILQ_INSERT_TAIL(&iql, q,
1425 ("%s: illegal response type %d on iq %p",
1426 __func__, rsp_type, iq));
1428 "%s: illegal response type %d on iq %p",
1429 device_get_nameunit(sc->dev), rsp_type, iq);
1434 if (__predict_false(++iq->cidx == iq->sidx)) {
1436 iq->gen ^= F_RSPD_GEN;
1439 if (__predict_false(++ndescs == limit)) {
1440 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1442 V_INGRESSQID(iq->cntxt_id) |
1443 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1446 #if defined(INET) || defined(INET6)
1447 if (iq->flags & IQ_LRO_ENABLED &&
1448 sc->lro_timeout != 0) {
1449 tcp_lro_flush_inactive(&rxq->lro,
1455 if (iq->flags & IQ_HAS_FL) {
1457 refill_fl(sc, fl, 32);
1460 return (EINPROGRESS);
1465 refill_fl(sc, fl, 32);
1467 fl_hw_cidx = fl->hw_cidx;
1472 if (STAILQ_EMPTY(&iql))
1476 * Process the head only, and send it to the back of the list if
1477 * it's still not done.
1479 q = STAILQ_FIRST(&iql);
1480 STAILQ_REMOVE_HEAD(&iql, link);
1481 if (service_iq(q, q->qsize / 8) == 0)
1482 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1484 STAILQ_INSERT_TAIL(&iql, q, link);
1487 #if defined(INET) || defined(INET6)
1488 if (iq->flags & IQ_LRO_ENABLED) {
1489 struct lro_ctrl *lro = &rxq->lro;
1490 struct lro_entry *l;
1492 while (!SLIST_EMPTY(&lro->lro_active)) {
1493 l = SLIST_FIRST(&lro->lro_active);
1494 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1495 tcp_lro_flush(lro, l);
1500 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1501 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1503 if (iq->flags & IQ_HAS_FL) {
1507 starved = refill_fl(sc, fl, 64);
1509 if (__predict_false(starved != 0))
1510 add_fl_to_sfl(sc, fl);
1517 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1519 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1522 MPASS(cll->region3 >= CL_METADATA_SIZE);
1527 static inline struct cluster_metadata *
1528 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1532 if (cl_has_metadata(fl, cll)) {
1533 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1535 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1541 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1543 uma_zone_t zone = arg1;
1546 uma_zfree(zone, cl);
1547 counter_u64_add(extfree_rels, 1);
1551 * The mbuf returned by this function could be allocated from zone_mbuf or
1552 * constructed in spare room in the cluster.
1554 * The mbuf carries the payload in one of these ways
1555 * a) frame inside the mbuf (mbuf from zone_mbuf)
1556 * b) m_cljset (for clusters without metadata) zone_mbuf
1557 * c) m_extaddref (cluster with metadata) inline mbuf
1558 * d) m_extaddref (cluster with metadata) zone_mbuf
1560 static struct mbuf *
1561 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1565 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1566 struct cluster_layout *cll = &sd->cll;
1567 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1568 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1569 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1573 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1574 len = min(remaining, blen);
1575 payload = sd->cl + cll->region1 + fl->rx_offset;
1576 if (fl->flags & FL_BUF_PACKING) {
1577 const u_int l = fr_offset + len;
1578 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1580 if (fl->rx_offset + len + pad < hwb->size)
1582 MPASS(fl->rx_offset + blen <= hwb->size);
1584 MPASS(fl->rx_offset == 0); /* not packing */
1588 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1591 * Copy payload into a freshly allocated mbuf.
1594 m = fr_offset == 0 ?
1595 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1598 fl->mbuf_allocated++;
1599 #ifdef T4_PKT_TIMESTAMP
1600 /* Leave room for a timestamp */
1603 /* copy data to mbuf */
1604 bcopy(payload, mtod(m, caddr_t), len);
1606 } else if (sd->nmbuf * MSIZE < cll->region1) {
1609 * There's spare room in the cluster for an mbuf. Create one
1610 * and associate it with the payload that's in the cluster.
1614 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1615 /* No bzero required */
1616 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1617 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1620 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1622 if (sd->nmbuf++ == 0)
1623 counter_u64_add(extfree_refs, 1);
1628 * Grab an mbuf from zone_mbuf and associate it with the
1629 * payload in the cluster.
1632 m = fr_offset == 0 ?
1633 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1636 fl->mbuf_allocated++;
1638 m_extaddref(m, payload, blen, &clm->refcount,
1639 rxb_free, swz->zone, sd->cl);
1640 if (sd->nmbuf++ == 0)
1641 counter_u64_add(extfree_refs, 1);
1643 m_cljset(m, sd->cl, swz->type);
1644 sd->cl = NULL; /* consumed, not a recycle candidate */
1648 m->m_pkthdr.len = remaining;
1651 if (fl->flags & FL_BUF_PACKING) {
1652 fl->rx_offset += blen;
1653 MPASS(fl->rx_offset <= hwb->size);
1654 if (fl->rx_offset < hwb->size)
1655 return (m); /* without advancing the cidx */
1658 if (__predict_false(++fl->cidx % 8 == 0)) {
1659 uint16_t cidx = fl->cidx / 8;
1661 if (__predict_false(cidx == fl->sidx))
1662 fl->cidx = cidx = 0;
1670 static struct mbuf *
1671 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1673 struct mbuf *m0, *m, **pnext;
1675 const u_int total = G_RSPD_LEN(len_newbuf);
1677 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1678 M_ASSERTPKTHDR(fl->m0);
1679 MPASS(fl->m0->m_pkthdr.len == total);
1680 MPASS(fl->remaining < total);
1684 remaining = fl->remaining;
1685 fl->flags &= ~FL_BUF_RESUME;
1689 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1691 if (__predict_false(++fl->cidx % 8 == 0)) {
1692 uint16_t cidx = fl->cidx / 8;
1694 if (__predict_false(cidx == fl->sidx))
1695 fl->cidx = cidx = 0;
1701 * Payload starts at rx_offset in the current hw buffer. Its length is
1702 * 'len' and it may span multiple hw buffers.
1705 m0 = get_scatter_segment(sc, fl, 0, total);
1708 remaining = total - m0->m_len;
1709 pnext = &m0->m_next;
1710 while (remaining > 0) {
1712 MPASS(fl->rx_offset == 0);
1713 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1714 if (__predict_false(m == NULL)) {
1717 fl->remaining = remaining;
1718 fl->flags |= FL_BUF_RESUME;
1723 remaining -= m->m_len;
1731 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1733 struct sge_rxq *rxq = iq_to_rxq(iq);
1734 struct ifnet *ifp = rxq->ifp;
1735 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1736 #if defined(INET) || defined(INET6)
1737 struct lro_ctrl *lro = &rxq->lro;
1739 static const int sw_hashtype[4][2] = {
1740 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1741 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1742 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1743 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1746 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1749 m0->m_pkthdr.len -= fl_pktshift;
1750 m0->m_len -= fl_pktshift;
1751 m0->m_data += fl_pktshift;
1753 m0->m_pkthdr.rcvif = ifp;
1754 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1755 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1757 if (cpl->csum_calc && !cpl->err_vec) {
1758 if (ifp->if_capenable & IFCAP_RXCSUM &&
1759 cpl->l2info & htobe32(F_RXF_IP)) {
1760 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1761 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1763 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1764 cpl->l2info & htobe32(F_RXF_IP6)) {
1765 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1770 if (__predict_false(cpl->ip_frag))
1771 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1773 m0->m_pkthdr.csum_data = 0xffff;
1777 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1778 m0->m_flags |= M_VLANTAG;
1779 rxq->vlan_extraction++;
1782 #if defined(INET) || defined(INET6)
1783 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1784 iq->flags & IQ_LRO_ENABLED &&
1785 tcp_lro_rx(lro, m0, 0) == 0) {
1786 /* queued for LRO */
1789 ifp->if_input(ifp, m0);
1795 * Must drain the wrq or make sure that someone else will.
1798 wrq_tx_drain(void *arg, int n)
1800 struct sge_wrq *wrq = arg;
1801 struct sge_eq *eq = &wrq->eq;
1804 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1805 drain_wrq_wr_list(wrq->adapter, wrq);
1810 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1812 struct sge_eq *eq = &wrq->eq;
1813 u_int available, dbdiff; /* # of hardware descriptors */
1816 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1818 EQ_LOCK_ASSERT_OWNED(eq);
1819 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1820 wr = STAILQ_FIRST(&wrq->wr_list);
1821 MPASS(wr != NULL); /* Must be called with something useful to do */
1822 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
1825 eq->cidx = read_hw_cidx(eq);
1826 if (eq->pidx == eq->cidx)
1827 available = eq->sidx - 1;
1829 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1831 MPASS(wr->wrq == wrq);
1832 n = howmany(wr->wr_len, EQ_ESIZE);
1836 dst = (void *)&eq->desc[eq->pidx];
1837 if (__predict_true(eq->sidx - eq->pidx > n)) {
1838 /* Won't wrap, won't end exactly at the status page. */
1839 bcopy(&wr->wr[0], dst, wr->wr_len);
1842 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1844 bcopy(&wr->wr[0], dst, first_portion);
1845 if (wr->wr_len > first_portion) {
1846 bcopy(&wr->wr[first_portion], &eq->desc[0],
1847 wr->wr_len - first_portion);
1849 eq->pidx = n - (eq->sidx - eq->pidx);
1852 if (available < eq->sidx / 4 &&
1853 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1854 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1856 eq->equeqidx = eq->pidx;
1857 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1858 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1859 eq->equeqidx = eq->pidx;
1864 ring_eq_db(sc, eq, dbdiff);
1868 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1870 MPASS(wrq->nwr_pending > 0);
1872 MPASS(wrq->ndesc_needed >= n);
1873 wrq->ndesc_needed -= n;
1874 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1877 ring_eq_db(sc, eq, dbdiff);
1881 * Doesn't fail. Holds on to work requests it can't send right away.
1884 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1887 struct sge_eq *eq = &wrq->eq;
1890 EQ_LOCK_ASSERT_OWNED(eq);
1892 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1893 MPASS((wr->wr_len & 0x7) == 0);
1895 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1897 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1899 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1900 return; /* commit_wrq_wr will drain wr_list as well. */
1902 drain_wrq_wr_list(sc, wrq);
1904 /* Doorbell must have caught up to the pidx. */
1905 MPASS(eq->pidx == eq->dbidx);
1909 t4_update_fl_bufsize(struct ifnet *ifp)
1911 struct port_info *pi = ifp->if_softc;
1912 struct adapter *sc = pi->adapter;
1913 struct sge_rxq *rxq;
1915 struct sge_ofld_rxq *ofld_rxq;
1918 int i, maxp, mtu = ifp->if_mtu;
1920 maxp = mtu_to_max_payload(sc, mtu, 0);
1921 for_each_rxq(pi, i, rxq) {
1925 find_best_refill_source(sc, fl, maxp);
1929 maxp = mtu_to_max_payload(sc, mtu, 1);
1930 for_each_ofld_rxq(pi, i, ofld_rxq) {
1934 find_best_refill_source(sc, fl, maxp);
1941 mbuf_nsegs(struct mbuf *m)
1945 KASSERT(m->m_pkthdr.l5hlen > 0,
1946 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1948 return (m->m_pkthdr.l5hlen);
1952 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1956 m->m_pkthdr.l5hlen = nsegs;
1960 mbuf_len16(struct mbuf *m)
1965 n = m->m_pkthdr.PH_loc.eight[0];
1966 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1972 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1976 m->m_pkthdr.PH_loc.eight[0] = len16;
1980 needs_tso(struct mbuf *m)
1985 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1986 KASSERT(m->m_pkthdr.tso_segsz > 0,
1987 ("%s: TSO requested in mbuf %p but MSS not provided",
1996 needs_l3_csum(struct mbuf *m)
2001 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2007 needs_l4_csum(struct mbuf *m)
2012 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2013 CSUM_TCP_IPV6 | CSUM_TSO))
2019 needs_vlan_insertion(struct mbuf *m)
2024 if (m->m_flags & M_VLANTAG) {
2025 KASSERT(m->m_pkthdr.ether_vtag != 0,
2026 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2034 m_advance(struct mbuf **pm, int *poffset, int len)
2036 struct mbuf *m = *pm;
2037 int offset = *poffset;
2043 if (offset + len < m->m_len) {
2045 p = mtod(m, uintptr_t) + offset;
2048 len -= m->m_len - offset;
2059 same_paddr(char *a, char *b)
2064 else if (a != NULL && b != NULL) {
2065 vm_offset_t x = (vm_offset_t)a;
2066 vm_offset_t y = (vm_offset_t)b;
2068 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
2069 pmap_kextract(x) == pmap_kextract(y))
2077 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2078 * must have at least one mbuf that's not empty.
2081 count_mbuf_nsegs(struct mbuf *m)
2083 char *prev_end, *start;
2090 for (; m; m = m->m_next) {
2093 if (__predict_false(len == 0))
2095 start = mtod(m, char *);
2097 nsegs += sglist_count(start, len);
2098 if (same_paddr(prev_end, start))
2100 prev_end = start + len;
2108 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2109 * a) caller can assume it's been freed if this function returns with an error.
2110 * b) it may get defragged up if the gather list is too long for the hardware.
2113 parse_pkt(struct mbuf **mp)
2115 struct mbuf *m0 = *mp, *m;
2116 int rc, nsegs, defragged = 0, offset;
2117 struct ether_header *eh;
2119 #if defined(INET) || defined(INET6)
2125 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2134 * First count the number of gather list segments in the payload.
2135 * Defrag the mbuf if nsegs exceeds the hardware limit.
2138 MPASS(m0->m_pkthdr.len > 0);
2139 nsegs = count_mbuf_nsegs(m0);
2140 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2141 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2145 *mp = m0 = m; /* update caller's copy after defrag */
2149 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2150 m0 = m_pullup(m0, m0->m_pkthdr.len);
2152 /* Should have left well enough alone. */
2156 *mp = m0; /* update caller's copy after pullup */
2159 set_mbuf_nsegs(m0, nsegs);
2160 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2166 eh = mtod(m, struct ether_header *);
2167 eh_type = ntohs(eh->ether_type);
2168 if (eh_type == ETHERTYPE_VLAN) {
2169 struct ether_vlan_header *evh = (void *)eh;
2171 eh_type = ntohs(evh->evl_proto);
2172 m0->m_pkthdr.l2hlen = sizeof(*evh);
2174 m0->m_pkthdr.l2hlen = sizeof(*eh);
2177 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2181 case ETHERTYPE_IPV6:
2183 struct ip6_hdr *ip6 = l3hdr;
2185 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
2187 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2194 struct ip *ip = l3hdr;
2196 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2201 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2202 " with the same INET/INET6 options as the kernel.",
2206 #if defined(INET) || defined(INET6)
2207 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2208 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2215 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2217 struct sge_eq *eq = &wrq->eq;
2218 struct adapter *sc = wrq->adapter;
2219 int ndesc, available;
2224 ndesc = howmany(len16, EQ_ESIZE / 16);
2225 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2229 if (!STAILQ_EMPTY(&wrq->wr_list))
2230 drain_wrq_wr_list(sc, wrq);
2232 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2235 wr = alloc_wrqe(len16 * 16, wrq);
2236 if (__predict_false(wr == NULL))
2239 cookie->ndesc = ndesc;
2243 eq->cidx = read_hw_cidx(eq);
2244 if (eq->pidx == eq->cidx)
2245 available = eq->sidx - 1;
2247 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2248 if (available < ndesc)
2251 cookie->pidx = eq->pidx;
2252 cookie->ndesc = ndesc;
2253 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2255 w = &eq->desc[eq->pidx];
2256 IDXINCR(eq->pidx, ndesc, eq->sidx);
2257 if (__predict_false(eq->pidx < ndesc - 1)) {
2259 wrq->ss_pidx = cookie->pidx;
2260 wrq->ss_len = len16 * 16;
2269 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2271 struct sge_eq *eq = &wrq->eq;
2272 struct adapter *sc = wrq->adapter;
2274 struct wrq_cookie *prev, *next;
2276 if (cookie->pidx == -1) {
2277 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2283 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2284 pidx = cookie->pidx;
2285 MPASS(pidx >= 0 && pidx < eq->sidx);
2286 if (__predict_false(w == &wrq->ss[0])) {
2287 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2289 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2290 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2291 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2294 wrq->tx_wrs_direct++;
2297 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2298 next = TAILQ_NEXT(cookie, link);
2300 MPASS(pidx == eq->dbidx);
2301 if (next == NULL || ndesc >= 16)
2302 ring_eq_db(wrq->adapter, eq, ndesc);
2304 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2306 next->ndesc += ndesc;
2309 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2310 prev->ndesc += ndesc;
2312 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2314 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2315 drain_wrq_wr_list(sc, wrq);
2318 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2319 /* Doorbell must have caught up to the pidx. */
2320 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2327 can_resume_eth_tx(struct mp_ring *r)
2329 struct sge_eq *eq = r->cookie;
2331 return (total_available_tx_desc(eq) > eq->sidx / 8);
2335 cannot_use_txpkts(struct mbuf *m)
2337 /* maybe put a GL limit too, to avoid silliness? */
2339 return (needs_tso(m));
2343 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2344 * be consumed. Return the actual number consumed. 0 indicates a stall.
2347 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2349 struct sge_txq *txq = r->cookie;
2350 struct sge_eq *eq = &txq->eq;
2351 struct ifnet *ifp = txq->ifp;
2352 struct port_info *pi = (void *)ifp->if_softc;
2353 struct adapter *sc = pi->adapter;
2354 u_int total, remaining; /* # of packets */
2355 u_int available, dbdiff; /* # of hardware descriptors */
2357 struct mbuf *m0, *tail;
2359 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2361 remaining = IDXDIFF(pidx, cidx, r->size);
2362 MPASS(remaining > 0); /* Must not be called without work to do. */
2366 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2367 while (cidx != pidx) {
2368 m0 = r->items[cidx];
2370 if (++cidx == r->size)
2373 reclaim_tx_descs(txq, 2048);
2378 /* How many hardware descriptors do we have readily available. */
2379 if (eq->pidx == eq->cidx)
2380 available = eq->sidx - 1;
2382 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2383 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2385 while (remaining > 0) {
2387 m0 = r->items[cidx];
2389 MPASS(m0->m_nextpkt == NULL);
2391 if (available < SGE_MAX_WR_NDESC) {
2392 available += reclaim_tx_descs(txq, 64);
2393 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2394 break; /* out of descriptors */
2397 next_cidx = cidx + 1;
2398 if (__predict_false(next_cidx == r->size))
2401 wr = (void *)&eq->desc[eq->pidx];
2402 if (remaining > 1 &&
2403 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2405 /* pkts at cidx, next_cidx should both be in txp. */
2406 MPASS(txp.npkt == 2);
2407 tail = r->items[next_cidx];
2408 MPASS(tail->m_nextpkt == NULL);
2409 ETHER_BPF_MTAP(ifp, m0);
2410 ETHER_BPF_MTAP(ifp, tail);
2411 m0->m_nextpkt = tail;
2413 if (__predict_false(++next_cidx == r->size))
2416 while (next_cidx != pidx) {
2417 if (add_to_txpkts(r->items[next_cidx], &txp,
2420 tail->m_nextpkt = r->items[next_cidx];
2421 tail = tail->m_nextpkt;
2422 ETHER_BPF_MTAP(ifp, tail);
2423 if (__predict_false(++next_cidx == r->size))
2427 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2429 remaining -= txp.npkt;
2433 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2434 ETHER_BPF_MTAP(ifp, m0);
2436 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2440 IDXINCR(eq->pidx, n, eq->sidx);
2442 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2443 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2444 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2446 eq->equeqidx = eq->pidx;
2447 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2448 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2449 eq->equeqidx = eq->pidx;
2452 if (dbdiff >= 16 && remaining >= 4) {
2453 ring_eq_db(sc, eq, dbdiff);
2454 available += reclaim_tx_descs(txq, 4 * dbdiff);
2461 ring_eq_db(sc, eq, dbdiff);
2462 reclaim_tx_descs(txq, 32);
2471 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2475 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2476 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2477 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2478 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2482 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2483 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2484 if (pktc_idx >= 0) {
2485 iq->intr_params |= F_QINTR_CNT_EN;
2486 iq->intr_pktc_idx = pktc_idx;
2488 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2489 iq->sidx = iq->qsize - spg_len / IQ_ESIZE;
2493 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2497 fl->sidx = qsize - spg_len / EQ_ESIZE;
2498 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2499 if (sc->flags & BUF_PACKING_OK &&
2500 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2501 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2502 fl->flags |= FL_BUF_PACKING;
2503 find_best_refill_source(sc, fl, maxp);
2504 find_safe_refill_source(sc, fl);
2508 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
2509 uint16_t iqid, char *name)
2511 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
2512 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2514 eq->flags = eqtype & EQ_TYPEMASK;
2515 eq->tx_chan = tx_chan;
2517 eq->sidx = qsize - spg_len / EQ_ESIZE;
2518 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2522 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2523 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2527 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2528 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2530 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2534 rc = bus_dmamem_alloc(*tag, va,
2535 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2537 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2541 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2543 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2548 free_ring(sc, *tag, *map, *pa, *va);
2554 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2555 bus_addr_t pa, void *va)
2558 bus_dmamap_unload(tag, map);
2560 bus_dmamem_free(tag, va, map);
2562 bus_dma_tag_destroy(tag);
2568 * Allocates the ring for an ingress queue and an optional freelist. If the
2569 * freelist is specified it will be allocated and then associated with the
2572 * Returns errno on failure. Resources allocated up to that point may still be
2573 * allocated. Caller is responsible for cleanup in case this function fails.
2575 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2576 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2577 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2580 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
2581 int intr_idx, int cong)
2583 int rc, i, cntxt_id;
2586 struct adapter *sc = iq->adapter;
2589 len = iq->qsize * IQ_ESIZE;
2590 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2591 (void **)&iq->desc);
2595 bzero(&c, sizeof(c));
2596 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2597 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2598 V_FW_IQ_CMD_VFN(0));
2600 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2603 /* Special handling for firmware event queue */
2604 if (iq == &sc->sge.fwq)
2605 v |= F_FW_IQ_CMD_IQASYNCH;
2607 if (iq->flags & IQ_INTR) {
2608 KASSERT(intr_idx < sc->intr_count,
2609 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2611 v |= F_FW_IQ_CMD_IQANDST;
2612 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2614 c.type_to_iqandstindex = htobe32(v |
2615 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2616 V_FW_IQ_CMD_VIID(pi->viid) |
2617 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2618 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2619 F_FW_IQ_CMD_IQGTSMODE |
2620 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2621 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2622 c.iqsize = htobe16(iq->qsize);
2623 c.iqaddr = htobe64(iq->ba);
2625 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2628 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2630 len = fl->qsize * EQ_ESIZE;
2631 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2632 &fl->ba, (void **)&fl->desc);
2636 /* Allocate space for one software descriptor per buffer. */
2637 rc = alloc_fl_sdesc(fl);
2639 device_printf(sc->dev,
2640 "failed to setup fl software descriptors: %d\n",
2645 if (fl->flags & FL_BUF_PACKING) {
2646 fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8);
2647 fl->buf_boundary = sc->sge.pack_boundary;
2649 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
2650 fl->buf_boundary = 16;
2652 if (fl_pad && fl->buf_boundary < sc->sge.pad_boundary)
2653 fl->buf_boundary = sc->sge.pad_boundary;
2655 c.iqns_to_fl0congen |=
2656 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2657 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2658 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2659 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2662 c.iqns_to_fl0congen |=
2663 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2664 F_FW_IQ_CMD_FL0CONGCIF |
2665 F_FW_IQ_CMD_FL0CONGEN);
2667 c.fl0dcaen_to_fl0cidxfthresh =
2668 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) |
2669 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2670 c.fl0size = htobe16(fl->qsize);
2671 c.fl0addr = htobe64(fl->ba);
2674 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2676 device_printf(sc->dev,
2677 "failed to create ingress queue: %d\n", rc);
2682 iq->gen = F_RSPD_GEN;
2683 iq->intr_next = iq->intr_params;
2684 iq->cntxt_id = be16toh(c.iqid);
2685 iq->abs_id = be16toh(c.physiqid);
2686 iq->flags |= IQ_ALLOCATED;
2688 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2689 if (cntxt_id >= sc->sge.niq) {
2690 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2691 cntxt_id, sc->sge.niq - 1);
2693 sc->sge.iqmap[cntxt_id] = iq;
2698 iq->flags |= IQ_HAS_FL;
2699 fl->cntxt_id = be16toh(c.fl0id);
2700 fl->pidx = fl->cidx = 0;
2702 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2703 if (cntxt_id >= sc->sge.neq) {
2704 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2705 __func__, cntxt_id, sc->sge.neq - 1);
2707 sc->sge.eqmap[cntxt_id] = (void *)fl;
2710 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2711 uint32_t s_qpp = sc->sge.eq_s_qpp;
2712 uint32_t mask = (1 << s_qpp) - 1;
2713 volatile uint8_t *udb;
2715 udb = sc->udbs_base + UDBS_DB_OFFSET;
2716 udb += (qid >> s_qpp) << PAGE_SHIFT;
2718 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2719 udb += qid << UDBS_SEG_SHIFT;
2722 fl->udb = (volatile void *)udb;
2724 fl->dbval = F_DBPRIO | V_QID(qid);
2726 fl->dbval |= F_DBTYPE;
2729 /* Enough to make sure the SGE doesn't think it's starved */
2730 refill_fl(sc, fl, fl->lowat);
2734 if (is_t5(sc) && cong >= 0) {
2735 uint32_t param, val;
2737 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2738 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2739 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2744 for (i = 0; i < 4; i++) {
2745 if (cong & (1 << i))
2746 val |= 1 << (i << 2);
2750 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2752 /* report error but carry on */
2753 device_printf(sc->dev,
2754 "failed to set congestion manager context for "
2755 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2759 /* Enable IQ interrupts */
2760 atomic_store_rel_int(&iq->state, IQS_IDLE);
2761 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2762 V_INGRESSQID(iq->cntxt_id));
2768 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
2771 struct adapter *sc = iq->adapter;
2775 return (0); /* nothing to do */
2777 dev = pi ? pi->dev : sc->dev;
2779 if (iq->flags & IQ_ALLOCATED) {
2780 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2781 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2782 fl ? fl->cntxt_id : 0xffff, 0xffff);
2785 "failed to free queue %p: %d\n", iq, rc);
2788 iq->flags &= ~IQ_ALLOCATED;
2791 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2793 bzero(iq, sizeof(*iq));
2796 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2800 free_fl_sdesc(sc, fl);
2802 if (mtx_initialized(&fl->fl_lock))
2803 mtx_destroy(&fl->fl_lock);
2805 bzero(fl, sizeof(*fl));
2812 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2815 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2817 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2819 children = SYSCTL_CHILDREN(oid);
2821 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2822 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2823 "SGE context id of the freelist");
2824 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2825 fl_pad ? 1 : 0, "padding enabled");
2826 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2827 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2828 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2829 0, "consumer index");
2830 if (fl->flags & FL_BUF_PACKING) {
2831 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2832 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2835 0, "producer index");
2836 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2837 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2838 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2839 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2840 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2841 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2842 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2843 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2844 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2845 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2849 alloc_fwq(struct adapter *sc)
2852 struct sge_iq *fwq = &sc->sge.fwq;
2853 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2854 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2856 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2857 fwq->flags |= IQ_INTR; /* always */
2858 intr_idx = sc->intr_count > 1 ? 1 : 0;
2859 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
2861 device_printf(sc->dev,
2862 "failed to create firmware event queue: %d\n", rc);
2866 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2867 NULL, "firmware event queue");
2868 children = SYSCTL_CHILDREN(oid);
2870 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2871 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2872 "absolute id of the queue");
2873 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2874 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2875 "SGE context id of the queue");
2876 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2877 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2884 free_fwq(struct adapter *sc)
2886 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2890 alloc_mgmtq(struct adapter *sc)
2893 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2895 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2896 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2898 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2899 NULL, "management queue");
2901 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2902 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2903 sc->sge.fwq.cntxt_id, name);
2904 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2906 device_printf(sc->dev,
2907 "failed to create management queue: %d\n", rc);
2915 free_mgmtq(struct adapter *sc)
2918 return free_wrq(sc, &sc->sge.mgmtq);
2922 tnl_cong(struct port_info *pi)
2925 if (cong_drop == -1)
2927 else if (cong_drop == 1)
2930 return (pi->rx_chan_map);
2934 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
2935 struct sysctl_oid *oid)
2938 struct sysctl_oid_list *children;
2941 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi));
2946 * The freelist is just barely above the starvation threshold right now,
2947 * fill it up a bit more.
2950 refill_fl(pi->adapter, &rxq->fl, 128);
2951 FL_UNLOCK(&rxq->fl);
2953 #if defined(INET) || defined(INET6)
2954 rc = tcp_lro_init(&rxq->lro);
2957 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
2959 if (pi->ifp->if_capenable & IFCAP_LRO)
2960 rxq->iq.flags |= IQ_LRO_ENABLED;
2964 children = SYSCTL_CHILDREN(oid);
2966 snprintf(name, sizeof(name), "%d", idx);
2967 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2969 children = SYSCTL_CHILDREN(oid);
2971 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2972 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2973 "absolute id of the queue");
2974 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2975 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2976 "SGE context id of the queue");
2977 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2978 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2980 #if defined(INET) || defined(INET6)
2981 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2982 &rxq->lro.lro_queued, 0, NULL);
2983 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2984 &rxq->lro.lro_flushed, 0, NULL);
2986 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2987 &rxq->rxcsum, "# of times hardware assisted with checksum");
2988 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction",
2989 CTLFLAG_RD, &rxq->vlan_extraction,
2990 "# of times hardware extracted 802.1Q tag");
2992 add_fl_sysctls(&pi->ctx, oid, &rxq->fl);
2998 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
3002 #if defined(INET) || defined(INET6)
3004 tcp_lro_free(&rxq->lro);
3005 rxq->lro.ifp = NULL;
3009 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
3011 bzero(rxq, sizeof(*rxq));
3018 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
3019 int intr_idx, int idx, struct sysctl_oid *oid)
3022 struct sysctl_oid_list *children;
3025 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3030 children = SYSCTL_CHILDREN(oid);
3032 snprintf(name, sizeof(name), "%d", idx);
3033 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3035 children = SYSCTL_CHILDREN(oid);
3037 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
3038 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3039 "I", "absolute id of the queue");
3040 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
3041 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3042 "I", "SGE context id of the queue");
3043 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3044 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3047 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl);
3053 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
3057 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
3059 bzero(ofld_rxq, sizeof(*ofld_rxq));
3067 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3068 int idx, struct sysctl_oid *oid)
3071 struct sysctl_oid_list *children;
3072 struct sysctl_ctx_list *ctx;
3075 struct adapter *sc = pi->adapter;
3076 struct netmap_adapter *na = NA(pi->nm_ifp);
3080 len = pi->qsize_rxq * IQ_ESIZE;
3081 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3082 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3086 len = na->num_rx_desc * EQ_ESIZE + spg_len;
3087 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3088 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3094 nm_rxq->iq_cidx = 0;
3095 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / IQ_ESIZE;
3096 nm_rxq->iq_gen = F_RSPD_GEN;
3097 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3098 nm_rxq->fl_sidx = na->num_rx_desc;
3099 nm_rxq->intr_idx = intr_idx;
3102 children = SYSCTL_CHILDREN(oid);
3104 snprintf(name, sizeof(name), "%d", idx);
3105 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3107 children = SYSCTL_CHILDREN(oid);
3109 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3110 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3111 "I", "absolute id of the queue");
3112 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3113 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3114 "I", "SGE context id of the queue");
3115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3116 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3119 children = SYSCTL_CHILDREN(oid);
3120 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3122 children = SYSCTL_CHILDREN(oid);
3124 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3125 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3126 "I", "SGE context id of the freelist");
3127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3128 &nm_rxq->fl_cidx, 0, "consumer index");
3129 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3130 &nm_rxq->fl_pidx, 0, "producer index");
3137 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
3139 struct adapter *sc = pi->adapter;
3141 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3143 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3150 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3151 struct sysctl_oid *oid)
3155 struct adapter *sc = pi->adapter;
3156 struct netmap_adapter *na = NA(pi->nm_ifp);
3158 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3160 len = na->num_tx_desc * EQ_ESIZE + spg_len;
3161 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3162 &nm_txq->ba, (void **)&nm_txq->desc);
3166 nm_txq->pidx = nm_txq->cidx = 0;
3167 nm_txq->sidx = na->num_tx_desc;
3169 nm_txq->iqidx = iqidx;
3170 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3171 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
3173 snprintf(name, sizeof(name), "%d", idx);
3174 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3175 NULL, "netmap tx queue");
3176 children = SYSCTL_CHILDREN(oid);
3178 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3179 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3180 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3181 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3183 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3184 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3191 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq)
3193 struct adapter *sc = pi->adapter;
3195 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3203 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3206 struct fw_eq_ctrl_cmd c;
3207 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3209 bzero(&c, sizeof(c));
3211 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3212 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3213 V_FW_EQ_CTRL_CMD_VFN(0));
3214 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3215 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3216 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3217 c.physeqid_pkd = htobe32(0);
3218 c.fetchszm_to_iqid =
3219 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3220 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3221 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3223 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3224 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3225 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3226 c.eqaddr = htobe64(eq->ba);
3228 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3230 device_printf(sc->dev,
3231 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3234 eq->flags |= EQ_ALLOCATED;
3236 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3237 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3238 if (cntxt_id >= sc->sge.neq)
3239 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3240 cntxt_id, sc->sge.neq - 1);
3241 sc->sge.eqmap[cntxt_id] = eq;
3247 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3250 struct fw_eq_eth_cmd c;
3251 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3253 bzero(&c, sizeof(c));
3255 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3256 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3257 V_FW_EQ_ETH_CMD_VFN(0));
3258 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3259 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3260 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3261 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(pi->viid));
3262 c.fetchszm_to_iqid =
3263 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3264 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3265 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3266 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3267 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3268 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3269 c.eqaddr = htobe64(eq->ba);
3271 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3273 device_printf(pi->dev,
3274 "failed to create Ethernet egress queue: %d\n", rc);
3277 eq->flags |= EQ_ALLOCATED;
3279 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3280 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3281 if (cntxt_id >= sc->sge.neq)
3282 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3283 cntxt_id, sc->sge.neq - 1);
3284 sc->sge.eqmap[cntxt_id] = eq;
3291 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3294 struct fw_eq_ofld_cmd c;
3295 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3297 bzero(&c, sizeof(c));
3299 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3300 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3301 V_FW_EQ_OFLD_CMD_VFN(0));
3302 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3303 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3304 c.fetchszm_to_iqid =
3305 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3306 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3307 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3309 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3310 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3311 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3312 c.eqaddr = htobe64(eq->ba);
3314 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3316 device_printf(pi->dev,
3317 "failed to create egress queue for TCP offload: %d\n", rc);
3320 eq->flags |= EQ_ALLOCATED;
3322 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3323 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3324 if (cntxt_id >= sc->sge.neq)
3325 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3326 cntxt_id, sc->sge.neq - 1);
3327 sc->sge.eqmap[cntxt_id] = eq;
3334 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3339 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3341 qsize = eq->sidx + spg_len / EQ_ESIZE;
3342 len = qsize * EQ_ESIZE;
3343 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3344 &eq->ba, (void **)&eq->desc);
3348 eq->pidx = eq->cidx = 0;
3349 eq->equeqidx = eq->dbidx = 0;
3350 eq->doorbells = sc->doorbells;
3352 switch (eq->flags & EQ_TYPEMASK) {
3354 rc = ctrl_eq_alloc(sc, eq);
3358 rc = eth_eq_alloc(sc, pi, eq);
3363 rc = ofld_eq_alloc(sc, pi, eq);
3368 panic("%s: invalid eq type %d.", __func__,
3369 eq->flags & EQ_TYPEMASK);
3372 device_printf(sc->dev,
3373 "failed to allocate egress queue(%d): %d\n",
3374 eq->flags & EQ_TYPEMASK, rc);
3377 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3378 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3379 isset(&eq->doorbells, DOORBELL_WCWR)) {
3380 uint32_t s_qpp = sc->sge.eq_s_qpp;
3381 uint32_t mask = (1 << s_qpp) - 1;
3382 volatile uint8_t *udb;
3384 udb = sc->udbs_base + UDBS_DB_OFFSET;
3385 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3386 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3387 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3388 clrbit(&eq->doorbells, DOORBELL_WCWR);
3390 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3393 eq->udb = (volatile void *)udb;
3400 free_eq(struct adapter *sc, struct sge_eq *eq)
3404 if (eq->flags & EQ_ALLOCATED) {
3405 switch (eq->flags & EQ_TYPEMASK) {
3407 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3412 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3418 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3424 panic("%s: invalid eq type %d.", __func__,
3425 eq->flags & EQ_TYPEMASK);
3428 device_printf(sc->dev,
3429 "failed to free egress queue (%d): %d\n",
3430 eq->flags & EQ_TYPEMASK, rc);
3433 eq->flags &= ~EQ_ALLOCATED;
3436 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3438 if (mtx_initialized(&eq->eq_lock))
3439 mtx_destroy(&eq->eq_lock);
3441 bzero(eq, sizeof(*eq));
3446 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
3447 struct sysctl_oid *oid)
3450 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
3451 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3453 rc = alloc_eq(sc, pi, &wrq->eq);
3458 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3459 TAILQ_INIT(&wrq->incomplete_wrs);
3460 STAILQ_INIT(&wrq->wr_list);
3461 wrq->nwr_pending = 0;
3462 wrq->ndesc_needed = 0;
3464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3465 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3467 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3469 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3470 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3472 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3473 &wrq->tx_wrs_direct, "# of work requests (direct)");
3474 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3475 &wrq->tx_wrs_copied, "# of work requests (copied)");
3481 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3485 rc = free_eq(sc, &wrq->eq);
3489 bzero(wrq, sizeof(*wrq));
3494 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
3495 struct sysctl_oid *oid)
3498 struct adapter *sc = pi->adapter;
3499 struct sge_eq *eq = &txq->eq;
3501 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3503 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3506 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3510 rc = alloc_eq(sc, pi, eq);
3512 mp_ring_free(txq->r);
3517 /* Can't fail after this point. */
3519 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3521 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3522 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3523 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
3524 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3527 snprintf(name, sizeof(name), "%d", idx);
3528 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3530 children = SYSCTL_CHILDREN(oid);
3532 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3533 &eq->cntxt_id, 0, "SGE context id of the queue");
3534 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3535 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3537 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3538 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3541 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3542 &txq->txcsum, "# of times hardware assisted with checksum");
3543 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion",
3544 CTLFLAG_RD, &txq->vlan_insertion,
3545 "# of times hardware inserted 802.1Q tag");
3546 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3547 &txq->tso_wrs, "# of TSO work requests");
3548 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3549 &txq->imm_wrs, "# of work requests with immediate data");
3550 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3551 &txq->sgl_wrs, "# of work requests with direct SGL");
3552 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3553 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3554 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts0_wrs",
3555 CTLFLAG_RD, &txq->txpkts0_wrs,
3556 "# of txpkts (type 0) work requests");
3557 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts1_wrs",
3558 CTLFLAG_RD, &txq->txpkts1_wrs,
3559 "# of txpkts (type 1) work requests");
3560 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts0_pkts",
3561 CTLFLAG_RD, &txq->txpkts0_pkts,
3562 "# of frames tx'd using type0 txpkts work requests");
3563 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts1_pkts",
3564 CTLFLAG_RD, &txq->txpkts1_pkts,
3565 "# of frames tx'd using type1 txpkts work requests");
3567 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_enqueues",
3568 CTLFLAG_RD, &txq->r->enqueues,
3569 "# of enqueues to the mp_ring for this queue");
3570 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_drops",
3571 CTLFLAG_RD, &txq->r->drops,
3572 "# of drops in the mp_ring for this queue");
3573 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_starts",
3574 CTLFLAG_RD, &txq->r->starts,
3575 "# of normal consumer starts in the mp_ring for this queue");
3576 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_stalls",
3577 CTLFLAG_RD, &txq->r->stalls,
3578 "# of consumer stalls in the mp_ring for this queue");
3579 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_restarts",
3580 CTLFLAG_RD, &txq->r->restarts,
3581 "# of consumer restarts in the mp_ring for this queue");
3582 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_abdications",
3583 CTLFLAG_RD, &txq->r->abdications,
3584 "# of consumer abdications in the mp_ring for this queue");
3590 free_txq(struct port_info *pi, struct sge_txq *txq)
3593 struct adapter *sc = pi->adapter;
3594 struct sge_eq *eq = &txq->eq;
3596 rc = free_eq(sc, eq);
3600 sglist_free(txq->gl);
3601 free(txq->sdesc, M_CXGBE);
3602 mp_ring_free(txq->r);
3604 bzero(txq, sizeof(*txq));
3609 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3611 bus_addr_t *ba = arg;
3614 ("%s meant for single segment mappings only.", __func__));
3616 *ba = error ? 0 : segs->ds_addr;
3620 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3624 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3628 v = fl->dbval | V_PIDX(n);
3630 *fl->udb = htole32(v);
3632 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3633 IDXINCR(fl->dbidx, n, fl->sidx);
3637 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3638 * recycled do not count towards this allocation budget.
3640 * Returns non-zero to indicate that this freelist should be added to the list
3641 * of starving freelists.
3644 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3647 struct fl_sdesc *sd;
3650 struct cluster_layout *cll;
3651 struct sw_zone_info *swz;
3652 struct cluster_metadata *clm;
3654 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3656 FL_LOCK_ASSERT_OWNED(fl);
3659 * We always stop at the begining of the hardware descriptor that's just
3660 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3661 * which would mean an empty freelist to the chip.
3663 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3664 if (fl->pidx == max_pidx * 8)
3667 d = &fl->desc[fl->pidx];
3668 sd = &fl->sdesc[fl->pidx];
3669 cll = &fl->cll_def; /* default layout */
3670 swz = &sc->sge.sw_zone_info[cll->zidx];
3674 if (sd->cl != NULL) {
3676 if (sd->nmbuf == 0) {
3678 * Fast recycle without involving any atomics on
3679 * the cluster's metadata (if the cluster has
3680 * metadata). This happens when all frames
3681 * received in the cluster were small enough to
3682 * fit within a single mbuf each.
3684 fl->cl_fast_recycled++;
3686 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3688 MPASS(clm->refcount == 1);
3694 * Cluster is guaranteed to have metadata. Clusters
3695 * without metadata always take the fast recycle path
3696 * when they're recycled.
3698 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3701 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3703 counter_u64_add(extfree_rels, 1);
3706 sd->cl = NULL; /* gave up my reference */
3708 MPASS(sd->cl == NULL);
3710 cl = uma_zalloc(swz->zone, M_NOWAIT);
3711 if (__predict_false(cl == NULL)) {
3712 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3713 fl->cll_def.zidx == fl->cll_alt.zidx)
3716 /* fall back to the safe zone */
3718 swz = &sc->sge.sw_zone_info[cll->zidx];
3724 pa = pmap_kextract((vm_offset_t)cl);
3728 *d = htobe64(pa | cll->hwidx);
3729 clm = cl_metadata(sc, fl, cll, cl);
3741 if (__predict_false(++fl->pidx % 8 == 0)) {
3742 uint16_t pidx = fl->pidx / 8;
3744 if (__predict_false(pidx == fl->sidx)) {
3750 if (pidx == max_pidx)
3753 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3758 if (fl->pidx / 8 != fl->dbidx)
3761 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3765 * Attempt to refill all starving freelists.
3768 refill_sfl(void *arg)
3770 struct adapter *sc = arg;
3771 struct sge_fl *fl, *fl_temp;
3773 mtx_lock(&sc->sfl_lock);
3774 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3776 refill_fl(sc, fl, 64);
3777 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3778 TAILQ_REMOVE(&sc->sfl, fl, link);
3779 fl->flags &= ~FL_STARVING;
3784 if (!TAILQ_EMPTY(&sc->sfl))
3785 callout_schedule(&sc->sfl_callout, hz / 5);
3786 mtx_unlock(&sc->sfl_lock);
3790 alloc_fl_sdesc(struct sge_fl *fl)
3793 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3800 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3802 struct fl_sdesc *sd;
3803 struct cluster_metadata *clm;
3804 struct cluster_layout *cll;
3808 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3813 clm = cl_metadata(sc, fl, cll, sd->cl);
3815 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3816 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3817 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3818 counter_u64_add(extfree_rels, 1);
3823 free(fl->sdesc, M_CXGBE);
3828 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3835 rc = sglist_append_mbuf(gl, m);
3836 if (__predict_false(rc != 0)) {
3837 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3838 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3841 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3842 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3843 mbuf_nsegs(m), gl->sg_nseg));
3844 KASSERT(gl->sg_nseg > 0 &&
3845 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3846 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3847 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3851 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3854 txpkt_len16(u_int nsegs, u_int tso)
3860 nsegs--; /* first segment is part of ulptx_sgl */
3861 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3862 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3864 n += sizeof(struct cpl_tx_pkt_lso_core);
3866 return (howmany(n, 16));
3870 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
3874 txpkts0_len16(u_int nsegs)
3880 nsegs--; /* first segment is part of ulptx_sgl */
3881 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
3882 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
3883 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3885 return (howmany(n, 16));
3889 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
3897 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
3899 return (howmany(n, 16));
3903 imm_payload(u_int ndesc)
3907 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
3908 sizeof(struct cpl_tx_pkt_core);
3914 * Write a txpkt WR for this packet to the hardware descriptors, update the
3915 * software descriptor, and advance the pidx. It is guaranteed that enough
3916 * descriptors are available.
3918 * The return value is the # of hardware descriptors used.
3921 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
3922 struct mbuf *m0, u_int available)
3924 struct sge_eq *eq = &txq->eq;
3925 struct tx_sdesc *txsd;
3926 struct cpl_tx_pkt_core *cpl;
3927 uint32_t ctrl; /* used in many unrelated places */
3929 int len16, ndesc, pktlen, nsegs;
3932 TXQ_LOCK_ASSERT_OWNED(txq);
3934 MPASS(available > 0 && available < eq->sidx);
3936 len16 = mbuf_len16(m0);
3937 nsegs = mbuf_nsegs(m0);
3938 pktlen = m0->m_pkthdr.len;
3939 ctrl = sizeof(struct cpl_tx_pkt_core);
3941 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3942 else if (pktlen <= imm_payload(2) && available >= 2) {
3943 /* Immediate data. Recalculate len16 and set nsegs to 0. */
3945 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
3946 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
3949 ndesc = howmany(len16, EQ_ESIZE / 16);
3950 MPASS(ndesc <= available);
3952 /* Firmware work request header */
3953 MPASS(wr == (void *)&eq->desc[eq->pidx]);
3954 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3955 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3957 ctrl = V_FW_WR_LEN16(len16);
3958 wr->equiq_to_len16 = htobe32(ctrl);
3961 if (needs_tso(m0)) {
3962 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3964 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
3965 m0->m_pkthdr.l4hlen > 0,
3966 ("%s: mbuf %p needs TSO but missing header lengths",
3969 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3970 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
3971 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
3972 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
3973 ctrl |= V_LSO_ETHHDR_LEN(1);
3974 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
3977 lso->lso_ctrl = htobe32(ctrl);
3978 lso->ipid_ofst = htobe16(0);
3979 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
3980 lso->seqno_offset = htobe32(0);
3981 lso->len = htobe32(pktlen);
3983 cpl = (void *)(lso + 1);
3987 cpl = (void *)(wr + 1);
3989 /* Checksum offload */
3991 if (needs_l3_csum(m0) == 0)
3992 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3993 if (needs_l4_csum(m0) == 0)
3994 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3995 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3996 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3997 txq->txcsum++; /* some hardware assistance provided */
3999 /* VLAN tag insertion */
4000 if (needs_vlan_insertion(m0)) {
4001 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4002 txq->vlan_insertion++;
4006 cpl->ctrl0 = txq->cpl_ctrl0;
4008 cpl->len = htobe16(pktlen);
4009 cpl->ctrl1 = htobe64(ctrl1);
4012 dst = (void *)(cpl + 1);
4015 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4020 for (m = m0; m != NULL; m = m->m_next) {
4021 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4027 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4034 txsd = &txq->sdesc[eq->pidx];
4036 txsd->desc_used = ndesc;
4042 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4044 u_int needed, nsegs1, nsegs2, l1, l2;
4046 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4049 nsegs1 = mbuf_nsegs(m);
4050 nsegs2 = mbuf_nsegs(n);
4051 if (nsegs1 + nsegs2 == 2) {
4053 l1 = l2 = txpkts1_len16();
4056 l1 = txpkts0_len16(nsegs1);
4057 l2 = txpkts0_len16(nsegs2);
4059 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4060 needed = howmany(txp->len16, EQ_ESIZE / 16);
4061 if (needed > SGE_MAX_WR_NDESC || needed > available)
4064 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4065 if (txp->plen > 65535)
4069 set_mbuf_len16(m, l1);
4070 set_mbuf_len16(n, l2);
4076 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4078 u_int plen, len16, needed, nsegs;
4080 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4082 nsegs = mbuf_nsegs(m);
4083 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4086 plen = txp->plen + m->m_pkthdr.len;
4090 if (txp->wr_type == 0)
4091 len16 = txpkts0_len16(nsegs);
4093 len16 = txpkts1_len16();
4094 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4095 if (needed > SGE_MAX_WR_NDESC || needed > available)
4100 txp->len16 += len16;
4101 set_mbuf_len16(m, len16);
4107 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4108 * the software descriptor, and advance the pidx. It is guaranteed that enough
4109 * descriptors are available.
4111 * The return value is the # of hardware descriptors used.
4114 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4115 struct mbuf *m0, const struct txpkts *txp, u_int available)
4117 struct sge_eq *eq = &txq->eq;
4118 struct tx_sdesc *txsd;
4119 struct cpl_tx_pkt_core *cpl;
4122 int ndesc, checkwrap;
4126 TXQ_LOCK_ASSERT_OWNED(txq);
4127 MPASS(txp->npkt > 0);
4128 MPASS(txp->plen < 65536);
4130 MPASS(m0->m_nextpkt != NULL);
4131 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4132 MPASS(available > 0 && available < eq->sidx);
4134 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4135 MPASS(ndesc <= available);
4137 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4138 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4139 ctrl = V_FW_WR_LEN16(txp->len16);
4140 wr->equiq_to_len16 = htobe32(ctrl);
4141 wr->plen = htobe16(txp->plen);
4142 wr->npkt = txp->npkt;
4144 wr->type = txp->wr_type;
4148 * At this point we are 16B into a hardware descriptor. If checkwrap is
4149 * set then we know the WR is going to wrap around somewhere. We'll
4150 * check for that at appropriate points.
4152 checkwrap = eq->sidx - ndesc < eq->pidx;
4153 for (m = m0; m != NULL; m = m->m_nextpkt) {
4154 if (txp->wr_type == 0) {
4155 struct ulp_txpkt *ulpmc;
4156 struct ulptx_idata *ulpsc;
4158 /* ULP master command */
4160 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4161 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4162 ulpmc->len = htobe32(mbuf_len16(m));
4164 /* ULP subcommand */
4165 ulpsc = (void *)(ulpmc + 1);
4166 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4168 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4170 cpl = (void *)(ulpsc + 1);
4172 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4173 cpl = (void *)&eq->desc[0];
4174 txq->txpkts0_pkts += txp->npkt;
4178 txq->txpkts1_pkts += txp->npkt;
4182 /* Checksum offload */
4184 if (needs_l3_csum(m) == 0)
4185 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4186 if (needs_l4_csum(m) == 0)
4187 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4188 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4189 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4190 txq->txcsum++; /* some hardware assistance provided */
4192 /* VLAN tag insertion */
4193 if (needs_vlan_insertion(m)) {
4194 ctrl1 |= F_TXPKT_VLAN_VLD |
4195 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4196 txq->vlan_insertion++;
4200 cpl->ctrl0 = txq->cpl_ctrl0;
4202 cpl->len = htobe16(m->m_pkthdr.len);
4203 cpl->ctrl1 = htobe64(ctrl1);
4207 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4208 flitp = (void *)&eq->desc[0];
4210 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4214 txsd = &txq->sdesc[eq->pidx];
4216 txsd->desc_used = ndesc;
4222 * If the SGL ends on an address that is not 16 byte aligned, this function will
4223 * add a 0 filled flit at the end.
4226 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4228 struct sge_eq *eq = &txq->eq;
4229 struct sglist *gl = txq->gl;
4230 struct sglist_seg *seg;
4231 __be64 *flitp, *wrap;
4232 struct ulptx_sgl *usgl;
4233 int i, nflits, nsegs;
4235 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4236 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4237 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4238 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4241 nsegs = gl->sg_nseg;
4244 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4245 flitp = (__be64 *)(*to);
4246 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4247 seg = &gl->sg_segs[0];
4248 usgl = (void *)flitp;
4251 * We start at a 16 byte boundary somewhere inside the tx descriptor
4252 * ring, so we're at least 16 bytes away from the status page. There is
4253 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4256 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4257 V_ULPTX_NSGE(nsegs));
4258 usgl->len0 = htobe32(seg->ss_len);
4259 usgl->addr0 = htobe64(seg->ss_paddr);
4262 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4264 /* Won't wrap around at all */
4266 for (i = 0; i < nsegs - 1; i++, seg++) {
4267 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4268 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4271 usgl->sge[i / 2].len[1] = htobe32(0);
4275 /* Will wrap somewhere in the rest of the SGL */
4277 /* 2 flits already written, write the rest flit by flit */
4278 flitp = (void *)(usgl + 1);
4279 for (i = 0; i < nflits - 2; i++) {
4281 flitp = (void *)eq->desc;
4282 *flitp++ = get_flit(seg, nsegs - 1, i);
4287 MPASS(((uintptr_t)flitp) & 0xf);
4291 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4292 if (__predict_false(flitp == wrap))
4293 *to = (void *)eq->desc;
4295 *to = (void *)flitp;
4299 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4302 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4303 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4305 if (__predict_true((uintptr_t)(*to) + len <=
4306 (uintptr_t)&eq->desc[eq->sidx])) {
4307 bcopy(from, *to, len);
4310 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4312 bcopy(from, *to, portion);
4314 portion = len - portion; /* remaining */
4315 bcopy(from, (void *)eq->desc, portion);
4316 (*to) = (caddr_t)eq->desc + portion;
4321 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4329 clrbit(&db, DOORBELL_WCWR);
4332 switch (ffs(db) - 1) {
4334 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4337 case DOORBELL_WCWR: {
4338 volatile uint64_t *dst, *src;
4342 * Queues whose 128B doorbell segment fits in the page do not
4343 * use relative qid (udb_qid is always 0). Only queues with
4344 * doorbell segments can do WCWR.
4346 KASSERT(eq->udb_qid == 0 && n == 1,
4347 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4348 __func__, eq->doorbells, n, eq->dbidx, eq));
4350 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4353 src = (void *)&eq->desc[i];
4354 while (src != (void *)&eq->desc[i + 1])
4360 case DOORBELL_UDBWC:
4361 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4366 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4367 V_QID(eq->cntxt_id) | V_PIDX(n));
4371 IDXINCR(eq->dbidx, n, eq->sidx);
4375 reclaimable_tx_desc(struct sge_eq *eq)
4379 hw_cidx = read_hw_cidx(eq);
4380 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4384 total_available_tx_desc(struct sge_eq *eq)
4386 uint16_t hw_cidx, pidx;
4388 hw_cidx = read_hw_cidx(eq);
4391 if (pidx == hw_cidx)
4392 return (eq->sidx - 1);
4394 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4397 static inline uint16_t
4398 read_hw_cidx(struct sge_eq *eq)
4400 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4401 uint16_t cidx = spg->cidx; /* stable snapshot */
4403 return (be16toh(cidx));
4407 * Reclaim 'n' descriptors approximately.
4410 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4412 struct tx_sdesc *txsd;
4413 struct sge_eq *eq = &txq->eq;
4414 u_int can_reclaim, reclaimed;
4416 TXQ_LOCK_ASSERT_OWNED(txq);
4420 can_reclaim = reclaimable_tx_desc(eq);
4421 while (can_reclaim && reclaimed < n) {
4423 struct mbuf *m, *nextpkt;
4425 txsd = &txq->sdesc[eq->cidx];
4426 ndesc = txsd->desc_used;
4428 /* Firmware doesn't return "partial" credits. */
4429 KASSERT(can_reclaim >= ndesc,
4430 ("%s: unexpected number of credits: %d, %d",
4431 __func__, can_reclaim, ndesc));
4433 for (m = txsd->m; m != NULL; m = nextpkt) {
4434 nextpkt = m->m_nextpkt;
4435 m->m_nextpkt = NULL;
4439 can_reclaim -= ndesc;
4440 IDXINCR(eq->cidx, ndesc, eq->sidx);
4447 tx_reclaim(void *arg, int n)
4449 struct sge_txq *txq = arg;
4450 struct sge_eq *eq = &txq->eq;
4453 if (TXQ_TRYLOCK(txq) == 0)
4455 n = reclaim_tx_descs(txq, 32);
4456 if (eq->cidx == eq->pidx)
4457 eq->equeqidx = eq->pidx;
4463 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4465 int i = (idx / 3) * 2;
4471 rc = htobe32(segs[i].ss_len);
4473 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4478 return (htobe64(segs[i].ss_paddr));
4480 return (htobe64(segs[i + 1].ss_paddr));
4487 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4489 int8_t zidx, hwidx, idx;
4490 uint16_t region1, region3;
4491 int spare, spare_needed, n;
4492 struct sw_zone_info *swz;
4493 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4496 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4497 * large enough for the max payload and cluster metadata. Otherwise
4498 * settle for the largest bufsize that leaves enough room in the cluster
4501 * Without buffer packing: Look for the smallest zone which has a
4502 * bufsize large enough for the max payload. Settle for the largest
4503 * bufsize available if there's nothing big enough for max payload.
4505 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4506 swz = &sc->sge.sw_zone_info[0];
4508 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4509 if (swz->size > largest_rx_cluster) {
4510 if (__predict_true(hwidx != -1))
4514 * This is a misconfiguration. largest_rx_cluster is
4515 * preventing us from finding a refill source. See
4516 * dev.t5nex.<n>.buffer_sizes to figure out why.
4518 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4519 " refill source for fl %p (dma %u). Ignored.\n",
4520 largest_rx_cluster, fl, maxp);
4522 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4523 hwb = &hwb_list[idx];
4524 spare = swz->size - hwb->size;
4525 if (spare < spare_needed)
4528 hwidx = idx; /* best option so far */
4529 if (hwb->size >= maxp) {
4531 if ((fl->flags & FL_BUF_PACKING) == 0)
4532 goto done; /* stop looking (not packing) */
4534 if (swz->size >= safest_rx_cluster)
4535 goto done; /* stop looking (packing) */
4537 break; /* keep looking, next zone */
4541 /* A usable hwidx has been located. */
4543 hwb = &hwb_list[hwidx];
4545 swz = &sc->sge.sw_zone_info[zidx];
4547 region3 = swz->size - hwb->size;
4550 * Stay within this zone and see if there is a better match when mbuf
4551 * inlining is allowed. Remember that the hwidx's are sorted in
4552 * decreasing order of size (so in increasing order of spare area).
4554 for (idx = hwidx; idx != -1; idx = hwb->next) {
4555 hwb = &hwb_list[idx];
4556 spare = swz->size - hwb->size;
4558 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4562 * Do not inline mbufs if doing so would violate the pad/pack
4563 * boundary alignment requirement.
4565 if (fl_pad && (MSIZE % sc->sge.pad_boundary) != 0)
4567 if (fl->flags & FL_BUF_PACKING &&
4568 (MSIZE % sc->sge.pack_boundary) != 0)
4571 if (spare < CL_METADATA_SIZE + MSIZE)
4573 n = (spare - CL_METADATA_SIZE) / MSIZE;
4574 if (n > howmany(hwb->size, maxp))
4578 if (fl->flags & FL_BUF_PACKING) {
4579 region1 = n * MSIZE;
4580 region3 = spare - region1;
4583 region3 = spare - region1;
4588 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4589 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4590 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4591 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4592 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4593 sc->sge.sw_zone_info[zidx].size,
4594 ("%s: bad buffer layout for fl %p, maxp %d. "
4595 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4596 sc->sge.sw_zone_info[zidx].size, region1,
4597 sc->sge.hw_buf_info[hwidx].size, region3));
4598 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4599 KASSERT(region3 >= CL_METADATA_SIZE,
4600 ("%s: no room for metadata. fl %p, maxp %d; "
4601 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4602 sc->sge.sw_zone_info[zidx].size, region1,
4603 sc->sge.hw_buf_info[hwidx].size, region3));
4604 KASSERT(region1 % MSIZE == 0,
4605 ("%s: bad mbuf region for fl %p, maxp %d. "
4606 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4607 sc->sge.sw_zone_info[zidx].size, region1,
4608 sc->sge.hw_buf_info[hwidx].size, region3));
4611 fl->cll_def.zidx = zidx;
4612 fl->cll_def.hwidx = hwidx;
4613 fl->cll_def.region1 = region1;
4614 fl->cll_def.region3 = region3;
4618 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4620 struct sge *s = &sc->sge;
4621 struct hw_buf_info *hwb;
4622 struct sw_zone_info *swz;
4626 if (fl->flags & FL_BUF_PACKING)
4627 hwidx = s->safe_hwidx2; /* with room for metadata */
4628 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4629 hwidx = s->safe_hwidx2;
4630 hwb = &s->hw_buf_info[hwidx];
4631 swz = &s->sw_zone_info[hwb->zidx];
4632 spare = swz->size - hwb->size;
4634 /* no good if there isn't room for an mbuf as well */
4635 if (spare < CL_METADATA_SIZE + MSIZE)
4636 hwidx = s->safe_hwidx1;
4638 hwidx = s->safe_hwidx1;
4641 /* No fallback source */
4642 fl->cll_alt.hwidx = -1;
4643 fl->cll_alt.zidx = -1;
4648 hwb = &s->hw_buf_info[hwidx];
4649 swz = &s->sw_zone_info[hwb->zidx];
4650 spare = swz->size - hwb->size;
4651 fl->cll_alt.hwidx = hwidx;
4652 fl->cll_alt.zidx = hwb->zidx;
4653 if (allow_mbufs_in_cluster &&
4654 (fl_pad == 0 || (MSIZE % sc->sge.pad_boundary) == 0))
4655 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4657 fl->cll_alt.region1 = 0;
4658 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4662 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4664 mtx_lock(&sc->sfl_lock);
4666 if ((fl->flags & FL_DOOMED) == 0) {
4667 fl->flags |= FL_STARVING;
4668 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4669 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4672 mtx_unlock(&sc->sfl_lock);
4676 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
4678 struct sge_wrq *wrq = (void *)eq;
4680 atomic_readandclear_int(&eq->equiq);
4681 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
4685 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
4687 struct sge_txq *txq = (void *)eq;
4689 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
4691 atomic_readandclear_int(&eq->equiq);
4692 mp_ring_check_drainage(txq->r, 0);
4693 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
4697 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4700 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4701 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4702 struct adapter *sc = iq->adapter;
4703 struct sge *s = &sc->sge;
4705 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
4706 &handle_wrq_egr_update, &handle_eth_egr_update,
4707 &handle_wrq_egr_update};
4709 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4712 eq = s->eqmap[qid - s->eq_start];
4713 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
4718 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4719 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4720 offsetof(struct cpl_fw6_msg, data));
4723 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4725 struct adapter *sc = iq->adapter;
4726 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4728 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4731 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4732 const struct rss_header *rss2;
4734 rss2 = (const struct rss_header *)&cpl->data[0];
4735 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4738 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4742 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4744 uint16_t *id = arg1;
4747 return sysctl_handle_int(oidp, &i, 0, req);
4751 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4753 struct sge *s = arg1;
4754 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4755 struct sw_zone_info *swz = &s->sw_zone_info[0];
4760 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4761 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4762 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4767 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4771 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);