2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/in_cksum.h>
57 #include <machine/md_var.h>
61 #include <machine/bus.h>
62 #include <sys/selinfo.h>
63 #include <net/if_var.h>
64 #include <net/netmap.h>
65 #include <dev/netmap/netmap_kern.h>
68 #include "common/common.h"
69 #include "common/t4_regs.h"
70 #include "common/t4_regs_values.h"
71 #include "common/t4_msg.h"
73 #include "t4_mp_ring.h"
75 #ifdef T4_PKT_TIMESTAMP
76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
78 #define RX_COPY_THRESHOLD MINCLSIZE
82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
83 * 0-7 are valid values.
85 static int fl_pktshift = 2;
86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
89 * Pad ethernet payload up to this boundary.
90 * -1: driver should figure out a good value.
92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
99 * -1: driver should figure out a good value.
100 * 64 or 128 are the only other valid values.
102 static int spg_len = -1;
103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
107 * -1: no congestion feedback (not recommended).
108 * 0: backpressure the channel instead of dropping packets right away.
109 * 1: no backpressure, drop packets for the congested queue immediately.
111 static int cong_drop = 0;
112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
115 * Deliver multiple frames in the same free list buffer if they fit.
116 * -1: let the driver decide whether to enable buffer packing or not.
117 * 0: disable buffer packing.
118 * 1: enable buffer packing.
120 static int buffer_packing = -1;
121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
124 * Start next frame in a packed buffer at this boundary.
125 * -1: driver should figure out a good value.
126 * T4: driver will ignore this and use the same value as fl_pad above.
127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
129 static int fl_pack = -1;
130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
133 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
135 * 1: ok to create mbuf(s) within a cluster if there is room.
137 static int allow_mbufs_in_cluster = 1;
138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
141 * Largest rx cluster size that the driver is allowed to allocate.
143 static int largest_rx_cluster = MJUM16BYTES;
144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
147 * Size of cluster allocation that's most likely to succeed. The driver will
148 * fall back to this size if it fails to allocate clusters larger than this.
150 static int safest_rx_cluster = PAGE_SIZE;
151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
154 * The interrupt holdoff timers are multiplied by this value on T6+.
155 * 1 and 3-17 (both inclusive) are legal values.
157 static int tscale = 1;
158 TUNABLE_INT("hw.cxgbe.tscale", &tscale);
161 u_int wr_type; /* type 0 or type 1 */
162 u_int npkt; /* # of packets in this work request */
163 u_int plen; /* total payload (sum of all packets) */
164 u_int len16; /* # of 16B pieces used by this work request */
167 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
170 struct sglist_seg seg[TX_SGL_SEGS];
173 static int service_iq(struct sge_iq *, int);
174 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
175 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
176 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
177 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
178 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
180 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
181 bus_addr_t *, void **);
182 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
184 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
186 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
187 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
188 struct sysctl_oid *, struct sge_fl *);
189 static int alloc_fwq(struct adapter *);
190 static int free_fwq(struct adapter *);
191 static int alloc_mgmtq(struct adapter *);
192 static int free_mgmtq(struct adapter *);
193 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
194 struct sysctl_oid *);
195 static int free_rxq(struct vi_info *, struct sge_rxq *);
197 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
198 struct sysctl_oid *);
199 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
202 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
203 struct sysctl_oid *);
204 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
205 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
206 struct sysctl_oid *);
207 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
209 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
210 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
212 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
214 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
215 static int free_eq(struct adapter *, struct sge_eq *);
216 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
217 struct sysctl_oid *);
218 static int free_wrq(struct adapter *, struct sge_wrq *);
219 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
220 struct sysctl_oid *);
221 static int free_txq(struct vi_info *, struct sge_txq *);
222 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
223 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
224 static int refill_fl(struct adapter *, struct sge_fl *, int);
225 static void refill_sfl(void *);
226 static int alloc_fl_sdesc(struct sge_fl *);
227 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
228 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
229 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
230 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
232 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
233 static inline u_int txpkt_len16(u_int, u_int);
234 static inline u_int txpkt_vm_len16(u_int, u_int);
235 static inline u_int txpkts0_len16(u_int);
236 static inline u_int txpkts1_len16(void);
237 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
238 struct mbuf *, u_int);
239 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
240 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
241 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
242 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
243 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
244 struct mbuf *, const struct txpkts *, u_int);
245 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
246 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
247 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
248 static inline uint16_t read_hw_cidx(struct sge_eq *);
249 static inline u_int reclaimable_tx_desc(struct sge_eq *);
250 static inline u_int total_available_tx_desc(struct sge_eq *);
251 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
252 static void tx_reclaim(void *, int);
253 static __be64 get_flit(struct sglist_seg *, int, int);
254 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
256 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
258 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
259 static void wrq_tx_drain(void *, int);
260 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
262 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
263 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
264 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
266 static counter_u64_t extfree_refs;
267 static counter_u64_t extfree_rels;
269 an_handler_t t4_an_handler;
270 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
271 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
275 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
279 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
281 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
288 t4_register_an_handler(an_handler_t h)
292 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
293 loc = (uintptr_t *) &t4_an_handler;
294 atomic_store_rel_ptr(loc, new);
300 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
302 const struct cpl_fw6_msg *cpl =
303 __containerof(rpl, struct cpl_fw6_msg, data[0]);
306 panic("%s: fw_msg type %d", __func__, cpl->type);
308 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
314 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
318 if (type >= nitems(t4_fw_msg_handler))
322 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
323 * handler dispatch table. Reject any attempt to install a handler for
326 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
329 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
330 loc = (uintptr_t *) &t4_fw_msg_handler[type];
331 atomic_store_rel_ptr(loc, new);
337 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
341 panic("%s: opcode 0x%02x on iq %p with payload %p",
342 __func__, rss->opcode, iq, m);
344 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
345 __func__, rss->opcode, iq, m);
352 t4_register_cpl_handler(int opcode, cpl_handler_t h)
356 if (opcode >= nitems(t4_cpl_handler))
359 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
360 loc = (uintptr_t *) &t4_cpl_handler[opcode];
361 atomic_store_rel_ptr(loc, new);
367 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
374 if (fl_pktshift < 0 || fl_pktshift > 7) {
375 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
376 " using 2 instead.\n", fl_pktshift);
380 if (spg_len != 64 && spg_len != 128) {
383 #if defined(__i386__) || defined(__amd64__)
384 len = cpu_clflush_line_size > 64 ? 128 : 64;
389 printf("Invalid hw.cxgbe.spg_len value (%d),"
390 " using %d instead.\n", spg_len, len);
395 if (cong_drop < -1 || cong_drop > 1) {
396 printf("Invalid hw.cxgbe.cong_drop value (%d),"
397 " using 0 instead.\n", cong_drop);
401 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
402 printf("Invalid hw.cxgbe.tscale value (%d),"
403 " using 1 instead.\n", tscale);
407 extfree_refs = counter_u64_alloc(M_WAITOK);
408 extfree_rels = counter_u64_alloc(M_WAITOK);
409 counter_u64_zero(extfree_refs);
410 counter_u64_zero(extfree_rels);
412 t4_an_handler = an_not_handled;
413 for (i = 0; i < nitems(t4_fw_msg_handler); i++)
414 t4_fw_msg_handler[i] = fw_msg_not_handled;
415 for (i = 0; i < nitems(t4_cpl_handler); i++)
416 t4_cpl_handler[i] = cpl_not_handled;
418 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
419 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
420 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
421 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
422 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
423 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
427 t4_sge_modunload(void)
430 counter_u64_free(extfree_refs);
431 counter_u64_free(extfree_rels);
435 t4_sge_extfree_refs(void)
439 rels = counter_u64_fetch(extfree_rels);
440 refs = counter_u64_fetch(extfree_refs);
442 return (refs - rels);
446 setup_pad_and_pack_boundaries(struct adapter *sc)
449 int pad, pack, pad_shift;
451 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
452 X_INGPADBOUNDARY_SHIFT;
454 if (fl_pad < (1 << pad_shift) ||
455 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
458 * If there is any chance that we might use buffer packing and
459 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
460 * it to the minimum allowed in all other cases.
462 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
465 * For fl_pad = 0 we'll still write a reasonable value to the
466 * register but all the freelists will opt out of padding.
467 * We'll complain here only if the user tried to set it to a
468 * value greater than 0 that was invalid.
471 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
472 " (%d), using %d instead.\n", fl_pad, pad);
475 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
476 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
477 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
480 if (fl_pack != -1 && fl_pack != pad) {
481 /* Complain but carry on. */
482 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
483 " using %d instead.\n", fl_pack, pad);
489 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
490 !powerof2(fl_pack)) {
491 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
492 MPASS(powerof2(pack));
500 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
501 " (%d), using %d instead.\n", fl_pack, pack);
504 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
506 v = V_INGPACKBOUNDARY(0);
508 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
510 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
511 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
515 * adap->params.vpd.cclk must be set up before this is called.
518 t4_tweak_chip_settings(struct adapter *sc)
522 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
523 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
524 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
525 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
526 static int sge_flbuf_sizes[] = {
528 #if MJUMPAGESIZE != MCLBYTES
530 MJUMPAGESIZE - CL_METADATA_SIZE,
531 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
535 MCLBYTES - MSIZE - CL_METADATA_SIZE,
536 MJUM9BYTES - CL_METADATA_SIZE,
537 MJUM16BYTES - CL_METADATA_SIZE,
540 KASSERT(sc->flags & MASTER_PF,
541 ("%s: trying to change chip settings when not master.", __func__));
543 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
544 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
545 V_EGRSTATUSPAGESIZE(spg_len == 128);
546 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
548 setup_pad_and_pack_boundaries(sc);
550 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
551 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
552 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
553 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
554 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
555 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
556 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
557 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
558 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
560 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
561 ("%s: hw buffer size table too big", __func__));
562 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
563 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
567 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
568 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
569 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
571 KASSERT(intr_timer[0] <= timer_max,
572 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
574 for (i = 1; i < nitems(intr_timer); i++) {
575 KASSERT(intr_timer[i] >= intr_timer[i - 1],
576 ("%s: timers not listed in increasing order (%d)",
579 while (intr_timer[i] > timer_max) {
580 if (i == nitems(intr_timer) - 1) {
581 intr_timer[i] = timer_max;
584 intr_timer[i] += intr_timer[i - 1];
589 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
590 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
591 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
592 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
593 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
594 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
595 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
596 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
597 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
599 if (chip_id(sc) >= CHELSIO_T6) {
600 m = V_TSCALE(M_TSCALE);
604 v = V_TSCALE(tscale - 2);
605 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
608 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
609 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
610 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
613 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
614 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
615 * may have to deal with is MAXPHYS + 1 page.
617 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
618 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
620 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
621 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
622 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
624 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
626 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
627 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
631 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
632 * padding is in use, the buffer's start and end need to be aligned to the pad
633 * boundary as well. We'll just make sure that the size is a multiple of the
634 * boundary here, it is up to the buffer allocation code to make sure the start
635 * of the buffer is aligned as well.
638 hwsz_ok(struct adapter *sc, int hwsz)
640 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
642 return (hwsz >= 64 && (hwsz & mask) == 0);
646 * XXX: driver really should be able to deal with unexpected settings.
649 t4_read_chip_settings(struct adapter *sc)
651 struct sge *s = &sc->sge;
652 struct sge_params *sp = &sc->params.sge;
655 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
656 static int sw_buf_sizes[] = { /* Sorted by size */
658 #if MJUMPAGESIZE != MCLBYTES
664 struct sw_zone_info *swz, *safe_swz;
665 struct hw_buf_info *hwb;
669 r = sc->params.sge.sge_control;
671 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
676 * If this changes then every single use of PAGE_SHIFT in the driver
677 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
679 if (sp->page_shift != PAGE_SHIFT) {
680 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
684 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
685 hwb = &s->hw_buf_info[0];
686 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
687 r = sc->params.sge.sge_fl_buffer_size[i];
689 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
694 * Create a sorted list in decreasing order of hw buffer sizes (and so
695 * increasing order of spare area) for each software zone.
697 * If padding is enabled then the start and end of the buffer must align
698 * to the pad boundary; if packing is enabled then they must align with
699 * the pack boundary as well. Allocations from the cluster zones are
700 * aligned to min(size, 4K), so the buffer starts at that alignment and
701 * ends at hwb->size alignment. If mbuf inlining is allowed the
702 * starting alignment will be reduced to MSIZE and the driver will
703 * exercise appropriate caution when deciding on the best buffer layout
706 n = 0; /* no usable buffer size to begin with */
707 swz = &s->sw_zone_info[0];
709 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
710 int8_t head = -1, tail = -1;
712 swz->size = sw_buf_sizes[i];
713 swz->zone = m_getzone(swz->size);
714 swz->type = m_gettype(swz->size);
716 if (swz->size < PAGE_SIZE) {
717 MPASS(powerof2(swz->size));
718 if (fl_pad && (swz->size % sp->pad_boundary != 0))
722 if (swz->size == safest_rx_cluster)
725 hwb = &s->hw_buf_info[0];
726 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
727 if (hwb->zidx != -1 || hwb->size > swz->size)
731 MPASS(hwb->size % sp->pad_boundary == 0);
736 else if (hwb->size < s->hw_buf_info[tail].size) {
737 s->hw_buf_info[tail].next = j;
741 struct hw_buf_info *t;
743 for (cur = &head; *cur != -1; cur = &t->next) {
744 t = &s->hw_buf_info[*cur];
745 if (hwb->size == t->size) {
749 if (hwb->size > t->size) {
757 swz->head_hwidx = head;
758 swz->tail_hwidx = tail;
762 if (swz->size - s->hw_buf_info[tail].size >=
764 sc->flags |= BUF_PACKING_OK;
768 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
774 if (safe_swz != NULL) {
775 s->safe_hwidx1 = safe_swz->head_hwidx;
776 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
779 hwb = &s->hw_buf_info[i];
782 MPASS(hwb->size % sp->pad_boundary == 0);
784 spare = safe_swz->size - hwb->size;
785 if (spare >= CL_METADATA_SIZE) {
792 if (sc->flags & IS_VF)
795 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
796 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
798 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
802 m = v = F_TDDPTAGTCB;
803 r = t4_read_reg(sc, A_ULP_RX_CTL);
805 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
809 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
811 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
812 r = t4_read_reg(sc, A_TP_PARA_REG5);
814 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
818 t4_init_tp_params(sc);
820 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
821 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
827 t4_create_dma_tag(struct adapter *sc)
831 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
832 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
833 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
836 device_printf(sc->dev,
837 "failed to create main DMA tag: %d\n", rc);
844 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
845 struct sysctl_oid_list *children)
847 struct sge_params *sp = &sc->params.sge;
849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
850 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
851 "freelist buffer sizes");
853 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
854 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
856 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
857 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
859 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
860 NULL, sp->spg_len, "status page size (bytes)");
862 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
863 NULL, cong_drop, "congestion drop setting");
865 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
866 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
870 t4_destroy_dma_tag(struct adapter *sc)
873 bus_dma_tag_destroy(sc->dmat);
879 * Allocate and initialize the firmware event queue and the management queue.
881 * Returns errno on failure. Resources allocated up to that point may still be
882 * allocated. Caller is responsible for cleanup in case this function fails.
885 t4_setup_adapter_queues(struct adapter *sc)
889 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
891 sysctl_ctx_init(&sc->ctx);
892 sc->flags |= ADAP_SYSCTL_CTX;
895 * Firmware event queue
902 * Management queue. This is just a control queue that uses the fwq as
905 if (!(sc->flags & IS_VF))
906 rc = alloc_mgmtq(sc);
915 t4_teardown_adapter_queues(struct adapter *sc)
918 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
920 /* Do this before freeing the queue */
921 if (sc->flags & ADAP_SYSCTL_CTX) {
922 sysctl_ctx_free(&sc->ctx);
923 sc->flags &= ~ADAP_SYSCTL_CTX;
933 first_vector(struct vi_info *vi)
935 struct adapter *sc = vi->pi->adapter;
937 if (sc->intr_count == 1)
940 return (vi->first_intr);
944 * Given an arbitrary "index," come up with an iq that can be used by other
945 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
946 * The iq returned is guaranteed to be something that takes direct interrupts.
948 static struct sge_iq *
949 vi_intr_iq(struct vi_info *vi, int idx)
951 struct adapter *sc = vi->pi->adapter;
952 struct sge *s = &sc->sge;
953 struct sge_iq *iq = NULL;
956 if (sc->intr_count == 1)
957 return (&sc->sge.fwq);
961 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
962 __func__, vi, sc->intr_count));
965 if (vi->flags & INTR_RXQ) {
967 iq = &s->rxq[vi->first_rxq + i].iq;
973 if (vi->flags & INTR_OFLD_RXQ) {
974 if (i < vi->nofldrxq) {
975 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
981 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
982 vi, vi->flags & INTR_ALL, idx, nintr);
985 KASSERT(iq->flags & IQ_INTR,
986 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
987 vi->flags & INTR_ALL, idx));
991 /* Maximum payload that can be delivered with a single iq descriptor */
993 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
999 payload = sc->tt.rx_coalesce ?
1000 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
1003 /* large enough even when hw VLAN extraction is disabled */
1004 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1005 ETHER_VLAN_ENCAP_LEN + mtu;
1014 t4_setup_vi_queues(struct vi_info *vi)
1016 int rc = 0, i, j, intr_idx, iqid;
1017 struct sge_rxq *rxq;
1018 struct sge_txq *txq;
1019 struct sge_wrq *ctrlq;
1021 struct sge_ofld_rxq *ofld_rxq;
1022 struct sge_wrq *ofld_txq;
1026 struct sge_nm_rxq *nm_rxq;
1027 struct sge_nm_txq *nm_txq;
1030 struct port_info *pi = vi->pi;
1031 struct adapter *sc = pi->adapter;
1032 struct ifnet *ifp = vi->ifp;
1033 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1034 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1035 int maxp, mtu = ifp->if_mtu;
1037 /* Interrupt vector to start from (when using multiple vectors) */
1038 intr_idx = first_vector(vi);
1041 saved_idx = intr_idx;
1042 if (ifp->if_capabilities & IFCAP_NETMAP) {
1044 /* netmap is supported with direct interrupts only. */
1045 MPASS(vi->flags & INTR_RXQ);
1048 * We don't have buffers to back the netmap rx queues
1049 * right now so we create the queues in a way that
1050 * doesn't set off any congestion signal in the chip.
1052 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1053 CTLFLAG_RD, NULL, "rx queues");
1054 for_each_nm_rxq(vi, i, nm_rxq) {
1055 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1061 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1062 CTLFLAG_RD, NULL, "tx queues");
1063 for_each_nm_txq(vi, i, nm_txq) {
1064 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
1065 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
1071 /* Normal rx queues and netmap rx queues share the same interrupts. */
1072 intr_idx = saved_idx;
1076 * First pass over all NIC and TOE rx queues:
1077 * a) initialize iq and fl
1078 * b) allocate queue iff it will take direct interrupts.
1080 maxp = mtu_to_max_payload(sc, mtu, 0);
1081 if (vi->flags & INTR_RXQ) {
1082 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1083 CTLFLAG_RD, NULL, "rx queues");
1085 for_each_rxq(vi, i, rxq) {
1087 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1089 snprintf(name, sizeof(name), "%s rxq%d-fl",
1090 device_get_nameunit(vi->dev), i);
1091 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1093 if (vi->flags & INTR_RXQ) {
1094 rxq->iq.flags |= IQ_INTR;
1095 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1102 if (ifp->if_capabilities & IFCAP_NETMAP)
1103 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1106 maxp = mtu_to_max_payload(sc, mtu, 1);
1107 if (vi->flags & INTR_OFLD_RXQ) {
1108 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1110 "rx queues for offloaded TCP connections");
1112 for_each_ofld_rxq(vi, i, ofld_rxq) {
1114 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
1117 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1118 device_get_nameunit(vi->dev), i);
1119 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1121 if (vi->flags & INTR_OFLD_RXQ) {
1122 ofld_rxq->iq.flags |= IQ_INTR;
1123 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1132 * Second pass over all NIC and TOE rx queues. The queues forwarding
1133 * their interrupts are allocated now.
1136 if (!(vi->flags & INTR_RXQ)) {
1137 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1138 CTLFLAG_RD, NULL, "rx queues");
1139 for_each_rxq(vi, i, rxq) {
1140 MPASS(!(rxq->iq.flags & IQ_INTR));
1142 intr_idx = vi_intr_iq(vi, j)->abs_id;
1144 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1151 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1152 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1154 "rx queues for offloaded TCP connections");
1155 for_each_ofld_rxq(vi, i, ofld_rxq) {
1156 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1158 intr_idx = vi_intr_iq(vi, j)->abs_id;
1160 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1169 * Now the tx queues. Only one pass needed.
1171 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1174 for_each_txq(vi, i, txq) {
1175 iqid = vi_intr_iq(vi, j)->cntxt_id;
1176 snprintf(name, sizeof(name), "%s txq%d",
1177 device_get_nameunit(vi->dev), i);
1178 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1181 rc = alloc_txq(vi, txq, i, oid);
1187 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1188 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1189 for_each_ofld_txq(vi, i, ofld_txq) {
1190 struct sysctl_oid *oid2;
1192 iqid = vi_intr_iq(vi, j)->cntxt_id;
1193 snprintf(name, sizeof(name), "%s ofld_txq%d",
1194 device_get_nameunit(vi->dev), i);
1195 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1198 snprintf(name, sizeof(name), "%d", i);
1199 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1200 name, CTLFLAG_RD, NULL, "offload tx queue");
1202 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1210 * Finally, the control queue.
1212 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1214 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1215 NULL, "ctrl queue");
1216 ctrlq = &sc->sge.ctrlq[pi->port_id];
1217 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1218 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1219 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1221 rc = alloc_wrq(sc, vi, ctrlq, oid);
1225 t4_teardown_vi_queues(vi);
1234 t4_teardown_vi_queues(struct vi_info *vi)
1237 struct port_info *pi = vi->pi;
1238 struct adapter *sc = pi->adapter;
1239 struct sge_rxq *rxq;
1240 struct sge_txq *txq;
1242 struct sge_ofld_rxq *ofld_rxq;
1243 struct sge_wrq *ofld_txq;
1246 struct sge_nm_rxq *nm_rxq;
1247 struct sge_nm_txq *nm_txq;
1250 /* Do this before freeing the queues */
1251 if (vi->flags & VI_SYSCTL_CTX) {
1252 sysctl_ctx_free(&vi->ctx);
1253 vi->flags &= ~VI_SYSCTL_CTX;
1257 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1258 for_each_nm_txq(vi, i, nm_txq) {
1259 free_nm_txq(vi, nm_txq);
1262 for_each_nm_rxq(vi, i, nm_rxq) {
1263 free_nm_rxq(vi, nm_rxq);
1269 * Take down all the tx queues first, as they reference the rx queues
1270 * (for egress updates, etc.).
1273 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1274 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1276 for_each_txq(vi, i, txq) {
1280 for_each_ofld_txq(vi, i, ofld_txq) {
1281 free_wrq(sc, ofld_txq);
1286 * Then take down the rx queues that forward their interrupts, as they
1287 * reference other rx queues.
1290 for_each_rxq(vi, i, rxq) {
1291 if ((rxq->iq.flags & IQ_INTR) == 0)
1295 for_each_ofld_rxq(vi, i, ofld_rxq) {
1296 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1297 free_ofld_rxq(vi, ofld_rxq);
1302 * Then take down the rx queues that take direct interrupts.
1305 for_each_rxq(vi, i, rxq) {
1306 if (rxq->iq.flags & IQ_INTR)
1310 for_each_ofld_rxq(vi, i, ofld_rxq) {
1311 if (ofld_rxq->iq.flags & IQ_INTR)
1312 free_ofld_rxq(vi, ofld_rxq);
1320 * Deals with errors and the firmware event queue. All data rx queues forward
1321 * their interrupt to the firmware event queue.
1324 t4_intr_all(void *arg)
1326 struct adapter *sc = arg;
1327 struct sge_iq *fwq = &sc->sge.fwq;
1330 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1332 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1336 /* Deals with error interrupts */
1338 t4_intr_err(void *arg)
1340 struct adapter *sc = arg;
1342 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1343 t4_slow_intr_handler(sc);
1347 t4_intr_evt(void *arg)
1349 struct sge_iq *iq = arg;
1351 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1353 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1360 struct sge_iq *iq = arg;
1362 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1364 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1369 t4_vi_intr(void *arg)
1371 struct irq *irq = arg;
1374 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1375 t4_nm_intr(irq->nm_rxq);
1376 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1379 if (irq->rxq != NULL)
1384 * Deals with anything and everything on the given ingress queue.
1387 service_iq(struct sge_iq *iq, int budget)
1390 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1391 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1392 struct adapter *sc = iq->adapter;
1393 struct iq_desc *d = &iq->desc[iq->cidx];
1394 int ndescs = 0, limit;
1395 int rsp_type, refill;
1397 uint16_t fl_hw_cidx;
1399 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1400 #if defined(INET) || defined(INET6)
1401 const struct timeval lro_timeout = {0, sc->lro_timeout};
1404 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1406 limit = budget ? budget : iq->qsize / 16;
1408 if (iq->flags & IQ_HAS_FL) {
1410 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1413 fl_hw_cidx = 0; /* to silence gcc warning */
1417 * We always come back and check the descriptor ring for new indirect
1418 * interrupts and other responses after running a single handler.
1421 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1427 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1428 lq = be32toh(d->rsp.pldbuflen_qid);
1431 case X_RSPD_TYPE_FLBUF:
1433 KASSERT(iq->flags & IQ_HAS_FL,
1434 ("%s: data for an iq (%p) with no freelist",
1437 m0 = get_fl_payload(sc, fl, lq);
1438 if (__predict_false(m0 == NULL))
1440 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1441 #ifdef T4_PKT_TIMESTAMP
1443 * 60 bit timestamp for the payload is
1444 * *(uint64_t *)m0->m_pktdat. Note that it is
1445 * in the leading free-space in the mbuf. The
1446 * kernel can clobber it during a pullup,
1447 * m_copymdata, etc. You need to make sure that
1448 * the mbuf reaches you unmolested if you care
1449 * about the timestamp.
1451 *(uint64_t *)m0->m_pktdat =
1452 be64toh(ctrl->u.last_flit) &
1458 case X_RSPD_TYPE_CPL:
1459 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1460 ("%s: bad opcode %02x.", __func__,
1462 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1465 case X_RSPD_TYPE_INTR:
1468 * Interrupts should be forwarded only to queues
1469 * that are not forwarding their interrupts.
1470 * This means service_iq can recurse but only 1
1473 KASSERT(budget == 0,
1474 ("%s: budget %u, rsp_type %u", __func__,
1478 * There are 1K interrupt-capable queues (qids 0
1479 * through 1023). A response type indicating a
1480 * forwarded interrupt with a qid >= 1K is an
1481 * iWARP async notification.
1484 t4_an_handler(iq, &d->rsp);
1488 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1490 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1492 if (service_iq(q, q->qsize / 16) == 0) {
1493 atomic_cmpset_int(&q->state,
1494 IQS_BUSY, IQS_IDLE);
1496 STAILQ_INSERT_TAIL(&iql, q,
1504 ("%s: illegal response type %d on iq %p",
1505 __func__, rsp_type, iq));
1507 "%s: illegal response type %d on iq %p",
1508 device_get_nameunit(sc->dev), rsp_type, iq);
1513 if (__predict_false(++iq->cidx == iq->sidx)) {
1515 iq->gen ^= F_RSPD_GEN;
1518 if (__predict_false(++ndescs == limit)) {
1519 t4_write_reg(sc, sc->sge_gts_reg,
1521 V_INGRESSQID(iq->cntxt_id) |
1522 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1525 #if defined(INET) || defined(INET6)
1526 if (iq->flags & IQ_LRO_ENABLED &&
1527 sc->lro_timeout != 0) {
1528 tcp_lro_flush_inactive(&rxq->lro,
1534 if (iq->flags & IQ_HAS_FL) {
1536 refill_fl(sc, fl, 32);
1539 return (EINPROGRESS);
1544 refill_fl(sc, fl, 32);
1546 fl_hw_cidx = fl->hw_cidx;
1551 if (STAILQ_EMPTY(&iql))
1555 * Process the head only, and send it to the back of the list if
1556 * it's still not done.
1558 q = STAILQ_FIRST(&iql);
1559 STAILQ_REMOVE_HEAD(&iql, link);
1560 if (service_iq(q, q->qsize / 8) == 0)
1561 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1563 STAILQ_INSERT_TAIL(&iql, q, link);
1566 #if defined(INET) || defined(INET6)
1567 if (iq->flags & IQ_LRO_ENABLED) {
1568 struct lro_ctrl *lro = &rxq->lro;
1570 tcp_lro_flush_all(lro);
1574 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1575 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1577 if (iq->flags & IQ_HAS_FL) {
1581 starved = refill_fl(sc, fl, 64);
1583 if (__predict_false(starved != 0))
1584 add_fl_to_sfl(sc, fl);
1591 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1593 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1596 MPASS(cll->region3 >= CL_METADATA_SIZE);
1601 static inline struct cluster_metadata *
1602 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1606 if (cl_has_metadata(fl, cll)) {
1607 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1609 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1615 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1617 uma_zone_t zone = arg1;
1620 uma_zfree(zone, cl);
1621 counter_u64_add(extfree_rels, 1);
1625 * The mbuf returned by this function could be allocated from zone_mbuf or
1626 * constructed in spare room in the cluster.
1628 * The mbuf carries the payload in one of these ways
1629 * a) frame inside the mbuf (mbuf from zone_mbuf)
1630 * b) m_cljset (for clusters without metadata) zone_mbuf
1631 * c) m_extaddref (cluster with metadata) inline mbuf
1632 * d) m_extaddref (cluster with metadata) zone_mbuf
1634 static struct mbuf *
1635 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1639 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1640 struct cluster_layout *cll = &sd->cll;
1641 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1642 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1643 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1647 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1648 len = min(remaining, blen);
1649 payload = sd->cl + cll->region1 + fl->rx_offset;
1650 if (fl->flags & FL_BUF_PACKING) {
1651 const u_int l = fr_offset + len;
1652 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1654 if (fl->rx_offset + len + pad < hwb->size)
1656 MPASS(fl->rx_offset + blen <= hwb->size);
1658 MPASS(fl->rx_offset == 0); /* not packing */
1662 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1665 * Copy payload into a freshly allocated mbuf.
1668 m = fr_offset == 0 ?
1669 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1672 fl->mbuf_allocated++;
1673 #ifdef T4_PKT_TIMESTAMP
1674 /* Leave room for a timestamp */
1677 /* copy data to mbuf */
1678 bcopy(payload, mtod(m, caddr_t), len);
1680 } else if (sd->nmbuf * MSIZE < cll->region1) {
1683 * There's spare room in the cluster for an mbuf. Create one
1684 * and associate it with the payload that's in the cluster.
1688 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1689 /* No bzero required */
1690 if (m_init(m, M_NOWAIT, MT_DATA,
1691 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1694 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1696 if (sd->nmbuf++ == 0)
1697 counter_u64_add(extfree_refs, 1);
1702 * Grab an mbuf from zone_mbuf and associate it with the
1703 * payload in the cluster.
1706 m = fr_offset == 0 ?
1707 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1710 fl->mbuf_allocated++;
1712 m_extaddref(m, payload, blen, &clm->refcount,
1713 rxb_free, swz->zone, sd->cl);
1714 if (sd->nmbuf++ == 0)
1715 counter_u64_add(extfree_refs, 1);
1717 m_cljset(m, sd->cl, swz->type);
1718 sd->cl = NULL; /* consumed, not a recycle candidate */
1722 m->m_pkthdr.len = remaining;
1725 if (fl->flags & FL_BUF_PACKING) {
1726 fl->rx_offset += blen;
1727 MPASS(fl->rx_offset <= hwb->size);
1728 if (fl->rx_offset < hwb->size)
1729 return (m); /* without advancing the cidx */
1732 if (__predict_false(++fl->cidx % 8 == 0)) {
1733 uint16_t cidx = fl->cidx / 8;
1735 if (__predict_false(cidx == fl->sidx))
1736 fl->cidx = cidx = 0;
1744 static struct mbuf *
1745 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1747 struct mbuf *m0, *m, **pnext;
1749 const u_int total = G_RSPD_LEN(len_newbuf);
1751 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1752 M_ASSERTPKTHDR(fl->m0);
1753 MPASS(fl->m0->m_pkthdr.len == total);
1754 MPASS(fl->remaining < total);
1758 remaining = fl->remaining;
1759 fl->flags &= ~FL_BUF_RESUME;
1763 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1765 if (__predict_false(++fl->cidx % 8 == 0)) {
1766 uint16_t cidx = fl->cidx / 8;
1768 if (__predict_false(cidx == fl->sidx))
1769 fl->cidx = cidx = 0;
1775 * Payload starts at rx_offset in the current hw buffer. Its length is
1776 * 'len' and it may span multiple hw buffers.
1779 m0 = get_scatter_segment(sc, fl, 0, total);
1782 remaining = total - m0->m_len;
1783 pnext = &m0->m_next;
1784 while (remaining > 0) {
1786 MPASS(fl->rx_offset == 0);
1787 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1788 if (__predict_false(m == NULL)) {
1791 fl->remaining = remaining;
1792 fl->flags |= FL_BUF_RESUME;
1797 remaining -= m->m_len;
1806 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1808 struct sge_rxq *rxq = iq_to_rxq(iq);
1809 struct ifnet *ifp = rxq->ifp;
1810 struct adapter *sc = iq->adapter;
1811 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1812 #if defined(INET) || defined(INET6)
1813 struct lro_ctrl *lro = &rxq->lro;
1815 static const int sw_hashtype[4][2] = {
1816 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1817 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1818 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1819 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1822 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1825 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1826 m0->m_len -= sc->params.sge.fl_pktshift;
1827 m0->m_data += sc->params.sge.fl_pktshift;
1829 m0->m_pkthdr.rcvif = ifp;
1830 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1831 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1833 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1834 if (ifp->if_capenable & IFCAP_RXCSUM &&
1835 cpl->l2info & htobe32(F_RXF_IP)) {
1836 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1837 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1839 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1840 cpl->l2info & htobe32(F_RXF_IP6)) {
1841 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1846 if (__predict_false(cpl->ip_frag))
1847 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1849 m0->m_pkthdr.csum_data = 0xffff;
1853 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1854 m0->m_flags |= M_VLANTAG;
1855 rxq->vlan_extraction++;
1858 #if defined(INET) || defined(INET6)
1859 if (iq->flags & IQ_LRO_ENABLED &&
1860 tcp_lro_rx(lro, m0, 0) == 0) {
1861 /* queued for LRO */
1864 ifp->if_input(ifp, m0);
1870 * Must drain the wrq or make sure that someone else will.
1873 wrq_tx_drain(void *arg, int n)
1875 struct sge_wrq *wrq = arg;
1876 struct sge_eq *eq = &wrq->eq;
1879 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1880 drain_wrq_wr_list(wrq->adapter, wrq);
1885 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1887 struct sge_eq *eq = &wrq->eq;
1888 u_int available, dbdiff; /* # of hardware descriptors */
1891 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1893 EQ_LOCK_ASSERT_OWNED(eq);
1894 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1895 wr = STAILQ_FIRST(&wrq->wr_list);
1896 MPASS(wr != NULL); /* Must be called with something useful to do */
1897 MPASS(eq->pidx == eq->dbidx);
1901 eq->cidx = read_hw_cidx(eq);
1902 if (eq->pidx == eq->cidx)
1903 available = eq->sidx - 1;
1905 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1907 MPASS(wr->wrq == wrq);
1908 n = howmany(wr->wr_len, EQ_ESIZE);
1912 dst = (void *)&eq->desc[eq->pidx];
1913 if (__predict_true(eq->sidx - eq->pidx > n)) {
1914 /* Won't wrap, won't end exactly at the status page. */
1915 bcopy(&wr->wr[0], dst, wr->wr_len);
1918 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1920 bcopy(&wr->wr[0], dst, first_portion);
1921 if (wr->wr_len > first_portion) {
1922 bcopy(&wr->wr[first_portion], &eq->desc[0],
1923 wr->wr_len - first_portion);
1925 eq->pidx = n - (eq->sidx - eq->pidx);
1927 wrq->tx_wrs_copied++;
1929 if (available < eq->sidx / 4 &&
1930 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1931 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1933 eq->equeqidx = eq->pidx;
1934 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1935 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1936 eq->equeqidx = eq->pidx;
1941 ring_eq_db(sc, eq, dbdiff);
1945 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1947 MPASS(wrq->nwr_pending > 0);
1949 MPASS(wrq->ndesc_needed >= n);
1950 wrq->ndesc_needed -= n;
1951 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1954 ring_eq_db(sc, eq, dbdiff);
1958 * Doesn't fail. Holds on to work requests it can't send right away.
1961 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1964 struct sge_eq *eq = &wrq->eq;
1967 EQ_LOCK_ASSERT_OWNED(eq);
1969 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1970 MPASS((wr->wr_len & 0x7) == 0);
1972 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1974 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1976 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1977 return; /* commit_wrq_wr will drain wr_list as well. */
1979 drain_wrq_wr_list(sc, wrq);
1981 /* Doorbell must have caught up to the pidx. */
1982 MPASS(eq->pidx == eq->dbidx);
1986 t4_update_fl_bufsize(struct ifnet *ifp)
1988 struct vi_info *vi = ifp->if_softc;
1989 struct adapter *sc = vi->pi->adapter;
1990 struct sge_rxq *rxq;
1992 struct sge_ofld_rxq *ofld_rxq;
1995 int i, maxp, mtu = ifp->if_mtu;
1997 maxp = mtu_to_max_payload(sc, mtu, 0);
1998 for_each_rxq(vi, i, rxq) {
2002 find_best_refill_source(sc, fl, maxp);
2006 maxp = mtu_to_max_payload(sc, mtu, 1);
2007 for_each_ofld_rxq(vi, i, ofld_rxq) {
2011 find_best_refill_source(sc, fl, maxp);
2018 mbuf_nsegs(struct mbuf *m)
2022 KASSERT(m->m_pkthdr.l5hlen > 0,
2023 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2025 return (m->m_pkthdr.l5hlen);
2029 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2033 m->m_pkthdr.l5hlen = nsegs;
2037 mbuf_len16(struct mbuf *m)
2042 n = m->m_pkthdr.PH_loc.eight[0];
2043 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2049 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2053 m->m_pkthdr.PH_loc.eight[0] = len16;
2057 needs_tso(struct mbuf *m)
2062 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2063 KASSERT(m->m_pkthdr.tso_segsz > 0,
2064 ("%s: TSO requested in mbuf %p but MSS not provided",
2073 needs_l3_csum(struct mbuf *m)
2078 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2084 needs_l4_csum(struct mbuf *m)
2089 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2090 CSUM_TCP_IPV6 | CSUM_TSO))
2096 needs_vlan_insertion(struct mbuf *m)
2101 if (m->m_flags & M_VLANTAG) {
2102 KASSERT(m->m_pkthdr.ether_vtag != 0,
2103 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2111 m_advance(struct mbuf **pm, int *poffset, int len)
2113 struct mbuf *m = *pm;
2114 int offset = *poffset;
2120 if (offset + len < m->m_len) {
2122 p = mtod(m, uintptr_t) + offset;
2125 len -= m->m_len - offset;
2136 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2137 * must have at least one mbuf that's not empty.
2140 count_mbuf_nsegs(struct mbuf *m)
2142 vm_paddr_t lastb, next;
2150 for (; m; m = m->m_next) {
2153 if (__predict_false(len == 0))
2155 va = mtod(m, vm_offset_t);
2156 next = pmap_kextract(va);
2157 nsegs += sglist_count(m->m_data, len);
2158 if (lastb + 1 == next)
2160 lastb = pmap_kextract(va + len - 1);
2168 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2169 * a) caller can assume it's been freed if this function returns with an error.
2170 * b) it may get defragged up if the gather list is too long for the hardware.
2173 parse_pkt(struct adapter *sc, struct mbuf **mp)
2175 struct mbuf *m0 = *mp, *m;
2176 int rc, nsegs, defragged = 0, offset;
2177 struct ether_header *eh;
2179 #if defined(INET) || defined(INET6)
2185 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2194 * First count the number of gather list segments in the payload.
2195 * Defrag the mbuf if nsegs exceeds the hardware limit.
2198 MPASS(m0->m_pkthdr.len > 0);
2199 nsegs = count_mbuf_nsegs(m0);
2200 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2201 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2205 *mp = m0 = m; /* update caller's copy after defrag */
2209 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2210 m0 = m_pullup(m0, m0->m_pkthdr.len);
2212 /* Should have left well enough alone. */
2216 *mp = m0; /* update caller's copy after pullup */
2219 set_mbuf_nsegs(m0, nsegs);
2220 if (sc->flags & IS_VF)
2221 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2223 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2225 if (!needs_tso(m0) &&
2226 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2230 eh = mtod(m, struct ether_header *);
2231 eh_type = ntohs(eh->ether_type);
2232 if (eh_type == ETHERTYPE_VLAN) {
2233 struct ether_vlan_header *evh = (void *)eh;
2235 eh_type = ntohs(evh->evl_proto);
2236 m0->m_pkthdr.l2hlen = sizeof(*evh);
2238 m0->m_pkthdr.l2hlen = sizeof(*eh);
2241 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2245 case ETHERTYPE_IPV6:
2247 struct ip6_hdr *ip6 = l3hdr;
2249 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2251 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2258 struct ip *ip = l3hdr;
2260 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2265 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2266 " with the same INET/INET6 options as the kernel.",
2270 #if defined(INET) || defined(INET6)
2271 if (needs_tso(m0)) {
2272 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2273 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2281 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2283 struct sge_eq *eq = &wrq->eq;
2284 struct adapter *sc = wrq->adapter;
2285 int ndesc, available;
2290 ndesc = howmany(len16, EQ_ESIZE / 16);
2291 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2295 if (!STAILQ_EMPTY(&wrq->wr_list))
2296 drain_wrq_wr_list(sc, wrq);
2298 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2301 wr = alloc_wrqe(len16 * 16, wrq);
2302 if (__predict_false(wr == NULL))
2305 cookie->ndesc = ndesc;
2309 eq->cidx = read_hw_cidx(eq);
2310 if (eq->pidx == eq->cidx)
2311 available = eq->sidx - 1;
2313 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2314 if (available < ndesc)
2317 cookie->pidx = eq->pidx;
2318 cookie->ndesc = ndesc;
2319 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2321 w = &eq->desc[eq->pidx];
2322 IDXINCR(eq->pidx, ndesc, eq->sidx);
2323 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2325 wrq->ss_pidx = cookie->pidx;
2326 wrq->ss_len = len16 * 16;
2335 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2337 struct sge_eq *eq = &wrq->eq;
2338 struct adapter *sc = wrq->adapter;
2340 struct wrq_cookie *prev, *next;
2342 if (cookie->pidx == -1) {
2343 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2349 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2350 pidx = cookie->pidx;
2351 MPASS(pidx >= 0 && pidx < eq->sidx);
2352 if (__predict_false(w == &wrq->ss[0])) {
2353 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2355 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2356 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2357 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2360 wrq->tx_wrs_direct++;
2363 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2364 next = TAILQ_NEXT(cookie, link);
2366 MPASS(pidx == eq->dbidx);
2367 if (next == NULL || ndesc >= 16)
2368 ring_eq_db(wrq->adapter, eq, ndesc);
2370 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2372 next->ndesc += ndesc;
2375 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2376 prev->ndesc += ndesc;
2378 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2380 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2381 drain_wrq_wr_list(sc, wrq);
2384 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2385 /* Doorbell must have caught up to the pidx. */
2386 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2393 can_resume_eth_tx(struct mp_ring *r)
2395 struct sge_eq *eq = r->cookie;
2397 return (total_available_tx_desc(eq) > eq->sidx / 8);
2401 cannot_use_txpkts(struct mbuf *m)
2403 /* maybe put a GL limit too, to avoid silliness? */
2405 return (needs_tso(m));
2409 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2410 * be consumed. Return the actual number consumed. 0 indicates a stall.
2413 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2415 struct sge_txq *txq = r->cookie;
2416 struct sge_eq *eq = &txq->eq;
2417 struct ifnet *ifp = txq->ifp;
2418 struct vi_info *vi = ifp->if_softc;
2419 struct port_info *pi = vi->pi;
2420 struct adapter *sc = pi->adapter;
2421 u_int total, remaining; /* # of packets */
2422 u_int available, dbdiff; /* # of hardware descriptors */
2424 struct mbuf *m0, *tail;
2426 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2428 remaining = IDXDIFF(pidx, cidx, r->size);
2429 MPASS(remaining > 0); /* Must not be called without work to do. */
2433 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2434 while (cidx != pidx) {
2435 m0 = r->items[cidx];
2437 if (++cidx == r->size)
2440 reclaim_tx_descs(txq, 2048);
2445 /* How many hardware descriptors do we have readily available. */
2446 if (eq->pidx == eq->cidx)
2447 available = eq->sidx - 1;
2449 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2450 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2452 while (remaining > 0) {
2454 m0 = r->items[cidx];
2456 MPASS(m0->m_nextpkt == NULL);
2458 if (available < SGE_MAX_WR_NDESC) {
2459 available += reclaim_tx_descs(txq, 64);
2460 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2461 break; /* out of descriptors */
2464 next_cidx = cidx + 1;
2465 if (__predict_false(next_cidx == r->size))
2468 wr = (void *)&eq->desc[eq->pidx];
2469 if (sc->flags & IS_VF) {
2472 ETHER_BPF_MTAP(ifp, m0);
2473 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2475 } else if (remaining > 1 &&
2476 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2478 /* pkts at cidx, next_cidx should both be in txp. */
2479 MPASS(txp.npkt == 2);
2480 tail = r->items[next_cidx];
2481 MPASS(tail->m_nextpkt == NULL);
2482 ETHER_BPF_MTAP(ifp, m0);
2483 ETHER_BPF_MTAP(ifp, tail);
2484 m0->m_nextpkt = tail;
2486 if (__predict_false(++next_cidx == r->size))
2489 while (next_cidx != pidx) {
2490 if (add_to_txpkts(r->items[next_cidx], &txp,
2493 tail->m_nextpkt = r->items[next_cidx];
2494 tail = tail->m_nextpkt;
2495 ETHER_BPF_MTAP(ifp, tail);
2496 if (__predict_false(++next_cidx == r->size))
2500 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2502 remaining -= txp.npkt;
2506 ETHER_BPF_MTAP(ifp, m0);
2507 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2509 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2513 IDXINCR(eq->pidx, n, eq->sidx);
2515 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2516 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2517 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2519 eq->equeqidx = eq->pidx;
2520 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2521 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2522 eq->equeqidx = eq->pidx;
2525 if (dbdiff >= 16 && remaining >= 4) {
2526 ring_eq_db(sc, eq, dbdiff);
2527 available += reclaim_tx_descs(txq, 4 * dbdiff);
2534 ring_eq_db(sc, eq, dbdiff);
2535 reclaim_tx_descs(txq, 32);
2544 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2548 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2549 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2550 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2551 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2555 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2556 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2557 if (pktc_idx >= 0) {
2558 iq->intr_params |= F_QINTR_CNT_EN;
2559 iq->intr_pktc_idx = pktc_idx;
2561 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2562 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2566 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2570 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2571 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2572 if (sc->flags & BUF_PACKING_OK &&
2573 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2574 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2575 fl->flags |= FL_BUF_PACKING;
2576 find_best_refill_source(sc, fl, maxp);
2577 find_safe_refill_source(sc, fl);
2581 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2582 uint8_t tx_chan, uint16_t iqid, char *name)
2584 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2586 eq->flags = eqtype & EQ_TYPEMASK;
2587 eq->tx_chan = tx_chan;
2589 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2590 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2594 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2595 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2599 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2600 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2602 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2606 rc = bus_dmamem_alloc(*tag, va,
2607 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2609 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2613 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2615 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2620 free_ring(sc, *tag, *map, *pa, *va);
2626 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2627 bus_addr_t pa, void *va)
2630 bus_dmamap_unload(tag, map);
2632 bus_dmamem_free(tag, va, map);
2634 bus_dma_tag_destroy(tag);
2640 * Allocates the ring for an ingress queue and an optional freelist. If the
2641 * freelist is specified it will be allocated and then associated with the
2644 * Returns errno on failure. Resources allocated up to that point may still be
2645 * allocated. Caller is responsible for cleanup in case this function fails.
2647 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2648 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2649 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2652 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2653 int intr_idx, int cong)
2655 int rc, i, cntxt_id;
2658 struct port_info *pi = vi->pi;
2659 struct adapter *sc = iq->adapter;
2660 struct sge_params *sp = &sc->params.sge;
2663 len = iq->qsize * IQ_ESIZE;
2664 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2665 (void **)&iq->desc);
2669 bzero(&c, sizeof(c));
2670 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2671 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2672 V_FW_IQ_CMD_VFN(0));
2674 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2677 /* Special handling for firmware event queue */
2678 if (iq == &sc->sge.fwq)
2679 v |= F_FW_IQ_CMD_IQASYNCH;
2681 if (iq->flags & IQ_INTR) {
2682 KASSERT(intr_idx < sc->intr_count,
2683 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2685 v |= F_FW_IQ_CMD_IQANDST;
2686 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2688 c.type_to_iqandstindex = htobe32(v |
2689 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2690 V_FW_IQ_CMD_VIID(vi->viid) |
2691 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2692 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2693 F_FW_IQ_CMD_IQGTSMODE |
2694 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2695 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2696 c.iqsize = htobe16(iq->qsize);
2697 c.iqaddr = htobe64(iq->ba);
2699 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2702 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2704 len = fl->qsize * EQ_ESIZE;
2705 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2706 &fl->ba, (void **)&fl->desc);
2710 /* Allocate space for one software descriptor per buffer. */
2711 rc = alloc_fl_sdesc(fl);
2713 device_printf(sc->dev,
2714 "failed to setup fl software descriptors: %d\n",
2719 if (fl->flags & FL_BUF_PACKING) {
2720 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2721 fl->buf_boundary = sp->pack_boundary;
2723 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2724 fl->buf_boundary = 16;
2726 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2727 fl->buf_boundary = sp->pad_boundary;
2729 c.iqns_to_fl0congen |=
2730 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2731 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2732 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2733 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2736 c.iqns_to_fl0congen |=
2737 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2738 F_FW_IQ_CMD_FL0CONGCIF |
2739 F_FW_IQ_CMD_FL0CONGEN);
2741 c.fl0dcaen_to_fl0cidxfthresh =
2742 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2743 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2744 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2745 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2746 c.fl0size = htobe16(fl->qsize);
2747 c.fl0addr = htobe64(fl->ba);
2750 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2752 device_printf(sc->dev,
2753 "failed to create ingress queue: %d\n", rc);
2758 iq->gen = F_RSPD_GEN;
2759 iq->intr_next = iq->intr_params;
2760 iq->cntxt_id = be16toh(c.iqid);
2761 iq->abs_id = be16toh(c.physiqid);
2762 iq->flags |= IQ_ALLOCATED;
2764 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2765 if (cntxt_id >= sc->sge.niq) {
2766 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2767 cntxt_id, sc->sge.niq - 1);
2769 sc->sge.iqmap[cntxt_id] = iq;
2774 iq->flags |= IQ_HAS_FL;
2775 fl->cntxt_id = be16toh(c.fl0id);
2776 fl->pidx = fl->cidx = 0;
2778 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2779 if (cntxt_id >= sc->sge.neq) {
2780 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2781 __func__, cntxt_id, sc->sge.neq - 1);
2783 sc->sge.eqmap[cntxt_id] = (void *)fl;
2786 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2787 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2788 uint32_t mask = (1 << s_qpp) - 1;
2789 volatile uint8_t *udb;
2791 udb = sc->udbs_base + UDBS_DB_OFFSET;
2792 udb += (qid >> s_qpp) << PAGE_SHIFT;
2794 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2795 udb += qid << UDBS_SEG_SHIFT;
2798 fl->udb = (volatile void *)udb;
2800 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2803 /* Enough to make sure the SGE doesn't think it's starved */
2804 refill_fl(sc, fl, fl->lowat);
2808 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2809 uint32_t param, val;
2811 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2812 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2813 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2818 for (i = 0; i < 4; i++) {
2819 if (cong & (1 << i))
2820 val |= 1 << (i << 2);
2824 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2826 /* report error but carry on */
2827 device_printf(sc->dev,
2828 "failed to set congestion manager context for "
2829 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2833 /* Enable IQ interrupts */
2834 atomic_store_rel_int(&iq->state, IQS_IDLE);
2835 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2836 V_INGRESSQID(iq->cntxt_id));
2842 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2845 struct adapter *sc = iq->adapter;
2849 return (0); /* nothing to do */
2851 dev = vi ? vi->dev : sc->dev;
2853 if (iq->flags & IQ_ALLOCATED) {
2854 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2855 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2856 fl ? fl->cntxt_id : 0xffff, 0xffff);
2859 "failed to free queue %p: %d\n", iq, rc);
2862 iq->flags &= ~IQ_ALLOCATED;
2865 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2867 bzero(iq, sizeof(*iq));
2870 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2874 free_fl_sdesc(sc, fl);
2876 if (mtx_initialized(&fl->fl_lock))
2877 mtx_destroy(&fl->fl_lock);
2879 bzero(fl, sizeof(*fl));
2886 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2887 struct sysctl_oid *oid, struct sge_fl *fl)
2889 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2891 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2893 children = SYSCTL_CHILDREN(oid);
2895 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2896 &fl->ba, "bus address of descriptor ring");
2897 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2898 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2899 "desc ring size in bytes");
2900 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2901 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2902 "SGE context id of the freelist");
2903 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2904 fl_pad ? 1 : 0, "padding enabled");
2905 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2906 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2907 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2908 0, "consumer index");
2909 if (fl->flags & FL_BUF_PACKING) {
2910 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2911 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2913 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2914 0, "producer index");
2915 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2916 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2917 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2918 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2919 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2920 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2921 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2922 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2923 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2924 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2928 alloc_fwq(struct adapter *sc)
2931 struct sge_iq *fwq = &sc->sge.fwq;
2932 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2933 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2935 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2936 fwq->flags |= IQ_INTR; /* always */
2937 if (sc->flags & IS_VF)
2940 intr_idx = sc->intr_count > 1 ? 1 : 0;
2941 fwq->set_tcb_rpl = t4_filter_rpl;
2942 fwq->l2t_write_rpl = do_l2t_write_rpl;
2944 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2946 device_printf(sc->dev,
2947 "failed to create firmware event queue: %d\n", rc);
2951 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2952 NULL, "firmware event queue");
2953 children = SYSCTL_CHILDREN(oid);
2955 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2956 &fwq->ba, "bus address of descriptor ring");
2957 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2958 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
2959 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2960 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2961 "absolute id of the queue");
2962 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2963 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2964 "SGE context id of the queue");
2965 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2966 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2973 free_fwq(struct adapter *sc)
2975 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2979 alloc_mgmtq(struct adapter *sc)
2982 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2984 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2985 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2987 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2988 NULL, "management queue");
2990 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2991 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2992 sc->sge.fwq.cntxt_id, name);
2993 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2995 device_printf(sc->dev,
2996 "failed to create management queue: %d\n", rc);
3004 free_mgmtq(struct adapter *sc)
3007 return free_wrq(sc, &sc->sge.mgmtq);
3011 tnl_cong(struct port_info *pi, int drop)
3019 return (pi->rx_chan_map);
3023 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3024 struct sysctl_oid *oid)
3027 struct adapter *sc = vi->pi->adapter;
3028 struct sysctl_oid_list *children;
3031 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3032 tnl_cong(vi->pi, cong_drop));
3037 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3039 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3040 ("iq_base mismatch"));
3041 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3042 ("PF with non-zero iq_base"));
3045 * The freelist is just barely above the starvation threshold right now,
3046 * fill it up a bit more.
3049 refill_fl(sc, &rxq->fl, 128);
3050 FL_UNLOCK(&rxq->fl);
3052 #if defined(INET) || defined(INET6)
3053 rc = tcp_lro_init(&rxq->lro);
3056 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
3058 if (vi->ifp->if_capenable & IFCAP_LRO)
3059 rxq->iq.flags |= IQ_LRO_ENABLED;
3063 children = SYSCTL_CHILDREN(oid);
3065 snprintf(name, sizeof(name), "%d", idx);
3066 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3068 children = SYSCTL_CHILDREN(oid);
3070 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3071 &rxq->iq.ba, "bus address of descriptor ring");
3072 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3073 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3074 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3075 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
3076 "absolute id of the queue");
3077 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3078 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
3079 "SGE context id of the queue");
3080 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3081 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
3083 #if defined(INET) || defined(INET6)
3084 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3085 &rxq->lro.lro_queued, 0, NULL);
3086 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3087 &rxq->lro.lro_flushed, 0, NULL);
3089 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3090 &rxq->rxcsum, "# of times hardware assisted with checksum");
3091 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3092 CTLFLAG_RD, &rxq->vlan_extraction,
3093 "# of times hardware extracted 802.1Q tag");
3095 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3101 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3105 #if defined(INET) || defined(INET6)
3107 tcp_lro_free(&rxq->lro);
3108 rxq->lro.ifp = NULL;
3112 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3114 bzero(rxq, sizeof(*rxq));
3121 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3122 int intr_idx, int idx, struct sysctl_oid *oid)
3124 struct port_info *pi = vi->pi;
3126 struct sysctl_oid_list *children;
3129 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3134 children = SYSCTL_CHILDREN(oid);
3136 snprintf(name, sizeof(name), "%d", idx);
3137 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3139 children = SYSCTL_CHILDREN(oid);
3141 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3142 &ofld_rxq->iq.ba, "bus address of descriptor ring");
3143 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3144 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3145 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3146 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3147 "I", "absolute id of the queue");
3148 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3149 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3150 "I", "SGE context id of the queue");
3151 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3152 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3155 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3161 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3165 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3167 bzero(ofld_rxq, sizeof(*ofld_rxq));
3175 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3176 int idx, struct sysctl_oid *oid)
3179 struct sysctl_oid_list *children;
3180 struct sysctl_ctx_list *ctx;
3183 struct adapter *sc = vi->pi->adapter;
3184 struct netmap_adapter *na = NA(vi->ifp);
3188 len = vi->qsize_rxq * IQ_ESIZE;
3189 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3190 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3194 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3195 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3196 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3202 nm_rxq->iq_cidx = 0;
3203 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3204 nm_rxq->iq_gen = F_RSPD_GEN;
3205 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3206 nm_rxq->fl_sidx = na->num_rx_desc;
3207 nm_rxq->intr_idx = intr_idx;
3210 children = SYSCTL_CHILDREN(oid);
3212 snprintf(name, sizeof(name), "%d", idx);
3213 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3215 children = SYSCTL_CHILDREN(oid);
3217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3218 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3219 "I", "absolute id of the queue");
3220 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3221 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3222 "I", "SGE context id of the queue");
3223 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3224 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3227 children = SYSCTL_CHILDREN(oid);
3228 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3230 children = SYSCTL_CHILDREN(oid);
3232 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3233 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3234 "I", "SGE context id of the freelist");
3235 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3236 &nm_rxq->fl_cidx, 0, "consumer index");
3237 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3238 &nm_rxq->fl_pidx, 0, "producer index");
3245 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3247 struct adapter *sc = vi->pi->adapter;
3249 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3251 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3258 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3259 struct sysctl_oid *oid)
3263 struct port_info *pi = vi->pi;
3264 struct adapter *sc = pi->adapter;
3265 struct netmap_adapter *na = NA(vi->ifp);
3267 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3269 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3270 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3271 &nm_txq->ba, (void **)&nm_txq->desc);
3275 nm_txq->pidx = nm_txq->cidx = 0;
3276 nm_txq->sidx = na->num_tx_desc;
3278 nm_txq->iqidx = iqidx;
3279 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3280 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3281 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3282 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3284 snprintf(name, sizeof(name), "%d", idx);
3285 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3286 NULL, "netmap tx queue");
3287 children = SYSCTL_CHILDREN(oid);
3289 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3290 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3291 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3292 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3294 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3295 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3302 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3304 struct adapter *sc = vi->pi->adapter;
3306 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3314 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3317 struct fw_eq_ctrl_cmd c;
3318 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3320 bzero(&c, sizeof(c));
3322 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3323 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3324 V_FW_EQ_CTRL_CMD_VFN(0));
3325 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3326 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3327 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3328 c.physeqid_pkd = htobe32(0);
3329 c.fetchszm_to_iqid =
3330 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3331 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3332 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3334 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3335 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3336 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
3337 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3338 c.eqaddr = htobe64(eq->ba);
3340 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3342 device_printf(sc->dev,
3343 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3346 eq->flags |= EQ_ALLOCATED;
3348 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3349 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3350 if (cntxt_id >= sc->sge.neq)
3351 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3352 cntxt_id, sc->sge.neq - 1);
3353 sc->sge.eqmap[cntxt_id] = eq;
3359 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3362 struct fw_eq_eth_cmd c;
3363 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3365 bzero(&c, sizeof(c));
3367 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3368 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3369 V_FW_EQ_ETH_CMD_VFN(0));
3370 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3371 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3372 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3373 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3374 c.fetchszm_to_iqid =
3375 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3376 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3377 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3378 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3379 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3380 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3381 c.eqaddr = htobe64(eq->ba);
3383 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3385 device_printf(vi->dev,
3386 "failed to create Ethernet egress queue: %d\n", rc);
3389 eq->flags |= EQ_ALLOCATED;
3391 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3392 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3393 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3394 if (cntxt_id >= sc->sge.neq)
3395 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3396 cntxt_id, sc->sge.neq - 1);
3397 sc->sge.eqmap[cntxt_id] = eq;
3404 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3407 struct fw_eq_ofld_cmd c;
3408 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3410 bzero(&c, sizeof(c));
3412 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3413 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3414 V_FW_EQ_OFLD_CMD_VFN(0));
3415 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3416 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3417 c.fetchszm_to_iqid =
3418 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3419 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3420 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3422 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3423 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3424 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3425 c.eqaddr = htobe64(eq->ba);
3427 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3429 device_printf(vi->dev,
3430 "failed to create egress queue for TCP offload: %d\n", rc);
3433 eq->flags |= EQ_ALLOCATED;
3435 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3436 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3437 if (cntxt_id >= sc->sge.neq)
3438 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3439 cntxt_id, sc->sge.neq - 1);
3440 sc->sge.eqmap[cntxt_id] = eq;
3447 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3452 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3454 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3455 len = qsize * EQ_ESIZE;
3456 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3457 &eq->ba, (void **)&eq->desc);
3461 eq->pidx = eq->cidx = 0;
3462 eq->equeqidx = eq->dbidx = 0;
3463 eq->doorbells = sc->doorbells;
3465 switch (eq->flags & EQ_TYPEMASK) {
3467 rc = ctrl_eq_alloc(sc, eq);
3471 rc = eth_eq_alloc(sc, vi, eq);
3476 rc = ofld_eq_alloc(sc, vi, eq);
3481 panic("%s: invalid eq type %d.", __func__,
3482 eq->flags & EQ_TYPEMASK);
3485 device_printf(sc->dev,
3486 "failed to allocate egress queue(%d): %d\n",
3487 eq->flags & EQ_TYPEMASK, rc);
3490 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3491 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3492 isset(&eq->doorbells, DOORBELL_WCWR)) {
3493 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3494 uint32_t mask = (1 << s_qpp) - 1;
3495 volatile uint8_t *udb;
3497 udb = sc->udbs_base + UDBS_DB_OFFSET;
3498 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3499 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3500 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3501 clrbit(&eq->doorbells, DOORBELL_WCWR);
3503 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3506 eq->udb = (volatile void *)udb;
3513 free_eq(struct adapter *sc, struct sge_eq *eq)
3517 if (eq->flags & EQ_ALLOCATED) {
3518 switch (eq->flags & EQ_TYPEMASK) {
3520 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3525 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3531 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3537 panic("%s: invalid eq type %d.", __func__,
3538 eq->flags & EQ_TYPEMASK);
3541 device_printf(sc->dev,
3542 "failed to free egress queue (%d): %d\n",
3543 eq->flags & EQ_TYPEMASK, rc);
3546 eq->flags &= ~EQ_ALLOCATED;
3549 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3551 if (mtx_initialized(&eq->eq_lock))
3552 mtx_destroy(&eq->eq_lock);
3554 bzero(eq, sizeof(*eq));
3559 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3560 struct sysctl_oid *oid)
3563 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3564 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3566 rc = alloc_eq(sc, vi, &wrq->eq);
3571 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3572 TAILQ_INIT(&wrq->incomplete_wrs);
3573 STAILQ_INIT(&wrq->wr_list);
3574 wrq->nwr_pending = 0;
3575 wrq->ndesc_needed = 0;
3577 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3578 &wrq->eq.ba, "bus address of descriptor ring");
3579 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3580 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3581 "desc ring size in bytes");
3582 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3583 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3584 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3585 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3588 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3590 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3591 wrq->eq.sidx, "status page index");
3592 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3593 &wrq->tx_wrs_direct, "# of work requests (direct)");
3594 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3595 &wrq->tx_wrs_copied, "# of work requests (copied)");
3596 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3597 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3603 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3607 rc = free_eq(sc, &wrq->eq);
3611 bzero(wrq, sizeof(*wrq));
3616 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3617 struct sysctl_oid *oid)
3620 struct port_info *pi = vi->pi;
3621 struct adapter *sc = pi->adapter;
3622 struct sge_eq *eq = &txq->eq;
3624 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3626 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3629 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3633 rc = alloc_eq(sc, vi, eq);
3635 mp_ring_free(txq->r);
3640 /* Can't fail after this point. */
3643 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3645 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3646 ("eq_base mismatch"));
3647 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3648 ("PF with non-zero eq_base"));
3650 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3652 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3653 if (sc->flags & IS_VF)
3654 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3655 V_TXPKT_INTF(pi->tx_chan));
3657 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3658 V_TXPKT_INTF(pi->tx_chan) |
3659 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3660 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3661 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3663 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3666 snprintf(name, sizeof(name), "%d", idx);
3667 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3669 children = SYSCTL_CHILDREN(oid);
3671 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3672 &eq->ba, "bus address of descriptor ring");
3673 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3674 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3675 "desc ring size in bytes");
3676 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3677 &eq->abs_id, 0, "absolute id of the queue");
3678 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3679 &eq->cntxt_id, 0, "SGE context id of the queue");
3680 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3681 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3683 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3684 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3686 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3687 eq->sidx, "status page index");
3689 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3690 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3691 "traffic class (-1 means none)");
3693 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3694 &txq->txcsum, "# of times hardware assisted with checksum");
3695 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3696 CTLFLAG_RD, &txq->vlan_insertion,
3697 "# of times hardware inserted 802.1Q tag");
3698 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3699 &txq->tso_wrs, "# of TSO work requests");
3700 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3701 &txq->imm_wrs, "# of work requests with immediate data");
3702 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3703 &txq->sgl_wrs, "# of work requests with direct SGL");
3704 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3705 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3706 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3707 CTLFLAG_RD, &txq->txpkts0_wrs,
3708 "# of txpkts (type 0) work requests");
3709 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3710 CTLFLAG_RD, &txq->txpkts1_wrs,
3711 "# of txpkts (type 1) work requests");
3712 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3713 CTLFLAG_RD, &txq->txpkts0_pkts,
3714 "# of frames tx'd using type0 txpkts work requests");
3715 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3716 CTLFLAG_RD, &txq->txpkts1_pkts,
3717 "# of frames tx'd using type1 txpkts work requests");
3719 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3720 CTLFLAG_RD, &txq->r->enqueues,
3721 "# of enqueues to the mp_ring for this queue");
3722 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3723 CTLFLAG_RD, &txq->r->drops,
3724 "# of drops in the mp_ring for this queue");
3725 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3726 CTLFLAG_RD, &txq->r->starts,
3727 "# of normal consumer starts in the mp_ring for this queue");
3728 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3729 CTLFLAG_RD, &txq->r->stalls,
3730 "# of consumer stalls in the mp_ring for this queue");
3731 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3732 CTLFLAG_RD, &txq->r->restarts,
3733 "# of consumer restarts in the mp_ring for this queue");
3734 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3735 CTLFLAG_RD, &txq->r->abdications,
3736 "# of consumer abdications in the mp_ring for this queue");
3742 free_txq(struct vi_info *vi, struct sge_txq *txq)
3745 struct adapter *sc = vi->pi->adapter;
3746 struct sge_eq *eq = &txq->eq;
3748 rc = free_eq(sc, eq);
3752 sglist_free(txq->gl);
3753 free(txq->sdesc, M_CXGBE);
3754 mp_ring_free(txq->r);
3756 bzero(txq, sizeof(*txq));
3761 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3763 bus_addr_t *ba = arg;
3766 ("%s meant for single segment mappings only.", __func__));
3768 *ba = error ? 0 : segs->ds_addr;
3772 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3776 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3780 v = fl->dbval | V_PIDX(n);
3782 *fl->udb = htole32(v);
3784 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3785 IDXINCR(fl->dbidx, n, fl->sidx);
3789 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
3790 * recycled do not count towards this allocation budget.
3792 * Returns non-zero to indicate that this freelist should be added to the list
3793 * of starving freelists.
3796 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3799 struct fl_sdesc *sd;
3802 struct cluster_layout *cll;
3803 struct sw_zone_info *swz;
3804 struct cluster_metadata *clm;
3806 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3808 FL_LOCK_ASSERT_OWNED(fl);
3811 * We always stop at the beginning of the hardware descriptor that's just
3812 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3813 * which would mean an empty freelist to the chip.
3815 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3816 if (fl->pidx == max_pidx * 8)
3819 d = &fl->desc[fl->pidx];
3820 sd = &fl->sdesc[fl->pidx];
3821 cll = &fl->cll_def; /* default layout */
3822 swz = &sc->sge.sw_zone_info[cll->zidx];
3826 if (sd->cl != NULL) {
3828 if (sd->nmbuf == 0) {
3830 * Fast recycle without involving any atomics on
3831 * the cluster's metadata (if the cluster has
3832 * metadata). This happens when all frames
3833 * received in the cluster were small enough to
3834 * fit within a single mbuf each.
3836 fl->cl_fast_recycled++;
3838 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3840 MPASS(clm->refcount == 1);
3846 * Cluster is guaranteed to have metadata. Clusters
3847 * without metadata always take the fast recycle path
3848 * when they're recycled.
3850 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3853 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3855 counter_u64_add(extfree_rels, 1);
3858 sd->cl = NULL; /* gave up my reference */
3860 MPASS(sd->cl == NULL);
3862 cl = uma_zalloc(swz->zone, M_NOWAIT);
3863 if (__predict_false(cl == NULL)) {
3864 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3865 fl->cll_def.zidx == fl->cll_alt.zidx)
3868 /* fall back to the safe zone */
3870 swz = &sc->sge.sw_zone_info[cll->zidx];
3876 pa = pmap_kextract((vm_offset_t)cl);
3880 *d = htobe64(pa | cll->hwidx);
3881 clm = cl_metadata(sc, fl, cll, cl);
3893 if (__predict_false(++fl->pidx % 8 == 0)) {
3894 uint16_t pidx = fl->pidx / 8;
3896 if (__predict_false(pidx == fl->sidx)) {
3902 if (pidx == max_pidx)
3905 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3910 if (fl->pidx / 8 != fl->dbidx)
3913 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3917 * Attempt to refill all starving freelists.
3920 refill_sfl(void *arg)
3922 struct adapter *sc = arg;
3923 struct sge_fl *fl, *fl_temp;
3925 mtx_assert(&sc->sfl_lock, MA_OWNED);
3926 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3928 refill_fl(sc, fl, 64);
3929 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3930 TAILQ_REMOVE(&sc->sfl, fl, link);
3931 fl->flags &= ~FL_STARVING;
3936 if (!TAILQ_EMPTY(&sc->sfl))
3937 callout_schedule(&sc->sfl_callout, hz / 5);
3941 alloc_fl_sdesc(struct sge_fl *fl)
3944 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3951 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3953 struct fl_sdesc *sd;
3954 struct cluster_metadata *clm;
3955 struct cluster_layout *cll;
3959 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3964 clm = cl_metadata(sc, fl, cll, sd->cl);
3966 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3967 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3968 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3969 counter_u64_add(extfree_rels, 1);
3974 free(fl->sdesc, M_CXGBE);
3979 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3986 rc = sglist_append_mbuf(gl, m);
3987 if (__predict_false(rc != 0)) {
3988 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3989 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3992 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3993 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3994 mbuf_nsegs(m), gl->sg_nseg));
3995 KASSERT(gl->sg_nseg > 0 &&
3996 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3997 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3998 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4002 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4005 txpkt_len16(u_int nsegs, u_int tso)
4011 nsegs--; /* first segment is part of ulptx_sgl */
4012 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4013 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4015 n += sizeof(struct cpl_tx_pkt_lso_core);
4017 return (howmany(n, 16));
4021 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4025 txpkt_vm_len16(u_int nsegs, u_int tso)
4031 nsegs--; /* first segment is part of ulptx_sgl */
4032 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4033 sizeof(struct cpl_tx_pkt_core) +
4034 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4036 n += sizeof(struct cpl_tx_pkt_lso_core);
4038 return (howmany(n, 16));
4042 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4046 txpkts0_len16(u_int nsegs)
4052 nsegs--; /* first segment is part of ulptx_sgl */
4053 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4054 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4055 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4057 return (howmany(n, 16));
4061 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4069 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4071 return (howmany(n, 16));
4075 imm_payload(u_int ndesc)
4079 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4080 sizeof(struct cpl_tx_pkt_core);
4086 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4087 * software descriptor, and advance the pidx. It is guaranteed that enough
4088 * descriptors are available.
4090 * The return value is the # of hardware descriptors used.
4093 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4094 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4096 struct sge_eq *eq = &txq->eq;
4097 struct tx_sdesc *txsd;
4098 struct cpl_tx_pkt_core *cpl;
4099 uint32_t ctrl; /* used in many unrelated places */
4101 int csum_type, len16, ndesc, pktlen, nsegs;
4104 TXQ_LOCK_ASSERT_OWNED(txq);
4106 MPASS(available > 0 && available < eq->sidx);
4108 len16 = mbuf_len16(m0);
4109 nsegs = mbuf_nsegs(m0);
4110 pktlen = m0->m_pkthdr.len;
4111 ctrl = sizeof(struct cpl_tx_pkt_core);
4113 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4114 ndesc = howmany(len16, EQ_ESIZE / 16);
4115 MPASS(ndesc <= available);
4117 /* Firmware work request header */
4118 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4119 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4120 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4122 ctrl = V_FW_WR_LEN16(len16);
4123 wr->equiq_to_len16 = htobe32(ctrl);
4128 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4129 * vlantci is ignored unless the ethtype is 0x8100, so it's
4130 * simpler to always copy it rather than making it
4131 * conditional. Also, it seems that we do not have to set
4132 * vlantci or fake the ethtype when doing VLAN tag insertion.
4134 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4137 if (needs_tso(m0)) {
4138 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4140 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4141 m0->m_pkthdr.l4hlen > 0,
4142 ("%s: mbuf %p needs TSO but missing header lengths",
4145 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4146 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4147 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4148 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4149 ctrl |= V_LSO_ETHHDR_LEN(1);
4150 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4153 lso->lso_ctrl = htobe32(ctrl);
4154 lso->ipid_ofst = htobe16(0);
4155 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4156 lso->seqno_offset = htobe32(0);
4157 lso->len = htobe32(pktlen);
4159 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4160 csum_type = TX_CSUM_TCPIP6;
4162 csum_type = TX_CSUM_TCPIP;
4164 cpl = (void *)(lso + 1);
4168 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4169 csum_type = TX_CSUM_TCPIP;
4170 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4171 csum_type = TX_CSUM_UDPIP;
4172 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4173 csum_type = TX_CSUM_TCPIP6;
4174 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4175 csum_type = TX_CSUM_UDPIP6;
4177 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4179 * XXX: The firmware appears to stomp on the
4180 * fragment/flags field of the IP header when
4181 * using TX_CSUM_IP. Fall back to doing
4182 * software checksums.
4190 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4191 offsetof(struct ip, ip_sum));
4192 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4193 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4194 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4198 cpl = (void *)(wr + 1);
4201 /* Checksum offload */
4203 if (needs_l3_csum(m0) == 0)
4204 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4205 if (csum_type >= 0) {
4206 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4207 ("%s: mbuf %p needs checksum offload but missing header lengths",
4210 if (chip_id(sc) <= CHELSIO_T5) {
4211 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4214 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4217 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4218 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4220 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4221 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4222 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4223 txq->txcsum++; /* some hardware assistance provided */
4225 /* VLAN tag insertion */
4226 if (needs_vlan_insertion(m0)) {
4227 ctrl1 |= F_TXPKT_VLAN_VLD |
4228 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4229 txq->vlan_insertion++;
4233 cpl->ctrl0 = txq->cpl_ctrl0;
4235 cpl->len = htobe16(pktlen);
4236 cpl->ctrl1 = htobe64(ctrl1);
4239 dst = (void *)(cpl + 1);
4242 * A packet using TSO will use up an entire descriptor for the
4243 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4244 * If this descriptor is the last descriptor in the ring, wrap
4245 * around to the front of the ring explicitly for the start of
4248 if (dst == (void *)&eq->desc[eq->sidx]) {
4249 dst = (void *)&eq->desc[0];
4250 write_gl_to_txd(txq, m0, &dst, 0);
4252 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4257 txsd = &txq->sdesc[eq->pidx];
4259 txsd->desc_used = ndesc;
4265 * Write a txpkt WR for this packet to the hardware descriptors, update the
4266 * software descriptor, and advance the pidx. It is guaranteed that enough
4267 * descriptors are available.
4269 * The return value is the # of hardware descriptors used.
4272 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4273 struct mbuf *m0, u_int available)
4275 struct sge_eq *eq = &txq->eq;
4276 struct tx_sdesc *txsd;
4277 struct cpl_tx_pkt_core *cpl;
4278 uint32_t ctrl; /* used in many unrelated places */
4280 int len16, ndesc, pktlen, nsegs;
4283 TXQ_LOCK_ASSERT_OWNED(txq);
4285 MPASS(available > 0 && available < eq->sidx);
4287 len16 = mbuf_len16(m0);
4288 nsegs = mbuf_nsegs(m0);
4289 pktlen = m0->m_pkthdr.len;
4290 ctrl = sizeof(struct cpl_tx_pkt_core);
4292 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4293 else if (pktlen <= imm_payload(2) && available >= 2) {
4294 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4296 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4297 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4300 ndesc = howmany(len16, EQ_ESIZE / 16);
4301 MPASS(ndesc <= available);
4303 /* Firmware work request header */
4304 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4305 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4306 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4308 ctrl = V_FW_WR_LEN16(len16);
4309 wr->equiq_to_len16 = htobe32(ctrl);
4312 if (needs_tso(m0)) {
4313 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4315 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4316 m0->m_pkthdr.l4hlen > 0,
4317 ("%s: mbuf %p needs TSO but missing header lengths",
4320 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4321 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4322 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4323 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4324 ctrl |= V_LSO_ETHHDR_LEN(1);
4325 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4328 lso->lso_ctrl = htobe32(ctrl);
4329 lso->ipid_ofst = htobe16(0);
4330 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4331 lso->seqno_offset = htobe32(0);
4332 lso->len = htobe32(pktlen);
4334 cpl = (void *)(lso + 1);
4338 cpl = (void *)(wr + 1);
4340 /* Checksum offload */
4342 if (needs_l3_csum(m0) == 0)
4343 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4344 if (needs_l4_csum(m0) == 0)
4345 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4346 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4347 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4348 txq->txcsum++; /* some hardware assistance provided */
4350 /* VLAN tag insertion */
4351 if (needs_vlan_insertion(m0)) {
4352 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4353 txq->vlan_insertion++;
4357 cpl->ctrl0 = txq->cpl_ctrl0;
4359 cpl->len = htobe16(pktlen);
4360 cpl->ctrl1 = htobe64(ctrl1);
4363 dst = (void *)(cpl + 1);
4366 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4371 for (m = m0; m != NULL; m = m->m_next) {
4372 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4378 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4385 txsd = &txq->sdesc[eq->pidx];
4387 txsd->desc_used = ndesc;
4393 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4395 u_int needed, nsegs1, nsegs2, l1, l2;
4397 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4400 nsegs1 = mbuf_nsegs(m);
4401 nsegs2 = mbuf_nsegs(n);
4402 if (nsegs1 + nsegs2 == 2) {
4404 l1 = l2 = txpkts1_len16();
4407 l1 = txpkts0_len16(nsegs1);
4408 l2 = txpkts0_len16(nsegs2);
4410 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4411 needed = howmany(txp->len16, EQ_ESIZE / 16);
4412 if (needed > SGE_MAX_WR_NDESC || needed > available)
4415 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4416 if (txp->plen > 65535)
4420 set_mbuf_len16(m, l1);
4421 set_mbuf_len16(n, l2);
4427 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4429 u_int plen, len16, needed, nsegs;
4431 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4433 nsegs = mbuf_nsegs(m);
4434 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4437 plen = txp->plen + m->m_pkthdr.len;
4441 if (txp->wr_type == 0)
4442 len16 = txpkts0_len16(nsegs);
4444 len16 = txpkts1_len16();
4445 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4446 if (needed > SGE_MAX_WR_NDESC || needed > available)
4451 txp->len16 += len16;
4452 set_mbuf_len16(m, len16);
4458 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4459 * the software descriptor, and advance the pidx. It is guaranteed that enough
4460 * descriptors are available.
4462 * The return value is the # of hardware descriptors used.
4465 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4466 struct mbuf *m0, const struct txpkts *txp, u_int available)
4468 struct sge_eq *eq = &txq->eq;
4469 struct tx_sdesc *txsd;
4470 struct cpl_tx_pkt_core *cpl;
4473 int ndesc, checkwrap;
4477 TXQ_LOCK_ASSERT_OWNED(txq);
4478 MPASS(txp->npkt > 0);
4479 MPASS(txp->plen < 65536);
4481 MPASS(m0->m_nextpkt != NULL);
4482 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4483 MPASS(available > 0 && available < eq->sidx);
4485 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4486 MPASS(ndesc <= available);
4488 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4489 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4490 ctrl = V_FW_WR_LEN16(txp->len16);
4491 wr->equiq_to_len16 = htobe32(ctrl);
4492 wr->plen = htobe16(txp->plen);
4493 wr->npkt = txp->npkt;
4495 wr->type = txp->wr_type;
4499 * At this point we are 16B into a hardware descriptor. If checkwrap is
4500 * set then we know the WR is going to wrap around somewhere. We'll
4501 * check for that at appropriate points.
4503 checkwrap = eq->sidx - ndesc < eq->pidx;
4504 for (m = m0; m != NULL; m = m->m_nextpkt) {
4505 if (txp->wr_type == 0) {
4506 struct ulp_txpkt *ulpmc;
4507 struct ulptx_idata *ulpsc;
4509 /* ULP master command */
4511 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4512 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4513 ulpmc->len = htobe32(mbuf_len16(m));
4515 /* ULP subcommand */
4516 ulpsc = (void *)(ulpmc + 1);
4517 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4519 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4521 cpl = (void *)(ulpsc + 1);
4523 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4524 cpl = (void *)&eq->desc[0];
4525 txq->txpkts0_pkts += txp->npkt;
4529 txq->txpkts1_pkts += txp->npkt;
4533 /* Checksum offload */
4535 if (needs_l3_csum(m) == 0)
4536 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4537 if (needs_l4_csum(m) == 0)
4538 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4539 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4540 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4541 txq->txcsum++; /* some hardware assistance provided */
4543 /* VLAN tag insertion */
4544 if (needs_vlan_insertion(m)) {
4545 ctrl1 |= F_TXPKT_VLAN_VLD |
4546 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4547 txq->vlan_insertion++;
4551 cpl->ctrl0 = txq->cpl_ctrl0;
4553 cpl->len = htobe16(m->m_pkthdr.len);
4554 cpl->ctrl1 = htobe64(ctrl1);
4558 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4559 flitp = (void *)&eq->desc[0];
4561 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4565 txsd = &txq->sdesc[eq->pidx];
4567 txsd->desc_used = ndesc;
4573 * If the SGL ends on an address that is not 16 byte aligned, this function will
4574 * add a 0 filled flit at the end.
4577 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4579 struct sge_eq *eq = &txq->eq;
4580 struct sglist *gl = txq->gl;
4581 struct sglist_seg *seg;
4582 __be64 *flitp, *wrap;
4583 struct ulptx_sgl *usgl;
4584 int i, nflits, nsegs;
4586 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4587 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4588 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4589 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4592 nsegs = gl->sg_nseg;
4595 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4596 flitp = (__be64 *)(*to);
4597 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4598 seg = &gl->sg_segs[0];
4599 usgl = (void *)flitp;
4602 * We start at a 16 byte boundary somewhere inside the tx descriptor
4603 * ring, so we're at least 16 bytes away from the status page. There is
4604 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4607 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4608 V_ULPTX_NSGE(nsegs));
4609 usgl->len0 = htobe32(seg->ss_len);
4610 usgl->addr0 = htobe64(seg->ss_paddr);
4613 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4615 /* Won't wrap around at all */
4617 for (i = 0; i < nsegs - 1; i++, seg++) {
4618 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4619 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4622 usgl->sge[i / 2].len[1] = htobe32(0);
4626 /* Will wrap somewhere in the rest of the SGL */
4628 /* 2 flits already written, write the rest flit by flit */
4629 flitp = (void *)(usgl + 1);
4630 for (i = 0; i < nflits - 2; i++) {
4632 flitp = (void *)eq->desc;
4633 *flitp++ = get_flit(seg, nsegs - 1, i);
4638 MPASS(((uintptr_t)flitp) & 0xf);
4642 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4643 if (__predict_false(flitp == wrap))
4644 *to = (void *)eq->desc;
4646 *to = (void *)flitp;
4650 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4653 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4654 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4656 if (__predict_true((uintptr_t)(*to) + len <=
4657 (uintptr_t)&eq->desc[eq->sidx])) {
4658 bcopy(from, *to, len);
4661 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4663 bcopy(from, *to, portion);
4665 portion = len - portion; /* remaining */
4666 bcopy(from, (void *)eq->desc, portion);
4667 (*to) = (caddr_t)eq->desc + portion;
4672 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4680 clrbit(&db, DOORBELL_WCWR);
4683 switch (ffs(db) - 1) {
4685 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4688 case DOORBELL_WCWR: {
4689 volatile uint64_t *dst, *src;
4693 * Queues whose 128B doorbell segment fits in the page do not
4694 * use relative qid (udb_qid is always 0). Only queues with
4695 * doorbell segments can do WCWR.
4697 KASSERT(eq->udb_qid == 0 && n == 1,
4698 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4699 __func__, eq->doorbells, n, eq->dbidx, eq));
4701 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4704 src = (void *)&eq->desc[i];
4705 while (src != (void *)&eq->desc[i + 1])
4711 case DOORBELL_UDBWC:
4712 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4717 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4718 V_QID(eq->cntxt_id) | V_PIDX(n));
4722 IDXINCR(eq->dbidx, n, eq->sidx);
4726 reclaimable_tx_desc(struct sge_eq *eq)
4730 hw_cidx = read_hw_cidx(eq);
4731 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4735 total_available_tx_desc(struct sge_eq *eq)
4737 uint16_t hw_cidx, pidx;
4739 hw_cidx = read_hw_cidx(eq);
4742 if (pidx == hw_cidx)
4743 return (eq->sidx - 1);
4745 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4748 static inline uint16_t
4749 read_hw_cidx(struct sge_eq *eq)
4751 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4752 uint16_t cidx = spg->cidx; /* stable snapshot */
4754 return (be16toh(cidx));
4758 * Reclaim 'n' descriptors approximately.
4761 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4763 struct tx_sdesc *txsd;
4764 struct sge_eq *eq = &txq->eq;
4765 u_int can_reclaim, reclaimed;
4767 TXQ_LOCK_ASSERT_OWNED(txq);
4771 can_reclaim = reclaimable_tx_desc(eq);
4772 while (can_reclaim && reclaimed < n) {
4774 struct mbuf *m, *nextpkt;
4776 txsd = &txq->sdesc[eq->cidx];
4777 ndesc = txsd->desc_used;
4779 /* Firmware doesn't return "partial" credits. */
4780 KASSERT(can_reclaim >= ndesc,
4781 ("%s: unexpected number of credits: %d, %d",
4782 __func__, can_reclaim, ndesc));
4784 for (m = txsd->m; m != NULL; m = nextpkt) {
4785 nextpkt = m->m_nextpkt;
4786 m->m_nextpkt = NULL;
4790 can_reclaim -= ndesc;
4791 IDXINCR(eq->cidx, ndesc, eq->sidx);
4798 tx_reclaim(void *arg, int n)
4800 struct sge_txq *txq = arg;
4801 struct sge_eq *eq = &txq->eq;
4804 if (TXQ_TRYLOCK(txq) == 0)
4806 n = reclaim_tx_descs(txq, 32);
4807 if (eq->cidx == eq->pidx)
4808 eq->equeqidx = eq->pidx;
4814 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4816 int i = (idx / 3) * 2;
4822 rc = htobe32(segs[i].ss_len);
4824 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4829 return (htobe64(segs[i].ss_paddr));
4831 return (htobe64(segs[i + 1].ss_paddr));
4838 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4840 int8_t zidx, hwidx, idx;
4841 uint16_t region1, region3;
4842 int spare, spare_needed, n;
4843 struct sw_zone_info *swz;
4844 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4847 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4848 * large enough for the max payload and cluster metadata. Otherwise
4849 * settle for the largest bufsize that leaves enough room in the cluster
4852 * Without buffer packing: Look for the smallest zone which has a
4853 * bufsize large enough for the max payload. Settle for the largest
4854 * bufsize available if there's nothing big enough for max payload.
4856 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4857 swz = &sc->sge.sw_zone_info[0];
4859 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4860 if (swz->size > largest_rx_cluster) {
4861 if (__predict_true(hwidx != -1))
4865 * This is a misconfiguration. largest_rx_cluster is
4866 * preventing us from finding a refill source. See
4867 * dev.t5nex.<n>.buffer_sizes to figure out why.
4869 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4870 " refill source for fl %p (dma %u). Ignored.\n",
4871 largest_rx_cluster, fl, maxp);
4873 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4874 hwb = &hwb_list[idx];
4875 spare = swz->size - hwb->size;
4876 if (spare < spare_needed)
4879 hwidx = idx; /* best option so far */
4880 if (hwb->size >= maxp) {
4882 if ((fl->flags & FL_BUF_PACKING) == 0)
4883 goto done; /* stop looking (not packing) */
4885 if (swz->size >= safest_rx_cluster)
4886 goto done; /* stop looking (packing) */
4888 break; /* keep looking, next zone */
4892 /* A usable hwidx has been located. */
4894 hwb = &hwb_list[hwidx];
4896 swz = &sc->sge.sw_zone_info[zidx];
4898 region3 = swz->size - hwb->size;
4901 * Stay within this zone and see if there is a better match when mbuf
4902 * inlining is allowed. Remember that the hwidx's are sorted in
4903 * decreasing order of size (so in increasing order of spare area).
4905 for (idx = hwidx; idx != -1; idx = hwb->next) {
4906 hwb = &hwb_list[idx];
4907 spare = swz->size - hwb->size;
4909 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4913 * Do not inline mbufs if doing so would violate the pad/pack
4914 * boundary alignment requirement.
4916 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4918 if (fl->flags & FL_BUF_PACKING &&
4919 (MSIZE % sc->params.sge.pack_boundary) != 0)
4922 if (spare < CL_METADATA_SIZE + MSIZE)
4924 n = (spare - CL_METADATA_SIZE) / MSIZE;
4925 if (n > howmany(hwb->size, maxp))
4929 if (fl->flags & FL_BUF_PACKING) {
4930 region1 = n * MSIZE;
4931 region3 = spare - region1;
4934 region3 = spare - region1;
4939 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4940 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4941 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4942 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4943 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4944 sc->sge.sw_zone_info[zidx].size,
4945 ("%s: bad buffer layout for fl %p, maxp %d. "
4946 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4947 sc->sge.sw_zone_info[zidx].size, region1,
4948 sc->sge.hw_buf_info[hwidx].size, region3));
4949 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4950 KASSERT(region3 >= CL_METADATA_SIZE,
4951 ("%s: no room for metadata. fl %p, maxp %d; "
4952 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4953 sc->sge.sw_zone_info[zidx].size, region1,
4954 sc->sge.hw_buf_info[hwidx].size, region3));
4955 KASSERT(region1 % MSIZE == 0,
4956 ("%s: bad mbuf region for fl %p, maxp %d. "
4957 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4958 sc->sge.sw_zone_info[zidx].size, region1,
4959 sc->sge.hw_buf_info[hwidx].size, region3));
4962 fl->cll_def.zidx = zidx;
4963 fl->cll_def.hwidx = hwidx;
4964 fl->cll_def.region1 = region1;
4965 fl->cll_def.region3 = region3;
4969 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4971 struct sge *s = &sc->sge;
4972 struct hw_buf_info *hwb;
4973 struct sw_zone_info *swz;
4977 if (fl->flags & FL_BUF_PACKING)
4978 hwidx = s->safe_hwidx2; /* with room for metadata */
4979 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4980 hwidx = s->safe_hwidx2;
4981 hwb = &s->hw_buf_info[hwidx];
4982 swz = &s->sw_zone_info[hwb->zidx];
4983 spare = swz->size - hwb->size;
4985 /* no good if there isn't room for an mbuf as well */
4986 if (spare < CL_METADATA_SIZE + MSIZE)
4987 hwidx = s->safe_hwidx1;
4989 hwidx = s->safe_hwidx1;
4992 /* No fallback source */
4993 fl->cll_alt.hwidx = -1;
4994 fl->cll_alt.zidx = -1;
4999 hwb = &s->hw_buf_info[hwidx];
5000 swz = &s->sw_zone_info[hwb->zidx];
5001 spare = swz->size - hwb->size;
5002 fl->cll_alt.hwidx = hwidx;
5003 fl->cll_alt.zidx = hwb->zidx;
5004 if (allow_mbufs_in_cluster &&
5005 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5006 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5008 fl->cll_alt.region1 = 0;
5009 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5013 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5015 mtx_lock(&sc->sfl_lock);
5017 if ((fl->flags & FL_DOOMED) == 0) {
5018 fl->flags |= FL_STARVING;
5019 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5020 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5023 mtx_unlock(&sc->sfl_lock);
5027 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5029 struct sge_wrq *wrq = (void *)eq;
5031 atomic_readandclear_int(&eq->equiq);
5032 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5036 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5038 struct sge_txq *txq = (void *)eq;
5040 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5042 atomic_readandclear_int(&eq->equiq);
5043 mp_ring_check_drainage(txq->r, 0);
5044 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5048 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5051 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5052 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5053 struct adapter *sc = iq->adapter;
5054 struct sge *s = &sc->sge;
5056 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5057 &handle_wrq_egr_update, &handle_eth_egr_update,
5058 &handle_wrq_egr_update};
5060 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5063 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5064 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5069 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5070 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5071 offsetof(struct cpl_fw6_msg, data));
5074 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5076 struct adapter *sc = iq->adapter;
5077 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5079 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5082 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5083 const struct rss_header *rss2;
5085 rss2 = (const struct rss_header *)&cpl->data[0];
5086 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5089 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5093 * t4_handle_wrerr_rpl - process a FW work request error message
5094 * @adap: the adapter
5095 * @rpl: start of the FW message
5098 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5100 u8 opcode = *(const u8 *)rpl;
5101 const struct fw_error_cmd *e = (const void *)rpl;
5104 if (opcode != FW_ERROR_CMD) {
5106 "%s: Received WRERR_RPL message with opcode %#x\n",
5107 device_get_nameunit(adap->dev), opcode);
5110 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5111 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5113 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5114 case FW_ERROR_TYPE_EXCEPTION:
5115 log(LOG_ERR, "exception info:\n");
5116 for (i = 0; i < nitems(e->u.exception.info); i++)
5117 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5118 be32toh(e->u.exception.info[i]));
5121 case FW_ERROR_TYPE_HWMODULE:
5122 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5123 be32toh(e->u.hwmodule.regaddr),
5124 be32toh(e->u.hwmodule.regval));
5126 case FW_ERROR_TYPE_WR:
5127 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5128 be16toh(e->u.wr.cidx),
5129 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5130 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5131 be32toh(e->u.wr.eqid));
5132 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5133 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5137 case FW_ERROR_TYPE_ACL:
5138 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5139 be16toh(e->u.acl.cidx),
5140 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5141 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5142 be32toh(e->u.acl.eqid),
5143 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5145 for (i = 0; i < nitems(e->u.acl.val); i++)
5146 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5150 log(LOG_ERR, "type %#x\n",
5151 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5158 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5160 uint16_t *id = arg1;
5163 return sysctl_handle_int(oidp, &i, 0, req);
5167 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5169 struct sge *s = arg1;
5170 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5171 struct sw_zone_info *swz = &s->sw_zone_info[0];
5176 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5177 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5178 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5183 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5187 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5193 sysctl_tc(SYSCTL_HANDLER_ARGS)
5195 struct vi_info *vi = arg1;
5196 struct port_info *pi;
5198 struct sge_txq *txq;
5199 struct tx_sched_class *tc;
5200 int qidx = arg2, rc, tc_idx;
5201 uint32_t fw_queue, fw_class;
5203 MPASS(qidx >= 0 && qidx < vi->ntxq);
5206 txq = &sc->sge.txq[vi->first_txq + qidx];
5208 tc_idx = txq->tc_idx;
5209 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5210 if (rc != 0 || req->newptr == NULL)
5213 /* Note that -1 is legitimate input (it means unbind). */
5214 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5217 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5221 if (tc_idx == txq->tc_idx) {
5222 rc = 0; /* No change, nothing to do. */
5226 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5227 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5228 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5231 fw_class = 0xffffffff; /* Unbind. */
5234 * Bind to a different class. Ethernet txq's are only allowed
5235 * to bind to cl-rl mode-class for now. XXX: too restrictive.
5237 tc = &pi->tc[tc_idx];
5238 if (tc->flags & TX_SC_OK &&
5239 tc->params.level == SCHED_CLASS_LEVEL_CL_RL &&
5240 tc->params.mode == SCHED_CLASS_MODE_CLASS) {
5241 /* Ok to proceed. */
5244 rc = tc->flags & TX_SC_OK ? EBUSY : ENXIO;
5249 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5251 if (txq->tc_idx != -1) {
5252 tc = &pi->tc[txq->tc_idx];
5253 MPASS(tc->refcount > 0);
5257 tc = &pi->tc[tc_idx];
5260 txq->tc_idx = tc_idx;
5263 end_synchronized_op(sc, 0);