2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
49 #include <sys/sglist.h>
50 #include <sys/sysctl.h>
52 #include <sys/socketvar.h>
53 #include <sys/counter.h>
55 #include <net/ethernet.h>
57 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/ip6.h>
61 #include <netinet/tcp.h>
62 #include <netinet/udp.h>
63 #include <machine/in_cksum.h>
64 #include <machine/md_var.h>
68 #include <machine/bus.h>
69 #include <sys/selinfo.h>
70 #include <net/if_var.h>
71 #include <net/netmap.h>
72 #include <dev/netmap/netmap_kern.h>
75 #include "common/common.h"
76 #include "common/t4_regs.h"
77 #include "common/t4_regs_values.h"
78 #include "common/t4_msg.h"
80 #include "t4_mp_ring.h"
82 #ifdef T4_PKT_TIMESTAMP
83 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
85 #define RX_COPY_THRESHOLD MINCLSIZE
88 /* Internal mbuf flags stored in PH_loc.eight[1]. */
90 #define MC_RAW_WR 0x02
94 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
95 * 0-7 are valid values.
97 static int fl_pktshift = 0;
98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
99 "payload DMA offset in rx buffer (bytes)");
102 * Pad ethernet payload up to this boundary.
103 * -1: driver should figure out a good value.
104 * 0: disable padding.
105 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
109 "payload pad boundary (bytes)");
112 * Status page length.
113 * -1: driver should figure out a good value.
114 * 64 or 128 are the only other valid values.
116 static int spg_len = -1;
117 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
118 "status page size (bytes)");
122 * -1: no congestion feedback (not recommended).
123 * 0: backpressure the channel instead of dropping packets right away.
124 * 1: no backpressure, drop packets for the congested queue immediately.
126 static int cong_drop = 0;
127 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
128 "Congestion control for RX queues (0 = backpressure, 1 = drop");
131 * Deliver multiple frames in the same free list buffer if they fit.
132 * -1: let the driver decide whether to enable buffer packing or not.
133 * 0: disable buffer packing.
134 * 1: enable buffer packing.
136 static int buffer_packing = -1;
137 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
138 0, "Enable buffer packing");
141 * Start next frame in a packed buffer at this boundary.
142 * -1: driver should figure out a good value.
143 * T4: driver will ignore this and use the same value as fl_pad above.
144 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
146 static int fl_pack = -1;
147 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
148 "payload pack boundary (bytes)");
151 * Largest rx cluster size that the driver is allowed to allocate.
153 static int largest_rx_cluster = MJUM16BYTES;
154 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
155 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
158 * Size of cluster allocation that's most likely to succeed. The driver will
159 * fall back to this size if it fails to allocate clusters larger than this.
161 static int safest_rx_cluster = PAGE_SIZE;
162 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
163 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
167 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
168 * for rewriting. -1 and 0-3 are all valid values.
169 * -1: hardware should leave the TCP timestamps alone.
175 static int tsclk = -1;
176 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
177 "Control TCP timestamp rewriting when using pacing");
179 static int eo_max_backlog = 1024 * 1024;
180 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
181 0, "Maximum backlog of ratelimited data per flow");
185 * The interrupt holdoff timers are multiplied by this value on T6+.
186 * 1 and 3-17 (both inclusive) are legal values.
188 static int tscale = 1;
189 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
190 "Interrupt holdoff timer scale on T6+");
193 * Number of LRO entries in the lro_ctrl structure per rx queue.
195 static int lro_entries = TCP_LRO_ENTRIES;
196 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
197 "Number of LRO entries per RX queue");
200 * This enables presorting of frames before they're fed into tcp_lro_rx.
202 static int lro_mbufs = 0;
203 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
204 "Enable presorting of LRO frames");
207 u_int wr_type; /* type 0 or type 1 */
208 u_int npkt; /* # of packets in this work request */
209 u_int plen; /* total payload (sum of all packets) */
210 u_int len16; /* # of 16B pieces used by this work request */
213 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
216 struct sglist_seg seg[TX_SGL_SEGS];
219 static int service_iq(struct sge_iq *, int);
220 static int service_iq_fl(struct sge_iq *, int);
221 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
222 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
224 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
225 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
226 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
228 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
229 bus_addr_t *, void **);
230 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
232 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
234 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
235 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
237 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
238 struct sysctl_oid *, struct sge_fl *);
239 static int alloc_fwq(struct adapter *);
240 static int free_fwq(struct adapter *);
241 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
242 struct sysctl_oid *);
243 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
244 struct sysctl_oid *);
245 static int free_rxq(struct vi_info *, struct sge_rxq *);
247 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
248 struct sysctl_oid *);
249 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
252 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
253 struct sysctl_oid *);
254 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
255 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
256 struct sysctl_oid *);
257 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
259 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
260 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
261 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
262 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
264 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
265 static int free_eq(struct adapter *, struct sge_eq *);
266 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
267 struct sysctl_oid *);
268 static int free_wrq(struct adapter *, struct sge_wrq *);
269 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
270 struct sysctl_oid *);
271 static int free_txq(struct vi_info *, struct sge_txq *);
272 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
273 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
274 static int refill_fl(struct adapter *, struct sge_fl *, int);
275 static void refill_sfl(void *);
276 static int alloc_fl_sdesc(struct sge_fl *);
277 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
278 static int find_refill_source(struct adapter *, int, bool);
279 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
281 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
282 static inline u_int txpkt_len16(u_int, u_int);
283 static inline u_int txpkt_vm_len16(u_int, u_int);
284 static inline u_int txpkts0_len16(u_int);
285 static inline u_int txpkts1_len16(void);
286 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
287 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *,
288 struct fw_eth_tx_pkt_wr *, struct mbuf *, u_int);
289 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
290 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
291 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
292 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
293 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *,
294 struct fw_eth_tx_pkts_wr *, struct mbuf *, const struct txpkts *, u_int);
295 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
296 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
297 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
298 static inline uint16_t read_hw_cidx(struct sge_eq *);
299 static inline u_int reclaimable_tx_desc(struct sge_eq *);
300 static inline u_int total_available_tx_desc(struct sge_eq *);
301 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
302 static void tx_reclaim(void *, int);
303 static __be64 get_flit(struct sglist_seg *, int, int);
304 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
306 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
308 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
309 static void wrq_tx_drain(void *, int);
310 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
312 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
313 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
315 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
316 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
320 static counter_u64_t extfree_refs;
321 static counter_u64_t extfree_rels;
323 an_handler_t t4_an_handler;
324 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
325 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
326 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
327 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
328 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
329 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
330 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
333 t4_register_an_handler(an_handler_t h)
337 MPASS(h == NULL || t4_an_handler == NULL);
339 loc = (uintptr_t *)&t4_an_handler;
340 atomic_store_rel_ptr(loc, (uintptr_t)h);
344 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
348 MPASS(type < nitems(t4_fw_msg_handler));
349 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
351 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
352 * handler dispatch table. Reject any attempt to install a handler for
355 MPASS(type != FW_TYPE_RSSCPL);
356 MPASS(type != FW6_TYPE_RSSCPL);
358 loc = (uintptr_t *)&t4_fw_msg_handler[type];
359 atomic_store_rel_ptr(loc, (uintptr_t)h);
363 t4_register_cpl_handler(int opcode, cpl_handler_t h)
367 MPASS(opcode < nitems(t4_cpl_handler));
368 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
370 loc = (uintptr_t *)&t4_cpl_handler[opcode];
371 atomic_store_rel_ptr(loc, (uintptr_t)h);
375 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
378 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
385 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
387 * The return code for filter-write is put in the CPL cookie so
388 * we have to rely on the hardware tid (is_ftid) to determine
389 * that this is a response to a filter.
391 cookie = CPL_COOKIE_FILTER;
393 cookie = G_COOKIE(cpl->cookie);
395 MPASS(cookie > CPL_COOKIE_RESERVED);
396 MPASS(cookie < nitems(set_tcb_rpl_handlers));
398 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
402 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
405 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
410 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
411 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
415 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
418 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
419 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
422 MPASS(cookie != CPL_COOKIE_RESERVED);
424 return (act_open_rpl_handlers[cookie](iq, rss, m));
428 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
431 struct adapter *sc = iq->adapter;
435 if (is_hashfilter(sc))
436 cookie = CPL_COOKIE_HASHFILTER;
438 cookie = CPL_COOKIE_TOM;
440 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
444 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
446 struct adapter *sc = iq->adapter;
447 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
448 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
452 if (is_etid(sc, tid))
453 cookie = CPL_COOKIE_ETHOFLD;
455 cookie = CPL_COOKIE_TOM;
457 return (fw4_ack_handlers[cookie](iq, rss, m));
461 t4_init_shared_cpl_handlers(void)
464 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
465 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
466 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
467 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
468 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
472 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
476 MPASS(opcode < nitems(t4_cpl_handler));
477 MPASS(cookie > CPL_COOKIE_RESERVED);
478 MPASS(cookie < NUM_CPL_COOKIES);
479 MPASS(t4_cpl_handler[opcode] != NULL);
482 case CPL_SET_TCB_RPL:
483 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
485 case CPL_L2T_WRITE_RPL:
486 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
488 case CPL_ACT_OPEN_RPL:
489 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
491 case CPL_ABORT_RPL_RSS:
492 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
495 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
501 MPASS(h == NULL || *loc == (uintptr_t)NULL);
502 atomic_store_rel_ptr(loc, (uintptr_t)h);
506 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
512 if (fl_pktshift < 0 || fl_pktshift > 7) {
513 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
514 " using 0 instead.\n", fl_pktshift);
518 if (spg_len != 64 && spg_len != 128) {
521 #if defined(__i386__) || defined(__amd64__)
522 len = cpu_clflush_line_size > 64 ? 128 : 64;
527 printf("Invalid hw.cxgbe.spg_len value (%d),"
528 " using %d instead.\n", spg_len, len);
533 if (cong_drop < -1 || cong_drop > 1) {
534 printf("Invalid hw.cxgbe.cong_drop value (%d),"
535 " using 0 instead.\n", cong_drop);
539 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
540 printf("Invalid hw.cxgbe.tscale value (%d),"
541 " using 1 instead.\n", tscale);
545 extfree_refs = counter_u64_alloc(M_WAITOK);
546 extfree_rels = counter_u64_alloc(M_WAITOK);
547 counter_u64_zero(extfree_refs);
548 counter_u64_zero(extfree_rels);
550 t4_init_shared_cpl_handlers();
551 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
552 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
553 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
555 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
558 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
559 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
563 t4_sge_modunload(void)
566 counter_u64_free(extfree_refs);
567 counter_u64_free(extfree_rels);
571 t4_sge_extfree_refs(void)
575 rels = counter_u64_fetch(extfree_rels);
576 refs = counter_u64_fetch(extfree_refs);
578 return (refs - rels);
582 #define MAX_PACK_BOUNDARY 512
585 setup_pad_and_pack_boundaries(struct adapter *sc)
588 int pad, pack, pad_shift;
590 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
591 X_INGPADBOUNDARY_SHIFT;
593 if (fl_pad < (1 << pad_shift) ||
594 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
597 * If there is any chance that we might use buffer packing and
598 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
599 * it to the minimum allowed in all other cases.
601 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
604 * For fl_pad = 0 we'll still write a reasonable value to the
605 * register but all the freelists will opt out of padding.
606 * We'll complain here only if the user tried to set it to a
607 * value greater than 0 that was invalid.
610 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
611 " (%d), using %d instead.\n", fl_pad, pad);
614 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
615 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
616 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
619 if (fl_pack != -1 && fl_pack != pad) {
620 /* Complain but carry on. */
621 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
622 " using %d instead.\n", fl_pack, pad);
628 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
629 !powerof2(fl_pack)) {
630 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
631 pack = MAX_PACK_BOUNDARY;
633 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
634 MPASS(powerof2(pack));
642 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
643 " (%d), using %d instead.\n", fl_pack, pack);
646 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
648 v = V_INGPACKBOUNDARY(0);
650 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
652 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
653 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
657 * adap->params.vpd.cclk must be set up before this is called.
660 t4_tweak_chip_settings(struct adapter *sc)
664 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
665 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
666 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
667 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
668 static int sw_buf_sizes[] = {
670 #if MJUMPAGESIZE != MCLBYTES
677 KASSERT(sc->flags & MASTER_PF,
678 ("%s: trying to change chip settings when not master.", __func__));
680 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
681 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
682 V_EGRSTATUSPAGESIZE(spg_len == 128);
683 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
685 setup_pad_and_pack_boundaries(sc);
687 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
688 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
689 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
690 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
691 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
692 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
693 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
694 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
695 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
697 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
698 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
699 reg = A_SGE_FL_BUFFER_SIZE2;
700 for (i = 0; i < nitems(sw_buf_sizes); i++) {
701 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
702 t4_write_reg(sc, reg, sw_buf_sizes[i]);
704 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
705 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
709 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
710 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
711 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
713 KASSERT(intr_timer[0] <= timer_max,
714 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
716 for (i = 1; i < nitems(intr_timer); i++) {
717 KASSERT(intr_timer[i] >= intr_timer[i - 1],
718 ("%s: timers not listed in increasing order (%d)",
721 while (intr_timer[i] > timer_max) {
722 if (i == nitems(intr_timer) - 1) {
723 intr_timer[i] = timer_max;
726 intr_timer[i] += intr_timer[i - 1];
731 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
732 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
733 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
734 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
735 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
736 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
737 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
738 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
739 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
741 if (chip_id(sc) >= CHELSIO_T6) {
742 m = V_TSCALE(M_TSCALE);
746 v = V_TSCALE(tscale - 2);
747 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
749 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
750 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
751 V_WRTHRTHRESH(M_WRTHRTHRESH);
752 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
754 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
756 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
760 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
761 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
762 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
765 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
766 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
767 * may have to deal with is MAXPHYS + 1 page.
769 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
770 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
772 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
773 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
774 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
776 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
778 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
779 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
783 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its
784 * address mut be 16B aligned. If padding is in use the buffer's start and end
785 * need to be aligned to the pad boundary as well. We'll just make sure that
786 * the size is a multiple of the pad boundary here, it is up to the buffer
787 * allocation code to make sure the start of the buffer is aligned.
790 hwsz_ok(struct adapter *sc, int hwsz)
792 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
794 return (hwsz >= 64 && (hwsz & mask) == 0);
798 * XXX: driver really should be able to deal with unexpected settings.
801 t4_read_chip_settings(struct adapter *sc)
803 struct sge *s = &sc->sge;
804 struct sge_params *sp = &sc->params.sge;
807 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
808 static int sw_buf_sizes[] = { /* Sorted by size */
810 #if MJUMPAGESIZE != MCLBYTES
816 struct rx_buf_info *rxb;
820 r = sc->params.sge.sge_control;
822 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
827 * If this changes then every single use of PAGE_SHIFT in the driver
828 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
830 if (sp->page_shift != PAGE_SHIFT) {
831 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
836 rxb = &s->rx_buf_info[0];
837 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
838 rxb->size1 = sw_buf_sizes[i];
839 rxb->zone = m_getzone(rxb->size1);
840 rxb->type = m_gettype(rxb->size1);
844 for (j = 0; j < SGE_FLBUF_SIZES; j++) {
845 int hwsize = sp->sge_fl_buffer_size[j];
847 if (!hwsz_ok(sc, hwsize))
850 /* hwidx for size1 */
851 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
854 /* hwidx for size2 (buffer packing) */
855 if (rxb->size1 - CL_METADATA_SIZE < hwsize)
857 n = rxb->size1 - hwsize - CL_METADATA_SIZE;
861 break; /* stop looking */
863 if (rxb->hwidx2 != -1) {
864 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
865 hwsize - CL_METADATA_SIZE) {
869 } else if (n <= 2 * CL_METADATA_SIZE) {
874 if (rxb->hwidx2 != -1)
875 sc->flags |= BUF_PACKING_OK;
876 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
880 if (sc->flags & IS_VF)
883 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
884 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
886 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
890 m = v = F_TDDPTAGTCB;
891 r = t4_read_reg(sc, A_ULP_RX_CTL);
893 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
897 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
899 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
900 r = t4_read_reg(sc, A_TP_PARA_REG5);
902 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
906 t4_init_tp_params(sc, 1);
908 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
909 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
915 t4_create_dma_tag(struct adapter *sc)
919 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
920 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
921 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
924 device_printf(sc->dev,
925 "failed to create main DMA tag: %d\n", rc);
932 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
933 struct sysctl_oid_list *children)
935 struct sge_params *sp = &sc->params.sge;
937 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
938 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
939 sysctl_bufsizes, "A", "freelist buffer sizes");
941 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
942 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
944 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
945 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
947 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
948 NULL, sp->spg_len, "status page size (bytes)");
950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
951 NULL, cong_drop, "congestion drop setting");
953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
954 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
958 t4_destroy_dma_tag(struct adapter *sc)
961 bus_dma_tag_destroy(sc->dmat);
967 * Allocate and initialize the firmware event queue, control queues, and special
968 * purpose rx queues owned by the adapter.
970 * Returns errno on failure. Resources allocated up to that point may still be
971 * allocated. Caller is responsible for cleanup in case this function fails.
974 t4_setup_adapter_queues(struct adapter *sc)
976 struct sysctl_oid *oid;
977 struct sysctl_oid_list *children;
980 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
982 sysctl_ctx_init(&sc->ctx);
983 sc->flags |= ADAP_SYSCTL_CTX;
986 * Firmware event queue
993 * That's all for the VF driver.
995 if (sc->flags & IS_VF)
998 oid = device_get_sysctl_tree(sc->dev);
999 children = SYSCTL_CHILDREN(oid);
1002 * XXX: General purpose rx queues, one per port.
1006 * Control queues, one per port.
1008 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1009 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1010 for_each_port(sc, i) {
1011 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1013 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1025 t4_teardown_adapter_queues(struct adapter *sc)
1029 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1031 /* Do this before freeing the queue */
1032 if (sc->flags & ADAP_SYSCTL_CTX) {
1033 sysctl_ctx_free(&sc->ctx);
1034 sc->flags &= ~ADAP_SYSCTL_CTX;
1037 if (!(sc->flags & IS_VF)) {
1038 for_each_port(sc, i)
1039 free_wrq(sc, &sc->sge.ctrlq[i]);
1046 /* Maximum payload that can be delivered with a single iq descriptor */
1048 mtu_to_max_payload(struct adapter *sc, int mtu)
1051 /* large enough even when hw VLAN extraction is disabled */
1052 return (sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1053 ETHER_VLAN_ENCAP_LEN + mtu);
1057 t4_setup_vi_queues(struct vi_info *vi)
1059 int rc = 0, i, intr_idx, iqidx;
1060 struct sge_rxq *rxq;
1061 struct sge_txq *txq;
1063 struct sge_ofld_rxq *ofld_rxq;
1065 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1066 struct sge_wrq *ofld_txq;
1070 struct sge_nm_rxq *nm_rxq;
1071 struct sge_nm_txq *nm_txq;
1074 struct port_info *pi = vi->pi;
1075 struct adapter *sc = pi->adapter;
1076 struct ifnet *ifp = vi->ifp;
1077 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1078 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1079 int maxp, mtu = ifp->if_mtu;
1081 /* Interrupt vector to start from (when using multiple vectors) */
1082 intr_idx = vi->first_intr;
1085 saved_idx = intr_idx;
1086 if (ifp->if_capabilities & IFCAP_NETMAP) {
1088 /* netmap is supported with direct interrupts only. */
1089 MPASS(!forwarding_intr_to_fwq(sc));
1092 * We don't have buffers to back the netmap rx queues
1093 * right now so we create the queues in a way that
1094 * doesn't set off any congestion signal in the chip.
1096 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1097 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues");
1098 for_each_nm_rxq(vi, i, nm_rxq) {
1099 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1105 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1106 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues");
1107 for_each_nm_txq(vi, i, nm_txq) {
1108 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1109 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1115 /* Normal rx queues and netmap rx queues share the same interrupts. */
1116 intr_idx = saved_idx;
1120 * Allocate rx queues first because a default iqid is required when
1121 * creating a tx queue.
1123 maxp = mtu_to_max_payload(sc, mtu);
1124 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1125 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues");
1126 for_each_rxq(vi, i, rxq) {
1128 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1130 snprintf(name, sizeof(name), "%s rxq%d-fl",
1131 device_get_nameunit(vi->dev), i);
1132 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1134 rc = alloc_rxq(vi, rxq,
1135 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1141 if (ifp->if_capabilities & IFCAP_NETMAP)
1142 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1145 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1146 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues for offloaded TCP connections");
1147 for_each_ofld_rxq(vi, i, ofld_rxq) {
1149 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1152 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1153 device_get_nameunit(vi->dev), i);
1154 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1156 rc = alloc_ofld_rxq(vi, ofld_rxq,
1157 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1165 * Now the tx queues.
1167 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq",
1168 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues");
1169 for_each_txq(vi, i, txq) {
1170 iqidx = vi->first_rxq + (i % vi->nrxq);
1171 snprintf(name, sizeof(name), "%s txq%d",
1172 device_get_nameunit(vi->dev), i);
1173 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1174 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1176 rc = alloc_txq(vi, txq, i, oid);
1180 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1181 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1182 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues for TOE/ETHOFLD");
1183 for_each_ofld_txq(vi, i, ofld_txq) {
1184 struct sysctl_oid *oid2;
1186 snprintf(name, sizeof(name), "%s ofld_txq%d",
1187 device_get_nameunit(vi->dev), i);
1188 if (vi->nofldrxq > 0) {
1189 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1190 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1191 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id,
1194 iqidx = vi->first_rxq + (i % vi->nrxq);
1195 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1196 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name);
1199 snprintf(name, sizeof(name), "%d", i);
1200 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1201 name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
1203 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1210 t4_teardown_vi_queues(vi);
1219 t4_teardown_vi_queues(struct vi_info *vi)
1222 struct sge_rxq *rxq;
1223 struct sge_txq *txq;
1224 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1225 struct port_info *pi = vi->pi;
1226 struct adapter *sc = pi->adapter;
1227 struct sge_wrq *ofld_txq;
1230 struct sge_ofld_rxq *ofld_rxq;
1233 struct sge_nm_rxq *nm_rxq;
1234 struct sge_nm_txq *nm_txq;
1237 /* Do this before freeing the queues */
1238 if (vi->flags & VI_SYSCTL_CTX) {
1239 sysctl_ctx_free(&vi->ctx);
1240 vi->flags &= ~VI_SYSCTL_CTX;
1244 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1245 for_each_nm_txq(vi, i, nm_txq) {
1246 free_nm_txq(vi, nm_txq);
1249 for_each_nm_rxq(vi, i, nm_rxq) {
1250 free_nm_rxq(vi, nm_rxq);
1256 * Take down all the tx queues first, as they reference the rx queues
1257 * (for egress updates, etc.).
1260 for_each_txq(vi, i, txq) {
1263 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1264 for_each_ofld_txq(vi, i, ofld_txq) {
1265 free_wrq(sc, ofld_txq);
1270 * Then take down the rx queues.
1273 for_each_rxq(vi, i, rxq) {
1277 for_each_ofld_rxq(vi, i, ofld_rxq) {
1278 free_ofld_rxq(vi, ofld_rxq);
1286 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1289 * a) Deals with errors, if any.
1290 * b) Services firmware event queue, which is taking interrupts for all other
1294 t4_intr_all(void *arg)
1296 struct adapter *sc = arg;
1297 struct sge_iq *fwq = &sc->sge.fwq;
1299 MPASS(sc->intr_count == 1);
1301 if (sc->intr_type == INTR_INTX)
1302 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1309 * Interrupt handler for errors (installed directly when multiple interrupts are
1310 * being used, or called by t4_intr_all).
1313 t4_intr_err(void *arg)
1315 struct adapter *sc = arg;
1317 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1319 if (sc->flags & ADAP_ERR)
1322 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1325 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1328 t4_slow_intr_handler(sc, verbose);
1332 * Interrupt handler for iq-only queues. The firmware event queue is the only
1333 * such queue right now.
1336 t4_intr_evt(void *arg)
1338 struct sge_iq *iq = arg;
1340 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1342 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1347 * Interrupt handler for iq+fl queues.
1352 struct sge_iq *iq = arg;
1354 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1355 service_iq_fl(iq, 0);
1356 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1362 * Interrupt handler for netmap rx queues.
1365 t4_nm_intr(void *arg)
1367 struct sge_nm_rxq *nm_rxq = arg;
1369 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1370 service_nm_rxq(nm_rxq);
1371 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1376 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1379 t4_vi_intr(void *arg)
1381 struct irq *irq = arg;
1383 MPASS(irq->nm_rxq != NULL);
1384 t4_nm_intr(irq->nm_rxq);
1386 MPASS(irq->rxq != NULL);
1392 * Deals with interrupts on an iq-only (no freelist) queue.
1395 service_iq(struct sge_iq *iq, int budget)
1398 struct adapter *sc = iq->adapter;
1399 struct iq_desc *d = &iq->desc[iq->cidx];
1400 int ndescs = 0, limit;
1403 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1405 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1406 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1407 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1409 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1410 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1412 limit = budget ? budget : iq->qsize / 16;
1415 * We always come back and check the descriptor ring for new indirect
1416 * interrupts and other responses after running a single handler.
1419 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1423 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1424 lq = be32toh(d->rsp.pldbuflen_qid);
1427 case X_RSPD_TYPE_FLBUF:
1428 panic("%s: data for an iq (%p) with no freelist",
1433 case X_RSPD_TYPE_CPL:
1434 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1435 ("%s: bad opcode %02x.", __func__,
1437 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1440 case X_RSPD_TYPE_INTR:
1442 * There are 1K interrupt-capable queues (qids 0
1443 * through 1023). A response type indicating a
1444 * forwarded interrupt with a qid >= 1K is an
1445 * iWARP async notification.
1447 if (__predict_true(lq >= 1024)) {
1448 t4_an_handler(iq, &d->rsp);
1452 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1454 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1456 if (service_iq_fl(q, q->qsize / 16) == 0) {
1457 (void) atomic_cmpset_int(&q->state,
1458 IQS_BUSY, IQS_IDLE);
1460 STAILQ_INSERT_TAIL(&iql, q,
1468 ("%s: illegal response type %d on iq %p",
1469 __func__, rsp_type, iq));
1471 "%s: illegal response type %d on iq %p",
1472 device_get_nameunit(sc->dev), rsp_type, iq);
1477 if (__predict_false(++iq->cidx == iq->sidx)) {
1479 iq->gen ^= F_RSPD_GEN;
1482 if (__predict_false(++ndescs == limit)) {
1483 t4_write_reg(sc, sc->sge_gts_reg,
1485 V_INGRESSQID(iq->cntxt_id) |
1486 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1490 return (EINPROGRESS);
1495 if (STAILQ_EMPTY(&iql))
1499 * Process the head only, and send it to the back of the list if
1500 * it's still not done.
1502 q = STAILQ_FIRST(&iql);
1503 STAILQ_REMOVE_HEAD(&iql, link);
1504 if (service_iq_fl(q, q->qsize / 8) == 0)
1505 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1507 STAILQ_INSERT_TAIL(&iql, q, link);
1510 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1511 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1517 sort_before_lro(struct lro_ctrl *lro)
1520 return (lro->lro_mbuf_max != 0);
1523 static inline uint64_t
1524 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1526 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1528 if (n > UINT64_MAX / 1000000)
1529 return (n / sc->params.vpd.cclk * 1000000);
1531 return (n * 1000000 / sc->params.vpd.cclk);
1535 move_to_next_rxbuf(struct sge_fl *fl)
1539 if (__predict_false((++fl->cidx & 7) == 0)) {
1540 uint16_t cidx = fl->cidx >> 3;
1542 if (__predict_false(cidx == fl->sidx))
1543 fl->cidx = cidx = 0;
1549 * Deals with interrupts on an iq+fl queue.
1552 service_iq_fl(struct sge_iq *iq, int budget)
1554 struct sge_rxq *rxq = iq_to_rxq(iq);
1556 struct adapter *sc = iq->adapter;
1557 struct iq_desc *d = &iq->desc[iq->cidx];
1559 int rsp_type, starved;
1561 uint16_t fl_hw_cidx;
1563 #if defined(INET) || defined(INET6)
1564 const struct timeval lro_timeout = {0, sc->lro_timeout};
1565 struct lro_ctrl *lro = &rxq->lro;
1568 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1569 MPASS(iq->flags & IQ_HAS_FL);
1572 #if defined(INET) || defined(INET6)
1573 if (iq->flags & IQ_ADJ_CREDIT) {
1574 MPASS(sort_before_lro(lro));
1575 iq->flags &= ~IQ_ADJ_CREDIT;
1576 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1577 tcp_lro_flush_all(lro);
1578 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1579 V_INGRESSQID((u32)iq->cntxt_id) |
1580 V_SEINTARM(iq->intr_params));
1586 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1589 limit = budget ? budget : iq->qsize / 16;
1591 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1592 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1597 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1598 lq = be32toh(d->rsp.pldbuflen_qid);
1601 case X_RSPD_TYPE_FLBUF:
1602 if (lq & F_RSPD_NEWBUF) {
1603 if (fl->rx_offset > 0)
1604 move_to_next_rxbuf(fl);
1605 lq = G_RSPD_LEN(lq);
1607 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1609 refill_fl(sc, fl, 64);
1611 fl_hw_cidx = fl->hw_cidx;
1614 if (d->rss.opcode == CPL_RX_PKT) {
1615 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1619 m0 = get_fl_payload(sc, fl, lq);
1620 if (__predict_false(m0 == NULL))
1625 case X_RSPD_TYPE_CPL:
1626 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1627 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1628 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1631 case X_RSPD_TYPE_INTR:
1634 * There are 1K interrupt-capable queues (qids 0
1635 * through 1023). A response type indicating a
1636 * forwarded interrupt with a qid >= 1K is an
1637 * iWARP async notification. That is the only
1638 * acceptable indirect interrupt on this queue.
1640 if (__predict_false(lq < 1024)) {
1641 panic("%s: indirect interrupt on iq_fl %p "
1642 "with qid %u", __func__, iq, lq);
1645 t4_an_handler(iq, &d->rsp);
1649 KASSERT(0, ("%s: illegal response type %d on iq %p",
1650 __func__, rsp_type, iq));
1651 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1652 device_get_nameunit(sc->dev), rsp_type, iq);
1657 if (__predict_false(++iq->cidx == iq->sidx)) {
1659 iq->gen ^= F_RSPD_GEN;
1662 if (__predict_false(++ndescs == limit)) {
1663 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1664 V_INGRESSQID(iq->cntxt_id) |
1665 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1667 #if defined(INET) || defined(INET6)
1668 if (iq->flags & IQ_LRO_ENABLED &&
1669 !sort_before_lro(lro) &&
1670 sc->lro_timeout != 0) {
1671 tcp_lro_flush_inactive(lro, &lro_timeout);
1675 return (EINPROGRESS);
1680 #if defined(INET) || defined(INET6)
1681 if (iq->flags & IQ_LRO_ENABLED) {
1682 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1683 MPASS(sort_before_lro(lro));
1684 /* hold back one credit and don't flush LRO state */
1685 iq->flags |= IQ_ADJ_CREDIT;
1688 tcp_lro_flush_all(lro);
1693 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1694 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1697 starved = refill_fl(sc, fl, 64);
1699 if (__predict_false(starved != 0))
1700 add_fl_to_sfl(sc, fl);
1705 static inline struct cluster_metadata *
1706 cl_metadata(struct fl_sdesc *sd)
1709 return ((void *)(sd->cl + sd->moff));
1713 rxb_free(struct mbuf *m)
1715 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1717 uma_zfree(clm->zone, clm->cl);
1718 counter_u64_add(extfree_rels, 1);
1722 * The mbuf returned comes from zone_muf and carries the payload in one of these
1724 * a) complete frame inside the mbuf
1725 * b) m_cljset (for clusters without metadata)
1726 * d) m_extaddref (cluster with metadata)
1728 static struct mbuf *
1729 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1733 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1734 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1735 struct cluster_metadata *clm;
1739 if (fl->flags & FL_BUF_PACKING) {
1742 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1743 len = min(remaining, blen);
1744 payload = sd->cl + fl->rx_offset;
1746 l = fr_offset + len;
1747 pad = roundup2(l, fl->buf_boundary) - l;
1748 if (fl->rx_offset + len + pad < rxb->size2)
1750 MPASS(fl->rx_offset + blen <= rxb->size2);
1752 MPASS(fl->rx_offset == 0); /* not packing */
1754 len = min(remaining, blen);
1758 if (fr_offset == 0) {
1759 m = m_gethdr(M_NOWAIT, MT_DATA);
1760 if (__predict_false(m == NULL))
1762 m->m_pkthdr.len = remaining;
1764 m = m_get(M_NOWAIT, MT_DATA);
1765 if (__predict_false(m == NULL))
1770 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1771 /* copy data to mbuf */
1772 bcopy(payload, mtod(m, caddr_t), len);
1773 if (fl->flags & FL_BUF_PACKING) {
1774 fl->rx_offset += blen;
1775 MPASS(fl->rx_offset <= rxb->size2);
1776 if (fl->rx_offset < rxb->size2)
1777 return (m); /* without advancing the cidx */
1779 } else if (fl->flags & FL_BUF_PACKING) {
1780 clm = cl_metadata(sd);
1781 if (sd->nmbuf++ == 0) {
1783 clm->zone = rxb->zone;
1785 counter_u64_add(extfree_refs, 1);
1787 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1790 fl->rx_offset += blen;
1791 MPASS(fl->rx_offset <= rxb->size2);
1792 if (fl->rx_offset < rxb->size2)
1793 return (m); /* without advancing the cidx */
1795 m_cljset(m, sd->cl, rxb->type);
1796 sd->cl = NULL; /* consumed, not a recycle candidate */
1799 move_to_next_rxbuf(fl);
1804 static struct mbuf *
1805 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1807 struct mbuf *m0, *m, **pnext;
1810 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1811 M_ASSERTPKTHDR(fl->m0);
1812 MPASS(fl->m0->m_pkthdr.len == plen);
1813 MPASS(fl->remaining < plen);
1817 remaining = fl->remaining;
1818 fl->flags &= ~FL_BUF_RESUME;
1823 * Payload starts at rx_offset in the current hw buffer. Its length is
1824 * 'len' and it may span multiple hw buffers.
1827 m0 = get_scatter_segment(sc, fl, 0, plen);
1830 remaining = plen - m0->m_len;
1831 pnext = &m0->m_next;
1832 while (remaining > 0) {
1834 MPASS(fl->rx_offset == 0);
1835 m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1836 if (__predict_false(m == NULL)) {
1839 fl->remaining = remaining;
1840 fl->flags |= FL_BUF_RESUME;
1845 remaining -= m->m_len;
1854 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1857 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1858 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1861 if (fl->flags & FL_BUF_PACKING) {
1864 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1865 len = min(remaining, blen);
1867 l = fr_offset + len;
1868 pad = roundup2(l, fl->buf_boundary) - l;
1869 if (fl->rx_offset + len + pad < rxb->size2)
1871 fl->rx_offset += blen;
1872 MPASS(fl->rx_offset <= rxb->size2);
1873 if (fl->rx_offset < rxb->size2)
1874 return (len); /* without advancing the cidx */
1876 MPASS(fl->rx_offset == 0); /* not packing */
1878 len = min(remaining, blen);
1880 move_to_next_rxbuf(fl);
1885 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1887 int remaining, fr_offset, len;
1891 while (remaining > 0) {
1892 len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1899 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1902 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1903 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1905 if (fl->flags & FL_BUF_PACKING)
1906 len = rxb->size2 - fl->rx_offset;
1910 return (min(plen, len));
1914 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1918 struct ifnet *ifp = rxq->ifp;
1919 struct sge_fl *fl = &rxq->fl;
1920 struct vi_info *vi = ifp->if_softc;
1921 const struct cpl_rx_pkt *cpl;
1922 #if defined(INET) || defined(INET6)
1923 struct lro_ctrl *lro = &rxq->lro;
1925 static const int sw_hashtype[4][2] = {
1926 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1927 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1928 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1929 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1932 MPASS(plen > sc->params.sge.fl_pktshift);
1933 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1934 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1935 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1939 slen = get_segment_len(sc, fl, plen) -
1940 sc->params.sge.fl_pktshift;
1941 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1942 CURVNET_SET_QUIET(ifp->if_vnet);
1943 rc = pfil_run_hooks(vi->pfil, frame, ifp,
1944 slen | PFIL_MEMPTR | PFIL_IN, NULL);
1946 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1947 skip_fl_payload(sc, fl, plen);
1950 if (rc == PFIL_REALLOCED) {
1951 skip_fl_payload(sc, fl, plen);
1952 m0 = pfil_mem2mbuf(frame);
1957 m0 = get_fl_payload(sc, fl, plen);
1958 if (__predict_false(m0 == NULL))
1961 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1962 m0->m_len -= sc->params.sge.fl_pktshift;
1963 m0->m_data += sc->params.sge.fl_pktshift;
1966 m0->m_pkthdr.rcvif = ifp;
1967 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
1968 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
1970 cpl = (const void *)(&d->rss + 1);
1971 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1972 if (ifp->if_capenable & IFCAP_RXCSUM &&
1973 cpl->l2info & htobe32(F_RXF_IP)) {
1974 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1975 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1977 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1978 cpl->l2info & htobe32(F_RXF_IP6)) {
1979 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1984 if (__predict_false(cpl->ip_frag))
1985 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1987 m0->m_pkthdr.csum_data = 0xffff;
1991 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1992 m0->m_flags |= M_VLANTAG;
1993 rxq->vlan_extraction++;
1996 if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
1998 * Fill up rcv_tstmp but do not set M_TSTMP.
1999 * rcv_tstmp is not in the format that the
2000 * kernel expects and we don't want to mislead
2001 * it. For now this is only for custom code
2002 * that knows how to interpret cxgbe's stamp.
2004 m0->m_pkthdr.rcv_tstmp =
2005 last_flit_to_ns(sc, d->rsp.u.last_flit);
2007 m0->m_flags |= M_TSTMP;
2012 m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2014 #if defined(INET) || defined(INET6)
2015 if (rxq->iq.flags & IQ_LRO_ENABLED &&
2016 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2017 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2018 if (sort_before_lro(lro)) {
2019 tcp_lro_queue_mbuf(lro, m0);
2020 return (0); /* queued for sort, then LRO */
2022 if (tcp_lro_rx(lro, m0, 0) == 0)
2023 return (0); /* queued for LRO */
2026 ifp->if_input(ifp, m0);
2032 * Must drain the wrq or make sure that someone else will.
2035 wrq_tx_drain(void *arg, int n)
2037 struct sge_wrq *wrq = arg;
2038 struct sge_eq *eq = &wrq->eq;
2041 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2042 drain_wrq_wr_list(wrq->adapter, wrq);
2047 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2049 struct sge_eq *eq = &wrq->eq;
2050 u_int available, dbdiff; /* # of hardware descriptors */
2053 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2055 EQ_LOCK_ASSERT_OWNED(eq);
2056 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2057 wr = STAILQ_FIRST(&wrq->wr_list);
2058 MPASS(wr != NULL); /* Must be called with something useful to do */
2059 MPASS(eq->pidx == eq->dbidx);
2063 eq->cidx = read_hw_cidx(eq);
2064 if (eq->pidx == eq->cidx)
2065 available = eq->sidx - 1;
2067 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2069 MPASS(wr->wrq == wrq);
2070 n = howmany(wr->wr_len, EQ_ESIZE);
2074 dst = (void *)&eq->desc[eq->pidx];
2075 if (__predict_true(eq->sidx - eq->pidx > n)) {
2076 /* Won't wrap, won't end exactly at the status page. */
2077 bcopy(&wr->wr[0], dst, wr->wr_len);
2080 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2082 bcopy(&wr->wr[0], dst, first_portion);
2083 if (wr->wr_len > first_portion) {
2084 bcopy(&wr->wr[first_portion], &eq->desc[0],
2085 wr->wr_len - first_portion);
2087 eq->pidx = n - (eq->sidx - eq->pidx);
2089 wrq->tx_wrs_copied++;
2091 if (available < eq->sidx / 4 &&
2092 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2094 * XXX: This is not 100% reliable with some
2095 * types of WRs. But this is a very unusual
2096 * situation for an ofld/ctrl queue anyway.
2098 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2104 ring_eq_db(sc, eq, dbdiff);
2108 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2110 MPASS(wrq->nwr_pending > 0);
2112 MPASS(wrq->ndesc_needed >= n);
2113 wrq->ndesc_needed -= n;
2114 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2117 ring_eq_db(sc, eq, dbdiff);
2121 * Doesn't fail. Holds on to work requests it can't send right away.
2124 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2127 struct sge_eq *eq = &wrq->eq;
2130 EQ_LOCK_ASSERT_OWNED(eq);
2132 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2133 MPASS((wr->wr_len & 0x7) == 0);
2135 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2137 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2139 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2140 return; /* commit_wrq_wr will drain wr_list as well. */
2142 drain_wrq_wr_list(sc, wrq);
2144 /* Doorbell must have caught up to the pidx. */
2145 MPASS(eq->pidx == eq->dbidx);
2149 t4_update_fl_bufsize(struct ifnet *ifp)
2151 struct vi_info *vi = ifp->if_softc;
2152 struct adapter *sc = vi->pi->adapter;
2153 struct sge_rxq *rxq;
2155 struct sge_ofld_rxq *ofld_rxq;
2158 int i, maxp, mtu = ifp->if_mtu;
2160 maxp = mtu_to_max_payload(sc, mtu);
2161 for_each_rxq(vi, i, rxq) {
2165 fl->zidx = find_refill_source(sc, maxp,
2166 fl->flags & FL_BUF_PACKING);
2170 for_each_ofld_rxq(vi, i, ofld_rxq) {
2174 fl->zidx = find_refill_source(sc, maxp,
2175 fl->flags & FL_BUF_PACKING);
2182 mbuf_nsegs(struct mbuf *m)
2186 KASSERT(m->m_pkthdr.l5hlen > 0,
2187 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2189 return (m->m_pkthdr.l5hlen);
2193 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2197 m->m_pkthdr.l5hlen = nsegs;
2201 mbuf_cflags(struct mbuf *m)
2205 return (m->m_pkthdr.PH_loc.eight[4]);
2209 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2213 m->m_pkthdr.PH_loc.eight[4] = flags;
2217 mbuf_len16(struct mbuf *m)
2222 n = m->m_pkthdr.PH_loc.eight[0];
2223 if (!(mbuf_cflags(m) & MC_TLS))
2224 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2230 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2234 m->m_pkthdr.PH_loc.eight[0] = len16;
2239 mbuf_eo_nsegs(struct mbuf *m)
2243 return (m->m_pkthdr.PH_loc.eight[1]);
2247 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2251 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2255 mbuf_eo_len16(struct mbuf *m)
2260 n = m->m_pkthdr.PH_loc.eight[2];
2261 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2267 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2271 m->m_pkthdr.PH_loc.eight[2] = len16;
2275 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2279 return (m->m_pkthdr.PH_loc.eight[3]);
2283 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2287 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2291 needs_eo(struct cxgbe_snd_tag *cst)
2294 return (cst != NULL && cst->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2299 * Try to allocate an mbuf to contain a raw work request. To make it
2300 * easy to construct the work request, don't allocate a chain but a
2304 alloc_wr_mbuf(int len, int how)
2309 m = m_gethdr(how, MT_DATA);
2310 else if (len <= MCLBYTES)
2311 m = m_getcl(how, MT_DATA, M_PKTHDR);
2316 m->m_pkthdr.len = len;
2318 set_mbuf_cflags(m, MC_RAW_WR);
2319 set_mbuf_len16(m, howmany(len, 16));
2324 needs_hwcsum(struct mbuf *m)
2329 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP |
2330 CSUM_TSO | CSUM_UDP_IPV6 | CSUM_TCP_IPV6));
2334 needs_tso(struct mbuf *m)
2339 return (m->m_pkthdr.csum_flags & CSUM_TSO);
2343 needs_l3_csum(struct mbuf *m)
2348 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO));
2352 needs_tcp_csum(struct mbuf *m)
2356 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO));
2361 needs_l4_csum(struct mbuf *m)
2366 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2367 CSUM_TCP_IPV6 | CSUM_TSO));
2371 needs_udp_csum(struct mbuf *m)
2375 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6));
2380 needs_vlan_insertion(struct mbuf *m)
2385 return (m->m_flags & M_VLANTAG);
2389 m_advance(struct mbuf **pm, int *poffset, int len)
2391 struct mbuf *m = *pm;
2392 int offset = *poffset;
2398 if (offset + len < m->m_len) {
2400 p = mtod(m, uintptr_t) + offset;
2403 len -= m->m_len - offset;
2414 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2416 struct mbuf_ext_pgs *ext_pgs;
2418 int i, len, off, pglen, pgoff, seglen, segoff;
2421 MBUF_EXT_PGS_ASSERT(m);
2422 ext_pgs = m->m_ext.ext_pgs;
2423 off = mtod(m, vm_offset_t);
2428 if (ext_pgs->hdr_len != 0) {
2429 if (off >= ext_pgs->hdr_len) {
2430 off -= ext_pgs->hdr_len;
2432 seglen = ext_pgs->hdr_len - off;
2434 seglen = min(seglen, len);
2437 paddr = pmap_kextract(
2438 (vm_offset_t)&ext_pgs->hdr[segoff]);
2439 if (*nextaddr != paddr)
2441 *nextaddr = paddr + seglen;
2444 pgoff = ext_pgs->first_pg_off;
2445 for (i = 0; i < ext_pgs->npgs && len > 0; i++) {
2446 pglen = mbuf_ext_pg_len(ext_pgs, i, pgoff);
2452 seglen = pglen - off;
2453 segoff = pgoff + off;
2455 seglen = min(seglen, len);
2457 paddr = ext_pgs->pa[i] + segoff;
2458 if (*nextaddr != paddr)
2460 *nextaddr = paddr + seglen;
2464 seglen = min(len, ext_pgs->trail_len - off);
2466 paddr = pmap_kextract((vm_offset_t)&ext_pgs->trail[off]);
2467 if (*nextaddr != paddr)
2469 *nextaddr = paddr + seglen;
2477 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2478 * must have at least one mbuf that's not empty. It is possible for this
2479 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2482 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2484 vm_paddr_t nextaddr, paddr;
2489 MPASS(m->m_pkthdr.len > 0);
2490 MPASS(m->m_pkthdr.len >= skip);
2494 for (; m; m = m->m_next) {
2496 if (__predict_false(len == 0))
2502 if ((m->m_flags & M_NOMAP) != 0) {
2503 *cflags |= MC_NOMAP;
2504 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2508 va = mtod(m, vm_offset_t) + skip;
2511 paddr = pmap_kextract(va);
2512 nsegs += sglist_count((void *)(uintptr_t)va, len);
2513 if (paddr == nextaddr)
2515 nextaddr = pmap_kextract(va + len - 1) + 1;
2522 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2523 * a) caller can assume it's been freed if this function returns with an error.
2524 * b) it may get defragged up if the gather list is too long for the hardware.
2527 parse_pkt(struct adapter *sc, struct mbuf **mp)
2529 struct mbuf *m0 = *mp, *m;
2530 int rc, nsegs, defragged = 0, offset;
2531 struct ether_header *eh;
2533 #if defined(INET) || defined(INET6)
2536 #if defined(KERN_TLS) || defined(RATELIMIT)
2537 struct cxgbe_snd_tag *cst;
2544 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2553 * First count the number of gather list segments in the payload.
2554 * Defrag the mbuf if nsegs exceeds the hardware limit.
2557 MPASS(m0->m_pkthdr.len > 0);
2558 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2559 #if defined(KERN_TLS) || defined(RATELIMIT)
2560 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2561 cst = mst_to_cst(m0->m_pkthdr.snd_tag);
2566 if (cst != NULL && cst->type == IF_SND_TAG_TYPE_TLS) {
2570 set_mbuf_cflags(m0, cflags);
2571 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2574 set_mbuf_nsegs(m0, nsegs);
2575 set_mbuf_len16(m0, len16);
2579 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2580 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2584 *mp = m0 = m; /* update caller's copy after defrag */
2588 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2589 !(cflags & MC_NOMAP))) {
2590 m0 = m_pullup(m0, m0->m_pkthdr.len);
2592 /* Should have left well enough alone. */
2596 *mp = m0; /* update caller's copy after pullup */
2599 set_mbuf_nsegs(m0, nsegs);
2600 set_mbuf_cflags(m0, cflags);
2601 if (sc->flags & IS_VF)
2602 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2604 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2608 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2609 * checksumming is enabled. needs_l4_csum happens to check for all the
2612 if (__predict_false(needs_eo(cst) && !needs_l4_csum(m0))) {
2613 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2614 m0->m_pkthdr.snd_tag = NULL;
2615 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2620 if (!needs_hwcsum(m0)
2628 eh = mtod(m, struct ether_header *);
2629 eh_type = ntohs(eh->ether_type);
2630 if (eh_type == ETHERTYPE_VLAN) {
2631 struct ether_vlan_header *evh = (void *)eh;
2633 eh_type = ntohs(evh->evl_proto);
2634 m0->m_pkthdr.l2hlen = sizeof(*evh);
2636 m0->m_pkthdr.l2hlen = sizeof(*eh);
2639 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2643 case ETHERTYPE_IPV6:
2645 struct ip6_hdr *ip6 = l3hdr;
2647 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2649 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2656 struct ip *ip = l3hdr;
2658 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2663 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2664 " with the same INET/INET6 options as the kernel.",
2668 #if defined(INET) || defined(INET6)
2669 if (needs_tcp_csum(m0)) {
2670 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2671 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2673 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2674 set_mbuf_eo_tsclk_tsoff(m0,
2675 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2676 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2678 set_mbuf_eo_tsclk_tsoff(m0, 0);
2679 } else if (needs_udp_csum(m0)) {
2680 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2684 if (needs_eo(cst)) {
2687 /* EO WRs have the headers in the WR and not the GL. */
2688 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2689 m0->m_pkthdr.l4hlen;
2691 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2692 MPASS(cflags == mbuf_cflags(m0));
2693 set_mbuf_eo_nsegs(m0, nsegs);
2694 set_mbuf_eo_len16(m0,
2695 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2704 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2706 struct sge_eq *eq = &wrq->eq;
2707 struct adapter *sc = wrq->adapter;
2708 int ndesc, available;
2713 ndesc = howmany(len16, EQ_ESIZE / 16);
2714 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2718 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2719 drain_wrq_wr_list(sc, wrq);
2721 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2724 wr = alloc_wrqe(len16 * 16, wrq);
2725 if (__predict_false(wr == NULL))
2728 cookie->ndesc = ndesc;
2732 eq->cidx = read_hw_cidx(eq);
2733 if (eq->pidx == eq->cidx)
2734 available = eq->sidx - 1;
2736 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2737 if (available < ndesc)
2740 cookie->pidx = eq->pidx;
2741 cookie->ndesc = ndesc;
2742 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2744 w = &eq->desc[eq->pidx];
2745 IDXINCR(eq->pidx, ndesc, eq->sidx);
2746 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2748 wrq->ss_pidx = cookie->pidx;
2749 wrq->ss_len = len16 * 16;
2758 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2760 struct sge_eq *eq = &wrq->eq;
2761 struct adapter *sc = wrq->adapter;
2763 struct wrq_cookie *prev, *next;
2765 if (cookie->pidx == -1) {
2766 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2772 if (__predict_false(w == &wrq->ss[0])) {
2773 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2775 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2776 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2777 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2780 wrq->tx_wrs_direct++;
2783 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2784 pidx = cookie->pidx;
2785 MPASS(pidx >= 0 && pidx < eq->sidx);
2786 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2787 next = TAILQ_NEXT(cookie, link);
2789 MPASS(pidx == eq->dbidx);
2790 if (next == NULL || ndesc >= 16) {
2792 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2795 * Note that the WR via which we'll request tx updates
2796 * is at pidx and not eq->pidx, which has moved on
2799 dst = (void *)&eq->desc[pidx];
2800 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2801 if (available < eq->sidx / 4 &&
2802 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2804 * XXX: This is not 100% reliable with some
2805 * types of WRs. But this is a very unusual
2806 * situation for an ofld/ctrl queue anyway.
2808 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2812 ring_eq_db(wrq->adapter, eq, ndesc);
2814 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2816 next->ndesc += ndesc;
2819 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2820 prev->ndesc += ndesc;
2822 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2824 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2825 drain_wrq_wr_list(sc, wrq);
2828 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2829 /* Doorbell must have caught up to the pidx. */
2830 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2837 can_resume_eth_tx(struct mp_ring *r)
2839 struct sge_eq *eq = r->cookie;
2841 return (total_available_tx_desc(eq) > eq->sidx / 8);
2845 cannot_use_txpkts(struct mbuf *m)
2847 /* maybe put a GL limit too, to avoid silliness? */
2849 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
2853 discard_tx(struct sge_eq *eq)
2856 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2860 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr)
2863 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
2865 case FW_ETH_TX_PKT_WR:
2866 case FW_ETH_TX_PKTS_WR:
2867 case FW_ETH_TX_PKTS2_WR:
2868 case FW_ETH_TX_PKT_VM_WR:
2876 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2877 * be consumed. Return the actual number consumed. 0 indicates a stall.
2880 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2882 struct sge_txq *txq = r->cookie;
2883 struct sge_eq *eq = &txq->eq;
2884 struct ifnet *ifp = txq->ifp;
2885 struct vi_info *vi = ifp->if_softc;
2886 struct port_info *pi = vi->pi;
2887 struct adapter *sc = pi->adapter;
2888 u_int total, remaining; /* # of packets */
2889 u_int available, dbdiff; /* # of hardware descriptors */
2891 struct mbuf *m0, *tail;
2893 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2895 remaining = IDXDIFF(pidx, cidx, r->size);
2896 MPASS(remaining > 0); /* Must not be called without work to do. */
2900 if (__predict_false(discard_tx(eq))) {
2901 while (cidx != pidx) {
2902 m0 = r->items[cidx];
2904 if (++cidx == r->size)
2907 reclaim_tx_descs(txq, 2048);
2912 /* How many hardware descriptors do we have readily available. */
2913 if (eq->pidx == eq->cidx)
2914 available = eq->sidx - 1;
2916 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2917 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2919 while (remaining > 0) {
2921 m0 = r->items[cidx];
2923 MPASS(m0->m_nextpkt == NULL);
2925 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) {
2926 MPASS(howmany(mbuf_len16(m0), EQ_ESIZE / 16) <= 64);
2927 available += reclaim_tx_descs(txq, 64);
2928 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2929 break; /* out of descriptors */
2932 next_cidx = cidx + 1;
2933 if (__predict_false(next_cidx == r->size))
2936 wr = (void *)&eq->desc[eq->pidx];
2937 if (mbuf_cflags(m0) & MC_RAW_WR) {
2940 n = write_raw_wr(txq, (void *)wr, m0, available);
2942 } else if (mbuf_cflags(m0) & MC_TLS) {
2945 ETHER_BPF_MTAP(ifp, m0);
2946 n = t6_ktls_write_wr(txq,(void *)wr, m0,
2947 mbuf_nsegs(m0), available);
2949 } else if (sc->flags & IS_VF) {
2952 ETHER_BPF_MTAP(ifp, m0);
2953 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2955 } else if (remaining > 1 &&
2956 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2958 /* pkts at cidx, next_cidx should both be in txp. */
2959 MPASS(txp.npkt == 2);
2960 tail = r->items[next_cidx];
2961 MPASS(tail->m_nextpkt == NULL);
2962 ETHER_BPF_MTAP(ifp, m0);
2963 ETHER_BPF_MTAP(ifp, tail);
2964 m0->m_nextpkt = tail;
2966 if (__predict_false(++next_cidx == r->size))
2969 while (next_cidx != pidx) {
2970 if (add_to_txpkts(r->items[next_cidx], &txp,
2973 tail->m_nextpkt = r->items[next_cidx];
2974 tail = tail->m_nextpkt;
2975 ETHER_BPF_MTAP(ifp, tail);
2976 if (__predict_false(++next_cidx == r->size))
2980 n = write_txpkts_wr(sc, txq, wr, m0, &txp, available);
2982 remaining -= txp.npkt;
2986 ETHER_BPF_MTAP(ifp, m0);
2987 n = write_txpkt_wr(sc, txq, (void *)wr, m0, available);
2989 MPASS(n >= 1 && n <= available);
2990 if (!(mbuf_cflags(m0) & MC_TLS))
2991 MPASS(n <= SGE_MAX_WR_NDESC);
2995 IDXINCR(eq->pidx, n, eq->sidx);
2997 if (wr_can_update_eq(wr)) {
2998 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2999 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3000 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3002 eq->equeqidx = eq->pidx;
3003 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >=
3005 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3006 eq->equeqidx = eq->pidx;
3010 if (dbdiff >= 16 && remaining >= 4) {
3011 ring_eq_db(sc, eq, dbdiff);
3012 available += reclaim_tx_descs(txq, 4 * dbdiff);
3019 ring_eq_db(sc, eq, dbdiff);
3020 reclaim_tx_descs(txq, 32);
3029 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3033 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3034 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3035 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3036 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3040 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3041 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3042 if (pktc_idx >= 0) {
3043 iq->intr_params |= F_QINTR_CNT_EN;
3044 iq->intr_pktc_idx = pktc_idx;
3046 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3047 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3051 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3055 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3056 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3057 if (sc->flags & BUF_PACKING_OK &&
3058 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3059 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3060 fl->flags |= FL_BUF_PACKING;
3061 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3062 fl->safe_zidx = sc->sge.safe_zidx;
3066 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3067 uint8_t tx_chan, uint16_t iqid, char *name)
3069 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
3071 eq->flags = eqtype & EQ_TYPEMASK;
3072 eq->tx_chan = tx_chan;
3074 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3075 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3079 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3080 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3084 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3085 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3087 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
3091 rc = bus_dmamem_alloc(*tag, va,
3092 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3094 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
3098 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3100 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
3105 free_ring(sc, *tag, *map, *pa, *va);
3111 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3112 bus_addr_t pa, void *va)
3115 bus_dmamap_unload(tag, map);
3117 bus_dmamem_free(tag, va, map);
3119 bus_dma_tag_destroy(tag);
3125 * Allocates the ring for an ingress queue and an optional freelist. If the
3126 * freelist is specified it will be allocated and then associated with the
3129 * Returns errno on failure. Resources allocated up to that point may still be
3130 * allocated. Caller is responsible for cleanup in case this function fails.
3132 * If the ingress queue will take interrupts directly then the intr_idx
3133 * specifies the vector, starting from 0. -1 means the interrupts for this
3134 * queue should be forwarded to the fwq.
3137 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3138 int intr_idx, int cong)
3140 int rc, i, cntxt_id;
3143 struct port_info *pi = vi->pi;
3144 struct adapter *sc = iq->adapter;
3145 struct sge_params *sp = &sc->params.sge;
3148 len = iq->qsize * IQ_ESIZE;
3149 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3150 (void **)&iq->desc);
3154 bzero(&c, sizeof(c));
3155 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3156 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3157 V_FW_IQ_CMD_VFN(0));
3159 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3162 /* Special handling for firmware event queue */
3163 if (iq == &sc->sge.fwq)
3164 v |= F_FW_IQ_CMD_IQASYNCH;
3167 /* Forwarded interrupts, all headed to fwq */
3168 v |= F_FW_IQ_CMD_IQANDST;
3169 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3171 KASSERT(intr_idx < sc->intr_count,
3172 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
3173 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
3176 c.type_to_iqandstindex = htobe32(v |
3177 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3178 V_FW_IQ_CMD_VIID(vi->viid) |
3179 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3180 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3181 F_FW_IQ_CMD_IQGTSMODE |
3182 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3183 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3184 c.iqsize = htobe16(iq->qsize);
3185 c.iqaddr = htobe64(iq->ba);
3187 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3190 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3192 len = fl->qsize * EQ_ESIZE;
3193 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3194 &fl->ba, (void **)&fl->desc);
3198 /* Allocate space for one software descriptor per buffer. */
3199 rc = alloc_fl_sdesc(fl);
3201 device_printf(sc->dev,
3202 "failed to setup fl software descriptors: %d\n",
3207 if (fl->flags & FL_BUF_PACKING) {
3208 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3209 fl->buf_boundary = sp->pack_boundary;
3211 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3212 fl->buf_boundary = 16;
3214 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3215 fl->buf_boundary = sp->pad_boundary;
3217 c.iqns_to_fl0congen |=
3218 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3219 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3220 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3221 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3224 c.iqns_to_fl0congen |=
3225 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3226 F_FW_IQ_CMD_FL0CONGCIF |
3227 F_FW_IQ_CMD_FL0CONGEN);
3229 c.fl0dcaen_to_fl0cidxfthresh =
3230 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3231 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3232 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3233 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3234 c.fl0size = htobe16(fl->qsize);
3235 c.fl0addr = htobe64(fl->ba);
3238 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3240 device_printf(sc->dev,
3241 "failed to create ingress queue: %d\n", rc);
3246 iq->gen = F_RSPD_GEN;
3247 iq->intr_next = iq->intr_params;
3248 iq->cntxt_id = be16toh(c.iqid);
3249 iq->abs_id = be16toh(c.physiqid);
3250 iq->flags |= IQ_ALLOCATED;
3252 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3253 if (cntxt_id >= sc->sge.niq) {
3254 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3255 cntxt_id, sc->sge.niq - 1);
3257 sc->sge.iqmap[cntxt_id] = iq;
3262 iq->flags |= IQ_HAS_FL;
3263 fl->cntxt_id = be16toh(c.fl0id);
3264 fl->pidx = fl->cidx = 0;
3266 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3267 if (cntxt_id >= sc->sge.neq) {
3268 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3269 __func__, cntxt_id, sc->sge.neq - 1);
3271 sc->sge.eqmap[cntxt_id] = (void *)fl;
3274 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3275 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3276 uint32_t mask = (1 << s_qpp) - 1;
3277 volatile uint8_t *udb;
3279 udb = sc->udbs_base + UDBS_DB_OFFSET;
3280 udb += (qid >> s_qpp) << PAGE_SHIFT;
3282 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3283 udb += qid << UDBS_SEG_SHIFT;
3286 fl->udb = (volatile void *)udb;
3288 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3291 /* Enough to make sure the SGE doesn't think it's starved */
3292 refill_fl(sc, fl, fl->lowat);
3296 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3297 uint32_t param, val;
3299 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3300 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3301 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3306 for (i = 0; i < 4; i++) {
3307 if (cong & (1 << i))
3308 val |= 1 << (i << 2);
3312 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3314 /* report error but carry on */
3315 device_printf(sc->dev,
3316 "failed to set congestion manager context for "
3317 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3321 /* Enable IQ interrupts */
3322 atomic_store_rel_int(&iq->state, IQS_IDLE);
3323 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3324 V_INGRESSQID(iq->cntxt_id));
3330 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3333 struct adapter *sc = iq->adapter;
3337 return (0); /* nothing to do */
3339 dev = vi ? vi->dev : sc->dev;
3341 if (iq->flags & IQ_ALLOCATED) {
3342 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3343 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3344 fl ? fl->cntxt_id : 0xffff, 0xffff);
3347 "failed to free queue %p: %d\n", iq, rc);
3350 iq->flags &= ~IQ_ALLOCATED;
3353 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3355 bzero(iq, sizeof(*iq));
3358 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3362 free_fl_sdesc(sc, fl);
3364 if (mtx_initialized(&fl->fl_lock))
3365 mtx_destroy(&fl->fl_lock);
3367 bzero(fl, sizeof(*fl));
3374 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3377 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3379 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3380 "bus address of descriptor ring");
3381 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3382 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3384 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->abs_id, 0,
3385 sysctl_uint16, "I", "absolute id of the queue");
3386 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3387 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->cntxt_id, 0,
3388 sysctl_uint16, "I", "SGE context id of the queue");
3389 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3390 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &iq->cidx, 0,
3391 sysctl_uint16, "I", "consumer index");
3395 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3396 struct sysctl_oid *oid, struct sge_fl *fl)
3398 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3400 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3401 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3402 children = SYSCTL_CHILDREN(oid);
3404 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3405 &fl->ba, "bus address of descriptor ring");
3406 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3407 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3408 "desc ring size in bytes");
3409 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3410 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &fl->cntxt_id, 0,
3411 sysctl_uint16, "I", "SGE context id of the freelist");
3412 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3413 fl_pad ? 1 : 0, "padding enabled");
3414 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3415 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3417 0, "consumer index");
3418 if (fl->flags & FL_BUF_PACKING) {
3419 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3420 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3422 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3423 0, "producer index");
3424 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3425 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3426 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3427 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3428 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3429 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3433 alloc_fwq(struct adapter *sc)
3436 struct sge_iq *fwq = &sc->sge.fwq;
3437 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3438 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3440 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3441 if (sc->flags & IS_VF)
3444 intr_idx = sc->intr_count > 1 ? 1 : 0;
3445 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3447 device_printf(sc->dev,
3448 "failed to create firmware event queue: %d\n", rc);
3452 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq",
3453 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
3454 add_iq_sysctls(&sc->ctx, oid, fwq);
3460 free_fwq(struct adapter *sc)
3462 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3466 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3467 struct sysctl_oid *oid)
3471 struct sysctl_oid_list *children;
3473 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3475 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3476 sc->sge.fwq.cntxt_id, name);
3478 children = SYSCTL_CHILDREN(oid);
3479 snprintf(name, sizeof(name), "%d", idx);
3480 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name,
3481 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ctrl queue");
3482 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3488 tnl_cong(struct port_info *pi, int drop)
3496 return (pi->rx_e_chan_map);
3500 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3501 struct sysctl_oid *oid)
3504 struct adapter *sc = vi->pi->adapter;
3505 struct sysctl_oid_list *children;
3508 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3509 tnl_cong(vi->pi, cong_drop));
3514 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3516 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3517 ("iq_base mismatch"));
3518 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3519 ("PF with non-zero iq_base"));
3522 * The freelist is just barely above the starvation threshold right now,
3523 * fill it up a bit more.
3526 refill_fl(sc, &rxq->fl, 128);
3527 FL_UNLOCK(&rxq->fl);
3529 #if defined(INET) || defined(INET6)
3530 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3533 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3535 if (vi->ifp->if_capenable & IFCAP_LRO)
3536 rxq->iq.flags |= IQ_LRO_ENABLED;
3538 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP)
3539 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3542 children = SYSCTL_CHILDREN(oid);
3544 snprintf(name, sizeof(name), "%d", idx);
3545 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
3546 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
3547 children = SYSCTL_CHILDREN(oid);
3549 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3550 #if defined(INET) || defined(INET6)
3551 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3552 &rxq->lro.lro_queued, 0, NULL);
3553 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3554 &rxq->lro.lro_flushed, 0, NULL);
3556 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3557 &rxq->rxcsum, "# of times hardware assisted with checksum");
3558 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3559 CTLFLAG_RD, &rxq->vlan_extraction,
3560 "# of times hardware extracted 802.1Q tag");
3562 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3568 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3572 #if defined(INET) || defined(INET6)
3574 tcp_lro_free(&rxq->lro);
3575 rxq->lro.ifp = NULL;
3579 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3581 bzero(rxq, sizeof(*rxq));
3588 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3589 int intr_idx, int idx, struct sysctl_oid *oid)
3591 struct port_info *pi = vi->pi;
3593 struct sysctl_oid_list *children;
3596 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3600 children = SYSCTL_CHILDREN(oid);
3602 snprintf(name, sizeof(name), "%d", idx);
3603 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
3604 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
3605 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3606 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3612 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3616 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3618 bzero(ofld_rxq, sizeof(*ofld_rxq));
3626 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3627 int idx, struct sysctl_oid *oid)
3630 struct sysctl_oid_list *children;
3631 struct sysctl_ctx_list *ctx;
3634 struct adapter *sc = vi->pi->adapter;
3635 struct netmap_adapter *na = NA(vi->ifp);
3639 len = vi->qsize_rxq * IQ_ESIZE;
3640 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3641 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3645 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3646 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3647 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3653 nm_rxq->iq_cidx = 0;
3654 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3655 nm_rxq->iq_gen = F_RSPD_GEN;
3656 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3657 nm_rxq->fl_sidx = na->num_rx_desc;
3658 nm_rxq->fl_sidx2 = nm_rxq->fl_sidx; /* copy for rxsync cacheline */
3659 nm_rxq->intr_idx = intr_idx;
3660 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3663 children = SYSCTL_CHILDREN(oid);
3665 snprintf(name, sizeof(name), "%d", idx);
3666 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name,
3667 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
3668 children = SYSCTL_CHILDREN(oid);
3670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3671 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_abs_id,
3672 0, sysctl_uint16, "I", "absolute id of the queue");
3673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3674 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_cntxt_id,
3675 0, sysctl_uint16, "I", "SGE context id of the queue");
3676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3677 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->iq_cidx, 0,
3678 sysctl_uint16, "I", "consumer index");
3680 children = SYSCTL_CHILDREN(oid);
3681 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3682 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3683 children = SYSCTL_CHILDREN(oid);
3685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3686 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_rxq->fl_cntxt_id,
3687 0, sysctl_uint16, "I", "SGE context id of the freelist");
3688 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3689 &nm_rxq->fl_cidx, 0, "consumer index");
3690 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3691 &nm_rxq->fl_pidx, 0, "producer index");
3698 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3700 struct adapter *sc = vi->pi->adapter;
3702 if (vi->flags & VI_INIT_DONE)
3703 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3705 MPASS(nm_rxq->iq_cntxt_id == 0);
3707 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3709 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3716 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3717 struct sysctl_oid *oid)
3721 struct port_info *pi = vi->pi;
3722 struct adapter *sc = pi->adapter;
3723 struct netmap_adapter *na = NA(vi->ifp);
3725 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3727 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3728 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3729 &nm_txq->ba, (void **)&nm_txq->desc);
3733 nm_txq->pidx = nm_txq->cidx = 0;
3734 nm_txq->sidx = na->num_tx_desc;
3736 nm_txq->iqidx = iqidx;
3737 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3738 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
3739 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
3740 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0))
3741 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
3743 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
3744 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3746 snprintf(name, sizeof(name), "%d", idx);
3747 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
3748 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "netmap tx queue");
3749 children = SYSCTL_CHILDREN(oid);
3751 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3752 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3753 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3754 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_txq->cidx, 0,
3755 sysctl_uint16, "I", "consumer index");
3756 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3757 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &nm_txq->pidx, 0,
3758 sysctl_uint16, "I", "producer index");
3764 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3766 struct adapter *sc = vi->pi->adapter;
3768 if (vi->flags & VI_INIT_DONE)
3769 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3771 MPASS(nm_txq->cntxt_id == 0);
3773 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3781 * Returns a reasonable automatic cidx flush threshold for a given queue size.
3784 qsize_to_fthresh(int qsize)
3788 while (!powerof2(qsize))
3790 fthresh = ilog2(qsize);
3791 if (fthresh > X_CIDXFLUSHTHRESH_128)
3792 fthresh = X_CIDXFLUSHTHRESH_128;
3798 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3801 struct fw_eq_ctrl_cmd c;
3802 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3804 bzero(&c, sizeof(c));
3806 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3807 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3808 V_FW_EQ_CTRL_CMD_VFN(0));
3809 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3810 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3811 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3812 c.physeqid_pkd = htobe32(0);
3813 c.fetchszm_to_iqid =
3814 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3815 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3816 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3818 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3819 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3820 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3821 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3822 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3823 c.eqaddr = htobe64(eq->ba);
3825 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3827 device_printf(sc->dev,
3828 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3831 eq->flags |= EQ_ALLOCATED;
3833 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3834 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3835 if (cntxt_id >= sc->sge.neq)
3836 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3837 cntxt_id, sc->sge.neq - 1);
3838 sc->sge.eqmap[cntxt_id] = eq;
3844 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3847 struct fw_eq_eth_cmd c;
3848 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3850 bzero(&c, sizeof(c));
3852 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3853 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3854 V_FW_EQ_ETH_CMD_VFN(0));
3855 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3856 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3857 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3858 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3859 c.fetchszm_to_iqid =
3860 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3861 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3862 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3864 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3865 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3866 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3867 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3868 c.eqaddr = htobe64(eq->ba);
3870 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3872 device_printf(vi->dev,
3873 "failed to create Ethernet egress queue: %d\n", rc);
3876 eq->flags |= EQ_ALLOCATED;
3878 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3879 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3880 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3881 if (cntxt_id >= sc->sge.neq)
3882 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3883 cntxt_id, sc->sge.neq - 1);
3884 sc->sge.eqmap[cntxt_id] = eq;
3889 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3891 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3894 struct fw_eq_ofld_cmd c;
3895 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3897 bzero(&c, sizeof(c));
3899 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3900 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3901 V_FW_EQ_OFLD_CMD_VFN(0));
3902 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3903 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3904 c.fetchszm_to_iqid =
3905 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3906 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3907 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3909 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3910 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3911 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3912 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3913 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3914 c.eqaddr = htobe64(eq->ba);
3916 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3918 device_printf(vi->dev,
3919 "failed to create egress queue for TCP offload: %d\n", rc);
3922 eq->flags |= EQ_ALLOCATED;
3924 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3925 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3926 if (cntxt_id >= sc->sge.neq)
3927 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3928 cntxt_id, sc->sge.neq - 1);
3929 sc->sge.eqmap[cntxt_id] = eq;
3936 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3941 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3943 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3944 len = qsize * EQ_ESIZE;
3945 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3946 &eq->ba, (void **)&eq->desc);
3950 eq->pidx = eq->cidx = eq->dbidx = 0;
3951 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
3953 eq->doorbells = sc->doorbells;
3955 switch (eq->flags & EQ_TYPEMASK) {
3957 rc = ctrl_eq_alloc(sc, eq);
3961 rc = eth_eq_alloc(sc, vi, eq);
3964 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3966 rc = ofld_eq_alloc(sc, vi, eq);
3971 panic("%s: invalid eq type %d.", __func__,
3972 eq->flags & EQ_TYPEMASK);
3975 device_printf(sc->dev,
3976 "failed to allocate egress queue(%d): %d\n",
3977 eq->flags & EQ_TYPEMASK, rc);
3980 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3981 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3982 isset(&eq->doorbells, DOORBELL_WCWR)) {
3983 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3984 uint32_t mask = (1 << s_qpp) - 1;
3985 volatile uint8_t *udb;
3987 udb = sc->udbs_base + UDBS_DB_OFFSET;
3988 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3989 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3990 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3991 clrbit(&eq->doorbells, DOORBELL_WCWR);
3993 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3996 eq->udb = (volatile void *)udb;
4003 free_eq(struct adapter *sc, struct sge_eq *eq)
4007 if (eq->flags & EQ_ALLOCATED) {
4008 switch (eq->flags & EQ_TYPEMASK) {
4010 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
4015 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
4019 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4021 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
4027 panic("%s: invalid eq type %d.", __func__,
4028 eq->flags & EQ_TYPEMASK);
4031 device_printf(sc->dev,
4032 "failed to free egress queue (%d): %d\n",
4033 eq->flags & EQ_TYPEMASK, rc);
4036 eq->flags &= ~EQ_ALLOCATED;
4039 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4041 if (mtx_initialized(&eq->eq_lock))
4042 mtx_destroy(&eq->eq_lock);
4044 bzero(eq, sizeof(*eq));
4049 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4050 struct sysctl_oid *oid)
4053 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
4054 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4056 rc = alloc_eq(sc, vi, &wrq->eq);
4061 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4062 TAILQ_INIT(&wrq->incomplete_wrs);
4063 STAILQ_INIT(&wrq->wr_list);
4064 wrq->nwr_pending = 0;
4065 wrq->ndesc_needed = 0;
4067 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4068 &wrq->eq.ba, "bus address of descriptor ring");
4069 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4070 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
4071 "desc ring size in bytes");
4072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4073 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
4074 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
4075 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &wrq->eq.cidx, 0,
4076 sysctl_uint16, "I", "consumer index");
4077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
4078 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &wrq->eq.pidx, 0,
4079 sysctl_uint16, "I", "producer index");
4080 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4081 wrq->eq.sidx, "status page index");
4082 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4083 &wrq->tx_wrs_direct, "# of work requests (direct)");
4084 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4085 &wrq->tx_wrs_copied, "# of work requests (copied)");
4086 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4087 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4093 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4097 rc = free_eq(sc, &wrq->eq);
4101 bzero(wrq, sizeof(*wrq));
4106 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
4107 struct sysctl_oid *oid)
4110 struct port_info *pi = vi->pi;
4111 struct adapter *sc = pi->adapter;
4112 struct sge_eq *eq = &txq->eq;
4114 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4116 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
4119 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
4123 rc = alloc_eq(sc, vi, eq);
4125 mp_ring_free(txq->r);
4130 /* Can't fail after this point. */
4133 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4135 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4136 ("eq_base mismatch"));
4137 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4138 ("PF with non-zero eq_base"));
4140 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4142 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4143 if (sc->flags & IS_VF)
4144 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4145 V_TXPKT_INTF(pi->tx_chan));
4147 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4148 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4149 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4151 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4154 snprintf(name, sizeof(name), "%d", idx);
4155 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
4156 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queue");
4157 children = SYSCTL_CHILDREN(oid);
4159 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4160 &eq->ba, "bus address of descriptor ring");
4161 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4162 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4163 "desc ring size in bytes");
4164 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4165 &eq->abs_id, 0, "absolute id of the queue");
4166 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4167 &eq->cntxt_id, 0, "SGE context id of the queue");
4168 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
4169 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &eq->cidx, 0,
4170 sysctl_uint16, "I", "consumer index");
4171 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
4172 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, &eq->pidx, 0,
4173 sysctl_uint16, "I", "producer index");
4174 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4175 eq->sidx, "status page index");
4177 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
4178 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, vi, idx, sysctl_tc,
4179 "I", "traffic class (-1 means none)");
4181 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4182 &txq->txcsum, "# of times hardware assisted with checksum");
4183 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
4184 CTLFLAG_RD, &txq->vlan_insertion,
4185 "# of times hardware inserted 802.1Q tag");
4186 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4187 &txq->tso_wrs, "# of TSO work requests");
4188 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4189 &txq->imm_wrs, "# of work requests with immediate data");
4190 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4191 &txq->sgl_wrs, "# of work requests with direct SGL");
4192 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4193 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4194 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
4195 CTLFLAG_RD, &txq->txpkts0_wrs,
4196 "# of txpkts (type 0) work requests");
4197 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
4198 CTLFLAG_RD, &txq->txpkts1_wrs,
4199 "# of txpkts (type 1) work requests");
4200 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
4201 CTLFLAG_RD, &txq->txpkts0_pkts,
4202 "# of frames tx'd using type0 txpkts work requests");
4203 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
4204 CTLFLAG_RD, &txq->txpkts1_pkts,
4205 "# of frames tx'd using type1 txpkts work requests");
4206 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4207 &txq->raw_wrs, "# of raw work requests (non-packets)");
4210 if (sc->flags & KERN_TLS_OK) {
4211 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4212 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records,
4213 "# of NIC TLS records transmitted");
4214 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4215 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short,
4216 "# of short NIC TLS records transmitted");
4217 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4218 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial,
4219 "# of partial NIC TLS records transmitted");
4220 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4221 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full,
4222 "# of full NIC TLS records transmitted");
4223 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4224 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets,
4225 "# of payload octets in transmitted NIC TLS records");
4226 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4227 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste,
4228 "# of octets DMAd but not transmitted in NIC TLS records");
4229 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4230 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options,
4231 "# of NIC TLS options-only packets transmitted");
4232 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4233 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header,
4234 "# of NIC TLS header-only packets transmitted");
4235 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4236 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin,
4237 "# of NIC TLS FIN-only packets transmitted");
4238 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4239 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short,
4240 "# of NIC TLS padded FIN packets on short TLS records");
4241 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4242 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc,
4243 "# of NIC TLS sessions using AES-CBC");
4244 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4245 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm,
4246 "# of NIC TLS sessions using AES-GCM");
4250 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
4251 CTLFLAG_RD, &txq->r->enqueues,
4252 "# of enqueues to the mp_ring for this queue");
4253 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
4254 CTLFLAG_RD, &txq->r->drops,
4255 "# of drops in the mp_ring for this queue");
4256 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
4257 CTLFLAG_RD, &txq->r->starts,
4258 "# of normal consumer starts in the mp_ring for this queue");
4259 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
4260 CTLFLAG_RD, &txq->r->stalls,
4261 "# of consumer stalls in the mp_ring for this queue");
4262 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
4263 CTLFLAG_RD, &txq->r->restarts,
4264 "# of consumer restarts in the mp_ring for this queue");
4265 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
4266 CTLFLAG_RD, &txq->r->abdications,
4267 "# of consumer abdications in the mp_ring for this queue");
4273 free_txq(struct vi_info *vi, struct sge_txq *txq)
4276 struct adapter *sc = vi->pi->adapter;
4277 struct sge_eq *eq = &txq->eq;
4279 rc = free_eq(sc, eq);
4283 sglist_free(txq->gl);
4284 free(txq->sdesc, M_CXGBE);
4285 mp_ring_free(txq->r);
4287 bzero(txq, sizeof(*txq));
4292 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4294 bus_addr_t *ba = arg;
4297 ("%s meant for single segment mappings only.", __func__));
4299 *ba = error ? 0 : segs->ds_addr;
4303 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4307 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4311 v = fl->dbval | V_PIDX(n);
4313 *fl->udb = htole32(v);
4315 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4316 IDXINCR(fl->dbidx, n, fl->sidx);
4320 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4321 * recycled do not count towards this allocation budget.
4323 * Returns non-zero to indicate that this freelist should be added to the list
4324 * of starving freelists.
4327 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4330 struct fl_sdesc *sd;
4333 struct rx_buf_info *rxb;
4334 struct cluster_metadata *clm;
4336 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4338 FL_LOCK_ASSERT_OWNED(fl);
4341 * We always stop at the beginning of the hardware descriptor that's just
4342 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4343 * which would mean an empty freelist to the chip.
4345 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4346 if (fl->pidx == max_pidx * 8)
4349 d = &fl->desc[fl->pidx];
4350 sd = &fl->sdesc[fl->pidx];
4354 if (sd->cl != NULL) {
4356 if (sd->nmbuf == 0) {
4358 * Fast recycle without involving any atomics on
4359 * the cluster's metadata (if the cluster has
4360 * metadata). This happens when all frames
4361 * received in the cluster were small enough to
4362 * fit within a single mbuf each.
4364 fl->cl_fast_recycled++;
4369 * Cluster is guaranteed to have metadata. Clusters
4370 * without metadata always take the fast recycle path
4371 * when they're recycled.
4373 clm = cl_metadata(sd);
4376 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4378 counter_u64_add(extfree_rels, 1);
4381 sd->cl = NULL; /* gave up my reference */
4383 MPASS(sd->cl == NULL);
4384 rxb = &sc->sge.rx_buf_info[fl->zidx];
4385 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4386 if (__predict_false(cl == NULL)) {
4387 if (fl->zidx != fl->safe_zidx) {
4388 rxb = &sc->sge.rx_buf_info[fl->safe_zidx];
4389 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4397 pa = pmap_kextract((vm_offset_t)cl);
4399 sd->zidx = fl->zidx;
4401 if (fl->flags & FL_BUF_PACKING) {
4402 *d = htobe64(pa | rxb->hwidx2);
4403 sd->moff = rxb->size2;
4405 *d = htobe64(pa | rxb->hwidx1);
4412 if (__predict_false((++fl->pidx & 7) == 0)) {
4413 uint16_t pidx = fl->pidx >> 3;
4415 if (__predict_false(pidx == fl->sidx)) {
4421 if (n < 8 || pidx == max_pidx)
4424 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4429 if ((fl->pidx >> 3) != fl->dbidx)
4432 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4436 * Attempt to refill all starving freelists.
4439 refill_sfl(void *arg)
4441 struct adapter *sc = arg;
4442 struct sge_fl *fl, *fl_temp;
4444 mtx_assert(&sc->sfl_lock, MA_OWNED);
4445 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4447 refill_fl(sc, fl, 64);
4448 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4449 TAILQ_REMOVE(&sc->sfl, fl, link);
4450 fl->flags &= ~FL_STARVING;
4455 if (!TAILQ_EMPTY(&sc->sfl))
4456 callout_schedule(&sc->sfl_callout, hz / 5);
4460 alloc_fl_sdesc(struct sge_fl *fl)
4463 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4470 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4472 struct fl_sdesc *sd;
4473 struct cluster_metadata *clm;
4477 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4482 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
4483 else if (fl->flags & FL_BUF_PACKING) {
4484 clm = cl_metadata(sd);
4485 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4486 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
4488 counter_u64_add(extfree_rels, 1);
4494 free(fl->sdesc, M_CXGBE);
4499 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4506 rc = sglist_append_mbuf(gl, m);
4507 if (__predict_false(rc != 0)) {
4508 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4509 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4512 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4513 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4514 mbuf_nsegs(m), gl->sg_nseg));
4515 KASSERT(gl->sg_nseg > 0 &&
4516 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4517 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4518 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4522 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4525 txpkt_len16(u_int nsegs, u_int tso)
4531 nsegs--; /* first segment is part of ulptx_sgl */
4532 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4533 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4535 n += sizeof(struct cpl_tx_pkt_lso_core);
4537 return (howmany(n, 16));
4541 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4545 txpkt_vm_len16(u_int nsegs, u_int tso)
4551 nsegs--; /* first segment is part of ulptx_sgl */
4552 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4553 sizeof(struct cpl_tx_pkt_core) +
4554 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4556 n += sizeof(struct cpl_tx_pkt_lso_core);
4558 return (howmany(n, 16));
4562 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4566 txpkts0_len16(u_int nsegs)
4572 nsegs--; /* first segment is part of ulptx_sgl */
4573 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4574 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4575 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4577 return (howmany(n, 16));
4581 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4589 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4591 return (howmany(n, 16));
4595 imm_payload(u_int ndesc)
4599 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4600 sizeof(struct cpl_tx_pkt_core);
4605 static inline uint64_t
4606 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
4613 if (needs_hwcsum(m) == 0)
4614 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
4617 if (needs_l3_csum(m) == 0)
4618 ctrl |= F_TXPKT_IPCSUM_DIS;
4619 switch (m->m_pkthdr.csum_flags &
4620 (CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) {
4622 csum_type = TX_CSUM_TCPIP;
4625 csum_type = TX_CSUM_UDPIP;
4628 csum_type = TX_CSUM_TCPIP6;
4631 csum_type = TX_CSUM_UDPIP6;
4634 /* needs_hwcsum told us that at least some hwcsum is needed. */
4636 MPASS(m->m_pkthdr.csum_flags & CSUM_IP);
4637 ctrl |= F_TXPKT_L4CSUM_DIS;
4638 csum_type = TX_CSUM_IP;
4642 MPASS(m->m_pkthdr.l2hlen > 0);
4643 MPASS(m->m_pkthdr.l3hlen > 0);
4644 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) |
4645 V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen);
4646 if (chip_id(sc) <= CHELSIO_T5)
4647 ctrl |= V_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN);
4649 ctrl |= V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN);
4655 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4656 * software descriptor, and advance the pidx. It is guaranteed that enough
4657 * descriptors are available.
4659 * The return value is the # of hardware descriptors used.
4662 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4663 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4665 struct sge_eq *eq = &txq->eq;
4666 struct tx_sdesc *txsd;
4667 struct cpl_tx_pkt_core *cpl;
4668 uint32_t ctrl; /* used in many unrelated places */
4670 int len16, ndesc, pktlen, nsegs;
4673 TXQ_LOCK_ASSERT_OWNED(txq);
4675 MPASS(available > 0 && available < eq->sidx);
4677 len16 = mbuf_len16(m0);
4678 nsegs = mbuf_nsegs(m0);
4679 pktlen = m0->m_pkthdr.len;
4680 ctrl = sizeof(struct cpl_tx_pkt_core);
4682 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4683 ndesc = howmany(len16, EQ_ESIZE / 16);
4684 MPASS(ndesc <= available);
4686 /* Firmware work request header */
4687 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4688 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4689 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4691 ctrl = V_FW_WR_LEN16(len16);
4692 wr->equiq_to_len16 = htobe32(ctrl);
4697 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4698 * vlantci is ignored unless the ethtype is 0x8100, so it's
4699 * simpler to always copy it rather than making it
4700 * conditional. Also, it seems that we do not have to set
4701 * vlantci or fake the ethtype when doing VLAN tag insertion.
4703 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4705 if (needs_tso(m0)) {
4706 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4708 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4709 m0->m_pkthdr.l4hlen > 0,
4710 ("%s: mbuf %p needs TSO but missing header lengths",
4713 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4714 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
4715 ETHER_HDR_LEN) >> 2) |
4716 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
4717 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4718 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4721 lso->lso_ctrl = htobe32(ctrl);
4722 lso->ipid_ofst = htobe16(0);
4723 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4724 lso->seqno_offset = htobe32(0);
4725 lso->len = htobe32(pktlen);
4727 cpl = (void *)(lso + 1);
4731 cpl = (void *)(wr + 1);
4733 /* Checksum offload */
4734 ctrl1 = csum_to_ctrl(sc, m0);
4735 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
4736 txq->txcsum++; /* some hardware assistance provided */
4738 /* VLAN tag insertion */
4739 if (needs_vlan_insertion(m0)) {
4740 ctrl1 |= F_TXPKT_VLAN_VLD |
4741 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4742 txq->vlan_insertion++;
4746 cpl->ctrl0 = txq->cpl_ctrl0;
4748 cpl->len = htobe16(pktlen);
4749 cpl->ctrl1 = htobe64(ctrl1);
4752 dst = (void *)(cpl + 1);
4755 * A packet using TSO will use up an entire descriptor for the
4756 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4757 * If this descriptor is the last descriptor in the ring, wrap
4758 * around to the front of the ring explicitly for the start of
4761 if (dst == (void *)&eq->desc[eq->sidx]) {
4762 dst = (void *)&eq->desc[0];
4763 write_gl_to_txd(txq, m0, &dst, 0);
4765 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4770 txsd = &txq->sdesc[eq->pidx];
4772 txsd->desc_used = ndesc;
4778 * Write a raw WR to the hardware descriptors, update the software
4779 * descriptor, and advance the pidx. It is guaranteed that enough
4780 * descriptors are available.
4782 * The return value is the # of hardware descriptors used.
4785 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
4787 struct sge_eq *eq = &txq->eq;
4788 struct tx_sdesc *txsd;
4793 len16 = mbuf_len16(m0);
4794 ndesc = howmany(len16, EQ_ESIZE / 16);
4795 MPASS(ndesc <= available);
4798 for (m = m0; m != NULL; m = m->m_next)
4799 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4803 txsd = &txq->sdesc[eq->pidx];
4805 txsd->desc_used = ndesc;
4811 * Write a txpkt WR for this packet to the hardware descriptors, update the
4812 * software descriptor, and advance the pidx. It is guaranteed that enough
4813 * descriptors are available.
4815 * The return value is the # of hardware descriptors used.
4818 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq,
4819 struct fw_eth_tx_pkt_wr *wr, struct mbuf *m0, u_int available)
4821 struct sge_eq *eq = &txq->eq;
4822 struct tx_sdesc *txsd;
4823 struct cpl_tx_pkt_core *cpl;
4824 uint32_t ctrl; /* used in many unrelated places */
4826 int len16, ndesc, pktlen, nsegs;
4829 TXQ_LOCK_ASSERT_OWNED(txq);
4831 MPASS(available > 0 && available < eq->sidx);
4833 len16 = mbuf_len16(m0);
4834 nsegs = mbuf_nsegs(m0);
4835 pktlen = m0->m_pkthdr.len;
4836 ctrl = sizeof(struct cpl_tx_pkt_core);
4838 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4839 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
4841 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4843 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4844 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4847 ndesc = howmany(len16, EQ_ESIZE / 16);
4848 MPASS(ndesc <= available);
4850 /* Firmware work request header */
4851 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4852 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4853 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4855 ctrl = V_FW_WR_LEN16(len16);
4856 wr->equiq_to_len16 = htobe32(ctrl);
4859 if (needs_tso(m0)) {
4860 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4862 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4863 m0->m_pkthdr.l4hlen > 0,
4864 ("%s: mbuf %p needs TSO but missing header lengths",
4867 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4868 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
4869 ETHER_HDR_LEN) >> 2) |
4870 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
4871 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4872 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4875 lso->lso_ctrl = htobe32(ctrl);
4876 lso->ipid_ofst = htobe16(0);
4877 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4878 lso->seqno_offset = htobe32(0);
4879 lso->len = htobe32(pktlen);
4881 cpl = (void *)(lso + 1);
4885 cpl = (void *)(wr + 1);
4887 /* Checksum offload */
4888 ctrl1 = csum_to_ctrl(sc, m0);
4889 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
4890 txq->txcsum++; /* some hardware assistance provided */
4892 /* VLAN tag insertion */
4893 if (needs_vlan_insertion(m0)) {
4894 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4895 txq->vlan_insertion++;
4899 cpl->ctrl0 = txq->cpl_ctrl0;
4901 cpl->len = htobe16(pktlen);
4902 cpl->ctrl1 = htobe64(ctrl1);
4905 dst = (void *)(cpl + 1);
4908 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4913 for (m = m0; m != NULL; m = m->m_next) {
4914 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4920 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4927 txsd = &txq->sdesc[eq->pidx];
4929 txsd->desc_used = ndesc;
4935 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4937 u_int needed, nsegs1, nsegs2, l1, l2;
4939 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4942 nsegs1 = mbuf_nsegs(m);
4943 nsegs2 = mbuf_nsegs(n);
4944 if (nsegs1 + nsegs2 == 2) {
4946 l1 = l2 = txpkts1_len16();
4949 l1 = txpkts0_len16(nsegs1);
4950 l2 = txpkts0_len16(nsegs2);
4952 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4953 needed = howmany(txp->len16, EQ_ESIZE / 16);
4954 if (needed > SGE_MAX_WR_NDESC || needed > available)
4957 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4958 if (txp->plen > 65535)
4962 set_mbuf_len16(m, l1);
4963 set_mbuf_len16(n, l2);
4969 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4971 u_int plen, len16, needed, nsegs;
4973 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4975 if (cannot_use_txpkts(m))
4978 nsegs = mbuf_nsegs(m);
4979 if (txp->wr_type == 1 && nsegs != 1)
4982 plen = txp->plen + m->m_pkthdr.len;
4986 if (txp->wr_type == 0)
4987 len16 = txpkts0_len16(nsegs);
4989 len16 = txpkts1_len16();
4990 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4991 if (needed > SGE_MAX_WR_NDESC || needed > available)
4996 txp->len16 += len16;
4997 set_mbuf_len16(m, len16);
5003 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5004 * the software descriptor, and advance the pidx. It is guaranteed that enough
5005 * descriptors are available.
5007 * The return value is the # of hardware descriptors used.
5010 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq,
5011 struct fw_eth_tx_pkts_wr *wr, struct mbuf *m0, const struct txpkts *txp,
5014 struct sge_eq *eq = &txq->eq;
5015 struct tx_sdesc *txsd;
5016 struct cpl_tx_pkt_core *cpl;
5019 int ndesc, checkwrap;
5023 TXQ_LOCK_ASSERT_OWNED(txq);
5024 MPASS(txp->npkt > 0);
5025 MPASS(txp->plen < 65536);
5027 MPASS(m0->m_nextpkt != NULL);
5028 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5029 MPASS(available > 0 && available < eq->sidx);
5031 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
5032 MPASS(ndesc <= available);
5034 MPASS(wr == (void *)&eq->desc[eq->pidx]);
5035 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5036 ctrl = V_FW_WR_LEN16(txp->len16);
5037 wr->equiq_to_len16 = htobe32(ctrl);
5038 wr->plen = htobe16(txp->plen);
5039 wr->npkt = txp->npkt;
5041 wr->type = txp->wr_type;
5045 * At this point we are 16B into a hardware descriptor. If checkwrap is
5046 * set then we know the WR is going to wrap around somewhere. We'll
5047 * check for that at appropriate points.
5049 checkwrap = eq->sidx - ndesc < eq->pidx;
5050 for (m = m0; m != NULL; m = m->m_nextpkt) {
5051 if (txp->wr_type == 0) {
5052 struct ulp_txpkt *ulpmc;
5053 struct ulptx_idata *ulpsc;
5055 /* ULP master command */
5057 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5058 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5059 ulpmc->len = htobe32(mbuf_len16(m));
5061 /* ULP subcommand */
5062 ulpsc = (void *)(ulpmc + 1);
5063 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5065 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5067 cpl = (void *)(ulpsc + 1);
5069 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5070 cpl = (void *)&eq->desc[0];
5075 /* Checksum offload */
5076 ctrl1 = csum_to_ctrl(sc, m);
5077 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5078 txq->txcsum++; /* some hardware assistance provided */
5080 /* VLAN tag insertion */
5081 if (needs_vlan_insertion(m)) {
5082 ctrl1 |= F_TXPKT_VLAN_VLD |
5083 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5084 txq->vlan_insertion++;
5088 cpl->ctrl0 = txq->cpl_ctrl0;
5090 cpl->len = htobe16(m->m_pkthdr.len);
5091 cpl->ctrl1 = htobe64(ctrl1);
5095 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5096 flitp = (void *)&eq->desc[0];
5098 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5102 if (txp->wr_type == 0) {
5103 txq->txpkts0_pkts += txp->npkt;
5106 txq->txpkts1_pkts += txp->npkt;
5110 txsd = &txq->sdesc[eq->pidx];
5112 txsd->desc_used = ndesc;
5118 * If the SGL ends on an address that is not 16 byte aligned, this function will
5119 * add a 0 filled flit at the end.
5122 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5124 struct sge_eq *eq = &txq->eq;
5125 struct sglist *gl = txq->gl;
5126 struct sglist_seg *seg;
5127 __be64 *flitp, *wrap;
5128 struct ulptx_sgl *usgl;
5129 int i, nflits, nsegs;
5131 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5132 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5133 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5134 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5137 nsegs = gl->sg_nseg;
5140 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5141 flitp = (__be64 *)(*to);
5142 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5143 seg = &gl->sg_segs[0];
5144 usgl = (void *)flitp;
5147 * We start at a 16 byte boundary somewhere inside the tx descriptor
5148 * ring, so we're at least 16 bytes away from the status page. There is
5149 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5152 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5153 V_ULPTX_NSGE(nsegs));
5154 usgl->len0 = htobe32(seg->ss_len);
5155 usgl->addr0 = htobe64(seg->ss_paddr);
5158 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5160 /* Won't wrap around at all */
5162 for (i = 0; i < nsegs - 1; i++, seg++) {
5163 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5164 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5167 usgl->sge[i / 2].len[1] = htobe32(0);
5171 /* Will wrap somewhere in the rest of the SGL */
5173 /* 2 flits already written, write the rest flit by flit */
5174 flitp = (void *)(usgl + 1);
5175 for (i = 0; i < nflits - 2; i++) {
5177 flitp = (void *)eq->desc;
5178 *flitp++ = get_flit(seg, nsegs - 1, i);
5183 MPASS(((uintptr_t)flitp) & 0xf);
5187 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5188 if (__predict_false(flitp == wrap))
5189 *to = (void *)eq->desc;
5191 *to = (void *)flitp;
5195 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5198 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5199 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5201 if (__predict_true((uintptr_t)(*to) + len <=
5202 (uintptr_t)&eq->desc[eq->sidx])) {
5203 bcopy(from, *to, len);
5206 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5208 bcopy(from, *to, portion);
5210 portion = len - portion; /* remaining */
5211 bcopy(from, (void *)eq->desc, portion);
5212 (*to) = (caddr_t)eq->desc + portion;
5217 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
5225 clrbit(&db, DOORBELL_WCWR);
5228 switch (ffs(db) - 1) {
5230 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5233 case DOORBELL_WCWR: {
5234 volatile uint64_t *dst, *src;
5238 * Queues whose 128B doorbell segment fits in the page do not
5239 * use relative qid (udb_qid is always 0). Only queues with
5240 * doorbell segments can do WCWR.
5242 KASSERT(eq->udb_qid == 0 && n == 1,
5243 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
5244 __func__, eq->doorbells, n, eq->dbidx, eq));
5246 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
5249 src = (void *)&eq->desc[i];
5250 while (src != (void *)&eq->desc[i + 1])
5256 case DOORBELL_UDBWC:
5257 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5262 t4_write_reg(sc, sc->sge_kdoorbell_reg,
5263 V_QID(eq->cntxt_id) | V_PIDX(n));
5267 IDXINCR(eq->dbidx, n, eq->sidx);
5271 reclaimable_tx_desc(struct sge_eq *eq)
5275 hw_cidx = read_hw_cidx(eq);
5276 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5280 total_available_tx_desc(struct sge_eq *eq)
5282 uint16_t hw_cidx, pidx;
5284 hw_cidx = read_hw_cidx(eq);
5287 if (pidx == hw_cidx)
5288 return (eq->sidx - 1);
5290 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5293 static inline uint16_t
5294 read_hw_cidx(struct sge_eq *eq)
5296 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5297 uint16_t cidx = spg->cidx; /* stable snapshot */
5299 return (be16toh(cidx));
5303 * Reclaim 'n' descriptors approximately.
5306 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5308 struct tx_sdesc *txsd;
5309 struct sge_eq *eq = &txq->eq;
5310 u_int can_reclaim, reclaimed;
5312 TXQ_LOCK_ASSERT_OWNED(txq);
5316 can_reclaim = reclaimable_tx_desc(eq);
5317 while (can_reclaim && reclaimed < n) {
5319 struct mbuf *m, *nextpkt;
5321 txsd = &txq->sdesc[eq->cidx];
5322 ndesc = txsd->desc_used;
5324 /* Firmware doesn't return "partial" credits. */
5325 KASSERT(can_reclaim >= ndesc,
5326 ("%s: unexpected number of credits: %d, %d",
5327 __func__, can_reclaim, ndesc));
5329 ("%s: descriptor with no credits: cidx %d",
5330 __func__, eq->cidx));
5332 for (m = txsd->m; m != NULL; m = nextpkt) {
5333 nextpkt = m->m_nextpkt;
5334 m->m_nextpkt = NULL;
5338 can_reclaim -= ndesc;
5339 IDXINCR(eq->cidx, ndesc, eq->sidx);
5346 tx_reclaim(void *arg, int n)
5348 struct sge_txq *txq = arg;
5349 struct sge_eq *eq = &txq->eq;
5352 if (TXQ_TRYLOCK(txq) == 0)
5354 n = reclaim_tx_descs(txq, 32);
5355 if (eq->cidx == eq->pidx)
5356 eq->equeqidx = eq->pidx;
5362 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5364 int i = (idx / 3) * 2;
5370 rc = (uint64_t)segs[i].ss_len << 32;
5372 rc |= (uint64_t)(segs[i + 1].ss_len);
5374 return (htobe64(rc));
5377 return (htobe64(segs[i].ss_paddr));
5379 return (htobe64(segs[i + 1].ss_paddr));
5386 find_refill_source(struct adapter *sc, int maxp, bool packing)
5389 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
5392 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
5393 if (rxb->hwidx2 == -1)
5395 if (rxb->size1 < PAGE_SIZE &&
5396 rxb->size1 < largest_rx_cluster)
5398 if (rxb->size1 > largest_rx_cluster)
5400 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
5401 if (rxb->size2 >= maxp)
5406 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
5407 if (rxb->hwidx1 == -1)
5409 if (rxb->size1 > largest_rx_cluster)
5411 if (rxb->size1 >= maxp)
5421 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5423 mtx_lock(&sc->sfl_lock);
5425 if ((fl->flags & FL_DOOMED) == 0) {
5426 fl->flags |= FL_STARVING;
5427 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5428 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5431 mtx_unlock(&sc->sfl_lock);
5435 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5437 struct sge_wrq *wrq = (void *)eq;
5439 atomic_readandclear_int(&eq->equiq);
5440 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5444 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5446 struct sge_txq *txq = (void *)eq;
5448 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5450 atomic_readandclear_int(&eq->equiq);
5451 mp_ring_check_drainage(txq->r, 0);
5452 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5456 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5459 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5460 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5461 struct adapter *sc = iq->adapter;
5462 struct sge *s = &sc->sge;
5464 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5465 &handle_wrq_egr_update, &handle_eth_egr_update,
5466 &handle_wrq_egr_update};
5468 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5471 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5472 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5477 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5478 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5479 offsetof(struct cpl_fw6_msg, data));
5482 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5484 struct adapter *sc = iq->adapter;
5485 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5487 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5490 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5491 const struct rss_header *rss2;
5493 rss2 = (const struct rss_header *)&cpl->data[0];
5494 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5497 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5501 * t4_handle_wrerr_rpl - process a FW work request error message
5502 * @adap: the adapter
5503 * @rpl: start of the FW message
5506 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5508 u8 opcode = *(const u8 *)rpl;
5509 const struct fw_error_cmd *e = (const void *)rpl;
5512 if (opcode != FW_ERROR_CMD) {
5514 "%s: Received WRERR_RPL message with opcode %#x\n",
5515 device_get_nameunit(adap->dev), opcode);
5518 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5519 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5521 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5522 case FW_ERROR_TYPE_EXCEPTION:
5523 log(LOG_ERR, "exception info:\n");
5524 for (i = 0; i < nitems(e->u.exception.info); i++)
5525 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5526 be32toh(e->u.exception.info[i]));
5529 case FW_ERROR_TYPE_HWMODULE:
5530 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5531 be32toh(e->u.hwmodule.regaddr),
5532 be32toh(e->u.hwmodule.regval));
5534 case FW_ERROR_TYPE_WR:
5535 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5536 be16toh(e->u.wr.cidx),
5537 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5538 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5539 be32toh(e->u.wr.eqid));
5540 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5541 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5545 case FW_ERROR_TYPE_ACL:
5546 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5547 be16toh(e->u.acl.cidx),
5548 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5549 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5550 be32toh(e->u.acl.eqid),
5551 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5553 for (i = 0; i < nitems(e->u.acl.val); i++)
5554 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5558 log(LOG_ERR, "type %#x\n",
5559 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5566 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5568 uint16_t *id = arg1;
5571 return sysctl_handle_int(oidp, &i, 0, req);
5575 bufidx_used(struct adapter *sc, int idx)
5577 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
5580 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
5581 if (rxb->size1 > largest_rx_cluster)
5583 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
5591 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5593 struct adapter *sc = arg1;
5594 struct sge_params *sp = &sc->params.sge;
5599 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
5600 for (i = 0; i < SGE_FLBUF_SIZES; i++) {
5601 if (bufidx_used(sc, i))
5606 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
5610 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5617 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5620 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
5626 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
5627 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
5628 if (__predict_false(nsegs == 0))
5631 nsegs--; /* first segment is part of ulptx_sgl */
5632 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5634 n += sizeof(struct cpl_tx_pkt_lso_core);
5637 return (howmany(n, 16));
5640 #define ETID_FLOWC_NPARAMS 6
5641 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
5642 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
5643 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
5646 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
5649 struct wrq_cookie cookie;
5650 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
5651 struct fw_flowc_wr *flowc;
5653 mtx_assert(&cst->lock, MA_OWNED);
5654 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
5657 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
5658 if (__predict_false(flowc == NULL))
5661 bzero(flowc, ETID_FLOWC_LEN);
5662 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5663 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
5664 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
5665 V_FW_WR_FLOWID(cst->etid));
5666 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
5667 flowc->mnemval[0].val = htobe32(pfvf);
5668 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
5669 flowc->mnemval[1].val = htobe32(pi->tx_chan);
5670 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
5671 flowc->mnemval[2].val = htobe32(pi->tx_chan);
5672 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
5673 flowc->mnemval[3].val = htobe32(cst->iqid);
5674 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
5675 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
5676 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
5677 flowc->mnemval[5].val = htobe32(cst->schedcl);
5679 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5681 cst->flags &= ~EO_FLOWC_PENDING;
5682 cst->flags |= EO_FLOWC_RPL_PENDING;
5683 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
5684 cst->tx_credits -= ETID_FLOWC_LEN16;
5689 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
5692 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
5694 struct fw_flowc_wr *flowc;
5695 struct wrq_cookie cookie;
5697 mtx_assert(&cst->lock, MA_OWNED);
5699 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
5700 if (__predict_false(flowc == NULL))
5701 CXGBE_UNIMPLEMENTED(__func__);
5703 bzero(flowc, ETID_FLUSH_LEN16 * 16);
5704 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5705 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
5706 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
5707 V_FW_WR_FLOWID(cst->etid));
5709 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5711 cst->flags |= EO_FLUSH_RPL_PENDING;
5712 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
5713 cst->tx_credits -= ETID_FLUSH_LEN16;
5718 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
5719 struct mbuf *m0, int compl)
5721 struct cpl_tx_pkt_core *cpl;
5723 uint32_t ctrl; /* used in many unrelated places */
5724 int len16, pktlen, nsegs, immhdrs;
5727 struct ulptx_sgl *usgl;
5729 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
5731 mtx_assert(&cst->lock, MA_OWNED);
5733 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5734 m0->m_pkthdr.l4hlen > 0,
5735 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
5737 len16 = mbuf_eo_len16(m0);
5738 nsegs = mbuf_eo_nsegs(m0);
5739 pktlen = m0->m_pkthdr.len;
5740 ctrl = sizeof(struct cpl_tx_pkt_core);
5742 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5743 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
5746 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
5747 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
5748 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
5749 V_FW_WR_FLOWID(cst->etid));
5751 if (needs_udp_csum(m0)) {
5752 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
5753 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
5754 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5755 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
5756 wr->u.udpseg.rtplen = 0;
5757 wr->u.udpseg.r4 = 0;
5758 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
5759 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
5760 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
5761 cpl = (void *)(wr + 1);
5763 MPASS(needs_tcp_csum(m0));
5764 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
5765 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
5766 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5767 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
5768 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
5769 wr->u.tcpseg.r4 = 0;
5770 wr->u.tcpseg.r5 = 0;
5771 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
5773 if (needs_tso(m0)) {
5774 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
5776 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
5778 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5779 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5780 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
5781 ETHER_HDR_LEN) >> 2) |
5782 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5783 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5784 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5786 lso->lso_ctrl = htobe32(ctrl);
5787 lso->ipid_ofst = htobe16(0);
5788 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5789 lso->seqno_offset = htobe32(0);
5790 lso->len = htobe32(pktlen);
5792 cpl = (void *)(lso + 1);
5794 wr->u.tcpseg.mss = htobe16(0xffff);
5795 cpl = (void *)(wr + 1);
5799 /* Checksum offload must be requested for ethofld. */
5800 MPASS(needs_l4_csum(m0));
5801 ctrl1 = csum_to_ctrl(cst->adapter, m0);
5803 /* VLAN tag insertion */
5804 if (needs_vlan_insertion(m0)) {
5805 ctrl1 |= F_TXPKT_VLAN_VLD |
5806 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5810 cpl->ctrl0 = cst->ctrl0;
5812 cpl->len = htobe16(pktlen);
5813 cpl->ctrl1 = htobe64(ctrl1);
5815 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
5816 p = (uintptr_t)(cpl + 1);
5817 m_copydata(m0, 0, immhdrs, (void *)p);
5820 dst = (void *)(cpl + 1);
5824 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
5826 pad = 16 - (immhdrs & 0xf);
5827 bzero((void *)p, pad);
5829 usgl = (void *)(p + pad);
5830 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5831 V_ULPTX_NSGE(nsegs));
5833 sglist_init(&sg, nitems(segs), segs);
5834 for (; m0 != NULL; m0 = m0->m_next) {
5835 if (__predict_false(m0->m_len == 0))
5837 if (immhdrs >= m0->m_len) {
5838 immhdrs -= m0->m_len;
5842 sglist_append(&sg, mtod(m0, char *) + immhdrs,
5843 m0->m_len - immhdrs);
5846 MPASS(sg.sg_nseg == nsegs);
5849 * Zero pad last 8B in case the WR doesn't end on a 16B
5852 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
5854 usgl->len0 = htobe32(segs[0].ss_len);
5855 usgl->addr0 = htobe64(segs[0].ss_paddr);
5856 for (i = 0; i < nsegs - 1; i++) {
5857 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
5858 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
5861 usgl->sge[i / 2].len[1] = htobe32(0);
5867 ethofld_tx(struct cxgbe_rate_tag *cst)
5870 struct wrq_cookie cookie;
5871 int next_credits, compl;
5872 struct fw_eth_tx_eo_wr *wr;
5874 mtx_assert(&cst->lock, MA_OWNED);
5876 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
5879 /* How many len16 credits do we need to send this mbuf. */
5880 next_credits = mbuf_eo_len16(m);
5881 MPASS(next_credits > 0);
5882 if (next_credits > cst->tx_credits) {
5884 * Tx will make progress eventually because there is at
5885 * least one outstanding fw4_ack that will return
5886 * credits and kick the tx.
5888 MPASS(cst->ncompl > 0);
5891 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
5892 if (__predict_false(wr == NULL)) {
5893 /* XXX: wishful thinking, not a real assertion. */
5894 MPASS(cst->ncompl > 0);
5897 cst->tx_credits -= next_credits;
5898 cst->tx_nocompl += next_credits;
5899 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
5900 ETHER_BPF_MTAP(cst->com.com.ifp, m);
5901 write_ethofld_wr(cst, wr, m, compl);
5902 commit_wrq_wr(cst->eo_txq, wr, &cookie);
5905 cst->tx_nocompl = 0;
5907 (void) mbufq_dequeue(&cst->pending_tx);
5910 * Drop the mbuf's reference on the tag now rather
5911 * than waiting until m_freem(). This ensures that
5912 * cxgbe_rate_tag_free gets called when the inp drops
5913 * its reference on the tag and there are no more
5914 * mbufs in the pending_tx queue and can flush any
5915 * pending requests. Otherwise if the last mbuf
5916 * doesn't request a completion the etid will never be
5919 m->m_pkthdr.snd_tag = NULL;
5920 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
5921 m_snd_tag_rele(&cst->com.com);
5923 mbufq_enqueue(&cst->pending_fwack, m);
5928 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
5930 struct cxgbe_rate_tag *cst;
5933 MPASS(m0->m_nextpkt == NULL);
5934 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
5935 MPASS(m0->m_pkthdr.snd_tag != NULL);
5936 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
5938 mtx_lock(&cst->lock);
5939 MPASS(cst->flags & EO_SND_TAG_REF);
5941 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
5942 struct vi_info *vi = ifp->if_softc;
5943 struct port_info *pi = vi->pi;
5944 struct adapter *sc = pi->adapter;
5945 const uint32_t rss_mask = vi->rss_size - 1;
5948 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
5949 if (M_HASHTYPE_ISHASH(m0))
5950 rss_hash = m0->m_pkthdr.flowid;
5952 rss_hash = arc4random();
5953 /* We assume RSS hashing */
5954 cst->iqid = vi->rss[rss_hash & rss_mask];
5955 cst->eo_txq += rss_hash % vi->nofldtxq;
5956 rc = send_etid_flowc_wr(cst, pi, vi);
5961 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
5966 mbufq_enqueue(&cst->pending_tx, m0);
5967 cst->plen += m0->m_pkthdr.len;
5970 * Hold an extra reference on the tag while generating work
5971 * requests to ensure that we don't try to free the tag during
5972 * ethofld_tx() in case we are sending the final mbuf after
5973 * the inp was freed.
5975 m_snd_tag_ref(&cst->com.com);
5977 mtx_unlock(&cst->lock);
5978 m_snd_tag_rele(&cst->com.com);
5982 mtx_unlock(&cst->lock);
5983 if (__predict_false(rc != 0))
5989 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
5991 struct adapter *sc = iq->adapter;
5992 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
5994 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
5995 struct cxgbe_rate_tag *cst;
5996 uint8_t credits = cpl->credits;
5998 cst = lookup_etid(sc, etid);
5999 mtx_lock(&cst->lock);
6000 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6001 MPASS(credits >= ETID_FLOWC_LEN16);
6002 credits -= ETID_FLOWC_LEN16;
6003 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6006 KASSERT(cst->ncompl > 0,
6007 ("%s: etid %u (%p) wasn't expecting completion.",
6008 __func__, etid, cst));
6011 while (credits > 0) {
6012 m = mbufq_dequeue(&cst->pending_fwack);
6013 if (__predict_false(m == NULL)) {
6015 * The remaining credits are for the final flush that
6016 * was issued when the tag was freed by the kernel.
6019 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6020 EO_FLUSH_RPL_PENDING);
6021 MPASS(credits == ETID_FLUSH_LEN16);
6022 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6023 MPASS(cst->ncompl == 0);
6025 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6026 cst->tx_credits += cpl->credits;
6027 cxgbe_rate_tag_free_locked(cst);
6028 return (0); /* cst is gone. */
6031 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6033 KASSERT(credits >= mbuf_eo_len16(m),
6034 ("%s: too few credits (%u, %u, %u)", __func__,
6035 cpl->credits, credits, mbuf_eo_len16(m)));
6036 credits -= mbuf_eo_len16(m);
6037 cst->plen -= m->m_pkthdr.len;
6041 cst->tx_credits += cpl->credits;
6042 MPASS(cst->tx_credits <= cst->tx_total);
6044 if (cst->flags & EO_SND_TAG_REF) {
6046 * As with ethofld_transmit(), hold an extra reference
6047 * so that the tag is stable across ethold_tx().
6049 m_snd_tag_ref(&cst->com.com);
6050 m = mbufq_first(&cst->pending_tx);
6051 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6053 mtx_unlock(&cst->lock);
6054 m_snd_tag_rele(&cst->com.com);
6057 * There shouldn't be any pending packets if the tag
6058 * was freed by the kernel since any pending packet
6059 * should hold a reference to the tag.
6061 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6062 mtx_unlock(&cst->lock);